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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include <stdint.h>

#include "c.h"
#include "fdisk.h"
#include "pt-sun.h"
#include "pt-mbr.h"

struct menu_entry {
	const char	key;			/* command key */
	const char	*title;			/* help string */
	unsigned int	normal : 1,		/* normal mode */
			expert : 1,		/* expert mode */
			hidden : 1;		/* be sensitive for this key,
						   but don't print it in help */

	enum fdisk_labeltype	label;		/* only for this label */
	enum fdisk_labeltype	exclude;	/* all labels except this */
	enum fdisk_labeltype	parent;		/* for nested PT */
};

#define IS_MENU_SEP(e)	((e)->key == '-')
#define IS_MENU_HID(e)	((e)->hidden)

struct menu {
	enum fdisk_labeltype	label;		/* only for this label */
	enum fdisk_labeltype	exclude;	/* all labels except this */

	unsigned int		nonested : 1;	/* don't make this menu active in nested PT */

	int (*callback)(struct fdisk_context **,
			const struct menu *,
			const struct menu_entry *);

	struct menu_entry	entries[];	/* NULL terminated array */
};

struct menu_context {
	size_t		menu_idx;		/* the current menu */
	size_t		entry_idx;		/* index with in the current menu */
};

#define MENU_CXT_EMPTY	{ 0, 0 }
#define DECLARE_MENU_CB(x) \
	static int x(struct fdisk_context **, \
		     const struct menu *, \
		     const struct menu_entry *)

DECLARE_MENU_CB(gpt_menu_cb);
DECLARE_MENU_CB(sun_menu_cb);
DECLARE_MENU_CB(sgi_menu_cb);
DECLARE_MENU_CB(geo_menu_cb);
DECLARE_MENU_CB(dos_menu_cb);
DECLARE_MENU_CB(bsd_menu_cb);
DECLARE_MENU_CB(createlabel_menu_cb);
DECLARE_MENU_CB(generic_menu_cb);

/*
 * Menu entry macros:
 *	MENU_X*    expert mode only
 *      MENU_B*    both -- expert + normal mode
 *
 *      *_E  exclude this label
 *      *_H  hidden
 *      *_L  only for this label
 */

/* separator */
#define MENU_SEP(t)		{ .title = t, .key = '-', .normal = 1 }
#define MENU_XSEP(t)		{ .title = t, .key = '-', .expert = 1 }
#define MENU_BSEP(t)		{ .title = t, .key = '-', .expert = 1, .normal = 1 }

/* entry */
#define MENU_ENT(k, t)		{ .title = t, .key = k, .normal = 1 }
#define MENU_ENT_E(k, t, l)	{ .title = t, .key = k, .normal = 1, .exclude = l }
#define MENU_ENT_L(k, t, l)	{ .title = t, .key = k, .normal = 1, .label = l }

#define MENU_XENT(k, t)		{ .title = t, .key = k, .expert = 1 }
#define MENU_XENT_H(k, t)	{ .title = t, .key = k, .expert = 1, .hidden = 1 }

#define MENU_BENT(k, t)		{ .title = t, .key = k, .expert = 1, .normal = 1 }
#define MENU_BENT_E(k, t, l)	{ .title = t, .key = k, .expert = 1, .normal = 1, .exclude = l }

#define MENU_ENT_NEST(k, t, l, p)	{ .title = t, .key = k, .normal = 1, .label = l, .parent = p }
#define MENU_XENT_NEST(k, t, l, p)	{ .title = t, .key = k, .expert = 1, .label = l, .parent = p }

/* Generic menu */
struct menu menu_generic = {
	.callback	= generic_menu_cb,
	.entries	= {
		MENU_BSEP(N_("Generic")),
		MENU_ENT  ('d', N_("delete a partition")),
		MENU_ENT  ('l', N_("list known partition types")),
		MENU_ENT  ('n', N_("add a new partition")),
		MENU_BENT ('p', N_("print the partition table")),
		MENU_ENT  ('t', N_("change a partition type")),
		MENU_BENT_E('v', N_("verify the partition table"), FDISK_DISKLABEL_BSD),

		MENU_XENT('d', N_("print the raw data of the first sector from the device")),
		MENU_XENT('D', N_("print the raw data of the disklabel from the device")),

		MENU_SEP(N_("Misc")),
		MENU_BENT ('m', N_("print this menu")),
		MENU_ENT_E('u', N_("change display/entry units"), FDISK_DISKLABEL_GPT),
		MENU_ENT_E('x', N_("extra functionality (experts only)"), FDISK_DISKLABEL_BSD),

		MENU_BSEP(N_("Save & Exit")),
		MENU_ENT_E('w', N_("write table to disk and exit"), FDISK_DISKLABEL_BSD),
		MENU_ENT_L('w', N_("write table to disk"), FDISK_DISKLABEL_BSD),
		MENU_BENT ('q', N_("quit without saving changes")),
		MENU_XENT ('r', N_("return to main menu")),

		MENU_ENT_NEST('r', N_("return from BSD to DOS"), FDISK_DISKLABEL_BSD, FDISK_DISKLABEL_DOS),

		{ 0, NULL }
	}
};

struct menu menu_createlabel = {
	.callback = createlabel_menu_cb,
	.exclude = FDISK_DISKLABEL_BSD,
	.nonested = 1,
	.entries = {
		MENU_SEP(N_("Create a new label")),
		MENU_ENT('g', N_("create a new empty GPT partition table")),
		MENU_ENT('G', N_("create a new empty SGI (IRIX) partition table")),
		MENU_ENT('o', N_("create a new empty DOS partition table")),
		MENU_ENT('s', N_("create a new empty Sun partition table")),

		/* backward compatibility -- be sensitive to 'g', but don't
		 * print it in the expert menu */
		MENU_XENT_H('g', N_("create an IRIX (SGI) partition table")),
		{ 0, NULL }
	}
};

struct menu menu_geo = {
	.callback = geo_menu_cb,
	.exclude = FDISK_DISKLABEL_GPT | FDISK_DISKLABEL_BSD,
	.entries = {
		MENU_XSEP(N_("Geometry")),
		MENU_XENT('c', N_("change number of cylinders")),
		MENU_XENT('h', N_("change number of heads")),
		MENU_XENT('s', N_("change number of sectors/track")),
		{ 0, NULL }
	}
};

struct menu menu_gpt = {
	.callback = gpt_menu_cb,
	.label = FDISK_DISKLABEL_GPT,
	.entries = {
		MENU_XSEP(N_("GPT")),
		MENU_XENT('i', N_("change disk GUID")),
		MENU_XENT('n', N_("change partition name")),
		MENU_XENT('u', N_("change partition UUID")),
		MENU_XENT('M', N_("enter protective/hybrid MBR")),

		MENU_XSEP(""),
		MENU_XENT('A', N_("toggle the legacy BIOS bootable flag")),
		MENU_XENT('B', N_("toggle the no block IO protocol flag")),
		MENU_XENT('R', N_("toggle the required partition flag")),
		MENU_XENT('S', N_("toggle the GUID specific bits")),

		{ 0, NULL }
	}
};

struct menu menu_sun = {
	.callback = sun_menu_cb,
	.label = FDISK_DISKLABEL_SUN,
	.entries = {
		MENU_BSEP(N_("Sun")),
		MENU_ENT('a', N_("toggle the read-only flag")),
		MENU_ENT('c', N_("toggle the mountable flag")),

		MENU_XENT('a', N_("change number of alternate cylinders")),
		MENU_XENT('e', N_("change number of extra sectors per cylinder")),
		MENU_XENT('i', N_("change interleave factor")),
		MENU_XENT('o', N_("change rotation speed (rpm)")),
		MENU_XENT('y', N_("change number of physical cylinders")),
		{ 0, NULL }
	}
};

struct menu menu_sgi = {
	.callback = sgi_menu_cb,
	.label = FDISK_DISKLABEL_SGI,
	.entries = {
		MENU_SEP(N_("SGI")),
		MENU_ENT('a', N_("select bootable partition")),
		MENU_ENT('b', N_("edit bootfile entry")),
		MENU_ENT('c', N_("select sgi swap partition")),
		MENU_ENT('i', N_("create SGI info")),
		{ 0, NULL }
	}
};

struct menu menu_dos = {
	.callback = dos_menu_cb,
	.label = FDISK_DISKLABEL_DOS,
	.entries = {
		MENU_BSEP(N_("DOS (MBR)")),
		MENU_ENT('a', N_("toggle a bootable flag")),
		MENU_ENT('b', N_("edit nested BSD disklabel")),
		MENU_ENT('c', N_("toggle the dos compatibility flag")),

		MENU_XENT('b', N_("move beginning of data in a partition")),
		MENU_XENT('f', N_("fix partition order")),
		MENU_XENT('i', N_("change the disk identifier")),

		MENU_XENT_NEST('M', N_("return from protective/hybrid MBR to GPT"),
					FDISK_DISKLABEL_DOS, FDISK_DISKLABEL_GPT),
		{ 0, NULL }
	}
};

struct menu menu_bsd = {
	.callback = bsd_menu_cb,
	.label = FDISK_DISKLABEL_BSD,
	.entries = {
		MENU_SEP(N_("BSD")),
		MENU_ENT('e', N_("edit drive data")),
		MENU_ENT('i', N_("install bootstrap")),
		MENU_ENT('s', N_("show complete disklabel")),
		MENU_ENT('x', N_("link BSD partition to non-BSD partition")),
		{ 0, NULL }
	}
};

static const struct menu *menus[] = {
	&menu_gpt,
	&menu_sun,
	&menu_sgi,
	&menu_dos,
	&menu_bsd,
	&menu_geo,
	&menu_generic,
	&menu_createlabel,
};

static const struct menu_entry *next_menu_entry(
			struct fdisk_context *cxt,
			struct menu_context *mc)
{
	while (mc->menu_idx < ARRAY_SIZE(menus)) {
		const struct menu *m = menus[mc->menu_idx];
		const struct menu_entry *e = &(m->entries[mc->entry_idx]);

		/*
		 * whole-menu filter
		 */

		/* no more entries */
		if (e->title == NULL ||
		/* menu wanted for specified labels only */
		    (m->label && cxt->label && !(m->label & cxt->label->id)) ||
		/* unwanted for nested PT */
		    (m->nonested && cxt->parent) ||
		/* menu excluded for specified labels */
		    (m->exclude && cxt->label && (m->exclude & cxt->label->id))) {
			mc->menu_idx++;
			mc->entry_idx = 0;
			continue;
		}

		/*
		 * per entry filter
		 */

		/* excluded for the current label */
		if ((e->exclude && cxt->label && e->exclude & cxt->label->id) ||
		/* entry wanted for specified labels only */
		    (e->label && cxt->label && !(e->label & cxt->label->id)) ||
		/* exclude non-expert entries in expect mode */
		    (e->expert == 0 && fdisk_context_display_details(cxt)) ||
		/* nested only */
		    (e->parent && (!cxt->parent || cxt->parent->label->id != e->parent)) ||
		/* exclude non-normal entries in normal mode */
		    (e->normal == 0 && !fdisk_context_display_details(cxt))) {

			mc->entry_idx++;
			continue;
		}
		mc->entry_idx++;
		return e;

	}
	return NULL;
}

/* returns @menu and menu entry for then @key */
static const struct menu_entry *get_fdisk_menu_entry(
		struct fdisk_context *cxt,
		int key,
		const struct menu **menu)
{
	struct menu_context mc = MENU_CXT_EMPTY;
	const struct menu_entry *e;

	while ((e = next_menu_entry(cxt, &mc))) {
		if (IS_MENU_SEP(e) || e->key != key)
			continue;

		if (menu)
			*menu = menus[mc.menu_idx];
		return e;
	}

	return NULL;
}

static int menu_detect_collisions(struct fdisk_context *cxt)
{
	struct menu_context mc = MENU_CXT_EMPTY;
	const struct menu_entry *e, *r;

	while ((e = next_menu_entry(cxt, &mc))) {
		if (IS_MENU_SEP(e))
			continue;

		r = get_fdisk_menu_entry(cxt, e->key, NULL);
		if (!r) {
			DBG(FRONTEND, ul_debug("warning: not found "
					"entry for %c", e->key));
			return -1;
		}
		if (r != e) {
			DBG(FRONTEND, ul_debug("warning: duplicate key '%c'",
						e->key));
			DBG(FRONTEND, ul_debug("       : %s", e->title));
			DBG(FRONTEND, ul_debug("       : %s", r->title));
			abort();
		}
	}

	return 0;
}

static int print_fdisk_menu(struct fdisk_context *cxt)
{
	struct menu_context mc = MENU_CXT_EMPTY;
	const struct menu_entry *e;

	ON_DBG(FRONTEND, menu_detect_collisions(cxt));

	if (fdisk_context_display_details(cxt))
		printf(_("\nHelp (expert commands):\n"));
	else
		printf(_("\nHelp:\n"));

	while ((e = next_menu_entry(cxt, &mc))) {
		if (IS_MENU_HID(e))
			continue;	/* hidden entry */
		if (IS_MENU_SEP(e) && (!e->title || !*e->title))
			printf("\n");
		else if (IS_MENU_SEP(e)) {
			color_enable(UL_COLOR_BOLD);
			printf("\n  %s\n", _(e->title));
			color_disable();
		} else
			printf("   %c   %s\n", e->key, _(e->title));
	}
	fputc('\n', stdout);

	if (cxt->parent)
		fdisk_info(cxt, _("You're editing nested '%s' partition table, "
				  "primary partition table is '%s'."),
				cxt->label->name,
				cxt->parent->label->name);

	return 0;
}

/* Asks for command, verify the key and perform the command or
 * returns the command key if no callback for the command is
 * implemented.
 *
 * Note that this function might exchange the context pointer to
 * switch to another (nested) context.
 *
 * Returns: <0 on error
 *           0 on success (the command performed)
 *          >0 if no callback (then returns the key)
 */
int process_fdisk_menu(struct fdisk_context **cxt0)
{
	struct fdisk_context *cxt = *cxt0;
	const struct menu_entry *ent;
	const struct menu *menu;
	int key, rc;
	const char *prompt;
	char buf[BUFSIZ];

	if (fdisk_context_display_details(cxt))
		prompt = _("Expert command (m for help): ");
	else
		prompt = _("Command (m for help): ");

	fputc('\n',stdout);
	rc = get_user_reply(cxt, prompt, buf, sizeof(buf));
	if (rc)
		return rc;

	key = buf[0];
	ent = get_fdisk_menu_entry(cxt, key, &menu);
	if (!ent) {
		fdisk_warnx(cxt, _("%c: unknown command"), key);
		return -EINVAL;
	}

	rc = 0;
	DBG(FRONTEND, ul_debug("selected: key=%c, entry='%s'",
				key, ent->title));

	/* menu has implemented callback, use it */
	if (menu->callback)
		rc = menu->callback(cxt0, menu, ent);
	else {
		DBG(FRONTEND, ul_debug("no callback for key '%c'", key));
		rc = -EINVAL;
	}

	DBG(FRONTEND, ul_debug("process menu done [rc=%d]", rc));
	return rc;
}

/*
 * Basic fdisk actions
 */
static int generic_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = 0;
	size_t n;

	/* actions shared between expert and normal mode */
	switch (ent->key) {
	case 'p':
		list_disk_geometry(cxt);
		list_disklabel(cxt);
		break;
	case 'w':
		if (fdisk_context_is_readonly(cxt)) {
			fdisk_warnx(cxt, _("Device open in read-only mode."));
			break;
		}
		rc = fdisk_write_disklabel(cxt);
		if (rc)
			err(EXIT_FAILURE, _("failed to write disklabel"));
		if (cxt->parent)
			break; /* nested PT, don't leave */
		fdisk_info(cxt, _("The partition table has been altered."));
		rc = fdisk_reread_partition_table(cxt);
		if (!rc)
			rc = fdisk_context_deassign_device(cxt);
		/* fallthrough */
	case 'q':
		fdisk_free_context(cxt);
		fputc('\n', stdout);
		exit(rc == 0 ? EXIT_SUCCESS : EXIT_FAILURE);
	case 'm':
		rc = print_fdisk_menu(cxt);
		break;
	case 'v':
		rc = fdisk_verify_disklabel(cxt);
		break;
	}

	/* expert mode */
	if (ent->expert) {
		switch (ent->key) {
		case 'd':
			dump_firstsector(cxt);
			break;
		case 'D':
			dump_disklabel(cxt);
			break;
		case 'r':
			rc = fdisk_context_enable_details(cxt, 0);
			break;
		}
		return rc;
	}

	/* normal mode */
	switch (ent->key) {
	case 'd':
		rc = fdisk_ask_partnum(cxt, &n, FALSE);
		if (!rc)
			rc = fdisk_delete_partition(cxt, n);
		if (rc)
			fdisk_warnx(cxt, _("Could not delete partition %zu"), n + 1);
		else
			fdisk_info(cxt, _("Partition %zu has been deleted."), n + 1);
		break;
	case 'l':
		list_partition_types(cxt);
		break;
	case 'n':
		rc = fdisk_add_partition(cxt, NULL);
		break;
	case 't':
		change_partition_type(cxt);
		break;
	case 'u':
		fdisk_context_set_unit(cxt,
			fdisk_context_use_cylinders(cxt) ? "sectors" :
							   "cylinders");
		if (fdisk_context_use_cylinders(cxt))
			fdisk_info(cxt, _("Changing display/entry units to cylinders (DEPRECATED!)."));
		else
			fdisk_info(cxt, _("Changing display/entry units to sectors."));
		break;
	case 'x':
		fdisk_context_enable_details(cxt, 1);
		break;
	case 'r':
		/* return from nested BSD to DOS */
		if (cxt->parent) {
			*cxt0 = cxt->parent;

			fdisk_info(cxt, _("Leaving nested disklabel."));
			fdisk_free_context(cxt);
			cxt = *cxt0;
		}
		break;
	}

	return rc;
}


/*
 * This is fdisk frontend for GPT specific libfdisk functions that
 * are not expported by generic libfdisk API.
 */
static int gpt_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	struct fdisk_context *mbr;
	size_t n;
	int rc = 0;

	assert(cxt);
	assert(ent);
	assert(fdisk_is_disklabel(cxt, GPT));

	DBG(FRONTEND, ul_debug("enter GPT menu"));

	if (ent->expert) {
		switch (ent->key) {
		case 'i':
			return fdisk_set_disklabel_id(cxt);
		case 'M':
			mbr = fdisk_new_nested_context(cxt, "dos");
			if (!mbr)
				return -ENOMEM;
			*cxt0 = cxt = mbr;
			fdisk_context_enable_details(cxt, 1);	/* keep us in expert mode */
			fdisk_sinfo(cxt, FDISK_INFO_SUCCESS,
					_("Entering protective/hybrid MBR disklabel."));
			return 0;
		}

		/* actions where is necessary partnum */
		rc = fdisk_ask_partnum(cxt, &n, FALSE);
		if (rc)
			return rc;

		switch(ent->key) {
		case 'u':
			rc = fdisk_gpt_partition_set_uuid(cxt, n);
			break;
		case 'n':
			rc = fdisk_gpt_partition_set_name(cxt, n);
			break;
		case 'A':
			rc = fdisk_partition_toggle_flag(cxt, n, GPT_FLAG_LEGACYBOOT);
			break;
		case 'B':
			rc = fdisk_partition_toggle_flag(cxt, n, GPT_FLAG_NOBLOCK);
			break;
		case 'R':
			rc = fdisk_partition_toggle_flag(cxt, n, GPT_FLAG_REQUIRED);
			break;
		case 'S':
			rc = fdisk_partition_toggle_flag(cxt, n, GPT_FLAG_GUIDSPECIFIC);
			break;
		}
	}
	return rc;
}


/*
 * This is fdisk frontend for MBR specific libfdisk functions that
 * are not expported by generic libfdisk API.
 */
static int dos_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = 0;

	DBG(FRONTEND, ul_debug("enter DOS menu"));

	if (!ent->expert) {
		switch (ent->key) {
		case 'a':
		{
			size_t n;
			rc = fdisk_ask_partnum(cxt, &n, FALSE);
			if (!rc)
				rc = fdisk_partition_toggle_flag(cxt, n, DOS_FLAG_ACTIVE);
			break;
		}
		case 'b':
		{
			struct fdisk_context *bsd
					= fdisk_new_nested_context(cxt, "bsd");
			if (!bsd)
				return -ENOMEM;
			if (!fdisk_dev_has_disklabel(bsd))
				rc = fdisk_create_disklabel(bsd, "bsd");
			if (rc)
				fdisk_free_context(bsd);
			else {
				*cxt0 = cxt = bsd;
				fdisk_sinfo(cxt, FDISK_INFO_SUCCESS,
						_("Entering nested BSD disklabel."));
			}
			break;
		}
		case 'c':
			toggle_dos_compatibility_flag(cxt);
			break;
		}
		return rc;
	}

	/* expert mode */
	switch (ent->key) {
	case 'b':
	{
		size_t n;
		rc = fdisk_ask_partnum(cxt, &n, FALSE);
		if (!rc)
			rc = fdisk_dos_move_begin(cxt, n);
		break;
	}
	case 'f':
		rc = fdisk_dos_fix_order(cxt);
		break;
	case 'i':
		rc = fdisk_set_disklabel_id(cxt);
		break;
	case 'M':
		/* return from nested MBR to GPT */
		if (cxt->parent) {
			*cxt0 = cxt->parent;

			fdisk_info(cxt, _("Leaving nested disklabel."));
			fdisk_free_context(cxt);
			cxt = *cxt0;
		}
		break;
	}
	return rc;
}

static int sun_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = 0;

	DBG(FRONTEND, ul_debug("enter SUN menu"));

	assert(cxt);
	assert(ent);
	assert(fdisk_is_disklabel(cxt, SUN));

	DBG(FRONTEND, ul_debug("enter SUN menu"));

	/* normal mode */
	if (!ent->expert) {
		size_t n;

		rc = fdisk_ask_partnum(cxt, &n, FALSE);
		if (rc)
			return rc;
		switch (ent->key) {
		case 'a':
			rc = fdisk_partition_toggle_flag(cxt, n, SUN_FLAG_RONLY);
			break;
		case 'c':
			rc = fdisk_partition_toggle_flag(cxt, n, SUN_FLAG_UNMNT);
			break;
		}
		return rc;
	}

	/* expert mode */
	switch (ent->key) {
	case 'a':
		rc = fdisk_sun_set_alt_cyl(cxt);
		break;
	case 'e':
		rc = fdisk_sun_set_xcyl(cxt);
		break;
	case 'i':
		rc = fdisk_sun_set_ilfact(cxt);
		break;
	case 'o':
		rc = fdisk_sun_set_rspeed(cxt);
		break;
	case 'y':
		rc = fdisk_sun_set_pcylcount(cxt);
		break;
	}
	return rc;
}

static int sgi_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = -EINVAL;
	size_t n = 0;

	DBG(FRONTEND, ul_debug("enter SGI menu"));

	assert(cxt);
	assert(ent);
	assert(fdisk_is_disklabel(cxt, SGI));

	if (ent->expert)
		return rc;

	switch (ent->key) {
	case 'a':
		rc = fdisk_ask_partnum(cxt, &n, FALSE);
		if (!rc)
			rc = fdisk_partition_toggle_flag(cxt, n, SGI_FLAG_BOOT);
		break;
	case 'b':
		fdisk_sgi_set_bootfile(cxt);
		break;
	case 'c':
		rc = fdisk_ask_partnum(cxt, &n, FALSE);
		if (!rc)
			rc = fdisk_partition_toggle_flag(cxt, n, SGI_FLAG_SWAP);
		break;
	case 'i':
		rc = fdisk_sgi_create_info(cxt);
		break;
	}

	return rc;
}

/*
 * This is fdisk frontend for BSD specific libfdisk functions that
 * are not expported by generic libfdisk API.
 */
static int bsd_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = 0, org;

	assert(cxt);
	assert(ent);
	assert(fdisk_is_disklabel(cxt, BSD));

	DBG(FRONTEND, ul_debug("enter BSD menu"));

	switch(ent->key) {
	case 'e':
		rc = fdisk_bsd_edit_disklabel(cxt);
		break;
	case 'i':
		rc = fdisk_bsd_write_bootstrap(cxt);
		break;
	case 's':
		org = fdisk_context_display_details(cxt);

		fdisk_context_enable_details(cxt, 1);
		list_disklabel(cxt);
		fdisk_context_enable_details(cxt, org);
		break;
	case 'x':
		rc = fdisk_bsd_link_partition(cxt);
		break;
	}
	return rc;
}

/* C/H/S commands */
static int geo_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = -EINVAL;
	uintmax_t c = 0, h = 0, s = 0;

	DBG(FRONTEND, ul_debug("enter GEO menu"));

	assert(cxt);
	assert(ent);

	switch (ent->key) {
	case 'c':
		rc =  fdisk_ask_number(cxt, 1, cxt->geom.cylinders,
				1048576, _("Number of cylinders"), &c);
		break;
	case 'h':
		rc =  fdisk_ask_number(cxt, 1, cxt->geom.heads,
				256, _("Number of heads"), &h);
		break;
	case 's':
		rc =  fdisk_ask_number(cxt, 1, cxt->geom.sectors,
				63, _("Number of sectors"), &s);
		break;
	}

	if (!rc)
		fdisk_override_geometry(cxt, c, h, s);
	return rc;
}

static int createlabel_menu_cb(struct fdisk_context **cxt0,
		       const struct menu *menu __attribute__((__unused__)),
		       const struct menu_entry *ent)
{
	struct fdisk_context *cxt = *cxt0;
	int rc = -EINVAL;

	DBG(FRONTEND, ul_debug("enter Create label menu"));

	assert(cxt);
	assert(ent);

	if (ent->expert) {
		switch (ent->key) {
		case 'g':
			/* Deprecated, use 'G' in main menu, just for backward
			 * compatibility only. */
			rc = fdisk_create_disklabel(cxt, "sgi");
			break;
		}
		return rc;
	}

	switch (ent->key) {
		case 'g':
			fdisk_create_disklabel(cxt, "gpt");
			break;
		case 'G':
			fdisk_create_disklabel(cxt, "sgi");
			break;
		case 'o':
			fdisk_create_disklabel(cxt, "dos");
			break;
		case 's':
			fdisk_create_disklabel(cxt, "sun");
			break;
	}
	return rc;
}
/> -rw-r--r--Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt6
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-rw-r--r--tools/testing/selftests/net/psock_fanout.c35
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-rw-r--r--tools/testing/selftests/powerpc/benchmarks/Makefile7
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-rw-r--r--tools/testing/selftests/powerpc/benchmarks/fork.c325
-rw-r--r--tools/testing/selftests/powerpc/copyloops/Makefile4
-rw-r--r--tools/testing/selftests/powerpc/tm/Makefile2
-rw-r--r--tools/testing/selftests/powerpc/tm/tm-sigreturn.c92
-rw-r--r--tools/testing/selftests/powerpc/tm/tm-unavailable.c24
-rw-r--r--tools/testing/selftests/proc/.gitignore8
-rw-r--r--tools/testing/selftests/proc/Makefile13
-rw-r--r--tools/testing/selftests/proc/config1
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-rw-r--r--tools/testing/selftests/proc/proc-self-map-files-001.c82
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-rw-r--r--virt/kvm/arm/arch_timer.c10
-rw-r--r--virt/kvm/arm/arm.c48
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-rw-r--r--virt/kvm/arm/vgic/vgic-v3.c66
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-rw-r--r--virt/kvm/arm/vgic/vgic.h3
-rw-r--r--virt/kvm/kvm_main.c36
13247 files changed, 635842 insertions, 824069 deletions
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 000000000000..faffc0d5af4e
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,428 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# clang-format configuration file. Intended for clang-format >= 4.
+#
+# For more information, see:
+#
+# Documentation/process/clang-format.rst
+# https://clang.llvm.org/docs/ClangFormat.html
+# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
+#
+---
+AccessModifierOffset: -4
+AlignAfterOpenBracket: Align
+AlignConsecutiveAssignments: false
+AlignConsecutiveDeclarations: false
+#AlignEscapedNewlines: Left # Unknown to clang-format-4.0
+AlignOperands: true
+AlignTrailingComments: false
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortBlocksOnASingleLine: false
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortIfStatementsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: false
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+ AfterClass: false
+ AfterControlStatement: false
+ AfterEnum: false
+ AfterFunction: true
+ AfterNamespace: true
+ AfterObjCDeclaration: false
+ AfterStruct: false
+ AfterUnion: false
+ #AfterExternBlock: false # Unknown to clang-format-5.0
+ BeforeCatch: false
+ BeforeElse: false
+ IndentBraces: false
+ #SplitEmptyFunction: true # Unknown to clang-format-4.0
+ #SplitEmptyRecord: true # Unknown to clang-format-4.0
+ #SplitEmptyNamespace: true # Unknown to clang-format-4.0
+BreakBeforeBinaryOperators: None
+BreakBeforeBraces: Custom
+#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
+BreakBeforeTernaryOperators: false
+BreakConstructorInitializersBeforeComma: false
+#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: false
+ColumnLimit: 80
+CommentPragmas: '^ IWYU pragma:'
+#CompactNamespaces: false # Unknown to clang-format-4.0
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+ConstructorInitializerIndentWidth: 8
+ContinuationIndentWidth: 8
+Cpp11BracedListStyle: false
+DerivePointerAlignment: false
+DisableFormat: false
+ExperimentalAutoDetectBinPacking: false
+#FixNamespaceComments: false # Unknown to clang-format-4.0
+
+# Taken from:
+# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
+# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
+# | sort | uniq
+ForEachMacros:
+ - 'apei_estatus_for_each_section'
+ - 'ata_for_each_dev'
+ - 'ata_for_each_link'
+ - 'ax25_for_each'
+ - 'ax25_uid_for_each'
+ - 'bio_for_each_integrity_vec'
+ - '__bio_for_each_segment'
+ - 'bio_for_each_segment'
+ - 'bio_for_each_segment_all'
+ - 'bio_list_for_each'
+ - 'bip_for_each_vec'
+ - 'blkg_for_each_descendant_post'
+ - 'blkg_for_each_descendant_pre'
+ - 'blk_queue_for_each_rl'
+ - 'bond_for_each_slave'
+ - 'bond_for_each_slave_rcu'
+ - 'btree_for_each_safe128'
+ - 'btree_for_each_safe32'
+ - 'btree_for_each_safe64'
+ - 'btree_for_each_safel'
+ - 'card_for_each_dev'
+ - 'cgroup_taskset_for_each'
+ - 'cgroup_taskset_for_each_leader'
+ - 'cpufreq_for_each_entry'
+ - 'cpufreq_for_each_entry_idx'
+ - 'cpufreq_for_each_valid_entry'
+ - 'cpufreq_for_each_valid_entry_idx'
+ - 'css_for_each_child'
+ - 'css_for_each_descendant_post'
+ - 'css_for_each_descendant_pre'
+ - 'device_for_each_child_node'
+ - 'drm_atomic_crtc_for_each_plane'
+ - 'drm_atomic_crtc_state_for_each_plane'
+ - 'drm_atomic_crtc_state_for_each_plane_state'
+ - 'drm_for_each_connector_iter'
+ - 'drm_for_each_crtc'
+ - 'drm_for_each_encoder'
+ - 'drm_for_each_encoder_mask'
+ - 'drm_for_each_fb'
+ - 'drm_for_each_legacy_plane'
+ - 'drm_for_each_plane'
+ - 'drm_for_each_plane_mask'
+ - 'drm_mm_for_each_hole'
+ - 'drm_mm_for_each_node'
+ - 'drm_mm_for_each_node_in_range'
+ - 'drm_mm_for_each_node_safe'
+ - 'for_each_active_drhd_unit'
+ - 'for_each_active_iommu'
+ - 'for_each_available_child_of_node'
+ - 'for_each_bio'
+ - 'for_each_board_func_rsrc'
+ - 'for_each_bvec'
+ - 'for_each_child_of_node'
+ - 'for_each_clear_bit'
+ - 'for_each_clear_bit_from'
+ - 'for_each_cmsghdr'
+ - 'for_each_compatible_node'
+ - 'for_each_console'
+ - 'for_each_cpu'
+ - 'for_each_cpu_and'
+ - 'for_each_cpu_not'
+ - 'for_each_cpu_wrap'
+ - 'for_each_dev_addr'
+ - 'for_each_dma_cap_mask'
+ - 'for_each_drhd_unit'
+ - 'for_each_dss_dev'
+ - 'for_each_efi_memory_desc'
+ - 'for_each_efi_memory_desc_in_map'
+ - 'for_each_endpoint_of_node'
+ - 'for_each_evictable_lru'
+ - 'for_each_fib6_node_rt_rcu'
+ - 'for_each_fib6_walker_rt'
+ - 'for_each_free_mem_range'
+ - 'for_each_free_mem_range_reverse'
+ - 'for_each_func_rsrc'
+ - 'for_each_hstate'
+ - 'for_each_if'
+ - 'for_each_iommu'
+ - 'for_each_ip_tunnel_rcu'
+ - 'for_each_irq_nr'
+ - 'for_each_lru'
+ - 'for_each_matching_node'
+ - 'for_each_matching_node_and_match'
+ - 'for_each_memblock'
+ - 'for_each_memblock_type'
+ - 'for_each_memcg_cache_index'
+ - 'for_each_mem_pfn_range'
+ - 'for_each_mem_range'
+ - 'for_each_mem_range_rev'
+ - 'for_each_migratetype_order'
+ - 'for_each_msi_entry'
+ - 'for_each_net'
+ - 'for_each_netdev'
+ - 'for_each_netdev_continue'
+ - 'for_each_netdev_continue_rcu'
+ - 'for_each_netdev_feature'
+ - 'for_each_netdev_in_bond_rcu'
+ - 'for_each_netdev_rcu'
+ - 'for_each_netdev_reverse'
+ - 'for_each_netdev_safe'
+ - 'for_each_net_rcu'
+ - 'for_each_new_connector_in_state'
+ - 'for_each_new_crtc_in_state'
+ - 'for_each_new_plane_in_state'
+ - 'for_each_new_private_obj_in_state'
+ - 'for_each_node'
+ - 'for_each_node_by_name'
+ - 'for_each_node_by_type'
+ - 'for_each_node_mask'
+ - 'for_each_node_state'
+ - 'for_each_node_with_cpus'
+ - 'for_each_node_with_property'
+ - 'for_each_of_allnodes'
+ - 'for_each_of_allnodes_from'
+ - 'for_each_of_pci_range'
+ - 'for_each_old_connector_in_state'
+ - 'for_each_old_crtc_in_state'
+ - 'for_each_oldnew_connector_in_state'
+ - 'for_each_oldnew_crtc_in_state'
+ - 'for_each_oldnew_plane_in_state'
+ - 'for_each_oldnew_private_obj_in_state'
+ - 'for_each_old_plane_in_state'
+ - 'for_each_old_private_obj_in_state'
+ - 'for_each_online_cpu'
+ - 'for_each_online_node'
+ - 'for_each_online_pgdat'
+ - 'for_each_pci_bridge'
+ - 'for_each_pci_dev'
+ - 'for_each_pci_msi_entry'
+ - 'for_each_populated_zone'
+ - 'for_each_possible_cpu'
+ - 'for_each_present_cpu'
+ - 'for_each_prime_number'
+ - 'for_each_prime_number_from'
+ - 'for_each_process'
+ - 'for_each_process_thread'
+ - 'for_each_property_of_node'
+ - 'for_each_reserved_mem_region'
+ - 'for_each_resv_unavail_range'
+ - 'for_each_rtdcom'
+ - 'for_each_rtdcom_safe'
+ - 'for_each_set_bit'
+ - 'for_each_set_bit_from'
+ - 'for_each_sg'
+ - 'for_each_sg_page'
+ - '__for_each_thread'
+ - 'for_each_thread'
+ - 'for_each_zone'
+ - 'for_each_zone_zonelist'
+ - 'for_each_zone_zonelist_nodemask'
+ - 'fwnode_for_each_available_child_node'
+ - 'fwnode_for_each_child_node'
+ - 'fwnode_graph_for_each_endpoint'
+ - 'gadget_for_each_ep'
+ - 'hash_for_each'
+ - 'hash_for_each_possible'
+ - 'hash_for_each_possible_rcu'
+ - 'hash_for_each_possible_rcu_notrace'
+ - 'hash_for_each_possible_safe'
+ - 'hash_for_each_rcu'
+ - 'hash_for_each_safe'
+ - 'hctx_for_each_ctx'
+ - 'hlist_bl_for_each_entry'
+ - 'hlist_bl_for_each_entry_rcu'
+ - 'hlist_bl_for_each_entry_safe'
+ - 'hlist_for_each'
+ - 'hlist_for_each_entry'
+ - 'hlist_for_each_entry_continue'
+ - 'hlist_for_each_entry_continue_rcu'
+ - 'hlist_for_each_entry_continue_rcu_bh'
+ - 'hlist_for_each_entry_from'
+ - 'hlist_for_each_entry_from_rcu'
+ - 'hlist_for_each_entry_rcu'
+ - 'hlist_for_each_entry_rcu_bh'
+ - 'hlist_for_each_entry_rcu_notrace'
+ - 'hlist_for_each_entry_safe'
+ - '__hlist_for_each_rcu'
+ - 'hlist_for_each_safe'
+ - 'hlist_nulls_for_each_entry'
+ - 'hlist_nulls_for_each_entry_from'
+ - 'hlist_nulls_for_each_entry_rcu'
+ - 'hlist_nulls_for_each_entry_safe'
+ - 'ide_host_for_each_port'
+ - 'ide_port_for_each_dev'
+ - 'ide_port_for_each_present_dev'
+ - 'idr_for_each_entry'
+ - 'idr_for_each_entry_continue'
+ - 'idr_for_each_entry_ul'
+ - 'inet_bind_bucket_for_each'
+ - 'inet_lhash2_for_each_icsk_rcu'
+ - 'iov_for_each'
+ - 'key_for_each'
+ - 'key_for_each_safe'
+ - 'klp_for_each_func'
+ - 'klp_for_each_object'
+ - 'kvm_for_each_memslot'
+ - 'kvm_for_each_vcpu'
+ - 'list_for_each'
+ - 'list_for_each_entry'
+ - 'list_for_each_entry_continue'
+ - 'list_for_each_entry_continue_rcu'
+ - 'list_for_each_entry_continue_reverse'
+ - 'list_for_each_entry_from'
+ - 'list_for_each_entry_from_reverse'
+ - 'list_for_each_entry_lockless'
+ - 'list_for_each_entry_rcu'
+ - 'list_for_each_entry_reverse'
+ - 'list_for_each_entry_safe'
+ - 'list_for_each_entry_safe_continue'
+ - 'list_for_each_entry_safe_from'
+ - 'list_for_each_entry_safe_reverse'
+ - 'list_for_each_prev'
+ - 'list_for_each_prev_safe'
+ - 'list_for_each_safe'
+ - 'llist_for_each'
+ - 'llist_for_each_entry'
+ - 'llist_for_each_entry_safe'
+ - 'llist_for_each_safe'
+ - 'media_device_for_each_entity'
+ - 'media_device_for_each_intf'
+ - 'media_device_for_each_link'
+ - 'media_device_for_each_pad'
+ - 'netdev_for_each_lower_dev'
+ - 'netdev_for_each_lower_private'
+ - 'netdev_for_each_lower_private_rcu'
+ - 'netdev_for_each_mc_addr'
+ - 'netdev_for_each_uc_addr'
+ - 'netdev_for_each_upper_dev_rcu'
+ - 'netdev_hw_addr_list_for_each'
+ - 'nft_rule_for_each_expr'
+ - 'nla_for_each_attr'
+ - 'nla_for_each_nested'
+ - 'nlmsg_for_each_attr'
+ - 'nlmsg_for_each_msg'
+ - 'nr_neigh_for_each'
+ - 'nr_neigh_for_each_safe'
+ - 'nr_node_for_each'
+ - 'nr_node_for_each_safe'
+ - 'of_for_each_phandle'
+ - 'of_property_for_each_string'
+ - 'of_property_for_each_u32'
+ - 'pci_bus_for_each_resource'
+ - 'ping_portaddr_for_each_entry'
+ - 'plist_for_each'
+ - 'plist_for_each_continue'
+ - 'plist_for_each_entry'
+ - 'plist_for_each_entry_continue'
+ - 'plist_for_each_entry_safe'
+ - 'plist_for_each_safe'
+ - 'pnp_for_each_card'
+ - 'pnp_for_each_dev'
+ - 'protocol_for_each_card'
+ - 'protocol_for_each_dev'
+ - 'queue_for_each_hw_ctx'
+ - 'radix_tree_for_each_contig'
+ - 'radix_tree_for_each_slot'
+ - 'radix_tree_for_each_tagged'
+ - 'rbtree_postorder_for_each_entry_safe'
+ - 'resource_list_for_each_entry'
+ - 'resource_list_for_each_entry_safe'
+ - 'rhl_for_each_entry_rcu'
+ - 'rhl_for_each_rcu'
+ - 'rht_for_each'
+ - 'rht_for_each_continue'
+ - 'rht_for_each_entry'
+ - 'rht_for_each_entry_continue'
+ - 'rht_for_each_entry_rcu'
+ - 'rht_for_each_entry_rcu_continue'
+ - 'rht_for_each_entry_safe'
+ - 'rht_for_each_rcu'
+ - 'rht_for_each_rcu_continue'
+ - '__rq_for_each_bio'
+ - 'rq_for_each_segment'
+ - 'scsi_for_each_prot_sg'
+ - 'scsi_for_each_sg'
+ - 'sctp_for_each_hentry'
+ - 'sctp_skb_for_each'
+ - 'shdma_for_each_chan'
+ - '__shost_for_each_device'
+ - 'shost_for_each_device'
+ - 'sk_for_each'
+ - 'sk_for_each_bound'
+ - 'sk_for_each_entry_offset_rcu'
+ - 'sk_for_each_from'
+ - 'sk_for_each_rcu'
+ - 'sk_for_each_safe'
+ - 'sk_nulls_for_each'
+ - 'sk_nulls_for_each_from'
+ - 'sk_nulls_for_each_rcu'
+ - 'snd_pcm_group_for_each_entry'
+ - 'snd_soc_dapm_widget_for_each_path'
+ - 'snd_soc_dapm_widget_for_each_path_safe'
+ - 'snd_soc_dapm_widget_for_each_sink_path'
+ - 'snd_soc_dapm_widget_for_each_source_path'
+ - 'tb_property_for_each'
+ - 'udp_portaddr_for_each_entry'
+ - 'udp_portaddr_for_each_entry_rcu'
+ - 'usb_hub_for_each_child'
+ - 'v4l2_device_for_each_subdev'
+ - 'v4l2_m2m_for_each_dst_buf'
+ - 'v4l2_m2m_for_each_dst_buf_safe'
+ - 'v4l2_m2m_for_each_src_buf'
+ - 'v4l2_m2m_for_each_src_buf_safe'
+ - 'zorro_for_each_dev'
+
+#IncludeBlocks: Preserve # Unknown to clang-format-5.0
+IncludeCategories:
+ - Regex: '.*'
+ Priority: 1
+IncludeIsMainRegex: '(Test)?$'
+IndentCaseLabels: false
+#IndentPPDirectives: None # Unknown to clang-format-5.0
+IndentWidth: 8
+IndentWrappedFunctionNames: true
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+MacroBlockBegin: ''
+MacroBlockEnd: ''
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: Inner
+#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
+ObjCBlockIndentWidth: 8
+ObjCSpaceAfterProperty: true
+ObjCSpaceBeforeProtocolList: true
+
+# Taken from git's rules
+#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0
+PenaltyBreakBeforeFirstCallParameter: 30
+PenaltyBreakComment: 10
+PenaltyBreakFirstLessLess: 0
+PenaltyBreakString: 10
+PenaltyExcessCharacter: 100
+PenaltyReturnTypeOnItsOwnLine: 60
+
+PointerAlignment: Right
+ReflowComments: false
+SortIncludes: false
+#SortUsingDeclarations: false # Unknown to clang-format-4.0
+SpaceAfterCStyleCast: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0
+#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0
+SpaceBeforeParens: ControlStatements
+#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles: false
+SpacesInContainerLiterals: false
+SpacesInCStyleCastParentheses: false
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+Standard: Cpp03
+TabWidth: 8
+UseTab: Always
+...
diff --git a/.gitignore b/.gitignore
index 1be78fd8163b..97ba6b79834c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,6 +11,7 @@
#
.*
*.a
+*.asn1.[ch]
*.bin
*.bz2
*.c.[012]*.*
@@ -22,6 +23,7 @@
*.gz
*.i
*.ko
+*.lex.c
*.ll
*.lst
*.lz4
@@ -37,6 +39,7 @@
*.so.dbg
*.su
*.symtypes
+*.tab.[ch]
*.tar
*.xz
Module.symvers
@@ -81,12 +84,14 @@ modules.builtin
!.gitignore
!.mailmap
!.cocciconfig
+!.clang-format
#
# Generated include files
#
include/config
include/generated
+include/ksym
arch/*/include/generated
# stgit generated dirs
@@ -127,7 +132,3 @@ all.config
# Kdevelop4
*.kdev4
-
-#Automatically generated by ASN.1 compiler
-net/ipv4/netfilter/nf_nat_snmp_basic-asn1.c
-net/ipv4/netfilter/nf_nat_snmp_basic-asn1.h
diff --git a/.mailmap b/.mailmap
index 4cb8bf0a8402..29ddeb1bf015 100644
--- a/.mailmap
+++ b/.mailmap
@@ -18,6 +18,7 @@ Aleksey Gorelov <aleksey_gorelov@phoenix.com>
Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
Al Viro <viro@ftp.linux.org.uk>
Al Viro <viro@zenIV.linux.org.uk>
+Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
Andreas Herrmann <aherrman@de.ibm.com>
Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
Andrew Morton <akpm@linux-foundation.org>
@@ -33,9 +34,9 @@ Axel Lin <axel.lin@gmail.com>
Ben Gardner <bgardner@wabtec.com>
Ben M Cahill <ben.m.cahill@intel.com>
Björn Steinbrink <B.Steinbrink@gmx.de>
-Boris Brezillon <boris.brezillon@free-electrons.com>
-Boris Brezillon <boris.brezillon@free-electrons.com> <b.brezillon.dev@gmail.com>
-Boris Brezillon <boris.brezillon@free-electrons.com> <b.brezillon@overkiz.com>
+Boris Brezillon <boris.brezillon@bootlin.com> <boris.brezillon@free-electrons.com>
+Boris Brezillon <boris.brezillon@bootlin.com> <b.brezillon.dev@gmail.com>
+Boris Brezillon <boris.brezillon@bootlin.com> <b.brezillon@overkiz.com>
Brian Avery <b.avery@hp.com>
Brian King <brking@us.ibm.com>
Christoph Hellwig <hch@lst.de>
@@ -62,6 +63,7 @@ Frank Zago <fzago@systemfabricworks.com>
Greg Kroah-Hartman <greg@echidna.(none)>
Greg Kroah-Hartman <gregkh@suse.de>
Greg Kroah-Hartman <greg@kroah.com>
+Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
Henk Vergonet <Henk.Vergonet@gmail.com>
Henrik Kretzschmar <henne@nachtwindheim.de>
Henrik Rydberg <rydberg@bitmath.org>
@@ -100,6 +102,8 @@ Koushik <raghavendra.koushik@neterion.com>
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
+Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
Leonid I Ananiev <leonid.i.ananiev@intel.com>
Linas Vepstas <linas@austin.ibm.com>
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
@@ -126,6 +130,7 @@ Mayuresh Janorkar <mayur@ti.com>
Michael Buesch <m@bues.ch>
Michel Dänzer <michel@tungstengraphics.com>
Miodrag Dinic <miodrag.dinic@mips.com> <miodrag.dinic@imgtec.com>
+Miquel Raynal <miquel.raynal@bootlin.com> <miquel.raynal@free-electrons.com>
Mitesh shah <mshah@teja.com>
Mohit Kumar <mohit.kumar@st.com> <mohit.kumar.dhaka@gmail.com>
Morten Welinder <terra@gnome.org>
diff --git a/COPYING b/COPYING
index ca442d313d86..da4cb28febe6 100644
--- a/COPYING
+++ b/COPYING
@@ -1,356 +1,18 @@
+The Linux Kernel is provided under:
- NOTE! This copyright does *not* cover user programs that use kernel
- services by normal system calls - this is merely considered normal use
- of the kernel, and does *not* fall under the heading of "derived work".
- Also note that the GPL below is copyrighted by the Free Software
- Foundation, but the instance of code that it refers to (the Linux
- kernel) is copyrighted by me and others who actually wrote it.
+ SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
- Also note that the only valid version of the GPL as far as the kernel
- is concerned is _this_ particular version of the license (ie v2, not
- v2.2 or v3.x or whatever), unless explicitly otherwise stated.
+Being under the terms of the GNU General Public License version 2 only,
+according with:
- Linus Torvalds
+ LICENSES/preferred/GPL-2.0
-----------------------------------------
+With an explicit syscall exception, as stated at:
- GNU GENERAL PUBLIC LICENSE
- Version 2, June 1991
+ LICENSES/exceptions/Linux-syscall-note
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
- 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
+In addition, other licenses may also apply. Please see:
- Preamble
+ Documentation/process/license-rules.rst
- The licenses for most software are designed to take away your
-freedom to share and change it. By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users. This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it. (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.) You can apply it to
-your programs, too.
-
- When we speak of free software, we are referring to freedom, not
-price. Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
- To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
- For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must give the recipients all the rights that
-you have. You must make sure that they, too, receive or can get the
-source code. And you must show them these terms so they know their
-rights.
-
- We protect your rights with two steps: (1) copyright the software, and
-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
- Also, for each author's protection and ours, we want to make certain
-that everyone understands that there is no warranty for this free
-software. If the software is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original, so
-that any problems introduced by others will not reflect on the original
-authors' reputations.
-
- Finally, any free program is threatened constantly by software
-patents. We wish to avoid the danger that redistributors of a free
-program will individually obtain patent licenses, in effect making the
-program proprietary. To prevent this, we have made it clear that any
-patent must be licensed for everyone's free use or not licensed at all.
-
- The precise terms and conditions for copying, distribution and
-modification follow.
-
- GNU GENERAL PUBLIC LICENSE
- TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
- 0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
-under the terms of this General Public License. The "Program", below,
-refers to any such program or work, and a "work based on the Program"
-means either the Program or any derivative work under copyright law:
-that is to say, a work containing the Program or a portion of it,
-either verbatim or with modifications and/or translated into another
-language. (Hereinafter, translation is included without limitation in
-the term "modification".) Each licensee is addressed as "you".
-
-Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope. The act of
-running the Program is not restricted, and the output from the Program
-is covered only if its contents constitute a work based on the
-Program (independent of having been made by running the Program).
-Whether that is true depends on what the Program does.
-
- 1. You may copy and distribute verbatim copies of the Program's
-source code as you receive it, in any medium, provided that you
-conspicuously and appropriately publish on each copy an appropriate
-copyright notice and disclaimer of warranty; keep intact all the
-notices that refer to this License and to the absence of any warranty;
-and give any other recipients of the Program a copy of this License
-along with the Program.
-
-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
-
- 2. You may modify your copy or copies of the Program or any portion
-of it, thus forming a work based on the Program, and copy and
-distribute such modifications or work under the terms of Section 1
-above, provided that you also meet all of these conditions:
-
- a) You must cause the modified files to carry prominent notices
- stating that you changed the files and the date of any change.
-
- b) You must cause any work that you distribute or publish, that in
- whole or in part contains or is derived from the Program or any
- part thereof, to be licensed as a whole at no charge to all third
- parties under the terms of this License.
-
- c) If the modified program normally reads commands interactively
- when run, you must cause it, when started running for such
- interactive use in the most ordinary way, to print or display an
- announcement including an appropriate copyright notice and a
- notice that there is no warranty (or else, saying that you provide
- a warranty) and that users may redistribute the program under
- these conditions, and telling the user how to view a copy of this
- License. (Exception: if the Program itself is interactive but
- does not normally print such an announcement, your work based on
- the Program is not required to print an announcement.)
-
-These requirements apply to the modified work as a whole. If
-identifiable sections of that work are not derived from the Program,
-and can be reasonably considered independent and separate works in
-themselves, then this License, and its terms, do not apply to those
-sections when you distribute them as separate works. But when you
-distribute the same sections as part of a whole which is a work based
-on the Program, the distribution of the whole must be on the terms of
-this License, whose permissions for other licensees extend to the
-entire whole, and thus to each and every part regardless of who wrote it.
-
-Thus, it is not the intent of this section to claim rights or contest
-your rights to work written entirely by you; rather, the intent is to
-exercise the right to control the distribution of derivative or
-collective works based on the Program.
-
-In addition, mere aggregation of another work not based on the Program
-with the Program (or with a work based on the Program) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
-
- 3. You may copy and distribute the Program (or a work based on it,
-under Section 2) in object code or executable form under the terms of
-Sections 1 and 2 above provided that you also do one of the following:
-
- a) Accompany it with the complete corresponding machine-readable
- source code, which must be distributed under the terms of Sections
- 1 and 2 above on a medium customarily used for software interchange; or,
-
- b) Accompany it with a written offer, valid for at least three
- years, to give any third party, for a charge no more than your
- cost of physically performing source distribution, a complete
- machine-readable copy of the corresponding source code, to be
- distributed under the terms of Sections 1 and 2 above on a medium
- customarily used for software interchange; or,
-
- c) Accompany it with the information you received as to the offer
- to distribute corresponding source code. (This alternative is
- allowed only for noncommercial distribution and only if you
- received the program in object code or executable form with such
- an offer, in accord with Subsection b above.)
-
-The source code for a work means the preferred form of the work for
-making modifications to it. For an executable work, complete source
-code means all the source code for all modules it contains, plus any
-associated interface definition files, plus the scripts used to
-control compilation and installation of the executable. However, as a
-special exception, the source code distributed need not include
-anything that is normally distributed (in either source or binary
-form) with the major components (compiler, kernel, and so on) of the
-operating system on which the executable runs, unless that component
-itself accompanies the executable.
-
-If distribution of executable or object code is made by offering
-access to copy from a designated place, then offering equivalent
-access to copy the source code from the same place counts as
-distribution of the source code, even though third parties are not
-compelled to copy the source along with the object code.
-
- 4. You may not copy, modify, sublicense, or distribute the Program
-except as expressly provided under this License. Any attempt
-otherwise to copy, modify, sublicense or distribute the Program is
-void, and will automatically terminate your rights under this License.
-However, parties who have received copies, or rights, from you under
-this License will not have their licenses terminated so long as such
-parties remain in full compliance.
-
- 5. You are not required to accept this License, since you have not
-signed it. However, nothing else grants you permission to modify or
-distribute the Program or its derivative works. These actions are
-prohibited by law if you do not accept this License. Therefore, by
-modifying or distributing the Program (or any work based on the
-Program), you indicate your acceptance of this License to do so, and
-all its terms and conditions for copying, distributing or modifying
-the Program or works based on it.
-
- 6. Each time you redistribute the Program (or any work based on the
-Program), the recipient automatically receives a license from the
-original licensor to copy, distribute or modify the Program subject to
-these terms and conditions. You may not impose any further
-restrictions on the recipients' exercise of the rights granted herein.
-You are not responsible for enforcing compliance by third parties to
-this License.
-
- 7. If, as a consequence of a court judgment or allegation of patent
-infringement or for any other reason (not limited to patent issues),
-conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
-excuse you from the conditions of this License. If you cannot
-distribute so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you
-may not distribute the Program at all. For example, if a patent
-license would not permit royalty-free redistribution of the Program by
-all those who receive copies directly or indirectly through you, then
-the only way you could satisfy both it and this License would be to
-refrain entirely from distribution of the Program.
-
-If any portion of this section is held invalid or unenforceable under
-any particular circumstance, the balance of the section is intended to
-apply and the section as a whole is intended to apply in other
-circumstances.
-
-It is not the purpose of this section to induce you to infringe any
-patents or other property right claims or to contest validity of any
-such claims; this section has the sole purpose of protecting the
-integrity of the free software distribution system, which is
-implemented by public license practices. Many people have made
-generous contributions to the wide range of software distributed
-through that system in reliance on consistent application of that
-system; it is up to the author/donor to decide if he or she is willing
-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
-
- 8. If the distribution and/or use of the Program is restricted in
-certain countries either by patents or by copyrighted interfaces, the
-original copyright holder who places the Program under this License
-may add an explicit geographical distribution limitation excluding
-those countries, so that distribution is permitted only in or among
-countries not thus excluded. In such case, this License incorporates
-the limitation as if written in the body of this License.
-
- 9. The Free Software Foundation may publish revised and/or new versions
-of the General Public License from time to time. Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
-Each version is given a distinguishing version number. If the Program
-specifies a version number of this License which applies to it and "any
-later version", you have the option of following the terms and conditions
-either of that version or of any later version published by the Free
-Software Foundation. If the Program does not specify a version number of
-this License, you may choose any version ever published by the Free Software
-Foundation.
-
- 10. If you wish to incorporate parts of the Program into other free
-programs whose distribution conditions are different, write to the author
-to ask for permission. For software which is copyrighted by the Free
-Software Foundation, write to the Free Software Foundation; we sometimes
-make exceptions for this. Our decision will be guided by the two goals
-of preserving the free status of all derivatives of our free software and
-of promoting the sharing and reuse of software generally.
-
- NO WARRANTY
-
- 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-REPAIR OR CORRECTION.
-
- 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Programs
-
- If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
- To do so, attach the following notices to the program. It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
- <one line to give the program's name and a brief idea of what it does.>
- Copyright (C) <year> <name of author>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
- Gnomovision version 69, Copyright (C) year name of author
- Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
- This is free software, and you are welcome to redistribute it
- under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License. Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary. Here is a sample; alter the names:
-
- Yoyodyne, Inc., hereby disclaims all copyright interest in the program
- `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
- <signature of Ty Coon>, 1 April 1989
- Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs. If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library. If this is what you want to do, use the GNU Library General
-Public License instead of this License.
+for more details.
diff --git a/CREDITS b/CREDITS
index a3ec0c744172..989cda91c427 100644
--- a/CREDITS
+++ b/CREDITS
@@ -1564,6 +1564,11 @@ W: http://www.carumba.com/
D: bug toaster (A1 sauce makes all the difference)
D: Random linux hacker
+N: James Hogan
+E: jhogan@kernel.org
+D: Metag architecture maintainer
+D: TZ1090 SoC maintainer
+
N: Tim Hockin
E: thockin@hockin.org
W: http://www.hockin.org/~thockin
diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX
index 7f3a0728ccf2..708dc4c166e4 100644
--- a/Documentation/00-INDEX
+++ b/Documentation/00-INDEX
@@ -66,8 +66,6 @@ backlight/
- directory with info on controlling backlights in flat panel displays
bcache.txt
- Block-layer cache on fast SSDs to improve slow (raid) I/O performance.
-blackfin/
- - directory with documentation for the Blackfin arch.
block/
- info on the Block I/O (BIO) layer.
blockdev/
@@ -114,8 +112,6 @@ cputopology.txt
- documentation on how CPU topology info is exported via sysfs.
crc32.txt
- brief tutorial on CRC computation
-cris/
- - directory with info about Linux on CRIS architecture.
crypto/
- directory with info on the Crypto API.
dcdbas.txt
@@ -172,8 +168,6 @@ fmc/
- information about the FMC bus abstraction
fpga/
- FPGA Manager Core.
-frv/
- - Fujitsu FR-V Linux documentation.
futex-requeue-pi.txt
- info on requeueing of tasks from a non-PI futex to a PI futex
gcc-plugins.txt
@@ -276,8 +270,6 @@ memory-hotplug.txt
- Hotpluggable memory support, how to use and current status.
men-chameleon-bus.txt
- info on MEN chameleon bus.
-metag/
- - directory with info about Linux on Meta architecture.
mic/
- Intel Many Integrated Core (MIC) architecture device driver.
mips/
@@ -286,8 +278,6 @@ misc-devices/
- directory with info about devices using the misc dev subsystem
mmc/
- directory with info about the MMC subsystem
-mn10300/
- - directory with info about the mn10300 architecture port
mtd/
- directory with info about memory technology devices (flash)
namespaces/
diff --git a/Documentation/ABI/stable/sysfs-bus-vmbus b/Documentation/ABI/stable/sysfs-bus-vmbus
index e46be65d0e1d..0c9d9dcd2151 100644
--- a/Documentation/ABI/stable/sysfs-bus-vmbus
+++ b/Documentation/ABI/stable/sysfs-bus-vmbus
@@ -132,3 +132,10 @@ KernelVersion: 4.16
Contact: Stephen Hemminger <sthemmin@microsoft.com>
Description: Monitor bit associated with channel
Users: Debugging tools and userspace drivers
+
+What: /sys/bus/vmbus/devices/vmbus_*/channels/NN/ring
+Date: January. 2018
+KernelVersion: 4.16
+Contact: Stephen Hemminger <sthemmin@microsoft.com>
+Description: Binary file created by uio_hv_generic for ring buffer
+Users: Userspace drivers
diff --git a/Documentation/ABI/stable/sysfs-class-infiniband b/Documentation/ABI/stable/sysfs-class-infiniband
new file mode 100644
index 000000000000..17211ceb9bf4
--- /dev/null
+++ b/Documentation/ABI/stable/sysfs-class-infiniband
@@ -0,0 +1,818 @@
+sysfs interface common for all infiniband devices
+-------------------------------------------------
+
+What: /sys/class/infiniband/<device>/node_type
+What: /sys/class/infiniband/<device>/node_guid
+What: /sys/class/infiniband/<device>/sys_image_guid
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: linux-rdma@vger.kernel.org
+Description:
+ node_type: (RO) Node type (CA, RNIC, usNIC, usNIC UDP,
+ switch or router)
+
+ node_guid: (RO) Node GUID
+
+ sys_image_guid: (RO) System image GUID
+
+
+What: /sys/class/infiniband/<device>/node_desc
+Date: Feb, 2006
+KernelVersion: v2.6.17
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RW) Update the node description with information such as the
+ node's hostname, so that IB network management software can tie
+ its view to the real world.
+
+
+What: /sys/class/infiniband/<device>/fw_ver
+Date: Jun, 2016
+KernelVersion: v4.10
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) Display firmware version
+
+
+What: /sys/class/infiniband/<device>/ports/<port-num>/lid
+What: /sys/class/infiniband/<device>/ports/<port-num>/rate
+What: /sys/class/infiniband/<device>/ports/<port-num>/lid_mask_count
+What: /sys/class/infiniband/<device>/ports/<port-num>/sm_sl
+What: /sys/class/infiniband/<device>/ports/<port-num>/sm_lid
+What: /sys/class/infiniband/<device>/ports/<port-num>/state
+What: /sys/class/infiniband/<device>/ports/<port-num>/phys_state
+What: /sys/class/infiniband/<device>/ports/<port-num>/cap_mask
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: linux-rdma@vger.kernel.org
+Description:
+
+ lid: (RO) Port LID
+
+ rate: (RO) Port data rate (active width * active
+ speed)
+
+ lid_mask_count: (RO) Port LID mask count
+
+ sm_sl: (RO) Subnet manager SL for port's subnet
+
+ sm_lid: (RO) Subnet manager LID for port's subnet
+
+ state: (RO) Port state (DOWN, INIT, ARMED, ACTIVE or
+ ACTIVE_DEFER)
+
+ phys_state: (RO) Port physical state (Sleep, Polling,
+ LinkUp, etc)
+
+ cap_mask: (RO) Port capability mask. 2 bits here are
+ settable- IsCommunicationManagementSupported
+ (set when CM module is loaded) and IsSM (set via
+ open of issmN file).
+
+
+What: /sys/class/infiniband/<device>/ports/<port-num>/link_layer
+Date: Oct, 2010
+KernelVersion: v2.6.37
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) Link layer type information (Infiniband or Ethernet type)
+
+
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/symbol_error
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_remote_physical_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_switch_relay_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/link_error_recovery
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_constraint_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_contraint_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/local_link_integrity_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/excessive_buffer_overrun_errors
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_data
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_data
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_packets
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_rcv_packets
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/unicast_rcv_packets
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/unicast_xmit_packets
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/multicast_rcv_packets
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/multicast_xmit_packets
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/link_downed
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_discards
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/VL15_dropped
+What: /sys/class/infiniband/<device>/ports/<port-num>/counters/port_xmit_wait
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: linux-rdma@vger.kernel.org
+Description:
+ Errors info:
+ -----------
+
+ symbol_error: (RO) Total number of minor link errors detected on
+ one or more physical lanes.
+
+ port_rcv_errors : (RO) Total number of packets containing an
+ error that were received on the port.
+
+ port_rcv_remote_physical_errors : (RO) Total number of packets
+ marked with the EBP delimiter received on the port.
+
+ port_rcv_switch_relay_errors : (RO) Total number of packets
+ received on the port that were discarded because they could not
+ be forwarded by the switch relay.
+
+ link_error_recovery: (RO) Total number of times the Port
+ Training state machine has successfully completed the link error
+ recovery process.
+
+ port_xmit_constraint_errors: (RO) Total number of packets not
+ transmitted from the switch physical port due to outbound raw
+ filtering or failing outbound partition or IP version check.
+
+ port_rcv_constraint_errors: (RO) Total number of packets
+ received on the switch physical port that are discarded due to
+ inbound raw filtering or failing inbound partition or IP version
+ check.
+
+ local_link_integrity_errors: (RO) The number of times that the
+ count of local physical errors exceeded the threshold specified
+ by LocalPhyErrors
+
+ excessive_buffer_overrun_errors: (RO) This counter, indicates an
+ input buffer overrun. It indicates possible misconfiguration of
+ a port, either by the Subnet Manager (SM) or by user
+ intervention. It can also indicate hardware issues or extremely
+ poor link signal integrity
+
+ Data info:
+ ---------
+
+ port_xmit_data: (RO) Total number of data octets, divided by 4
+ (lanes), transmitted on all VLs. This is 64 bit counter
+
+ port_rcv_data: (RO) Total number of data octets, divided by 4
+ (lanes), received on all VLs. This is 64 bit counter.
+
+ port_xmit_packets: (RO) Total number of packets transmitted on
+ all VLs from this port. This may include packets with errors.
+ This is 64 bit counter.
+
+ port_rcv_packets: (RO) Total number of packets (this may include
+ packets containing Errors. This is 64 bit counter.
+
+ link_downed: (RO) Total number of times the Port Training state
+ machine has failed the link error recovery process and downed
+ the link.
+
+ unicast_rcv_packets: (RO) Total number of unicast packets,
+ including unicast packets containing errors.
+
+ unicast_xmit_packets: (RO) Total number of unicast packets
+ transmitted on all VLs from the port. This may include unicast
+ packets with errors.
+
+ multicast_rcv_packets: (RO) Total number of multicast packets,
+ including multicast packets containing errors.
+
+ multicast_xmit_packets: (RO) Total number of multicast packets
+ transmitted on all VLs from the port. This may include multicast
+ packets with errors.
+
+ Misc info:
+ ---------
+
+ port_xmit_discards: (RO) Total number of outbound packets
+ discarded by the port because the port is down or congested.
+
+ VL15_dropped: (RO) Number of incoming VL15 packets dropped due
+ to resource limitations (e.g., lack of buffers) of the port.
+
+ port_xmit_wait: (RO) The number of ticks during which the port
+ had data to transmit but no data was sent during the entire tick
+ (either because of insufficient credits or because of lack of
+ arbitration).
+
+ Each of these files contains the corresponding value from the
+ port's Performance Management PortCounters attribute, as
+ described in the InfiniBand Architecture Specification.
+
+
+What: /sys/class/infiniband/<device-name>/hw_counters/lifespan
+What: /sys/class/infiniband/<device-name>/ports/<port-num>/hw_counters/lifespan
+Date: May, 2016
+KernelVersion: 4.6
+Contact: linux-rdma@vger.kernel.org
+Description:
+ The optional "hw_counters" subdirectory can be under either the
+ parent device or the port subdirectories or both. If present,
+ there are a list of counters provided by the hardware. They may
+ match some of the counters in the counters directory, but they
+ often include many other counters. In addition to the various
+ counters, there will be a file named "lifespan" that configures
+ how frequently the core should update the counters when they are
+ being accessed (counters are not updated if they are not being
+ accessed). The lifespan is in milliseconds and defaults to 10
+ unless set to something else by the driver. Users may echo a
+ value between 0-10000 to the lifespan file to set the length
+ of time between updates in milliseconds.
+
+
+What: /sys/class/infiniband/<hca>/ports/<port-number>/gid_attrs/ndevs/<gid-index>
+Date: November 29, 2015
+KernelVersion: 4.4.0
+Contact: linux-rdma@vger.kernel.org
+Description: The net-device's name associated with the GID resides
+ at index <gid-index>.
+
+What: /sys/class/infiniband/<hca>/ports/<port-number>/gid_attrs/types/<gid-index>
+Date: November 29, 2015
+KernelVersion: 4.4.0
+Contact: linux-rdma@vger.kernel.org
+Description: The RoCE type of the associated GID resides at index <gid-index>.
+ This could either be "IB/RoCE v1" for IB and RoCE v1 based GIDs
+ or "RoCE v2" for RoCE v2 based GIDs.
+
+
+What: /sys/class/infiniband_mad/umadN/ibdev
+What: /sys/class/infiniband_mad/umadN/port
+What: /sys/class/infiniband_mad/issmN/ibdev
+What: /sys/class/infiniband_mad/issmN/port
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: linux-rdma@vger.kernel.org
+Description:
+ Each port of each InfiniBand device has a "umad" device and an
+ "issm" device attached. For example, a two-port HCA will have
+ two umad devices and two issm devices, while a switch will have
+ one device of each type (for switch port 0).
+
+ ibdev: (RO) Show Infiniband (IB) device name
+
+ port: (RO) Display port number
+
+
+What: /sys/class/infiniband_mad/abi_version
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) Value is incremented if any changes are made that break
+ userspace ABI compatibility of umad & issm devices.
+
+
+What: /sys/class/infiniband_cm/ucmN/ibdev
+Date: Oct, 2005
+KernelVersion: v2.6.14
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) Display Infiniband (IB) device name
+
+
+What: /sys/class/infiniband_cm/abi_version
+Date: Oct, 2005
+KernelVersion: v2.6.14
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) Value is incremented if any changes are made that break
+ userspace ABI compatibility of ucm devices.
+
+
+What: /sys/class/infiniband_verbs/uverbsN/ibdev
+What: /sys/class/infiniband_verbs/uverbsN/abi_version
+Date: Sept, 2005
+KernelVersion: v2.6.14
+Contact: linux-rdma@vger.kernel.org
+Description:
+ ibdev: (RO) Display Infiniband (IB) device name
+
+ abi_version: (RO) Show ABI version of IB device specific
+ interfaces.
+
+
+What: /sys/class/infiniband_verbs/abi_version
+Date: Sep, 2005
+KernelVersion: v2.6.14
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) Value is incremented if any changes are made that break
+ userspace ABI compatibility of uverbs devices.
+
+
+sysfs interface for Mellanox IB HCA low-level driver (mthca)
+------------------------------------------------------------
+
+What: /sys/class/infiniband/mthcaX/hw_rev
+What: /sys/class/infiniband/mthcaX/hca_type
+What: /sys/class/infiniband/mthcaX/board_id
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Host Channel Adapter type: MT23108, MT25208
+ (MT23108 compat mode), MT25208 or MT25204
+
+ board_id: (RO) Manufacturing board ID
+
+
+sysfs interface for Chelsio T3 RDMA Driver (cxgb3)
+--------------------------------------------------
+
+What: /sys/class/infiniband/cxgb3_X/hw_rev
+What: /sys/class/infiniband/cxgb3_X/hca_type
+What: /sys/class/infiniband/cxgb3_X/board_id
+Date: Feb, 2007
+KernelVersion: v2.6.21
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) HCA type. Here it is a driver short name.
+ It should normally match the name in its bus
+ driver structure (e.g. pci_driver::name).
+
+ board_id: (RO) Manufacturing board id
+
+
+sysfs interface for Mellanox ConnectX HCA IB driver (mlx4)
+----------------------------------------------------------
+
+What: /sys/class/infiniband/mlx4_X/hw_rev
+What: /sys/class/infiniband/mlx4_X/hca_type
+What: /sys/class/infiniband/mlx4_X/board_id
+Date: Sep, 2007
+KernelVersion: v2.6.24
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Host channel adapter type
+
+ board_id: (RO) Manufacturing board ID
+
+
+What: /sys/class/infiniband/mlx4_X/iov/ports/<port-num>/gids/<n>
+What: /sys/class/infiniband/mlx4_X/iov/ports/<port-num>/admin_guids/<n>
+What: /sys/class/infiniband/mlx4_X/iov/ports/<port-num>/pkeys/<n>
+What: /sys/class/infiniband/mlx4_X/iov/ports/<port-num>/mcgs/
+What: /sys/class/infiniband/mlx4_X/iov/ports/<pci-slot-num>/ports/<m>/gid_idx/0
+What: /sys/class/infiniband/mlx4_X/iov/ports/<pci-slot-num>/ports/<m>/pkey_idx/<n>
+Date: Aug, 2012
+KernelVersion: v3.6.15
+Contact: linux-rdma@vger.kernel.org
+Description:
+ The sysfs iov directory is used to manage and examine the port
+ P_Key and guid paravirtualization. This directory is added only
+ for the master -- slaves do not have it.
+
+ Under iov/ports, the administrator may examine the gid and P_Key
+ tables as they are present in the device (and as are seen in the
+ "network view" presented to the SM).
+
+ The "pkeys" and "gids" subdirectories contain one file for each
+ entry in the port's P_Key or GID table respectively. For
+ example, ports/1/pkeys/10 contains the value at index 10 in port
+ 1's P_Key table.
+
+ gids/<n>: (RO) The physical port gids n = 0..127
+
+ admin_guids/<n>: (RW) Allows examining or changing the
+ administrative state of a given GUID
+ n = 0..127
+
+ pkeys/<n>: (RO) Displays the contents of the physical
+ key table n = 0..126
+
+ mcgs/: (RO) Muticast group table
+
+ <m>/gid_idx/0: (RO) Display the GID mapping m = 1..2
+
+ <m>/pkey_idx/<n>: (RW) Writable except for RoCE pkeys.
+ m = 1..2, n = 0..126
+
+ Under the iov/<pci slot number>
+ directories, the admin may map the index
+ numbers in the physical tables (as under
+ iov/ports) to the paravirtualized index
+ numbers that guests see.
+
+ For example, if the administrator, for
+ port 1 on guest 2 maps physical pkey
+ index 10 to virtual index 1, then that
+ guest, whenever it uses its pkey index
+ 1, will actually be using the real pkey
+ index 10.
+
+
+What: /sys/class/infiniband/mlx4_X/iov/<pci-slot-num>/ports/<m>/smi_enabled
+What: /sys/class/infiniband/mlx4_X/iov/<pci-slot-num>/ports/<m>/enable_smi_admin
+Date: May, 2014
+KernelVersion: v3.15.7
+Contact: linux-rdma@vger.kernel.org
+Description:
+ Enabling QP0 on VFs for selected VF/port. By default, no VFs are
+ enabled for QP0 operation.
+
+ smi_enabled: (RO) Indicates whether smi is currently enabled
+ for the indicated VF/port
+
+ enable_smi_admin:(RW) Used by the admin to request that smi
+ capability be enabled or disabled for the
+ indicated VF/port. 0 = disable, 1 = enable.
+
+ The requested enablement will occur at the next reset of the VF
+ (e.g. driver restart on the VM which owns the VF).
+
+
+sysfs interface for NetEffect RNIC Low-Level iWARP driver (nes)
+---------------------------------------------------------------
+
+What: /sys/class/infiniband/nesX/hw_rev
+What: /sys/class/infiniband/nesX/hca_type
+What: /sys/class/infiniband/nesX/board_id
+Date: Feb, 2008
+KernelVersion: v2.6.25
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Host Channel Adapter type (NEX020)
+
+ board_id: (RO) Manufacturing board id
+
+
+sysfs interface for Chelsio T4/T5 RDMA driver (cxgb4)
+-----------------------------------------------------
+
+What: /sys/class/infiniband/cxgb4_X/hw_rev
+What: /sys/class/infiniband/cxgb4_X/hca_type
+What: /sys/class/infiniband/cxgb4_X/board_id
+Date: Apr, 2010
+KernelVersion: v2.6.35
+Contact: linux-rdma@vger.kernel.org
+Description:
+
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Driver short name. Should normally match
+ the name in its bus driver structure (e.g.
+ pci_driver::name)
+
+ board_id: (RO) Manufacturing board id. (Vendor + device
+ information)
+
+
+sysfs interface for Intel IB driver qib
+---------------------------------------
+
+What: /sys/class/infiniband/qibX/version
+What: /sys/class/infiniband/qibX/hw_rev
+What: /sys/class/infiniband/qibX/hca_type
+What: /sys/class/infiniband/qibX/board_id
+What: /sys/class/infiniband/qibX/boardversion
+What: /sys/class/infiniband/qibX/nctxts
+What: /sys/class/infiniband/qibX/localbus_info
+What: /sys/class/infiniband/qibX/tempsense
+What: /sys/class/infiniband/qibX/serial
+What: /sys/class/infiniband/qibX/nfreectxts
+What: /sys/class/infiniband/qibX/chip_reset
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: linux-rdma@vger.kernel.org
+Description:
+ version: (RO) Display version information of installed software
+ and drivers.
+
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Host channel adapter type
+
+ board_id: (RO) Manufacturing board id
+
+ boardversion: (RO) Current version of the chip architecture
+
+ nctxts: (RO) Return the number of user ports (contexts)
+ available
+
+ localbus_info: (RO) Human readable localbus info
+
+ tempsense: (RO) Display temp sense registers in decimal
+
+ serial: (RO) Serial number of the HCA
+
+ nfreectxts: (RO) The number of free user ports (contexts)
+ available.
+
+ chip_reset: (WO) Reset the chip if possible by writing
+ "reset" to this file. Only allowed if no user
+ contexts are open that use chip resources.
+
+
+What: /sys/class/infiniband/qibX/ports/N/sl2vl/[0-15]
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: linux-rdma@vger.kernel.org
+Description:
+ (RO) The directory contains 16 files numbered 0-15 that specify
+ the Service Level (SL). Listing the SL files returns the Virtual
+ Lane (VL) as programmed by the SL.
+
+What: /sys/class/infiniband/qibX/ports/N/CCMgtA/cc_settings_bin
+What: /sys/class/infiniband/qibX/ports/N/CCMgtA/cc_table_bin
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: linux-rdma@vger.kernel.org
+Description:
+ Per-port congestion control. Both are binary attributes.
+
+ cc_table_bin: (RO) Congestion control table size followed by
+ table entries.
+
+ cc_settings_bin:(RO) Congestion settings: port control, control
+ map and an array of 16 entries for the
+ congestion entries - increase, timer, event log
+ trigger threshold and the minimum injection rate
+ delay.
+
+What: /sys/class/infiniband/qibX/ports/N/linkstate/loopback
+What: /sys/class/infiniband/qibX/ports/N/linkstate/led_override
+What: /sys/class/infiniband/qibX/ports/N/linkstate/hrtbt_enable
+What: /sys/class/infiniband/qibX/ports/N/linkstate/status
+What: /sys/class/infiniband/qibX/ports/N/linkstate/status_str
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: linux-rdma@vger.kernel.org
+Description:
+ [to be documented]
+
+ loopback: (WO)
+ led_override: (WO)
+ hrtbt_enable: (RW)
+ status: (RO)
+
+ status_str: (RO) Displays information about the link state,
+ possible cable/switch problems, and hardware
+ errors. Possible states are- "Initted",
+ "Present", "IB_link_up", "IB_configured" or
+ "Fatal_Hardware_Error".
+
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/rc_resends
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/seq_naks
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/rdma_seq
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/rnr_naks
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/other_naks
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/rc_timeouts
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/look_pkts
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/pkt_drops
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/dma_wait
+What: /sys/class/infiniband/qibX/ports/N/diag_counters/unaligned
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: linux-rdma@vger.kernel.org
+Description:
+ [to be documented]
+
+
+sysfs interface for Mellanox Connect-IB HCA driver mlx5
+-------------------------------------------------------
+
+What: /sys/class/infiniband/mlx5_X/hw_rev
+What: /sys/class/infiniband/mlx5_X/hca_type
+What: /sys/class/infiniband/mlx5_X/reg_pages
+What: /sys/class/infiniband/mlx5_X/fw_pages
+Date: Jul, 2013
+KernelVersion: v3.11
+Contact: linux-rdma@vger.kernel.org
+Description:
+ [to be documented]
+
+
+sysfs interface for Cisco VIC (usNIC) Verbs Driver
+--------------------------------------------------
+
+What: /sys/class/infiniband/usnic_X/board_id
+What: /sys/class/infiniband/usnic_X/config
+What: /sys/class/infiniband/usnic_X/qp_per_vf
+What: /sys/class/infiniband/usnic_X/max_vf
+What: /sys/class/infiniband/usnic_X/cq_per_vf
+What: /sys/class/infiniband/usnic_X/iface
+Date: Sep, 2013
+KernelVersion: v3.14
+Contact: Christian Benvenuti <benve@cisco.com>,
+ Dave Goodell <dgoodell@cisco.com>,
+ linux-rdma@vger.kernel.org
+Description:
+
+ board_id: (RO) Manufacturing board id
+
+ config: (RO) Report the configuration for this PF
+
+ qp_per_vf: (RO) Queue pairs per virtual function.
+
+ max_vf: (RO) Max virtual functions
+
+ cq_per_vf: (RO) Completion queue per virtual function
+
+ iface: (RO) Shows which network interface this usNIC
+ entry is associated to (visible with ifconfig).
+
+What: /sys/class/infiniband/usnic_X/qpn/summary
+What: /sys/class/infiniband/usnic_X/qpn/context
+Date: Sep, 2013
+KernelVersion: v3.14
+Contact: Christian Benvenuti <benve@cisco.com>,
+ Dave Goodell <dgoodell@cisco.com>,
+ linux-rdma@vger.kernel.org
+Description:
+ [to be documented]
+
+
+sysfs interface for Emulex RoCE HCA Driver
+------------------------------------------
+
+What: /sys/class/infiniband/ocrdmaX/hw_rev
+Date: Feb, 2014
+KernelVersion: v3.14
+Description:
+ hw_rev: (RO) Hardware revision number
+
+What: /sys/class/infiniband/ocrdmaX/hca_type
+Date: Jun, 2014
+KernelVersion: v3.16
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hca_type: (RO) Display FW version
+
+
+sysfs interface for Intel Omni-Path driver (HFI1)
+-------------------------------------------------
+
+What: /sys/class/infiniband/hfi1_X/hw_rev
+What: /sys/class/infiniband/hfi1_X/board_id
+What: /sys/class/infiniband/hfi1_X/nctxts
+What: /sys/class/infiniband/hfi1_X/serial
+What: /sys/class/infiniband/hfi1_X/chip_reset
+What: /sys/class/infiniband/hfi1_X/boardversion
+What: /sys/class/infiniband/hfi1_X/nfreectxts
+What: /sys/class/infiniband/hfi1_X/tempsense
+Date: May, 2016
+KernelVersion: v4.6
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ board_id: (RO) Manufacturing board id
+
+ nctxts: (RO) Total contexts available.
+
+ serial: (RO) Board serial number
+
+ chip_reset: (WO) Write "reset" to this file to reset the
+ chip if possible. Only allowed if no user
+ contexts are open that use chip resources.
+
+ boardversion: (RO) Human readable board info
+
+ nfreectxts: (RO) The number of free user ports (contexts)
+ available.
+
+ tempsense: (RO) Thermal sense information
+
+
+What: /sys/class/infiniband/hfi1_X/ports/N/CCMgtA/cc_settings_bin
+What: /sys/class/infiniband/hfi1_X/ports/N/CCMgtA/cc_table_bin
+What: /sys/class/infiniband/hfi1_X/ports/N/CCMgtA/cc_prescan
+Date: May, 2016
+KernelVersion: v4.6
+Contact: linux-rdma@vger.kernel.org
+Description:
+ Per-port congestion control.
+
+ cc_table_bin: (RO) CCA tables used by PSM2 Congestion control
+ table size followed by table entries. Binary
+ attribute.
+
+ cc_settings_bin:(RO) Congestion settings: port control, control
+ map and an array of 16 entries for the
+ congestion entries - increase, timer, event log
+ trigger threshold and the minimum injection rate
+ delay. Binary attribute.
+
+ cc_prescan: (RW) enable prescanning for faster BECN
+ response. Write "on" to enable and "off" to
+ disable.
+
+What: /sys/class/infiniband/hfi1_X/ports/N/sc2vl/[0-31]
+What: /sys/class/infiniband/hfi1_X/ports/N/sl2sc/[0-31]
+What: /sys/class/infiniband/hfi1_X/ports/N/vl2mtu/[0-15]
+Date: May, 2016
+KernelVersion: v4.6
+Contact: linux-rdma@vger.kernel.org
+Description:
+ sc2vl/: (RO) 32 files (0 - 31) used to translate sl->vl
+
+ sl2sc/: (RO) 32 files (0 - 31) used to translate sl->sc
+
+ vl2mtu/: (RO) 16 files (0 - 15) used to determine MTU for vl
+
+
+What: /sys/class/infiniband/hfi1_X/sdma_N/cpu_list
+What: /sys/class/infiniband/hfi1_X/sdma_N/vl
+Date: Sept, 2016
+KernelVersion: v4.8
+Contact: linux-rdma@vger.kernel.org
+Description:
+ sdma<N>/ contains one directory per sdma engine (0 - 15)
+
+ cpu_list: (RW) List of cpus for user-process to sdma
+ engine assignment.
+
+ vl: (RO) Displays the virtual lane (vl) the sdma
+ engine maps to.
+
+ This interface gives the user control on the affinity settings
+ for the device. As an example, to set an sdma engine irq
+ affinity and thread affinity of a user processes to use the
+ sdma engine, which is "near" in terms of NUMA configuration, or
+ physical cpu location, the user will do:
+
+ echo "3" > /proc/irq/<N>/smp_affinity_list
+ echo "4-7" > /sys/devices/.../sdma3/cpu_list
+ cat /sys/devices/.../sdma3/vl
+ 0
+ echo "8" > /proc/irq/<M>/smp_affinity_list
+ echo "9-12" > /sys/devices/.../sdma4/cpu_list
+ cat /sys/devices/.../sdma4/vl
+ 1
+
+ to make sure that when a process runs on cpus 4,5,6, or 7, and
+ uses vl=0, then sdma engine 3 is selected by the driver, and
+ also the interrupt of the sdma engine 3 is steered to cpu 3.
+ Similarly, when a process runs on cpus 9,10,11, or 12 and sets
+ vl=1, then engine 4 will be selected and the irq of the sdma
+ engine 4 is steered to cpu 8. This assumes that in the above N
+ is the irq number of "sdma3", and M is irq number of "sdma4" in
+ the /proc/interrupts file.
+
+
+sysfs interface for Intel(R) X722 iWARP i40iw driver
+----------------------------------------------------
+
+What: /sys/class/infiniband/i40iwX/hw_rev
+What: /sys/class/infiniband/i40iwX/hca_type
+What: /sys/class/infiniband/i40iwX/board_id
+Date: Jan, 2016
+KernelVersion: v4.10
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Show HCA type (I40IW)
+
+ board_id: (RO) I40IW board ID
+
+
+sysfs interface for QLogic qedr NIC Driver
+------------------------------------------
+
+What: /sys/class/infiniband/qedrX/hw_rev
+What: /sys/class/infiniband/qedrX/hca_type
+Date: Oct, 2016
+KernelVersion: v4.10
+Contact: linux-rdma@vger.kernel.org
+Description:
+
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Display HCA type
+
+
+sysfs interface for VMware Paravirtual RDMA driver
+--------------------------------------------------
+
+What: /sys/class/infiniband/vmw_pvrdmaX/hw_rev
+What: /sys/class/infiniband/vmw_pvrdmaX/hca_type
+What: /sys/class/infiniband/vmw_pvrdmaX/board_id
+Date: Oct, 2016
+KernelVersion: v4.10
+Contact: linux-rdma@vger.kernel.org
+Description:
+
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Host channel adapter type
+
+ board_id: (RO) Display PVRDMA manufacturing board ID
+
+
+sysfs interface for Broadcom NetXtreme-E RoCE driver
+----------------------------------------------------
+
+What: /sys/class/infiniband/bnxt_reX/hw_rev
+What: /sys/class/infiniband/bnxt_reX/hca_type
+Date: Feb, 2017
+KernelVersion: v4.11
+Contact: linux-rdma@vger.kernel.org
+Description:
+ hw_rev: (RO) Hardware revision number
+
+ hca_type: (RO) Host channel adapter type
diff --git a/Documentation/ABI/testing/debugfs-cec-error-inj b/Documentation/ABI/testing/debugfs-cec-error-inj
new file mode 100644
index 000000000000..122b65c5fe62
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-cec-error-inj
@@ -0,0 +1,40 @@
+What: /sys/kernel/debug/cec/*/error-inj
+Date: March 2018
+Contact: Hans Verkuil <hans.verkuil@cisco.com>
+Description:
+
+The CEC Framework allows for CEC error injection commands through
+debugfs. Drivers that support this will create an error-inj file
+through which the error injection commands can be given.
+
+The basic syntax is as follows:
+
+Leading spaces/tabs are ignored. If the next character is a '#' or the
+end of the line was reached, then the whole line is ignored. Otherwise
+a command is expected.
+
+It is up to the driver to decide what commands to implement. The only
+exception is that the command 'clear' without any arguments must be
+implemented and that it will remove all current error injection
+commands.
+
+This ensures that you can always do 'echo clear >error-inj' to clear any
+error injections without having to know the details of the driver-specific
+commands.
+
+Note that the output of 'error-inj' shall be valid as input to 'error-inj'.
+So this must work:
+
+ $ cat error-inj >einj.txt
+ $ cat einj.txt >error-inj
+
+Other than these basic rules described above this ABI is not considered
+stable and may change in the future.
+
+Drivers that implement this functionality must document the commands as
+part of the CEC documentation and must keep that documentation up to date
+when changes are made.
+
+The following CEC error injection implementations exist:
+
+- Documentation/media/uapi/cec/cec-pin-error-inj.rst
diff --git a/Documentation/ABI/testing/ima_policy b/Documentation/ABI/testing/ima_policy
index 2028f2d093b2..b8465e00ba5f 100644
--- a/Documentation/ABI/testing/ima_policy
+++ b/Documentation/ABI/testing/ima_policy
@@ -26,7 +26,7 @@ Description:
[obj_user=] [obj_role=] [obj_type=]]
option: [[appraise_type=]] [permit_directio]
- base: func:= [BPRM_CHECK][MMAP_CHECK][FILE_CHECK][MODULE_CHECK]
+ base: func:= [BPRM_CHECK][MMAP_CHECK][CREDS_CHECK][FILE_CHECK][MODULE_CHECK]
[FIRMWARE_CHECK]
[KEXEC_KERNEL_CHECK] [KEXEC_INITRAMFS_CHECK]
mask:= [[^]MAY_READ] [[^]MAY_WRITE] [[^]MAY_APPEND]
diff --git a/Documentation/ABI/testing/sysfs-block-aoe b/Documentation/ABI/testing/sysfs-block-aoe
new file mode 100644
index 000000000000..b5837765bcdd
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-block-aoe
@@ -0,0 +1,45 @@
+What: /sys/block/etherd*/mac
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: Ed L. Cashin <ed.cashin@acm.org>
+Description:
+ (RO) The ethernet address of the remote Ata over Ethernet (AoE)
+ device.
+
+What: /sys/block/etherd*/netif
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: Ed L. Cashin <ed.cashin@acm.org>
+Description:
+ (RO) The names of the network interfaces on the localhost (comma
+ separated) through which we are communicating with the remote
+ AoE device.
+
+What: /sys/block/etherd*/state
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: Ed L. Cashin <ed.cashin@acm.org>
+Description:
+ (RO) Device status. The state attribute is "up" when the device
+ is ready for I/O and "down" if detected but unusable. The
+ "down,closewait" state shows that the device is still open and
+ cannot come up again until it has been closed. The "up,kickme"
+ state means that the driver wants to send more commands to the
+ target but found out there were already the max number of
+ commands waiting for a response. It will retry again after being
+ kicked by the periodic timer handler routine.
+
+What: /sys/block/etherd*/firmware-version
+Date: Apr, 2005
+KernelVersion: v2.6.12
+Contact: Ed L. Cashin <ed.cashin@acm.org>
+Description:
+ (RO) Version of the firmware in the target.
+
+What: /sys/block/etherd*/payload
+Date: Dec, 2012
+KernelVersion: v3.10
+Contact: Ed L. Cashin <ed.cashin@acm.org>
+Description:
+ (RO) The amount of user data transferred (in bytes) inside each AoE
+ command on the network, network headers excluded.
diff --git a/Documentation/ABI/testing/sysfs-block-loop b/Documentation/ABI/testing/sysfs-block-loop
new file mode 100644
index 000000000000..627f4eb87286
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-block-loop
@@ -0,0 +1,50 @@
+What: /sys/block/loopX/loop/autoclear
+Date: Aug, 2010
+KernelVersion: v2.6.37
+Contact: linux-block@vger.kernel.org
+Description:
+ (RO) Shows if the device is in autoclear mode or not ( "1" or
+ "0"). Autoclear (if set) indicates that the loopback device will
+ self-distruct after last close.
+
+What: /sys/block/loopX/loop/backing_file
+Date: Aug, 2010
+KernelVersion: v2.6.37
+Contact: linux-block@vger.kernel.org
+Description:
+ (RO) The path of the backing file that the loop device maps its
+ data blocks to.
+
+What: /sys/block/loopX/loop/offset
+Date: Aug, 2010
+KernelVersion: v2.6.37
+Contact: linux-block@vger.kernel.org
+Description:
+ (RO) Start offset (in bytes).
+
+What: /sys/block/loopX/loop/sizelimit
+Date: Aug, 2010
+KernelVersion: v2.6.37
+Contact: linux-block@vger.kernel.org
+Description:
+ (RO) The size (in bytes) that the block device maps, starting
+ from the offset.
+
+What: /sys/block/loopX/loop/partscan
+Date: Aug, 2011
+KernelVersion: v3.10
+Contact: linux-block@vger.kernel.org
+Description:
+ (RO) Shows if automatic partition scanning is enabled for the
+ device or not ("1" or "0"). This can be requested individually
+ per loop device during its setup by setting LO_FLAGS_PARTSCAN in
+ in the ioctl request. By default, no partition tables are
+ scanned.
+
+What: /sys/block/loopX/loop/dio
+Date: Aug, 2015
+KernelVersion: v4.10
+Contact: linux-block@vger.kernel.org
+Description:
+ (RO) Shows if direct IO is being used to access backing file or
+ not ("1 or "0").
diff --git a/Documentation/ABI/testing/sysfs-bus-acpi b/Documentation/ABI/testing/sysfs-bus-acpi
index 7fa9cbc75344..e7898cfe5fb1 100644
--- a/Documentation/ABI/testing/sysfs-bus-acpi
+++ b/Documentation/ABI/testing/sysfs-bus-acpi
@@ -56,3 +56,40 @@ Description:
Writing 1 to this attribute will trigger hot removal of
this device object. This file exists for every device
object that has _EJ0 method.
+
+What: /sys/bus/acpi/devices/.../status
+Date: Jan, 2014
+Contact: Rafael J. Wysocki <rjw@rjwysocki.net>
+Description:
+ (RO) Returns the ACPI device status: enabled, disabled or
+ functioning or present, if the method _STA is present.
+
+ The return value is a decimal integer representing the device's
+ status bitmap:
+
+ Bit [0] – Set if the device is present.
+ Bit [1] – Set if the device is enabled and decoding its
+ resources.
+ Bit [2] – Set if the device should be shown in the UI.
+ Bit [3] – Set if the device is functioning properly (cleared if
+ device failed its diagnostics).
+ Bit [4] – Set if the battery is present.
+ Bits [31:5] – Reserved (must be cleared)
+
+ If bit [0] is clear, then bit 1 must also be clear (a device
+ that is not present cannot be enabled).
+
+ Bit 0 can be clear (not present) with bit [3] set (device is
+ functional). This case is used to indicate a valid device for
+ which no device driver should be loaded.
+
+ More special cases are covered in the ACPI specification.
+
+What: /sys/bus/acpi/devices/.../hrv
+Date: Apr, 2016
+Contact: Rafael J. Wysocki <rjw@rjwysocki.net>
+Description:
+ (RO) Allows users to read the hardware version of non-PCI
+ hardware, if the _HRV control method is present. It is mostly
+ useful for non-PCI devices because lspci can list the hardware
+ version for PCI devices.
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-chemical-vz89x b/Documentation/ABI/testing/sysfs-bus-iio-chemical-vz89x
index c0c1ea924535..d512f865600e 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio-chemical-vz89x
+++ b/Documentation/ABI/testing/sysfs-bus-iio-chemical-vz89x
@@ -1,7 +1,7 @@
What: /sys/bus/iio/devices/iio:deviceX/in_concentration_VOC_short_raw
Date: September 2015
KernelVersion: 4.3
-Contact: Matt Ranostay <mranostay@gmail.com>
+Contact: Matt Ranostay <matt.ranostay@konsulko.com>
Description:
Get the raw calibration VOC value from the sensor.
This value has little application outside of calibration.
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-proximity-as3935 b/Documentation/ABI/testing/sysfs-bus-iio-proximity-as3935
index 147d4e8a1403..9a17ab5036a4 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio-proximity-as3935
+++ b/Documentation/ABI/testing/sysfs-bus-iio-proximity-as3935
@@ -1,7 +1,7 @@
What /sys/bus/iio/devices/iio:deviceX/in_proximity_input
Date: March 2014
KernelVersion: 3.15
-Contact: Matt Ranostay <mranostay@gmail.com>
+Contact: Matt Ranostay <matt.ranostay@konsulko.com>
Description:
Get the current distance in meters of storm (1km steps)
1000-40000 = distance in meters
@@ -9,7 +9,7 @@ Description:
What /sys/bus/iio/devices/iio:deviceX/sensor_sensitivity
Date: March 2014
KernelVersion: 3.15
-Contact: Matt Ranostay <mranostay@gmail.com>
+Contact: Matt Ranostay <matt.ranostay@konsulko.com>
Description:
Show or set the gain boost of the amp, from 0-31 range.
18 = indoors (default)
diff --git a/Documentation/ABI/testing/sysfs-bus-nfit b/Documentation/ABI/testing/sysfs-bus-nfit
new file mode 100644
index 000000000000..619eb8ca0f99
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-nfit
@@ -0,0 +1,233 @@
+For all of the nmem device attributes under nfit/*, see the 'NVDIMM Firmware
+Interface Table (NFIT)' section in the ACPI specification
+(http://www.uefi.org/specifications) for more details.
+
+What: /sys/bus/nd/devices/nmemX/nfit/serial
+Date: Jun, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Serial number of the NVDIMM (non-volatile dual in-line
+ memory module), assigned by the module vendor.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/handle
+Date: Apr, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) The address (given by the _ADR object) of the device on its
+ parent bus of the NVDIMM device containing the NVDIMM region.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/device
+Date: Apr, 2015
+KernelVersion: v4.1
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Device id for the NVDIMM, assigned by the module vendor.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/rev_id
+Date: Jun, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Revision of the NVDIMM, assigned by the module vendor.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/phys_id
+Date: Apr, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Handle (i.e., instance number) for the SMBIOS (system
+ management BIOS) Memory Device structure describing the NVDIMM
+ containing the NVDIMM region.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/flags
+Date: Jun, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) The flags in the NFIT memory device sub-structure indicate
+ the state of the data on the nvdimm relative to its energy
+ source or last "flush to persistence".
+
+ The attribute is a translation of the 'NVDIMM State Flags' field
+ in section 5.2.25.3 'NVDIMM Region Mapping' Structure of the
+ ACPI specification 6.2.
+
+ The health states are "save_fail", "restore_fail", "flush_fail",
+ "not_armed", "smart_event", "map_fail" and "smart_notify".
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/format
+What: /sys/bus/nd/devices/nmemX/nfit/format1
+What: /sys/bus/nd/devices/nmemX/nfit/formats
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) The interface codes indicate support for persistent memory
+ mapped directly into system physical address space and / or a
+ block aperture access mechanism to the NVDIMM media.
+ The 'formats' attribute displays the number of supported
+ interfaces.
+
+ This layout is compatible with existing libndctl binaries that
+ only expect one code per-dimm as they will ignore
+ nmemX/nfit/formats and nmemX/nfit/formatN.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/vendor
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Vendor id of the NVDIMM.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/dsm_mask
+Date: May, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) The bitmask indicates the supported device specific control
+ functions relative to the NVDIMM command family supported by the
+ device
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/family
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Displays the NVDIMM family command sets. Values
+ 0, 1, 2 and 3 correspond to NVDIMM_FAMILY_INTEL,
+ NVDIMM_FAMILY_HPE1, NVDIMM_FAMILY_HPE2 and NVDIMM_FAMILY_MSFT
+ respectively.
+
+ See the specifications for these command families here:
+ http://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf
+ https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/
+ https://msdn.microsoft.com/library/windows/hardware/mt604741"
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/id
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) ACPI specification 6.2 section 5.2.25.9, defines an
+ identifier for an NVDIMM, which refelects the id attribute.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/subsystem_vendor
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Sub-system vendor id of the NVDIMM non-volatile memory
+ subsystem controller.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/subsystem_rev_id
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Sub-system revision id of the NVDIMM non-volatile memory subsystem
+ controller, assigned by the non-volatile memory subsystem
+ controller vendor.
+
+
+What: /sys/bus/nd/devices/nmemX/nfit/subsystem_device
+Date: Apr, 2016
+KernelVersion: v4.7
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Sub-system device id for the NVDIMM non-volatile memory
+ subsystem controller, assigned by the non-volatile memory
+ subsystem controller vendor.
+
+
+What: /sys/bus/nd/devices/ndbusX/nfit/revision
+Date: Jun, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) ACPI NFIT table revision number.
+
+
+What: /sys/bus/nd/devices/ndbusX/nfit/scrub
+Date: Sep, 2016
+KernelVersion: v4.9
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RW) This shows the number of full Address Range Scrubs (ARS)
+ that have been completed since driver load time. Userspace can
+ wait on this using select/poll etc. A '+' at the end indicates
+ an ARS is in progress
+
+ Writing a value of 1 triggers an ARS scan.
+
+
+What: /sys/bus/nd/devices/ndbusX/nfit/hw_error_scrub
+Date: Sep, 2016
+KernelVersion: v4.9
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RW) Provides a way to toggle the behavior between just adding
+ the address (cache line) where the MCE happened to the poison
+ list and doing a full scrub. The former (selective insertion of
+ the address) is done unconditionally.
+
+ This attribute can have the following values written to it:
+
+ '0': Switch to the default mode where an exception will only
+ insert the address of the memory error into the poison and
+ badblocks lists.
+ '1': Enable a full scrub to happen if an exception for a memory
+ error is received.
+
+
+What: /sys/bus/nd/devices/ndbusX/nfit/dsm_mask
+Date: Jun, 2017
+KernelVersion: v4.13
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) The bitmask indicates the supported bus specific control
+ functions. See the section named 'NVDIMM Root Device _DSMs' in
+ the ACPI specification.
+
+
+What: /sys/bus/nd/devices/regionX/nfit/range_index
+Date: Jun, 2015
+KernelVersion: v4.2
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) A unique number provided by the BIOS to identify an address
+ range. Used by NVDIMM Region Mapping Structure to uniquely refer
+ to this structure. Value of 0 is reserved and not used as an
+ index.
+
+
+What: /sys/bus/nd/devices/regionX/nfit/ecc_unit_size
+Date: Aug, 2017
+KernelVersion: v4.14
+Contact: linux-nvdimm@lists.01.org
+Description:
+ (RO) Size of a write request to a DIMM that will not incur a
+ read-modify-write cycle at the memory controller.
+
+ When the nfit driver initializes it runs an ARS (Address Range
+ Scrub) operation across every pmem range. Part of that process
+ involves determining the ARS capabilities of a given address
+ range. One of the capabilities that is reported is the 'Clear
+ Uncorrectable Error Range Length Unit Size' (see: ACPI 6.2
+ section 9.20.7.4 Function Index 1 - Query ARS Capabilities).
+ This property indicates the boundary at which the NVDIMM may
+ need to perform read-modify-write cycles to maintain ECC (Error
+ Correcting Code) blocks.
diff --git a/Documentation/ABI/testing/sysfs-bus-rapidio b/Documentation/ABI/testing/sysfs-bus-rapidio
new file mode 100644
index 000000000000..13208b27dd87
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-rapidio
@@ -0,0 +1,198 @@
+What: /sys/bus/rapidio/devices/nn:d:iiii
+Description:
+ For each RapidIO device, the RapidIO subsystem creates files in
+ an individual subdirectory with the following name format of
+ device_name "nn:d:iiii", where:
+
+ nn - two-digit hexadecimal ID of RapidIO network where the
+ device resides
+ d - device type: 'e' - for endpoint or 's' - for switch
+ iiii - four-digit device destID for endpoints, or switchID for
+ switches
+
+ For example, below is a list of device directories that
+ represents a typical RapidIO network with one switch, one host,
+ and two agent endpoints, as it is seen by the enumerating host
+ (with destID = 1):
+
+ /sys/bus/rapidio/devices/00:e:0000
+ /sys/bus/rapidio/devices/00:e:0002
+ /sys/bus/rapidio/devices/00:s:0001
+
+ NOTE: An enumerating or discovering endpoint does not create a
+ sysfs entry for itself, this is why an endpoint with destID=1 is
+ not shown in the list.
+
+Attributes Common for All RapidIO Devices
+-----------------------------------------
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/did
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns the device identifier
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/vid
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns the device vendor identifier
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/device_rev
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns the device revision level
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/asm_did
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns identifier for the assembly containing the device
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/asm_rev
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns revision level of the assembly containing the
+ device
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/asm_vid
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns vendor identifier of the assembly containing the
+ device
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/destid
+Date: Mar, 2011
+KernelVersion: v2.6.3
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns device destination ID assigned by the enumeration
+ routine
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/lprev
+Date: Mar, 2011
+KernelVersion: v2.6.39
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns name of previous device (switch) on the path to the
+ device that that owns this attribute
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/modalias
+Date: Jul, 2013
+KernelVersion: v3.11
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns the device modalias
+
+What: /sys/bus/rapidio/devices/nn:d:iiii/config
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RW) Binary attribute to read from and write to the device
+ configuration registers using the RapidIO maintenance
+ transactions. This attribute is similar in behaviour to the
+ "config" attribute of PCI devices and provides an access to the
+ RapidIO device registers using standard file read and write
+ operations.
+
+RapidIO Switch Device Attributes
+--------------------------------
+
+RapidIO switches have additional attributes in sysfs. RapidIO subsystem supports
+common and device-specific sysfs attributes for switches. Because switches are
+integrated into the RapidIO subsystem, it offers a method to create
+device-specific sysfs attributes by specifying a callback function that may be
+set by the switch initialization routine during enumeration or discovery
+process.
+
+What: /sys/bus/rapidio/devices/nn:s:iiii/routes
+Date: Nov, 2005
+KernelVersion: v2.6.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) reports switch routing information in "destID port" format.
+ This attribute reports only valid routing table entries, one
+ line for each entry.
+
+What: /sys/bus/rapidio/devices/nn:s:iiii/destid
+Date: Mar, 2011
+KernelVersion: v2.6.3
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) device destination ID of the associated device that defines
+ a route to the switch
+
+What: /sys/bus/rapidio/devices/nn:s:iiii/hopcount
+Date: Mar, 2011
+KernelVersion: v2.6.39
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) number of hops on the path to the switch
+
+What: /sys/bus/rapidio/devices/nn:s:iiii/lnext
+Date: Mar, 2011
+KernelVersion: v2.6.39
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) returns names of devices linked to the switch except one of
+ a device linked to the ingress port (reported as "lprev"). This
+ is an array names with number of lines equal to number of ports
+ in switch. If a switch port has no attached device, returns
+ "null" instead of a device name.
+
+Device-specific Switch Attributes
+---------------------------------
+
+IDT_GEN2-
+
+What: /sys/bus/rapidio/devices/nn:s:iiii/errlog
+Date: Oct, 2010
+KernelVersion: v2.6.37
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) reads contents of device error log until it is empty.
+
+RapidIO Bus Attributes
+----------------------
+
+What: /sys/bus/rapidio/scan
+Date: May, 2013
+KernelVersion: v3.11
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (WO) Allows to trigger enumeration discovery process from user
+ space. To initiate an enumeration or discovery process on
+ specific mport device, a user needs to write mport_ID (not
+ RapidIO destination ID) into this file. The mport_ID is a
+ sequential number (0 ... RIO_MAX_MPORTS) assigned to the mport
+ device. For example, for a machine with a single RapidIO
+ controller, mport_ID for that controller always will be 0. To
+ initiate RapidIO enumeration/discovery on all available mports a
+ user must write '-1' (or RIO_MPORT_ANY) into this attribute
+ file.
diff --git a/Documentation/ABI/testing/sysfs-bus-rbd b/Documentation/ABI/testing/sysfs-bus-rbd
index f208ac58d613..cc30bee8b5f4 100644
--- a/Documentation/ABI/testing/sysfs-bus-rbd
+++ b/Documentation/ABI/testing/sysfs-bus-rbd
@@ -1,121 +1,162 @@
-What: /sys/bus/rbd/
-Date: November 2010
-Contact: Yehuda Sadeh <yehuda@newdream.net>,
- Sage Weil <sage@newdream.net>
+What: /sys/bus/rbd/add
+Date: Oct, 2010
+KernelVersion: v2.6.37
+Contact: Sage Weil <sage@newdream.net>
Description:
+ (WO) Add rbd block device.
-Being used for adding and removing rbd block devices.
+ Usage: <mon ip addr> <options> <pool name> <rbd image name> [<snap name>]
-Usage: <mon ip addr> <options> <pool name> <rbd image name> [<snap name>]
+ $ echo "192.168.0.1 name=admin rbd foo" > /sys/bus/rbd/add
- $ echo "192.168.0.1 name=admin rbd foo" > /sys/bus/rbd/add
+ The snapshot name can be "-" or omitted to map the image
+ read/write. A <dev-id> will be assigned for any registered block
+ device. If snapshot is used, it will be mapped read-only.
-The snapshot name can be "-" or omitted to map the image read/write. A <dev-id>
-will be assigned for any registered block device. If snapshot is used, it will
-be mapped read-only.
-Usage: <dev-id> [force]
+What: /sys/bus/rbd/remove
+Date: Oct, 2010
+KernelVersion: v2.6.37
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (WO) Remove rbd block device.
+
+ Usage: <dev-id> [force]
- $ echo 2 > /sys/bus/rbd/remove
+ $ echo 2 > /sys/bus/rbd/remove
+
+ Optional "force" argument which when passed will wait for
+ running requests and then unmap the image. Requests sent to the
+ driver after initiating the removal will be failed. (August
+ 2016, since 4.9.)
-Optional "force" argument which when passed will wait for running requests and
-then unmap the image. Requests sent to the driver after initiating the removal
-will be failed. (August 2016, since 4.9.)
What: /sys/bus/rbd/add_single_major
-Date: December 2013
-KernelVersion: 3.14
-Contact: Sage Weil <sage@inktank.com>
-Description: Available only if rbd module is inserted with single_major
+Date: Dec, 2013
+KernelVersion: v3.14
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (WO) Available only if rbd module is inserted with single_major
parameter set to true.
- Usage is the same as for /sys/bus/rbd/add. If present,
+
+ Usage is the same as for /sys/bus/rbd/add. If present, this
should be used instead of the latter: any attempts to use
- /sys/bus/rbd/add if /sys/bus/rbd/add_single_major is
- available will fail for backwards compatibility reasons.
+ /sys/bus/rbd/add if /sys/bus/rbd/add_single_major is available
+ will fail for backwards compatibility reasons.
+
What: /sys/bus/rbd/remove_single_major
-Date: December 2013
-KernelVersion: 3.14
-Contact: Sage Weil <sage@inktank.com>
-Description: Available only if rbd module is inserted with single_major
+Date: Dec, 2013
+KernelVersion: v3.14
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (WO) Available only if rbd module is inserted with single_major
parameter set to true.
- Usage is the same as for /sys/bus/rbd/remove. If present,
+
+ Usage is the same as for /sys/bus/rbd/remove. If present, this
should be used instead of the latter: any attempts to use
/sys/bus/rbd/remove if /sys/bus/rbd/remove_single_major is
available will fail for backwards compatibility reasons.
-Entries under /sys/bus/rbd/devices/<dev-id>/
---------------------------------------------
-
-client_addr
-
- The ceph unique client entity_addr_t (address + nonce).
- The format is <address>:<port>/<nonce>: '1.2.3.4:1234/5678' or
- '[1:2:3:4:5:6:7:8]:1234/5678'. (August 2016, since 4.9.)
-
-client_id
-
- The ceph unique client id that was assigned for this specific session.
-
-cluster_fsid
- The ceph cluster UUID. (August 2016, since 4.9.)
-
-config_info
-
- The string written into /sys/bus/rbd/add{,_single_major}. (August
- 2016, since 4.9.)
-
-features
-
- A hexadecimal encoding of the feature bits for this image.
-
-major
-
- The block device major number.
+What: /sys/bus/rbd/supported_features
+Date: Mar, 2017
+KernelVersion: v4.11
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (RO) Displays the features supported by the rbd module so that
+ userspace can generate meaningful error messages and spell out
+ unsupported features that need to be disabled.
+
+
+What: /sys/bus/rbd/devices/<dev-id>/size
+What: /sys/bus/rbd/devices/<dev-id>/major
+What: /sys/bus/rbd/devices/<dev-id>/client_id
+What: /sys/bus/rbd/devices/<dev-id>/pool
+What: /sys/bus/rbd/devices/<dev-id>/name
+What: /sys/bus/rbd/devices/<dev-id>/refresh
+What: /sys/bus/rbd/devices/<dev-id>/current_snap
+Date: Oct, 2010
+KernelVersion: v2.6.37
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ size: (RO) The size (in bytes) of the mapped block
+ device.
-minor
+ major: (RO) The block device major number.
- The block device minor number. (December 2013, since 3.14.)
+ client_id: (RO) The ceph unique client id that was assigned
+ for this specific session.
-name
+ pool: (RO) The name of the storage pool where this rbd
+ image resides. An rbd image name is unique
+ within its pool.
- The name of the rbd image.
+ name: (RO) The name of the rbd image.
-image_id
+ refresh: (WO) Writing to this file will reread the image
+ header data and set all relevant data structures
+ accordingly.
- The unique id for the rbd image. (For rbd image format 1
- this is empty.)
+ current_snap: (RO) The current snapshot for which the device
+ is mapped.
-pool
- The name of the storage pool where this rbd image resides.
- An rbd image name is unique within its pool.
+What: /sys/bus/rbd/devices/<dev-id>/pool_id
+Date: Jul, 2012
+KernelVersion: v3.6
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (RO) The unique identifier for the rbd image's pool. This is a
+ permanent attribute of the pool. A pool's id will never change.
-pool_id
- The unique identifier for the rbd image's pool. This is
- a permanent attribute of the pool. A pool's id will never
- change.
+What: /sys/bus/rbd/devices/<dev-id>/image_id
+What: /sys/bus/rbd/devices/<dev-id>/features
+Date: Oct, 2012
+KernelVersion: v3.7
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ image_id: (RO) The unique id for the rbd image. (For rbd
+ image format 1 this is empty.)
-size
+ features: (RO) A hexadecimal encoding of the feature bits
+ for this image.
- The size (in bytes) of the mapped block device.
-refresh
+What: /sys/bus/rbd/devices/<dev-id>/parent
+Date: Nov, 2012
+KernelVersion: v3.8
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (RO) Information identifying the chain of parent images in a
+ layered rbd image. Entries are separated by empty lines.
- Writing to this file will reread the image header data and set
- all relevant datastructures accordingly.
-current_snap
+What: /sys/bus/rbd/devices/<dev-id>/minor
+Date: Dec, 2013
+KernelVersion: v3.14
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ (RO) The block device minor number.
- The current snapshot for which the device is mapped.
-snap_id
+What: /sys/bus/rbd/devices/<dev-id>/snap_id
+What: /sys/bus/rbd/devices/<dev-id>/config_info
+What: /sys/bus/rbd/devices/<dev-id>/cluster_fsid
+What: /sys/bus/rbd/devices/<dev-id>/client_addr
+Date: Aug, 2016
+KernelVersion: v4.9
+Contact: Sage Weil <sage@newdream.net>
+Description:
+ snap_id: (RO) The current snapshot's id.
- The current snapshot's id. (August 2016, since 4.9.)
+ config_info: (RO) The string written into
+ /sys/bus/rbd/add{,_single_major}.
-parent
+ cluster_fsid: (RO) The ceph cluster UUID.
- Information identifying the chain of parent images in a layered rbd
- image. Entries are separated by empty lines.
+ client_addr: (RO) The ceph unique client
+ entity_addr_t (address + nonce). The format is
+ <address>:<port>/<nonce>: '1.2.3.4:1234/5678' or
+ '[1:2:3:4:5:6:7:8]:1234/5678'.
diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt b/Documentation/ABI/testing/sysfs-bus-thunderbolt
index 93798c02e28b..151584a1f950 100644
--- a/Documentation/ABI/testing/sysfs-bus-thunderbolt
+++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt
@@ -1,3 +1,26 @@
+What: /sys/bus/thunderbolt/devices/.../domainX/boot_acl
+Date: Jun 2018
+KernelVersion: 4.17
+Contact: thunderbolt-software@lists.01.org
+Description: Holds a comma separated list of device unique_ids that
+ are allowed to be connected automatically during system
+ startup (e.g boot devices). The list always contains
+ maximum supported number of unique_ids where unused
+ entries are empty. This allows the userspace software
+ to determine how many entries the controller supports.
+ If there are multiple controllers, each controller has
+ its own ACL list and size may be different between the
+ controllers.
+
+ System BIOS may have an option "Preboot ACL" or similar
+ that needs to be selected before this list is taken into
+ consideration.
+
+ Software always updates a full list in each write.
+
+ If a device is authorized automatically during boot its
+ boot attribute is set to 1.
+
What: /sys/bus/thunderbolt/devices/.../domainX/security
Date: Sep 2017
KernelVersion: 4.13
@@ -12,6 +35,9 @@ Description: This attribute holds current Thunderbolt security level
minimum. User needs to authorize each device.
dponly: Automatically tunnel Display port (and USB). No
PCIe tunnels are created.
+ usbonly: Automatically tunnel USB controller of the
+ connected Thunderbolt dock (and Display Port). All
+ PCIe links downstream of the dock are removed.
What: /sys/bus/thunderbolt/devices/.../authorized
Date: Sep 2017
@@ -38,6 +64,13 @@ Description: This attribute is used to authorize Thunderbolt devices
the device did not contain a key at all, and
EKEYREJECTED if the challenge response did not match.
+What: /sys/bus/thunderbolt/devices/.../boot
+Date: Jun 2018
+KernelVersion: 4.17
+Contact: thunderbolt-software@lists.01.org
+Description: This attribute contains 1 if Thunderbolt device was already
+ authorized on boot and 0 otherwise.
+
What: /sys/bus/thunderbolt/devices/.../key
Date: Sep 2017
KernelVersion: 4.13
diff --git a/Documentation/ABI/testing/sysfs-bus-usb b/Documentation/ABI/testing/sysfs-bus-usb
index 0bd731cbb50c..c702c78f24d8 100644
--- a/Documentation/ABI/testing/sysfs-bus-usb
+++ b/Documentation/ABI/testing/sysfs-bus-usb
@@ -189,6 +189,16 @@ Description:
The file will read "hotplug", "wired" and "not used" if the
information is available, and "unknown" otherwise.
+What: /sys/bus/usb/devices/.../(hub interface)/portX/over_current_count
+Date: February 2018
+Contact: Richard Leitner <richard.leitner@skidata.com>
+Description:
+ Most hubs are able to detect over-current situations on their
+ ports and report them to the kernel. This attribute is to expose
+ the number of over-current situation occurred on a specific port
+ to user space. This file will contain an unsigned 32 bit value
+ which wraps to 0 after its maximum is reached.
+
What: /sys/bus/usb/devices/.../(hub interface)/portX/usb3_lpm_permit
Date: November 2015
Contact: Lu Baolu <baolu.lu@linux.intel.com>
diff --git a/Documentation/ABI/testing/sysfs-class-backlight-adp5520 b/Documentation/ABI/testing/sysfs-class-backlight-adp5520
new file mode 100644
index 000000000000..34b6ebafa210
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-backlight-adp5520
@@ -0,0 +1,31 @@
+sysfs interface for analog devices adp5520(01) backlight driver
+---------------------------------------------------------------
+
+The backlight brightness control operates at three different levels for the
+adp5520 and adp5501 devices: daylight (level 1), office (level 2) and dark
+(level 3). By default the brightness operates at the daylight brightness level.
+
+What: /sys/class/backlight/<backlight>/daylight_max
+What: /sys/class/backlight/<backlight>/office_max
+What: /sys/class/backlight/<backlight>/dark_max
+Date: Sep, 2009
+KernelVersion: v2.6.32
+Contact: Michael Hennerich <michael.hennerich@analog.com>
+Description:
+ (RW) Maximum current setting for the backlight when brightness
+ is at one of the three levels (daylight, office or dark). This
+ is an input code between 0 and 127, which is transformed to a
+ value between 0 mA and 30 mA using linear or non-linear
+ algorithms.
+
+What: /sys/class/backlight/<backlight>/daylight_dim
+What: /sys/class/backlight/<backlight>/office_dim
+What: /sys/class/backlight/<backlight>/dark_dim
+Date: Sep, 2009
+KernelVersion: v2.6.32
+Contact: Michael Hennerich <michael.hennerich@analog.com>
+Description:
+ (RW) Dim current setting for the backlight when brightness is at
+ one of the three levels (daylight, office or dark). This is an
+ input code between 0 and 127, which is transformed to a value
+ between 0 mA and 30 mA using linear or non-linear algorithms.
diff --git a/Documentation/ABI/testing/sysfs-class-backlight-adp8860 b/Documentation/ABI/testing/sysfs-class-backlight-adp8860
new file mode 100644
index 000000000000..54d61c788b1b
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-backlight-adp8860
@@ -0,0 +1,54 @@
+sysfs interface for analog devices adp8860 backlight driver
+-----------------------------------------------------------
+
+The backlight brightness control operates at three different levels for the
+adp8860, adp8861 and adp8863 devices: daylight (level 1), office (level 2) and
+dark (level 3). By default the brightness operates at the daylight brightness
+level.
+
+What: /sys/class/backlight/<backlight>/ambient_light_level
+Date: Apr, 2010
+KernelVersion: v2.6.35
+Contact: Michael Hennerich <michael.hennerich@analog.com>
+Description:
+ (RO) 13-bit conversion value for the first light sensor—high
+ byte (Bit 12 to Bit 8). The value is updated every 80 ms (when
+ the light sensor is enabled).
+
+
+What: /sys/class/backlight/<backlight>/ambient_light_zone
+Date: Apr, 2010
+KernelVersion: v2.6.35
+Contact: Michael Hennerich <michael.hennerich@analog.com>
+Description:
+ (RW) Read or write the specific level at which the backlight
+ operates. Value "0" enables automatic ambient light sensing, and
+ values "1", "2" or "3" set the control to daylight, office or
+ dark respectively.
+
+
+What: /sys/class/backlight/<backlight>/l1_daylight_max
+What: /sys/class/backlight/<backlight>/l2_office_max
+What: /sys/class/backlight/<backlight>/l3_dark_max
+Date: Apr, 2010
+KernelVersion: v2.6.35
+Contact: Michael Hennerich <michael.hennerich@analog.com>
+Description:
+ (RW) Maximum current setting for the backlight when brightness
+ is at one of the three levels (daylight, office or dark). This
+ is an input code between 0 and 127, which is transformed to a
+ value between 0 mA and 30 mA using linear or non-linear
+ algorithms.
+
+
+What: /sys/class/backlight/<backlight>/l1_daylight_dim
+What: /sys/class/backlight/<backlight>/l2_office_dim
+What: /sys/class/backlight/<backlight>/l3_dark_dim
+Date: Apr, 2010
+KernelVersion: v2.6.35
+Contact: Michael Hennerich <michael.hennerich@analog.com>
+Description:
+ (RW) Dim current setting for the backlight when brightness is at
+ one of the three levels (daylight, office or dark). This is an
+ input code between 0 and 127, which is transformed to a value
+ between 0 mA and 30 mA using linear or non-linear algorithms.
diff --git a/Documentation/ABI/testing/sysfs-class-backlight-lm3639 b/Documentation/ABI/testing/sysfs-class-backlight-lm3639
new file mode 100644
index 000000000000..f7e92a82ea25
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-backlight-lm3639
@@ -0,0 +1,11 @@
+sysfs interface for Texas Instruments lm3639 backlight + flash led driver chip
+------------------------------------------------------------------------------
+
+What: /sys/class/backlight/<backlight>/bled_mode
+Date: Oct, 2012
+KernelVersion: v3.10
+Contact: dri-devel@lists.freedesktop.org
+Description:
+ (WO) Write to the backlight mapping mode. The backlight current
+ can be mapped for either exponential (value "0") or linear
+ mapping modes (default).
diff --git a/Documentation/ABI/testing/sysfs-class-bsr b/Documentation/ABI/testing/sysfs-class-bsr
new file mode 100644
index 000000000000..7bf145d32cbc
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-bsr
@@ -0,0 +1,25 @@
+What: /sys/class/bsr/bsr*/bsr_size
+Date: Jul, 2008
+KernelVersion: 2.6.27
+Contact: Arnd Bergmann <arnd@arndb.de>,
+ Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Description:
+ (RO) Size of the barrier-synchronization register (BSR)
+ register in bytes.
+
+What: /sys/class/bsr/bsr*/bsr_length
+Date: Jul, 2008
+KernelVersion: 2.6.27
+Contact: Arnd Bergmann <arnd@arndb.de>,
+ Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Description:
+ (RO) The length of memory region that can be mapped in bytes.
+
+What: /sys/class/bsr/bsr*/bsr_stride
+Date: Jul, 2008
+KernelVersion: 2.6.27
+Contact: Arnd Bergmann <arnd@arndb.de>,
+ Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Description:
+ (RO) The stride or the interval at which the allocated BSR bytes
+ repeat within the mapping.
diff --git a/Documentation/ABI/testing/sysfs-class-infiniband b/Documentation/ABI/testing/sysfs-class-infiniband
deleted file mode 100644
index a86abe66a316..000000000000
--- a/Documentation/ABI/testing/sysfs-class-infiniband
+++ /dev/null
@@ -1,16 +0,0 @@
-What: /sys/class/infiniband/<hca>/ports/<port-number>/gid_attrs/ndevs/<gid-index>
-Date: November 29, 2015
-KernelVersion: 4.4.0
-Contact: linux-rdma@vger.kernel.org
-Description: The net-device's name associated with the GID resides
- at index <gid-index>.
-
-What: /sys/class/infiniband/<hca>/ports/<port-number>/gid_attrs/types/<gid-index>
-Date: November 29, 2015
-KernelVersion: 4.4.0
-Contact: linux-rdma@vger.kernel.org
-Description: The RoCE type of the associated GID resides at index <gid-index>.
- This could either be "IB/RoCE v1" for IB and RoCE v1 based GODs
- or "RoCE v2" for RoCE v2 based GIDs.
-
-
diff --git a/Documentation/ABI/testing/sysfs-class-lcd-s6e63m0 b/Documentation/ABI/testing/sysfs-class-lcd-s6e63m0
new file mode 100644
index 000000000000..ae0a2d3dcc07
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-lcd-s6e63m0
@@ -0,0 +1,27 @@
+sysfs interface for the S6E63M0 AMOLED LCD panel driver
+-------------------------------------------------------
+
+What: /sys/class/lcd/<lcd>/gamma_mode
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: dri-devel@lists.freedesktop.org
+Description:
+ (RW) Read or write the gamma mode. Following three modes are
+ supported:
+ 0 - gamma value 2.2,
+ 1 - gamma value 1.9 and
+ 2 - gamma value 1.7.
+
+
+What: /sys/class/lcd/<lcd>/gamma_table
+Date: May, 2010
+KernelVersion: v2.6.35
+Contact: dri-devel@lists.freedesktop.org
+Description:
+ (RO) Displays the size of the gamma table i.e. the number of
+ gamma modes available.
+
+This is a backlight lcd driver. These interfaces are an extension to the API
+documented in Documentation/ABI/testing/sysfs-class-lcd and in
+Documentation/ABI/stable/sysfs-class-backlight (under
+/sys/class/backlight/<backlight>/).
diff --git a/Documentation/ABI/testing/sysfs-class-mei b/Documentation/ABI/testing/sysfs-class-mei
index 5096a82f4cde..81ff6abf9673 100644
--- a/Documentation/ABI/testing/sysfs-class-mei
+++ b/Documentation/ABI/testing/sysfs-class-mei
@@ -45,3 +45,12 @@ Contact: Tomas Winkler <tomas.winkler@intel.com>
Description: Display the driver HBM protocol version.
The HBM protocol version supported by the driver.
+
+What: /sys/class/mei/meiN/tx_queue_limit
+Date: Jan 2018
+KernelVersion: 4.16
+Contact: Tomas Winkler <tomas.winkler@intel.com>
+Description: Configure tx queue limit
+
+ Set maximal number of pending writes
+ per opened session.
diff --git a/Documentation/ABI/testing/sysfs-class-pktcdvd b/Documentation/ABI/testing/sysfs-class-pktcdvd
index b1c3f0263359..dde4f26d0780 100644
--- a/Documentation/ABI/testing/sysfs-class-pktcdvd
+++ b/Documentation/ABI/testing/sysfs-class-pktcdvd
@@ -1,60 +1,81 @@
-What: /sys/class/pktcdvd/
-Date: Oct. 2006
-KernelVersion: 2.6.20
-Contact: Thomas Maier <balagi@justmail.de>
-Description:
-
sysfs interface
---------------
+The pktcdvd module (packet writing driver) creates the following files in the
+sysfs: (<devid> is in the format major:minor)
+
+What: /sys/class/pktcdvd/add
+What: /sys/class/pktcdvd/remove
+What: /sys/class/pktcdvd/device_map
+Date: Oct. 2006
+KernelVersion: 2.6.20
+Contact: Thomas Maier <balagi@justmail.de>
+Description:
+
+ add: (WO) Write a block device id (major:minor) to
+ create a new pktcdvd device and map it to the
+ block device.
+
+ remove: (WO) Write the pktcdvd device id (major:minor)
+ to remove the pktcdvd device.
+
+ device_map: (RO) Shows the device mapping in format:
+ pktcdvd[0-7] <pktdevid> <blkdevid>
+
+
+What: /sys/class/pktcdvd/pktcdvd[0-7]/dev
+What: /sys/class/pktcdvd/pktcdvd[0-7]/uevent
+Date: Oct. 2006
+KernelVersion: 2.6.20
+Contact: Thomas Maier <balagi@justmail.de>
+Description:
+ dev: (RO) Device id
+
+ uevent: (WO) To send a uevent
+
+
+What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/packets_started
+What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/packets_finished
+What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/kb_written
+What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/kb_read
+What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/kb_read_gather
+What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/reset
+Date: Oct. 2006
+KernelVersion: 2.6.20
+Contact: Thomas Maier <balagi@justmail.de>
+Description:
+ packets_started: (RO) Number of started packets.
+
+ packets_finished: (RO) Number of finished packets.
+
+ kb_written: (RO) kBytes written.
+
+ kb_read: (RO) kBytes read.
+
+ kb_read_gather: (RO) kBytes read to fill write packets.
+
+ reset: (WO) Write any value to it to reset
+ pktcdvd device statistic values, like
+ bytes read/written.
+
+
+What: /sys/class/pktcdvd/pktcdvd[0-7]/write_queue/size
+What: /sys/class/pktcdvd/pktcdvd[0-7]/write_queue/congestion_off
+What: /sys/class/pktcdvd/pktcdvd[0-7]/write_queue/congestion_on
+Date: Oct. 2006
+KernelVersion: 2.6.20
+Contact: Thomas Maier <balagi@justmail.de>
+Description:
+ size: (RO) Contains the size of the bio write queue.
+
+ congestion_off: (RW) If bio write queue size is below this mark,
+ accept new bio requests from the block layer.
-The pktcdvd module (packet writing driver) creates
-these files in the sysfs:
-(<devid> is in format major:minor )
-
-/sys/class/pktcdvd/
- add (0200) Write a block device id (major:minor)
- to create a new pktcdvd device and map
- it to the block device.
-
- remove (0200) Write the pktcdvd device id (major:minor)
- to it to remove the pktcdvd device.
-
- device_map (0444) Shows the device mapping in format:
- pktcdvd[0-7] <pktdevid> <blkdevid>
-
-/sys/class/pktcdvd/pktcdvd[0-7]/
- dev (0444) Device id
- uevent (0200) To send an uevent.
-
-/sys/class/pktcdvd/pktcdvd[0-7]/stat/
- packets_started (0444) Number of started packets.
- packets_finished (0444) Number of finished packets.
-
- kb_written (0444) kBytes written.
- kb_read (0444) kBytes read.
- kb_read_gather (0444) kBytes read to fill write packets.
-
- reset (0200) Write any value to it to reset
- pktcdvd device statistic values, like
- bytes read/written.
-
-/sys/class/pktcdvd/pktcdvd[0-7]/write_queue/
- size (0444) Contains the size of the bio write
- queue.
-
- congestion_off (0644) If bio write queue size is below
- this mark, accept new bio requests
- from the block layer.
-
- congestion_on (0644) If bio write queue size is higher
- as this mark, do no longer accept
- bio write requests from the block
- layer and wait till the pktcdvd
- device has processed enough bio's
- so that bio write queue size is
- below congestion off mark.
- A value of <= 0 disables congestion
- control.
+ congestion_on: (RW) If bio write queue size is higher as this
+ mark, do no longer accept bio write requests
+ from the block layer and wait till the pktcdvd
+ device has processed enough bio's so that bio
+ write queue size is below congestion off mark.
+ A value of <= 0 disables congestion control.
Example:
diff --git a/Documentation/ABI/testing/sysfs-class-rapidio b/Documentation/ABI/testing/sysfs-class-rapidio
new file mode 100644
index 000000000000..8716beeb16c1
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-rapidio
@@ -0,0 +1,55 @@
+What: /sys/class/rapidio_port
+Description:
+ On-chip RapidIO controllers and PCIe-to-RapidIO bridges
+ (referenced as "Master Port" or "mport") are presented in sysfs
+ as the special class of devices: "rapidio_port".
+ The /sys/class/rapidio_port subdirectory contains individual
+ subdirectories named as "rapidioN" where N = mport ID registered
+ with RapidIO subsystem.
+ NOTE: An mport ID is not a RapidIO destination ID assigned to a
+ given local mport device.
+
+What: /sys/class/rapidio_port/rapidioN/sys_size
+Date: Apr, 2014
+KernelVersion: v3.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) reports RapidIO common transport system size:
+ 0 = small (8-bit destination ID, max. 256 devices),
+ 1 = large (16-bit destination ID, max. 65536 devices).
+
+What: /sys/class/rapidio_port/rapidioN/port_destid
+Date: Apr, 2014
+KernelVersion: v3.15
+Contact: Matt Porter <mporter@kernel.crashing.org>,
+ Alexandre Bounine <alexandre.bounine@idt.com>
+Description:
+ (RO) reports RapidIO destination ID assigned to the given
+ RapidIO mport device. If value 0xFFFFFFFF is returned this means
+ that no valid destination ID have been assigned to the mport
+ (yet). Normally, before enumeration/discovery have been executed
+ only fabric enumerating mports have a valid destination ID
+ assigned to them using "hdid=..." rapidio module parameter.
+
+After enumeration or discovery was performed for a given mport device,
+the corresponding subdirectory will also contain subdirectories for each
+child RapidIO device connected to the mport.
+
+The example below shows mport device subdirectory with several child RapidIO
+devices attached to it.
+
+[rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
+total 0
+drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
+drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
+drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0007
+drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0002
+drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0003
+drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0005
+lrwxrwxrwx 1 root root 0 Feb 11 15:11 device -> ../../../0000:01:00.0
+-r--r--r-- 1 root root 4096 Feb 11 15:11 port_destid
+drwxr-xr-x 2 root root 0 Feb 11 15:11 power
+lrwxrwxrwx 1 root root 0 Feb 11 15:04 subsystem -> ../../../../../../class/rapidio_port
+-r--r--r-- 1 root root 4096 Feb 11 15:11 sys_size
+-rw-r--r-- 1 root root 4096 Feb 11 15:04 uevent
diff --git a/Documentation/ABI/testing/sysfs-class-rtc b/Documentation/ABI/testing/sysfs-class-rtc
index cf60412882f0..95984289a4ee 100644
--- a/Documentation/ABI/testing/sysfs-class-rtc
+++ b/Documentation/ABI/testing/sysfs-class-rtc
@@ -43,6 +43,14 @@ Contact: linux-rtc@vger.kernel.org
Description:
(RO) The name of the RTC corresponding to this sysfs directory
+What: /sys/class/rtc/rtcX/range
+Date: January 2018
+KernelVersion: 4.16
+Contact: linux-rtc@vger.kernel.org
+Description:
+ Valid time range for the RTC, as seconds from epoch, formatted
+ as [min, max]
+
What: /sys/class/rtc/rtcX/since_epoch
Date: March 2006
KernelVersion: 2.6.17
@@ -57,14 +65,6 @@ Contact: linux-rtc@vger.kernel.org
Description:
(RO) RTC-provided time in 24-hour notation (hh:mm:ss)
-What: /sys/class/rtc/rtcX/*/nvmem
-Date: February 2016
-KernelVersion: 4.6
-Contact: linux-rtc@vger.kernel.org
-Description:
- (RW) The non volatile storage exported as a raw file, as
- described in Documentation/nvmem/nvmem.txt
-
What: /sys/class/rtc/rtcX/offset
Date: February 2016
KernelVersion: 4.6
diff --git a/Documentation/ABI/testing/sysfs-class-usb_role b/Documentation/ABI/testing/sysfs-class-usb_role
new file mode 100644
index 000000000000..3b810a425a52
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-usb_role
@@ -0,0 +1,21 @@
+What: /sys/class/usb_role/
+Date: Jan 2018
+Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+ Place in sysfs for USB Role Switches. USB Role Switch is a
+ device that can select the data role (host or device) for USB
+ port.
+
+What: /sys/class/usb_role/<switch>/role
+Date: Jan 2018
+Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+ The current role of the switch. This attribute can be used for
+ requesting role swapping with non-USB Type-C ports. With USB
+ Type-C ports, the ABI defined for USB Type-C connector class
+ must be used.
+
+ Valid values:
+ - none
+ - host
+ - device
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD b/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
new file mode 100644
index 000000000000..7e43cdce9a52
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-ACPI-TAD
@@ -0,0 +1,113 @@
+ ACPI Time and Alarm (TAD) device attributes.
+
+What: /sys/bus/platform/devices/ACPI000E:00/caps
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Description:
+ (RO) Hexadecimal bitmask of the TAD attributes are reported by
+ the platform firmware (see ACPI 6.2, section 9.18.2):
+
+ BIT(0): AC wakeup implemented if set
+ BIT(1): DC wakeup implemented if set
+ BIT(2): Get/set real time features implemented if set
+ BIT(3): Real time accuracy in milliseconds if set
+ BIT(4): Correct status reported for wakeups from S4/S5 if set
+ BIT(5): The AC timer wakes up from S4 if set
+ BIT(6): The AC timer wakes up from S5 if set
+ BIT(7): The DC timer wakes up from S4 if set
+ BIT(8): The DC timer wakes up from S5 if set
+
+ The other bits are reserved.
+
+What: /sys/bus/platform/devices/ACPI000E:00/ac_alarm
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Description:
+ (RW) The AC alarm timer value.
+
+ Reads return the current AC alarm timer value in seconds or
+ "disabled", if the AC alarm is not set to wake up the system.
+
+ Write a new AC alarm timer value in seconds or "disabled" to it
+ to set the AC alarm timer or to disable it, respectively.
+
+ If the AC alarm timer is set through this attribute and it
+ expires, it will immediately wake up the system from the S3
+ sleep state (and from S4/S5 too if supported) until its status
+ is explicitly cleared via the ac_status attribute.
+
+What: /sys/bus/platform/devices/ACPI000E:00/ac_policy
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Description:
+ (RW) The AC alarm expired timer wake policy (see ACPI 6.2,
+ Section 9.18 for details).
+
+ Reads return the current expired timer wake delay for the AC
+ alarm timer or "never", if the policy is to discard AC timer
+ wakeups if the system is on DC power.
+
+ Write a new expired timer wake delay for the AC alarm timer in
+ seconds or "never" to it to set the expired timer wake delay for
+ the AC alarm timer or to set its expired wake policy to discard
+ wakeups if the system is on DC power, respectively.
+
+What: /sys/bus/platform/devices/ACPI000E:00/ac_status
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Description:
+ (RW) The AC alarm status.
+
+ Reads return a hexadecimal bitmask representing the AC alarm
+ timer status with the following meaning of bits (see ACPI 6.2,
+ Section 9.18.5):
+
+ Bit(0): The timer has expired if set.
+ Bit(1): The timer has woken up the system from a sleep state
+ (S3 or S4/S5 if supported) if set.
+
+ The other bits are reserved.
+
+ Reads also cause the AC alarm timer status to be reset.
+
+ Another way to reset the the status of the AC alarm timer is to
+ write (the number) 0 to this file.
+
+ If the status return value indicates that the timer has expired,
+ it will immediately wake up the system from the S3 sleep state
+ (and from S4/S5 too if supported) until its status is explicitly
+ cleared through this attribute.
+
+What: /sys/bus/platform/devices/ACPI000E:00/dc_alarm
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Description:
+ (RW,optional) The DC alarm timer value.
+
+ This attribute is only present if the TAD supports a separate
+ DC timer.
+
+ It is analogous to the ac_alarm attribute.
+
+What: /sys/bus/platform/devices/ACPI000E:00/dc_policy
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Description:
+ (RW,optional) The DC alarm expired timer wake policy.
+
+ This attribute is only present if the TAD supports a separate
+ DC timer.
+
+ It is analogous to the ac_policy attribute.
+
+What: /sys/bus/platform/devices/ACPI000E:00/dc_status
+Date: March 2018
+Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+
+Description:
+ (RW,optional) The DC alarm status.
+
+ This attribute is only present if the TAD supports a separate
+ DC timer.
+
+ It is analogous to the ac_status attribute.
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-ipmi b/Documentation/ABI/testing/sysfs-devices-platform-ipmi
new file mode 100644
index 000000000000..2a781e7513b7
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-ipmi
@@ -0,0 +1,238 @@
+What: /sys/devices/platform/ipmi_bmc.*/firmware_revision
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) The major and minor revision of the firmware.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/aux_firmware_revision
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Holds additional information about the firmware revision,
+ such as boot block or internal data structure version numbers.
+ The meanings of the numbers are specific to the vendor
+ identified by Manufacturer ID.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/revision
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Device revision. Useful for identifying if significant
+ hardware changes have been made to the implementation of the
+ management controller.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/provides_device_sdrs
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Indicates whether device provides device sensor data
+ records (1) or not (0).
+
+
+What: /sys/devices/platform/ipmi_bmc.*/device_id
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Device id is specified by the manufacturer identified by
+ the Manufacturer ID field. This field allows controller specific
+ software to identify the unique application command, OEM
+ fields, and functionality that are provided by the controller
+
+
+What: /sys/devices/platform/ipmi_bmc.*/additional_device_support
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Lists the IPMI ‘logical device’ commands and functions
+ that the controller supports that are in addition to the
+ mandatory IPM and Application commands.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/ipmi_version
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Displays the IPMI Command Specification Version.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/manufacturer_id
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Identifies the manufacturer responsible for the
+ specification of functionality of the vendor (OEM)-specific
+ commands, codes, and interfaces used in the controller.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/product_id
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Displays a number that identifies a particular system,
+ module, add-in card, or board set. The number is specified
+ according to the manufacturer given by Manufacturer ID.
+
+For detailed definitions of the above attributes, refer to section 20.1 'Get
+Device ID Command' of the IPMI specification v2.0.
+
+
+What: /sys/devices/platform/ipmi_bmc.*/guid
+Date: Mar, 2006
+KernelVersion: v2.6.17
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) A GUID (Globally Unique ID), also referred to as a UUID
+ (Universally Unique Identifier), for the management controller,
+ as described in section 20.8 'Get Device GUID Command' of the
+ IPMI specification v2.0.
+
+
+What: /sys/devices/platform/ipmi_si.*/type
+Date: Sep, 2017
+KernelVersion: v4.15
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) The device interface for IPMI "kcs", "smic", "bt" or
+ "invalid"
+
+What: /sys/devices/platform/ipmi_si.*/idles
+What: /sys/devices/platform/ipmi_si.*/watchdog_pretimeouts
+What: /sys/devices/platform/ipmi_si.*/complete_transactions
+What: /sys/devices/platform/ipmi_si.*/events
+What: /sys/devices/platform/ipmi_si.*/interrupts
+What: /sys/devices/platform/ipmi_si.*/hosed_count
+What: /sys/devices/platform/ipmi_si.*/long_timeouts
+What: /sys/devices/platform/ipmi_si.*/flag_fetches
+What: /sys/devices/platform/ipmi_si.*/attentions
+What: /sys/devices/platform/ipmi_si.*/incoming_messages
+What: /sys/devices/platform/ipmi_si.*/short_timeouts
+Date: Sep, 2017
+KernelVersion: v4.15
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+
+ idles: (RO) Number of times the interface was
+ idle while being polled.
+
+ watchdog_pretimeouts: (RO) Number of watchdog pretimeouts.
+
+ complete_transactions: (RO) Number of completed messages.
+
+ events: (RO) Number of IPMI events received from
+ the hardware.
+
+ interrupts: (RO) Number of interrupts the driver
+ handled.
+
+ hosed_count: (RO) Number of times the hardware didn't
+ follow the state machine.
+
+ long_timeouts: (RO) Number of times the driver
+ requested a timer while nothing was in
+ progress.
+
+ flag_fetches: (RO) Number of times the driver
+ requested flags from the hardware.
+
+ attentions: (RO) Number of time the driver got an
+ ATTN from the hardware.
+
+ incoming_messages: (RO) Number of asynchronous messages
+ received.
+
+ short_timeouts: (RO) Number of times the driver
+ requested a timer while an operation was
+ in progress.
+
+
+What: /sys/devices/platform/ipmi_si.*/interrupts_enabled
+Date: Sep, 2017
+KernelVersion: v4.15
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Indicates whether interrupts are enabled or not. The driver
+ disables interrupts when it gets into a situation where it
+ cannot handle messages due to lack of memory. Once that
+ situation clears up, it will re-enable interrupts.
+
+
+What: /sys/devices/platform/ipmi_si.*/params
+Date: Sep, 2017
+KernelVersion: v4.15
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ [to be documented]
+
+
+What: /sys/devices/platform/dmi-ipmi-ssif.*/type
+Date: Sep, 2017
+KernelVersion: v4.15
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ (RO) Shows the IMPI device interface type - "ssif" here.
+
+
+What: /sys/devices/platform/dmi-ipmi-ssif.*/hosed
+What: /sys/devices/platform/dmi-ipmi-ssif.*/alerts
+What: /sys/devices/platform/dmi-ipmi-ssif.*/sent_messages
+What: /sys/devices/platform/dmi-ipmi-ssif.*/sent_messages_parts
+What: /sys/devices/platform/dmi-ipmi-ssif.*/received_messages
+What: /sys/devices/platform/dmi-ipmi-ssif.*/received_message_parts
+What: /sys/devices/platform/dmi-ipmi-ssif.*/events
+What: /sys/devices/platform/dmi-ipmi-ssif.*/watchdog_pretimeouts
+What: /sys/devices/platform/dmi-ipmi-ssif.*/flag_fetches
+What: /sys/devices/platform/dmi-ipmi-ssif.*/send_retries
+What: /sys/devices/platform/dmi-ipmi-ssif.*/receive_retries
+What: /sys/devices/platform/dmi-ipmi-ssif.*/send_errors
+What: /sys/devices/platform/dmi-ipmi-ssif.*/receive_errors
+Date: Sep, 2017
+KernelVersion: v4.15
+Contact: openipmi-developer@lists.sourceforge.net
+Description:
+ hosed: (RO) Number of times the hardware didn't
+ follow the state machine.
+
+ alerts: (RO) Number of alerts received.
+
+ sent_messages: (RO) Number of total messages sent.
+
+ sent_message_parts: (RO) Number of message parts sent.
+ Messages may be broken into parts if
+ they are long.
+
+ receieved_messages: (RO) Number of message responses
+ received.
+
+ received_message_parts: (RO) Number of message fragments
+ received.
+
+ events: (RO) Number of received events.
+
+ watchdog_pretimeouts: (RO) Number of watchdog pretimeouts.
+
+ flag_fetches: (RO) Number of times a flag fetch was
+ requested.
+
+ send_retries: (RO) Number of time a message was
+ retried.
+
+ receive_retries: (RO) Number of times the receive of a
+ message was retried.
+
+ send_errors: (RO) Number of times the send of a
+ message failed.
+
+ receive_errors: (RO) Number of errors in receiving
+ messages.
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-trackpoint b/Documentation/ABI/testing/sysfs-devices-platform-trackpoint
new file mode 100644
index 000000000000..df11901a6b3d
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-trackpoint
@@ -0,0 +1,115 @@
+What: /sys/devices/platform/i8042/.../sensitivity
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Trackpoint sensitivity.
+
+What: /sys/devices/platform/i8042/.../intertia
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Negative inertia factor. High values cause the cursor to
+ snap backward when the trackpoint is released.
+
+What: /sys/devices/platform/i8042/.../reach
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Backup range for z-axis press.
+
+What: /sys/devices/platform/i8042/.../draghys
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) The drag hysteresis controls how hard it is to drag with
+ z-axis pressed.
+
+What: /sys/devices/platform/i8042/.../mindrag
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Minimum amount of force needed to trigger dragging.
+
+What: /sys/devices/platform/i8042/.../speed
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Speed of the trackpoint cursor.
+
+What: /sys/devices/platform/i8042/.../thresh
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Minimum value for z-axis force required to trigger a press
+ or release, relative to the running average.
+
+What: /sys/devices/platform/i8042/.../upthresh
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) The offset from the running average required to generate a
+ select (click) on z-axis on release.
+
+What: /sys/devices/platform/i8042/.../ztime
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) This attribute determines how sharp a press has to be in
+ order to be recognized.
+
+What: /sys/devices/platform/i8042/.../jenks
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Minimum curvature in degrees required to generate a double
+ click without a release.
+
+What: /sys/devices/platform/i8042/.../skipback
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) When the skipback bit is set, backup cursor movement during
+ releases from drags will be suppressed. The default value for
+ this bit is 0.
+
+What: /sys/devices/platform/i8042/.../ext_dev
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Disable (0) or enable (1) external pointing device.
+
+What: /sys/devices/platform/i8042/.../press_to_select
+Date: Aug, 2005
+KernelVersion: 2.6.14
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Writing a value of 1 to this file will enable the Press to
+ Select functions like tapping the control stick to simulate a
+ left click, and writing 0 will disable it.
+
+What: /sys/devices/platform/i8042/.../drift_time
+Date: Dec, 2014
+KernelVersion: 3.19
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) This parameter controls the period of time to test for a
+ ‘hands off’ condition (i.e. when no force is applied) before a
+ drift (noise) calibration occurs.
+
+ IBM Trackpoints have a feature to compensate for drift by
+ recalibrating themselves periodically. By default, if for 0.5
+ seconds there is no change in position, it's used as the new
+ zero. This duration is too low. Often, the calibration happens
+ when the trackpoint is in fact being used.
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 4ed63b6cfb15..025b7cf3768d 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -198,6 +198,31 @@ Description:
time (in microseconds) this cpu should spend in this idle state
to make the transition worth the effort.
+What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/s2idle/
+Date: March 2018
+KernelVersion: v4.17
+Contact: Linux power management list <linux-pm@vger.kernel.org>
+Description:
+ Idle state usage statistics related to suspend-to-idle.
+
+ This attribute group is only present for states that can be
+ used in suspend-to-idle with suspended timekeeping.
+
+What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/s2idle/time
+Date: March 2018
+KernelVersion: v4.17
+Contact: Linux power management list <linux-pm@vger.kernel.org>
+Description:
+ Total time spent by the CPU in suspend-to-idle (with scheduler
+ tick suspended) after requesting this state.
+
+What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/s2idle/usage
+Date: March 2018
+KernelVersion: v4.17
+Contact: Linux power management list <linux-pm@vger.kernel.org>
+Description:
+ Total number of times this state has been requested by the CPU
+ while entering suspend-to-idle.
What: /sys/devices/system/cpu/cpu#/cpufreq/*
Date: pre-git history
diff --git a/Documentation/ABI/testing/sysfs-driver-fsi-master-gpio b/Documentation/ABI/testing/sysfs-driver-fsi-master-gpio
new file mode 100644
index 000000000000..1f29c8843cfd
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-fsi-master-gpio
@@ -0,0 +1,10 @@
+What: /sys/bus/platform/devices/[..]/fsi-master-gpio/external_mode
+Date: Feb 2018
+KernelVersion: 4.17
+Contact: jk@ozlabs.org
+Description:
+ Controls access arbitration for GPIO-based FSI master. A
+ value of 0 (the default) sets normal mode, where the
+ driver performs FSI bus transactions, 1 sets external mode,
+ where the FSI bus is driven externally (for example, by
+ a debug device).
diff --git a/Documentation/ABI/testing/sysfs-driver-hid-logitech-hidpp b/Documentation/ABI/testing/sysfs-driver-hid-logitech-hidpp
new file mode 100644
index 000000000000..d8f831f2d6b5
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-hid-logitech-hidpp
@@ -0,0 +1,19 @@
+What: /sys/bus/hid/drivers/logitech-hidpp-device/<dev>/range
+Date: Jan, 2016
+KernelVersion: 4.6
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) This attribute controls the amount of 'turn' permitted in
+ Logitech G920 wheel. Reading from the file shows the current
+ range of the steering wheel. Writing a value within the min and
+ max boundary sets the range of the wheel.
+
+What: /sys/bus/hid/drivers/logitech-hidpp-device/<dev>/builtin_power_supply
+Date: Apr, 2017
+KernelVersion: 4.12
+Contact: linux-input@vger.kernel.org
+Description:
+ Presence of this file indicates that HID++ driver is capable of
+ handling battery properties in the kernel. This way, upower can
+ add a udev rule to decide whether or not it should use the
+ internal unifying support or the generic kernel one.
diff --git a/Documentation/ABI/testing/sysfs-driver-hid-ntrig b/Documentation/ABI/testing/sysfs-driver-hid-ntrig
new file mode 100644
index 000000000000..e574a5625efe
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-hid-ntrig
@@ -0,0 +1,70 @@
+What: /sys/bus/hid/drivers/ntrig/<dev>/activate_slack
+Date: May, 2010
+KernelVersion: 2.6.35
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Number of contact frames ignored before acknowledging the
+ start of activity (activating touch).
+
+
+What: /sys/bus/hid/drivers/ntrig/<dev>/decativate_slack
+Date: May, 2010
+KernelVersion: 2.6.35
+Contact: linux-input@vger.kernel.org
+Description:
+ (RW) Number of empty (no contact) frames ignored before
+ acknowledging the end of activity (deactivating touch).
+
+ When the last finger is removed from the device, it sends a
+ number of empty frames. By holding off on deactivation for a few
+ frames false erroneous disconnects can be tolerated, where the
+ sensor may mistakenly not detect a finger that is still present.
+
+
+What: /sys/bus/hid/drivers/ntrig/<dev>/activation_width
+What: /sys/bus/hid/drivers/ntrig/<dev>/activation_height
+Date: May, 2010
+KernelVersion: 2.6.35
+Contact: linux-input@vger.kernel.org
+Description:
+ Threholds to override activation slack.
+
+ activation_width: (RW) Width threshold to immediately
+ start processing touch events.
+
+ activation_height: (RW) Height threshold to immediately
+ start processing touch events.
+
+
+What: /sys/bus/hid/drivers/ntrig/<dev>/min_width
+What: /sys/bus/hid/drivers/ntrig/<dev>/min_height
+Date: May, 2010
+KernelVersion: 2.6.35
+Contact: linux-input@vger.kernel.org
+Description:
+ Minimum size contact accepted.
+
+ min_width: (RW) Minimum touch contact width to decide
+ activation and activity.
+
+ min_height: (RW) Minimum touch contact height to decide
+ activation and activity.
+
+
+What: /sys/bus/hid/drivers/ntrig/<dev>/sensor_physical_width
+What: /sys/bus/hid/drivers/ntrig/<dev>/sensor_physical_height
+Date: May, 2010
+KernelVersion: 2.6.35
+Contact: linux-input@vger.kernel.org
+Description:
+ (RO) These are internal ranges not used for normal events but
+ useful for tuning.
+
+
+What: /sys/bus/hid/drivers/ntrig/<dev>/sensor_logical_width
+What: /sys/bus/hid/drivers/ntrig/<dev>/sensor_logical_height
+Date: May, 2010
+KernelVersion: 2.6.35
+Contact: linux-input@vger.kernel.org
+Description:
+ (RO) The range for positions reported during activity.
diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI/testing/sysfs-driver-ufs
new file mode 100644
index 000000000000..016724ec26d5
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-ufs
@@ -0,0 +1,885 @@
+What: /sys/bus/*/drivers/ufshcd/*/auto_hibern8
+Date: March 2018
+Contact: linux-scsi@vger.kernel.org
+Description:
+ This file contains the auto-hibernate idle timer setting of a
+ UFS host controller. A value of '0' means auto-hibernate is not
+ enabled. Otherwise the value is the number of microseconds of
+ idle time before the UFS host controller will autonomously put
+ the link into hibernate state. That will save power at the
+ expense of increased latency. Note that the hardware supports
+ 10-bit values with a power-of-ten multiplier which allows a
+ maximum value of 102300000. Refer to the UFS Host Controller
+ Interface specification for more details.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_type
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the device type. This is one of the UFS
+ device descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_class
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the device class. This is one of the UFS
+ device descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_sub_class
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the UFS storage subclass. This is one of
+ the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/protocol
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the protocol supported by an UFS device.
+ This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/number_of_luns
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows number of logical units. This is one of
+ the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/number_of_wluns
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows number of well known logical units.
+ This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/boot_enable
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows value that indicates whether the device is
+ enabled for boot. This is one of the UFS device descriptor
+ parameters. The full information about the descriptor could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/descriptor_access_enable
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows value that indicates whether the device
+ descriptor could be read after partial initialization phase
+ of the boot sequence. This is one of the UFS device descriptor
+ parameters. The full information about the descriptor could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/initial_power_mode
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows value that defines the power mode after
+ device initialization or hardware reset. This is one of
+ the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/high_priority_lun
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the high priority lun. This is one of
+ the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/secure_removal_type
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the secure removal type. This is one of
+ the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/support_security_lun
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether the security lun is supported.
+ This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/bkops_termination_latency
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the background operations termination
+ latency. This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/initial_active_icc_level
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the initial active ICC level. This is one
+ of the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/specification_version
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the specification version. This is one
+ of the UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/manufacturing_date
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the manufacturing date in BCD format.
+ This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/manufacturer_id
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the manufacturee ID. This is one of the
+ UFS device descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/rtt_capability
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum number of outstanding RTTs
+ supported by the device. This is one of the UFS device
+ descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/rtc_update
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the frequency and method of the realtime
+ clock update. This is one of the UFS device descriptor
+ parameters. The full information about the descriptor
+ could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/ufs_features
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows which features are supported by the device.
+ This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be
+ found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/ffu_timeout
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the FFU timeout. This is one of the
+ UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/queue_depth
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the device queue depth. This is one of the
+ UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/device_version
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the device version. This is one of the
+ UFS device descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/number_of_secure_wpa
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows number of secure write protect areas
+ supported by the device. This is one of the UFS device
+ descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/psa_max_data_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum amount of data that may be
+ written during the pre-soldering phase of the PSA flow.
+ This is one of the UFS device descriptor parameters.
+ The full information about the descriptor could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/device_descriptor/psa_state_timeout
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the command maximum timeout for a change
+ in PSA state. This is one of the UFS device descriptor
+ parameters. The full information about the descriptor could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/interconnect_descriptor/unipro_version
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the MIPI UniPro version number in BCD format.
+ This is one of the UFS interconnect descriptor parameters.
+ The full information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/interconnect_descriptor/mphy_version
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the MIPI M-PHY version number in BCD format.
+ This is one of the UFS interconnect descriptor parameters.
+ The full information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/raw_device_capacity
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the total memory quantity available to
+ the user to configure the device logical units. This is one
+ of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_number_of_luns
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum number of logical units
+ supported by the UFS device. This is one of the UFS
+ geometry descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/segment_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the segment size. This is one of the UFS
+ geometry descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/allocation_unit_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the allocation unit size. This is one of
+ the UFS geometry descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/min_addressable_block_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the minimum addressable block size. This
+ is one of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at UFS
+ specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/optimal_read_block_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the optimal read block size. This is one
+ of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at UFS
+ specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/optimal_write_block_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the optimal write block size. This is one
+ of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at UFS
+ specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_in_buffer_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum data-in buffer size. This
+ is one of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at UFS
+ specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_out_buffer_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum data-out buffer size. This
+ is one of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at UFS
+ specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/rpmb_rw_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum number of RPMB frames allowed
+ in Security Protocol In/Out. This is one of the UFS geometry
+ descriptor parameters. The full information about the
+ descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/dyn_capacity_resource_policy
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the dynamic capacity resource policy. This
+ is one of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/data_ordering
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows support for out-of-order data transfer.
+ This is one of the UFS geometry descriptor parameters.
+ The full information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/max_number_of_contexts
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows maximum available number of contexts which
+ are supported by the device. This is one of the UFS geometry
+ descriptor parameters. The full information about the
+ descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/sys_data_tag_unit_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows system data tag unit size. This is one of
+ the UFS geometry descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/sys_data_tag_resource_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows maximum storage area size allocated by
+ the device to handle system data by the tagging mechanism.
+ This is one of the UFS geometry descriptor parameters.
+ The full information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/secure_removal_types
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows supported secure removal types. This is
+ one of the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/memory_types
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows supported memory types. This is one of
+ the UFS geometry descriptor parameters. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/*_memory_max_alloc_units
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum number of allocation units for
+ different memory types (system code, non persistent,
+ enhanced type 1-4). This is one of the UFS geometry
+ descriptor parameters. The full information about the
+ descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/geometry_descriptor/*_memory_capacity_adjustment_factor
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the memory capacity adjustment factor for
+ different memory types (system code, non persistent,
+ enhanced type 1-4). This is one of the UFS geometry
+ descriptor parameters. The full information about the
+ descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/health_descriptor/eol_info
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows preend of life information. This is one
+ of the UFS health descriptor parameters. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/health_descriptor/life_time_estimation_a
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows indication of the device life time
+ (method a). This is one of the UFS health descriptor
+ parameters. The full information about the descriptor
+ could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/health_descriptor/life_time_estimation_b
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows indication of the device life time
+ (method b). This is one of the UFS health descriptor
+ parameters. The full information about the descriptor
+ could be found at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/power_descriptor/active_icc_levels_vcc*
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows maximum VCC, VCCQ and VCCQ2 value for
+ active ICC levels from 0 to 15. This is one of the UFS
+ power descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/manufacturer_name
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file contains a device manufactureer name string.
+ The full information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/product_name
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file contains a product name string. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/oem_id
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file contains a OEM ID string. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/serial_number
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file contains a device serial number string. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/string_descriptors/product_revision
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file contains a product revision string. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/boot_lun_id
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows boot LUN information. This is one of
+ the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/lun_write_protect
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows LUN write protection status. This is one of
+ the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/lun_queue_depth
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows LUN queue depth. This is one of the UFS
+ unit descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/psa_sensitive
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows PSA sensitivity. This is one of the UFS
+ unit descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/lun_memory_type
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows LUN memory type. This is one of the UFS
+ unit descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/data_reliability
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file defines the device behavior when a power failure
+ occurs during a write operation. This is one of the UFS
+ unit descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/logical_block_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the size of addressable logical blocks
+ (calculated as an exponent with base 2). This is one of
+ the UFS unit descriptor parameters. The full information about
+ the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/logical_block_count
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows total number of addressable logical blocks.
+ This is one of the UFS unit descriptor parameters. The full
+ information about the descriptor could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/erase_block_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the erase block size. This is one of
+ the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/provisioning_type
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the thin provisioning type. This is one of
+ the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/physical_memory_resourse_count
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the total physical memory resources. This is
+ one of the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/context_capabilities
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the context capabilities. This is one of
+ the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/class/scsi_device/*/device/unit_descriptor/large_unit_granularity
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the granularity of the LUN. This is one of
+ the UFS unit descriptor parameters. The full information
+ about the descriptor could be found at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/device_init
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the device init status. The full information
+ about the flag could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/permanent_wpe
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether permanent write protection is enabled.
+ The full information about the flag could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/power_on_wpe
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether write protection is enabled on all
+ logical units configured as power on write protected. The
+ full information about the flag could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/bkops_enable
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether the device background operations are
+ enabled. The full information about the flag could be
+ found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/life_span_mode_enable
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether the device life span mode is enabled.
+ The full information about the flag could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/phy_resource_removal
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether physical resource removal is enable.
+ The full information about the flag could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/busy_rtc
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether the device is executing internal
+ operation related to real time clock. The full information
+ about the flag could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/flags/disable_fw_update
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether the device FW update is permanently
+ disabled. The full information about the flag could be found
+ at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/boot_lun_enabled
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the boot lun enabled UFS device attribute.
+ The full information about the attribute could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/current_power_mode
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the current power mode UFS device attribute.
+ The full information about the attribute could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/active_icc_level
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the active icc level UFS device attribute.
+ The full information about the attribute could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/ooo_data_enabled
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the out of order data transfer enabled UFS
+ device attribute. The full information about the attribute
+ could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/bkops_status
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the background operations status UFS device
+ attribute. The full information about the attribute could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/purge_status
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the purge operation status UFS device
+ attribute. The full information about the attribute could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/max_data_in_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum data size in a DATA IN
+ UPIU. The full information about the attribute could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/max_data_out_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the maximum number of bytes that can be
+ requested with a READY TO TRANSFER UPIU. The full information
+ about the attribute could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/reference_clock_frequency
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the reference clock frequency UFS device
+ attribute. The full information about the attribute could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/configuration_descriptor_lock
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows whether the configuration descriptor is locked.
+ The full information about the attribute could be found at
+ UFS specifications 2.1. The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/max_number_of_rtt
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the maximum current number of
+ outstanding RTTs in device that is allowed. The full
+ information about the attribute could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/exception_event_control
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the exception event control UFS device
+ attribute. The full information about the attribute could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/exception_event_status
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the exception event status UFS device
+ attribute. The full information about the attribute could
+ be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/ffu_status
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file provides the ffu status UFS device attribute.
+ The full information about the attribute could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/psa_state
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file show the PSA feature status. The full information
+ about the attribute could be found at UFS specifications 2.1.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/attributes/psa_data_size
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the amount of data that the host plans to
+ load to all logical units in pre-soldering state.
+ The full information about the attribute could be found at
+ UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/class/scsi_device/*/device/dyn_cap_needed
+Date: February 2018
+Contact: Stanislav Nijnikov <stanislav.nijnikov@wdc.com>
+Description: This file shows the The amount of physical memory needed
+ to be removed from the physical memory resources pool of
+ the particular logical unit. The full information about
+ the attribute could be found at UFS specifications 2.1.
+ The file is read only.
+
+
+What: /sys/bus/platform/drivers/ufshcd/*/rpm_lvl
+Date: September 2014
+Contact: Subhash Jadavani <subhashj@codeaurora.org>
+Description: This entry could be used to set or show the UFS device
+ runtime power management level. The current driver
+ implementation supports 6 levels with next target states:
+ 0 - an UFS device will stay active, an UIC link will
+ stay active
+ 1 - an UFS device will stay active, an UIC link will
+ hibernate
+ 2 - an UFS device will moved to sleep, an UIC link will
+ stay active
+ 3 - an UFS device will moved to sleep, an UIC link will
+ hibernate
+ 4 - an UFS device will be powered off, an UIC link will
+ hibernate
+ 5 - an UFS device will be powered off, an UIC link will
+ be powered off
+
+What: /sys/bus/platform/drivers/ufshcd/*/rpm_target_dev_state
+Date: February 2018
+Contact: Subhash Jadavani <subhashj@codeaurora.org>
+Description: This entry shows the target power mode of an UFS device
+ for the chosen runtime power management level.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/rpm_target_link_state
+Date: February 2018
+Contact: Subhash Jadavani <subhashj@codeaurora.org>
+Description: This entry shows the target state of an UFS UIC link
+ for the chosen runtime power management level.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/spm_lvl
+Date: September 2014
+Contact: Subhash Jadavani <subhashj@codeaurora.org>
+Description: This entry could be used to set or show the UFS device
+ system power management level. The current driver
+ implementation supports 6 levels with next target states:
+ 0 - an UFS device will stay active, an UIC link will
+ stay active
+ 1 - an UFS device will stay active, an UIC link will
+ hibernate
+ 2 - an UFS device will moved to sleep, an UIC link will
+ stay active
+ 3 - an UFS device will moved to sleep, an UIC link will
+ hibernate
+ 4 - an UFS device will be powered off, an UIC link will
+ hibernate
+ 5 - an UFS device will be powered off, an UIC link will
+ be powered off
+
+What: /sys/bus/platform/drivers/ufshcd/*/spm_target_dev_state
+Date: February 2018
+Contact: Subhash Jadavani <subhashj@codeaurora.org>
+Description: This entry shows the target power mode of an UFS device
+ for the chosen system power management level.
+ The file is read only.
+
+What: /sys/bus/platform/drivers/ufshcd/*/spm_target_link_state
+Date: February 2018
+Contact: Subhash Jadavani <subhashj@codeaurora.org>
+Description: This entry shows the target state of an UFS UIC link
+ for the chosen system power management level.
+ The file is read only.
diff --git a/Documentation/ABI/testing/sysfs-fs-f2fs b/Documentation/ABI/testing/sysfs-fs-f2fs
index d870b5514d15..540553c933b6 100644
--- a/Documentation/ABI/testing/sysfs-fs-f2fs
+++ b/Documentation/ABI/testing/sysfs-fs-f2fs
@@ -192,3 +192,14 @@ Date: November 2017
Contact: "Sheng Yong" <shengyong1@huawei.com>
Description:
Controls readahead inode block in readdir.
+
+What: /sys/fs/f2fs/<disk>/extension_list
+Date: Feburary 2018
+Contact: "Chao Yu" <yuchao0@huawei.com>
+Description:
+ Used to control configure extension list:
+ - Query: cat /sys/fs/f2fs/<disk>/extension_list
+ - Add: echo '[h/c]extension' > /sys/fs/f2fs/<disk>/extension_list
+ - Del: echo '[h/c]!extension' > /sys/fs/f2fs/<disk>/extension_list
+ - [h] means add/del hot file extension
+ - [c] means add/del cold file extension
diff --git a/Documentation/ABI/testing/sysfs-kernel-irq b/Documentation/ABI/testing/sysfs-kernel-irq
index eb074b100986..8910d0c4bcd8 100644
--- a/Documentation/ABI/testing/sysfs-kernel-irq
+++ b/Documentation/ABI/testing/sysfs-kernel-irq
@@ -51,3 +51,10 @@ Date: September 2016
KernelVersion: 4.9
Contact: Craig Gallek <kraig@google.com>
Description: The type of the interrupt. Either the string 'level' or 'edge'.
+
+What: /sys/kernel/irq/<irq>/wakeup
+Date: March 2018
+KernelVersion: 4.17
+Contact: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Description: The wakeup state of the interrupt. Either the string
+ 'enabled' or 'disabled'.
diff --git a/Documentation/ABI/testing/sysfs-power b/Documentation/ABI/testing/sysfs-power
index 1e0d1dac706b..2f813d644c69 100644
--- a/Documentation/ABI/testing/sysfs-power
+++ b/Documentation/ABI/testing/sysfs-power
@@ -287,3 +287,17 @@ Description:
Writing a "1" to this file enables the debug messages and
writing a "0" (default) to it disables them. Reads from
this file return the current value.
+
+What: /sys/power/resume_offset
+Date: April 2018
+Contact: Mario Limonciello <mario.limonciello@dell.com>
+Description:
+ This file is used for telling the kernel an offset into a disk
+ to use when hibernating the system such as with a swap file.
+
+ Reads from this file will display the current offset
+ the kernel will be using on the next hibernation
+ attempt.
+
+ Using this sysfs file will override any values that were
+ set using the kernel command line for disk offset. \ No newline at end of file
diff --git a/Documentation/admin-guide/README.rst b/Documentation/admin-guide/README.rst
index af5a437198d0..02caa7efd5ef 100644
--- a/Documentation/admin-guide/README.rst
+++ b/Documentation/admin-guide/README.rst
@@ -26,8 +26,8 @@ On what hardware does it run?
Although originally developed first for 32-bit x86-based PCs (386 or higher),
today Linux also runs on (at least) the Compaq Alpha AXP, Sun SPARC and
UltraSPARC, Motorola 68000, PowerPC, PowerPC64, ARM, Hitachi SuperH, Cell,
- IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64, AXIS CRIS,
- Xtensa, Tilera TILE, ARC and Renesas M32R architectures.
+ IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64 Xtensa, and
+ ARC architectures.
Linux is easily portable to most general-purpose 32- or 64-bit architectures
as long as they have a paged memory management unit (PMMU) and a port of the
@@ -218,6 +218,13 @@ Configuring the kernel
"make localyesconfig" Similar to localmodconfig, except it will convert
all module options to built in (=y) options.
+ "make kvmconfig" Enable additional options for kvm guest kernel support.
+
+ "make xenconfig" Enable additional options for xen dom0 guest kernel
+ support.
+
+ "make tinyconfig" Configure the tiniest possible kernel.
+
You can find more information on using the Linux kernel config tools
in Documentation/kbuild/kconfig.txt.
diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentation/admin-guide/kernel-parameters.rst
index 7242cbda15dd..b8d0bc07ed0a 100644
--- a/Documentation/admin-guide/kernel-parameters.rst
+++ b/Documentation/admin-guide/kernel-parameters.rst
@@ -89,7 +89,6 @@ parameter is applicable::
APM Advanced Power Management support is enabled.
ARM ARM architecture is enabled.
AX25 Appropriate AX.25 support is enabled.
- BLACKFIN Blackfin architecture is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
DRM Direct Rendering Management support is enabled.
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 1d1d53f85ddd..11fc28ecdb6d 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -389,15 +389,15 @@
Use software keyboard repeat
audit= [KNL] Enable the audit sub-system
- Format: { "0" | "1" } (0 = disabled, 1 = enabled)
- 0 - kernel audit is disabled and can not be enabled
- until the next reboot
+ Format: { "0" | "1" | "off" | "on" }
+ 0 | off - kernel audit is disabled and can not be
+ enabled until the next reboot
unset - kernel audit is initialized but disabled and
will be fully enabled by the userspace auditd.
- 1 - kernel audit is initialized and partially enabled,
- storing at most audit_backlog_limit messages in
- RAM until it is fully enabled by the userspace
- auditd.
+ 1 | on - kernel audit is initialized and partially
+ enabled, storing at most audit_backlog_limit
+ messages in RAM until it is fully enabled by the
+ userspace auditd.
Default: unset
audit_backlog_limit= [KNL] Set the audit queue size limit.
@@ -1025,7 +1025,7 @@
address. The serial port must already be setup
and configured. Options are not yet supported.
- earlyprintk= [X86,SH,BLACKFIN,ARM,M68k,S390]
+ earlyprintk= [X86,SH,ARM,M68k,S390]
earlyprintk=vga
earlyprintk=efi
earlyprintk=sclp
@@ -1347,10 +1347,6 @@
If specified, z/VM IUCV HVC accepts connections
from listed z/VM user IDs only.
- hwthread_map= [METAG] Comma-separated list of Linux cpu id to
- hardware thread id mappings.
- Format: <cpu>:<hwthread>
-
keep_bootcon [KNL]
Do not unregister boot console at start. This is only
useful for debugging when something happens in the window
@@ -1525,7 +1521,8 @@
ima_policy= [IMA]
The builtin policies to load during IMA setup.
- Format: "tcb | appraise_tcb | secure_boot"
+ Format: "tcb | appraise_tcb | secure_boot |
+ fail_securely"
The "tcb" policy measures all programs exec'd, files
mmap'd for exec, and all files opened with the read
@@ -1540,6 +1537,11 @@
of files (eg. kexec kernel image, kernel modules,
firmware, policy, etc) based on file signatures.
+ The "fail_securely" policy forces file signature
+ verification failure also on privileged mounted
+ filesystems with the SB_I_UNVERIFIABLE_SIGNATURE
+ flag.
+
ima_tcb [IMA] Deprecated. Use ima_policy= instead.
Load a policy which meets the needs of the Trusted
Computing Base. This means IMA will measure all
@@ -1743,6 +1745,14 @@
of a GICv2 controller even if the memory range
exposed by the device tree is too small.
+ irqchip.gicv3_nolpi=
+ [ARM, ARM64]
+ Force the kernel to ignore the availability of
+ LPIs (and by consequence ITSs). Intended for system
+ that use the kernel as a bootloader, and thus want
+ to let secondary kernels in charge of setting up
+ LPIs.
+
irqfixup [HW]
When an interrupt is not handled search all handlers
for it. Intended to get systems with badly broken
@@ -1766,6 +1776,17 @@
nohz
Disable the tick when a single task runs.
+
+ A residual 1Hz tick is offloaded to workqueues, which you
+ need to affine to housekeeping through the global
+ workqueue's affinity configured via the
+ /sys/devices/virtual/workqueue/cpumask sysfs file, or
+ by using the 'domain' flag described below.
+
+ NOTE: by default the global workqueue runs on all CPUs,
+ so to protect individual CPUs the 'cpumask' file has to
+ be configured manually after bootup.
+
domain
Isolate from the general SMP balancing and scheduling
algorithms. Note that performing domain isolation this way
@@ -1825,30 +1846,29 @@
keepinitrd [HW,ARM]
kernelcore= [KNL,X86,IA-64,PPC]
- Format: nn[KMGTPE] | "mirror"
- This parameter
- specifies the amount of memory usable by the kernel
- for non-movable allocations. The requested amount is
- spread evenly throughout all nodes in the system. The
- remaining memory in each node is used for Movable
- pages. In the event, a node is too small to have both
- kernelcore and Movable pages, kernelcore pages will
- take priority and other nodes will have a larger number
- of Movable pages. The Movable zone is used for the
- allocation of pages that may be reclaimed or moved
- by the page migration subsystem. This means that
- HugeTLB pages may not be allocated from this zone.
- Note that allocations like PTEs-from-HighMem still
- use the HighMem zone if it exists, and the Normal
+ Format: nn[KMGTPE] | nn% | "mirror"
+ This parameter specifies the amount of memory usable by
+ the kernel for non-movable allocations. The requested
+ amount is spread evenly throughout all nodes in the
+ system as ZONE_NORMAL. The remaining memory is used for
+ movable memory in its own zone, ZONE_MOVABLE. In the
+ event, a node is too small to have both ZONE_NORMAL and
+ ZONE_MOVABLE, kernelcore memory will take priority and
+ other nodes will have a larger ZONE_MOVABLE.
+
+ ZONE_MOVABLE is used for the allocation of pages that
+ may be reclaimed or moved by the page migration
+ subsystem. Note that allocations like PTEs-from-HighMem
+ still use the HighMem zone if it exists, and the Normal
zone if it does not.
- Instead of specifying the amount of memory (nn[KMGTPE]),
- you can specify "mirror" option. In case "mirror"
+ It is possible to specify the exact amount of memory in
+ the form of "nn[KMGTPE]", a percentage of total system
+ memory in the form of "nn%", or "mirror". If "mirror"
option is specified, mirrored (reliable) memory is used
for non-movable allocations and remaining memory is used
- for Movable pages. nn[KMGTPE] and "mirror" are exclusive,
- so you can NOT specify nn[KMGTPE] and "mirror" at the same
- time.
+ for Movable pages. "nn[KMGTPE]", "nn%", and "mirror"
+ are exclusive, so you cannot specify multiple forms.
kgdbdbgp= [KGDB,HW] kgdb over EHCI usb debug port.
Format: <Controller#>[,poll interval]
@@ -1887,6 +1907,9 @@
kvm.ignore_msrs=[KVM] Ignore guest accesses to unhandled MSRs.
Default is 0 (don't ignore, but inject #GP)
+ kvm.enable_vmware_backdoor=[KVM] Support VMware backdoor PV interface.
+ Default is false (don't support).
+
kvm.mmu_audit= [KVM] This is a R/W parameter which allows audit
KVM MMU at runtime.
Default is 0 (off)
@@ -2237,6 +2260,15 @@
The memory region may be marked as e820 type 12 (0xc)
and is NVDIMM or ADR memory.
+ memmap=<size>%<offset>-<oldtype>+<newtype>
+ [KNL,ACPI] Convert memory within the specified region
+ from <oldtype> to <newtype>. If "-<oldtype>" is left
+ out, the whole region will be marked as <newtype>,
+ even if previously unavailable. If "+<newtype>" is left
+ out, matching memory will be removed. Types are
+ specified as e820 types, e.g., 1 = RAM, 2 = reserved,
+ 3 = ACPI, 12 = PRAM.
+
memory_corruption_check=0/1 [X86]
Some BIOSes seem to corrupt the first 64k of
memory when doing things like suspend/resume.
@@ -2353,13 +2385,14 @@
mousedev.yres= [MOUSE] Vertical screen resolution, used for devices
reporting absolute coordinates, such as tablets
- movablecore=nn[KMG] [KNL,X86,IA-64,PPC] This parameter
- is similar to kernelcore except it specifies the
- amount of memory used for migratable allocations.
- If both kernelcore and movablecore is specified,
- then kernelcore will be at *least* the specified
- value but may be more. If movablecore on its own
- is specified, the administrator must be careful
+ movablecore= [KNL,X86,IA-64,PPC]
+ Format: nn[KMGTPE] | nn%
+ This parameter is the complement to kernelcore=, it
+ specifies the amount of memory used for migratable
+ allocations. If both kernelcore and movablecore is
+ specified, then kernelcore will be at *least* the
+ specified value but may be more. If movablecore on its
+ own is specified, the administrator must be careful
that the amount of memory usable for all allocations
is not too small.
@@ -3130,18 +3163,13 @@
force Enable ASPM even on devices that claim not to support it.
WARNING: Forcing ASPM on may cause system lockups.
- pcie_hp= [PCIE] PCI Express Hotplug driver options:
- nomsi Do not use MSI for PCI Express Native Hotplug (this
- makes all PCIe ports use INTx for hotplug services).
-
- pcie_ports= [PCIE] PCIe ports handling:
- auto Ask the BIOS whether or not to use native PCIe services
- associated with PCIe ports (PME, hot-plug, AER). Use
- them only if that is allowed by the BIOS.
- native Use native PCIe services associated with PCIe ports
- unconditionally.
- compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe
- ports driver.
+ pcie_ports= [PCIE] PCIe port services handling:
+ native Use native PCIe services (PME, AER, DPC, PCIe hotplug)
+ even if the platform doesn't give the OS permission to
+ use them. This may cause conflicts if the platform
+ also tries to use these services.
+ compat Disable native PCIe services (PME, AER, DPC, PCIe
+ hotplug).
pcie_port_pm= [PCIE] PCIe port power management handling:
off Disable power management of all PCIe ports
@@ -4368,12 +4396,73 @@
usbcore.nousb [USB] Disable the USB subsystem
+ usbcore.quirks=
+ [USB] A list of quirk entries to augment the built-in
+ usb core quirk list. List entries are separated by
+ commas. Each entry has the form
+ VendorID:ProductID:Flags. The IDs are 4-digit hex
+ numbers and Flags is a set of letters. Each letter
+ will change the built-in quirk; setting it if it is
+ clear and clearing it if it is set. The letters have
+ the following meanings:
+ a = USB_QUIRK_STRING_FETCH_255 (string
+ descriptors must not be fetched using
+ a 255-byte read);
+ b = USB_QUIRK_RESET_RESUME (device can't resume
+ correctly so reset it instead);
+ c = USB_QUIRK_NO_SET_INTF (device can't handle
+ Set-Interface requests);
+ d = USB_QUIRK_CONFIG_INTF_STRINGS (device can't
+ handle its Configuration or Interface
+ strings);
+ e = USB_QUIRK_RESET (device can't be reset
+ (e.g morph devices), don't use reset);
+ f = USB_QUIRK_HONOR_BNUMINTERFACES (device has
+ more interface descriptions than the
+ bNumInterfaces count, and can't handle
+ talking to these interfaces);
+ g = USB_QUIRK_DELAY_INIT (device needs a pause
+ during initialization, after we read
+ the device descriptor);
+ h = USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL (For
+ high speed and super speed interrupt
+ endpoints, the USB 2.0 and USB 3.0 spec
+ require the interval in microframes (1
+ microframe = 125 microseconds) to be
+ calculated as interval = 2 ^
+ (bInterval-1).
+ Devices with this quirk report their
+ bInterval as the result of this
+ calculation instead of the exponent
+ variable used in the calculation);
+ i = USB_QUIRK_DEVICE_QUALIFIER (device can't
+ handle device_qualifier descriptor
+ requests);
+ j = USB_QUIRK_IGNORE_REMOTE_WAKEUP (device
+ generates spurious wakeup, ignore
+ remote wakeup capability);
+ k = USB_QUIRK_NO_LPM (device can't handle Link
+ Power Management);
+ l = USB_QUIRK_LINEAR_FRAME_INTR_BINTERVAL
+ (Device reports its bInterval as linear
+ frames instead of the USB 2.0
+ calculation);
+ m = USB_QUIRK_DISCONNECT_SUSPEND (Device needs
+ to be disconnected before suspend to
+ prevent spurious wakeup);
+ n = USB_QUIRK_DELAY_CTRL_MSG (Device needs a
+ pause after every control message);
+ Example: quirks=0781:5580:bk,0a5c:5834:gij
+
usbhid.mousepoll=
[USBHID] The interval which mice are to be polled at.
usbhid.jspoll=
[USBHID] The interval which joysticks are to be polled at.
+ usbhid.kbpoll=
+ [USBHID] The interval which keyboards are to be polled at.
+
usb-storage.delay_use=
[UMS] The delay in seconds before a new device is
scanned for Logical Units (default 1).
diff --git a/Documentation/admin-guide/module-signing.rst b/Documentation/admin-guide/module-signing.rst
index 27e59498b487..f8b584179cff 100644
--- a/Documentation/admin-guide/module-signing.rst
+++ b/Documentation/admin-guide/module-signing.rst
@@ -180,11 +180,11 @@ Public keys in the kernel
=========================
The kernel contains a ring of public keys that can be viewed by root. They're
-in a keyring called ".system_keyring" that can be seen by::
+in a keyring called ".builtin_trusted_keys" that can be seen by::
[root@deneb ~]# cat /proc/keys
...
- 223c7853 I------ 1 perm 1f030000 0 0 keyring .system_keyring: 1
+ 223c7853 I------ 1 perm 1f030000 0 0 keyring .builtin_trusted_keys: 1
302d2d52 I------ 1 perm 1f010000 0 0 asymmetri Fedora kernel signing key: d69a84e6bce3d216b979e9505b3e3ef9a7118079: X509.RSA a7118079 []
...
@@ -197,15 +197,15 @@ add those in also (e.g. from the UEFI key database).
Finally, it is possible to add additional public keys by doing::
- keyctl padd asymmetric "" [.system_keyring-ID] <[key-file]
+ keyctl padd asymmetric "" [.builtin_trusted_keys-ID] <[key-file]
e.g.::
keyctl padd asymmetric "" 0x223c7853 <my_public_key.x509
Note, however, that the kernel will only permit keys to be added to
-``.system_keyring _if_`` the new key's X.509 wrapper is validly signed by a key
-that is already resident in the .system_keyring at the time the key was added.
+``.builtin_trusted_keys`` **if** the new key's X.509 wrapper is validly signed by a key
+that is already resident in the ``.builtin_trusted_keys`` at the time the key was added.
========================
diff --git a/Documentation/admin-guide/security-bugs.rst b/Documentation/admin-guide/security-bugs.rst
index 47574b382d75..30491d91e93d 100644
--- a/Documentation/admin-guide/security-bugs.rst
+++ b/Documentation/admin-guide/security-bugs.rst
@@ -29,18 +29,20 @@ made public.
Disclosure
----------
-The goal of the Linux kernel security team is to work with the
-bug submitter to bug resolution as well as disclosure. We prefer
-to fully disclose the bug as soon as possible. It is reasonable to
-delay disclosure when the bug or the fix is not yet fully understood,
-the solution is not well-tested or for vendor coordination. However, we
-expect these delays to be short, measurable in days, not weeks or months.
-A disclosure date is negotiated by the security team working with the
-bug submitter as well as vendors. However, the kernel security team
-holds the final say when setting a disclosure date. The timeframe for
-disclosure is from immediate (esp. if it's already publicly known)
+The goal of the Linux kernel security team is to work with the bug
+submitter to understand and fix the bug. We prefer to publish the fix as
+soon as possible, but try to avoid public discussion of the bug itself
+and leave that to others.
+
+Publishing the fix may be delayed when the bug or the fix is not yet
+fully understood, the solution is not well-tested or for vendor
+coordination. However, we expect these delays to be short, measurable in
+days, not weeks or months. A release date is negotiated by the security
+team working with the bug submitter as well as vendors. However, the
+kernel security team holds the final say when setting a timeframe. The
+timeframe varies from immediate (esp. if it's already publicly known bug)
to a few weeks. As a basic default policy, we expect report date to
-disclosure date to be on the order of 7 days.
+release date to be on the order of 7 days.
Coordination
------------
diff --git a/Documentation/admin-guide/tainted-kernels.rst b/Documentation/admin-guide/tainted-kernels.rst
index 1df03b5cb02f..28a869c509a0 100644
--- a/Documentation/admin-guide/tainted-kernels.rst
+++ b/Documentation/admin-guide/tainted-kernels.rst
@@ -6,34 +6,34 @@ counter. This indicates that the kernel has been tainted by some
mechanism. The string is followed by a series of position-sensitive
characters, each representing a particular tainted value.
- 1) 'G' if all modules loaded have a GPL or compatible license, 'P' if
+ 1) ``G`` if all modules loaded have a GPL or compatible license, ``P`` if
any proprietary module has been loaded. Modules without a
MODULE_LICENSE or with a MODULE_LICENSE that is not recognised by
insmod as GPL compatible are assumed to be proprietary.
- 2) ``F`` if any module was force loaded by ``insmod -f``, ``' '`` if all
+ 2) ``F`` if any module was force loaded by ``insmod -f``, ``' '`` if all
modules were loaded normally.
- 3) ``S`` if the oops occurred on an SMP kernel running on hardware that
+ 3) ``S`` if the oops occurred on an SMP kernel running on hardware that
hasn't been certified as safe to run multiprocessor.
Currently this occurs only on various Athlons that are not
SMP capable.
- 4) ``R`` if a module was force unloaded by ``rmmod -f``, ``' '`` if all
+ 4) ``R`` if a module was force unloaded by ``rmmod -f``, ``' '`` if all
modules were unloaded normally.
- 5) ``M`` if any processor has reported a Machine Check Exception,
+ 5) ``M`` if any processor has reported a Machine Check Exception,
``' '`` if no Machine Check Exceptions have occurred.
- 6) ``B`` if a page-release function has found a bad page reference or
+ 6) ``B`` if a page-release function has found a bad page reference or
some unexpected page flags.
- 7) ``U`` if a user or user application specifically requested that the
+ 7) ``U`` if a user or user application specifically requested that the
Tainted flag be set, ``' '`` otherwise.
- 8) ``D`` if the kernel has died recently, i.e. there was an OOPS or BUG.
+ 8) ``D`` if the kernel has died recently, i.e. there was an OOPS or BUG.
- 9) ``A`` if the ACPI table has been overridden.
+ 9) ``A`` if the ACPI table has been overridden.
10) ``W`` if a warning has previously been issued by the kernel.
(Though some warnings may set more specific taint flags.)
diff --git a/Documentation/admin-guide/thunderbolt.rst b/Documentation/admin-guide/thunderbolt.rst
index 9948ec36a204..35fccba6a9a6 100644
--- a/Documentation/admin-guide/thunderbolt.rst
+++ b/Documentation/admin-guide/thunderbolt.rst
@@ -21,11 +21,11 @@ vulnerable to DMA attacks.
Security levels and how to use them
-----------------------------------
Starting with Intel Falcon Ridge Thunderbolt controller there are 4
-security levels available. The reason for these is the fact that the
-connected devices can be DMA masters and thus read contents of the host
-memory without CPU and OS knowing about it. There are ways to prevent
-this by setting up an IOMMU but it is not always available for various
-reasons.
+security levels available. Intel Titan Ridge added one more security level
+(usbonly). The reason for these is the fact that the connected devices can
+be DMA masters and thus read contents of the host memory without CPU and OS
+knowing about it. There are ways to prevent this by setting up an IOMMU but
+it is not always available for various reasons.
The security levels are as follows:
@@ -52,6 +52,11 @@ The security levels are as follows:
USB. No PCIe tunneling is done. In BIOS settings this is
typically called *Display Port Only*.
+ usbonly
+ The firmware automatically creates tunnels for the USB controller and
+ Display Port in a dock. All PCIe links downstream of the dock are
+ removed.
+
The current security level can be read from
``/sys/bus/thunderbolt/devices/domainX/security`` where ``domainX`` is
the Thunderbolt domain the host controller manages. There is typically
diff --git a/Documentation/arm/Atmel/README b/Documentation/arm/Atmel/README
deleted file mode 100644
index afb13c15389d..000000000000
--- a/Documentation/arm/Atmel/README
+++ /dev/null
@@ -1,171 +0,0 @@
-ARM Atmel SoCs (aka AT91)
-=========================
-
-
-Introduction
-------------
-This document gives useful information about the ARM Atmel SoCs that are
-currently supported in Linux Mainline (you know, the one on kernel.org).
-
-It is important to note that the Atmel | SMART ARM-based MPU product line is
-historically named "AT91" or "at91" throughout the Linux kernel development
-process even if this product prefix has completely disappeared from the
-official Atmel product name. Anyway, files, directories, git trees,
-git branches/tags and email subject always contain this "at91" sub-string.
-
-
-AT91 SoCs
----------
-Documentation and detailed datasheet for each product are available on
-the Atmel website: http://www.atmel.com.
-
- Flavors:
- * ARM 920 based SoC
- - at91rm9200
- + Datasheet
- http://www.atmel.com/Images/doc1768.pdf
-
- * ARM 926 based SoCs
- - at91sam9260
- + Datasheet
- http://www.atmel.com/Images/doc6221.pdf
-
- - at91sam9xe
- + Datasheet
- http://www.atmel.com/Images/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
-
- - at91sam9261
- + Datasheet
- http://www.atmel.com/Images/doc6062.pdf
-
- - at91sam9263
- + Datasheet
- http://www.atmel.com/Images/Atmel_6249_32-bit-ARM926EJ-S-Microcontroller_SAM9263_Datasheet.pdf
-
- - at91sam9rl
- + Datasheet
- http://www.atmel.com/Images/doc6289.pdf
-
- - at91sam9g20
- + Datasheet
- http://www.atmel.com/Images/doc6384.pdf
-
- - at91sam9g45 family
- - at91sam9g45
- - at91sam9g46
- - at91sam9m10
- - at91sam9m11 (device superset)
- + Datasheet
- http://www.atmel.com/Images/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
-
- - at91sam9x5 family (aka "The 5 series")
- - at91sam9g15
- - at91sam9g25
- - at91sam9g35
- - at91sam9x25
- - at91sam9x35
- + Datasheet (can be considered as covering the whole family)
- http://www.atmel.com/Images/Atmel_11055_32-bit-ARM926EJ-S-Microcontroller_SAM9X35_Datasheet.pdf
-
- - at91sam9n12
- + Datasheet
- http://www.atmel.com/Images/Atmel_11063_32-bit-ARM926EJ-S-Microcontroller_SAM9N12CN11CN12_Datasheet.pdf
-
- * ARM Cortex-A5 based SoCs
- - sama5d3 family
- - sama5d31
- - sama5d33
- - sama5d34
- - sama5d35
- - sama5d36 (device superset)
- + Datasheet
- http://www.atmel.com/Images/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
-
- * ARM Cortex-A5 + NEON based SoCs
- - sama5d4 family
- - sama5d41
- - sama5d42
- - sama5d43
- - sama5d44 (device superset)
- + Datasheet
- http://www.atmel.com/Images/Atmel-11238-32-bit-Cortex-A5-Microcontroller-SAMA5D4_Datasheet.pdf
-
- - sama5d2 family
- - sama5d21
- - sama5d22
- - sama5d23
- - sama5d24
- - sama5d26
- - sama5d27 (device superset)
- - sama5d28 (device superset + environmental monitors)
- + Datasheet
- http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf
-
- * ARM Cortex-M7 MCUs
- - sams70 family
- - sams70j19
- - sams70j20
- - sams70j21
- - sams70n19
- - sams70n20
- - sams70n21
- - sams70q19
- - sams70q20
- - sams70q21
- + Datasheet
- http://www.atmel.com/Images/Atmel-11242-32-bit-Cortex-M7-Microcontroller-SAM-S70Q-SAM-S70N-SAM-S70J_Datasheet.pdf
-
- - samv70 family
- - samv70j19
- - samv70j20
- - samv70n19
- - samv70n20
- - samv70q19
- - samv70q20
- + Datasheet
- http://www.atmel.com/Images/Atmel-11297-32-bit-Cortex-M7-Microcontroller-SAM-V70Q-SAM-V70N-SAM-V70J_Datasheet.pdf
-
- - samv71 family
- - samv71j19
- - samv71j20
- - samv71j21
- - samv71n19
- - samv71n20
- - samv71n21
- - samv71q19
- - samv71q20
- - samv71q21
- + Datasheet
- http://www.atmel.com/Images/Atmel-44003-32-bit-Cortex-M7-Microcontroller-SAM-V71Q-SAM-V71N-SAM-V71J_Datasheet.pdf
-
-Linux kernel information
-------------------------
-Linux kernel mach directory: arch/arm/mach-at91
-MAINTAINERS entry is: "ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES"
-
-
-Device Tree for AT91 SoCs and boards
-------------------------------------
-All AT91 SoCs are converted to Device Tree. Since Linux 3.19, these products
-must use this method to boot the Linux kernel.
-
-Work In Progress statement:
-Device Tree files and Device Tree bindings that apply to AT91 SoCs and boards are
-considered as "Unstable". To be completely clear, any at91 binding can change at
-any time. So, be sure to use a Device Tree Binary and a Kernel Image generated from
-the same source tree.
-Please refer to the Documentation/devicetree/bindings/ABI.txt file for a
-definition of a "Stable" binding/ABI.
-This statement will be removed by AT91 MAINTAINERS when appropriate.
-
-Naming conventions and best practice:
-- SoCs Device Tree Source Include files are named after the official name of
- the product (at91sam9g20.dtsi or sama5d33.dtsi for instance).
-- Device Tree Source Include files (.dtsi) are used to collect common nodes that can be
- shared across SoCs or boards (sama5d3.dtsi or at91sam9x5cm.dtsi for instance).
- When collecting nodes for a particular peripheral or topic, the identifier have to
- be placed at the end of the file name, separated with a "_" (at91sam9x5_can.dtsi
- or sama5d3_gmac.dtsi for example).
-- board Device Tree Source files (.dts) are prefixed by the string "at91-" so
- that they can be identified easily. Note that some files are historical exceptions
- to this rule (sama5d3[13456]ek.dts, usb_a9g20.dts or animeo_ip.dts for example).
diff --git a/Documentation/arm/Microchip/README b/Documentation/arm/Microchip/README
new file mode 100644
index 000000000000..a366f37d38f1
--- /dev/null
+++ b/Documentation/arm/Microchip/README
@@ -0,0 +1,169 @@
+ARM Microchip SoCs (aka AT91)
+=============================
+
+
+Introduction
+------------
+This document gives useful information about the ARM Microchip SoCs that are
+currently supported in Linux Mainline (you know, the one on kernel.org).
+
+It is important to note that the Microchip (previously Atmel) ARM-based MPU
+product line is historically named "AT91" or "at91" throughout the Linux kernel
+development process even if this product prefix has completely disappeared from
+the official Microchip product name. Anyway, files, directories, git trees,
+git branches/tags and email subject always contain this "at91" sub-string.
+
+
+AT91 SoCs
+---------
+Documentation and detailed datasheet for each product are available on
+the Microchip website: http://www.microchip.com.
+
+ Flavors:
+ * ARM 920 based SoC
+ - at91rm9200
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-AT91RM9200_Datasheet.pdf
+
+ * ARM 926 based SoCs
+ - at91sam9260
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9260_Datasheet.pdf
+
+ - at91sam9xe
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
+
+ - at91sam9261
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6062-ARM926EJ-S-Microprocessor-SAM9261_Datasheet.pdf
+
+ - at91sam9263
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6249-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9263_Datasheet.pdf
+
+ - at91sam9rl
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/doc6289.pdf
+
+ - at91sam9g20
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001516A.pdf
+
+ - at91sam9g45 family
+ - at91sam9g45
+ - at91sam9g46
+ - at91sam9m10
+ - at91sam9m11 (device superset)
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
+
+ - at91sam9x5 family (aka "The 5 series")
+ - at91sam9g15
+ - at91sam9g25
+ - at91sam9g35
+ - at91sam9x25
+ - at91sam9x35
+ + Datasheet (can be considered as covering the whole family)
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11055-32-bit-ARM926EJ-S-Microcontroller-SAM9X35_Datasheet.pdf
+
+ - at91sam9n12
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf
+
+ * ARM Cortex-A5 based SoCs
+ - sama5d3 family
+ - sama5d31
+ - sama5d33
+ - sama5d34
+ - sama5d35
+ - sama5d36 (device superset)
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
+
+ * ARM Cortex-A5 + NEON based SoCs
+ - sama5d4 family
+ - sama5d41
+ - sama5d42
+ - sama5d43
+ - sama5d44 (device superset)
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/60001525A.pdf
+
+ - sama5d2 family
+ - sama5d21
+ - sama5d22
+ - sama5d23
+ - sama5d24
+ - sama5d26
+ - sama5d27 (device superset)
+ - sama5d28 (device superset + environmental monitors)
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001476B.pdf
+
+ * ARM Cortex-M7 MCUs
+ - sams70 family
+ - sams70j19
+ - sams70j20
+ - sams70j21
+ - sams70n19
+ - sams70n20
+ - sams70n21
+ - sams70q19
+ - sams70q20
+ - sams70q21
+
+ - samv70 family
+ - samv70j19
+ - samv70j20
+ - samv70n19
+ - samv70n20
+ - samv70q19
+ - samv70q20
+
+ - samv71 family
+ - samv71j19
+ - samv71j20
+ - samv71j21
+ - samv71n19
+ - samv71n20
+ - samv71n21
+ - samv71q19
+ - samv71q20
+ - samv71q21
+
+ + Datasheet
+ http://ww1.microchip.com/downloads/en/DeviceDoc/60001527A.pdf
+
+
+Linux kernel information
+------------------------
+Linux kernel mach directory: arch/arm/mach-at91
+MAINTAINERS entry is: "ARM/Microchip (AT91) SoC support"
+
+
+Device Tree for AT91 SoCs and boards
+------------------------------------
+All AT91 SoCs are converted to Device Tree. Since Linux 3.19, these products
+must use this method to boot the Linux kernel.
+
+Work In Progress statement:
+Device Tree files and Device Tree bindings that apply to AT91 SoCs and boards are
+considered as "Unstable". To be completely clear, any at91 binding can change at
+any time. So, be sure to use a Device Tree Binary and a Kernel Image generated from
+the same source tree.
+Please refer to the Documentation/devicetree/bindings/ABI.txt file for a
+definition of a "Stable" binding/ABI.
+This statement will be removed by AT91 MAINTAINERS when appropriate.
+
+Naming conventions and best practice:
+- SoCs Device Tree Source Include files are named after the official name of
+ the product (at91sam9g20.dtsi or sama5d33.dtsi for instance).
+- Device Tree Source Include files (.dtsi) are used to collect common nodes that can be
+ shared across SoCs or boards (sama5d3.dtsi or at91sam9x5cm.dtsi for instance).
+ When collecting nodes for a particular peripheral or topic, the identifier have to
+ be placed at the end of the file name, separated with a "_" (at91sam9x5_can.dtsi
+ or sama5d3_gmac.dtsi for example).
+- board Device Tree Source files (.dts) are prefixed by the string "at91-" so
+ that they can be identified easily. Note that some files are historical exceptions
+ to this rule (sama5d3[13456]ek.dts, usb_a9g20.dts or animeo_ip.dts for example).
diff --git a/Documentation/arm/Samsung-S3C24XX/S3C2412.txt b/Documentation/arm/Samsung-S3C24XX/S3C2412.txt
index f057876b920b..dc1fd362d3c1 100644
--- a/Documentation/arm/Samsung-S3C24XX/S3C2412.txt
+++ b/Documentation/arm/Samsung-S3C24XX/S3C2412.txt
@@ -46,7 +46,7 @@ NAND
----
The NAND hardware is similar to the S3C2440, and is supported by the
- s3c2410 driver in the drivers/mtd/nand directory.
+ s3c2410 driver in the drivers/mtd/nand/raw directory.
USB Host
diff --git a/Documentation/arm/stm32/overview.rst b/Documentation/arm/stm32/overview.rst
new file mode 100644
index 000000000000..85cfc8410798
--- /dev/null
+++ b/Documentation/arm/stm32/overview.rst
@@ -0,0 +1,34 @@
+========================
+STM32 ARM Linux Overview
+========================
+
+Introduction
+------------
+
+The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
+Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
+ARM Linux.
+
+Configuration
+-------------
+
+For MCUs, use the provided default configuration:
+ make stm32_defconfig
+For MPUs, use multi_v7 configuration:
+ make multi_v7_defconfig
+
+Layout
+------
+
+All the files for multiple machine families are located in the platform code
+contained in arch/arm/mach-stm32
+
+There is a generic board board-dt.c in the mach folder which support
+Flattened Device Tree, which means, it works with any compatible board with
+Device Trees.
+
+:Authors:
+
+- Maxime Coquelin <mcoquelin.stm32@gmail.com>
+- Ludovic Barre <ludovic.barre@st.com>
+- Gerald Baeza <gerald.baeza@st.com>
diff --git a/Documentation/arm/stm32/overview.txt b/Documentation/arm/stm32/overview.txt
deleted file mode 100644
index a03b0357c017..000000000000
--- a/Documentation/arm/stm32/overview.txt
+++ /dev/null
@@ -1,33 +0,0 @@
- STM32 ARM Linux Overview
- ========================
-
-Introduction
-------------
-
- The STMicroelectronics family of Cortex-M based MCUs are supported by the
- 'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
- and STM32F746 (Cortex-M7) are supported.
-
-
-Configuration
--------------
-
- A generic configuration is provided for STM32 family, and can be used as the
- default by
- make stm32_defconfig
-
-Layout
-------
-
- All the files for multiple machine families are located in the platform code
- contained in arch/arm/mach-stm32
-
- There is a generic board board-dt.c in the mach folder which support
- Flattened Device Tree, which means, it works with any compatible board with
- Device Trees.
-
-
-Document Author
----------------
-
- Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/stm32f429-overview.rst b/Documentation/arm/stm32/stm32f429-overview.rst
new file mode 100644
index 000000000000..18feda97f483
--- /dev/null
+++ b/Documentation/arm/stm32/stm32f429-overview.rst
@@ -0,0 +1,26 @@
+STM32F429 Overview
+==================
+
+Introduction
+------------
+
+The STM32F429 is a Cortex-M4 MCU aimed at various applications.
+It features:
+
+- ARM Cortex-M4 up to 180MHz with FPU
+- 2MB internal Flash Memory
+- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
+- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
+- LCD controller & Camera interface
+- Cryptographic processor
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32F429_).
+
+.. _STM32F429: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
+
+:Authors:
+
+Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/stm32f429-overview.txt b/Documentation/arm/stm32/stm32f429-overview.txt
deleted file mode 100644
index 5206822bd8ef..000000000000
--- a/Documentation/arm/stm32/stm32f429-overview.txt
+++ /dev/null
@@ -1,22 +0,0 @@
- STM32F429 Overview
- ==================
-
- Introduction
- ------------
- The STM32F429 is a Cortex-M4 MCU aimed at various applications.
- It features:
- - ARM Cortex-M4 up to 180MHz with FPU
- - 2MB internal Flash Memory
- - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
- - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
- - LCD controller & Camera interface
- - Cryptographic processor
-
- Resources
- ---------
- Datasheet and reference manual are publicly available on ST website:
- - http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
-
- Document Author
- ---------------
- Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/stm32f746-overview.rst b/Documentation/arm/stm32/stm32f746-overview.rst
new file mode 100644
index 000000000000..b5f4b6ce7656
--- /dev/null
+++ b/Documentation/arm/stm32/stm32f746-overview.rst
@@ -0,0 +1,33 @@
+STM32F746 Overview
+==================
+
+Introduction
+------------
+
+The STM32F746 is a Cortex-M7 MCU aimed at various applications.
+It features:
+
+- Cortex-M7 core running up to @216MHz
+- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
+- FMC controller to connect SDRAM, NOR and NAND memories
+- Dual mode QSPI
+- SD/MMC/SDIO support
+- Ethernet controller
+- USB OTFG FS & HS controllers
+- I2C, SPI, CAN busses support
+- Several 16 & 32 bits general purpose timers
+- Serial Audio interface
+- LCD controller
+- HDMI-CEC
+- SPDIFRX
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32F746_).
+
+.. _STM32F746: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
+
+:Authors:
+
+Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arm/stm32/stm32f746-overview.txt b/Documentation/arm/stm32/stm32f746-overview.txt
deleted file mode 100644
index cffd2b1ccd6f..000000000000
--- a/Documentation/arm/stm32/stm32f746-overview.txt
+++ /dev/null
@@ -1,34 +0,0 @@
- STM32F746 Overview
- ==================
-
- Introduction
- ------------
- The STM32F746 is a Cortex-M7 MCU aimed at various applications.
- It features:
- - Cortex-M7 core running up to @216MHz
- - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- - FMC controller to connect SDRAM, NOR and NAND memories
- - Dual mode QSPI
- - SD/MMC/SDIO support
- - Ethernet controller
- - USB OTFG FS & HS controllers
- - I2C, SPI, CAN busses support
- - Several 16 & 32 bits general purpose timers
- - Serial Audio interface
- - LCD controller
- - HDMI-CEC
- - SPDIFRX
-
- Resources
- ---------
- Datasheet and reference manual are publicly available on ST website:
- - http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
-
- Document Author
- ---------------
- Alexandre Torgue <alexandre.torgue@st.com>
-
-
-
-
-
diff --git a/Documentation/arm/stm32/stm32f769-overview.rst b/Documentation/arm/stm32/stm32f769-overview.rst
new file mode 100644
index 000000000000..228656ced2fe
--- /dev/null
+++ b/Documentation/arm/stm32/stm32f769-overview.rst
@@ -0,0 +1,35 @@
+STM32F769 Overview
+==================
+
+Introduction
+------------
+
+The STM32F769 is a Cortex-M7 MCU aimed at various applications.
+It features:
+
+- Cortex-M7 core running up to @216MHz
+- 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
+- FMC controller to connect SDRAM, NOR and NAND memories
+- Dual mode QSPI
+- SD/MMC/SDIO support*2
+- Ethernet controller
+- USB OTFG FS & HS controllers
+- I2C*4, SPI*6, CAN*3 busses support
+- Several 16 & 32 bits general purpose timers
+- Serial Audio interface*2
+- LCD controller
+- HDMI-CEC
+- DSI
+- SPDIFRX
+- MDIO salave interface
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32F769_).
+
+.. _STM32F769: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html
+
+:Authors:
+
+Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arm/stm32/stm32h743-overview.rst b/Documentation/arm/stm32/stm32h743-overview.rst
new file mode 100644
index 000000000000..3458dc00095d
--- /dev/null
+++ b/Documentation/arm/stm32/stm32h743-overview.rst
@@ -0,0 +1,34 @@
+STM32H743 Overview
+==================
+
+Introduction
+------------
+
+The STM32H743 is a Cortex-M7 MCU aimed at various applications.
+It features:
+
+- Cortex-M7 core running up to @400MHz
+- 2MB internal flash, 1MBytes internal RAM
+- FMC controller to connect SDRAM, NOR and NAND memories
+- Dual mode QSPI
+- SD/MMC/SDIO support
+- Ethernet controller
+- USB OTFG FS & HS controllers
+- I2C, SPI, CAN busses support
+- Several 16 & 32 bits general purpose timers
+- Serial Audio interface
+- LCD controller
+- HDMI-CEC
+- SPDIFRX
+- DFSDM
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32H743_).
+
+.. _STM32H743: http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
+
+:Authors:
+
+Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arm/stm32/stm32h743-overview.txt b/Documentation/arm/stm32/stm32h743-overview.txt
deleted file mode 100644
index 3031cbae31a5..000000000000
--- a/Documentation/arm/stm32/stm32h743-overview.txt
+++ /dev/null
@@ -1,30 +0,0 @@
- STM32H743 Overview
- ==================
-
- Introduction
- ------------
- The STM32H743 is a Cortex-M7 MCU aimed at various applications.
- It features:
- - Cortex-M7 core running up to @400MHz
- - 2MB internal flash, 1MBytes internal RAM
- - FMC controller to connect SDRAM, NOR and NAND memories
- - Dual mode QSPI
- - SD/MMC/SDIO support
- - Ethernet controller
- - USB OTFG FS & HS controllers
- - I2C, SPI, CAN busses support
- - Several 16 & 32 bits general purpose timers
- - Serial Audio interface
- - LCD controller
- - HDMI-CEC
- - SPDIFRX
- - DFSDM
-
- Resources
- ---------
- Datasheet and reference manual are publicly available on ST website:
- - http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
-
- Document Author
- ---------------
- Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arm/stm32/stm32mp157-overview.rst b/Documentation/arm/stm32/stm32mp157-overview.rst
new file mode 100644
index 000000000000..62e176d47ca7
--- /dev/null
+++ b/Documentation/arm/stm32/stm32mp157-overview.rst
@@ -0,0 +1,19 @@
+STM32MP157 Overview
+===================
+
+Introduction
+------------
+
+The STM32MP157 is a Cortex-A MPU aimed at various applications.
+It features:
+
+- Dual core Cortex-A7 application core
+- 2D/3D image composition with GPU
+- Standard memories interface support
+- Standard connectivity, widely inherited from the STM32 MCU family
+- Comprehensive security support
+
+:Authors:
+
+- Ludovic Barre <ludovic.barre@st.com>
+- Gerald Baeza <gerald.baeza@st.com>
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt
index a70090b28b07..7964f03846b1 100644
--- a/Documentation/arm64/cpu-feature-registers.txt
+++ b/Documentation/arm64/cpu-feature-registers.txt
@@ -110,7 +110,7 @@ infrastructure:
x--------------------------------------------------x
| Name | bits | visible |
|--------------------------------------------------|
- | RES0 | [63-52] | n |
+ | TS | [55-52] | y |
|--------------------------------------------------|
| FHM | [51-48] | y |
|--------------------------------------------------|
@@ -124,8 +124,6 @@ infrastructure:
|--------------------------------------------------|
| RDM | [31-28] | y |
|--------------------------------------------------|
- | RES0 | [27-24] | n |
- |--------------------------------------------------|
| ATOMICS | [23-20] | y |
|--------------------------------------------------|
| CRC32 | [19-16] | y |
@@ -135,8 +133,6 @@ infrastructure:
| SHA1 | [11-8] | y |
|--------------------------------------------------|
| AES | [7-4] | y |
- |--------------------------------------------------|
- | RES0 | [3-0] | n |
x--------------------------------------------------x
@@ -144,12 +140,10 @@ infrastructure:
x--------------------------------------------------x
| Name | bits | visible |
|--------------------------------------------------|
- | RES0 | [63-36] | n |
+ | DIT | [51-48] | y |
|--------------------------------------------------|
| SVE | [35-32] | y |
|--------------------------------------------------|
- | RES0 | [31-28] | n |
- |--------------------------------------------------|
| GIC | [27-24] | n |
|--------------------------------------------------|
| AdvSIMD | [23-20] | y |
@@ -199,6 +193,14 @@ infrastructure:
| DPB | [3-0] | y |
x--------------------------------------------------x
+ 5) ID_AA64MMFR2_EL1 - Memory model feature register 2
+
+ x--------------------------------------------------x
+ | Name | bits | visible |
+ |--------------------------------------------------|
+ | AT | [35-32] | y |
+ x--------------------------------------------------x
+
Appendix I: Example
---------------------------
diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt
index 57324ee55ecc..d6aff2c5e9e2 100644
--- a/Documentation/arm64/elf_hwcaps.txt
+++ b/Documentation/arm64/elf_hwcaps.txt
@@ -162,3 +162,19 @@ HWCAP_SVE
HWCAP_ASIMDFHM
Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
+
+HWCAP_DIT
+
+ Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001.
+
+HWCAP_USCAT
+
+ Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001.
+
+HWCAP_ILRCPC
+
+ Functionality implied by ID_AA64ISR1_EL1.LRCPC == 0b0002.
+
+HWCAP_FLAGM
+
+ Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index 671bc0639262..c5dab30d3389 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -86,9 +86,12 @@ Translation table lookup with 64KB pages:
+-------------------------------------------------> [63] TTBR0/1
-When using KVM without the Virtualization Host Extensions, the hypervisor
-maps kernel pages in EL2 at a fixed offset from the kernel VA. See the
-kern_hyp_va macro for more details.
+When using KVM without the Virtualization Host Extensions, the
+hypervisor maps kernel pages in EL2 at a fixed (and potentially
+random) offset from the linear mapping. See the kern_hyp_va macro and
+kvm_update_va_mask function for more details. MMIO devices such as
+GICv2 gets mapped next to the HYP idmap page, as do vectors when
+ARM64_HARDEN_EL2_VECTORS is selected for particular CPUs.
When using KVM with the Virtualization Host Extensions, no additional
mappings are created, since the host kernel runs directly in EL2.
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index c1d520de6dfe..3b2f2dd82225 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -55,6 +55,7 @@ stable kernels.
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
| ARM | Cortex-A72 | #853709 | N/A |
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
+| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
| ARM | MMU-500 | #841119,#826419 | N/A |
| | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
diff --git a/Documentation/blackfin/00-INDEX b/Documentation/blackfin/00-INDEX
deleted file mode 100644
index 265a1effebde..000000000000
--- a/Documentation/blackfin/00-INDEX
+++ /dev/null
@@ -1,6 +0,0 @@
-00-INDEX
- - This file
-bfin-gpio-notes.txt
- - Notes in developing/using bfin-gpio driver.
-bfin-spi-notes.txt
- - Notes for using bfin spi bus driver.
diff --git a/Documentation/blackfin/bfin-gpio-notes.txt b/Documentation/blackfin/bfin-gpio-notes.txt
deleted file mode 100644
index d245f39c3d01..000000000000
--- a/Documentation/blackfin/bfin-gpio-notes.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * File: Documentation/blackfin/bfin-gpio-notes.txt
- * Based on:
- * Author:
- *
- * Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $
- * Description: This file contains the notes in developing/using bfin-gpio.
- *
- *
- * Rev:
- *
- * Modified:
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- */
-
-
-1. Blackfin GPIO introduction
-
- There are many GPIO pins on Blackfin. Most of these pins are muxed to
- multi-functions. They can be configured as peripheral, or just as GPIO,
- configured to input with interrupt enabled, or output.
-
- For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c",
- or the relevant HRM.
-
-
-2. Avoiding resource conflict
-
- Followed function groups are used to avoiding resource conflict,
- - Use the pin as peripheral,
- int peripheral_request(unsigned short per, const char *label);
- int peripheral_request_list(const unsigned short per[], const char *label);
- void peripheral_free(unsigned short per);
- void peripheral_free_list(const unsigned short per[]);
- - Use the pin as GPIO,
- int bfin_gpio_request(unsigned gpio, const char *label);
- void bfin_gpio_free(unsigned gpio);
- - Use the pin as GPIO interrupt,
- int bfin_gpio_irq_request(unsigned gpio, const char *label);
- void bfin_gpio_irq_free(unsigned gpio);
-
- The request functions will record the function state for a certain pin,
- the free functions will clear its function state.
- Once a pin is requested, it can't be requested again before it is freed by
- previous caller, otherwise kernel will dump stacks, and the request
- function fail.
- These functions are wrapped by other functions, most of the users need not
- care.
-
-
-3. But there are some exceptions
- - Kernel permit the identical GPIO be requested both as GPIO and GPIO
- interrupt.
- Some drivers, like gpio-keys, need this behavior. Kernel only print out
- warning messages like,
- bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are
-configuring it as IRQ!
-
- Note: Consider the case that, if there are two drivers need the
- identical GPIO, one of them use it as GPIO, the other use it as
- GPIO interrupt. This will really cause resource conflict. So if
- there is any abnormal driver behavior, please check the bfin-gpio
- warning messages.
-
- - Kernel permit the identical GPIO be requested from the same driver twice.
-
-
-
diff --git a/Documentation/blackfin/bfin-spi-notes.txt b/Documentation/blackfin/bfin-spi-notes.txt
deleted file mode 100644
index eae6eaf2a09d..000000000000
--- a/Documentation/blackfin/bfin-spi-notes.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-SPI Chip Select behavior:
-
-With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA
-bit whether the Slave Select Line is controlled by hardware (CPHA=0) or
-controlled by software (CPHA=1). However, the Linux SPI bus driver assumes that
-the Slave Select is always under software control and being asserted during
-the entire SPI transfer. - And not just bits_per_word duration.
-
-In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
-behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2
-timing, you can utilize the GPIO controlled SPI Slave Select option instead.
-In this case, you should use GPIO based CS for all of your slaves and not just
-the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior.
-
-You can even use the same pin whose peripheral role is a SSEL,
-but use it as a GPIO instead.
diff --git a/Documentation/bpf/bpf_devel_QA.txt b/Documentation/bpf/bpf_devel_QA.txt
index 84cbb302f2b5..1a0b704e1a38 100644
--- a/Documentation/bpf/bpf_devel_QA.txt
+++ b/Documentation/bpf/bpf_devel_QA.txt
@@ -539,6 +539,18 @@ A: Although LLVM IR generation and optimization try to stay architecture
The clang option "-fno-jump-tables" can be used to disable
switch table generation.
+ - For clang -target bpf, it is guaranteed that pointer or long /
+ unsigned long types will always have a width of 64 bit, no matter
+ whether underlying clang binary or default target (or kernel) is
+ 32 bit. However, when native clang target is used, then it will
+ compile these types based on the underlying architecture's conventions,
+ meaning in case of 32 bit architecture, pointer or long / unsigned
+ long types e.g. in BPF context structure will have width of 32 bit
+ while the BPF LLVM back end still operates in 64 bit. The native
+ target is mostly needed in tracing for the case of walking pt_regs
+ or other kernel structures where CPU's register width matters.
+ Otherwise, clang -target bpf is generally recommended.
+
You should use default target when:
- Your program includes a header file, e.g., ptrace.h, which eventually
diff --git a/Documentation/cdrom/cdrom-standard.tex b/Documentation/cdrom/cdrom-standard.tex
index 8f85b0e41046..f7cd455973f7 100644
--- a/Documentation/cdrom/cdrom-standard.tex
+++ b/Documentation/cdrom/cdrom-standard.tex
@@ -234,6 +234,7 @@ struct& cdrom_device_ops\ \{ \hidewidth\cr
&int& (* open)(struct\ cdrom_device_info *, int)\cr
&void& (* release)(struct\ cdrom_device_info *);\cr
&int& (* drive_status)(struct\ cdrom_device_info *, int);\cr
+ &unsigned\ int& (* check_events)(struct\ cdrom_device_info *, unsigned\ int, int);\cr
&int& (* media_changed)(struct\ cdrom_device_info *, int);\cr
&int& (* tray_move)(struct\ cdrom_device_info *, int);\cr
&int& (* lock_door)(struct\ cdrom_device_info *, int);\cr
@@ -245,10 +246,9 @@ struct& cdrom_device_ops\ \{ \hidewidth\cr
&int& (* reset)(struct\ cdrom_device_info *);\cr
&int& (* audio_ioctl)(struct\ cdrom_device_info *, unsigned\ int,
void *{});\cr
- &int& (* dev_ioctl)(struct\ cdrom_device_info *, unsigned\ int,
- unsigned\ long);\cr
\noalign{\medskip}
&const\ int& capability;& capability flags \cr
+ &int& (* generic_packet)(struct\ cdrom_device_info *, struct\ packet_command *{});\cr
\};\cr
}
$$
@@ -274,19 +274,32 @@ $$
\halign{$#$\ \hfil&$#$\ \hfil&\hbox to 10em{$#$\hss}&
$/*$ \rm# $*/$\hfil\cr
struct& cdrom_device_info\ \{ \hidewidth\cr
- & struct\ cdrom_device_ops *& ops;& device operations for this major\cr
- & struct\ cdrom_device_info *& next;& next device_info for this major\cr
+ & const\ struct\ cdrom_device_ops *& ops;& device operations for this major\cr
+ & struct\ list_head& list;& linked list of all device_info\cr
+ & struct\ gendisk *& disk;& matching block layer disk\cr
& void *& handle;& driver-dependent data\cr
\noalign{\medskip}
- & kdev_t& dev;& device number (incorporates minor)\cr
& int& mask;& mask of capability: disables them \cr
& int& speed;& maximum speed for reading data \cr
& int& capacity;& number of discs in a jukebox \cr
\noalign{\medskip}
- &int& options : 30;& options flags \cr
+ &unsigned\ int& options : 30;& options flags \cr
&unsigned& mc_flags : 2;& media-change buffer flags \cr
+ &unsigned\ int& vfs_events;& cached events for vfs path\cr
+ &unsigned\ int& ioctl_events;& cached events for ioctl path\cr
& int& use_count;& number of times device is opened\cr
& char& name[20];& name of the device type\cr
+\noalign{\medskip}
+ &__u8& sanyo_slot : 2;& Sanyo 3-CD changer support\cr
+ &__u8& keeplocked : 1;& CDROM_LOCKDOOR status\cr
+ &__u8& reserved : 5;& not used yet\cr
+ & int& cdda_method;& see CDDA_* flags\cr
+ &__u8& last_sense;& saves last sense key\cr
+ &__u8& media_written;& dirty flag, DVD+RW bookkeeping\cr
+ &unsigned\ short& mmc3_profile;& current MMC3 profile\cr
+ & int& for_data;& unknown:TBD\cr
+ & int\ (* exit)\ (struct\ cdrom_device_info *);&& unknown:TBD\cr
+ & int& mrw_mode_page;& which MRW mode page is in use\cr
\}\cr
}$$
Using this $struct$, a linked list of the registered minor devices is
@@ -298,9 +311,7 @@ The $mask$ flags can be used to mask out some of the capabilities listed
in $ops\to capability$, if a specific drive doesn't support a feature
of the driver. The value $speed$ specifies the maximum head-rate of the
drive, measured in units of normal audio speed (176\,kB/sec raw data or
-150\,kB/sec file system data). The value $n_discs$ should reflect the
-number of discs the drive can hold simultaneously, if it is designed
-as a juke-box, or otherwise~1. The parameters are declared $const$
+150\,kB/sec file system data). The parameters are declared $const$
because they describe properties of the drive, which don't change after
registration.
@@ -1002,7 +1013,7 @@ taken over the torch in maintaining \cdromc\ and integrating much
\cdrom-related code in the 2.1-kernel. Thanks to Scott Snyder and
Gerd Knorr, who were the first to implement this interface for SCSI
and IDE-CD drivers and added many ideas for extension of the data
-structures relative to kernel~2.0. Further thanks to Heiko Ei{\sz}feldt,
+structures relative to kernel~2.0. Further thanks to Heiko Ei{\ss}feldt,
Thomas Quinot, Jon Tombs, Ken Pizzini, Eberhard M\"onkeberg and Andrew
Kroll, the \linux\ \cdrom\ device driver developers who were kind
enough to give suggestions and criticisms during the writing. Finally
diff --git a/Documentation/cgroup-v1/memory.txt b/Documentation/cgroup-v1/memory.txt
index a4af2e124e24..3682e99234c2 100644
--- a/Documentation/cgroup-v1/memory.txt
+++ b/Documentation/cgroup-v1/memory.txt
@@ -262,7 +262,7 @@ When oom event notifier is registered, event will be delivered.
2.6 Locking
lock_page_cgroup()/unlock_page_cgroup() should not be called under
- mapping->tree_lock.
+ the i_pages lock.
Other lock order is following:
PG_locked.
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index be909ed45970..511628bb3d3a 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -268,9 +268,19 @@ The common clock framework uses two global locks, the prepare lock and the
enable lock.
The enable lock is a spinlock and is held across calls to the .enable,
-.disable and .is_enabled operations. Those operations are thus not allowed to
-sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API
-functions are allowed in atomic context.
+.disable operations. Those operations are thus not allowed to sleep,
+and calls to the clk_enable(), clk_disable() API functions are allowed in
+atomic context.
+
+For clk_is_enabled() API, it is also designed to be allowed to be used in
+atomic context. However, it doesn't really make any sense to hold the enable
+lock in core, unless you want to do something else with the information of
+the enable state with that lock held. Otherwise, seeing if a clk is enabled is
+a one-shot read of the enabled state, which could just as easily change after
+the function returns because the lock is released. Thus the user of this API
+needs to handle synchronizing the read of the state with whatever they're
+using it for to make sure that the enable state doesn't change during that
+time.
The prepare lock is a mutex and is held across calls to all other operations.
All those operations are allowed to sleep, and calls to the corresponding API
diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst
index 934559b3c130..eb30efdd2e78 100644
--- a/Documentation/core-api/printk-formats.rst
+++ b/Documentation/core-api/printk-formats.rst
@@ -60,8 +60,8 @@ Plain Pointers
Pointers printed without a specifier extension (i.e unadorned %p) are
hashed to prevent leaking information about the kernel memory layout. This
has the added benefit of providing a unique identifier. On 64-bit machines
-the first 32 bits are zeroed. If you *really* want the address see %px
-below.
+the first 32 bits are zeroed. The kernel will print ``(ptrval)`` until it
+gathers enough entropy. If you *really* want the address see %px below.
Symbols/Function Pointers
-------------------------
diff --git a/Documentation/cpu-freq/core.txt b/Documentation/cpu-freq/core.txt
index 978463a7c81e..073f128af5a7 100644
--- a/Documentation/cpu-freq/core.txt
+++ b/Documentation/cpu-freq/core.txt
@@ -97,12 +97,10 @@ flags - flags of the cpufreq driver
==================================================================
For details about OPP, see Documentation/power/opp.txt
-dev_pm_opp_init_cpufreq_table - cpufreq framework typically is initialized with
- cpufreq_table_validate_and_show() which is provided with the list of
- frequencies that are available for operation. This function provides
- a ready to use conversion routine to translate the OPP layer's internal
- information about the available frequencies into a format readily
- providable to cpufreq.
+dev_pm_opp_init_cpufreq_table -
+ This function provides a ready to use conversion routine to translate
+ the OPP layer's internal information about the available frequencies
+ into a format readily providable to cpufreq.
WARNING: Do not use this function in interrupt context.
@@ -112,7 +110,7 @@ dev_pm_opp_init_cpufreq_table - cpufreq framework typically is initialized with
/* Do things */
r = dev_pm_opp_init_cpufreq_table(dev, &freq_table);
if (!r)
- cpufreq_table_validate_and_show(policy, freq_table);
+ policy->freq_table = freq_table;
/* Do other things */
}
diff --git a/Documentation/cpu-freq/cpu-drivers.txt b/Documentation/cpu-freq/cpu-drivers.txt
index 61546ac578d6..6e353d00cdc6 100644
--- a/Documentation/cpu-freq/cpu-drivers.txt
+++ b/Documentation/cpu-freq/cpu-drivers.txt
@@ -259,10 +259,8 @@ CPUFREQ_ENTRY_INVALID. The entries don't need to be in sorted in any
particular order, but if they are cpufreq core will do DVFS a bit
quickly for them as search for best match is faster.
-By calling cpufreq_table_validate_and_show(), the cpuinfo.min_freq and
-cpuinfo.max_freq values are detected, and policy->min and policy->max
-are set to the same values. This is helpful for the per-CPU
-initialization stage.
+The cpufreq table is verified automatically by the core if the policy contains a
+valid pointer in its policy->freq_table field.
cpufreq_frequency_table_verify() assures that at least one valid
frequency is within policy->min and policy->max, and all other criteria
diff --git a/Documentation/cpuidle/sysfs.txt b/Documentation/cpuidle/sysfs.txt
index b6f44f490ed7..d1587f434e7b 100644
--- a/Documentation/cpuidle/sysfs.txt
+++ b/Documentation/cpuidle/sysfs.txt
@@ -40,6 +40,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
+-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
@@ -50,6 +51,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
+-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
@@ -60,6 +62,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
+-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
@@ -70,6 +73,7 @@ total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
+-r--r--r-- 1 root root 4096 Feb 8 10:42 residency
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
--------------------------------------------------------------------------------
@@ -78,6 +82,8 @@ total 0
* desc : Small description about the idle state (string)
* disable : Option to disable this idle state (bool) -> see note below
* latency : Latency to exit out of this idle state (in microseconds)
+* residency : Time after which a state becomes more effecient than any
+ shallower state (in microseconds)
* name : Name of the idle state (string)
* power : Power consumed while in this idle state (in milliwatts)
* time : Total time spent in this idle state (in microseconds)
diff --git a/Documentation/cris/README b/Documentation/cris/README
deleted file mode 100644
index 8dbdb1a44429..000000000000
--- a/Documentation/cris/README
+++ /dev/null
@@ -1,195 +0,0 @@
-Linux on the CRIS architecture
-==============================
-
-This is a port of Linux to Axis Communications ETRAX 100LX,
-ETRAX FS and ARTPEC-3 embedded network CPUs.
-
-For more information about CRIS and ETRAX please see further below.
-
-In order to compile this you need a version of gcc with support for the
-ETRAX chip family. Please see this link for more information on how to
-download the compiler and other tools useful when building and booting
-software for the ETRAX platform:
-
-http://developer.axis.com/wiki/doku.php?id=axis:install-howto-2_20
-
-What is CRIS ?
---------------
-
-CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU
-architecture in Axis Communication AB's range of embedded network CPU's,
-called ETRAX.
-
-The ETRAX 100LX chip
---------------------
-
-For reference, please see the following link:
-
-http://www.axis.com/products/dev_etrax_100lx/index.htm
-
-The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
-range of built-in interfaces, all with modern scatter/gather DMA.
-
-Memory interfaces:
-
- * SRAM
- * NOR-flash/ROM
- * EDO or page-mode DRAM
- * SDRAM
-
-I/O interfaces:
-
- * one 10/100 Mbit/s ethernet controller
- * four serial-ports (up to 6 Mbit/s)
- * two synchronous serial-ports for multimedia codec's etc.
- * USB host controller and USB slave
- * ATA
- * SCSI
- * two parallel-ports
- * two generic 8-bit ports
-
- (not all interfaces are available at the same time due to chip pin
- multiplexing)
-
-ETRAX 100LX is CRISv10 architecture.
-
-
-The ETRAX FS and ARTPEC-3 chips
--------------------------------
-
-The ETRAX FS is a 200MHz 32-bit RISC processor with on-chip 16kB
-I-cache and 16kB D-cache and with a wide range of device interfaces
-including multiple high speed serial ports and an integrated USB 1.1 PHY.
-
-The ARTPEC-3 is a variant of the ETRAX FS with additional IO-units
-used by the Axis Communications network cameras.
-
-See below link for more information:
-
-http://www.axis.com/products/dev_etrax_fs/index.htm
-
-ETRAX FS and ARTPEC-3 are both CRISv32 architectures.
-
-Bootlog
--------
-
-Just as an example, this is the debug-output from a boot of Linux 2.4 on
-a board with ETRAX 100LX. The displayed BogoMIPS value is 5 times too small :)
-At the end you see some user-mode programs booting like telnet and ftp daemons.
-
-Linux version 2.4.1 (bjornw@godzilla.axis.se) (gcc version 2.96 20000427 (experimental)) #207 Wed Feb 21 15:48:15 CET 2001
-ROM fs in RAM, size 1376256 bytes
-Setting up paging and the MMU.
-On node 0 totalpages: 2048
-zone(0): 2048 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Linux/CRIS port on ETRAX 100LX (c) 2001 Axis Communications AB
-Kernel command line:
-Calibrating delay loop... 19.91 BogoMIPS
-Memory: 13872k/16384k available (587k kernel code, 2512k reserved, 44k data, 24k init)
-kmem_create: Forcing size word alignment - vm_area_struct
-kmem_create: Forcing size word alignment - filp
-Dentry-cache hash table entries: 2048 (order: 1, 16384 bytes)
-Buffer-cache hash table entries: 2048 (order: 0, 8192 bytes)
-Page-cache hash table entries: 2048 (order: 0, 8192 bytes)
-kmem_create: Forcing size word alignment - kiobuf
-kmem_create: Forcing size word alignment - bdev_cache
-Inode-cache hash table entries: 1024 (order: 0, 8192 bytes)
-kmem_create: Forcing size word alignment - inode_cache
-POSIX conformance testing by UNIFIX
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Starting kswapd v1.8
-kmem_create: Forcing size word alignment - file lock cache
-kmem_create: Forcing size word alignment - blkdev_requests
-block: queued sectors max/low 9109kB/3036kB, 64 slots per queue
-ETRAX 100LX 10/100MBit ethernet v2.0 (c) 2000 Axis Communications AB
-eth0 initialized
-eth0: changed MAC to 00:40:8C:CD:00:00
-ETRAX 100LX serial-driver $Revision: 1.7 $, (c) 2000 Axis Communications AB
-ttyS0 at 0xb0000060 is a builtin UART with DMA
-ttyS1 at 0xb0000068 is a builtin UART with DMA
-ttyS2 at 0xb0000070 is a builtin UART with DMA
-ttyS3 at 0xb0000078 is a builtin UART with DMA
-Axis flash mapping: 200000 at 50000000
-Axis flash: Found 1 x16 CFI device at 0x0 in 16 bit mode
- Amd/Fujitsu Extended Query Table v1.0 at 0x0040
-Axis flash: JEDEC Device ID is 0xC4. Assuming broken CFI table.
-Axis flash: Swapping erase regions for broken CFI table.
-number of CFI chips: 1
- Using default partition table
-I2C driver v2.2, (c) 1999-2001 Axis Communications AB
-ETRAX 100LX GPIO driver v2.1, (c) 2001 Axis Communications AB
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP
-kmem_create: Forcing size word alignment - ip_dst_cache
-IP: routing cache hash table of 1024 buckets, 8Kbytes
-TCP: Hash tables configured (established 2048 bind 2048)
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-VFS: Mounted root (cramfs filesystem) readonly.
-Init starts up...
-Mounted none on /proc ok.
-Setting up eth0 with ip 10.13.9.116 and mac 00:40:8c:18:04:60
-eth0: changed MAC to 00:40:8C:18:04:60
-Setting up lo with ip 127.0.0.1
-Default gateway is 10.13.9.1
-Hostname is bbox1
-Telnetd starting, using port 23.
- using /bin/sash as shell.
-sftpd[15]: sftpd $Revision: 1.7 $ starting up
-
-
-
-And here is how some /proc entries look:
-
-17# cd /proc
-17# cat cpuinfo
-cpu : CRIS
-cpu revision : 10
-cpu model : ETRAX 100LX
-cache size : 8 kB
-fpu : no
-mmu : yes
-ethernet : 10/100 Mbps
-token ring : no
-scsi : yes
-ata : yes
-usb : yes
-bogomips : 99.84
-
-17# cat meminfo
- total: used: free: shared: buffers: cached:
-Mem: 7028736 925696 6103040 114688 0 229376
-Swap: 0 0 0
-MemTotal: 6864 kB
-MemFree: 5960 kB
-MemShared: 112 kB
-Buffers: 0 kB
-Cached: 224 kB
-Active: 224 kB
-Inact_dirty: 0 kB
-Inact_clean: 0 kB
-Inact_target: 0 kB
-HighTotal: 0 kB
-HighFree: 0 kB
-LowTotal: 6864 kB
-LowFree: 5960 kB
-SwapTotal: 0 kB
-SwapFree: 0 kB
-17# ls -l /bin
--rwxr-xr-x 1 342 100 10356 Jan 01 00:00 ifconfig
--rwxr-xr-x 1 342 100 17548 Jan 01 00:00 init
--rwxr-xr-x 1 342 100 9488 Jan 01 00:00 route
--rwxr-xr-x 1 342 100 46036 Jan 01 00:00 sftpd
--rwxr-xr-x 1 342 100 48104 Jan 01 00:00 sh
--rwxr-xr-x 1 342 100 16252 Jan 01 00:00 telnetd
-
-
-
-
-
-
-
-
-
diff --git a/Documentation/crypto/crypto_engine.rst b/Documentation/crypto/crypto_engine.rst
new file mode 100644
index 000000000000..8272ac92a14f
--- /dev/null
+++ b/Documentation/crypto/crypto_engine.rst
@@ -0,0 +1,48 @@
+=============
+CRYPTO ENGINE
+=============
+
+Overview
+--------
+The crypto engine API (CE), is a crypto queue manager.
+
+Requirement
+-----------
+You have to put at start of your tfm_ctx the struct crypto_engine_ctx
+struct your_tfm_ctx {
+ struct crypto_engine_ctx enginectx;
+ ...
+};
+Why: Since CE manage only crypto_async_request, it cannot know the underlying
+request_type and so have access only on the TFM.
+So using container_of for accessing __ctx is impossible.
+Furthermore, the crypto engine cannot know the "struct your_tfm_ctx",
+so it must assume that crypto_engine_ctx is at start of it.
+
+Order of operations
+-------------------
+You have to obtain a struct crypto_engine via crypto_engine_alloc_init().
+And start it via crypto_engine_start().
+
+Before transferring any request, you have to fill the enginectx.
+- prepare_request: (taking a function pointer) If you need to do some processing before doing the request
+- unprepare_request: (taking a function pointer) Undoing what's done in prepare_request
+- do_one_request: (taking a function pointer) Do encryption for current request
+
+Note: that those three functions get the crypto_async_request associated with the received request.
+So your need to get the original request via container_of(areq, struct yourrequesttype_request, base);
+
+When your driver receive a crypto_request, you have to transfer it to
+the cryptoengine via one of:
+- crypto_transfer_ablkcipher_request_to_engine()
+- crypto_transfer_aead_request_to_engine()
+- crypto_transfer_akcipher_request_to_engine()
+- crypto_transfer_hash_request_to_engine()
+- crypto_transfer_skcipher_request_to_engine()
+
+At the end of the request process, a call to one of the following function is needed:
+- crypto_finalize_ablkcipher_request
+- crypto_finalize_aead_request
+- crypto_finalize_akcipher_request
+- crypto_finalize_hash_request
+- crypto_finalize_skcipher_request
diff --git a/Documentation/crypto/devel-algos.rst b/Documentation/crypto/devel-algos.rst
index 66f50d32dcec..c45c6f400dbd 100644
--- a/Documentation/crypto/devel-algos.rst
+++ b/Documentation/crypto/devel-algos.rst
@@ -236,6 +236,14 @@ when used from another part of the kernel.
|
'---------------> HASH2
+Note that it is perfectly legal to "abandon" a request object:
+- call .init() and then (as many times) .update()
+- _not_ call any of .final(), .finup() or .export() at any point in future
+
+In other words implementations should mind the resource allocation and clean-up.
+No resources related to request objects should remain allocated after a call
+to .init() or .update(), since there might be no chance to free them.
+
Specifics Of Asynchronous HASH Transformation
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/Documentation/dev-tools/kmemleak.rst b/Documentation/dev-tools/kmemleak.rst
index cb8862659178..e6f51260ff32 100644
--- a/Documentation/dev-tools/kmemleak.rst
+++ b/Documentation/dev-tools/kmemleak.rst
@@ -8,7 +8,7 @@ with the difference that the orphan objects are not freed but only
reported via /sys/kernel/debug/kmemleak. A similar method is used by the
Valgrind tool (``memcheck --leak-check``) to detect the memory leaks in
user-space applications.
-Kmemleak is supported on x86, arm, powerpc, sparc, sh, microblaze, ppc, mips, s390, metag and tile.
+Kmemleak is supported on x86, arm, powerpc, sparc, sh, microblaze, ppc, mips, s390 and tile.
Usage
-----
diff --git a/Documentation/dev-tools/sparse.rst b/Documentation/dev-tools/sparse.rst
index 78aa00a604a0..c401c952a340 100644
--- a/Documentation/dev-tools/sparse.rst
+++ b/Documentation/dev-tools/sparse.rst
@@ -67,7 +67,7 @@ __releases - The specified lock is held on function entry, but not exit.
If the function enters and exits without the lock held, acquiring and
releasing the lock inside the function in a balanced way, no
-annotation is needed. The tree annotations above are for cases where
+annotation is needed. The three annotations above are for cases where
sparse would otherwise report a context imbalance.
Getting sparse
diff --git a/Documentation/device-mapper/verity.txt b/Documentation/device-mapper/verity.txt
index 89fd8f9a259f..b3d2e4a42255 100644
--- a/Documentation/device-mapper/verity.txt
+++ b/Documentation/device-mapper/verity.txt
@@ -109,6 +109,17 @@ fec_start <offset>
This is the offset, in <data_block_size> blocks, from the start of the
FEC device to the beginning of the encoding data.
+check_at_most_once
+ Verify data blocks only the first time they are read from the data device,
+ rather than every time. This reduces the overhead of dm-verity so that it
+ can be used on systems that are memory and/or CPU constrained. However, it
+ provides a reduced level of security because only offline tampering of the
+ data device's content will be detected, not online tampering.
+
+ Hash blocks are still verified each time they are read from the hash device,
+ since verification of hash blocks is less performance critical than data
+ blocks, and a hash block will not be verified any more after all the data
+ blocks it covers have been verified anyway.
Theory of operation
===================
diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt
new file mode 100644
index 000000000000..5f3719ab7075
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt
@@ -0,0 +1,179 @@
+System Control and Management Interface (SCMI) Message Protocol
+----------------------------------------------------------
+
+The SCMI is intended to allow agents such as OSPM to manage various functions
+that are provided by the hardware platform it is running on, including power
+and performance functions.
+
+This binding is intended to define the interface the firmware implementing
+the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
+and Management Interface Platform Design Document")[0] provide for OSPM in
+the device tree.
+
+Required properties:
+
+The scmi node with the following properties shall be under the /firmware/ node.
+
+- compatible : shall be "arm,scmi"
+- mboxes: List of phandle and mailbox channel specifiers. It should contain
+ exactly one or two mailboxes, one for transmitting messages("tx")
+ and another optional for receiving the notifications("rx") if
+ supported.
+- shmem : List of phandle pointing to the shared memory(SHM) area as per
+ generic mailbox client binding.
+- #address-cells : should be '1' if the device has sub-nodes, maps to
+ protocol identifier for a given sub-node.
+- #size-cells : should be '0' as 'reg' property doesn't have any size
+ associated with it.
+
+Optional properties:
+
+- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
+about the generic mailbox controller and client driver bindings.
+
+The mailbox is the only permitted method of calling the SCMI firmware.
+Mailbox doorbell is used as a mechanism to alert the presence of a
+messages and/or notification.
+
+Each protocol supported shall have a sub-node with corresponding compatible
+as described in the following sections. If the platform supports dedicated
+communication channel for a particular protocol, the 3 properties namely:
+mboxes, mbox-names and shmem shall be present in the sub-node corresponding
+to that protocol.
+
+Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Required properties:
+- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
+
+Power domain bindings for the power domains based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding for the SCMI power domain providers uses the generic power
+domain binding[2].
+
+Required properties:
+ - #power-domain-cells : Should be 1. Contains the device or the power
+ domain ID value used by SCMI commands.
+
+Sensor bindings for the sensors based on SCMI Message Protocol
+--------------------------------------------------------------
+SCMI provides an API to access the various sensors on the SoC.
+
+Required properties:
+- #thermal-sensor-cells: should be set to 1. This property follows the
+ thermal device tree bindings[3].
+
+ Valid cell values are raw identifiers (Sensor ID)
+ as used by the firmware. Refer to platform details
+ for your implementation for the IDs to use.
+
+SRAM and Shared Memory for SCMI
+-------------------------------
+
+A small area of SRAM is reserved for SCMI communication between application
+processors and SCP.
+
+The properties should follow the generic mmio-sram description found in [4]
+
+Each sub-node represents the reserved area for SCMI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
+ shared memory
+
+[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/power/power_domain.txt
+[3] Documentation/devicetree/bindings/thermal/thermal.txt
+[4] Documentation/devicetree/bindings/sram/sram.txt
+
+Example:
+
+sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+};
+
+mailbox@40000000 {
+ ....
+ #mbox-cells = <1>;
+ reg = <0x0 0x40000000 0x0 0x10000>;
+};
+
+firmware {
+
+ ...
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensors0: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+};
+
+cpu@0 {
+ ...
+ reg = <0 0>;
+ clocks = <&scmi_dvfs 0>;
+};
+
+hdlcd@7ff60000 {
+ ...
+ reg = <0 0x7ff60000 0 0x1000>;
+ clocks = <&scmi_clk 4>;
+ power-domains = <&scmi_devpd 1>;
+};
+
+thermal-zones {
+ soc_thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ /* sensor ID */
+ thermal-sensors = <&scmi_sensors0 3>;
+ ...
+ };
+};
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
new file mode 100644
index 000000000000..8e043301e28e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
@@ -0,0 +1,42 @@
+=========================================================
+Secondary CPU enable-method "nuvoton,npcm750-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name: "nuvoton,npcm750-smp"
+Compatible machines: "nuvoton,npcm750"
+Compatible CPUs: "arm,cortex-a9"
+Related properties: (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f4a777039f03..29e1dc5d506d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,7 @@ described below.
"nvidia,tegra186-denver"
"qcom,krait"
"qcom,kryo"
+ "qcom,kryo385"
"qcom,scorpion"
- enable-method
Value type: <stringlist>
@@ -198,6 +199,7 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
+ "allwinner,sun9i-a80-smp"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
new file mode 100644
index 000000000000..10bd35f9207f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
@@ -0,0 +1,33 @@
+Hisilicon Hip06 Low Pin Count device
+ Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
+ provides I/O access to some legacy ISA devices.
+ Hip06 is based on arm64 architecture where there is no I/O space. So, the
+ I/O ports here are not CPU addresses, and there is no 'ranges' property in
+ LPC device node.
+
+Required properties:
+- compatible: value should be as follows:
+ (a) "hisilicon,hip06-lpc"
+ (b) "hisilicon,hip07-lpc"
+- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
+- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
+- reg: base memory range where the LPC register set is mapped.
+
+Note:
+ The node name before '@' must be "isa" to represent the binding stick to the
+ ISA/EISA binding specification.
+
+Example:
+
+isa@a01b0000 {
+ compatible = "hisilicon,hip06-lpc";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x0 0xa01b0000 0x0 0x1000>;
+
+ ipmi0: bt@e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 7111fbc82a4e..199cd36fe1ba 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -75,6 +75,29 @@ Example:
};
-----------------------------------------------------------------------
+Hisilicon Hi3798CV200 Peripheral Controller
+
+The Hi3798CV200 Peripheral Controller controls peripherals, queries
+their status, and configures some functions of peripherals.
+
+Required properties:
+- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
+ and "simple-mfd".
+- reg: Register address and size of Peripheral Controller.
+- #address-cells: Should be 1.
+- #size-cells: Should be 1.
+
+Examples:
+
+ perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+-----------------------------------------------------------------------
Hisilicon Hi6220 system controller
Required properties:
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index 91d517849483..7d21ab37c19c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -50,6 +50,15 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+- Reference board for MT7623a with eMMC:
+ Required root node properties:
+ - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
+- Reference board for MT7623a with NAND:
+ Required root node properties:
+ - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
+- Reference board for MT7623n with eMMC:
+ Required root node properties:
+ - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623n with NAND:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 9b8f578d5e19..34a69ba67f13 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
+ - "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- #clock-cells: Must be 1
@@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+Required sub-nodes:
+-------
+For common binding part and usage, refer to
+../sonud/mt2701-afe-pcm.txt.
+
Example:
-audsys: audsys@11220000 {
- compatible = "mediatek,mt7622-audsys", "syscon";
- reg = <0 0x11220000 0 0x1000>;
- #clock-cells = <1>;
-};
+ audsys: clock-controller@11220000 {
+ compatible = "mediatek,mt7622-audsys", "syscon";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: audio-controller {
+ ...
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 6cc7840ff37a..8f5335b480ac 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f1227665..7fe5dc6097a6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
index 00760019da00..b8184da2508c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
new file mode 100644
index 000000000000..2d87d9ecea85
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+ - compatible = "nuvoton,npcm750";
+
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
index ce8dabf8c0f9..f35b77920786 100644
--- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
+ "ti,omap5-scm-wkup-pad-conf"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
index 763695db2bd9..f301e636fd52 100644
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -13,6 +13,13 @@ Required properties:
Optional properties:
- sram: Phandle to the ocmcram node
+am335x and am437x only:
+- pm-sram: Phandles to ocmcram nodes to be used for power management.
+ First should be type 'protect-exec' for the driver to use to copy
+ and run PM functions, second should be regular pool to be used for
+ data region for code. See Documentation/devicetree/bindings/sram/sram.txt
+ for more details.
+
Examples:
- For an OMAP5 SMP system:
@@ -36,3 +43,12 @@ mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
+
+- For an AM335x system:
+
+mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ pm-sram = <&pm_sram_code
+ &pm_sram_data>;
+};
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index 0ed4d39d7fe1..ee532e705d6c 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings:
msm8996
mdm9615
ipq8074
+ sdm845
The 'board' element must be one of the following strings:
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 326d24bca1a9..1c1d62d03c4f 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -50,6 +50,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+- Firefly roc-rk3328-cc board:
+ Required root node properties:
+ - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -181,10 +185,18 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+- Rockchip RK3399 Sapphire board standalone:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
+
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
+ Required root node properties:
+ - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
+
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 779f5614bcee..16685787d2bd 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -43,6 +43,12 @@ following properties:
- interrupt-parent: a phandle indicating which interrupt controller
this PMU signals interrupts to.
+
+Optional nodes:
+
+- nodes defining the restart and poweroff syscon children
+
+
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 469ac98ecf8f..14510b215480 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -9,7 +9,11 @@ Required root node properties:
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
+ - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
+ - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
+ - "samsung,midas" - for Exynos4412-based Samsung Midas board.
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
+ - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 5c3af7ef0761..d3d1df97834f 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -39,8 +39,12 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car M3-N (R8A77965)
+ compatible = "renesas,r8a77965"
- R-Car V3M (R8A77970)
compatible = "renesas,r8a77970"
+ - R-Car V3H (R8A77980)
+ compatible = "renesas,r8a77980"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@@ -52,11 +56,13 @@ Boards:
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
- compatible = "renesas,armadillo800eva"
+ compatible = "renesas,armadillo800eva", "renesas,r8a7740"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
+ - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
+ compatible = "renesas,condor", "renesas,r8a77980"
- Draak (RTP0RC77995SEB0010S)
compatible = "renesas,draak", "renesas,r8a77995"
- Eagle (RTP0RC77970SEB0010S)
@@ -102,19 +108,25 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796"
+ - Salvator-X (RTP0RC7796SIPB0011S (M3N))
+ compatible = "renesas,salvator-x", "renesas,r8a77965"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7796"
+ - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
+ compatible = "renesas,salvator-xs", "renesas,r8a77965"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- - V3MSK
+ - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+ compatible = "renesas,stout", "renesas,r8a7790"
+ - V3MSK (Y-ASK-RCAR-V3M-WS10)
compatible = "renesas,v3msk", "renesas,r8a77970"
- - Wheat
+ - Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt
index 05762b08a7bb..6808ed9ddfd5 100644
--- a/Documentation/devicetree/bindings/arm/stm32.txt
+++ b/Documentation/devicetree/bindings/arm/stm32.txt
@@ -7,3 +7,4 @@ using one of the following compatible strings:
st,stm32f469
st,stm32f746
st,stm32h743
+ st,stm32mp157
diff --git a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt
new file mode 100644
index 000000000000..082e6a9382d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt
@@ -0,0 +1,44 @@
+Allwinner SRAM for smp bringup:
+------------------------------------------------
+
+Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
+primary core (cpu0). Once the core gets powered up it checks if a magic
+value is set at a specific location. If it is then the BROM will jump
+to the software entry address, instead of executing a standard boot.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Note that this is separate from the Allwinner SRAM controller found in
+../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
+any device.
+
+Also there are no "secure-only" properties. The implementation should
+check if this SRAM is usable first.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+ "allwinner,sun9i-a80-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+ sram_b: sram@20000 {
+ /* 256 KiB secure SRAM at 0x20000 */
+ compatible = "mmio-sram";
+ reg = <0x00020000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00020000 0x40000>;
+
+ smp-sram@1000 {
+ /*
+ * This is checked by BROM to determine if
+ * cpu0 should jump to SMP entry vector
+ */
+ compatible = "allwinner,sun9i-a80-smp-sram";
+ reg = <0x1000 0x8>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 7f1411bbabf7..32f62bb7006d 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -9,6 +9,12 @@ following compatible values:
nvidia,tegra20
nvidia,tegra30
+ nvidia,tegra114
+ nvidia,tegra124
+ nvidia,tegra132
+ nvidia,tegra210
+ nvidia,tegra186
+ nvidia,tegra194
Boards
-------------------------------------------
@@ -26,8 +32,18 @@ board-specific compatible values:
nvidia,cardhu
nvidia,cardhu-a02
nvidia,cardhu-a04
+ nvidia,dalmore
nvidia,harmony
+ nvidia,jetson-tk1
+ nvidia,norrin
+ nvidia,p2371-0000
+ nvidia,p2371-2180
+ nvidia,p2571
+ nvidia,p2771-0000
+ nvidia,p2972-0000
+ nvidia,roth
nvidia,seaboard
+ nvidia,tn7
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 078a58b0302f..5a3bf7c5a7a0 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC)
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
+ - "nvidia,tegra194-pmc": for Tegra194
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
@@ -10,6 +11,7 @@ Required properties:
- "wake"
- "aotag"
- "scratch"
+ - "misc" (Only for Tegra194)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt
index 1f7995357888..b9043bc35c14 100644
--- a/Documentation/devicetree/bindings/arm/xilinx.txt
+++ b/Documentation/devicetree/bindings/arm/xilinx.txt
@@ -5,3 +5,59 @@ shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynq-7000";
+
+Additional compatible strings:
+
+- Xilinx internal board cc108
+ "xlnx,zynq-cc108"
+
+- Xilinx internal board zc770 with different FMC cards
+ "xlnx,zynq-zc770-xm010"
+ "xlnx,zynq-zc770-xm011"
+ "xlnx,zynq-zc770-xm012"
+ "xlnx,zynq-zc770-xm013"
+
+- Digilent Zybo Z7 board
+ "digilent,zynq-zybo-z7"
+
+---------------------------------------------------------------
+
+Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
+
+Boards with ZynqMP SOC based on an ARM Cortex A53 processor
+shall have the following properties.
+
+Required root node properties:
+ - compatible = "xlnx,zynqmp";
+
+
+Additional compatible strings:
+
+- Xilinx internal board zc1232
+ "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
+
+- Xilinx internal board zc1254
+ "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
+
+- Xilinx internal board zc1275
+ "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
+
+- Xilinx internal board zc1751
+ "xlnx,zynqmp-zc1751"
+
+- Xilinx 96boards compatible board zcu100
+ "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
+
+- Xilinx evaluation board zcu102
+ "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
+ "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
+ "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
+
+- Xilinx evaluation board zcu104
+ "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
+
+- Xilinx evaluation board zcu106
+ "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
+
+- Xilinx evaluation board zcu111
+ "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c760ecb81381..f4006d3c9fdf 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -30,6 +30,7 @@ compatible:
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
+- resets : a list of phandle + reset specifier pairs
- target-supply : regulator for SATA target power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt
index a3d14719e478..781f88751762 100644
--- a/Documentation/devicetree/bindings/ata/imx-sata.txt
+++ b/Documentation/devicetree/bindings/ata/imx-sata.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible : should be one of the following:
- "fsl,imx53-ahci" for i.MX53 SATA controller
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
+ - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
- interrupts : interrupt mapping for SATA IRQ
- reg : registers mapping
- clocks : list of clock specifiers, must contain an entry for each
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3e8915..12ab2f723eb0 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,9 +1,10 @@
-Tegra124 SoC SATA AHCI controller
+Tegra SoC SATA AHCI controller
Required properties :
-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
- must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
- is tegra132.
+- compatible : Must be one of:
+ - Tegra124 : "nvidia,tegra124-ahci"
+ - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
+ - Tegra210 : "nvidia,tegra210-ahci"
- reg : Should contain 2 entries:
- AHCI register set (SATA BAR5)
- SATA register set
@@ -13,8 +14,6 @@ Required properties :
- clock-names : Must include the following entries:
- sata
- sata-oob
- - cml1
- - pll_e
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
@@ -24,9 +23,22 @@ Required properties :
- phys : Must contain an entry for each entry in phy-names.
See ../phy/phy-bindings.txt for details.
- phy-names : Must include the following entries:
- - sata-phy : XUSB PADCTL SATA PHY
-- hvdd-supply : Defines the SATA HVDD regulator
-- vddio-supply : Defines the SATA VDDIO regulator
-- avdd-supply : Defines the SATA AVDD regulator
-- target-5v-supply : Defines the SATA 5V power regulator
-- target-12v-supply : Defines the SATA 12V power regulator
+ - For Tegra124 and Tegra132:
+ - sata-phy : XUSB PADCTL SATA PHY
+- For Tegra124 and Tegra132:
+ - hvdd-supply : Defines the SATA HVDD regulator
+ - vddio-supply : Defines the SATA VDDIO regulator
+ - avdd-supply : Defines the SATA AVDD regulator
+ - target-5v-supply : Defines the SATA 5V power regulator
+ - target-12v-supply : Defines the SATA 12V power regulator
+
+Optional properties:
+- reg :
+ - AUX register set
+- clock-names :
+ - cml1 :
+ cml1 clock should be defined here if the PHY driver
+ doesn't manage them. If it does, they should not be.
+- phy-names :
+ - For T210:
+ - sata-phy
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
index 3e21eb822811..c1e70621799b 100644
--- a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
@@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
controllers with a simple-bus node since they are all connected to the same
chip-select (CS4), in this example external address decoding is provided:
-gmi@70090000 {
+gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
-
bus@4,0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -109,7 +108,7 @@ gmi@70090000 {
Example with one SJA1000 CAN controller connected to the GMI bus
on CS4:
-gmi@70090000 {
+gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@@ -120,7 +119,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
-
can@4,0 {
reg = <4 0 0x100>;
nvidia,snor-mux-mode;
diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt
new file mode 100644
index 000000000000..fee849d5fdd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt
@@ -0,0 +1,36 @@
+* Clock bindings for Freescale i.MX6 SLL
+
+Required properties:
+- compatible: Should be "fsl,imx6sll-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
+for the full list of i.MX6 SLL clock IDs.
+
+Examples:
+
+#include <dt-bindings/clock/imx6sll-clock.h>
+
+clks: clock-controller@20c4000 {
+ compatible = "fsl,imx6sll-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+};
+
+uart1: serial@2020000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
+ <&clks IMX6SLL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+};
diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt
new file mode 100644
index 000000000000..9f4ec5cb5c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intc_stratix10.txt
@@ -0,0 +1,20 @@
+Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be
+ "intel,stratix10-clkmgr"
+
+- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
+
+- #clock-cells : from common clock binding, shall be set to 1.
+
+Example:
+ clkmgr: clock-controller@ffd10000 {
+ compatible = "intel,stratix10-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index f1890d0777a6..773a5226342f 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -22,7 +22,9 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+ - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +34,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77970, r8a77995)
- - "extalr" (r8a7795, r8a7796, r8a77970)
+ r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
index e71c675ba5da..904ae682ea90 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
@@ -32,6 +32,7 @@ clock-output-names:
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
+ - "hdmi_phy" - output clock of the hdmi phy pll - optional
Example: Clock controller node:
diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt b/Documentation/devicetree/bindings/clock/silabs,si544.txt
new file mode 100644
index 000000000000..b86535b80920
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/silabs,si544.txt
@@ -0,0 +1,25 @@
+Binding for Silicon Labs 544 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si544 datasheet
+ https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
+
+Required properties:
+ - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
+ to the speed grade of the chip.
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si544".
+
+Example:
+ si544: clock-controller@55 {
+ reg = <0x55>;
+ #clock-cells = <0>;
+ compatible = "silabs,si544b";
+ };
diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
new file mode 100644
index 000000000000..fb9495ea582c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
@@ -0,0 +1,60 @@
+STMicroelectronics STM32 Peripheral Reset Clock Controller
+==========================================================
+
+The RCC IP is both a reset and a clock controller.
+
+RCC makes also power management (resume/supend and wakeup interrupt).
+
+Please also refer to reset.txt for common reset controller binding usage.
+
+Please also refer to clock-bindings.txt for common clock controller
+binding usage.
+
+
+Required properties:
+- compatible: "st,stm32mp1-rcc", "syscon"
+- reg: should be register base and length as documented in the datasheet
+- #clock-cells: 1, device nodes should specify the clock in their
+ "clocks" property, containing a phandle to the clock device node,
+ an index specifying the clock to use.
+- #reset-cells: Shall be 1
+- interrupts: Should contain a general interrupt line and a interrupt line
+ to the wake-up of processor (CSTOP).
+
+Example:
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp1-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
+ <GIC_SPI 145 IRQ_TYPE_NONE>;
+ };
+
+Specifying clocks
+=================
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/stm32mp1-clks.h header and can be used in device
+tree sources.
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example on STM32MP1, for LTDC reset:
+ ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
+ = 0x180 / 4 * 32 + 0 = 3072
+
+The list of valid indices for STM32MP1 is available in:
+include/dt-bindings/reset-controller/stm32mp1-resets.h
+
+This file implements defines like:
+#define LTDC_R 3072
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 4ca21c3a6fc9..460ef27b1008 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@@ -31,6 +32,9 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
+For the main CCU on H6, one more clock is needed:
+- "iosc": the SoC's internal frequency oscillator
+
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt
new file mode 100644
index 000000000000..1e03dce99a8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt
@@ -0,0 +1,93 @@
+Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
+
+TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
+registers call CFGCHIPn. Some of these registers function as clock
+gates. This document describes the bindings for those clocks.
+
+All of the clock nodes described below must be child nodes of a CFGCHIP node
+(compatible = "ti,da830-cfgchip").
+
+USB PHY clocks
+--------------
+Required properties:
+- compatible: shall be "ti,da830-usb-phy-clocks".
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "fck", "usb_refclkin", "auxclk"
+
+This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
+clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
+
+eHRPWM Time Base Clock (TBCLK)
+------------------------------
+Required properties:
+- compatible: shall be "ti,da830-tbclksync".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+- clock-names: shall be "fck"
+
+PLL DIV4.5 divider
+------------------
+Required properties:
+- compatible: shall be "ti,da830-div4p5ena".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+- clock-names: shall be "pll0_pllout"
+
+EMIFA clock source (ASYNC1)
+---------------------------
+Required properties:
+- compatible: shall be "ti,da850-async1-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "pll0_sysclk3", "div4.5"
+
+ASYNC3 clock source
+-------------------
+Required properties:
+- compatible: shall be "ti,da850-async3-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
+
+Examples:
+
+ cfgchip: syscon@1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ usb_phy_clk: usb-phy-clocks {
+ compatible = "ti,da830-usb-phy-clocks";
+ #clock-cells = <1>;
+ clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
+ clock-names = "fck", "usb_refclkin", "auxclk";
+ };
+ ehrpwm_tbclk: ehrpwm_tbclk {
+ compatible = "ti,da830-tbclksync";
+ #clock-cells = <0>;
+ clocks = <&psc1 17>;
+ clock-names = "fck";
+ };
+ div4p5_clk: div4.5 {
+ compatible = "ti,da830-div4p5ena";
+ #clock-cells = <0>;
+ clocks = <&pll0_pllout>;
+ clock-names = "pll0_pllout";
+ };
+ async1_clk: async1 {
+ compatible = "ti,da850-async1-clksrc";
+ #clock-cells = <0>;
+ clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
+ clock-names = "pll0_sysclk3", "div4.5";
+ };
+ async3_clk: async3 {
+ compatible = "ti,da850-async3-clksrc";
+ #clock-cells = <0>;
+ clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
+ clock-names = "pll0_sysclk2", "pll1_sysclk2";
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
new file mode 100644
index 000000000000..36998e184821
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
@@ -0,0 +1,96 @@
+Binding for TI DaVinci PLL Controllers
+
+The PLL provides clocks to most of the components on the SoC. In addition
+to the PLL itself, this controller also contains bypasses, gates, dividers,
+an multiplexers for various clock signals.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area.
+- clocks: phandles corresponding to the clock names
+- clock-names: names of the clock sources - depends on compatible string
+ - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
+ - for "ti,da850-pll1", shall be "clksrc"
+
+Optional properties:
+- ti,clkmode-square-wave: Indicates that the the board is supplying a square
+ wave input on the OSCIN pin instead of using a crystal oscillator.
+ This property is only valid when compatible = "ti,da850-pll0".
+
+
+Optional child nodes:
+
+pllout
+ Describes the main PLL clock output (before POSTDIV). The node name must
+ be "pllout".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+sysclk
+ Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
+ domains. The node name must be "sysclk". Consumers of this node should
+ use "n" in "SYSCLKn" as the index parameter for the clock cell.
+
+ Required properties:
+ - #clock-cells: shall be 1
+
+auxclk
+ Describes the AUXCLK output of the PLL. The node name must be "auxclk".
+ This child node is only valid when compatible = "ti,da850-pll0".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+obsclk
+ Describes the OBSCLK output of the PLL. The node name must be "obsclk".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+
+Examples:
+
+ pll0: clock-controller@11000 {
+ compatible = "ti,da850-pll0";
+ reg = <0x11000 0x1000>;
+ clocks = <&ref_clk>, <&pll1_sysclk 3>;
+ clock-names = "clksrc", "extclksrc";
+ ti,clkmode-square-wave;
+
+ pll0_pllout: pllout {
+ #clock-cells = <0>;
+ };
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_auxclk: auxclk {
+ #clock-cells = <0>;
+ };
+
+ pll0_obsclk: obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+ pll1: clock-controller@21a000 {
+ compatible = "ti,da850-pll1";
+ reg = <0x21a000 0x1000>;
+ clocks = <&ref_clk>;
+ clock-names = "clksrc";
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_obsclk: obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
new file mode 100644
index 000000000000..dae4ad8e198c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
@@ -0,0 +1,71 @@
+Binding for TI DaVinci Power Sleep Controller (PSC)
+
+The PSC provides power management, clock gating and reset functionality. It is
+primarily used for clocking.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area
+- #clock-cells: from common clock binding; shall be set to 1
+- #power-domain-cells: from generic power domain binding; shall be set to 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names - depends on compatible value
+ - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
+ "pll0_sysclk4", "pll0_sysclk6", "async1"
+ - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
+
+Optional properties:
+- #reset-cells: from reset binding; shall be set to 1 - only applicable when
+ at least one local domain provides a local reset.
+
+Consumers:
+
+ Clock, power domain and reset consumers shall use the local power domain
+ module ID (LPSC) as the index corresponding to the clock cell. Refer to
+ the device-specific datasheet to find these numbers. NB: Most local
+ domains only provide a clock/power domain and not a reset.
+
+Examples:
+
+ psc0: clock-controller@10000 {
+ compatible = "ti,da850-psc0";
+ reg = <0x10000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
+ <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
+ clock_names = "pll0_sysclk1", "pll0_sysclk2",
+ "pll0_sysclk4", "pll0_sysclk6", "async1";
+ };
+ psc1: clock-controller@227000 {
+ compatible = "ti,da850-psc1";
+ reg = <0x227000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
+ clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
+ };
+
+ /* consumer */
+ dsp: dsp@11800000 {
+ compatible = "ti,da850-dsp";
+ reg = <0x11800000 0x40000>,
+ <0x11e00000 0x8000>,
+ <0x11f00000 0x8000>,
+ <0x01c14044 0x4>,
+ <0x01c14174 0x8>;
+ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ clocks = <&psc0 15>;
+ power-domains = <&psc0 15>;
+ resets = <&psc0 15>;
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+- Documentation/devicetree/bindings/power/power_domain.txt
+- Documentation/devicetree/bindings/reset/reset.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt
index 35a6f5c7e5c2..9b13b32974f9 100644
--- a/Documentation/devicetree/bindings/clock/ti/divider.txt
+++ b/Documentation/devicetree/bindings/clock/ti/divider.txt
@@ -75,6 +75,9 @@ Optional properties:
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
+- ti,latch-bit : latch the divider value to HW, only needed if the register
+ access requires this. As an example dra76x DPLL_GMAC H14 divider implements
+ such behavior.
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt
index 2d0d170f8001..eec8994b9be8 100644
--- a/Documentation/devicetree/bindings/clock/ti/mux.txt
+++ b/Documentation/devicetree/bindings/clock/ti/mux.txt
@@ -48,6 +48,9 @@ Optional properties:
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
+- ti,latch-bit : latch the mux value to HW, only needed if the register
+ access requires this. As an example, dra7x DPLL_GMAC H14 muxing
+ implements such behavior.
Examples:
diff --git a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
new file mode 100644
index 000000000000..22256e295a7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
@@ -0,0 +1,49 @@
+Samsung micro-USB 11-pin connector
+==================================
+
+Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
+It is present in multiple Samsung mobile devices.
+It has additional pins to route MHL traffic simultanously with USB.
+
+The bindings are superset of usb-connector bindings for micro-USB connector[1].
+
+Required properties:
+- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
+- type: must be "micro".
+
+Required nodes:
+- any data bus to the connector should be modeled using the OF graph bindings
+ specified in bindings/graph.txt, unless the bus is between parent node and
+ the connector. Since single connector can have multpile data buses every bus
+ has assigned OF graph port number as follows:
+ 0: High Speed (HS),
+ 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
+
+[1]: bindings/connector/usb-connector.txt
+
+Example
+-------
+
+Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
+connected to HDMI-MHL bridge (sii8620):
+
+muic-max77843@66 {
+ ...
+ usb_con: connector {
+ compatible = "samsung,usb-connector-11pin", "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ usb_con_mhl: endpoint {
+ remote-endpoint = <&sii8620_mhl>;
+ };
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt
new file mode 100644
index 000000000000..e1463f14af38
--- /dev/null
+++ b/Documentation/devicetree/bindings/connector/usb-connector.txt
@@ -0,0 +1,75 @@
+USB Connector
+=============
+
+USB connector node represents physical USB connector. It should be
+a child of USB interface controller.
+
+Required properties:
+- compatible: describes type of the connector, must be one of:
+ "usb-a-connector",
+ "usb-b-connector",
+ "usb-c-connector".
+
+Optional properties:
+- label: symbolic name for the connector,
+- type: size of the connector, should be specified in case of USB-A, USB-B
+ non-fullsize connectors: "mini", "micro".
+
+Required nodes:
+- any data bus to the connector should be modeled using the OF graph bindings
+ specified in bindings/graph.txt, unless the bus is between parent node and
+ the connector. Since single connector can have multpile data buses every bus
+ has assigned OF graph port number as follows:
+ 0: High Speed (HS), present in all connectors,
+ 1: Super Speed (SS), present in SS capable connectors,
+ 2: Sideband use (SBU), present in USB-C.
+
+Examples
+--------
+
+1. Micro-USB connector with HS lines routed via controller (MUIC):
+
+muic-max77843@66 {
+ ...
+ usb_con: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
+};
+
+2. USB-C connector attached to CC controller (s2mm005), HS lines routed
+to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
+DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
+
+ccic: s2mm005@33 {
+ ...
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint = <&max77865_usbc_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&usbdrd_phy_ss>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ usb_con_sbu: endpoint {
+ remote-endpoint = <&dp_aux>;
+ };
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
index dd3929e85dec..332aed8f4597 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
@@ -18,8 +18,6 @@ Optional properties:
in unit of nanoseconds.
- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
- #cooling-cells:
-- cooling-min-level:
-- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
Examples:
@@ -40,8 +38,6 @@ cpus {
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <2>;
};
cpu@1 {
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
index f6403089edcf..d36f07e0a2bb 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -21,8 +21,6 @@ Optional properties:
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- #cooling-cells:
-- cooling-min-level:
-- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
for detail.
@@ -67,8 +65,6 @@ Example 1 (MT7623 SoC):
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
};
cpu@1 {
device_type = "cpu";
diff --git a/Documentation/devicetree/bindings/cris/axis.txt b/Documentation/devicetree/bindings/cris/axis.txt
deleted file mode 100644
index d209ca2a47c0..000000000000
--- a/Documentation/devicetree/bindings/cris/axis.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Axis Communications AB
-ARTPEC series SoC Device Tree Bindings
-
-
-CRISv32 based SoCs are ETRAX FS and ARTPEC-3:
-
- - compatible = "axis,crisv32";
-
-
diff --git a/Documentation/devicetree/bindings/cris/boards.txt b/Documentation/devicetree/bindings/cris/boards.txt
deleted file mode 100644
index 533dd273ccf7..000000000000
--- a/Documentation/devicetree/bindings/cris/boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Boards based on the CRIS SoCs:
-
-Required root node properties:
- - compatible = should be one or more of the following:
- - "axis,dev88" - for Axis devboard 88 with ETRAX FS
-
-Optional:
-
diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt
index cec8d5d74e26..c2598ab27f2e 100644
--- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt
+++ b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt
@@ -1,7 +1,8 @@
Arm TrustZone CryptoCell cryptographic engine
Required properties:
-- compatible: Should be "arm,cryptocell-712-ree".
+- compatible: Should be one of: "arm,cryptocell-712-ree",
+ "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt number for the device.
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index 76aec8a3724d..3c1f3a229eab 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
+ - clocks
+ Usage: optional, required if SNVS LP RTC requires explicit
+ enablement of clocks
+ Value type: <prop_encoded-array>
+ Definition: a clock specifier describing the clock required for
+ enabling and disabling SNVS LP RTC.
+
+ - clock-names
+ Usage: optional, required if SNVS LP RTC requires explicit
+ enablement of clocks
+ Value type: <string>
+ Definition: clock name string should be "snvs-rtc".
+
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
=====================================================================
@@ -543,6 +558,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {
diff --git a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
index 30c3ce6b502e..5dba55cdfa63 100644
--- a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
+++ b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
@@ -8,7 +8,11 @@ Required properties:
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
Optional properties:
-- clocks: Reference to the crypto engine clock.
+- clocks: Reference to the crypto engine clocks, the second clock is
+ needed for the Armada 7K/8K SoCs.
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for
+ the second one.
Example:
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
new file mode 100644
index 000000000000..4f0ab3ed3b6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
@@ -0,0 +1,58 @@
+Renesas R-Car LVDS Encoder
+==========================
+
+These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
+Gen2, R-Car Gen3 and RZ/G SoCs.
+
+Required properties:
+
+- compatible : Shall contain one of
+ - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
+ - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
+ - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
+ - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
+ - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
+ - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
+ - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
+ - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
+
+- reg: Base address and length for the memory-mapped registers
+- clocks: A phandle + clock-specifier pair for the functional clock
+- resets: A phandle + reset specifier for the module reset
+
+Required nodes:
+
+The LVDS encoder has two video ports. Their connections are modelled using the
+OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 corresponds to the parallel RGB input
+- Video port 1 corresponds to the LVDS output
+
+Each port shall have a single endpoint.
+
+
+Example:
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a7790-lvds";
+ reg = <0 0xfeb90000 0 0x1c>;
+ clocks = <&cpg CPG_MOD 726>;
+ resets = <&cpg 726>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt b/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
deleted file mode 100644
index 6ec1a880ac18..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-THS8135 Video DAC
------------------
-
-This is the binding for Texas Instruments THS8135 Video DAC bridge.
-
-Required properties:
-
-- compatible: Must be "ti,ths8135"
-
-Required nodes:
-
-This device has two video ports. Their connections are modelled using the OF
-graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-
-- Video port 0 for RGB input
-- Video port 1 for VGA output
-
-Example
--------
-
-vga-bridge {
- compatible = "ti,ths8135";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- vga_bridge_in: endpoint {
- remote-endpoint = <&lcdc_out_vga>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- vga_bridge_out: endpoint {
- remote-endpoint = <&vga_con_in>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
new file mode 100644
index 000000000000..df3d7c1ac09e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
@@ -0,0 +1,51 @@
+THS8134 and THS8135 Video DAC
+-----------------------------
+
+This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and
+THS8135 Video DAC bridges.
+
+Required properties:
+
+- compatible: Must be one of
+ "ti,ths8134"
+ "ti,ths8134a," "ti,ths8134"
+ "ti,ths8134b", "ti,ths8134"
+ "ti,ths8135"
+
+Required nodes:
+
+This device has two video ports. Their connections are modelled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for RGB input
+- Video port 1 for VGA output
+
+Example
+-------
+
+vga-bridge {
+ compatible = "ti,ths8135";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&lcdc_out_vga>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
index fc53f7c60bc6..207e42e9eba0 100644
--- a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
+++ b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
@@ -10,6 +10,7 @@ Optional properties:
- analog: the connector has DVI analog pins
- digital: the connector has DVI digital pins
- dual-link: the connector has pins for DVI dual-link
+- hpd-gpios: HPD GPIO number
Required nodes:
- Video port for DVI input
diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
index 05176f1ae108..8def11b16a24 100644
--- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
+++ b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
@@ -1,23 +1,3 @@
-Etnaviv DRM master device
-=========================
-
-The Etnaviv DRM master device is a virtual device needed to list all
-Vivante GPU cores that comprise the GPU subsystem.
-
-Required properties:
-- compatible: Should be one of
- "fsl,imx-gpu-subsystem"
- "marvell,dove-gpu-subsystem"
-- cores: Should contain a list of phandles pointing to Vivante GPU devices
-
-example:
-
-gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu_2d>, <&gpu_3d>;
-};
-
-
Vivante GPU core devices
========================
@@ -32,7 +12,9 @@ Required properties:
- clocks: should contain one clock for entry in clock-names
see Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names:
- - "bus": AXI/register clock
+ - "bus": AXI/master interface clock
+ - "reg": AHB/slave interface clock
+ (only required if GPU can gate slave interface independently)
- "core": GPU core clock
- "shader": Shader clock (only required if GPU has feature PIPE_3D)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index a6671bd2c85a..518e9cdf0d4b 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -7,8 +7,6 @@ Required properties:
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
* "dsi_ctrl"
-- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
- be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
@@ -22,6 +20,8 @@ Required properties:
* "core"
For DSIv2, we need an additional clock:
* "src"
+ For DSI6G v2.0 onwards, we need also need the clock:
+ * "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
@@ -88,21 +88,35 @@ Required properties:
* "qcom,dsi-phy-28nm-lp"
* "qcom,dsi-phy-20nm"
* "qcom,dsi-phy-28nm-8960"
-- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
+ * "qcom,dsi-phy-14nm"
+ * "qcom,dsi-phy-10nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
+ For DSI 14nm and 10nm PHYs:
+ * "dsi_pll"
+ * "dsi_phy"
+ * "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
-- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
- be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
* "iface"
+ For 28nm HPM/LP, 28nm 8960 PHYs:
+- vddio-supply: phandle to vdd-io regulator device node
+ For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
+ For 14nm PHY:
+- vcca-supply: phandle to vcca regulator device node
+ For 10nm PHY:
+- vdds-supply: phandle to vdds regulator device node
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
diff --git a/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt b/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt
new file mode 100644
index 000000000000..248141c3c7e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt
@@ -0,0 +1,31 @@
+ARM Versatile TFT Panels
+
+These panels are connected to the daughterboards found on the
+ARM Versatile reference designs.
+
+This device node must appear as a child to a "syscon"-compatible
+node.
+
+Required properties:
+- compatible: should be "arm,versatile-tft-panel"
+
+Required subnodes:
+- port: see display/panel/panel-common.txt, graph.txt
+
+
+Example:
+
+sysreg@0 {
+ compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
+ reg = <0x00000 0x1000>;
+
+ panel: display@0 {
+ compatible = "arm,versatile-tft-panel";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&foo>;
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt b/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt
new file mode 100644
index 000000000000..85626edf63e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt
@@ -0,0 +1,12 @@
+AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,g104sn02"
+- power-supply: as specified in the base binding
+
+Optional properties:
+- backlight: as specified in the base binding
+- enable-gpios: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/display-timing.txt b/Documentation/devicetree/bindings/display/panel/display-timing.txt
index 58fa3e48481d..78222ced1874 100644
--- a/Documentation/devicetree/bindings/display/panel/display-timing.txt
+++ b/Documentation/devicetree/bindings/display/panel/display-timing.txt
@@ -80,6 +80,11 @@ The parameters are defined as:
| | v | | |
+----------+-------------------------------------+----------+-------+
+Note: In addition to being used as subnode(s) of display-timings, the timing
+ subnode may also be used on its own. This is appropriate if only one mode
+ need be conveyed. In this case, the node should be named 'panel-timing'.
+
+
Example:
display-timings {
diff --git a/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt b/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt
new file mode 100644
index 000000000000..6a036ede3e28
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt
@@ -0,0 +1,25 @@
+Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+Required properties:
+- compatible: should be "koe,tx31d200vm0baa"
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Optional nodes:
+- Video port for LVDS panel input.
+
+Example:
+ panel {
+ compatible = "koe,tx31d200vm0baa";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
index 6862028e7b2e..203b03eefb68 100644
--- a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
+++ b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
@@ -9,6 +9,7 @@ Required properties:
Optional properties:
- reset-gpios: a GPIO spec for the reset pin (active low).
+ - power-supply: phandle of the regulator that provides the supply voltage.
Example:
&dsi {
@@ -17,5 +18,6 @@ Example:
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+ power-supply = <&v1v8>;
};
};
diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
new file mode 100644
index 000000000000..cbb79ef3bfc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
@@ -0,0 +1,25 @@
+Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
+
+The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
+panel connected using a MIPI-DSI video interface.
+
+Required properties:
+ - compatible: "raydium,rm68200"
+ - reg: the virtual channel number of a DSI peripheral
+
+Optional properties:
+ - reset-gpios: a GPIO spec for the reset pin (active low).
+ - power-supply: phandle of the regulator that provides the supply voltage.
+ - backlight: phandle of the backlight device attached to the panel.
+
+Example:
+&dsi {
+ ...
+ panel@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ power-supply = <&v1v8>;
+ backlight = <&pwm_backlight>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/display/panel/simple-panel.txt b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
index 16d8ff088b7d..45a457ad38f0 100644
--- a/Documentation/devicetree/bindings/display/panel/simple-panel.txt
+++ b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
@@ -1,4 +1,8 @@
Simple display panel
+====================
+
+panel node
+----------
Required properties:
- power-supply: See panel-common.txt
diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt
index cd48aba3bc8c..c9cd17f99702 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.txt
+++ b/Documentation/devicetree/bindings/display/renesas,du.txt
@@ -13,13 +13,10 @@ Required Properties:
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+ - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
+ - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
- - reg: A list of base address and length of each memory resource, one for
- each entry in the reg-names property.
- - reg-names: Name of the memory resources. The DU requires one memory
- resource for the DU core (named "du") and one memory resource for each
- LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
- index).
+ - reg: the memory-mapped I/O registers base address and length
- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifiers for the DU interrupts.
@@ -29,14 +26,13 @@ Required Properties:
- clock-names: Name of the clocks. This property is model-dependent.
- R8A7779 uses a single functional clock. The clock doesn't need to be
named.
- - All other DU instances use one functional clock per channel and one
- clock per LVDS encoder (if available). The functional clocks must be
- named "du.x" with "x" being the channel numerical index. The LVDS clocks
- must be named "lvds.x" with "x" being the LVDS encoder numerical index.
- - In addition to the functional and encoder clocks, all DU versions also
- support externally supplied pixel clocks. Those clocks are optional.
- When supplied they must be named "dclkin.x" with "x" being the input
- clock numerical index.
+ - All other DU instances use one functional clock per channel The
+ functional clocks must be named "du.x" with "x" being the channel
+ numerical index.
+ - In addition to the functional clocks, all DU versions also support
+ externally supplied pixel clocks. Those clocks are optional. When
+ supplied they must be named "dclkin.x" with "x" being the input clock
+ numerical index.
- vsps: A list of phandle and channel index tuples to the VSPs that handle
the memory interfaces for the DU channels. The phandle identifies the VSP
@@ -63,15 +59,15 @@ corresponding to each DU output.
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
+ R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
+ R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
Example: R8A7795 (R-Car H3) ES2.0 DU
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>,
- <0 0xfeb90000 0 0x14>;
- reg-names = "du", "lvds.0";
+ reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -79,9 +75,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.2", "du.3";
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
new file mode 100644
index 000000000000..8df7d2e393d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3399 specific extensions to the cdn Display Port
+================================
+
+Required properties:
+- compatible: must be "rockchip,rk3399-cdn-dp"
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+
+- clock-names: from common clock binding:
+ Required elements: "core-clk" "pclk" "spdif" "grf"
+
+- resets : a list of phandle + reset specifier pairs
+- reset-names : string of reset names
+ Required elements: "apb", "core", "dptx", "spdif"
+- power-domains : power-domain property defined with a phandle
+ to respective power domain.
+- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
+- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ contained 2 endpoints, connecting to the output of vop.
+
+- phys: from general PHY binding: the phandle for the PHY device.
+
+- extcon: extcon specifier for the Power Delivery
+
+- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
+
+-------------------------------------------------------------------------------
+
+Example:
+ cdn_dp: dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>;
+ reset-names = "spdif";
+ extcon = <&fusb0>, <&fusb1>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 029252253ad4..3eb1b48b47dd 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -98,7 +98,7 @@ Example 2: DSI panel
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "ref", "pclk";
+ clock-names = "pclk", "ref";
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index cd626ee1147a..3346c1e2a7a0 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -64,6 +64,56 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
+DWC HDMI TX Encoder
+-------------------
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
+Required properties:
+
+ - compatible: value must be one of:
+ * "allwinner,sun8i-a83t-dw-hdmi"
+ - reg: base address and size of memory-mapped region
+ - reg-io-width: See dw_hdmi.txt. Shall be 1.
+ - interrupts: HDMI interrupt number
+ - clocks: phandles to the clocks feeding the HDMI encoder
+ * iahb: the HDMI bus clock
+ * isfr: the HDMI register clock
+ * tmds: TMDS clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller
+ - reset-names: must be "ctrl"
+ - phys: phandle to the DWC HDMI PHY
+ - phy-names: must be "phy"
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint. The second should be the
+ output, usually to an HDMI connector.
+
+DWC HDMI PHY
+------------
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-a83t-hdmi-phy
+ * allwinner,sun8i-h3-hdmi-phy
+ - reg: base address and size of memory-mapped region
+ - clocks: phandles to the clocks feeding the HDMI PHY
+ * bus: the HDMI PHY interface clock
+ * mod: the HDMI PHY module clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller driving the PHY
+ - reset-names: must be "phy"
+
+H3 HDMI PHY requires additional clock:
+ - pll-0: parent of phy clock
+
TV Encoder
----------
@@ -94,24 +144,29 @@ Required properties:
* allwinner,sun7i-a20-tcon
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
+ * allwinner,sun8i-a83t-tcon-tv
* allwinner,sun8i-v3s-tcon
+ * allwinner,sun9i-a80-tcon-lcd
+ * allwinner,sun9i-a80-tcon-tv
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- - clocks: phandles to the clocks feeding the TCON. Three are needed:
+ - clocks: phandles to the clocks feeding the TCON.
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
+ - 'tcon-ch0': The clock driving the TCON channel 0, if supported
- resets: phandles to the reset controllers driving the encoder
- - "lcd": the reset line for the TCON channel 0
+ - "lcd": the reset line for the TCON
+ - "edp": the reset line for the eDP block (A80 only)
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
+ - clock-output-names: Name of the pixel clock created, if TCON supports
+ channel 0.
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint, the second one the output
- The output may have multiple endpoints. The TCON has two channels,
+ The output may have multiple endpoints. TCON can have 1 or 2 channels,
usually with the first channel being used for the panels interfaces
(RGB, LVDS, etc.), and the second being used for the outputs that
require another controller (TV Encoder, HDMI, etc.). The endpoints
@@ -119,11 +174,13 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For TCONs with channel 0, there is one more clock required:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
-need one more reset line:
+When TCON support LVDS (all TCONs except TV TCON on A83T and those found
+in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
And on the A23, A31, A31s and A33, you need one more clock line:
@@ -134,7 +191,7 @@ DRC
---
The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
-(A31, A23, A33), allows to dynamically adjust pixel
+(A31, A23, A33, A80), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content
adaptive backlight control.
@@ -144,6 +201,7 @@ Required properties:
* allwinner,sun6i-a31-drc
* allwinner,sun6i-a31s-drc
* allwinner,sun8i-a33-drc
+ * allwinner,sun9i-a80-drc
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DRC
@@ -170,6 +228,7 @@ Required properties:
* allwinner,sun6i-a31-display-backend
* allwinner,sun7i-a20-display-backend
* allwinner,sun8i-a33-display-backend
+ * allwinner,sun9i-a80-display-backend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@@ -191,6 +250,28 @@ On the A33, some additional properties are required:
- resets and reset-names need to have a phandle to the SAT bus
resets, whose name will be "sat"
+DEU
+---
+
+The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
+can sharpen the display content in both luma and chroma channels.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun9i-a80-deu
+ - reg: base address and size of the memory-mapped region.
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the DEU
+ * ahb: the DEU interface clock
+ * mod: the DEU module clock
+ * ram: the DEU DRAM clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset line driving the DEU
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the outputs
+
Display Engine Frontend
-----------------------
@@ -204,6 +285,7 @@ Required properties:
* allwinner,sun6i-a31-display-frontend
* allwinner,sun7i-a20-display-frontend
* allwinner,sun8i-a33-display-frontend
+ * allwinner,sun9i-a80-display-frontend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@@ -226,6 +308,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-de2-mixer-0
+ * allwinner,sun8i-a83t-de2-mixer-1
+ * allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
@@ -256,7 +340,9 @@ Required properties:
* allwinner,sun7i-a20-display-engine
* allwinner,sun8i-a33-display-engine
* allwinner,sun8i-a83t-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
+ * allwinner,sun9i-a80-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
index baf9b34d20bf..b6a8cc0978cd 100644
--- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
+++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
@@ -74,8 +74,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = < 0x7e203000 0x20>,
- < 0x7e101098 0x02>;
+ reg = < 0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
diff --git a/Documentation/devicetree/bindings/dma/mtk-hsdma.txt b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt
new file mode 100644
index 000000000000..4bb317359dc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt
@@ -0,0 +1,33 @@
+MediaTek High-Speed DMA Controller
+==================================
+
+This device follows the generic DMA bindings defined in dma/dma.txt.
+
+Required properties:
+
+- compatible: Must be one of
+ "mediatek,mt7622-hsdma": for MT7622 SoC
+ "mediatek,mt7623-hsdma": for MT7623 SoC
+- reg: Should contain the register's base address and length.
+- interrupts: Should contain a reference to the interrupt used by this
+ device.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "hsdma" entries.
+- power-domains: Phandle to the power domain that the device is part of
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+ hsdma: dma-controller@1b007000 {
+ compatible = "mediatek,mt7623-hsdma";
+ reg = <0 0x1b007000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ethsys CLK_ETHSYS_HSDMA>;
+ clock-names = "hsdma";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
index 9cbf5d9df8fd..cf5b9e44432c 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
@@ -15,6 +15,10 @@ Required properties:
the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
remote proccessor i.e. execution environment.
+- num-channels : optional, indicates supported number of DMA channels in a
+ remotely controlled bam.
+- qcom,num-ees : optional, indicates supported number of Execution Environments
+ in a remotely controlled bam.
Example:
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index 891db41e9420..aadfb236d53a 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -18,6 +18,7 @@ Required Properties:
Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
+ - "renesas,dmac-r8a77470" (RZ/G1C)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
@@ -26,6 +27,7 @@ Required Properties:
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
- "renesas,dmac-r8a77970" (R-Car V3M)
+ - "renesas,dmac-r8a77980" (R-Car V3H)
- reg: base address and length of the registers block for the DMAC
diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
index f3d1f151ba80..9dc935e24e55 100644
--- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
@@ -11,6 +11,7 @@ Required Properties:
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
+ - "renesas,r8a77965-usb-dmac" (R-Car M3-N)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
new file mode 100644
index 000000000000..f237b7928283
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
@@ -0,0 +1,41 @@
+Synopsys DesignWare AXI DMA Controller
+
+Required properties:
+- compatible: "snps,axi-dma-1.01a"
+- reg: Address range of the DMAC registers. This should include
+ all of the per-channel registers.
+- interrupt: Should contain the DMAC interrupt number.
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device.
+- dma-channels: Number of channels supported by hardware.
+- snps,dma-masters: Number of AXI masters supported by the hardware.
+- snps,data-width: Maximum AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+- snps,priority: Priority of channel. Array size is equal to the number of
+ dma-channels. Priority value must be programmed within [0:dma-channels-1]
+ range. (0 - minimum priority)
+- snps,block-size: Maximum block size supported by the controller channel.
+ Array size is equal to the number of dma-channels.
+
+Optional properties:
+- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
+ in this property. If this property is missing the maximum AXI burst length
+ supported by DMAC is used. [1:256]
+
+Example:
+
+dmac: dma-controller@80000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x80000 0x400>;
+ clocks = <&core_clk>, <&cfgr_clk>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+
+ dma-channels = <4>;
+ snps,dma-masters = <2>;
+ snps,data-width = <3>;
+ snps,block-size = <4096 4096 4096 4096>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+};
diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
index 0b55718bf889..c5f519097204 100644
--- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
+++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
@@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
0x1: medium
0x2: high
0x3: very high
-4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
- dependent:
- -bit 0-1: Fifo threshold
+4. A 32bit bitfield value specifying DMA features which are device dependent:
+ -bit 0-1: DMA FIFO threshold selection
0x0: 1/4 full FIFO
0x1: 1/2 full FIFO
0x2: 3/4 full FIFO
0x3: full FIFO
+
Example:
usart1: serial@40011000 {
diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
index abfae1beca2b..61d833abafbf 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.txt
+++ b/Documentation/devicetree/bindings/eeprom/at24.txt
@@ -41,12 +41,16 @@ Required properties:
"nxp",
"ramtron",
"renesas",
+ "rohm",
"st",
Some vendors use different model names for chips which are just
variants of the above. Known such exceptions are listed below:
+ "nxp,se97b" - the fallback is "atmel,24c02",
"renesas,r1ex24002" - the fallback is "atmel,24c02"
+ "renesas,r1ex24128" - the fallback is "atmel,24c128"
+ "rohm,br24t01" - the fallback is "atmel,24c01"
- reg: The I2C address of the EEPROM.
diff --git a/Documentation/devicetree/bindings/fsi/fsi.txt b/Documentation/devicetree/bindings/fsi/fsi.txt
new file mode 100644
index 000000000000..ab516c673a4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/fsi/fsi.txt
@@ -0,0 +1,151 @@
+FSI bus & engine generic device tree bindings
+=============================================
+
+The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
+engines within those slaves. However, we have a facility to match devicetree
+nodes to probed engines. This allows for fsi engines to expose non-probeable
+busses, which are then exposed by the device tree. For example, an FSI engine
+that is an I2C master - the I2C bus can be described by the device tree under
+the engine's device tree node.
+
+FSI masters may require their own DT nodes (to describe the master HW itself);
+that requirement is defined by the master's implementation, and is described by
+the fsi-master-* binding specifications.
+
+Under the masters' nodes, we can describe the bus topology using nodes to
+represent the FSI slaves and their slave engines. As a basic outline:
+
+ fsi-master {
+ /* top-level of FSI bus topology, bound to an FSI master driver and
+ * exposes an FSI bus */
+
+ fsi-slave@<link,id> {
+ /* this node defines the FSI slave device, and is handled
+ * entirely with FSI core code */
+
+ fsi-slave-engine@<addr> {
+ /* this node defines the engine endpoint & address range, which
+ * is bound to the relevant fsi device driver */
+ ...
+ };
+
+ fsi-slave-engine@<addr> {
+ ...
+ };
+
+ };
+ };
+
+Note that since the bus is probe-able, some (or all) of the topology may
+not be described; this binding only provides an optional facility for
+adding subordinate device tree nodes as children of FSI engines.
+
+FSI masters
+-----------
+
+FSI master nodes declare themselves as such with the "fsi-master" compatible
+value. It's likely that an implementation-specific compatible value will
+be needed as well, for example:
+
+ compatible = "fsi-master-gpio", "fsi-master";
+
+Since the master nodes describe the top-level of the FSI topology, they also
+need to declare the FSI-standard addressing scheme. This requires two cells for
+addresses (link index and slave ID), and no size:
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+An optional boolean property can be added to indicate that a particular master
+should not scan for connected devices at initialization time. This is
+necessary in cases where a scan could cause arbitration issues with other
+masters that may be present on the bus.
+
+ no-scan-on-init;
+
+FSI slaves
+----------
+
+Slaves are identified by a (link-index, slave-id) pair, so require two cells
+for an address identifier. Since these are not a range, no size cells are
+required. For an example, a slave on link 1, with ID 2, could be represented
+as:
+
+ cfam@1,2 {
+ reg = <1 2>;
+ [...];
+ }
+
+Each slave provides an address-space, under which the engines are accessible.
+That address space has a maximum of 23 bits, so we use one cell to represent
+addresses and sizes in the slave address space:
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+FSI engines (devices)
+---------------------
+
+Engines are identified by their address under the slaves' address spaces. We
+use a single cell for address and size. Engine nodes represent the endpoint
+FSI device, and are passed to those FSI device drivers' ->probe() functions.
+
+For example, for a slave using a single 0x400-byte page starting at address
+0xc00:
+
+ engine@c00 {
+ reg = <0xc00 0x400>;
+ };
+
+
+Full example
+------------
+
+Here's an example that illustrates:
+ - an FSI master
+ - connected to an FSI slave
+ - that contains an engine that is an I2C master
+ - connected to an I2C EEPROM
+
+The FSI master may be connected to additional slaves, and slaves may have
+additional engines, but they don't necessarily need to be describe in the
+device tree if no extra platform information is required.
+
+ /* The GPIO-based FSI master node, describing the top level of the
+ * FSI bus
+ */
+ gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* A FSI slave (aka. CFAM) at link 0, ID 0. */
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* FSI engine at 0xc00, using a single page. In this example,
+ * it's an I2C master controller, so subnodes describe the
+ * I2C bus.
+ */
+ i2c-controller@c00 {
+ reg = <0xc00 0x400>;
+
+ /* Engine-specific data. In this case, we're describing an
+ * I2C bus, so we're conforming to the generic I2C binding
+ */
+ compatible = "some-vendor,fsi-i2c-controller";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* I2C endpoint device: an Atmel EEPROM */
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt
new file mode 100644
index 000000000000..93d98d09d92b
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt
@@ -0,0 +1,97 @@
+Spreadtrum EIC controller bindings
+
+The EIC is the abbreviation of external interrupt controller, which can
+be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
+one is in digital chip, and another one is in PMIC. The digital chip EIC
+controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
+EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
+module.
+
+The EIC-debounce sub-module provides up to 8 source input signal
+connections. A debounce mechanism is used to capture the input signals'
+stable status (millisecond resolution) and a single-trigger mechanism
+is introduced into this sub-module to enhance the input event detection
+reliability. In addition, this sub-module's clock can be shut off
+automatically to reduce power dissipation. Moreover the debounce range
+is from 1ms to 4s with a step size of 1ms. The input signal will be
+ignored if it is asserted for less than 1 ms.
+
+The EIC-latch sub-module is used to latch some special power down signals
+and generate interrupts, since the EIC-latch does not depend on the APB
+clock to capture signals.
+
+The EIC-async sub-module uses a 32kHz clock to capture the short signals
+(microsecond resolution) to generate interrupts by level or edge trigger.
+
+The EIC-sync is similar with GPIO's input function, which is a synchronized
+signal input register. It can generate interrupts by level or edge trigger
+when detecting input signals.
+
+Required properties:
+- compatible: Should be one of the following:
+ "sprd,sc9860-eic-debounce",
+ "sprd,sc9860-eic-latch",
+ "sprd,sc9860-eic-async",
+ "sprd,sc9860-eic-sync",
+ "sprd,sc27xx-eic".
+- reg: Define the base and range of the I/O address space containing
+ the GPIO controller registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the gpio number and
+ the second cell is used to specify optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <2>. Specifies the number of cells needed
+ to encode interrupt source.
+- interrupts: Should be the port interrupt shared by all the gpios.
+
+Example:
+ eic_debounce: gpio@40210000 {
+ compatible = "sprd,sc9860-eic-debounce";
+ reg = <0 0x40210000 0 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_latch: gpio@40210080 {
+ compatible = "sprd,sc9860-eic-latch";
+ reg = <0 0x40210080 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_async: gpio@402100a0 {
+ compatible = "sprd,sc9860-eic-async";
+ reg = <0 0x402100a0 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_sync: gpio@402100c0 {
+ compatible = "sprd,sc9860-eic-sync";
+ reg = <0 0x402100c0 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmic_eic: gpio@300 {
+ compatible = "sprd,sc27xx-eic";
+ reg = <0x300>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt b/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt
deleted file mode 100644
index 170194af3027..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Axis ETRAX FS General I/O controller bindings
-
-Required properties:
-
-- compatible: one of:
- - "axis,etraxfs-gio"
- - "axis,artpec3-gio"
-- reg: Physical base address and length of the controller's registers.
-- #gpio-cells: Should be 3
- - The first cell is the gpio offset number.
- - The second cell is reserved and is currently unused.
- - The third cell is the port number (hex).
-- gpio-controller: Marks the device node as a GPIO controller.
-
-Example:
-
- gio: gpio@b001a000 {
- compatible = "axis,etraxfs-gio";
- reg = <0xb001a000 0x1000>;
- gpio-controller;
- #gpio-cells = <3>;
- };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
index 0d0158728f89..d2a937682836 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
@@ -16,6 +16,8 @@ Required properties:
nxp,pca9574
nxp,pca9575
nxp,pca9698
+ nxp,pcal6524
+ nxp,pcal9555a
maxim,max7310
maxim,max7312
maxim,max7313
diff --git a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt
new file mode 100644
index 000000000000..eca97d45388f
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt
@@ -0,0 +1,28 @@
+Spreadtrum GPIO controller bindings
+
+The controller's registers are organized as sets of sixteen 16-bit
+registers with each set controlling a bank of up to 16 pins. A single
+interrupt is shared for all of the banks handled by the controller.
+
+Required properties:
+- compatible: Should be "sprd,sc9860-gpio".
+- reg: Define the base and range of the I/O address space containing
+the GPIO controller registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the gpio number and
+the second cell is used to specify optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <2>. Specifies the number of cells needed
+to encode interrupt source.
+- interrupts: Should be the port interrupt shared by all the gpios.
+
+Example:
+ ap_gpio: gpio@40280000 {
+ compatible = "sprd,sc9860-gpio";
+ reg = <0 0x40280000 0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt
deleted file mode 100644
index 528f5ef5a893..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-ImgTec TZ1090 PDC GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "img,tz1090-pdc-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
- region. This starts at and cover the SOC_GPIO_CONTROL registers.
-
-- gpio-controller: Specifies that the node is a gpio controller.
-
-- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should have the following values.
- <[phandle of the gpio controller node]
- [PDC gpio number]
- [gpio flags]>
-
- Values for gpio specifier:
- - GPIO number: a value in the range 0 to 6.
- - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the following flags are supported:
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
-
-Optional properties:
-- gpio-ranges: Mapping to pin controller pins (as described in
- Documentation/devicetree/bindings/gpio/gpio.txt)
-
-- interrupts: Individual syswake interrupts (other GPIOs cannot interrupt)
-
-
-Example:
-
- pdc_gpios: gpio-controller@2006500 {
- gpio-controller;
- #gpio-cells = <2>;
-
- compatible = "img,tz1090-pdc-gpio";
- reg = <0x02006500 0x100>;
-
- interrupt-parent = <&pdc>;
- interrupts = <8 IRQ_TYPE_NONE>, /* Syswake 0 */
- <9 IRQ_TYPE_NONE>, /* Syswake 1 */
- <10 IRQ_TYPE_NONE>; /* Syswake 2 */
- gpio-ranges = <&pdc_pinctrl 0 0 7>;
- };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt
deleted file mode 100644
index b05a90e0ab29..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-ImgTec TZ1090 GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "img,tz1090-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
- region.
-
-- #address-cells: Should be 1 (for bank subnodes)
-
-- #size-cells: Should be 0 (for bank subnodes)
-
-- Each bank of GPIOs should have a subnode to represent it.
-
- Bank subnode required properties:
- - reg: Index of bank in the range 0 to 2.
-
- - gpio-controller: Specifies that the node is a gpio controller.
-
- - #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should have the following values.
- <[phandle of the gpio controller node]
- [gpio number within the gpio bank]
- [gpio flags]>
-
- Values for gpio specifier:
- - GPIO number: a value in the range 0 to 29.
- - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the following flags are supported:
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
-
- Bank subnode optional properties:
- - gpio-ranges: Mapping to pin controller pins (as described in
- Documentation/devicetree/bindings/gpio/gpio.txt)
-
- - interrupts: Interrupt for the entire bank
-
- - interrupt-controller: Specifies that the node is an interrupt controller
-
- - #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by
- client nodes should have the following values.
- <[phandle of the interurupt controller]
- [gpio number within the gpio bank]
- [irq flags]>
-
- Values for irq specifier:
- - GPIO number: a value in the range 0 to 29
- - IRQ flags: value to describe edge and level triggering, as defined in
- <dt-bindings/interrupt-controller/irq.h>. Only the following flags are
- supported:
- IRQ_TYPE_EDGE_RISING
- IRQ_TYPE_EDGE_FALLING
- IRQ_TYPE_EDGE_BOTH
- IRQ_TYPE_LEVEL_HIGH
- IRQ_TYPE_LEVEL_LOW
-
-
-
-Example:
-
- gpios: gpio-controller@2005800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "img,tz1090-gpio";
- reg = <0x02005800 0x90>;
-
- /* bank 0 with an interrupt */
- gpios0: bank@0 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- reg = <0>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 30>;
- interrupt-controller;
- };
-
- /* bank 2 without interrupt */
- gpios2: bank@2 {
- #gpio-cells = <2>;
- reg = <2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 60 30>;
- };
- };
-
-
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index b5de08e3b1a2..a7c31de29362 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using
first 18 GPIOs, at local offset 0 .. 17, are in use.
If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
-additional bitmask is needed to specify which GPIOs are actually in use,
-and which are dummies. The bindings for this case has not yet been
-specified, but should be specified if/when such hardware appears.
+additional set of tuples is needed to specify which GPIOs are unusable, with
+the gpio-reserved-ranges binding. This property indicates the start and size
+of the GPIOs that can't be used.
Optionally, a GPIO controller may have a "gpio-line-names" property. This is
an array of strings defining the names of the GPIO lines going out of the
@@ -178,6 +178,7 @@ gpio-controller@00000000 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <18>;
+ gpio-reserved-ranges = <0 4>, <12 2>;
gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
"Row A", "Row B", "Row C", "Row D", "NMI button",
diff --git a/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt b/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
new file mode 100644
index 000000000000..20fc72d9e61e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
@@ -0,0 +1,27 @@
+Nintendo Wii (Hollywood) GPIO controller
+
+Required properties:
+- compatible: "nintendo,hollywood-gpio
+- reg: Physical base address and length of the controller's registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted).
+
+Optional properties:
+- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
+ interrupt.
+- interrupt-parent: phandle of the parent interrupt controller.
+
+Example:
+
+ GPIO: gpio@d8000c0 {
+ #gpio-cells = <2>;
+ compatible = "nintendo,hollywood-gpio";
+ reg = <0x0d8000c0 0x40>;
+ gpio-controller;
+ ngpios = <24>;
+ }
diff --git a/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt b/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt
new file mode 100644
index 000000000000..ce97265e23ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt
@@ -0,0 +1,30 @@
+Raspberry Pi GPIO expander
+
+The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The
+firmware exposes a mailbox interface that allows the ARM core to control the
+GPIO lines on the expander.
+
+The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi
+firmware node.
+
+Required properties:
+
+- compatible : Should be "raspberrypi,firmware-gpio"
+- gpio-controller : Marks the device node as a gpio controller
+- #gpio-cells : Should be two. The first cell is the pin number, and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+
+Example:
+
+firmware: firmware-rpi {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index ad876548ab5d..c1f65d1dac1d 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ + allwinner,sun8i-h3-mali
+ allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
index a777477e4547..4a7811ecd954 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
@@ -13,7 +13,9 @@ Required properties:
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
+ "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
+ "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
index 224390999e81..fc7e17802746 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
@@ -13,6 +13,7 @@ Required properties:
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
+ - "renesas,iic-r8a77965" (R-Car M3-N)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
compatible device)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
new file mode 100644
index 000000000000..72f4a2f0fedc
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
@@ -0,0 +1,29 @@
+Socionext SynQuacer I2C
+
+Required properties:
+- compatible : Must be "socionext,synquacer-i2c"
+- reg : Offset and length of the register set for the device
+- interrupts : A single interrupt specifier
+- #address-cells : Must be <1>;
+- #size-cells : Must be <0>;
+- clock-names : Must contain "pclk".
+- clocks : Must contain an entry for each name in clock-names.
+ (See the common clock bindings.)
+
+Optional properties:
+- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
+ Fast modes are supported, possible values are 100000 and
+ 400000.
+
+Example :
+
+ i2c@51210000 {
+ compatible = "socionext,synquacer-i2c";
+ reg = <0x51210000 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "pclk";
+ clocks = <&clk_i2c>;
+ clock-frequency = <400000>;
+ };
diff --git a/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt b/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt
new file mode 100644
index 000000000000..7a6313913923
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt
@@ -0,0 +1,48 @@
+* X-Powers AXP ADC bindings
+
+Required properties:
+ - compatible: should be one of:
+ - "x-powers,axp209-adc",
+ - "x-powers,axp221-adc",
+ - "x-powers,axp813-adc",
+ - #io-channel-cells: should be 1,
+
+Example:
+
+&axp22x {
+ adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+};
+
+ADC channels and their indexes per variant:
+
+AXP209
+------
+ 0 | acin_v
+ 1 | acin_i
+ 2 | vbus_v
+ 3 | vbus_i
+ 4 | pmic_temp
+ 5 | gpio0_v
+ 6 | gpio1_v
+ 7 | ipsout_v
+ 8 | batt_v
+ 9 | batt_chrg_i
+10 | batt_dischrg_i
+
+AXP22x
+------
+ 0 | pmic_temp
+ 1 | batt_v
+ 2 | batt_chrg_i
+ 3 | batt_dischrg_i
+
+AXP813
+------
+ 0 | pmic_temp
+ 1 | gpio0_v
+ 2 | batt_v
+ 3 | batt_chrg_i
+ 4 | batt_dischrg_i
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
index 911492da48f3..ed7520d1d051 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt
@@ -32,6 +32,10 @@ Optional properties:
to "clock" property. Frequency must be a multiple of the rcc
clock frequency. If not, SPI CLKOUT frequency will not be
accurate.
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration
+ nodes to set pins in mode of operation for dfsdm
+ on external pin.
Contents of a STM32 DFSDM child nodes:
--------------------------------------
@@ -68,8 +72,8 @@ Optional properties:
- st,adc-channel-types: Single-ended channel input type.
- "SPI_R": SPI with data on rising edge (default)
- "SPI_F": SPI with data on falling edge
- - "MANCH_R": manchester codec, rising edge = logic 0
- - "MANCH_F": manchester codec, falling edge = logic 1
+ - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1
+ - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0
- st,adc-channel-clk-src: Conversion clock source.
- "CLKIN": external SPI clock (CLKIN x)
- "CLKOUT": internal SPI clock (CLKOUT) (default)
diff --git a/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt b/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt
new file mode 100644
index 000000000000..f9b2eef946aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt
@@ -0,0 +1,27 @@
+* Analog Devices AD5272 digital potentiometer
+
+The node for this device must be a child node of a I2C controller, hence
+all mandatory properties for your controller must be specified. See directory:
+
+ Documentation/devicetree/bindings/i2c
+
+for more details.
+
+Required properties:
+ - compatible: Must be one of the following, depending on the model:
+ adi,ad5272-020
+ adi,ad5272-050
+ adi,ad5272-100
+ adi,ad5274-020
+ adi,ad5274-100
+
+Optional properties:
+ - reset-gpios: GPIO specification for the RESET input. This is an
+ active low signal to the AD5272.
+
+Example:
+ad5272: potentiometer@2f {
+ reg = <0x2F>;
+ compatible = "adi,ad5272-020";
+ reset-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
+};
diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
new file mode 100644
index 000000000000..0b05812001f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt
@@ -0,0 +1,28 @@
+* Melexis MLX90632 contactless Infra Red temperature sensor
+
+Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632
+
+There are various applications for the Infra Red contactless temperature sensor
+and MLX90632 is most suitable for consumer applications where measured object
+temperature is in range between -20 to 200 degrees Celsius with relative error
+of measurement below 1 degree Celsius in object temperature range for
+industrial applications. Since it can operate and measure ambient temperature
+in range of -20 to 85 degrees Celsius it is suitable also for outdoor use.
+
+Be aware that electronics surrounding the sensor can increase ambient
+temperature. MLX90632 can be calibrated to reduce the housing effect via
+already existing EEPROM parameters.
+
+Since measured object emissivity effects Infra Red energy emitted, emissivity
+should be set before requesting the object temperature.
+
+Required properties:
+ - compatible: should be "melexis,mlx90632"
+ - reg: the I2C address of the sensor (default 0x3a)
+
+Example:
+
+mlx90632@3a {
+ compatible = "melexis,mlx90632";
+ reg = <0x3a>;
+};
diff --git a/Documentation/devicetree/bindings/input/gpio-keys.txt b/Documentation/devicetree/bindings/input/gpio-keys.txt
index a94940481e55..996ce84352cb 100644
--- a/Documentation/devicetree/bindings/input/gpio-keys.txt
+++ b/Documentation/devicetree/bindings/input/gpio-keys.txt
@@ -26,6 +26,14 @@ Optional subnode-properties:
If not specified defaults to 5.
- wakeup-source: Boolean, button can wake-up the system.
(Legacy property supported: "gpio-key,wakeup")
+ - wakeup-event-action: Specifies whether the key should wake the
+ system when asserted, when deasserted, or both. This property is
+ only valid for keys that wake up the system (e.g., when the
+ "wakeup-source" property is also provided).
+ Supported values are defined in linux-event-codes.h:
+ EV_ACT_ASSERTED - asserted
+ EV_ACT_DEASSERTED - deasserted
+ EV_ACT_ANY - both asserted and deasserted
- linux,can-disable: Boolean, indicates that button is connected
to dedicated (not shared) interrupt which can be disabled to
suppress events from the button.
diff --git a/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt b/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt
new file mode 100644
index 000000000000..43ef770dfeb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt
@@ -0,0 +1,22 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings
+
+RAVE SP input device is a "MFD cell" device corresponding to power
+button functionality of RAVE Supervisory Processor. It is expected
+that its Device Tree node is specified as a child of the node
+corresponding to the parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+
+- compatible: Should be "zii,rave-sp-pwrbutton"
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ pwrbutton {
+ compatible = "zii,rave-sp-pwrbutton";
+ };
+ }
diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
new file mode 100644
index 000000000000..f4b4193d830e
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
@@ -0,0 +1,19 @@
+* Andestech Internal Vector Interrupt Controller
+
+The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
+suitable for a simpler SoC platform not requiring a more sophisticated and
+bigger External Vector Interrupt Controller.
+
+
+Main node required properties:
+
+- compatible : should at least contain "andestech,ativic32".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
+
+Examples:
+ intc: interrupt-controller {
+ compatible = "andestech,ativic32";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/axis,crisv32-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/axis,crisv32-intc.txt
deleted file mode 100644
index e8b123b0a5e6..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/axis,crisv32-intc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* CRISv32 Interrupt Controller
-
-Interrupt controller for the CRISv32 SoCs.
-
-Main node required properties:
-
-- compatible : should be:
- "axis,crisv32-intc"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The type shall be a <u32> and the value shall be 1.
-- reg: physical base address and size of the intc registers map.
-
-Example:
-
- intc: interrupt-controller {
- compatible = "axis,crisv32-intc";
- reg = <0xb001c000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
-
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
new file mode 100644
index 000000000000..b47a8a02b17b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -0,0 +1,22 @@
+Microsemi Ocelot SoC ICPU Interrupt Controller
+
+Required properties:
+
+- compatible : should be "mscc,ocelot-icpu-intr"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+- interrupt-parent : phandle of the CPU interrupt controller.
+- interrupts : Specifies the CPU interrupt the controller is connected to.
+
+Example:
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
new file mode 100644
index 000000000000..0b2c97ddb520
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
@@ -0,0 +1,78 @@
+PDC interrupt controller
+
+Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
+Power Domain Controller (PDC) that is on always-on domain. In addition to
+providing power control for the power domains, the hardware also has an
+interrupt controller that can be used to help detect edge low interrupts as
+well detect interrupts when the GIC is non-operational.
+
+GIC is parent interrupt controller at the highest level. Platform interrupt
+controller PDC is next in hierarchy, followed by others. Drivers requiring
+wakeup capabilities of their device interrupts routed through the PDC, must
+specify PDC as their interrupt controller and request the PDC port associated
+with the GIC interrupt. See example below.
+
+Properties:
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should contain "qcom,<soc>-pdc"
+ - "qcom,sdm845-pdc": For SDM845
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Specifies the base physical address for PDC hardware.
+
+- interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Specifies the number of cells needed to encode an interrupt
+ source.
+ Must be 2.
+ The first element of the tuple is the PDC pin for the
+ interrupt.
+ The second element is the trigger type.
+
+- interrupt-parent:
+ Usage: required
+ Value type: <phandle>
+ Definition: Specifies the interrupt parent necessary for hierarchical
+ domain to operate.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <bool>
+ Definition: Identifies the node as an interrupt controller.
+
+- qcom,pdc-ranges:
+ Usage: required
+ Value type: <u32 array>
+ Definition: Specifies the PDC pin offset and the number of PDC ports.
+ The tuples indicates the valid mapping of valid PDC ports
+ and their hwirq mapping.
+ The first element of the tuple is the starting PDC port.
+ The second element is the GIC hwirq number for the PDC port.
+ The third element is the number of interrupts in sequence.
+
+Example:
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sdm845-pdc";
+ reg = <0xb220000 0x30000>;
+ qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+DT binding of a device that wants to use the GIC SPI 514 as a wakeup
+interrupt, must do -
+
+ wake-device {
+ interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
+the qcom,pdc-ranges property.
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
index 1fd5d69647ca..ffadb7c6f1f3 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
@@ -11,6 +11,8 @@ Required Properties:
the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
+ - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
+ - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
@@ -19,7 +21,8 @@ Required Properties:
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
- - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
+ - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
+ IPMMU.
- reg: Base address and size of the IPMMU registers.
- interrupts: Specifiers for the MMU fault interrupts. For instances that
diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
index 2098f7732264..6ecefea1c6f9 100644
--- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt
@@ -14,6 +14,11 @@ Required properties:
"single-master" device, and needs no additional information
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
+- clocks : A list of clocks required for the IOMMU to be accessible by
+ the host CPU.
+- clock-names : Should contain the following:
+ "iface" - Main peripheral bus clock (PCLK/HCL) (required)
+ "aclk" - AXI bus clock (required)
Optional properties:
- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
@@ -27,5 +32,7 @@ Example:
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
};
diff --git a/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt
new file mode 100644
index 000000000000..d98a9bf45d6c
--- /dev/null
+++ b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt
@@ -0,0 +1,25 @@
+* Aspeed KCS (Keyboard Controller Style) IPMI interface
+
+The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
+(Baseboard Management Controllers) and the KCS interface can be
+used to perform in-band IPMI communication with their host.
+
+Required properties:
+- compatible : should be one of
+ "aspeed,ast2400-kcs-bmc"
+ "aspeed,ast2500-kcs-bmc"
+- interrupts : interrupt generated by the controller
+- kcs_chan : The LPC channel number in the controller
+- kcs_addr : The host CPU IO map address
+
+
+Example:
+
+ kcs3: kcs3@0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ kcs_chan = <3>;
+ kcs_addr = <0xCA2>;
+ status = "okay";
+ };
diff --git a/Documentation/devicetree/bindings/jailhouse.txt b/Documentation/devicetree/bindings/jailhouse.txt
new file mode 100644
index 000000000000..2901c25ff340
--- /dev/null
+++ b/Documentation/devicetree/bindings/jailhouse.txt
@@ -0,0 +1,8 @@
+Jailhouse non-root cell device tree bindings
+--------------------------------------------
+
+When running in a non-root Jailhouse cell (partition), the device tree of this
+platform shall have a top-level "hypervisor" node with the following
+properties:
+
+- compatible = "jailhouse,cell"
diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
new file mode 100644
index 000000000000..3e5b4537407d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt
@@ -0,0 +1,51 @@
+Hisilicon Hi3660 Mailbox Controller
+
+Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
+are passed between processors, including application & communication
+processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
+by using MMIO registers; it supports maximum to 8 words message.
+
+Controller
+----------
+
+Required properties:
+- compatible: : Shall be "hisilicon,hi3660-mbox"
+- reg: : Offset and length of the device's register set
+- #mbox-cells: : Must be 3
+ <&phandle channel dst_irq ack_irq>
+ phandle : Label name of controller
+ channel : Channel number
+ dst_irq : Remote interrupt vector
+ ack_irq : Local interrupt vector
+
+- interrupts: : Contains the two IRQ lines for mailbox.
+
+Example:
+
+mailbox: mailbox@e896b000 {
+ compatible = "hisilicon,hi3660-mbox";
+ reg = <0x0 0xe896b000 0x0 0x1000>;
+ interrupts = <0x0 0xc0 0x4>,
+ <0x0 0xc1 0x4>;
+ #mbox-cells = <3>;
+};
+
+Client
+------
+
+Required properties:
+- compatible : See the client docs
+- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
+ Cells must match 'mbox-cells' (See Controller docs above)
+
+Optional properties
+- mbox-names : Name given to channels seen in the 'mboxes' property.
+
+Example:
+
+stub_clock: stub_clock@e896b500 {
+ compatible = "hisilicon,hi3660-stub-clk";
+ reg = <0x0 0xe896b500 0x0 0x0100>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 13 3 0>;
+};
diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Documentation/devicetree/bindings/mailbox/mailbox.txt
index be05b9746c69..af8ecee2ac68 100644
--- a/Documentation/devicetree/bindings/mailbox/mailbox.txt
+++ b/Documentation/devicetree/bindings/mailbox/mailbox.txt
@@ -23,6 +23,11 @@ Required property:
Optional property:
- mbox-names: List of identifier strings for each mailbox channel.
+- shmem : List of phandle pointing to the shared memory(SHM) area between the
+ users of these mailboxes for IPC, one for each mailbox. This shared
+ memory can be part of any memory reserved for the purpose of this
+ communication between the mailbox client and the remote.
+
Example:
pwr_cntrl: power {
@@ -30,3 +35,26 @@ Example:
mbox-names = "pwr-ctrl", "rpc";
mboxes = <&mailbox 0 &mailbox 1>;
};
+
+Example with shared memory(shmem):
+
+ sram: sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x50000000 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50000000 0x10000>;
+
+ cl_shmem: shmem@0 {
+ compatible = "client-shmem";
+ reg = <0x0 0x200>;
+ };
+ };
+
+ client@2e000000 {
+ ...
+ mboxes = <&mailbox 0>;
+ shmem = <&cl_shmem>;
+ ..
+ };
diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt
index 2865d04e4030..90eb74cc1993 100644
--- a/Documentation/devicetree/bindings/media/coda.txt
+++ b/Documentation/devicetree/bindings/media/coda.txt
@@ -7,8 +7,9 @@ called VPU (Video Processing Unit).
Required properties:
- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
(a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
- (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
- (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
+ (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
+ (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
+ (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
- reg: should be register base and length as documented in the
SoC reference manual
- interrupts : Should contain the VPU interrupt. For CODA960,
diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.txt b/Documentation/devicetree/bindings/media/i2c/adv7604.txt
index 9cbd92eb5d05..dcf57e7c60eb 100644
--- a/Documentation/devicetree/bindings/media/i2c/adv7604.txt
+++ b/Documentation/devicetree/bindings/media/i2c/adv7604.txt
@@ -13,7 +13,11 @@ Required Properties:
- "adi,adv7611" for the ADV7611
- "adi,adv7612" for the ADV7612
- - reg: I2C slave address
+ - reg: I2C slave addresses
+ The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
+ main I2C ports. Each map has it own I2C address and acts as a standard
+ slave device on the I2C bus. The main address is mandatory, others are
+ optional and revert to defaults if not specified.
- hpd-gpios: References to the GPIOs that control the HDMI hot-plug
detection pins, one per HDMI input. The active flag indicates the GPIO
@@ -35,6 +39,11 @@ Optional Properties:
- reset-gpios: Reference to the GPIO connected to the device's reset pin.
- default-input: Select which input is selected after reset.
+ - reg-names : Names of maps with programmable addresses.
+ It can contain any map needing a non-default address.
+ Possible maps names are :
+ "main", "avlink", "cec", "infoframe", "esdp", "dpp", "afe",
+ "rep", "edid", "hdmi", "test", "cp", "vdp"
Optional Endpoint Properties:
@@ -52,7 +61,12 @@ Example:
hdmi_receiver@4c {
compatible = "adi,adv7611";
- reg = <0x4c>;
+ /*
+ * The edid page will be accessible @ 0x66 on the I2C bus. All
+ * other maps will retain their default addresses.
+ */
+ reg = <0x4c>, <0x66>;
+ reg-names "main", "edid";
reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
diff --git a/Documentation/devicetree/bindings/media/i2c/ov2685.txt b/Documentation/devicetree/bindings/media/i2c/ov2685.txt
new file mode 100644
index 000000000000..625c4a8c0d53
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ov2685.txt
@@ -0,0 +1,41 @@
+* Omnivision OV2685 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: shall be "ovti,ov2685"
+- clocks: reference to the xvclk input clock
+- clock-names: shall be "xvclk"
+- avdd-supply: Analog voltage supply, 2.8 volts
+- dovdd-supply: Digital I/O voltage supply, 1.8 volts
+- dvdd-supply: Digital core voltage supply, 1.8 volts
+- reset-gpios: Low active reset gpio
+
+The device node shall contain one 'port' child node with an
+'endpoint' subnode for its digital output video port,
+in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+The endpoint optional property 'data-lanes' shall be "<1>".
+
+Example:
+&i2c7 {
+ ov2685: camera-sensor@3c {
+ compatible = "ovti,ov2685";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_24m_cam>;
+
+ clocks = <&cru SCLK_TESTCLKOUT1>;
+ clock-names = "xvclk";
+
+ avdd-supply = <&pp2800_cam>;
+ dovdd-supply = <&pp1800>;
+ dvdd-supply = <&pp1800>;
+ reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1>;
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/media/i2c/ov5695.txt b/Documentation/devicetree/bindings/media/i2c/ov5695.txt
new file mode 100644
index 000000000000..640a63717d96
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ov5695.txt
@@ -0,0 +1,41 @@
+* Omnivision OV5695 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: shall be "ovti,ov5695"
+- clocks: reference to the xvclk input clock
+- clock-names: shall be "xvclk"
+- avdd-supply: Analog voltage supply, 2.8 volts
+- dovdd-supply: Digital I/O voltage supply, 1.8 volts
+- dvdd-supply: Digital core voltage supply, 1.2 volts
+- reset-gpios: Low active reset gpio
+
+The device node shall contain one 'port' child node with an
+'endpoint' subnode for its digital output video port,
+in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+The endpoint optional property 'data-lanes' shall be "<1 2>".
+
+Example:
+&i2c7 {
+ ov5695: camera-sensor@36 {
+ compatible = "ovti,ov5695";
+ reg = <0x36>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_24m_cam>;
+
+ clocks = <&cru SCLK_TESTCLKOUT1>;
+ clock-names = "xvclk";
+
+ avdd-supply = <&pp2800_cam>;
+ dovdd-supply = <&pp1800>;
+ dvdd-supply = <&pp1250_cam>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+
+ port {
+ wcam_out: endpoint {
+ remote-endpoint = <&mipi_in_wcam>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/media/i2c/ov7670.txt b/Documentation/devicetree/bindings/media/i2c/ov7670.txt
index 826b6563b009..2c972a56f3cb 100644
--- a/Documentation/devicetree/bindings/media/i2c/ov7670.txt
+++ b/Documentation/devicetree/bindings/media/i2c/ov7670.txt
@@ -9,14 +9,21 @@ Required Properties:
- clocks: reference to the xclk input clock.
- clock-names: should be "xclk".
+Required Endpoint Properties:
+- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
+- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
+
Optional Properties:
- reset-gpios: reference to the GPIO connected to the resetb pin, if any.
Active is low.
- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
Active is high.
+- ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output
+ signal during horizontal blankings.
-The device node must contain one 'port' child node for its digital output
-video port, in accordance with the video interface bindings defined in
+The device node must contain one 'port' child node with one 'endpoint' child
+sub-node for its digital output video port, in accordance with the video
+interface bindings defined in:
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
@@ -34,8 +41,13 @@ Example:
assigned-clocks = <&pck0>;
assigned-clock-rates = <25000000>;
+ ov7670,pclk-hb-disable;
+
port {
ov7670_0: endpoint {
+ hsync-active = <0>;
+ vsync-active = <0>;
+
remote-endpoint = <&isi_0>;
};
};
diff --git a/Documentation/devicetree/bindings/media/i2c/ov9650.txt b/Documentation/devicetree/bindings/media/i2c/ov9650.txt
new file mode 100644
index 000000000000..506dfc52872a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ov9650.txt
@@ -0,0 +1,36 @@
+* Omnivision OV9650/OV9652 CMOS sensor
+
+Required Properties:
+- compatible: shall be one of
+ "ovti,ov9650"
+ "ovti,ov9652"
+- clocks: reference to the xvclk input clock.
+
+Optional Properties:
+- reset-gpios: reference to the GPIO connected to the resetb pin, if any.
+ Active is high.
+- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
+ Active is high.
+
+The device node shall contain one 'port' child node with one child 'endpoint'
+subnode for its digital output video port, in accordance with the video
+interface bindings defined in Documentation/devicetree/bindings/media/
+video-interfaces.txt.
+
+Example:
+
+&i2c0 {
+ ov9650: camera@30 {
+ compatible = "ovti,ov9650";
+ reg = <0x30>;
+ reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_HIGH>;
+ clocks = <&xclk>;
+
+ port {
+ ov9650_0: endpoint {
+ remote-endpoint = <&vcap1_in0>;
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt
new file mode 100644
index 000000000000..e76167999d76
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt
@@ -0,0 +1,178 @@
+Device-Tree bindings for the NXP TDA1997x HDMI receiver
+
+The TDA19971/73 are HDMI video receivers.
+
+The TDA19971 Video port output pins can be used as follows:
+ - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
+ - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
+ - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
+ - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
+ - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
+ - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
+ - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
+
+The TDA19973 Video port output pins can be used as follows:
+ - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
+ - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
+ - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
+
+The Video port output pins are mapped via 4-bit 'pin groups' allowing
+for a variety of connection possibilities including swapping pin order within
+pin groups. The video_portcfg device-tree property consists of register mapping
+pairs which map a chip-specific VP output register to a 4-bit pin group. If
+the pin group needs to be bit-swapped you can use the *_S pin-group defines.
+
+Required Properties:
+ - compatible :
+ - "nxp,tda19971" for the TDA19971
+ - "nxp,tda19973" for the TDA19973
+ - reg : I2C slave address
+ - interrupts : The interrupt number
+ - DOVDD-supply : Digital I/O supply
+ - DVDD-supply : Digital Core supply
+ - AVDD-supply : Analog supply
+ - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
+
+Optional Properties:
+ - nxp,audout-format : DAI bus format: "i2s" or "spdif".
+ - nxp,audout-width : width of audio output data bus (1-4).
+ - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
+ - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec
+ mclk.
+
+The port node shall contain one endpoint child node for its digital
+output video port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Optional Endpoint Properties:
+ The following three properties are defined in video-interfaces.txt and
+ are valid for the output parallel bus endpoint:
+ - hsync-active: Horizontal synchronization polarity. Defaults to active high.
+ - vsync-active: Vertical synchronization polarity. Defaults to active high.
+ - data-active: Data polarity. Defaults to active high.
+
+Examples:
+ - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_1p8v>;
+ DVDD-supply = <&reg_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same pixclk cycle.
+ */
+ nxp,vidout-portcfg =
+ /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_1p8v>;
+ DVDD-supply = <&reg_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
+ * and Y[11:4] across 16bits in the same pixclk cycle.
+ */
+ nxp,vidout-portcfg =
+ /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
+ /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
+ /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
+ < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
+ /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
+ < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
+ 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
+ hdmi-receiver@48 {
+ compatible = "nxp,tda19971";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tda1997x>;
+ reg = <0x48>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_1p8v>;
+ DVDD-supply = <&reg_1p8v>;
+ /* audio */
+ #sound-dai-cells = <0>;
+ nxp,audout-format = "i2s";
+ nxp,audout-layout = <0>;
+ nxp,audout-width = <16>;
+ nxp,audout-mclk-fs = <128>;
+ /*
+ * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
+ * 2 pixclk cycles.
+ */
+ nxp,vidout-portcfg =
+ /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
+ < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
+ /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
+ < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,
+
+ port {
+ tda1997x_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <16>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
index 19357d0bbe65..1ce7ff9449c5 100644
--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
+++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
@@ -56,7 +56,7 @@ Board setup example (vin1 composite video input)
------------------------------------------------
&i2c2 {
- status = "ok";
+ status = "okay";
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@@ -79,7 +79,7 @@ Board setup example (vin1 composite video input)
pinctrl-0 = <&vin1_pins>;
pinctrl-names = "default";
- status = "ok";
+ status = "okay";
port {
#address-cells = <1>;
diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt b/Documentation/devicetree/bindings/media/renesas,ceu.txt
new file mode 100644
index 000000000000..3fc66dfb192c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/renesas,ceu.txt
@@ -0,0 +1,81 @@
+Renesas Capture Engine Unit (CEU)
+----------------------------------------------
+
+The Capture Engine Unit is the image capture interface found in the Renesas
+SH Mobile and RZ SoCs.
+
+The interface supports a single parallel input with data bus width of 8 or 16
+bits.
+
+Required properties:
+- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
+ and RZ/A1M SoCs.
+- reg: Registers address base and size.
+- interrupts: The interrupt specifier.
+
+The CEU supports a single parallel input and should contain a single 'port'
+subnode with a single 'endpoint'. Connection to input devices are modeled
+according to the video interfaces OF bindings specified in:
+Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Optional endpoint properties applicable to parallel input bus described in
+the above mentioned "video-interfaces.txt" file are supported.
+
+- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
+ If property is not present, default is active high.
+- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
+ If property is not present, default is active high.
+
+Example:
+
+The example describes the connection between the Capture Engine Unit and an
+OV7670 image sensor connected to i2c1 interface.
+
+ceu: ceu@e8210000 {
+ reg = <0xe8210000 0x209c>;
+ compatible = "renesas,r7s72100-ceu";
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vio_pins>;
+
+ status = "okay";
+
+ port {
+ ceu_in: endpoint {
+ remote-endpoint = <&ov7670_out>;
+
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+};
+
+i2c1: i2c@fcfee400 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ ov7670: camera@21 {
+ compatible = "ovti,ov7670";
+ reg = <0x21>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vio_pins>;
+
+ reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov7670_out: endpoint {
+ remote-endpoint = <&ceu_in>;
+
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index d3404b5d4d17..aa54c8159d9f 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -13,6 +13,7 @@ Required properties:
(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
+ (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
diff --git a/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt
new file mode 100644
index 000000000000..fc5aa263abe5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt
@@ -0,0 +1,14 @@
+Sony CXD2880 DVB-T2/T tuner + demodulator driver SPI adapter
+
+Required properties:
+- compatible: Should be "sony,cxd2880".
+- reg: SPI chip select number for the device.
+- spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
+
+Example:
+
+cxd2880@0 {
+ compatible = "sony,cxd2880";
+ reg = <0>; /* CE0 */
+ spi-max-frequency = <55000000>; /* 55MHz */
+};
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+ if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <3000000>;
resets = <&apb0_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
index 621b41c79faa..44d71469c914 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -3,7 +3,9 @@
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
-of the EMIF IP and memory parts attached to it.
+of the EMIF IP and memory parts attached to it. Certain revisions
+of the EMIF controller also contain optional ECC support, which
+corrects one bit errors and detects two bit errors.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
@@ -11,6 +13,8 @@ Required properties:
compatible should be one of the following:
"ti,emif-am3352"
"ti,emif-am4372"
+ "ti,emif-dra7xx"
+ "ti,emif-keystone"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
@@ -22,6 +26,7 @@ Required properties:
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
+- interrupts : interrupt used by the controller
Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram : Phandles for generic sram driver nodes,
@@ -71,3 +76,9 @@ emif: emif@4c000000 {
sram = <&pm_sram_code
&pm_sram_data>;
};
+
+emif1: emif@4c000000 {
+ compatible = "ti,emif-dra7xx";
+ reg = <0x4c000000 0x200>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/Documentation/devicetree/bindings/metag/meta.txt b/Documentation/devicetree/bindings/metag/meta.txt
deleted file mode 100644
index f4457f57ab08..000000000000
--- a/Documentation/devicetree/bindings/metag/meta.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Meta Processor Binding
-
-This binding specifies what properties must be available in the device tree
-representation of a Meta Processor Core, which is the root node in the tree.
-
-Required properties:
-
- - compatible: Specifies the compatibility list for the Meta processor.
- The type shall be <string> and the value shall include "img,meta".
-
-Optional properties:
-
- - clocks: Clock consumer specifiers as described in
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
- - clock-names: Clock consumer names as described in
- Documentation/devicetree/bindings/clock/clock-bindings.txt.
-
-Clocks are identified by name. Valid clocks are:
-
- - "core": The Meta core clock from which the Meta timers are derived.
-
-* Examples
-
-/ {
- compatible = "toumaz,tz1090", "img,meta";
-
- clocks = <&meta_core_clk>;
- clock-names = "core";
-};
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index 514d82ced95b..34dd89087cff 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -109,9 +109,50 @@ lpc: lpc@1e789000 {
};
};
+BMC Node Children
+==================
+
+
Host Node Children
==================
+LPC Host Interface Controller
+-------------------
+
+The LPC Host Interface Controller manages functions exposed to the host such as
+LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+management and bus snoop configuration.
+
+Required properties:
+
+- compatible: One of:
+ "aspeed,ast2400-lpc-ctrl";
+ "aspeed,ast2500-lpc-ctrl";
+
+- reg: contains offset/length values of the host interface controller
+ memory regions
+
+- clocks: contains a phandle to the syscon node describing the clocks.
+ There should then be one cell representing the clock to use
+
+- memory-region: A phandle to a reserved_memory region to be used for the LPC
+ to AHB mapping
+
+- flash: A phandle to the SPI flash controller containing the flash to
+ be exposed over the LPC to AHB mapping
+
+Example:
+
+lpc-host@80 {
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+ };
+};
+
LPC Host Controller
-------------------
@@ -135,3 +176,24 @@ lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
+
+LPC reset control
+-----------------
+
+The UARTs present in the ASPEED SoC can have their resets tied to the reset
+state of the LPC bus. Some systems may chose to modify this configuration.
+
+Required properties:
+
+ - compatible: "aspeed,ast2500-lpc-reset" or
+ "aspeed,ast2400-lpc-reset"
+ - reg: offset and length of the IP in the LHC memory region
+ - #reset-controller indicates the number of reset cells expected
+
+Example:
+
+lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..ae15ec333542
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,43 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianness, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
diff --git a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt
new file mode 100644
index 000000000000..a0693b7145f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt
@@ -0,0 +1,40 @@
+* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile
+ Storage Host Controller
+
+Read synopsys-dw-mshc.txt for more details
+
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
+specific extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+Required Properties:
+- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+- clock-names: Should contain the following:
+ "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
+ "biu" - The biu clock described in synopsys-dw-mshc.txt.
+ "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
+ "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
+
+Example:
+
+ emmc: mmc@9830000 {
+ compatible = "hisilicon,hi3798cv200-dw-mshc";
+ reg = <0x9830000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_MMC_CIU_CLK>,
+ <&crg HISTB_MMC_BIU_CLK>,
+ <&crg HISTB_MMC_SAMPLE_CLK>,
+ <&crg HISTB_MMC_DRV_CLK>;
+ clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+ fifo-depth = <256>;
+ clock-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ bus-width = <8>;
+ };
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index 9b8017670870..f33467a54a05 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
+ "mediatek,mt7622-mmc": for MT7622 SoC
"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
- reg: physical base address of the controller and length
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index c6558785e61b..8ce49b255974 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -21,7 +21,7 @@ Required Properties:
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
Optional Properties:
-* clocks: from common clock binding: if ciu_drive and ciu_sample are
+* clocks: from common clock binding: if ciu-drive and ciu-sample are
specified in clock-names, should contain handles to these clocks.
* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt
@@ -29,7 +29,7 @@ Optional Properties:
to control the clock phases, "ciu-sample" is required for tuning high-
speed modes.
-* rockchip,default-sample-phase: The default phase to set ciu_sample at
+* rockchip,default-sample-phase: The default phase to set ciu-sample at
probing, low speeds or in case where all phases work at tuning time.
If not specified 0 deg will be used.
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index ef3e5f14067a..7e5e427a22ce 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -59,15 +59,6 @@ Optional properties:
is specified and the ciu clock is specified then we'll try to set the ciu
clock to this at probe time.
-* clock-freq-min-max (DEPRECATED): Minimum and Maximum clock frequency for card output
- clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
- (Use the "max-frequency" instead of "clock-freq-min-max".)
-
-* num-slots (DEPRECATED): specifies the number of slots supported by the controller.
- The number of physical slots actually used could be equal or less than the
- value specified by num-slots. If this property is not specified, the value
- of num-slot property is assumed to be 1.
-
* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
specified, the default value of the fifo size is determined from the
controller registers.
diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index d8685cb83325..2d5287eeed95 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -50,7 +50,6 @@ Required properties:
2: R7S72100
Optional properties:
-- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 63d4d626fbd5..483e9cfac1b1 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -39,3 +39,27 @@ qspi0: quadspi@40044000 {
....
};
};
+
+Example showing the usage of two SPI NOR devices:
+
+&qspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi2>;
+ status = "okay";
+
+ flash0: n25q256a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <0>;
+ };
+
+ flash1: n25q256a@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <1>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
index c08fb477b3c6..e0c790706b9b 100644
--- a/Documentation/devicetree/bindings/mtd/marvell-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
@@ -14,7 +14,10 @@ Required properties:
- #address-cells: shall be set to 1. Encode the NAND CS.
- #size-cells: shall be set to 0.
- interrupts: shall define the NAND controller interrupt.
-- clocks: shall reference the NAND controller clock.
+- clocks: shall reference the NAND controller clocks, the second one is
+ is only needed for the Armada 7K/8K SoCs
+- clock-names: mandatory if there is a second clock, in this case there
+ should be one clock named "core" and another one named "reg"
- marvell,system-controller: Set to retrieve the syscon node that handles
NAND controller related registers (only required with the
"marvell,armada-8k-nand[-controller]" compatibles).
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
index 4a0a48bf4ecb..232fa12e90ef 100644
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
@@ -41,6 +41,13 @@ additional (optional) property is defined:
- erase-size : The chip's physical erase block size in bytes.
+ The device tree may optionally contain endianness property.
+ little-endian or big-endian : It Represents the endianness that should be used
+ by the controller to properly read/write data
+ from/to the flash. If this property is missing,
+ the endianness is chosen by the system
+ (potentially based on extra configuration options).
+
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
deleted file mode 100644
index d4ee4da58463..000000000000
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-PXA3xx NAND DT bindings
-
-Required properties:
-
- - compatible: Should be set to one of the following:
- marvell,pxa3xx-nand
- marvell,armada370-nand
- marvell,armada-8k-nand
- - reg: The register base for the controller
- - interrupts: The interrupt to map
- - #address-cells: Set to <1> if the node includes partitions
- - marvell,system-controller: Set to retrieve the syscon node that handles
- NAND controller related registers (only required
- with marvell,armada-8k-nand compatible).
-
-Optional properties:
-
- - dmas: dma data channel, see dma.txt binding doc
- - marvell,nand-enable-arbiter: Set to enable the bus arbiter
- - marvell,nand-keep-config: Set to keep the NAND controller config as set
- by the bootloader
- - num-cs: Number of chipselect lines to use
- - nand-on-flash-bbt: boolean to enable on flash bbt option if
- not present false
- - nand-ecc-strength: number of bits to correct per ECC step
- - nand-ecc-step-size: number of data bytes covered by a single ECC step
-
-The following ECC strength and step size are currently supported:
-
- - nand-ecc-strength = <1>, nand-ecc-step-size = <512>
- - nand-ecc-strength = <4>, nand-ecc-step-size = <512>
- - nand-ecc-strength = <8>, nand-ecc-step-size = <512>
-
-Example:
-
- nand0: nand@43100000 {
- compatible = "marvell,pxa3xx-nand";
- reg = <0x43100000 90>;
- interrupts = <45>;
- dmas = <&pdma 97 0>;
- dma-names = "data";
- #address-cells = <1>;
-
- marvell,nand-enable-arbiter;
- marvell,nand-keep-config;
- num-cs = <1>;
-
- /* partitions (optional) */
- };
-
diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
index 5e13a5cdff03..0734f03bf3d3 100644
--- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
@@ -24,8 +24,8 @@ Optional properties:
- allwinner,rb : shall contain the native Ready/Busy ids.
or
- rb-gpios : shall contain the gpios used as R/B pins.
-- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
- "soft_bch" or "none")
+- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
+ "none")
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards b/Documentation/devicetree/bindings/nds32/andestech-boards
new file mode 100644
index 000000000000..f5d75693e3c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/andestech-boards
@@ -0,0 +1,40 @@
+Andestech(nds32) AE3XX Platform
+-----------------------------------------------------------------------------
+The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
+is composed of one Andestech(nds32) processor and AE3XX.
+
+Required properties (in root node):
+- compatible = "andestech,ae3xx";
+
+Example:
+/dts-v1/;
+/ {
+ compatible = "andestech,ae3xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+};
+
+Andestech(nds32) AG101P Platform
+-----------------------------------------------------------------------------
+AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
+processors to provide a cost-effective and high performance solution for
+majority of embedded systems in variety of application domains. Users may
+simply attach their IP on one of the system buses together with certain glue
+logics to complete a SoC solution for a specific application. With
+comprehensive simulation and design environments, users may evaluate the
+system performance of their applications and track bugs of their designs
+efficiently. The optional hardware development platform further provides real
+system environment for early prototyping and software/hardware co-development.
+
+Required properties (in root node):
+ compatible = "andestech,ag101p";
+
+Example:
+/dts-v1/;
+/ {
+ compatible = "andestech,ag101p";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+};
diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index 000000000000..da8ab8e7ae9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,28 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: "andestech,atl2c"
+ - reg : Physical base address and size of cache controller's memory mapped
+ - cache-unified : Specifies the cache is a unified cache.
+ - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+ cache-controller@e0500000 {
+ compatible = "andestech,atl2c";
+ reg = <0xe0500000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt
new file mode 100644
index 000000000000..6f9e311b6589
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/cpus.txt
@@ -0,0 +1,38 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should be "andestech,<core_name>", "andestech,nds32v3" as fallback.
+ Must contain "andestech,nds32v3" as the most generic value, in addition to
+ one of the following identifiers for a particular CPU core:
+ "andestech,n13"
+ "andestech,n15"
+ "andestech,d15"
+ "andestech,n10"
+ "andestech,d10"
+ - device_type
+ Usage: required
+ Value type: <string>
+ Definition: must be "cpu"
+ - reg: Contains CPU index.
+ - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+ cpus {
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "andestech,n13", "andestech,nds32v3";
+ reg = <0x0>;
+ clock-frequency = <60000000>
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index 8c033d48e2ba..60d50a2b0323 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -13,9 +13,18 @@ placed as a child node of an mdio device.
The properties described here are those specific to Marvell devices.
Additional required and optional properties can be found in dsa.txt.
+The compatibility string is used only to find an identification register,
+which is at a different MDIO base address in different switch families.
+- "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
+ 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
+ 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
+ 6341, 6350, 6351, 6352
+- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
+ 6190, 6190X, 6191, 6290, 6390, 6390X
+
Required properties:
- compatible : Should be one of "marvell,mv88e6085" or
- "marvell,mv88e6190"
+ "marvell,mv88e6190" as indicated above
- reg : Address on the MII bus for the switch.
Optional properties:
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
index 2974e63ba311..cfc376bc977a 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -10,6 +10,8 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt.
the boot program; should be used in cases where the MAC address assigned to
the device by the boot program is different from the "local-mac-address"
property;
+- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
+- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
the maximum frame size (there's contradiction in the Devicetree
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 594982c6b9f9..79bf352e659c 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -6,7 +6,11 @@ the definition of the PHY node in booting-without-of.txt for an example
of how to define a PHY.
Required properties:
- - reg : Offset and length of the register set for the device
+ - reg : Offset and length of the register set for the device, and optionally
+ the offset and length of the TBIPA register (TBI PHY address
+ register). If TBIPA register is not specified, the driver will
+ attempt to infer it from the register set specified (your mileage may
+ vary).
- compatible : Should define the compatible device type for the
mdio. Currently supported strings/devices are:
- "fsl,gianfar-tbi"
diff --git a/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt b/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt
new file mode 100644
index 000000000000..2aaef567c5be
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt
@@ -0,0 +1,23 @@
+* MCR20A IEEE 802.15.4 *
+
+Required properties:
+ - compatible: should be "nxp,mcr20a"
+ - spi-max-frequency: maximal bus speed, should be set to a frequency
+ lower than 9000000 depends sync or async operation mode
+ - reg: the chipselect index
+ - interrupts: the interrupt generated by the device. Non high-level
+ can occur deadlocks while handling isr.
+
+Optional properties:
+ - rst_b-gpio: GPIO spec for the RST_B pin
+
+Example:
+
+ mcr20a@0 {
+ compatible = "nxp,mcr20a";
+ spi-max-frequency = <9000000>;
+ reg = <0>;
+ interrupts = <17 2>;
+ interrupt-parent = <&gpio>;
+ rst_b-gpio = <&gpio 27 1>
+ };
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 27966ae741e0..457d5ae16f23 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -29,6 +29,7 @@ Optional properties for PHY child node:
- reset-gpios : Should specify the gpio for phy reset
- magic-packet : If present, indicates that the hardware supports waking
up via magic packet.
+- phy-handle : see ethernet.txt file in the same directory
Examples:
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 354dd9896bb5..61cada22ae6c 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -9,6 +9,7 @@ Required properties on all platforms:
- compatible: Depending on the platform this should be one of:
- "amlogic,meson6-dwmac"
- "amlogic,meson8b-dwmac"
+ - "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
@@ -19,13 +20,13 @@ Required properties on all platforms:
configuration (for example the PRG_ETHERNET register range
on Meson8b and newer)
-Required properties on Meson8b and newer:
+Required properties on Meson8b, Meson8m2, GXBB and newer:
- clock-names: Should contain the following:
- "stmmaceth" - see stmmac.txt
- "clkin0" - first parent clock of the internal mux
- "clkin1" - second parent clock of the internal mux
-Optional properties on Meson8b and newer:
+Optional properties on Meson8b, Meson8m2, GXBB and newer:
- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
by this driver) in nanoseconds. Allowed values
are: 0ns, 2ns, 4ns, 6ns.
diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt
new file mode 100644
index 000000000000..e55af7f0881a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nixge.txt
@@ -0,0 +1,32 @@
+* NI XGE Ethernet controller
+
+Required properties:
+- compatible: Should be "ni,xge-enet-2.00"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain tx and rx interrupt
+- interrupt-names: Should be "rx" and "tx"
+- phy-mode: See ethernet.txt file in the same directory.
+- phy-handle: See ethernet.txt file in the same directory.
+- nvmem-cells: Phandle of nvmem cell containing the MAC address
+- nvmem-cell-names: Should be "address"
+
+Examples (10G generic PHY):
+ nixge0: ethernet@40000000 {
+ compatible = "ni,xge-enet-2.00";
+ reg = <0x40000000 0x6000>;
+
+ nvmem-cells = <&eth1_addr>;
+ nvmem-cell-names = "address";
+
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
+ interrupt-parent = <&intc>;
+
+ phy-mode = "xgmii";
+ phy-handle = <&ethernet_phy1>;
+
+ ethernet_phy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index b4dc455eb155..c306f55d335b 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,etheravb-r8a7743" for the R8A7743 SoC.
- "renesas,etheravb-r8a7745" for the R8A7745 SoC.
+ - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
- "renesas,etheravb-r8a7790" for the R8A7790 SoC.
- "renesas,etheravb-r8a7791" for the R8A7791 SoC.
- "renesas,etheravb-r8a7792" for the R8A7792 SoC.
diff --git a/Documentation/devicetree/bindings/net/sff,sfp.txt b/Documentation/devicetree/bindings/net/sff,sfp.txt
index f1c441bedf68..929591d52ed6 100644
--- a/Documentation/devicetree/bindings/net/sff,sfp.txt
+++ b/Documentation/devicetree/bindings/net/sff,sfp.txt
@@ -33,6 +33,10 @@ Optional Properties:
Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high:
high Tx rate. Must not be present for SFF modules
+- maximum-power-milliwatt : Maximum module power consumption
+ Specifies the maximum power consumption allowable by a module in the
+ slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W.
+
Example #1: Direct serdes to SFP connection
sfp_eth3: sfp-eth3 {
@@ -40,6 +44,7 @@ sfp_eth3: sfp-eth3 {
i2c-bus = <&sfp_1g_i2c>;
los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <1000>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
index 270ea4efff13..96398cc2982f 100644
--- a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
+++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
@@ -9,6 +9,7 @@ Required properties:
- "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
- "socionext,uniphier-ld11-ave4" : for LD11 SoC
- "socionext,uniphier-ld20-ave4" : for LD20 SoC
+ - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC
- reg: Address where registers are mapped and size of region.
- interrupts: Should contain the MAC interrupt.
- phy-mode: See ethernet.txt in the same directory. Allow to choose
diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt
index 02c4353b5cf2..9ef9338aaee1 100644
--- a/Documentation/devicetree/bindings/net/ti,dp83867.txt
+++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt
@@ -25,6 +25,8 @@ Optional property:
software needs to take when this pin is
strapped in these modes. See data manual
for details.
+ - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
+ for applicable values.
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index f162c72b4e36..729f6747813b 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -11,17 +11,32 @@ Required properties:
"fsl,imx6ul-ocotp" (i.MX6UL),
"fsl,imx7d-ocotp" (i.MX7D/S),
followed by "syscon".
+- #address-cells : Should be 1
+- #size-cells : Should be 1
- reg: Should contain the register base and length.
- clocks: Should contain a phandle pointing to the gated peripheral clock.
Optional properties:
- read-only: disable write access
-Example:
+Optional Child nodes:
+
+- Data cells of ocotp:
+ Detailed bindings are described in bindings/nvmem/nvmem.txt
+Example:
ocotp: ocotp@21bc000 {
- compatible = "fsl,imx6q-ocotp", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx6sx-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_IIM>;
- read-only;
+ clocks = <&clks IMX6SX_CLK_OCOTP>;
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
index 20bc49b49799..3cb170896658 100644
--- a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -1,5 +1,5 @@
Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
-Secure Non-Volatile Storage.
+and i.MX7 Secure Non-Volatile Storage.
This DT node should be represented as a sub-node of a "syscon",
"simple-mfd" node.
@@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of the fallowing variants:
"fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
"fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
+ "fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S
Example:
snvs: snvs@020cc000 {
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
index c84bc027930b..760b4d740616 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
@@ -34,6 +34,7 @@ Required properties
Optional properties:
- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
+- vpcie-supply: The regulator in charge of PCIe port power.
- phys: List of phandle and phy mode specifier, should be 0.
- phy-names: Must be "phy".
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 3a6ce55dd310..20227a875ac8 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -78,7 +78,7 @@ Examples for MT7623:
#reset-cells = <1>;
};
- pcie: pcie-controller@1a140000 {
+ pcie: pcie@1a140000 {
compatible = "mediatek,mt7623-pcie";
device_type = "pci";
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
@@ -111,7 +111,6 @@ Examples for MT7623:
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
pcie@0,0 {
- device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -123,7 +122,6 @@ Examples for MT7623:
};
pcie@1,0 {
- device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -135,7 +133,6 @@ Examples for MT7623:
};
pcie@2,0 {
- device_type = "pci";
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -148,6 +145,7 @@ Examples for MT7623:
};
Examples for MT2712:
+
pcie: pcie@11700000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
@@ -169,7 +167,6 @@ Examples for MT2712:
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
- device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -189,7 +186,6 @@ Examples for MT2712:
};
pcie1: pcie@1,0 {
- device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -210,6 +206,7 @@ Examples for MT2712:
};
Examples for MT7622:
+
pcie: pcie@1a140000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
@@ -243,7 +240,6 @@ Examples for MT7622:
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
pcie0: pcie@0,0 {
- device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -263,7 +259,6 @@ Examples for MT7622:
};
pcie1: pcie@1,0 {
- device_type = "pci";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 3c9d321b3d3b..1fd703bd73e0 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -189,6 +189,10 @@
Value type: <phandle>
Definition: A phandle to the analog power supply for IC which generates
reference clock
+- vddpe-3v3-supply:
+ Usage: optional
+ Value type: <phandle>
+ Definition: A phandle to the PCIe endpoint power supply
- phys:
Usage: required for apq8084
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index 76ba3a61d1a3..1fb614e615da 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -1,13 +1,15 @@
* Renesas R-Car PCIe interface
Required properties:
-compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
+compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
+ "renesas,pcie-r8a7779" for the R8A7779 SoC;
"renesas,pcie-r8a7790" for the R8A7790 SoC;
"renesas,pcie-r8a7791" for the R8A7791 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
"renesas,pcie-r8a7796" for the R8A7796 SoC;
- "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
+ "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
+ RZ/G1 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/Documentation/devicetree/bindings/arm/ccn.txt b/Documentation/devicetree/bindings/perf/arm-ccn.txt
index 43b5a71a5a9d..43b5a71a5a9d 100644
--- a/Documentation/devicetree/bindings/arm/ccn.txt
+++ b/Documentation/devicetree/bindings/perf/arm-ccn.txt
diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
index a105494a0fc9..b84a02ebffdf 100644
--- a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
+++ b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
@@ -6,6 +6,10 @@ Required properties:
- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
Optional properties:
+- clocks: a phandle to the clock of this PHY
+- clock-names: must be "phy"
+- resets: a phandle to the reset line of this PHY
+- reset-names: must be "phy"
- phy-supply: see phy-bindings.txt in this directory
diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
new file mode 100644
index 000000000000..114947e1de3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
+
+Required properties:
+- compatible: Should be "amlogic,meson-gxl-usb3-phy"
+- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
+- reg: The base address and length of the registers
+- interrupts: the interrupt specifier for the OTG detection
+- clocks: phandles to the clocks for
+ - the USB3 PHY
+ - and peripheral mode/OTG detection
+- clock-names: must contain "phy" and "peripheral"
+- resets: phandle to the reset lines for:
+ - the USB3 PHY and
+ - peripheral mode/OTG detection
+- reset-names: must contain "phy" and "peripheral"
+
+Optional properties:
+- phy-supply: see phy-bindings.txt in this directory
+
+
+Example:
+ usb3_phy0: phy@78080 {
+ compatible = "amlogic,meson-gxl-usb3-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x78080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "phy", "peripheral";
+ resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
+ reset-names = "phy", "peripheral";
+ };
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
index a9aa79fb90ed..1aa6f2674af5 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
@@ -21,7 +21,9 @@ Required properties :
- timer: The timeout clock (clk_m). Present if phy_type == utmi.
- utmi-pads: The clock needed to access the UTMI pad control registers.
Present if phy_type == utmi.
- - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
+ - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
+ with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
+ "nvidia,function" pllp_out4).
Present if phy_type == ulpi, and ULPI link mode is in use.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt
new file mode 100644
index 000000000000..17b0c761370a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt
@@ -0,0 +1,59 @@
+HiSilicon STB PCIE/SATA/USB3 PHY
+
+Required properties:
+- compatible: Should be "hisilicon,hi3798cv200-combphy"
+- reg: Should be the address space for COMBPHY configuration and state
+ registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
+ PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
+- #phy-cells: Should be 1. The cell number is used to select the phy mode
+ as defined in <dt-bindings/phy/phy.h>.
+- clocks: The phandle to clock provider and clock specifier pair.
+- resets: The phandle to reset controller and reset specifier pair.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Optional properties:
+- hisilicon,fixed-mode: If the phy device doesn't support mode select
+ but a fixed mode setting, the property should be present to specify
+ the particular mode.
+- hisilicon,mode-select-bits: If the phy device support mode select,
+ this property should be present to specify the register bits in
+ peripheral controller, as a 3 integers tuple:
+ <register_offset bit_shift bit_mask>.
+
+Notes:
+- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
+ one of them should be present.
+- The device node should be a child of peripheral controller that contains
+ COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
+ Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
+ bindings.
+
+Examples:
+
+perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ combphy0: phy@850 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x850 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY0_CLK>;
+ resets = <&crg 0x188 4>;
+ hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+ };
+
+ combphy1: phy@858 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x858 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY1_CLK>;
+ resets = <&crg 0x188 12>;
+ hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
new file mode 100644
index 000000000000..0d70c8341095
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
@@ -0,0 +1,71 @@
+Device tree bindings for HiSilicon INNO USB2 PHY
+
+Required properties:
+- compatible: Should be one of the following strings:
+ "hisilicon,inno-usb2-phy",
+ "hisilicon,hi3798cv200-usb2-phy".
+- reg: Should be the address space for PHY configuration register in peripheral
+ controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
+- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
+ reference clock.
+- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
+ signal.
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+
+The INNO USB2 PHY device should be a child node of peripheral controller that
+contains the PHY configuration register, and each device suppports up to 2 PHY
+ports which are represented as child nodes of INNO USB2 PHY device.
+
+Required properties for PHY port node:
+- reg: The PHY port instance number.
+- #phy-cells: Defined by generic PHY bindings. Must be 0.
+- resets: The phandle and reset specifier pair for PHY port reset signal.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+
+perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ usb2_phy1: usb2-phy@120 {
+ compatible = "hisilicon,hi3798cv200-usb2-phy";
+ reg = <0x120 0x4>;
+ clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+ resets = <&crg 0xbc 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_phy1_port0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 8>;
+ };
+
+ usb2_phy1_port1: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 9>;
+ };
+ };
+
+ usb2_phy2: usb2-phy@124 {
+ compatible = "hisilicon,hi3798cv200-usb2-phy";
+ reg = <0x124 0x4>;
+ clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
+ resets = <&crg 0xbc 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_phy2_port0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 10>;
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt b/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt
new file mode 100644
index 000000000000..29427d4f047a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt
@@ -0,0 +1,29 @@
+Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY
+
+Required properties:
+- compatible Must be "motorola,mapphone-mdm6600"
+- enable-gpios GPIO to enable the USB PHY
+- power-gpios GPIO to power on the device
+- reset-gpios GPIO to reset the device
+- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for
+ normal mode versus USB flashing mode
+- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600
+- motorola,status-gpios Three GPIOs to read the power state of the MDM6600
+
+Example:
+
+usb-phy {
+ compatible = "motorola,mapphone-mdm6600";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+};
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
index 41e09ed2ca70..0d34b2b4a6b7 100644
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
@@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
- reg : offset and length of register shared by multiple ports,
exclude port's private register. It is needed on mt2701
and mt8173, but not on mt2712.
+ - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
+ calibrate
+ - mediatek,src-coef : coefficient for slew rate calibrate, depends on
+ SoC process
Required properties (port (child) node):
- reg : address and length of the register set for the port.
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
index 6ea867e3176f..960da7fcaa9e 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
@@ -14,25 +14,9 @@ Required properties:
- resets : a list of phandle + reset specifier pairs
- reset-names : string reset name, must be:
"uphy", "uphy-pipe", "uphy-tcphy"
- - extcon : extcon specifier for the Power Delivery
-Note, there are 2 type-c phys for RK3399, and they are almost identical, except
-these registers(description below), every register node contains 3 sections:
-offset, enable bit, write mask bit.
- - rockchip,typec-conn-dir : the register of type-c connector direction,
- for type-c phy0, it must be <0xe580 0 16>;
- for type-c phy1, it must be <0xe58c 0 16>;
- - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable
- control.
- for type-c phy0, it must be <0xe580 3 19>;
- for type-c phy1, it must be <0xe58c 3 19>;
- - rockchip,external-psm : the register of type-c phy external psm clock
- selection.
- for type-c phy0, it must be <0xe588 14 30>;
- for type-c phy1, it must be <0xe594 14 30>;
- - rockchip,pipe-status : the register of type-c phy pipe status.
- for type-c phy0, it must be <0xe5c0 0 0>;
- for type-c phy1, it must be <0xe5c0 16 16>;
+Optional properties:
+ - extcon : extcon specifier for the Power Delivery
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify dp or usb3 port,
@@ -43,6 +27,13 @@ Required nodes : a sub-node is required for each port the phy provides.
Required properties (port (child) node):
- #phy-cells : must be 0, See ./phy-bindings.txt for details.
+Deprecated properties, do not use in new device tree sources, these
+properties are determined by the compatible value:
+ - rockchip,typec-conn-dir
+ - rockchip,usb3tousb2-en
+ - rockchip,external-psm
+ - rockchip,pipe-status
+
Example:
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
@@ -58,10 +49,6 @@ Example:
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
- rockchip,typec-conn-dir = <0xe580 0 16>;
- rockchip,usb3tousb2-en = <0xe580 3 19>;
- rockchip,external-psm = <0xe588 14 30>;
- rockchip,pipe-status = <0xe5c0 0 0>;
tcphy0_dp: dp-port {
#phy-cells = <0>;
@@ -86,10 +73,6 @@ Example:
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
- rockchip,typec-conn-dir = <0xe58c 0 16>;
- rockchip,usb3tousb2-en = <0xe58c 3 19>;
- rockchip,external-psm = <0xe594 14 30>;
- rockchip,pipe-status = <0xe5c0 16 16>;
tcphy1_dp: dp-port {
#phy-cells = <0>;
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
new file mode 100644
index 000000000000..725ae71ae653
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
@@ -0,0 +1,73 @@
+STMicroelectronics STM32 USB HS PHY controller
+
+The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+switch. It controls PHY configuration and status, and the UTMI+ switch that
+selects either OTG or HOST controller for the second PHY port. It also sets
+PLL configuration.
+
+USBPHYC
+ |_ PLL
+ |
+ |_ PHY port#1 _________________ HOST controller
+ | _ |
+ | / 1|________________|
+ |_ PHY port#2 ----| |________________
+ | \_0| |
+ |_ UTMI switch_______| OTG controller
+
+
+Phy provider node
+=================
+
+Required properties:
+- compatible: must be "st,stm32mp1-usbphyc"
+- reg: address and length of the usb phy control register set
+- clocks: phandle + clock specifier for the PLL phy clock
+- #address-cells: number of address cells for phys sub-nodes, must be <1>
+- #size-cells: number of size cells for phys sub-nodes, must be <0>
+
+Optional properties:
+- assigned-clocks: phandle + clock specifier for the PLL phy clock
+- assigned-clock-parents: the PLL phy clock parent
+- resets: phandle + reset specifier
+
+Required nodes: one sub-node per port the controller provides.
+
+Phy sub-nodes
+==============
+
+Required properties:
+- reg: phy port index
+- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
+ see phy-bindings.txt in the same directory.
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
+ port#1 and must be <1> for PHY port#2, to select USB controller
+
+
+Example:
+ usbphyc: usb-phy@5a006000 {
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc_clk USBPHY_K>;
+ resets = <&rcc_rst USBPHY_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphyc_port0: usb-phy@0 {
+ reg = <0>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>
+ #phy-cells = <0>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ reg = <1>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>
+ #phy-cells = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index b6a9f2b92bab..dcf1b8f691d5 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -8,7 +8,8 @@ Required properties:
- compatible: compatible list, contains:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
- "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
+ "qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy.
- reg: offset and length of register set for PHY's common serdes block.
@@ -25,10 +26,13 @@ Required properties:
- clock-names: "cfg_ahb" for phy config clock,
"aux" for phy aux clock,
"ref" for 19.2 MHz ref clk,
+ "com_aux" for phy common block aux clock,
For "qcom,msm8996-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref".
+ For "qcom,qmp-v3-usb3-phy" must contain:
+ "aux", "cfg_ahb", "ref", "com_aux".
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
index aa0fcb05acb3..42c97426836e 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
@@ -4,7 +4,10 @@ Qualcomm QUSB2 phy controller
QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
+ - compatible: compatible list, contains
+ "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
+ "qcom,qusb2-v2-phy" for QUSB2 V2 PHY.
+
- reg: offset and length of the PHY register set.
- #phy-cells: must be 0.
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
index 99b651b33110..dbd137c079e2 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
@@ -8,6 +8,8 @@ Required properties:
SoC.
"renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
SoC.
+ "renesas,usb2-phy-r8a77965" if the device is a part of an
+ R8A77965 SoC.
"renesas,usb2-phy-r8a77995" if the device is a part of an
R8A77995 SoC.
"renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
index f94cea48f6b1..47dd296ecead 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
@@ -11,6 +11,8 @@ Required properties:
SoC.
"renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
SoC.
+ "renesas,r8a77965-usb3-phy" if the device is a part of an
+ R8A77965 SoC.
"renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible
device.
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index c1ce5a0a652e..07ca4ec4a745 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -11,6 +11,7 @@ Required properties:
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-a83t-usb-phy
* allwinner,sun8i-h3-usb-phy
+ * allwinner,sun8i-r40-usb-phy
* allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
new file mode 100644
index 000000000000..fb87c7d74f2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
@@ -0,0 +1,178 @@
+Actions Semi S900 Pin Controller
+
+This binding describes the pin controller found in the S900 SoC.
+
+Required Properties:
+
+- compatible: Should be "actions,s900-pinctrl"
+- reg: Should contain the register base address and size of
+ the pin controller.
+- clocks: phandle of the clock feeding the pin controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+Pinmux functions are available only for the pin groups while pinconf
+parameters are available for both pin groups and individual pins.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+Required Properties:
+
+- pins: An array of strings, each string containing the name of a pin.
+ These pins are used for selecting the pull control and schmitt
+ trigger parameters. The following are the list of pins
+ available:
+
+ eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
+ eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
+ sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
+ i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
+ pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
+ eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
+ lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
+ lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
+ lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
+ lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
+ sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
+ sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
+ spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
+ uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
+ uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
+ uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
+ i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
+ csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
+ csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
+ dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
+ csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
+ sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
+ nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
+ nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
+ nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
+ nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
+ nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
+ nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
+
+- groups: An array of strings, each string containing the name of a pin
+ group. These pin groups are used for selecting the pinmux
+ functions.
+
+ lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
+ sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
+ rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
+ rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
+ i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
+ pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
+ eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
+ eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
+ lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
+ spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
+ uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
+ sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
+ uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
+ csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
+ dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
+ nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
+ csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
+
+
+ These pin groups are used for selecting the drive strength
+ parameters.
+
+ sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
+ rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
+ rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
+ sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
+ i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
+ lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
+ sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
+ spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
+ uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
+
+ These pin groups are used for selecting the slew rate
+ parameters.
+
+ sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
+ rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
+ rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
+ i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
+ pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
+ spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
+ uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
+ sensor0_sr
+
+- function: An array of strings, each string containing the name of the
+ pinmux functions. These functions can only be selected by
+ the corresponding pin groups. The following are the list of
+ pinmux functions available:
+
+ eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
+ uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
+ pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
+ sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
+ usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
+ nand1, spdif, sirq0, sirq1, sirq2
+
+Optional Properties:
+
+- bias-bus-hold: No arguments. The specified pins should retain the previous
+ state value.
+- bias-high-impedance: No arguments. The specified pins should be configured
+ as high impedance.
+- bias-pull-down: No arguments. The specified pins should be configured as
+ pull down.
+- bias-pull-up: No arguments. The specified pins should be configured as
+ pull up.
+- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
+ pins
+- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
+ pins
+- slew-rate: Integer. Sets slew rate for the specified pins.
+ Valid values are:
+ <0> - Slow
+ <1> - Fast
+- drive-strength: Integer. Selects the drive strength for the specified
+ pins in mA.
+ Valid values are:
+ <2>
+ <4>
+ <8>
+ <12>
+
+Example:
+
+ pinctrl: pinctrl@e01b0000 {
+ compatible = "actions,s900-pinctrl";
+ reg = <0x0 0xe01b0000 0x0 0x1000>;
+ clocks = <&cmu CLK_GPIO>;
+
+ uart2-default: uart2-default {
+ pinmux {
+ groups = "lvds_oep_odn_mfp";
+ function = "uart2";
+ };
+ pinconf {
+ groups = "lvds_oep_odn_drv";
+ drive-strength = <12>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 09789fdfa749..ed5eb547afc8 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -27,6 +27,7 @@ Required properties:
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
+ "allwinner,sun50i-h6-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
index 47284f85ec80..678f5097058e 100644
--- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
@@ -19,8 +19,10 @@ Required subnode-properties:
Available functions and groups (function: group0, group1...):
gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
- spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
- uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
+ spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
+ uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
+ uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
+ uart5nocts
cpuclkout: cpuclkoutgrp0
udlclkout: udlclkoutgrp0
i2c1: i2c1grp0
@@ -32,12 +34,12 @@ Required subnode-properties:
spi0: spi0grp0
spi1: spi1grp0
pciedebug: pciedebuggrp0
- uart0: uart0grp0, uart0grp1
- uart1: uart1grp0
- uart2: uart2grp0, uart2grp1
+ uart0: uart0grp0, uart0grp1, uart0grp2
+ uart1: uart1grp0, uart1grp1
+ uart2: uart2grp0, uart2grp1, uart2grp2
uart3: uart3grp0
- uart4: uart4grp0
- uart5: uart5grp0
+ uart4: uart4grp0, uart4grp1
+ uart5: uart5grp0, uart5grp1, uart5nocts
nand: nandgrp0
sdio0: sdio0grp0
sdio1: sdio1grp0
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
new file mode 100644
index 000000000000..175e8939a301
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
@@ -0,0 +1,40 @@
+* Freescale i.MX6 SLL IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6sll-iomuxc"
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
+ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+ imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
+ the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
+ Reference Manual for detailed CONFIG settings.
+
+CONFIG bits definition:
+PAD_CTL_LVE (1 << 22)
+PAD_CTL_HYS (1 << 16)
+PAD_CTL_PUS_100K_DOWN (0 << 14)
+PAD_CTL_PUS_47K_UP (1 << 14)
+PAD_CTL_PUS_100K_UP (2 << 14)
+PAD_CTL_PUS_22K_UP (3 << 14)
+PAD_CTL_PUE (1 << 13)
+PAD_CTL_PKE (1 << 12)
+PAD_CTL_ODE (1 << 11)
+PAD_CTL_SPEED_LOW (0 << 6)
+PAD_CTL_SPEED_MED (1 << 6)
+PAD_CTL_SPEED_HIGH (3 << 6)
+PAD_CTL_DSE_DISABLE (0 << 3)
+PAD_CTL_DSE_260ohm (1 << 3)
+PAD_CTL_DSE_130ohm (2 << 3)
+PAD_CTL_DSE_87ohm (3 << 3)
+PAD_CTL_DSE_65ohm (4 << 3)
+PAD_CTL_DSE_52ohm (5 << 3)
+PAD_CTL_DSE_43ohm (6 << 3)
+PAD_CTL_DSE_37ohm (7 << 3)
+PAD_CTL_SRE_FAST (1 << 0)
+PAD_CTL_SRE_SLOW (0 << 0)
+
+Refer to imx6sll-pinfunc.h in device tree source folder for all available
+imx6sll PIN_FUNC_ID.
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
deleted file mode 100644
index cf9ccdff4455..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
+++ /dev/null
@@ -1,127 +0,0 @@
-ImgTec TZ1090 PDC pin controller
-
-Required properties:
-- compatible: "img,tz1090-pdc-pinctrl"
-- reg: Should contain the register physical address and length of the
- SOC_GPIO_CONTROL registers in the PDC register region.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
-of subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function. For this reason, even seemingly boolean
-values are actually tristates in this binding: unspecified, off, or on.
-Unspecified is represented as an absent property, and off/on are represented as
-integer values 0 and 1.
-
-Required subnode-properties:
-- tz1090,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- tz1090,function: A string containing the name of the function to mux to the
- pin or group. Valid values for function names are listed below, including
- which pingroups can be muxed to them.
-- supported generic pinconfig properties (for further details see
- Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- - bias-disable
- - bias-high-impedance
- - bias-bus-hold
- - bias-pull-up
- - bias-pull-down
- - input-schmitt-enable
- - input-schmitt-disable
- - drive-strength: Integer, control drive strength of pins in mA.
- 2: 2mA
- 4: 4mA
- 8: 8mA
- 12: 12mA
- - low-power-enable: Flag, power-on-start weak pull-down for invalid power.
- - low-power-disable: Flag, power-on-start weak pull-down disabled.
-
-Note that many of these properties are only valid for certain specific pins
-or groups. See the TZ1090 TRM for complete details regarding which groups
-support which functionality. The Linux pinctrl driver may also be a useful
-reference.
-
-Valid values for pin and group names are:
-
- pins:
-
- These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
- bias-bus-hold (which can also be provided to any of the groups below to set
- it for all gpio pins in that group).
-
- gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
-
- mux groups:
-
- These all support function.
-
- gpio0
- pins: gpio0.
- function: ir_mod_stable_out.
- gpio1
- pins: gpio1.
- function: ir_mod_power_out.
-
- drive groups:
-
- These support input-schmitt-enable, input-schmitt-disable,
- drive-strength, low-power-enable, and low-power-disable.
-
- pdc
- pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
- ext_power.
-
-Example:
-
- pinctrl_pdc: pinctrl@2006500 {
- #gpio-range-cells = <3>;
- compatible = "img,tz1090-pdc-pinctrl";
- reg = <0x02006500 0x100>;
- };
-
-Example board file extracts:
-
- &pinctrl_pdc {
- pinctrl-names = "default";
- pinctrl-0 = <&syswake_default>;
-
- syswake_default: syswakes {
- syswake_cfg {
- tz1090,pins = "sys_wake0",
- "sys_wake1",
- "sys_wake2";
- pull-up;
- };
- };
- irmod_default: irmod {
- gpio0_cfg {
- tz1090,pins = "gpio0";
- tz1090,function = "ir_mod_stable_out";
- };
- gpio1_cfg {
- tz1090,pins = "gpio1";
- tz1090,function = "ir_mod_power_out";
- };
- };
- };
-
- ir: ir@2006200 {
- pinctrl-names = "default";
- pinctrl-0 = <&irmod_default>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
deleted file mode 100644
index 2dfd9a3fc1e4..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
+++ /dev/null
@@ -1,227 +0,0 @@
-ImgTec TZ1090 pin controller
-
-Required properties:
-- compatible: "img,tz1090-pinctrl"
-- reg: Should contain the register physical address and length of the pad
- configuration registers (CR_PADS_* and CR_IF_CTL0).
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-TZ1090's pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function. For this reason, even seemingly boolean
-values are actually tristates in this binding: unspecified, off, or on.
-Unspecified is represented as an absent property, and off/on are represented as
-integer values 0 and 1.
-
-Required subnode-properties:
-- tz1090,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- tz1090,function: A string containing the name of the function to mux to the
- pin or group. Valid values for function names are listed below, including
- which pingroups can be muxed to them.
-- supported generic pinconfig properties (for further details see
- Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- - bias-disable
- - bias-high-impedance
- - bias-bus-hold
- - bias-pull-up
- - bias-pull-down
- - input-schmitt-enable
- - input-schmitt-disable
- - drive-strength: Integer, control drive strength of pins in mA.
- 2: 2mA
- 4: 4mA
- 8: 8mA
- 12: 12mA
-
-
-Note that many of these properties are only valid for certain specific pins
-or groups. See the TZ1090 TRM for complete details regarding which groups
-support which functionality. The Linux pinctrl driver may also be a useful
-reference.
-
-Valid values for pin and group names are:
-
- gpio pins:
-
- These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
- bias-bus-hold (which can also be provided to any of the groups below to set
- it for all pins in that group).
-
- They also all support the some form of muxing. Any pins which are contained
- in one of the mux groups (see below) can be muxed only to the functions
- supported by the mux group. All other pins can be muxed to the "perip"
- function which enables them with their intended peripheral.
-
- Different pins in the same mux group cannot be muxed to different functions,
- however it is possible to mux only a subset of the pins in a mux group to a
- particular function and leave the remaining pins unmuxed. This is useful if
- the board connects certain pins in a group to other devices to be controlled
- by GPIO, and you don't want the usual peripheral to have any control of the
- pin.
-
- ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
- i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
- i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
- scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
- sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
- spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
- spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
- tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
- tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
- tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
- tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
- tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
- uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
-
- bias-high-impediance: supported.
- bias-pull-up: supported.
- bias-pull-down: supported.
- bias-bus-hold: supported.
- function: perip or those supported by pin's mux group.
-
- other pins:
-
- These other pins are part of various pin groups below, but can't be
- controlled as GPIOs. They do however support bias-high-impediance,
- bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
- to any of the groups below to set it for all pins in that group).
-
- clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
-
- bias-high-impediance: supported.
- bias-pull-up: supported.
- bias-pull-down: supported.
- bias-bus-hold: supported.
-
- mux groups:
-
- These all support function, and some support drive configs.
-
- afe
- pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
- ant_sel1, gain0, gain1, gain2, gain3, gain4,
- gain5, gain6, gain7.
- function: afe, ts_out_0.
- input-schmitt-enable: supported.
- input-schmitt-disable: supported.
- drive-strength: supported.
- pdm_d
- pins: pdm_d.
- function: pdm_dac, usb_vbus.
- sdh
- pins: sdh_cd, sdh_wp, sdh_clk_in.
- function: sdh, sdio.
- sdio
- pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
- sdio_d3.
- function: sdio, sdh.
- spi1_cs2
- pins: spi1_cs2.
- function: spi1_cs2, usb_vbus.
- tft
- pins: tft_red0, tft_red1, tft_red2, tft_red3,
- tft_red4, tft_red5, tft_red6, tft_red7,
- tft_green0, tft_green1, tft_green2, tft_green3,
- tft_green4, tft_green5, tft_green6, tft_green7,
- tft_blue0, tft_blue1, tft_blue2, tft_blue3,
- tft_blue4, tft_blue5, tft_blue6, tft_blue7,
- tft_vdden_gd, tft_panelclk, tft_blank_ls,
- tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
- tft_pwrsave.
- function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
- lcd_trace, phy_ringosc.
- input-schmitt-enable: supported.
- input-schmitt-disable: supported.
- drive-strength: supported.
-
- drive groups:
-
- These all support input-schmitt-enable, input-schmitt-disable,
- and drive-strength.
-
- jtag
- pins: tck, trst, tdi, tdo, tms.
- scb1
- pins: scb1_sdat, scb1_sclk.
- scb2
- pins: scb2_sdat, scb2_sclk.
- spi0
- pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
- spi1
- pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
- uart
- pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
- uart1_txd, uart1_rxd.
- drive_i2s
- pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
- i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
- drive_pdm
- pins: clk_out0, pdm_b, pdm_a.
- drive_scb0
- pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
- drive_sdio
- pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
- sdh_wp, sdh_cd, sdh_clk_in.
-
- convenience groups:
-
- These are just convenient groupings of pins and don't support any drive
- configs.
-
- uart0
- pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
- uart1
- pins: uart1_rxd, uart1_txd.
- scb0
- pins: scb0_sclk, scb0_sdat.
- i2s
- pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
- i2s_lrclk_out, i2s_mclk.
-
-Example:
-
- pinctrl: pinctrl@2005800 {
- #gpio-range-cells = <3>;
- compatible = "img,tz1090-pinctrl";
- reg = <0x02005800 0xe4>;
- };
-
-Example board file extract:
-
- &pinctrl {
- uart0_default: uart0 {
- uart0_cfg {
- tz1090,pins = "uart0_rxd",
- "uart0_txd";
- tz1090,function = "perip";
- };
- };
- tft_default: tft {
- tft_cfg {
- tz1090,pins = "tft";
- tz1090,function = "tft";
- };
- };
- };
-
- uart@2004b00 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_default>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
index 9c451c20dda4..a5a8322a31bd 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -45,6 +45,8 @@ Optional properties:
- first cell is the pin number
- second cell is used to specify flags.
- interrupt-controller: Marks the device node as a interrupt controller.
+- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
+ the IRQ output as open drain active low.
Optional device specific properties:
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index afa8a18ea11a..e7d6f81c227f 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -76,12 +76,12 @@ Examples:
...
{
- syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
- syscfg_pctl_b: syscfg_pctl_b@1020c020 {
+ syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
new file mode 100644
index 000000000000..665aadb5ea28
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
@@ -0,0 +1,176 @@
+Qualcomm SDM845 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+SDM845 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode.
+
+ Valid pins are:
+ gpio0-gpio149
+ Supports mux, bias and drive-strength
+
+ sdc2_clk, sdc2_cmd, sdc2_data
+ Supports bias and drive-strength
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+
+ gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
+ atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
+ atest_usb12, atest_usb13, atest_usb2, atest_usb20,
+ atest_usb21, atest_usb22, atest_usb23, audio_ref,
+ btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
+ cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
+ ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
+ gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
+ lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
+ mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
+ pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
+ pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
+ qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
+ qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
+ qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
+ qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
+ sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
+ tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
+ tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
+ tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
+ uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
+ uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
+ vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
+ wlan2_adc1,
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@3400000 {
+ compatible = "qcom,sdm845-pinctrl";
+ reg = <0x03400000 0xc00000>;
+ interrupts = <GIC_SPI 208 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ qup9_active: qup9-active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "qup9";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index bb1790e0b176..892d8fd7b700 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -15,7 +15,7 @@ Required Properties:
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
+ - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
@@ -24,7 +24,9 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
+ - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
+ - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 2c46f30b62c5..9a06e1fdbc42 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -11,6 +11,7 @@ Required properies:
"st,stm32f429-pinctrl"
"st,stm32f469-pinctrl"
"st,stm32f746-pinctrl"
+ "st,stm32f769-pinctrl"
"st,stm32h743-pinctrl"
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"
diff --git a/Documentation/devicetree/bindings/pmem/pmem-region.txt b/Documentation/devicetree/bindings/pmem/pmem-region.txt
new file mode 100644
index 000000000000..5cfa4f016a00
--- /dev/null
+++ b/Documentation/devicetree/bindings/pmem/pmem-region.txt
@@ -0,0 +1,65 @@
+Device-tree bindings for persistent memory regions
+-----------------------------------------------------
+
+Persistent memory refers to a class of memory devices that are:
+
+ a) Usable as main system memory (i.e. cacheable), and
+ b) Retain their contents across power failure.
+
+Given b) it is best to think of persistent memory as a kind of memory mapped
+storage device. To ensure data integrity the operating system needs to manage
+persistent regions separately to the normal memory pool. To aid with that this
+binding provides a standardised interface for discovering where persistent
+memory regions exist inside the physical address space.
+
+Bindings for the region nodes:
+-----------------------------
+
+Required properties:
+ - compatible = "pmem-region"
+
+ - reg = <base, size>;
+ The reg property should specificy an address range that is
+ translatable to a system physical address range. This address
+ range should be mappable as normal system memory would be
+ (i.e cacheable).
+
+ If the reg property contains multiple address ranges
+ each address range will be treated as though it was specified
+ in a separate device node. Having multiple address ranges in a
+ node implies no special relationship between the two ranges.
+
+Optional properties:
+ - Any relevant NUMA assocativity properties for the target platform.
+
+ - volatile; This property indicates that this region is actually
+ backed by non-persistent memory. This lets the OS know that it
+ may skip the cache flushes required to ensure data is made
+ persistent after a write.
+
+ If this property is absent then the OS must assume that the region
+ is backed by non-volatile memory.
+
+Examples:
+--------------------
+
+ /*
+ * This node specifies one 4KB region spanning from
+ * 0x5000 to 0x5fff that is backed by non-volatile memory.
+ */
+ pmem@5000 {
+ compatible = "pmem-region";
+ reg = <0x00005000 0x00001000>;
+ };
+
+ /*
+ * This node specifies two 4KB regions that are backed by
+ * volatile (normal) memory.
+ */
+ pmem@6000 {
+ compatible = "pmem-region";
+ reg = < 0x00006000 0x00001000
+ 0x00008000 0x00001000 >;
+ volatile;
+ };
+
diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index 8690f10426a3..ab399e559257 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -17,7 +17,9 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
+ - "renesas,r8a77965-sysc" (R-Car M3-N)
- "renesas,r8a77970-sysc" (R-Car V3M)
+ - "renesas,r8a77980-sysc" (R-Car V3H)
- "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
index e62d53d844cc..6d8980c18c34 100644
--- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
+++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
@@ -27,10 +27,13 @@ Optional properties:
it to an output when the power-off handler is called. If this optional
property is not specified, the GPIO is initialized as an output in its
inactive state.
+- timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is
+ specified, 3000 ms is used.
Examples:
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 4 0>;
+ timeout-ms = <3000>;
};
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 000000000000..1b4213eb3473
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,14 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+
+Example:
+ reset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt
index c24886676a60..41916f69902c 100644
--- a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt
+++ b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt
@@ -4,12 +4,12 @@ Required Properties:
- compatible, one of:
"x-powers,axp209-battery-power-supply"
"x-powers,axp221-battery-power-supply"
+ "x-powers,axp813-battery-power-supply"
-This node is a subnode of the axp20x/axp22x PMIC.
+This node is a subnode of its respective PMIC DT node.
-The AXP20X and AXP22X can read the battery voltage, charge and discharge
-currents of the battery by reading ADC channels from the AXP20X/AXP22X
-ADC.
+The supported devices can read the battery voltage, charge and discharge
+currents of the battery by reading ADC channels from the ADC.
Example:
diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
index 36afa322b04b..a3dc4b9fa11a 100644
--- a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
+++ b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
@@ -152,14 +152,7 @@ Nintendo Wii device tree
1.l) The General Purpose I/O (GPIO) controller node
- Represents the dual access 32 GPIO controller interface.
-
- Required properties:
-
- - #gpio-cells : <2>
- - compatible : should be "nintendo,hollywood-gpio"
- - reg : should contain the IPC registers location and length
- - gpio-controller
+ see Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
1.m) The control node
diff --git a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
new file mode 100644
index 000000000000..7d9d3f90641b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
@@ -0,0 +1,25 @@
+Ingenic JZ47xx PWM Controller
+=============================
+
+Required properties:
+- compatible: One of:
+ * "ingenic,jz4740-pwm"
+ * "ingenic,jz4770-pwm"
+ * "ingenic,jz4780-pwm"
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description
+ of the cells format.
+- clocks : phandle to the external clock.
+- clock-names : Should be "ext".
+
+
+Example:
+
+ pwm: pwm@10002000 {
+ compatible = "ingenic,jz4740-pwm";
+ reg = <0x10002000 0x1000>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&ext>;
+ clock-names = "ext";
+ };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
index f8338d11fd2b..bd23302e84be 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
@@ -7,6 +7,8 @@ See ../mfd/stm32-lptimer.txt for details about the parent node.
Required parameters:
- compatible: Must be "st,stm32-pwm-lp".
+- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
+ bindings defined in pwm.txt.
Optional properties:
- pinctrl-names: Set to "default".
@@ -18,6 +20,7 @@ Example:
...
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&lppwm1_pins>;
};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt
index 51ff54c8b8ef..2a1affbff45e 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt
@@ -7,6 +7,8 @@ Required properties:
- "allwinner,sun5i-a13-pwm"
- "allwinner,sun7i-a20-pwm"
- "allwinner,sun8i-h3-pwm"
+ - "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"
+ - "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format.
diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
index 74c118015980..35a3b9761ee5 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
@@ -2,6 +2,8 @@
Required Properties:
- compatible: should be "renesas,pwm-rcar" and one of the following.
+ - "renesas,pwm-r8a7743": for RZ/G1M
+ - "renesas,pwm-r8a7745": for RZ/G1E
- "renesas,pwm-r8a7778": for R-Car M1A
- "renesas,pwm-r8a7779": for R-Car H1
- "renesas,pwm-r8a7790": for R-Car H2
@@ -9,6 +11,7 @@ Required Properties:
- "renesas,pwm-r8a7794": for R-Car E2
- "renesas,pwm-r8a7795": for R-Car H3
- "renesas,pwm-r8a7796": for R-Car M3-W
+ - "renesas,pwm-r8a77965": for R-Car M3-N
- "renesas,pwm-r8a77995": for R-Car D3
- reg: base address and length of the registers block for the PWM.
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
@@ -17,13 +20,15 @@ Required Properties:
- pinctrl-0: phandle, referring to a default pin configuration node.
- pinctrl-names: Set to "default".
-Example: R8A7790 (R-Car H2) PWM Timer node
+Example: R8A7743 (RZ/G1M) PWM Timer node
pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
#pwm-cells = <2>;
- clocks = <&mstp5_clks R8A7790_CLK_PWM>;
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
};
diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
index 1aadc804dae4..d53a16715da6 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
@@ -3,10 +3,12 @@
Required Properties:
- compatible: should be one of the following.
- - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
+ - "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller.
- "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
+ - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
+ - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
- "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
- - "renesas,tpu": for generic R-Car TPU PWM controller.
+ - "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller.
- reg: Base address and length of each memory resource used by the PWM
controller hardware module.
@@ -18,10 +20,10 @@ Required Properties:
Please refer to pwm.txt in this directory for details of the common PWM bindings
used by client devices.
-Example: R8A7740 (R-Car A1) TPU controller node
+Example: R8A7740 (R-Mobile A1) TPU controller node
tpu: pwm@e6600000 {
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
- reg = <0xe6600000 0x100>;
+ reg = <0xe6600000 0x148>;
#pwm-cells = <3>;
};
diff --git a/Documentation/devicetree/bindings/regulator/88pg86x.txt b/Documentation/devicetree/bindings/regulator/88pg86x.txt
new file mode 100644
index 000000000000..13b7f49a2ea8
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/88pg86x.txt
@@ -0,0 +1,22 @@
+Marvell 88PG867/88PG868 voltage regulators
+
+Required properties:
+- compatible: one of "marvell,88pg867", "marvell,88pg868";
+- reg: I2C slave address.
+
+Optional subnodes for regulators: "buck1", "buck2", using common regulator
+bindings given in <Documentation/devicetree/bindings/regulator/regulator.txt>.
+
+Example:
+
+ pg868@19 {
+ compatible = "marvell,88pg868";
+ reg = <0x19>;
+
+ vcpu: buck1 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
index 4fae41d54798..0c2a6c8a1536 100644
--- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -2,6 +2,7 @@ Fixed Voltage regulators
Required properties:
- compatible: Must be "regulator-fixed";
+- regulator-name: Defined in regulator.txt as optional, but required here.
Optional properties:
- gpio: gpio to use for enable control
diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
index dd1ed789728e..1f496159e2bb 100644
--- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
@@ -2,6 +2,8 @@ GPIO controlled regulators
Required properties:
- compatible : Must be "regulator-gpio".
+- regulator-name : Defined in regulator.txt as optional, but required
+ here.
- states : Selection of available voltages and GPIO configs.
if there are no states, then use a fixed regulator
diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt
index 4e3dfb5b5f16..58a1d97972f5 100644
--- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt
@@ -23,7 +23,9 @@ Regulator nodes are identified by their compatible:
"qcom,rpm-pm8916-regulators"
"qcom,rpm-pm8941-regulators"
"qcom,rpm-pm8994-regulators"
+ "qcom,rpm-pm8998-regulators"
"qcom,rpm-pma8084-regulators"
+ "qcom,rpm-pmi8998-regulators"
- vdd_s1-supply:
- vdd_s2-supply:
@@ -131,6 +133,38 @@ Regulator nodes are identified by their compatible:
- vdd_s10-supply:
- vdd_s11-supply:
- vdd_s12-supply:
+- vdd_s13-supply:
+- vdd_l1_l27-supply:
+- vdd_l20_l24-supply:
+- vdd_l26-supply:
+- vdd_l2_l8_l17-supply:
+- vdd_l3_l11-supply:
+- vdd_l4_l5-supply:
+- vdd_l6-supply:
+- vdd_l7_l12_l14_l15-supply:
+- vdd_l9-supply:
+- vdd_l10_l23_l25-supply:
+- vdd_l13_l19_l21-supply:
+- vdd_l16_l28-supply:
+- vdd_l18_l22-supply:
+- vdd_lvs1_lvs2-supply:
+ Usage: optional (pmi8998 only)
+ Value type: <phandle>
+ Definition: reference to regulator supplying the input pin, as
+ described in the data sheet
+
+- vdd_s1-supply:
+- vdd_s2-supply:
+- vdd_s3-supply:
+- vdd_s4-supply:
+- vdd_s5-supply:
+- vdd_s6-supply:
+- vdd_s7-supply:
+- vdd_s8-supply:
+- vdd_s9-supply:
+- vdd_s10-supply:
+- vdd_s11-supply:
+- vdd_s12-supply:
- vdd_l1_l11-supply:
- vdd_l2_l3_l4_l27-supply:
- vdd_l5_l7-supply:
@@ -148,6 +182,12 @@ Regulator nodes are identified by their compatible:
Definition: reference to regulator supplying the input pin, as
described in the data sheet
+- vdd_bob-supply:
+ Usage: optional (pmi8998 only)
+ Value type: <phandle>
+ Definition: reference to regulator supplying the input pin, as
+ described in the data sheet
+
The regulator node houses sub-nodes for each regulator within the device. Each
sub-node is identified using the node's name, with valid values listed for each
of the pmics below.
@@ -169,11 +209,19 @@ pm8994:
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2
+pm8998:
+ s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4,
+ l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
+ l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2
+
pma8084:
s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
+pmi8998:
+ bob
+
The content of each sub-node is defined by the standard binding for regulators -
see regulator.txt.
diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index a8014f3ab8ba..294a0dae106a 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -26,7 +26,9 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
+ - "renesas,r8a77965-rst" (R-Car M3-N)
- "renesas,r8a77970-rst" (R-Car V3M)
+ - "renesas,r8a77980-rst" (R-Car V3H)
- "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.
diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 000000000000..b4edaf7c7ff3
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+=======================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
diff --git a/Documentation/devicetree/bindings/rng/imx-rng.txt b/Documentation/devicetree/bindings/rng/imx-rng.txt
new file mode 100644
index 000000000000..405c2b00ccb0
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/imx-rng.txt
@@ -0,0 +1,20 @@
+Freescale RNGA/RNGB/RNGC (Random Number Generator Versions A, B and C)
+
+Required properties:
+- compatible : should be one of
+ "fsl,imx21-rnga"
+ "fsl,imx31-rnga" (backward compatible with "fsl,imx21-rnga")
+ "fsl,imx25-rngb"
+ "fsl,imx35-rngc"
+- reg : offset and length of the register set of this block
+- interrupts : the interrupt number for the RNG block
+- clocks : the RNG clk source
+
+Example:
+
+rng@53fb0000 {
+ compatible = "fsl,imx25-rngb";
+ reg = <0x53fb0000 0x4000>;
+ interrupts = <22>;
+ clocks = <&trng_clk>;
+};
diff --git a/Documentation/devicetree/bindings/rng/imx-rngc.txt b/Documentation/devicetree/bindings/rng/imx-rngc.txt
deleted file mode 100644
index 93c7174a7bed..000000000000
--- a/Documentation/devicetree/bindings/rng/imx-rngc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Freescale RNGC (Random Number Generator Version C)
-
-The driver also supports version B, which is mostly compatible
-to version C.
-
-Required properties:
-- compatible : should be one of
- "fsl,imx25-rngb"
- "fsl,imx35-rngc"
-- reg : offset and length of the register set of this block
-- interrupts : the interrupt number for the RNGC block
-- clocks : the RNGC clk source
-
-Example:
-
-rng@53fb0000 {
- compatible = "fsl,imx25-rngb";
- reg = <0x53fb0000 0x4000>;
- interrupts = <22>;
- clocks = <&trng_clk>;
-};
diff --git a/Documentation/devicetree/bindings/rng/ks-sa-rng.txt b/Documentation/devicetree/bindings/rng/ks-sa-rng.txt
new file mode 100644
index 000000000000..b7a65b487901
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/ks-sa-rng.txt
@@ -0,0 +1,21 @@
+Keystone SoC Hardware Random Number Generator(HWRNG) Module
+
+On Keystone SoCs HWRNG module is a submodule of the Security Accelerator.
+
+- compatible: should be "ti,keystone-rng"
+- ti,syscon-sa-cfg: phandle to syscon node of the SA configuration registers.
+ This registers are shared between hwrng and crypto drivers.
+- clocks: phandle to the reference clocks for the subsystem
+- clock-names: functional clock name. Should be set to "fck"
+- reg: HWRNG module register space
+
+Example:
+/* K2HK */
+
+rng@24000 {
+ compatible = "ti,keystone-rng";
+ ti,syscon-sa-cfg = <&sa_config>;
+ clocks = <&clksa>;
+ clock-names = "fck";
+ reg = <0x24000 0x1000>;
+};
diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt
index 9cf7876ab434..ea434ce50f36 100644
--- a/Documentation/devicetree/bindings/rng/omap_rng.txt
+++ b/Documentation/devicetree/bindings/rng/omap_rng.txt
@@ -13,7 +13,12 @@ Required properties:
- interrupts : the interrupt number for the RNG module.
Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
- clocks: the trng clock source. Only mandatory for the
- "inside-secure,safexcel-eip76" compatible.
+ "inside-secure,safexcel-eip76" compatible, the second clock is
+ needed for the Armada 7K/8K SoCs
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for the second
+ one
+
Example:
/* AM335x */
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
index 47f04176f93b..1dfa7d51e006 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt
@@ -11,6 +11,10 @@ Required properties:
- interrupts : The designated IRQ line for the RNG
- clocks : The clock needed to enable the RNG
+Optional properties:
+- resets : The reset to properly start RNG
+- clock-error-detect : Enable the clock detection management
+
Example:
rng: rng@50060800 {
diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
new file mode 100644
index 000000000000..2e0be45193bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt
@@ -0,0 +1,28 @@
+ISL12026 I2C RTC/EEPROM
+
+ISL12026 is an I2C RTC/EEPROM combination device. The RTC and control
+registers respond at bus address 0x6f, and the EEPROM array responds
+at bus address 0x57. The canonical "reg" value will be for the RTC portion.
+
+Required properties supported by the device:
+
+ - "compatible": must be "isil,isl12026"
+ - "reg": I2C bus address of the device (always 0x6f)
+
+Optional properties:
+
+ - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
+ value for proper operation.
+
+ - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
+ value for proper operation.
+
+
+Example:
+
+ rtc@6f {
+ compatible = "isil,isl12026";
+ reg = <0x6f>;
+ isil,pwr-bsw = <0>;
+ isil,pwr-sbib = <1>;
+ }
diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
index df3bef7998fa..8c6659ed2cfc 100644
--- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -53,6 +53,13 @@ Main node required properties:
Optional main node properties:
- hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
"am-max-transmissions" limitation.
+ - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis,
+ preshoot, and boost attenuation readings for the board. They
+ are used to describe the signal attenuation of the board. These
+ values' range is 7600 to 12400, and used to represent -24dB to
+ 24dB.
+ The formula is "y = (x-10000)/10000". For example, 10478
+ means 4.78dB.
Example:
sas0: sas@c1000000 {
diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt
index dad3b2ec66d4..aeb6db4e35c3 100644
--- a/Documentation/devicetree/bindings/serial/8250.txt
+++ b/Documentation/devicetree/bindings/serial/8250.txt
@@ -24,6 +24,7 @@ Required properties:
- "ti,da830-uart"
- "aspeed,ast2400-vuart"
- "aspeed,ast2500-vuart"
+ - "nuvoton,npcm750-uart"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
diff --git a/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt b/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
deleted file mode 100644
index 048c3818c826..000000000000
--- a/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-ETRAX FS UART
-
-Required properties:
-- compatible : "axis,etraxfs-uart"
-- reg: offset and length of the register set for the device.
-- interrupts: device interrupt
-
-Optional properties:
-- {dtr,dsr,rng,dcd}-gpios: specify a GPIO for DTR/DSR/RI/DCD
- line respectively.
-
-Example:
-
-serial@b00260000 {
- compatible = "axis,etraxfs-uart";
- reg = <0xb0026000 0x1000>;
- interrupts = <68>;
- dtr-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
- rng-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&sysgpio 3 GPIO_ACTIVE_LOW>;
-};
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index cf504d0380ae..ad962f4ec3aa 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -43,6 +43,8 @@ Required properties:
- "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
- "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
- "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
+ - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART.
+ - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART.
- "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
- "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt
index d150b04a6229..9d3efed55deb 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt
+++ b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt
@@ -15,6 +15,8 @@ Required properties:
Optional properties:
- pinctrl: The reference on the pins configuration
- st,hw-flow-ctrl: bool flag to enable hardware flow control.
+- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low,
+ linux,rs485-enabled-at-boot-time: see rs485.txt.
- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt
- dma-names: "rx" and/or "tx"
diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt
new file mode 100644
index 000000000000..8dd7b3a7de65
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt
@@ -0,0 +1,16 @@
+Broadcom VCHIQ firmware services
+
+Required properties:
+
+- compatible: Should be "brcm,bcm2835-vchiq"
+- reg: Physical base address and length of the doorbell register pair
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+Example:
+
+mailbox@7e00b840 {
+ compatible = "brcm,bcm2835-vchiq";
+ reg = <0x7e00b840 0xf>;
+ interrupts = <0 2>;
+};
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 76bf45b893fa..d6fe16f094af 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -21,6 +21,8 @@ Required properties:
- "mediatek,mt2712-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
+ - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
+ - "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@@ -28,10 +30,11 @@ Required properties:
- clock, clock-names: clocks according to the common clock binding.
These are clocks which hardware needs to be
enabled before enabling certain power domains.
- Required clocks for MT2701: "mm", "mfg", "ethif"
+ Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622: "hif_sel"
+ Required clocks for MT7622A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
index 65783de0aedf..7bb0362828ec 100644
--- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
@@ -2,9 +2,8 @@
Required properties:
- compatible: "brcm,bcm2835-i2s"
-- reg: A list of base address and size entries:
- * The first entry should cover the PCM registers
- * The second entry should cover the PCM clock registers
+- reg: Should contain PCM registers location and length.
+- clocks: the (PCM) clock to use
- dmas: List of DMA controller phandle and DMA request line ordered pairs.
- dma-names: Identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
@@ -16,8 +15,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = <0x7e203000 0x20>,
- <0x7e101098 0x02>;
+ reg = <0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
diff --git a/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt
new file mode 100644
index 000000000000..0ae29de15bfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt
@@ -0,0 +1,42 @@
+Mediatek AFE PCM controller for mt6797
+
+Required properties:
+- compatible = "mediatek,mt6797-audio";
+- reg: register location and size
+- interrupts: should contain AFE interrupt
+- power-domains: should define the power domain
+- clocks: Must contain an entry for each entry in clock-names
+- clock-names: should have these clock names:
+ "infra_sys_audio_clk",
+ "infra_sys_audio_26m",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_sys_pll3_d4",
+ "top_sys_pll1_d4",
+ "top_clk26m_clk";
+
+Example:
+
+ afe: mt6797-afe-pcm@11220000 {
+ compatible = "mediatek,mt6797-audio";
+ reg = <0 0x11220000 0 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>;
+ clocks = <&infrasys CLK_INFRA_AUDIO>,
+ <&infrasys CLK_INFRA_AUDIO_26M>,
+ <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>,
+ <&topckgen CLK_TOP_MUX_AUDIO>,
+ <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&topckgen CLK_TOP_SYSPLL3_D4>,
+ <&topckgen CLK_TOP_SYSPLL1_D4>,
+ <&clk26m>;
+ clock-names = "infra_sys_audio_clk",
+ "infra_sys_audio_26m",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_sys_pll3_d4",
+ "top_sys_pll1_d4",
+ "top_clk26m_clk";
+ };
diff --git a/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt b/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt
new file mode 100644
index 000000000000..1d95a8840f19
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt
@@ -0,0 +1,14 @@
+MT6797 with MT6351 CODEC
+
+Required properties:
+- compatible: "mediatek,mt6797-mt6351-sound"
+- mediatek,platform: the phandle of MT6797 ASoC platform
+- mediatek,audio-codec: the phandles of MT6351 codec
+
+Example:
+
+ sound {
+ compatible = "mediatek,mt6797-mt6351-sound";
+ mediatek,audio-codec = <&mt6351_snd>;
+ mediatek,platform = <&afe>;
+ };
diff --git a/Documentation/devicetree/bindings/sound/rt5668.txt b/Documentation/devicetree/bindings/sound/rt5668.txt
new file mode 100644
index 000000000000..c88b96e7764b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5668.txt
@@ -0,0 +1,50 @@
+RT5668B audio CODEC
+
+This device supports I2C only.
+
+Required properties:
+
+- compatible : "realtek,rt5668b"
+
+- reg : The I2C address of the device.
+
+Optional properties:
+
+- interrupts : The CODEC's interrupt output.
+
+- realtek,dmic1-data-pin
+ 0: dmic1 is not used
+ 1: using GPIO2 pin as dmic1 data pin
+ 2: using GPIO5 pin as dmic1 data pin
+
+- realtek,dmic1-clk-pin
+ 0: using GPIO1 pin as dmic1 clock pin
+ 1: using GPIO3 pin as dmic1 clock pin
+
+- realtek,jd-src
+ 0: No JD is used
+ 1: using JD1 as JD source
+
+- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
+
+Pins on the device (for linking into audio routes) for RT5668B:
+
+ * DMIC L1
+ * DMIC R1
+ * IN1P
+ * HPOL
+ * HPOR
+
+Example:
+
+rt5668 {
+ compatible = "realtek,rt5668b";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
+ realtek,ldo1-en-gpios =
+ <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ realtek,dmic1-data-pin = <1>;
+ realtek,dmic1-clk-pin = <1>;
+ realtek,jd-src = <1>;
+};
diff --git a/Documentation/devicetree/bindings/sound/tscs42xx.txt b/Documentation/devicetree/bindings/sound/tscs42xx.txt
index 2ac2f0996697..7eea32e9d078 100644
--- a/Documentation/devicetree/bindings/sound/tscs42xx.txt
+++ b/Documentation/devicetree/bindings/sound/tscs42xx.txt
@@ -8,9 +8,15 @@ Required Properties:
- reg : <0x71> for analog mic
<0x69> for digital mic
+ - clock-names: Must one of the following "mclk1", "xtal", "mclk2"
+
+ - clocks: phandle of the clock that provides the codec sysclk
+
Example:
wookie: codec@69 {
compatible = "tempo,tscs42A2";
reg = <0x69>;
+ clock-names = "xtal";
+ clocks = <&audio_xtal>;
};
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 80710f0f0448..39806329c193 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -10,6 +10,7 @@ Required properties:
"renesas,msiof-r8a7794" (R-Car E2)
"renesas,msiof-r8a7795" (R-Car H3)
"renesas,msiof-r8a7796" (R-Car M3-W)
+ "renesas,msiof-r8a77965" (R-Car M3-N)
"renesas,msiof-sh73a0" (SH-Mobile AG5)
"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
"renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt
index a95603bcf6ff..52db562f17a4 100644
--- a/Documentation/devicetree/bindings/spi/spi-gpio.txt
+++ b/Documentation/devicetree/bindings/spi/spi-gpio.txt
@@ -1,18 +1,30 @@
SPI-GPIO devicetree bindings
+This represents a group of 3-n GPIO lines used for bit-banged SPI on dedicated
+GPIO lines.
+
Required properties:
- compatible: should be set to "spi-gpio"
- #address-cells: should be set to <0x1>
- ranges
- - gpio-sck: GPIO spec for the SCK line to use
- - gpio-miso: GPIO spec for the MISO line to use
- - gpio-mosi: GPIO spec for the MOSI line to use
+ - sck-gpios: GPIO spec for the SCK line to use
+ - miso-gpios: GPIO spec for the MISO line to use
+ - mosi-gpios: GPIO spec for the MOSI line to use
- cs-gpios: GPIOs to use for chipselect lines.
Not needed if num-chipselects = <0>.
- num-chipselects: Number of chipselect lines. Should be <0> if a single device
with no chip select is connected.
+Deprecated bindings:
+
+These legacy GPIO line bindings can alternatively be used to define the
+GPIO lines used, they should not be used in new device trees.
+
+ - gpio-sck: GPIO spec for the SCK line to use
+ - gpio-miso: GPIO spec for the MISO line to use
+ - gpio-mosi: GPIO spec for the MOSI line to use
+
Example:
spi {
@@ -20,9 +32,9 @@ Example:
#address-cells = <0x1>;
ranges;
- gpio-sck = <&gpio 95 0>;
- gpio-miso = <&gpio 98 0>;
- gpio-mosi = <&gpio 97 0>;
+ sck-gpios = <&gpio 95 0>;
+ miso-gpios = <&gpio 98 0>;
+ mosi-gpios = <&gpio 97 0>;
cs-gpios = <&gpio 125 0>;
num-chipselects = <1>;
diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 000000000000..4c9ea5989e35
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+------------------------------------------------------------------
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible : Should be "andestech,atcpit100"
+- reg : Address and length of the register set
+- interrupts : Reference to the timer interrupt
+- clocks : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2>;
+ clocks = <&apb>;
+ clock-names = "PCLK";
+};
diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt
index 2e3740f98c41..763a2808a95c 100644
--- a/Documentation/devicetree/bindings/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/trivial-devices.txt
@@ -75,6 +75,18 @@ maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
mcube,mc3230 mCube 3-axis 8-bit digital accelerometer
memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer
+microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k)
+microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k)
+microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k)
+microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k)
+microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k)
+microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k)
+microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k)
+microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k)
+microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k)
+microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k)
+microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k)
+microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k)
microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
new file mode 100644
index 000000000000..9a8b631904fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
@@ -0,0 +1,42 @@
+Amlogic Meson GX DWC3 USB SoC controller
+
+Required properties:
+- compatible: depending on the SoC this should contain one of:
+ * amlogic,meson-axg-dwc3
+ * amlogic,meson-gxl-dwc3
+- clocks: a handle for the "USB general" clock
+- clock-names: must be "usb_general"
+- resets: a handle for the shared "USB OTG" reset line
+- reset-names: must be "usb_otg"
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+PHY documentation is provided in the following places:
+- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
+- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
+
+Example device nodes:
+ usb0: usb@ff500000 {
+ compatible = "amlogic,meson-axg-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>;
+ clock-names = "usb_general";
+ resets = <&reset RESET_USB_OTG>;
+ reset-names = "usb_otg";
+
+ dwc3: dwc3@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk;
+ phys = <&usb3_phy>, <&usb2_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 44e8bab159ad..0dbd3083e7dd 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -57,6 +57,22 @@ Optional properties:
- snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
register for post-silicon frame length adjustment when the
fladj_30mhz_sdbnd signal is invalid or incorrect.
+ - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode
+ only. Set this and rx-max-burst-prd to a valid,
+ non-zero value 1-16 (DWC_usb31 programming guide
+ section 1.2.4) to enable periodic ESS RX threshold.
+ - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set
+ this and rx-thr-num-pkt-prd to a valid, non-zero value
+ 1-16 (DWC_usb31 programming guide section 1.2.4) to
+ enable periodic ESS RX threshold.
+ - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode
+ only. Set this and tx-max-burst-prd to a valid,
+ non-zero value 1-16 (DWC_usb31 programming guide
+ section 1.2.3) to enable periodic ESS TX threshold.
+ - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set
+ this and tx-thr-num-pkt-prd to a valid, non-zero value
+ 1-16 (DWC_usb31 programming guide section 1.2.3) to
+ enable periodic ESS TX threshold.
- <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
index 88d9f4a4b280..266c2d917a28 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
@@ -32,7 +32,7 @@ Required properties:
"mcu_ck": mcu_bus clock for register access,
"dma_ck": dma_bus clock for data transfer by DMA
- - phys : a list of phandle + phy specifier pairs
+ - phys : see usb-hcd.txt in the current directory
Optional properties:
- wakeup-source : enable USB remote wakeup;
@@ -52,6 +52,9 @@ Optional properties:
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
- imod-interval-ns: default interrupt moderation interval is 5000ns
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
usb30: usb@11270000 {
compatible = "mediatek,mt8173-xhci";
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
index d589a1ef96a1..3382b5cb471d 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
@@ -17,7 +17,7 @@ Required properties:
- clock-names : must contain "sys_ck" for clock of controller,
the following clocks are optional:
"ref_ck", "mcu_ck" and "dam_ck";
- - phys : a list of phandle + phy specifier pairs
+ - phys : see usb-hcd.txt in the current directory
- dr_mode : should be one of "host", "peripheral" or "otg",
refer to usb/generic.txt
@@ -53,6 +53,9 @@ Optional properties:
- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
bit1 for u3port1, ... etc;
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Sub-nodes:
The xhci should be added as subnode to mtu3 as shown in the following example
if host mode is enabled. The DT binding details of xhci can be found in:
diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
index 3efde12b5d68..0f1b75386207 100644
--- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
@@ -16,10 +16,12 @@ Optional properties:
- has-transaction-translator : boolean, set this if EHCI have a Transaction
Translator built into the root hub.
- clocks : a list of phandle + clock specifier pairs
- - phys : phandle + phy specifier pair
- - phy-names : "usb"
+ - phys : see usb-hcd.txt in the current directory
- resets : phandle + reset specifier pair
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example (Sequoia 440EPx):
ehci@e0000300 {
compatible = "ibm,usb-ehci-440epx", "usb-ehci";
diff --git a/Documentation/devicetree/bindings/usb/usb-hcd.txt b/Documentation/devicetree/bindings/usb/usb-hcd.txt
new file mode 100644
index 000000000000..50529b838c9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb-hcd.txt
@@ -0,0 +1,9 @@
+Generic USB HCD (Host Controller Device) Properties
+
+Optional properties:
+- phys: a list of all USB PHYs on this HCD
+
+Example:
+ &usb1 {
+ phys = <&usb2_phy1>, <&usb3_phy1>;
+ };
diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
index 09e70c875bc6..a8d2103d1f3d 100644
--- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
@@ -13,10 +13,12 @@ Optional properties:
- remote-wakeup-connected: remote wakeup is wired on the platform
- num-ports : u32, to override the detected port count
- clocks : a list of phandle + clock specifier pairs
-- phys : phandle + phy specifier pair
-- phy-names : "usb"
+- phys : see usb-hcd.txt in the current directory
- resets : a list of phandle + reset specifier pairs
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
ohci0: usb@1c14400 {
diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.txt b/Documentation/devicetree/bindings/usb/usb-uhci.txt
index 298133416c97..cc2e6f7d602e 100644
--- a/Documentation/devicetree/bindings/usb/usb-uhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-uhci.txt
@@ -6,6 +6,9 @@ Required properties:
- reg : Should contain 1 register ranges(address and length)
- interrupts : UHCI controller interrupt
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
uhci@d8007b00 {
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index 1651483a7048..c4c00dff4b56 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -33,6 +33,11 @@ Optional properties:
- usb3-lpm-capable: determines if platform is USB3 LPM capable
- quirk-broken-port-ped: set if the controller has broken port disable mechanism
- imod-interval-ns: default interrupt moderation interval is 5000ns
+ - phys : see usb-hcd.txt in the current directory
+
+additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
Example:
usb@f0931000 {
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ae850d6c0ad3..b5f978a4cac6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -104,6 +104,7 @@ eeti eGalax_eMPIA Technology Inc
elan Elan Microelectronic Corp.
embest Shenzhen Embest Technology Co., Ltd.
emmicro EM Microelectronic
+emtrion emtrion GmbH
energymicro Silicon Laboratories (formerly Energy Micro AS)
engicam Engicam S.r.l.
epcos EPCOS AG
@@ -224,6 +225,7 @@ motorola Motorola, Inc.
moxa Moxa Inc.
mpl MPL AG
mqmaker mqmaker Inc.
+mscc Microsemi Corporation
msi Micro-Star International Co. Ltd.
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
multi-inno Multi-Inno Technology Co.,Ltd
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt
index 107280ef0025..adc6b76fcb3a 100644
--- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt
@@ -11,6 +11,7 @@ Optional properties:
detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
- fsl,ext-reset-output: If present the watchdog device is configured to
assert its external reset (WDOG_B) instead of issuing a software reset.
+- timeout-sec : Contains the watchdog timeout in seconds
Examples:
@@ -19,4 +20,5 @@ wdt@73f98000 {
reg = <0x73f98000 0x4000>;
interrupts = <58>;
big-endian;
+ timeout-sec = <20>;
};
diff --git a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt
index 8a6d84cb36c9..7588cc3971bf 100644
--- a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt
@@ -9,9 +9,13 @@ Required properties:
"amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs
- reg : Specifies base physical address and size of the registers.
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+
Example:
wdt: watchdog@c1109900 {
compatible = "amlogic,meson6-wdt";
reg = <0xc1109900 0x8>;
+ timeout-sec = <10>;
};
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 5b38a30e608c..859dee167b91 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -11,9 +11,13 @@ Required properties:
- reg : Specifies base physical address and size of the registers.
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+
Example:
wdt: watchdog@10000000 {
compatible = "mediatek,mt6589-wdt";
reg = <0x10000000 0x18>;
+ timeout-sec = <10>;
};
diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
new file mode 100644
index 000000000000..6d593003c933
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
@@ -0,0 +1,28 @@
+Nuvoton NPCM Watchdog
+
+Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
+The watchdog supports a pre-timeout interrupt that fires 10ms before the
+expiry.
+
+Required properties:
+- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg).
+- reg : Offset and length of the register set for the device.
+- interrupts : Contain the timer interrupt with flags for
+ falling edge.
+
+Required clocking property, have to be one of:
+- clocks : phandle of timer reference clock.
+- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
+ timer (usually 25000000).
+
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
+Example:
+
+timer@f000801c {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf000801c 0x4>;
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+};
diff --git a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt
index 9cbc76c89b2b..0dce5e3100b4 100644
--- a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt
@@ -5,10 +5,14 @@ Required properties:
- reg: Address range of tick timer/WDT register set
- interrupts: interrupt number to the cpu
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Example:
timer@b0020000 {
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
+ timeout-sec = <30>;
};
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
index 62dd5baad70e..ed11ce0ac836 100644
--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -2,13 +2,19 @@ Allwinner SoCs Watchdog timer
Required properties:
-- compatible : should be either "allwinner,sun4i-a10-wdt" or
- "allwinner,sun6i-a31-wdt"
+- compatible : should be one of
+ "allwinner,sun4i-a10-wdt"
+ "allwinner,sun6i-a31-wdt"
+ "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
- reg : Specifies base physical address and size of the registers.
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+
Example:
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
+ timeout-sec = <10>;
};
diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt b/Documentation/devicetree/bindings/x86/ce4100.txt
index b49ae593a60b..cd1221bfb539 100644
--- a/Documentation/devicetree/bindings/x86/ce4100.txt
+++ b/Documentation/devicetree/bindings/x86/ce4100.txt
@@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the ce4100
name in their compatible property because they first appeared in this
SoC.
-The CPU node
-------------
- cpu@0 {
- device_type = "cpu";
- compatible = "intel,ce4100";
- reg = <0>;
- lapic = <&lapic0>;
+The CPU nodes
+-------------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x00>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,ce4100";
+ reg = <0x02>;
+ };
};
-The reg property describes the CPU number. The lapic property points to
-the local APIC timer.
+A "cpu" node describes one logical processor (hardware thread).
+
+Required properties:
+
+- device_type
+ Device type, must be "cpu".
+
+- reg
+ Local APIC ID, the unique number assigned to each processor by
+ system hardware.
The SoC node
------------
diff --git a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt
index c4aa0adf13ec..a4feb6dde8cd 100644
--- a/Documentation/devicetree/overlay-notes.txt
+++ b/Documentation/devicetree/overlay-notes.txt
@@ -87,12 +87,12 @@ Overlay in-kernel API
The API is quite easy to use.
-1. Call of_overlay_apply() to create and apply an overlay changeset. The return
-value is an error or a cookie identifying this overlay.
+1. Call of_overlay_fdt_apply() to create and apply an overlay changeset. The
+return value is an error or a cookie identifying this overlay.
2. Call of_overlay_remove() to remove and cleanup the overlay changeset
-previously created via the call to of_overlay_apply(). Removal of an overlay
-changeset that is stacked by another will not be permitted.
+previously created via the call to of_overlay_fdt_apply(). Removal of an
+overlay changeset that is stacked by another will not be permitted.
Finally, if you need to remove all overlays in one-go, just call
of_overlay_remove_all() which will remove every single one in the correct
diff --git a/Documentation/doc-guide/kernel-doc.rst b/Documentation/doc-guide/kernel-doc.rst
index 722d4525f7cf..80383b1a574a 100644
--- a/Documentation/doc-guide/kernel-doc.rst
+++ b/Documentation/doc-guide/kernel-doc.rst
@@ -1,201 +1,59 @@
-Including kernel-doc comments
-=============================
-
-The Linux kernel source files may contain structured documentation comments, or
-kernel-doc comments to describe the functions and types and design of the
-code. The documentation comments may be included to any of the reStructuredText
-documents using a dedicated kernel-doc Sphinx directive extension.
-
-The kernel-doc directive is of the format::
-
- .. kernel-doc:: source
- :option:
-
-The *source* is the path to a source file, relative to the kernel source
-tree. The following directive options are supported:
-
-export: *[source-pattern ...]*
- Include documentation for all functions in *source* that have been exported
- using ``EXPORT_SYMBOL`` or ``EXPORT_SYMBOL_GPL`` either in *source* or in any
- of the files specified by *source-pattern*.
-
- The *source-pattern* is useful when the kernel-doc comments have been placed
- in header files, while ``EXPORT_SYMBOL`` and ``EXPORT_SYMBOL_GPL`` are next to
- the function definitions.
-
- Examples::
-
- .. kernel-doc:: lib/bitmap.c
- :export:
-
- .. kernel-doc:: include/net/mac80211.h
- :export: net/mac80211/*.c
-
-internal: *[source-pattern ...]*
- Include documentation for all functions and types in *source* that have
- **not** been exported using ``EXPORT_SYMBOL`` or ``EXPORT_SYMBOL_GPL`` either
- in *source* or in any of the files specified by *source-pattern*.
-
- Example::
-
- .. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
- :internal:
-
-doc: *title*
- Include documentation for the ``DOC:`` paragraph identified by *title* in
- *source*. Spaces are allowed in *title*; do not quote the *title*. The *title*
- is only used as an identifier for the paragraph, and is not included in the
- output. Please make sure to have an appropriate heading in the enclosing
- reStructuredText document.
-
- Example::
-
- .. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
- :doc: High Definition Audio over HDMI and Display Port
-
-functions: *function* *[...]*
- Include documentation for each *function* in *source*.
-
- Example::
-
- .. kernel-doc:: lib/bitmap.c
- :functions: bitmap_parselist bitmap_parselist_user
-
-Without options, the kernel-doc directive includes all documentation comments
-from the source file.
-
-The kernel-doc extension is included in the kernel source tree, at
-``Documentation/sphinx/kerneldoc.py``. Internally, it uses the
-``scripts/kernel-doc`` script to extract the documentation comments from the
-source.
-
-.. _kernel_doc:
-
Writing kernel-doc comments
===========================
-In order to provide embedded, "C" friendly, easy to maintain, but consistent and
-extractable overview, function and type documentation, the Linux kernel has
-adopted a consistent style for documentation comments. The format for this
-documentation is called the kernel-doc format, described below. This style
-embeds the documentation within the source files, using a few simple conventions
-for adding documentation paragraphs and documenting functions and their
-parameters, structures and unions and their members, enumerations, and typedefs.
-
-.. note:: The kernel-doc format is deceptively similar to gtk-doc or Doxygen,
- yet distinctively different, for historical reasons. The kernel source
- contains tens of thousands of kernel-doc comments. Please stick to the style
- described here.
+The Linux kernel source files may contain structured documentation
+comments in the kernel-doc format to describe the functions, types
+and design of the code. It is easier to keep documentation up-to-date
+when it is embedded in source files.
-The ``scripts/kernel-doc`` script is used by the Sphinx kernel-doc extension in
-the documentation build to extract this embedded documentation into the various
-HTML, PDF, and other format documents.
-
-In order to provide good documentation of kernel functions and data structures,
-please use the following conventions to format your kernel-doc comments in the
-Linux kernel source.
-
-How to format kernel-doc comments
----------------------------------
+.. note:: The kernel-doc format is deceptively similar to javadoc,
+ gtk-doc or Doxygen, yet distinctively different, for historical
+ reasons. The kernel source contains tens of thousands of kernel-doc
+ comments. Please stick to the style described here.
-The opening comment mark ``/**`` is reserved for kernel-doc comments. Only
-comments so marked will be considered by the ``kernel-doc`` tool. Use it only
-for comment blocks that contain kernel-doc formatted comments. The usual ``*/``
-should be used as the closing comment marker. The lines in between should be
-prefixed by `` * `` (space star space).
-
-The function and type kernel-doc comments should be placed just before the
-function or type being described. The overview kernel-doc comments may be freely
-placed at the top indentation level.
-
-Example kernel-doc function comment::
-
- /**
- * foobar() - Brief description of foobar.
- * @argument1: Description of parameter argument1 of foobar.
- * @argument2: Description of parameter argument2 of foobar.
- *
- * Longer description of foobar.
- *
- * Return: Description of return value of foobar.
- */
- int foobar(int argument1, char *argument2)
-
-The format is similar for documentation for structures, enums, paragraphs,
-etc. See the sections below for specific details of each type.
-
-The kernel-doc structure is extracted from the comments, and proper `Sphinx C
-Domain`_ function and type descriptions with anchors are generated for them. The
-descriptions are filtered for special kernel-doc highlights and
-cross-references. See below for details.
+The kernel-doc structure is extracted from the comments, and proper
+`Sphinx C Domain`_ function and type descriptions with anchors are
+generated from them. The descriptions are filtered for special kernel-doc
+highlights and cross-references. See below for details.
.. _Sphinx C Domain: http://www.sphinx-doc.org/en/stable/domains.html
+Every function that is exported to loadable modules using
+``EXPORT_SYMBOL`` or ``EXPORT_SYMBOL_GPL`` should have a kernel-doc
+comment. Functions and data structures in header files which are intended
+to be used by modules should also have kernel-doc comments.
-Parameters and member arguments
--------------------------------
-
-The kernel-doc function comments describe each parameter to the function and
-function typedefs or each member of struct/union, in order, with the
-``@argument:`` descriptions. For each non-private member argument, one
-``@argument`` definition is needed.
-
-The ``@argument:`` descriptions begin on the very next line following
-the opening brief function description line, with no intervening blank
-comment lines.
-
-The ``@argument:`` descriptions may span multiple lines.
-
-.. note::
-
- If the ``@argument`` description has multiple lines, the continuation
- of the description should be starting exactly at the same column as
- the previous line, e. g.::
-
- * @argument: some long description
- * that continues on next lines
+It is good practice to also provide kernel-doc formatted documentation
+for functions externally visible to other kernel files (not marked
+``static``). We also recommend providing kernel-doc formatted
+documentation for private (file ``static``) routines, for consistency of
+kernel source code layout. This is lower priority and at the discretion
+of the maintainer of that kernel source file.
- or::
-
- * @argument:
- * some long description
- * that continues on next lines
-
-If a function or typedef parameter argument is ``...`` (e. g. a variable
-number of arguments), its description should be listed in kernel-doc
-notation as::
+How to format kernel-doc comments
+---------------------------------
- * @...: description
+The opening comment mark ``/**`` is used for kernel-doc comments. The
+``kernel-doc`` tool will extract comments marked this way. The rest of
+the comment is formatted like a normal multi-line comment with a column
+of asterisks on the left side, closing with ``*/`` on a line by itself.
-Private members
-~~~~~~~~~~~~~~~
+The function and type kernel-doc comments should be placed just before
+the function or type being described in order to maximise the chance
+that somebody changing the code will also change the documentation. The
+overview kernel-doc comments may be placed anywhere at the top indentation
+level.
-Inside a struct or union description, you can use the ``private:`` and
-``public:`` comment tags. Structure fields that are inside a ``private:``
-area are not listed in the generated output documentation.
+Running the ``kernel-doc`` tool with increased verbosity and without actual
+output generation may be used to verify proper formatting of the
+documentation comments. For example::
-The ``private:`` and ``public:`` tags must begin immediately following a
-``/*`` comment marker. They may optionally include comments between the
-``:`` and the ending ``*/`` marker.
+ scripts/kernel-doc -v -none drivers/foo/bar.c
-Example::
+The documentation format is verified by the kernel build when it is
+requested to perform extra gcc checks::
- /**
- * struct my_struct - short description
- * @a: first member
- * @b: second member
- * @d: fourth member
- *
- * Longer description
- */
- struct my_struct {
- int a;
- int b;
- /* private: internal use only */
- int c;
- /* public: the next one is public */
- int d;
- };
+ make W=n
Function documentation
----------------------
@@ -216,6 +74,9 @@ The general format of a function and function-like macro kernel-doc comment is::
*
* The longer description may have multiple paragraphs.
*
+ * Context: Describes whether the function can sleep, what locks it takes,
+ * releases, or expects to be held. It can extend over multiple
+ * lines.
* Return: Describe the return value of foobar.
*
* The return value description can also have multiple paragraphs, and should
@@ -226,6 +87,52 @@ The brief description following the function name may span multiple lines, and
ends with an argument description, a blank comment line, or the end of the
comment block.
+Function parameters
+~~~~~~~~~~~~~~~~~~~
+
+Each function argument should be described in order, immediately following
+the short function description. Do not leave a blank line between the
+function description and the arguments, nor between the arguments.
+
+Each ``@argument:`` description may span multiple lines.
+
+.. note::
+
+ If the ``@argument`` description has multiple lines, the continuation
+ of the description should start at the same column as the previous line::
+
+ * @argument: some long description
+ * that continues on next lines
+
+ or::
+
+ * @argument:
+ * some long description
+ * that continues on next lines
+
+If a function has a variable number of arguments, its description should
+be written in kernel-doc notation as::
+
+ * @...: description
+
+Function context
+~~~~~~~~~~~~~~~~
+
+The context in which a function can be called should be described in a
+section named ``Context``. This should include whether the function
+sleeps or can be called from interrupt context, as well as what locks
+it takes, releases and expects to be held by its caller.
+
+Examples::
+
+ * Context: Any context.
+ * Context: Any context. Takes and releases the RCU lock.
+ * Context: Any context. Expects <lock> to be held by caller.
+ * Context: Process context. May sleep if @gfp flags permit.
+ * Context: Process context. Takes and releases <mutex>.
+ * Context: Softirq or process context. Takes and releases <lock>, BH-safe.
+ * Context: Interrupt context.
+
Return values
~~~~~~~~~~~~~
@@ -255,7 +162,7 @@ named ``Return``.
#) If the descriptive text you provide has lines that begin with
some phrase followed by a colon, each of those phrases will be taken
- as a new section heading, with probably won't produce the desired
+ as a new section heading, which probably won't produce the desired
effect.
Structure, union, and enumeration documentation
@@ -265,69 +172,144 @@ The general format of a struct, union, and enum kernel-doc comment is::
/**
* struct struct_name - Brief description.
- * @argument: Description of member member_name.
+ * @member1: Description of member1.
+ * @member2: Description of member2.
+ * One can provide multiple line descriptions
+ * for members.
*
* Description of the structure.
*/
-On the above, ``struct`` is used to mean structs. You can also use ``union``
-and ``enum`` to describe unions and enums. ``argument`` is used
-to mean struct and union member names as well as enumerations in an enum.
+You can replace the ``struct`` in the above example with ``union`` or
+``enum`` to describe unions or enums. ``member`` is used to mean struct
+and union member names as well as enumerations in an enum.
-The brief description following the structure name may span multiple lines, and
-ends with a member description, a blank comment line, or the end of the
-comment block.
+The brief description following the structure name may span multiple
+lines, and ends with a member description, a blank comment line, or the
+end of the comment block.
+
+Members
+~~~~~~~
-The kernel-doc data structure comments describe each member of the structure,
-in order, with the member descriptions.
+Members of structs, unions and enums should be documented the same way
+as function parameters; they immediately succeed the short description
+and may be multi-line.
+
+Inside a struct or union description, you can use the ``private:`` and
+``public:`` comment tags. Structure fields that are inside a ``private:``
+area are not listed in the generated output documentation.
+
+The ``private:`` and ``public:`` tags must begin immediately following a
+``/*`` comment marker. They may optionally include comments between the
+``:`` and the ending ``*/`` marker.
+
+Example::
+
+ /**
+ * struct my_struct - short description
+ * @a: first member
+ * @b: second member
+ * @d: fourth member
+ *
+ * Longer description
+ */
+ struct my_struct {
+ int a;
+ int b;
+ /* private: internal use only */
+ int c;
+ /* public: the next one is public */
+ int d;
+ };
Nested structs/unions
~~~~~~~~~~~~~~~~~~~~~
-It is possible to document nested structs unions, like::
+It is possible to document nested structs and unions, like::
/**
* struct nested_foobar - a struct with nested unions and structs
- * @arg1: - first argument of anonymous union/anonymous struct
- * @arg2: - second argument of anonymous union/anonymous struct
- * @arg3: - third argument of anonymous union/anonymous struct
- * @arg4: - fourth argument of anonymous union/anonymous struct
- * @bar.st1.arg1 - first argument of struct st1 on union bar
- * @bar.st1.arg2 - second argument of struct st1 on union bar
- * @bar.st2.arg1 - first argument of struct st2 on union bar
- * @bar.st2.arg2 - second argument of struct st2 on union bar
+ * @memb1: first member of anonymous union/anonymous struct
+ * @memb2: second member of anonymous union/anonymous struct
+ * @memb3: third member of anonymous union/anonymous struct
+ * @memb4: fourth member of anonymous union/anonymous struct
+ * @bar: non-anonymous union
+ * @bar.st1: struct st1 inside @bar
+ * @bar.st2: struct st2 inside @bar
+ * @bar.st1.memb1: first member of struct st1 on union bar
+ * @bar.st1.memb2: second member of struct st1 on union bar
+ * @bar.st2.memb1: first member of struct st2 on union bar
+ * @bar.st2.memb2: second member of struct st2 on union bar
+ */
struct nested_foobar {
/* Anonymous union/struct*/
union {
struct {
- int arg1;
- int arg2;
- }
+ int memb1;
+ int memb2;
+ }
struct {
- void *arg3;
- int arg4;
- }
- }
- union {
+ void *memb3;
+ int memb4;
+ }
+ }
+ union {
struct {
- int arg1;
- int arg2;
- } st1;
+ int memb1;
+ int memb2;
+ } st1;
struct {
- void *arg1;
- int arg2;
- } st2;
- } bar;
+ void *memb1;
+ int memb2;
+ } st2;
+ } bar;
};
.. note::
#) When documenting nested structs or unions, if the struct/union ``foo``
- is named, the argument ``bar`` inside it should be documented as
+ is named, the member ``bar`` inside it should be documented as
``@foo.bar:``
- #) When the nested struct/union is anonymous, the argument ``bar`` on it
+ #) When the nested struct/union is anonymous, the member ``bar`` in it
should be documented as ``@bar:``
+In-line member documentation comments
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The structure members may also be documented in-line within the definition.
+There are two styles, single-line comments where both the opening ``/**`` and
+closing ``*/`` are on the same line, and multi-line comments where they are each
+on a line of their own, like all other kernel-doc comments::
+
+ /**
+ * struct foo - Brief description.
+ * @foo: The Foo member.
+ */
+ struct foo {
+ int foo;
+ /**
+ * @bar: The Bar member.
+ */
+ int bar;
+ /**
+ * @baz: The Baz member.
+ *
+ * Here, the member description may contain several paragraphs.
+ */
+ int baz;
+ union {
+ /** @foobar: Single line description. */
+ int foobar;
+ };
+ /** @bar2: Description for struct @bar2 inside @foo */
+ struct {
+ /**
+ * @bar2.barbar: Description for @barbar inside @foo.bar2
+ */
+ int barbar;
+ } bar2;
+ };
+
Typedef documentation
---------------------
@@ -347,10 +329,12 @@ Typedefs with function prototypes can also be documented::
* @arg2: description of arg2
*
* Description of the type.
+ *
+ * Context: Locking context.
+ * Return: Meaning of the return value.
*/
typedef void (*type_name)(struct v4l2_ctrl *arg1, void *arg2);
-
Highlights and cross-references
-------------------------------
@@ -422,37 +406,6 @@ cross-references.
For further details, please refer to the `Sphinx C Domain`_ documentation.
-
-
-In-line member documentation comments
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The structure members may also be documented in-line within the definition.
-There are two styles, single-line comments where both the opening ``/**`` and
-closing ``*/`` are on the same line, and multi-line comments where they are each
-on a line of their own, like all other kernel-doc comments::
-
- /**
- * struct foo - Brief description.
- * @foo: The Foo member.
- */
- struct foo {
- int foo;
- /**
- * @bar: The Bar member.
- */
- int bar;
- /**
- * @baz: The Baz member.
- *
- * Here, the member description may contain several paragraphs.
- */
- int baz;
- /** @foobar: Single line description. */
- int foobar;
- }
-
-
Overview documentation comments
-------------------------------
@@ -482,53 +435,81 @@ The title following ``DOC:`` acts as a heading within the source file, but also
as an identifier for extracting the documentation comment. Thus, the title must
be unique within the file.
-Recommendations
----------------
+Including kernel-doc comments
+=============================
-We definitely need kernel-doc formatted documentation for functions that are
-exported to loadable modules using ``EXPORT_SYMBOL`` or ``EXPORT_SYMBOL_GPL``.
+The documentation comments may be included in any of the reStructuredText
+documents using a dedicated kernel-doc Sphinx directive extension.
-We also look to provide kernel-doc formatted documentation for functions
-externally visible to other kernel files (not marked "static").
+The kernel-doc directive is of the format::
-We also recommend providing kernel-doc formatted documentation for private (file
-"static") routines, for consistency of kernel source code layout. But this is
-lower priority and at the discretion of the MAINTAINER of that kernel source
-file.
+ .. kernel-doc:: source
+ :option:
-Data structures visible in kernel include files should also be documented using
-kernel-doc formatted comments.
+The *source* is the path to a source file, relative to the kernel source
+tree. The following directive options are supported:
-How to use kernel-doc to generate man pages
--------------------------------------------
+export: *[source-pattern ...]*
+ Include documentation for all functions in *source* that have been exported
+ using ``EXPORT_SYMBOL`` or ``EXPORT_SYMBOL_GPL`` either in *source* or in any
+ of the files specified by *source-pattern*.
-If you just want to use kernel-doc to generate man pages you can do this
-from the Kernel git tree::
+ The *source-pattern* is useful when the kernel-doc comments have been placed
+ in header files, while ``EXPORT_SYMBOL`` and ``EXPORT_SYMBOL_GPL`` are next to
+ the function definitions.
+
+ Examples::
+
+ .. kernel-doc:: lib/bitmap.c
+ :export:
+
+ .. kernel-doc:: include/net/mac80211.h
+ :export: net/mac80211/*.c
+
+internal: *[source-pattern ...]*
+ Include documentation for all functions and types in *source* that have
+ **not** been exported using ``EXPORT_SYMBOL`` or ``EXPORT_SYMBOL_GPL`` either
+ in *source* or in any of the files specified by *source-pattern*.
- $ scripts/kernel-doc -man $(git grep -l '/\*\*' |grep -v Documentation/) | ./split-man.pl /tmp/man
+ Example::
-Using the small ``split-man.pl`` script below::
+ .. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
+ :internal:
+doc: *title*
+ Include documentation for the ``DOC:`` paragraph identified by *title* in
+ *source*. Spaces are allowed in *title*; do not quote the *title*. The *title*
+ is only used as an identifier for the paragraph, and is not included in the
+ output. Please make sure to have an appropriate heading in the enclosing
+ reStructuredText document.
- #!/usr/bin/perl
+ Example::
- if ($#ARGV < 0) {
- die "where do I put the results?\n";
- }
+ .. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
+ :doc: High Definition Audio over HDMI and Display Port
- mkdir $ARGV[0],0777;
- $state = 0;
- while (<STDIN>) {
- if (/^\.TH \"[^\"]*\" 9 \"([^\"]*)\"/) {
- if ($state == 1) { close OUT }
- $state = 1;
- $fn = "$ARGV[0]/$1.9";
- print STDERR "Creating $fn\n";
- open OUT, ">$fn" or die "can't open $fn: $!\n";
- print OUT $_;
- } elsif ($state != 0) {
- print OUT $_;
- }
- }
+functions: *function* *[...]*
+ Include documentation for each *function* in *source*.
+
+ Example::
+
+ .. kernel-doc:: lib/bitmap.c
+ :functions: bitmap_parselist bitmap_parselist_user
+
+Without options, the kernel-doc directive includes all documentation comments
+from the source file.
+
+The kernel-doc extension is included in the kernel source tree, at
+``Documentation/sphinx/kerneldoc.py``. Internally, it uses the
+``scripts/kernel-doc`` script to extract the documentation comments from the
+source.
+
+.. _kernel_doc:
+
+How to use kernel-doc to generate man pages
+-------------------------------------------
+
+If you just want to use kernel-doc to generate man pages you can do this
+from the kernel git tree::
- close OUT;
+ $ scripts/kernel-doc -man $(git grep -l '/\*\*' -- :^Documentation :^tools) | scripts/split-man.pl /tmp/man
diff --git a/Documentation/driver-api/device_connection.rst b/Documentation/driver-api/device_connection.rst
new file mode 100644
index 000000000000..affbc5566ab0
--- /dev/null
+++ b/Documentation/driver-api/device_connection.rst
@@ -0,0 +1,43 @@
+==================
+Device connections
+==================
+
+Introduction
+------------
+
+Devices often have connections to other devices that are outside of the direct
+child/parent relationship. A serial or network communication controller, which
+could be a PCI device, may need to be able to get a reference to its PHY
+component, which could be attached for example to the I2C bus. Some device
+drivers need to be able to control the clocks or the GPIOs for their devices,
+and so on.
+
+Device connections are generic descriptions of any type of connection between
+two separate devices.
+
+Device connections alone do not create a dependency between the two devices.
+They are only descriptions which are not tied to either of the devices directly.
+A dependency between the two devices exists only if one of the two endpoint
+devices requests a reference to the other. The descriptions themselves can be
+defined in firmware (not yet supported) or they can be built-in.
+
+Usage
+-----
+
+Device connections should exist before device ``->probe`` callback is called for
+either endpoint device in the description. If the connections are defined in
+firmware, this is not a problem. It should be considered if the connection
+descriptions are "built-in", and need to be added separately.
+
+The connection description consists of the names of the two devices with the
+connection, i.e. the endpoints, and unique identifier for the connection which
+is needed if there are multiple connections between the two devices.
+
+After a description exists, the devices in it can request reference to the other
+endpoint device, or they can request the description itself.
+
+API
+---
+
+.. kernel-doc:: drivers/base/devcon.c
+ : functions: device_connection_find_match device_connection_find device_connection_add device_connection_remove
diff --git a/Documentation/driver-api/dmaengine/dmatest.rst b/Documentation/driver-api/dmaengine/dmatest.rst
index 3922c0a3f0c0..7ce5e71c353e 100644
--- a/Documentation/driver-api/dmaengine/dmatest.rst
+++ b/Documentation/driver-api/dmaengine/dmatest.rst
@@ -6,10 +6,16 @@ Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This small document introduces how to test DMA drivers using dmatest module.
+.. note::
+ The test suite works only on the channels that have at least one
+ capability of the following: DMA_MEMCPY (memory-to-memory), DMA_MEMSET
+ (const-to-memory or memory-to-memory, when emulated), DMA_XOR, DMA_PQ.
+
Part 1 - How to build the test module
=====================================
The menuconfig contains an option that could be found by following path:
+
Device Drivers -> DMA Engine support -> DMA Test client
In the configuration file the option called CONFIG_DMATEST. The dmatest could
@@ -18,11 +24,11 @@ be built as module or inside kernel. Let's consider those cases.
Part 2 - When dmatest is built as a module
==========================================
-Example of usage: ::
+Example of usage::
% modprobe dmatest channel=dma0chan0 timeout=2000 iterations=1 run=1
-...or: ::
+...or::
% modprobe dmatest
% echo dma0chan0 > /sys/module/dmatest/parameters/channel
@@ -30,14 +36,12 @@ Example of usage: ::
% echo 1 > /sys/module/dmatest/parameters/iterations
% echo 1 > /sys/module/dmatest/parameters/run
-...or on the kernel command line: ::
+...or on the kernel command line::
dmatest.channel=dma0chan0 dmatest.timeout=2000 dmatest.iterations=1 dmatest.run=1
-..hint:: available channel list could be extracted by running the following
- command:
-
-::
+.. hint::
+ available channel list could be extracted by running the following command::
% ls -1 /sys/class/dma/
@@ -59,12 +63,12 @@ before returning. For example, the following scripts wait for 42 tests
to complete before exiting. Note that if 'iterations' is set to 'infinite' then
waiting is disabled.
-Example: ::
+Example::
% modprobe dmatest run=1 iterations=42 wait=1
% modprobe -r dmatest
-...or: ::
+...or::
% modprobe dmatest run=1 iterations=42
% cat /sys/module/dmatest/parameters/wait
@@ -76,7 +80,7 @@ Part 3 - When built-in in the kernel
The module parameters that is supplied to the kernel command line will be used
for the first performed test. After user gets a control, the test could be
re-run with the same or different parameters. For the details see the above
-section "Part 2 - When dmatest is built as a module..."
+section `Part 2 - When dmatest is built as a module`_.
In both cases the module parameters are used as the actual values for the test
case. You always could check them at run-time by running ::
@@ -86,22 +90,22 @@ case. You always could check them at run-time by running ::
Part 4 - Gathering the test results
===================================
-Test results are printed to the kernel log buffer with the format: ::
+Test results are printed to the kernel log buffer with the format::
"dmatest: result <channel>: <test id>: '<error msg>' with src_off=<val> dst_off=<val> len=<val> (<err code>)"
-Example of output: ::
-
+Example of output::
% dmesg | tail -n 1
dmatest: result dma0chan0-copy0: #1: No errors with src_off=0x7bf dst_off=0x8ad len=0x3fea (0)
-The message format is unified across the different types of errors. A number in
-the parens represents additional information, e.g. error code, error counter,
-or status. A test thread also emits a summary line at completion listing the
-number of tests executed, number that failed, and a result code.
+The message format is unified across the different types of errors. A
+number in the parentheses represents additional information, e.g. error
+code, error counter, or status. A test thread also emits a summary line at
+completion listing the number of tests executed, number that failed, and a
+result code.
-Example: ::
+Example::
% dmesg | tail -n 1
dmatest: dma0chan0-copy0: summary 1 test, 0 failures 1000 iops 100000 KB/s (0)
diff --git a/Documentation/driver-api/firmware/fallback-mechanisms.rst b/Documentation/driver-api/firmware/fallback-mechanisms.rst
index 4055ac76b288..f353783ae0be 100644
--- a/Documentation/driver-api/firmware/fallback-mechanisms.rst
+++ b/Documentation/driver-api/firmware/fallback-mechanisms.rst
@@ -112,7 +112,7 @@ Since a device is created for the sysfs interface to help load firmware as a
fallback mechanism userspace can be informed of the addition of the device by
relying on kobject uevents. The addition of the device into the device
hierarchy means the fallback mechanism for firmware loading has been initiated.
-For details of implementation refer to _request_firmware_load(), in particular
+For details of implementation refer to fw_load_sysfs_fallback(), in particular
on the use of dev_set_uevent_suppress() and kobject_uevent().
The kernel's kobject uevent mechanism is implemented in lib/kobject_uevent.c,
diff --git a/Documentation/driver-api/firmware/request_firmware.rst b/Documentation/driver-api/firmware/request_firmware.rst
index cc0aea880824..cf4516dfbf96 100644
--- a/Documentation/driver-api/firmware/request_firmware.rst
+++ b/Documentation/driver-api/firmware/request_firmware.rst
@@ -44,6 +44,20 @@ request_firmware_nowait
.. kernel-doc:: drivers/base/firmware_class.c
:functions: request_firmware_nowait
+Special optimizations on reboot
+===============================
+
+Some devices have an optimization in place to enable the firmware to be
+retained during system reboot. When such optimizations are used the driver
+author must ensure the firmware is still available on resume from suspend,
+this can be done with firmware_request_cache() insted of requesting for the
+firmare to be loaded.
+
+firmware_request_cache()
+-----------------------
+.. kernel-doc:: drivers/base/firmware_class.c
+ :functions: firmware_request_cache
+
request firmware API expected driver use
========================================
diff --git a/Documentation/driver-api/gpio.rst b/Documentation/driver-api/gpio.rst
deleted file mode 100644
index 6dd4aa647f27..000000000000
--- a/Documentation/driver-api/gpio.rst
+++ /dev/null
@@ -1,45 +0,0 @@
-===================================
-General Purpose Input/Output (GPIO)
-===================================
-
-Core
-====
-
-.. kernel-doc:: include/linux/gpio/driver.h
- :internal:
-
-.. kernel-doc:: drivers/gpio/gpiolib.c
- :export:
-
-Legacy API
-==========
-
-The functions listed in this section are deprecated. The GPIO descriptor based
-API described above should be used in new code.
-
-.. kernel-doc:: drivers/gpio/gpiolib-legacy.c
- :export:
-
-ACPI support
-============
-
-.. kernel-doc:: drivers/gpio/gpiolib-acpi.c
- :export:
-
-Device tree support
-===================
-
-.. kernel-doc:: drivers/gpio/gpiolib-of.c
- :export:
-
-Device-managed API
-==================
-
-.. kernel-doc:: drivers/gpio/devres.c
- :export:
-
-sysfs helpers
-=============
-
-.. kernel-doc:: drivers/gpio/gpiolib-sysfs.c
- :export:
diff --git a/Documentation/driver-api/gpio/board.rst b/Documentation/driver-api/gpio/board.rst
new file mode 100644
index 000000000000..25d62b2e9fd0
--- /dev/null
+++ b/Documentation/driver-api/gpio/board.rst
@@ -0,0 +1,179 @@
+=============
+GPIO Mappings
+=============
+
+This document explains how GPIOs can be assigned to given devices and functions.
+
+Note that it only applies to the new descriptor-based interface. For a
+description of the deprecated integer-based GPIO interface please refer to
+gpio-legacy.txt (actually, there is no real mapping possible with the old
+interface; you just fetch an integer from somewhere and request the
+corresponding GPIO).
+
+All platforms can enable the GPIO library, but if the platform strictly
+requires GPIO functionality to be present, it needs to select GPIOLIB from its
+Kconfig. Then, how GPIOs are mapped depends on what the platform uses to
+describe its hardware layout. Currently, mappings can be defined through device
+tree, ACPI, and platform data.
+
+Device Tree
+-----------
+GPIOs can easily be mapped to devices and functions in the device tree. The
+exact way to do it depends on the GPIO controller providing the GPIOs, see the
+device tree bindings for your controller.
+
+GPIOs mappings are defined in the consumer device's node, in a property named
+<function>-gpios, where <function> is the function the driver will request
+through gpiod_get(). For example::
+
+ foo_device {
+ compatible = "acme,foo";
+ ...
+ led-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>, /* red */
+ <&gpio 16 GPIO_ACTIVE_HIGH>, /* green */
+ <&gpio 17 GPIO_ACTIVE_HIGH>; /* blue */
+
+ power-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+Properties named <function>-gpio are also considered valid and old bindings use
+it but are only supported for compatibility reasons and should not be used for
+newer bindings since it has been deprecated.
+
+This property will make GPIOs 15, 16 and 17 available to the driver under the
+"led" function, and GPIO 1 as the "power" GPIO::
+
+ struct gpio_desc *red, *green, *blue, *power;
+
+ red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
+ green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
+ blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
+
+ power = gpiod_get(dev, "power", GPIOD_OUT_HIGH);
+
+The led GPIOs will be active high, while the power GPIO will be active low (i.e.
+gpiod_is_active_low(power) will be true).
+
+The second parameter of the gpiod_get() functions, the con_id string, has to be
+the <function>-prefix of the GPIO suffixes ("gpios" or "gpio", automatically
+looked up by the gpiod functions internally) used in the device tree. With above
+"led-gpios" example, use the prefix without the "-" as con_id parameter: "led".
+
+Internally, the GPIO subsystem prefixes the GPIO suffix ("gpios" or "gpio")
+with the string passed in con_id to get the resulting string
+(``snprintf(... "%s-%s", con_id, gpio_suffixes[]``).
+
+ACPI
+----
+ACPI also supports function names for GPIOs in a similar fashion to DT.
+The above DT example can be converted to an equivalent ACPI description
+with the help of _DSD (Device Specific Data), introduced in ACPI 5.1::
+
+ Device (FOO) {
+ Name (_CRS, ResourceTemplate () {
+ GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
+ "\\_SB.GPI0") {15} // red
+ GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
+ "\\_SB.GPI0") {16} // green
+ GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
+ "\\_SB.GPI0") {17} // blue
+ GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
+ "\\_SB.GPI0") {1} // power
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {
+ "led-gpios",
+ Package () {
+ ^FOO, 0, 0, 1,
+ ^FOO, 1, 0, 1,
+ ^FOO, 2, 0, 1,
+ }
+ },
+ Package () {
+ "power-gpios",
+ Package () {^FOO, 3, 0, 0},
+ },
+ }
+ })
+ }
+
+For more information about the ACPI GPIO bindings see
+Documentation/acpi/gpio-properties.txt.
+
+Platform Data
+-------------
+Finally, GPIOs can be bound to devices and functions using platform data. Board
+files that desire to do so need to include the following header::
+
+ #include <linux/gpio/machine.h>
+
+GPIOs are mapped by the means of tables of lookups, containing instances of the
+gpiod_lookup structure. Two macros are defined to help declaring such mappings::
+
+ GPIO_LOOKUP(chip_label, chip_hwnum, con_id, flags)
+ GPIO_LOOKUP_IDX(chip_label, chip_hwnum, con_id, idx, flags)
+
+where
+
+ - chip_label is the label of the gpiod_chip instance providing the GPIO
+ - chip_hwnum is the hardware number of the GPIO within the chip
+ - con_id is the name of the GPIO function from the device point of view. It
+ can be NULL, in which case it will match any function.
+ - idx is the index of the GPIO within the function.
+ - flags is defined to specify the following properties:
+ * GPIO_ACTIVE_HIGH - GPIO line is active high
+ * GPIO_ACTIVE_LOW - GPIO line is active low
+ * GPIO_OPEN_DRAIN - GPIO line is set up as open drain
+ * GPIO_OPEN_SOURCE - GPIO line is set up as open source
+ * GPIO_PERSISTENT - GPIO line is persistent during
+ suspend/resume and maintains its value
+ * GPIO_TRANSITORY - GPIO line is transitory and may loose its
+ electrical state during suspend/resume
+
+In the future, these flags might be extended to support more properties.
+
+Note that GPIO_LOOKUP() is just a shortcut to GPIO_LOOKUP_IDX() where idx = 0.
+
+A lookup table can then be defined as follows, with an empty entry defining its
+end. The 'dev_id' field of the table is the identifier of the device that will
+make use of these GPIOs. It can be NULL, in which case it will be matched for
+calls to gpiod_get() with a NULL device.
+
+.. code-block:: c
+
+ struct gpiod_lookup_table gpios_table = {
+ .dev_id = "foo.0",
+ .table = {
+ GPIO_LOOKUP_IDX("gpio.0", 15, "led", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("gpio.0", 16, "led", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("gpio.0", 17, "led", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio.0", 1, "power", GPIO_ACTIVE_LOW),
+ { },
+ },
+ };
+
+And the table can be added by the board code as follows::
+
+ gpiod_add_lookup_table(&gpios_table);
+
+The driver controlling "foo.0" will then be able to obtain its GPIOs as follows::
+
+ struct gpio_desc *red, *green, *blue, *power;
+
+ red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
+ green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
+ blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
+
+ power = gpiod_get(dev, "power", GPIOD_OUT_HIGH);
+
+Since the "led" GPIOs are mapped as active-high, this example will switch their
+signals to 1, i.e. enabling the LEDs. And for the "power" GPIO, which is mapped
+as active-low, its actual signal will be 0 after this code. Contrary to the
+legacy integer GPIO interface, the active-low property is handled during
+mapping and is thus transparent to GPIO consumers.
+
+A set of functions such as gpiod_set_value() is available to work with
+the new descriptor-oriented interface.
diff --git a/Documentation/driver-api/gpio/consumer.rst b/Documentation/driver-api/gpio/consumer.rst
new file mode 100644
index 000000000000..c71a50d85b50
--- /dev/null
+++ b/Documentation/driver-api/gpio/consumer.rst
@@ -0,0 +1,439 @@
+==================================
+GPIO Descriptor Consumer Interface
+==================================
+
+This document describes the consumer interface of the GPIO framework. Note that
+it describes the new descriptor-based interface. For a description of the
+deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
+
+
+Guidelines for GPIOs consumers
+==============================
+
+Drivers that can't work without standard GPIO calls should have Kconfig entries
+that depend on GPIOLIB or select GPIOLIB. The functions that allow a driver to
+obtain and use GPIOs are available by including the following file:
+
+ #include <linux/gpio/consumer.h>
+
+There are static inline stubs for all functions in the header file in the case
+where GPIOLIB is disabled. When these stubs are called they will emit
+warnings. These stubs are used for two use cases:
+
+- Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
+ the current platform does not enable or select GPIOLIB because we are not
+ going to execute the system anyway.
+
+- Truly optional GPIOLIB support - where the driver does not really make use
+ of the GPIOs on certain compile-time configurations for certain systems, but
+ will use it under other compile-time configurations. In this case the
+ consumer must make sure not to call into these functions, or the user will
+ be met with console warnings that may be perceived as intimidating.
+
+All the functions that work with the descriptor-based GPIO interface are
+prefixed with ``gpiod_``. The ``gpio_`` prefix is used for the legacy
+interface. No other function in the kernel should use these prefixes. The use
+of the legacy functions is strongly discouraged, new code should use
+<linux/gpio/consumer.h> and descriptors exclusively.
+
+
+Obtaining and Disposing GPIOs
+=============================
+
+With the descriptor-based interface, GPIOs are identified with an opaque,
+non-forgeable handler that must be obtained through a call to one of the
+gpiod_get() functions. Like many other kernel subsystems, gpiod_get() takes the
+device that will use the GPIO and the function the requested GPIO is supposed to
+fulfill::
+
+ struct gpio_desc *gpiod_get(struct device *dev, const char *con_id,
+ enum gpiod_flags flags)
+
+If a function is implemented by using several GPIOs together (e.g. a simple LED
+device that displays digits), an additional index argument can be specified::
+
+ struct gpio_desc *gpiod_get_index(struct device *dev,
+ const char *con_id, unsigned int idx,
+ enum gpiod_flags flags)
+
+For a more detailed description of the con_id parameter in the DeviceTree case
+see Documentation/gpio/board.txt
+
+The flags parameter is used to optionally specify a direction and initial value
+for the GPIO. Values can be:
+
+* GPIOD_ASIS or 0 to not initialize the GPIO at all. The direction must be set
+ later with one of the dedicated functions.
+* GPIOD_IN to initialize the GPIO as input.
+* GPIOD_OUT_LOW to initialize the GPIO as output with a value of 0.
+* GPIOD_OUT_HIGH to initialize the GPIO as output with a value of 1.
+* GPIOD_OUT_LOW_OPEN_DRAIN same as GPIOD_OUT_LOW but also enforce the line
+ to be electrically used with open drain.
+* GPIOD_OUT_HIGH_OPEN_DRAIN same as GPIOD_OUT_HIGH but also enforce the line
+ to be electrically used with open drain.
+
+The two last flags are used for use cases where open drain is mandatory, such
+as I2C: if the line is not already configured as open drain in the mappings
+(see board.txt), then open drain will be enforced anyway and a warning will be
+printed that the board configuration needs to be updated to match the use case.
+
+Both functions return either a valid GPIO descriptor, or an error code checkable
+with IS_ERR() (they will never return a NULL pointer). -ENOENT will be returned
+if and only if no GPIO has been assigned to the device/function/index triplet,
+other error codes are used for cases where a GPIO has been assigned but an error
+occurred while trying to acquire it. This is useful to discriminate between mere
+errors and an absence of GPIO for optional GPIO parameters. For the common
+pattern where a GPIO is optional, the gpiod_get_optional() and
+gpiod_get_index_optional() functions can be used. These functions return NULL
+instead of -ENOENT if no GPIO has been assigned to the requested function::
+
+ struct gpio_desc *gpiod_get_optional(struct device *dev,
+ const char *con_id,
+ enum gpiod_flags flags)
+
+ struct gpio_desc *gpiod_get_index_optional(struct device *dev,
+ const char *con_id,
+ unsigned int index,
+ enum gpiod_flags flags)
+
+Note that gpio_get*_optional() functions (and their managed variants), unlike
+the rest of gpiolib API, also return NULL when gpiolib support is disabled.
+This is helpful to driver authors, since they do not need to special case
+-ENOSYS return codes. System integrators should however be careful to enable
+gpiolib on systems that need it.
+
+For a function using multiple GPIOs all of those can be obtained with one call::
+
+ struct gpio_descs *gpiod_get_array(struct device *dev,
+ const char *con_id,
+ enum gpiod_flags flags)
+
+This function returns a struct gpio_descs which contains an array of
+descriptors::
+
+ struct gpio_descs {
+ unsigned int ndescs;
+ struct gpio_desc *desc[];
+ }
+
+The following function returns NULL instead of -ENOENT if no GPIOs have been
+assigned to the requested function::
+
+ struct gpio_descs *gpiod_get_array_optional(struct device *dev,
+ const char *con_id,
+ enum gpiod_flags flags)
+
+Device-managed variants of these functions are also defined::
+
+ struct gpio_desc *devm_gpiod_get(struct device *dev, const char *con_id,
+ enum gpiod_flags flags)
+
+ struct gpio_desc *devm_gpiod_get_index(struct device *dev,
+ const char *con_id,
+ unsigned int idx,
+ enum gpiod_flags flags)
+
+ struct gpio_desc *devm_gpiod_get_optional(struct device *dev,
+ const char *con_id,
+ enum gpiod_flags flags)
+
+ struct gpio_desc *devm_gpiod_get_index_optional(struct device *dev,
+ const char *con_id,
+ unsigned int index,
+ enum gpiod_flags flags)
+
+ struct gpio_descs *devm_gpiod_get_array(struct device *dev,
+ const char *con_id,
+ enum gpiod_flags flags)
+
+ struct gpio_descs *devm_gpiod_get_array_optional(struct device *dev,
+ const char *con_id,
+ enum gpiod_flags flags)
+
+A GPIO descriptor can be disposed of using the gpiod_put() function::
+
+ void gpiod_put(struct gpio_desc *desc)
+
+For an array of GPIOs this function can be used::
+
+ void gpiod_put_array(struct gpio_descs *descs)
+
+It is strictly forbidden to use a descriptor after calling these functions.
+It is also not allowed to individually release descriptors (using gpiod_put())
+from an array acquired with gpiod_get_array().
+
+The device-managed variants are, unsurprisingly::
+
+ void devm_gpiod_put(struct device *dev, struct gpio_desc *desc)
+
+ void devm_gpiod_put_array(struct device *dev, struct gpio_descs *descs)
+
+
+Using GPIOs
+===========
+
+Setting Direction
+-----------------
+The first thing a driver must do with a GPIO is setting its direction. If no
+direction-setting flags have been given to gpiod_get*(), this is done by
+invoking one of the gpiod_direction_*() functions::
+
+ int gpiod_direction_input(struct gpio_desc *desc)
+ int gpiod_direction_output(struct gpio_desc *desc, int value)
+
+The return value is zero for success, else a negative errno. It should be
+checked, since the get/set calls don't return errors and since misconfiguration
+is possible. You should normally issue these calls from a task context. However,
+for spinlock-safe GPIOs it is OK to use them before tasking is enabled, as part
+of early board setup.
+
+For output GPIOs, the value provided becomes the initial output value. This
+helps avoid signal glitching during system startup.
+
+A driver can also query the current direction of a GPIO::
+
+ int gpiod_get_direction(const struct gpio_desc *desc)
+
+This function returns 0 for output, 1 for input, or an error code in case of error.
+
+Be aware that there is no default direction for GPIOs. Therefore, **using a GPIO
+without setting its direction first is illegal and will result in undefined
+behavior!**
+
+
+Spinlock-Safe GPIO Access
+-------------------------
+Most GPIO controllers can be accessed with memory read/write instructions. Those
+don't need to sleep, and can safely be done from inside hard (non-threaded) IRQ
+handlers and similar contexts.
+
+Use the following calls to access GPIOs from an atomic context::
+
+ int gpiod_get_value(const struct gpio_desc *desc);
+ void gpiod_set_value(struct gpio_desc *desc, int value);
+
+The values are boolean, zero for low, nonzero for high. When reading the value
+of an output pin, the value returned should be what's seen on the pin. That
+won't always match the specified output value, because of issues including
+open-drain signaling and output latencies.
+
+The get/set calls do not return errors because "invalid GPIO" should have been
+reported earlier from gpiod_direction_*(). However, note that not all platforms
+can read the value of output pins; those that can't should always return zero.
+Also, using these calls for GPIOs that can't safely be accessed without sleeping
+(see below) is an error.
+
+
+GPIO Access That May Sleep
+--------------------------
+Some GPIO controllers must be accessed using message based buses like I2C or
+SPI. Commands to read or write those GPIO values require waiting to get to the
+head of a queue to transmit a command and get its response. This requires
+sleeping, which can't be done from inside IRQ handlers.
+
+Platforms that support this type of GPIO distinguish them from other GPIOs by
+returning nonzero from this call::
+
+ int gpiod_cansleep(const struct gpio_desc *desc)
+
+To access such GPIOs, a different set of accessors is defined::
+
+ int gpiod_get_value_cansleep(const struct gpio_desc *desc)
+ void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
+
+Accessing such GPIOs requires a context which may sleep, for example a threaded
+IRQ handler, and those accessors must be used instead of spinlock-safe
+accessors without the cansleep() name suffix.
+
+Other than the fact that these accessors might sleep, and will work on GPIOs
+that can't be accessed from hardIRQ handlers, these calls act the same as the
+spinlock-safe calls.
+
+
+The active low and open drain semantics
+---------------------------------------
+As a consumer should not have to care about the physical line level, all of the
+gpiod_set_value_xxx() or gpiod_set_array_value_xxx() functions operate with
+the *logical* value. With this they take the active low property into account.
+This means that they check whether the GPIO is configured to be active low,
+and if so, they manipulate the passed value before the physical line level is
+driven.
+
+The same is applicable for open drain or open source output lines: those do not
+actively drive their output high (open drain) or low (open source), they just
+switch their output to a high impedance value. The consumer should not need to
+care. (For details read about open drain in driver.txt.)
+
+With this, all the gpiod_set_(array)_value_xxx() functions interpret the
+parameter "value" as "asserted" ("1") or "de-asserted" ("0"). The physical line
+level will be driven accordingly.
+
+As an example, if the active low property for a dedicated GPIO is set, and the
+gpiod_set_(array)_value_xxx() passes "asserted" ("1"), the physical line level
+will be driven low.
+
+To summarize::
+
+ Function (example) line property physical line
+ gpiod_set_raw_value(desc, 0); don't care low
+ gpiod_set_raw_value(desc, 1); don't care high
+ gpiod_set_value(desc, 0); default (active high) low
+ gpiod_set_value(desc, 1); default (active high) high
+ gpiod_set_value(desc, 0); active low high
+ gpiod_set_value(desc, 1); active low low
+ gpiod_set_value(desc, 0); default (active high) low
+ gpiod_set_value(desc, 1); default (active high) high
+ gpiod_set_value(desc, 0); open drain low
+ gpiod_set_value(desc, 1); open drain high impedance
+ gpiod_set_value(desc, 0); open source high impedance
+ gpiod_set_value(desc, 1); open source high
+
+It is possible to override these semantics using the set_raw/get_raw functions
+but it should be avoided as much as possible, especially by system-agnostic drivers
+which should not need to care about the actual physical line level and worry about
+the logical value instead.
+
+
+Accessing raw GPIO values
+-------------------------
+Consumers exist that need to manage the logical state of a GPIO line, i.e. the value
+their device will actually receive, no matter what lies between it and the GPIO
+line.
+
+The following set of calls ignore the active-low or open drain property of a GPIO and
+work on the raw line value::
+
+ int gpiod_get_raw_value(const struct gpio_desc *desc)
+ void gpiod_set_raw_value(struct gpio_desc *desc, int value)
+ int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
+ void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)
+ int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
+
+The active low state of a GPIO can also be queried using the following call::
+
+ int gpiod_is_active_low(const struct gpio_desc *desc)
+
+Note that these functions should only be used with great moderation; a driver
+should not have to care about the physical line level or open drain semantics.
+
+
+Access multiple GPIOs with a single function call
+-------------------------------------------------
+The following functions get or set the values of an array of GPIOs::
+
+ int gpiod_get_array_value(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array);
+ int gpiod_get_raw_array_value(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array);
+ int gpiod_get_array_value_cansleep(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array);
+ int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array);
+
+ void gpiod_set_array_value(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+ void gpiod_set_raw_array_value(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+ void gpiod_set_array_value_cansleep(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+ void gpiod_set_raw_array_value_cansleep(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+
+The array can be an arbitrary set of GPIOs. The functions will try to access
+GPIOs belonging to the same bank or chip simultaneously if supported by the
+corresponding chip driver. In that case a significantly improved performance
+can be expected. If simultaneous access is not possible the GPIOs will be
+accessed sequentially.
+
+The functions take three arguments:
+ * array_size - the number of array elements
+ * desc_array - an array of GPIO descriptors
+ * value_array - an array to store the GPIOs' values (get) or
+ an array of values to assign to the GPIOs (set)
+
+The descriptor array can be obtained using the gpiod_get_array() function
+or one of its variants. If the group of descriptors returned by that function
+matches the desired group of GPIOs, those GPIOs can be accessed by simply using
+the struct gpio_descs returned by gpiod_get_array()::
+
+ struct gpio_descs *my_gpio_descs = gpiod_get_array(...);
+ gpiod_set_array_value(my_gpio_descs->ndescs, my_gpio_descs->desc,
+ my_gpio_values);
+
+It is also possible to access a completely arbitrary array of descriptors. The
+descriptors may be obtained using any combination of gpiod_get() and
+gpiod_get_array(). Afterwards the array of descriptors has to be setup
+manually before it can be passed to one of the above functions.
+
+Note that for optimal performance GPIOs belonging to the same chip should be
+contiguous within the array of descriptors.
+
+The return value of gpiod_get_array_value() and its variants is 0 on success
+or negative on error. Note the difference to gpiod_get_value(), which returns
+0 or 1 on success to convey the GPIO value. With the array functions, the GPIO
+values are stored in value_array rather than passed back as return value.
+
+
+GPIOs mapped to IRQs
+--------------------
+GPIO lines can quite often be used as IRQs. You can get the IRQ number
+corresponding to a given GPIO using the following call::
+
+ int gpiod_to_irq(const struct gpio_desc *desc)
+
+It will return an IRQ number, or a negative errno code if the mapping can't be
+done (most likely because that particular GPIO cannot be used as IRQ). It is an
+unchecked error to use a GPIO that wasn't set up as an input using
+gpiod_direction_input(), or to use an IRQ number that didn't originally come
+from gpiod_to_irq(). gpiod_to_irq() is not allowed to sleep.
+
+Non-error values returned from gpiod_to_irq() can be passed to request_irq() or
+free_irq(). They will often be stored into IRQ resources for platform devices,
+by the board-specific initialization code. Note that IRQ trigger options are
+part of the IRQ interface, e.g. IRQF_TRIGGER_FALLING, as are system wakeup
+capabilities.
+
+
+GPIOs and ACPI
+==============
+
+On ACPI systems, GPIOs are described by GpioIo()/GpioInt() resources listed by
+the _CRS configuration objects of devices. Those resources do not provide
+connection IDs (names) for GPIOs, so it is necessary to use an additional
+mechanism for this purpose.
+
+Systems compliant with ACPI 5.1 or newer may provide a _DSD configuration object
+which, among other things, may be used to provide connection IDs for specific
+GPIOs described by the GpioIo()/GpioInt() resources in _CRS. If that is the
+case, it will be handled by the GPIO subsystem automatically. However, if the
+_DSD is not present, the mappings between GpioIo()/GpioInt() resources and GPIO
+connection IDs need to be provided by device drivers.
+
+For details refer to Documentation/acpi/gpio-properties.txt
+
+
+Interacting With the Legacy GPIO Subsystem
+==========================================
+Many kernel subsystems still handle GPIOs using the legacy integer-based
+interface. Although it is strongly encouraged to upgrade them to the safer
+descriptor-based API, the following two functions allow you to convert a GPIO
+descriptor into the GPIO integer namespace and vice-versa::
+
+ int desc_to_gpio(const struct gpio_desc *desc)
+ struct gpio_desc *gpio_to_desc(unsigned gpio)
+
+The GPIO number returned by desc_to_gpio() can be safely used as long as the
+GPIO descriptor has not been freed. All the same, a GPIO number passed to
+gpio_to_desc() must have been properly acquired, and usage of the returned GPIO
+descriptor is only possible after the GPIO number has been released.
+
+Freeing a GPIO obtained by one API with the other API is forbidden and an
+unchecked error.
diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst
new file mode 100644
index 000000000000..505ee906d7d9
--- /dev/null
+++ b/Documentation/driver-api/gpio/driver.rst
@@ -0,0 +1,429 @@
+================================
+GPIO Descriptor Driver Interface
+================================
+
+This document serves as a guide for GPIO chip drivers writers. Note that it
+describes the new descriptor-based interface. For a description of the
+deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
+
+Each GPIO controller driver needs to include the following header, which defines
+the structures used to define a GPIO driver:
+
+ #include <linux/gpio/driver.h>
+
+
+Internal Representation of GPIOs
+================================
+
+Inside a GPIO driver, individual GPIOs are identified by their hardware number,
+which is a unique number between 0 and n, n being the number of GPIOs managed by
+the chip. This number is purely internal: the hardware number of a particular
+GPIO descriptor is never made visible outside of the driver.
+
+On top of this internal number, each GPIO also need to have a global number in
+the integer GPIO namespace so that it can be used with the legacy GPIO
+interface. Each chip must thus have a "base" number (which can be automatically
+assigned), and for each GPIO the global number will be (base + hardware number).
+Although the integer representation is considered deprecated, it still has many
+users and thus needs to be maintained.
+
+So for example one platform could use numbers 32-159 for GPIOs, with a
+controller defining 128 GPIOs at a "base" of 32 ; while another platform uses
+numbers 0..63 with one set of GPIO controllers, 64-79 with another type of GPIO
+controller, and on one particular board 80-95 with an FPGA. The numbers need not
+be contiguous; either of those platforms could also use numbers 2000-2063 to
+identify GPIOs in a bank of I2C GPIO expanders.
+
+
+Controller Drivers: gpio_chip
+=============================
+
+In the gpiolib framework each GPIO controller is packaged as a "struct
+gpio_chip" (see linux/gpio/driver.h for its complete definition) with members
+common to each controller of that type:
+
+ - methods to establish GPIO line direction
+ - methods used to access GPIO line values
+ - method to set electrical configuration to a a given GPIO line
+ - method to return the IRQ number associated to a given GPIO line
+ - flag saying whether calls to its methods may sleep
+ - optional line names array to identify lines
+ - optional debugfs dump method (showing extra state like pullup config)
+ - optional base number (will be automatically assigned if omitted)
+ - optional label for diagnostics and GPIO chip mapping using platform data
+
+The code implementing a gpio_chip should support multiple instances of the
+controller, possibly using the driver model. That code will configure each
+gpio_chip and issue ``gpiochip_add[_data]()`` or ``devm_gpiochip_add_data()``.
+Removing a GPIO controller should be rare; use ``[devm_]gpiochip_remove()``
+when it is unavoidable.
+
+Often a gpio_chip is part of an instance-specific structure with states not
+exposed by the GPIO interfaces, such as addressing, power management, and more.
+Chips such as audio codecs will have complex non-GPIO states.
+
+Any debugfs dump method should normally ignore signals which haven't been
+requested as GPIOs. They can use gpiochip_is_requested(), which returns either
+NULL or the label associated with that GPIO when it was requested.
+
+RT_FULL: the GPIO driver should not use spinlock_t or any sleepable APIs
+(like PM runtime) in its gpio_chip implementation (.get/.set and direction
+control callbacks) if it is expected to call GPIO APIs from atomic context
+on -RT (inside hard IRQ handlers and similar contexts). Normally this should
+not be required.
+
+
+GPIO electrical configuration
+-----------------------------
+
+GPIOs can be configured for several electrical modes of operation by using the
+.set_config() callback. Currently this API supports setting debouncing and
+single-ended modes (open drain/open source). These settings are described
+below.
+
+The .set_config() callback uses the same enumerators and configuration
+semantics as the generic pin control drivers. This is not a coincidence: it is
+possible to assign the .set_config() to the function gpiochip_generic_config()
+which will result in pinctrl_gpio_set_config() being called and eventually
+ending up in the pin control back-end "behind" the GPIO controller, usually
+closer to the actual pins. This way the pin controller can manage the below
+listed GPIO configurations.
+
+If a pin controller back-end is used, the GPIO controller or hardware
+description needs to provide "GPIO ranges" mapping the GPIO line offsets to pin
+numbers on the pin controller so they can properly cross-reference each other.
+
+
+GPIOs with debounce support
+---------------------------
+
+Debouncing is a configuration set to a pin indicating that it is connected to
+a mechanical switch or button, or similar that may bounce. Bouncing means the
+line is pulled high/low quickly at very short intervals for mechanical
+reasons. This can result in the value being unstable or irqs fireing repeatedly
+unless the line is debounced.
+
+Debouncing in practice involves setting up a timer when something happens on
+the line, wait a little while and then sample the line again, so see if it
+still has the same value (low or high). This could also be repeated by a clever
+state machine, waiting for a line to become stable. In either case, it sets
+a certain number of milliseconds for debouncing, or just "on/off" if that time
+is not configurable.
+
+
+GPIOs with open drain/source support
+------------------------------------
+
+Open drain (CMOS) or open collector (TTL) means the line is not actively driven
+high: instead you provide the drain/collector as output, so when the transistor
+is not open, it will present a high-impedance (tristate) to the external rail::
+
+
+ CMOS CONFIGURATION TTL CONFIGURATION
+
+ ||--- out +--- out
+ in ----|| |/
+ ||--+ in ----|
+ | |\
+ GND GND
+
+This configuration is normally used as a way to achieve one of two things:
+
+- Level-shifting: to reach a logical level higher than that of the silicon
+ where the output resides.
+
+- inverse wire-OR on an I/O line, for example a GPIO line, making it possible
+ for any driving stage on the line to drive it low even if any other output
+ to the same line is simultaneously driving it high. A special case of this
+ is driving the SCL and SCA lines of an I2C bus, which is by definition a
+ wire-OR bus.
+
+Both usecases require that the line be equipped with a pull-up resistor. This
+resistor will make the line tend to high level unless one of the transistors on
+the rail actively pulls it down.
+
+The level on the line will go as high as the VDD on the pull-up resistor, which
+may be higher than the level supported by the transistor, achieveing a
+level-shift to the higher VDD.
+
+Integrated electronics often have an output driver stage in the form of a CMOS
+"totem-pole" with one N-MOS and one P-MOS transistor where one of them drives
+the line high and one of them drives the line low. This is called a push-pull
+output. The "totem-pole" looks like so::
+
+ VDD
+ |
+ OD ||--+
+ +--/ ---o|| P-MOS-FET
+ | ||--+
+ IN --+ +----- out
+ | ||--+
+ +--/ ----|| N-MOS-FET
+ OS ||--+
+ |
+ GND
+
+The desired output signal (e.g. coming directly from some GPIO output register)
+arrives at IN. The switches named "OD" and "OS" are normally closed, creating
+a push-pull circuit.
+
+Consider the little "switches" named "OD" and "OS" that enable/disable the
+P-MOS or N-MOS transistor right after the split of the input. As you can see,
+either transistor will go totally numb if this switch is open. The totem-pole
+is then halved and give high impedance instead of actively driving the line
+high or low respectively. That is usually how software-controlled open
+drain/source works.
+
+Some GPIO hardware come in open drain / open source configuration. Some are
+hard-wired lines that will only support open drain or open source no matter
+what: there is only one transistor there. Some are software-configurable:
+by flipping a bit in a register the output can be configured as open drain
+or open source, in practice by flicking open the switches labeled "OD" and "OS"
+in the drawing above.
+
+By disabling the P-MOS transistor, the output can be driven between GND and
+high impedance (open drain), and by disabling the N-MOS transistor, the output
+can be driven between VDD and high impedance (open source). In the first case,
+a pull-up resistor is needed on the outgoing rail to complete the circuit, and
+in the second case, a pull-down resistor is needed on the rail.
+
+Hardware that supports open drain or open source or both, can implement a
+special callback in the gpio_chip: .set_config() that takes a generic
+pinconf packed value telling whether to configure the line as open drain,
+open source or push-pull. This will happen in response to the
+GPIO_OPEN_DRAIN or GPIO_OPEN_SOURCE flag set in the machine file, or coming
+from other hardware descriptions.
+
+If this state can not be configured in hardware, i.e. if the GPIO hardware does
+not support open drain/open source in hardware, the GPIO library will instead
+use a trick: when a line is set as output, if the line is flagged as open
+drain, and the IN output value is low, it will be driven low as usual. But
+if the IN output value is set to high, it will instead *NOT* be driven high,
+instead it will be switched to input, as input mode is high impedance, thus
+achieveing an "open drain emulation" of sorts: electrically the behaviour will
+be identical, with the exception of possible hardware glitches when switching
+the mode of the line.
+
+For open source configuration the same principle is used, just that instead
+of actively driving the line low, it is set to input.
+
+
+GPIO drivers providing IRQs
+---------------------------
+It is custom that GPIO drivers (GPIO chips) are also providing interrupts,
+most often cascaded off a parent interrupt controller, and in some special
+cases the GPIO logic is melded with a SoC's primary interrupt controller.
+
+The IRQ portions of the GPIO block are implemented using an irqchip, using
+the header <linux/irq.h>. So basically such a driver is utilizing two sub-
+systems simultaneously: gpio and irq.
+
+RT_FULL: a realtime compliant GPIO driver should not use spinlock_t or any
+sleepable APIs (like PM runtime) as part of its irq_chip implementation.
+
+* spinlock_t should be replaced with raw_spinlock_t [1].
+* If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
+ and .irq_bus_unlock() callbacks, as these are the only slowpath callbacks
+ on an irqchip. Create the callbacks if needed [2].
+
+GPIO irqchips usually fall in one of two categories:
+
+* CHAINED GPIO irqchips: these are usually the type that is embedded on
+ an SoC. This means that there is a fast IRQ flow handler for the GPIOs that
+ gets called in a chain from the parent IRQ handler, most typically the
+ system interrupt controller. This means that the GPIO irqchip handler will
+ be called immediately from the parent irqchip, while holding the IRQs
+ disabled. The GPIO irqchip will then end up calling something like this
+ sequence in its interrupt handler::
+
+ static irqreturn_t foo_gpio_irq(int irq, void *data)
+ chained_irq_enter(...);
+ generic_handle_irq(...);
+ chained_irq_exit(...);
+
+ Chained GPIO irqchips typically can NOT set the .can_sleep flag on
+ struct gpio_chip, as everything happens directly in the callbacks: no
+ slow bus traffic like I2C can be used.
+
+ RT_FULL: Note, chained IRQ handlers will not be forced threaded on -RT.
+ As result, spinlock_t or any sleepable APIs (like PM runtime) can't be used
+ in chained IRQ handler.
+ If required (and if it can't be converted to the nested threaded GPIO irqchip)
+ a chained IRQ handler can be converted to generic irq handler and this way
+ it will be a threaded IRQ handler on -RT and a hard IRQ handler on non-RT
+ (for example, see [3]).
+ Know W/A: The generic_handle_irq() is expected to be called with IRQ disabled,
+ so the IRQ core will complain if it is called from an IRQ handler which is
+ forced to a thread. The "fake?" raw lock can be used to W/A this problem::
+
+ raw_spinlock_t wa_lock;
+ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
+ unsigned long wa_lock_flags;
+ raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
+ generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
+ raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
+
+* GENERIC CHAINED GPIO irqchips: these are the same as "CHAINED GPIO irqchips",
+ but chained IRQ handlers are not used. Instead GPIO IRQs dispatching is
+ performed by generic IRQ handler which is configured using request_irq().
+ The GPIO irqchip will then end up calling something like this sequence in
+ its interrupt handler::
+
+ static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
+ for each detected GPIO IRQ
+ generic_handle_irq(...);
+
+ RT_FULL: Such kind of handlers will be forced threaded on -RT, as result IRQ
+ core will complain that generic_handle_irq() is called with IRQ enabled and
+ the same W/A as for "CHAINED GPIO irqchips" can be applied.
+
+* NESTED THREADED GPIO irqchips: these are off-chip GPIO expanders and any
+ other GPIO irqchip residing on the other side of a sleeping bus. Of course
+ such drivers that need slow bus traffic to read out IRQ status and similar,
+ traffic which may in turn incur other IRQs to happen, cannot be handled
+ in a quick IRQ handler with IRQs disabled. Instead they need to spawn a
+ thread and then mask the parent IRQ line until the interrupt is handled
+ by the driver. The hallmark of this driver is to call something like
+ this in its interrupt handler::
+
+ static irqreturn_t foo_gpio_irq(int irq, void *data)
+ ...
+ handle_nested_irq(irq);
+
+ The hallmark of threaded GPIO irqchips is that they set the .can_sleep
+ flag on struct gpio_chip to true, indicating that this chip may sleep
+ when accessing the GPIOs.
+
+To help out in handling the set-up and management of GPIO irqchips and the
+associated irqdomain and resource allocation callbacks, the gpiolib has
+some helpers that can be enabled by selecting the GPIOLIB_IRQCHIP Kconfig
+symbol:
+
+* gpiochip_irqchip_add(): adds a chained irqchip to a gpiochip. It will pass
+ the struct gpio_chip* for the chip to all IRQ callbacks, so the callbacks
+ need to embed the gpio_chip in its state container and obtain a pointer
+ to the container using container_of().
+ (See Documentation/driver-model/design-patterns.txt)
+
+* gpiochip_irqchip_add_nested(): adds a nested irqchip to a gpiochip.
+ Apart from that it works exactly like the chained irqchip.
+
+* gpiochip_set_chained_irqchip(): sets up a chained irq handler for a
+ gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler
+ data. (Notice handler data, since the irqchip data is likely used by the
+ parent irqchip!).
+
+* gpiochip_set_nested_irqchip(): sets up a nested irq handler for a
+ gpio_chip from a parent IRQ. As the parent IRQ has usually been
+ explicitly requested by the driver, this does very little more than
+ mark all the child IRQs as having the other IRQ as parent.
+
+If there is a need to exclude certain GPIOs from the IRQ domain, you can
+set .irq.need_valid_mask of the gpiochip before gpiochip_add_data() is
+called. This allocates an .irq.valid_mask with as many bits set as there
+are GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this
+mask. The mask must be filled in before gpiochip_irqchip_add() or
+gpiochip_irqchip_add_nested() is called.
+
+To use the helpers please keep the following in mind:
+
+- Make sure to assign all relevant members of the struct gpio_chip so that
+ the irqchip can initialize. E.g. .dev and .can_sleep shall be set up
+ properly.
+
+- Nominally set all handlers to handle_bad_irq() in the setup call and pass
+ handle_bad_irq() as flow handler parameter in gpiochip_irqchip_add() if it is
+ expected for GPIO driver that irqchip .set_type() callback have to be called
+ before using/enabling GPIO IRQ. Then set the handler to handle_level_irq()
+ and/or handle_edge_irq() in the irqchip .set_type() callback depending on
+ what your controller supports.
+
+It is legal for any IRQ consumer to request an IRQ from any irqchip no matter
+if that is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
+irq_chip are orthogonal, and offering their services independent of each
+other.
+
+gpiod_to_irq() is just a convenience function to figure out the IRQ for a
+certain GPIO line and should not be relied upon to have been called before
+the IRQ is used.
+
+So always prepare the hardware and make it ready for action in respective
+callbacks from the GPIO and irqchip APIs. Do not rely on gpiod_to_irq() having
+been called first.
+
+This orthogonality leads to ambiguities that we need to solve: if there is
+competition inside the subsystem which side is using the resource (a certain
+GPIO line and register for example) it needs to deny certain operations and
+keep track of usage inside of the gpiolib subsystem. This is why the API
+below exists.
+
+
+Locking IRQ usage
+-----------------
+Input GPIOs can be used as IRQ signals. When this happens, a driver is requested
+to mark the GPIO as being used as an IRQ::
+
+ int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
+
+This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
+is released::
+
+ void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
+
+When implementing an irqchip inside a GPIO driver, these two functions should
+typically be called in the .startup() and .shutdown() callbacks from the
+irqchip.
+
+When using the gpiolib irqchip helpers, these callback are automatically
+assigned.
+
+Real-Time compliance for GPIO IRQ chips
+---------------------------------------
+
+Any provider of irqchips needs to be carefully tailored to support Real Time
+preemption. It is desirable that all irqchips in the GPIO subsystem keep this
+in mind and does the proper testing to assure they are real time-enabled.
+So, pay attention on above " RT_FULL:" notes, please.
+The following is a checklist to follow when preparing a driver for real
+time-compliance:
+
+- ensure spinlock_t is not used as part irq_chip implementation;
+- ensure that sleepable APIs are not used as part irq_chip implementation.
+ If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
+ and .irq_bus_unlock() callbacks;
+- Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
+ from chained IRQ handler;
+- Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
+ apply corresponding W/A;
+- Chained GPIO irqchips: get rid of chained IRQ handler and use generic irq
+ handler if possible :)
+- regmap_mmio: Sry, but you are in trouble :( if MMIO regmap is used as for
+ GPIO IRQ chip implementation;
+- Test your driver with the appropriate in-kernel real time test cases for both
+ level and edge IRQs.
+
+
+Requesting self-owned GPIO pins
+-------------------------------
+
+Sometimes it is useful to allow a GPIO chip driver to request its own GPIO
+descriptors through the gpiolib API. Using gpio_request() for this purpose
+does not help since it pins the module to the kernel forever (it calls
+try_module_get()). A GPIO driver can use the following functions instead
+to request and free descriptors without being pinned to the kernel forever::
+
+ struct gpio_desc *gpiochip_request_own_desc(struct gpio_desc *desc,
+ const char *label)
+
+ void gpiochip_free_own_desc(struct gpio_desc *desc)
+
+Descriptors requested with gpiochip_request_own_desc() must be released with
+gpiochip_free_own_desc().
+
+These functions must be used with care since they do not affect module use
+count. Do not use the functions to request gpio descriptors not owned by the
+calling driver.
+
+* [1] http://www.spinics.net/lists/linux-omap/msg120425.html
+* [2] https://lkml.org/lkml/2015/9/25/494
+* [3] https://lkml.org/lkml/2015/9/25/495
diff --git a/Documentation/driver-api/gpio/drivers-on-gpio.rst b/Documentation/driver-api/gpio/drivers-on-gpio.rst
new file mode 100644
index 000000000000..7da0c1dd1f7a
--- /dev/null
+++ b/Documentation/driver-api/gpio/drivers-on-gpio.rst
@@ -0,0 +1,97 @@
+============================
+Subsystem drivers using GPIO
+============================
+
+Note that standard kernel drivers exist for common GPIO tasks and will provide
+the right in-kernel and userspace APIs/ABIs for the job, and that these
+drivers can quite easily interconnect with other kernel subsystems using
+hardware descriptions such as device tree or ACPI:
+
+- leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
+ lines, giving you the LED sysfs interface
+
+- ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
+ i.e. a LED will turn on/off in response to a GPIO line going high or low
+ (and that LED may in turn use the leds-gpio as per above).
+
+- gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
+ can generate interrupts in response to a key press. Also supports debounce.
+
+- gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
+ GPIO line cannot generate interrupts, so it needs to be periodically polled
+ by a timer.
+
+- gpio_mouse: drivers/input/mouse/gpio_mouse.c is used to provide a mouse with
+ up to three buttons by simply using GPIOs and no mouse port. You can cut the
+ mouse cable and connect the wires to GPIO lines or solder a mouse connector
+ to the lines for a more permanent solution of this type.
+
+- gpio-beeper: drivers/input/misc/gpio-beeper.c is used to provide a beep from
+ an external speaker connected to a GPIO line.
+
+- extcon-gpio: drivers/extcon/extcon-gpio.c is used when you need to read an
+ external connector status, such as a headset line for an audio driver or an
+ HDMI connector. It will provide a better userspace sysfs interface than GPIO.
+
+- restart-gpio: drivers/power/reset/gpio-restart.c is used to restart/reboot
+ the system by pulling a GPIO line and will register a restart handler so
+ userspace can issue the right system call to restart the system.
+
+- poweroff-gpio: drivers/power/reset/gpio-poweroff.c is used to power the
+ system down by pulling a GPIO line and will register a pm_power_off()
+ callback so that userspace can issue the right system call to power down the
+ system.
+
+- gpio-gate-clock: drivers/clk/clk-gpio.c is used to control a gated clock
+ (off/on) that uses a GPIO, and integrated with the clock subsystem.
+
+- i2c-gpio: drivers/i2c/busses/i2c-gpio.c is used to drive an I2C bus
+ (two wires, SDA and SCL lines) by hammering (bitbang) two GPIO lines. It will
+ appear as any other I2C bus to the system and makes it possible to connect
+ drivers for the I2C devices on the bus like any other I2C bus driver.
+
+- spi_gpio: drivers/spi/spi-gpio.c is used to drive an SPI bus (variable number
+ of wires, at least SCK and optionally MISO, MOSI and chip select lines) using
+ GPIO hammering (bitbang). It will appear as any other SPI bus on the system
+ and makes it possible to connect drivers for SPI devices on the bus like
+ any other SPI bus driver. For example any MMC/SD card can then be connected
+ to this SPI by using the mmc_spi host from the MMC/SD card subsystem.
+
+- w1-gpio: drivers/w1/masters/w1-gpio.c is used to drive a one-wire bus using
+ a GPIO line, integrating with the W1 subsystem and handling devices on
+ the bus like any other W1 device.
+
+- gpio-fan: drivers/hwmon/gpio-fan.c is used to control a fan for cooling the
+ system, connected to a GPIO line (and optionally a GPIO alarm line),
+ presenting all the right in-kernel and sysfs interfaces to make your system
+ not overheat.
+
+- gpio-regulator: drivers/regulator/gpio-regulator.c is used to control a
+ regulator providing a certain voltage by pulling a GPIO line, integrating
+ with the regulator subsystem and giving you all the right interfaces.
+
+- gpio-wdt: drivers/watchdog/gpio_wdt.c is used to provide a watchdog timer
+ that will periodically "ping" a hardware connected to a GPIO line by toggling
+ it from 1-to-0-to-1. If that hardware does not receive its "ping"
+ periodically, it will reset the system.
+
+- gpio-nand: drivers/mtd/nand/raw/gpio.c is used to connect a NAND flash chip
+ to a set of simple GPIO lines: RDY, NCE, ALE, CLE, NWP. It interacts with the
+ NAND flash MTD subsystem and provides chip access and partition parsing like
+ any other NAND driving hardware.
+
+- ps2-gpio: drivers/input/serio/ps2-gpio.c is used to drive a PS/2 (IBM) serio
+ bus, data and clock line, by bit banging two GPIO lines. It will appear as
+ any other serio bus to the system and makes it possible to connect drivers
+ for e.g. keyboards and other PS/2 protocol based devices.
+
+Apart from this there are special GPIO drivers in subsystems like MMC/SD to
+read card detect and write protect GPIO lines, and in the TTY serial subsystem
+to emulate MCTRL (modem control) signals CTS/RTS by using two GPIO lines. The
+MTD NOR flash has add-ons for extra GPIO lines too, though the address bus is
+usually connected directly to the flash.
+
+Use those instead of talking directly to the GPIOs using sysfs; they integrate
+with kernel frameworks better than your userspace code could. Needless to say,
+just using the appropriate kernel drivers will simplify and speed up your
+embedded hacking in particular by providing ready-made components.
diff --git a/Documentation/driver-api/gpio/index.rst b/Documentation/driver-api/gpio/index.rst
new file mode 100644
index 000000000000..6a374ded1287
--- /dev/null
+++ b/Documentation/driver-api/gpio/index.rst
@@ -0,0 +1,48 @@
+===================================
+General Purpose Input/Output (GPIO)
+===================================
+
+Contents:
+
+.. toctree::
+ :maxdepth: 2
+
+ intro
+ driver
+ consumer
+ board
+ drivers-on-gpio
+ legacy
+
+Core
+====
+
+.. kernel-doc:: include/linux/gpio/driver.h
+ :internal:
+
+.. kernel-doc:: drivers/gpio/gpiolib.c
+ :export:
+
+ACPI support
+============
+
+.. kernel-doc:: drivers/gpio/gpiolib-acpi.c
+ :export:
+
+Device tree support
+===================
+
+.. kernel-doc:: drivers/gpio/gpiolib-of.c
+ :export:
+
+Device-managed API
+==================
+
+.. kernel-doc:: drivers/gpio/devres.c
+ :export:
+
+sysfs helpers
+=============
+
+.. kernel-doc:: drivers/gpio/gpiolib-sysfs.c
+ :export:
diff --git a/Documentation/driver-api/gpio/intro.rst b/Documentation/driver-api/gpio/intro.rst
new file mode 100644
index 000000000000..74591489d0b5
--- /dev/null
+++ b/Documentation/driver-api/gpio/intro.rst
@@ -0,0 +1,124 @@
+============
+Introduction
+============
+
+
+GPIO Interfaces
+===============
+
+The documents in this directory give detailed instructions on how to access
+GPIOs in drivers, and how to write a driver for a device that provides GPIOs
+itself.
+
+Due to the history of GPIO interfaces in the kernel, there are two different
+ways to obtain and use GPIOs:
+
+ - The descriptor-based interface is the preferred way to manipulate GPIOs,
+ and is described by all the files in this directory excepted gpio-legacy.txt.
+ - The legacy integer-based interface which is considered deprecated (but still
+ usable for compatibility reasons) is documented in gpio-legacy.txt.
+
+The remainder of this document applies to the new descriptor-based interface.
+gpio-legacy.txt contains the same information applied to the legacy
+integer-based interface.
+
+
+What is a GPIO?
+===============
+
+A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
+digital signal. They are provided from many kinds of chip, and are familiar
+to Linux developers working with embedded and custom hardware. Each GPIO
+represents a bit connected to a particular pin, or "ball" on Ball Grid Array
+(BGA) packages. Board schematics show which external hardware connects to
+which GPIOs. Drivers can be written generically, so that board setup code
+passes such pin configuration data to drivers.
+
+System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
+non-dedicated pin can be configured as a GPIO; and most chips have at least
+several dozen of them. Programmable logic devices (like FPGAs) can easily
+provide GPIOs; multifunction chips like power managers, and audio codecs
+often have a few such pins to help with pin scarcity on SOCs; and there are
+also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
+Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
+firmware knowing how they're used).
+
+The exact capabilities of GPIOs vary between systems. Common options:
+
+ - Output values are writable (high=1, low=0). Some chips also have
+ options about how that value is driven, so that for example only one
+ value might be driven, supporting "wire-OR" and similar schemes for the
+ other value (notably, "open drain" signaling).
+
+ - Input values are likewise readable (1, 0). Some chips support readback
+ of pins configured as "output", which is very useful in such "wire-OR"
+ cases (to support bidirectional signaling). GPIO controllers may have
+ input de-glitch/debounce logic, sometimes with software controls.
+
+ - Inputs can often be used as IRQ signals, often edge triggered but
+ sometimes level triggered. Such IRQs may be configurable as system
+ wakeup events, to wake the system from a low power state.
+
+ - Usually a GPIO will be configurable as either input or output, as needed
+ by different product boards; single direction ones exist too.
+
+ - Most GPIOs can be accessed while holding spinlocks, but those accessed
+ through a serial bus normally can't. Some systems support both types.
+
+On a given board each GPIO is used for one specific purpose like monitoring
+MMC/SD card insertion/removal, detecting card write-protect status, driving
+a LED, configuring a transceiver, bit-banging a serial bus, poking a hardware
+watchdog, sensing a switch, and so on.
+
+
+Common GPIO Properties
+======================
+
+These properties are met through all the other documents of the GPIO interface
+and it is useful to understand them, especially if you need to define GPIO
+mappings.
+
+Active-High and Active-Low
+--------------------------
+It is natural to assume that a GPIO is "active" when its output signal is 1
+("high"), and inactive when it is 0 ("low"). However in practice the signal of a
+GPIO may be inverted before is reaches its destination, or a device could decide
+to have different conventions about what "active" means. Such decisions should
+be transparent to device drivers, therefore it is possible to define a GPIO as
+being either active-high ("1" means "active", the default) or active-low ("0"
+means "active") so that drivers only need to worry about the logical signal and
+not about what happens at the line level.
+
+Open Drain and Open Source
+--------------------------
+Sometimes shared signals need to use "open drain" (where only the low signal
+level is actually driven), or "open source" (where only the high signal level is
+driven) signaling. That term applies to CMOS transistors; "open collector" is
+used for TTL. A pullup or pulldown resistor causes the high or low signal level.
+This is sometimes called a "wire-AND"; or more practically, from the negative
+logic (low=true) perspective this is a "wire-OR".
+
+One common example of an open drain signal is a shared active-low IRQ line.
+Also, bidirectional data bus signals sometimes use open drain signals.
+
+Some GPIO controllers directly support open drain and open source outputs; many
+don't. When you need open drain signaling but your hardware doesn't directly
+support it, there's a common idiom you can use to emulate it with any GPIO pin
+that can be used as either an input or an output:
+
+ LOW: gpiod_direction_output(gpio, 0) ... this drives the signal and overrides
+ the pullup.
+
+ HIGH: gpiod_direction_input(gpio) ... this turns off the output, so the pullup
+ (or some other device) controls the signal.
+
+The same logic can be applied to emulate open source signaling, by driving the
+high signal and configuring the GPIO as input for low. This open drain/open
+source emulation can be handled transparently by the GPIO framework.
+
+If you are "driving" the signal high but gpiod_get_value(gpio) reports a low
+value (after the appropriate rise time passes), you know some other component is
+driving the shared signal low. That's not necessarily an error. As one common
+example, that's how I2C clocks are stretched: a slave that needs a slower clock
+delays the rising edge of SCK, and the I2C master adjusts its signaling rate
+accordingly.
diff --git a/Documentation/driver-api/gpio/legacy.rst b/Documentation/driver-api/gpio/legacy.rst
new file mode 100644
index 000000000000..5e9421e05f1d
--- /dev/null
+++ b/Documentation/driver-api/gpio/legacy.rst
@@ -0,0 +1,770 @@
+======================
+Legacy GPIO Interfaces
+======================
+
+This provides an overview of GPIO access conventions on Linux.
+
+These calls use the gpio_* naming prefix. No other calls should use that
+prefix, or the related __gpio_* prefix.
+
+
+What is a GPIO?
+===============
+A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
+digital signal. They are provided from many kinds of chip, and are familiar
+to Linux developers working with embedded and custom hardware. Each GPIO
+represents a bit connected to a particular pin, or "ball" on Ball Grid Array
+(BGA) packages. Board schematics show which external hardware connects to
+which GPIOs. Drivers can be written generically, so that board setup code
+passes such pin configuration data to drivers.
+
+System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
+non-dedicated pin can be configured as a GPIO; and most chips have at least
+several dozen of them. Programmable logic devices (like FPGAs) can easily
+provide GPIOs; multifunction chips like power managers, and audio codecs
+often have a few such pins to help with pin scarcity on SOCs; and there are
+also "GPIO Expander" chips that connect using the I2C or SPI serial busses.
+Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
+firmware knowing how they're used).
+
+The exact capabilities of GPIOs vary between systems. Common options:
+
+ - Output values are writable (high=1, low=0). Some chips also have
+ options about how that value is driven, so that for example only one
+ value might be driven ... supporting "wire-OR" and similar schemes
+ for the other value (notably, "open drain" signaling).
+
+ - Input values are likewise readable (1, 0). Some chips support readback
+ of pins configured as "output", which is very useful in such "wire-OR"
+ cases (to support bidirectional signaling). GPIO controllers may have
+ input de-glitch/debounce logic, sometimes with software controls.
+
+ - Inputs can often be used as IRQ signals, often edge triggered but
+ sometimes level triggered. Such IRQs may be configurable as system
+ wakeup events, to wake the system from a low power state.
+
+ - Usually a GPIO will be configurable as either input or output, as needed
+ by different product boards; single direction ones exist too.
+
+ - Most GPIOs can be accessed while holding spinlocks, but those accessed
+ through a serial bus normally can't. Some systems support both types.
+
+On a given board each GPIO is used for one specific purpose like monitoring
+MMC/SD card insertion/removal, detecting card writeprotect status, driving
+a LED, configuring a transceiver, bitbanging a serial bus, poking a hardware
+watchdog, sensing a switch, and so on.
+
+
+GPIO conventions
+================
+Note that this is called a "convention" because you don't need to do it this
+way, and it's no crime if you don't. There **are** cases where portability
+is not the main issue; GPIOs are often used for the kind of board-specific
+glue logic that may even change between board revisions, and can't ever be
+used on a board that's wired differently. Only least-common-denominator
+functionality can be very portable. Other features are platform-specific,
+and that can be critical for glue logic.
+
+Plus, this doesn't require any implementation framework, just an interface.
+One platform might implement it as simple inline functions accessing chip
+registers; another might implement it by delegating through abstractions
+used for several very different kinds of GPIO controller. (There is some
+optional code supporting such an implementation strategy, described later
+in this document, but drivers acting as clients to the GPIO interface must
+not care how it's implemented.)
+
+That said, if the convention is supported on their platform, drivers should
+use it when possible. Platforms must select GPIOLIB if GPIO functionality
+is strictly required. Drivers that can't work without
+standard GPIO calls should have Kconfig entries which depend on GPIOLIB. The
+GPIO calls are available, either as "real code" or as optimized-away stubs,
+when drivers use the include file:
+
+ #include <linux/gpio.h>
+
+If you stick to this convention then it'll be easier for other developers to
+see what your code is doing, and help maintain it.
+
+Note that these operations include I/O barriers on platforms which need to
+use them; drivers don't need to add them explicitly.
+
+
+Identifying GPIOs
+-----------------
+GPIOs are identified by unsigned integers in the range 0..MAX_INT. That
+reserves "negative" numbers for other purposes like marking signals as
+"not available on this board", or indicating faults. Code that doesn't
+touch the underlying hardware treats these integers as opaque cookies.
+
+Platforms define how they use those integers, and usually #define symbols
+for the GPIO lines so that board-specific setup code directly corresponds
+to the relevant schematics. In contrast, drivers should only use GPIO
+numbers passed to them from that setup code, using platform_data to hold
+board-specific pin configuration data (along with other board specific
+data they need). That avoids portability problems.
+
+So for example one platform uses numbers 32-159 for GPIOs; while another
+uses numbers 0..63 with one set of GPIO controllers, 64-79 with another
+type of GPIO controller, and on one particular board 80-95 with an FPGA.
+The numbers need not be contiguous; either of those platforms could also
+use numbers 2000-2063 to identify GPIOs in a bank of I2C GPIO expanders.
+
+If you want to initialize a structure with an invalid GPIO number, use
+some negative number (perhaps "-EINVAL"); that will never be valid. To
+test if such number from such a structure could reference a GPIO, you
+may use this predicate:
+
+ int gpio_is_valid(int number);
+
+A number that's not valid will be rejected by calls which may request
+or free GPIOs (see below). Other numbers may also be rejected; for
+example, a number might be valid but temporarily unused on a given board.
+
+Whether a platform supports multiple GPIO controllers is a platform-specific
+implementation issue, as are whether that support can leave "holes" in the space
+of GPIO numbers, and whether new controllers can be added at runtime. Such issues
+can affect things including whether adjacent GPIO numbers are both valid.
+
+Using GPIOs
+-----------
+The first thing a system should do with a GPIO is allocate it, using
+the gpio_request() call; see later.
+
+One of the next things to do with a GPIO, often in board setup code when
+setting up a platform_device using the GPIO, is mark its direction::
+
+ /* set as input or output, returning 0 or negative errno */
+ int gpio_direction_input(unsigned gpio);
+ int gpio_direction_output(unsigned gpio, int value);
+
+The return value is zero for success, else a negative errno. It should
+be checked, since the get/set calls don't have error returns and since
+misconfiguration is possible. You should normally issue these calls from
+a task context. However, for spinlock-safe GPIOs it's OK to use them
+before tasking is enabled, as part of early board setup.
+
+For output GPIOs, the value provided becomes the initial output value.
+This helps avoid signal glitching during system startup.
+
+For compatibility with legacy interfaces to GPIOs, setting the direction
+of a GPIO implicitly requests that GPIO (see below) if it has not been
+requested already. That compatibility is being removed from the optional
+gpiolib framework.
+
+Setting the direction can fail if the GPIO number is invalid, or when
+that particular GPIO can't be used in that mode. It's generally a bad
+idea to rely on boot firmware to have set the direction correctly, since
+it probably wasn't validated to do more than boot Linux. (Similarly,
+that board setup code probably needs to multiplex that pin as a GPIO,
+and configure pullups/pulldowns appropriately.)
+
+
+Spinlock-Safe GPIO access
+-------------------------
+Most GPIO controllers can be accessed with memory read/write instructions.
+Those don't need to sleep, and can safely be done from inside hard
+(nonthreaded) IRQ handlers and similar contexts.
+
+Use the following calls to access such GPIOs,
+for which gpio_cansleep() will always return false (see below)::
+
+ /* GPIO INPUT: return zero or nonzero */
+ int gpio_get_value(unsigned gpio);
+
+ /* GPIO OUTPUT */
+ void gpio_set_value(unsigned gpio, int value);
+
+The values are boolean, zero for low, nonzero for high. When reading the
+value of an output pin, the value returned should be what's seen on the
+pin ... that won't always match the specified output value, because of
+issues including open-drain signaling and output latencies.
+
+The get/set calls have no error returns because "invalid GPIO" should have
+been reported earlier from gpio_direction_*(). However, note that not all
+platforms can read the value of output pins; those that can't should always
+return zero. Also, using these calls for GPIOs that can't safely be accessed
+without sleeping (see below) is an error.
+
+Platform-specific implementations are encouraged to optimize the two
+calls to access the GPIO value in cases where the GPIO number (and for
+output, value) are constant. It's normal for them to need only a couple
+of instructions in such cases (reading or writing a hardware register),
+and not to need spinlocks. Such optimized calls can make bitbanging
+applications a lot more efficient (in both space and time) than spending
+dozens of instructions on subroutine calls.
+
+
+GPIO access that may sleep
+--------------------------
+Some GPIO controllers must be accessed using message based busses like I2C
+or SPI. Commands to read or write those GPIO values require waiting to
+get to the head of a queue to transmit a command and get its response.
+This requires sleeping, which can't be done from inside IRQ handlers.
+
+Platforms that support this type of GPIO distinguish them from other GPIOs
+by returning nonzero from this call (which requires a valid GPIO number,
+which should have been previously allocated with gpio_request)::
+
+ int gpio_cansleep(unsigned gpio);
+
+To access such GPIOs, a different set of accessors is defined::
+
+ /* GPIO INPUT: return zero or nonzero, might sleep */
+ int gpio_get_value_cansleep(unsigned gpio);
+
+ /* GPIO OUTPUT, might sleep */
+ void gpio_set_value_cansleep(unsigned gpio, int value);
+
+
+Accessing such GPIOs requires a context which may sleep, for example
+a threaded IRQ handler, and those accessors must be used instead of
+spinlock-safe accessors without the cansleep() name suffix.
+
+Other than the fact that these accessors might sleep, and will work
+on GPIOs that can't be accessed from hardIRQ handlers, these calls act
+the same as the spinlock-safe calls.
+
+**IN ADDITION** calls to setup and configure such GPIOs must be made
+from contexts which may sleep, since they may need to access the GPIO
+controller chip too (These setup calls are usually made from board
+setup or driver probe/teardown code, so this is an easy constraint.)::
+
+ gpio_direction_input()
+ gpio_direction_output()
+ gpio_request()
+
+ ## gpio_request_one()
+ ## gpio_request_array()
+ ## gpio_free_array()
+
+ gpio_free()
+ gpio_set_debounce()
+
+
+
+Claiming and Releasing GPIOs
+----------------------------
+To help catch system configuration errors, two calls are defined::
+
+ /* request GPIO, returning 0 or negative errno.
+ * non-null labels may be useful for diagnostics.
+ */
+ int gpio_request(unsigned gpio, const char *label);
+
+ /* release previously-claimed GPIO */
+ void gpio_free(unsigned gpio);
+
+Passing invalid GPIO numbers to gpio_request() will fail, as will requesting
+GPIOs that have already been claimed with that call. The return value of
+gpio_request() must be checked. You should normally issue these calls from
+a task context. However, for spinlock-safe GPIOs it's OK to request GPIOs
+before tasking is enabled, as part of early board setup.
+
+These calls serve two basic purposes. One is marking the signals which
+are actually in use as GPIOs, for better diagnostics; systems may have
+several hundred potential GPIOs, but often only a dozen are used on any
+given board. Another is to catch conflicts, identifying errors when
+(a) two or more drivers wrongly think they have exclusive use of that
+signal, or (b) something wrongly believes it's safe to remove drivers
+needed to manage a signal that's in active use. That is, requesting a
+GPIO can serve as a kind of lock.
+
+Some platforms may also use knowledge about what GPIOs are active for
+power management, such as by powering down unused chip sectors and, more
+easily, gating off unused clocks.
+
+For GPIOs that use pins known to the pinctrl subsystem, that subsystem should
+be informed of their use; a gpiolib driver's .request() operation may call
+pinctrl_gpio_request(), and a gpiolib driver's .free() operation may call
+pinctrl_gpio_free(). The pinctrl subsystem allows a pinctrl_gpio_request()
+to succeed concurrently with a pin or pingroup being "owned" by a device for
+pin multiplexing.
+
+Any programming of pin multiplexing hardware that is needed to route the
+GPIO signal to the appropriate pin should occur within a GPIO driver's
+.direction_input() or .direction_output() operations, and occur after any
+setup of an output GPIO's value. This allows a glitch-free migration from a
+pin's special function to GPIO. This is sometimes required when using a GPIO
+to implement a workaround on signals typically driven by a non-GPIO HW block.
+
+Some platforms allow some or all GPIO signals to be routed to different pins.
+Similarly, other aspects of the GPIO or pin may need to be configured, such as
+pullup/pulldown. Platform software should arrange that any such details are
+configured prior to gpio_request() being called for those GPIOs, e.g. using
+the pinctrl subsystem's mapping table, so that GPIO users need not be aware
+of these details.
+
+Also note that it's your responsibility to have stopped using a GPIO
+before you free it.
+
+Considering in most cases GPIOs are actually configured right after they
+are claimed, three additional calls are defined::
+
+ /* request a single GPIO, with initial configuration specified by
+ * 'flags', identical to gpio_request() wrt other arguments and
+ * return value
+ */
+ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label);
+
+ /* request multiple GPIOs in a single call
+ */
+ int gpio_request_array(struct gpio *array, size_t num);
+
+ /* release multiple GPIOs in a single call
+ */
+ void gpio_free_array(struct gpio *array, size_t num);
+
+where 'flags' is currently defined to specify the following properties:
+
+ * GPIOF_DIR_IN - to configure direction as input
+ * GPIOF_DIR_OUT - to configure direction as output
+
+ * GPIOF_INIT_LOW - as output, set initial level to LOW
+ * GPIOF_INIT_HIGH - as output, set initial level to HIGH
+ * GPIOF_OPEN_DRAIN - gpio pin is open drain type.
+ * GPIOF_OPEN_SOURCE - gpio pin is open source type.
+
+ * GPIOF_EXPORT_DIR_FIXED - export gpio to sysfs, keep direction
+ * GPIOF_EXPORT_DIR_CHANGEABLE - also export, allow changing direction
+
+since GPIOF_INIT_* are only valid when configured as output, so group valid
+combinations as:
+
+ * GPIOF_IN - configure as input
+ * GPIOF_OUT_INIT_LOW - configured as output, initial level LOW
+ * GPIOF_OUT_INIT_HIGH - configured as output, initial level HIGH
+
+When setting the flag as GPIOF_OPEN_DRAIN then it will assume that pins is
+open drain type. Such pins will not be driven to 1 in output mode. It is
+require to connect pull-up on such pins. By enabling this flag, gpio lib will
+make the direction to input when it is asked to set value of 1 in output mode
+to make the pin HIGH. The pin is make to LOW by driving value 0 in output mode.
+
+When setting the flag as GPIOF_OPEN_SOURCE then it will assume that pins is
+open source type. Such pins will not be driven to 0 in output mode. It is
+require to connect pull-down on such pin. By enabling this flag, gpio lib will
+make the direction to input when it is asked to set value of 0 in output mode
+to make the pin LOW. The pin is make to HIGH by driving value 1 in output mode.
+
+In the future, these flags can be extended to support more properties.
+
+Further more, to ease the claim/release of multiple GPIOs, 'struct gpio' is
+introduced to encapsulate all three fields as::
+
+ struct gpio {
+ unsigned gpio;
+ unsigned long flags;
+ const char *label;
+ };
+
+A typical example of usage::
+
+ static struct gpio leds_gpios[] = {
+ { 32, GPIOF_OUT_INIT_HIGH, "Power LED" }, /* default to ON */
+ { 33, GPIOF_OUT_INIT_LOW, "Green LED" }, /* default to OFF */
+ { 34, GPIOF_OUT_INIT_LOW, "Red LED" }, /* default to OFF */
+ { 35, GPIOF_OUT_INIT_LOW, "Blue LED" }, /* default to OFF */
+ { ... },
+ };
+
+ err = gpio_request_one(31, GPIOF_IN, "Reset Button");
+ if (err)
+ ...
+
+ err = gpio_request_array(leds_gpios, ARRAY_SIZE(leds_gpios));
+ if (err)
+ ...
+
+ gpio_free_array(leds_gpios, ARRAY_SIZE(leds_gpios));
+
+
+GPIOs mapped to IRQs
+--------------------
+GPIO numbers are unsigned integers; so are IRQ numbers. These make up
+two logically distinct namespaces (GPIO 0 need not use IRQ 0). You can
+map between them using calls like::
+
+ /* map GPIO numbers to IRQ numbers */
+ int gpio_to_irq(unsigned gpio);
+
+ /* map IRQ numbers to GPIO numbers (avoid using this) */
+ int irq_to_gpio(unsigned irq);
+
+Those return either the corresponding number in the other namespace, or
+else a negative errno code if the mapping can't be done. (For example,
+some GPIOs can't be used as IRQs.) It is an unchecked error to use a GPIO
+number that wasn't set up as an input using gpio_direction_input(), or
+to use an IRQ number that didn't originally come from gpio_to_irq().
+
+These two mapping calls are expected to cost on the order of a single
+addition or subtraction. They're not allowed to sleep.
+
+Non-error values returned from gpio_to_irq() can be passed to request_irq()
+or free_irq(). They will often be stored into IRQ resources for platform
+devices, by the board-specific initialization code. Note that IRQ trigger
+options are part of the IRQ interface, e.g. IRQF_TRIGGER_FALLING, as are
+system wakeup capabilities.
+
+Non-error values returned from irq_to_gpio() would most commonly be used
+with gpio_get_value(), for example to initialize or update driver state
+when the IRQ is edge-triggered. Note that some platforms don't support
+this reverse mapping, so you should avoid using it.
+
+
+Emulating Open Drain Signals
+----------------------------
+Sometimes shared signals need to use "open drain" signaling, where only the
+low signal level is actually driven. (That term applies to CMOS transistors;
+"open collector" is used for TTL.) A pullup resistor causes the high signal
+level. This is sometimes called a "wire-AND"; or more practically, from the
+negative logic (low=true) perspective this is a "wire-OR".
+
+One common example of an open drain signal is a shared active-low IRQ line.
+Also, bidirectional data bus signals sometimes use open drain signals.
+
+Some GPIO controllers directly support open drain outputs; many don't. When
+you need open drain signaling but your hardware doesn't directly support it,
+there's a common idiom you can use to emulate it with any GPIO pin that can
+be used as either an input or an output:
+
+ LOW: gpio_direction_output(gpio, 0) ... this drives the signal
+ and overrides the pullup.
+
+ HIGH: gpio_direction_input(gpio) ... this turns off the output,
+ so the pullup (or some other device) controls the signal.
+
+If you are "driving" the signal high but gpio_get_value(gpio) reports a low
+value (after the appropriate rise time passes), you know some other component
+is driving the shared signal low. That's not necessarily an error. As one
+common example, that's how I2C clocks are stretched: a slave that needs a
+slower clock delays the rising edge of SCK, and the I2C master adjusts its
+signaling rate accordingly.
+
+
+GPIO controllers and the pinctrl subsystem
+------------------------------------------
+
+A GPIO controller on a SOC might be tightly coupled with the pinctrl
+subsystem, in the sense that the pins can be used by other functions
+together with an optional gpio feature. We have already covered the
+case where e.g. a GPIO controller need to reserve a pin or set the
+direction of a pin by calling any of::
+
+ pinctrl_gpio_request()
+ pinctrl_gpio_free()
+ pinctrl_gpio_direction_input()
+ pinctrl_gpio_direction_output()
+
+But how does the pin control subsystem cross-correlate the GPIO
+numbers (which are a global business) to a certain pin on a certain
+pin controller?
+
+This is done by registering "ranges" of pins, which are essentially
+cross-reference tables. These are described in
+Documentation/driver-api/pinctl.rst
+
+While the pin allocation is totally managed by the pinctrl subsystem,
+gpio (under gpiolib) is still maintained by gpio drivers. It may happen
+that different pin ranges in a SoC is managed by different gpio drivers.
+
+This makes it logical to let gpio drivers announce their pin ranges to
+the pin ctrl subsystem before it will call 'pinctrl_gpio_request' in order
+to request the corresponding pin to be prepared by the pinctrl subsystem
+before any gpio usage.
+
+For this, the gpio controller can register its pin range with pinctrl
+subsystem. There are two ways of doing it currently: with or without DT.
+
+For with DT support refer to Documentation/devicetree/bindings/gpio/gpio.txt.
+
+For non-DT support, user can call gpiochip_add_pin_range() with appropriate
+parameters to register a range of gpio pins with a pinctrl driver. For this
+exact name string of pinctrl device has to be passed as one of the
+argument to this routine.
+
+
+What do these conventions omit?
+===============================
+One of the biggest things these conventions omit is pin multiplexing, since
+this is highly chip-specific and nonportable. One platform might not need
+explicit multiplexing; another might have just two options for use of any
+given pin; another might have eight options per pin; another might be able
+to route a given GPIO to any one of several pins. (Yes, those examples all
+come from systems that run Linux today.)
+
+Related to multiplexing is configuration and enabling of the pullups or
+pulldowns integrated on some platforms. Not all platforms support them,
+or support them in the same way; and any given board might use external
+pullups (or pulldowns) so that the on-chip ones should not be used.
+(When a circuit needs 5 kOhm, on-chip 100 kOhm resistors won't do.)
+Likewise drive strength (2 mA vs 20 mA) and voltage (1.8V vs 3.3V) is a
+platform-specific issue, as are models like (not) having a one-to-one
+correspondence between configurable pins and GPIOs.
+
+There are other system-specific mechanisms that are not specified here,
+like the aforementioned options for input de-glitching and wire-OR output.
+Hardware may support reading or writing GPIOs in gangs, but that's usually
+configuration dependent: for GPIOs sharing the same bank. (GPIOs are
+commonly grouped in banks of 16 or 32, with a given SOC having several such
+banks.) Some systems can trigger IRQs from output GPIOs, or read values
+from pins not managed as GPIOs. Code relying on such mechanisms will
+necessarily be nonportable.
+
+Dynamic definition of GPIOs is not currently standard; for example, as
+a side effect of configuring an add-on board with some GPIO expanders.
+
+
+GPIO implementor's framework (OPTIONAL)
+=======================================
+As noted earlier, there is an optional implementation framework making it
+easier for platforms to support different kinds of GPIO controller using
+the same programming interface. This framework is called "gpiolib".
+
+As a debugging aid, if debugfs is available a /sys/kernel/debug/gpio file
+will be found there. That will list all the controllers registered through
+this framework, and the state of the GPIOs currently in use.
+
+
+Controller Drivers: gpio_chip
+-----------------------------
+In this framework each GPIO controller is packaged as a "struct gpio_chip"
+with information common to each controller of that type:
+
+ - methods to establish GPIO direction
+ - methods used to access GPIO values
+ - flag saying whether calls to its methods may sleep
+ - optional debugfs dump method (showing extra state like pullup config)
+ - label for diagnostics
+
+There is also per-instance data, which may come from device.platform_data:
+the number of its first GPIO, and how many GPIOs it exposes.
+
+The code implementing a gpio_chip should support multiple instances of the
+controller, possibly using the driver model. That code will configure each
+gpio_chip and issue gpiochip_add(). Removing a GPIO controller should be
+rare; use gpiochip_remove() when it is unavoidable.
+
+Most often a gpio_chip is part of an instance-specific structure with state
+not exposed by the GPIO interfaces, such as addressing, power management,
+and more. Chips such as codecs will have complex non-GPIO state.
+
+Any debugfs dump method should normally ignore signals which haven't been
+requested as GPIOs. They can use gpiochip_is_requested(), which returns
+either NULL or the label associated with that GPIO when it was requested.
+
+
+Platform Support
+----------------
+To force-enable this framework, a platform's Kconfig will "select" GPIOLIB,
+else it is up to the user to configure support for GPIO.
+
+It may also provide a custom value for ARCH_NR_GPIOS, so that it better
+reflects the number of GPIOs in actual use on that platform, without
+wasting static table space. (It should count both built-in/SoC GPIOs and
+also ones on GPIO expanders.
+
+If neither of these options are selected, the platform does not support
+GPIOs through GPIO-lib and the code cannot be enabled by the user.
+
+Trivial implementations of those functions can directly use framework
+code, which always dispatches through the gpio_chip::
+
+ #define gpio_get_value __gpio_get_value
+ #define gpio_set_value __gpio_set_value
+ #define gpio_cansleep __gpio_cansleep
+
+Fancier implementations could instead define those as inline functions with
+logic optimizing access to specific SOC-based GPIOs. For example, if the
+referenced GPIO is the constant "12", getting or setting its value could
+cost as little as two or three instructions, never sleeping. When such an
+optimization is not possible those calls must delegate to the framework
+code, costing at least a few dozen instructions. For bitbanged I/O, such
+instruction savings can be significant.
+
+For SOCs, platform-specific code defines and registers gpio_chip instances
+for each bank of on-chip GPIOs. Those GPIOs should be numbered/labeled to
+match chip vendor documentation, and directly match board schematics. They
+may well start at zero and go up to a platform-specific limit. Such GPIOs
+are normally integrated into platform initialization to make them always be
+available, from arch_initcall() or earlier; they can often serve as IRQs.
+
+
+Board Support
+-------------
+For external GPIO controllers -- such as I2C or SPI expanders, ASICs, multi
+function devices, FPGAs or CPLDs -- most often board-specific code handles
+registering controller devices and ensures that their drivers know what GPIO
+numbers to use with gpiochip_add(). Their numbers often start right after
+platform-specific GPIOs.
+
+For example, board setup code could create structures identifying the range
+of GPIOs that chip will expose, and passes them to each GPIO expander chip
+using platform_data. Then the chip driver's probe() routine could pass that
+data to gpiochip_add().
+
+Initialization order can be important. For example, when a device relies on
+an I2C-based GPIO, its probe() routine should only be called after that GPIO
+becomes available. That may mean the device should not be registered until
+calls for that GPIO can work. One way to address such dependencies is for
+such gpio_chip controllers to provide setup() and teardown() callbacks to
+board specific code; those board specific callbacks would register devices
+once all the necessary resources are available, and remove them later when
+the GPIO controller device becomes unavailable.
+
+
+Sysfs Interface for Userspace (OPTIONAL)
+========================================
+Platforms which use the "gpiolib" implementors framework may choose to
+configure a sysfs user interface to GPIOs. This is different from the
+debugfs interface, since it provides control over GPIO direction and
+value instead of just showing a gpio state summary. Plus, it could be
+present on production systems without debugging support.
+
+Given appropriate hardware documentation for the system, userspace could
+know for example that GPIO #23 controls the write protect line used to
+protect boot loader segments in flash memory. System upgrade procedures
+may need to temporarily remove that protection, first importing a GPIO,
+then changing its output state, then updating the code before re-enabling
+the write protection. In normal use, GPIO #23 would never be touched,
+and the kernel would have no need to know about it.
+
+Again depending on appropriate hardware documentation, on some systems
+userspace GPIO can be used to determine system configuration data that
+standard kernels won't know about. And for some tasks, simple userspace
+GPIO drivers could be all that the system really needs.
+
+Note that standard kernel drivers exist for common "LEDs and Buttons"
+GPIO tasks: "leds-gpio" and "gpio_keys", respectively. Use those
+instead of talking directly to the GPIOs; they integrate with kernel
+frameworks better than your userspace code could.
+
+
+Paths in Sysfs
+--------------
+There are three kinds of entry in /sys/class/gpio:
+
+ - Control interfaces used to get userspace control over GPIOs;
+
+ - GPIOs themselves; and
+
+ - GPIO controllers ("gpio_chip" instances).
+
+That's in addition to standard files including the "device" symlink.
+
+The control interfaces are write-only:
+
+ /sys/class/gpio/
+
+ "export" ... Userspace may ask the kernel to export control of
+ a GPIO to userspace by writing its number to this file.
+
+ Example: "echo 19 > export" will create a "gpio19" node
+ for GPIO #19, if that's not requested by kernel code.
+
+ "unexport" ... Reverses the effect of exporting to userspace.
+
+ Example: "echo 19 > unexport" will remove a "gpio19"
+ node exported using the "export" file.
+
+GPIO signals have paths like /sys/class/gpio/gpio42/ (for GPIO #42)
+and have the following read/write attributes:
+
+ /sys/class/gpio/gpioN/
+
+ "direction" ... reads as either "in" or "out". This value may
+ normally be written. Writing as "out" defaults to
+ initializing the value as low. To ensure glitch free
+ operation, values "low" and "high" may be written to
+ configure the GPIO as an output with that initial value.
+
+ Note that this attribute *will not exist* if the kernel
+ doesn't support changing the direction of a GPIO, or
+ it was exported by kernel code that didn't explicitly
+ allow userspace to reconfigure this GPIO's direction.
+
+ "value" ... reads as either 0 (low) or 1 (high). If the GPIO
+ is configured as an output, this value may be written;
+ any nonzero value is treated as high.
+
+ If the pin can be configured as interrupt-generating interrupt
+ and if it has been configured to generate interrupts (see the
+ description of "edge"), you can poll(2) on that file and
+ poll(2) will return whenever the interrupt was triggered. If
+ you use poll(2), set the events POLLPRI and POLLERR. If you
+ use select(2), set the file descriptor in exceptfds. After
+ poll(2) returns, either lseek(2) to the beginning of the sysfs
+ file and read the new value or close the file and re-open it
+ to read the value.
+
+ "edge" ... reads as either "none", "rising", "falling", or
+ "both". Write these strings to select the signal edge(s)
+ that will make poll(2) on the "value" file return.
+
+ This file exists only if the pin can be configured as an
+ interrupt generating input pin.
+
+ "active_low" ... reads as either 0 (false) or 1 (true). Write
+ any nonzero value to invert the value attribute both
+ for reading and writing. Existing and subsequent
+ poll(2) support configuration via the edge attribute
+ for "rising" and "falling" edges will follow this
+ setting.
+
+GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the
+controller implementing GPIOs starting at #42) and have the following
+read-only attributes:
+
+ /sys/class/gpio/gpiochipN/
+
+ "base" ... same as N, the first GPIO managed by this chip
+
+ "label" ... provided for diagnostics (not always unique)
+
+ "ngpio" ... how many GPIOs this manges (N to N + ngpio - 1)
+
+Board documentation should in most cases cover what GPIOs are used for
+what purposes. However, those numbers are not always stable; GPIOs on
+a daughtercard might be different depending on the base board being used,
+or other cards in the stack. In such cases, you may need to use the
+gpiochip nodes (possibly in conjunction with schematics) to determine
+the correct GPIO number to use for a given signal.
+
+
+Exporting from Kernel code
+--------------------------
+Kernel code can explicitly manage exports of GPIOs which have already been
+requested using gpio_request()::
+
+ /* export the GPIO to userspace */
+ int gpio_export(unsigned gpio, bool direction_may_change);
+
+ /* reverse gpio_export() */
+ void gpio_unexport();
+
+ /* create a sysfs link to an exported GPIO node */
+ int gpio_export_link(struct device *dev, const char *name,
+ unsigned gpio)
+
+After a kernel driver requests a GPIO, it may only be made available in
+the sysfs interface by gpio_export(). The driver can control whether the
+signal direction may change. This helps drivers prevent userspace code
+from accidentally clobbering important system state.
+
+This explicit exporting can help with debugging (by making some kinds
+of experiments easier), or can provide an always-there interface that's
+suitable for documenting as part of a board support package.
+
+After the GPIO has been exported, gpio_export_link() allows creating
+symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can
+use this to provide the interface under their own device in sysfs with
+a descriptive name.
+
+
+API Reference
+=============
+
+The functions listed in this section are deprecated. The GPIO descriptor based
+API should be used in new code.
+
+.. kernel-doc:: drivers/gpio/gpiolib-legacy.c
+ :export:
diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
index e9b41b1634f3..6d8352c0f354 100644
--- a/Documentation/driver-api/index.rst
+++ b/Documentation/driver-api/index.rst
@@ -44,7 +44,7 @@ available subsections can be seen below.
uio-howto
firmware/index
pinctl
- gpio
+ gpio/index
misc_devices
dmaengine/index
slimbus
diff --git a/Documentation/driver-api/mtdnand.rst b/Documentation/driver-api/mtdnand.rst
index 2a5191b6d445..dcd63599f700 100644
--- a/Documentation/driver-api/mtdnand.rst
+++ b/Documentation/driver-api/mtdnand.rst
@@ -967,10 +967,10 @@ API functions which are exported. Each function has a short description
which is marked with an [XXX] identifier. See the chapter "Documentation
hints" for an explanation.
-.. kernel-doc:: drivers/mtd/nand/nand_base.c
+.. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
:export:
-.. kernel-doc:: drivers/mtd/nand/nand_ecc.c
+.. kernel-doc:: drivers/mtd/nand/raw/nand_ecc.c
:export:
Internal Functions Provided
@@ -982,10 +982,10 @@ marked with an [XXX] identifier. See the chapter "Documentation hints"
for an explanation. The functions marked with [DEFAULT] might be
relevant for a board driver developer.
-.. kernel-doc:: drivers/mtd/nand/nand_base.c
+.. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
:internal:
-.. kernel-doc:: drivers/mtd/nand/nand_bbt.c
+.. kernel-doc:: drivers/mtd/nand/raw/nand_bbt.c
:internal:
Credits
diff --git a/Documentation/driver-api/scsi.rst b/Documentation/driver-api/scsi.rst
index 3ae337929721..31ad0fed6763 100644
--- a/Documentation/driver-api/scsi.rst
+++ b/Documentation/driver-api/scsi.rst
@@ -154,12 +154,6 @@ lists).
.. kernel-doc:: drivers/scsi/scsi_lib_dma.c
:export:
-drivers/scsi/scsi_module.c
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The file drivers/scsi/scsi_module.c contains legacy support for
-old-style host templates. It should never be used by any new driver.
-
drivers/scsi/scsi_proc.c
~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/Documentation/driver-api/slimbus.rst b/Documentation/driver-api/slimbus.rst
index 7555ecd538de..a97449cf603a 100644
--- a/Documentation/driver-api/slimbus.rst
+++ b/Documentation/driver-api/slimbus.rst
@@ -90,7 +90,7 @@ controller resets the bus. This notification allows the driver to take necessary
steps to boot the device so that it's functional after the bus has been reset.
Driver and Controller APIs:
---------------------------
+---------------------------
.. kernel-doc:: include/linux/slimbus.h
:internal:
diff --git a/Documentation/driver-api/uio-howto.rst b/Documentation/driver-api/uio-howto.rst
index 693e3bd84e79..92056c20e070 100644
--- a/Documentation/driver-api/uio-howto.rst
+++ b/Documentation/driver-api/uio-howto.rst
@@ -709,6 +709,11 @@ The vmbus device regions are mapped into uio device resources:
3) Network receive buffer region
4) Network send buffer region
+If a subchannel is created by a request to host, then the uio_hv_generic
+device driver will create a sysfs binary file for the per-channel ring buffer.
+For example:
+ /sys/bus/vmbus/devices/3811fe4d-0fa0-4b62-981a-74fc1084c757/channels/21/ring
+
Further information
===================
diff --git a/Documentation/driver-api/usb/typec.rst b/Documentation/driver-api/usb/typec.rst
index 8a7249f2ff04..feb31946490b 100644
--- a/Documentation/driver-api/usb/typec.rst
+++ b/Documentation/driver-api/usb/typec.rst
@@ -61,7 +61,7 @@ Registering the ports
The port drivers will describe every Type-C port they control with struct
typec_capability data structure, and register them with the following API:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_register_port typec_unregister_port
When registering the ports, the prefer_role member in struct typec_capability
@@ -80,7 +80,7 @@ typec_partner_desc. The class copies the details of the partner during
registration. The class offers the following API for registering/unregistering
partners.
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_register_partner typec_unregister_partner
The class will provide a handle to struct typec_partner if the registration was
@@ -92,7 +92,7 @@ should include handle to struct usb_pd_identity instance. The class will then
create a sysfs directory for the identity under the partner device. The result
of Discover Identity command can then be reported with the following API:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_partner_set_identity
Registering Cables
@@ -113,7 +113,7 @@ typec_cable_desc and about a plug in struct typec_plug_desc. The class copies
the details during registration. The class offers the following API for
registering/unregistering cables and their plugs:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_register_cable typec_unregister_cable typec_register_plug typec_unregister_plug
The class will provide a handle to struct typec_cable and struct typec_plug if
@@ -125,7 +125,7 @@ include handle to struct usb_pd_identity instance. The class will then create a
sysfs directory for the identity under the cable device. The result of Discover
Identity command can then be reported with the following API:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_cable_set_identity
Notifications
@@ -135,7 +135,7 @@ When the partner has executed a role change, or when the default roles change
during connection of a partner or cable, the port driver must use the following
APIs to report it to the class:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_set_data_role typec_set_pwr_role typec_set_vconn_role typec_set_pwr_opmode
Alternate Modes
@@ -150,7 +150,7 @@ and struct typec_altmode_desc which is a container for all the supported modes.
Ports that support Alternate Modes need to register each SVID they support with
the following API:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_port_register_altmode
If a partner or cable plug provides a list of SVIDs as response to USB Power
@@ -159,12 +159,12 @@ registered.
API for the partners:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_partner_register_altmode
API for the Cable Plugs:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_plug_register_altmode
So ports, partners and cable plugs will register the alternate modes with their
@@ -172,11 +172,62 @@ own functions, but the registration will always return a handle to struct
typec_altmode on success, or NULL. The unregistration will happen with the same
function:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_unregister_altmode
If a partner or cable plug enters or exits a mode, the port driver needs to
notify the class with the following API:
-.. kernel-doc:: drivers/usb/typec/typec.c
+.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_altmode_update_active
+
+Multiplexer/DeMultiplexer Switches
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+USB Type-C connectors may have one or more mux/demux switches behind them. Since
+the plugs can be inserted right-side-up or upside-down, a switch is needed to
+route the correct data pairs from the connector to the USB controllers. If
+Alternate or Accessory Modes are supported, another switch is needed that can
+route the pins on the connector to some other component besides USB. USB Type-C
+Connector Class supplies an API for registering those switches.
+
+.. kernel-doc:: drivers/usb/typec/mux.c
+ :functions: typec_switch_register typec_switch_unregister typec_mux_register typec_mux_unregister
+
+In most cases the same physical mux will handle both the orientation and mode.
+However, as the port drivers will be responsible for the orientation, and the
+alternate mode drivers for the mode, the two are always separated into their
+own logical components: "mux" for the mode and "switch" for the orientation.
+
+When a port is registered, USB Type-C Connector Class requests both the mux and
+the switch for the port. The drivers can then use the following API for
+controlling them:
+
+.. kernel-doc:: drivers/usb/typec/class.c
+ :functions: typec_set_orientation typec_set_mode
+
+If the connector is dual-role capable, there may also be a switch for the data
+role. USB Type-C Connector Class does not supply separate API for them. The
+port drivers can use USB Role Class API with those.
+
+Illustration of the muxes behind a connector that supports an alternate mode:
+
+ ------------------------
+ | Connector |
+ ------------------------
+ | |
+ ------------------------
+ \ Orientation /
+ --------------------
+ |
+ --------------------
+ / Mode \
+ ------------------------
+ / \
+ ------------------------ --------------------
+ | Alt Mode | / USB Role \
+ ------------------------ ------------------------
+ / \
+ ------------------------ ------------------------
+ | USB Host | | USB Device |
+ ------------------------ ------------------------
diff --git a/Documentation/driver-api/usb/writing_musb_glue_layer.rst b/Documentation/driver-api/usb/writing_musb_glue_layer.rst
index e90e8fa95600..5bf7152fd76f 100644
--- a/Documentation/driver-api/usb/writing_musb_glue_layer.rst
+++ b/Documentation/driver-api/usb/writing_musb_glue_layer.rst
@@ -718,6 +718,3 @@ http://www.maximintegrated.com/app-notes/index.mvp/id/1822
Texas Instruments USB Configuration Wiki Page:
http://processors.wiki.ti.com/index.php/Usbgeneralpage
-
-Analog Devices Blackfin MUSB Configuration:
-http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:musb
diff --git a/Documentation/fault-injection/fault-injection.txt b/Documentation/fault-injection/fault-injection.txt
index de1dc35fe500..4d1b7b4ccfaf 100644
--- a/Documentation/fault-injection/fault-injection.txt
+++ b/Documentation/fault-injection/fault-injection.txt
@@ -36,6 +36,14 @@ o fail_function
ALLOW_ERROR_INJECTION() macro, by setting debugfs entries
under /sys/kernel/debug/fail_function. No boot option supported.
+o NVMe fault injection
+
+ inject NVMe status code and retry flag on devices permitted by setting
+ debugfs entries under /sys/kernel/debug/nvme*/fault_inject. The default
+ status code is NVME_SC_INVALID_OPCODE with no retry. The status code and
+ retry flag can be set via the debugfs.
+
+
Configure fault-injection capabilities behavior
-----------------------------------------------
diff --git a/Documentation/fault-injection/nvme-fault-injection.txt b/Documentation/fault-injection/nvme-fault-injection.txt
new file mode 100644
index 000000000000..8fbf3bf60b62
--- /dev/null
+++ b/Documentation/fault-injection/nvme-fault-injection.txt
@@ -0,0 +1,116 @@
+NVMe Fault Injection
+====================
+Linux's fault injection framework provides a systematic way to support
+error injection via debugfs in the /sys/kernel/debug directory. When
+enabled, the default NVME_SC_INVALID_OPCODE with no retry will be
+injected into the nvme_end_request. Users can change the default status
+code and no retry flag via the debugfs. The list of Generic Command
+Status can be found in include/linux/nvme.h
+
+Following examples show how to inject an error into the nvme.
+
+First, enable CONFIG_FAULT_INJECTION_DEBUG_FS kernel config,
+recompile the kernel. After booting up the kernel, do the
+following.
+
+Example 1: Inject default status code with no retry
+---------------------------------------------------
+
+mount /dev/nvme0n1 /mnt
+echo 1 > /sys/kernel/debug/nvme0n1/fault_inject/times
+echo 100 > /sys/kernel/debug/nvme0n1/fault_inject/probability
+cp a.file /mnt
+
+Expected Result:
+
+cp: cannot stat ‘/mnt/a.file’: Input/output error
+
+Message from dmesg:
+
+FAULT_INJECTION: forcing a failure.
+name fault_inject, interval 1, probability 100, space 0, times 1
+CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
+Hardware name: innotek GmbH VirtualBox/VirtualBox,
+BIOS VirtualBox 12/01/2006
+Call Trace:
+ <IRQ>
+ dump_stack+0x5c/0x7d
+ should_fail+0x148/0x170
+ nvme_should_fail+0x2f/0x50 [nvme_core]
+ nvme_process_cq+0xe7/0x1d0 [nvme]
+ nvme_irq+0x1e/0x40 [nvme]
+ __handle_irq_event_percpu+0x3a/0x190
+ handle_irq_event_percpu+0x30/0x70
+ handle_irq_event+0x36/0x60
+ handle_fasteoi_irq+0x78/0x120
+ handle_irq+0xa7/0x130
+ ? tick_irq_enter+0xa8/0xc0
+ do_IRQ+0x43/0xc0
+ common_interrupt+0xa2/0xa2
+ </IRQ>
+RIP: 0010:native_safe_halt+0x2/0x10
+RSP: 0018:ffffffff82003e90 EFLAGS: 00000246 ORIG_RAX: ffffffffffffffdd
+RAX: ffffffff817a10c0 RBX: ffffffff82012480 RCX: 0000000000000000
+RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
+RBP: 0000000000000000 R08: 000000008e38ce64 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000000 R12: ffffffff82012480
+R13: ffffffff82012480 R14: 0000000000000000 R15: 0000000000000000
+ ? __sched_text_end+0x4/0x4
+ default_idle+0x18/0xf0
+ do_idle+0x150/0x1d0
+ cpu_startup_entry+0x6f/0x80
+ start_kernel+0x4c4/0x4e4
+ ? set_init_arg+0x55/0x55
+ secondary_startup_64+0xa5/0xb0
+ print_req_error: I/O error, dev nvme0n1, sector 9240
+EXT4-fs error (device nvme0n1): ext4_find_entry:1436:
+inode #2: comm cp: reading directory lblock 0
+
+Example 2: Inject default status code with retry
+------------------------------------------------
+
+mount /dev/nvme0n1 /mnt
+echo 1 > /sys/kernel/debug/nvme0n1/fault_inject/times
+echo 100 > /sys/kernel/debug/nvme0n1/fault_inject/probability
+echo 1 > /sys/kernel/debug/nvme0n1/fault_inject/status
+echo 0 > /sys/kernel/debug/nvme0n1/fault_inject/dont_retry
+
+cp a.file /mnt
+
+Expected Result:
+
+command success without error
+
+Message from dmesg:
+
+FAULT_INJECTION: forcing a failure.
+name fault_inject, interval 1, probability 100, space 0, times 1
+CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.15.0-rc8+ #4
+Hardware name: innotek GmbH VirtualBox/VirtualBox, BIOS VirtualBox 12/01/2006
+Call Trace:
+ <IRQ>
+ dump_stack+0x5c/0x7d
+ should_fail+0x148/0x170
+ nvme_should_fail+0x30/0x60 [nvme_core]
+ nvme_loop_queue_response+0x84/0x110 [nvme_loop]
+ nvmet_req_complete+0x11/0x40 [nvmet]
+ nvmet_bio_done+0x28/0x40 [nvmet]
+ blk_update_request+0xb0/0x310
+ blk_mq_end_request+0x18/0x60
+ flush_smp_call_function_queue+0x3d/0xf0
+ smp_call_function_single_interrupt+0x2c/0xc0
+ call_function_single_interrupt+0xa2/0xb0
+ </IRQ>
+RIP: 0010:native_safe_halt+0x2/0x10
+RSP: 0018:ffffc9000068bec0 EFLAGS: 00000246 ORIG_RAX: ffffffffffffff04
+RAX: ffffffff817a10c0 RBX: ffff88011a3c9680 RCX: 0000000000000000
+RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
+RBP: 0000000000000001 R08: 000000008e38c131 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000000 R12: ffff88011a3c9680
+R13: ffff88011a3c9680 R14: 0000000000000000 R15: 0000000000000000
+ ? __sched_text_end+0x4/0x4
+ default_idle+0x18/0xf0
+ do_idle+0x150/0x1d0
+ cpu_startup_entry+0x6f/0x80
+ start_secondary+0x187/0x1e0
+ secondary_startup_64+0xa5/0xb0
diff --git a/Documentation/features/core/BPF-JIT/arch-support.txt b/Documentation/features/core/BPF-JIT/arch-support.txt
index 5575d2d09625..0b96b4e1e7d4 100644
--- a/Documentation/features/core/BPF-JIT/arch-support.txt
+++ b/Documentation/features/core/BPF-JIT/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | ok |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt
index abb5f271a792..372a2b18a617 100644
--- a/Documentation/features/core/generic-idle-thread/arch-support.txt
+++ b/Documentation/features/core/generic-idle-thread/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | ok |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | ok |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Documentation/features/core/jump-labels/arch-support.txt
index dbdaffcc5110..ad97217b003b 100644
--- a/Documentation/features/core/jump-labels/arch-support.txt
+++ b/Documentation/features/core/jump-labels/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | ok |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/core/tracehook/arch-support.txt b/Documentation/features/core/tracehook/arch-support.txt
index dfb638c2f842..36ee7bef5d18 100644
--- a/Documentation/features/core/tracehook/arch-support.txt
+++ b/Documentation/features/core/tracehook/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | ok |
- | cris: | TODO |
- | frv: | ok |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | ok |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | ok |
| nios2: | ok |
| openrisc: | ok |
| parisc: | ok |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt
index 3406fae833c3..f5c99fa576d3 100644
--- a/Documentation/features/debug/KASAN/arch-support.txt
+++ b/Documentation/features/debug/KASAN/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok | 64-bit only
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
index 830dbe801aaf..5170a9934843 100644
--- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
+++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | ok |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/kgdb/arch-support.txt b/Documentation/features/debug/kgdb/arch-support.txt
index 0217bf6e942d..13b6e994ae1f 100644
--- a/Documentation/features/debug/kgdb/arch-support.txt
+++ b/Documentation/features/debug/kgdb/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | ok |
| mips: | ok |
- | mn10300: | ok |
| nios2: | ok |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
index 1e84be3c142e..419bb38820e7 100644
--- a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
+++ b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/kprobes/arch-support.txt b/Documentation/features/debug/kprobes/arch-support.txt
index 529f66eda679..52b3ace0a030 100644
--- a/Documentation/features/debug/kprobes/arch-support.txt
+++ b/Documentation/features/debug/kprobes/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/kretprobes/arch-support.txt b/Documentation/features/debug/kretprobes/arch-support.txt
index 43353242e439..180d24419518 100644
--- a/Documentation/features/debug/kretprobes/arch-support.txt
+++ b/Documentation/features/debug/kretprobes/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/optprobes/arch-support.txt b/Documentation/features/debug/optprobes/arch-support.txt
index f559f1ba5416..0a1241f45e41 100644
--- a/Documentation/features/debug/optprobes/arch-support.txt
+++ b/Documentation/features/debug/optprobes/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/stackprotector/arch-support.txt b/Documentation/features/debug/stackprotector/arch-support.txt
index 59a4c9ffb7f3..570019572383 100644
--- a/Documentation/features/debug/stackprotector/arch-support.txt
+++ b/Documentation/features/debug/stackprotector/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | ok |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/uprobes/arch-support.txt b/Documentation/features/debug/uprobes/arch-support.txt
index 53ed42b0e7e5..0b8d922eb799 100644
--- a/Documentation/features/debug/uprobes/arch-support.txt
+++ b/Documentation/features/debug/uprobes/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/debug/user-ret-profiler/arch-support.txt b/Documentation/features/debug/user-ret-profiler/arch-support.txt
index 149443936de9..13852ae62e9e 100644
--- a/Documentation/features/debug/user-ret-profiler/arch-support.txt
+++ b/Documentation/features/debug/user-ret-profiler/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/io/dma-api-debug/arch-support.txt b/Documentation/features/io/dma-api-debug/arch-support.txt
index 6be920643be6..e438ed675623 100644
--- a/Documentation/features/io/dma-api-debug/arch-support.txt
+++ b/Documentation/features/io/dma-api-debug/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | ok |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | ok |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt
index 0eb08e1e32b8..47f64a433df0 100644
--- a/Documentation/features/io/dma-contiguous/arch-support.txt
+++ b/Documentation/features/io/dma-contiguous/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/io/sg-chain/arch-support.txt b/Documentation/features/io/sg-chain/arch-support.txt
index 514ad3468aa5..07f357fadbff 100644
--- a/Documentation/features/io/sg-chain/arch-support.txt
+++ b/Documentation/features/io/sg-chain/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | ok |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/lib/strncasecmp/arch-support.txt b/Documentation/features/lib/strncasecmp/arch-support.txt
index 532c6f0fc15c..4f3a6a0e4e68 100644
--- a/Documentation/features/lib/strncasecmp/arch-support.txt
+++ b/Documentation/features/lib/strncasecmp/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | TODO |
diff --git a/Documentation/features/list-arch.sh b/Documentation/features/list-arch.sh
index c16b5b595688..1ec47c3bb5fa 100755
--- a/Documentation/features/list-arch.sh
+++ b/Documentation/features/list-arch.sh
@@ -17,7 +17,7 @@ for F in */*/arch-support.txt; do
N=$(grep -h "^# Feature name:" $F | cut -c25-)
C=$(grep -h "^# Kconfig:" $F | cut -c25-)
D=$(grep -h "^# description:" $F | cut -c25-)
- S=$(grep -hw $ARCH $F | cut -d\| -f3)
+ S=$(grep -hv "^#" $F | grep -w $ARCH | cut -d\| -f3)
printf "%10s/%-22s:%s| %35s # %s\n" "$SUBSYS" "$N" "$S" "$C" "$D"
done
diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt
index f3eec26c8cf8..482a0b09d1f8 100644
--- a/Documentation/features/locking/cmpxchg-local/arch-support.txt
+++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/locking/lockdep/arch-support.txt b/Documentation/features/locking/lockdep/arch-support.txt
index 9756abc680a7..bb35c5ba6286 100644
--- a/Documentation/features/locking/lockdep/arch-support.txt
+++ b/Documentation/features/locking/lockdep/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | ok |
| microblaze: | ok |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | ok |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | ok |
| unicore32: | ok |
| x86: | ok |
diff --git a/Documentation/features/locking/queued-rwlocks/arch-support.txt b/Documentation/features/locking/queued-rwlocks/arch-support.txt
index 62f4ee5c156c..627e9a6b2db9 100644
--- a/Documentation/features/locking/queued-rwlocks/arch-support.txt
+++ b/Documentation/features/locking/queued-rwlocks/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt b/Documentation/features/locking/queued-spinlocks/arch-support.txt
index 321b32f6e63c..9edda216cdfb 100644
--- a/Documentation/features/locking/queued-spinlocks/arch-support.txt
+++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/locking/rwsem-optimized/arch-support.txt b/Documentation/features/locking/rwsem-optimized/arch-support.txt
index 79bfa4d6e41f..8d9afb10b16e 100644
--- a/Documentation/features/locking/rwsem-optimized/arch-support.txt
+++ b/Documentation/features/locking/rwsem-optimized/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt b/Documentation/features/perf/kprobes-event/arch-support.txt
index 00f1606bbf45..d01239ee34b3 100644
--- a/Documentation/features/perf/kprobes-event/arch-support.txt
+++ b/Documentation/features/perf/kprobes-event/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | TODO |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/perf/perf-regs/arch-support.txt b/Documentation/features/perf/perf-regs/arch-support.txt
index 7d516eacf7b9..458faba5311a 100644
--- a/Documentation/features/perf/perf-regs/arch-support.txt
+++ b/Documentation/features/perf/perf-regs/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/perf/perf-stackdump/arch-support.txt b/Documentation/features/perf/perf-stackdump/arch-support.txt
index f974b8df5d82..545d01c69c88 100644
--- a/Documentation/features/perf/perf-stackdump/arch-support.txt
+++ b/Documentation/features/perf/perf-stackdump/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
index 2c815a7f1ba7..85a6c9d4571c 100644
--- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt
+++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
@@ -33,28 +33,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/sched/numa-balancing/arch-support.txt b/Documentation/features/sched/numa-balancing/arch-support.txt
index 1d3c0f669152..347508863872 100644
--- a/Documentation/features/sched/numa-balancing/arch-support.txt
+++ b/Documentation/features/sched/numa-balancing/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | .. |
| arm: | .. |
| arm64: | .. |
- | blackfin: | .. |
| c6x: | .. |
- | cris: | .. |
- | frv: | .. |
| h8300: | .. |
| hexagon: | .. |
| ia64: | TODO |
- | m32r: | .. |
| m68k: | .. |
- | metag: | .. |
| microblaze: | .. |
| mips: | TODO |
- | mn10300: | .. |
| nios2: | .. |
| openrisc: | .. |
| parisc: | .. |
| powerpc: | ok |
| s390: | .. |
- | score: | .. |
| sh: | .. |
| sparc: | TODO |
- | tile: | TODO |
| um: | .. |
| unicore32: | .. |
| x86: | ok |
diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt
index a32d5b207679..e4fad58a05e5 100644
--- a/Documentation/features/seccomp/seccomp-filter/arch-support.txt
+++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | ok |
| um: | ok |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/time/arch-tick-broadcast/arch-support.txt b/Documentation/features/time/arch-tick-broadcast/arch-support.txt
index caee8f64d1bc..8052904b25fc 100644
--- a/Documentation/features/time/arch-tick-broadcast/arch-support.txt
+++ b/Documentation/features/time/arch-tick-broadcast/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | TODO |
diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt
index 1cd87f6cd07d..7c76b946297e 100644
--- a/Documentation/features/time/clockevents/arch-support.txt
+++ b/Documentation/features/time/clockevents/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | ok |
- | cris: | ok |
- | frv: | TODO |
| h8300: | ok |
| hexagon: | ok |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | ok |
- | metag: | ok |
| microblaze: | ok |
| mips: | ok |
- | mn10300: | ok |
| nios2: | ok |
| openrisc: | ok |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | ok |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | ok |
| unicore32: | ok |
| x86: | ok |
diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt
index e6d7c7b2253c..9433b3e523b3 100644
--- a/Documentation/features/time/context-tracking/arch-support.txt
+++ b/Documentation/features/time/context-tracking/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/time/irq-time-acct/arch-support.txt b/Documentation/features/time/irq-time-acct/arch-support.txt
index 15c6071788ae..212dde0b578c 100644
--- a/Documentation/features/time/irq-time-acct/arch-support.txt
+++ b/Documentation/features/time/irq-time-acct/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | .. |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | .. |
| powerpc: | .. |
| s390: | .. |
- | score: | TODO |
| sh: | TODO |
| sparc: | .. |
- | tile: | .. |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/time/modern-timekeeping/arch-support.txt b/Documentation/features/time/modern-timekeeping/arch-support.txt
index baee7611ba3d..4074028f72f7 100644
--- a/Documentation/features/time/modern-timekeeping/arch-support.txt
+++ b/Documentation/features/time/modern-timekeeping/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | ok |
- | cris: | TODO |
- | frv: | ok |
| h8300: | ok |
| hexagon: | ok |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | ok |
| microblaze: | ok |
| mips: | ok |
- | mn10300: | ok |
| nios2: | ok |
| openrisc: | ok |
| parisc: | ok |
| powerpc: | ok |
| s390: | ok |
- | score: | ok |
| sh: | ok |
| sparc: | ok |
- | tile: | ok |
| um: | ok |
| unicore32: | ok |
| x86: | ok |
diff --git a/Documentation/features/time/virt-cpuacct/arch-support.txt b/Documentation/features/time/virt-cpuacct/arch-support.txt
index 9129530cb73c..a394d8820517 100644
--- a/Documentation/features/time/virt-cpuacct/arch-support.txt
+++ b/Documentation/features/time/virt-cpuacct/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | ok |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | ok |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/vm/ELF-ASLR/arch-support.txt b/Documentation/features/vm/ELF-ASLR/arch-support.txt
index f6829af3255f..082f93d5b40e 100644
--- a/Documentation/features/vm/ELF-ASLR/arch-support.txt
+++ b/Documentation/features/vm/ELF-ASLR/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/vm/PG_uncached/arch-support.txt b/Documentation/features/vm/PG_uncached/arch-support.txt
index 1a09ea99d486..605e0abb756d 100644
--- a/Documentation/features/vm/PG_uncached/arch-support.txt
+++ b/Documentation/features/vm/PG_uncached/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/vm/THP/arch-support.txt b/Documentation/features/vm/THP/arch-support.txt
index d170e6236503..7a8eb0bd5ca8 100644
--- a/Documentation/features/vm/THP/arch-support.txt
+++ b/Documentation/features/vm/THP/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | .. |
| c6x: | .. |
- | cris: | .. |
- | frv: | .. |
| h8300: | .. |
| hexagon: | .. |
| ia64: | TODO |
- | m32r: | .. |
| m68k: | .. |
- | metag: | TODO |
| microblaze: | .. |
| mips: | ok |
- | mn10300: | .. |
| nios2: | .. |
| openrisc: | .. |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | .. |
| sh: | .. |
| sparc: | ok |
- | tile: | TODO |
| um: | .. |
| unicore32: | .. |
| x86: | ok |
diff --git a/Documentation/features/vm/TLB/arch-support.txt b/Documentation/features/vm/TLB/arch-support.txt
index abfab4080a91..35fb99b2b3ea 100644
--- a/Documentation/features/vm/TLB/arch-support.txt
+++ b/Documentation/features/vm/TLB/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | .. |
- | cris: | .. |
- | frv: | .. |
| h8300: | .. |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | .. |
- | metag: | TODO |
| microblaze: | .. |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | .. |
| openrisc: | .. |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | .. |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | .. |
| unicore32: | .. |
| x86: | ok |
diff --git a/Documentation/features/vm/huge-vmap/arch-support.txt b/Documentation/features/vm/huge-vmap/arch-support.txt
index f81f09b22b08..ed8b943ad8fc 100644
--- a/Documentation/features/vm/huge-vmap/arch-support.txt
+++ b/Documentation/features/vm/huge-vmap/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | TODO |
| s390: | TODO |
- | score: | TODO |
| sh: | TODO |
| sparc: | TODO |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt
index 0cc3e11c42e2..589947bdf0a8 100644
--- a/Documentation/features/vm/ioremap_prot/arch-support.txt
+++ b/Documentation/features/vm/ioremap_prot/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | TODO |
- | score: | TODO |
| sh: | ok |
| sparc: | TODO |
- | tile: | ok |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/features/vm/numa-memblock/arch-support.txt b/Documentation/features/vm/numa-memblock/arch-support.txt
index 9a3fdac42ce1..8b8bea0318a0 100644
--- a/Documentation/features/vm/numa-memblock/arch-support.txt
+++ b/Documentation/features/vm/numa-memblock/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | .. |
| arm: | .. |
| arm64: | .. |
- | blackfin: | .. |
| c6x: | .. |
- | cris: | .. |
- | frv: | .. |
| h8300: | .. |
| hexagon: | .. |
| ia64: | ok |
- | m32r: | TODO |
| m68k: | .. |
- | metag: | ok |
| microblaze: | ok |
| mips: | ok |
- | mn10300: | TODO |
| nios2: | .. |
| openrisc: | .. |
| parisc: | .. |
| powerpc: | ok |
| s390: | ok |
- | score: | ok |
| sh: | ok |
| sparc: | ok |
- | tile: | TODO |
| um: | .. |
| unicore32: | .. |
| x86: | ok |
diff --git a/Documentation/features/vm/pte_special/arch-support.txt b/Documentation/features/vm/pte_special/arch-support.txt
index dfaa39e664ff..055004f467d2 100644
--- a/Documentation/features/vm/pte_special/arch-support.txt
+++ b/Documentation/features/vm/pte_special/arch-support.txt
@@ -10,28 +10,20 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
- | cris: | TODO |
- | frv: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
- | m32r: | TODO |
| m68k: | TODO |
- | metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
- | mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
| s390: | ok |
- | score: | TODO |
| sh: | ok |
| sparc: | ok |
- | tile: | TODO |
| um: | TODO |
| unicore32: | TODO |
| x86: | ok |
diff --git a/Documentation/filesystems/afs.txt b/Documentation/filesystems/afs.txt
index c5254f6d234d..8c6ea7b41048 100644
--- a/Documentation/filesystems/afs.txt
+++ b/Documentation/filesystems/afs.txt
@@ -11,7 +11,7 @@ Contents:
- Proc filesystem.
- The cell database.
- Security.
- - Examples.
+ - The @sys substitution.
========
@@ -230,3 +230,29 @@ If a file is opened with a particular key and then the file descriptor is
passed to a process that doesn't have that key (perhaps over an AF_UNIX
socket), then the operations on the file will be made with key that was used to
open the file.
+
+
+=====================
+THE @SYS SUBSTITUTION
+=====================
+
+The list of up to 16 @sys substitutions for the current network namespace can
+be configured by writing a list to /proc/fs/afs/sysname:
+
+ [root@andromeda ~]# echo foo amd64_linux_26 >/proc/fs/afs/sysname
+
+or cleared entirely by writing an empty list:
+
+ [root@andromeda ~]# echo >/proc/fs/afs/sysname
+
+The current list for current network namespace can be retrieved by:
+
+ [root@andromeda ~]# cat /proc/fs/afs/sysname
+ foo
+ amd64_linux_26
+
+When @sys is being substituted for, each element of the list is tried in the
+order given.
+
+By default, the list will contain one item that conforms to the pattern
+"<arch>_linux_26", amd64 being the name for x86_64.
diff --git a/Documentation/filesystems/caching/netfs-api.txt b/Documentation/filesystems/caching/netfs-api.txt
index 0eb31de3a2c1..2a6f7399c1f3 100644
--- a/Documentation/filesystems/caching/netfs-api.txt
+++ b/Documentation/filesystems/caching/netfs-api.txt
@@ -129,20 +129,10 @@ To define an object, a structure of the following type should be filled out:
const void *parent_netfs_data,
const void *cookie_netfs_data);
- uint16_t (*get_key)(const void *cookie_netfs_data,
- void *buffer,
- uint16_t bufmax);
-
- void (*get_attr)(const void *cookie_netfs_data,
- uint64_t *size);
-
- uint16_t (*get_aux)(const void *cookie_netfs_data,
- void *buffer,
- uint16_t bufmax);
-
enum fscache_checkaux (*check_aux)(void *cookie_netfs_data,
const void *data,
- uint16_t datalen);
+ uint16_t datalen,
+ loff_t object_size);
void (*get_context)(void *cookie_netfs_data, void *context);
@@ -187,36 +177,7 @@ This has the following fields:
cache in the parent's list will be chosen, or failing that, the first
cache in the master list.
- (4) A function to retrieve an object's key from the netfs [mandatory].
-
- This function will be called with the netfs data that was passed to the
- cookie acquisition function and the maximum length of key data that it may
- provide. It should write the required key data into the given buffer and
- return the quantity it wrote.
-
- (5) A function to retrieve attribute data from the netfs [optional].
-
- This function will be called with the netfs data that was passed to the
- cookie acquisition function. It should return the size of the file if
- this is a data file. The size may be used to govern how much cache must
- be reserved for this file in the cache.
-
- If the function is absent, a file size of 0 is assumed.
-
- (6) A function to retrieve auxiliary data from the netfs [optional].
-
- This function will be called with the netfs data that was passed to the
- cookie acquisition function and the maximum length of auxiliary data that
- it may provide. It should write the auxiliary data into the given buffer
- and return the quantity it wrote.
-
- If this function is absent, the auxiliary data length will be set to 0.
-
- The length of the auxiliary data buffer may be dependent on the key
- length. A netfs mustn't rely on being able to provide more than 400 bytes
- for both.
-
- (7) A function to check the auxiliary data [optional].
+ (4) A function to check the auxiliary data [optional].
This function will be called to check that a match found in the cache for
this object is valid. For instance with AFS it could check the auxiliary
@@ -226,6 +187,9 @@ This has the following fields:
If this function is absent, it will be assumed that matching objects in a
cache are always valid.
+ The function is also passed the cache's idea of the object size and may
+ use this to manage coherency also.
+
If present, the function should return one of the following values:
(*) FSCACHE_CHECKAUX_OKAY - the entry is okay as is
@@ -235,7 +199,7 @@ This has the following fields:
This function can also be used to extract data from the auxiliary data in
the cache and copy it into the netfs's structures.
- (8) A pair of functions to manage contexts for the completion callback
+ (5) A pair of functions to manage contexts for the completion callback
[optional].
The cache read/write functions are passed a context which is then passed
@@ -249,7 +213,7 @@ This has the following fields:
required for indices as indices may not contain data. These functions may
be called in interrupt context and so may not sleep.
- (9) A function to mark a page as retaining cache metadata [optional].
+ (6) A function to mark a page as retaining cache metadata [optional].
This is called by the cache to indicate that it is retaining in-memory
information for this page and that the netfs should uncache the page when
@@ -261,7 +225,7 @@ This has the following fields:
This function is not required for indices as they're not permitted data.
-(10) A function to unmark all the pages retaining cache metadata [mandatory].
+ (7) A function to unmark all the pages retaining cache metadata [mandatory].
This is called by FS-Cache to indicate that a backing store is being
unbound from a cookie and that all the marks on the pages should be
@@ -333,12 +297,32 @@ the path to the file:
struct fscache_cookie *
fscache_acquire_cookie(struct fscache_cookie *parent,
const struct fscache_object_def *def,
+ const void *index_key,
+ size_t index_key_len,
+ const void *aux_data,
+ size_t aux_data_len,
void *netfs_data,
+ loff_t object_size,
bool enable);
This function creates an index entry in the index represented by parent,
filling in the index entry by calling the operations pointed to by def.
+A unique key that represents the object within the parent must be pointed to by
+index_key and is of length index_key_len.
+
+An optional blob of auxiliary data that is to be stored within the cache can be
+pointed to with aux_data and should be of length aux_data_len. This would
+typically be used for storing coherency data.
+
+The netfs may pass an arbitrary value in netfs_data and this will be presented
+to it in the event of any calling back. This may also be used in tracing or
+logging of messages.
+
+The cache tracks the size of the data attached to an object and this set to be
+object_size. For indices, this should be 0. This value will be passed to the
+->check_aux() callback.
+
Note that this function never returns an error - all errors are handled
internally. It may, however, return NULL to indicate no cookie. It is quite
acceptable to pass this token back to this function as the parent to another
@@ -355,30 +339,24 @@ must be enabled to do anything with it. A disabled cookie can be enabled by
calling fscache_enable_cookie() (see below).
For example, with AFS, a cell would be added to the primary index. This index
-entry would have a dependent inode containing a volume location index for the
-volume mappings within this cell:
+entry would have a dependent inode containing volume mappings within this cell:
cell->cache =
fscache_acquire_cookie(afs_cache_netfs.primary_index,
&afs_cell_cache_index_def,
- cell, true);
-
-Then when a volume location was accessed, it would be entered into the cell's
-index and an inode would be allocated that acts as a volume type and hash chain
-combination:
+ cell->name, strlen(cell->name),
+ NULL, 0,
+ cell, 0, true);
- vlocation->cache =
- fscache_acquire_cookie(cell->cache,
- &afs_vlocation_cache_index_def,
- vlocation, true);
-
-And then a particular flavour of volume (R/O for example) could be added to
-that index, creating another index for vnodes (AFS inode equivalents):
+And then a particular volume could be added to that index by ID, creating
+another index for vnodes (AFS inode equivalents):
volume->cache =
- fscache_acquire_cookie(vlocation->cache,
+ fscache_acquire_cookie(volume->cell->cache,
&afs_volume_cache_index_def,
- volume, true);
+ &volume->vid, sizeof(volume->vid),
+ NULL, 0,
+ volume, 0, true);
======================
@@ -392,7 +370,9 @@ the object definition should be something other than index type.
vnode->cache =
fscache_acquire_cookie(volume->cache,
&afs_vnode_cache_object_def,
- vnode, true);
+ &key, sizeof(key),
+ &aux, sizeof(aux),
+ vnode, vnode->status.size, true);
=================================
@@ -408,7 +388,9 @@ it would be some other type of object such as a data file.
xattr->cache =
fscache_acquire_cookie(vnode->cache,
&afs_xattr_cache_object_def,
- xattr, true);
+ &xattr->name, strlen(xattr->name),
+ NULL, 0,
+ xattr, strlen(xattr->val), true);
Miscellaneous objects might be used to store extended attributes or directory
entries for example.
@@ -425,8 +407,7 @@ cache to adjust its metadata for data tracking appropriately:
int fscache_attr_changed(struct fscache_cookie *cookie);
The cache will return -ENOBUFS if there is no backing cache or if there is no
-space to allocate any extra metadata required in the cache. The attributes
-will be accessed with the get_attr() cookie definition operation.
+space to allocate any extra metadata required in the cache.
Note that attempts to read or write data pages in the cache over this size may
be rebuffed with -ENOBUFS.
@@ -551,12 +532,13 @@ written back to the cache:
int fscache_write_page(struct fscache_cookie *cookie,
struct page *page,
+ loff_t object_size,
gfp_t gfp);
The cookie argument must specify a data file cookie, the page specified should
contain the data to be written (and is also used to specify the page number),
-and the gfp argument is used to control how any memory allocations made are
-satisfied.
+object_size is the revised size of the object and the gfp argument is used to
+control how any memory allocations made are satisfied.
The page must have first been read or allocated successfully and must not have
been uncached before writing is performed.
@@ -717,21 +699,23 @@ INDEX AND DATA FILE CONSISTENCY
To find out whether auxiliary data for an object is up to data within the
cache, the following function can be called:
- int fscache_check_consistency(struct fscache_cookie *cookie)
+ int fscache_check_consistency(struct fscache_cookie *cookie,
+ const void *aux_data);
This will call back to the netfs to check whether the auxiliary data associated
-with a cookie is correct. It returns 0 if it is and -ESTALE if it isn't; it
-may also return -ENOMEM and -ERESTARTSYS.
+with a cookie is correct; if aux_data is non-NULL, it will update the auxiliary
+data buffer first. It returns 0 if it is and -ESTALE if it isn't; it may also
+return -ENOMEM and -ERESTARTSYS.
To request an update of the index data for an index or other object, the
following function should be called:
- void fscache_update_cookie(struct fscache_cookie *cookie);
+ void fscache_update_cookie(struct fscache_cookie *cookie,
+ const void *aux_data);
-This function will refer back to the netfs_data pointer stored in the cookie by
-the acquisition function to obtain the data to write into each revised index
-entry. The update method in the parent index definition will be called to
-transfer the data.
+This function will update the cookie's auxiliary data buffer from aux_data if
+that is non-NULL and then schedule this to be stored on disk. The update
+method in the parent index definition will be called to transfer the data.
Note that partial updates may happen automatically at other times, such as when
data blocks are added to a data file object.
@@ -748,10 +732,11 @@ still possible to uncache pages and relinquish the cookie.
The initial enablement state is set by fscache_acquire_cookie(), but the cookie
can be enabled or disabled later. To disable a cookie, call:
-
+
void fscache_disable_cookie(struct fscache_cookie *cookie,
+ const void *aux_data,
bool invalidate);
-
+
If the cookie is not already disabled, this locks the cookie against other
enable and disable ops, marks the cookie as being disabled, discards or
invalidates any backing objects and waits for cessation of activity on any
@@ -760,13 +745,15 @@ associated object before unlocking the cookie.
All possible failures are handled internally. The caller should consider
calling fscache_uncache_all_inode_pages() afterwards to make sure all page
markings are cleared up.
-
+
Cookies can be enabled or reenabled with:
-
+
void fscache_enable_cookie(struct fscache_cookie *cookie,
+ const void *aux_data,
+ loff_t object_size,
bool (*can_enable)(void *data),
void *data)
-
+
If the cookie is not already enabled, this locks the cookie against other
enable and disable ops, invokes can_enable() and, if the cookie is not an index
cookie, will begin the procedure of acquiring backing objects.
@@ -777,6 +764,12 @@ ruling as to whether or not enablement should actually be permitted to begin.
All possible failures are handled internally. The cookie will only be marked
as enabled if provisional backing objects are allocated.
+The object's data size is updated from object_size and is passed to the
+->check_aux() function.
+
+In both cases, the cookie's auxiliary data buffer is updated from aux_data if
+that is non-NULL inside the enablement lock before proceeding.
+
===============================
MISCELLANEOUS COOKIE OPERATIONS
@@ -823,6 +816,7 @@ COOKIE UNREGISTRATION
To get rid of a cookie, this function should be called.
void fscache_relinquish_cookie(struct fscache_cookie *cookie,
+ const void *aux_data,
bool retire);
If retire is non-zero, then the object will be marked for recycling, and all
@@ -833,6 +827,9 @@ If retire is zero, then the object may be available again when next the
acquisition function is called. Retirement here will overrule the pinning on a
cookie.
+The cookie's auxiliary data will be updated from aux_data if that is non-NULL
+so that the cache can lazily update it on disk.
+
One very important note - relinquish must NOT be called for a cookie unless all
the cookies for "child" indices, objects and pages have been relinquished
first.
diff --git a/Documentation/filesystems/ceph.txt b/Documentation/filesystems/ceph.txt
index 0b302a11718a..d7f011ddc150 100644
--- a/Documentation/filesystems/ceph.txt
+++ b/Documentation/filesystems/ceph.txt
@@ -62,6 +62,18 @@ subdirectories, and a summation of all nested file sizes. This makes
the identification of large disk space consumers relatively quick, as
no 'du' or similar recursive scan of the file system is required.
+Finally, Ceph also allows quotas to be set on any directory in the system.
+The quota can restrict the number of bytes or the number of files stored
+beneath that point in the directory hierarchy. Quotas can be set using
+extended attributes 'ceph.quota.max_files' and 'ceph.quota.max_bytes', eg:
+
+ setfattr -n ceph.quota.max_bytes -v 100000000 /some/dir
+ getfattr -n ceph.quota.max_bytes /some/dir
+
+A limitation of the current quotas implementation is that it relies on the
+cooperation of the client mounting the file system to stop writers when a
+limit is reached. A modified or adversarial client cannot be prevented
+from writing as much data as it needs.
Mount Syntax
============
@@ -137,6 +149,10 @@ Mount Options
noasyncreaddir
Do not use the dcache as above for readdir.
+ noquotadf
+ Report overall filesystem usage in statfs instead of using the root
+ directory quota.
+
More Information
================
diff --git a/Documentation/filesystems/cifs/README b/Documentation/filesystems/cifs/README
index a9da51553ba3..99ce3d25003d 100644
--- a/Documentation/filesystems/cifs/README
+++ b/Documentation/filesystems/cifs/README
@@ -11,13 +11,14 @@ Information Foundation. CIFS and now SMB3 has now become a defacto
standard for interoperating between Macs and Windows and major NAS appliances.
Please see
+ MS-SMB2 (for detailed SMB2/SMB3/SMB3.1.1 protocol specification)
http://protocolfreedom.org/ and
http://samba.org/samba/PFIF/
for more details.
For questions or bug reports please contact:
- sfrench@samba.org (sfrench@us.ibm.com)
+ smfrench@gmail.com
See the project page at: https://wiki.samba.org/index.php/LinuxCIFS_utils
@@ -37,15 +38,15 @@ Installation instructions:
=========================
If you have built the CIFS vfs as module (successfully) simply
type "make modules_install" (or if you prefer, manually copy the file to
-the modules directory e.g. /lib/modules/2.4.10-4GB/kernel/fs/cifs/cifs.o).
+the modules directory e.g. /lib/modules/2.4.10-4GB/kernel/fs/cifs/cifs.ko).
If you have built the CIFS vfs into the kernel itself, follow the instructions
for your distribution on how to install a new kernel (usually you
would simply type "make install").
-If you do not have the utility mount.cifs (in the Samba 3.0 source tree and on
-the CIFS VFS web site) copy it to the same directory in which mount.smbfs and
-similar files reside (usually /sbin). Although the helper software is not
+If you do not have the utility mount.cifs (in the Samba 4.x source tree and on
+the CIFS VFS web site) copy it to the same directory in which mount helpers
+reside (usually /sbin). Although the helper software is not
required, mount.cifs is recommended. Most distros include a "cifs-utils"
package that includes this utility so it is recommended to install this.
@@ -118,10 +119,13 @@ this can become unwieldy when potential mount targets include many
or unpredictable UNC names.
Samba Considerations
-====================
-To get the maximum benefit from the CIFS VFS, we recommend using a server that
-supports the SNIA CIFS Unix Extensions standard (e.g. Samba 2.2.5 or later or
-Samba 3.0) but the CIFS vfs works fine with a wide variety of CIFS servers.
+====================
+Most current servers support SMB2.1 and SMB3 which are more secure,
+but there are useful protocol extensions for the older less secure CIFS
+dialect, so to get the maximum benefit if mounting using the older dialect
+(CIFS/SMB1), we recommend using a server that supports the SNIA CIFS
+Unix Extensions standard (e.g. almost any version of Samba ie version
+2.2.5 or later) but the CIFS vfs works fine with a wide variety of CIFS servers.
Note that uid, gid and file permissions will display default values if you do
not have a server that supports the Unix extensions for CIFS (such as Samba
2.2.5 or later). To enable the Unix CIFS Extensions in the Samba server, add
@@ -603,11 +607,6 @@ Stats Lists summary resource usage information as well as per
in the kernel configuration.
Configuration pseudo-files:
-PacketSigningEnabled If set to one, cifs packet signing is enabled
- and will be used if the server requires
- it. If set to two, cifs packet signing is
- required even if the server considers packet
- signing optional. (default 1)
SecurityFlags Flags which control security negotiation and
also packet signing. Authentication (may/must)
flags (e.g. for NTLM and/or NTLMv2) may be combined with
@@ -666,8 +665,6 @@ traceSMB If set to one, debug information is logged to the
LookupCacheEnable If set to one, inode information is kept cached
for one second improving performance of lookups
(default 1)
-OplockEnabled If set to one, safe distributed caching enabled.
- (default 1)
LinuxExtensionsEnabled If set to one then the client will attempt to
use the CIFS "UNIX" extensions which are optional
protocol enhancements that allow CIFS servers
diff --git a/Documentation/filesystems/cifs/TODO b/Documentation/filesystems/cifs/TODO
index 396ecfd6ff4a..c5adf149b57f 100644
--- a/Documentation/filesystems/cifs/TODO
+++ b/Documentation/filesystems/cifs/TODO
@@ -1,4 +1,4 @@
-Version 2.04 September 13, 2017
+Version 2.11 September 13, 2017
A Partial List of Missing Features
==================================
@@ -8,10 +8,10 @@ for visible, important contributions to this module. Here
is a partial list of the known problems and missing features:
a) SMB3 (and SMB3.02) missing optional features:
- - RDMA (started)
- - multichannel (started)
+ - multichannel (started), integration with RDMA
- directory leases (improved metadata caching)
- - T10 copy offload (copy chunk is only mechanism supported)
+ - T10 copy offload (copy chunk, and "Duplicate Extents" ioctl
+ currently the only two server side copy mechanisms supported)
b) improved sparse file support
@@ -21,9 +21,8 @@ using Directory Leases
d) quota support (needs minor kernel change since quota calls
to make it to network filesystems or deviceless filesystems)
-e) Better optimize open to reduce redundant opens (using reference
-counts more) and to improve use of compounding in SMB3 to reduce
-number of roundtrips.
+e) Compounding (in progress) to reduce number of roundtrips, and also
+better optimize open to reduce redundant opens (using reference counts more).
f) Finish inotify support so kde and gnome file list windows
will autorefresh (partially complete by Asser). Needs minor kernel
@@ -35,7 +34,8 @@ the CIFS statistics (started)
h) implement support for security and trusted categories of xattrs
(requires minor protocol extension) to enable better support for SELINUX
-i) Implement O_DIRECT flag on open (already supported on mount)
+i) Add support for tree connect contexts (see MS-SMB2) a new SMB3.1.1 protocol
+ feature (may be especially useful for virtualization).
j) Create UID mapping facility so server UIDs can be mapped on a per
mount or a per server basis to client UIDs or nobody if no mapping
@@ -53,13 +53,16 @@ viewing them.
o) mount helper GUI (to simplify the various configuration options on mount)
-p) autonegotiation of dialects (offering more than one dialect ie SMB3.02,
-SMB3, SMB2.1 not just SMB3).
+p) Add support for witness protocol (perhaps ioctl to cifs.ko from user space
+ tool listening on witness protocol RPC) to allow for notification of share
+ move, server failover, and server adapter changes. And also improve other
+ failover scenarios, e.g. when client knows multiple DFS entries point to
+ different servers, and the server we are connected to has gone down.
q) Allow mount.cifs to be more verbose in reporting errors with dialect
or unsupported feature errors.
-r) updating cifs documentation, and user guid.
+r) updating cifs documentation, and user guide.
s) Addressing bugs found by running a broader set of xfstests in standard
file system xfstest suite.
diff --git a/Documentation/filesystems/f2fs.txt b/Documentation/filesystems/f2fs.txt
index 13c2ff034348..12a147c9f87f 100644
--- a/Documentation/filesystems/f2fs.txt
+++ b/Documentation/filesystems/f2fs.txt
@@ -174,6 +174,23 @@ offgrpjquota Turn off group journelled quota.
offprjjquota Turn off project journelled quota.
quota Enable plain user disk quota accounting.
noquota Disable all plain disk quota option.
+whint_mode=%s Control which write hints are passed down to block
+ layer. This supports "off", "user-based", and
+ "fs-based". In "off" mode (default), f2fs does not pass
+ down hints. In "user-based" mode, f2fs tries to pass
+ down hints given by users. And in "fs-based" mode, f2fs
+ passes down hints with its policy.
+alloc_mode=%s Adjust block allocation policy, which supports "reuse"
+ and "default".
+fsync_mode=%s Control the policy of fsync. Currently supports "posix"
+ and "strict". In "posix" mode, which is default, fsync
+ will follow POSIX semantics and does a light operation
+ to improve the filesystem performance. In "strict" mode,
+ fsync will be heavy and behaves in line with xfs, ext4
+ and btrfs, where xfstest generic/342 will pass, but the
+ performance will regress.
+test_dummy_encryption Enable dummy encryption, which provides a fake fscrypt
+ context. The fake fscrypt context is used by xfstests.
================================================================================
DEBUGFS ENTRIES
@@ -611,3 +628,63 @@ algorithm.
In order to identify whether the data in the victim segment are valid or not,
F2FS manages a bitmap. Each bit represents the validity of a block, and the
bitmap is composed of a bit stream covering whole blocks in main area.
+
+Write-hint Policy
+-----------------
+
+1) whint_mode=off. F2FS only passes down WRITE_LIFE_NOT_SET.
+
+2) whint_mode=user-based. F2FS tries to pass down hints given by
+users.
+
+User F2FS Block
+---- ---- -----
+ META WRITE_LIFE_NOT_SET
+ HOT_NODE "
+ WARM_NODE "
+ COLD_NODE "
+*ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
+*extension list " "
+
+-- buffered io
+WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
+WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
+WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
+WRITE_LIFE_NONE " "
+WRITE_LIFE_MEDIUM " "
+WRITE_LIFE_LONG " "
+
+-- direct io
+WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
+WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
+WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
+WRITE_LIFE_NONE " WRITE_LIFE_NONE
+WRITE_LIFE_MEDIUM " WRITE_LIFE_MEDIUM
+WRITE_LIFE_LONG " WRITE_LIFE_LONG
+
+3) whint_mode=fs-based. F2FS passes down hints with its policy.
+
+User F2FS Block
+---- ---- -----
+ META WRITE_LIFE_MEDIUM;
+ HOT_NODE WRITE_LIFE_NOT_SET
+ WARM_NODE "
+ COLD_NODE WRITE_LIFE_NONE
+ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
+extension list " "
+
+-- buffered io
+WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
+WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
+WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_LONG
+WRITE_LIFE_NONE " "
+WRITE_LIFE_MEDIUM " "
+WRITE_LIFE_LONG " "
+
+-- direct io
+WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
+WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
+WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
+WRITE_LIFE_NONE " WRITE_LIFE_NONE
+WRITE_LIFE_MEDIUM " WRITE_LIFE_MEDIUM
+WRITE_LIFE_LONG " WRITE_LIFE_LONG
diff --git a/Documentation/filesystems/gfs2-glocks.txt b/Documentation/filesystems/gfs2-glocks.txt
index 1fb12f9dfe48..7059623635b2 100644
--- a/Documentation/filesystems/gfs2-glocks.txt
+++ b/Documentation/filesystems/gfs2-glocks.txt
@@ -100,14 +100,15 @@ indicates that it is caching uptodate data.
Glock locking order within GFS2:
- 1. i_mutex (if required)
+ 1. i_rwsem (if required)
2. Rename glock (for rename only)
3. Inode glock(s)
(Parents before children, inodes at "same level" with same parent in
lock number order)
4. Rgrp glock(s) (for (de)allocation operations)
5. Transaction glock (via gfs2_trans_begin) for non-read operations
- 6. Page lock (always last, very important!)
+ 6. i_rw_mutex (if required)
+ 7. Page lock (always last, very important!)
There are two glocks per inode. One deals with access to the inode
itself (locking order as above), and the other, known as the iopen
diff --git a/Documentation/filesystems/orangefs.txt b/Documentation/filesystems/orangefs.txt
index e2818b60a5c2..f4ba94950e3f 100644
--- a/Documentation/filesystems/orangefs.txt
+++ b/Documentation/filesystems/orangefs.txt
@@ -21,10 +21,16 @@ Orangefs features include:
* Stateless
-MAILING LIST
-============
+MAILING LIST ARCHIVES
+=====================
-http://beowulf-underground.org/mailman/listinfo/pvfs2-users
+http://lists.orangefs.org/pipermail/devel_lists.orangefs.org/
+
+
+MAILING LIST SUBMISSIONS
+========================
+
+devel@lists.orangefs.org
DOCUMENTATION
@@ -42,12 +48,59 @@ Orangefs versions prior to 2.9.3 would not be compatible with the
upstream version of the kernel client.
-BUILDING THE USERSPACE FILESYSTEM ON A SINGLE SERVER
-====================================================
+RUNNING ORANGEFS ON A SINGLE SERVER
+===================================
+
+OrangeFS is usually run in large installations with multiple servers and
+clients, but a complete filesystem can be run on a single machine for
+development and testing.
+
+On Fedora, install orangefs and orangefs-server.
+
+dnf -y install orangefs orangefs-server
+
+There is an example server configuration file in
+/etc/orangefs/orangefs.conf. Change localhost to your hostname if
+necessary.
+
+To generate a filesystem to run xfstests against, see below.
+
+There is an example client configuration file in /etc/pvfs2tab. It is a
+single line. Uncomment it and change the hostname if necessary. This
+controls clients which use libpvfs2. This does not control the
+pvfs2-client-core.
+
+Create the filesystem.
+
+pvfs2-server -f /etc/orangefs/orangefs.conf
+
+Start the server.
+
+systemctl start orangefs-server
+
+Test the server.
+
+pvfs2-ping -m /pvfsmnt
+
+Start the client. The module must be compiled in or loaded before this
+point.
+
+systemctl start orangefs-client
+
+Mount the filesystem.
+
+mount -t pvfs2 tcp://localhost:3334/orangefs /pvfsmnt
+
-You can omit --prefix if you don't care that things are sprinkled around in
-/usr/local. As of version 2.9.6, Orangefs uses Berkeley DB by default, we
-will probably be changing the default to lmdb soon.
+BUILDING ORANGEFS ON A SINGLE SERVER
+====================================
+
+Where OrangeFS cannot be installed from distribution packages, it may be
+built from source.
+
+You can omit --prefix if you don't care that things are sprinkled around
+in /usr/local. As of version 2.9.6, OrangeFS uses Berkeley DB by
+default, we will probably be changing the default to LMDB soon.
./configure --prefix=/opt/ofs --with-db-backend=lmdb
@@ -55,35 +108,69 @@ make
make install
-Create an orangefs config file:
+Create an orangefs config file.
+
/opt/ofs/bin/pvfs2-genconfig /etc/pvfs2.conf
- for "Enter hostnames", use the hostname, don't let it default to
- localhost.
+Create an /etc/pvfs2tab file.
+
+echo tcp://localhost:3334/orangefs /pvfsmnt pvfs2 defaults,noauto 0 0 > \
+ /etc/pvfs2tab
+
+Create the mount point you specified in the tab file if needed.
-create a pvfs2tab file in /etc:
-cat /etc/pvfs2tab
-tcp://myhostname:3334/orangefs /mymountpoint pvfs2 defaults,noauto 0 0
+mkdir /pvfsmnt
-create the mount point you specified in the tab file if needed:
-mkdir /mymountpoint
+Bootstrap the server.
-bootstrap the server:
-/opt/ofs/sbin/pvfs2-server /etc/pvfs2.conf -f
+/opt/ofs/sbin/pvfs2-server -f /etc/pvfs2.conf
+
+Start the server.
-start the server:
/opt/osf/sbin/pvfs2-server /etc/pvfs2.conf
-Now the server is running. At this point you might like to
-prove things are working with:
+Now the server should be running. Pvfs2-ls is a simple
+test to verify that the server is running.
+
+/opt/ofs/bin/pvfs2-ls /pvfsmnt
-/opt/osf/bin/pvfs2-ls /mymountpoint
+If stuff seems to be working, load the kernel module and
+turn on the client core.
-If stuff seems to be working, turn on the client core:
-/opt/osf/sbin/pvfs2-client -p /opt/osf/sbin/pvfs2-client-core
+/opt/ofs/sbin/pvfs2-client -p /opt/osf/sbin/pvfs2-client-core
Mount your filesystem.
-mount -t pvfs2 tcp://myhostname:3334/orangefs /mymountpoint
+
+mount -t pvfs2 tcp://localhost:3334/orangefs /pvfsmnt
+
+
+RUNNING XFSTESTS
+================
+
+It is useful to use a scratch filesystem with xfstests. This can be
+done with only one server.
+
+Make a second copy of the FileSystem section in the server configuration
+file, which is /etc/orangefs/orangefs.conf. Change the Name to scratch.
+Change the ID to something other than the ID of the first FileSystem
+section (2 is usually a good choice).
+
+Then there are two FileSystem sections: orangefs and scratch.
+
+This change should be made before creating the filesystem.
+
+pvfs2-server -f /etc/orangefs/orangefs.conf
+
+To run xfstests, create /etc/xfsqa.config.
+
+TEST_DIR=/orangefs
+TEST_DEV=tcp://localhost:3334/orangefs
+SCRATCH_MNT=/scratch
+SCRATCH_DEV=tcp://localhost:3334/scratch
+
+Then xfstests can be run
+
+./check -pvfs2
OPTIONS
diff --git a/Documentation/filesystems/overlayfs.txt b/Documentation/filesystems/overlayfs.txt
index 6ea1e64d1464..961b287ef323 100644
--- a/Documentation/filesystems/overlayfs.txt
+++ b/Documentation/filesystems/overlayfs.txt
@@ -14,9 +14,13 @@ The result will inevitably fail to look exactly like a normal
filesystem for various technical reasons. The expectation is that
many use cases will be able to ignore these differences.
-This approach is 'hybrid' because the objects that appear in the
-filesystem do not all appear to belong to that filesystem. In many
-cases an object accessed in the union will be indistinguishable
+
+Overlay objects
+---------------
+
+The overlay filesystem approach is 'hybrid', because the objects that
+appear in the filesystem do not always appear to belong to that filesystem.
+In many cases, an object accessed in the union will be indistinguishable
from accessing the corresponding object from the original filesystem.
This is most obvious from the 'st_dev' field returned by stat(2).
@@ -34,6 +38,19 @@ make the overlay mount more compliant with filesystem scanners and
overlay objects will be distinguishable from the corresponding
objects in the original filesystem.
+On 64bit systems, even if all overlay layers are not on the same
+underlying filesystem, the same compliant behavior could be achieved
+with the "xino" feature. The "xino" feature composes a unique object
+identifier from the real object st_ino and an underlying fsid index.
+If all underlying filesystems support NFS file handles and export file
+handles with 32bit inode number encoding (e.g. ext4), overlay filesystem
+will use the high inode number bits for fsid. Even when the underlying
+filesystem uses 64bit inode numbers, users can still enable the "xino"
+feature with the "-o xino=on" overlay mount option. That is useful for the
+case of underlying filesystems like xfs and tmpfs, which use 64bit inode
+numbers, but are very unlikely to use the high inode number bit.
+
+
Upper and Lower
---------------
@@ -290,10 +307,19 @@ Non-standard behavior
---------------------
The copy_up operation essentially creates a new, identical file and
-moves it over to the old name. The new file may be on a different
-filesystem, so both st_dev and st_ino of the file may change.
+moves it over to the old name. Any open files referring to this inode
+will access the old data.
+
+The new file may be on a different filesystem, so both st_dev and st_ino
+of the real file may change. The values of st_dev and st_ino returned by
+stat(2) on an overlay object are often not the same as the real file
+stat(2) values to prevent the values from changing on copy_up.
-Any open files referring to this inode will access the old data.
+Unless "xino" feature is enabled, when overlay layers are not all on the
+same underlying filesystem, the value of st_dev may be different for two
+non-directory objects in the same overlay filesystem and the value of
+st_ino for directory objects may be non persistent and could change even
+while the overlay filesystem is still mounted.
Unless "inode index" feature is enabled, if a file with multiple hard
links is copied up, then this will "break" the link. Changes will not be
@@ -302,6 +328,7 @@ propagated to other names referring to the same inode.
Unless "redirect_dir" feature is enabled, rename(2) on a lower or merged
directory will fail with EXDEV.
+
Changes to underlying filesystems
---------------------------------
diff --git a/Documentation/filesystems/udf.txt b/Documentation/filesystems/udf.txt
index d3d0e3218f86..e2f2faf32f18 100644
--- a/Documentation/filesystems/udf.txt
+++ b/Documentation/filesystems/udf.txt
@@ -36,18 +36,14 @@ The following mount options are supported:
iocharset= Set the NLS character set
The uid= and gid= options need a bit more explaining. They will accept a
-decimal numeric value which will be used as the default ID for that mount.
-They will also accept the string "ignore" and "forget". For files on the disk
-that are owned by nobody ( -1 ), they will instead look as if they are owned
-by the default ID. The ignore option causes the default ID to override all
-IDs on the disk, not just -1. The forget option causes all IDs to be written
-to disk as -1, so when the media is later remounted, they will appear to be
-owned by whatever default ID it is mounted with at that time.
+decimal numeric value and all inodes on that mount will then appear as
+belonging to that uid and gid. Mount options also accept the string "forget".
+The forget option causes all IDs to be written to disk as -1 which is a way
+of UDF standard to indicate that IDs are not supported for these files .
-For typical desktop use of removable media, you should set the ID to that
-of the interactively logged on user, and also specify both the forget and
-ignore options. This way the interactive user will always see the files
-on the disk as belonging to him.
+For typical desktop use of removable media, you should set the ID to that of
+the interactively logged on user, and also specify the forget option. This way
+the interactive user will always see the files on the disk as belonging to him.
The remaining are for debugging and disaster recovery:
@@ -57,16 +53,8 @@ The following expect a offset from 0.
session= Set the CDROM session (default= last session)
anchor= Override standard anchor location. (default= 256)
- volume= Override the VolumeDesc location. (unused)
- partition= Override the PartitionDesc location. (unused)
lastblock= Set the last block of the filesystem/
-The following expect a offset from the partition root.
-
- fileset= Override the fileset block location. (unused)
- rootdir= Override the root directory location. (unused)
- WARNING: overriding the rootdir to a non-directory may
- yield highly unpredictable results.
-------------------------------------------------------------------------------
diff --git a/Documentation/filesystems/xfs.txt b/Documentation/filesystems/xfs.txt
index 3b9b5c149f32..4d9ff0a7f8e1 100644
--- a/Documentation/filesystems/xfs.txt
+++ b/Documentation/filesystems/xfs.txt
@@ -9,7 +9,7 @@ variable block sizes, is extent based, and makes extensive use of
Btrees (directories, extents, free space) to aid both performance
and scalability.
-Refer to the documentation at http://oss.sgi.com/projects/xfs/
+Refer to the documentation at https://xfs.wiki.kernel.org/
for further details. This implementation is on-disk compatible
with the IRIX version of XFS.
diff --git a/Documentation/frv/README.txt b/Documentation/frv/README.txt
deleted file mode 100644
index a984faa968e8..000000000000
--- a/Documentation/frv/README.txt
+++ /dev/null
@@ -1,51 +0,0 @@
- ================================
- Fujitsu FR-V LINUX DOCUMENTATION
- ================================
-
-This directory contains documentation for the Fujitsu FR-V CPU architecture
-port of Linux.
-
-The following documents are available:
-
- (*) features.txt
-
- A description of the basic features inherent in this architecture port.
-
-
- (*) configuring.txt
-
- A summary of the configuration options particular to this architecture.
-
-
- (*) booting.txt
-
- A description of how to boot the kernel image and a summary of the kernel
- command line options.
-
-
- (*) gdbstub.txt
-
- A description of how to debug the kernel using GDB attached by serial
- port, and a summary of the services available.
-
-
- (*) mmu-layout.txt
-
- A description of the virtual and physical memory layout used in the
- MMU linux kernel, and the registers used to support it.
-
-
- (*) gdbinit
-
- An example .gdbinit file for use with GDB. It includes macros for viewing
- MMU state on the FR451. See mmu-layout.txt for more information.
-
-
- (*) clock.txt
-
- A description of the CPU clock scaling interface.
-
-
- (*) atomic-ops.txt
-
- A description of how the FR-V kernel's atomic operations work.
diff --git a/Documentation/frv/atomic-ops.txt b/Documentation/frv/atomic-ops.txt
deleted file mode 100644
index 96638e9b9fe0..000000000000
--- a/Documentation/frv/atomic-ops.txt
+++ /dev/null
@@ -1,134 +0,0 @@
- =====================================
- FUJITSU FR-V KERNEL ATOMIC OPERATIONS
- =====================================
-
-On the FR-V CPUs, there is only one atomic Read-Modify-Write operation: the SWAP/SWAPI
-instruction. Unfortunately, this alone can't be used to implement the following operations:
-
- (*) Atomic add to memory
-
- (*) Atomic subtract from memory
-
- (*) Atomic bit modification (set, clear or invert)
-
- (*) Atomic compare and exchange
-
-On such CPUs, the standard way of emulating such operations in uniprocessor mode is to disable
-interrupts, but on the FR-V CPUs, modifying the PSR takes a lot of clock cycles, and it has to be
-done twice. This means the CPU runs for a relatively long time with interrupts disabled,
-potentially having a great effect on interrupt latency.
-
-
-=============
-NEW ALGORITHM
-=============
-
-To get around this, the following algorithm has been implemented. It operates in a way similar to
-the LL/SC instruction pairs supported on a number of platforms.
-
- (*) The CCCR.CC3 register is reserved within the kernel to act as an atomic modify abort flag.
-
- (*) In the exception prologues run on kernel->kernel entry, CCCR.CC3 is set to 0 (Undefined
- state).
-
- (*) All atomic operations can then be broken down into the following algorithm:
-
- (1) Set ICC3.Z to true and set CC3 to True (ORCC/CKEQ/ORCR).
-
- (2) Load the value currently in the memory to be modified into a register.
-
- (3) Make changes to the value.
-
- (4) If CC3 is still True, simultaneously and atomically (by VLIW packing):
-
- (a) Store the modified value back to memory.
-
- (b) Set ICC3.Z to false (CORCC on GR29 is sufficient for this - GR29 holds the current
- task pointer in the kernel, and so is guaranteed to be non-zero).
-
- (5) If ICC3.Z is still true, go back to step (1).
-
-This works in a non-SMP environment because any interrupt or other exception that happens between
-steps (1) and (4) will set CC3 to the Undefined, thus aborting the store in (4a), and causing the
-condition in ICC3 to remain with the Z flag set, thus causing step (5) to loop back to step (1).
-
-
-This algorithm suffers from two problems:
-
- (1) The condition CCCR.CC3 is cleared unconditionally by an exception, irrespective of whether or
- not any changes were made to the target memory location during that exception.
-
- (2) The branch from step (5) back to step (1) may have to happen more than once until the store
- manages to take place. In theory, this loop could cycle forever because there are too many
- interrupts coming in, but it's unlikely.
-
-
-=======
-EXAMPLE
-=======
-
-Taking an example from include/asm-frv/atomic.h:
-
- static inline int atomic_add_return(int i, atomic_t *v)
- {
- unsigned long val;
-
- asm("0: \n"
-
-It starts by setting ICC3.Z to true for later use, and also transforming that into CC3 being in the
-True state.
-
- " orcc gr0,gr0,gr0,icc3 \n" <-- (1)
- " ckeq icc3,cc7 \n" <-- (1)
-
-Then it does the load. Note that the final phase of step (1) is done at the same time as the
-load. The VLIW packing ensures they are done simultaneously. The ".p" on the load must not be
-removed without swapping the order of these two instructions.
-
- " ld.p %M0,%1 \n" <-- (2)
- " orcr cc7,cc7,cc3 \n" <-- (1)
-
-Then the proposed modification is generated. Note that the old value can be retained if required
-(such as in test_and_set_bit()).
-
- " add%I2 %1,%2,%1 \n" <-- (3)
-
-Then it attempts to store the value back, contingent on no exception having cleared CC3 since it
-was set to True.
-
- " cst.p %1,%M0 ,cc3,#1 \n" <-- (4a)
-
-It simultaneously records the success or failure of the store in ICC3.Z.
-
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" <-- (4b)
-
-Such that the branch can then be taken if the operation was aborted.
-
- " beq icc3,#0,0b \n" <-- (5)
- : "+U"(v->counter), "=&r"(val)
- : "NPr"(i)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- return val;
- }
-
-
-=============
-CONFIGURATION
-=============
-
-The atomic ops implementation can be made inline or out-of-line by changing the
-CONFIG_FRV_OUTOFLINE_ATOMIC_OPS configuration variable. Making it out-of-line has a number of
-advantages:
-
- - The resulting kernel image may be smaller
- - Debugging is easier as atomic ops can just be stepped over and they can be breakpointed
-
-Keeping it inline also has a number of advantages:
-
- - The resulting kernel may be Faster
- - no out-of-line function calls need to be made
- - the compiler doesn't have half its registers clobbered by making a call
-
-The out-of-line implementations live in arch/frv/lib/atomic-ops.S.
diff --git a/Documentation/frv/booting.txt b/Documentation/frv/booting.txt
deleted file mode 100644
index cd9dc1dfb144..000000000000
--- a/Documentation/frv/booting.txt
+++ /dev/null
@@ -1,182 +0,0 @@
- =========================
- BOOTING FR-V LINUX KERNEL
- =========================
-
-======================
-PROVIDING A FILESYSTEM
-======================
-
-First of all, a root filesystem must be made available. This can be done in
-one of two ways:
-
- (1) NFS Export
-
- A filesystem should be constructed in a directory on an NFS server that
- the target board can reach. This directory should then be NFS exported
- such that the target board can read and write into it as root.
-
- (2) Flash Filesystem (JFFS2 Recommended)
-
- In this case, the image must be stored or built up on flash before it
- can be used. A complete image can be built using the mkfs.jffs2 or
- similar program and then downloaded and stored into flash by RedBoot.
-
-
-========================
-LOADING THE KERNEL IMAGE
-========================
-
-The kernel will need to be loaded into RAM by RedBoot (or by some alternative
-boot loader) before it can be run. The kernel image (arch/frv/boot/Image) may
-be loaded in one of three ways:
-
- (1) Load from Flash
-
- This is the simplest. RedBoot can store an image in the flash (see the
- RedBoot documentation) and then load it back into RAM. RedBoot keeps
- track of the load address, entry point and size, so the command to do
- this is simply:
-
- fis load linux
-
- The image is then ready to be executed.
-
- (2) Load by TFTP
-
- The following command will download a raw binary kernel image from the
- default server (as negotiated by BOOTP) and store it into RAM:
-
- load -b 0x00100000 -r /tftpboot/image.bin
-
- The image is then ready to be executed.
-
- (3) Load by Y-Modem
-
- The following command will download a raw binary kernel image across the
- serial port that RedBoot is currently using:
-
- load -m ymodem -b 0x00100000 -r zImage
-
- The serial client (such as minicom) must then be told to transmit the
- program by Y-Modem.
-
- When finished, the image will then be ready to be executed.
-
-
-==================
-BOOTING THE KERNEL
-==================
-
-Boot the image with the following RedBoot command:
-
- exec -c "<CMDLINE>" 0x00100000
-
-For example:
-
- exec -c "console=ttySM0,115200 ip=:::::dhcp root=/dev/mtdblock2 rw"
-
-This will start the kernel running. Note that if the GDB-stub is compiled in,
-then the kernel will immediately wait for GDB to connect over serial before
-doing anything else. See the section on kernel debugging with GDB.
-
-The kernel command line <CMDLINE> tells the kernel where its console is and
-how to find its root filesystem. This is made up of the following components,
-separated by spaces:
-
- (*) console=ttyS<x>[,<baud>[<parity>[<bits>[<flow>]]]]
-
- This specifies that the system console should output through on-chip
- serial port <x> (which can be "0" or "1").
-
- <baud> is a standard baud rate between 1200 and 115200 (default 9600).
-
- <parity> is a parity setting of "N", "O", "E", "M" or "S" for None, Odd,
- Even, Mark or Space. "None" is the default.
-
- <stop> is "7" or "8" for the number of bits per character. "8" is the
- default.
-
- <flow> is "r" to use flow control (XCTS on serial port 2 only). The
- default is to not use flow control.
-
- For example:
-
- console=ttyS0,115200
-
- To use the first on-chip serial port at baud rate 115200, no parity, 8
- bits, and no flow control.
-
- (*) root=<xxxx>
-
- This specifies the device upon which the root filesystem resides. It
- may be specified by major and minor number, device path, or even
- partition uuid, if supported. For example:
-
- /dev/nfs NFS root filesystem
- /dev/mtdblock3 Fourth RedBoot partition on the System Flash
- PARTUUID=00112233-4455-6677-8899-AABBCCDDEEFF/PARTNROFF=1
- first partition after the partition with the given UUID
- 253:0 Device with major 253 and minor 0
-
- Authoritative information can be found in
- "Documentation/admin-guide/kernel-parameters.rst".
-
- (*) rw
-
- Start with the root filesystem mounted Read/Write.
-
- The remaining components are all optional:
-
- (*) ip=<ip>::::<host>:<iface>:<cfg>
-
- Configure the network interface. If <cfg> is "off" then <ip> should
- specify the IP address for the network device <iface>. <host> provide
- the hostname for the device.
-
- If <cfg> is "bootp" or "dhcp", then all of these parameters will be
- discovered by consulting a BOOTP or DHCP server.
-
- For example, the following might be used:
-
- ip=192.168.73.12::::frv:eth0:off
-
- This sets the IP address on the VDK motherboard RTL8029 ethernet chipset
- (eth0) to be 192.168.73.12, and sets the board's hostname to be "frv".
-
- (*) nfsroot=<server>:<dir>[,v<vers>]
-
- This is mandatory if "root=/dev/nfs" is given as an option. It tells the
- kernel the IP address of the NFS server providing its root filesystem,
- and the pathname on that server of the filesystem.
-
- The NFS version to use can also be specified. v2 and v3 are supported by
- Linux.
-
- For example:
-
- nfsroot=192.168.73.1:/nfsroot-frv
-
- (*) profile=1
-
- Turns on the kernel profiler (accessible through /proc/profile).
-
- (*) console=gdb0
-
- This can be used as an alternative to the "console=ttyS..." listed
- above. I tells the kernel to pass the console output to GDB if the
- gdbstub is compiled in to the kernel.
-
- If this is used, then the gdbstub passes the text to GDB, which then
- simply dumps it to its standard output.
-
- (*) mem=<xxx>M
-
- Normally the kernel will work out how much SDRAM it has by reading the
- SDRAM controller registers. That can be overridden with this
- option. This allows the kernel to be told that it has <xxx> megabytes of
- memory available.
-
- (*) init=<prog> [<arg> [<arg> [<arg> ...]]]
-
- This tells the kernel what program to run initially. By default this is
- /sbin/init, but /sbin/sash or /bin/sh are common alternatives.
diff --git a/Documentation/frv/clock.txt b/Documentation/frv/clock.txt
deleted file mode 100644
index c72d350e177a..000000000000
--- a/Documentation/frv/clock.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Clock scaling
--------------
-
-The kernel supports scaling of CLCK.CMODE, CLCK.CM and CLKC.P0 clock
-registers. If built with CONFIG_PM and CONFIG_SYSCTL options enabled, four
-extra files will appear in the directory /proc/sys/pm/. Reading these files
-will show:
-
- p0 -- current value of the P0 bit in CLKC register.
- cm -- current value of the CM bits in CLKC register.
- cmode -- current value of the CMODE bits in CLKC register.
-
-On all boards, the 'p0' file should also be writable, and either '1' or '0'
-can be rewritten, to set or clear the CLKC_P0 bit respectively, hence
-controlling whether the resource bus rate clock is halved.
-
-The 'cm' file should also be available on all boards. '0' can be written to it
-to shift the board into High-Speed mode (normal), and '1' can be written to
-shift the board into Medium-Speed mode. Selecting Low-Speed mode is not
-supported by this interface, even though some CPUs do support it.
-
-On the boards with FR405 CPU (i.e. CB60 and CB70), the 'cmode' file is also
-writable, allowing the CPU core speed (and other clock speeds) to be
-controlled from userspace.
-
-
-Determining current and possible settings
------------------------------------------
-
-The current state and the available masks can be found in /proc/cpuinfo. For
-example, on the CB70:
-
- # cat /proc/cpuinfo
- CPU-Series: fr400
- CPU-Core: fr405, gr0-31, BE, CCCR
- CPU: mb93405
- MMU: Prot
- FP-Media: fr0-31, Media
- System: mb93091-cb70, mb93090-mb00
- PM-Controls: cmode=0xd31f, cm=0x3, p0=0x3, suspend=0x9
- PM-Status: cmode=3, cm=0, p0=0
- Clock-In: 50.00 MHz
- Clock-Core: 300.00 MHz
- Clock-SDRAM: 100.00 MHz
- Clock-CBus: 100.00 MHz
- Clock-Res: 50.00 MHz
- Clock-Ext: 50.00 MHz
- Clock-DSU: 25.00 MHz
- BogoMips: 300.00
-
-And on the PDK, the PM lines look like the following:
-
- PM-Controls: cm=0x3, p0=0x3, suspend=0x9
- PM-Status: cmode=9, cm=0, p0=0
-
-The PM-Controls line, if present, will indicate which /proc/sys/pm files can
-be set to what values. The specification values are bitmasks; so, for example,
-"suspend=0x9" indicates that 0 and 3 can be written validly to
-/proc/sys/pm/suspend.
-
-The PM-Controls line will only be present if CONFIG_PM is configured to Y.
-
-The PM-Status line indicates which clock controls are set to which value. If
-the file can be read, then the suspend value must be 0, and so that's not
-included.
diff --git a/Documentation/frv/configuring.txt b/Documentation/frv/configuring.txt
deleted file mode 100644
index 36e76a2336fa..000000000000
--- a/Documentation/frv/configuring.txt
+++ /dev/null
@@ -1,125 +0,0 @@
- =======================================
- FUJITSU FR-V LINUX KERNEL CONFIGURATION
- =======================================
-
-=====================
-CONFIGURATION OPTIONS
-=====================
-
-The most important setting is in the "MMU support options" tab (the first
-presented in the configuration tools available):
-
- (*) "Kernel Type"
-
- This options allows selection of normal, MMU-requiring linux, and uClinux
- (which doesn't require an MMU and doesn't have inter-process protection).
-
-There are a number of settings in the "Processor type and features" section of
-the kernel configuration that need to be considered.
-
- (*) "CPU"
-
- The register and instruction sets at the core of the processor. This can
- only be set to "FR40x/45x/55x" at the moment - but this permits usage of
- the kernel with MB93091 CB10, CB11, CB30, CB41, CB60, CB70 and CB451
- CPU boards, and with the MB93093 PDK board.
-
- (*) "System"
-
- This option allows a choice of basic system. This governs the peripherals
- that are expected to be available.
-
- (*) "Motherboard"
-
- This specifies the type of motherboard being used, and the peripherals
- upon it. Currently only "MB93090-MB00" can be set here.
-
- (*) "Default cache-write mode"
-
- This controls the initial data cache write management mode. By default
- Write-Through is selected, but Write-Back (Copy-Back) can also be
- selected. This can be changed dynamically once the kernel is running (see
- features.txt).
-
-There are some architecture specific configuration options in the "General
-Setup" section of the kernel configuration too:
-
- (*) "Reserve memory uncached for (PCI) DMA"
-
- This requests that a uClinux kernel set aside some memory in an uncached
- window for the use as consistent DMA memory (mainly for PCI). At least a
- megabyte will be allocated in this way, possibly more. Any memory so
- reserved will not be available for normal allocations.
-
- (*) "Kernel support for ELF-FDPIC binaries"
-
- This enables the binary-format driver for the new FDPIC ELF binaries that
- this platform normally uses. These binaries are totally relocatable -
- their separate sections can relocated independently, allowing them to be
- shared on uClinux where possible. This should normally be enabled.
-
- (*) "Kernel image protection"
-
- This makes the protection register governing access to the core kernel
- image prohibit access by userspace programs. This option is available on
- uClinux only.
-
-There are also a number of settings in the "Kernel Hacking" section of the
-kernel configuration especially for debugging a kernel on this
-architecture. See the "gdbstub.txt" file for information about those.
-
-
-======================
-DEFAULT CONFIGURATIONS
-======================
-
-The kernel sources include a number of example default configurations:
-
- (*) defconfig-mb93091
-
- Default configuration for the MB93091-VDK with both CPU board and
- MB93090-MB00 motherboard running uClinux.
-
-
- (*) defconfig-mb93091-fb
-
- Default configuration for the MB93091-VDK with CPU board,
- MB93090-MB00 motherboard, and DAV board running uClinux.
- Includes framebuffer driver.
-
-
- (*) defconfig-mb93093
-
- Default configuration for the MB93093-PDK board running uClinux.
-
-
- (*) defconfig-cb70-standalone
-
- Default configuration for the MB93091-VDK with only CB70 CPU board
- running uClinux. This will use the CB70's DM9000 for network access.
-
-
- (*) defconfig-mmu
-
- Default configuration for the MB93091-VDK with both CB451 CPU board and
- MB93090-MB00 motherboard running MMU linux.
-
- (*) defconfig-mmu-audio
-
- Default configuration for the MB93091-VDK with CB451 CPU board, DAV
- board, and MB93090-MB00 motherboard running MMU linux. Includes
- audio driver.
-
- (*) defconfig-mmu-fb
-
- Default configuration for the MB93091-VDK with CB451 CPU board, DAV
- board, and MB93090-MB00 motherboard running MMU linux. Includes
- framebuffer driver.
-
- (*) defconfig-mmu-standalone
-
- Default configuration for the MB93091-VDK with only CB451 CPU board
- running MMU linux.
-
-
-
diff --git a/Documentation/frv/features.txt b/Documentation/frv/features.txt
deleted file mode 100644
index fa20c0e72833..000000000000
--- a/Documentation/frv/features.txt
+++ /dev/null
@@ -1,310 +0,0 @@
- ===========================
- FUJITSU FR-V LINUX FEATURES
- ===========================
-
-This kernel port has a number of features of which the user should be aware:
-
- (*) Linux and uClinux
-
- The FR-V architecture port supports both normal MMU linux and uClinux out
- of the same sources.
-
-
- (*) CPU support
-
- Support for the FR401, FR403, FR405, FR451 and FR555 CPUs should work with
- the same uClinux kernel configuration.
-
- In normal (MMU) Linux mode, only the FR451 CPU will work as that is the
- only one with a suitably featured CPU.
-
- The kernel is written and compiled with the assumption that only the
- bottom 32 GR registers and no FR registers will be used by the kernel
- itself, however all extra userspace registers will be saved on context
- switch. Note that since most CPUs can't support lazy switching, no attempt
- is made to do lazy register saving where that would be possible (FR555
- only currently).
-
-
- (*) Board support
-
- The board on which the kernel will run can be configured on the "Processor
- type and features" configuration tab.
-
- Set the System to "MB93093-PDK" to boot from the MB93093 (FR403) PDK.
-
- Set the System to "MB93091-VDK" to boot from the CB11, CB30, CB41, CB60,
- CB70 or CB451 VDK boards. Set the Motherboard setting to "MB93090-MB00" to
- boot with the standard ATA90590B VDK motherboard, and set it to "None" to
- boot without any motherboard.
-
-
- (*) Binary Formats
-
- The only userspace binary format supported is FDPIC ELF. Normal ELF, FLAT
- and AOUT binaries are not supported for this architecture.
-
- FDPIC ELF supports shared library and program interpreter facilities.
-
-
- (*) Scheduler Speed
-
- The kernel scheduler runs at 100Hz irrespective of the clock speed on this
- architecture. This value is set in asm/param.h (see the HZ macro defined
- there).
-
-
- (*) Normal (MMU) Linux Memory Layout.
-
- See mmu-layout.txt in this directory for a description of the normal linux
- memory layout
-
- See include/asm-frv/mem-layout.h for constants pertaining to the memory
- layout.
-
- See include/asm-frv/mb-regs.h for the constants pertaining to the I/O bus
- controller configuration.
-
-
- (*) uClinux Memory Layout
-
- The memory layout used by the uClinux kernel is as follows:
-
- 0x00000000 - 0x00000FFF Null pointer catch page
- 0x20000000 - 0x200FFFFF CS2# [PDK] FPGA
- 0xC0000000 - 0xCFFFFFFF SDRAM
- 0xC0000000 Base of Linux kernel image
- 0xE0000000 - 0xEFFFFFFF CS2# [VDK] SLBUS/PCI window
- 0xF0000000 - 0xF0FFFFFF CS5# MB93493 CSC area (DAV daughter board)
- 0xF1000000 - 0xF1FFFFFF CS7# [CB70/CB451] CPU-card PCMCIA port space
- 0xFC000000 - 0xFC0FFFFF CS1# [VDK] MB86943 config space
- 0xFC100000 - 0xFC1FFFFF CS6# [CB70/CB451] CPU-card DM9000 NIC space
- 0xFC100000 - 0xFC1FFFFF CS6# [PDK] AX88796 NIC space
- 0xFC200000 - 0xFC2FFFFF CS3# MB93493 CSR area (DAV daughter board)
- 0xFD000000 - 0xFDFFFFFF CS4# [CB70/CB451] CPU-card extra flash space
- 0xFE000000 - 0xFEFFFFFF Internal CPU peripherals
- 0xFF000000 - 0xFF1FFFFF CS0# Flash 1
- 0xFF200000 - 0xFF3FFFFF CS0# Flash 2
- 0xFFC00000 - 0xFFC0001F CS0# [VDK] FPGA
-
- The kernel reads the size of the SDRAM from the memory bus controller
- registers by default.
-
- The kernel initialisation code (1) adjusts the SDRAM base addresses to
- move the SDRAM to desired address, (2) moves the kernel image down to the
- bottom of SDRAM, (3) adjusts the bus controller registers to move I/O
- windows, and (4) rearranges the protection registers to protect all of
- this.
-
- The reasons for doing this are: (1) the page at address 0 should be
- inaccessible so that NULL pointer errors can be caught; and (2) the bottom
- three quarters are left unoccupied so that an FR-V CPU with an MMU can use
- it for virtual userspace mappings.
-
- See include/asm-frv/mem-layout.h for constants pertaining to the memory
- layout.
-
- See include/asm-frv/mb-regs.h for the constants pertaining to the I/O bus
- controller configuration.
-
-
- (*) uClinux Memory Protection
-
- A DAMPR register is used to cover the entire region used for I/O
- (0xE0000000 - 0xFFFFFFFF). This permits the kernel to make uncached
- accesses to this region. Userspace is not permitted to access it.
-
- The DAMPR/IAMPR protection registers not in use for any other purpose are
- tiled over the top of the SDRAM such that:
-
- (1) The core kernel image is covered by as small a tile as possible
- granting only the kernel access to the underlying data, whilst
- making sure no SDRAM is actually made unavailable by this approach.
-
- (2) All other tiles are arranged to permit userspace access to the rest
- of the SDRAM.
-
- Barring point (1), there is nothing to protect kernel data against
- userspace damage - but this is uClinux.
-
-
- (*) Exceptions and Fixups
-
- Since the FR40x and FR55x CPUs that do not have full MMUs generate
- imprecise data error exceptions, there are currently no automatic fixup
- services available in uClinux. This includes misaligned memory access
- fixups.
-
- Userspace EFAULT errors can be trapped by issuing a MEMBAR instruction and
- forcing the fault to happen there.
-
- On the FR451, however, data exceptions are mostly precise, and so
- exception fixup handling is implemented as normal.
-
-
- (*) Userspace Breakpoints
-
- The ptrace() system call supports the following userspace debugging
- features:
-
- (1) Hardware assisted single step.
-
- (2) Breakpoint via the FR-V "BREAK" instruction.
-
- (3) Breakpoint via the FR-V "TIRA GR0, #1" instruction.
-
- (4) Syscall entry/exit trap.
-
- Each of the above generates a SIGTRAP.
-
-
- (*) On-Chip Serial Ports
-
- The FR-V on-chip serial ports are made available as ttyS0 and ttyS1. Note
- that if the GDB stub is compiled in, ttyS1 will not actually be available
- as it will be being used for the GDB stub.
-
- These ports can be made by:
-
- mknod /dev/ttyS0 c 4 64
- mknod /dev/ttyS1 c 4 65
-
-
- (*) Maskable Interrupts
-
- Level 15 (Non-maskable) interrupts are dealt with by the GDB stub if
- present, and cause a panic if not. If the GDB stub is present, ttyS1's
- interrupts are rated at level 15.
-
- All other interrupts are distributed over the set of available priorities
- so that no IRQs are shared where possible. The arch interrupt handling
- routines attempt to disentangle the various sources available through the
- CPU's own multiplexor, and those on off-CPU peripherals.
-
-
- (*) Accessing PCI Devices
-
- Where PCI is available, care must be taken when dealing with drivers that
- access PCI devices. PCI devices present their data in little-endian form,
- but the CPU sees it in big-endian form. The macros in asm/io.h try to get
- this right, but may not under all circumstances...
-
-
- (*) Ax88796 Ethernet Driver
-
- The MB93093 PDK board has an Ax88796 ethernet chipset (an NE2000 clone). A
- driver has been written to deal specifically with this. The driver
- provides MII services for the card.
-
- The driver can be configured by running make xconfig, and going to:
-
- (*) Network device support
- - turn on "Network device support"
- (*) Ethernet (10 or 100Mbit)
- - turn on "Ethernet (10 or 100Mbit)"
- - turn on "AX88796 NE2000 compatible chipset"
-
- The driver can be found in:
-
- drivers/net/ax88796.c
- include/asm/ax88796.h
-
-
- (*) WorkRAM Driver
-
- This driver provides a character device that permits access to the WorkRAM
- that can be found on the FR451 CPU. Each page is accessible through a
- separate minor number, thereby permitting each page to have its own
- filesystem permissions set on the device file.
-
- The device files should be:
-
- mknod /dev/frv/workram0 c 240 0
- mknod /dev/frv/workram1 c 240 1
- mknod /dev/frv/workram2 c 240 2
- ...
-
- The driver will not permit the opening of any device file that does not
- correspond to at least a partial page of WorkRAM. So the first device file
- is the only one available on the FR451. If any other CPU is detected, none
- of the devices will be openable.
-
- The devices can be accessed with read, write and llseek, and can also be
- mmapped. If they're mmapped, they will only map at the appropriate
- 0x7e8nnnnn address on linux and at the 0xfe8nnnnn address on uClinux. If
- MAP_FIXED is not specified, the appropriate address will be chosen anyway.
-
- The mappings must be MAP_SHARED not MAP_PRIVATE, and must not be
- PROT_EXEC. They must also start at file offset 0, and must not be longer
- than one page in size.
-
- This driver can be configured by running make xconfig, and going to:
-
- (*) Character devices
- - turn on "Fujitsu FR-V CPU WorkRAM support"
-
-
- (*) Dynamic data cache write mode changing
-
- It is possible to view and to change the data cache's write mode through
- the /proc/sys/frv/cache-mode file while the kernel is running. There are
- two modes available:
-
- NAME MEANING
- ===== ==========================================
- wthru Data cache is in Write-Through mode
- wback Data cache is in Write-Back/Copy-Back mode
-
- To read the cache mode:
-
- # cat /proc/sys/frv/cache-mode
- wthru
-
- To change the cache mode:
-
- # echo wback >/proc/sys/frv/cache-mode
- # cat /proc/sys/frv/cache-mode
- wback
-
-
- (*) MMU Context IDs and Pinning
-
- On MMU Linux the CPU supports the concept of a context ID in its MMU to
- make it more efficient (TLB entries are labelled with a context ID to link
- them to specific tasks).
-
- Normally once a context ID is allocated, it will remain affixed to a task
- or CLONE_VM'd group of tasks for as long as it exists. However, since the
- kernel is capable of supporting more tasks than there are possible ID
- numbers, the kernel will pass context IDs from one task to another if
- there are insufficient available.
-
- The context ID currently in use by a task can be viewed in /proc:
-
- # grep CXNR /proc/1/status
- CXNR: 1
-
- Note that kernel threads do not have a userspace context, and so will not
- show a CXNR entry in that file.
-
- Under some circumstances, however, it is desirable to pin a context ID on
- a process such that the kernel won't pass it on. This can be done by
- writing the process ID of the target process to a special file:
-
- # echo 17 >/proc/sys/frv/pin-cxnr
-
- Reading from the file will then show the context ID pinned.
-
- # cat /proc/sys/frv/pin-cxnr
- 4
-
- The context ID will remain pinned as long as any process is using that
- context, i.e.: when the all the subscribing processes have exited or
- exec'd; or when an unpinning request happens:
-
- # echo 0 >/proc/sys/frv/pin-cxnr
-
- When there isn't a pinned context, the file shows -1:
-
- # cat /proc/sys/frv/pin-cxnr
- -1
diff --git a/Documentation/frv/gdbinit b/Documentation/frv/gdbinit
deleted file mode 100644
index 51517b6f307f..000000000000
--- a/Documentation/frv/gdbinit
+++ /dev/null
@@ -1,102 +0,0 @@
-set remotebreak 1
-
-define _amr
-
-printf "AMRx DAMR IAMR \n"
-printf "==== ===================== =====================\n"
-printf "amr0 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x0].L,__debug_mmu.damr[0x0].P,__debug_mmu.iamr[0x0].L,__debug_mmu.iamr[0x0].P
-printf "amr1 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x1].L,__debug_mmu.damr[0x1].P,__debug_mmu.iamr[0x1].L,__debug_mmu.iamr[0x1].P
-printf "amr2 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x2].L,__debug_mmu.damr[0x2].P,__debug_mmu.iamr[0x2].L,__debug_mmu.iamr[0x2].P
-printf "amr3 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x3].L,__debug_mmu.damr[0x3].P,__debug_mmu.iamr[0x3].L,__debug_mmu.iamr[0x3].P
-printf "amr4 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x4].L,__debug_mmu.damr[0x4].P,__debug_mmu.iamr[0x4].L,__debug_mmu.iamr[0x4].P
-printf "amr5 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x5].L,__debug_mmu.damr[0x5].P,__debug_mmu.iamr[0x5].L,__debug_mmu.iamr[0x5].P
-printf "amr6 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x6].L,__debug_mmu.damr[0x6].P,__debug_mmu.iamr[0x6].L,__debug_mmu.iamr[0x6].P
-printf "amr7 : L:%08lx P:%08lx : L:%08lx P:%08lx\n",__debug_mmu.damr[0x7].L,__debug_mmu.damr[0x7].P,__debug_mmu.iamr[0x7].L,__debug_mmu.iamr[0x7].P
-
-printf "amr8 : L:%08lx P:%08lx\n",__debug_mmu.damr[0x8].L,__debug_mmu.damr[0x8].P
-printf "amr9 : L:%08lx P:%08lx\n",__debug_mmu.damr[0x9].L,__debug_mmu.damr[0x9].P
-printf "amr10: L:%08lx P:%08lx\n",__debug_mmu.damr[0xa].L,__debug_mmu.damr[0xa].P
-printf "amr11: L:%08lx P:%08lx\n",__debug_mmu.damr[0xb].L,__debug_mmu.damr[0xb].P
-
-end
-
-
-define _tlb
-printf "tlb[0x00]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x0].L,__debug_mmu.tlb[0x0].P,__debug_mmu.tlb[0x40+0x0].L,__debug_mmu.tlb[0x40+0x0].P
-printf "tlb[0x01]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1].L,__debug_mmu.tlb[0x1].P,__debug_mmu.tlb[0x40+0x1].L,__debug_mmu.tlb[0x40+0x1].P
-printf "tlb[0x02]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2].L,__debug_mmu.tlb[0x2].P,__debug_mmu.tlb[0x40+0x2].L,__debug_mmu.tlb[0x40+0x2].P
-printf "tlb[0x03]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3].L,__debug_mmu.tlb[0x3].P,__debug_mmu.tlb[0x40+0x3].L,__debug_mmu.tlb[0x40+0x3].P
-printf "tlb[0x04]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x4].L,__debug_mmu.tlb[0x4].P,__debug_mmu.tlb[0x40+0x4].L,__debug_mmu.tlb[0x40+0x4].P
-printf "tlb[0x05]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x5].L,__debug_mmu.tlb[0x5].P,__debug_mmu.tlb[0x40+0x5].L,__debug_mmu.tlb[0x40+0x5].P
-printf "tlb[0x06]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x6].L,__debug_mmu.tlb[0x6].P,__debug_mmu.tlb[0x40+0x6].L,__debug_mmu.tlb[0x40+0x6].P
-printf "tlb[0x07]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x7].L,__debug_mmu.tlb[0x7].P,__debug_mmu.tlb[0x40+0x7].L,__debug_mmu.tlb[0x40+0x7].P
-printf "tlb[0x08]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x8].L,__debug_mmu.tlb[0x8].P,__debug_mmu.tlb[0x40+0x8].L,__debug_mmu.tlb[0x40+0x8].P
-printf "tlb[0x09]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x9].L,__debug_mmu.tlb[0x9].P,__debug_mmu.tlb[0x40+0x9].L,__debug_mmu.tlb[0x40+0x9].P
-printf "tlb[0x0a]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0xa].L,__debug_mmu.tlb[0xa].P,__debug_mmu.tlb[0x40+0xa].L,__debug_mmu.tlb[0x40+0xa].P
-printf "tlb[0x0b]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0xb].L,__debug_mmu.tlb[0xb].P,__debug_mmu.tlb[0x40+0xb].L,__debug_mmu.tlb[0x40+0xb].P
-printf "tlb[0x0c]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0xc].L,__debug_mmu.tlb[0xc].P,__debug_mmu.tlb[0x40+0xc].L,__debug_mmu.tlb[0x40+0xc].P
-printf "tlb[0x0d]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0xd].L,__debug_mmu.tlb[0xd].P,__debug_mmu.tlb[0x40+0xd].L,__debug_mmu.tlb[0x40+0xd].P
-printf "tlb[0x0e]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0xe].L,__debug_mmu.tlb[0xe].P,__debug_mmu.tlb[0x40+0xe].L,__debug_mmu.tlb[0x40+0xe].P
-printf "tlb[0x0f]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0xf].L,__debug_mmu.tlb[0xf].P,__debug_mmu.tlb[0x40+0xf].L,__debug_mmu.tlb[0x40+0xf].P
-printf "tlb[0x10]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x10].L,__debug_mmu.tlb[0x10].P,__debug_mmu.tlb[0x40+0x10].L,__debug_mmu.tlb[0x40+0x10].P
-printf "tlb[0x11]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x11].L,__debug_mmu.tlb[0x11].P,__debug_mmu.tlb[0x40+0x11].L,__debug_mmu.tlb[0x40+0x11].P
-printf "tlb[0x12]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x12].L,__debug_mmu.tlb[0x12].P,__debug_mmu.tlb[0x40+0x12].L,__debug_mmu.tlb[0x40+0x12].P
-printf "tlb[0x13]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x13].L,__debug_mmu.tlb[0x13].P,__debug_mmu.tlb[0x40+0x13].L,__debug_mmu.tlb[0x40+0x13].P
-printf "tlb[0x14]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x14].L,__debug_mmu.tlb[0x14].P,__debug_mmu.tlb[0x40+0x14].L,__debug_mmu.tlb[0x40+0x14].P
-printf "tlb[0x15]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x15].L,__debug_mmu.tlb[0x15].P,__debug_mmu.tlb[0x40+0x15].L,__debug_mmu.tlb[0x40+0x15].P
-printf "tlb[0x16]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x16].L,__debug_mmu.tlb[0x16].P,__debug_mmu.tlb[0x40+0x16].L,__debug_mmu.tlb[0x40+0x16].P
-printf "tlb[0x17]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x17].L,__debug_mmu.tlb[0x17].P,__debug_mmu.tlb[0x40+0x17].L,__debug_mmu.tlb[0x40+0x17].P
-printf "tlb[0x18]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x18].L,__debug_mmu.tlb[0x18].P,__debug_mmu.tlb[0x40+0x18].L,__debug_mmu.tlb[0x40+0x18].P
-printf "tlb[0x19]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x19].L,__debug_mmu.tlb[0x19].P,__debug_mmu.tlb[0x40+0x19].L,__debug_mmu.tlb[0x40+0x19].P
-printf "tlb[0x1a]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1a].L,__debug_mmu.tlb[0x1a].P,__debug_mmu.tlb[0x40+0x1a].L,__debug_mmu.tlb[0x40+0x1a].P
-printf "tlb[0x1b]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1b].L,__debug_mmu.tlb[0x1b].P,__debug_mmu.tlb[0x40+0x1b].L,__debug_mmu.tlb[0x40+0x1b].P
-printf "tlb[0x1c]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1c].L,__debug_mmu.tlb[0x1c].P,__debug_mmu.tlb[0x40+0x1c].L,__debug_mmu.tlb[0x40+0x1c].P
-printf "tlb[0x1d]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1d].L,__debug_mmu.tlb[0x1d].P,__debug_mmu.tlb[0x40+0x1d].L,__debug_mmu.tlb[0x40+0x1d].P
-printf "tlb[0x1e]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1e].L,__debug_mmu.tlb[0x1e].P,__debug_mmu.tlb[0x40+0x1e].L,__debug_mmu.tlb[0x40+0x1e].P
-printf "tlb[0x1f]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x1f].L,__debug_mmu.tlb[0x1f].P,__debug_mmu.tlb[0x40+0x1f].L,__debug_mmu.tlb[0x40+0x1f].P
-printf "tlb[0x20]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x20].L,__debug_mmu.tlb[0x20].P,__debug_mmu.tlb[0x40+0x20].L,__debug_mmu.tlb[0x40+0x20].P
-printf "tlb[0x21]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x21].L,__debug_mmu.tlb[0x21].P,__debug_mmu.tlb[0x40+0x21].L,__debug_mmu.tlb[0x40+0x21].P
-printf "tlb[0x22]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x22].L,__debug_mmu.tlb[0x22].P,__debug_mmu.tlb[0x40+0x22].L,__debug_mmu.tlb[0x40+0x22].P
-printf "tlb[0x23]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x23].L,__debug_mmu.tlb[0x23].P,__debug_mmu.tlb[0x40+0x23].L,__debug_mmu.tlb[0x40+0x23].P
-printf "tlb[0x24]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x24].L,__debug_mmu.tlb[0x24].P,__debug_mmu.tlb[0x40+0x24].L,__debug_mmu.tlb[0x40+0x24].P
-printf "tlb[0x25]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x25].L,__debug_mmu.tlb[0x25].P,__debug_mmu.tlb[0x40+0x25].L,__debug_mmu.tlb[0x40+0x25].P
-printf "tlb[0x26]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x26].L,__debug_mmu.tlb[0x26].P,__debug_mmu.tlb[0x40+0x26].L,__debug_mmu.tlb[0x40+0x26].P
-printf "tlb[0x27]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x27].L,__debug_mmu.tlb[0x27].P,__debug_mmu.tlb[0x40+0x27].L,__debug_mmu.tlb[0x40+0x27].P
-printf "tlb[0x28]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x28].L,__debug_mmu.tlb[0x28].P,__debug_mmu.tlb[0x40+0x28].L,__debug_mmu.tlb[0x40+0x28].P
-printf "tlb[0x29]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x29].L,__debug_mmu.tlb[0x29].P,__debug_mmu.tlb[0x40+0x29].L,__debug_mmu.tlb[0x40+0x29].P
-printf "tlb[0x2a]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2a].L,__debug_mmu.tlb[0x2a].P,__debug_mmu.tlb[0x40+0x2a].L,__debug_mmu.tlb[0x40+0x2a].P
-printf "tlb[0x2b]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2b].L,__debug_mmu.tlb[0x2b].P,__debug_mmu.tlb[0x40+0x2b].L,__debug_mmu.tlb[0x40+0x2b].P
-printf "tlb[0x2c]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2c].L,__debug_mmu.tlb[0x2c].P,__debug_mmu.tlb[0x40+0x2c].L,__debug_mmu.tlb[0x40+0x2c].P
-printf "tlb[0x2d]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2d].L,__debug_mmu.tlb[0x2d].P,__debug_mmu.tlb[0x40+0x2d].L,__debug_mmu.tlb[0x40+0x2d].P
-printf "tlb[0x2e]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2e].L,__debug_mmu.tlb[0x2e].P,__debug_mmu.tlb[0x40+0x2e].L,__debug_mmu.tlb[0x40+0x2e].P
-printf "tlb[0x2f]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x2f].L,__debug_mmu.tlb[0x2f].P,__debug_mmu.tlb[0x40+0x2f].L,__debug_mmu.tlb[0x40+0x2f].P
-printf "tlb[0x30]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x30].L,__debug_mmu.tlb[0x30].P,__debug_mmu.tlb[0x40+0x30].L,__debug_mmu.tlb[0x40+0x30].P
-printf "tlb[0x31]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x31].L,__debug_mmu.tlb[0x31].P,__debug_mmu.tlb[0x40+0x31].L,__debug_mmu.tlb[0x40+0x31].P
-printf "tlb[0x32]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x32].L,__debug_mmu.tlb[0x32].P,__debug_mmu.tlb[0x40+0x32].L,__debug_mmu.tlb[0x40+0x32].P
-printf "tlb[0x33]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x33].L,__debug_mmu.tlb[0x33].P,__debug_mmu.tlb[0x40+0x33].L,__debug_mmu.tlb[0x40+0x33].P
-printf "tlb[0x34]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x34].L,__debug_mmu.tlb[0x34].P,__debug_mmu.tlb[0x40+0x34].L,__debug_mmu.tlb[0x40+0x34].P
-printf "tlb[0x35]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x35].L,__debug_mmu.tlb[0x35].P,__debug_mmu.tlb[0x40+0x35].L,__debug_mmu.tlb[0x40+0x35].P
-printf "tlb[0x36]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x36].L,__debug_mmu.tlb[0x36].P,__debug_mmu.tlb[0x40+0x36].L,__debug_mmu.tlb[0x40+0x36].P
-printf "tlb[0x37]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x37].L,__debug_mmu.tlb[0x37].P,__debug_mmu.tlb[0x40+0x37].L,__debug_mmu.tlb[0x40+0x37].P
-printf "tlb[0x38]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x38].L,__debug_mmu.tlb[0x38].P,__debug_mmu.tlb[0x40+0x38].L,__debug_mmu.tlb[0x40+0x38].P
-printf "tlb[0x39]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x39].L,__debug_mmu.tlb[0x39].P,__debug_mmu.tlb[0x40+0x39].L,__debug_mmu.tlb[0x40+0x39].P
-printf "tlb[0x3a]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3a].L,__debug_mmu.tlb[0x3a].P,__debug_mmu.tlb[0x40+0x3a].L,__debug_mmu.tlb[0x40+0x3a].P
-printf "tlb[0x3b]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3b].L,__debug_mmu.tlb[0x3b].P,__debug_mmu.tlb[0x40+0x3b].L,__debug_mmu.tlb[0x40+0x3b].P
-printf "tlb[0x3c]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3c].L,__debug_mmu.tlb[0x3c].P,__debug_mmu.tlb[0x40+0x3c].L,__debug_mmu.tlb[0x40+0x3c].P
-printf "tlb[0x3d]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3d].L,__debug_mmu.tlb[0x3d].P,__debug_mmu.tlb[0x40+0x3d].L,__debug_mmu.tlb[0x40+0x3d].P
-printf "tlb[0x3e]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3e].L,__debug_mmu.tlb[0x3e].P,__debug_mmu.tlb[0x40+0x3e].L,__debug_mmu.tlb[0x40+0x3e].P
-printf "tlb[0x3f]: %08lx %08lx %08lx %08lx\n",__debug_mmu.tlb[0x3f].L,__debug_mmu.tlb[0x3f].P,__debug_mmu.tlb[0x40+0x3f].L,__debug_mmu.tlb[0x40+0x3f].P
-end
-
-
-define _pgd
-p (pgd_t[0x40])*(pgd_t*)(__debug_mmu.damr[0x3].L)
-end
-
-define _ptd_i
-p (pte_t[0x1000])*(pte_t*)(__debug_mmu.damr[0x4].L)
-end
-
-define _ptd_d
-p (pte_t[0x1000])*(pte_t*)(__debug_mmu.damr[0x5].L)
-end
diff --git a/Documentation/frv/gdbstub.txt b/Documentation/frv/gdbstub.txt
deleted file mode 100644
index b92bfd902a4e..000000000000
--- a/Documentation/frv/gdbstub.txt
+++ /dev/null
@@ -1,130 +0,0 @@
- ====================
- DEBUGGING FR-V LINUX
- ====================
-
-
-The kernel contains a GDB stub that talks GDB remote protocol across a serial
-port. This permits GDB to single step through the kernel, set breakpoints and
-trap exceptions that happen in kernel space and interrupt execution. It also
-permits the NMI interrupt button or serial port events to jump the kernel into
-the debugger.
-
-On the CPUs that have on-chip UARTs (FR400, FR403, FR405, FR555), the
-GDB stub hijacks a serial port for its own purposes, and makes it
-generate level 15 interrupts (NMI). The kernel proper cannot see the serial
-port in question under these conditions.
-
-On the MB93091-VDK CPU boards, the GDB stub uses UART1, which would otherwise
-be /dev/ttyS1. On the MB93093-PDK, the GDB stub uses UART0. Therefore, on the
-PDK there is no externally accessible serial port and the serial port to
-which the touch screen is attached becomes /dev/ttyS0.
-
-Note that the GDB stub runs entirely within CPU debug mode, and so should not
-incur any exceptions or interrupts whilst it is active. In particular, note
-that the clock will lose time since it is implemented in software.
-
-
-==================
-KERNEL PREPARATION
-==================
-
-Firstly, a debuggable kernel must be built. To do this, unpack the kernel tree
-and copy the configuration that you wish to use to .config. Then reconfigure
-the following things on the "Kernel Hacking" tab:
-
- (*) "Include debugging information"
-
- Set this to "Y". This causes all C and Assembly files to be compiled
- to include debugging information.
-
- (*) "In-kernel GDB stub"
-
- Set this to "Y". This causes the GDB stub to be compiled into the
- kernel.
-
- (*) "Immediate activation"
-
- Set this to "Y" if you want the GDB stub to activate as soon as possible
- and wait for GDB to connect. This allows you to start tracing right from
- the beginning of start_kernel() in init/main.c.
-
- (*) "Console through GDB stub"
-
- Set this to "Y" if you wish to be able to use "console=gdb0" on the
- command line. That tells the kernel to pass system console messages to
- GDB (which then prints them on its standard output). This is useful when
- debugging the serial drivers that'd otherwise be used to pass console
- messages to the outside world.
-
-Then build as usual, download to the board and execute. Note that if
-"Immediate activation" was selected, then the kernel will wait for GDB to
-attach. If not, then the kernel will boot immediately and GDB will have to
-interrupt it or wait for an exception to occur before doing anything with
-the kernel.
-
-
-=========================
-KERNEL DEBUGGING WITH GDB
-=========================
-
-Set the serial port on the computer that's going to run GDB to the appropriate
-baud rate. Assuming the board's debug port is connected to ttyS0/COM1 on the
-computer doing the debugging:
-
- stty -F /dev/ttyS0 115200
-
-Then start GDB in the base of the kernel tree:
-
- frv-uclinux-gdb linux [uClinux]
-
-Or:
-
- frv-uclinux-gdb vmlinux [MMU linux]
-
-When the prompt appears:
-
- GNU gdb frv-031024
- Copyright 2003 Free Software Foundation, Inc.
- GDB is free software, covered by the GNU General Public License, and you are
- welcome to change it and/or distribute copies of it under certain conditions.
- Type "show copying" to see the conditions.
- There is absolutely no warranty for GDB. Type "show warranty" for details.
- This GDB was configured as "--host=i686-pc-linux-gnu --target=frv-uclinux"...
- (gdb)
-
-Attach to the board like this:
-
- (gdb) target remote /dev/ttyS0
- Remote debugging using /dev/ttyS0
- start_kernel () at init/main.c:395
- (gdb)
-
-This should show the appropriate lines from the source too. The kernel can
-then be debugged almost as if it's any other program.
-
-
-===============================
-INTERRUPTING THE RUNNING KERNEL
-===============================
-
-The kernel can be interrupted whilst it is running, causing a jump back to the
-GDB stub and the debugger:
-
- (*) Pressing Ctrl-C in GDB. This will cause GDB to try and interrupt the
- kernel by sending an RS232 BREAK over the serial line to the GDB
- stub. This will (mostly) immediately interrupt the kernel and return it
- to the debugger.
-
- (*) Pressing the NMI button on the board will also cause a jump into the
- debugger.
-
- (*) Setting a software breakpoint. This sets a break instruction at the
- desired location which the GDB stub then traps the exception for.
-
- (*) Setting a hardware breakpoint. The GDB stub is capable of using the IBAR
- and DBAR registers to assist debugging.
-
-Furthermore, the GDB stub will intercept a number of exceptions automatically
-if they are caused by kernel execution. It will also intercept BUG() macro
-invocation.
-
diff --git a/Documentation/frv/kernel-ABI.txt b/Documentation/frv/kernel-ABI.txt
deleted file mode 100644
index aaa1cec86f0b..000000000000
--- a/Documentation/frv/kernel-ABI.txt
+++ /dev/null
@@ -1,262 +0,0 @@
- =================================
- INTERNAL KERNEL ABI FOR FR-V ARCH
- =================================
-
-The internal FRV kernel ABI is not quite the same as the userspace ABI. A
-number of the registers are used for special purposed, and the ABI is not
-consistent between modules vs core, and MMU vs no-MMU.
-
-This partly stems from the fact that FRV CPUs do not have a separate
-supervisor stack pointer, and most of them do not have any scratch
-registers, thus requiring at least one general purpose register to be
-clobbered in such an event. Also, within the kernel core, it is possible to
-simply jump or call directly between functions using a relative offset.
-This cannot be extended to modules for the displacement is likely to be too
-far. Thus in modules the address of a function to call must be calculated
-in a register and then used, requiring two extra instructions.
-
-This document has the following sections:
-
- (*) System call register ABI
- (*) CPU operating modes
- (*) Internal kernel-mode register ABI
- (*) Internal debug-mode register ABI
- (*) Virtual interrupt handling
-
-
-========================
-SYSTEM CALL REGISTER ABI
-========================
-
-When a system call is made, the following registers are effective:
-
- REGISTERS CALL RETURN
- =============== ======================= =======================
- GR7 System call number Preserved
- GR8 Syscall arg #1 Return value
- GR9-GR13 Syscall arg #2-6 Preserved
-
-
-===================
-CPU OPERATING MODES
-===================
-
-The FR-V CPU has three basic operating modes. In order of increasing
-capability:
-
- (1) User mode.
-
- Basic userspace running mode.
-
- (2) Kernel mode.
-
- Normal kernel mode. There are many additional control registers
- available that may be accessed in this mode, in addition to all the
- stuff available to user mode. This has two submodes:
-
- (a) Exceptions enabled (PSR.T == 1).
-
- Exceptions will invoke the appropriate normal kernel mode
- handler. On entry to the handler, the PSR.T bit will be cleared.
-
- (b) Exceptions disabled (PSR.T == 0).
-
- No exceptions or interrupts may happen. Any mandatory exceptions
- will cause the CPU to halt unless the CPU is told to jump into
- debug mode instead.
-
- (3) Debug mode.
-
- No exceptions may happen in this mode. Memory protection and
- management exceptions will be flagged for later consideration, but
- the exception handler won't be invoked. Debugging traps such as
- hardware breakpoints and watchpoints will be ignored. This mode is
- entered only by debugging events obtained from the other two modes.
-
- All kernel mode registers may be accessed, plus a few extra debugging
- specific registers.
-
-
-=================================
-INTERNAL KERNEL-MODE REGISTER ABI
-=================================
-
-There are a number of permanent register assignments that are set up by
-entry.S in the exception prologue. Note that there is a complete set of
-exception prologues for each of user->kernel transition and kernel->kernel
-transition. There are also user->debug and kernel->debug mode transition
-prologues.
-
-
- REGISTER FLAVOUR USE
- =============== ======= ==============================================
- GR1 Supervisor stack pointer
- GR15 Current thread info pointer
- GR16 GP-Rel base register for small data
- GR28 Current exception frame pointer (__frame)
- GR29 Current task pointer (current)
- GR30 Destroyed by kernel mode entry
- GR31 NOMMU Destroyed by debug mode entry
- GR31 MMU Destroyed by TLB miss kernel mode entry
- CCR.ICC2 Virtual interrupt disablement tracking
- CCCR.CC3 Cleared by exception prologue
- (atomic op emulation)
- SCR0 MMU See mmu-layout.txt.
- SCR1 MMU See mmu-layout.txt.
- SCR2 MMU Save for EAR0 (destroyed by icache insns
- in debug mode)
- SCR3 MMU Save for GR31 during debug exceptions
- DAMR/IAMR NOMMU Fixed memory protection layout.
- DAMR/IAMR MMU See mmu-layout.txt.
-
-
-Certain registers are also used or modified across function calls:
-
- REGISTER CALL RETURN
- =============== =============================== ======================
- GR0 Fixed Zero -
- GR2 Function call frame pointer
- GR3 Special Preserved
- GR3-GR7 - Clobbered
- GR8 Function call arg #1 Return value
- (or clobbered)
- GR9 Function call arg #2 Return value MSW
- (or clobbered)
- GR10-GR13 Function call arg #3-#6 Clobbered
- GR14 - Clobbered
- GR15-GR16 Special Preserved
- GR17-GR27 - Preserved
- GR28-GR31 Special Only accessed
- explicitly
- LR Return address after CALL Clobbered
- CCR/CCCR - Mostly Clobbered
-
-
-================================
-INTERNAL DEBUG-MODE REGISTER ABI
-================================
-
-This is the same as the kernel-mode register ABI for functions calls. The
-difference is that in debug-mode there's a different stack and a different
-exception frame. Almost all the global registers from kernel-mode
-(including the stack pointer) may be changed.
-
- REGISTER FLAVOUR USE
- =============== ======= ==============================================
- GR1 Debug stack pointer
- GR16 GP-Rel base register for small data
- GR31 Current debug exception frame pointer
- (__debug_frame)
- SCR3 MMU Saved value of GR31
-
-
-Note that debug mode is able to interfere with the kernel's emulated atomic
-ops, so it must be exceedingly careful not to do any that would interact
-with the main kernel in this regard. Hence the debug mode code (gdbstub) is
-almost completely self-contained. The only external code used is the
-sprintf family of functions.
-
-Furthermore, break.S is so complicated because single-step mode does not
-switch off on entry to an exception. That means unless manually disabled,
-single-stepping will blithely go on stepping into things like interrupts.
-See gdbstub.txt for more information.
-
-
-==========================
-VIRTUAL INTERRUPT HANDLING
-==========================
-
-Because accesses to the PSR is so slow, and to disable interrupts we have
-to access it twice (once to read and once to write), we don't actually
-disable interrupts at all if we don't have to. What we do instead is use
-the ICC2 condition code flags to note virtual disablement, such that if we
-then do take an interrupt, we note the flag, really disable interrupts, set
-another flag and resume execution at the point the interrupt happened.
-Setting condition flags as a side effect of an arithmetic or logical
-instruction is really fast. This use of the ICC2 only occurs within the
-kernel - it does not affect userspace.
-
-The flags we use are:
-
- (*) CCR.ICC2.Z [Zero flag]
-
- Set to virtually disable interrupts, clear when interrupts are
- virtually enabled. Can be modified by logical instructions without
- affecting the Carry flag.
-
- (*) CCR.ICC2.C [Carry flag]
-
- Clear to indicate hardware interrupts are really disabled, set otherwise.
-
-
-What happens is this:
-
- (1) Normal kernel-mode operation.
-
- ICC2.Z is 0, ICC2.C is 1.
-
- (2) An interrupt occurs. The exception prologue examines ICC2.Z and
- determines that nothing needs doing. This is done simply with an
- unlikely BEQ instruction.
-
- (3) The interrupts are disabled (local_irq_disable)
-
- ICC2.Z is set to 1.
-
- (4) If interrupts were then re-enabled (local_irq_enable):
-
- ICC2.Z would be set to 0.
-
- A TIHI #2 instruction (trap #2 if condition HI - Z==0 && C==0) would
- be used to trap if interrupts were now virtually enabled, but
- physically disabled - which they're not, so the trap isn't taken. The
- kernel would then be back to state (1).
-
- (5) An interrupt occurs. The exception prologue examines ICC2.Z and
- determines that the interrupt shouldn't actually have happened. It
- jumps aside, and there disabled interrupts by setting PSR.PIL to 14
- and then it clears ICC2.C.
-
- (6) If interrupts were then saved and disabled again (local_irq_save):
-
- ICC2.Z would be shifted into the save variable and masked off
- (giving a 1).
-
- ICC2.Z would then be set to 1 (thus unchanged), and ICC2.C would be
- unaffected (ie: 0).
-
- (7) If interrupts were then restored from state (6) (local_irq_restore):
-
- ICC2.Z would be set to indicate the result of XOR'ing the saved
- value (ie: 1) with 1, which gives a result of 0 - thus leaving
- ICC2.Z set.
-
- ICC2.C would remain unaffected (ie: 0).
-
- A TIHI #2 instruction would be used to again assay the current state,
- but this would do nothing as Z==1.
-
- (8) If interrupts were then enabled (local_irq_enable):
-
- ICC2.Z would be cleared. ICC2.C would be left unaffected. Both
- flags would now be 0.
-
- A TIHI #2 instruction again issued to assay the current state would
- then trap as both Z==0 [interrupts virtually enabled] and C==0
- [interrupts really disabled] would then be true.
-
- (9) The trap #2 handler would simply enable hardware interrupts
- (set PSR.PIL to 0), set ICC2.C to 1 and return.
-
-(10) Immediately upon returning, the pending interrupt would be taken.
-
-(11) The interrupt handler would take the path of actually processing the
- interrupt (ICC2.Z is clear, BEQ fails as per step (2)).
-
-(12) The interrupt handler would then set ICC2.C to 1 since hardware
- interrupts are definitely enabled - or else the kernel wouldn't be here.
-
-(13) On return from the interrupt handler, things would be back to state (1).
-
-This trap (#2) is only available in kernel mode. In user mode it will
-result in SIGILL.
diff --git a/Documentation/frv/mmu-layout.txt b/Documentation/frv/mmu-layout.txt
deleted file mode 100644
index db10250df6be..000000000000
--- a/Documentation/frv/mmu-layout.txt
+++ /dev/null
@@ -1,306 +0,0 @@
- =================================
- FR451 MMU LINUX MEMORY MANAGEMENT
- =================================
-
-============
-MMU HARDWARE
-============
-
-FR451 MMU Linux puts the MMU into EDAT mode whilst running. This means that it uses both the SAT
-registers and the DAT TLB to perform address translation.
-
-There are 8 IAMLR/IAMPR register pairs and 16 DAMLR/DAMPR register pairs for SAT mode.
-
-In DAT mode, there is also a TLB organised in cache format as 64 lines x 2 ways. Each line spans a
-16KB range of addresses, but can match a larger region.
-
-
-===========================
-MEMORY MANAGEMENT REGISTERS
-===========================
-
-Certain control registers are used by the kernel memory management routines:
-
- REGISTERS USAGE
- ====================== ==================================================
- IAMR0, DAMR0 Kernel image and data mappings
- IAMR1, DAMR1 First-chance TLB lookup mapping
- DAMR2 Page attachment for cache flush by page
- DAMR3 Current PGD mapping
- SCR0, DAMR4 Instruction TLB PGE/PTD cache
- SCR1, DAMR5 Data TLB PGE/PTD cache
- DAMR6-10 kmap_atomic() mappings
- DAMR11 I/O mapping
- CXNR mm_struct context ID
- TTBR Page directory (PGD) pointer (physical address)
-
-
-=====================
-GENERAL MEMORY LAYOUT
-=====================
-
-The physical memory layout is as follows:
-
- PHYSICAL ADDRESS CONTROLLER DEVICE
- =================== ============== =======================================
- 00000000 - BFFFFFFF SDRAM SDRAM area
- E0000000 - EFFFFFFF L-BUS CS2# VDK SLBUS/PCI window
- F0000000 - F0FFFFFF L-BUS CS5# MB93493 CSC area (DAV daughter board)
- F1000000 - F1FFFFFF L-BUS CS7# (CB70 CPU-card PCMCIA port I/O space)
- FC000000 - FC0FFFFF L-BUS CS1# VDK MB86943 config space
- FC100000 - FC1FFFFF L-BUS CS6# DM9000 NIC I/O space
- FC200000 - FC2FFFFF L-BUS CS3# MB93493 CSR area (DAV daughter board)
- FD000000 - FDFFFFFF L-BUS CS4# (CB70 CPU-card extra flash space)
- FE000000 - FEFFFFFF Internal CPU peripherals
- FF000000 - FF1FFFFF L-BUS CS0# Flash 1
- FF200000 - FF3FFFFF L-BUS CS0# Flash 2
- FFC00000 - FFC0001F L-BUS CS0# FPGA
-
-The virtual memory layout is:
-
- VIRTUAL ADDRESS PHYSICAL TRANSLATOR FLAGS SIZE OCCUPATION
- ================= ======== ============== ======= ======= ===================================
- 00004000-BFFFFFFF various TLB,xAMR1 D-N-??V 3GB Userspace
- C0000000-CFFFFFFF 00000000 xAMPR0 -L-S--V 256MB Kernel image and data
- D0000000-D7FFFFFF various TLB,xAMR1 D-NS??V 128MB vmalloc area
- D8000000-DBFFFFFF various TLB,xAMR1 D-NS??V 64MB kmap() area
- DC000000-DCFFFFFF various TLB 1MB Secondary kmap_atomic() frame
- DD000000-DD27FFFF various DAMR 160KB Primary kmap_atomic() frame
- DD040000 DAMR2/IAMR2 -L-S--V page Page cache flush attachment point
- DD080000 DAMR3 -L-SC-V page Page Directory (PGD)
- DD0C0000 DAMR4 -L-SC-V page Cached insn TLB Page Table lookup
- DD100000 DAMR5 -L-SC-V page Cached data TLB Page Table lookup
- DD140000 DAMR6 -L-S--V page kmap_atomic(KM_BOUNCE_READ)
- DD180000 DAMR7 -L-S--V page kmap_atomic(KM_SKB_SUNRPC_DATA)
- DD1C0000 DAMR8 -L-S--V page kmap_atomic(KM_SKB_DATA_SOFTIRQ)
- DD200000 DAMR9 -L-S--V page kmap_atomic(KM_USER0)
- DD240000 DAMR10 -L-S--V page kmap_atomic(KM_USER1)
- E0000000-FFFFFFFF E0000000 DAMR11 -L-SC-V 512MB I/O region
-
-IAMPR1 and DAMPR1 are used as an extension to the TLB.
-
-
-====================
-KMAP AND KMAP_ATOMIC
-====================
-
-To access pages in the page cache (which may not be directly accessible if highmem is available),
-the kernel calls kmap(), does the access and then calls kunmap(); or it calls kmap_atomic(), does
-the access and then calls kunmap_atomic().
-
-kmap() creates an attachment between an arbitrary inaccessible page and a range of virtual
-addresses by installing a PTE in a special page table. The kernel can then access this page as it
-wills. When it's finished, the kernel calls kunmap() to clear the PTE.
-
-kmap_atomic() does something slightly different. In the interests of speed, it chooses one of two
-strategies:
-
- (1) If possible, kmap_atomic() attaches the requested page to one of DAMPR5 through DAMPR10
- register pairs; and the matching kunmap_atomic() clears the DAMPR. This makes high memory
- support really fast as there's no need to flush the TLB or modify the page tables. The DAMLR
- registers being used for this are preset during boot and don't change over the lifetime of the
- process. There's a direct mapping between the first few kmap_atomic() types, DAMR number and
- virtual address slot.
-
- However, there are more kmap_atomic() types defined than there are DAMR registers available,
- so we fall back to:
-
- (2) kmap_atomic() uses a slot in the secondary frame (determined by the type parameter), and then
- locks an entry in the TLB to translate that slot to the specified page. The number of slots is
- obviously limited, and their positions are controlled such that each slot is matched by a
- different line in the TLB. kunmap() ejects the entry from the TLB.
-
-Note that the first three kmap atomic types are really just declared as placeholders. The DAMPR
-registers involved are actually modified directly.
-
-Also note that kmap() itself may sleep, kmap_atomic() may never sleep and both always succeed;
-furthermore, a driver using kmap() may sleep before calling kunmap(), but may not sleep before
-calling kunmap_atomic() if it had previously called kmap_atomic().
-
-
-===============================
-USING MORE THAN 256MB OF MEMORY
-===============================
-
-The kernel cannot access more than 256MB of memory directly. The physical layout, however, permits
-up to 3GB of SDRAM (possibly 3.25GB) to be made available. By using CONFIG_HIGHMEM, the kernel can
-allow userspace (by way of page tables) and itself (by way of kmap) to deal with the memory
-allocation.
-
-External devices can, of course, still DMA to and from all of the SDRAM, even if the kernel can't
-see it directly. The kernel translates page references into real addresses for communicating to the
-devices.
-
-
-===================
-PAGE TABLE TOPOLOGY
-===================
-
-The page tables are arranged in 2-layer format. There is a middle layer (PMD) that would be used in
-3-layer format tables but that is folded into the top layer (PGD) and so consumes no extra memory
-or processing power.
-
- +------+ PGD PMD
- | TTBR |--->+-------------------+
- +------+ | | : STE |
- | PGE0 | PME0 : STE |
- | | : STE |
- +-------------------+ Page Table
- | | : STE -------------->+--------+ +0x0000
- | PGE1 | PME0 : STE -----------+ | PTE0 |
- | | : STE -------+ | +--------+
- +-------------------+ | | | PTE63 |
- | | : STE | | +-->+--------+ +0x0100
- | PGE2 | PME0 : STE | | | PTE64 |
- | | : STE | | +--------+
- +-------------------+ | | PTE127 |
- | | : STE | +------>+--------+ +0x0200
- | PGE3 | PME0 : STE | | PTE128 |
- | | : STE | +--------+
- +-------------------+ | PTE191 |
- +--------+ +0x0300
-
-Each Page Directory (PGD) is 16KB (page size) in size and is divided into 64 entries (PGEs). Each
-PGE contains one Page Mid Directory (PMD).
-
-Each PMD is 256 bytes in size and contains a single entry (PME). Each PME holds 64 FR451 MMU
-segment table entries of 4 bytes apiece. Each PME "points to" a page table. In practice, each STE
-points to a subset of the page table, the first to PT+0x0000, the second to PT+0x0100, the third to
-PT+0x200, and so on.
-
-Each PGE and PME covers 64MB of the total virtual address space.
-
-Each Page Table (PTD) is 16KB (page size) in size, and is divided into 4096 entries (PTEs). Each
-entry can point to one 16KB page. In practice, each Linux page table is subdivided into 64 FR451
-MMU page tables. But they are all grouped together to make management easier, in particular rmap
-support is then trivial.
-
-Grouping page tables in this fashion makes PGE caching in SCR0/SCR1 more efficient because the
-coverage of the cached item is greater.
-
-Page tables for the vmalloc area are allocated at boot time and shared between all mm_structs.
-
-
-=================
-USER SPACE LAYOUT
-=================
-
-For MMU capable Linux, the regions userspace code are allowed to access are kept entirely separate
-from those dedicated to the kernel:
-
- VIRTUAL ADDRESS SIZE PURPOSE
- ================= ===== ===================================
- 00000000-00003fff 4KB NULL pointer access trap
- 00004000-01ffffff ~32MB lower mmap space (grows up)
- 02000000-021fffff 2MB Stack space (grows down from top)
- 02200000-nnnnnnnn Executable mapping
- nnnnnnnn- brk space (grows up)
- -bfffffff upper mmap space (grows down)
-
-This is so arranged so as to make best use of the 16KB page tables and the way in which PGEs/PMEs
-are cached by the TLB handler. The lower mmap space is filled first, and then the upper mmap space
-is filled.
-
-
-===============================
-GDB-STUB MMU DEBUGGING SERVICES
-===============================
-
-The gdb-stub included in this kernel provides a number of services to aid in the debugging of MMU
-related kernel services:
-
- (*) Every time the kernel stops, certain state information is dumped into __debug_mmu. This
- variable is defined in arch/frv/kernel/gdb-stub.c. Note that the gdbinit file in this
- directory has some useful macros for dealing with this.
-
- (*) __debug_mmu.tlb[]
-
- This receives the current TLB contents. This can be viewed with the _tlb GDB macro:
-
- (gdb) _tlb
- tlb[0x00]: 01000005 00718203 01000002 00718203
- tlb[0x01]: 01004002 006d4201 01004005 006d4203
- tlb[0x02]: 01008002 006d0201 01008006 00004200
- tlb[0x03]: 0100c006 007f4202 0100c002 0064c202
- tlb[0x04]: 01110005 00774201 01110002 00774201
- tlb[0x05]: 01114005 00770201 01114002 00770201
- tlb[0x06]: 01118002 0076c201 01118005 0076c201
- ...
- tlb[0x3d]: 010f4002 00790200 001f4002 0054ca02
- tlb[0x3e]: 010f8005 0078c201 010f8002 0078c201
- tlb[0x3f]: 001fc002 0056ca01 001fc005 00538a01
-
- (*) __debug_mmu.iamr[]
- (*) __debug_mmu.damr[]
-
- These receive the current IAMR and DAMR contents. These can be viewed with the _amr
- GDB macro:
-
- (gdb) _amr
- AMRx DAMR IAMR
- ==== ===================== =====================
- amr0 : L:c0000000 P:00000cb9 : L:c0000000 P:000004b9
- amr1 : L:01070005 P:006f9203 : L:0102c005 P:006a1201
- amr2 : L:d8d00000 P:00000000 : L:d8d00000 P:00000000
- amr3 : L:d8d04000 P:00534c0d : L:00000000 P:00000000
- amr4 : L:d8d08000 P:00554c0d : L:00000000 P:00000000
- amr5 : L:d8d0c000 P:00554c0d : L:00000000 P:00000000
- amr6 : L:d8d10000 P:00000000 : L:00000000 P:00000000
- amr7 : L:d8d14000 P:00000000 : L:00000000 P:00000000
- amr8 : L:d8d18000 P:00000000
- amr9 : L:d8d1c000 P:00000000
- amr10: L:d8d20000 P:00000000
- amr11: L:e0000000 P:e0000ccd
-
- (*) The current task's page directory is bound to DAMR3.
-
- This can be viewed with the _pgd GDB macro:
-
- (gdb) _pgd
- $3 = {{pge = {{ste = {0x554001, 0x554101, 0x554201, 0x554301, 0x554401,
- 0x554501, 0x554601, 0x554701, 0x554801, 0x554901, 0x554a01,
- 0x554b01, 0x554c01, 0x554d01, 0x554e01, 0x554f01, 0x555001,
- 0x555101, 0x555201, 0x555301, 0x555401, 0x555501, 0x555601,
- 0x555701, 0x555801, 0x555901, 0x555a01, 0x555b01, 0x555c01,
- 0x555d01, 0x555e01, 0x555f01, 0x556001, 0x556101, 0x556201,
- 0x556301, 0x556401, 0x556501, 0x556601, 0x556701, 0x556801,
- 0x556901, 0x556a01, 0x556b01, 0x556c01, 0x556d01, 0x556e01,
- 0x556f01, 0x557001, 0x557101, 0x557201, 0x557301, 0x557401,
- 0x557501, 0x557601, 0x557701, 0x557801, 0x557901, 0x557a01,
- 0x557b01, 0x557c01, 0x557d01, 0x557e01, 0x557f01}}}}, {pge = {{
- ste = {0x0 <repeats 64 times>}}}} <repeats 51 times>, {pge = {{ste = {
- 0x248001, 0x248101, 0x248201, 0x248301, 0x248401, 0x248501,
- 0x248601, 0x248701, 0x248801, 0x248901, 0x248a01, 0x248b01,
- 0x248c01, 0x248d01, 0x248e01, 0x248f01, 0x249001, 0x249101,
- 0x249201, 0x249301, 0x249401, 0x249501, 0x249601, 0x249701,
- 0x249801, 0x249901, 0x249a01, 0x249b01, 0x249c01, 0x249d01,
- 0x249e01, 0x249f01, 0x24a001, 0x24a101, 0x24a201, 0x24a301,
- 0x24a401, 0x24a501, 0x24a601, 0x24a701, 0x24a801, 0x24a901,
- 0x24aa01, 0x24ab01, 0x24ac01, 0x24ad01, 0x24ae01, 0x24af01,
- 0x24b001, 0x24b101, 0x24b201, 0x24b301, 0x24b401, 0x24b501,
- 0x24b601, 0x24b701, 0x24b801, 0x24b901, 0x24ba01, 0x24bb01,
- 0x24bc01, 0x24bd01, 0x24be01, 0x24bf01}}}}, {pge = {{ste = {
- 0x0 <repeats 64 times>}}}} <repeats 11 times>}
-
- (*) The PTD last used by the instruction TLB miss handler is attached to DAMR4.
- (*) The PTD last used by the data TLB miss handler is attached to DAMR5.
-
- These can be viewed with the _ptd_i and _ptd_d GDB macros:
-
- (gdb) _ptd_d
- $5 = {{pte = 0x0} <repeats 127 times>, {pte = 0x539b01}, {
- pte = 0x0} <repeats 896 times>, {pte = 0x719303}, {pte = 0x6d5303}, {
- pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {
- pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {pte = 0x6a1303}, {
- pte = 0x0} <repeats 12 times>, {pte = 0x709303}, {pte = 0x0}, {pte = 0x0},
- {pte = 0x6fd303}, {pte = 0x6f9303}, {pte = 0x6f5303}, {pte = 0x0}, {
- pte = 0x6ed303}, {pte = 0x531b01}, {pte = 0x50db01}, {
- pte = 0x0} <repeats 13 times>, {pte = 0x5303}, {pte = 0x7f5303}, {
- pte = 0x509b01}, {pte = 0x505b01}, {pte = 0x7c9303}, {pte = 0x7b9303}, {
- pte = 0x7b5303}, {pte = 0x7b1303}, {pte = 0x7ad303}, {pte = 0x0}, {
- pte = 0x0}, {pte = 0x7a1303}, {pte = 0x0}, {pte = 0x795303}, {pte = 0x0}, {
- pte = 0x78d303}, {pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {pte = 0x0}, {
- pte = 0x0}, {pte = 0x775303}, {pte = 0x771303}, {pte = 0x76d303}, {
- pte = 0x0}, {pte = 0x765303}, {pte = 0x7c5303}, {pte = 0x501b01}, {
- pte = 0x4f1b01}, {pte = 0x4edb01}, {pte = 0x0}, {pte = 0x4f9b01}, {
- pte = 0x4fdb01}, {pte = 0x0} <repeats 2992 times>}
diff --git a/Documentation/gpio/00-INDEX b/Documentation/gpio/00-INDEX
index 179beb234f98..17e19a68058f 100644
--- a/Documentation/gpio/00-INDEX
+++ b/Documentation/gpio/00-INDEX
@@ -1,17 +1,4 @@
00-INDEX
- This file
-gpio.txt
- - Introduction to GPIOs and their kernel interfaces
-consumer.txt
- - How to obtain and use GPIOs in a driver
-driver.txt
- - How to write a GPIO driver
-drivers-on-gpio.txt:
- - Drivers in other subsystems that can use GPIO to provide more
- complex functionality.
-board.txt
- - How to assign GPIOs to a consumer device and a function
sysfs.txt
- Information about the GPIO sysfs interface
-gpio-legacy.txt
- - Historical documentation of the deprecated GPIO integer interface
diff --git a/Documentation/gpio/board.txt b/Documentation/gpio/board.txt
deleted file mode 100644
index 659bb19f5b3c..000000000000
--- a/Documentation/gpio/board.txt
+++ /dev/null
@@ -1,176 +0,0 @@
-GPIO Mappings
-=============
-
-This document explains how GPIOs can be assigned to given devices and functions.
-
-Note that it only applies to the new descriptor-based interface. For a
-description of the deprecated integer-based GPIO interface please refer to
-gpio-legacy.txt (actually, there is no real mapping possible with the old
-interface; you just fetch an integer from somewhere and request the
-corresponding GPIO).
-
-All platforms can enable the GPIO library, but if the platform strictly
-requires GPIO functionality to be present, it needs to select GPIOLIB from its
-Kconfig. Then, how GPIOs are mapped depends on what the platform uses to
-describe its hardware layout. Currently, mappings can be defined through device
-tree, ACPI, and platform data.
-
-Device Tree
------------
-GPIOs can easily be mapped to devices and functions in the device tree. The
-exact way to do it depends on the GPIO controller providing the GPIOs, see the
-device tree bindings for your controller.
-
-GPIOs mappings are defined in the consumer device's node, in a property named
-<function>-gpios, where <function> is the function the driver will request
-through gpiod_get(). For example:
-
- foo_device {
- compatible = "acme,foo";
- ...
- led-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>, /* red */
- <&gpio 16 GPIO_ACTIVE_HIGH>, /* green */
- <&gpio 17 GPIO_ACTIVE_HIGH>; /* blue */
-
- power-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
- };
-
-Properties named <function>-gpio are also considered valid and old bindings use
-it but are only supported for compatibility reasons and should not be used for
-newer bindings since it has been deprecated.
-
-This property will make GPIOs 15, 16 and 17 available to the driver under the
-"led" function, and GPIO 1 as the "power" GPIO:
-
- struct gpio_desc *red, *green, *blue, *power;
-
- red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
- green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
- blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
-
- power = gpiod_get(dev, "power", GPIOD_OUT_HIGH);
-
-The led GPIOs will be active high, while the power GPIO will be active low (i.e.
-gpiod_is_active_low(power) will be true).
-
-The second parameter of the gpiod_get() functions, the con_id string, has to be
-the <function>-prefix of the GPIO suffixes ("gpios" or "gpio", automatically
-looked up by the gpiod functions internally) used in the device tree. With above
-"led-gpios" example, use the prefix without the "-" as con_id parameter: "led".
-
-Internally, the GPIO subsystem prefixes the GPIO suffix ("gpios" or "gpio")
-with the string passed in con_id to get the resulting string
-(snprintf(... "%s-%s", con_id, gpio_suffixes[]).
-
-ACPI
-----
-ACPI also supports function names for GPIOs in a similar fashion to DT.
-The above DT example can be converted to an equivalent ACPI description
-with the help of _DSD (Device Specific Data), introduced in ACPI 5.1:
-
- Device (FOO) {
- Name (_CRS, ResourceTemplate () {
- GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
- "\\_SB.GPI0") {15} // red
- GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
- "\\_SB.GPI0") {16} // green
- GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
- "\\_SB.GPI0") {17} // blue
- GpioIo (Exclusive, ..., IoRestrictionOutputOnly,
- "\\_SB.GPI0") {1} // power
- })
-
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {
- "led-gpios",
- Package () {
- ^FOO, 0, 0, 1,
- ^FOO, 1, 0, 1,
- ^FOO, 2, 0, 1,
- }
- },
- Package () {
- "power-gpios",
- Package () {^FOO, 3, 0, 0},
- },
- }
- })
- }
-
-For more information about the ACPI GPIO bindings see
-Documentation/acpi/gpio-properties.txt.
-
-Platform Data
--------------
-Finally, GPIOs can be bound to devices and functions using platform data. Board
-files that desire to do so need to include the following header:
-
- #include <linux/gpio/machine.h>
-
-GPIOs are mapped by the means of tables of lookups, containing instances of the
-gpiod_lookup structure. Two macros are defined to help declaring such mappings:
-
- GPIO_LOOKUP(chip_label, chip_hwnum, con_id, flags)
- GPIO_LOOKUP_IDX(chip_label, chip_hwnum, con_id, idx, flags)
-
-where
-
- - chip_label is the label of the gpiod_chip instance providing the GPIO
- - chip_hwnum is the hardware number of the GPIO within the chip
- - con_id is the name of the GPIO function from the device point of view. It
- can be NULL, in which case it will match any function.
- - idx is the index of the GPIO within the function.
- - flags is defined to specify the following properties:
- * GPIO_ACTIVE_HIGH - GPIO line is active high
- * GPIO_ACTIVE_LOW - GPIO line is active low
- * GPIO_OPEN_DRAIN - GPIO line is set up as open drain
- * GPIO_OPEN_SOURCE - GPIO line is set up as open source
- * GPIO_PERSISTENT - GPIO line is persistent during
- suspend/resume and maintains its value
- * GPIO_TRANSITORY - GPIO line is transitory and may loose its
- electrical state during suspend/resume
-
-In the future, these flags might be extended to support more properties.
-
-Note that GPIO_LOOKUP() is just a shortcut to GPIO_LOOKUP_IDX() where idx = 0.
-
-A lookup table can then be defined as follows, with an empty entry defining its
-end. The 'dev_id' field of the table is the identifier of the device that will
-make use of these GPIOs. It can be NULL, in which case it will be matched for
-calls to gpiod_get() with a NULL device.
-
-struct gpiod_lookup_table gpios_table = {
- .dev_id = "foo.0",
- .table = {
- GPIO_LOOKUP_IDX("gpio.0", 15, "led", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("gpio.0", 16, "led", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("gpio.0", 17, "led", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio.0", 1, "power", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-And the table can be added by the board code as follows:
-
- gpiod_add_lookup_table(&gpios_table);
-
-The driver controlling "foo.0" will then be able to obtain its GPIOs as follows:
-
- struct gpio_desc *red, *green, *blue, *power;
-
- red = gpiod_get_index(dev, "led", 0, GPIOD_OUT_HIGH);
- green = gpiod_get_index(dev, "led", 1, GPIOD_OUT_HIGH);
- blue = gpiod_get_index(dev, "led", 2, GPIOD_OUT_HIGH);
-
- power = gpiod_get(dev, "power", GPIOD_OUT_HIGH);
-
-Since the "led" GPIOs are mapped as active-high, this example will switch their
-signals to 1, i.e. enabling the LEDs. And for the "power" GPIO, which is mapped
-as active-low, its actual signal will be 0 after this code. Contrary to the
-legacy integer GPIO interface, the active-low property is handled during
-mapping and is thus transparent to GPIO consumers.
-
-A set of functions such as gpiod_set_value() is available to work with
-the new descriptor-oriented interface.
diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt
deleted file mode 100644
index d53e5b5cfc9c..000000000000
--- a/Documentation/gpio/consumer.txt
+++ /dev/null
@@ -1,438 +0,0 @@
-GPIO Descriptor Consumer Interface
-==================================
-
-This document describes the consumer interface of the GPIO framework. Note that
-it describes the new descriptor-based interface. For a description of the
-deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
-
-
-Guidelines for GPIOs consumers
-==============================
-
-Drivers that can't work without standard GPIO calls should have Kconfig entries
-that depend on GPIOLIB or select GPIOLIB. The functions that allow a driver to
-obtain and use GPIOs are available by including the following file:
-
- #include <linux/gpio/consumer.h>
-
-There are static inline stubs for all functions in the header file in the case
-where GPIOLIB is disabled. When these stubs are called they will emit
-warnings. These stubs are used for two use cases:
-
-- Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
- the current platform does not enable or select GPIOLIB because we are not
- going to execute the system anyway.
-
-- Truly optional GPIOLIB support - where the driver does not really make use
- of the GPIOs on certain compile-time configurations for certain systems, but
- will use it under other compile-time configurations. In this case the
- consumer must make sure not to call into these functions, or the user will
- be met with console warnings that may be perceived as intimidating.
-
-All the functions that work with the descriptor-based GPIO interface are
-prefixed with gpiod_. The gpio_ prefix is used for the legacy interface. No
-other function in the kernel should use these prefixes. The use of the legacy
-functions is strongly discouraged, new code should use <linux/gpio/consumer.h>
-and descriptors exclusively.
-
-
-Obtaining and Disposing GPIOs
-=============================
-
-With the descriptor-based interface, GPIOs are identified with an opaque,
-non-forgeable handler that must be obtained through a call to one of the
-gpiod_get() functions. Like many other kernel subsystems, gpiod_get() takes the
-device that will use the GPIO and the function the requested GPIO is supposed to
-fulfill:
-
- struct gpio_desc *gpiod_get(struct device *dev, const char *con_id,
- enum gpiod_flags flags)
-
-If a function is implemented by using several GPIOs together (e.g. a simple LED
-device that displays digits), an additional index argument can be specified:
-
- struct gpio_desc *gpiod_get_index(struct device *dev,
- const char *con_id, unsigned int idx,
- enum gpiod_flags flags)
-
-For a more detailed description of the con_id parameter in the DeviceTree case
-see Documentation/gpio/board.txt
-
-The flags parameter is used to optionally specify a direction and initial value
-for the GPIO. Values can be:
-
-* GPIOD_ASIS or 0 to not initialize the GPIO at all. The direction must be set
- later with one of the dedicated functions.
-* GPIOD_IN to initialize the GPIO as input.
-* GPIOD_OUT_LOW to initialize the GPIO as output with a value of 0.
-* GPIOD_OUT_HIGH to initialize the GPIO as output with a value of 1.
-* GPIOD_OUT_LOW_OPEN_DRAIN same as GPIOD_OUT_LOW but also enforce the line
- to be electrically used with open drain.
-* GPIOD_OUT_HIGH_OPEN_DRAIN same as GPIOD_OUT_HIGH but also enforce the line
- to be electrically used with open drain.
-
-The two last flags are used for use cases where open drain is mandatory, such
-as I2C: if the line is not already configured as open drain in the mappings
-(see board.txt), then open drain will be enforced anyway and a warning will be
-printed that the board configuration needs to be updated to match the use case.
-
-Both functions return either a valid GPIO descriptor, or an error code checkable
-with IS_ERR() (they will never return a NULL pointer). -ENOENT will be returned
-if and only if no GPIO has been assigned to the device/function/index triplet,
-other error codes are used for cases where a GPIO has been assigned but an error
-occurred while trying to acquire it. This is useful to discriminate between mere
-errors and an absence of GPIO for optional GPIO parameters. For the common
-pattern where a GPIO is optional, the gpiod_get_optional() and
-gpiod_get_index_optional() functions can be used. These functions return NULL
-instead of -ENOENT if no GPIO has been assigned to the requested function:
-
- struct gpio_desc *gpiod_get_optional(struct device *dev,
- const char *con_id,
- enum gpiod_flags flags)
-
- struct gpio_desc *gpiod_get_index_optional(struct device *dev,
- const char *con_id,
- unsigned int index,
- enum gpiod_flags flags)
-
-Note that gpio_get*_optional() functions (and their managed variants), unlike
-the rest of gpiolib API, also return NULL when gpiolib support is disabled.
-This is helpful to driver authors, since they do not need to special case
--ENOSYS return codes. System integrators should however be careful to enable
-gpiolib on systems that need it.
-
-For a function using multiple GPIOs all of those can be obtained with one call:
-
- struct gpio_descs *gpiod_get_array(struct device *dev,
- const char *con_id,
- enum gpiod_flags flags)
-
-This function returns a struct gpio_descs which contains an array of
-descriptors:
-
- struct gpio_descs {
- unsigned int ndescs;
- struct gpio_desc *desc[];
- }
-
-The following function returns NULL instead of -ENOENT if no GPIOs have been
-assigned to the requested function:
-
- struct gpio_descs *gpiod_get_array_optional(struct device *dev,
- const char *con_id,
- enum gpiod_flags flags)
-
-Device-managed variants of these functions are also defined:
-
- struct gpio_desc *devm_gpiod_get(struct device *dev, const char *con_id,
- enum gpiod_flags flags)
-
- struct gpio_desc *devm_gpiod_get_index(struct device *dev,
- const char *con_id,
- unsigned int idx,
- enum gpiod_flags flags)
-
- struct gpio_desc *devm_gpiod_get_optional(struct device *dev,
- const char *con_id,
- enum gpiod_flags flags)
-
- struct gpio_desc *devm_gpiod_get_index_optional(struct device *dev,
- const char *con_id,
- unsigned int index,
- enum gpiod_flags flags)
-
- struct gpio_descs *devm_gpiod_get_array(struct device *dev,
- const char *con_id,
- enum gpiod_flags flags)
-
- struct gpio_descs *devm_gpiod_get_array_optional(struct device *dev,
- const char *con_id,
- enum gpiod_flags flags)
-
-A GPIO descriptor can be disposed of using the gpiod_put() function:
-
- void gpiod_put(struct gpio_desc *desc)
-
-For an array of GPIOs this function can be used:
-
- void gpiod_put_array(struct gpio_descs *descs)
-
-It is strictly forbidden to use a descriptor after calling these functions.
-It is also not allowed to individually release descriptors (using gpiod_put())
-from an array acquired with gpiod_get_array().
-
-The device-managed variants are, unsurprisingly:
-
- void devm_gpiod_put(struct device *dev, struct gpio_desc *desc)
-
- void devm_gpiod_put_array(struct device *dev, struct gpio_descs *descs)
-
-
-Using GPIOs
-===========
-
-Setting Direction
------------------
-The first thing a driver must do with a GPIO is setting its direction. If no
-direction-setting flags have been given to gpiod_get*(), this is done by
-invoking one of the gpiod_direction_*() functions:
-
- int gpiod_direction_input(struct gpio_desc *desc)
- int gpiod_direction_output(struct gpio_desc *desc, int value)
-
-The return value is zero for success, else a negative errno. It should be
-checked, since the get/set calls don't return errors and since misconfiguration
-is possible. You should normally issue these calls from a task context. However,
-for spinlock-safe GPIOs it is OK to use them before tasking is enabled, as part
-of early board setup.
-
-For output GPIOs, the value provided becomes the initial output value. This
-helps avoid signal glitching during system startup.
-
-A driver can also query the current direction of a GPIO:
-
- int gpiod_get_direction(const struct gpio_desc *desc)
-
-This function returns 0 for output, 1 for input, or an error code in case of error.
-
-Be aware that there is no default direction for GPIOs. Therefore, **using a GPIO
-without setting its direction first is illegal and will result in undefined
-behavior!**
-
-
-Spinlock-Safe GPIO Access
--------------------------
-Most GPIO controllers can be accessed with memory read/write instructions. Those
-don't need to sleep, and can safely be done from inside hard (non-threaded) IRQ
-handlers and similar contexts.
-
-Use the following calls to access GPIOs from an atomic context:
-
- int gpiod_get_value(const struct gpio_desc *desc);
- void gpiod_set_value(struct gpio_desc *desc, int value);
-
-The values are boolean, zero for low, nonzero for high. When reading the value
-of an output pin, the value returned should be what's seen on the pin. That
-won't always match the specified output value, because of issues including
-open-drain signaling and output latencies.
-
-The get/set calls do not return errors because "invalid GPIO" should have been
-reported earlier from gpiod_direction_*(). However, note that not all platforms
-can read the value of output pins; those that can't should always return zero.
-Also, using these calls for GPIOs that can't safely be accessed without sleeping
-(see below) is an error.
-
-
-GPIO Access That May Sleep
---------------------------
-Some GPIO controllers must be accessed using message based buses like I2C or
-SPI. Commands to read or write those GPIO values require waiting to get to the
-head of a queue to transmit a command and get its response. This requires
-sleeping, which can't be done from inside IRQ handlers.
-
-Platforms that support this type of GPIO distinguish them from other GPIOs by
-returning nonzero from this call:
-
- int gpiod_cansleep(const struct gpio_desc *desc)
-
-To access such GPIOs, a different set of accessors is defined:
-
- int gpiod_get_value_cansleep(const struct gpio_desc *desc)
- void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
-
-Accessing such GPIOs requires a context which may sleep, for example a threaded
-IRQ handler, and those accessors must be used instead of spinlock-safe
-accessors without the cansleep() name suffix.
-
-Other than the fact that these accessors might sleep, and will work on GPIOs
-that can't be accessed from hardIRQ handlers, these calls act the same as the
-spinlock-safe calls.
-
-
-The active low and open drain semantics
----------------------------------------
-As a consumer should not have to care about the physical line level, all of the
-gpiod_set_value_xxx() or gpiod_set_array_value_xxx() functions operate with
-the *logical* value. With this they take the active low property into account.
-This means that they check whether the GPIO is configured to be active low,
-and if so, they manipulate the passed value before the physical line level is
-driven.
-
-The same is applicable for open drain or open source output lines: those do not
-actively drive their output high (open drain) or low (open source), they just
-switch their output to a high impedance value. The consumer should not need to
-care. (For details read about open drain in driver.txt.)
-
-With this, all the gpiod_set_(array)_value_xxx() functions interpret the
-parameter "value" as "asserted" ("1") or "de-asserted" ("0"). The physical line
-level will be driven accordingly.
-
-As an example, if the active low property for a dedicated GPIO is set, and the
-gpiod_set_(array)_value_xxx() passes "asserted" ("1"), the physical line level
-will be driven low.
-
-To summarize:
-
-Function (example) line property physical line
-gpiod_set_raw_value(desc, 0); don't care low
-gpiod_set_raw_value(desc, 1); don't care high
-gpiod_set_value(desc, 0); default (active high) low
-gpiod_set_value(desc, 1); default (active high) high
-gpiod_set_value(desc, 0); active low high
-gpiod_set_value(desc, 1); active low low
-gpiod_set_value(desc, 0); default (active high) low
-gpiod_set_value(desc, 1); default (active high) high
-gpiod_set_value(desc, 0); open drain low
-gpiod_set_value(desc, 1); open drain high impedance
-gpiod_set_value(desc, 0); open source high impedance
-gpiod_set_value(desc, 1); open source high
-
-It is possible to override these semantics using the *set_raw/'get_raw functions
-but it should be avoided as much as possible, especially by system-agnostic drivers
-which should not need to care about the actual physical line level and worry about
-the logical value instead.
-
-
-Accessing raw GPIO values
--------------------------
-Consumers exist that need to manage the logical state of a GPIO line, i.e. the value
-their device will actually receive, no matter what lies between it and the GPIO
-line.
-
-The following set of calls ignore the active-low or open drain property of a GPIO and
-work on the raw line value:
-
- int gpiod_get_raw_value(const struct gpio_desc *desc)
- void gpiod_set_raw_value(struct gpio_desc *desc, int value)
- int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
- void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)
- int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
-
-The active low state of a GPIO can also be queried using the following call:
-
- int gpiod_is_active_low(const struct gpio_desc *desc)
-
-Note that these functions should only be used with great moderation; a driver
-should not have to care about the physical line level or open drain semantics.
-
-
-Access multiple GPIOs with a single function call
--------------------------------------------------
-The following functions get or set the values of an array of GPIOs:
-
- int gpiod_get_array_value(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array);
- int gpiod_get_raw_array_value(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array);
- int gpiod_get_array_value_cansleep(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array);
- int gpiod_get_raw_array_value_cansleep(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array);
-
- void gpiod_set_array_value(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
- void gpiod_set_raw_array_value(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
- void gpiod_set_array_value_cansleep(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
- void gpiod_set_raw_array_value_cansleep(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
-
-The array can be an arbitrary set of GPIOs. The functions will try to access
-GPIOs belonging to the same bank or chip simultaneously if supported by the
-corresponding chip driver. In that case a significantly improved performance
-can be expected. If simultaneous access is not possible the GPIOs will be
-accessed sequentially.
-
-The functions take three arguments:
- * array_size - the number of array elements
- * desc_array - an array of GPIO descriptors
- * value_array - an array to store the GPIOs' values (get) or
- an array of values to assign to the GPIOs (set)
-
-The descriptor array can be obtained using the gpiod_get_array() function
-or one of its variants. If the group of descriptors returned by that function
-matches the desired group of GPIOs, those GPIOs can be accessed by simply using
-the struct gpio_descs returned by gpiod_get_array():
-
- struct gpio_descs *my_gpio_descs = gpiod_get_array(...);
- gpiod_set_array_value(my_gpio_descs->ndescs, my_gpio_descs->desc,
- my_gpio_values);
-
-It is also possible to access a completely arbitrary array of descriptors. The
-descriptors may be obtained using any combination of gpiod_get() and
-gpiod_get_array(). Afterwards the array of descriptors has to be setup
-manually before it can be passed to one of the above functions.
-
-Note that for optimal performance GPIOs belonging to the same chip should be
-contiguous within the array of descriptors.
-
-The return value of gpiod_get_array_value() and its variants is 0 on success
-or negative on error. Note the difference to gpiod_get_value(), which returns
-0 or 1 on success to convey the GPIO value. With the array functions, the GPIO
-values are stored in value_array rather than passed back as return value.
-
-
-GPIOs mapped to IRQs
---------------------
-GPIO lines can quite often be used as IRQs. You can get the IRQ number
-corresponding to a given GPIO using the following call:
-
- int gpiod_to_irq(const struct gpio_desc *desc)
-
-It will return an IRQ number, or a negative errno code if the mapping can't be
-done (most likely because that particular GPIO cannot be used as IRQ). It is an
-unchecked error to use a GPIO that wasn't set up as an input using
-gpiod_direction_input(), or to use an IRQ number that didn't originally come
-from gpiod_to_irq(). gpiod_to_irq() is not allowed to sleep.
-
-Non-error values returned from gpiod_to_irq() can be passed to request_irq() or
-free_irq(). They will often be stored into IRQ resources for platform devices,
-by the board-specific initialization code. Note that IRQ trigger options are
-part of the IRQ interface, e.g. IRQF_TRIGGER_FALLING, as are system wakeup
-capabilities.
-
-
-GPIOs and ACPI
-==============
-
-On ACPI systems, GPIOs are described by GpioIo()/GpioInt() resources listed by
-the _CRS configuration objects of devices. Those resources do not provide
-connection IDs (names) for GPIOs, so it is necessary to use an additional
-mechanism for this purpose.
-
-Systems compliant with ACPI 5.1 or newer may provide a _DSD configuration object
-which, among other things, may be used to provide connection IDs for specific
-GPIOs described by the GpioIo()/GpioInt() resources in _CRS. If that is the
-case, it will be handled by the GPIO subsystem automatically. However, if the
-_DSD is not present, the mappings between GpioIo()/GpioInt() resources and GPIO
-connection IDs need to be provided by device drivers.
-
-For details refer to Documentation/acpi/gpio-properties.txt
-
-
-Interacting With the Legacy GPIO Subsystem
-==========================================
-Many kernel subsystems still handle GPIOs using the legacy integer-based
-interface. Although it is strongly encouraged to upgrade them to the safer
-descriptor-based API, the following two functions allow you to convert a GPIO
-descriptor into the GPIO integer namespace and vice-versa:
-
- int desc_to_gpio(const struct gpio_desc *desc)
- struct gpio_desc *gpio_to_desc(unsigned gpio)
-
-The GPIO number returned by desc_to_gpio() can be safely used as long as the
-GPIO descriptor has not been freed. All the same, a GPIO number passed to
-gpio_to_desc() must have been properly acquired, and usage of the returned GPIO
-descriptor is only possible after the GPIO number has been released.
-
-Freeing a GPIO obtained by one API with the other API is forbidden and an
-unchecked error.
diff --git a/Documentation/gpio/driver.txt b/Documentation/gpio/driver.txt
deleted file mode 100644
index 3392a0fd4c23..000000000000
--- a/Documentation/gpio/driver.txt
+++ /dev/null
@@ -1,427 +0,0 @@
-GPIO Descriptor Driver Interface
-================================
-
-This document serves as a guide for GPIO chip drivers writers. Note that it
-describes the new descriptor-based interface. For a description of the
-deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
-
-Each GPIO controller driver needs to include the following header, which defines
-the structures used to define a GPIO driver:
-
- #include <linux/gpio/driver.h>
-
-
-Internal Representation of GPIOs
-================================
-
-Inside a GPIO driver, individual GPIOs are identified by their hardware number,
-which is a unique number between 0 and n, n being the number of GPIOs managed by
-the chip. This number is purely internal: the hardware number of a particular
-GPIO descriptor is never made visible outside of the driver.
-
-On top of this internal number, each GPIO also need to have a global number in
-the integer GPIO namespace so that it can be used with the legacy GPIO
-interface. Each chip must thus have a "base" number (which can be automatically
-assigned), and for each GPIO the global number will be (base + hardware number).
-Although the integer representation is considered deprecated, it still has many
-users and thus needs to be maintained.
-
-So for example one platform could use numbers 32-159 for GPIOs, with a
-controller defining 128 GPIOs at a "base" of 32 ; while another platform uses
-numbers 0..63 with one set of GPIO controllers, 64-79 with another type of GPIO
-controller, and on one particular board 80-95 with an FPGA. The numbers need not
-be contiguous; either of those platforms could also use numbers 2000-2063 to
-identify GPIOs in a bank of I2C GPIO expanders.
-
-
-Controller Drivers: gpio_chip
-=============================
-
-In the gpiolib framework each GPIO controller is packaged as a "struct
-gpio_chip" (see linux/gpio/driver.h for its complete definition) with members
-common to each controller of that type:
-
- - methods to establish GPIO line direction
- - methods used to access GPIO line values
- - method to set electrical configuration to a a given GPIO line
- - method to return the IRQ number associated to a given GPIO line
- - flag saying whether calls to its methods may sleep
- - optional line names array to identify lines
- - optional debugfs dump method (showing extra state like pullup config)
- - optional base number (will be automatically assigned if omitted)
- - optional label for diagnostics and GPIO chip mapping using platform data
-
-The code implementing a gpio_chip should support multiple instances of the
-controller, possibly using the driver model. That code will configure each
-gpio_chip and issue gpiochip_add[_data]() or devm_gpiochip_add_data().
-Removing a GPIO controller should be rare; use [devm_]gpiochip_remove() when
-it is unavoidable.
-
-Often a gpio_chip is part of an instance-specific structure with states not
-exposed by the GPIO interfaces, such as addressing, power management, and more.
-Chips such as audio codecs will have complex non-GPIO states.
-
-Any debugfs dump method should normally ignore signals which haven't been
-requested as GPIOs. They can use gpiochip_is_requested(), which returns either
-NULL or the label associated with that GPIO when it was requested.
-
-RT_FULL: the GPIO driver should not use spinlock_t or any sleepable APIs
-(like PM runtime) in its gpio_chip implementation (.get/.set and direction
-control callbacks) if it is expected to call GPIO APIs from atomic context
-on -RT (inside hard IRQ handlers and similar contexts). Normally this should
-not be required.
-
-
-GPIO electrical configuration
------------------------------
-
-GPIOs can be configured for several electrical modes of operation by using the
-.set_config() callback. Currently this API supports setting debouncing and
-single-ended modes (open drain/open source). These settings are described
-below.
-
-The .set_config() callback uses the same enumerators and configuration
-semantics as the generic pin control drivers. This is not a coincidence: it is
-possible to assign the .set_config() to the function gpiochip_generic_config()
-which will result in pinctrl_gpio_set_config() being called and eventually
-ending up in the pin control back-end "behind" the GPIO controller, usually
-closer to the actual pins. This way the pin controller can manage the below
-listed GPIO configurations.
-
-If a pin controller back-end is used, the GPIO controller or hardware
-description needs to provide "GPIO ranges" mapping the GPIO line offsets to pin
-numbers on the pin controller so they can properly cross-reference each other.
-
-
-GPIOs with debounce support
----------------------------
-
-Debouncing is a configuration set to a pin indicating that it is connected to
-a mechanical switch or button, or similar that may bounce. Bouncing means the
-line is pulled high/low quickly at very short intervals for mechanical
-reasons. This can result in the value being unstable or irqs fireing repeatedly
-unless the line is debounced.
-
-Debouncing in practice involves setting up a timer when something happens on
-the line, wait a little while and then sample the line again, so see if it
-still has the same value (low or high). This could also be repeated by a clever
-state machine, waiting for a line to become stable. In either case, it sets
-a certain number of milliseconds for debouncing, or just "on/off" if that time
-is not configurable.
-
-
-GPIOs with open drain/source support
-------------------------------------
-
-Open drain (CMOS) or open collector (TTL) means the line is not actively driven
-high: instead you provide the drain/collector as output, so when the transistor
-is not open, it will present a high-impedance (tristate) to the external rail.
-
-
- CMOS CONFIGURATION TTL CONFIGURATION
-
- ||--- out +--- out
- in ----|| |/
- ||--+ in ----|
- | |\
- GND GND
-
-This configuration is normally used as a way to achieve one of two things:
-
-- Level-shifting: to reach a logical level higher than that of the silicon
- where the output resides.
-
-- inverse wire-OR on an I/O line, for example a GPIO line, making it possible
- for any driving stage on the line to drive it low even if any other output
- to the same line is simultaneously driving it high. A special case of this
- is driving the SCL and SCA lines of an I2C bus, which is by definition a
- wire-OR bus.
-
-Both usecases require that the line be equipped with a pull-up resistor. This
-resistor will make the line tend to high level unless one of the transistors on
-the rail actively pulls it down.
-
-The level on the line will go as high as the VDD on the pull-up resistor, which
-may be higher than the level supported by the transistor, achieveing a
-level-shift to the higher VDD.
-
-Integrated electronics often have an output driver stage in the form of a CMOS
-"totem-pole" with one N-MOS and one P-MOS transistor where one of them drives
-the line high and one of them drives the line low. This is called a push-pull
-output. The "totem-pole" looks like so:
-
- VDD
- |
- OD ||--+
- +--/ ---o|| P-MOS-FET
- | ||--+
-IN --+ +----- out
- | ||--+
- +--/ ----|| N-MOS-FET
- OS ||--+
- |
- GND
-
-The desired output signal (e.g. coming directly from some GPIO output register)
-arrives at IN. The switches named "OD" and "OS" are normally closed, creating
-a push-pull circuit.
-
-Consider the little "switches" named "OD" and "OS" that enable/disable the
-P-MOS or N-MOS transistor right after the split of the input. As you can see,
-either transistor will go totally numb if this switch is open. The totem-pole
-is then halved and give high impedance instead of actively driving the line
-high or low respectively. That is usually how software-controlled open
-drain/source works.
-
-Some GPIO hardware come in open drain / open source configuration. Some are
-hard-wired lines that will only support open drain or open source no matter
-what: there is only one transistor there. Some are software-configurable:
-by flipping a bit in a register the output can be configured as open drain
-or open source, in practice by flicking open the switches labeled "OD" and "OS"
-in the drawing above.
-
-By disabling the P-MOS transistor, the output can be driven between GND and
-high impedance (open drain), and by disabling the N-MOS transistor, the output
-can be driven between VDD and high impedance (open source). In the first case,
-a pull-up resistor is needed on the outgoing rail to complete the circuit, and
-in the second case, a pull-down resistor is needed on the rail.
-
-Hardware that supports open drain or open source or both, can implement a
-special callback in the gpio_chip: .set_config() that takes a generic
-pinconf packed value telling whether to configure the line as open drain,
-open source or push-pull. This will happen in response to the
-GPIO_OPEN_DRAIN or GPIO_OPEN_SOURCE flag set in the machine file, or coming
-from other hardware descriptions.
-
-If this state can not be configured in hardware, i.e. if the GPIO hardware does
-not support open drain/open source in hardware, the GPIO library will instead
-use a trick: when a line is set as output, if the line is flagged as open
-drain, and the IN output value is low, it will be driven low as usual. But
-if the IN output value is set to high, it will instead *NOT* be driven high,
-instead it will be switched to input, as input mode is high impedance, thus
-achieveing an "open drain emulation" of sorts: electrically the behaviour will
-be identical, with the exception of possible hardware glitches when switching
-the mode of the line.
-
-For open source configuration the same principle is used, just that instead
-of actively driving the line low, it is set to input.
-
-
-GPIO drivers providing IRQs
----------------------------
-It is custom that GPIO drivers (GPIO chips) are also providing interrupts,
-most often cascaded off a parent interrupt controller, and in some special
-cases the GPIO logic is melded with a SoC's primary interrupt controller.
-
-The IRQ portions of the GPIO block are implemented using an irqchip, using
-the header <linux/irq.h>. So basically such a driver is utilizing two sub-
-systems simultaneously: gpio and irq.
-
-RT_FULL: a realtime compliant GPIO driver should not use spinlock_t or any
-sleepable APIs (like PM runtime) as part of its irq_chip implementation.
-- spinlock_t should be replaced with raw_spinlock_t [1].
-- If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
- and .irq_bus_unlock() callbacks, as these are the only slowpath callbacks
- on an irqchip. Create the callbacks if needed [2].
-
-GPIO irqchips usually fall in one of two categories:
-
-* CHAINED GPIO irqchips: these are usually the type that is embedded on
- an SoC. This means that there is a fast IRQ flow handler for the GPIOs that
- gets called in a chain from the parent IRQ handler, most typically the
- system interrupt controller. This means that the GPIO irqchip handler will
- be called immediately from the parent irqchip, while holding the IRQs
- disabled. The GPIO irqchip will then end up calling something like this
- sequence in its interrupt handler:
-
- static irqreturn_t foo_gpio_irq(int irq, void *data)
- chained_irq_enter(...);
- generic_handle_irq(...);
- chained_irq_exit(...);
-
- Chained GPIO irqchips typically can NOT set the .can_sleep flag on
- struct gpio_chip, as everything happens directly in the callbacks: no
- slow bus traffic like I2C can be used.
-
- RT_FULL: Note, chained IRQ handlers will not be forced threaded on -RT.
- As result, spinlock_t or any sleepable APIs (like PM runtime) can't be used
- in chained IRQ handler.
- If required (and if it can't be converted to the nested threaded GPIO irqchip)
- a chained IRQ handler can be converted to generic irq handler and this way
- it will be a threaded IRQ handler on -RT and a hard IRQ handler on non-RT
- (for example, see [3]).
- Know W/A: The generic_handle_irq() is expected to be called with IRQ disabled,
- so the IRQ core will complain if it is called from an IRQ handler which is
- forced to a thread. The "fake?" raw lock can be used to W/A this problem:
-
- raw_spinlock_t wa_lock;
- static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
- unsigned long wa_lock_flags;
- raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
- generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
- raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
-
-* GENERIC CHAINED GPIO irqchips: these are the same as "CHAINED GPIO irqchips",
- but chained IRQ handlers are not used. Instead GPIO IRQs dispatching is
- performed by generic IRQ handler which is configured using request_irq().
- The GPIO irqchip will then end up calling something like this sequence in
- its interrupt handler:
-
- static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
- for each detected GPIO IRQ
- generic_handle_irq(...);
-
- RT_FULL: Such kind of handlers will be forced threaded on -RT, as result IRQ
- core will complain that generic_handle_irq() is called with IRQ enabled and
- the same W/A as for "CHAINED GPIO irqchips" can be applied.
-
-* NESTED THREADED GPIO irqchips: these are off-chip GPIO expanders and any
- other GPIO irqchip residing on the other side of a sleeping bus. Of course
- such drivers that need slow bus traffic to read out IRQ status and similar,
- traffic which may in turn incur other IRQs to happen, cannot be handled
- in a quick IRQ handler with IRQs disabled. Instead they need to spawn a
- thread and then mask the parent IRQ line until the interrupt is handled
- by the driver. The hallmark of this driver is to call something like
- this in its interrupt handler:
-
- static irqreturn_t foo_gpio_irq(int irq, void *data)
- ...
- handle_nested_irq(irq);
-
- The hallmark of threaded GPIO irqchips is that they set the .can_sleep
- flag on struct gpio_chip to true, indicating that this chip may sleep
- when accessing the GPIOs.
-
-To help out in handling the set-up and management of GPIO irqchips and the
-associated irqdomain and resource allocation callbacks, the gpiolib has
-some helpers that can be enabled by selecting the GPIOLIB_IRQCHIP Kconfig
-symbol:
-
-* gpiochip_irqchip_add(): adds a chained irqchip to a gpiochip. It will pass
- the struct gpio_chip* for the chip to all IRQ callbacks, so the callbacks
- need to embed the gpio_chip in its state container and obtain a pointer
- to the container using container_of().
- (See Documentation/driver-model/design-patterns.txt)
-
-* gpiochip_irqchip_add_nested(): adds a nested irqchip to a gpiochip.
- Apart from that it works exactly like the chained irqchip.
-
-* gpiochip_set_chained_irqchip(): sets up a chained irq handler for a
- gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler
- data. (Notice handler data, since the irqchip data is likely used by the
- parent irqchip!).
-
-* gpiochip_set_nested_irqchip(): sets up a nested irq handler for a
- gpio_chip from a parent IRQ. As the parent IRQ has usually been
- explicitly requested by the driver, this does very little more than
- mark all the child IRQs as having the other IRQ as parent.
-
-If there is a need to exclude certain GPIOs from the IRQ domain, you can
-set .irq.need_valid_mask of the gpiochip before gpiochip_add_data() is
-called. This allocates an .irq.valid_mask with as many bits set as there
-are GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this
-mask. The mask must be filled in before gpiochip_irqchip_add() or
-gpiochip_irqchip_add_nested() is called.
-
-To use the helpers please keep the following in mind:
-
-- Make sure to assign all relevant members of the struct gpio_chip so that
- the irqchip can initialize. E.g. .dev and .can_sleep shall be set up
- properly.
-
-- Nominally set all handlers to handle_bad_irq() in the setup call and pass
- handle_bad_irq() as flow handler parameter in gpiochip_irqchip_add() if it is
- expected for GPIO driver that irqchip .set_type() callback have to be called
- before using/enabling GPIO IRQ. Then set the handler to handle_level_irq()
- and/or handle_edge_irq() in the irqchip .set_type() callback depending on
- what your controller supports.
-
-It is legal for any IRQ consumer to request an IRQ from any irqchip no matter
-if that is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
-irq_chip are orthogonal, and offering their services independent of each
-other.
-
-gpiod_to_irq() is just a convenience function to figure out the IRQ for a
-certain GPIO line and should not be relied upon to have been called before
-the IRQ is used.
-
-So always prepare the hardware and make it ready for action in respective
-callbacks from the GPIO and irqchip APIs. Do not rely on gpiod_to_irq() having
-been called first.
-
-This orthogonality leads to ambiguities that we need to solve: if there is
-competition inside the subsystem which side is using the resource (a certain
-GPIO line and register for example) it needs to deny certain operations and
-keep track of usage inside of the gpiolib subsystem. This is why the API
-below exists.
-
-
-Locking IRQ usage
------------------
-Input GPIOs can be used as IRQ signals. When this happens, a driver is requested
-to mark the GPIO as being used as an IRQ:
-
- int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
-
-This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
-is released:
-
- void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
-
-When implementing an irqchip inside a GPIO driver, these two functions should
-typically be called in the .startup() and .shutdown() callbacks from the
-irqchip.
-
-When using the gpiolib irqchip helpers, these callback are automatically
-assigned.
-
-Real-Time compliance for GPIO IRQ chips
----------------------------------------
-
-Any provider of irqchips needs to be carefully tailored to support Real Time
-preemption. It is desirable that all irqchips in the GPIO subsystem keep this
-in mind and does the proper testing to assure they are real time-enabled.
-So, pay attention on above " RT_FULL:" notes, please.
-The following is a checklist to follow when preparing a driver for real
-time-compliance:
-
-- ensure spinlock_t is not used as part irq_chip implementation;
-- ensure that sleepable APIs are not used as part irq_chip implementation.
- If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
- and .irq_bus_unlock() callbacks;
-- Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
- from chained IRQ handler;
-- Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
- apply corresponding W/A;
-- Chained GPIO irqchips: get rid of chained IRQ handler and use generic irq
- handler if possible :)
-- regmap_mmio: Sry, but you are in trouble :( if MMIO regmap is used as for
- GPIO IRQ chip implementation;
-- Test your driver with the appropriate in-kernel real time test cases for both
- level and edge IRQs.
-
-
-Requesting self-owned GPIO pins
--------------------------------
-
-Sometimes it is useful to allow a GPIO chip driver to request its own GPIO
-descriptors through the gpiolib API. Using gpio_request() for this purpose
-does not help since it pins the module to the kernel forever (it calls
-try_module_get()). A GPIO driver can use the following functions instead
-to request and free descriptors without being pinned to the kernel forever.
-
- struct gpio_desc *gpiochip_request_own_desc(struct gpio_desc *desc,
- const char *label)
-
- void gpiochip_free_own_desc(struct gpio_desc *desc)
-
-Descriptors requested with gpiochip_request_own_desc() must be released with
-gpiochip_free_own_desc().
-
-These functions must be used with care since they do not affect module use
-count. Do not use the functions to request gpio descriptors not owned by the
-calling driver.
-
-[1] http://www.spinics.net/lists/linux-omap/msg120425.html
-[2] https://lkml.org/lkml/2015/9/25/494
-[3] https://lkml.org/lkml/2015/9/25/495
diff --git a/Documentation/gpio/drivers-on-gpio.txt b/Documentation/gpio/drivers-on-gpio.txt
deleted file mode 100644
index a2ccbab12eb7..000000000000
--- a/Documentation/gpio/drivers-on-gpio.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Subsystem drivers using GPIO
-============================
-
-Note that standard kernel drivers exist for common GPIO tasks and will provide
-the right in-kernel and userspace APIs/ABIs for the job, and that these
-drivers can quite easily interconnect with other kernel subsystems using
-hardware descriptions such as device tree or ACPI:
-
-- leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
- lines, giving you the LED sysfs interface
-
-- ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
- i.e. a LED will turn on/off in response to a GPIO line going high or low
- (and that LED may in turn use the leds-gpio as per above).
-
-- gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
- can generate interrupts in response to a key press. Also supports debounce.
-
-- gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
- GPIO line cannot generate interrupts, so it needs to be periodically polled
- by a timer.
-
-- gpio_mouse: drivers/input/mouse/gpio_mouse.c is used to provide a mouse with
- up to three buttons by simply using GPIOs and no mouse port. You can cut the
- mouse cable and connect the wires to GPIO lines or solder a mouse connector
- to the lines for a more permanent solution of this type.
-
-- gpio-beeper: drivers/input/misc/gpio-beeper.c is used to provide a beep from
- an external speaker connected to a GPIO line.
-
-- extcon-gpio: drivers/extcon/extcon-gpio.c is used when you need to read an
- external connector status, such as a headset line for an audio driver or an
- HDMI connector. It will provide a better userspace sysfs interface than GPIO.
-
-- restart-gpio: drivers/power/reset/gpio-restart.c is used to restart/reboot
- the system by pulling a GPIO line and will register a restart handler so
- userspace can issue the right system call to restart the system.
-
-- poweroff-gpio: drivers/power/reset/gpio-poweroff.c is used to power the
- system down by pulling a GPIO line and will register a pm_power_off()
- callback so that userspace can issue the right system call to power down the
- system.
-
-- gpio-gate-clock: drivers/clk/clk-gpio.c is used to control a gated clock
- (off/on) that uses a GPIO, and integrated with the clock subsystem.
-
-- i2c-gpio: drivers/i2c/busses/i2c-gpio.c is used to drive an I2C bus
- (two wires, SDA and SCL lines) by hammering (bitbang) two GPIO lines. It will
- appear as any other I2C bus to the system and makes it possible to connect
- drivers for the I2C devices on the bus like any other I2C bus driver.
-
-- spi_gpio: drivers/spi/spi-gpio.c is used to drive an SPI bus (variable number
- of wires, at least SCK and optionally MISO, MOSI and chip select lines) using
- GPIO hammering (bitbang). It will appear as any other SPI bus on the system
- and makes it possible to connect drivers for SPI devices on the bus like
- any other SPI bus driver. For example any MMC/SD card can then be connected
- to this SPI by using the mmc_spi host from the MMC/SD card subsystem.
-
-- w1-gpio: drivers/w1/masters/w1-gpio.c is used to drive a one-wire bus using
- a GPIO line, integrating with the W1 subsystem and handling devices on
- the bus like any other W1 device.
-
-- gpio-fan: drivers/hwmon/gpio-fan.c is used to control a fan for cooling the
- system, connected to a GPIO line (and optionally a GPIO alarm line),
- presenting all the right in-kernel and sysfs interfaces to make your system
- not overheat.
-
-- gpio-regulator: drivers/regulator/gpio-regulator.c is used to control a
- regulator providing a certain voltage by pulling a GPIO line, integrating
- with the regulator subsystem and giving you all the right interfaces.
-
-- gpio-wdt: drivers/watchdog/gpio_wdt.c is used to provide a watchdog timer
- that will periodically "ping" a hardware connected to a GPIO line by toggling
- it from 1-to-0-to-1. If that hardware does not receive its "ping"
- periodically, it will reset the system.
-
-- gpio-nand: drivers/mtd/nand/gpio.c is used to connect a NAND flash chip to
- a set of simple GPIO lines: RDY, NCE, ALE, CLE, NWP. It interacts with the
- NAND flash MTD subsystem and provides chip access and partition parsing like
- any other NAND driving hardware.
-
-- ps2-gpio: drivers/input/serio/ps2-gpio.c is used to drive a PS/2 (IBM) serio
- bus, data and clock line, by bit banging two GPIO lines. It will appear as
- any other serio bus to the system and makes it possible to connect drivers
- for e.g. keyboards and other PS/2 protocol based devices.
-
-Apart from this there are special GPIO drivers in subsystems like MMC/SD to
-read card detect and write protect GPIO lines, and in the TTY serial subsystem
-to emulate MCTRL (modem control) signals CTS/RTS by using two GPIO lines. The
-MTD NOR flash has add-ons for extra GPIO lines too, though the address bus is
-usually connected directly to the flash.
-
-Use those instead of talking directly to the GPIOs using sysfs; they integrate
-with kernel frameworks better than your userspace code could. Needless to say,
-just using the appropriate kernel drivers will simplify and speed up your
-embedded hacking in particular by providing ready-made components.
diff --git a/Documentation/gpio/gpio-legacy.txt b/Documentation/gpio/gpio-legacy.txt
deleted file mode 100644
index 8356d0e78f67..000000000000
--- a/Documentation/gpio/gpio-legacy.txt
+++ /dev/null
@@ -1,758 +0,0 @@
-GPIO Interfaces
-
-This provides an overview of GPIO access conventions on Linux.
-
-These calls use the gpio_* naming prefix. No other calls should use that
-prefix, or the related __gpio_* prefix.
-
-
-What is a GPIO?
-===============
-A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
-digital signal. They are provided from many kinds of chip, and are familiar
-to Linux developers working with embedded and custom hardware. Each GPIO
-represents a bit connected to a particular pin, or "ball" on Ball Grid Array
-(BGA) packages. Board schematics show which external hardware connects to
-which GPIOs. Drivers can be written generically, so that board setup code
-passes such pin configuration data to drivers.
-
-System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
-non-dedicated pin can be configured as a GPIO; and most chips have at least
-several dozen of them. Programmable logic devices (like FPGAs) can easily
-provide GPIOs; multifunction chips like power managers, and audio codecs
-often have a few such pins to help with pin scarcity on SOCs; and there are
-also "GPIO Expander" chips that connect using the I2C or SPI serial busses.
-Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
-firmware knowing how they're used).
-
-The exact capabilities of GPIOs vary between systems. Common options:
-
- - Output values are writable (high=1, low=0). Some chips also have
- options about how that value is driven, so that for example only one
- value might be driven ... supporting "wire-OR" and similar schemes
- for the other value (notably, "open drain" signaling).
-
- - Input values are likewise readable (1, 0). Some chips support readback
- of pins configured as "output", which is very useful in such "wire-OR"
- cases (to support bidirectional signaling). GPIO controllers may have
- input de-glitch/debounce logic, sometimes with software controls.
-
- - Inputs can often be used as IRQ signals, often edge triggered but
- sometimes level triggered. Such IRQs may be configurable as system
- wakeup events, to wake the system from a low power state.
-
- - Usually a GPIO will be configurable as either input or output, as needed
- by different product boards; single direction ones exist too.
-
- - Most GPIOs can be accessed while holding spinlocks, but those accessed
- through a serial bus normally can't. Some systems support both types.
-
-On a given board each GPIO is used for one specific purpose like monitoring
-MMC/SD card insertion/removal, detecting card writeprotect status, driving
-a LED, configuring a transceiver, bitbanging a serial bus, poking a hardware
-watchdog, sensing a switch, and so on.
-
-
-GPIO conventions
-================
-Note that this is called a "convention" because you don't need to do it this
-way, and it's no crime if you don't. There **are** cases where portability
-is not the main issue; GPIOs are often used for the kind of board-specific
-glue logic that may even change between board revisions, and can't ever be
-used on a board that's wired differently. Only least-common-denominator
-functionality can be very portable. Other features are platform-specific,
-and that can be critical for glue logic.
-
-Plus, this doesn't require any implementation framework, just an interface.
-One platform might implement it as simple inline functions accessing chip
-registers; another might implement it by delegating through abstractions
-used for several very different kinds of GPIO controller. (There is some
-optional code supporting such an implementation strategy, described later
-in this document, but drivers acting as clients to the GPIO interface must
-not care how it's implemented.)
-
-That said, if the convention is supported on their platform, drivers should
-use it when possible. Platforms must select GPIOLIB if GPIO functionality
-is strictly required. Drivers that can't work without
-standard GPIO calls should have Kconfig entries which depend on GPIOLIB. The
-GPIO calls are available, either as "real code" or as optimized-away stubs,
-when drivers use the include file:
-
- #include <linux/gpio.h>
-
-If you stick to this convention then it'll be easier for other developers to
-see what your code is doing, and help maintain it.
-
-Note that these operations include I/O barriers on platforms which need to
-use them; drivers don't need to add them explicitly.
-
-
-Identifying GPIOs
------------------
-GPIOs are identified by unsigned integers in the range 0..MAX_INT. That
-reserves "negative" numbers for other purposes like marking signals as
-"not available on this board", or indicating faults. Code that doesn't
-touch the underlying hardware treats these integers as opaque cookies.
-
-Platforms define how they use those integers, and usually #define symbols
-for the GPIO lines so that board-specific setup code directly corresponds
-to the relevant schematics. In contrast, drivers should only use GPIO
-numbers passed to them from that setup code, using platform_data to hold
-board-specific pin configuration data (along with other board specific
-data they need). That avoids portability problems.
-
-So for example one platform uses numbers 32-159 for GPIOs; while another
-uses numbers 0..63 with one set of GPIO controllers, 64-79 with another
-type of GPIO controller, and on one particular board 80-95 with an FPGA.
-The numbers need not be contiguous; either of those platforms could also
-use numbers 2000-2063 to identify GPIOs in a bank of I2C GPIO expanders.
-
-If you want to initialize a structure with an invalid GPIO number, use
-some negative number (perhaps "-EINVAL"); that will never be valid. To
-test if such number from such a structure could reference a GPIO, you
-may use this predicate:
-
- int gpio_is_valid(int number);
-
-A number that's not valid will be rejected by calls which may request
-or free GPIOs (see below). Other numbers may also be rejected; for
-example, a number might be valid but temporarily unused on a given board.
-
-Whether a platform supports multiple GPIO controllers is a platform-specific
-implementation issue, as are whether that support can leave "holes" in the space
-of GPIO numbers, and whether new controllers can be added at runtime. Such issues
-can affect things including whether adjacent GPIO numbers are both valid.
-
-Using GPIOs
------------
-The first thing a system should do with a GPIO is allocate it, using
-the gpio_request() call; see later.
-
-One of the next things to do with a GPIO, often in board setup code when
-setting up a platform_device using the GPIO, is mark its direction:
-
- /* set as input or output, returning 0 or negative errno */
- int gpio_direction_input(unsigned gpio);
- int gpio_direction_output(unsigned gpio, int value);
-
-The return value is zero for success, else a negative errno. It should
-be checked, since the get/set calls don't have error returns and since
-misconfiguration is possible. You should normally issue these calls from
-a task context. However, for spinlock-safe GPIOs it's OK to use them
-before tasking is enabled, as part of early board setup.
-
-For output GPIOs, the value provided becomes the initial output value.
-This helps avoid signal glitching during system startup.
-
-For compatibility with legacy interfaces to GPIOs, setting the direction
-of a GPIO implicitly requests that GPIO (see below) if it has not been
-requested already. That compatibility is being removed from the optional
-gpiolib framework.
-
-Setting the direction can fail if the GPIO number is invalid, or when
-that particular GPIO can't be used in that mode. It's generally a bad
-idea to rely on boot firmware to have set the direction correctly, since
-it probably wasn't validated to do more than boot Linux. (Similarly,
-that board setup code probably needs to multiplex that pin as a GPIO,
-and configure pullups/pulldowns appropriately.)
-
-
-Spinlock-Safe GPIO access
--------------------------
-Most GPIO controllers can be accessed with memory read/write instructions.
-Those don't need to sleep, and can safely be done from inside hard
-(nonthreaded) IRQ handlers and similar contexts.
-
-Use the following calls to access such GPIOs,
-for which gpio_cansleep() will always return false (see below):
-
- /* GPIO INPUT: return zero or nonzero */
- int gpio_get_value(unsigned gpio);
-
- /* GPIO OUTPUT */
- void gpio_set_value(unsigned gpio, int value);
-
-The values are boolean, zero for low, nonzero for high. When reading the
-value of an output pin, the value returned should be what's seen on the
-pin ... that won't always match the specified output value, because of
-issues including open-drain signaling and output latencies.
-
-The get/set calls have no error returns because "invalid GPIO" should have
-been reported earlier from gpio_direction_*(). However, note that not all
-platforms can read the value of output pins; those that can't should always
-return zero. Also, using these calls for GPIOs that can't safely be accessed
-without sleeping (see below) is an error.
-
-Platform-specific implementations are encouraged to optimize the two
-calls to access the GPIO value in cases where the GPIO number (and for
-output, value) are constant. It's normal for them to need only a couple
-of instructions in such cases (reading or writing a hardware register),
-and not to need spinlocks. Such optimized calls can make bitbanging
-applications a lot more efficient (in both space and time) than spending
-dozens of instructions on subroutine calls.
-
-
-GPIO access that may sleep
---------------------------
-Some GPIO controllers must be accessed using message based busses like I2C
-or SPI. Commands to read or write those GPIO values require waiting to
-get to the head of a queue to transmit a command and get its response.
-This requires sleeping, which can't be done from inside IRQ handlers.
-
-Platforms that support this type of GPIO distinguish them from other GPIOs
-by returning nonzero from this call (which requires a valid GPIO number,
-which should have been previously allocated with gpio_request):
-
- int gpio_cansleep(unsigned gpio);
-
-To access such GPIOs, a different set of accessors is defined:
-
- /* GPIO INPUT: return zero or nonzero, might sleep */
- int gpio_get_value_cansleep(unsigned gpio);
-
- /* GPIO OUTPUT, might sleep */
- void gpio_set_value_cansleep(unsigned gpio, int value);
-
-
-Accessing such GPIOs requires a context which may sleep, for example
-a threaded IRQ handler, and those accessors must be used instead of
-spinlock-safe accessors without the cansleep() name suffix.
-
-Other than the fact that these accessors might sleep, and will work
-on GPIOs that can't be accessed from hardIRQ handlers, these calls act
-the same as the spinlock-safe calls.
-
- ** IN ADDITION ** calls to setup and configure such GPIOs must be made
-from contexts which may sleep, since they may need to access the GPIO
-controller chip too: (These setup calls are usually made from board
-setup or driver probe/teardown code, so this is an easy constraint.)
-
- gpio_direction_input()
- gpio_direction_output()
- gpio_request()
-
-## gpio_request_one()
-## gpio_request_array()
-## gpio_free_array()
-
- gpio_free()
- gpio_set_debounce()
-
-
-
-Claiming and Releasing GPIOs
-----------------------------
-To help catch system configuration errors, two calls are defined.
-
- /* request GPIO, returning 0 or negative errno.
- * non-null labels may be useful for diagnostics.
- */
- int gpio_request(unsigned gpio, const char *label);
-
- /* release previously-claimed GPIO */
- void gpio_free(unsigned gpio);
-
-Passing invalid GPIO numbers to gpio_request() will fail, as will requesting
-GPIOs that have already been claimed with that call. The return value of
-gpio_request() must be checked. You should normally issue these calls from
-a task context. However, for spinlock-safe GPIOs it's OK to request GPIOs
-before tasking is enabled, as part of early board setup.
-
-These calls serve two basic purposes. One is marking the signals which
-are actually in use as GPIOs, for better diagnostics; systems may have
-several hundred potential GPIOs, but often only a dozen are used on any
-given board. Another is to catch conflicts, identifying errors when
-(a) two or more drivers wrongly think they have exclusive use of that
-signal, or (b) something wrongly believes it's safe to remove drivers
-needed to manage a signal that's in active use. That is, requesting a
-GPIO can serve as a kind of lock.
-
-Some platforms may also use knowledge about what GPIOs are active for
-power management, such as by powering down unused chip sectors and, more
-easily, gating off unused clocks.
-
-For GPIOs that use pins known to the pinctrl subsystem, that subsystem should
-be informed of their use; a gpiolib driver's .request() operation may call
-pinctrl_gpio_request(), and a gpiolib driver's .free() operation may call
-pinctrl_gpio_free(). The pinctrl subsystem allows a pinctrl_gpio_request()
-to succeed concurrently with a pin or pingroup being "owned" by a device for
-pin multiplexing.
-
-Any programming of pin multiplexing hardware that is needed to route the
-GPIO signal to the appropriate pin should occur within a GPIO driver's
-.direction_input() or .direction_output() operations, and occur after any
-setup of an output GPIO's value. This allows a glitch-free migration from a
-pin's special function to GPIO. This is sometimes required when using a GPIO
-to implement a workaround on signals typically driven by a non-GPIO HW block.
-
-Some platforms allow some or all GPIO signals to be routed to different pins.
-Similarly, other aspects of the GPIO or pin may need to be configured, such as
-pullup/pulldown. Platform software should arrange that any such details are
-configured prior to gpio_request() being called for those GPIOs, e.g. using
-the pinctrl subsystem's mapping table, so that GPIO users need not be aware
-of these details.
-
-Also note that it's your responsibility to have stopped using a GPIO
-before you free it.
-
-Considering in most cases GPIOs are actually configured right after they
-are claimed, three additional calls are defined:
-
- /* request a single GPIO, with initial configuration specified by
- * 'flags', identical to gpio_request() wrt other arguments and
- * return value
- */
- int gpio_request_one(unsigned gpio, unsigned long flags, const char *label);
-
- /* request multiple GPIOs in a single call
- */
- int gpio_request_array(struct gpio *array, size_t num);
-
- /* release multiple GPIOs in a single call
- */
- void gpio_free_array(struct gpio *array, size_t num);
-
-where 'flags' is currently defined to specify the following properties:
-
- * GPIOF_DIR_IN - to configure direction as input
- * GPIOF_DIR_OUT - to configure direction as output
-
- * GPIOF_INIT_LOW - as output, set initial level to LOW
- * GPIOF_INIT_HIGH - as output, set initial level to HIGH
- * GPIOF_OPEN_DRAIN - gpio pin is open drain type.
- * GPIOF_OPEN_SOURCE - gpio pin is open source type.
-
- * GPIOF_EXPORT_DIR_FIXED - export gpio to sysfs, keep direction
- * GPIOF_EXPORT_DIR_CHANGEABLE - also export, allow changing direction
-
-since GPIOF_INIT_* are only valid when configured as output, so group valid
-combinations as:
-
- * GPIOF_IN - configure as input
- * GPIOF_OUT_INIT_LOW - configured as output, initial level LOW
- * GPIOF_OUT_INIT_HIGH - configured as output, initial level HIGH
-
-When setting the flag as GPIOF_OPEN_DRAIN then it will assume that pins is
-open drain type. Such pins will not be driven to 1 in output mode. It is
-require to connect pull-up on such pins. By enabling this flag, gpio lib will
-make the direction to input when it is asked to set value of 1 in output mode
-to make the pin HIGH. The pin is make to LOW by driving value 0 in output mode.
-
-When setting the flag as GPIOF_OPEN_SOURCE then it will assume that pins is
-open source type. Such pins will not be driven to 0 in output mode. It is
-require to connect pull-down on such pin. By enabling this flag, gpio lib will
-make the direction to input when it is asked to set value of 0 in output mode
-to make the pin LOW. The pin is make to HIGH by driving value 1 in output mode.
-
-In the future, these flags can be extended to support more properties.
-
-Further more, to ease the claim/release of multiple GPIOs, 'struct gpio' is
-introduced to encapsulate all three fields as:
-
- struct gpio {
- unsigned gpio;
- unsigned long flags;
- const char *label;
- };
-
-A typical example of usage:
-
- static struct gpio leds_gpios[] = {
- { 32, GPIOF_OUT_INIT_HIGH, "Power LED" }, /* default to ON */
- { 33, GPIOF_OUT_INIT_LOW, "Green LED" }, /* default to OFF */
- { 34, GPIOF_OUT_INIT_LOW, "Red LED" }, /* default to OFF */
- { 35, GPIOF_OUT_INIT_LOW, "Blue LED" }, /* default to OFF */
- { ... },
- };
-
- err = gpio_request_one(31, GPIOF_IN, "Reset Button");
- if (err)
- ...
-
- err = gpio_request_array(leds_gpios, ARRAY_SIZE(leds_gpios));
- if (err)
- ...
-
- gpio_free_array(leds_gpios, ARRAY_SIZE(leds_gpios));
-
-
-GPIOs mapped to IRQs
---------------------
-GPIO numbers are unsigned integers; so are IRQ numbers. These make up
-two logically distinct namespaces (GPIO 0 need not use IRQ 0). You can
-map between them using calls like:
-
- /* map GPIO numbers to IRQ numbers */
- int gpio_to_irq(unsigned gpio);
-
- /* map IRQ numbers to GPIO numbers (avoid using this) */
- int irq_to_gpio(unsigned irq);
-
-Those return either the corresponding number in the other namespace, or
-else a negative errno code if the mapping can't be done. (For example,
-some GPIOs can't be used as IRQs.) It is an unchecked error to use a GPIO
-number that wasn't set up as an input using gpio_direction_input(), or
-to use an IRQ number that didn't originally come from gpio_to_irq().
-
-These two mapping calls are expected to cost on the order of a single
-addition or subtraction. They're not allowed to sleep.
-
-Non-error values returned from gpio_to_irq() can be passed to request_irq()
-or free_irq(). They will often be stored into IRQ resources for platform
-devices, by the board-specific initialization code. Note that IRQ trigger
-options are part of the IRQ interface, e.g. IRQF_TRIGGER_FALLING, as are
-system wakeup capabilities.
-
-Non-error values returned from irq_to_gpio() would most commonly be used
-with gpio_get_value(), for example to initialize or update driver state
-when the IRQ is edge-triggered. Note that some platforms don't support
-this reverse mapping, so you should avoid using it.
-
-
-Emulating Open Drain Signals
-----------------------------
-Sometimes shared signals need to use "open drain" signaling, where only the
-low signal level is actually driven. (That term applies to CMOS transistors;
-"open collector" is used for TTL.) A pullup resistor causes the high signal
-level. This is sometimes called a "wire-AND"; or more practically, from the
-negative logic (low=true) perspective this is a "wire-OR".
-
-One common example of an open drain signal is a shared active-low IRQ line.
-Also, bidirectional data bus signals sometimes use open drain signals.
-
-Some GPIO controllers directly support open drain outputs; many don't. When
-you need open drain signaling but your hardware doesn't directly support it,
-there's a common idiom you can use to emulate it with any GPIO pin that can
-be used as either an input or an output:
-
- LOW: gpio_direction_output(gpio, 0) ... this drives the signal
- and overrides the pullup.
-
- HIGH: gpio_direction_input(gpio) ... this turns off the output,
- so the pullup (or some other device) controls the signal.
-
-If you are "driving" the signal high but gpio_get_value(gpio) reports a low
-value (after the appropriate rise time passes), you know some other component
-is driving the shared signal low. That's not necessarily an error. As one
-common example, that's how I2C clocks are stretched: a slave that needs a
-slower clock delays the rising edge of SCK, and the I2C master adjusts its
-signaling rate accordingly.
-
-
-GPIO controllers and the pinctrl subsystem
-------------------------------------------
-
-A GPIO controller on a SOC might be tightly coupled with the pinctrl
-subsystem, in the sense that the pins can be used by other functions
-together with an optional gpio feature. We have already covered the
-case where e.g. a GPIO controller need to reserve a pin or set the
-direction of a pin by calling any of:
-
-pinctrl_gpio_request()
-pinctrl_gpio_free()
-pinctrl_gpio_direction_input()
-pinctrl_gpio_direction_output()
-
-But how does the pin control subsystem cross-correlate the GPIO
-numbers (which are a global business) to a certain pin on a certain
-pin controller?
-
-This is done by registering "ranges" of pins, which are essentially
-cross-reference tables. These are described in
-Documentation/driver-api/pinctl.rst
-
-While the pin allocation is totally managed by the pinctrl subsystem,
-gpio (under gpiolib) is still maintained by gpio drivers. It may happen
-that different pin ranges in a SoC is managed by different gpio drivers.
-
-This makes it logical to let gpio drivers announce their pin ranges to
-the pin ctrl subsystem before it will call 'pinctrl_gpio_request' in order
-to request the corresponding pin to be prepared by the pinctrl subsystem
-before any gpio usage.
-
-For this, the gpio controller can register its pin range with pinctrl
-subsystem. There are two ways of doing it currently: with or without DT.
-
-For with DT support refer to Documentation/devicetree/bindings/gpio/gpio.txt.
-
-For non-DT support, user can call gpiochip_add_pin_range() with appropriate
-parameters to register a range of gpio pins with a pinctrl driver. For this
-exact name string of pinctrl device has to be passed as one of the
-argument to this routine.
-
-
-What do these conventions omit?
-===============================
-One of the biggest things these conventions omit is pin multiplexing, since
-this is highly chip-specific and nonportable. One platform might not need
-explicit multiplexing; another might have just two options for use of any
-given pin; another might have eight options per pin; another might be able
-to route a given GPIO to any one of several pins. (Yes, those examples all
-come from systems that run Linux today.)
-
-Related to multiplexing is configuration and enabling of the pullups or
-pulldowns integrated on some platforms. Not all platforms support them,
-or support them in the same way; and any given board might use external
-pullups (or pulldowns) so that the on-chip ones should not be used.
-(When a circuit needs 5 kOhm, on-chip 100 kOhm resistors won't do.)
-Likewise drive strength (2 mA vs 20 mA) and voltage (1.8V vs 3.3V) is a
-platform-specific issue, as are models like (not) having a one-to-one
-correspondence between configurable pins and GPIOs.
-
-There are other system-specific mechanisms that are not specified here,
-like the aforementioned options for input de-glitching and wire-OR output.
-Hardware may support reading or writing GPIOs in gangs, but that's usually
-configuration dependent: for GPIOs sharing the same bank. (GPIOs are
-commonly grouped in banks of 16 or 32, with a given SOC having several such
-banks.) Some systems can trigger IRQs from output GPIOs, or read values
-from pins not managed as GPIOs. Code relying on such mechanisms will
-necessarily be nonportable.
-
-Dynamic definition of GPIOs is not currently standard; for example, as
-a side effect of configuring an add-on board with some GPIO expanders.
-
-
-GPIO implementor's framework (OPTIONAL)
-=======================================
-As noted earlier, there is an optional implementation framework making it
-easier for platforms to support different kinds of GPIO controller using
-the same programming interface. This framework is called "gpiolib".
-
-As a debugging aid, if debugfs is available a /sys/kernel/debug/gpio file
-will be found there. That will list all the controllers registered through
-this framework, and the state of the GPIOs currently in use.
-
-
-Controller Drivers: gpio_chip
------------------------------
-In this framework each GPIO controller is packaged as a "struct gpio_chip"
-with information common to each controller of that type:
-
- - methods to establish GPIO direction
- - methods used to access GPIO values
- - flag saying whether calls to its methods may sleep
- - optional debugfs dump method (showing extra state like pullup config)
- - label for diagnostics
-
-There is also per-instance data, which may come from device.platform_data:
-the number of its first GPIO, and how many GPIOs it exposes.
-
-The code implementing a gpio_chip should support multiple instances of the
-controller, possibly using the driver model. That code will configure each
-gpio_chip and issue gpiochip_add(). Removing a GPIO controller should be
-rare; use gpiochip_remove() when it is unavoidable.
-
-Most often a gpio_chip is part of an instance-specific structure with state
-not exposed by the GPIO interfaces, such as addressing, power management,
-and more. Chips such as codecs will have complex non-GPIO state.
-
-Any debugfs dump method should normally ignore signals which haven't been
-requested as GPIOs. They can use gpiochip_is_requested(), which returns
-either NULL or the label associated with that GPIO when it was requested.
-
-
-Platform Support
-----------------
-To force-enable this framework, a platform's Kconfig will "select" GPIOLIB,
-else it is up to the user to configure support for GPIO.
-
-It may also provide a custom value for ARCH_NR_GPIOS, so that it better
-reflects the number of GPIOs in actual use on that platform, without
-wasting static table space. (It should count both built-in/SoC GPIOs and
-also ones on GPIO expanders.
-
-If neither of these options are selected, the platform does not support
-GPIOs through GPIO-lib and the code cannot be enabled by the user.
-
-Trivial implementations of those functions can directly use framework
-code, which always dispatches through the gpio_chip:
-
- #define gpio_get_value __gpio_get_value
- #define gpio_set_value __gpio_set_value
- #define gpio_cansleep __gpio_cansleep
-
-Fancier implementations could instead define those as inline functions with
-logic optimizing access to specific SOC-based GPIOs. For example, if the
-referenced GPIO is the constant "12", getting or setting its value could
-cost as little as two or three instructions, never sleeping. When such an
-optimization is not possible those calls must delegate to the framework
-code, costing at least a few dozen instructions. For bitbanged I/O, such
-instruction savings can be significant.
-
-For SOCs, platform-specific code defines and registers gpio_chip instances
-for each bank of on-chip GPIOs. Those GPIOs should be numbered/labeled to
-match chip vendor documentation, and directly match board schematics. They
-may well start at zero and go up to a platform-specific limit. Such GPIOs
-are normally integrated into platform initialization to make them always be
-available, from arch_initcall() or earlier; they can often serve as IRQs.
-
-
-Board Support
--------------
-For external GPIO controllers -- such as I2C or SPI expanders, ASICs, multi
-function devices, FPGAs or CPLDs -- most often board-specific code handles
-registering controller devices and ensures that their drivers know what GPIO
-numbers to use with gpiochip_add(). Their numbers often start right after
-platform-specific GPIOs.
-
-For example, board setup code could create structures identifying the range
-of GPIOs that chip will expose, and passes them to each GPIO expander chip
-using platform_data. Then the chip driver's probe() routine could pass that
-data to gpiochip_add().
-
-Initialization order can be important. For example, when a device relies on
-an I2C-based GPIO, its probe() routine should only be called after that GPIO
-becomes available. That may mean the device should not be registered until
-calls for that GPIO can work. One way to address such dependencies is for
-such gpio_chip controllers to provide setup() and teardown() callbacks to
-board specific code; those board specific callbacks would register devices
-once all the necessary resources are available, and remove them later when
-the GPIO controller device becomes unavailable.
-
-
-Sysfs Interface for Userspace (OPTIONAL)
-========================================
-Platforms which use the "gpiolib" implementors framework may choose to
-configure a sysfs user interface to GPIOs. This is different from the
-debugfs interface, since it provides control over GPIO direction and
-value instead of just showing a gpio state summary. Plus, it could be
-present on production systems without debugging support.
-
-Given appropriate hardware documentation for the system, userspace could
-know for example that GPIO #23 controls the write protect line used to
-protect boot loader segments in flash memory. System upgrade procedures
-may need to temporarily remove that protection, first importing a GPIO,
-then changing its output state, then updating the code before re-enabling
-the write protection. In normal use, GPIO #23 would never be touched,
-and the kernel would have no need to know about it.
-
-Again depending on appropriate hardware documentation, on some systems
-userspace GPIO can be used to determine system configuration data that
-standard kernels won't know about. And for some tasks, simple userspace
-GPIO drivers could be all that the system really needs.
-
-Note that standard kernel drivers exist for common "LEDs and Buttons"
-GPIO tasks: "leds-gpio" and "gpio_keys", respectively. Use those
-instead of talking directly to the GPIOs; they integrate with kernel
-frameworks better than your userspace code could.
-
-
-Paths in Sysfs
---------------
-There are three kinds of entry in /sys/class/gpio:
-
- - Control interfaces used to get userspace control over GPIOs;
-
- - GPIOs themselves; and
-
- - GPIO controllers ("gpio_chip" instances).
-
-That's in addition to standard files including the "device" symlink.
-
-The control interfaces are write-only:
-
- /sys/class/gpio/
-
- "export" ... Userspace may ask the kernel to export control of
- a GPIO to userspace by writing its number to this file.
-
- Example: "echo 19 > export" will create a "gpio19" node
- for GPIO #19, if that's not requested by kernel code.
-
- "unexport" ... Reverses the effect of exporting to userspace.
-
- Example: "echo 19 > unexport" will remove a "gpio19"
- node exported using the "export" file.
-
-GPIO signals have paths like /sys/class/gpio/gpio42/ (for GPIO #42)
-and have the following read/write attributes:
-
- /sys/class/gpio/gpioN/
-
- "direction" ... reads as either "in" or "out". This value may
- normally be written. Writing as "out" defaults to
- initializing the value as low. To ensure glitch free
- operation, values "low" and "high" may be written to
- configure the GPIO as an output with that initial value.
-
- Note that this attribute *will not exist* if the kernel
- doesn't support changing the direction of a GPIO, or
- it was exported by kernel code that didn't explicitly
- allow userspace to reconfigure this GPIO's direction.
-
- "value" ... reads as either 0 (low) or 1 (high). If the GPIO
- is configured as an output, this value may be written;
- any nonzero value is treated as high.
-
- If the pin can be configured as interrupt-generating interrupt
- and if it has been configured to generate interrupts (see the
- description of "edge"), you can poll(2) on that file and
- poll(2) will return whenever the interrupt was triggered. If
- you use poll(2), set the events POLLPRI and POLLERR. If you
- use select(2), set the file descriptor in exceptfds. After
- poll(2) returns, either lseek(2) to the beginning of the sysfs
- file and read the new value or close the file and re-open it
- to read the value.
-
- "edge" ... reads as either "none", "rising", "falling", or
- "both". Write these strings to select the signal edge(s)
- that will make poll(2) on the "value" file return.
-
- This file exists only if the pin can be configured as an
- interrupt generating input pin.
-
- "active_low" ... reads as either 0 (false) or 1 (true). Write
- any nonzero value to invert the value attribute both
- for reading and writing. Existing and subsequent
- poll(2) support configuration via the edge attribute
- for "rising" and "falling" edges will follow this
- setting.
-
-GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the
-controller implementing GPIOs starting at #42) and have the following
-read-only attributes:
-
- /sys/class/gpio/gpiochipN/
-
- "base" ... same as N, the first GPIO managed by this chip
-
- "label" ... provided for diagnostics (not always unique)
-
- "ngpio" ... how many GPIOs this manges (N to N + ngpio - 1)
-
-Board documentation should in most cases cover what GPIOs are used for
-what purposes. However, those numbers are not always stable; GPIOs on
-a daughtercard might be different depending on the base board being used,
-or other cards in the stack. In such cases, you may need to use the
-gpiochip nodes (possibly in conjunction with schematics) to determine
-the correct GPIO number to use for a given signal.
-
-
-Exporting from Kernel code
---------------------------
-Kernel code can explicitly manage exports of GPIOs which have already been
-requested using gpio_request():
-
- /* export the GPIO to userspace */
- int gpio_export(unsigned gpio, bool direction_may_change);
-
- /* reverse gpio_export() */
- void gpio_unexport();
-
- /* create a sysfs link to an exported GPIO node */
- int gpio_export_link(struct device *dev, const char *name,
- unsigned gpio)
-
-After a kernel driver requests a GPIO, it may only be made available in
-the sysfs interface by gpio_export(). The driver can control whether the
-signal direction may change. This helps drivers prevent userspace code
-from accidentally clobbering important system state.
-
-This explicit exporting can help with debugging (by making some kinds
-of experiments easier), or can provide an always-there interface that's
-suitable for documenting as part of a board support package.
-
-After the GPIO has been exported, gpio_export_link() allows creating
-symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can
-use this to provide the interface under their own device in sysfs with
-a descriptive name.
diff --git a/Documentation/gpio/gpio.txt b/Documentation/gpio/gpio.txt
deleted file mode 100644
index cd9b356e88cd..000000000000
--- a/Documentation/gpio/gpio.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-GPIO Interfaces
-===============
-
-The documents in this directory give detailed instructions on how to access
-GPIOs in drivers, and how to write a driver for a device that provides GPIOs
-itself.
-
-Due to the history of GPIO interfaces in the kernel, there are two different
-ways to obtain and use GPIOs:
-
- - The descriptor-based interface is the preferred way to manipulate GPIOs,
-and is described by all the files in this directory excepted gpio-legacy.txt.
- - The legacy integer-based interface which is considered deprecated (but still
-usable for compatibility reasons) is documented in gpio-legacy.txt.
-
-The remainder of this document applies to the new descriptor-based interface.
-gpio-legacy.txt contains the same information applied to the legacy
-integer-based interface.
-
-
-What is a GPIO?
-===============
-
-A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
-digital signal. They are provided from many kinds of chip, and are familiar
-to Linux developers working with embedded and custom hardware. Each GPIO
-represents a bit connected to a particular pin, or "ball" on Ball Grid Array
-(BGA) packages. Board schematics show which external hardware connects to
-which GPIOs. Drivers can be written generically, so that board setup code
-passes such pin configuration data to drivers.
-
-System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
-non-dedicated pin can be configured as a GPIO; and most chips have at least
-several dozen of them. Programmable logic devices (like FPGAs) can easily
-provide GPIOs; multifunction chips like power managers, and audio codecs
-often have a few such pins to help with pin scarcity on SOCs; and there are
-also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
-Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
-firmware knowing how they're used).
-
-The exact capabilities of GPIOs vary between systems. Common options:
-
- - Output values are writable (high=1, low=0). Some chips also have
- options about how that value is driven, so that for example only one
- value might be driven, supporting "wire-OR" and similar schemes for the
- other value (notably, "open drain" signaling).
-
- - Input values are likewise readable (1, 0). Some chips support readback
- of pins configured as "output", which is very useful in such "wire-OR"
- cases (to support bidirectional signaling). GPIO controllers may have
- input de-glitch/debounce logic, sometimes with software controls.
-
- - Inputs can often be used as IRQ signals, often edge triggered but
- sometimes level triggered. Such IRQs may be configurable as system
- wakeup events, to wake the system from a low power state.
-
- - Usually a GPIO will be configurable as either input or output, as needed
- by different product boards; single direction ones exist too.
-
- - Most GPIOs can be accessed while holding spinlocks, but those accessed
- through a serial bus normally can't. Some systems support both types.
-
-On a given board each GPIO is used for one specific purpose like monitoring
-MMC/SD card insertion/removal, detecting card write-protect status, driving
-a LED, configuring a transceiver, bit-banging a serial bus, poking a hardware
-watchdog, sensing a switch, and so on.
-
-
-Common GPIO Properties
-======================
-
-These properties are met through all the other documents of the GPIO interface
-and it is useful to understand them, especially if you need to define GPIO
-mappings.
-
-Active-High and Active-Low
---------------------------
-It is natural to assume that a GPIO is "active" when its output signal is 1
-("high"), and inactive when it is 0 ("low"). However in practice the signal of a
-GPIO may be inverted before is reaches its destination, or a device could decide
-to have different conventions about what "active" means. Such decisions should
-be transparent to device drivers, therefore it is possible to define a GPIO as
-being either active-high ("1" means "active", the default) or active-low ("0"
-means "active") so that drivers only need to worry about the logical signal and
-not about what happens at the line level.
-
-Open Drain and Open Source
---------------------------
-Sometimes shared signals need to use "open drain" (where only the low signal
-level is actually driven), or "open source" (where only the high signal level is
-driven) signaling. That term applies to CMOS transistors; "open collector" is
-used for TTL. A pullup or pulldown resistor causes the high or low signal level.
-This is sometimes called a "wire-AND"; or more practically, from the negative
-logic (low=true) perspective this is a "wire-OR".
-
-One common example of an open drain signal is a shared active-low IRQ line.
-Also, bidirectional data bus signals sometimes use open drain signals.
-
-Some GPIO controllers directly support open drain and open source outputs; many
-don't. When you need open drain signaling but your hardware doesn't directly
-support it, there's a common idiom you can use to emulate it with any GPIO pin
-that can be used as either an input or an output:
-
- LOW: gpiod_direction_output(gpio, 0) ... this drives the signal and overrides
- the pullup.
-
- HIGH: gpiod_direction_input(gpio) ... this turns off the output, so the pullup
- (or some other device) controls the signal.
-
-The same logic can be applied to emulate open source signaling, by driving the
-high signal and configuring the GPIO as input for low. This open drain/open
-source emulation can be handled transparently by the GPIO framework.
-
-If you are "driving" the signal high but gpiod_get_value(gpio) reports a low
-value (after the appropriate rise time passes), you know some other component is
-driving the shared signal low. That's not necessarily an error. As one common
-example, that's how I2C clocks are stretched: a slave that needs a slower clock
-delays the rising edge of SCK, and the I2C master adjusts its signaling rate
-accordingly.
diff --git a/Documentation/gpio/sysfs.txt b/Documentation/gpio/sysfs.txt
index 6cdeab8650cd..58eeab81f349 100644
--- a/Documentation/gpio/sysfs.txt
+++ b/Documentation/gpio/sysfs.txt
@@ -32,9 +32,8 @@ standard kernels won't know about. And for some tasks, simple userspace
GPIO drivers could be all that the system really needs.
DO NOT ABUSE SYSFS TO CONTROL HARDWARE THAT HAS PROPER KERNEL DRIVERS.
-PLEASE READ THE DOCUMENT NAMED "drivers-on-gpio.txt" IN THIS DOCUMENTATION
-DIRECTORY TO AVOID REINVENTING KERNEL WHEELS IN USERSPACE. I MEAN IT.
-REALLY.
+PLEASE READ THE DOCUMENT AT Documentation/driver-api/gpio/drivers-on-gpio.rst
+TO AVOID REINVENTING KERNEL WHEELS IN USERSPACE. I MEAN IT. REALLY.
Paths in Sysfs
--------------
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
new file mode 100644
index 000000000000..e8c84419a2a1
--- /dev/null
+++ b/Documentation/gpu/drivers.rst
@@ -0,0 +1,21 @@
+========================
+GPU Driver Documentation
+========================
+
+.. toctree::
+
+ i915
+ meson
+ pl111
+ tegra
+ tinydrm
+ tve200
+ vc4
+ bridge/dw-hdmi
+
+.. only:: subproject and html
+
+ Indices
+ =======
+
+ * :ref:`genindex`
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 2dcf5b42015d..1dffd1ac4cd4 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -286,6 +286,9 @@ Atomic Mode Setting Function Reference
.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
:export:
+.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
+ :internal:
+
CRTC Abstraction
================
@@ -547,8 +550,9 @@ Explicit Fencing Properties
Existing KMS Properties
-----------------------
-The following table gives description of drm properties exposed by
-various modules/drivers.
+The following table gives description of drm properties exposed by various
+modules/drivers. Because this table is very unwieldy, do not add any new
+properties here. Instead document them in a section above.
.. csv-table::
:header-rows: 1
diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst
index c36586dad29d..00288f34c5a6 100644
--- a/Documentation/gpu/index.rst
+++ b/Documentation/gpu/index.rst
@@ -10,16 +10,9 @@ Linux GPU Driver Developer's Guide
drm-kms
drm-kms-helpers
drm-uapi
- i915
- meson
- pl111
- tegra
- tinydrm
- tve200
- vc4
+ drivers
vga-switcheroo
vgaarbiter
- bridge/dw-hdmi
todo
.. only:: subproject and html
diff --git a/Documentation/gpu/kms-properties.csv b/Documentation/gpu/kms-properties.csv
index 927b65e14219..6b28b014cb7d 100644
--- a/Documentation/gpu/kms-properties.csv
+++ b/Documentation/gpu/kms-properties.csv
@@ -1,5 +1,4 @@
Owner Module/Drivers,Group,Property Name,Type,Property Values,Object attached,Description/Restrictions
-,,“scaling mode”,ENUM,"{ ""None"", ""Full"", ""Center"", ""Full aspect"" }",Connector,"Supported by: amdgpu, gma500, i915, nouveau and radeon."
,DVI-I,“subconnector”,ENUM,"{ “Unknown”, “DVI-D”, “DVI-A” }",Connector,TBD
,,“select subconnector”,ENUM,"{ “Automatic”, “DVI-D”, “DVI-A” }",Connector,TBD
,TV,“subconnector”,ENUM,"{ ""Unknown"", ""Composite"", ""SVIDEO"", ""Component"", ""SCART"" }",Connector,TBD
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 1e593370f64f..f4d0b3476d9c 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -212,6 +212,16 @@ probably use drm_fb_helper_fbdev_teardown().
Contact: Maintainer of the driver you plan to convert
+idr_init_base()
+---------------
+
+DRM core&drivers uses a lot of idr (integer lookup directories) for mapping
+userspace IDs to internal objects, and in most places ID=0 means NULL and hence
+is never used. Switching to idr_init_base() for these would make the idr more
+efficient.
+
+Contact: Daniel Vetter
+
Core refactorings
=================
@@ -440,5 +450,12 @@ See drivers/gpu/drm/amd/display/TODO for tasks.
Contact: Harry Wentland, Alex Deucher
+i915
+----
+
+- Our early/late pm callbacks could be removed in favour of using
+ device_link_add to model the dependency between i915 and snd_had. See
+ https://dri.freedesktop.org/docs/drm/driver-api/device_link.html
+
Outside DRM
===========
diff --git a/Documentation/hwmon/adm1275 b/Documentation/hwmon/adm1275
index 791bc0bd91e6..39033538eb03 100644
--- a/Documentation/hwmon/adm1275
+++ b/Documentation/hwmon/adm1275
@@ -6,6 +6,10 @@ Supported chips:
Prefix: 'adm1075'
Addresses scanned: -
Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1075.pdf
+ * Analog Devices ADM1272
+ Prefix: 'adm1272'
+ Addresses scanned: -
+ Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1272.pdf
* Analog Devices ADM1275
Prefix: 'adm1275'
Addresses scanned: -
@@ -29,11 +33,11 @@ Author: Guenter Roeck <linux@roeck-us.net>
Description
-----------
-This driver supports hardware monitoring for Analog Devices ADM1075, ADM1275,
-ADM1276, ADM1278, ADM1293, and ADM1294 Hot-Swap Controller and Digital
-Power Monitors.
+This driver supports hardware monitoring for Analog Devices ADM1075, ADM1272,
+ADM1275, ADM1276, ADM1278, ADM1293, and ADM1294 Hot-Swap Controller and
+Digital Power Monitors.
-ADM1075, ADM1275, ADM1276, ADM1278, ADM1293, and ADM1294 are hot-swap
+ADM1075, ADM1272, ADM1275, ADM1276, ADM1278, ADM1293, and ADM1294 are hot-swap
controllers that allow a circuit board to be removed from or inserted into
a live backplane. They also feature current and voltage readback via an
integrated 12 bit analog-to-digital converter (ADC), accessed using a
@@ -100,11 +104,10 @@ power1_input_lowest Lowest observed input power. ADM1293 and ADM1294 only.
power1_input_highest Highest observed input power.
power1_reset_history Write any value to reset history.
- Power attributes are supported on ADM1075, ADM1276,
- ADM1293, and ADM1294.
+ Power attributes are supported on ADM1075, ADM1272,
+ ADM1276, ADM1293, and ADM1294.
temp1_input Chip temperature.
- Temperature attributes are only available on ADM1278.
temp1_max Maximum chip temperature.
temp1_max_alarm Temperature alarm.
temp1_crit Critical chip temperature.
@@ -112,4 +115,5 @@ temp1_crit_alarm Critical temperature high alarm.
temp1_highest Highest observed temperature.
temp1_reset_history Write any value to reset history.
- Temperature attributes are supported on ADM1278.
+ Temperature attributes are supported on ADM1272 and
+ ADM1278.
diff --git a/Documentation/hwmon/lm92 b/Documentation/hwmon/lm92
index 22f68ad032cf..cfa99a353b8c 100644
--- a/Documentation/hwmon/lm92
+++ b/Documentation/hwmon/lm92
@@ -11,10 +11,8 @@ Supported chips:
Addresses scanned: none, force parameter needed
Datasheet: http://www.national.com/pf/LM/LM76.html
* Maxim MAX6633/MAX6634/MAX6635
- Prefix: 'lm92'
- Addresses scanned: I2C 0x48 - 0x4b
- MAX6633 with address in 0x40 - 0x47, 0x4c - 0x4f needs force parameter
- and MAX6634 with address in 0x4c - 0x4f needs force parameter
+ Prefix: 'max6635'
+ Addresses scanned: none, force parameter needed
Datasheet: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3074
Authors:
diff --git a/Documentation/hwmon/nct6775 b/Documentation/hwmon/nct6775
index 76add4c9cd68..bd59834d310f 100644
--- a/Documentation/hwmon/nct6775
+++ b/Documentation/hwmon/nct6775
@@ -36,6 +36,14 @@ Supported chips:
Prefix: 'nct6793'
Addresses scanned: ISA address retrieved from Super I/O registers
Datasheet: Available from Nuvoton upon request
+ * Nuvoton NCT6795D
+ Prefix: 'nct6795'
+ Addresses scanned: ISA address retrieved from Super I/O registers
+ Datasheet: Available from Nuvoton upon request
+ * Nuvoton NCT6796D
+ Prefix: 'nct6796'
+ Addresses scanned: ISA address retrieved from Super I/O registers
+ Datasheet: Available from Nuvoton upon request
Authors:
Guenter Roeck <linux@roeck-us.net>
@@ -88,10 +96,10 @@ The mode works for fan1-fan5.
sysfs attributes
----------------
-pwm[1-5] - this file stores PWM duty cycle or DC value (fan speed) in range:
+pwm[1-7] - this file stores PWM duty cycle or DC value (fan speed) in range:
0 (lowest speed) to 255 (full)
-pwm[1-5]_enable - this file controls mode of fan/temperature control:
+pwm[1-7]_enable - this file controls mode of fan/temperature control:
* 0 Fan control disabled (fans set to maximum speed)
* 1 Manual mode, write to pwm[0-5] any value 0-255
* 2 "Thermal Cruise" mode
@@ -99,16 +107,16 @@ pwm[1-5]_enable - this file controls mode of fan/temperature control:
* 4 "Smart Fan III" mode (NCT6775F only)
* 5 "Smart Fan IV" mode
-pwm[1-5]_mode - controls if output is PWM or DC level
+pwm[1-7]_mode - controls if output is PWM or DC level
* 0 DC output
* 1 PWM output
Common fan control attributes
-----------------------------
-pwm[1-5]_temp_sel Temperature source. Value is temperature sensor index.
+pwm[1-7]_temp_sel Temperature source. Value is temperature sensor index.
For example, select '1' for temp1_input.
-pwm[1-5]_weight_temp_sel
+pwm[1-7]_weight_temp_sel
Secondary temperature source. Value is temperature
sensor index. For example, select '1' for temp1_input.
Set to 0 to disable secondary temperature control.
@@ -116,16 +124,16 @@ pwm[1-5]_weight_temp_sel
If secondary temperature functionality is enabled, it is controlled with the
following attributes.
-pwm[1-5]_weight_duty_step
+pwm[1-7]_weight_duty_step
Duty step size.
-pwm[1-5]_weight_temp_step
+pwm[1-7]_weight_temp_step
Temperature step size. With each step over
temp_step_base, the value of weight_duty_step is added
to the current pwm value.
-pwm[1-5]_weight_temp_step_base
+pwm[1-7]_weight_temp_step_base
Temperature at which secondary temperature control kicks
in.
-pwm[1-5]_weight_temp_step_tol
+pwm[1-7]_weight_temp_step_tol
Temperature step tolerance.
Thermal Cruise mode (2)
@@ -133,9 +141,9 @@ Thermal Cruise mode (2)
If the temperature is in the range defined by:
-pwm[1-5]_target_temp Target temperature, unit millidegree Celsius
+pwm[1-7]_target_temp Target temperature, unit millidegree Celsius
(range 0 - 127000)
-pwm[1-5]_temp_tolerance
+pwm[1-7]_temp_tolerance
Target temperature tolerance, unit millidegree Celsius
there are no changes to fan speed. Once the temperature leaves the interval, fan
@@ -143,14 +151,14 @@ speed increases (if temperature is higher that desired) or decreases (if
temperature is lower than desired), using the following limits and time
intervals.
-pwm[1-5]_start fan pwm start value (range 1 - 255), to start fan
+pwm[1-7]_start fan pwm start value (range 1 - 255), to start fan
when the temperature is above defined range.
-pwm[1-5]_floor lowest fan pwm (range 0 - 255) if temperature is below
+pwm[1-7]_floor lowest fan pwm (range 0 - 255) if temperature is below
the defined range. If set to 0, the fan is expected to
stop if the temperature is below the defined range.
-pwm[1-5]_step_up_time milliseconds before fan speed is increased
-pwm[1-5]_step_down_time milliseconds before fan speed is decreased
-pwm[1-5]_stop_time how many milliseconds must elapse to switch
+pwm[1-7]_step_up_time milliseconds before fan speed is increased
+pwm[1-7]_step_down_time milliseconds before fan speed is decreased
+pwm[1-7]_stop_time how many milliseconds must elapse to switch
corresponding fan off (when the temperature was below
defined range).
@@ -159,8 +167,8 @@ Speed Cruise mode (3)
This modes tries to keep the fan speed constant.
-fan[1-5]_target Target fan speed
-fan[1-5]_tolerance
+fan[1-7]_target Target fan speed
+fan[1-7]_tolerance
Target speed tolerance
@@ -177,19 +185,19 @@ points should be set to higher temperatures and higher pwm values to achieve
higher fan speeds with increasing temperature. The last data point reflects
critical temperature mode, in which the fans should run at full speed.
-pwm[1-5]_auto_point[1-7]_pwm
+pwm[1-7]_auto_point[1-7]_pwm
pwm value to be set if temperature reaches matching
temperature range.
-pwm[1-5]_auto_point[1-7]_temp
+pwm[1-7]_auto_point[1-7]_temp
Temperature over which the matching pwm is enabled.
-pwm[1-5]_temp_tolerance
+pwm[1-7]_temp_tolerance
Temperature tolerance, unit millidegree Celsius
-pwm[1-5]_crit_temp_tolerance
+pwm[1-7]_crit_temp_tolerance
Temperature tolerance for critical temperature,
unit millidegree Celsius
-pwm[1-5]_step_up_time milliseconds before fan speed is increased
-pwm[1-5]_step_down_time milliseconds before fan speed is decreased
+pwm[1-7]_step_up_time milliseconds before fan speed is increased
+pwm[1-7]_step_down_time milliseconds before fan speed is decreased
Usage Notes
-----------
diff --git a/Documentation/hwmon/sht21 b/Documentation/hwmon/sht21
index 47f4765db256..8b3cdda541c1 100644
--- a/Documentation/hwmon/sht21
+++ b/Documentation/hwmon/sht21
@@ -6,13 +6,13 @@ Supported chips:
Prefix: 'sht21'
Addresses scanned: none
Datasheet: Publicly available at the Sensirion website
- http://www.sensirion.com/en/pdf/product_information/Datasheet-humidity-sensor-SHT21.pdf
+ http://www.sensirion.com/file/datasheet_sht21
* Sensirion SHT25
- Prefix: 'sht21'
+ Prefix: 'sht25'
Addresses scanned: none
Datasheet: Publicly available at the Sensirion website
- http://www.sensirion.com/en/pdf/product_information/Datasheet-humidity-sensor-SHT25.pdf
+ http://www.sensirion.com/file/datasheet_sht25
Author:
Urs Fleisch <urs.fleisch@sensirion.com>
diff --git a/Documentation/hwmon/sht3x b/Documentation/hwmon/sht3x
index b0d88184f48e..d9daa6ab1e8e 100644
--- a/Documentation/hwmon/sht3x
+++ b/Documentation/hwmon/sht3x
@@ -5,7 +5,7 @@ Supported chips:
* Sensirion SHT3x-DIS
Prefix: 'sht3x'
Addresses scanned: none
- Datasheet: http://www.sensirion.com/fileadmin/user_upload/customers/sensirion/Dokumente/Humidity/Sensirion_Humidity_Datasheet_SHT3x_DIS.pdf
+ Datasheet: https://www.sensirion.com/file/datasheet_sht3x_digital
Author:
David Frey <david.frey@sensirion.com>
diff --git a/Documentation/index.rst b/Documentation/index.rst
index ef5080cbf009..3b99ab931d41 100644
--- a/Documentation/index.rst
+++ b/Documentation/index.rst
@@ -64,6 +64,7 @@ merged much easier.
dev-tools/index
doc-guide/index
kernel-hacking/index
+ trace/index
maintainer/index
Kernel API documentation
diff --git a/Documentation/infiniband/sysfs.txt b/Documentation/infiniband/sysfs.txt
index 77570d16b170..9fab5062f84b 100644
--- a/Documentation/infiniband/sysfs.txt
+++ b/Documentation/infiniband/sysfs.txt
@@ -1,129 +1,4 @@
SYSFS FILES
- For each InfiniBand device, the InfiniBand drivers create the
- following files under /sys/class/infiniband/<device name>:
-
- node_type - Node type (CA, switch or router)
- node_guid - Node GUID
- sys_image_guid - System image GUID
-
- In addition, there is a "ports" subdirectory, with one subdirectory
- for each port. For example, if mthca0 is a 2-port HCA, there will
- be two directories:
-
- /sys/class/infiniband/mthca0/ports/1
- /sys/class/infiniband/mthca0/ports/2
-
- (A switch will only have a single "0" subdirectory for switch port
- 0; no subdirectory is created for normal switch ports)
-
- In each port subdirectory, the following files are created:
-
- cap_mask - Port capability mask
- lid - Port LID
- lid_mask_count - Port LID mask count
- rate - Port data rate (active width * active speed)
- sm_lid - Subnet manager LID for port's subnet
- sm_sl - Subnet manager SL for port's subnet
- state - Port state (DOWN, INIT, ARMED, ACTIVE or ACTIVE_DEFER)
- phys_state - Port physical state (Sleep, Polling, LinkUp, etc)
-
- There is also a "counters" subdirectory, with files
-
- VL15_dropped
- excessive_buffer_overrun_errors
- link_downed
- link_error_recovery
- local_link_integrity_errors
- port_rcv_constraint_errors
- port_rcv_data
- port_rcv_errors
- port_rcv_packets
- port_rcv_remote_physical_errors
- port_rcv_switch_relay_errors
- port_xmit_constraint_errors
- port_xmit_data
- port_xmit_discards
- port_xmit_packets
- symbol_error
-
- Each of these files contains the corresponding value from the port's
- Performance Management PortCounters attribute, as described in
- section 16.1.3.5 of the InfiniBand Architecture Specification.
-
- The "pkeys" and "gids" subdirectories contain one file for each
- entry in the port's P_Key or GID table respectively. For example,
- ports/1/pkeys/10 contains the value at index 10 in port 1's P_Key
- table.
-
- There is an optional "hw_counters" subdirectory that may be under either
- the parent device or the port subdirectories or both. If present,
- there are a list of counters provided by the hardware. They may match
- some of the counters in the counters directory, but they often include
- many other counters. In addition to the various counters, there will
- be a file named "lifespan" that configures how frequently the core
- should update the counters when they are being accessed (counters are
- not updated if they are not being accessed). The lifespan is in milli-
- seconds and defaults to 10 unless set to something else by the driver.
- Users may echo a value between 0 - 10000 to the lifespan file to set
- the length of time between updates in milliseconds.
-
-MTHCA
-
- The Mellanox HCA driver also creates the files:
-
- hw_rev - Hardware revision number
- fw_ver - Firmware version
- hca_type - HCA type: "MT23108", "MT25208 (MT23108 compat mode)",
- or "MT25208"
-
-HFI1
-
- The hfi1 driver also creates these additional files:
-
- hw_rev - hardware revision
- board_id - manufacturing board id
- tempsense - thermal sense information
- serial - board serial number
- nfreectxts - number of free user contexts
- nctxts - number of allowed contexts (PSM2)
- chip_reset - diagnostic (root only)
- boardversion - board version
-
- sdma<N>/ - one directory per sdma engine (0 - 15)
- sdma<N>/cpu_list - read-write, list of cpus for user-process to sdma
- engine assignment.
- sdma<N>/vl - read-only, vl the sdma engine maps to.
-
- The new interface will give the user control on the affinity settings
- for the hfi1 device.
- As an example, to set an sdma engine irq affinity and thread affinity
- of a user processes to use the sdma engine, which is "near" in terms
- of NUMA configuration, or physical cpu location, the user will do:
-
- echo "3" > /proc/irq/<N>/smp_affinity_list
- echo "4-7" > /sys/devices/.../sdma3/cpu_list
- cat /sys/devices/.../sdma3/vl
- 0
- echo "8" > /proc/irq/<M>/smp_affinity_list
- echo "9-12" > /sys/devices/.../sdma4/cpu_list
- cat /sys/devices/.../sdma4/vl
- 1
-
- to make sure that when a process runs on cpus 4,5,6, or 7,
- and uses vl=0, then sdma engine 3 is selected by the driver,
- and also the interrupt of the sdma engine 3 is steered to cpu 3.
- Similarly, when a process runs on cpus 9,10,11, or 12 and sets vl=1,
- then engine 4 will be selected and the irq of the sdma engine 4 is
- steered to cpu 8.
- This assumes that in the above N is the irq number of "sdma3",
- and M is irq number of "sdma4" in the /proc/interrupts file.
-
- ports/1/
- CCMgtA/
- cc_settings_bin - CCA tables used by PSM2
- cc_table_bin
- cc_prescan - enable prescaning for faster BECN response
- sc2v/ - 32 files (0 - 31) used to translate sl->vl
- sl2sc/ - 32 files (0 - 31) used to translate sl->sc
- vl2mtu/ - 16 (0 - 15) files used to determine MTU for vl
+The sysfs interface has moved to
+Documentation/ABI/stable/sysfs-class-infiniband.
diff --git a/Documentation/input/devices/alps.rst b/Documentation/input/devices/alps.rst
index 6779148e428c..b556d6bde5e1 100644
--- a/Documentation/input/devices/alps.rst
+++ b/Documentation/input/devices/alps.rst
@@ -192,10 +192,13 @@ The final v3 packet type is the trackstick packet::
byte 0: 1 1 x7 y7 1 1 1 1
byte 1: 0 x6 x5 x4 x3 x2 x1 x0
byte 2: 0 y6 y5 y4 y3 y2 y1 y0
- byte 3: 0 1 0 0 1 0 0 0
- byte 4: 0 z4 z3 z2 z1 z0 ? ?
+ byte 3: 0 1 TP SW 1 M R L
+ byte 4: 0 z6 z5 z4 z3 z2 z1 z0
byte 5: 0 0 1 1 1 1 1 1
+TP means Tap SW status when tap processing is enabled or Press status when press
+processing is enabled. SW means scroll up when 4 buttons are available.
+
ALPS Absolute Mode - Protocol Version 4
---------------------------------------
diff --git a/Documentation/input/devices/pxrc.rst b/Documentation/input/devices/pxrc.rst
new file mode 100644
index 000000000000..ca11f646bae8
--- /dev/null
+++ b/Documentation/input/devices/pxrc.rst
@@ -0,0 +1,57 @@
+=======================================================
+pxrc - PhoenixRC Flight Controller Adapter
+=======================================================
+
+:Author: Marcus Folkesson <marcus.folkesson@gmail.com>
+
+This driver let you use your own RC controller plugged into the
+adapter that comes with PhoenixRC [1]_ or other compatible adapters.
+
+The adapter supports 7 analog channels and 1 digital input switch.
+
+Notes
+=====
+
+Many RC controllers is able to configure which stick goes to which channel.
+This is also configurable in most simulators, so a matching is not necessary.
+
+The driver is generating the following input event for analog channels:
+
++---------+----------------+
+| Channel | Event |
++=========+================+
+| 1 | ABS_X |
++---------+----------------+
+| 2 | ABS_Y |
++---------+----------------+
+| 3 | ABS_RX |
++---------+----------------+
+| 4 | ABS_RY |
++---------+----------------+
+| 5 | ABS_RUDDER |
++---------+----------------+
+| 6 | ABS_THROTTLE |
++---------+----------------+
+| 7 | ABS_MISC |
++---------+----------------+
+
+The digital input switch is generated as an `BTN_A` event.
+
+Manual Testing
+==============
+
+To test this driver's functionality you may use `input-event` which is part of
+the `input layer utilities` suite [2]_.
+
+For example::
+
+ > modprobe pxrc
+ > input-events <devnr>
+
+To print all input events from input `devnr`.
+
+References
+==========
+
+.. [1] http://www.phoenix-sim.com/
+.. [2] https://www.kraxel.org/cgit/input/
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index 6501389d55b9..84bb74dcae12 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -305,7 +305,6 @@ Code Seq#(hex) Include File Comments
0xA0 all linux/sdp/sdp.h Industrial Device Project
<mailto:kenji@bitgate.com>
0xA1 0 linux/vtpm_proxy.h TPM Emulator Proxy Driver
-0xA2 00-0F arch/tile/include/asm/hardwall.h
0xA3 80-8F Port ACL in development:
<mailto:tlewis@mindspring.com>
0xA3 90-9F linux/dtlk.h
diff --git a/Documentation/isdn/INTERFACE.CAPI b/Documentation/isdn/INTERFACE.CAPI
index 1688b5a1fd77..021aa9cf139d 100644
--- a/Documentation/isdn/INTERFACE.CAPI
+++ b/Documentation/isdn/INTERFACE.CAPI
@@ -18,7 +18,7 @@ corresponding hardware driver. Kernel CAPI then forwards CAPI messages in both
directions between the application and the hardware driver.
Format and semantics of CAPI messages are specified in the CAPI 2.0 standard.
-This standard is freely available from http://www.capi.org.
+This standard is freely available from https://www.capi.org.
2. Driver and Device Registration
diff --git a/Documentation/isdn/README b/Documentation/isdn/README
index 32d4e80c2c03..74bd2bdb455b 100644
--- a/Documentation/isdn/README
+++ b/Documentation/isdn/README
@@ -33,10 +33,10 @@ README for the ISDN-subsystem
de.alt.comm.isdn4linux
There is also a well maintained FAQ in English available at
- http://www.mhessler.de/i4lfaq/
+ https://www.mhessler.de/i4lfaq/
It can be viewed online, or downloaded in sgml/text/html format.
The FAQ can also be viewed online at
- http://www.isdn4linux.de/faq/
+ https://www.isdn4linux.de/faq/i4lfaq.html
or downloaded from
ftp://ftp.isdn4linux.de/pub/isdn4linux/FAQ/
diff --git a/Documentation/isdn/README.FAQ b/Documentation/isdn/README.FAQ
index 356f7944641d..e5dd1addacdd 100644
--- a/Documentation/isdn/README.FAQ
+++ b/Documentation/isdn/README.FAQ
@@ -8,9 +8,9 @@ You find it in:
In case you just want to see the FAQ online, or download the newest version,
you can have a look at my website:
-http://www.mhessler.de/i4lfaq/ (view + download)
+https://www.mhessler.de/i4lfaq/ (view + download)
or:
-http://www.isdn4linux.de/faq/ (view)
+https://www.isdn4linux.de/faq/4lfaq.html (view)
As the extension tells, the FAQ is in SGML format, and you can convert it
into text/html/... format by using the sgml2txt/sgml2html/... tools.
diff --git a/Documentation/isdn/README.gigaset b/Documentation/isdn/README.gigaset
index 7534c6039adc..9b1ce277ca3d 100644
--- a/Documentation/isdn/README.gigaset
+++ b/Documentation/isdn/README.gigaset
@@ -29,8 +29,9 @@ GigaSet 307x Device Driver
T-Com Sinus 721 data
Chicago 390 USB (KPN)
- See also http://www.erbze.info/sinus_gigaset.htm and
- http://gigaset307x.sourceforge.net/
+ See also http://www.erbze.info/sinus_gigaset.htm
+ (archived at https://web.archive.org/web/20100717020421/http://www.erbze.info:80/sinus_gigaset.htm ) and
+ http://gigaset307x.sourceforge.net/
We had also reports from users of Gigaset M105 who could use the drivers
with SX 100 and CX 100 ISDN bases (only in unimodem mode, see section 2.5.)
@@ -52,7 +53,7 @@ GigaSet 307x Device Driver
to use CAPI 2.0 or ISDN4Linux for ISDN connections (voice or data).
There are some user space tools available at
- http://sourceforge.net/projects/gigaset307x/
+ https://sourceforge.net/projects/gigaset307x/
which provide access to additional device specific functions like SMS,
phonebook or call journal.
@@ -202,7 +203,7 @@ GigaSet 307x Device Driver
You can use some configuration tool of your distribution to configure this
"modem" or configure pppd/wvdial manually. There are some example ppp
configuration files and chat scripts in the gigaset-VERSION/ppp directory
- in the driver packages from http://sourceforge.net/projects/gigaset307x/.
+ in the driver packages from https://sourceforge.net/projects/gigaset307x/.
Please note that the USB drivers are not able to change the state of the
control lines. This means you must use "Stupid Mode" if you are using
wvdial or you should use the nocrtscts option of pppd.
@@ -361,7 +362,7 @@ GigaSet 307x Device Driver
---------------------------
If you can't solve problems with the driver on your own, feel free to
use one of the forums, bug trackers, or mailing lists on
- http://sourceforge.net/projects/gigaset307x
+ https://sourceforge.net/projects/gigaset307x
or write an electronic mail to the maintainers.
Try to provide as much information as possible, such as
@@ -391,11 +392,12 @@ GigaSet 307x Device Driver
4. Links, other software
---------------------
- Sourceforge project developing this driver and associated tools
- http://sourceforge.net/projects/gigaset307x
+ https://sourceforge.net/projects/gigaset307x
- Yahoo! Group on the Siemens Gigaset family of devices
- http://de.groups.yahoo.com/group/Siemens-Gigaset
+ https://de.groups.yahoo.com/group/Siemens-Gigaset
- Siemens Gigaset/T-Sinus compatibility table
http://www.erbze.info/sinus_gigaset.htm
+ (archived at https://web.archive.org/web/20100717020421/http://www.erbze.info:80/sinus_gigaset.htm )
5. Credits
diff --git a/Documentation/kbuild/kbuild.txt b/Documentation/kbuild/kbuild.txt
index ac2363ea05c5..6c9c69ec3986 100644
--- a/Documentation/kbuild/kbuild.txt
+++ b/Documentation/kbuild/kbuild.txt
@@ -50,10 +50,6 @@ LDFLAGS_MODULE
--------------------------------------------------
Additional options used for $(LD) when linking modules.
-LDFLAGS_vmlinux
---------------------------------------------------
-Additional options passed to final link of vmlinux.
-
KBUILD_VERBOSE
--------------------------------------------------
Set the kbuild verbosity. Can be assigned same values as "V=...".
diff --git a/Documentation/kbuild/kconfig.txt b/Documentation/kbuild/kconfig.txt
index bbc99c0c1094..7233118f3a05 100644
--- a/Documentation/kbuild/kconfig.txt
+++ b/Documentation/kbuild/kconfig.txt
@@ -119,7 +119,7 @@ Examples:
15% of tristates will be set to 'y', 15% to 'm', 70% to 'n'
______________________________________________________________________
-Environment variables for 'silentoldconfig'
+Environment variables for 'syncconfig'
KCONFIG_NOSILENTUPDATE
--------------------------------------------------
diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
index 71e9feefb63c..048fc39a6b91 100644
--- a/Documentation/kbuild/makefiles.txt
+++ b/Documentation/kbuild/makefiles.txt
@@ -153,12 +153,18 @@ more details, with real examples.
configuration.
Kbuild compiles all the $(obj-y) files. It then calls
- "$(LD) -r" to merge these files into one built-in.o file.
- built-in.o is later linked into vmlinux by the parent Makefile.
+ "$(AR) rcSTP" to merge these files into one built-in.a file.
+ This is a thin archive without a symbol table, which makes it
+ unsuitable as a linker input.
+
+ The scripts/link-vmlinux.sh script later makes an aggregate
+ built-in.a with "${AR} rcsTP", which creates the thin archive
+ with a symbol table and an index, making it a valid input for
+ the final vmlinux link passes.
The order of files in $(obj-y) is significant. Duplicates in
the lists are allowed: the first instance will be linked into
- built-in.o and succeeding instances will be ignored.
+ built-in.a and succeeding instances will be ignored.
Link order is significant, because certain functions
(module_init() / __initcall) will be called during boot in the
@@ -222,7 +228,7 @@ more details, with real examples.
Note: Of course, when you are building objects into the kernel,
the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
kbuild will build an ext2.o file for you out of the individual
- parts and then link this into built-in.o, as you would expect.
+ parts and then link this into built-in.a, as you would expect.
--- 3.4 Objects which export symbols
@@ -232,7 +238,7 @@ more details, with real examples.
--- 3.5 Library file goals - lib-y
Objects listed with obj-* are used for modules, or
- combined in a built-in.o for that specific directory.
+ combined in a built-in.a for that specific directory.
There is also the possibility to list objects that will
be included in a library, lib.a.
All objects listed with lib-y are combined in a single
@@ -244,7 +250,7 @@ more details, with real examples.
Note that the same kbuild makefile may list files to be built-in
and to be part of a library. Therefore the same directory
- may contain both a built-in.o and a lib.a file.
+ may contain both a built-in.a and a lib.a file.
Example:
#arch/x86/lib/Makefile
@@ -831,12 +837,6 @@ When kbuild executes, the following steps are followed (roughly):
Note: ldflags-y can be used to further customise
the flags used. See chapter 3.7.
- LDFLAGS_MODULE Options for $(LD) when linking modules
-
- LDFLAGS_MODULE is used to set specific flags for $(LD) when
- linking the .ko files used for modules.
- Default is "-r", for relocatable output.
-
LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
LDFLAGS_vmlinux is used to specify additional flags to pass to
@@ -986,7 +986,7 @@ When kbuild executes, the following steps are followed (roughly):
$(head-y) lists objects to be linked first in vmlinux.
$(libs-y) lists directories where a lib.a archive can be located.
- The rest list directories where a built-in.o object file can be
+ The rest list directories where a built-in.a object file can be
located.
$(init-y) objects will be located after $(head-y).
@@ -1071,7 +1071,7 @@ When kbuild executes, the following steps are followed (roughly):
extra-y := head.o init_task.o
In this example, extra-y is used to list object files that
- shall be built, but shall not be linked as part of built-in.o.
+ shall be built, but shall not be linked as part of built-in.a.
--- 6.7 Commands useful for building a boot image
diff --git a/Documentation/locking/lockdep-design.txt b/Documentation/locking/lockdep-design.txt
index 9de1c158d44c..49f58a07ee7b 100644
--- a/Documentation/locking/lockdep-design.txt
+++ b/Documentation/locking/lockdep-design.txt
@@ -27,7 +27,8 @@ lock-class.
State
-----
-The validator tracks lock-class usage history into 4n + 1 separate state bits:
+The validator tracks lock-class usage history into 4 * nSTATEs + 1 separate
+state bits:
- 'ever held in STATE context'
- 'ever held as readlock in STATE context'
@@ -37,7 +38,6 @@ The validator tracks lock-class usage history into 4n + 1 separate state bits:
Where STATE can be either one of (kernel/locking/lockdep_states.h)
- hardirq
- softirq
- - reclaim_fs
- 'ever used' [ == !unused ]
@@ -169,6 +169,53 @@ Note: When changing code to use the _nested() primitives, be careful and
check really thoroughly that the hierarchy is correctly mapped; otherwise
you can get false positives or false negatives.
+Annotations
+-----------
+
+Two constructs can be used to annotate and check where and if certain locks
+must be held: lockdep_assert_held*(&lock) and lockdep_*pin_lock(&lock).
+
+As the name suggests, lockdep_assert_held* family of macros assert that a
+particular lock is held at a certain time (and generate a WARN() otherwise).
+This annotation is largely used all over the kernel, e.g. kernel/sched/
+core.c
+
+ void update_rq_clock(struct rq *rq)
+ {
+ s64 delta;
+
+ lockdep_assert_held(&rq->lock);
+ [...]
+ }
+
+where holding rq->lock is required to safely update a rq's clock.
+
+The other family of macros is lockdep_*pin_lock(), which is admittedly only
+used for rq->lock ATM. Despite their limited adoption these annotations
+generate a WARN() if the lock of interest is "accidentally" unlocked. This turns
+out to be especially helpful to debug code with callbacks, where an upper
+layer assumes a lock remains taken, but a lower layer thinks it can maybe drop
+and reacquire the lock ("unwittingly" introducing races). lockdep_pin_lock()
+returns a 'struct pin_cookie' that is then used by lockdep_unpin_lock() to check
+that nobody tampered with the lock, e.g. kernel/sched/sched.h
+
+ static inline void rq_pin_lock(struct rq *rq, struct rq_flags *rf)
+ {
+ rf->cookie = lockdep_pin_lock(&rq->lock);
+ [...]
+ }
+
+ static inline void rq_unpin_lock(struct rq *rq, struct rq_flags *rf)
+ {
+ [...]
+ lockdep_unpin_lock(&rq->lock, rf->cookie);
+ }
+
+While comments about locking requirements might provide useful information,
+the runtime checks performed by annotations are invaluable when debugging
+locking problems and they carry the same level of details when inspecting
+code. Always prefer annotations when in doubt!
+
Proof of 100% correctness:
--------------------------
diff --git a/Documentation/media/kapi/cec-core.rst b/Documentation/media/kapi/cec-core.rst
index 62b9a1448177..a9f53f069a2d 100644
--- a/Documentation/media/kapi/cec-core.rst
+++ b/Documentation/media/kapi/cec-core.rst
@@ -110,11 +110,14 @@ your driver:
void (*adap_status)(struct cec_adapter *adap, struct seq_file *file);
void (*adap_free)(struct cec_adapter *adap);
+ /* Error injection callbacks */
+ ...
+
/* High-level callbacks */
...
};
-The five low-level ops deal with various aspects of controlling the CEC adapter
+The seven low-level ops deal with various aspects of controlling the CEC adapter
hardware:
@@ -286,6 +289,70 @@ handling the receive interrupt. The framework expects to see the cec_transmit_do
call before the cec_received_msg call, otherwise it can get confused if the
received message was in reply to the transmitted message.
+Optional: Implementing Error Injection Support
+----------------------------------------------
+
+If the CEC adapter supports Error Injection functionality, then that can
+be exposed through the Error Injection callbacks:
+
+.. code-block:: none
+
+ struct cec_adap_ops {
+ /* Low-level callbacks */
+ ...
+
+ /* Error injection callbacks */
+ int (*error_inj_show)(struct cec_adapter *adap, struct seq_file *sf);
+ bool (*error_inj_parse_line)(struct cec_adapter *adap, char *line);
+
+ /* High-level CEC message callback */
+ ...
+ };
+
+If both callbacks are set, then an ``error-inj`` file will appear in debugfs.
+The basic syntax is as follows:
+
+Leading spaces/tabs are ignored. If the next character is a ``#`` or the end of the
+line was reached, then the whole line is ignored. Otherwise a command is expected.
+
+This basic parsing is done in the CEC Framework. It is up to the driver to decide
+what commands to implement. The only requirement is that the command ``clear`` without
+any arguments must be implemented and that it will remove all current error injection
+commands.
+
+This ensures that you can always do ``echo clear >error-inj`` to clear any error
+injections without having to know the details of the driver-specific commands.
+
+Note that the output of ``error-inj`` shall be valid as input to ``error-inj``.
+So this must work:
+
+.. code-block:: none
+
+ $ cat error-inj >einj.txt
+ $ cat einj.txt >error-inj
+
+The first callback is called when this file is read and it should show the
+the current error injection state:
+
+.. c:function::
+ int (*error_inj_show)(struct cec_adapter *adap, struct seq_file *sf);
+
+It is recommended that it starts with a comment block with basic usage
+information. It returns 0 for success and an error otherwise.
+
+The second callback will parse commands written to the ``error-inj`` file:
+
+.. c:function::
+ bool (*error_inj_parse_line)(struct cec_adapter *adap, char *line);
+
+The ``line`` argument points to the start of the command. Any leading
+spaces or tabs have already been skipped. It is a single line only (so there
+are no embedded newlines) and it is 0-terminated. The callback is free to
+modify the contents of the buffer. It is only called for lines containing a
+command, so this callback is never called for empty lines or comment lines.
+
+Return true if the command was valid or false if there were syntax errors.
+
Implementing the High-Level CEC Adapter
---------------------------------------
@@ -298,6 +365,9 @@ CEC protocol driven. The following high-level callbacks are available:
/* Low-level callbacks */
...
+ /* Error injection callbacks */
+ ...
+
/* High-level CEC message callback */
int (*received)(struct cec_adapter *adap, struct cec_msg *msg);
};
diff --git a/Documentation/media/kapi/v4l2-dev.rst b/Documentation/media/kapi/v4l2-dev.rst
index 7bb0505b60f1..eb03ccc41c41 100644
--- a/Documentation/media/kapi/v4l2-dev.rst
+++ b/Documentation/media/kapi/v4l2-dev.rst
@@ -31,7 +31,7 @@ of the video device exits.
The default :c:func:`video_device_release` callback currently
just calls ``kfree`` to free the allocated memory.
-There is also a ::c:func:`video_device_release_empty` function that does
+There is also a :c:func:`video_device_release_empty` function that does
nothing (is empty) and should be used if the struct is embedded and there
is nothing to do when it is released.
diff --git a/Documentation/media/lirc.h.rst.exceptions b/Documentation/media/lirc.h.rst.exceptions
index c6e3a35d2c4e..984b61dc3f2e 100644
--- a/Documentation/media/lirc.h.rst.exceptions
+++ b/Documentation/media/lirc.h.rst.exceptions
@@ -57,6 +57,7 @@ ignore symbol RC_PROTO_RC6_MCE
ignore symbol RC_PROTO_SHARP
ignore symbol RC_PROTO_XMP
ignore symbol RC_PROTO_CEC
+ignore symbol RC_PROTO_IMON
# Undocumented macros
diff --git a/Documentation/media/uapi/cec/cec-api.rst b/Documentation/media/uapi/cec/cec-api.rst
index b68ca9c1d2e0..1e2cf498ba30 100644
--- a/Documentation/media/uapi/cec/cec-api.rst
+++ b/Documentation/media/uapi/cec/cec-api.rst
@@ -23,6 +23,7 @@ This part describes the CEC: Consumer Electronics Control
cec-intro
cec-funcs
+ cec-pin-error-inj
cec-header
diff --git a/Documentation/media/uapi/cec/cec-pin-error-inj.rst b/Documentation/media/uapi/cec/cec-pin-error-inj.rst
new file mode 100644
index 000000000000..464b006dbe0a
--- /dev/null
+++ b/Documentation/media/uapi/cec/cec-pin-error-inj.rst
@@ -0,0 +1,325 @@
+CEC Pin Framework Error Injection
+=================================
+
+The CEC Pin Framework is a core CEC framework for CEC hardware that only
+has low-level support for the CEC bus. Most hardware today will have
+high-level CEC support where the hardware deals with driving the CEC bus,
+but some older devices aren't that fancy. However, this framework also
+allows you to connect the CEC pin to a GPIO on e.g. a Raspberry Pi and
+you have now made a CEC adapter.
+
+What makes doing this so interesting is that since we have full control
+over the bus it is easy to support error injection. This is ideal to
+test how well CEC adapters can handle error conditions.
+
+Currently only the cec-gpio driver (when the CEC line is directly
+connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
+support this framework.
+
+If ``CONFIG_CEC_PIN_ERROR_INJ`` is enabled, then error injection is available
+through debugfs. Specifically, in ``/sys/kernel/debug/cec/cecX/`` there is
+now an ``error-inj`` file.
+
+.. note::
+
+ The error injection commands are not a stable ABI and may change in the
+ future.
+
+With ``cat error-inj`` you can see both the possible commands and the current
+error injection status::
+
+ $ cat /sys/kernel/debug/cec/cec0/error-inj
+ # Clear error injections:
+ # clear clear all rx and tx error injections
+ # rx-clear clear all rx error injections
+ # tx-clear clear all tx error injections
+ # <op> clear clear all rx and tx error injections for <op>
+ # <op> rx-clear clear all rx error injections for <op>
+ # <op> tx-clear clear all tx error injections for <op>
+ #
+ # RX error injection:
+ # <op>[,<mode>] rx-nack NACK the message instead of sending an ACK
+ # <op>[,<mode>] rx-low-drive <bit> force a low-drive condition at this bit position
+ # <op>[,<mode>] rx-add-byte add a spurious byte to the received CEC message
+ # <op>[,<mode>] rx-remove-byte remove the last byte from the received CEC message
+ # <op>[,<mode>] rx-arb-lost <poll> generate a POLL message to trigger an arbitration lost
+ #
+ # TX error injection settings:
+ # tx-ignore-nack-until-eom ignore early NACKs until EOM
+ # tx-custom-low-usecs <usecs> define the 'low' time for the custom pulse
+ # tx-custom-high-usecs <usecs> define the 'high' time for the custom pulse
+ # tx-custom-pulse transmit the custom pulse once the bus is idle
+ #
+ # TX error injection:
+ # <op>[,<mode>] tx-no-eom don't set the EOM bit
+ # <op>[,<mode>] tx-early-eom set the EOM bit one byte too soon
+ # <op>[,<mode>] tx-add-bytes <num> append <num> (1-255) spurious bytes to the message
+ # <op>[,<mode>] tx-remove-byte drop the last byte from the message
+ # <op>[,<mode>] tx-short-bit <bit> make this bit shorter than allowed
+ # <op>[,<mode>] tx-long-bit <bit> make this bit longer than allowed
+ # <op>[,<mode>] tx-custom-bit <bit> send the custom pulse instead of this bit
+ # <op>[,<mode>] tx-short-start send a start pulse that's too short
+ # <op>[,<mode>] tx-long-start send a start pulse that's too long
+ # <op>[,<mode>] tx-custom-start send the custom pulse instead of the start pulse
+ # <op>[,<mode>] tx-last-bit <bit> stop sending after this bit
+ # <op>[,<mode>] tx-low-drive <bit> force a low-drive condition at this bit position
+ #
+ # <op> CEC message opcode (0-255) or 'any'
+ # <mode> 'once' (default), 'always', 'toggle' or 'off'
+ # <bit> CEC message bit (0-159)
+ # 10 bits per 'byte': bits 0-7: data, bit 8: EOM, bit 9: ACK
+ # <poll> CEC poll message used to test arbitration lost (0x00-0xff, default 0x0f)
+ # <usecs> microseconds (0-10000000, default 1000)
+
+ clear
+
+You can write error injection commands to ``error-inj`` using
+``echo 'cmd' >error-inj`` or ``cat cmd.txt >error-inj``. The ``cat error-inj``
+output contains the current error commands. You can save the output to a file
+and use it as an input to ``error-inj`` later.
+
+Basic Syntax
+------------
+
+Leading spaces/tabs are ignored. If the next character is a ``#`` or the end
+of the line was reached, then the whole line is ignored. Otherwise a command
+is expected.
+
+The error injection commands fall in two main groups: those relating to
+receiving CEC messages and those relating to transmitting CEC messages. In
+addition, there are commands to clear existing error injection commands and
+to create custom pulses on the CEC bus.
+
+Most error injection commands can be executed for specific CEC opcodes or for
+all opcodes (``any``). Each command also has a 'mode' which can be ``off``
+(can be used to turn off an existing error injection command), ``once``
+(the default) which will trigger the error injection only once for the next
+received or transmitted message, ``always`` to always trigger the error
+injection and ``toggle`` to toggle the error injection on or off for every
+transmit or receive.
+
+So '``any rx-nack``' will NACK the next received CEC message,
+'``any,always rx-nack``' will NACK all received CEC messages and
+'``0x82,toggle rx-nack``' will only NACK if an Active Source message was
+received and do that only for every other received message.
+
+After an error was injected with mode ``once`` the error injection command
+is cleared automatically, so ``once`` is a one-time deal.
+
+All combinations of ``<op>`` and error injection commands can co-exist. So
+this is fine::
+
+ 0x9e tx-add-bytes 1
+ 0x9e tx-early-eom
+ 0x9f tx-add-bytes 2
+ any rx-nack
+
+All four error injection commands will be active simultaneously.
+
+However, if the same ``<op>`` and command combination is specified,
+but with different arguments::
+
+ 0x9e tx-add-bytes 1
+ 0x9e tx-add-bytes 2
+
+Then the second will overwrite the first.
+
+Clear Error Injections
+----------------------
+
+``clear``
+ Clear all error injections.
+
+``rx-clear``
+ Clear all receive error injections
+
+``tx-clear``
+ Clear all transmit error injections
+
+``<op> clear``
+ Clear all error injections for the given opcode.
+
+``<op> rx-clear``
+ Clear all receive error injections for the given opcode.
+
+``<op> tx-clear``
+ Clear all transmit error injections for the given opcode.
+
+Receive Messages
+----------------
+
+``<op>[,<mode>] rx-nack``
+ NACK broadcast messages and messages directed to this CEC adapter.
+ Every byte of the message will be NACKed in case the transmitter
+ keeps transmitting after the first byte was NACKed.
+
+``<op>[,<mode>] rx-low-drive <bit>``
+ Force a Low Drive condition at this bit position. If <op> specifies
+ a specific CEC opcode then the bit position must be at least 18,
+ otherwise the opcode hasn't been received yet. This tests if the
+ transmitter can handle the Low Drive condition correctly and reports
+ the error correctly. Note that a Low Drive in the first 4 bits can also
+ be interpreted as an Arbitration Lost condition by the transmitter.
+ This is implementation dependent.
+
+``<op>[,<mode>] rx-add-byte``
+ Add a spurious 0x55 byte to the received CEC message, provided
+ the message was 15 bytes long or less. This is useful to test
+ the high-level protocol since spurious bytes should be ignored.
+
+``<op>[,<mode>] rx-remove-byte``
+ Remove the last byte from the received CEC message, provided it
+ was at least 2 bytes long. This is useful to test the high-level
+ protocol since messages that are too short should be ignored.
+
+``<op>[,<mode>] rx-arb-lost <poll>``
+ Generate a POLL message to trigger an Arbitration Lost condition.
+ This command is only allowed for ``<op>`` values of ``next`` or ``all``.
+ As soon as a start bit has been received the CEC adapter will switch
+ to transmit mode and it will transmit a POLL message. By default this is
+ 0x0f, but it can also be specified explicitly via the ``<poll>`` argument.
+
+ This command can be used to test the Arbitration Lost condition in
+ the remote CEC transmitter. Arbitration happens when two CEC adapters
+ start sending a message at the same time. In that case the initiator
+ with the most leading zeroes wins and the other transmitter has to
+ stop transmitting ('Arbitration Lost'). This is very hard to test,
+ except by using this error injection command.
+
+ This does not work if the remote CEC transmitter has logical address
+ 0 ('TV') since that will always win.
+
+Transmit Messages
+-----------------
+
+``tx-ignore-nack-until-eom``
+ This setting changes the behavior of transmitting CEC messages. Normally
+ as soon as the receiver NACKs a byte the transmit will stop, but the
+ specification also allows that the full message is transmitted and only
+ at the end will the transmitter look at the ACK bit. This is not
+ recommended behavior since there is no point in keeping the CEC bus busy
+ for longer than is strictly needed. Especially given how slow the bus is.
+
+ This setting can be used to test how well a receiver deals with
+ transmitters that ignore NACKs until the very end of the message.
+
+``<op>[,<mode>] tx-no-eom``
+ Don't set the EOM bit. Normally the last byte of the message has the EOM
+ (End-Of-Message) bit set. With this command the transmit will just stop
+ without ever sending an EOM. This can be used to test how a receiver
+ handles this case. Normally receivers have a time-out after which
+ they will go back to the Idle state.
+
+``<op>[,<mode>] tx-early-eom``
+ Set the EOM bit one byte too soon. This obviously only works for messages
+ of two bytes or more. The EOM bit will be set for the second-to-last byte
+ and not for the final byte. The receiver should ignore the last byte in
+ this case. Since the resulting message is likely to be too short for this
+ same reason the whole message is typically ignored. The receiver should be
+ in Idle state after the last byte was transmitted.
+
+``<op>[,<mode>] tx-add-bytes <num>``
+ Append ``<num>`` (1-255) spurious bytes to the message. The extra bytes
+ have the value of the byte position in the message. So if you transmit a
+ two byte message (e.g. a Get CEC Version message) and add 2 bytes, then
+ the full message received by the remote CEC adapter is
+ ``0x40 0x9f 0x02 0x03``.
+
+ This command can be used to test buffer overflows in the receiver. E.g.
+ what does it do when it receives more than the maximum message size of 16
+ bytes.
+
+``<op>[,<mode>] tx-remove-byte``
+ Drop the last byte from the message, provided the message is at least
+ two bytes long. The receiver should ignore messages that are too short.
+
+``<op>[,<mode>] tx-short-bit <bit>``
+ Make this bit period shorter than allowed. The bit position cannot be
+ an Ack bit. If <op> specifies a specific CEC opcode then the bit position
+ must be at least 18, otherwise the opcode hasn't been received yet.
+ Normally the period of a data bit is between 2.05 and 2.75 milliseconds.
+ With this command the period of this bit is 1.8 milliseconds, this is
+ done by reducing the time the CEC bus is high. This bit period is less
+ than is allowed and the receiver should respond with a Low Drive
+ condition.
+
+ This command is ignored for 0 bits in bit positions 0 to 3. This is
+ because the receiver also looks for an Arbitration Lost condition in
+ those first four bits and it is undefined what will happen if it
+ sees a too-short 0 bit.
+
+``<op>[,<mode>] tx-long-bit <bit>``
+ Make this bit period longer than is valid. The bit position cannot be
+ an Ack bit. If <op> specifies a specific CEC opcode then the bit position
+ must be at least 18, otherwise the opcode hasn't been received yet.
+ Normally the period of a data bit is between 2.05 and 2.75 milliseconds.
+ With this command the period of this bit is 2.9 milliseconds, this is
+ done by increasing the time the CEC bus is high.
+
+ Even though this bit period is longer than is valid it is undefined what
+ a receiver will do. It might just accept it, or it might time out and
+ return to Idle state. Unfortunately the CEC specification is silent about
+ this.
+
+ This command is ignored for 0 bits in bit positions 0 to 3. This is
+ because the receiver also looks for an Arbitration Lost condition in
+ those first four bits and it is undefined what will happen if it
+ sees a too-long 0 bit.
+
+``<op>[,<mode>] tx-short-start``
+ Make this start bit period shorter than allowed. Normally the period of
+ a start bit is between 4.3 and 4.7 milliseconds. With this command the
+ period of the start bit is 4.1 milliseconds, this is done by reducing
+ the time the CEC bus is high. This start bit period is less than is
+ allowed and the receiver should return to Idle state when this is detected.
+
+``<op>[,<mode>] tx-long-start``
+ Make this start bit period longer than is valid. Normally the period of
+ a start bit is between 4.3 and 4.7 milliseconds. With this command the
+ period of the start bit is 5 milliseconds, this is done by increasing
+ the time the CEC bus is high. This start bit period is more than is
+ valid and the receiver should return to Idle state when this is detected.
+
+ Even though this start bit period is longer than is valid it is undefined
+ what a receiver will do. It might just accept it, or it might time out and
+ return to Idle state. Unfortunately the CEC specification is silent about
+ this.
+
+``<op>[,<mode>] tx-last-bit <bit>``
+ Just stop transmitting after this bit. If <op> specifies a specific CEC
+ opcode then the bit position must be at least 18, otherwise the opcode
+ hasn't been received yet. This command can be used to test how the receiver
+ reacts when a message just suddenly stops. It should time out and go back
+ to Idle state.
+
+``<op>[,<mode>] tx-low-drive <bit>``
+ Force a Low Drive condition at this bit position. If <op> specifies a
+ specific CEC opcode then the bit position must be at least 18, otherwise
+ the opcode hasn't been received yet. This can be used to test how the
+ receiver handles Low Drive conditions. Note that if this happens at bit
+ positions 0-3 the receiver can interpret this as an Arbitration Lost
+ condition. This is implementation dependent.
+
+Custom Pulses
+-------------
+
+``tx-custom-low-usecs <usecs>``
+ This defines the duration in microseconds that the custom pulse pulls
+ the CEC line low. The default is 1000 microseconds.
+
+``tx-custom-high-usecs <usecs>``
+ This defines the duration in microseconds that the custom pulse keeps the
+ CEC line high (unless another CEC adapter pulls it low in that time).
+ The default is 1000 microseconds. The total period of the custom pulse is
+ ``tx-custom-low-usecs + tx-custom-high-usecs``.
+
+``<op>[,<mode>] tx-custom-bit <bit>``
+ Send the custom bit instead of a regular data bit. The bit position cannot
+ be an Ack bit. If <op> specifies a specific CEC opcode then the bit
+ position must be at least 18, otherwise the opcode hasn't been received yet.
+
+``<op>[,<mode>] tx-custom-start``
+ Send the custom bit instead of a regular start bit.
+
+``tx-custom-pulse``
+ Transmit a single custom pulse as soon as the CEC bus is idle.
diff --git a/Documentation/media/uapi/mediactl/media-ioc-enum-entities.rst b/Documentation/media/uapi/mediactl/media-ioc-enum-entities.rst
index b59ce149efb5..582fda488810 100644
--- a/Documentation/media/uapi/mediactl/media-ioc-enum-entities.rst
+++ b/Documentation/media/uapi/mediactl/media-ioc-enum-entities.rst
@@ -89,7 +89,7 @@ id's until they get an error.
-
-
- - Entity type, see :ref:`media-entity-type` for details.
+ - Entity type, see :ref:`media-entity-functions` for details.
- .. row 4
@@ -144,10 +144,21 @@ id's until they get an error.
- .. row 9
- - union
+ - __u32
+
+ - ``reserved[4]``
+
+ -
+ -
+ - Reserved for future extensions. Drivers and applications must set
+ the array to zero.
- .. row 10
+ - union
+
+ - .. row 11
+
-
- struct
@@ -156,7 +167,7 @@ id's until they get an error.
-
- Valid for (sub-)devices that create a single device node.
- - .. row 11
+ - .. row 12
-
-
@@ -166,7 +177,7 @@ id's until they get an error.
- Device node major number.
- - .. row 12
+ - .. row 13
-
-
@@ -176,7 +187,7 @@ id's until they get an error.
- Device node minor number.
- - .. row 13
+ - .. row 14
-
- __u8
diff --git a/Documentation/media/uapi/mediactl/media-ioc-enum-links.rst b/Documentation/media/uapi/mediactl/media-ioc-enum-links.rst
index d05be16ffaf6..256168b3c3be 100644
--- a/Documentation/media/uapi/mediactl/media-ioc-enum-links.rst
+++ b/Documentation/media/uapi/mediactl/media-ioc-enum-links.rst
@@ -125,6 +125,15 @@ returned during the enumeration process.
- Pad flags, see :ref:`media-pad-flag` for more details.
+ - .. row 4
+
+ - __u32
+
+ - ``reserved[2]``
+
+ - Reserved for future extensions. Drivers and applications must set
+ the array to zero.
+
.. c:type:: media_link_desc
@@ -161,6 +170,15 @@ returned during the enumeration process.
- Link flags, see :ref:`media-link-flag` for more details.
+ - .. row 4
+
+ - __u32
+
+ - ``reserved[4]``
+
+ - Reserved for future extensions. Drivers and applications must set
+ the array to zero.
+
Return Value
============
diff --git a/Documentation/media/uapi/mediactl/media-ioc-g-topology.rst b/Documentation/media/uapi/mediactl/media-ioc-g-topology.rst
index 997e6b17440d..c4055ddf070a 100644
--- a/Documentation/media/uapi/mediactl/media-ioc-g-topology.rst
+++ b/Documentation/media/uapi/mediactl/media-ioc-g-topology.rst
@@ -68,7 +68,7 @@ desired arrays with the media graph elements.
- .. row 2
- - __u64
+ - __u32
- ``num_entities``
@@ -76,6 +76,14 @@ desired arrays with the media graph elements.
- .. row 3
+ - __u32
+
+ - ``reserved1``
+
+ - Applications and drivers shall set this to 0.
+
+ - .. row 4
+
- __u64
- ``ptr_entities``
@@ -85,15 +93,23 @@ desired arrays with the media graph elements.
the ioctl won't store the entities. It will just update
``num_entities``
- - .. row 4
+ - .. row 5
- - __u64
+ - __u32
- ``num_interfaces``
- Number of interfaces in the graph
- - .. row 5
+ - .. row 6
+
+ - __u32
+
+ - ``reserved2``
+
+ - Applications and drivers shall set this to 0.
+
+ - .. row 7
- __u64
@@ -104,15 +120,23 @@ desired arrays with the media graph elements.
the ioctl won't store the interfaces. It will just update
``num_interfaces``
- - .. row 6
+ - .. row 8
- - __u64
+ - __u32
- ``num_pads``
- Total number of pads in the graph
- - .. row 7
+ - .. row 9
+
+ - __u32
+
+ - ``reserved3``
+
+ - Applications and drivers shall set this to 0.
+
+ - .. row 10
- __u64
@@ -122,15 +146,23 @@ desired arrays with the media graph elements.
converted to a 64-bits integer. It can be zero. if zero, the ioctl
won't store the pads. It will just update ``num_pads``
- - .. row 8
+ - .. row 11
- - __u64
+ - __u32
- ``num_links``
- Total number of data and interface links in the graph
- - .. row 9
+ - .. row 12
+
+ - __u32
+
+ - ``reserved4``
+
+ - Applications and drivers shall set this to 0.
+
+ - .. row 13
- __u64
@@ -173,13 +205,13 @@ desired arrays with the media graph elements.
- ``function``
- - Entity main function, see :ref:`media-entity-type` for details.
+ - Entity main function, see :ref:`media-entity-functions` for details.
- .. row 4
- __u32
- - ``reserved``\ [12]
+ - ``reserved``\ [6]
- Reserved for future extensions. Drivers and applications must set
this array to zero.
@@ -302,7 +334,7 @@ desired arrays with the media graph elements.
- __u32
- - ``reserved``\ [9]
+ - ``reserved``\ [5]
- Reserved for future extensions. Drivers and applications must set
this array to zero.
@@ -334,7 +366,7 @@ desired arrays with the media graph elements.
- On pad to pad links: unique ID for the source pad.
- On interface to entity links: unique ID for the entity.
+ On interface to entity links: unique ID for the interface.
- .. row 3
@@ -358,7 +390,7 @@ desired arrays with the media graph elements.
- __u32
- - ``reserved``\ [5]
+ - ``reserved``\ [6]
- Reserved for future extensions. Drivers and applications must set
this array to zero.
diff --git a/Documentation/media/uapi/mediactl/media-types.rst b/Documentation/media/uapi/mediactl/media-types.rst
index 8d64b0c06ebc..2dda14bd89b7 100644
--- a/Documentation/media/uapi/mediactl/media-types.rst
+++ b/Documentation/media/uapi/mediactl/media-types.rst
@@ -7,11 +7,11 @@ Types and flags used to represent the media graph elements
.. tabularcolumns:: |p{8.2cm}|p{10.3cm}|
-.. _media-entity-type:
+.. _media-entity-functions:
.. cssclass:: longtable
-.. flat-table:: Media entity types
+.. flat-table:: Media entity functions
:header-rows: 0
:stub-columns: 0
@@ -26,7 +26,7 @@ Types and flags used to represent the media graph elements
``MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN``
- Unknown entity. That generally indicates that a driver didn't
- initialize properly the entity, with is a Kernel bug
+ initialize properly the entity, which is a Kernel bug
- .. row 2
@@ -293,7 +293,7 @@ Types and flags used to represent the media graph elements
- ``MEDIA_ENT_F_PROC_VIDEO_STATISTICS``
- - Video statistics computation (histogram, 3A, ...). An entity
+ - Video statistics computation (histogram, 3A, etc.). An entity
capable of statistics computation must have one sink pad and
one source pad. It computes statistics over the frames
received on its sink pad and outputs the statistics data on
@@ -318,8 +318,19 @@ Types and flags used to represent the media graph elements
- Video interface bridge. A video interface bridge entity must have at
least one sink pad and at least one source pad. It receives video
frames on its sink pad from an input video bus of one type (HDMI, eDP,
- MIPI CSI-2, ...), and outputs them on its source pad to an output
- video bus of another type (eDP, MIPI CSI-2, parallel, ...).
+ MIPI CSI-2, etc.), and outputs them on its source pad to an output
+ video bus of another type (eDP, MIPI CSI-2, parallel, etc.).
+
+ - .. row 31
+
+ .. _MEDIA-ENT-F-DTV-DECODER:
+
+ - ``MEDIA_ENT_F_DTV_DECODER``
+
+ - Digital video decoder. The basic function of the video decoder is
+ to accept digital video from a wide variety of sources
+ and output it in some digital video standard, with appropriate
+ timing signals.
.. tabularcolumns:: |p{5.5cm}|p{12.0cm}|
@@ -337,7 +348,7 @@ Types and flags used to represent the media graph elements
- ``MEDIA_ENT_FL_DEFAULT``
- Default entity for its type. Used to discover the default audio,
- VBI and video devices, the default camera sensor, ...
+ VBI and video devices, the default camera sensor, etc.
- .. row 2
@@ -345,7 +356,7 @@ Types and flags used to represent the media graph elements
- ``MEDIA_ENT_FL_CONNECTOR``
- - The entity represents a data conector
+ - The entity represents a connector.
.. tabularcolumns:: |p{6.5cm}|p{6.0cm}|p{5.0cm}|
diff --git a/Documentation/media/uapi/rc/lirc-dev-intro.rst b/Documentation/media/uapi/rc/lirc-dev-intro.rst
index 3a74fec66d69..698e4f80270e 100644
--- a/Documentation/media/uapi/rc/lirc-dev-intro.rst
+++ b/Documentation/media/uapi/rc/lirc-dev-intro.rst
@@ -18,7 +18,6 @@ Example dmesg output upon a driver registering w/LIRC:
.. code-block:: none
$ dmesg |grep lirc_dev
- lirc_dev: IR Remote Control driver registered, major 248
rc rc0: lirc_dev: driver mceusb registered at minor = 0
What you should see for a chardev:
diff --git a/Documentation/media/uapi/v4l/buffer.rst b/Documentation/media/uapi/v4l/buffer.rst
index ae6ee73f151c..e2c85ddc990b 100644
--- a/Documentation/media/uapi/v4l/buffer.rst
+++ b/Documentation/media/uapi/v4l/buffer.rst
@@ -13,7 +13,7 @@ Only pointers to buffers (planes) are exchanged, the data itself is not
copied. These pointers, together with meta-information like timestamps
or field parity, are stored in a struct :c:type:`v4l2_buffer`,
argument to the :ref:`VIDIOC_QUERYBUF`,
-:ref:`VIDIOC_QBUF` and
+:ref:`VIDIOC_QBUF <VIDIOC_QBUF>` and
:ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl. In the multi-planar API,
some plane-specific members of struct :c:type:`v4l2_buffer`,
such as pointers and sizes for each plane, are stored in struct
diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst
index dfe49ae57e78..03931f9b1285 100644
--- a/Documentation/media/uapi/v4l/extended-controls.rst
+++ b/Documentation/media/uapi/v4l/extended-controls.rst
@@ -1960,6 +1960,416 @@ enum v4l2_vp8_golden_frame_sel -
1, 2 and 3 corresponding to encoder profiles 0, 1, 2 and 3.
+High Efficiency Video Coding (HEVC/H.265) Control Reference
+-----------------------------------------------------------
+
+The HEVC/H.265 controls include controls for encoding parameters of HEVC/H.265
+video codec.
+
+
+.. _hevc-control-id:
+
+HEVC/H.265 Control IDs
+^^^^^^^^^^^^^^^^^^^^^^
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP (integer)``
+ Minimum quantization parameter for HEVC.
+ Valid range: from 0 to 51.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP (integer)``
+ Maximum quantization parameter for HEVC.
+ Valid range: from 0 to 51.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP (integer)``
+ Quantization parameter for an I frame for HEVC.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP (integer)``
+ Quantization parameter for a P frame for HEVC.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP (integer)``
+ Quantization parameter for a B frame for HEVC.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP (boolean)``
+ HIERARCHICAL_QP allows the host to specify the quantization parameter
+ values for each temporal layer through HIERARCHICAL_QP_LAYER. This is
+ valid only if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the
+ control value to 1 enables setting of the QP values for the layers.
+
+.. _v4l2-hevc-hier-coding-type:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE``
+ (enum)
+
+enum v4l2_mpeg_video_hevc_hier_coding_type -
+ Selects the hierarchical coding type for encoding. Possible values are:
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B``
+ - Use the B frame for hierarchical coding.
+ * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P``
+ - Use the P frame for hierarchical coding.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER (integer)``
+ Selects the hierarchical coding layer. In normal encoding
+ (non-hierarchial coding), it should be zero. Possible values are [0, 6].
+ 0 indicates HIERARCHICAL CODING LAYER 0, 1 indicates HIERARCHICAL CODING
+ LAYER 1 and so on.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 0.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 1.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 2.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 3.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 4.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 5.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP (integer)``
+ Indicates quantization parameter for hierarchical coding layer 6.
+ Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+ V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP].
+
+.. _v4l2-hevc-profile:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_PROFILE``
+ (enum)
+
+enum v4l2_mpeg_video_hevc_profile -
+ Select the desired profile for HEVC encoder.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN``
+ - Main profile.
+ * - ``V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE``
+ - Main still picture profile.
+ * - ``V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10``
+ - Main 10 profile.
+
+.. raw:: latex
+
+ \normalsize
+
+
+.. _v4l2-hevc-level:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LEVEL``
+ (enum)
+
+enum v4l2_mpeg_video_hevc_level -
+ Selects the desired level for HEVC encoder.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_1``
+ - Level 1.0
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_2``
+ - Level 2.0
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1``
+ - Level 2.1
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_3``
+ - Level 3.0
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1``
+ - Level 3.1
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_4``
+ - Level 4.0
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1``
+ - Level 4.1
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_5``
+ - Level 5.0
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1``
+ - Level 5.1
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2``
+ - Level 5.2
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_6``
+ - Level 6.0
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1``
+ - Level 6.1
+ * - ``V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2``
+ - Level 6.2
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION (integer)``
+ Indicates the number of evenly spaced subintervals, called ticks, within
+ one second. This is a 16 bit unsigned integer and has a maximum value up to
+ 0xffff and a minimum value of 1.
+
+.. _v4l2-hevc-tier:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_TIER``
+ (enum)
+
+enum v4l2_mpeg_video_hevc_tier -
+ TIER_FLAG specifies tiers information of the HEVC encoded picture. Tier
+ were made to deal with applications that differ in terms of maximum bit
+ rate. Setting the flag to 0 selects HEVC tier as Main tier and setting
+ this flag to 1 indicates High tier. High tier is for applications requiring
+ high bit rates.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_TIER_MAIN``
+ - Main tier.
+ * - ``V4L2_MPEG_VIDEO_HEVC_TIER_HIGH``
+ - High tier.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH (integer)``
+ Selects HEVC maximum coding unit depth.
+
+.. _v4l2-hevc-loop-filter-mode:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE``
+ (enum)
+
+enum v4l2_mpeg_video_hevc_loop_filter_mode -
+ Loop filter mode for HEVC encoder. Possible values are:
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{10.7cm}|p{6.3cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED``
+ - Loop filter is disabled.
+ * - ``V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED``
+ - Loop filter is enabled.
+ * - ``V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY``
+ - Loop filter is disabled at the slice boundary.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2 (integer)``
+ Selects HEVC loop filter beta offset. The valid range is [-6, +6].
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2 (integer)``
+ Selects HEVC loop filter tc offset. The valid range is [-6, +6].
+
+.. _v4l2-hevc-refresh-type:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE``
+ (enum)
+
+enum v4l2_mpeg_video_hevc_hier_refresh_type -
+ Selects refresh type for HEVC encoder.
+ Host has to specify the period into
+ V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{8.0cm}|p{9.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE``
+ - Use the B frame for hierarchical coding.
+ * - ``V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA``
+ - Use CRA (Clean Random Access Unit) picture encoding.
+ * - ``V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR``
+ - Use IDR (Instantaneous Decoding Refresh) picture encoding.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD (integer)``
+ Selects the refresh period for HEVC encoder.
+ This specifies the number of I pictures between two CRA/IDR pictures.
+ This is valid only if REFRESH_TYPE is not 0.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU (boolean)``
+ Indicates HEVC lossless encoding. Setting it to 0 disables lossless
+ encoding. Setting it to 1 enables lossless encoding.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED (boolean)``
+ Indicates constant intra prediction for HEVC encoder. Specifies the
+ constrained intra prediction in which intra largest coding unit (LCU)
+ prediction is performed by using residual data and decoded samples of
+ neighboring intra LCU only. Setting the value to 1 enables constant intra
+ prediction and setting the value to 0 disables constant intra prediction.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT (boolean)``
+ Indicates wavefront parallel processing for HEVC encoder. Setting it to 0
+ disables the feature and setting it to 1 enables the wavefront parallel
+ processing.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB (boolean)``
+ Setting the value to 1 enables combination of P and B frame for HEVC
+ encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID (boolean)``
+ Indicates temporal identifier for HEVC encoder which is enabled by
+ setting the value to 1.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING (boolean)``
+ Indicates bi-linear interpolation is conditionally used in the intra
+ prediction filtering process in the CVS when set to 1. Indicates bi-linear
+ interpolation is not used in the CVS when set to 0.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1 (integer)``
+ Indicates maximum number of merge candidate motion vectors.
+ Values are from 0 to 4.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION (boolean)``
+ Indicates temporal motion vector prediction for HEVC encoder. Setting it to
+ 1 enables the prediction. Setting it to 0 disables the prediction.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE (boolean)``
+ Specifies if HEVC generates a stream with a size of the length field
+ instead of start code pattern. The size of the length field is configurable
+ through the V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD control. Setting
+ the value to 0 disables encoding without startcode pattern. Setting the
+ value to 1 will enables encoding without startcode pattern.
+
+.. _v4l2-hevc-size-of-length-field:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD``
+(enum)
+
+enum v4l2_mpeg_video_hevc_size_of_length_field -
+ Indicates the size of length field.
+ This is valid when encoding WITHOUT_STARTCODE_ENABLE is enabled.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{6.0cm}|p{11.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_0``
+ - Generate start code pattern (Normal).
+ * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_1``
+ - Generate size of length field instead of start code pattern and length is 1.
+ * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_2``
+ - Generate size of length field instead of start code pattern and length is 2.
+ * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_4``
+ - Generate size of length field instead of start code pattern and length is 4.
+
+.. raw:: latex
+
+ \normalsize
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 0 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 1 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 2 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 3 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 4 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 5 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR (integer)``
+ Indicates bit rate for hierarchical coding layer 6 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES (integer)``
+ Selects number of P reference pictures required for HEVC encoder.
+ P-Frame can use 1 or 2 frames for reference.
+
+``V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR (integer)``
+ Indicates whether to generate SPS and PPS at every IDR. Setting it to 0
+ disables generating SPS and PPS at every IDR. Setting it to one enables
+ generating SPS and PPS at every IDR.
+
+
.. _camera-controls:
Camera Control Reference
@@ -3155,7 +3565,7 @@ enum v4l2_dv_it_content_type -
HDMI carries 5V on one of the pins). This is often used to power an
eeprom which contains EDID information, such that the source can
read the EDID even if the sink is in standby/power off. Each bit
- corresponds to an input pad on the transmitter. If an input pad
+ corresponds to an input pad on the receiver. If an input pad
cannot detect whether power is present, then the bit for that pad
will be 0. This read-only control is applicable to DVI-D, HDMI and
DisplayPort connectors.
diff --git a/Documentation/media/uapi/v4l/func-poll.rst b/Documentation/media/uapi/v4l/func-poll.rst
index d0432dc09b05..360bc6523ae2 100644
--- a/Documentation/media/uapi/v4l/func-poll.rst
+++ b/Documentation/media/uapi/v4l/func-poll.rst
@@ -39,7 +39,7 @@ When streaming I/O has been negotiated this function waits until a
buffer has been filled by the capture device and can be dequeued with
the :ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl. For output devices this
function waits until the device is ready to accept a new buffer to be
-queued up with the :ref:`VIDIOC_QBUF` ioctl for
+queued up with the :ref:`VIDIOC_QBUF <VIDIOC_QBUF>` ioctl for
display. When buffers are already in the outgoing queue of the driver
(capture) or the incoming queue isn't full (display) the function
returns immediately.
@@ -52,11 +52,11 @@ flags in the ``revents`` field, output devices the ``POLLOUT`` and
``POLLWRNORM`` flags. When the function timed out it returns a value of
zero, on failure it returns -1 and the ``errno`` variable is set
appropriately. When the application did not call
-:ref:`VIDIOC_STREAMON` the :ref:`poll() <func-poll>`
+:ref:`VIDIOC_STREAMON <VIDIOC_STREAMON>` the :ref:`poll() <func-poll>`
function succeeds, but sets the ``POLLERR`` flag in the ``revents``
field. When the application has called
-:ref:`VIDIOC_STREAMON` for a capture device but
-hasn't yet called :ref:`VIDIOC_QBUF`, the
+:ref:`VIDIOC_STREAMON <VIDIOC_STREAMON>` for a capture device but
+hasn't yet called :ref:`VIDIOC_QBUF <VIDIOC_QBUF>`, the
:ref:`poll() <func-poll>` function succeeds and sets the ``POLLERR`` flag in
the ``revents`` field. For output devices this same situation will cause
:ref:`poll() <func-poll>` to succeed as well, but it sets the ``POLLOUT`` and
diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst
index 728d7ede10fa..abec03937bb3 100644
--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst
+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst
@@ -90,3 +90,8 @@ Compressed Formats
- ``V4L2_PIX_FMT_VP9``
- 'VP90'
- VP9 video elementary stream.
+ * .. _V4L2-PIX-FMT-HEVC:
+
+ - ``V4L2_PIX_FMT_HEVC``
+ - 'HEVC'
+ - HEVC/H.265 video elementary stream.
diff --git a/Documentation/media/uapi/v4l/pixfmt-v4l2-mplane.rst b/Documentation/media/uapi/v4l/pixfmt-v4l2-mplane.rst
index 337e8188caf1..ef52f637d8e9 100644
--- a/Documentation/media/uapi/v4l/pixfmt-v4l2-mplane.rst
+++ b/Documentation/media/uapi/v4l/pixfmt-v4l2-mplane.rst
@@ -55,12 +55,14 @@ describing all planes of that format.
- ``pixelformat``
- The pixel format. Both single- and multi-planar four character
codes can be used.
- * - enum :c:type:`v4l2_field`
+ * - __u32
- ``field``
- - See struct :c:type:`v4l2_pix_format`.
- * - enum :c:type:`v4l2_colorspace`
+ - Field order, from enum :c:type:`v4l2_field`.
+ See struct :c:type:`v4l2_pix_format`.
+ * - __u32
- ``colorspace``
- - See struct :c:type:`v4l2_pix_format`.
+ - Colorspace encoding, from enum :c:type:`v4l2_colorspace`.
+ See struct :c:type:`v4l2_pix_format`.
* - struct :c:type:`v4l2_plane_pix_format`
- ``plane_fmt[VIDEO_MAX_PLANES]``
- An array of structures describing format of each plane this pixel
@@ -73,24 +75,34 @@ describing all planes of that format.
* - __u8
- ``flags``
- Flags set by the application or driver, see :ref:`format-flags`.
- * - enum :c:type:`v4l2_ycbcr_encoding`
+ * - union {
+ - (anonymous)
+ -
+ * - __u8
- ``ycbcr_enc``
- - This information supplements the ``colorspace`` and must be set by
+ - Y'CbCr encoding, from enum :c:type:`v4l2_ycbcr_encoding`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
- * - enum :c:type:`v4l2_hsv_encoding`
+ * - __u8
- ``hsv_enc``
- - This information supplements the ``colorspace`` and must be set by
+ - HSV encoding, from enum :c:type:`v4l2_hsv_encoding`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
- * - enum :c:type:`v4l2_quantization`
+ * - }
+ -
+ -
+ * - __u8
- ``quantization``
- - This information supplements the ``colorspace`` and must be set by
+ - Quantization range, from enum :c:type:`v4l2_quantization`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
- * - enum :c:type:`v4l2_xfer_func`
+ * - __u8
- ``xfer_func``
- - This information supplements the ``colorspace`` and must be set by
+ - Transfer function, from enum :c:type:`v4l2_xfer_func`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
* - __u8
diff --git a/Documentation/media/uapi/v4l/pixfmt-v4l2.rst b/Documentation/media/uapi/v4l/pixfmt-v4l2.rst
index 2ee164c25637..826f2305da01 100644
--- a/Documentation/media/uapi/v4l/pixfmt-v4l2.rst
+++ b/Documentation/media/uapi/v4l/pixfmt-v4l2.rst
@@ -40,9 +40,10 @@ Single-planar format structure
RGB formats in :ref:`rgb-formats`, YUV formats in
:ref:`yuv-formats`, and reserved codes in
:ref:`reserved-formats`
- * - enum :c:type::`v4l2_field`
+ * - __u32
- ``field``
- - Video images are typically interlaced. Applications can request to
+ - Field order, from enum :c:type:`v4l2_field`.
+ Video images are typically interlaced. Applications can request to
capture or output only the top or bottom field, or both fields
interlaced or sequentially stored in one buffer or alternating in
separate buffers. Drivers return the actual field order selected.
@@ -82,9 +83,10 @@ Single-planar format structure
driver. Usually this is ``bytesperline`` times ``height``. When
the image consists of variable length compressed data this is the
maximum number of bytes required to hold an image.
- * - enum :c:type:`v4l2_colorspace`
+ * - __u32
- ``colorspace``
- - This information supplements the ``pixelformat`` and must be set
+ - Image colorspace, from enum :c:type:`v4l2_colorspace`.
+ This information supplements the ``pixelformat`` and must be set
by the driver for capture streams and by the application for
output streams, see :ref:`colorspaces`.
* - __u32
@@ -116,23 +118,33 @@ Single-planar format structure
* - __u32
- ``flags``
- Flags set by the application or driver, see :ref:`format-flags`.
- * - enum :c:type:`v4l2_ycbcr_encoding`
+ * - union {
+ - (anonymous)
+ -
+ * - __u32
- ``ycbcr_enc``
- - This information supplements the ``colorspace`` and must be set by
+ - Y'CbCr encoding, from enum :c:type:`v4l2_ycbcr_encoding`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
- * - enum :c:type:`v4l2_hsv_encoding`
+ * - __u32
- ``hsv_enc``
- - This information supplements the ``colorspace`` and must be set by
+ - HSV encoding, from enum :c:type:`v4l2_hsv_encoding`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
- * - enum :c:type:`v4l2_quantization`
+ * - }
+ -
+ -
+ * - __u32
- ``quantization``
- - This information supplements the ``colorspace`` and must be set by
+ - Quantization range, from enum :c:type:`v4l2_quantization`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
- * - enum :c:type:`v4l2_xfer_func`
+ * - __u32
- ``xfer_func``
- - This information supplements the ``colorspace`` and must be set by
+ - Transfer function, from enum :c:type:`v4l2_xfer_func`.
+ This information supplements the ``colorspace`` and must be set by
the driver for capture streams and by the application for output
streams, see :ref:`colorspaces`.
diff --git a/Documentation/media/uapi/v4l/subdev-formats.rst b/Documentation/media/uapi/v4l/subdev-formats.rst
index b1eea44550e1..9fcabe7f9367 100644
--- a/Documentation/media/uapi/v4l/subdev-formats.rst
+++ b/Documentation/media/uapi/v4l/subdev-formats.rst
@@ -16,10 +16,14 @@ Media Bus Formats
* - __u32
- ``width``
- - Image width, in pixels.
+ - Image width in pixels.
* - __u32
- ``height``
- - Image height, in pixels.
+ - Image height in pixels. If ``field`` is one of ``V4L2_FIELD_TOP``,
+ ``V4L2_FIELD_BOTTOM`` or ``V4L2_FIELD_ALTERNATE`` then height
+ refers to the number of lines in the field, otherwise it refers to
+ the number of lines in the frame (which is twice the field height
+ for interlaced formats).
* - __u32
- ``code``
- Format code, from enum
diff --git a/Documentation/media/uapi/v4l/vidioc-g-parm.rst b/Documentation/media/uapi/v4l/vidioc-g-parm.rst
index 616a5ea3f8fa..e831fa5512f0 100644
--- a/Documentation/media/uapi/v4l/vidioc-g-parm.rst
+++ b/Documentation/media/uapi/v4l/vidioc-g-parm.rst
@@ -66,7 +66,7 @@ union holding separate parameters for input and output devices.
-
- The buffer (stream) type, same as struct
:c:type:`v4l2_format` ``type``, set by the
- application. See :c:type:`v4l2_buf_type`
+ application. See :c:type:`v4l2_buf_type`.
* - union
- ``parm``
-
@@ -75,12 +75,13 @@ union holding separate parameters for input and output devices.
- struct :c:type:`v4l2_captureparm`
- ``capture``
- Parameters for capture devices, used when ``type`` is
- ``V4L2_BUF_TYPE_VIDEO_CAPTURE``.
+ ``V4L2_BUF_TYPE_VIDEO_CAPTURE`` or
+ ``V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE``.
* -
- struct :c:type:`v4l2_outputparm`
- ``output``
- Parameters for output devices, used when ``type`` is
- ``V4L2_BUF_TYPE_VIDEO_OUTPUT``.
+ ``V4L2_BUF_TYPE_VIDEO_OUTPUT`` or ``V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE``.
* -
- __u8
- ``raw_data``\ [200]
diff --git a/Documentation/media/uapi/v4l/vidioc-prepare-buf.rst b/Documentation/media/uapi/v4l/vidioc-prepare-buf.rst
index 70687a86ae38..49f9f4c181de 100644
--- a/Documentation/media/uapi/v4l/vidioc-prepare-buf.rst
+++ b/Documentation/media/uapi/v4l/vidioc-prepare-buf.rst
@@ -34,7 +34,7 @@ Description
Applications can optionally call the :ref:`VIDIOC_PREPARE_BUF` ioctl to
pass ownership of the buffer to the driver before actually enqueuing it,
-using the :ref:`VIDIOC_QBUF` ioctl, and to prepare it for future I/O. Such
+using the :ref:`VIDIOC_QBUF <VIDIOC_QBUF>` ioctl, and to prepare it for future I/O. Such
preparations may include cache invalidation or cleaning. Performing them
in advance saves time during the actual I/O. In case such cache
operations are not required, the application can use one of
diff --git a/Documentation/media/v4l-drivers/imx.rst b/Documentation/media/v4l-drivers/imx.rst
index 3c4f58bda178..65d3d15eb159 100644
--- a/Documentation/media/v4l-drivers/imx.rst
+++ b/Documentation/media/v4l-drivers/imx.rst
@@ -109,7 +109,7 @@ imx6-mipi-csi2
This is the MIPI CSI-2 receiver entity. It has one sink pad to receive
the MIPI CSI-2 stream (usually from a MIPI CSI-2 camera sensor). It has
four source pads, corresponding to the four MIPI CSI-2 demuxed virtual
-channel outputs. Multpiple source pads can be enabled to independently
+channel outputs. Multiple source pads can be enabled to independently
stream from multiple virtual channels.
This entity actually consists of two sub-blocks. One is the MIPI CSI-2
@@ -213,9 +213,11 @@ To give an example of crop and /2 downscale, this will crop a
1280x960 input frame to 640x480, and then /2 downscale in both
dimensions to 320x240 (assumes ipu1_csi0 is linked to ipu1_csi0_mux):
-media-ctl -V "'ipu1_csi0_mux':2[fmt:UYVY2X8/1280x960]"
-media-ctl -V "'ipu1_csi0':0[crop:(0,0)/640x480]"
-media-ctl -V "'ipu1_csi0':0[compose:(0,0)/320x240]"
+.. code-block:: none
+
+ media-ctl -V "'ipu1_csi0_mux':2[fmt:UYVY2X8/1280x960]"
+ media-ctl -V "'ipu1_csi0':0[crop:(0,0)/640x480]"
+ media-ctl -V "'ipu1_csi0':0[compose:(0,0)/320x240]"
Frame Skipping in ipuX_csiY
---------------------------
@@ -229,8 +231,10 @@ at the source pad.
The following example reduces an assumed incoming 60 Hz frame
rate by half at the IDMAC output source pad:
-media-ctl -V "'ipu1_csi0':0[fmt:UYVY2X8/640x480@1/60]"
-media-ctl -V "'ipu1_csi0':2[fmt:UYVY2X8/640x480@1/30]"
+.. code-block:: none
+
+ media-ctl -V "'ipu1_csi0':0[fmt:UYVY2X8/640x480@1/60]"
+ media-ctl -V "'ipu1_csi0':2[fmt:UYVY2X8/640x480@1/30]"
Frame Interval Monitor in ipuX_csiY
-----------------------------------
@@ -422,8 +426,7 @@ This pipeline uses the preprocess encode entity to route frames directly
from the CSI to the IC, to carry out scaling up to 1024x1024 resolution,
CSC, flipping, and image rotation:
--> ipuX_csiY:1 -> 0:ipuX_ic_prp:1 -> 0:ipuX_ic_prpenc:1 ->
- ipuX_ic_prpenc capture
+-> ipuX_csiY:1 -> 0:ipuX_ic_prp:1 -> 0:ipuX_ic_prpenc:1 -> ipuX_ic_prpenc capture
Motion Compensated De-interlace:
--------------------------------
@@ -432,8 +435,7 @@ This pipeline routes frames from the CSI direct pad to the VDIC entity to
support motion-compensated de-interlacing (high motion mode only),
scaling up to 1024x1024, CSC, flip, and rotation:
--> ipuX_csiY:1 -> 0:ipuX_vdic:2 -> 0:ipuX_ic_prp:2 ->
- 0:ipuX_ic_prpvf:1 -> ipuX_ic_prpvf capture
+-> ipuX_csiY:1 -> 0:ipuX_vdic:2 -> 0:ipuX_ic_prp:2 -> 0:ipuX_ic_prpvf:1 -> ipuX_ic_prpvf capture
Usage Notes
@@ -458,8 +460,8 @@ This platform requires the OmniVision OV5642 module with a parallel
camera interface, and the OV5640 module with a MIPI CSI-2
interface. Both modules are available from Boundary Devices:
-https://boundarydevices.com/product/nit6x_5mp
-https://boundarydevices.com/product/nit6x_5mp_mipi
+- https://boundarydevices.com/product/nit6x_5mp
+- https://boundarydevices.com/product/nit6x_5mp_mipi
Note that if only one camera module is available, the other sensor
node can be disabled in the device tree.
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index a863009849a3..6dafc8085acc 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -14,7 +14,11 @@ DISCLAIMER
This document is not a specification; it is intentionally (for the sake of
brevity) and unintentionally (due to being human) incomplete. This document is
meant as a guide to using the various memory barriers provided by Linux, but
-in case of any doubt (and there are many) please ask.
+in case of any doubt (and there are many) please ask. Some doubts may be
+resolved by referring to the formal memory consistency model and related
+documentation at tools/memory-model/. Nevertheless, even this memory
+model should be viewed as the collective opinion of its maintainers rather
+than as an infallible oracle.
To repeat, this document is not a specification of what Linux expects from
hardware.
@@ -48,7 +52,7 @@ CONTENTS
- Varieties of memory barrier.
- What may not be assumed about memory barriers?
- - Data dependency barriers.
+ - Data dependency barriers (historical).
- Control dependencies.
- SMP barrier pairing.
- Examples of memory barrier sequences.
@@ -399,7 +403,7 @@ Memory barriers come in four basic varieties:
where two loads are performed such that the second depends on the result
of the first (eg: the first load retrieves the address to which the second
load will be directed), a data dependency barrier would be required to
- make sure that the target of the second load is updated before the address
+ make sure that the target of the second load is updated after the address
obtained by the first load is accessed.
A data dependency barrier is a partial ordering on interdependent loads
@@ -550,8 +554,15 @@ There are certain things that the Linux kernel memory barriers do not guarantee:
Documentation/DMA-API.txt
-DATA DEPENDENCY BARRIERS
-------------------------
+DATA DEPENDENCY BARRIERS (HISTORICAL)
+-------------------------------------
+
+As of v4.15 of the Linux kernel, an smp_read_barrier_depends() was
+added to READ_ONCE(), which means that about the only people who
+need to pay attention to this section are those working on DEC Alpha
+architecture-specific code and those working on READ_ONCE() itself.
+For those who need it, and for those who are interested in the history,
+here is the story of data-dependency barriers.
The usage requirements of data dependency barriers are a little subtle, and
it's not always obvious that they're needed. To illustrate, consider the
@@ -2839,8 +2850,9 @@ as that committed on CPU 1.
To intervene, we need to interpolate a data dependency barrier or a read
-barrier between the loads. This will force the cache to commit its coherency
-queue before processing any further requests:
+barrier between the loads (which as of v4.15 is supplied unconditionally
+by the READ_ONCE() macro). This will force the cache to commit its
+coherency queue before processing any further requests:
CPU 1 CPU 2 COMMENT
=============== =============== =======================================
@@ -2869,8 +2881,8 @@ Other CPUs may also have split caches, but must coordinate between the various
cachelets for normal memory accesses. The semantics of the Alpha removes the
need for hardware coordination in the absence of memory barriers, which
permitted Alpha to sport higher CPU clock rates back in the day. However,
-please note that smp_read_barrier_depends() should not be used except in
-Alpha arch-specific code and within the READ_ONCE() macro.
+please note that (again, as of v4.15) smp_read_barrier_depends() should not
+be used except in Alpha arch-specific code and within the READ_ONCE() macro.
CACHE COHERENCY VS DMA
@@ -3035,7 +3047,9 @@ the data dependency barrier really becomes necessary as this synchronises both
caches with the memory coherence system, thus making it seem like pointer
changes vs new data occur in the right order.
-The Alpha defines the Linux kernel's memory barrier model.
+The Alpha defines the Linux kernel's memory model, although as of v4.15
+the Linux kernel's addition of smp_read_barrier_depends() to READ_ONCE()
+greatly reduced Alpha's impact on the memory model.
See the subsection on "Cache Coherency" above.
diff --git a/Documentation/metag/00-INDEX b/Documentation/metag/00-INDEX
deleted file mode 100644
index db11c513bd5c..000000000000
--- a/Documentation/metag/00-INDEX
+++ /dev/null
@@ -1,4 +0,0 @@
-00-INDEX
- - this file
-kernel-ABI.txt
- - Documents metag ABI details
diff --git a/Documentation/metag/kernel-ABI.txt b/Documentation/metag/kernel-ABI.txt
deleted file mode 100644
index 628216603198..000000000000
--- a/Documentation/metag/kernel-ABI.txt
+++ /dev/null
@@ -1,256 +0,0 @@
- ==========================
- KERNEL ABIS FOR METAG ARCH
- ==========================
-
-This document describes the Linux ABIs for the metag architecture, and has the
-following sections:
-
- (*) Outline of registers
- (*) Userland registers
- (*) Kernel registers
- (*) System call ABI
- (*) Calling conventions
-
-
-====================
-OUTLINE OF REGISTERS
-====================
-
-The main Meta core registers are arranged in units:
-
- UNIT Type DESCRIPTION GP EXT PRIV GLOBAL
- ======= ======= =============== ======= ======= ======= =======
- CT Special Control unit
- D0 General Data unit 0 0-7 8-15 16-31 16-31
- D1 General Data unit 1 0-7 8-15 16-31 16-31
- A0 General Address unit 0 0-3 4-7 8-15 8-15
- A1 General Address unit 1 0-3 4-7 8-15 8-15
- PC Special PC unit 0 1
- PORT Special Ports
- TR Special Trigger unit 0-7
- TT Special Trace unit 0-5
- FX General FP unit 0-15
-
-GP registers form part of the main context.
-
-Extended context registers (EXT) may not be present on all hardware threads and
-can be context switched if support is enabled and the appropriate bits are set
-in e.g. the D0.8 register to indicate what extended state to preserve.
-
-Global registers are shared between threads and are privilege protected.
-
-See arch/metag/include/asm/metag_regs.h for definitions relating to core
-registers and the fields and bits they contain. See the TRMs for further details
-about special registers.
-
-Several special registers are preserved in the main context, these are the
-interesting ones:
-
- REG (ALIAS) PURPOSE
- ======================= ===============================================
- CT.1 (TXMODE) Processor mode bits (particularly for DSP)
- CT.2 (TXSTATUS) Condition flags and LSM_STEP (MGET/MSET step)
- CT.3 (TXRPT) Branch repeat counter
- PC.0 (PC) Program counter
-
-Some of the general registers have special purposes in the ABI and therefore
-have aliases:
-
- D0 REG (ALIAS) PURPOSE D1 REG (ALIAS) PURPOSE
- =============== =============== =============== =======================
- D0.0 (D0Re0) 32bit result D1.0 (D1Re0) Top half of 64bit result
- D0.1 (D0Ar6) Argument 6 D1.1 (D1Ar5) Argument 5
- D0.2 (D0Ar4) Argument 4 D1.2 (D1Ar3) Argument 3
- D0.3 (D0Ar2) Argument 2 D1.3 (D1Ar1) Argument 1
- D0.4 (D0FrT) Frame temp D1.4 (D1RtP) Return pointer
- D0.5 Call preserved D1.5 Call preserved
- D0.6 Call preserved D1.6 Call preserved
- D0.7 Call preserved D1.7 Call preserved
-
- A0 REG (ALIAS) PURPOSE A1 REG (ALIAS) PURPOSE
- =============== =============== =============== =======================
- A0.0 (A0StP) Stack pointer A1.0 (A1GbP) Global base pointer
- A0.1 (A0FrP) Frame pointer A1.1 (A1LbP) Local base pointer
- A0.2 A1.2
- A0.3 A1.3
-
-
-==================
-USERLAND REGISTERS
-==================
-
-All the general purpose D0, D1, A0, A1 registers are preserved when entering the
-kernel (including asynchronous events such as interrupts and timer ticks) except
-the following which have special purposes in the ABI:
-
- REGISTERS WHEN STATUS PURPOSE
- =============== ======= =============== ===============================
- D0.8 DSP Preserved ECH, determines what extended
- DSP state to preserve.
- A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
- at any time by the creation of a
- signal frame.
- A1.0 (A1GbP) SMP Clobbered Used as temporary for loading
- kernel stack pointer and saving
- core context.
- A0.15 !SMP Protected Stores kernel stack pointer.
- A1.15 ALWAYS Protected Stores kernel base pointer.
-
-On UP A0.15 is used to store the kernel stack pointer for storing the userland
-context. A0.15 is global between hardware threads though which means it cannot
-be used on SMP for this purpose. Since no protected local registers are
-available A1GbP is reserved for use as a temporary to allow a percpu stack
-pointer to be loaded for storing the rest of the context.
-
-
-================
-KERNEL REGISTERS
-================
-
-When in the kernel the following registers have special purposes in the ABI:
-
- REGISTERS WHEN STATUS PURPOSE
- =============== ======= =============== ===============================
- A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
- at any time by the creation of
- an irq signal frame.
- A1.0 (A1GbP) ALWAYS Preserved Reserved (kernel base pointer).
-
-
-===============
-SYSTEM CALL ABI
-===============
-
-When a system call is made, the following registers are effective:
-
- REGISTERS CALL RETURN
- =============== ======================= ===============================
- D0.0 (D0Re0) Return value (or -errno)
- D1.0 (D1Re0) System call number Clobbered
- D0.1 (D0Ar6) Syscall arg #6 Preserved
- D1.1 (D1Ar5) Syscall arg #5 Preserved
- D0.2 (D0Ar4) Syscall arg #4 Preserved
- D1.2 (D1Ar3) Syscall arg #3 Preserved
- D0.3 (D0Ar2) Syscall arg #2 Preserved
- D1.3 (D1Ar1) Syscall arg #1 Preserved
-
-Due to the limited number of argument registers and some system calls with badly
-aligned 64-bit arguments, 64-bit values are always packed in consecutive
-arguments, even if this is contrary to the normal calling conventions (where the
-two halves would go in a matching pair of data registers).
-
-For example fadvise64_64 usually has the signature:
-
- long sys_fadvise64_64(i32 fd, i64 offs, i64 len, i32 advice);
-
-But for metag fadvise64_64 is wrapped so that the 64-bit arguments are packed:
-
- long sys_fadvise64_64_metag(i32 fd, i32 offs_lo,
- i32 offs_hi, i32 len_lo,
- i32 len_hi, i32 advice)
-
-So the arguments are packed in the registers like this:
-
- D0 REG (ALIAS) VALUE D1 REG (ALIAS) VALUE
- =============== =============== =============== =======================
- D0.1 (D0Ar6) advice D1.1 (D1Ar5) hi(len)
- D0.2 (D0Ar4) lo(len) D1.2 (D1Ar3) hi(offs)
- D0.3 (D0Ar2) lo(offs) D1.3 (D1Ar1) fd
-
-
-===================
-CALLING CONVENTIONS
-===================
-
-These calling conventions apply to both user and kernel code. The stack grows
-from low addresses to high addresses in the metag ABI. The stack pointer (A0StP)
-should always point to the next free address on the stack and should at all
-times be 64-bit aligned. The following registers are effective at the point of a
-call:
-
- REGISTERS CALL RETURN
- =============== ======================= ===============================
- D0.0 (D0Re0) 32bit return value
- D1.0 (D1Re0) Upper half of 64bit return value
- D0.1 (D0Ar6) 32bit argument #6 Clobbered
- D1.1 (D1Ar5) 32bit argument #5 Clobbered
- D0.2 (D0Ar4) 32bit argument #4 Clobbered
- D1.2 (D1Ar3) 32bit argument #3 Clobbered
- D0.3 (D0Ar2) 32bit argument #2 Clobbered
- D1.3 (D1Ar1) 32bit argument #1 Clobbered
- D0.4 (D0FrT) Clobbered
- D1.4 (D1RtP) Return pointer Clobbered
- D{0-1}.{5-7} Preserved
- A0.0 (A0StP) Stack pointer Preserved
- A1.0 (A0GbP) Preserved
- A0.1 (A0FrP) Frame pointer Preserved
- A1.1 (A0LbP) Preserved
- A{0-1},{2-3} Clobbered
-
-64-bit arguments are placed in matching pairs of registers (i.e. the same
-register number in both D0 and D1 units), with the least significant half in D0
-and the most significant half in D1, leaving a gap where necessary. Further
-arguments are stored on the stack in reverse order (earlier arguments at higher
-addresses):
-
- ADDRESS 0 1 2 3 4 5 6 7
- =============== ===== ===== ===== ===== ===== ===== ===== =====
- A0StP -->
- A0StP-0x08 32bit argument #8 32bit argument #7
- A0StP-0x10 32bit argument #10 32bit argument #9
-
-Function prologues tend to look a bit like this:
-
- /* If frame pointer in use, move it to frame temp register so it can be
- easily pushed onto stack */
- MOV D0FrT,A0FrP
-
- /* If frame pointer in use, set it to stack pointer */
- ADD A0FrP,A0StP,#0
-
- /* Preserve D0FrT, D1RtP, D{0-1}.{5-7} on stack, incrementing A0StP */
- MSETL [A0StP++],D0FrT,D0.5,D0.6,D0.7
-
- /* Allocate some stack space for local variables */
- ADD A0StP,A0StP,#0x10
-
-At this point the stack would look like this:
-
- ADDRESS 0 1 2 3 4 5 6 7
- =============== ===== ===== ===== ===== ===== ===== ===== =====
- A0StP -->
- A0StP-0x08
- A0StP-0x10
- A0StP-0x18 Old D0.7 Old D1.7
- A0StP-0x20 Old D0.6 Old D1.6
- A0StP-0x28 Old D0.5 Old D1.5
- A0FrP --> Old A0FrP (frame ptr) Old D1RtP (return ptr)
- A0FrP-0x08 32bit argument #8 32bit argument #7
- A0FrP-0x10 32bit argument #10 32bit argument #9
-
-Function epilogues tend to differ depending on the use of a frame pointer. An
-example of a frame pointer epilogue:
-
- /* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack, incrementing A0FrP */
- MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP++]
- /* Restore stack pointer to where frame pointer was before increment */
- SUB A0StP,A0FrP,#0x20
- /* Restore frame pointer from frame temp */
- MOV A0FrP,D0FrT
- /* Return to caller via restored return pointer */
- MOV PC,D1RtP
-
-If the function hasn't touched the frame pointer, MGETL cannot be safely used
-with A0StP as it always increments and that would expose the stack to clobbering
-by interrupts (kernel) or signals (user). Therefore it's common to see the MGETL
-split into separate GETL instructions:
-
- /* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack */
- GETL D0FrT,D1RtP,[A0StP+#-0x30]
- GETL D0.5,D1.5,[A0StP+#-0x28]
- GETL D0.6,D1.6,[A0StP+#-0x20]
- GETL D0.7,D1.7,[A0StP+#-0x18]
- /* Restore stack pointer */
- SUB A0StP,A0StP,#0x30
- /* Return to caller via restored return pointer */
- MOV PC,D1RtP
diff --git a/Documentation/mn10300/ABI.txt b/Documentation/mn10300/ABI.txt
deleted file mode 100644
index d3507bad428d..000000000000
--- a/Documentation/mn10300/ABI.txt
+++ /dev/null
@@ -1,149 +0,0 @@
- =========================
- MN10300 FUNCTION CALL ABI
- =========================
-
-=======
-GENERAL
-=======
-
-The MN10300/AM33 kernel runs in little-endian mode; big-endian mode is not
-supported.
-
-The stack grows downwards, and should always be 32-bit aligned. There are
-separate stack pointer registers for userspace and the kernel.
-
-
-================
-ARGUMENT PASSING
-================
-
-The first two arguments (assuming up to 32-bits per argument) to a function are
-passed in the D0 and D1 registers respectively; all other arguments are passed
-on the stack.
-
-If 64-bit arguments are being passed, then they are never split between
-registers and the stack. If the first argument is a 64-bit value, it will be
-passed in D0:D1. If the first argument is not a 64-bit value, but the second
-is, the second will be passed entirely on the stack and D1 will be unused.
-
-Arguments smaller than 32-bits are not coalesced within a register or a stack
-word. For example, two byte-sized arguments will always be passed in separate
-registers or word-sized stack slots.
-
-
-=================
-CALLING FUNCTIONS
-=================
-
-The caller must allocate twelve bytes on the stack for the callee's use before
-it inserts a CALL instruction. The CALL instruction will write into the TOS
-word, but won't actually modify the stack pointer; similarly, the RET
-instruction reads from the TOS word of the stack, but doesn't move the stack
-pointer beyond it.
-
-
- Stack:
- | |
- | |
- |---------------| SP+20
- | 4th Arg |
- |---------------| SP+16
- | 3rd Arg |
- |---------------| SP+12
- | D1 Save Slot |
- |---------------| SP+8
- | D0 Save Slot |
- |---------------| SP+4
- | Return Addr |
- |---------------| SP
- | |
- | |
-
-
-The caller must leave space on the stack (hence an allocation of twelve bytes)
-in which the callee may store the first two arguments.
-
-
-============
-RETURN VALUE
-============
-
-The return value is passed in D0 for an integer (or D0:D1 for a 64-bit value),
-or A0 for a pointer.
-
-If the return value is a value larger than 64-bits, or is a structure or an
-array, then a hidden first argument will be passed to the callee by the caller:
-this will point to a piece of memory large enough to hold the result of the
-function. In this case, the callee will return the value in that piece of
-memory, and no value will be returned in D0 or A0.
-
-
-===================
-REGISTER CLOBBERING
-===================
-
-The values in certain registers may be clobbered by the callee, and other
-values must be saved:
-
- Clobber: D0-D1, A0-A1, E0-E3
- Save: D2-D3, A2-A3, E4-E7, SP
-
-All other non-supervisor-only registers are clobberable (such as MDR, MCRL,
-MCRH).
-
-
-=================
-SPECIAL REGISTERS
-=================
-
-Certain ordinary registers may carry special usage for the compiler:
-
- A3: Frame pointer
- E2: TLS pointer
-
-
-==========
-KERNEL ABI
-==========
-
-The kernel may use a slightly different ABI internally.
-
- (*) E2
-
- If CONFIG_MN10300_CURRENT_IN_E2 is defined, then the current task pointer
- will be kept in the E2 register, and that register will be marked
- unavailable for the compiler to use as a scratch register.
-
- Normally the kernel uses something like:
-
- MOV SP,An
- AND 0xFFFFE000,An
- MOV (An),Rm // Rm holds current
- MOV (yyy,Rm) // Access current->yyy
-
- To find the address of current; but since this option permits current to
- be carried globally in an register, it can use:
-
- MOV (yyy,E2) // Access current->yyy
-
- instead.
-
-
-===============
-SYSTEM CALL ABI
-===============
-
-System calls are called with the following convention:
-
- REGISTER ENTRY EXIT
- =============== ======================= =======================
- D0 Syscall number Return value
- A0 1st syscall argument Saved
- D1 2nd syscall argument Saved
- A3 3rd syscall argument Saved
- A2 4th syscall argument Saved
- D3 5th syscall argument Saved
- D2 6th syscall argument Saved
-
-All other registers are saved. The layout is a consequence of the way the MOVM
-instruction stores registers onto the stack.
diff --git a/Documentation/mn10300/compartmentalisation.txt b/Documentation/mn10300/compartmentalisation.txt
deleted file mode 100644
index 8958b51dac4b..000000000000
--- a/Documentation/mn10300/compartmentalisation.txt
+++ /dev/null
@@ -1,60 +0,0 @@
- =========================================
- PART-SPECIFIC SOURCE COMPARTMENTALISATION
- =========================================
-
-The sources for various parts are compartmentalised at two different levels:
-
- (1) Processor level
-
- The "processor level" is a CPU core plus the other on-silicon
- peripherals.
-
- Processor-specific header files are divided among directories in a similar
- way to the CPU level:
-
- (*) include/asm-mn10300/proc-mn103e010/
-
- Support for the AM33v2 CPU core.
-
- The appropriate processor is selected by a CONFIG_MN10300_PROC_YYYY option
- from the "Processor support" choice menu in the arch/mn10300/Kconfig file.
-
-
- (2) Unit level
-
- The "unit level" is a processor plus all the external peripherals
- controlled by that processor.
-
- Unit-specific header files are divided among directories in a similar way
- to the CPU level; not only that, but specific sources may also be
- segregated into separate directories under the arch directory:
-
- (*) include/asm-mn10300/unit-asb2303/
- (*) arch/mn10300/unit-asb2303/
-
- Support for the ASB2303 board with an ASB2308 daughter board.
-
- (*) include/asm-mn10300/unit-asb2305/
- (*) arch/mn10300/unit-asb2305/
-
- Support for the ASB2305 board.
-
- The appropriate processor is selected by a CONFIG_MN10300_UNIT_ZZZZ option
- from the "Unit type" choice menu in the arch/mn10300/Kconfig file.
-
-
-============
-COMPILE TIME
-============
-
-When the kernel is compiled, symbolic links will be made in the asm header file
-directory for this arch:
-
- include/asm-mn10300/proc => include/asm-mn10300/proc-YYYY/
- include/asm-mn10300/unit => include/asm-mn10300/unit-ZZZZ/
-
-So that the header files contained in those directories can be accessed without
-lots of #ifdef-age.
-
-The appropriate arch/mn10300/unit-ZZZZ directory will also be entered by the
-compilation process; all other unit-specific directories will be ignored.
diff --git a/Documentation/networking/dpaa2/index.rst b/Documentation/networking/dpaa2/index.rst
new file mode 100644
index 000000000000..4c6586c87969
--- /dev/null
+++ b/Documentation/networking/dpaa2/index.rst
@@ -0,0 +1,8 @@
+===================
+DPAA2 Documentation
+===================
+
+.. toctree::
+ :maxdepth: 1
+
+ overview
diff --git a/drivers/staging/fsl-mc/overview.rst b/Documentation/networking/dpaa2/overview.rst
index 79fede4447d6..79fede4447d6 100644
--- a/drivers/staging/fsl-mc/overview.rst
+++ b/Documentation/networking/dpaa2/overview.rst
diff --git a/Documentation/networking/i40e.txt b/Documentation/networking/i40e.txt
index 57e616ed10b0..c2d6e1824b29 100644
--- a/Documentation/networking/i40e.txt
+++ b/Documentation/networking/i40e.txt
@@ -32,7 +32,7 @@ Enabling the driver
The driver is enabled via the standard kernel configuration system,
using the make command:
- Make oldconfig/silentoldconfig/menuconfig/etc.
+ make config/oldconfig/menuconfig/etc.
The driver is located in the menu structure at:
diff --git a/Documentation/networking/ice.txt b/Documentation/networking/ice.txt
new file mode 100644
index 000000000000..6261c46378e1
--- /dev/null
+++ b/Documentation/networking/ice.txt
@@ -0,0 +1,39 @@
+Intel(R) Ethernet Connection E800 Series Linux Driver
+===================================================================
+
+Intel ice Linux driver.
+Copyright(c) 2018 Intel Corporation.
+
+Contents
+========
+- Enabling the driver
+- Support
+
+The driver in this release supports Intel's E800 Series of products. For
+more information, visit Intel's support page at http://support.intel.com.
+
+Enabling the driver
+===================
+
+The driver is enabled via the standard kernel configuration system,
+using the make command:
+
+ Make oldconfig/silentoldconfig/menuconfig/etc.
+
+The driver is located in the menu structure at:
+
+ -> Device Drivers
+ -> Network device support (NETDEVICES [=y])
+ -> Ethernet driver support
+ -> Intel devices
+ -> Intel(R) Ethernet Connection E800 Series Support
+
+Support
+=======
+
+For general information, go to the Intel support website at:
+
+ http://support.intel.com
+
+If an issue is identified with the released source code, please email
+the maintainer listed in the MAINTAINERS file.
diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
index 90966c2692d8..f204eaff657d 100644
--- a/Documentation/networking/index.rst
+++ b/Documentation/networking/index.rst
@@ -8,6 +8,7 @@ Contents:
batman-adv
can
+ dpaa2/index
kapi
z8530book
msg_zerocopy
diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt
index a553d4e4a0fb..5dc1a040a2f1 100644
--- a/Documentation/networking/ip-sysctl.txt
+++ b/Documentation/networking/ip-sysctl.txt
@@ -133,14 +133,11 @@ min_adv_mss - INTEGER
IP Fragmentation:
-ipfrag_high_thresh - INTEGER
- Maximum memory used to reassemble IP fragments. When
- ipfrag_high_thresh bytes of memory is allocated for this purpose,
- the fragment handler will toss packets until ipfrag_low_thresh
- is reached. This also serves as a maximum limit to namespaces
- different from the initial one.
-
-ipfrag_low_thresh - INTEGER
+ipfrag_high_thresh - LONG INTEGER
+ Maximum memory used to reassemble IP fragments.
+
+ipfrag_low_thresh - LONG INTEGER
+ (Obsolete since linux-4.17)
Maximum memory used to reassemble IP fragments before the kernel
begins to remove incomplete fragment queues to free up resources.
The kernel still accepts new fragments for defragmentation.
@@ -755,13 +752,13 @@ udp_rmem_min - INTEGER
Minimal size of receive buffer used by UDP sockets in moderation.
Each UDP socket is able to use the size for receiving data, even if
total pages of UDP sockets exceed udp_mem pressure. The unit is byte.
- Default: 1 page
+ Default: 4K
udp_wmem_min - INTEGER
Minimal size of send buffer used by UDP sockets in moderation.
Each UDP socket is able to use the size for sending data, even if
total pages of UDP sockets exceed udp_mem pressure. The unit is byte.
- Default: 1 page
+ Default: 4K
CIPSOv4 Variables:
@@ -1363,6 +1360,13 @@ flowlabel_reflect - BOOLEAN
FALSE: disabled
Default: FALSE
+fib_multipath_hash_policy - INTEGER
+ Controls which hash policy to use for multipath routes.
+ Default: 0 (Layer 3)
+ Possible values:
+ 0 - Layer 3 (source and destination addresses plus flow label)
+ 1 - Layer 4 (standard 5-tuple)
+
anycast_src_echo_reply - BOOLEAN
Controls the use of anycast addresses as source addresses for ICMPv6
echo reply
@@ -1696,7 +1700,9 @@ disable_ipv6 - BOOLEAN
interface and start Duplicate Address Detection, if necessary.
When this value is changed from 0 to 1 (IPv6 is being disabled),
- it will dynamically delete all address on the given interface.
+ it will dynamically delete all addresses and routes on the given
+ interface. From now on it will not possible to add addresses/routes
+ to the selected interface.
accept_dad - INTEGER
Whether to accept DAD (Duplicate Address Detection).
@@ -2094,7 +2100,7 @@ sctp_rmem - vector of 3 INTEGERs: min, default, max
It is guaranteed to each SCTP socket (but not association) even
under moderate memory pressure.
- Default: 1 page
+ Default: 4K
sctp_wmem - vector of 3 INTEGERs: min, default, max
Currently this tunable has no effect.
diff --git a/Documentation/networking/irda.txt b/Documentation/networking/irda.txt
deleted file mode 100644
index bff26c138be6..000000000000
--- a/Documentation/networking/irda.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-To use the IrDA protocols within Linux you will need to get a suitable copy
-of the IrDA Utilities. More detailed information about these and associated
-programs can be found on http://irda.sourceforge.net/
-
-For more information about how to use the IrDA protocol stack, see the
-Linux Infrared HOWTO by Werner Heuser <wehe@tuxmobil.org>:
-<http://www.tuxmobil.org/Infrared-HOWTO/Infrared-HOWTO.html>
-
-There is an active mailing list for discussing Linux-IrDA matters called
- irda-users@lists.sourceforge.net
diff --git a/Documentation/networking/msg_zerocopy.rst b/Documentation/networking/msg_zerocopy.rst
index 291a01264967..fe46d4867e2d 100644
--- a/Documentation/networking/msg_zerocopy.rst
+++ b/Documentation/networking/msg_zerocopy.rst
@@ -72,11 +72,6 @@ this flag, a process must first signal intent by setting a socket option:
if (setsockopt(fd, SOL_SOCKET, SO_ZEROCOPY, &one, sizeof(one)))
error(1, errno, "setsockopt zerocopy");
-Setting the socket option only works when the socket is in its initial
-(TCP_CLOSED) state. Trying to set the option for a socket returned by accept(),
-for example, will lead to an EBUSY error. In this case, the option should be set
-to the listening socket and it will be inherited by the accepted sockets.
-
Transmission
------------
diff --git a/Documentation/networking/net_dim.txt b/Documentation/networking/net_dim.txt
new file mode 100644
index 000000000000..9cb31c5e2dcd
--- /dev/null
+++ b/Documentation/networking/net_dim.txt
@@ -0,0 +1,174 @@
+Net DIM - Generic Network Dynamic Interrupt Moderation
+======================================================
+
+Author:
+ Tal Gilboa <talgi@mellanox.com>
+
+
+Contents
+=========
+
+- Assumptions
+- Introduction
+- The Net DIM Algorithm
+- Registering a Network Device to DIM
+- Example
+
+Part 0: Assumptions
+======================
+
+This document assumes the reader has basic knowledge in network drivers
+and in general interrupt moderation.
+
+
+Part I: Introduction
+======================
+
+Dynamic Interrupt Moderation (DIM) (in networking) refers to changing the
+interrupt moderation configuration of a channel in order to optimize packet
+processing. The mechanism includes an algorithm which decides if and how to
+change moderation parameters for a channel, usually by performing an analysis on
+runtime data sampled from the system. Net DIM is such a mechanism. In each
+iteration of the algorithm, it analyses a given sample of the data, compares it
+to the previous sample and if required, it can decide to change some of the
+interrupt moderation configuration fields. The data sample is composed of data
+bandwidth, the number of packets and the number of events. The time between
+samples is also measured. Net DIM compares the current and the previous data and
+returns an adjusted interrupt moderation configuration object. In some cases,
+the algorithm might decide not to change anything. The configuration fields are
+the minimum duration (microseconds) allowed between events and the maximum
+number of wanted packets per event. The Net DIM algorithm ascribes importance to
+increase bandwidth over reducing interrupt rate.
+
+
+Part II: The Net DIM Algorithm
+===============================
+
+Each iteration of the Net DIM algorithm follows these steps:
+1. Calculates new data sample.
+2. Compares it to previous sample.
+3. Makes a decision - suggests interrupt moderation configuration fields.
+4. Applies a schedule work function, which applies suggested configuration.
+
+The first two steps are straightforward, both the new and the previous data are
+supplied by the driver registered to Net DIM. The previous data is the new data
+supplied to the previous iteration. The comparison step checks the difference
+between the new and previous data and decides on the result of the last step.
+A step would result as "better" if bandwidth increases and as "worse" if
+bandwidth reduces. If there is no change in bandwidth, the packet rate is
+compared in a similar fashion - increase == "better" and decrease == "worse".
+In case there is no change in the packet rate as well, the interrupt rate is
+compared. Here the algorithm tries to optimize for lower interrupt rate so an
+increase in the interrupt rate is considered "worse" and a decrease is
+considered "better". Step #2 has an optimization for avoiding false results: it
+only considers a difference between samples as valid if it is greater than a
+certain percentage. Also, since Net DIM does not measure anything by itself, it
+assumes the data provided by the driver is valid.
+
+Step #3 decides on the suggested configuration based on the result from step #2
+and the internal state of the algorithm. The states reflect the "direction" of
+the algorithm: is it going left (reducing moderation), right (increasing
+moderation) or standing still. Another optimization is that if a decision
+to stay still is made multiple times, the interval between iterations of the
+algorithm would increase in order to reduce calculation overhead. Also, after
+"parking" on one of the most left or most right decisions, the algorithm may
+decide to verify this decision by taking a step in the other direction. This is
+done in order to avoid getting stuck in a "deep sleep" scenario. Once a
+decision is made, an interrupt moderation configuration is selected from
+the predefined profiles.
+
+The last step is to notify the registered driver that it should apply the
+suggested configuration. This is done by scheduling a work function, defined by
+the Net DIM API and provided by the registered driver.
+
+As you can see, Net DIM itself does not actively interact with the system. It
+would have trouble making the correct decisions if the wrong data is supplied to
+it and it would be useless if the work function would not apply the suggested
+configuration. This does, however, allow the registered driver some room for
+manoeuvre as it may provide partial data or ignore the algorithm suggestion
+under some conditions.
+
+
+Part III: Registering a Network Device to DIM
+==============================================
+
+Net DIM API exposes the main function net_dim(struct net_dim *dim,
+struct net_dim_sample end_sample). This function is the entry point to the Net
+DIM algorithm and has to be called every time the driver would like to check if
+it should change interrupt moderation parameters. The driver should provide two
+data structures: struct net_dim and struct net_dim_sample. Struct net_dim
+describes the state of DIM for a specific object (RX queue, TX queue,
+other queues, etc.). This includes the current selected profile, previous data
+samples, the callback function provided by the driver and more.
+Struct net_dim_sample describes a data sample, which will be compared to the
+data sample stored in struct net_dim in order to decide on the algorithm's next
+step. The sample should include bytes, packets and interrupts, measured by
+the driver.
+
+In order to use Net DIM from a networking driver, the driver needs to call the
+main net_dim() function. The recommended method is to call net_dim() on each
+interrupt. Since Net DIM has a built-in moderation and it might decide to skip
+iterations under certain conditions, there is no need to moderate the net_dim()
+calls as well. As mentioned above, the driver needs to provide an object of type
+struct net_dim to the net_dim() function call. It is advised for each entity
+using Net DIM to hold a struct net_dim as part of its data structure and use it
+as the main Net DIM API object. The struct net_dim_sample should hold the latest
+bytes, packets and interrupts count. No need to perform any calculations, just
+include the raw data.
+
+The net_dim() call itself does not return anything. Instead Net DIM relies on
+the driver to provide a callback function, which is called when the algorithm
+decides to make a change in the interrupt moderation parameters. This callback
+will be scheduled and run in a separate thread in order not to add overhead to
+the data flow. After the work is done, Net DIM algorithm needs to be set to
+the proper state in order to move to the next iteration.
+
+
+Part IV: Example
+=================
+
+The following code demonstrates how to register a driver to Net DIM. The actual
+usage is not complete but it should make the outline of the usage clear.
+
+my_driver.c:
+
+#include <linux/net_dim.h>
+
+/* Callback for net DIM to schedule on a decision to change moderation */
+void my_driver_do_dim_work(struct work_struct *work)
+{
+ /* Get struct net_dim from struct work_struct */
+ struct net_dim *dim = container_of(work, struct net_dim,
+ work);
+ /* Do interrupt moderation related stuff */
+ ...
+
+ /* Signal net DIM work is done and it should move to next iteration */
+ dim->state = NET_DIM_START_MEASURE;
+}
+
+/* My driver's interrupt handler */
+int my_driver_handle_interrupt(struct my_driver_entity *my_entity, ...)
+{
+ ...
+ /* A struct to hold current measured data */
+ struct net_dim_sample dim_sample;
+ ...
+ /* Initiate data sample struct with current data */
+ net_dim_sample(my_entity->events,
+ my_entity->packets,
+ my_entity->bytes,
+ &dim_sample);
+ /* Call net DIM */
+ net_dim(&my_entity->dim, dim_sample);
+ ...
+}
+
+/* My entity's initialization function (my_entity was already allocated) */
+int my_driver_init_my_entity(struct my_driver_entity *my_entity, ...)
+{
+ ...
+ /* Initiate struct work_struct with my driver's callback function */
+ INIT_WORK(&my_entity->dim.work, my_driver_do_dim_work);
+ ...
+}
diff --git a/Documentation/networking/nf_flowtable.txt b/Documentation/networking/nf_flowtable.txt
new file mode 100644
index 000000000000..54128c50d508
--- /dev/null
+++ b/Documentation/networking/nf_flowtable.txt
@@ -0,0 +1,112 @@
+Netfilter's flowtable infrastructure
+====================================
+
+This documentation describes the software flowtable infrastructure available in
+Netfilter since Linux kernel 4.16.
+
+Overview
+--------
+
+Initial packets follow the classic forwarding path, once the flow enters the
+established state according to the conntrack semantics (ie. we have seen traffic
+in both directions), then you can decide to offload the flow to the flowtable
+from the forward chain via the 'flow offload' action available in nftables.
+
+Packets that find an entry in the flowtable (ie. flowtable hit) are sent to the
+output netdevice via neigh_xmit(), hence, they bypass the classic forwarding
+path (the visible effect is that you do not see these packets from any of the
+netfilter hooks coming after the ingress). In case of flowtable miss, the packet
+follows the classic forward path.
+
+The flowtable uses a resizable hashtable, lookups are based on the following
+7-tuple selectors: source, destination, layer 3 and layer 4 protocols, source
+and destination ports and the input interface (useful in case there are several
+conntrack zones in place).
+
+Flowtables are populated via the 'flow offload' nftables action, so the user can
+selectively specify what flows are placed into the flow table. Hence, packets
+follow the classic forwarding path unless the user explicitly instruct packets
+to use this new alternative forwarding path via nftables policy.
+
+This is represented in Fig.1, which describes the classic forwarding path
+including the Netfilter hooks and the flowtable fastpath bypass.
+
+ userspace process
+ ^ |
+ | |
+ _____|____ ____\/___
+ / \ / \
+ | input | | output |
+ \__________/ \_________/
+ ^ |
+ | |
+ _________ __________ --------- _____\/_____
+ / \ / \ |Routing | / \
+ --> ingress ---> prerouting ---> |decision| | postrouting |--> neigh_xmit
+ \_________/ \__________/ ---------- \____________/ ^
+ | ^ | | ^ |
+ flowtable | | ____\/___ | |
+ | | | / \ | |
+ __\/___ | --------->| forward |------------ |
+ |-----| | \_________/ |
+ |-----| | 'flow offload' rule |
+ |-----| | adds entry to |
+ |_____| | flowtable |
+ | | |
+ / \ | |
+ /hit\_no_| |
+ \ ? / |
+ \ / |
+ |__yes_________________fastpath bypass ____________________________|
+
+ Fig.1 Netfilter hooks and flowtable interactions
+
+The flowtable entry also stores the NAT configuration, so all packets are
+mangled according to the NAT policy that matches the initial packets that went
+through the classic forwarding path. The TTL is decremented before calling
+neigh_xmit(). Fragmented traffic is passed up to follow the classic forwarding
+path given that the transport selectors are missing, therefore flowtable lookup
+is not possible.
+
+Example configuration
+---------------------
+
+Enabling the flowtable bypass is relatively easy, you only need to create a
+flowtable and add one rule to your forward chain.
+
+ table inet x {
+ flowtable f {
+ hook ingress priority 0 devices = { eth0, eth1 };
+ }
+ chain y {
+ type filter hook forward priority 0; policy accept;
+ ip protocol tcp flow offload @f
+ counter packets 0 bytes 0
+ }
+ }
+
+This example adds the flowtable 'f' to the ingress hook of the eth0 and eth1
+netdevices. You can create as many flowtables as you want in case you need to
+perform resource partitioning. The flowtable priority defines the order in which
+hooks are run in the pipeline, this is convenient in case you already have a
+nftables ingress chain (make sure the flowtable priority is smaller than the
+nftables ingress chain hence the flowtable runs before in the pipeline).
+
+The 'flow offload' action from the forward chain 'y' adds an entry to the
+flowtable for the TCP syn-ack packet coming in the reply direction. Once the
+flow is offloaded, you will observe that the counter rule in the example above
+does not get updated for the packets that are being forwarded through the
+forwarding bypass.
+
+More reading
+------------
+
+This documentation is based on the LWN.net articles [1][2]. Rafal Milecki also
+made a very complete and comprehensive summary called "A state of network
+acceleration" that describes how things were before this infrastructure was
+mailined [3] and it also makes a rough summary of this work [4].
+
+[1] https://lwn.net/Articles/738214/
+[2] https://lwn.net/Articles/742164/
+[3] http://lists.infradead.org/pipermail/lede-dev/2018-January/010830.html
+[4] http://lists.infradead.org/pipermail/lede-dev/2018-January/010829.html
diff --git a/Documentation/networking/packet_mmap.txt b/Documentation/networking/packet_mmap.txt
index bf654845556e..999eb41da81d 100644
--- a/Documentation/networking/packet_mmap.txt
+++ b/Documentation/networking/packet_mmap.txt
@@ -7,15 +7,12 @@ socket interface on 2.4/2.6/3.x kernels. This type of sockets is used for
i) capture network traffic with utilities like tcpdump, ii) transmit network
traffic, or any other that needs raw access to network interface.
-You can find the latest version of this document at:
- http://wiki.ipxwarzone.com/index.php5?title=Linux_packet_mmap
-
Howto can be found at:
- http://wiki.gnu-log.net (packet_mmap)
+ https://sites.google.com/site/packetmmap/
Please send your comments to
Ulisses Alonso Camaró <uaca@i.hate.spam.alumni.uv.es>
- Johann Baudy <johann.baudy@gnu-log.net>
+ Johann Baudy
-------------------------------------------------------------------------------
+ Why use PACKET_MMAP
@@ -51,17 +48,8 @@ From the user standpoint, you should use the higher level libpcap library, which
is a de facto standard, portable across nearly all operating systems
including Win32.
-Said that, at time of this writing, official libpcap 0.8.1 is out and doesn't include
-support for PACKET_MMAP, and also probably the libpcap included in your distribution.
-
-I'm aware of two implementations of PACKET_MMAP in libpcap:
-
- http://wiki.ipxwarzone.com/ (by Simon Patarin, based on libpcap 0.6.2)
- http://public.lanl.gov/cpw/ (by Phil Wood, based on lastest libpcap)
-
-The rest of this document is intended for people who want to understand
-the low level details or want to improve libpcap by including PACKET_MMAP
-support.
+Packet MMAP support was integrated into libpcap around the time of version 1.3.0;
+TPACKET_V3 support was added in version 1.5.0
--------------------------------------------------------------------------------
+ How to use mmap() directly to improve capture process
@@ -174,7 +162,7 @@ As capture, each frame contains two parts:
/* bind socket to eth0 */
bind(this->socket, (struct sockaddr *)&my_addr, sizeof(struct sockaddr_ll));
- A complete tutorial is available at: http://wiki.gnu-log.net/
+ A complete tutorial is available at: https://sites.google.com/site/packetmmap/
By default, the user should put data at :
frame base + TPACKET_HDRLEN - sizeof(struct sockaddr_ll)
diff --git a/Documentation/networking/tls.txt b/Documentation/networking/tls.txt
index 77ed00631c12..58b5ef75f1b7 100644
--- a/Documentation/networking/tls.txt
+++ b/Documentation/networking/tls.txt
@@ -48,6 +48,9 @@ the transmit and the receive into the kernel.
setsockopt(sock, SOL_TLS, TLS_TX, &crypto_info, sizeof(crypto_info));
+Transmit and receive are set separately, but the setup is the same, using either
+TLS_TX or TLS_RX.
+
Sending TLS application data
----------------------------
@@ -79,6 +82,28 @@ for memory), or the encryption will always succeed. If send() returns
-ENOMEM and some data was left on the socket buffer from a previous
call using MSG_MORE, the MSG_MORE data is left on the socket buffer.
+Receiving TLS application data
+------------------------------
+
+After setting the TLS_RX socket option, all recv family socket calls
+are decrypted using TLS parameters provided. A full TLS record must
+be received before decryption can happen.
+
+ char buffer[16384];
+ recv(sock, buffer, 16384);
+
+Received data is decrypted directly in to the user buffer if it is
+large enough, and no additional allocations occur. If the userspace
+buffer is too small, data is decrypted in the kernel and copied to
+userspace.
+
+EINVAL is returned if the TLS version in the received message does not
+match the version passed in setsockopt.
+
+EMSGSIZE is returned if the received message is too big.
+
+EBADMSG is returned if decryption failed for any other reason.
+
Send TLS control messages
-------------------------
@@ -118,6 +143,43 @@ using a record of type @record_type.
Control message data should be provided unencrypted, and will be
encrypted by the kernel.
+Receiving TLS control messages
+------------------------------
+
+TLS control messages are passed in the userspace buffer, with message
+type passed via cmsg. If no cmsg buffer is provided, an error is
+returned if a control message is received. Data messages may be
+received without a cmsg buffer set.
+
+ char buffer[16384];
+ char cmsg[CMSG_SPACE(sizeof(unsigned char))];
+ struct msghdr msg = {0};
+ msg.msg_control = cmsg;
+ msg.msg_controllen = sizeof(cmsg);
+
+ struct iovec msg_iov;
+ msg_iov.iov_base = buffer;
+ msg_iov.iov_len = 16384;
+
+ msg.msg_iov = &msg_iov;
+ msg.msg_iovlen = 1;
+
+ int ret = recvmsg(sock, &msg, 0 /* flags */);
+
+ struct cmsghdr *cmsg = CMSG_FIRSTHDR(&msg);
+ if (cmsg->cmsg_level == SOL_TLS &&
+ cmsg->cmsg_type == TLS_GET_RECORD_TYPE) {
+ int record_type = *((unsigned char *)CMSG_DATA(cmsg));
+ // Do something with record_type, and control message data in
+ // buffer.
+ //
+ // Note that record_type may be == to application data (23).
+ } else {
+ // Buffer contains application data.
+ }
+
+recv will never return data from mixed types of TLS records.
+
Integrating in to userspace TLS library
---------------------------------------
@@ -126,10 +188,10 @@ layer of a userspace TLS library.
A patchset to OpenSSL to use ktls as the record layer is here:
-https://github.com/Mellanox/tls-openssl
+https://github.com/Mellanox/openssl/commits/tls_rx2
An example of calling send directly after a handshake using
gnutls. Since it doesn't implement a full record layer, control
messages are not supported:
-https://github.com/Mellanox/tls-af_ktls_tool
+https://github.com/ktls/af_ktls-tool/commits/RX
diff --git a/Documentation/arm/CCN.txt b/Documentation/perf/arm-ccn.txt
index 15cdb7bc57c3..15cdb7bc57c3 100644
--- a/Documentation/arm/CCN.txt
+++ b/Documentation/perf/arm-ccn.txt
diff --git a/Documentation/power/swsusp.txt b/Documentation/power/swsusp.txt
index 9f2f942a01cf..cc87adf44c0a 100644
--- a/Documentation/power/swsusp.txt
+++ b/Documentation/power/swsusp.txt
@@ -24,8 +24,16 @@ Some warnings, first.
* see the FAQ below for details. (This is not true for more traditional
* power states like "standby", which normally don't turn USB off.)
+Swap partition:
You need to append resume=/dev/your_swap_partition to kernel command
-line. Then you suspend by
+line or specify it using /sys/power/resume.
+
+Swap file:
+If using a swapfile you can also specify a resume offset using
+resume_offset=<number> on the kernel command line or specify it
+in /sys/power/resume_offset.
+
+After preparing then you suspend by
echo shutdown > /sys/power/disk; echo disk > /sys/power/state
diff --git a/Documentation/process/4.Coding.rst b/Documentation/process/4.Coding.rst
index 26b106071364..eb4b185d168c 100644
--- a/Documentation/process/4.Coding.rst
+++ b/Documentation/process/4.Coding.rst
@@ -58,6 +58,14 @@ can never be transgressed. If there is a good reason to go against the
style (a line which becomes far less readable if split to fit within the
80-column limit, for example), just do it.
+Note that you can also use the ``clang-format`` tool to help you with
+these rules, to quickly re-format parts of your code automatically,
+and to review full files in order to spot coding style mistakes,
+typos and possible improvements. It is also handy for sorting ``#includes``,
+for aligning variables/macros, for reflowing text and other similar tasks.
+See the file :ref:`Documentation/process/clang-format.rst <clangformat>`
+for more details.
+
Abstraction layers
******************
diff --git a/Documentation/process/5.Posting.rst b/Documentation/process/5.Posting.rst
index 645fa9c7388a..c209d70da66f 100644
--- a/Documentation/process/5.Posting.rst
+++ b/Documentation/process/5.Posting.rst
@@ -213,7 +213,7 @@ The tags in common use are:
which can be found in Documentation/process/submitting-patches.rst. Code without a
proper signoff cannot be merged into the mainline.
- - Co-Developed-by: states that the patch was also created by another developer
+ - Co-developed-by: states that the patch was also created by another developer
along with the original author. This is useful at times when multiple
people work on a single patch. Note, this person also needs to have a
Signed-off-by: line in the patch as well.
diff --git a/Documentation/process/adding-syscalls.rst b/Documentation/process/adding-syscalls.rst
index 8cc25a06f353..0d4f29bc798b 100644
--- a/Documentation/process/adding-syscalls.rst
+++ b/Documentation/process/adding-syscalls.rst
@@ -222,7 +222,7 @@ your new syscall number may get adjusted to resolve conflicts.
The file ``kernel/sys_ni.c`` provides a fallback stub implementation of each
system call, returning ``-ENOSYS``. Add your new system call here too::
- cond_syscall(sys_xyzzy);
+ COND_SYSCALL(xyzzy);
Your new kernel functionality, and the system call that controls it, should
normally be optional, so add a ``CONFIG`` option (typically to
@@ -360,7 +360,7 @@ First, the entry in ``arch/x86/entry/syscalls/syscall_32.tbl`` gets an extra
column to indicate that a 32-bit userspace program running on a 64-bit kernel
should hit the compat entry point::
- 380 i386 xyzzy sys_xyzzy compat_sys_xyzzy
+ 380 i386 xyzzy sys_xyzzy __ia32_compat_sys_xyzzy
Second, you need to figure out what should happen for the x32 ABI version of
the new system call. There's a choice here: the layout of the arguments
@@ -373,7 +373,7 @@ the compatibility wrapper::
333 64 xyzzy sys_xyzzy
...
- 555 x32 xyzzy compat_sys_xyzzy
+ 555 x32 xyzzy __x32_compat_sys_xyzzy
If no pointers are involved, then it is preferable to re-use the 64-bit system
call for the x32 ABI (and consequently the entry in
@@ -487,6 +487,38 @@ patchset, for the convenience of reviewers.
The man page should be cc'ed to linux-man@vger.kernel.org
For more details, see https://www.kernel.org/doc/man-pages/patches.html
+
+Do not call System Calls in the Kernel
+--------------------------------------
+
+System calls are, as stated above, interaction points between userspace and
+the kernel. Therefore, system call functions such as ``sys_xyzzy()`` or
+``compat_sys_xyzzy()`` should only be called from userspace via the syscall
+table, but not from elsewhere in the kernel. If the syscall functionality is
+useful to be used within the kernel, needs to be shared between an old and a
+new syscall, or needs to be shared between a syscall and its compatibility
+variant, it should be implemented by means of a "helper" function (such as
+``kern_xyzzy()``). This kernel function may then be called within the
+syscall stub (``sys_xyzzy()``), the compatibility syscall stub
+(``compat_sys_xyzzy()``), and/or other kernel code.
+
+At least on 64-bit x86, it will be a hard requirement from v4.17 onwards to not
+call system call functions in the kernel. It uses a different calling
+convention for system calls where ``struct pt_regs`` is decoded on-the-fly in a
+syscall wrapper which then hands processing over to the actual syscall function.
+This means that only those parameters which are actually needed for a specific
+syscall are passed on during syscall entry, instead of filling in six CPU
+registers with random user space content all the time (which may cause serious
+trouble down the call chain).
+
+Moreover, rules on how data may be accessed may differ between kernel data and
+user data. This is another reason why calling ``sys_xyzzy()`` is generally a
+bad idea.
+
+Exceptions to this rule are only allowed in architecture-specific overrides,
+architecture-specific compatibility wrappers, or other code in arch/.
+
+
References and Sources
----------------------
diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst
index 81cdb528ad46..ddc029734b25 100644
--- a/Documentation/process/changes.rst
+++ b/Documentation/process/changes.rst
@@ -78,7 +78,7 @@ Binutils
--------
The build system has, as of 4.13, switched to using thin archives (`ar T`)
-rather than incremental linking (`ld -r`) for built-in.o intermediate steps.
+rather than incremental linking (`ld -r`) for built-in.a intermediate steps.
This requires binutils 2.20 or newer.
Flex
@@ -430,7 +430,7 @@ udev
FUSE
----
-- <http://sourceforge.net/projects/fuse>
+- <https://github.com/libfuse/libfuse/releases>
mcelog
------
diff --git a/Documentation/process/clang-format.rst b/Documentation/process/clang-format.rst
new file mode 100644
index 000000000000..6710c0707721
--- /dev/null
+++ b/Documentation/process/clang-format.rst
@@ -0,0 +1,184 @@
+.. _clangformat:
+
+clang-format
+============
+
+``clang-format`` is a tool to format C/C++/... code according to
+a set of rules and heuristics. Like most tools, it is not perfect
+nor covers every single case, but it is good enough to be helpful.
+
+``clang-format`` can be used for several purposes:
+
+ - Quickly reformat a block of code to the kernel style. Specially useful
+ when moving code around and aligning/sorting. See clangformatreformat_.
+
+ - Spot style mistakes, typos and possible improvements in files
+ you maintain, patches you review, diffs, etc. See clangformatreview_.
+
+ - Help you follow the coding style rules, specially useful for those
+ new to kernel development or working at the same time in several
+ projects with different coding styles.
+
+Its configuration file is ``.clang-format`` in the root of the kernel tree.
+The rules contained there try to approximate the most common kernel
+coding style. They also try to follow :ref:`Documentation/process/coding-style.rst <codingstyle>`
+as much as possible. Since not all the kernel follows the same style,
+it is possible that you may want to tweak the defaults for a particular
+subsystem or folder. To do so, you can override the defaults by writing
+another ``.clang-format`` file in a subfolder.
+
+The tool itself has already been included in the repositories of popular
+Linux distributions for a long time. Search for ``clang-format`` in
+your repositories. Otherwise, you can either download pre-built
+LLVM/clang binaries or build the source code from:
+
+ http://releases.llvm.org/download.html
+
+See more information about the tool at:
+
+ https://clang.llvm.org/docs/ClangFormat.html
+
+ https://clang.llvm.org/docs/ClangFormatStyleOptions.html
+
+
+.. _clangformatreview:
+
+Review files and patches for coding style
+-----------------------------------------
+
+By running the tool in its inline mode, you can review full subsystems,
+folders or individual files for code style mistakes, typos or improvements.
+
+To do so, you can run something like::
+
+ # Make sure your working directory is clean!
+ clang-format -i kernel/*.[ch]
+
+And then take a look at the git diff.
+
+Counting the lines of such a diff is also useful for improving/tweaking
+the style options in the configuration file; as well as testing new
+``clang-format`` features/versions.
+
+``clang-format`` also supports reading unified diffs, so you can review
+patches and git diffs easily. See the documentation at:
+
+ https://clang.llvm.org/docs/ClangFormat.html#script-for-patch-reformatting
+
+To avoid ``clang-format`` formatting some portion of a file, you can do::
+
+ int formatted_code;
+ // clang-format off
+ void unformatted_code ;
+ // clang-format on
+ void formatted_code_again;
+
+While it might be tempting to use this to keep a file always in sync with
+``clang-format``, specially if you are writing new files or if you are
+a maintainer, please note that people might be running different
+``clang-format`` versions or not have it available at all. Therefore,
+you should probably refrain yourself from using this in kernel sources;
+at least until we see if ``clang-format`` becomes commonplace.
+
+
+.. _clangformatreformat:
+
+Reformatting blocks of code
+---------------------------
+
+By using an integration with your text editor, you can reformat arbitrary
+blocks (selections) of code with a single keystroke. This is specially
+useful when moving code around, for complex code that is deeply intended,
+for multi-line macros (and aligning their backslashes), etc.
+
+Remember that you can always tweak the changes afterwards in those cases
+where the tool did not do an optimal job. But as a first approximation,
+it can be very useful.
+
+There are integrations for many popular text editors. For some of them,
+like vim, emacs, BBEdit and Visual Studio you can find support built-in.
+For instructions, read the appropiate section at:
+
+ https://clang.llvm.org/docs/ClangFormat.html
+
+For Atom, Eclipse, Sublime Text, Visual Studio Code, XCode and other
+editors and IDEs you should be able to find ready-to-use plugins.
+
+For this use case, consider using a secondary ``.clang-format``
+so that you can tweak a few options. See clangformatextra_.
+
+
+.. _clangformatmissing:
+
+Missing support
+---------------
+
+``clang-format`` is missing support for some things that are common
+in kernel code. They are easy to remember, so if you use the tool
+regularly, you will quickly learn to avoid/ignore those.
+
+In particular, some very common ones you will notice are:
+
+ - Aligned blocks of one-line ``#defines``, e.g.::
+
+ #define TRACING_MAP_BITS_DEFAULT 11
+ #define TRACING_MAP_BITS_MAX 17
+ #define TRACING_MAP_BITS_MIN 7
+
+ vs.::
+
+ #define TRACING_MAP_BITS_DEFAULT 11
+ #define TRACING_MAP_BITS_MAX 17
+ #define TRACING_MAP_BITS_MIN 7
+
+ - Aligned designated initializers, e.g.::
+
+ static const struct file_operations uprobe_events_ops = {
+ .owner = THIS_MODULE,
+ .open = probes_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+ .write = probes_write,
+ };
+
+ vs.::
+
+ static const struct file_operations uprobe_events_ops = {
+ .owner = THIS_MODULE,
+ .open = probes_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+ .write = probes_write,
+ };
+
+
+.. _clangformatextra:
+
+Extra features/options
+----------------------
+
+Some features/style options are not enabled by default in the configuration
+file in order to minimize the differences between the output and the current
+code. In other words, to make the difference as small as possible,
+which makes reviewing full-file style, as well diffs and patches as easy
+as possible.
+
+In other cases (e.g. particular subsystems/folders/files), the kernel style
+might be different and enabling some of these options may approximate
+better the style there.
+
+For instance:
+
+ - Aligning assignments (``AlignConsecutiveAssignments``).
+
+ - Aligning declarations (``AlignConsecutiveDeclarations``).
+
+ - Reflowing text in comments (``ReflowComments``).
+
+ - Sorting ``#includes`` (``SortIncludes``).
+
+They are typically useful for block re-formatting, rather than full-file.
+You might want to create another ``.clang-format`` file and use that one
+from your editor/IDE instead.
diff --git a/Documentation/process/coding-style.rst b/Documentation/process/coding-style.rst
index a20b44a40ec4..4e7c0a1c427a 100644
--- a/Documentation/process/coding-style.rst
+++ b/Documentation/process/coding-style.rst
@@ -200,6 +200,15 @@ statement; in the latter case use braces in both branches:
otherwise();
}
+Also, use braces when a loop contains more than a single simple statement:
+
+.. code-block:: c
+
+ while (condition) {
+ if (test)
+ do_something();
+ }
+
3.1) Spaces
***********
@@ -622,6 +631,14 @@ options ``-kr -i8`` (stands for ``K&R, 8 character indents``), or use
re-formatting you may want to take a look at the man page. But
remember: ``indent`` is not a fix for bad programming.
+Note that you can also use the ``clang-format`` tool to help you with
+these rules, to quickly re-format parts of your code automatically,
+and to review full files in order to spot coding style mistakes,
+typos and possible improvements. It is also handy for sorting ``#includes``,
+for aligning variables/macros, for reflowing text and other similar tasks.
+See the file :ref:`Documentation/process/clang-format.rst <clangformat>`
+for more details.
+
10) Kconfig configuration files
-------------------------------
diff --git a/Documentation/process/howto.rst b/Documentation/process/howto.rst
index c6875b1db56f..3df55811b916 100644
--- a/Documentation/process/howto.rst
+++ b/Documentation/process/howto.rst
@@ -213,13 +213,6 @@ will learn the basics of getting your patch into the Linux kernel tree,
and possibly be pointed in the direction of what to go work on next, if
you do not already have an idea.
-If you already have a chunk of code that you want to put into the kernel
-tree, but need some help getting it in the proper form, the
-kernel-mentors project was created to help you out with this. It is a
-mailing list, and can be found at:
-
- https://selenic.com/mailman/listinfo/kernel-mentors
-
Before making any actual modifications to the Linux kernel code, it is
imperative to understand how the code in question works. For this
purpose, nothing is better than reading through it directly (most tricky
@@ -381,14 +374,6 @@ bugs is one of the best ways to get merits among other developers, because
not many people like wasting time fixing other people's bugs.
To work in the already reported bug reports, go to https://bugzilla.kernel.org.
-If you want to be advised of the future bug reports, you can subscribe to the
-bugme-new mailing list (only new bug reports are mailed here) or to the
-bugme-janitor mailing list (every change in the bugzilla is mailed here)
-
- https://lists.linux-foundation.org/mailman/listinfo/bugme-new
-
- https://lists.linux-foundation.org/mailman/listinfo/bugme-janitors
-
Mailing lists
diff --git a/Documentation/process/kernel-driver-statement.rst b/Documentation/process/kernel-driver-statement.rst
index 60d9d868f300..e78452c2164c 100644
--- a/Documentation/process/kernel-driver-statement.rst
+++ b/Documentation/process/kernel-driver-statement.rst
@@ -103,6 +103,7 @@ today, have in the past, or will in the future.
- Auke Kok
- Peter Korsgaard
- Jiri Kosina
+ - Aaro Koskinen
- Mariusz Kozlowski
- Greg Kroah-Hartman
- Michael Krufky
diff --git a/Documentation/process/license-rules.rst b/Documentation/process/license-rules.rst
index 408f77dc6157..8ea26325fe3f 100644
--- a/Documentation/process/license-rules.rst
+++ b/Documentation/process/license-rules.rst
@@ -4,15 +4,17 @@ Linux kernel licensing rules
============================
The Linux Kernel is provided under the terms of the GNU General Public
-License version 2 only (GPL-2.0), as published by the Free Software
-Foundation, and provided in the COPYING file. This documentation file is
-not meant to replace the COPYING file, but provides a description of how
-each source file should be annotated to make the licensing it is governed
-under clear and unambiguous.
-
-The license in the COPYING file applies to the kernel source as a whole,
-though individual source files can have a different license which is
-required to be compatible with the GPL-2.0::
+License version 2 only (GPL-2.0), as provided in LICENSES/preferred/GPL-2.0,
+with an explicit syscall exception described in
+LICENSES/exceptions/Linux-syscall-note, as described in the COPYING file.
+
+This documentation file provides a description of how each source file
+should be annotated to make its license clear and unambiguous.
+It doesn't replace the Kernel's license.
+
+The license described in the COPYING file applies to the kernel source
+as a whole, though individual source files can have a different license
+which is required to be compatible with the GPL-2.0::
GPL-1.0+ : GNU General Public License v1.0 or later
GPL-2.0+ : GNU General Public License v2.0 or later
diff --git a/Documentation/process/magic-number.rst b/Documentation/process/magic-number.rst
index c74199f60c6c..00cecf1fcba9 100644
--- a/Documentation/process/magic-number.rst
+++ b/Documentation/process/magic-number.rst
@@ -14,7 +14,7 @@ passing pointers to structures via a void * pointer. The tty code,
for example, does this frequently to pass driver-specific and line
discipline-specific structures back and forth.
-The way to use magic numbers is to declare then at the beginning of
+The way to use magic numbers is to declare them at the beginning of
the structure, like so::
struct tty_ldisc {
diff --git a/Documentation/process/submitting-patches.rst b/Documentation/process/submitting-patches.rst
index 1ef19d3a3eee..f7152ed565e5 100644
--- a/Documentation/process/submitting-patches.rst
+++ b/Documentation/process/submitting-patches.rst
@@ -510,8 +510,8 @@ tracking your trees, and to people trying to troubleshoot bugs in your
tree.
-12) When to use Acked-by: and Cc:
----------------------------------
+12) When to use Acked-by:, Cc:, and Co-Developed-by:
+-------------------------------------------------------
The Signed-off-by: tag indicates that the signer was involved in the
development of the patch, or that he/she was in the patch's delivery path.
@@ -543,6 +543,11 @@ person it names - but it should indicate that this person was copied on the
patch. This tag documents that potentially interested parties
have been included in the discussion.
+A Co-Developed-by: states that the patch was also created by another developer
+along with the original author. This is useful at times when multiple people
+work on a single patch. Note, this person also needs to have a Signed-off-by:
+line in the patch as well.
+
13) Using Reported-by:, Tested-by:, Reviewed-by:, Suggested-by: and Fixes:
--------------------------------------------------------------------------
diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt
index ae8fef86b832..11e904ee073f 100644
--- a/Documentation/ptp/ptp.txt
+++ b/Documentation/ptp/ptp.txt
@@ -18,7 +18,6 @@
- Adjust clock frequency
+ Ancillary clock features
- - One short or periodic alarms, with signal delivery to user program
- Time stamp external events
- Period output signals configurable from user space
- Synchronization of the Linux system time via the PPS subsystem
@@ -48,9 +47,7 @@
User space programs may control the clock using standardized
ioctls. A program may query, enable, configure, and disable the
ancillary clock features. User space can receive time stamped
- events via blocking read() and poll(). One shot and periodic
- signals may be configured via the POSIX timer_settime() system
- call.
+ events via blocking read() and poll().
** Writing clock drivers
diff --git a/Documentation/rapidio/sysfs.txt b/Documentation/rapidio/sysfs.txt
index 47ce9a5336e1..a1adac888e6e 100644
--- a/Documentation/rapidio/sysfs.txt
+++ b/Documentation/rapidio/sysfs.txt
@@ -1,158 +1,3 @@
- RapidIO sysfs Files
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-1. RapidIO Device Subdirectories
---------------------------------
-
-For each RapidIO device, the RapidIO subsystem creates files in an individual
-subdirectory with the following name, /sys/bus/rapidio/devices/<device_name>.
-
-The format of device_name is "nn:d:iiii", where:
-
-nn - two-digit hexadecimal ID of RapidIO network where the device resides
-d - device typr: 'e' - for endpoint or 's' - for switch
-iiii - four-digit device destID for endpoints, or switchID for switches
-
-For example, below is a list of device directories that represents a typical
-RapidIO network with one switch, one host, and two agent endpoints, as it is
-seen by the enumerating host (destID = 1):
-
-/sys/bus/rapidio/devices/00:e:0000
-/sys/bus/rapidio/devices/00:e:0002
-/sys/bus/rapidio/devices/00:s:0001
-
-NOTE: An enumerating or discovering endpoint does not create a sysfs entry for
-itself, this is why an endpoint with destID=1 is not shown in the list.
-
-2. Attributes Common for All RapidIO Devices
---------------------------------------------
-
-Each device subdirectory contains the following informational read-only files:
-
- did - returns the device identifier
- vid - returns the device vendor identifier
-device_rev - returns the device revision level
- asm_did - returns identifier for the assembly containing the device
- asm_rev - returns revision level of the assembly containing the device
- asm_vid - returns vendor identifier of the assembly containing the device
- destid - returns device destination ID assigned by the enumeration routine
- (see 4.1 for switch specific details)
- lprev - returns name of previous device (switch) on the path to the device
- that that owns this attribute
- modalias - returns the device modalias
-
-In addition to the files listed above, each device has a binary attribute file
-that allows read/write access to the device configuration registers using
-the RapidIO maintenance transactions:
-
- config - reads from and writes to the device configuration registers.
-
-This attribute is similar in behavior to the "config" attribute of PCI devices
-and provides an access to the RapidIO device registers using standard file read
-and write operations.
-
-3. RapidIO Endpoint Device Attributes
--------------------------------------
-
-Currently Linux RapidIO subsystem does not create any endpoint specific sysfs
-attributes. It is possible that RapidIO master port drivers and endpoint device
-drivers will add their device-specific sysfs attributes but such attributes are
-outside the scope of this document.
-
-4. RapidIO Switch Device Attributes
------------------------------------
-
-RapidIO switches have additional attributes in sysfs. RapidIO subsystem supports
-common and device-specific sysfs attributes for switches. Because switches are
-integrated into the RapidIO subsystem, it offers a method to create
-device-specific sysfs attributes by specifying a callback function that may be
-set by the switch initialization routine during enumeration or discovery process.
-
-4.1 Common Switch Attributes
-
- routes - reports switch routing information in "destID port" format. This
- attribute reports only valid routing table entries, one line for
- each entry.
- destid - device destination ID that defines a route to the switch
- hopcount - number of hops on the path to the switch
- lnext - returns names of devices linked to the switch except one of a device
- linked to the ingress port (reported as "lprev"). This is an array
- names with number of lines equal to number of ports in switch. If
- a switch port has no attached device, returns "null" instead of
- a device name.
-
-4.2 Device-specific Switch Attributes
-
-Device-specific switch attributes are listed for each RapidIO switch driver
-that exports additional attributes.
-
-IDT_GEN2:
- errlog - reads contents of device error log until it is empty.
-
-
-5. RapidIO Bus Attributes
--------------------------
-
-RapidIO bus subdirectory /sys/bus/rapidio implements the following bus-specific
-attribute:
-
- scan - allows to trigger enumeration discovery process from user space. This
- is a write-only attribute. To initiate an enumeration or discovery
- process on specific mport device, a user needs to write mport_ID (not
- RapidIO destination ID) into this file. The mport_ID is a sequential
- number (0 ... RIO_MAX_MPORTS) assigned to the mport device.
- For example, for a machine with a single RapidIO controller, mport_ID
- for that controller always will be 0.
- To initiate RapidIO enumeration/discovery on all available mports
- a user must write '-1' (or RIO_MPORT_ANY) into this attribute file.
-
-
-6. RapidIO Bus Controllers/Ports
---------------------------------
-
-On-chip RapidIO controllers and PCIe-to-RapidIO bridges (referenced as
-"Master Port" or "mport") are presented in sysfs as the special class of
-devices: "rapidio_port".
-
-The /sys/class/rapidio_port subdirectory contains individual subdirectories
-named as "rapidioN" where N = mport ID registered with RapidIO subsystem.
-
-NOTE: An mport ID is not a RapidIO destination ID assigned to a given local
-mport device.
-
-Each mport device subdirectory in addition to standard entries contains the
-following device-specific attributes:
-
- port_destid - reports RapidIO destination ID assigned to the given RapidIO
- mport device. If value 0xFFFFFFFF is returned this means that
- no valid destination ID have been assigned to the mport (yet).
- Normally, before enumeration/discovery have been executed only
- fabric enumerating mports have a valid destination ID assigned
- to them using "hdid=..." rapidio module parameter.
- sys_size - reports RapidIO common transport system size:
- 0 = small (8-bit destination ID, max. 256 devices),
- 1 = large (16-bit destination ID, max. 65536 devices).
-
-After enumeration or discovery was performed for a given mport device,
-the corresponding subdirectory will also contain subdirectories for each
-child RapidIO device connected to the mport. Naming conventions for RapidIO
-devices are described in Section 1 above.
-
-The example below shows mport device subdirectory with several child RapidIO
-devices attached to it.
-
-[rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
-total 0
-drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
-drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
-drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0007
-drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0002
-drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0003
-drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0005
-lrwxrwxrwx 1 root root 0 Feb 11 15:11 device -> ../../../0000:01:00.0
--r--r--r-- 1 root root 4096 Feb 11 15:11 port_destid
-drwxr-xr-x 2 root root 0 Feb 11 15:11 power
-lrwxrwxrwx 1 root root 0 Feb 11 15:04 subsystem -> ../../../../../../class/rapidio_port
--r--r--r-- 1 root root 4096 Feb 11 15:11 sys_size
--rw-r--r-- 1 root root 4096 Feb 11 15:04 uevent
+The RapidIO sysfs files have moved to:
+Documentation/ABI/testing/sysfs-bus-rapidio and
+Documentation/ABI/testing/sysfs-class-rapidio
diff --git a/Documentation/s390/vfio-ccw.txt b/Documentation/s390/vfio-ccw.txt
index 90b3dfead81b..2be11ad864ff 100644
--- a/Documentation/s390/vfio-ccw.txt
+++ b/Documentation/s390/vfio-ccw.txt
@@ -28,7 +28,7 @@ every detail. More information/reference could be found here:
https://en.wikipedia.org/wiki/Channel_I/O
- s390 architecture:
s390 Principles of Operation manual (IBM Form. No. SA22-7832)
-- The existing Qemu code which implements a simple emulated channel
+- The existing QEMU code which implements a simple emulated channel
subsystem could also be a good reference. It makes it easier to follow
the flow.
qemu/hw/s390x/css.c
@@ -39,22 +39,22 @@ For vfio mediated device framework:
Motivation of vfio-ccw
----------------------
-Currently, a guest virtualized via qemu/kvm on s390 only sees
+Typically, a guest virtualized via QEMU/KVM on s390 only sees
paravirtualized virtio devices via the "Virtio Over Channel I/O
(virtio-ccw)" transport. This makes virtio devices discoverable via
standard operating system algorithms for handling channel devices.
However this is not enough. On s390 for the majority of devices, which
use the standard Channel I/O based mechanism, we also need to provide
-the functionality of passing through them to a Qemu virtual machine.
+the functionality of passing through them to a QEMU virtual machine.
This includes devices that don't have a virtio counterpart (e.g. tape
drives) or that have specific characteristics which guests want to
exploit.
For passing a device to a guest, we want to use the same interface as
-everybody else, namely vfio. Thus, we would like to introduce vfio
-support for channel devices. And we would like to name this new vfio
-device "vfio-ccw".
+everybody else, namely vfio. We implement this vfio support for channel
+devices via the vfio mediated device framework and the subchannel device
+driver "vfio_ccw".
Access patterns of CCW devices
------------------------------
@@ -99,7 +99,7 @@ As mentioned above, we realize vfio-ccw with a mdev implementation.
Channel I/O does not have IOMMU hardware support, so the physical
vfio-ccw device does not have an IOMMU level translation or isolation.
-Sub-channel I/O instructions are all privileged instructions, When
+Subchannel I/O instructions are all privileged instructions. When
handling the I/O instruction interception, vfio-ccw has the software
policing and translation how the channel program is programmed before
it gets sent to hardware.
@@ -121,7 +121,7 @@ devices:
- The vfio_mdev driver for the mediated vfio ccw device.
This is provided by the mdev framework. It is a vfio device driver for
the mdev that created by vfio_ccw.
- It realize a group of vfio device driver callbacks, adds itself to a
+ It realizes a group of vfio device driver callbacks, adds itself to a
vfio group, and registers itself to the mdev framework as a mdev
driver.
It uses a vfio iommu backend that uses the existing map and unmap
@@ -178,7 +178,7 @@ vfio-ccw I/O region
An I/O region is used to accept channel program request from user
space and store I/O interrupt result for user space to retrieve. The
-defination of the region is:
+definition of the region is:
struct ccw_io_region {
#define ORB_AREA_SIZE 12
@@ -198,30 +198,23 @@ irb_area stores the I/O result.
ret_code stores a return code for each access of the region.
-vfio-ccw patches overview
--------------------------
+vfio-ccw operation details
+--------------------------
-For now, our patches are rebased on the latest mdev implementation.
-vfio-ccw follows what vfio-pci did on the s390 paltform and uses
-vfio-iommu-type1 as the vfio iommu backend. It's a good start to launch
-the code review for vfio-ccw. Note that the implementation is far from
-complete yet; but we'd like to get feedback for the general
-architecture.
+vfio-ccw follows what vfio-pci did on the s390 platform and uses
+vfio-iommu-type1 as the vfio iommu backend.
* CCW translation APIs
-- Description:
- These introduce a group of APIs (start with 'cp_') to do CCW
- translation. The CCWs passed in by a user space program are
- organized with their guest physical memory addresses. These APIs
- will copy the CCWs into the kernel space, and assemble a runnable
- kernel channel program by updating the guest physical addresses with
- their corresponding host physical addresses.
-- Patches:
- vfio: ccw: introduce channel program interfaces
+ A group of APIs (start with 'cp_') to do CCW translation. The CCWs
+ passed in by a user space program are organized with their guest
+ physical memory addresses. These APIs will copy the CCWs into kernel
+ space, and assemble a runnable kernel channel program by updating the
+ guest physical addresses with their corresponding host physical addresses.
+ Note that we have to use IDALs even for direct-access CCWs, as the
+ referenced memory can be located anywhere, including above 2G.
* vfio_ccw device driver
-- Description:
- The following patches utilizes the CCW translation APIs and introduce
+ This driver utilizes the CCW translation APIs and introduces
vfio_ccw, which is the driver for the I/O subchannel devices you want
to pass through.
vfio_ccw implements the following vfio ioctls:
@@ -236,20 +229,14 @@ architecture.
This also provides the SET_IRQ ioctl to setup an event notifier to
notify the user space program the I/O completion in an asynchronous
way.
-- Patches:
- vfio: ccw: basic implementation for vfio_ccw driver
- vfio: ccw: introduce ccw_io_region
- vfio: ccw: realize VFIO_DEVICE_GET_REGION_INFO ioctl
- vfio: ccw: realize VFIO_DEVICE_RESET ioctl
- vfio: ccw: realize VFIO_DEVICE_G(S)ET_IRQ_INFO ioctls
-
-The user of vfio-ccw is not limited to Qemu, while Qemu is definitely a
+
+The use of vfio-ccw is not limited to QEMU, while QEMU is definitely a
good example to get understand how these patches work. Here is a little
-bit more detail how an I/O request triggered by the Qemu guest will be
+bit more detail how an I/O request triggered by the QEMU guest will be
handled (without error handling).
Explanation:
-Q1-Q7: Qemu side process.
+Q1-Q7: QEMU side process.
K1-K5: Kernel side process.
Q1. Get I/O region info during initialization.
@@ -263,7 +250,7 @@ Q4. Write the guest channel program and ORB to the I/O region.
K2. Translate the guest channel program to a host kernel space
channel program, which becomes runnable for a real device.
K3. With the necessary information contained in the orb passed in
- by Qemu, issue the ccwchain to the device.
+ by QEMU, issue the ccwchain to the device.
K4. Return the ssch CC code.
Q5. Return the CC code to the guest.
@@ -271,7 +258,7 @@ Q5. Return the CC code to the guest.
K5. Interrupt handler gets the I/O result and write the result to
the I/O region.
- K6. Signal Qemu to retrieve the result.
+ K6. Signal QEMU to retrieve the result.
Q6. Get the signal and event handler reads out the result from the I/O
region.
Q7. Update the irb for the guest.
@@ -289,10 +276,20 @@ More information for DASD and ECKD could be found here:
https://en.wikipedia.org/wiki/Direct-access_storage_device
https://en.wikipedia.org/wiki/Count_key_data
-Together with the corresponding work in Qemu, we can bring the passed
+Together with the corresponding work in QEMU, we can bring the passed
through DASD/ECKD device online in a guest now and use it as a block
device.
+While the current code allows the guest to start channel programs via
+START SUBCHANNEL, support for HALT SUBCHANNEL or CLEAR SUBCHANNEL is
+not yet implemented.
+
+vfio-ccw supports classic (command mode) channel I/O only. Transport
+mode (HPF) is not supported.
+
+QDIO subchannels are currently not supported. Classic devices other than
+DASD/ECKD might work, but have not been tested.
+
Reference
---------
1. ESA/s390 Principles of Operation manual (IBM Form. No. SA22-7832)
diff --git a/Documentation/scsi/ChangeLog.1992-1997 b/Documentation/scsi/ChangeLog.1992-1997
deleted file mode 100644
index 6faad7e6417c..000000000000
--- a/Documentation/scsi/ChangeLog.1992-1997
+++ /dev/null
@@ -1,2023 +0,0 @@
-Sat Jan 18 15:51:45 1997 Richard Henderson <rth@tamu.edu>
-
- * Don't play with usage_count directly, instead hand around
- the module header and use the module macros.
-
-Fri May 17 00:00:00 1996 Leonard N. Zubkoff <lnz@dandelion.com>
-
- * BusLogic Driver Version 2.0.3 Released.
-
-Tue Apr 16 21:00:00 1996 Leonard N. Zubkoff <lnz@dandelion.com>
-
- * BusLogic Driver Version 1.3.2 Released.
-
-Sun Dec 31 23:26:00 1995 Leonard N. Zubkoff <lnz@dandelion.com>
-
- * BusLogic Driver Version 1.3.1 Released.
-
-Fri Nov 10 15:29:49 1995 Leonard N. Zubkoff <lnz@dandelion.com>
-
- * Released new BusLogic driver.
-
-Wed Aug 9 22:37:04 1995 Andries Brouwer <aeb@cwi.nl>
-
- As a preparation for new device code, separated the various
- functions the request->dev field had into the device proper,
- request->rq_dev and a status field request->rq_status.
-
- The 2nd argument of bios_param is now a kdev_t.
-
-Wed Jul 19 10:43:15 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * scsi.c (scsi_proc_info): /proc/scsi/scsi now also lists all
- attached devices.
-
- * scsi_proc.c (proc_print_scsidevice): Added. Used by scsi.c and
- eata_dma_proc.c to produce some device info for /proc/scsi.
-
- * eata_dma.c (eata_queue)(eata_int_handler)(eata_scsi_done):
- Changed handling of internal SCSI commands send to the HBA.
-
-
-Wed Jul 19 10:09:17 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * Linux 1.3.11 released.
-
- * eata_dma.c (eata_queue)(eata_int_handler): Added code to do
- command latency measurements if requested by root through
- /proc/scsi interface.
- Throughout Use HZ constant for time references.
-
- * eata_pio.c: Use HZ constant for time references.
-
- * aic7xxx.c, aic7xxx.h, aic7xxx_asm.c: Changed copyright from BSD
- to GNU style.
-
- * scsi.h: Added READ_12 command opcode constant
-
-Wed Jul 19 09:25:30 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * Linux 1.3.10 released.
-
- * scsi_proc.c (dispatch_scsi_info): Removed unused variable.
-
-Wed Jul 19 09:25:30 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * Linux 1.3.9 released.
-
- * scsi.c Blacklist concept expanded to 'support' more device
- deficiencies. blacklist[] renamed to device_list[]
- (scan_scsis): Code cleanup.
-
- * scsi_debug.c (scsi_debug_proc_info): Added support to control
- device lockup simulation via /proc/scsi interface.
-
-
-Wed Jul 19 09:22:34 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * Linux 1.3.7 released.
-
- * scsi_proc.c: Fixed a number of bugs in directory handling
-
-Wed Jul 19 09:18:28 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * Linux 1.3.5 released.
-
- * Native wide, multichannel and /proc/scsi support now in official
- kernel distribution.
-
- * scsi.c/h, hosts.c/h et al reindented to increase readability
- (especially on 80 column wide terminals).
-
- * scsi.c, scsi_proc.c, ../../fs/proc/inode.c: Added
- /proc/scsi/scsi which allows root to scan for hotplugged devices.
-
- * scsi.c (scsi_proc_info): Added, to support /proc/scsi/scsi.
- (scan_scsis): Added some 'spaghetti' code to allow scanning for
- single devices.
-
-
-Thu Jun 20 15:20:27 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * proc.c: Renamed to scsi_proc.c
-
-Mon Jun 12 20:32:45 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * Linux 1.3.0 released.
-
-Mon May 15 19:33:14 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * scsi.c: Added native multichannel and wide scsi support.
-
- * proc.c (dispatch_scsi_info) (build_proc_dir_hba_entries):
- Updated /proc/scsi interface.
-
-Thu May 4 17:58:48 1995 Michael Neuffer <neuffer@goofy.zdv.uni-mainz.de>
-
- * sd.c (requeue_sd_request): Zero out the scatterlist only if
- scsi_malloc returned memory for it.
-
- * eata_dma.c (register_HBA) (eata_queue): Add support for
- large scatter/gather tables and set use_clustering accordingly
-
- * hosts.c: Make use_clustering changeable in the Scsi_Host structure.
-
-Wed Apr 12 15:25:52 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.2.5 released.
-
- * buslogic.c: Update to version 1.15 (From Leonard N. Zubkoff).
- Fixed interrupt routine to avoid races when handling multiple
- complete commands per interrupt. Seems to come up with faster
- cards.
-
- * eata_dma.c: Update to 2.3.5r. Modularize. Improved error handling
- throughout and fixed bug interrupt routine which resulted in shifted
- status bytes. Added blink LED state checks for ISA and EISA HBAs.
- Memory management bug seems to have disappeared ==> increasing
- C_P_L_CURRENT_MAX to 16 for now. Decreasing C_P_L_DIV to 3 for
- performance reasons.
-
- * scsi.c: If we get a FMK, EOM, or ILI when attempting to scan
- the bus, assume that it was just noise on the bus, and ignore
- the device.
-
- * scsi.h: Update and add a bunch of missing commands which we
- were never using.
-
- * sd.c: Use restore_flags in do_sd_request - this may result in
- latency conditions, but it gets rid of races and crashes.
- Do not save flags again when searching for a second command to
- queue.
-
- * st.c: Use bytes, not STP->buffer->buffer_size when reading
- from tape.
-
-
-Tue Apr 4 09:42:08 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.2.4 released.
-
- * st.c: Fix typo - restoring wrong flags.
-
-Wed Mar 29 06:55:12 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.2.3 released.
-
- * st.c: Perform some waiting operations with interrupts off.
- Is this correct???
-
-Wed Mar 22 10:34:26 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.2.2 released.
-
- * aha152x.c: Modularize. Add support for PCMCIA.
-
- * eata.c: Update to version 2.0. Fixed bug preventing media
- detection. If scsi_register_host returns NULL, fail gracefully.
-
- * scsi.c: Detect as NEC (for photo-cd purposes) for the 84
- and 25 models as "NEC_OLDCDR".
-
- * scsi.h: Add define for NEC_OLDCDR
-
- * sr.c: Add handling for NEC_OLDCDR. Treat as unknown.
-
- * u14-34f.c: Update to version 2.0. Fixed same bug as in
- eata.c.
-
-
-Mon Mar 6 11:11:20 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.2.0 released. Yeah!!!
-
- * Minor spelling/punctuation changes throughout. Nothing
- substantive.
-
-Mon Feb 20 21:33:03 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.95 released.
-
- * qlogic.c: Update to version 0.41.
-
- * seagate.c: Change some message to be more descriptive about what
- we detected.
-
- * sr.c: spelling/whitespace changes.
-
-Mon Feb 20 21:33:03 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.94 released.
-
-Mon Feb 20 08:57:17 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.93 released.
-
- * hosts.h: Change io_port to long int from short.
-
- * 53c7,8xx.c: crash on AEN fixed, SCSI reset is no longer a NOP,
- NULL pointer panic on odd UDCs fixed, two bugs in diagnostic output
- fixed, should initialize correctly if left running, now loadable,
- new memory allocation, extraneous diagnostic output suppressed,
- splx() replaced with save/restore flags. [ Drew ]
-
- * hosts.c, hosts.h, scsi_ioctl.c, sd.c, sd_ioctl.c, sg.c, sr.c,
- sr_ioctl.c: Add special junk at end that Emacs will use for
- formatting the file.
-
- * qlogic.c: Update to v0.40a. Improve parity handling.
-
- * scsi.c: Add Hitachi DK312C to blacklist. Change "};" to "}" in
- many places. Use scsi_init_malloc to get command block - may
- need this to be dma compatible for some host adapters.
- Restore interrupts after unregistering a host.
-
- * sd.c: Use sti instead of restore flags - causes latency problems.
-
- * seagate.c: Use controller_type to determine string used when
- registering irq.
-
- * sr.c: More photo-cd hacks to make sure we get the xa stuff right.
- * sr.h, sr.c: Change is_xa to xa_flags field.
-
- * st.c: Disable retries for write operations.
-
-Wed Feb 15 10:52:56 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.92 released.
-
- * eata.c: Update to 1.17.
-
- * eata_dma.c: Update to 2.31a. Add more support for /proc/scsi.
- Continuing modularization. Less crashes because of the bug in the
- memory management ==> increase C_P_L_CURRENT_MAX to 10
- and decrease C_P_L_DIV to 4.
-
- * hosts.c: If we remove last host registered, reuse host number.
- When freeing memory from host being deregistered, free extra_bytes
- too.
-
- * scsi.c (scan_scsis): memset(SDpnt, 0) and set SCmd.device to SDpnt.
- Change memory allocation to work around bugs in __get_dma_pages.
- Do not free host if usage count is not zero (for modules).
-
- * sr_ioctl.c: Increase IOCTL_TIMEOUT to 3000.
-
- * st.c: Allow for ST_EXTRA_DEVS in st data structures.
-
- * u14-34f.c: Update to 1.17.
-
-Thu Feb 9 10:11:16 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.91 released.
-
- * eata.c: Update to 1.16. Use wish_block instead of host->block.
-
- * hosts.c: Initialize wish_block to 0.
-
- * hosts.h: Add wish_block.
-
- * scsi.c: Use wish_block as indicator that the host should be added
- to block list.
-
- * sg.c: Add SG_EXTRA_DEVS to number of slots.
-
- * u14-34f.c: Use wish_block.
-
-Tue Feb 7 11:46:04 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.90 released.
-
- * eata.c: Change naming from eata_* to eata2x_*. Now at vers 1.15.
- Update interrupt handler to take pt_regs as arg. Allow blocking
- even if loaded as module. Initialize target_time_out array.
- Do not put sti(); in timing loop.
-
- * hosts.c: Do not reuse host numbers.
- Use scsi_make_blocked_list to generate blocking list.
-
- * script_asm.pl: Beats me. Don't know perl. Something to do with
- phase index.
-
- * scsi.c (scsi_make_blocked_list): New function - code copied from
- hosts.c.
-
- * scsi.c: Update code to disable photo CD for Toshiba cdroms.
- Use just manufacturer name, not model number.
-
- * sr.c: Fix setting density for Toshiba drives.
-
- * u14-34f.c: Clear target_time_out array during reset.
-
-Wed Feb 1 09:20:45 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.89 released.
-
- * Makefile, u14-34f.c: Modularize.
-
- * Makefile, eata.c: Modularize. Now version 1.14
-
- * NCR5380.c: Update interrupt handler with new arglist. Minor
- cleanups.
-
- * eata_dma.c: Begin to modularize. Add hooks for /proc/scsi.
- New version 2.3.0a. Add code in interrupt handler to allow
- certain CDROM drivers to be detected which return a
- CHECK_CONDITION during SCSI bus scan. Add opcode check to get
- all DATA IN and DATA OUT phases right. Utilize HBA_interpret flag.
- Improvements in HBA identification. Various other minor stuff.
-
- * hosts.c: Initialize ->dma_channel and ->io_port when registering
- a new host.
-
- * qlogic.c: Modularize and add PCMCIA support.
-
- * scsi.c: Add Hitachi to blacklist.
-
- * scsi.c: Change default to no lun scan (too many problem devices).
-
- * scsi.h: Define QUEUE_FULL condition.
-
- * sd.c: Do not check for non-existent partition until after
- new media check.
-
- * sg.c: Undo previous change which was wrong.
-
- * sr_ioctl.c: Increase IOCTL_TIMEOUT to 2000.
-
- * st.c: Patches from Kai - improve filemark handling.
-
-Tue Jan 31 17:32:12 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.88 released.
-
- * Throughout - spelling/grammar fixups.
-
- * scsi.c: Make sure that all buffers are 16 byte aligned - some
- drivers (buslogic) need this.
-
- * scsi.c (scan_scsis): Remove message printed.
-
- * scsi.c (scsi_init): Move message here.
-
-Mon Jan 30 06:40:25 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.87 released.
-
- * sr.c: Photo-cd related changes. (Gerd Knorr??).
-
- * st.c: Changes from Kai related to EOM detection.
-
-Mon Jan 23 23:53:10 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.86 released.
-
- * 53c7,8xx.h: Change SG size to 127.
-
- * eata_dma: Update to version 2.10i. Remove bug in the registration
- of multiple HBAs and channels. Minor other improvements and stylistic
- changes.
-
- * scsi.c: Test for Toshiba XM-3401TA and exclude from detection
- as toshiba drive - photo cd does not work with this drive.
-
- * sr.c: Update photocd code.
-
-Mon Jan 23 23:53:10 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.85 released.
-
- * st.c, st_ioctl.c, sg.c, sd_ioctl.c, scsi_ioctl.c, hosts.c:
- include linux/mm.h
-
- * qlogic.c, buslogic.c, aha1542.c: Include linux/module.h.
-
-Sun Jan 22 22:08:46 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.84 released.
-
- * Makefile: Support for loadable QLOGIC boards.
-
- * aha152x.c: Update to version 1.8 from Juergen.
-
- * eata_dma.c: Update from Michael Neuffer.
- Remove hard limit of 2 commands per lun and make it better
- configurable. Improvements in HBA identification.
-
- * in2000.c: Fix biosparam to support large disks.
-
- * qlogic.c: Minor changes (change sti -> restore_flags).
-
-Wed Jan 18 23:33:09 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.83 released.
-
- * aha1542.c(aha1542_intr_handle): Use arguments handed down to find
- which irq.
-
- * buslogic.c: Likewise.
-
- * eata_dma.c: Use min of 2 cmd_per_lun for OCS_enabled boards.
-
- * scsi.c: Make RECOVERED_ERROR a SUGGEST_IS_OK.
-
- * sd.c: Fail if we are opening a non-existent partition.
-
- * sr.c: Bump SR_TIMEOUT to 15000.
- Do not probe for media size at boot time(hard on changers).
- Flag device as needing sector size instead.
-
- * sr_ioctl.c: Remove CDROMMULTISESSION_SYS ioctl.
-
- * ultrastor.c: Fix bug in call to ultrastor_interrupt (wrong #args).
-
-Mon Jan 16 07:18:23 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.82 released.
-
- Throughout.
- - Change all interrupt handlers to accept new calling convention.
- In particular, we now receive the irq number as one of the arguments.
-
- * More minor spelling corrections in some of the new files.
-
- * aha1542.c, buslogic.c: Clean up interrupt handler a little now
- that we receive the irq as an arg.
-
- * aha274x.c: s/snarf_region/request_region/
-
- * eata.c: Update to version 1.12. Fix some comments and display a
- message if we cannot reserve the port addresses.
-
- * u14-34f.c: Update to version 1.13. Fix some comments and display a
- message if we cannot reserve the port addresses.
-
- * eata_dma.c: Define get_board_data function (send INQUIRY command).
- Use to improve detection of variants of different DPT boards. Change
- version subnumber to "0g".
-
- * fdomain.c: Update to version 5.26. Improve detection of some boards
- repackaged by IBM.
-
- * scsi.c (scsi_register_host): Change "name" to const char *.
-
- * sr.c: Fix problem in set mode command for Toshiba drives.
-
- * sr.c: Fix typo from patch 81.
-
-Fri Jan 13 12:54:46 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.81 released. Codefreeze for 1.2 release announced.
-
- Big changes here.
-
- * eata_dma.*: New files from Michael Neuffer.
- (neuffer@goofy.zdv.uni-mainz.de). Should support
- all eata/dpt cards.
-
- * hosts.c, Makefile: Add eata_dma.
-
- * README.st: Document MTEOM.
-
- Patches from me (ERY) to finish support for low-level loadable scsi.
- It now works, and is actually useful.
-
- * Throughout - add new argument to scsi_init_malloc that takes an
- additional parameter. This is used as a priority to kmalloc,
- and you can specify the GFP_DMA flag if you need DMA-able memory.
-
- * Makefile: For source files that are loadable, always add name
- to SCSI_SRCS. Fill in modules: target.
-
- * hosts.c: Change next_host to next_scsi_host, and make global.
- Print hosts after we have identified all of them. Use info()
- function if present, otherwise use name field.
-
- * hosts.h: Change attach function to return int, not void.
- Define number of device slots to allow for loadable devices.
- Define tags to tell scsi module code what type of module we
- are loading.
-
- * scsi.c: Fix scan_scsis so that it can be run by a user process.
- Do not use waiting loops - use up and down mechanism as long
- as current != task[0].
-
- * scsi.c(scan_scsis): Do not use stack variables for I/O - this
- could be > 16Mb if we are loading a module at runtime (i.e. use
- scsi_init_malloc to get some memory we know will be safe).
-
- * scsi.c: Change dma freelist to be a set of pages. This allows
- us to dynamically adjust the size of the list by adding more pages
- to the pagelist. Fix scsi_malloc and scsi_free accordingly.
-
- * scsi_module.c: Fix include.
-
- * sd.c: Declare detach function. Increment/decrement module usage
- count as required. Fix init functions to allow loaded devices.
- Revalidate all new disks so we get the partition tables. Define
- detach function.
-
- * sr.c: Likewise.
-
- * sg.c: Declare detach function. Allow attachment of devices on
- loaded drivers.
-
- * st.c: Declare detach function. Increment/decrement module usage
- count as required.
-
-Tue Jan 10 10:09:58 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.79 released.
-
- Patch from some undetermined individual who needs to get a life :-).
-
- * sr.c: Attacked by spelling bee...
-
- Patches from Gerd Knorr:
-
- * sr.c: make printk messages for photoCD a little more informative.
-
- * sr_ioctl.c: Fix CDROMMULTISESSION_SYS ioctl.
-
-Mon Jan 9 10:01:37 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.78 released.
-
- * Makefile: Add empty modules: target.
-
- * Wheee. Now change register_iomem to request_region.
-
- * in2000.c: Bugfix - apparently this is the fix that we have
- all been waiting for. It fixes a problem whereby the driver
- is not stable under heavy load. Race condition and all that.
- Patch from Peter Lu.
-
-Wed Jan 4 21:17:40 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.77 released.
-
- * 53c7,8xx.c: Fix from Linus - emulate splx.
-
- Throughout:
-
- Change "snarf_region" with "register_iomem".
-
- * scsi_module.c: New file. Contains support for low-level loadable
- scsi drivers. [ERY].
-
- * sd.c: More s/int/long/ changes.
-
- * seagate.c: Explicitly include linux/config.h
-
- * sg.c: Increment/decrement module usage count on open/close.
-
- * sg.c: Be a bit more careful about the user not supplying enough
- information for a valid command. Pass correct size down to
- scsi_do_cmd.
-
- * sr.c: More changes for Photo-CD. This apparently breaks NEC drives.
-
- * sr_ioctl.c: Support CDROMMULTISESSION ioctl.
-
-
-Sun Jan 1 19:55:21 1995 Eric Youngdale (eric@andante)
-
- * Linux 1.1.76 released.
-
- * constants.c: Add type cast in switch statement.
-
- * scsi.c (scsi_free): Change datatype of "offset" to long.
- (scsi_malloc): Change a few more variables to long. Who
- did this and why was it important? 64 bit machines?
-
-
- Lots of changes to use save_state/restore_state instead of cli/sti.
- Files changed include:
-
- * aha1542.c:
- * aha1740.c:
- * buslogic.c:
- * in2000.c:
- * scsi.c:
- * scsi_debug.c:
- * sd.c:
- * sr.c:
- * st.c:
-
-Wed Dec 28 16:38:29 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.75 released.
-
- * buslogic.c: Spelling fix.
-
- * scsi.c: Add HP C1790A and C2500A scanjet to blacklist.
-
- * scsi.c: Spelling fixup.
-
- * sd.c: Add support for sd_hardsizes (hard sector sizes).
-
- * ultrastor.c: Use save_flags/restore_flags instead of cli/sti.
-
-Fri Dec 23 13:36:25 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.74 released.
-
- * README.st: Update from Kai Makisara.
-
- * eata.c: New version from Dario - version 1.11.
- use scsicam bios_param routine. Add support for 2011
- and 2021 boards.
-
- * hosts.c: Add support for blocking. Linked list automatically
- generated when shpnt->block is set.
-
- * scsi.c: Add sankyo & HP scanjet to blacklist. Add support for
- kicking things loose when we deadlock.
-
- * scsi.c: Recognize scanners and processors in scan_scsis.
-
- * scsi_ioctl.h: Increase timeout to 9 seconds.
-
- * st.c: New version from Kai - add better support for backspace.
-
- * u14-34f.c: New version from Dario. Supports blocking.
-
-Wed Dec 14 14:46:30 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.73 released.
-
- * buslogic.c: Update from Dave Gentzel. Version 1.14.
- Add module related stuff. More fault tolerant if out of
- DMA memory.
-
- * fdomain.c: New version from Rik Faith - version 5.22. Add support
- for ISA-200S SCSI adapter.
-
- * hosts.c: Spelling.
-
- * qlogic.c: Update to version 0.38a. Add more support for PCMCIA.
-
- * scsi.c: Mask device type with 0x1f during scan_scsis.
- Add support for deadlocking, err, make that getting out of
- deadlock situations that are created when we allow the user
- to limit requests to one host adapter at a time.
-
- * scsi.c: Bugfix - pass pid, not SCpnt as second arg to
- scsi_times_out.
-
- * scsi.c: Restore interrupt state to previous value instead of using
- cli/sti pairs.
-
- * scsi.c: Add a bunch of module stuff (all commented out for now).
-
- * scsi.c: Clean up scsi_dump_status.
-
-Tue Dec 6 12:34:20 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.72 released.
-
- * sg.c: Bugfix - always use sg_free, since we might have big buff.
-
-Fri Dec 2 11:24:53 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.71 released.
-
- * sg.c: Clear buff field when not in use. Only call scsi_free if
- non-null.
-
- * scsi.h: Call wake_up(&wait_for_request) when done with a
- command.
-
- * scsi.c (scsi_times_out): Pass pid down so that we can protect
- against race conditions.
-
- * scsi.c (scsi_abort): Zero timeout field if we get the
- NOT_RUNNING message back from low-level driver.
-
-
- * scsi.c (scsi_done): Restore cmd_len, use_sg here.
-
- * scsi.c (request_sense): Not here.
-
- * hosts.h: Add new forbidden_addr, forbidden_size fields. Who
- added these and why????
-
- * hosts.c (scsi_mem_init): Mark pages as reserved if they fall in
- the forbidden regions. I am not sure - I think this is so that
- we can deal with boards that do incomplete decoding of their
- address lines for the bios chips, but I am not entirely sure.
-
- * buslogic.c: Set forbidden_addr stuff if using a buggy board.
-
- * aha1740.c: Test for NULL pointer in SCtmp. This should not
- occur, but a nice message is better than a kernel segfault.
-
- * 53c7,8xx.c: Add new PCI chip ID for 815.
-
-Fri Dec 2 11:24:53 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.70 released.
-
- * ChangeLog, st.c: Spelling.
-
-Tue Nov 29 18:48:42 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.69 released.
-
- * u14-34f.h: Non-functional change. [Dario].
-
- * u14-34f.c: Use block field in Scsi_Host to prevent commands from
- being queued to more than one host at the same time (used when
- motherboard does not deal with multiple bus-masters very well).
- Only when SINGLE_HOST_OPERATIONS is defined.
- Use new cmd_per_lun field. [Dario]
-
- * eata.c: Likewise.
-
- * st.c: More changes from Kai. Add ready flag to indicate drive
- status.
-
- * README.st: Document this.
-
- * sr.c: Bugfix (do not subtract CD_BLOCK_OFFSET) for photo-cd
- code.
-
- * sg.c: Bugfix - fix problem where opcode is not correctly set up.
-
- * seagate.[c,h]: Use #defines to set driver name.
-
- * scsi_ioctl.c: Zero buffer before executing command.
-
- * scsi.c: Use new cmd_per_lun field in Scsi_Hosts as appropriate.
- Add Sony CDU55S to blacklist.
-
- * hosts.h: Add new cmd_per_lun field to Scsi_Hosts.
-
- * hosts.c: Initialize cmd_per_lun in Scsi_Hosts from template.
-
- * buslogic.c: Use cmd_per_lun field - initialize to different
- values depending upon bus type (i.e. use 1 if ISA, so we do not
- hog memory). Use other patches which got lost from 1.1.68.
-
- * aha1542.c: Spelling.
-
-Tue Nov 29 15:43:50 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.68 released.
-
- Add support for 12 byte vendor specific commands in scsi-generics,
- more (i.e. the last mandatory) low-level changes to support
- loadable modules, plus a few other changes people have requested
- lately. Changes by me (ERY) unless otherwise noted. Spelling
- changes appear from some unknown corner of the universe.
-
- * Throughout: Change COMMAND_SIZE() to use SCpnt->cmd_len.
-
- * Throughout: Change info() low level function to take a Scsi_Host
- pointer. This way the info function can return specific
- information about the host in question, if desired.
-
- * All low-level drivers: Add NULL in initializer for the
- usage_count field added to Scsi_Host_Template.
-
- * aha152x.[c,h]: Remove redundant info() function.
-
- * aha1542.[c,h]: Likewise.
-
- * aha1740.[c,h]: Likewise.
-
- * aha274x.[c,h]: Likewise.
-
- * eata.[c,h]: Likewise.
-
- * pas16.[c,h]: Likewise.
-
- * scsi_debug.[c,h]: Likewise.
-
- * t128.[c,h]: Likewise.
-
- * u14-34f.[c,h]: Likewise.
-
- * ultrastor.[c,h]: Likewise.
-
- * wd7000.[c,h]: Likewise.
-
- * aha1542.c: Add support for command line options with lilo to set
- DMA parameters, I/O port. From Matt Aarnio.
-
- * buslogic.[c,h]: New version (1.13) from Dave Gentzel.
-
- * hosts.h: Add new field to Scsi_Hosts "block" to allow blocking
- all I/O to certain other cards. Helps prevent problems with some
- ISA motherboards.
-
- * hosts.h: Add usage_count to Scsi_Host_Template.
-
- * hosts.h: Add n_io_port to Scsi_Host (used when releasing module).
-
- * hosts.c: Initialize block field.
-
- * in2000.c: Remove "static" declarations from exported functions.
-
- * in2000.h: Likewise.
-
- * scsi.c: Correctly set cmd_len field as required. Save and
- change setting when doing a request_sense, restore when done.
- Move abort timeout message. Fix panic in request_queueable to
- print correct function name.
-
- * scsi.c: When incrementing usage count, walk block linked list
- for host, and or in SCSI_HOST_BLOCK bit. When decrementing usage
- count to 0, clear this bit to allow usage to continue, wake up
- processes waiting.
-
-
- * scsi_ioctl.c: If we have an info() function, call it, otherwise
- if we have a "name" field, use it, else do nothing.
-
- * sd.c, sr.c: Clear cmd_len field prior to each command we
- generate.
-
- * sd.h: Add "has_part_table" bit to rscsi_disks.
-
- * sg.[c,h]: Add support for vendor specific 12 byte commands (i.e.
- override command length in COMMAND_SIZE).
-
- * sr.c: Bugfix from Gerd in photocd code.
-
- * sr.c: Bugfix in get_sectorsize - always use scsi_malloc buffer -
- we cannot guarantee that the stack is < 16Mb.
-
-Tue Nov 22 15:40:46 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.67 released.
-
- * sr.c: Change spelling of manufactor to manufacturer.
-
- * scsi.h: Likewise.
-
- * scsi.c: Likewise.
-
- * qlogic.c: Spelling corrections.
-
- * in2000.h: Spelling corrections.
-
- * in2000.c: Update from Bill Earnest, change from
- jshiffle@netcom.com. Support new bios versions.
-
- * README.qlogic: Spelling correction.
-
-Tue Nov 22 15:40:46 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.66 released.
-
- * u14-34f.c: Spelling corrections.
-
- * sr.[h,c]: Add support for multi-session CDs from Gerd Knorr.
-
- * scsi.h: Add manufactor field for keeping track of device
- manufacturer.
-
- * scsi.c: More spelling corrections.
-
- * qlogic.h, qlogic.c, README.qlogic: New driver from Tom Zerucha.
-
- * in2000.c, in2000.h: New driver from Brad McLean/Bill Earnest.
-
- * fdomain.c: Spelling correction.
-
- * eata.c: Spelling correction.
-
-Fri Nov 18 15:22:44 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.65 released.
-
- * eata.h: Update version string to 1.08.00.
-
- * eata.c: Set sg_tablesize correctly for DPT PM2012 boards.
-
- * aha274x.seq: Spell checking.
-
- * README.st: Likewise.
-
- * README.aha274x: Likewise.
-
- * ChangeLog: Likewise.
-
-Tue Nov 15 15:35:08 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.64 released.
-
- * u14-34f.h: Update version number to 1.10.01.
-
- * u14-34f.c: Use Scsi_Host can_queue variable instead of one from template.
-
- * eata.[c,h]: New driver for DPT boards from Dario Ballabio.
-
- * buslogic.c: Use can_queue field.
-
-Wed Nov 30 12:09:09 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.63 released.
-
- * sd.c: Give I/O error if we attempt 512 byte I/O to a disk with
- 1024 byte sectors.
-
- * scsicam.c: Make sure we do read from whole disk (mask off
- partition).
-
- * scsi.c: Use can_queue in Scsi_Host structure.
- Fix panic message about invalid host.
-
- * hosts.c: Initialize can_queue from template.
-
- * hosts.h: Add can_queue to Scsi_Host structure.
-
- * aha1740.c: Print out warning about NULL ecbptr.
-
-Fri Nov 4 12:40:30 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.62 released.
-
- * fdomain.c: Update to version 5.20. (From Rik Faith). Support
- BIOS version 3.5.
-
- * st.h: Add ST_EOD symbol.
-
- * st.c: Patches from Kai Makisara - support additional densities,
- add support for MTFSS, MTBSS, MTWSM commands.
-
- * README.st: Update to document new commands.
-
- * scsi.c: Add Mediavision CDR-H93MV to blacklist.
-
-Sat Oct 29 20:57:36 1994 Eric Youngdale (eric@andante.aib.com)
-
- * Linux 1.1.60 released.
-
- * u14-34f.[c,h]: New driver from Dario Ballabio.
-
- * aic7770.c, aha274x_seq.h, aha274x.seq, aha274x.h, aha274x.c,
- README.aha274x: New files, new driver from John Aycock.
-
-
-Tue Oct 11 08:47:39 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.54 released.
-
- * Add third PCI chip id. [Drew]
-
- * buslogic.c: Set BUSLOGIC_CMDLUN back to 1 [Eric].
-
- * ultrastor.c: Fix asm directives for new GCC.
-
- * sr.c, sd.c: Use new end_scsi_request function.
-
- * scsi.h(end_scsi_request): Return pointer to block if still
- active, else return NULL if inactive. Fixes race condition.
-
-Sun Oct 9 20:23:14 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.53 released.
-
- * scsi.c: Do not allocate dma bounce buffers if we have exactly
- 16Mb.
-
-Fri Sep 9 05:35:30 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.51 released.
-
- * aha152x.c: Add support for disabling the parity check. Update
- to version 1.4. [Juergen].
-
- * seagate.c: Tweak debugging message.
-
-Wed Aug 31 10:15:55 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.50 released.
-
- * aha152x.c: Add eb800 for Vtech Platinum SMP boards. [Juergen].
-
- * scsi.c: Add Quantum PD1225S to blacklist.
-
-Fri Aug 26 09:38:45 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.49 released.
-
- * sd.c: Fix bug when we were deleting the wrong entry if we
- get an unsupported sector size device.
-
- * sr.c: Another spelling patch.
-
-Thu Aug 25 09:15:27 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.48 released.
-
- * Throughout: Use new semantics for request_dma, as appropriate.
-
- * sr.c: Print correct device number.
-
-Sun Aug 21 17:49:23 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.47 released.
-
- * NCR5380.c: Add support for LIMIT_TRANSFERSIZE.
-
- * constants.h: Add prototype for print_Scsi_Cmnd.
-
- * pas16.c: Some more minor tweaks. Test for Mediavision board.
- Allow for disks > 1Gb. [Drew??]
-
- * sr.c: Set SCpnt->transfersize.
-
-Tue Aug 16 17:29:35 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.46 released.
-
- * Throughout: More spelling fixups.
-
- * buslogic.c: Add a few more fixups from Dave. Disk translation
- mainly.
-
- * pas16.c: Add a few patches (Drew?).
-
-
-Thu Aug 11 20:45:15 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.44 released.
-
- * hosts.c: Add type casts for scsi_init_malloc.
-
- * scsicam.c: Add type cast.
-
-Wed Aug 10 19:23:01 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.43 released.
-
- * Throughout: Spelling cleanups. [??]
-
- * aha152x.c, NCR53*.c, fdomain.c, g_NCR5380.c, pas16.c, seagate.c,
- t128.c: Use request_irq, not irqaction. [??]
-
- * aha1542.c: Move test for shost before we start to use shost.
-
- * aha1542.c, aha1740.c, ultrastor.c, wd7000.c: Use new
- calling sequence for request_irq.
-
- * buslogic.c: Update from Dave Gentzel.
-
-Tue Aug 9 09:32:59 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.42 released.
-
- * NCR5380.c: Change NCR5380_print_status to static.
-
- * seagate.c: A few more bugfixes. Only Drew knows what they are
- for.
-
- * ultrastor.c: Tweak some __asm__ directives so that it works
- with newer compilers. [??]
-
-Sat Aug 6 21:29:36 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.40 released.
-
- * NCR5380.c: Return SCSI_RESET_WAKEUP from reset function.
-
- * aha1542.c: Reset mailbox status after a bus device reset.
-
- * constants.c: Fix typo (;;).
-
- * g_NCR5380.c:
- * pas16.c: Correct usage of NCR5380_init.
-
- * scsi.c: Remove redundant (and unused variables).
-
- * sd.c: Use memset to clear all of rscsi_disks before we use it.
-
- * sg.c: Ditto, except for scsi_generics.
-
- * sr.c: Ditto, except for scsi_CDs.
-
- * st.c: Initialize STp->device.
-
- * seagate.c: Fix bug. [Drew]
-
-Thu Aug 4 08:47:27 1994 Eric Youngdale (eric@andante)
-
- * Linux 1.1.39 released.
-
- * Makefile: Fix typo in NCR53C7xx.
-
- * st.c: Print correct number for device.
-
-Tue Aug 2 11:29:14 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.38 released.
-
- Lots of changes in 1.1.38. All from Drew unless otherwise noted.
-
- * 53c7,8xx.c: New file from Drew. PCI driver.
-
- * 53c7,8xx.h: Likewise.
-
- * 53c7,8xx.scr: Likewise.
-
- * 53c8xx_d.h, 53c8xx_u.h, script_asm.pl: Likewise.
-
- * scsicam.c: New file from Drew. Read block 0 on the disk and
- read the partition table. Attempt to deduce the geometry from
- the partition table if possible. Only used by 53c[7,8]xx right
- now, but could be used by any device for which we have no way
- of identifying the geometry.
-
- * sd.c: Use device letters instead of sd%d in a lot of messages.
-
- * seagate.c: Fix bug that resulted in lockups with some devices.
-
- * sr.c (sr_open): Return -EROFS, not -EACCES if we attempt to open
- device for write.
-
- * hosts.c, Makefile: Update for new driver.
-
- * NCR5380.c, NCR5380.h, g_NCR5380.h: Update from Drew to support
- 53C400 chip.
-
- * constants.c: Define CONST_CMND and CONST_MSG. Other minor
- cleanups along the way. Improve handling of CONST_MSG.
-
- * fdomain.c, fdomain.h: New version from Rik Faith. Update to
- 5.18. Should now support TMC-3260 PCI card with 18C30 chip.
-
- * pas16.c: Update with new irq initialization.
-
- * t128.c: Update with minor cleanups.
-
- * scsi.c (scsi_pid): New variable - gives each command a unique
- id. Add Quantum LPS5235S to blacklist. Change in_scan to
- in_scan_scsis and make global.
-
- * scsi.h: Add some defines for extended message handling,
- INITIATE/RELEASE_RECOVERY. Add a few new fields to support sync
- transfers.
-
- * scsi_ioctl.h: Add ioctl to request synchronous transfers.
-
-
-Tue Jul 26 21:36:58 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.37 released.
-
- * aha1542.c: Always call aha1542_mbenable, use new udelay
- mechanism so we do not wait a long time if the board does not
- implement this command.
-
- * g_NCR5380.c: Remove #include <linux/config.h> and #if
- defined(CONFIG_SCSI_*).
-
- * seagate.c: Likewise.
-
- Next round of changes to support loadable modules. Getting closer
- now, still not possible to do anything remotely usable.
-
- hosts.c: Create a linked list of detected high level devices.
- (scsi_register_device): New function to insert into this list.
- (scsi_init): Call scsi_register_device for each of the known high
- level drivers.
-
- hosts.h: Add prototype for linked list header. Add structure
- definition for device template structure which defines the linked
- list.
-
- scsi.c: (scan_scsis): Use linked list instead of knowledge about
- existing high level device drivers.
- (scsi_dev_init): Use init functions for drivers on linked list
- instead of explicit list to initialize and attach devices to high
- level drivers.
-
- scsi.h: Add new field "attached" to scsi_device - count of number
- of high level devices attached.
-
- sd.c, sr.c, sg.c, st.c: Adjust init/attach functions to use new
- scheme.
-
-Sat Jul 23 13:03:17 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.35 released.
-
- * ultrastor.c: Change constraint on asm() operand so that it works
- with gcc 2.6.0.
-
-Thu Jul 21 10:37:39 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.33 released.
-
- * sr.c(sr_open): Do not allow opens with write access.
-
-Mon Jul 18 09:51:22 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.31 released.
-
- * sd.c: Increase SD_TIMEOUT from 300 to 600.
-
- * sr.c: Remove stray task_struct* variable that was no longer
- used.
-
- * sr_ioctl.c: Fix typo in up() call.
-
-Sun Jul 17 16:25:29 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.30 released.
-
- * scsi.c (scan_scsis): Fix detection of some Toshiba CDROM drives
- that report themselves as disk drives.
-
- * (Throughout): Use request.sem instead of request.waiting.
- Should fix swap problem with fdomain.
-
-Thu Jul 14 10:51:42 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.29 released.
-
- * scsi.c (scan_scsis): Add new devices to end of linked list, not
- to the beginning.
-
- * scsi.h (SCSI_SLEEP): Remove brain dead hack to try to save
- the task state before sleeping.
-
-Sat Jul 9 15:01:03 1994 Eric Youngdale (eric@esp22)
-
- More changes to eventually support loadable modules. Mainly
- we want to use linked lists instead of arrays because it is easier
- to dynamically add and remove things this way.
-
- Quite a bit more work is needed before loadable modules are
- possible (and usable) with scsi, but this is most of the grunge
- work.
-
- * Linux 1.1.28 released.
-
- * scsi.c, scsi.h (allocate_device, request_queueable): Change
- argument from index into scsi_devices to a pointer to the
- Scsi_Device struct.
-
- * Throughout: Change all calls to allocate_device,
- request_queueable to use new calling sequence.
-
- * Throughout: Use SCpnt->device instead of
- scsi_devices[SCpnt->index]. Ugh - the pointer was there all along
- - much cleaner this way.
-
- * scsi.c (scsi_init_malloc, scsi_free_malloc): New functions -
- allow us to pretend that we have a working malloc when we
- initialize. Use this instead of passing memory_start, memory_end
- around all over the place.
-
- * scsi.h, st.c, sr.c, sd.c, sg.c: Change *_init1 functions to use
- scsi_init_malloc, remove all arguments, no return value.
-
- * scsi.h: Remove index field from Scsi_Device and Scsi_Cmnd
- structs.
-
- * scsi.c (scsi_dev_init): Set up for scsi_init_malloc.
- (scan_scsis): Get SDpnt from scsi_init_malloc, and refresh
- when we discover a device. Free pointer before returning.
- Change scsi_devices into a linked list.
-
- * scsi.c (scan_scsis): Change to only scan one host.
- (scsi_dev_init): Loop over all detected hosts, and scan them.
-
- * hosts.c (scsi_init_free): Change so that number of extra bytes
- is stored in struct, and we do not have to pass it each time.
-
- * hosts.h: Change Scsi_Host_Template struct to include "next" and
- "release" functions. Initialize to NULL in all low level
- adapters.
-
- * hosts.c: Rename scsi_hosts to builtin_scsi_hosts, create linked
- list scsi_hosts, linked together with the new "next" field.
-
-Wed Jul 6 05:45:02 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.25 released.
-
- * aha152x.c: Changes from Juergen - cleanups and updates.
-
- * sd.c, sr.c: Use new check_media_change and revalidate
- file_operations fields.
-
- * st.c, st.h: Add changes from Kai Makisara, dated Jun 22.
-
- * hosts.h: Change SG_ALL back to 0xff. Apparently soft error
- in /dev/brain resulted in having this bumped up.
- Change first parameter in bios_param function to be Disk * instead
- of index into rscsi_disks.
-
- * sd_ioctl.c: Pass pointer to rscsi_disks element instead of index
- to array.
-
- * sd.h: Add struct name "scsi_disk" to typedef for Scsi_Disk.
-
- * scsi.c: Remove redundant Maxtor XT8760S from blacklist.
- In scsi_reset, add printk when DEBUG defined.
-
- * All low level drivers: Modify definitions of bios_param in
- appropriate way.
-
-Thu Jun 16 10:31:59 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.20 released.
-
- * scsi_ioctl.c: Only pass down the actual number of characters
- required to scsi_do_cmd, not the one rounded up to a even number
- of sectors.
-
- * ultrastor.c: Changes from Caleb Epstein for 24f cards. Support
- larger SG lists.
-
- * ultrastor.c: Changes from me - use scsi_register to register
- host. Add some consistency checking,
-
-Wed Jun 1 21:12:13 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.19 released.
-
- * scsi.h: Add new return code for reset() function:
- SCSI_RESET_PUNT.
-
- * scsi.c: Make SCSI_RESET_PUNT the same as SCSI_RESET_WAKEUP for
- now.
-
- * aha1542.c: If the command responsible for the reset is not
- pending, return SCSI_RESET_PUNT.
-
- * aha1740.c, buslogic.c, wd7000.c, ultrastor.c: Return
- SCSI_RESET_PUNT instead of SCSI_RESET_SNOOZE.
-
-Tue May 31 19:36:01 1994 Eric Youngdale (eric@esp22)
-
- * buslogic.c: Do not print out message about "must be Adaptec"
- if we have detected a buslogic card. Print out a warning message
- if we are configuring for >16Mb, since the 445S at board level
- D or earlier does not work right. The "D" level board can be made
- to work by flipping an undocumented switch, but this is too subtle.
-
- Changes based upon patches in Yggdrasil distribution.
-
- * sg.c, sg.h: Return sense data to user.
-
- * aha1542.c, aha1740.c, buslogic.c: Do not panic if
- sense buffer is wrong size.
-
- * hosts.c: Test for ultrastor card before any of the others.
-
- * scsi.c: Allow boot-time option for max_scsi_luns=? so that
- buggy firmware has an easy work-around.
-
-Sun May 15 20:24:34 1994 Eric Youngdale (eric@esp22)
-
- * Linux 1.1.15 released.
-
- Post-codefreeze thaw...
-
- * buslogic.[c,h]: New driver from David Gentzel.
-
- * hosts.h: Add use_clustering field to explicitly say whether
- clustering should be used for devices attached to this host
- adapter. The buslogic board apparently supports large SG lists,
- but it is apparently faster if sd.c condenses this into a smaller
- list.
-
- * sd.c: Use this field instead of heuristic.
-
- * All host adapter include files: Add appropriate initializer for
- use_clustering field.
-
- * scsi.h: Add #defines for return codes for the abort and reset
- functions. There are now a specific set of return codes to fully
- specify all of the possible things that the low-level adapter
- could do.
-
- * scsi.c: Act based upon return codes from abort/reset functions.
-
- * All host adapter abort/reset functions: Return new return code.
-
- * Add code in scsi.c to help debug timeouts. Use #define
- DEBUG_TIMEOUT to enable this.
-
- * scsi.c: If the host->irq field is set, use
- disable_irq/enable_irq before calling queuecommand if we
- are not already in an interrupt. Reduce races, and we
- can be sloppier about cli/sti in the interrupt routines now
- (reduce interrupt latency).
-
- * constants.c: Fix some things to eliminate warnings. Add some
- sense descriptions that were omitted before.
-
- * aha1542.c: Watch for SCRD from host adapter - if we see it, set
- a flag. Currently we only print out the number of pending
- commands that might need to be restarted.
-
- * aha1542.c (aha1542_abort): Look for lost interrupts, OGMB still
- full, and attempt to recover. Otherwise give up.
-
- * aha1542.c (aha1542_reset): Try BUS DEVICE RESET, and then pass
- DID_RESET back up to the upper level code for all commands running
- on this target (even on different LUNs).
-
-Sat May 7 14:54:01 1994
-
- * Linux 1.1.12 released.
-
- * st.c, st.h: New version from Kai. Supports boot time
- specification of number of buffers.
-
- * wd7000.[c,h]: Updated driver from John Boyd. Now supports
- more than one wd7000 board in machine at one time, among other things.
-
-Wed Apr 20 22:20:35 1994
-
- * Linux 1.1.8 released.
-
- * sd.c: Add a few type casts where scsi_malloc is called.
-
-Wed Apr 13 12:53:29 1994
-
- * Linux 1.1.4 released.
-
- * scsi.c: Clean up a few printks (use %p to print pointers).
-
-Wed Apr 13 11:33:02 1994
-
- * Linux 1.1.3 released.
-
- * fdomain.c: Update to version 5.16 (Handle different FIFO sizes
- better).
-
-Fri Apr 8 08:57:19 1994
-
- * Linux 1.1.2 released.
-
- * Throughout: SCSI portion of cluster diffs added.
-
-Tue Apr 5 07:41:50 1994
-
- * Linux 1.1 development tree initiated.
-
- * The linux 1.0 development tree is now effectively frozen except
- for obvious bugfixes.
-
-******************************************************************
-******************************************************************
-******************************************************************
-******************************************************************
-
-Sun Apr 17 00:17:39 1994
-
- * Linux 1.0, patchlevel 9 released.
-
- * fdomain.c: Update to version 5.16 (Handle different FIFO sizes
- better).
-
-Thu Apr 7 08:36:20 1994
-
- * Linux 1.0, patchlevel8 released.
-
- * fdomain.c: Update to version 5.15 from 5.9. Handles 3.4 bios.
-
-Sun Apr 3 14:43:03 1994
-
- * Linux 1.0, patchlevel6 released.
-
- * wd7000.c: Make stab at fixing race condition.
-
-Sat Mar 26 14:14:50 1994
-
- * Linux 1.0, patchlevel5 released.
-
- * aha152x.c, Makefile: Fix a few bugs (too much data message).
- Add a few more bios signatures. (Patches from Juergen).
-
- * aha1542.c: Fix race condition in aha1542_out.
-
-Mon Mar 21 16:36:20 1994
-
- * Linux 1.0, patchlevel3 released.
-
- * sd.c, st.c, sr.c, sg.c: Return -ENXIO, not -ENODEV if we attempt
- to open a non-existent device.
-
- * scsi.c: Add Chinon cdrom to blacklist.
-
- * sr_ioctl.c: Check return status of verify_area.
-
-Sat Mar 6 16:06:19 1994
-
- * Linux 1.0 released (technically a pre-release).
-
- * scsi.c: Add IMS CDD521, Maxtor XT-8760S to blacklist.
-
-Tue Feb 15 10:58:20 1994
-
- * pl15e released.
-
- * aha1542.c: For 1542C, allow dynamic device scan with >1Gb turned
- off.
-
- * constants.c: Fix typo in definition of CONSTANTS.
-
- * pl15d released.
-
-Fri Feb 11 10:10:16 1994
-
- * pl15c released.
-
- * scsi.c: Add Maxtor XT-3280 and Rodime RO3000S to blacklist.
-
- * scsi.c: Allow tagged queueing for scsi 3 devices as well.
- Some really old devices report a version number of 0. Disallow
- LUN != 0 for these.
-
-Thu Feb 10 09:48:57 1994
-
- * pl15b released.
-
-Sun Feb 6 12:19:46 1994
-
- * pl15a released.
-
-Fri Feb 4 09:02:17 1994
-
- * scsi.c: Add Teac cdrom to blacklist.
-
-Thu Feb 3 14:16:43 1994
-
- * pl15 released.
-
-Tue Feb 1 15:47:43 1994
-
- * pl14w released.
-
- * wd7000.c (wd_bases): Fix typo in last change.
-
-Mon Jan 24 17:37:23 1994
-
- * pl14u released.
-
- * aha1542.c: Support 1542CF/extended bios. Different from 1542C
-
- * wd7000.c: Allow bios at 0xd8000 as well.
-
- * ultrastor.c: Do not truncate cylinders to 1024.
-
- * fdomain.c: Update to version 5.9 (add new bios signature).
-
- * NCR5380.c: Update from Drew - should work a lot better now.
-
-Sat Jan 8 15:13:10 1994
-
- * pl14o released.
-
- * sr_ioctl.c: Zero reserved field before trying to set audio volume.
-
-Wed Jan 5 13:21:10 1994
-
- * pl14m released.
-
- * fdomain.c: Update to version 5.8. No functional difference???
-
-Tue Jan 4 14:26:13 1994
-
- * pl14l released.
-
- * ultrastor.c: Remove outl, inl functions (now provided elsewhere).
-
-Mon Jan 3 12:27:25 1994
-
- * pl14k released.
-
- * aha152x.c: Remove insw and outsw functions.
-
- * fdomain.c: Ditto.
-
-Wed Dec 29 09:47:20 1993
-
- * pl14i released.
-
- * scsi.c: Support RECOVERED_ERROR for tape drives.
-
- * st.c: Update of tape driver from Kai.
-
-Tue Dec 21 09:18:30 1993
-
- * pl14g released.
-
- * aha1542.[c,h]: Support extended BIOS stuff.
-
- * scsi.c: Clean up messages about disks, so they are displayed as
- sda, sdb, etc instead of sd0, sd1, etc.
-
- * sr.c: Force reread of capacity if disk was changed.
- Clear buffer before asking for capacity/sectorsize (some drives
- do not report this properly). Set needs_sector_size flag if
- drive did not return sensible sector size.
-
-Mon Dec 13 12:13:47 1993
-
- * aha152x.c: Update to version .101 from Juergen.
-
-Mon Nov 29 03:03:00 1993
-
- * linux 0.99.14 released.
-
- * All scsi stuff moved from kernel/blk_drv/scsi to drivers/scsi.
-
- * Throughout: Grammatical corrections to various comments.
-
- * Makefile: fix so that we do not need to compile things we are
- not going to use.
-
- * NCR5380.c, NCR5380.h, g_NCR5380.c, g_NCR5380.h, pas16.c,
- pas16.h, t128.c, t128.h: New files from Drew.
-
- * aha152x.c, aha152x.h: New files from Juergen Fischer.
-
- * aha1542.c: Support for more than one 1542 in the machine
- at the same time. Make functions static that do not need
- visibility.
-
- * aha1740.c: Set NEEDS_JUMPSTART flag in reset function, so we
- know to restart the command. Change prototype of aha1740_reset
- to take a command pointer.
-
- * constants.c: Clean up a few things.
-
- * fdomain.c: Update to version 5.6. Move snarf_region. Allow
- board to be set at different SCSI ids. Remove support for
- reselection (did not work well). Set JUMPSTART flag in reset
- code.
-
- * hosts.c: Support new low-level adapters. Allow for more than
- one adapter of a given type.
-
- * hosts.h: Allow for more than one adapter of a given type.
-
- * scsi.c: Add scsi_device_types array, if NEEDS_JUMPSTART is set
- after a low-level reset, start the command again. Sort blacklist,
- and add Maxtor MXT-1240S, XT-4170S, NEC CDROM 84, Seagate ST157N.
-
- * scsi.h: Add constants for tagged queueing.
-
- * Throughout: Use constants from major.h instead of hardcoded
- numbers for major numbers.
-
- * scsi_ioctl.c: Fix bug in buffer length in ioctl_command. Use
- verify_area in GET_IDLUN ioctl. Add new ioctls for
- TAGGED_QUEUE_ENABLE, DISABLE. Only allow IOCTL_SEND_COMMAND by
- superuser.
-
- * sd.c: Only pay attention to UNIT_ATTENTION for removable disks.
- Fix bug where sometimes portions of blocks would get lost
- resulting in processes hanging. Add messages when we spin up a
- disk, and fix a bug in the timing. Increase read-ahead for disks
- that are on a scatter-gather capable host adapter.
-
- * seagate.c: Fix so that some parameters can be set from the lilo
- prompt. Supply jumpstart flag if we are resetting and need the
- command restarted. Fix so that we return 1 if we detect a card
- so that multiple card detection works correctly. Add yet another
- signature for FD cards (950). Add another signature for ST0x.
-
- * sg.c, sg.h: New files from Lawrence Foard for generic scsi
- access.
-
- * sr.c: Add type casts for (void*) so that we can do pointer
- arithmetic. Works with GCC without this, but it is not strictly
- correct. Same bugfix as was in sd.c. Increase read-ahead a la
- disk driver.
-
- * sr_ioctl.c: Use scsi_malloc buffer instead of buffer from stack
- since we cannot guarantee that the stack is < 16Mb.
-
- ultrastor.c: Update to support 24f properly (JFC's driver).
-
- wd7000.c: Supply jumpstart flag for reset. Do not round up
- number of cylinders in biosparam function.
-
-Sat Sep 4 20:49:56 1993
-
- * 0.99pl13 released.
-
- * Throughout: Use check_region/snarf_region for all low-level
- drivers.
-
- * aha1542.c: Do hard reset instead of soft (some ethercard probes
- screw us up).
-
- * scsi.c: Add new flag ASKED_FOR_SENSE so that we can tell if we are
- in a loop whereby the device returns null sense data.
-
- * sd.c: Add code to spin up a drive if it is not already spinning.
- Do this one at a time to make it easier on power supplies.
-
- * sd_ioctl.c: Use sync_dev instead of fsync_dev in BLKFLSBUF ioctl.
-
- * seagate.c: Switch around DATA/CONTROL lines.
-
- * st.c: Change sense to unsigned.
-
-Thu Aug 5 11:59:18 1993
-
- * 0.99pl12 released.
-
- * constants.c, constants.h: New files with ascii descriptions of
- various conditions.
-
- * Makefile: Do not try to count the number of low-level drivers,
- just generate the list of .o files.
-
- * aha1542.c: Replace 16 with sizeof(SCpnt->sense_buffer). Add tests
- for addresses > 16Mb, panic if we find one.
-
- * aha1740.c: Ditto with sizeof().
-
- * fdomain.c: Update to version 3.18. Add new signature, register IRQ
- with irqaction. Use ID 7 for new board. Be more intelligent about
- obtaining the h/s/c numbers for biosparam.
-
- * hosts.c: Do not depend upon Makefile generated count of the number
- of low-level host adapters.
-
- * scsi.c: Use array for scsi_command_size instead of a function. Add
- Texel cdrom and Maxtor XT-4380S to blacklist. Allow compile time
- option for no-multi lun scan. Add semaphore for possible problems
- with handshaking, assume device is faulty until we know it not to be
- the case. Add DEBUG_INIT symbol to dump info as we scan for devices.
- Zero sense buffer so we can tell if we need to request it. When
- examining sense information, request sense if buffer is all zero.
- If RESET, request sense information to see what to do next.
-
- * scsi_debug.c: Change some constants to use symbols like INT_MAX.
-
- * scsi_ioctl.c (kernel_scsi_ioctl): New function -for making ioctl
- calls from kernel space.
-
- * sd.c: Increase timeout to 300. Use functions in constants.h to
- display info. Use scsi_malloc buffer for READ_CAPACITY, since
- we cannot guarantee that a stack based buffer is < 16Mb.
-
- * sd_ioctl.c: Add BLKFLSBUF ioctl.
-
- * seagate.c: Add new compile time options for ARBITRATE,
- SLOW_HANDSHAKE, and SLOW_RATE. Update assembly loops for transferring
- data. Use kernel_scsi_ioctl to request mode page with geometry.
-
- * sr.c: Use functions in constants.c to display messages.
-
- * st.c: Support for variable block size.
-
- * ultrastor.c: Do not use cache for tape drives. Set
- unchecked_isa_dma flag, even though this may not be needed (gets set
- later).
-
-Sat Jul 17 18:32:44 1993
-
- * 0.99pl11 released. C++ compilable.
-
- * Throughout: Add type casts all over the place, and use "ip" instead
- of "info" in the various biosparam functions.
-
- * Makefile: Compile seagate.c with C++ compiler.
-
- * aha1542.c: Always set ccb pointer as this gets trashed somehow on
- some systems. Add a few type casts. Update biosparam function a little.
-
- * aha1740.c: Add a few type casts.
-
- * fdomain.c: Update to version 3.17 from 3.6. Now works with
- TMC-18C50.
-
- * scsi.c: Minor changes here and there with datatypes. Save use_sg
- when requesting sense information so that this can properly be
- restored if we retry the command. Set aside dma buffers assuming each
- block is 1 page, not 1Kb minix block.
-
- * scsi_ioctl.c: Add a few type casts. Other minor changes.
-
- * sd.c: Correctly free all scsi_malloc'd memory if we run out of
- dma_pool. Store blocksize information for each partition.
-
- * seagate.c: Minor cleanups here and there.
-
- * sr.c: Set up blocksize array for all discs. Fix bug in freeing
- buffers if we run out of dma pool.
-
-Thu Jun 2 17:58:11 1993
-
- * 0.99pl10 released.
-
- * aha1542.c: Support for BT 445S (VL-bus board with no dma channel).
-
- * fdomain.c: Upgrade to version 3.6. Preliminary support for TNC-18C50.
-
- * scsi.c: First attempt to fix problem with old_use_sg. Change
- NOT_READY to a SUGGEST_ABORT. Fix timeout race where time might
- get decremented past zero.
-
- * sd.c: Add block_fsync function to dispatch table.
-
- * sr.c: Increase timeout to 500 from 250. Add entry for sync in
- dispatch table (supply NULL). If we do not have a sectorsize,
- try to get it in the sd_open function. Add new function just to
- obtain sectorsize.
-
- * sr.h: Add needs_sector_size semaphore.
-
- * st.c: Add NULL for fsync in dispatch table.
-
- * wd7000.c: Allow another condition for power on that are normal
- and do not require a panic.
-
-Thu Apr 22 23:10:11 1993
-
- * 0.99pl9 released.
-
- * aha1542.c: Use (void) instead of () in setup_mailboxes.
-
- * scsi.c: Initialize transfersize and underflow fields in SCmd to 0.
- Do not panic for unsupported message bytes.
-
- * scsi.h: Allocate 12 bytes instead of 10 for commands. Add
- transfersize and underflow fields.
-
- * scsi_ioctl.c: Further bugfix to ioctl_probe.
-
- * sd.c: Use long instead of int for last parameter in sd_ioctl.
- Initialize transfersize and underflow fields.
-
- * sd_ioctl.c: Ditto for sd_ioctl(,,,,);
-
- * seagate.c: New version from Drew. Includes new signatures for FD
- cards. Support for 0ws jumper. Correctly initialize
- scsi_hosts[hostnum].this_id. Improved handing of
- disconnect/reconnect, and support command linking. Use
- transfersize and underflow fields. Support scatter-gather.
-
- * sr.c, sr_ioctl.c: Use long instead of int for last parameter in sr_ioctl.
- Use buffer and buflength in do_ioctl. Patches from Chris Newbold for
- scsi-2 audio commands.
-
- * ultrastor.c: Comment out in_byte (compiler warning).
-
- * wd7000.c: Change () to (void) in wd7000_enable_dma.
-
-Wed Mar 31 16:36:25 1993
-
- * 0.99pl8 released.
-
- * aha1542.c: Handle mailboxes better for 1542C.
- Do not truncate number of cylinders at 1024 for biosparam call.
-
- * aha1740.c: Fix a few minor bugs for multiple devices.
- Same as above for biosparam.
-
- * scsi.c: Add lockable semaphore for removable devices that can have
- media removal prevented. Add another signature for flopticals.
- (allocate_device): Fix race condition. Allow more space in dma pool
- for blocksizes of up to 4Kb.
-
- * scsi.h: Define COMMAND_SIZE. Define a SCSI specific version of
- INIT_REQUEST that can run with interrupts off.
-
- * scsi_ioctl.c: Make ioctl_probe function more idiot-proof. If
- a removable device says ILLEGAL REQUEST to a door-locking command,
- clear lockable flag. Add SCSI_IOCTL_GET_IDLUN ioctl. Do not attempt
- to lock door for devices that do not have lockable semaphore set.
-
- * sd.c: Fix race condition for multiple disks. Use INIT_SCSI_REQUEST
- instead of INIT_REQUEST. Allow sector sizes of 1024 and 256. For
- removable disks that are not ready, mark them as having a media change
- (some drives do not report this later).
-
- * seagate.c: Use volatile keyword for memory-mapped register pointers.
-
- * sr.c: Fix race condition, a la sd.c. Increase the number of retries
- to 1. Use INIT_SCSI_REQUEST. Allow 512 byte sector sizes. Do a
- read_capacity when we init the device so we know the size and
- sectorsize.
-
- * st.c: If ioctl not found in st.c, try scsi_ioctl for others.
-
- * ultrastor.c: Do not truncate number of cylinders at 1024 for
- biosparam call.
-
- * wd7000.c: Ditto.
- Throughout: Use COMMAND_SIZE macro to determine length of scsi
- command.
-
-
-
-Sat Mar 13 17:31:29 1993
-
- * 0.99pl7 released.
-
- Throughout: Improve punctuation in some messages, and use new
- verify_area syntax.
-
- * aha1542.c: Handle unexpected interrupts better.
-
- * scsi.c: Ditto. Handle reset conditions a bit better, asking for
- sense information and retrying if required.
-
- * scsi_ioctl.c: Allow for 12 byte scsi commands.
-
- * ultrastor.c: Update to use scatter-gather.
-
-Sat Feb 20 17:57:15 1993
-
- * 0.99pl6 released.
-
- * fdomain.c: Update to version 3.5. Handle spurious interrupts
- better.
-
- * sd.c: Use register_blkdev function.
-
- * sr.c: Ditto.
-
- * st.c: Use register_chrdev function.
-
- * wd7000.c: Undo previous change.
-
-Sat Feb 6 11:20:43 1993
-
- * 0.99pl5 released.
-
- * scsi.c: Fix bug in testing for UNIT_ATTENTION.
-
- * wd7000.c: Check at more addresses for bios. Fix bug in biosparam
- (heads & sectors turned around).
-
-Wed Jan 20 18:13:59 1993
-
- * 0.99pl4 released.
-
- * scsi.c: Ignore leading spaces when looking for blacklisted devices.
-
- * seagate.c: Add a few new signatures for FD cards. Another patch
- with SCint to fix race condition. Use recursion_depth to keep track
- of how many times we have been recursively called, and do not start
- another command unless we are on the outer level. Fixes bug
- with Syquest cartridge drives (used to crash kernel), because
- they do not disconnect with large data transfers.
-
-Tue Jan 12 14:33:36 1993
-
- * 0.99pl3 released.
-
- * fdomain.c: Update to version 3.3 (a few new signatures).
-
- * scsi.c: Add CDU-541, Denon DRD-25X to blacklist.
- (allocate_request, request_queueable): Init request.waiting to NULL if
- non-buffer type of request.
-
- * seagate.c: Allow controller to be overridden with CONTROLLER symbol.
- Set SCint=NULL when we are done, to remove race condition.
-
- * st.c: Changes from Kai.
-
-Wed Dec 30 20:03:47 1992
-
- * 0.99pl2 released.
-
- * scsi.c: Blacklist back in. Remove Newbury drive as other bugfix
- eliminates need for it here.
-
- * sd.c: Return ENODEV instead of EACCES if no such device available.
- (sd_init) Init blkdev_fops earlier so that sd_open is available sooner.
-
- * sr.c: Same as above for sd.c.
-
- * st.c: Return ENODEV instead of ENXIO if no device. Init chrdev_fops
- sooner, so that it is always there even if no tapes.
-
- * seagate.c (controller_type): New variable to keep track of ST0x or
- FD. Modify signatures list to indicate controller type, and init
- controller_type once we find a match.
-
- * wd7000.c (wd7000_set_sync): Remove redundant function.
-
-Sun Dec 20 16:26:24 1992
-
- * 0.99pl1 released.
-
- * scsi_ioctl.c: Bugfix - check dev->index, not dev->id against
- NR_SCSI_DEVICES.
-
- * sr_ioctl.c: Verify that device exists before allowing an ioctl.
-
- * st.c: Patches from Kai - change timeout values, improve end of tape
- handling.
-
-Sun Dec 13 18:15:23 1992
-
- * 0.99 kernel released. Baseline for this ChangeLog.
diff --git a/Documentation/scsi/Mylex.txt b/Documentation/scsi/Mylex.txt
deleted file mode 100644
index 3797f3e6c2b5..000000000000
--- a/Documentation/scsi/Mylex.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Please see the file README.BusLogic for information about Linux support for
-Mylex (formerly BusLogic) MultiMaster and FlashPoint SCSI Host Adapters.
-
-The Mylex DAC960 PCI RAID Controllers are now supported. Please consult
-http://sourceforge.net/projects/dandelion for further information on the DAC960 driver.
diff --git a/Documentation/scsi/scsi-parameters.txt b/Documentation/scsi/scsi-parameters.txt
index 453d4b79c78d..25a4b4cf04a6 100644
--- a/Documentation/scsi/scsi-parameters.txt
+++ b/Documentation/scsi/scsi-parameters.txt
@@ -34,11 +34,6 @@ parameters may be changed at runtime by the command
See drivers/scsi/BusLogic.c, comment before function
BusLogic_ParseDriverOptions().
- eata= [HW,SCSI]
-
- fdomain= [HW,SCSI]
- See header of drivers/scsi/fdomain.c.
-
gdth= [HW,SCSI]
See header of drivers/scsi/gdth.c.
@@ -70,8 +65,6 @@ parameters may be changed at runtime by the command
ncr53c400a= [HW,SCSI]
See Documentation/scsi/g_NCR5380.txt.
- ncr53c406a= [HW,SCSI]
-
ncr53c8xx= [HW,SCSI]
osst= [HW,SCSI] SCSI Tape Driver
@@ -110,12 +103,5 @@ parameters may be changed at runtime by the command
st= [HW,SCSI] SCSI tape parameters (buffers, etc.)
See Documentation/scsi/st.txt.
- sym53c416= [HW,SCSI]
- See header of drivers/scsi/sym53c416.c.
-
- tmscsim= [HW,SCSI]
- See comment before function dc390_setup() in
- drivers/scsi/tmscsim.c.
-
wd33c93= [HW,SCSI]
See header of drivers/scsi/wd33c93.c.
diff --git a/Documentation/scsi/scsi_mid_low_api.txt b/Documentation/scsi/scsi_mid_low_api.txt
index 2c31d9ee6776..177c031763c0 100644
--- a/Documentation/scsi/scsi_mid_low_api.txt
+++ b/Documentation/scsi/scsi_mid_low_api.txt
@@ -114,9 +114,7 @@ called "xxx" could be defined as
"static int xxx_slave_alloc(struct scsi_device * sdev) { /* code */ }"
** the scsi_host_alloc() function is a replacement for the rather vaguely
-named scsi_register() function in most situations. The scsi_register()
-and scsi_unregister() functions remain to support legacy LLDs that use
-the passive initialization model.
+named scsi_register() function in most situations.
Hotplug initialization model
@@ -228,79 +226,6 @@ slave_configure() callbacks). Such instances are "owned" by the mid-level.
struct scsi_device instances are freed after slave_destroy().
-Passive initialization model
-============================
-These older LLDs include a file called "scsi_module.c" [yes the ".c" is a
-little surprising] in their source code. For that file to work an
-instance of struct scsi_host_template with the name "driver_template"
-needs to be defined. Here is a typical code sequence used in this model:
- static struct scsi_host_template driver_template = {
- ...
- };
- #include "scsi_module.c"
-
-The scsi_module.c file contains two functions:
- - init_this_scsi_driver() which is executed when the LLD is
- initialized (i.e. boot time or module load time)
- - exit_this_scsi_driver() which is executed when the LLD is shut
- down (i.e. module unload time)
-Note: since these functions are tagged with __init and __exit qualifiers
-an LLD should not call them explicitly (since the kernel does that).
-
-Here is an example of an initialization sequence when two hosts are
-detected (so detect() returns 2) and the SCSI bus scan on each host
-finds 1 SCSI device (and a second device does not respond).
-
-LLD mid level LLD
-===----------------------=========-----------------===------
-init_this_scsi_driver() ----+
- |
- detect() -----------------+
- | |
- | scsi_register()
- | scsi_register()
- |
- slave_alloc()
- slave_configure() --> scsi_change_queue_depth()
- slave_alloc() ***
- slave_destroy() ***
- |
- slave_alloc()
- slave_configure()
- slave_alloc() ***
- slave_destroy() ***
-------------------------------------------------------------
-
-The mid level invokes scsi_change_queue_depth() with "cmd_per_lun" for that
-host as the queue length. These settings can be overridden by a
-slave_configure() supplied by the LLD.
-
-*** For scsi devices that the mid level tries to scan but do not
- respond, a slave_alloc(), slave_destroy() pair is called.
-
-Here is an LLD shutdown sequence:
-
-LLD mid level LLD
-===----------------------=========-----------------===------
-exit_this_scsi_driver() ----+
- |
- slave_destroy()
- release() --> scsi_unregister()
- |
- slave_destroy()
- release() --> scsi_unregister()
-------------------------------------------------------------
-
-An LLD need not define slave_destroy() (i.e. it is optional).
-
-The shortcoming of the "passive initialization model" is that host
-registration and de-registration are (typically) tied to LLD initialization
-and shutdown. Once the LLD is initialized then a new host that appears
-(e.g. via hotplugging) cannot easily be added without a redundant
-driver shutdown and re-initialization. It may be possible to write an LLD
-that uses both initialization models.
-
-
Reference Counting
==================
The Scsi_Host structure has had reference counting infrastructure added.
@@ -738,7 +663,6 @@ The interface functions are listed below in alphabetical order.
Summary:
bios_param - fetch head, sector, cylinder info for a disk
- detect - detects HBAs this driver wants to control
eh_timed_out - notify the host that a command timer expired
eh_abort_handler - abort given command
eh_bus_reset_handler - issue SCSI bus reset
@@ -748,7 +672,6 @@ Summary:
ioctl - driver can respond to ioctls
proc_info - supports /proc/scsi/{driver_name}/{host_no}
queuecommand - queue scsi command, invoke 'done' on completion
- release - release all resources associated with given host
slave_alloc - prior to any commands being sent to a new device
slave_configure - driver fine tuning for given device after attach
slave_destroy - given device is about to be shut down
@@ -785,28 +708,6 @@ Details:
/**
- * detect - detects HBAs this driver wants to control
- * @shtp: host template for this driver.
- *
- * Returns number of hosts this driver wants to control. 0 means no
- * suitable hosts found.
- *
- * Locks: none held
- *
- * Calling context: process [invoked from init_this_scsi_driver()]
- *
- * Notes: First function called from the SCSI mid level on this
- * driver. Upper level drivers (e.g. sd) may not (yet) be present.
- * For each host found, this method should call scsi_register()
- * [see hosts.c].
- *
- * Defined in: LLD (required if "passive initialization mode" is used,
- * not invoked in "hotplug initialization mode")
- **/
- int detect(struct scsi_host_template * shtp)
-
-
-/**
* eh_timed_out - The timer for the command has just fired
* @scp: identifies command timing out
*
@@ -1074,27 +975,6 @@ Details:
/**
- * release - release all resources associated with given host
- * @shp: host to be released.
- *
- * Return value ignored (could soon be a function returning void).
- *
- * Locks: none held
- *
- * Calling context: process
- *
- * Notes: Invoked from scsi_module.c's exit_this_scsi_driver().
- * LLD's implementation of this function should call
- * scsi_unregister(shp) prior to returning.
- * Only needed for old-style host templates.
- *
- * Defined in: LLD (required in "passive initialization model",
- * should not be defined in hotplug model)
- **/
- int release(struct Scsi_Host * shp)
-
-
-/**
* slave_alloc - prior to any commands being sent to a new device
* (i.e. just prior to scan) this call is made
* @sdp: pointer to new device (about to be scanned)
diff --git a/Documentation/scsi/sd-parameters.txt b/Documentation/scsi/sd-parameters.txt
new file mode 100644
index 000000000000..8e5af00d88e7
--- /dev/null
+++ b/Documentation/scsi/sd-parameters.txt
@@ -0,0 +1,22 @@
+Linux SCSI Disk Driver (sd) Parameters
+======================================
+
+cache_type (RW)
+---------------
+Enable/disable drive write & read cache.
+
+ cache_type string | WCE RCD | Write cache | Read cache
+----------------------------+---------+-------------+------------
+ write through | 0 0 | off | on
+ none | 0 1 | off | off
+ write back | 1 0 | on | on
+ write back, no read (daft) | 1 1 | on | off
+
+To set cache type to "write back" and save this setting to the drive:
+
+ # echo "write back" > cache_type
+
+To modify the caching mode without making the change persistent, prepend
+"temporary " to the cache type string. E.g.:
+
+ # echo "temporary write back" > cache_type
diff --git a/Documentation/scsi/tmscsim.txt b/Documentation/scsi/tmscsim.txt
deleted file mode 100644
index 0e0322bf0020..000000000000
--- a/Documentation/scsi/tmscsim.txt
+++ /dev/null
@@ -1,443 +0,0 @@
-The tmscsim driver
-==================
-
-1. Purpose and history
-2. Installation
-3. Features
-4. Configuration via /proc/scsi/tmscsim/?
-5. Configuration via boot/module params
-6. Potential improvements
-7. Bug reports, debugging and updates
-8. Acknowledgements
-9. Copyright
-
-
-1. Purpose and history
-----------------------
-The tmscsim driver supports PCI SCSI Host Adapters based on the AM53C974
-chip. AM53C974 based SCSI adapters include:
- Tekram DC390, DC390T
- Dawicontrol 2974
- QLogic Fast! PCI Basic
- some on-board adapters
-(This is most probably not a complete list)
-
-It has originally written by C.L. Huang from the Tekram corp. to support the
-Tekram DC390(T) adapter. This is where the name comes from: tm = Tekram
-scsi = SCSI driver, m = AMD (?) as opposed to w for the DC390W/U/F
-(NCR53c8X5, X=2/7) driver. Yes, there was also a driver for the latter,
-tmscsiw, which supported DC390W/U/F adapters. It's not maintained any more,
-as the ncr53c8xx is perfectly supporting these adapters since some time.
-
-The driver first appeared in April 1996, exclusively supported the DC390
-and has been enhanced since then in various steps. In May 1998 support for
-general AM53C974 based adapters and some possibilities to configure it were
-added. The non-DC390 support works by assuming some values for the data
-normally taken from the DC390 EEPROM. See below (chapter 5) for details.
-
-When using the DC390, the configuration is still be done using the DC390
-BIOS setup. The DC390 EEPROM is read and used by the driver, any boot or
-module parameters (chapter 5) are ignored! However, you can change settings
-dynamically, as described in chapter 4.
-
-For a more detailed description of the driver's history, see the first lines
-of tmscsim.c.
-The numbering scheme isn't consistent. The first versions went from 1.00 to
-1.12, then 1.20a to 1.20t. Finally I decided to use the ncr53c8xx scheme. So
-the next revisions will be 2.0a to 2.0X (stable), 2.1a to 2.1X (experimental),
-2.2a to 2.2X (stable, again) etc. (X = anything between a and z.) If I send
-fixes to people for testing, I create intermediate versions with a digit
-appended, e.g. 2.0c3.
-
-
-2. Installation
----------------
-If you got any recent kernel with this driver and document included in
-linux/drivers/scsi, you basically have to do nothing special to use this
-driver. Of course you have to choose to compile SCSI support and DC390(T)
-support into your kernel or as module when configuring your kernel for
-compiling.
-NEW: You may as well compile this module outside your kernel, using the
-supplied Makefile.
-
- If you got an old kernel (pre 2.1.127, pre 2.0.37p1) with an old version of
- this driver: Get dc390-21125-20b.diff.gz or dc390-2036p21-20b1.diff.gz from
- my web page and apply the patch. Apply further patches to upgrade to the
- latest version of the driver.
-
- If you want to do it manually, you should copy the files (dc390.h,
- tmscsim.h, tmscsim.c, scsiiom.c and README.tmscsim) from this directory to
- linux/drivers/scsi. You have to recompile your kernel/module of course.
-
- You should apply the three patches included in dc390-120-kernel.diff
- (Applying them: cd /usr/src; patch -p0 <~/dc390-120-kernel.diff)
- The patches are against 2.1.125, so you might have to manually resolve
- rejections when applying to another kernel version.
-
- The patches will update the kernel startup code to allow boot parameters to
- be passed to the driver, update the Documentation and finally offer you the
- possibility to omit the non-DC390 parts of the driver.
- (By selecting "Omit support for non DC390" you basically disable the
- emulation of a DC390 EEPROM for non DC390 adapters. This saves a few bytes
- of memory.)
-
-If you got a very old kernel without the tmscsim driver (pre 2.0.31)
-I recommend upgrading your kernel. However, if you don't want to, please
-contact me to get the appropriate patches.
-
-
-Upgrading a SCSI driver is always a delicate thing to do. The 2.0 driver has
-proven stable on many systems, but it's still a good idea to take some
-precautions. In an ideal world you would have a full backup of your disks.
-The world isn't ideal and most people don't have full backups (me neither).
-So take at least the following measures:
-* make your kernel remount the FS read-only on detecting an error:
- tune2fs -e remount-ro /dev/sd??
-* have copies of your SCSI disk's partition tables on some safe location:
- dd if=/dev/sda of=/mnt/floppy/sda bs=512 count=1
- or just print it with:
- fdisk -l | lpr
-* make sure you are able to boot Linux (e.g. from floppy disk using InitRD)
- if your SCSI disk gets corrupted. You can use
- ftp://student.physik.uni-dortmund.de/pub/linux/kernel/bootdisk.gz
-
-One more warning: I used to overclock my PCI bus to 41.67 MHz. My Tekram
-DC390F (Sym53c875) accepted this as well as my Millennium. But the Am53C974
-produced errors and started to corrupt my disks. So don't do that! A 37.50
-MHz PCI bus works for me, though, but I don't recommend using higher clocks
-than the 33.33 MHz being in the PCI spec.
-
-
-3.Features
-----------
-- SCSI
- * Tagged command queueing
- * Sync speed up to 10 MHz
- * Disconnection
- * Multiple LUNs
-
-- General / Linux interface
- * Support for up to 4 AM53C974 adapters.
- * DC390 EEPROM usage or boot/module params
- * Information via cat /proc/scsi/tmscsim/?
- * Dynamically configurable by writing to /proc/scsi/tmscsim/?
- * Dynamic allocation of resources
- * SMP support: Locking on io_request lock (Linux 2.1/2.2) or adapter
- specific locks (Linux 2.5?)
- * Uniform source code for Linux-2.x.y
- * Support for dyn. addition/removal of devices via add/remove-single-device
- (Try: echo "scsi add-single-device C B T U" >/proc/scsi/scsi
- C = Controller, B = Bus, T = Target SCSI ID, U = Unit SCSI LUN.)
- Use with care!
- * Try to use the partition table for the determination of the mapping
-
-
-4. Configuration via /proc/scsi/tmscsim/?
------------------------------------------
-First of all look at the output of /proc/scsi/tmscsim/? by typing
- cat /proc/scsi/tmscsim/?
-The "?" should be replaced by the SCSI host number. (The shell might do this
-for you.)
-You will see some info regarding the adapter and, at the end, a listing of
-the attached devices and their settings.
-
-Here's an example:
-garloff@kurt:/home/garloff > cat /proc/scsi/tmscsim/0
-Tekram DC390/AM53C974 PCI SCSI Host Adapter, Driver Version 2.0e7 2000-11-28
-SCSI Host Nr 1, AM53C974 Adapter Nr 0
-IOPortBase 0xb000, IRQ 10
-MaxID 8, MaxLUN 8, AdapterID 6, SelTimeout 250 ms, DelayReset 1 s
-TagMaxNum 16, Status 0x00, ACBFlag 0x00, GlitchEater 24 ns
-Statistics: Cmnds 1470165, Cmnds not sent directly 0, Out of SRB conds 0
- Lost arbitrations 587, Sel. connected 0, Connected: No
-Nr of attached devices: 4, Nr of DCBs: 4
-Map of attached LUNs: 01 00 00 03 01 00 00 00
-Idx ID LUN Prty Sync DsCn SndS TagQ NegoPeriod SyncSpeed SyncOffs MaxCmd
-00 00 00 Yes Yes Yes Yes Yes 100 ns 10.0 M 15 16
-01 03 00 Yes Yes Yes Yes No 100 ns 10.0 M 15 01
-02 03 01 Yes Yes Yes Yes No 100 ns 10.0 M 15 01
-03 04 00 Yes Yes Yes Yes No 100 ns 10.0 M 15 01
-
-Note that the settings MaxID and MaxLUN are not zero- but one-based, which
-means that a setting MaxLUN=4, will result in the support of LUNs 0..3. This
-is somehow inconvenient, but the way the mid-level SCSI code expects it to be.
-
-ACB and DCB are acronyms for Adapter Control Block and Device Control Block.
-These are data structures of the driver containing information about the
-adapter and the connected SCSI devices respectively.
-
-Idx is the device index (just a consecutive number for the driver), ID and
-LUN are the SCSI ID and LUN, Prty means Parity checking, Sync synchronous
-negotiation, DsCn Disconnection, SndS Send Start command on startup (not
-used by the driver) and TagQ Tagged Command Queueing. NegoPeriod and
-SyncSpeed are somehow redundant, because they are reciprocal values
-(1 / 112 ns = 8.9 MHz). At least in theory. The driver is able to adjust the
-NegoPeriod more accurate (4ns) than the SyncSpeed (1 / 25ns). I don't know
-if certain devices will have problems with this discrepancy. Max. speed is
-10 MHz corresp. to a min. NegoPeriod of 100 ns.
-(The driver allows slightly higher speeds if the devices (Ultra SCSI) accept
-it, but that's out of adapter spec, on your own risk and unlikely to improve
-performance. You're likely to crash your disks.)
-SyncOffs is the offset used for synchronous negotiations; max. is 15.
-The last values are only shown, if Sync is enabled. (NegoPeriod is still
-displayed in brackets to show the values which will be used after enabling
-Sync.)
-MaxCmd ist the number of commands (=tags) which can be processed at the same
-time by the device.
-
-If you want to change a setting, you can do that by writing to
-/proc/scsi/tmscsim/?. Basically you have to imitate the output of driver.
-(Don't use the brackets for NegoPeriod on Sync disabled devices.)
-You don't have to care about capitalisation. The driver will accept space,
-tab, comma, = and : as separators.
-
-There are three kinds of changes:
-
-(1) Change driver settings:
- You type the names of the parameters and the params following it.
- Example:
- echo "MaxLUN=8 seltimeout 200" >/proc/scsi/tmscsim/0
-
- Note that you can only change MaxID, MaxLUN, AdapterID, SelTimeOut,
- TagMaxNum, ACBFlag, GlitchEater and DelayReset. Don't change ACBFlag
- unless you want to see what happens, if the driver hangs.
-
-(2) Change device settings: You write a config line to the driver. The Nr
- must match the ID and LUN given. If you give "-" as parameter, it is
- ignored and the corresponding setting won't be changed.
- You can use "y" or "n" instead of "Yes" and "No" if you want to.
- You don't need to specify a full line. The driver automatically performs
- an INQUIRY on the device if necessary to check if it is capable to operate
- with the given settings (Sync, TagQ).
- Examples:
- echo "0 0 0 y y y - y - 10 " >/proc/scsi/tmscsim/0
- echo "3 5 0 y n y " >/proc/scsi/tmscsim/0
-
- To give a short explanation of the first example:
- The first three numbers, "0 0 0" (Device index 0, SCSI ID 0, SCSI LUN 0),
- select the device to which the following parameters apply. Note that it
- would be sufficient to use the index or both SCSI ID and LUN, but I chose
- to require all three to have a syntax similar to the output.
- The following "y y y - y" enables Parity checking, enables Synchronous
- transfers, Disconnection, leaves Send Start (not used) untouched and
- enables Tagged Command Queueing for the selected device. The "-" skips
- the Negotiation Period setting but the "10" sets the max sync. speed to
- 10 MHz. It's useless to specify both NegoPeriod and SyncSpeed as
- discussed above. The values used in this example will result in maximum
- performance.
-
-(3) Special commands: You can force a SCSI bus reset, an INQUIRY command, the
- removal or the addition of a device's DCB and a SCSI register dump.
- This is only used for debugging when you meet problems. The parameter of
- the INQUIRY and REMOVE commands is the device index as shown by the
- output of /proc/scsi/tmscsim/? in the device listing in the first column
- (Idx). ADD takes the SCSI ID and LUN.
- Examples:
- echo "reset" >/proc/scsi/tmscsim/0
- echo "inquiry 1" >/proc/scsi/tmscsim/0
- echo "remove 2" >/proc/scsi/tmscsim/1
- echo "add 2 3" >/proc/scsi/tmscsim/?
- echo "dump" >/proc/scsi/tmscsim/0
-
- Note that you will meet problems when you REMOVE a device's DCB with the
- remove command if it contains partitions which are mounted. Only use it
- after unmounting its partitions, telling the SCSI mid-level code to
- remove it (scsi remove-single-device) and you really need a few bytes of
- memory.
- The ADD command allows you to configure a device before you tell the
- mid-level code to try detection.
-
-
-I'd suggest reviewing the output of /proc/scsi/tmscsim/? after changing
-settings to see if everything changed as requested.
-
-
-5. Configuration via boot/module parameters
--------------------------------------------
-With the DC390, the driver reads its EEPROM settings and tries to use them.
-But you may want to override the settings prior to being able to change the
-driver configuration via /proc/scsi/tmscsim/?.
-If you do have another AM53C974 based adapter, that's even the only
-possibility to adjust settings before you are able to write to the
-/proc/scsi/tmscsim/? pseudo-file, e.g. if you want to use another
-adapter ID than 7.
-(BTW, the log message "DC390: No EEPROM found!" is normal without a DC390.)
-For this purpose, you can pass options to the driver before it is initialised
-by using kernel or module parameters. See lilo(8) or modprobe(1) manual
-pages on how to pass params to the kernel or a module.
-[NOTE: Formerly, it was not possible to override the EEPROM supplied
- settings of the DC390 with cmd line parameters. This has changed since
- 2.0e7]
-
-The syntax of the params is much shorter than the syntax of the /proc/...
-interface. This makes it a little bit more difficult to use. However, long
-parameter lines have the risk to be misinterpreted and the length of kernel
-parameters is limited.
-
-As the support for non-DC390 adapters works by simulating the values of the
-DC390 EEPROM, the settings are given in a DC390 BIOS' way.
-
-Here's the syntax:
-tmscsim=AdaptID,SpdIdx,DevMode,AdaptMode,TaggedCmnds,DelayReset
-
-Each of the parameters is a number, containing the described information:
-
-* AdaptID: The SCSI ID of the host adapter. Must be in the range 0..7
- Default is 7.
-
-* SpdIdx: The index of the maximum speed as in the DC390 BIOS. The values
- 0..7 mean 10, 8.0, 6.7, 5.7, 5.0, 4.0, 3.1 and 2 MHz resp. Default is
- 0 (10.0 MHz).
-
-* DevMode is a bit mapped value describing the per-device features. It
- applies to all devices. (Sync, Disc and TagQ will only apply, if the
- device supports it.) The meaning of the bits (* = default):
-
- Bit Val(hex) Val(dec) Meaning
- *0 0x01 1 Parity check
- *1 0x02 2 Synchronous Negotiation
- *2 0x04 4 Disconnection
- *3 0x08 8 Send Start command on startup. (Not used)
- *4 0x10 16 Tagged Command Queueing
-
- As usual, the desired value is obtained by adding the wanted values. If
- you want to enable all values, e.g., you would use 31(0x1f). Default is 31.
-
-* AdaptMode is a bit mapped value describing the enabled adapter features.
-
- Bit Val(hex) Val(dec) Meaning
- *0 0x01 1 Support more than two drives. (Not used)
- *1 0x02 2 Use DOS compatible mapping for HDs greater than 1GB.
- *2 0x04 4 Reset SCSI Bus on startup.
- *3 0x08 8 Active Negation: Improves SCSI Bus noise immunity.
- 4 0x10 16 Immediate return on BIOS seek command. (Not used)
- (*)5 0x20 32 Check for LUNs >= 1.
-
-* TaggedCmnds is a number indicating the maximum number of Tagged Commands.
- It is the binary logarithm - 1 of the actual number. Max is 4 (32).
- Value Number of Tagged Commands
- 0 2
- 1 4
- 2 8
- *3 16
- 4 32
-
-* DelayReset is the time in seconds (minus 0.5s), the adapter waits, after a
- bus reset. Default is 1 (corresp. to 1.5s).
-
-Example:
- modprobe tmscsim tmscsim=6,2,31
-would set the adapter ID to 6, max. speed to 6.7 MHz, enable all device
-features and leave the adapter features, the number of Tagged Commands
-and the Delay after a reset to the defaults.
-
-As you can see, you don't need to specify all of the six params.
-If you want values to be ignored (i.e. the EEprom settings or the defaults
-will be used), you may pass -2 (not 0!) at the corresponding position.
-
-The defaults (7,0,31,15,3,1) are aggressive to allow good performance. You
-can use tmscsim=7,0,31,63,4,0 for maximum performance, if your SCSI chain
-allows it. If you meet problems, you can use tmscsim=-1 which is a shortcut
-for tmscsim=7,4,9,15,2,10.
-
-
-6. Potential improvements
--------------------------
-Most of the intended work on the driver has been done. Here are a few ideas
-to further improve its usability:
-
-* Cleanly separate per-Target and per-LUN properties (DCB)
-* More intelligent abort() routine
-* Use new_eh code (Linux-2.1+)
-* Have the mid-level (ML) code (and not the driver) handle more of the
- various conditions.
-* Command queueing in the driver: Eliminate Query list and use ML instead.
-* More user friendly boot/module param syntax
-
-Further investigation on these problems:
-
-* Driver hangs with sync readcdda (xcdroast) (most probably VIA PCI error)
-
-Known problems:
-Please see http://www.garloff.de/kurt/linux/dc390/problems.html
-
-* Changing the parameters of multi-lun by the tmscsim/? interface will
- cause problems, cause these settings are mostly per Target and not per LUN
- and should be updated accordingly. To be fixed for 2.0d24.
-* CDRs (eg Yam CRW4416) not recognized, because some buggy devices don't
- recover from a SCSI reset in time. Use a higher delay or don't issue
- a SCSI bus reset on driver initialization. See problems page.
- For the CRW4416S, this seems to be solved with firmware 1.0g (reported by
- Jean-Yves Barbier).
-* TEAC CD-532S not being recognized. (Works with 1.11).
-* Scanners (eg. Astra UMAX 1220S) don't work: Disable Sync Negotiation.
- If this does not help, try echo "INQUIRY t" >/proc/scsi/tmscsim/? (t
- replaced by the dev index of your scanner). You may try to reset your SCSI
- bus afterwards (echo "RESET" >/proc/scsi/tmscsim/?).
- The problem seems to be solved as of 2.0d18, thanks to Andreas Rick.
-* If there is a valid partition table, the driver will use it for determining
- the mapping. If there's none, a reasonable mapping (Symbios-like) will be
- assumed. Other operating systems may not like this mapping, though
- it's consistent with the BIOS' behaviour. Old DC390 drivers ignored the
- partition table and used a H/S = 64/32 or 255/63 translation. So if you
- want to be compatible to those, use this old mapping when creating
- partition tables. Even worse, on bootup the DC390 might complain if other
- mappings are found, so auto rebooting may fail.
-* In some situations, the driver will get stuck in an abort loop. This is a
- bad interaction between the Mid-Layer of Linux' SCSI code and the driver.
- Try to disable DsCn, if you meet this problem. Please contact me for
- further debugging.
-
-
-7. Bug reports, debugging and updates
--------------------------------------
-Whenever you have problems with the driver, you are invited to ask the
-author for help. However, I'd suggest reading the docs and trying to solve
-the problem yourself, first.
-If you find something, which you believe to be a bug, please report it to me.
-Please append the output of /proc/scsi/scsi, /proc/scsi/tmscsim/? and
-maybe the DC390 log messages to the report.
-
-Bug reports should be send to me (Kurt Garloff <dc390@garloff.de>) as well
-as to the linux-scsi list (<linux-scsi@vger.kernel.org>), as sometimes bugs
-are caused by the SCSI mid-level code.
-
-I will ask you for some more details and probably I will also ask you to
-enable some of the DEBUG options in the driver (tmscsim.c:DC390_DEBUGXXX
-defines). The driver will produce some data for the syslog facility then.
-Beware: If your syslog gets written to a SCSI disk connected to your
-AM53C974, the logging might produce log output again, and you might end
-having your box spending most of its time doing the logging.
-
-The latest version of the driver can be found at:
- http://www.garloff.de/kurt/linux/dc390/
- ftp://ftp.suse.com/pub/people/garloff/linux/dc390/
-
-
-8. Acknowledgements
--------------------
-Thanks to Linus Torvalds, Alan Cox, the FSF people, the XFree86 team and
-all the others for the wonderful OS and software.
-Thanks to C.L. Huang and Philip Giang (Tekram) for the initial driver
-release and support.
-Thanks to Doug Ledford, Gérard Roudier for support with SCSI coding.
-Thanks to a lot of people (espec. Chiaki Ishikawa, Andreas Haumer, Hubert
-Tonneau) for intensively testing the driver (and even risking data loss
-doing this during early revisions).
-Recently, SuSE GmbH, Nuernberg, FRG, has been paying me for the driver
-development and maintenance. Special thanks!
-
-
-9. Copyright
-------------
- This driver is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; version 2 of the License.
- If you want to use any later version of the GNU GPL, you will probably
- be allowed to, but you have to ask me and Tekram <erich@tekram.com.tw>
- before.
-
--------------------------------------------------------------------------
-Written by Kurt Garloff <kurt@garloff.de> 1998/06/11
-Last updated 2000/11/28, driver revision 2.0e7
-$Id: README.tmscsim,v 2.25.2.7 2000/12/20 01:07:12 garloff Exp $
diff --git a/Documentation/security/LSM-sctp.rst b/Documentation/security/LSM-sctp.rst
new file mode 100644
index 000000000000..6e5a3925a860
--- /dev/null
+++ b/Documentation/security/LSM-sctp.rst
@@ -0,0 +1,175 @@
+SCTP LSM Support
+================
+
+For security module support, three SCTP specific hooks have been implemented::
+
+ security_sctp_assoc_request()
+ security_sctp_bind_connect()
+ security_sctp_sk_clone()
+
+Also the following security hook has been utilised::
+
+ security_inet_conn_established()
+
+The usage of these hooks are described below with the SELinux implementation
+described in ``Documentation/security/SELinux-sctp.rst``
+
+
+security_sctp_assoc_request()
+-----------------------------
+Passes the ``@ep`` and ``@chunk->skb`` of the association INIT packet to the
+security module. Returns 0 on success, error on failure.
+::
+
+ @ep - pointer to sctp endpoint structure.
+ @skb - pointer to skbuff of association packet.
+
+
+security_sctp_bind_connect()
+-----------------------------
+Passes one or more ipv4/ipv6 addresses to the security module for validation
+based on the ``@optname`` that will result in either a bind or connect
+service as shown in the permission check tables below.
+Returns 0 on success, error on failure.
+::
+
+ @sk - Pointer to sock structure.
+ @optname - Name of the option to validate.
+ @address - One or more ipv4 / ipv6 addresses.
+ @addrlen - The total length of address(s). This is calculated on each
+ ipv4 or ipv6 address using sizeof(struct sockaddr_in) or
+ sizeof(struct sockaddr_in6).
+
+ ------------------------------------------------------------------
+ | BIND Type Checks |
+ | @optname | @address contains |
+ |----------------------------|-----------------------------------|
+ | SCTP_SOCKOPT_BINDX_ADD | One or more ipv4 / ipv6 addresses |
+ | SCTP_PRIMARY_ADDR | Single ipv4 or ipv6 address |
+ | SCTP_SET_PEER_PRIMARY_ADDR | Single ipv4 or ipv6 address |
+ ------------------------------------------------------------------
+
+ ------------------------------------------------------------------
+ | CONNECT Type Checks |
+ | @optname | @address contains |
+ |----------------------------|-----------------------------------|
+ | SCTP_SOCKOPT_CONNECTX | One or more ipv4 / ipv6 addresses |
+ | SCTP_PARAM_ADD_IP | One or more ipv4 / ipv6 addresses |
+ | SCTP_SENDMSG_CONNECT | Single ipv4 or ipv6 address |
+ | SCTP_PARAM_SET_PRIMARY | Single ipv4 or ipv6 address |
+ ------------------------------------------------------------------
+
+A summary of the ``@optname`` entries is as follows::
+
+ SCTP_SOCKOPT_BINDX_ADD - Allows additional bind addresses to be
+ associated after (optionally) calling
+ bind(3).
+ sctp_bindx(3) adds a set of bind
+ addresses on a socket.
+
+ SCTP_SOCKOPT_CONNECTX - Allows the allocation of multiple
+ addresses for reaching a peer
+ (multi-homed).
+ sctp_connectx(3) initiates a connection
+ on an SCTP socket using multiple
+ destination addresses.
+
+ SCTP_SENDMSG_CONNECT - Initiate a connection that is generated by a
+ sendmsg(2) or sctp_sendmsg(3) on a new asociation.
+
+ SCTP_PRIMARY_ADDR - Set local primary address.
+
+ SCTP_SET_PEER_PRIMARY_ADDR - Request peer sets address as
+ association primary.
+
+ SCTP_PARAM_ADD_IP - These are used when Dynamic Address
+ SCTP_PARAM_SET_PRIMARY - Reconfiguration is enabled as explained below.
+
+
+To support Dynamic Address Reconfiguration the following parameters must be
+enabled on both endpoints (or use the appropriate **setsockopt**\(2))::
+
+ /proc/sys/net/sctp/addip_enable
+ /proc/sys/net/sctp/addip_noauth_enable
+
+then the following *_PARAM_*'s are sent to the peer in an
+ASCONF chunk when the corresponding ``@optname``'s are present::
+
+ @optname ASCONF Parameter
+ ---------- ------------------
+ SCTP_SOCKOPT_BINDX_ADD -> SCTP_PARAM_ADD_IP
+ SCTP_SET_PEER_PRIMARY_ADDR -> SCTP_PARAM_SET_PRIMARY
+
+
+security_sctp_sk_clone()
+-------------------------
+Called whenever a new socket is created by **accept**\(2)
+(i.e. a TCP style socket) or when a socket is 'peeled off' e.g userspace
+calls **sctp_peeloff**\(3).
+::
+
+ @ep - pointer to current sctp endpoint structure.
+ @sk - pointer to current sock structure.
+ @sk - pointer to new sock structure.
+
+
+security_inet_conn_established()
+---------------------------------
+Called when a COOKIE ACK is received::
+
+ @sk - pointer to sock structure.
+ @skb - pointer to skbuff of the COOKIE ACK packet.
+
+
+Security Hooks used for Association Establishment
+=================================================
+The following diagram shows the use of ``security_sctp_bind_connect()``,
+``security_sctp_assoc_request()``, ``security_inet_conn_established()`` when
+establishing an association.
+::
+
+ SCTP endpoint "A" SCTP endpoint "Z"
+ ================= =================
+ sctp_sf_do_prm_asoc()
+ Association setup can be initiated
+ by a connect(2), sctp_connectx(3),
+ sendmsg(2) or sctp_sendmsg(3).
+ These will result in a call to
+ security_sctp_bind_connect() to
+ initiate an association to
+ SCTP peer endpoint "Z".
+ INIT --------------------------------------------->
+ sctp_sf_do_5_1B_init()
+ Respond to an INIT chunk.
+ SCTP peer endpoint "A" is
+ asking for an association. Call
+ security_sctp_assoc_request()
+ to set the peer label if first
+ association.
+ If not first association, check
+ whether allowed, IF so send:
+ <----------------------------------------------- INIT ACK
+ | ELSE audit event and silently
+ | discard the packet.
+ |
+ COOKIE ECHO ------------------------------------------>
+ |
+ |
+ |
+ <------------------------------------------- COOKIE ACK
+ | |
+ sctp_sf_do_5_1E_ca |
+ Call security_inet_conn_established() |
+ to set the peer label. |
+ | |
+ | If SCTP_SOCKET_TCP or peeled off
+ | socket security_sctp_sk_clone() is
+ | called to clone the new socket.
+ | |
+ ESTABLISHED ESTABLISHED
+ | |
+ ------------------------------------------------------------------
+ | Association Established |
+ ------------------------------------------------------------------
+
+
diff --git a/Documentation/security/SELinux-sctp.rst b/Documentation/security/SELinux-sctp.rst
new file mode 100644
index 000000000000..a332cb1c5334
--- /dev/null
+++ b/Documentation/security/SELinux-sctp.rst
@@ -0,0 +1,158 @@
+SCTP SELinux Support
+=====================
+
+Security Hooks
+===============
+
+``Documentation/security/LSM-sctp.rst`` describes the following SCTP security
+hooks with the SELinux specifics expanded below::
+
+ security_sctp_assoc_request()
+ security_sctp_bind_connect()
+ security_sctp_sk_clone()
+ security_inet_conn_established()
+
+
+security_sctp_assoc_request()
+-----------------------------
+Passes the ``@ep`` and ``@chunk->skb`` of the association INIT packet to the
+security module. Returns 0 on success, error on failure.
+::
+
+ @ep - pointer to sctp endpoint structure.
+ @skb - pointer to skbuff of association packet.
+
+The security module performs the following operations:
+ IF this is the first association on ``@ep->base.sk``, then set the peer
+ sid to that in ``@skb``. This will ensure there is only one peer sid
+ assigned to ``@ep->base.sk`` that may support multiple associations.
+
+ ELSE validate the ``@ep->base.sk peer_sid`` against the ``@skb peer sid``
+ to determine whether the association should be allowed or denied.
+
+ Set the sctp ``@ep sid`` to socket's sid (from ``ep->base.sk``) with
+ MLS portion taken from ``@skb peer sid``. This will be used by SCTP
+ TCP style sockets and peeled off connections as they cause a new socket
+ to be generated.
+
+ If IP security options are configured (CIPSO/CALIPSO), then the ip
+ options are set on the socket.
+
+
+security_sctp_bind_connect()
+-----------------------------
+Checks permissions required for ipv4/ipv6 addresses based on the ``@optname``
+as follows::
+
+ ------------------------------------------------------------------
+ | BIND Permission Checks |
+ | @optname | @address contains |
+ |----------------------------|-----------------------------------|
+ | SCTP_SOCKOPT_BINDX_ADD | One or more ipv4 / ipv6 addresses |
+ | SCTP_PRIMARY_ADDR | Single ipv4 or ipv6 address |
+ | SCTP_SET_PEER_PRIMARY_ADDR | Single ipv4 or ipv6 address |
+ ------------------------------------------------------------------
+
+ ------------------------------------------------------------------
+ | CONNECT Permission Checks |
+ | @optname | @address contains |
+ |----------------------------|-----------------------------------|
+ | SCTP_SOCKOPT_CONNECTX | One or more ipv4 / ipv6 addresses |
+ | SCTP_PARAM_ADD_IP | One or more ipv4 / ipv6 addresses |
+ | SCTP_SENDMSG_CONNECT | Single ipv4 or ipv6 address |
+ | SCTP_PARAM_SET_PRIMARY | Single ipv4 or ipv6 address |
+ ------------------------------------------------------------------
+
+
+``Documentation/security/LSM-sctp.rst`` gives a summary of the ``@optname``
+entries and also describes ASCONF chunk processing when Dynamic Address
+Reconfiguration is enabled.
+
+
+security_sctp_sk_clone()
+-------------------------
+Called whenever a new socket is created by **accept**\(2) (i.e. a TCP style
+socket) or when a socket is 'peeled off' e.g userspace calls
+**sctp_peeloff**\(3). ``security_sctp_sk_clone()`` will set the new
+sockets sid and peer sid to that contained in the ``@ep sid`` and
+``@ep peer sid`` respectively.
+::
+
+ @ep - pointer to current sctp endpoint structure.
+ @sk - pointer to current sock structure.
+ @sk - pointer to new sock structure.
+
+
+security_inet_conn_established()
+---------------------------------
+Called when a COOKIE ACK is received where it sets the connection's peer sid
+to that in ``@skb``::
+
+ @sk - pointer to sock structure.
+ @skb - pointer to skbuff of the COOKIE ACK packet.
+
+
+Policy Statements
+==================
+The following class and permissions to support SCTP are available within the
+kernel::
+
+ class sctp_socket inherits socket { node_bind }
+
+whenever the following policy capability is enabled::
+
+ policycap extended_socket_class;
+
+SELinux SCTP support adds the ``name_connect`` permission for connecting
+to a specific port type and the ``association`` permission that is explained
+in the section below.
+
+If userspace tools have been updated, SCTP will support the ``portcon``
+statement as shown in the following example::
+
+ portcon sctp 1024-1036 system_u:object_r:sctp_ports_t:s0
+
+
+SCTP Peer Labeling
+===================
+An SCTP socket will only have one peer label assigned to it. This will be
+assigned during the establishment of the first association. Any further
+associations on this socket will have their packet peer label compared to
+the sockets peer label, and only if they are different will the
+``association`` permission be validated. This is validated by checking the
+socket peer sid against the received packets peer sid to determine whether
+the association should be allowed or denied.
+
+NOTES:
+ 1) If peer labeling is not enabled, then the peer context will always be
+ ``SECINITSID_UNLABELED`` (``unlabeled_t`` in Reference Policy).
+
+ 2) As SCTP can support more than one transport address per endpoint
+ (multi-homing) on a single socket, it is possible to configure policy
+ and NetLabel to provide different peer labels for each of these. As the
+ socket peer label is determined by the first associations transport
+ address, it is recommended that all peer labels are consistent.
+
+ 3) **getpeercon**\(3) may be used by userspace to retrieve the sockets peer
+ context.
+
+ 4) While not SCTP specific, be aware when using NetLabel that if a label
+ is assigned to a specific interface, and that interface 'goes down',
+ then the NetLabel service will remove the entry. Therefore ensure that
+ the network startup scripts call **netlabelctl**\(8) to set the required
+ label (see **netlabel-config**\(8) helper script for details).
+
+ 5) The NetLabel SCTP peer labeling rules apply as discussed in the following
+ set of posts tagged "netlabel" at: http://www.paul-moore.com/blog/t.
+
+ 6) CIPSO is only supported for IPv4 addressing: ``socket(AF_INET, ...)``
+ CALIPSO is only supported for IPv6 addressing: ``socket(AF_INET6, ...)``
+
+ Note the following when testing CIPSO/CALIPSO:
+ a) CIPSO will send an ICMP packet if an SCTP packet cannot be
+ delivered because of an invalid label.
+ b) CALIPSO does not send an ICMP packet, just silently discards it.
+
+ 7) IPSEC is not supported as RFC 3554 - sctp/ipsec support has not been
+ implemented in userspace (**racoon**\(8) or **ipsec_pluto**\(8)),
+ although the kernel supports SCTP/IPSEC.
diff --git a/Documentation/sound/soc/codec.rst b/Documentation/sound/soc/codec.rst
index f87612b94812..58f625fe3d39 100644
--- a/Documentation/sound/soc/codec.rst
+++ b/Documentation/sound/soc/codec.rst
@@ -179,12 +179,12 @@ i.e.
static int wm8974_mute(struct snd_soc_dai *dai, int mute)
{
- struct snd_soc_codec *codec = dai->codec;
- u16 mute_reg = snd_soc_read(codec, WM8974_DAC) & 0xffbf;
+ struct snd_soc_component *component = dai->component;
+ u16 mute_reg = snd_soc_component_read32(component, WM8974_DAC) & 0xffbf;
if (mute)
- snd_soc_write(codec, WM8974_DAC, mute_reg | 0x40);
+ snd_soc_component_write(component, WM8974_DAC, mute_reg | 0x40);
else
- snd_soc_write(codec, WM8974_DAC, mute_reg);
+ snd_soc_component_write(component, WM8974_DAC, mute_reg);
return 0;
}
diff --git a/Documentation/sparc/adi.txt b/Documentation/sparc/adi.txt
new file mode 100644
index 000000000000..e1aed155fb89
--- /dev/null
+++ b/Documentation/sparc/adi.txt
@@ -0,0 +1,278 @@
+Application Data Integrity (ADI)
+================================
+
+SPARC M7 processor adds the Application Data Integrity (ADI) feature.
+ADI allows a task to set version tags on any subset of its address
+space. Once ADI is enabled and version tags are set for ranges of
+address space of a task, the processor will compare the tag in pointers
+to memory in these ranges to the version set by the application
+previously. Access to memory is granted only if the tag in given pointer
+matches the tag set by the application. In case of mismatch, processor
+raises an exception.
+
+Following steps must be taken by a task to enable ADI fully:
+
+1. Set the user mode PSTATE.mcde bit. This acts as master switch for
+ the task's entire address space to enable/disable ADI for the task.
+
+2. Set TTE.mcd bit on any TLB entries that correspond to the range of
+ addresses ADI is being enabled on. MMU checks the version tag only
+ on the pages that have TTE.mcd bit set.
+
+3. Set the version tag for virtual addresses using stxa instruction
+ and one of the MCD specific ASIs. Each stxa instruction sets the
+ given tag for one ADI block size number of bytes. This step must
+ be repeated for entire page to set tags for entire page.
+
+ADI block size for the platform is provided by the hypervisor to kernel
+in machine description tables. Hypervisor also provides the number of
+top bits in the virtual address that specify the version tag. Once
+version tag has been set for a memory location, the tag is stored in the
+physical memory and the same tag must be present in the ADI version tag
+bits of the virtual address being presented to the MMU. For example on
+SPARC M7 processor, MMU uses bits 63-60 for version tags and ADI block
+size is same as cacheline size which is 64 bytes. A task that sets ADI
+version to, say 10, on a range of memory, must access that memory using
+virtual addresses that contain 0xa in bits 63-60.
+
+ADI is enabled on a set of pages using mprotect() with PROT_ADI flag.
+When ADI is enabled on a set of pages by a task for the first time,
+kernel sets the PSTATE.mcde bit fot the task. Version tags for memory
+addresses are set with an stxa instruction on the addresses using
+ASI_MCD_PRIMARY or ASI_MCD_ST_BLKINIT_PRIMARY. ADI block size is
+provided by the hypervisor to the kernel. Kernel returns the value of
+ADI block size to userspace using auxiliary vector along with other ADI
+info. Following auxiliary vectors are provided by the kernel:
+
+ AT_ADI_BLKSZ ADI block size. This is the granularity and
+ alignment, in bytes, of ADI versioning.
+ AT_ADI_NBITS Number of ADI version bits in the VA
+
+
+IMPORTANT NOTES:
+
+- Version tag values of 0x0 and 0xf are reserved. These values match any
+ tag in virtual address and never generate a mismatch exception.
+
+- Version tags are set on virtual addresses from userspace even though
+ tags are stored in physical memory. Tags are set on a physical page
+ after it has been allocated to a task and a pte has been created for
+ it.
+
+- When a task frees a memory page it had set version tags on, the page
+ goes back to free page pool. When this page is re-allocated to a task,
+ kernel clears the page using block initialization ASI which clears the
+ version tags as well for the page. If a page allocated to a task is
+ freed and allocated back to the same task, old version tags set by the
+ task on that page will no longer be present.
+
+- ADI tag mismatches are not detected for non-faulting loads.
+
+- Kernel does not set any tags for user pages and it is entirely a
+ task's responsibility to set any version tags. Kernel does ensure the
+ version tags are preserved if a page is swapped out to the disk and
+ swapped back in. It also preserves that version tags if a page is
+ migrated.
+
+- ADI works for any size pages. A userspace task need not be aware of
+ page size when using ADI. It can simply select a virtual address
+ range, enable ADI on the range using mprotect() and set version tags
+ for the entire range. mprotect() ensures range is aligned to page size
+ and is a multiple of page size.
+
+- ADI tags can only be set on writable memory. For example, ADI tags can
+ not be set on read-only mappings.
+
+
+
+ADI related traps
+-----------------
+
+With ADI enabled, following new traps may occur:
+
+Disrupting memory corruption
+
+ When a store accesses a memory localtion that has TTE.mcd=1,
+ the task is running with ADI enabled (PSTATE.mcde=1), and the ADI
+ tag in the address used (bits 63:60) does not match the tag set on
+ the corresponding cacheline, a memory corruption trap occurs. By
+ default, it is a disrupting trap and is sent to the hypervisor
+ first. Hypervisor creates a sun4v error report and sends a
+ resumable error (TT=0x7e) trap to the kernel. The kernel sends
+ a SIGSEGV to the task that resulted in this trap with the following
+ info:
+
+ siginfo.si_signo = SIGSEGV;
+ siginfo.errno = 0;
+ siginfo.si_code = SEGV_ADIDERR;
+ siginfo.si_addr = addr; /* PC where first mismatch occurred */
+ siginfo.si_trapno = 0;
+
+
+Precise memory corruption
+
+ When a store accesses a memory location that has TTE.mcd=1,
+ the task is running with ADI enabled (PSTATE.mcde=1), and the ADI
+ tag in the address used (bits 63:60) does not match the tag set on
+ the corresponding cacheline, a memory corruption trap occurs. If
+ MCD precise exception is enabled (MCDPERR=1), a precise
+ exception is sent to the kernel with TT=0x1a. The kernel sends
+ a SIGSEGV to the task that resulted in this trap with the following
+ info:
+
+ siginfo.si_signo = SIGSEGV;
+ siginfo.errno = 0;
+ siginfo.si_code = SEGV_ADIPERR;
+ siginfo.si_addr = addr; /* address that caused trap */
+ siginfo.si_trapno = 0;
+
+ NOTE: ADI tag mismatch on a load always results in precise trap.
+
+
+MCD disabled
+
+ When a task has not enabled ADI and attempts to set ADI version
+ on a memory address, processor sends an MCD disabled trap. This
+ trap is handled by hypervisor first and the hypervisor vectors this
+ trap through to the kernel as Data Access Exception trap with
+ fault type set to 0xa (invalid ASI). When this occurs, the kernel
+ sends the task SIGSEGV signal with following info:
+
+ siginfo.si_signo = SIGSEGV;
+ siginfo.errno = 0;
+ siginfo.si_code = SEGV_ACCADI;
+ siginfo.si_addr = addr; /* address that caused trap */
+ siginfo.si_trapno = 0;
+
+
+Sample program to use ADI
+-------------------------
+
+Following sample program is meant to illustrate how to use the ADI
+functionality.
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <elf.h>
+#include <sys/ipc.h>
+#include <sys/shm.h>
+#include <sys/mman.h>
+#include <asm/asi.h>
+
+#ifndef AT_ADI_BLKSZ
+#define AT_ADI_BLKSZ 48
+#endif
+#ifndef AT_ADI_NBITS
+#define AT_ADI_NBITS 49
+#endif
+
+#ifndef PROT_ADI
+#define PROT_ADI 0x10
+#endif
+
+#define BUFFER_SIZE 32*1024*1024UL
+
+main(int argc, char* argv[], char* envp[])
+{
+ unsigned long i, mcde, adi_blksz, adi_nbits;
+ char *shmaddr, *tmp_addr, *end, *veraddr, *clraddr;
+ int shmid, version;
+ Elf64_auxv_t *auxv;
+
+ adi_blksz = 0;
+
+ while(*envp++ != NULL);
+ for (auxv = (Elf64_auxv_t *)envp; auxv->a_type != AT_NULL; auxv++) {
+ switch (auxv->a_type) {
+ case AT_ADI_BLKSZ:
+ adi_blksz = auxv->a_un.a_val;
+ break;
+ case AT_ADI_NBITS:
+ adi_nbits = auxv->a_un.a_val;
+ break;
+ }
+ }
+ if (adi_blksz == 0) {
+ fprintf(stderr, "Oops! ADI is not supported\n");
+ exit(1);
+ }
+
+ printf("ADI capabilities:\n");
+ printf("\tBlock size = %ld\n", adi_blksz);
+ printf("\tNumber of bits = %ld\n", adi_nbits);
+
+ if ((shmid = shmget(2, BUFFER_SIZE,
+ IPC_CREAT | SHM_R | SHM_W)) < 0) {
+ perror("shmget failed");
+ exit(1);
+ }
+
+ shmaddr = shmat(shmid, NULL, 0);
+ if (shmaddr == (char *)-1) {
+ perror("shm attach failed");
+ shmctl(shmid, IPC_RMID, NULL);
+ exit(1);
+ }
+
+ if (mprotect(shmaddr, BUFFER_SIZE, PROT_READ|PROT_WRITE|PROT_ADI)) {
+ perror("mprotect failed");
+ goto err_out;
+ }
+
+ /* Set the ADI version tag on the shm segment
+ */
+ version = 10;
+ tmp_addr = shmaddr;
+ end = shmaddr + BUFFER_SIZE;
+ while (tmp_addr < end) {
+ asm volatile(
+ "stxa %1, [%0]0x90\n\t"
+ :
+ : "r" (tmp_addr), "r" (version));
+ tmp_addr += adi_blksz;
+ }
+ asm volatile("membar #Sync\n\t");
+
+ /* Create a versioned address from the normal address by placing
+ * version tag in the upper adi_nbits bits
+ */
+ tmp_addr = (void *) ((unsigned long)shmaddr << adi_nbits);
+ tmp_addr = (void *) ((unsigned long)tmp_addr >> adi_nbits);
+ veraddr = (void *) (((unsigned long)version << (64-adi_nbits))
+ | (unsigned long)tmp_addr);
+
+ printf("Starting the writes:\n");
+ for (i = 0; i < BUFFER_SIZE; i++) {
+ veraddr[i] = (char)(i);
+ if (!(i % (1024 * 1024)))
+ printf(".");
+ }
+ printf("\n");
+
+ printf("Verifying data...");
+ fflush(stdout);
+ for (i = 0; i < BUFFER_SIZE; i++)
+ if (veraddr[i] != (char)i)
+ printf("\nIndex %lu mismatched\n", i);
+ printf("Done.\n");
+
+ /* Disable ADI and clean up
+ */
+ if (mprotect(shmaddr, BUFFER_SIZE, PROT_READ|PROT_WRITE)) {
+ perror("mprotect failed");
+ goto err_out;
+ }
+
+ if (shmdt((const void *)shmaddr) != 0)
+ perror("Detach failure");
+ shmctl(shmid, IPC_RMID, NULL);
+
+ exit(0);
+
+err_out:
+ if (shmdt((const void *)shmaddr) != 0)
+ perror("Detach failure");
+ shmctl(shmid, IPC_RMID, NULL);
+ exit(1);
+}
diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt
index 412314eebda6..eded671d55eb 100644
--- a/Documentation/sysctl/kernel.txt
+++ b/Documentation/sysctl/kernel.txt
@@ -964,32 +964,34 @@ detect a hard lockup condition.
tainted:
-Non-zero if the kernel has been tainted. Numeric values, which
-can be ORed together:
-
- 1 - A module with a non-GPL license has been loaded, this
- includes modules with no license.
- Set by modutils >= 2.4.9 and module-init-tools.
- 2 - A module was force loaded by insmod -f.
- Set by modutils >= 2.4.9 and module-init-tools.
- 4 - Unsafe SMP processors: SMP with CPUs not designed for SMP.
- 8 - A module was forcibly unloaded from the system by rmmod -f.
- 16 - A hardware machine check error occurred on the system.
- 32 - A bad page was discovered on the system.
- 64 - The user has asked that the system be marked "tainted". This
- could be because they are running software that directly modifies
- the hardware, or for other reasons.
- 128 - The system has died.
- 256 - The ACPI DSDT has been overridden with one supplied by the user
- instead of using the one provided by the hardware.
- 512 - A kernel warning has occurred.
-1024 - A module from drivers/staging was loaded.
-2048 - The system is working around a severe firmware bug.
-4096 - An out-of-tree module has been loaded.
-8192 - An unsigned module has been loaded in a kernel supporting module
- signature.
-16384 - A soft lockup has previously occurred on the system.
-32768 - The kernel has been live patched.
+Non-zero if the kernel has been tainted. Numeric values, which can be
+ORed together. The letters are seen in "Tainted" line of Oops reports.
+
+ 1 (P): A module with a non-GPL license has been loaded, this
+ includes modules with no license.
+ Set by modutils >= 2.4.9 and module-init-tools.
+ 2 (F): A module was force loaded by insmod -f.
+ Set by modutils >= 2.4.9 and module-init-tools.
+ 4 (S): Unsafe SMP processors: SMP with CPUs not designed for SMP.
+ 8 (R): A module was forcibly unloaded from the system by rmmod -f.
+ 16 (M): A hardware machine check error occurred on the system.
+ 32 (B): A bad page was discovered on the system.
+ 64 (U): The user has asked that the system be marked "tainted". This
+ could be because they are running software that directly modifies
+ the hardware, or for other reasons.
+ 128 (D): The system has died.
+ 256 (A): The ACPI DSDT has been overridden with one supplied by the user
+ instead of using the one provided by the hardware.
+ 512 (W): A kernel warning has occurred.
+ 1024 (C): A module from drivers/staging was loaded.
+ 2048 (I): The system is working around a severe firmware bug.
+ 4096 (O): An out-of-tree module has been loaded.
+ 8192 (E): An unsigned module has been loaded in a kernel supporting module
+ signature.
+ 16384 (L): A soft lockup has previously occurred on the system.
+ 32768 (K): The kernel has been live patched.
+ 65536 (X): Auxiliary taint, defined and used by for distros.
+131072 (T): The kernel was built with the struct randomization plugin.
==============================================================
diff --git a/Documentation/sysctl/net.txt b/Documentation/sysctl/net.txt
index 35c62f522754..5992602469d8 100644
--- a/Documentation/sysctl/net.txt
+++ b/Documentation/sysctl/net.txt
@@ -270,6 +270,18 @@ optmem_max
Maximum ancillary buffer size allowed per socket. Ancillary data is a sequence
of struct cmsghdr structures with appended data.
+fb_tunnels_only_for_init_net
+----------------------------
+
+Controls if fallback tunnels (like tunl0, gre0, gretap0, erspan0,
+sit0, ip6tnl0, ip6gre0) are automatically created when a new
+network namespace is created, if corresponding tunnel is present
+in initial network namespace.
+If set to 1, these devices are not automatically created, and
+user space is responsible for creating them if needed.
+
+Default : 0 (for compatibility reasons)
+
2. /proc/sys/net/unix - Parameters for Unix domain sockets
-------------------------------------------------------
diff --git a/Documentation/sysctl/vm.txt b/Documentation/sysctl/vm.txt
index ff234d229cbb..17256f2ad919 100644
--- a/Documentation/sysctl/vm.txt
+++ b/Documentation/sysctl/vm.txt
@@ -312,8 +312,6 @@ The lowmem_reserve_ratio is an array. You can see them by reading this file.
% cat /proc/sys/vm/lowmem_reserve_ratio
256 256 32
-
-Note: # of this elements is one fewer than number of zones. Because the highest
- zone's value is not necessary for following calculation.
But, these values are not used directly. The kernel calculates # of protection
pages for each zones from them. These are shown as array of protection pages
@@ -364,7 +362,8 @@ As above expression, they are reciprocal number of ratio.
pages of higher zones on the node.
If you would like to protect more pages, smaller values are effective.
-The minimum value is 1 (1/1 -> 100%).
+The minimum value is 1 (1/1 -> 100%). The value less than 1 completely
+disables protection of the pages.
==============================================================
diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt
index bb9a0a53e76b..911399730c1c 100644
--- a/Documentation/thermal/sysfs-api.txt
+++ b/Documentation/thermal/sysfs-api.txt
@@ -255,6 +255,7 @@ temperature) and throttle appropriate devices.
2. sysfs attributes structure
RO read only value
+WO write only value
RW read/write value
Thermal sysfs attributes will be represented under /sys/class/thermal.
@@ -286,6 +287,11 @@ Thermal cooling device sys I/F, created once it's registered:
|---type: Type of the cooling device(processor/fan/...)
|---max_state: Maximum cooling state of the cooling device
|---cur_state: Current cooling state of the cooling device
+ |---stats: Directory containing cooling device's statistics
+ |---stats/reset: Writing any value resets the statistics
+ |---stats/time_in_state_ms: Time (msec) spent in various cooling states
+ |---stats/total_trans: Total number of times cooling state is changed
+ |---stats/trans_table: Cooing state transition table
Then next two dynamic attributes are created/removed in pairs. They represent
@@ -490,6 +496,31 @@ cur_state
- cur_state == max_state means the maximum cooling.
RW, Required
+stats/reset
+ Writing any value resets the cooling device's statistics.
+ WO, Required
+
+stats/time_in_state_ms:
+ The amount of time spent by the cooling device in various cooling
+ states. The output will have "<state> <time>" pair in each line, which
+ will mean this cooling device spent <time> msec of time at <state>.
+ Output will have one line for each of the supported states. usertime
+ units here is 10mS (similar to other time exported in /proc).
+ RO, Required
+
+stats/total_trans:
+ A single positive value showing the total number of times the state of a
+ cooling device is changed.
+ RO, Required
+
+stats/trans_table:
+ This gives fine grained information about all the cooling state
+ transitions. The cat output here is a two dimensional matrix, where an
+ entry <i,j> (row i, column j) represents the number of transitions from
+ State_i to State_j. If the transition table is bigger than PAGE_SIZE,
+ reading this will return an -EFBIG error.
+ RO, Required
+
3. A simple implementation
ACPI thermal zone may support multiple trip points like critical, hot,
diff --git a/Documentation/timers/NO_HZ.txt b/Documentation/timers/NO_HZ.txt
index 2dcaf9adb7a7..9591092da5e0 100644
--- a/Documentation/timers/NO_HZ.txt
+++ b/Documentation/timers/NO_HZ.txt
@@ -131,13 +131,6 @@ error message, and the boot CPU will be removed from the mask. Note that
this means that your system must have at least two CPUs in order for
CONFIG_NO_HZ_FULL=y to do anything for you.
-Alternatively, the CONFIG_NO_HZ_FULL_ALL=y Kconfig parameter specifies
-that all CPUs other than the boot CPU are adaptive-ticks CPUs. This
-Kconfig parameter will be overridden by the "nohz_full=" boot parameter,
-so that if both the CONFIG_NO_HZ_FULL_ALL=y Kconfig parameter and
-the "nohz_full=1" boot parameter is specified, the boot parameter will
-prevail so that only CPU 1 will be an adaptive-ticks CPU.
-
Finally, adaptive-ticks CPUs must have their RCU callbacks offloaded.
This is covered in the "RCU IMPLICATIONS" section below.
diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight.txt
index a33c88cd5d1d..6f0120c3a4f1 100644
--- a/Documentation/trace/coresight.txt
+++ b/Documentation/trace/coresight.txt
@@ -330,3 +330,54 @@ Details on how to use the generic STM API can be found here [2].
[1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
[2]. Documentation/trace/stm.txt
+
+
+Using perf tools
+----------------
+
+perf can be used to record and analyze trace of programs.
+
+Execution can be recorded using 'perf record' with the cs_etm event,
+specifying the name of the sink to record to, e.g:
+
+ perf record -e cs_etm/@20070000.etr/u --per-thread
+
+The 'perf report' and 'perf script' commands can be used to analyze execution,
+synthesizing instruction and branch events from the instruction trace.
+'perf inject' can be used to replace the trace data with the synthesized events.
+The --itrace option controls the type and frequency of synthesized events
+(see perf documentation).
+
+Note that only 64-bit programs are currently supported - further work is
+required to support instruction decode of 32-bit Arm programs.
+
+
+Generating coverage files for Feedback Directed Optimization: AutoFDO
+---------------------------------------------------------------------
+
+'perf inject' accepts the --itrace option in which case tracing data is
+removed and replaced with the synthesized events. e.g.
+
+ perf inject --itrace --strip -i perf.data -o perf.data.new
+
+Below is an example of using ARM ETM for autoFDO. It requires autofdo
+(https://github.com/google/autofdo) and gcc version 5. The bubble
+sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial).
+
+ $ gcc-5 -O3 sort.c -o sort
+ $ taskset -c 2 ./sort
+ Bubble sorting array of 30000 elements
+ 5910 ms
+
+ $ perf record -e cs_etm/@20070000.etr/u --per-thread taskset -c 2 ./sort
+ Bubble sorting array of 30000 elements
+ 12543 ms
+ [ perf record: Woken up 35 times to write data ]
+ [ perf record: Captured and wrote 69.640 MB perf.data ]
+
+ $ perf inject -i perf.data -o inj.data --itrace=il64 --strip
+ $ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1
+ $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo
+ $ taskset -c 2 ./sort_autofdo
+ Bubble sorting array of 30000 elements
+ 5806 ms
diff --git a/Documentation/trace/events-kmem.rst b/Documentation/trace/events-kmem.rst
new file mode 100644
index 000000000000..555484110e36
--- /dev/null
+++ b/Documentation/trace/events-kmem.rst
@@ -0,0 +1,119 @@
+============================
+Subsystem Trace Points: kmem
+============================
+
+The kmem tracing system captures events related to object and page allocation
+within the kernel. Broadly speaking there are five major subheadings.
+
+ - Slab allocation of small objects of unknown type (kmalloc)
+ - Slab allocation of small objects of known type
+ - Page allocation
+ - Per-CPU Allocator Activity
+ - External Fragmentation
+
+This document describes what each of the tracepoints is and why they
+might be useful.
+
+1. Slab allocation of small objects of unknown type
+===================================================
+::
+
+ kmalloc call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s
+ kmalloc_node call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s node=%d
+ kfree call_site=%lx ptr=%p
+
+Heavy activity for these events may indicate that a specific cache is
+justified, particularly if kmalloc slab pages are getting significantly
+internal fragmented as a result of the allocation pattern. By correlating
+kmalloc with kfree, it may be possible to identify memory leaks and where
+the allocation sites were.
+
+
+2. Slab allocation of small objects of known type
+=================================================
+::
+
+ kmem_cache_alloc call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s
+ kmem_cache_alloc_node call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s node=%d
+ kmem_cache_free call_site=%lx ptr=%p
+
+These events are similar in usage to the kmalloc-related events except that
+it is likely easier to pin the event down to a specific cache. At the time
+of writing, no information is available on what slab is being allocated from,
+but the call_site can usually be used to extrapolate that information.
+
+3. Page allocation
+==================
+::
+
+ mm_page_alloc page=%p pfn=%lu order=%d migratetype=%d gfp_flags=%s
+ mm_page_alloc_zone_locked page=%p pfn=%lu order=%u migratetype=%d cpu=%d percpu_refill=%d
+ mm_page_free page=%p pfn=%lu order=%d
+ mm_page_free_batched page=%p pfn=%lu order=%d cold=%d
+
+These four events deal with page allocation and freeing. mm_page_alloc is
+a simple indicator of page allocator activity. Pages may be allocated from
+the per-CPU allocator (high performance) or the buddy allocator.
+
+If pages are allocated directly from the buddy allocator, the
+mm_page_alloc_zone_locked event is triggered. This event is important as high
+amounts of activity imply high activity on the zone->lock. Taking this lock
+impairs performance by disabling interrupts, dirtying cache lines between
+CPUs and serialising many CPUs.
+
+When a page is freed directly by the caller, the only mm_page_free event
+is triggered. Significant amounts of activity here could indicate that the
+callers should be batching their activities.
+
+When pages are freed in batch, the also mm_page_free_batched is triggered.
+Broadly speaking, pages are taken off the LRU lock in bulk and
+freed in batch with a page list. Significant amounts of activity here could
+indicate that the system is under memory pressure and can also indicate
+contention on the zone->lru_lock.
+
+4. Per-CPU Allocator Activity
+=============================
+::
+
+ mm_page_alloc_zone_locked page=%p pfn=%lu order=%u migratetype=%d cpu=%d percpu_refill=%d
+ mm_page_pcpu_drain page=%p pfn=%lu order=%d cpu=%d migratetype=%d
+
+In front of the page allocator is a per-cpu page allocator. It exists only
+for order-0 pages, reduces contention on the zone->lock and reduces the
+amount of writing on struct page.
+
+When a per-CPU list is empty or pages of the wrong type are allocated,
+the zone->lock will be taken once and the per-CPU list refilled. The event
+triggered is mm_page_alloc_zone_locked for each page allocated with the
+event indicating whether it is for a percpu_refill or not.
+
+When the per-CPU list is too full, a number of pages are freed, each one
+which triggers a mm_page_pcpu_drain event.
+
+The individual nature of the events is so that pages can be tracked
+between allocation and freeing. A number of drain or refill pages that occur
+consecutively imply the zone->lock being taken once. Large amounts of per-CPU
+refills and drains could imply an imbalance between CPUs where too much work
+is being concentrated in one place. It could also indicate that the per-CPU
+lists should be a larger size. Finally, large amounts of refills on one CPU
+and drains on another could be a factor in causing large amounts of cache
+line bounces due to writes between CPUs and worth investigating if pages
+can be allocated and freed on the same CPU through some algorithm change.
+
+5. External Fragmentation
+=========================
+::
+
+ mm_page_alloc_extfrag page=%p pfn=%lu alloc_order=%d fallback_order=%d pageblock_order=%d alloc_migratetype=%d fallback_migratetype=%d fragmenting=%d change_ownership=%d
+
+External fragmentation affects whether a high-order allocation will be
+successful or not. For some types of hardware, this is important although
+it is avoided where possible. If the system is using huge pages and needs
+to be able to resize the pool over the lifetime of the system, this value
+is important.
+
+Large numbers of this event implies that memory is fragmenting and
+high-order allocations will start failing at some time in the future. One
+means of reducing the occurrence of this event is to increase the size of
+min_free_kbytes in increments of 3*pageblock_size*nr_online_nodes where
+pageblock_size is usually the size of the default hugepage size.
diff --git a/Documentation/trace/events-kmem.txt b/Documentation/trace/events-kmem.txt
deleted file mode 100644
index 194800410061..000000000000
--- a/Documentation/trace/events-kmem.txt
+++ /dev/null
@@ -1,107 +0,0 @@
- Subsystem Trace Points: kmem
-
-The kmem tracing system captures events related to object and page allocation
-within the kernel. Broadly speaking there are five major subheadings.
-
- o Slab allocation of small objects of unknown type (kmalloc)
- o Slab allocation of small objects of known type
- o Page allocation
- o Per-CPU Allocator Activity
- o External Fragmentation
-
-This document describes what each of the tracepoints is and why they
-might be useful.
-
-1. Slab allocation of small objects of unknown type
-===================================================
-kmalloc call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s
-kmalloc_node call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s node=%d
-kfree call_site=%lx ptr=%p
-
-Heavy activity for these events may indicate that a specific cache is
-justified, particularly if kmalloc slab pages are getting significantly
-internal fragmented as a result of the allocation pattern. By correlating
-kmalloc with kfree, it may be possible to identify memory leaks and where
-the allocation sites were.
-
-
-2. Slab allocation of small objects of known type
-=================================================
-kmem_cache_alloc call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s
-kmem_cache_alloc_node call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s node=%d
-kmem_cache_free call_site=%lx ptr=%p
-
-These events are similar in usage to the kmalloc-related events except that
-it is likely easier to pin the event down to a specific cache. At the time
-of writing, no information is available on what slab is being allocated from,
-but the call_site can usually be used to extrapolate that information.
-
-3. Page allocation
-==================
-mm_page_alloc page=%p pfn=%lu order=%d migratetype=%d gfp_flags=%s
-mm_page_alloc_zone_locked page=%p pfn=%lu order=%u migratetype=%d cpu=%d percpu_refill=%d
-mm_page_free page=%p pfn=%lu order=%d
-mm_page_free_batched page=%p pfn=%lu order=%d cold=%d
-
-These four events deal with page allocation and freeing. mm_page_alloc is
-a simple indicator of page allocator activity. Pages may be allocated from
-the per-CPU allocator (high performance) or the buddy allocator.
-
-If pages are allocated directly from the buddy allocator, the
-mm_page_alloc_zone_locked event is triggered. This event is important as high
-amounts of activity imply high activity on the zone->lock. Taking this lock
-impairs performance by disabling interrupts, dirtying cache lines between
-CPUs and serialising many CPUs.
-
-When a page is freed directly by the caller, the only mm_page_free event
-is triggered. Significant amounts of activity here could indicate that the
-callers should be batching their activities.
-
-When pages are freed in batch, the also mm_page_free_batched is triggered.
-Broadly speaking, pages are taken off the LRU lock in bulk and
-freed in batch with a page list. Significant amounts of activity here could
-indicate that the system is under memory pressure and can also indicate
-contention on the zone->lru_lock.
-
-4. Per-CPU Allocator Activity
-=============================
-mm_page_alloc_zone_locked page=%p pfn=%lu order=%u migratetype=%d cpu=%d percpu_refill=%d
-mm_page_pcpu_drain page=%p pfn=%lu order=%d cpu=%d migratetype=%d
-
-In front of the page allocator is a per-cpu page allocator. It exists only
-for order-0 pages, reduces contention on the zone->lock and reduces the
-amount of writing on struct page.
-
-When a per-CPU list is empty or pages of the wrong type are allocated,
-the zone->lock will be taken once and the per-CPU list refilled. The event
-triggered is mm_page_alloc_zone_locked for each page allocated with the
-event indicating whether it is for a percpu_refill or not.
-
-When the per-CPU list is too full, a number of pages are freed, each one
-which triggers a mm_page_pcpu_drain event.
-
-The individual nature of the events is so that pages can be tracked
-between allocation and freeing. A number of drain or refill pages that occur
-consecutively imply the zone->lock being taken once. Large amounts of per-CPU
-refills and drains could imply an imbalance between CPUs where too much work
-is being concentrated in one place. It could also indicate that the per-CPU
-lists should be a larger size. Finally, large amounts of refills on one CPU
-and drains on another could be a factor in causing large amounts of cache
-line bounces due to writes between CPUs and worth investigating if pages
-can be allocated and freed on the same CPU through some algorithm change.
-
-5. External Fragmentation
-=========================
-mm_page_alloc_extfrag page=%p pfn=%lu alloc_order=%d fallback_order=%d pageblock_order=%d alloc_migratetype=%d fallback_migratetype=%d fragmenting=%d change_ownership=%d
-
-External fragmentation affects whether a high-order allocation will be
-successful or not. For some types of hardware, this is important although
-it is avoided where possible. If the system is using huge pages and needs
-to be able to resize the pool over the lifetime of the system, this value
-is important.
-
-Large numbers of this event implies that memory is fragmenting and
-high-order allocations will start failing at some time in the future. One
-means of reducing the occurrence of this event is to increase the size of
-min_free_kbytes in increments of 3*pageblock_size*nr_online_nodes where
-pageblock_size is usually the size of the default hugepage size.
diff --git a/Documentation/trace/events-msr.rst b/Documentation/trace/events-msr.rst
new file mode 100644
index 000000000000..e938aa0b6f4f
--- /dev/null
+++ b/Documentation/trace/events-msr.rst
@@ -0,0 +1,40 @@
+================
+MSR Trace Events
+================
+
+The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
+To see the definition of the MSRs on Intel systems please see the SDM
+at http://www.intel.com/sdm (Volume 3)
+
+Available trace points:
+
+/sys/kernel/debug/tracing/events/msr/
+
+Trace MSR reads:
+
+read_msr
+
+ - msr: MSR number
+ - val: Value written
+ - failed: 1 if the access failed, otherwise 0
+
+
+Trace MSR writes:
+
+write_msr
+
+ - msr: MSR number
+ - val: Value written
+ - failed: 1 if the access failed, otherwise 0
+
+
+Trace RDPMC in kernel:
+
+rdpmc
+
+The trace data can be post processed with the postprocess/decode_msr.py script::
+
+ cat /sys/kernel/debug/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h
+
+to add symbolic MSR names.
+
diff --git a/Documentation/trace/events-msr.txt b/Documentation/trace/events-msr.txt
deleted file mode 100644
index 78c383bf06aa..000000000000
--- a/Documentation/trace/events-msr.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-
-The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
-To see the definition of the MSRs on Intel systems please see the SDM
-at http://www.intel.com/sdm (Volume 3)
-
-Available trace points:
-
-/sys/kernel/debug/tracing/events/msr/
-
-Trace MSR reads
-
-read_msr
-
-msr: MSR number
-val: Value written
-failed: 1 if the access failed, otherwise 0
-
-
-Trace MSR writes
-
-write_msr
-
-msr: MSR number
-val: Value written
-failed: 1 if the access failed, otherwise 0
-
-
-Trace RDPMC in kernel
-
-rdpmc
-
-The trace data can be post processed with the postprocess/decode_msr.py script
-
-cat /sys/kernel/debug/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h
-
-to add symbolic MSR names.
-
diff --git a/Documentation/trace/events-nmi.rst b/Documentation/trace/events-nmi.rst
new file mode 100644
index 000000000000..9e0a7289d80a
--- /dev/null
+++ b/Documentation/trace/events-nmi.rst
@@ -0,0 +1,45 @@
+================
+NMI Trace Events
+================
+
+These events normally show up here:
+
+ /sys/kernel/debug/tracing/events/nmi
+
+
+nmi_handler
+-----------
+
+You might want to use this tracepoint if you suspect that your
+NMI handlers are hogging large amounts of CPU time. The kernel
+will warn if it sees long-running handlers::
+
+ INFO: NMI handler took too long to run: 9.207 msecs
+
+and this tracepoint will allow you to drill down and get some
+more details.
+
+Let's say you suspect that perf_event_nmi_handler() is causing
+you some problems and you only want to trace that handler
+specifically. You need to find its address::
+
+ $ grep perf_event_nmi_handler /proc/kallsyms
+ ffffffff81625600 t perf_event_nmi_handler
+
+Let's also say you are only interested in when that function is
+really hogging a lot of CPU time, like a millisecond at a time.
+Note that the kernel's output is in milliseconds, but the input
+to the filter is in nanoseconds! You can filter on 'delta_ns'::
+
+ cd /sys/kernel/debug/tracing/events/nmi/nmi_handler
+ echo 'handler==0xffffffff81625600 && delta_ns>1000000' > filter
+ echo 1 > enable
+
+Your output would then look like::
+
+ $ cat /sys/kernel/debug/tracing/trace_pipe
+ <idle>-0 [000] d.h3 505.397558: nmi_handler: perf_event_nmi_handler() delta_ns: 3236765 handled: 1
+ <idle>-0 [000] d.h3 505.805893: nmi_handler: perf_event_nmi_handler() delta_ns: 3174234 handled: 1
+ <idle>-0 [000] d.h3 506.158206: nmi_handler: perf_event_nmi_handler() delta_ns: 3084642 handled: 1
+ <idle>-0 [000] d.h3 506.334346: nmi_handler: perf_event_nmi_handler() delta_ns: 3080351 handled: 1
+
diff --git a/Documentation/trace/events-nmi.txt b/Documentation/trace/events-nmi.txt
deleted file mode 100644
index c03c8c89f08d..000000000000
--- a/Documentation/trace/events-nmi.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-NMI Trace Events
-
-These events normally show up here:
-
- /sys/kernel/debug/tracing/events/nmi
-
---
-
-nmi_handler:
-
-You might want to use this tracepoint if you suspect that your
-NMI handlers are hogging large amounts of CPU time. The kernel
-will warn if it sees long-running handlers:
-
- INFO: NMI handler took too long to run: 9.207 msecs
-
-and this tracepoint will allow you to drill down and get some
-more details.
-
-Let's say you suspect that perf_event_nmi_handler() is causing
-you some problems and you only want to trace that handler
-specifically. You need to find its address:
-
- $ grep perf_event_nmi_handler /proc/kallsyms
- ffffffff81625600 t perf_event_nmi_handler
-
-Let's also say you are only interested in when that function is
-really hogging a lot of CPU time, like a millisecond at a time.
-Note that the kernel's output is in milliseconds, but the input
-to the filter is in nanoseconds! You can filter on 'delta_ns':
-
-cd /sys/kernel/debug/tracing/events/nmi/nmi_handler
-echo 'handler==0xffffffff81625600 && delta_ns>1000000' > filter
-echo 1 > enable
-
-Your output would then look like:
-
-$ cat /sys/kernel/debug/tracing/trace_pipe
-<idle>-0 [000] d.h3 505.397558: nmi_handler: perf_event_nmi_handler() delta_ns: 3236765 handled: 1
-<idle>-0 [000] d.h3 505.805893: nmi_handler: perf_event_nmi_handler() delta_ns: 3174234 handled: 1
-<idle>-0 [000] d.h3 506.158206: nmi_handler: perf_event_nmi_handler() delta_ns: 3084642 handled: 1
-<idle>-0 [000] d.h3 506.334346: nmi_handler: perf_event_nmi_handler() delta_ns: 3080351 handled: 1
-
diff --git a/Documentation/trace/events-power.rst b/Documentation/trace/events-power.rst
new file mode 100644
index 000000000000..a77daca75e30
--- /dev/null
+++ b/Documentation/trace/events-power.rst
@@ -0,0 +1,104 @@
+=============================
+Subsystem Trace Points: power
+=============================
+
+The power tracing system captures events related to power transitions
+within the kernel. Broadly speaking there are three major subheadings:
+
+ - Power state switch which reports events related to suspend (S-states),
+ cpuidle (C-states) and cpufreq (P-states)
+ - System clock related changes
+ - Power domains related changes and transitions
+
+This document describes what each of the tracepoints is and why they
+might be useful.
+
+Cf. include/trace/events/power.h for the events definitions.
+
+1. Power state switch events
+============================
+
+1.1 Trace API
+-----------------
+
+A 'cpu' event class gathers the CPU-related events: cpuidle and
+cpufreq.
+::
+
+ cpu_idle "state=%lu cpu_id=%lu"
+ cpu_frequency "state=%lu cpu_id=%lu"
+
+A suspend event is used to indicate the system going in and out of the
+suspend mode:
+::
+
+ machine_suspend "state=%lu"
+
+
+Note: the value of '-1' or '4294967295' for state means an exit from the current state,
+i.e. trace_cpu_idle(4, smp_processor_id()) means that the system
+enters the idle state 4, while trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id())
+means that the system exits the previous idle state.
+
+The event which has 'state=4294967295' in the trace is very important to the user
+space tools which are using it to detect the end of the current state, and so to
+correctly draw the states diagrams and to calculate accurate statistics etc.
+
+2. Clocks events
+================
+The clock events are used for clock enable/disable and for
+clock rate change.
+::
+
+ clock_enable "%s state=%lu cpu_id=%lu"
+ clock_disable "%s state=%lu cpu_id=%lu"
+ clock_set_rate "%s state=%lu cpu_id=%lu"
+
+The first parameter gives the clock name (e.g. "gpio1_iclk").
+The second parameter is '1' for enable, '0' for disable, the target
+clock rate for set_rate.
+
+3. Power domains events
+=======================
+The power domain events are used for power domains transitions
+::
+
+ power_domain_target "%s state=%lu cpu_id=%lu"
+
+The first parameter gives the power domain name (e.g. "mpu_pwrdm").
+The second parameter is the power domain target state.
+
+4. PM QoS events
+================
+The PM QoS events are used for QoS add/update/remove request and for
+target/flags update.
+::
+
+ pm_qos_add_request "pm_qos_class=%s value=%d"
+ pm_qos_update_request "pm_qos_class=%s value=%d"
+ pm_qos_remove_request "pm_qos_class=%s value=%d"
+ pm_qos_update_request_timeout "pm_qos_class=%s value=%d, timeout_us=%ld"
+
+The first parameter gives the QoS class name (e.g. "CPU_DMA_LATENCY").
+The second parameter is value to be added/updated/removed.
+The third parameter is timeout value in usec.
+::
+
+ pm_qos_update_target "action=%s prev_value=%d curr_value=%d"
+ pm_qos_update_flags "action=%s prev_value=0x%x curr_value=0x%x"
+
+The first parameter gives the QoS action name (e.g. "ADD_REQ").
+The second parameter is the previous QoS value.
+The third parameter is the current QoS value to update.
+
+And, there are also events used for device PM QoS add/update/remove request.
+::
+
+ dev_pm_qos_add_request "device=%s type=%s new_value=%d"
+ dev_pm_qos_update_request "device=%s type=%s new_value=%d"
+ dev_pm_qos_remove_request "device=%s type=%s new_value=%d"
+
+The first parameter gives the device name which tries to add/update/remove
+QoS requests.
+The second parameter gives the request type (e.g. "DEV_PM_QOS_RESUME_LATENCY").
+The third parameter is value to be added/updated/removed.
diff --git a/Documentation/trace/events-power.txt b/Documentation/trace/events-power.txt
deleted file mode 100644
index 21d514ced212..000000000000
--- a/Documentation/trace/events-power.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-
- Subsystem Trace Points: power
-
-The power tracing system captures events related to power transitions
-within the kernel. Broadly speaking there are three major subheadings:
-
- o Power state switch which reports events related to suspend (S-states),
- cpuidle (C-states) and cpufreq (P-states)
- o System clock related changes
- o Power domains related changes and transitions
-
-This document describes what each of the tracepoints is and why they
-might be useful.
-
-Cf. include/trace/events/power.h for the events definitions.
-
-1. Power state switch events
-============================
-
-1.1 Trace API
------------------
-
-A 'cpu' event class gathers the CPU-related events: cpuidle and
-cpufreq.
-
-cpu_idle "state=%lu cpu_id=%lu"
-cpu_frequency "state=%lu cpu_id=%lu"
-
-A suspend event is used to indicate the system going in and out of the
-suspend mode:
-
-machine_suspend "state=%lu"
-
-
-Note: the value of '-1' or '4294967295' for state means an exit from the current state,
-i.e. trace_cpu_idle(4, smp_processor_id()) means that the system
-enters the idle state 4, while trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id())
-means that the system exits the previous idle state.
-
-The event which has 'state=4294967295' in the trace is very important to the user
-space tools which are using it to detect the end of the current state, and so to
-correctly draw the states diagrams and to calculate accurate statistics etc.
-
-2. Clocks events
-================
-The clock events are used for clock enable/disable and for
-clock rate change.
-
-clock_enable "%s state=%lu cpu_id=%lu"
-clock_disable "%s state=%lu cpu_id=%lu"
-clock_set_rate "%s state=%lu cpu_id=%lu"
-
-The first parameter gives the clock name (e.g. "gpio1_iclk").
-The second parameter is '1' for enable, '0' for disable, the target
-clock rate for set_rate.
-
-3. Power domains events
-=======================
-The power domain events are used for power domains transitions
-
-power_domain_target "%s state=%lu cpu_id=%lu"
-
-The first parameter gives the power domain name (e.g. "mpu_pwrdm").
-The second parameter is the power domain target state.
-
-4. PM QoS events
-================
-The PM QoS events are used for QoS add/update/remove request and for
-target/flags update.
-
-pm_qos_add_request "pm_qos_class=%s value=%d"
-pm_qos_update_request "pm_qos_class=%s value=%d"
-pm_qos_remove_request "pm_qos_class=%s value=%d"
-pm_qos_update_request_timeout "pm_qos_class=%s value=%d, timeout_us=%ld"
-
-The first parameter gives the QoS class name (e.g. "CPU_DMA_LATENCY").
-The second parameter is value to be added/updated/removed.
-The third parameter is timeout value in usec.
-
-pm_qos_update_target "action=%s prev_value=%d curr_value=%d"
-pm_qos_update_flags "action=%s prev_value=0x%x curr_value=0x%x"
-
-The first parameter gives the QoS action name (e.g. "ADD_REQ").
-The second parameter is the previous QoS value.
-The third parameter is the current QoS value to update.
-
-And, there are also events used for device PM QoS add/update/remove request.
-
-dev_pm_qos_add_request "device=%s type=%s new_value=%d"
-dev_pm_qos_update_request "device=%s type=%s new_value=%d"
-dev_pm_qos_remove_request "device=%s type=%s new_value=%d"
-
-The first parameter gives the device name which tries to add/update/remove
-QoS requests.
-The second parameter gives the request type (e.g. "DEV_PM_QOS_RESUME_LATENCY").
-The third parameter is value to be added/updated/removed.
diff --git a/Documentation/trace/events.rst b/Documentation/trace/events.rst
new file mode 100644
index 000000000000..a5ea2cb0082b
--- /dev/null
+++ b/Documentation/trace/events.rst
@@ -0,0 +1,523 @@
+=============
+Event Tracing
+=============
+
+:Author: Theodore Ts'o
+:Updated: Li Zefan and Tom Zanussi
+
+1. Introduction
+===============
+
+Tracepoints (see Documentation/trace/tracepoints.txt) can be used
+without creating custom kernel modules to register probe functions
+using the event tracing infrastructure.
+
+Not all tracepoints can be traced using the event tracing system;
+the kernel developer must provide code snippets which define how the
+tracing information is saved into the tracing buffer, and how the
+tracing information should be printed.
+
+2. Using Event Tracing
+======================
+
+2.1 Via the 'set_event' interface
+---------------------------------
+
+The events which are available for tracing can be found in the file
+/sys/kernel/debug/tracing/available_events.
+
+To enable a particular event, such as 'sched_wakeup', simply echo it
+to /sys/kernel/debug/tracing/set_event. For example::
+
+ # echo sched_wakeup >> /sys/kernel/debug/tracing/set_event
+
+.. Note:: '>>' is necessary, otherwise it will firstly disable all the events.
+
+To disable an event, echo the event name to the set_event file prefixed
+with an exclamation point::
+
+ # echo '!sched_wakeup' >> /sys/kernel/debug/tracing/set_event
+
+To disable all events, echo an empty line to the set_event file::
+
+ # echo > /sys/kernel/debug/tracing/set_event
+
+To enable all events, echo ``*:*`` or ``*:`` to the set_event file::
+
+ # echo *:* > /sys/kernel/debug/tracing/set_event
+
+The events are organized into subsystems, such as ext4, irq, sched,
+etc., and a full event name looks like this: <subsystem>:<event>. The
+subsystem name is optional, but it is displayed in the available_events
+file. All of the events in a subsystem can be specified via the syntax
+``<subsystem>:*``; for example, to enable all irq events, you can use the
+command::
+
+ # echo 'irq:*' > /sys/kernel/debug/tracing/set_event
+
+2.2 Via the 'enable' toggle
+---------------------------
+
+The events available are also listed in /sys/kernel/debug/tracing/events/ hierarchy
+of directories.
+
+To enable event 'sched_wakeup'::
+
+ # echo 1 > /sys/kernel/debug/tracing/events/sched/sched_wakeup/enable
+
+To disable it::
+
+ # echo 0 > /sys/kernel/debug/tracing/events/sched/sched_wakeup/enable
+
+To enable all events in sched subsystem::
+
+ # echo 1 > /sys/kernel/debug/tracing/events/sched/enable
+
+To enable all events::
+
+ # echo 1 > /sys/kernel/debug/tracing/events/enable
+
+When reading one of these enable files, there are four results:
+
+ - 0 - all events this file affects are disabled
+ - 1 - all events this file affects are enabled
+ - X - there is a mixture of events enabled and disabled
+ - ? - this file does not affect any event
+
+2.3 Boot option
+---------------
+
+In order to facilitate early boot debugging, use boot option::
+
+ trace_event=[event-list]
+
+event-list is a comma separated list of events. See section 2.1 for event
+format.
+
+3. Defining an event-enabled tracepoint
+=======================================
+
+See The example provided in samples/trace_events
+
+4. Event formats
+================
+
+Each trace event has a 'format' file associated with it that contains
+a description of each field in a logged event. This information can
+be used to parse the binary trace stream, and is also the place to
+find the field names that can be used in event filters (see section 5).
+
+It also displays the format string that will be used to print the
+event in text mode, along with the event name and ID used for
+profiling.
+
+Every event has a set of ``common`` fields associated with it; these are
+the fields prefixed with ``common_``. The other fields vary between
+events and correspond to the fields defined in the TRACE_EVENT
+definition for that event.
+
+Each field in the format has the form::
+
+ field:field-type field-name; offset:N; size:N;
+
+where offset is the offset of the field in the trace record and size
+is the size of the data item, in bytes.
+
+For example, here's the information displayed for the 'sched_wakeup'
+event::
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/format
+
+ name: sched_wakeup
+ ID: 60
+ format:
+ field:unsigned short common_type; offset:0; size:2;
+ field:unsigned char common_flags; offset:2; size:1;
+ field:unsigned char common_preempt_count; offset:3; size:1;
+ field:int common_pid; offset:4; size:4;
+ field:int common_tgid; offset:8; size:4;
+
+ field:char comm[TASK_COMM_LEN]; offset:12; size:16;
+ field:pid_t pid; offset:28; size:4;
+ field:int prio; offset:32; size:4;
+ field:int success; offset:36; size:4;
+ field:int cpu; offset:40; size:4;
+
+ print fmt: "task %s:%d [%d] success=%d [%03d]", REC->comm, REC->pid,
+ REC->prio, REC->success, REC->cpu
+
+This event contains 10 fields, the first 5 common and the remaining 5
+event-specific. All the fields for this event are numeric, except for
+'comm' which is a string, a distinction important for event filtering.
+
+5. Event filtering
+==================
+
+Trace events can be filtered in the kernel by associating boolean
+'filter expressions' with them. As soon as an event is logged into
+the trace buffer, its fields are checked against the filter expression
+associated with that event type. An event with field values that
+'match' the filter will appear in the trace output, and an event whose
+values don't match will be discarded. An event with no filter
+associated with it matches everything, and is the default when no
+filter has been set for an event.
+
+5.1 Expression syntax
+---------------------
+
+A filter expression consists of one or more 'predicates' that can be
+combined using the logical operators '&&' and '||'. A predicate is
+simply a clause that compares the value of a field contained within a
+logged event with a constant value and returns either 0 or 1 depending
+on whether the field value matched (1) or didn't match (0)::
+
+ field-name relational-operator value
+
+Parentheses can be used to provide arbitrary logical groupings and
+double-quotes can be used to prevent the shell from interpreting
+operators as shell metacharacters.
+
+The field-names available for use in filters can be found in the
+'format' files for trace events (see section 4).
+
+The relational-operators depend on the type of the field being tested:
+
+The operators available for numeric fields are:
+
+==, !=, <, <=, >, >=, &
+
+And for string fields they are:
+
+==, !=, ~
+
+The glob (~) accepts a wild card character (\*,?) and character classes
+([). For example::
+
+ prev_comm ~ "*sh"
+ prev_comm ~ "sh*"
+ prev_comm ~ "*sh*"
+ prev_comm ~ "ba*sh"
+
+5.2 Setting filters
+-------------------
+
+A filter for an individual event is set by writing a filter expression
+to the 'filter' file for the given event.
+
+For example::
+
+ # cd /sys/kernel/debug/tracing/events/sched/sched_wakeup
+ # echo "common_preempt_count > 4" > filter
+
+A slightly more involved example::
+
+ # cd /sys/kernel/debug/tracing/events/signal/signal_generate
+ # echo "((sig >= 10 && sig < 15) || sig == 17) && comm != bash" > filter
+
+If there is an error in the expression, you'll get an 'Invalid
+argument' error when setting it, and the erroneous string along with
+an error message can be seen by looking at the filter e.g.::
+
+ # cd /sys/kernel/debug/tracing/events/signal/signal_generate
+ # echo "((sig >= 10 && sig < 15) || dsig == 17) && comm != bash" > filter
+ -bash: echo: write error: Invalid argument
+ # cat filter
+ ((sig >= 10 && sig < 15) || dsig == 17) && comm != bash
+ ^
+ parse_error: Field not found
+
+Currently the caret ('^') for an error always appears at the beginning of
+the filter string; the error message should still be useful though
+even without more accurate position info.
+
+5.3 Clearing filters
+--------------------
+
+To clear the filter for an event, write a '0' to the event's filter
+file.
+
+To clear the filters for all events in a subsystem, write a '0' to the
+subsystem's filter file.
+
+5.3 Subsystem filters
+---------------------
+
+For convenience, filters for every event in a subsystem can be set or
+cleared as a group by writing a filter expression into the filter file
+at the root of the subsystem. Note however, that if a filter for any
+event within the subsystem lacks a field specified in the subsystem
+filter, or if the filter can't be applied for any other reason, the
+filter for that event will retain its previous setting. This can
+result in an unintended mixture of filters which could lead to
+confusing (to the user who might think different filters are in
+effect) trace output. Only filters that reference just the common
+fields can be guaranteed to propagate successfully to all events.
+
+Here are a few subsystem filter examples that also illustrate the
+above points:
+
+Clear the filters on all events in the sched subsystem::
+
+ # cd /sys/kernel/debug/tracing/events/sched
+ # echo 0 > filter
+ # cat sched_switch/filter
+ none
+ # cat sched_wakeup/filter
+ none
+
+Set a filter using only common fields for all events in the sched
+subsystem (all events end up with the same filter)::
+
+ # cd /sys/kernel/debug/tracing/events/sched
+ # echo common_pid == 0 > filter
+ # cat sched_switch/filter
+ common_pid == 0
+ # cat sched_wakeup/filter
+ common_pid == 0
+
+Attempt to set a filter using a non-common field for all events in the
+sched subsystem (all events but those that have a prev_pid field retain
+their old filters)::
+
+ # cd /sys/kernel/debug/tracing/events/sched
+ # echo prev_pid == 0 > filter
+ # cat sched_switch/filter
+ prev_pid == 0
+ # cat sched_wakeup/filter
+ common_pid == 0
+
+5.4 PID filtering
+-----------------
+
+The set_event_pid file in the same directory as the top events directory
+exists, will filter all events from tracing any task that does not have the
+PID listed in the set_event_pid file.
+::
+
+ # cd /sys/kernel/debug/tracing
+ # echo $$ > set_event_pid
+ # echo 1 > events/enable
+
+Will only trace events for the current task.
+
+To add more PIDs without losing the PIDs already included, use '>>'.
+::
+
+ # echo 123 244 1 >> set_event_pid
+
+
+6. Event triggers
+=================
+
+Trace events can be made to conditionally invoke trigger 'commands'
+which can take various forms and are described in detail below;
+examples would be enabling or disabling other trace events or invoking
+a stack trace whenever the trace event is hit. Whenever a trace event
+with attached triggers is invoked, the set of trigger commands
+associated with that event is invoked. Any given trigger can
+additionally have an event filter of the same form as described in
+section 5 (Event filtering) associated with it - the command will only
+be invoked if the event being invoked passes the associated filter.
+If no filter is associated with the trigger, it always passes.
+
+Triggers are added to and removed from a particular event by writing
+trigger expressions to the 'trigger' file for the given event.
+
+A given event can have any number of triggers associated with it,
+subject to any restrictions that individual commands may have in that
+regard.
+
+Event triggers are implemented on top of "soft" mode, which means that
+whenever a trace event has one or more triggers associated with it,
+the event is activated even if it isn't actually enabled, but is
+disabled in a "soft" mode. That is, the tracepoint will be called,
+but just will not be traced, unless of course it's actually enabled.
+This scheme allows triggers to be invoked even for events that aren't
+enabled, and also allows the current event filter implementation to be
+used for conditionally invoking triggers.
+
+The syntax for event triggers is roughly based on the syntax for
+set_ftrace_filter 'ftrace filter commands' (see the 'Filter commands'
+section of Documentation/trace/ftrace.txt), but there are major
+differences and the implementation isn't currently tied to it in any
+way, so beware about making generalizations between the two.
+
+6.1 Expression syntax
+---------------------
+
+Triggers are added by echoing the command to the 'trigger' file::
+
+ # echo 'command[:count] [if filter]' > trigger
+
+Triggers are removed by echoing the same command but starting with '!'
+to the 'trigger' file::
+
+ # echo '!command[:count] [if filter]' > trigger
+
+The [if filter] part isn't used in matching commands when removing, so
+leaving that off in a '!' command will accomplish the same thing as
+having it in.
+
+The filter syntax is the same as that described in the 'Event
+filtering' section above.
+
+For ease of use, writing to the trigger file using '>' currently just
+adds or removes a single trigger and there's no explicit '>>' support
+('>' actually behaves like '>>') or truncation support to remove all
+triggers (you have to use '!' for each one added.)
+
+6.2 Supported trigger commands
+------------------------------
+
+The following commands are supported:
+
+- enable_event/disable_event
+
+ These commands can enable or disable another trace event whenever
+ the triggering event is hit. When these commands are registered,
+ the other trace event is activated, but disabled in a "soft" mode.
+ That is, the tracepoint will be called, but just will not be traced.
+ The event tracepoint stays in this mode as long as there's a trigger
+ in effect that can trigger it.
+
+ For example, the following trigger causes kmalloc events to be
+ traced when a read system call is entered, and the :1 at the end
+ specifies that this enablement happens only once::
+
+ # echo 'enable_event:kmem:kmalloc:1' > \
+ /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+
+ The following trigger causes kmalloc events to stop being traced
+ when a read system call exits. This disablement happens on every
+ read system call exit::
+
+ # echo 'disable_event:kmem:kmalloc' > \
+ /sys/kernel/debug/tracing/events/syscalls/sys_exit_read/trigger
+
+ The format is::
+
+ enable_event:<system>:<event>[:count]
+ disable_event:<system>:<event>[:count]
+
+ To remove the above commands::
+
+ # echo '!enable_event:kmem:kmalloc:1' > \
+ /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+
+ # echo '!disable_event:kmem:kmalloc' > \
+ /sys/kernel/debug/tracing/events/syscalls/sys_exit_read/trigger
+
+ Note that there can be any number of enable/disable_event triggers
+ per triggering event, but there can only be one trigger per
+ triggered event. e.g. sys_enter_read can have triggers enabling both
+ kmem:kmalloc and sched:sched_switch, but can't have two kmem:kmalloc
+ versions such as kmem:kmalloc and kmem:kmalloc:1 or 'kmem:kmalloc if
+ bytes_req == 256' and 'kmem:kmalloc if bytes_alloc == 256' (they
+ could be combined into a single filter on kmem:kmalloc though).
+
+- stacktrace
+
+ This command dumps a stacktrace in the trace buffer whenever the
+ triggering event occurs.
+
+ For example, the following trigger dumps a stacktrace every time the
+ kmalloc tracepoint is hit::
+
+ # echo 'stacktrace' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ The following trigger dumps a stacktrace the first 5 times a kmalloc
+ request happens with a size >= 64K::
+
+ # echo 'stacktrace:5 if bytes_req >= 65536' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ The format is::
+
+ stacktrace[:count]
+
+ To remove the above commands::
+
+ # echo '!stacktrace' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ # echo '!stacktrace:5 if bytes_req >= 65536' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ The latter can also be removed more simply by the following (without
+ the filter)::
+
+ # echo '!stacktrace:5' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ Note that there can be only one stacktrace trigger per triggering
+ event.
+
+- snapshot
+
+ This command causes a snapshot to be triggered whenever the
+ triggering event occurs.
+
+ The following command creates a snapshot every time a block request
+ queue is unplugged with a depth > 1. If you were tracing a set of
+ events or functions at the time, the snapshot trace buffer would
+ capture those events when the trigger event occurred::
+
+ # echo 'snapshot if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ To only snapshot once::
+
+ # echo 'snapshot:1 if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ To remove the above commands::
+
+ # echo '!snapshot if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ # echo '!snapshot:1 if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ Note that there can be only one snapshot trigger per triggering
+ event.
+
+- traceon/traceoff
+
+ These commands turn tracing on and off when the specified events are
+ hit. The parameter determines how many times the tracing system is
+ turned on and off. If unspecified, there is no limit.
+
+ The following command turns tracing off the first time a block
+ request queue is unplugged with a depth > 1. If you were tracing a
+ set of events or functions at the time, you could then examine the
+ trace buffer to see the sequence of events that led up to the
+ trigger event::
+
+ # echo 'traceoff:1 if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ To always disable tracing when nr_rq > 1::
+
+ # echo 'traceoff if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ To remove the above commands::
+
+ # echo '!traceoff:1 if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ # echo '!traceoff if nr_rq > 1' > \
+ /sys/kernel/debug/tracing/events/block/block_unplug/trigger
+
+ Note that there can be only one traceon or traceoff trigger per
+ triggering event.
+
+- hist
+
+ This command aggregates event hits into a hash table keyed on one or
+ more trace event format fields (or stacktrace) and a set of running
+ totals derived from one or more trace event format fields and/or
+ event counts (hitcount).
+
+ See Documentation/trace/histogram.txt for details and examples.
diff --git a/Documentation/trace/events.txt b/Documentation/trace/events.txt
deleted file mode 100644
index 2cc08d4a326e..000000000000
--- a/Documentation/trace/events.txt
+++ /dev/null
@@ -1,2066 +0,0 @@
- Event Tracing
-
- Documentation written by Theodore Ts'o
- Updated by Li Zefan and Tom Zanussi
-
-1. Introduction
-===============
-
-Tracepoints (see Documentation/trace/tracepoints.txt) can be used
-without creating custom kernel modules to register probe functions
-using the event tracing infrastructure.
-
-Not all tracepoints can be traced using the event tracing system;
-the kernel developer must provide code snippets which define how the
-tracing information is saved into the tracing buffer, and how the
-tracing information should be printed.
-
-2. Using Event Tracing
-======================
-
-2.1 Via the 'set_event' interface
----------------------------------
-
-The events which are available for tracing can be found in the file
-/sys/kernel/debug/tracing/available_events.
-
-To enable a particular event, such as 'sched_wakeup', simply echo it
-to /sys/kernel/debug/tracing/set_event. For example:
-
- # echo sched_wakeup >> /sys/kernel/debug/tracing/set_event
-
-[ Note: '>>' is necessary, otherwise it will firstly disable
- all the events. ]
-
-To disable an event, echo the event name to the set_event file prefixed
-with an exclamation point:
-
- # echo '!sched_wakeup' >> /sys/kernel/debug/tracing/set_event
-
-To disable all events, echo an empty line to the set_event file:
-
- # echo > /sys/kernel/debug/tracing/set_event
-
-To enable all events, echo '*:*' or '*:' to the set_event file:
-
- # echo *:* > /sys/kernel/debug/tracing/set_event
-
-The events are organized into subsystems, such as ext4, irq, sched,
-etc., and a full event name looks like this: <subsystem>:<event>. The
-subsystem name is optional, but it is displayed in the available_events
-file. All of the events in a subsystem can be specified via the syntax
-"<subsystem>:*"; for example, to enable all irq events, you can use the
-command:
-
- # echo 'irq:*' > /sys/kernel/debug/tracing/set_event
-
-2.2 Via the 'enable' toggle
----------------------------
-
-The events available are also listed in /sys/kernel/debug/tracing/events/ hierarchy
-of directories.
-
-To enable event 'sched_wakeup':
-
- # echo 1 > /sys/kernel/debug/tracing/events/sched/sched_wakeup/enable
-
-To disable it:
-
- # echo 0 > /sys/kernel/debug/tracing/events/sched/sched_wakeup/enable
-
-To enable all events in sched subsystem:
-
- # echo 1 > /sys/kernel/debug/tracing/events/sched/enable
-
-To enable all events:
-
- # echo 1 > /sys/kernel/debug/tracing/events/enable
-
-When reading one of these enable files, there are four results:
-
- 0 - all events this file affects are disabled
- 1 - all events this file affects are enabled
- X - there is a mixture of events enabled and disabled
- ? - this file does not affect any event
-
-2.3 Boot option
----------------
-
-In order to facilitate early boot debugging, use boot option:
-
- trace_event=[event-list]
-
-event-list is a comma separated list of events. See section 2.1 for event
-format.
-
-3. Defining an event-enabled tracepoint
-=======================================
-
-See The example provided in samples/trace_events
-
-4. Event formats
-================
-
-Each trace event has a 'format' file associated with it that contains
-a description of each field in a logged event. This information can
-be used to parse the binary trace stream, and is also the place to
-find the field names that can be used in event filters (see section 5).
-
-It also displays the format string that will be used to print the
-event in text mode, along with the event name and ID used for
-profiling.
-
-Every event has a set of 'common' fields associated with it; these are
-the fields prefixed with 'common_'. The other fields vary between
-events and correspond to the fields defined in the TRACE_EVENT
-definition for that event.
-
-Each field in the format has the form:
-
- field:field-type field-name; offset:N; size:N;
-
-where offset is the offset of the field in the trace record and size
-is the size of the data item, in bytes.
-
-For example, here's the information displayed for the 'sched_wakeup'
-event:
-
-# cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/format
-
-name: sched_wakeup
-ID: 60
-format:
- field:unsigned short common_type; offset:0; size:2;
- field:unsigned char common_flags; offset:2; size:1;
- field:unsigned char common_preempt_count; offset:3; size:1;
- field:int common_pid; offset:4; size:4;
- field:int common_tgid; offset:8; size:4;
-
- field:char comm[TASK_COMM_LEN]; offset:12; size:16;
- field:pid_t pid; offset:28; size:4;
- field:int prio; offset:32; size:4;
- field:int success; offset:36; size:4;
- field:int cpu; offset:40; size:4;
-
-print fmt: "task %s:%d [%d] success=%d [%03d]", REC->comm, REC->pid,
- REC->prio, REC->success, REC->cpu
-
-This event contains 10 fields, the first 5 common and the remaining 5
-event-specific. All the fields for this event are numeric, except for
-'comm' which is a string, a distinction important for event filtering.
-
-5. Event filtering
-==================
-
-Trace events can be filtered in the kernel by associating boolean
-'filter expressions' with them. As soon as an event is logged into
-the trace buffer, its fields are checked against the filter expression
-associated with that event type. An event with field values that
-'match' the filter will appear in the trace output, and an event whose
-values don't match will be discarded. An event with no filter
-associated with it matches everything, and is the default when no
-filter has been set for an event.
-
-5.1 Expression syntax
----------------------
-
-A filter expression consists of one or more 'predicates' that can be
-combined using the logical operators '&&' and '||'. A predicate is
-simply a clause that compares the value of a field contained within a
-logged event with a constant value and returns either 0 or 1 depending
-on whether the field value matched (1) or didn't match (0):
-
- field-name relational-operator value
-
-Parentheses can be used to provide arbitrary logical groupings and
-double-quotes can be used to prevent the shell from interpreting
-operators as shell metacharacters.
-
-The field-names available for use in filters can be found in the
-'format' files for trace events (see section 4).
-
-The relational-operators depend on the type of the field being tested:
-
-The operators available for numeric fields are:
-
-==, !=, <, <=, >, >=, &
-
-And for string fields they are:
-
-==, !=, ~
-
-The glob (~) accepts a wild card character (*,?) and character classes
-([). For example:
-
- prev_comm ~ "*sh"
- prev_comm ~ "sh*"
- prev_comm ~ "*sh*"
- prev_comm ~ "ba*sh"
-
-5.2 Setting filters
--------------------
-
-A filter for an individual event is set by writing a filter expression
-to the 'filter' file for the given event.
-
-For example:
-
-# cd /sys/kernel/debug/tracing/events/sched/sched_wakeup
-# echo "common_preempt_count > 4" > filter
-
-A slightly more involved example:
-
-# cd /sys/kernel/debug/tracing/events/signal/signal_generate
-# echo "((sig >= 10 && sig < 15) || sig == 17) && comm != bash" > filter
-
-If there is an error in the expression, you'll get an 'Invalid
-argument' error when setting it, and the erroneous string along with
-an error message can be seen by looking at the filter e.g.:
-
-# cd /sys/kernel/debug/tracing/events/signal/signal_generate
-# echo "((sig >= 10 && sig < 15) || dsig == 17) && comm != bash" > filter
--bash: echo: write error: Invalid argument
-# cat filter
-((sig >= 10 && sig < 15) || dsig == 17) && comm != bash
-^
-parse_error: Field not found
-
-Currently the caret ('^') for an error always appears at the beginning of
-the filter string; the error message should still be useful though
-even without more accurate position info.
-
-5.3 Clearing filters
---------------------
-
-To clear the filter for an event, write a '0' to the event's filter
-file.
-
-To clear the filters for all events in a subsystem, write a '0' to the
-subsystem's filter file.
-
-5.3 Subsystem filters
----------------------
-
-For convenience, filters for every event in a subsystem can be set or
-cleared as a group by writing a filter expression into the filter file
-at the root of the subsystem. Note however, that if a filter for any
-event within the subsystem lacks a field specified in the subsystem
-filter, or if the filter can't be applied for any other reason, the
-filter for that event will retain its previous setting. This can
-result in an unintended mixture of filters which could lead to
-confusing (to the user who might think different filters are in
-effect) trace output. Only filters that reference just the common
-fields can be guaranteed to propagate successfully to all events.
-
-Here are a few subsystem filter examples that also illustrate the
-above points:
-
-Clear the filters on all events in the sched subsystem:
-
-# cd /sys/kernel/debug/tracing/events/sched
-# echo 0 > filter
-# cat sched_switch/filter
-none
-# cat sched_wakeup/filter
-none
-
-Set a filter using only common fields for all events in the sched
-subsystem (all events end up with the same filter):
-
-# cd /sys/kernel/debug/tracing/events/sched
-# echo common_pid == 0 > filter
-# cat sched_switch/filter
-common_pid == 0
-# cat sched_wakeup/filter
-common_pid == 0
-
-Attempt to set a filter using a non-common field for all events in the
-sched subsystem (all events but those that have a prev_pid field retain
-their old filters):
-
-# cd /sys/kernel/debug/tracing/events/sched
-# echo prev_pid == 0 > filter
-# cat sched_switch/filter
-prev_pid == 0
-# cat sched_wakeup/filter
-common_pid == 0
-
-5.4 PID filtering
------------------
-
-The set_event_pid file in the same directory as the top events directory
-exists, will filter all events from tracing any task that does not have the
-PID listed in the set_event_pid file.
-
-# cd /sys/kernel/debug/tracing
-# echo $$ > set_event_pid
-# echo 1 > events/enabled
-
-Will only trace events for the current task.
-
-To add more PIDs without losing the PIDs already included, use '>>'.
-
-# echo 123 244 1 >> set_event_pid
-
-
-6. Event triggers
-=================
-
-Trace events can be made to conditionally invoke trigger 'commands'
-which can take various forms and are described in detail below;
-examples would be enabling or disabling other trace events or invoking
-a stack trace whenever the trace event is hit. Whenever a trace event
-with attached triggers is invoked, the set of trigger commands
-associated with that event is invoked. Any given trigger can
-additionally have an event filter of the same form as described in
-section 5 (Event filtering) associated with it - the command will only
-be invoked if the event being invoked passes the associated filter.
-If no filter is associated with the trigger, it always passes.
-
-Triggers are added to and removed from a particular event by writing
-trigger expressions to the 'trigger' file for the given event.
-
-A given event can have any number of triggers associated with it,
-subject to any restrictions that individual commands may have in that
-regard.
-
-Event triggers are implemented on top of "soft" mode, which means that
-whenever a trace event has one or more triggers associated with it,
-the event is activated even if it isn't actually enabled, but is
-disabled in a "soft" mode. That is, the tracepoint will be called,
-but just will not be traced, unless of course it's actually enabled.
-This scheme allows triggers to be invoked even for events that aren't
-enabled, and also allows the current event filter implementation to be
-used for conditionally invoking triggers.
-
-The syntax for event triggers is roughly based on the syntax for
-set_ftrace_filter 'ftrace filter commands' (see the 'Filter commands'
-section of Documentation/trace/ftrace.txt), but there are major
-differences and the implementation isn't currently tied to it in any
-way, so beware about making generalizations between the two.
-
-6.1 Expression syntax
----------------------
-
-Triggers are added by echoing the command to the 'trigger' file:
-
- # echo 'command[:count] [if filter]' > trigger
-
-Triggers are removed by echoing the same command but starting with '!'
-to the 'trigger' file:
-
- # echo '!command[:count] [if filter]' > trigger
-
-The [if filter] part isn't used in matching commands when removing, so
-leaving that off in a '!' command will accomplish the same thing as
-having it in.
-
-The filter syntax is the same as that described in the 'Event
-filtering' section above.
-
-For ease of use, writing to the trigger file using '>' currently just
-adds or removes a single trigger and there's no explicit '>>' support
-('>' actually behaves like '>>') or truncation support to remove all
-triggers (you have to use '!' for each one added.)
-
-6.2 Supported trigger commands
-------------------------------
-
-The following commands are supported:
-
-- enable_event/disable_event
-
- These commands can enable or disable another trace event whenever
- the triggering event is hit. When these commands are registered,
- the other trace event is activated, but disabled in a "soft" mode.
- That is, the tracepoint will be called, but just will not be traced.
- The event tracepoint stays in this mode as long as there's a trigger
- in effect that can trigger it.
-
- For example, the following trigger causes kmalloc events to be
- traced when a read system call is entered, and the :1 at the end
- specifies that this enablement happens only once:
-
- # echo 'enable_event:kmem:kmalloc:1' > \
- /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
-
- The following trigger causes kmalloc events to stop being traced
- when a read system call exits. This disablement happens on every
- read system call exit:
-
- # echo 'disable_event:kmem:kmalloc' > \
- /sys/kernel/debug/tracing/events/syscalls/sys_exit_read/trigger
-
- The format is:
-
- enable_event:<system>:<event>[:count]
- disable_event:<system>:<event>[:count]
-
- To remove the above commands:
-
- # echo '!enable_event:kmem:kmalloc:1' > \
- /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
-
- # echo '!disable_event:kmem:kmalloc' > \
- /sys/kernel/debug/tracing/events/syscalls/sys_exit_read/trigger
-
- Note that there can be any number of enable/disable_event triggers
- per triggering event, but there can only be one trigger per
- triggered event. e.g. sys_enter_read can have triggers enabling both
- kmem:kmalloc and sched:sched_switch, but can't have two kmem:kmalloc
- versions such as kmem:kmalloc and kmem:kmalloc:1 or 'kmem:kmalloc if
- bytes_req == 256' and 'kmem:kmalloc if bytes_alloc == 256' (they
- could be combined into a single filter on kmem:kmalloc though).
-
-- stacktrace
-
- This command dumps a stacktrace in the trace buffer whenever the
- triggering event occurs.
-
- For example, the following trigger dumps a stacktrace every time the
- kmalloc tracepoint is hit:
-
- # echo 'stacktrace' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- The following trigger dumps a stacktrace the first 5 times a kmalloc
- request happens with a size >= 64K
-
- # echo 'stacktrace:5 if bytes_req >= 65536' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- The format is:
-
- stacktrace[:count]
-
- To remove the above commands:
-
- # echo '!stacktrace' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- # echo '!stacktrace:5 if bytes_req >= 65536' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- The latter can also be removed more simply by the following (without
- the filter):
-
- # echo '!stacktrace:5' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- Note that there can be only one stacktrace trigger per triggering
- event.
-
-- snapshot
-
- This command causes a snapshot to be triggered whenever the
- triggering event occurs.
-
- The following command creates a snapshot every time a block request
- queue is unplugged with a depth > 1. If you were tracing a set of
- events or functions at the time, the snapshot trace buffer would
- capture those events when the trigger event occurred:
-
- # echo 'snapshot if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- To only snapshot once:
-
- # echo 'snapshot:1 if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- To remove the above commands:
-
- # echo '!snapshot if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- # echo '!snapshot:1 if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- Note that there can be only one snapshot trigger per triggering
- event.
-
-- traceon/traceoff
-
- These commands turn tracing on and off when the specified events are
- hit. The parameter determines how many times the tracing system is
- turned on and off. If unspecified, there is no limit.
-
- The following command turns tracing off the first time a block
- request queue is unplugged with a depth > 1. If you were tracing a
- set of events or functions at the time, you could then examine the
- trace buffer to see the sequence of events that led up to the
- trigger event:
-
- # echo 'traceoff:1 if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- To always disable tracing when nr_rq > 1 :
-
- # echo 'traceoff if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- To remove the above commands:
-
- # echo '!traceoff:1 if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- # echo '!traceoff if nr_rq > 1' > \
- /sys/kernel/debug/tracing/events/block/block_unplug/trigger
-
- Note that there can be only one traceon or traceoff trigger per
- triggering event.
-
-- hist
-
- This command aggregates event hits into a hash table keyed on one or
- more trace event format fields (or stacktrace) and a set of running
- totals derived from one or more trace event format fields and/or
- event counts (hitcount).
-
- The format of a hist trigger is as follows:
-
- hist:keys=<field1[,field2,...]>[:values=<field1[,field2,...]>]
- [:sort=<field1[,field2,...]>][:size=#entries][:pause][:continue]
- [:clear][:name=histname1] [if <filter>]
-
- When a matching event is hit, an entry is added to a hash table
- using the key(s) and value(s) named. Keys and values correspond to
- fields in the event's format description. Values must correspond to
- numeric fields - on an event hit, the value(s) will be added to a
- sum kept for that field. The special string 'hitcount' can be used
- in place of an explicit value field - this is simply a count of
- event hits. If 'values' isn't specified, an implicit 'hitcount'
- value will be automatically created and used as the only value.
- Keys can be any field, or the special string 'stacktrace', which
- will use the event's kernel stacktrace as the key. The keywords
- 'keys' or 'key' can be used to specify keys, and the keywords
- 'values', 'vals', or 'val' can be used to specify values. Compound
- keys consisting of up to two fields can be specified by the 'keys'
- keyword. Hashing a compound key produces a unique entry in the
- table for each unique combination of component keys, and can be
- useful for providing more fine-grained summaries of event data.
- Additionally, sort keys consisting of up to two fields can be
- specified by the 'sort' keyword. If more than one field is
- specified, the result will be a 'sort within a sort': the first key
- is taken to be the primary sort key and the second the secondary
- key. If a hist trigger is given a name using the 'name' parameter,
- its histogram data will be shared with other triggers of the same
- name, and trigger hits will update this common data. Only triggers
- with 'compatible' fields can be combined in this way; triggers are
- 'compatible' if the fields named in the trigger share the same
- number and type of fields and those fields also have the same names.
- Note that any two events always share the compatible 'hitcount' and
- 'stacktrace' fields and can therefore be combined using those
- fields, however pointless that may be.
-
- 'hist' triggers add a 'hist' file to each event's subdirectory.
- Reading the 'hist' file for the event will dump the hash table in
- its entirety to stdout. If there are multiple hist triggers
- attached to an event, there will be a table for each trigger in the
- output. The table displayed for a named trigger will be the same as
- any other instance having the same name. Each printed hash table
- entry is a simple list of the keys and values comprising the entry;
- keys are printed first and are delineated by curly braces, and are
- followed by the set of value fields for the entry. By default,
- numeric fields are displayed as base-10 integers. This can be
- modified by appending any of the following modifiers to the field
- name:
-
- .hex display a number as a hex value
- .sym display an address as a symbol
- .sym-offset display an address as a symbol and offset
- .syscall display a syscall id as a system call name
- .execname display a common_pid as a program name
-
- Note that in general the semantics of a given field aren't
- interpreted when applying a modifier to it, but there are some
- restrictions to be aware of in this regard:
-
- - only the 'hex' modifier can be used for values (because values
- are essentially sums, and the other modifiers don't make sense
- in that context).
- - the 'execname' modifier can only be used on a 'common_pid'. The
- reason for this is that the execname is simply the 'comm' value
- saved for the 'current' process when an event was triggered,
- which is the same as the common_pid value saved by the event
- tracing code. Trying to apply that comm value to other pid
- values wouldn't be correct, and typically events that care save
- pid-specific comm fields in the event itself.
-
- A typical usage scenario would be the following to enable a hist
- trigger, read its current contents, and then turn it off:
-
- # echo 'hist:keys=skbaddr.hex:vals=len' > \
- /sys/kernel/debug/tracing/events/net/netif_rx/trigger
-
- # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
-
- # echo '!hist:keys=skbaddr.hex:vals=len' > \
- /sys/kernel/debug/tracing/events/net/netif_rx/trigger
-
- The trigger file itself can be read to show the details of the
- currently attached hist trigger. This information is also displayed
- at the top of the 'hist' file when read.
-
- By default, the size of the hash table is 2048 entries. The 'size'
- parameter can be used to specify more or fewer than that. The units
- are in terms of hashtable entries - if a run uses more entries than
- specified, the results will show the number of 'drops', the number
- of hits that were ignored. The size should be a power of 2 between
- 128 and 131072 (any non- power-of-2 number specified will be rounded
- up).
-
- The 'sort' parameter can be used to specify a value field to sort
- on. The default if unspecified is 'hitcount' and the default sort
- order is 'ascending'. To sort in the opposite direction, append
- .descending' to the sort key.
-
- The 'pause' parameter can be used to pause an existing hist trigger
- or to start a hist trigger but not log any events until told to do
- so. 'continue' or 'cont' can be used to start or restart a paused
- hist trigger.
-
- The 'clear' parameter will clear the contents of a running hist
- trigger and leave its current paused/active state.
-
- Note that the 'pause', 'cont', and 'clear' parameters should be
- applied using 'append' shell operator ('>>') if applied to an
- existing trigger, rather than via the '>' operator, which will cause
- the trigger to be removed through truncation.
-
-- enable_hist/disable_hist
-
- The enable_hist and disable_hist triggers can be used to have one
- event conditionally start and stop another event's already-attached
- hist trigger. Any number of enable_hist and disable_hist triggers
- can be attached to a given event, allowing that event to kick off
- and stop aggregations on a host of other events.
-
- The format is very similar to the enable/disable_event triggers:
-
- enable_hist:<system>:<event>[:count]
- disable_hist:<system>:<event>[:count]
-
- Instead of enabling or disabling the tracing of the target event
- into the trace buffer as the enable/disable_event triggers do, the
- enable/disable_hist triggers enable or disable the aggregation of
- the target event into a hash table.
-
- A typical usage scenario for the enable_hist/disable_hist triggers
- would be to first set up a paused hist trigger on some event,
- followed by an enable_hist/disable_hist pair that turns the hist
- aggregation on and off when conditions of interest are hit:
-
- # echo 'hist:keys=skbaddr.hex:vals=len:pause' > \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
-
- # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
-
- # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
-
- The above sets up an initially paused hist trigger which is unpaused
- and starts aggregating events when a given program is executed, and
- which stops aggregating when the process exits and the hist trigger
- is paused again.
-
- The examples below provide a more concrete illustration of the
- concepts and typical usage patterns discussed above.
-
-
-6.2 'hist' trigger examples
----------------------------
-
- The first set of examples creates aggregations using the kmalloc
- event. The fields that can be used for the hist trigger are listed
- in the kmalloc event's format file:
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/format
- name: kmalloc
- ID: 374
- format:
- field:unsigned short common_type; offset:0; size:2; signed:0;
- field:unsigned char common_flags; offset:2; size:1; signed:0;
- field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
- field:int common_pid; offset:4; size:4; signed:1;
-
- field:unsigned long call_site; offset:8; size:8; signed:0;
- field:const void * ptr; offset:16; size:8; signed:0;
- field:size_t bytes_req; offset:24; size:8; signed:0;
- field:size_t bytes_alloc; offset:32; size:8; signed:0;
- field:gfp_t gfp_flags; offset:40; size:4; signed:0;
-
- We'll start by creating a hist trigger that generates a simple table
- that lists the total number of bytes requested for each function in
- the kernel that made one or more calls to kmalloc:
-
- # echo 'hist:key=call_site:val=bytes_req' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- This tells the tracing system to create a 'hist' trigger using the
- call_site field of the kmalloc event as the key for the table, which
- just means that each unique call_site address will have an entry
- created for it in the table. The 'val=bytes_req' parameter tells
- the hist trigger that for each unique entry (call_site) in the
- table, it should keep a running total of the number of bytes
- requested by that call_site.
-
- We'll let it run for awhile and then dump the contents of the 'hist'
- file in the kmalloc event's subdirectory (for readability, a number
- of entries have been omitted):
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
-
- { call_site: 18446744072106379007 } hitcount: 1 bytes_req: 176
- { call_site: 18446744071579557049 } hitcount: 1 bytes_req: 1024
- { call_site: 18446744071580608289 } hitcount: 1 bytes_req: 16384
- { call_site: 18446744071581827654 } hitcount: 1 bytes_req: 24
- { call_site: 18446744071580700980 } hitcount: 1 bytes_req: 8
- { call_site: 18446744071579359876 } hitcount: 1 bytes_req: 152
- { call_site: 18446744071580795365 } hitcount: 3 bytes_req: 144
- { call_site: 18446744071581303129 } hitcount: 3 bytes_req: 144
- { call_site: 18446744071580713234 } hitcount: 4 bytes_req: 2560
- { call_site: 18446744071580933750 } hitcount: 4 bytes_req: 736
- .
- .
- .
- { call_site: 18446744072106047046 } hitcount: 69 bytes_req: 5576
- { call_site: 18446744071582116407 } hitcount: 73 bytes_req: 2336
- { call_site: 18446744072106054684 } hitcount: 136 bytes_req: 140504
- { call_site: 18446744072106224230 } hitcount: 136 bytes_req: 19584
- { call_site: 18446744072106078074 } hitcount: 153 bytes_req: 2448
- { call_site: 18446744072106062406 } hitcount: 153 bytes_req: 36720
- { call_site: 18446744071582507929 } hitcount: 153 bytes_req: 37088
- { call_site: 18446744072102520590 } hitcount: 273 bytes_req: 10920
- { call_site: 18446744071582143559 } hitcount: 358 bytes_req: 716
- { call_site: 18446744072106465852 } hitcount: 417 bytes_req: 56712
- { call_site: 18446744072102523378 } hitcount: 485 bytes_req: 27160
- { call_site: 18446744072099568646 } hitcount: 1676 bytes_req: 33520
-
- Totals:
- Hits: 4610
- Entries: 45
- Dropped: 0
-
- The output displays a line for each entry, beginning with the key
- specified in the trigger, followed by the value(s) also specified in
- the trigger. At the beginning of the output is a line that displays
- the trigger info, which can also be displayed by reading the
- 'trigger' file:
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
- hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
-
- At the end of the output are a few lines that display the overall
- totals for the run. The 'Hits' field shows the total number of
- times the event trigger was hit, the 'Entries' field shows the total
- number of used entries in the hash table, and the 'Dropped' field
- shows the number of hits that were dropped because the number of
- used entries for the run exceeded the maximum number of entries
- allowed for the table (normally 0, but if not a hint that you may
- want to increase the size of the table using the 'size' parameter).
-
- Notice in the above output that there's an extra field, 'hitcount',
- which wasn't specified in the trigger. Also notice that in the
- trigger info output, there's a parameter, 'sort=hitcount', which
- wasn't specified in the trigger either. The reason for that is that
- every trigger implicitly keeps a count of the total number of hits
- attributed to a given entry, called the 'hitcount'. That hitcount
- information is explicitly displayed in the output, and in the
- absence of a user-specified sort parameter, is used as the default
- sort field.
-
- The value 'hitcount' can be used in place of an explicit value in
- the 'values' parameter if you don't really need to have any
- particular field summed and are mainly interested in hit
- frequencies.
-
- To turn the hist trigger off, simply call up the trigger in the
- command history and re-execute it with a '!' prepended:
-
- # echo '!hist:key=call_site:val=bytes_req' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- Finally, notice that the call_site as displayed in the output above
- isn't really very useful. It's an address, but normally addresses
- are displayed in hex. To have a numeric field displayed as a hex
- value, simply append '.hex' to the field name in the trigger:
-
- # echo 'hist:key=call_site.hex:val=bytes_req' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=call_site.hex:vals=bytes_req:sort=hitcount:size=2048 [active]
-
- { call_site: ffffffffa026b291 } hitcount: 1 bytes_req: 433
- { call_site: ffffffffa07186ff } hitcount: 1 bytes_req: 176
- { call_site: ffffffff811ae721 } hitcount: 1 bytes_req: 16384
- { call_site: ffffffff811c5134 } hitcount: 1 bytes_req: 8
- { call_site: ffffffffa04a9ebb } hitcount: 1 bytes_req: 511
- { call_site: ffffffff8122e0a6 } hitcount: 1 bytes_req: 12
- { call_site: ffffffff8107da84 } hitcount: 1 bytes_req: 152
- { call_site: ffffffff812d8246 } hitcount: 1 bytes_req: 24
- { call_site: ffffffff811dc1e5 } hitcount: 3 bytes_req: 144
- { call_site: ffffffffa02515e8 } hitcount: 3 bytes_req: 648
- { call_site: ffffffff81258159 } hitcount: 3 bytes_req: 144
- { call_site: ffffffff811c80f4 } hitcount: 4 bytes_req: 544
- .
- .
- .
- { call_site: ffffffffa06c7646 } hitcount: 106 bytes_req: 8024
- { call_site: ffffffffa06cb246 } hitcount: 132 bytes_req: 31680
- { call_site: ffffffffa06cef7a } hitcount: 132 bytes_req: 2112
- { call_site: ffffffff8137e399 } hitcount: 132 bytes_req: 23232
- { call_site: ffffffffa06c941c } hitcount: 185 bytes_req: 171360
- { call_site: ffffffffa06f2a66 } hitcount: 185 bytes_req: 26640
- { call_site: ffffffffa036a70e } hitcount: 265 bytes_req: 10600
- { call_site: ffffffff81325447 } hitcount: 292 bytes_req: 584
- { call_site: ffffffffa072da3c } hitcount: 446 bytes_req: 60656
- { call_site: ffffffffa036b1f2 } hitcount: 526 bytes_req: 29456
- { call_site: ffffffffa0099c06 } hitcount: 1780 bytes_req: 35600
-
- Totals:
- Hits: 4775
- Entries: 46
- Dropped: 0
-
- Even that's only marginally more useful - while hex values do look
- more like addresses, what users are typically more interested in
- when looking at text addresses are the corresponding symbols
- instead. To have an address displayed as symbolic value instead,
- simply append '.sym' or '.sym-offset' to the field name in the
- trigger:
-
- # echo 'hist:key=call_site.sym:val=bytes_req' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=hitcount:size=2048 [active]
-
- { call_site: [ffffffff810adcb9] syslog_print_all } hitcount: 1 bytes_req: 1024
- { call_site: [ffffffff8154bc62] usb_control_msg } hitcount: 1 bytes_req: 8
- { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid] } hitcount: 1 bytes_req: 7
- { call_site: [ffffffff8154acbe] usb_alloc_urb } hitcount: 1 bytes_req: 192
- { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid] } hitcount: 1 bytes_req: 7
- { call_site: [ffffffff811e3a25] __seq_open_private } hitcount: 1 bytes_req: 40
- { call_site: [ffffffff8109524a] alloc_fair_sched_group } hitcount: 2 bytes_req: 128
- { call_site: [ffffffff811febd5] fsnotify_alloc_group } hitcount: 2 bytes_req: 528
- { call_site: [ffffffff81440f58] __tty_buffer_request_room } hitcount: 2 bytes_req: 2624
- { call_site: [ffffffff81200ba6] inotify_new_group } hitcount: 2 bytes_req: 96
- { call_site: [ffffffffa05e19af] ieee80211_start_tx_ba_session [mac80211] } hitcount: 2 bytes_req: 464
- { call_site: [ffffffff81672406] tcp_get_metrics } hitcount: 2 bytes_req: 304
- { call_site: [ffffffff81097ec2] alloc_rt_sched_group } hitcount: 2 bytes_req: 128
- { call_site: [ffffffff81089b05] sched_create_group } hitcount: 2 bytes_req: 1424
- .
- .
- .
- { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915] } hitcount: 1185 bytes_req: 123240
- { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm] } hitcount: 1185 bytes_req: 104280
- { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915] } hitcount: 1402 bytes_req: 190672
- { call_site: [ffffffff812891ca] ext4_find_extent } hitcount: 1518 bytes_req: 146208
- { call_site: [ffffffffa029070e] drm_vma_node_allow [drm] } hitcount: 1746 bytes_req: 69840
- { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 2021 bytes_req: 792312
- { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm] } hitcount: 2592 bytes_req: 145152
- { call_site: [ffffffffa0489a66] intel_ring_begin [i915] } hitcount: 2629 bytes_req: 378576
- { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915] } hitcount: 2629 bytes_req: 3783248
- { call_site: [ffffffff81325607] apparmor_file_alloc_security } hitcount: 5192 bytes_req: 10384
- { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid] } hitcount: 5529 bytes_req: 110584
- { call_site: [ffffffff8131ebf7] aa_alloc_task_context } hitcount: 21943 bytes_req: 702176
- { call_site: [ffffffff8125847d] ext4_htree_store_dirent } hitcount: 55759 bytes_req: 5074265
-
- Totals:
- Hits: 109928
- Entries: 71
- Dropped: 0
-
- Because the default sort key above is 'hitcount', the above shows a
- the list of call_sites by increasing hitcount, so that at the bottom
- we see the functions that made the most kmalloc calls during the
- run. If instead we we wanted to see the top kmalloc callers in
- terms of the number of bytes requested rather than the number of
- calls, and we wanted the top caller to appear at the top, we can use
- the 'sort' parameter, along with the 'descending' modifier:
-
- # echo 'hist:key=call_site.sym:val=bytes_req:sort=bytes_req.descending' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
-
- { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915] } hitcount: 2186 bytes_req: 3397464
- { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 1790 bytes_req: 712176
- { call_site: [ffffffff8125847d] ext4_htree_store_dirent } hitcount: 8132 bytes_req: 513135
- { call_site: [ffffffff811e2a1b] seq_buf_alloc } hitcount: 106 bytes_req: 440128
- { call_site: [ffffffffa0489a66] intel_ring_begin [i915] } hitcount: 2186 bytes_req: 314784
- { call_site: [ffffffff812891ca] ext4_find_extent } hitcount: 2174 bytes_req: 208992
- { call_site: [ffffffff811ae8e1] __kmalloc } hitcount: 8 bytes_req: 131072
- { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915] } hitcount: 859 bytes_req: 116824
- { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm] } hitcount: 1834 bytes_req: 102704
- { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915] } hitcount: 972 bytes_req: 101088
- { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm] } hitcount: 972 bytes_req: 85536
- { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid] } hitcount: 3333 bytes_req: 66664
- { call_site: [ffffffff8137e559] sg_kmalloc } hitcount: 209 bytes_req: 61632
- .
- .
- .
- { call_site: [ffffffff81095225] alloc_fair_sched_group } hitcount: 2 bytes_req: 128
- { call_site: [ffffffff81097ec2] alloc_rt_sched_group } hitcount: 2 bytes_req: 128
- { call_site: [ffffffff812d8406] copy_semundo } hitcount: 2 bytes_req: 48
- { call_site: [ffffffff81200ba6] inotify_new_group } hitcount: 1 bytes_req: 48
- { call_site: [ffffffffa027121a] drm_getmagic [drm] } hitcount: 1 bytes_req: 48
- { call_site: [ffffffff811e3a25] __seq_open_private } hitcount: 1 bytes_req: 40
- { call_site: [ffffffff811c52f4] bprm_change_interp } hitcount: 2 bytes_req: 16
- { call_site: [ffffffff8154bc62] usb_control_msg } hitcount: 1 bytes_req: 8
- { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid] } hitcount: 1 bytes_req: 7
- { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid] } hitcount: 1 bytes_req: 7
-
- Totals:
- Hits: 32133
- Entries: 81
- Dropped: 0
-
- To display the offset and size information in addition to the symbol
- name, just use 'sym-offset' instead:
-
- # echo 'hist:key=call_site.sym-offset:val=bytes_req:sort=bytes_req.descending' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=call_site.sym-offset:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
-
- { call_site: [ffffffffa046041c] i915_gem_execbuffer2+0x6c/0x2c0 [i915] } hitcount: 4569 bytes_req: 3163720
- { call_site: [ffffffffa0489a66] intel_ring_begin+0xc6/0x1f0 [i915] } hitcount: 4569 bytes_req: 657936
- { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23+0x694/0x1020 [i915] } hitcount: 1519 bytes_req: 472936
- { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23+0x516/0x1020 [i915] } hitcount: 3050 bytes_req: 211832
- { call_site: [ffffffff811e2a1b] seq_buf_alloc+0x1b/0x50 } hitcount: 34 bytes_req: 148384
- { call_site: [ffffffffa04a580c] intel_crtc_page_flip+0xbc/0x870 [i915] } hitcount: 1385 bytes_req: 144040
- { call_site: [ffffffff811ae8e1] __kmalloc+0x191/0x1b0 } hitcount: 8 bytes_req: 131072
- { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl+0x282/0x360 [drm] } hitcount: 1385 bytes_req: 121880
- { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc+0x32/0x100 [drm] } hitcount: 1848 bytes_req: 103488
- { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state+0x2c/0xa0 [i915] } hitcount: 461 bytes_req: 62696
- { call_site: [ffffffffa029070e] drm_vma_node_allow+0x2e/0xd0 [drm] } hitcount: 1541 bytes_req: 61640
- { call_site: [ffffffff815f8d7b] sk_prot_alloc+0xcb/0x1b0 } hitcount: 57 bytes_req: 57456
- .
- .
- .
- { call_site: [ffffffff8109524a] alloc_fair_sched_group+0x5a/0x1a0 } hitcount: 2 bytes_req: 128
- { call_site: [ffffffffa027b921] drm_vm_open_locked+0x31/0xa0 [drm] } hitcount: 3 bytes_req: 96
- { call_site: [ffffffff8122e266] proc_self_follow_link+0x76/0xb0 } hitcount: 8 bytes_req: 96
- { call_site: [ffffffff81213e80] load_elf_binary+0x240/0x1650 } hitcount: 3 bytes_req: 84
- { call_site: [ffffffff8154bc62] usb_control_msg+0x42/0x110 } hitcount: 1 bytes_req: 8
- { call_site: [ffffffffa00bf6fe] hidraw_send_report+0x7e/0x1a0 [hid] } hitcount: 1 bytes_req: 7
- { call_site: [ffffffffa00bf1ca] hidraw_report_event+0x8a/0x120 [hid] } hitcount: 1 bytes_req: 7
-
- Totals:
- Hits: 26098
- Entries: 64
- Dropped: 0
-
- We can also add multiple fields to the 'values' parameter. For
- example, we might want to see the total number of bytes allocated
- alongside bytes requested, and display the result sorted by bytes
- allocated in a descending order:
-
- # echo 'hist:keys=call_site.sym:values=bytes_req,bytes_alloc:sort=bytes_alloc.descending' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=call_site.sym:vals=bytes_req,bytes_alloc:sort=bytes_alloc.descending:size=2048 [active]
-
- { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915] } hitcount: 7403 bytes_req: 4084360 bytes_alloc: 5958016
- { call_site: [ffffffff811e2a1b] seq_buf_alloc } hitcount: 541 bytes_req: 2213968 bytes_alloc: 2228224
- { call_site: [ffffffffa0489a66] intel_ring_begin [i915] } hitcount: 7404 bytes_req: 1066176 bytes_alloc: 1421568
- { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 1565 bytes_req: 557368 bytes_alloc: 1037760
- { call_site: [ffffffff8125847d] ext4_htree_store_dirent } hitcount: 9557 bytes_req: 595778 bytes_alloc: 695744
- { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 5839 bytes_req: 430680 bytes_alloc: 470400
- { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915] } hitcount: 2388 bytes_req: 324768 bytes_alloc: 458496
- { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm] } hitcount: 3911 bytes_req: 219016 bytes_alloc: 250304
- { call_site: [ffffffff815f8d7b] sk_prot_alloc } hitcount: 235 bytes_req: 236880 bytes_alloc: 240640
- { call_site: [ffffffff8137e559] sg_kmalloc } hitcount: 557 bytes_req: 169024 bytes_alloc: 221760
- { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid] } hitcount: 9378 bytes_req: 187548 bytes_alloc: 206312
- { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915] } hitcount: 1519 bytes_req: 157976 bytes_alloc: 194432
- .
- .
- .
- { call_site: [ffffffff8109bd3b] sched_autogroup_create_attach } hitcount: 2 bytes_req: 144 bytes_alloc: 192
- { call_site: [ffffffff81097ee8] alloc_rt_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
- { call_site: [ffffffff8109524a] alloc_fair_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
- { call_site: [ffffffff81095225] alloc_fair_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
- { call_site: [ffffffff81097ec2] alloc_rt_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
- { call_site: [ffffffff81213e80] load_elf_binary } hitcount: 3 bytes_req: 84 bytes_alloc: 96
- { call_site: [ffffffff81079a2e] kthread_create_on_node } hitcount: 1 bytes_req: 56 bytes_alloc: 64
- { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid] } hitcount: 1 bytes_req: 7 bytes_alloc: 8
- { call_site: [ffffffff8154bc62] usb_control_msg } hitcount: 1 bytes_req: 8 bytes_alloc: 8
- { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid] } hitcount: 1 bytes_req: 7 bytes_alloc: 8
-
- Totals:
- Hits: 66598
- Entries: 65
- Dropped: 0
-
- Finally, to finish off our kmalloc example, instead of simply having
- the hist trigger display symbolic call_sites, we can have the hist
- trigger additionally display the complete set of kernel stack traces
- that led to each call_site. To do that, we simply use the special
- value 'stacktrace' for the key parameter:
-
- # echo 'hist:keys=stacktrace:values=bytes_req,bytes_alloc:sort=bytes_alloc' > \
- /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
-
- The above trigger will use the kernel stack trace in effect when an
- event is triggered as the key for the hash table. This allows the
- enumeration of every kernel callpath that led up to a particular
- event, along with a running total of any of the event fields for
- that event. Here we tally bytes requested and bytes allocated for
- every callpath in the system that led up to a kmalloc (in this case
- every callpath to a kmalloc for a kernel compile):
-
- # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
- # trigger info: hist:keys=stacktrace:vals=bytes_req,bytes_alloc:sort=bytes_alloc:size=2048 [active]
-
- { stacktrace:
- __kmalloc_track_caller+0x10b/0x1a0
- kmemdup+0x20/0x50
- hidraw_report_event+0x8a/0x120 [hid]
- hid_report_raw_event+0x3ea/0x440 [hid]
- hid_input_report+0x112/0x190 [hid]
- hid_irq_in+0xc2/0x260 [usbhid]
- __usb_hcd_giveback_urb+0x72/0x120
- usb_giveback_urb_bh+0x9e/0xe0
- tasklet_hi_action+0xf8/0x100
- __do_softirq+0x114/0x2c0
- irq_exit+0xa5/0xb0
- do_IRQ+0x5a/0xf0
- ret_from_intr+0x0/0x30
- cpuidle_enter+0x17/0x20
- cpu_startup_entry+0x315/0x3e0
- rest_init+0x7c/0x80
- } hitcount: 3 bytes_req: 21 bytes_alloc: 24
- { stacktrace:
- __kmalloc_track_caller+0x10b/0x1a0
- kmemdup+0x20/0x50
- hidraw_report_event+0x8a/0x120 [hid]
- hid_report_raw_event+0x3ea/0x440 [hid]
- hid_input_report+0x112/0x190 [hid]
- hid_irq_in+0xc2/0x260 [usbhid]
- __usb_hcd_giveback_urb+0x72/0x120
- usb_giveback_urb_bh+0x9e/0xe0
- tasklet_hi_action+0xf8/0x100
- __do_softirq+0x114/0x2c0
- irq_exit+0xa5/0xb0
- do_IRQ+0x5a/0xf0
- ret_from_intr+0x0/0x30
- } hitcount: 3 bytes_req: 21 bytes_alloc: 24
- { stacktrace:
- kmem_cache_alloc_trace+0xeb/0x150
- aa_alloc_task_context+0x27/0x40
- apparmor_cred_prepare+0x1f/0x50
- security_prepare_creds+0x16/0x20
- prepare_creds+0xdf/0x1a0
- SyS_capset+0xb5/0x200
- system_call_fastpath+0x12/0x6a
- } hitcount: 1 bytes_req: 32 bytes_alloc: 32
- .
- .
- .
- { stacktrace:
- __kmalloc+0x11b/0x1b0
- i915_gem_execbuffer2+0x6c/0x2c0 [i915]
- drm_ioctl+0x349/0x670 [drm]
- do_vfs_ioctl+0x2f0/0x4f0
- SyS_ioctl+0x81/0xa0
- system_call_fastpath+0x12/0x6a
- } hitcount: 17726 bytes_req: 13944120 bytes_alloc: 19593808
- { stacktrace:
- __kmalloc+0x11b/0x1b0
- load_elf_phdrs+0x76/0xa0
- load_elf_binary+0x102/0x1650
- search_binary_handler+0x97/0x1d0
- do_execveat_common.isra.34+0x551/0x6e0
- SyS_execve+0x3a/0x50
- return_from_execve+0x0/0x23
- } hitcount: 33348 bytes_req: 17152128 bytes_alloc: 20226048
- { stacktrace:
- kmem_cache_alloc_trace+0xeb/0x150
- apparmor_file_alloc_security+0x27/0x40
- security_file_alloc+0x16/0x20
- get_empty_filp+0x93/0x1c0
- path_openat+0x31/0x5f0
- do_filp_open+0x3a/0x90
- do_sys_open+0x128/0x220
- SyS_open+0x1e/0x20
- system_call_fastpath+0x12/0x6a
- } hitcount: 4766422 bytes_req: 9532844 bytes_alloc: 38131376
- { stacktrace:
- __kmalloc+0x11b/0x1b0
- seq_buf_alloc+0x1b/0x50
- seq_read+0x2cc/0x370
- proc_reg_read+0x3d/0x80
- __vfs_read+0x28/0xe0
- vfs_read+0x86/0x140
- SyS_read+0x46/0xb0
- system_call_fastpath+0x12/0x6a
- } hitcount: 19133 bytes_req: 78368768 bytes_alloc: 78368768
-
- Totals:
- Hits: 6085872
- Entries: 253
- Dropped: 0
-
- If you key a hist trigger on common_pid, in order for example to
- gather and display sorted totals for each process, you can use the
- special .execname modifier to display the executable names for the
- processes in the table rather than raw pids. The example below
- keeps a per-process sum of total bytes read:
-
- # echo 'hist:key=common_pid.execname:val=count:sort=count.descending' > \
- /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
-
- # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/hist
- # trigger info: hist:keys=common_pid.execname:vals=count:sort=count.descending:size=2048 [active]
-
- { common_pid: gnome-terminal [ 3196] } hitcount: 280 count: 1093512
- { common_pid: Xorg [ 1309] } hitcount: 525 count: 256640
- { common_pid: compiz [ 2889] } hitcount: 59 count: 254400
- { common_pid: bash [ 8710] } hitcount: 3 count: 66369
- { common_pid: dbus-daemon-lau [ 8703] } hitcount: 49 count: 47739
- { common_pid: irqbalance [ 1252] } hitcount: 27 count: 27648
- { common_pid: 01ifupdown [ 8705] } hitcount: 3 count: 17216
- { common_pid: dbus-daemon [ 772] } hitcount: 10 count: 12396
- { common_pid: Socket Thread [ 8342] } hitcount: 11 count: 11264
- { common_pid: nm-dhcp-client. [ 8701] } hitcount: 6 count: 7424
- { common_pid: gmain [ 1315] } hitcount: 18 count: 6336
- .
- .
- .
- { common_pid: postgres [ 1892] } hitcount: 2 count: 32
- { common_pid: postgres [ 1891] } hitcount: 2 count: 32
- { common_pid: gmain [ 8704] } hitcount: 2 count: 32
- { common_pid: upstart-dbus-br [ 2740] } hitcount: 21 count: 21
- { common_pid: nm-dispatcher.a [ 8696] } hitcount: 1 count: 16
- { common_pid: indicator-datet [ 2904] } hitcount: 1 count: 16
- { common_pid: gdbus [ 2998] } hitcount: 1 count: 16
- { common_pid: rtkit-daemon [ 2052] } hitcount: 1 count: 8
- { common_pid: init [ 1] } hitcount: 2 count: 2
-
- Totals:
- Hits: 2116
- Entries: 51
- Dropped: 0
-
- Similarly, if you key a hist trigger on syscall id, for example to
- gather and display a list of systemwide syscall hits, you can use
- the special .syscall modifier to display the syscall names rather
- than raw ids. The example below keeps a running total of syscall
- counts for the system during the run:
-
- # echo 'hist:key=id.syscall:val=hitcount' > \
- /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
-
- # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
- # trigger info: hist:keys=id.syscall:vals=hitcount:sort=hitcount:size=2048 [active]
-
- { id: sys_fsync [ 74] } hitcount: 1
- { id: sys_newuname [ 63] } hitcount: 1
- { id: sys_prctl [157] } hitcount: 1
- { id: sys_statfs [137] } hitcount: 1
- { id: sys_symlink [ 88] } hitcount: 1
- { id: sys_sendmmsg [307] } hitcount: 1
- { id: sys_semctl [ 66] } hitcount: 1
- { id: sys_readlink [ 89] } hitcount: 3
- { id: sys_bind [ 49] } hitcount: 3
- { id: sys_getsockname [ 51] } hitcount: 3
- { id: sys_unlink [ 87] } hitcount: 3
- { id: sys_rename [ 82] } hitcount: 4
- { id: unknown_syscall [ 58] } hitcount: 4
- { id: sys_connect [ 42] } hitcount: 4
- { id: sys_getpid [ 39] } hitcount: 4
- .
- .
- .
- { id: sys_rt_sigprocmask [ 14] } hitcount: 952
- { id: sys_futex [202] } hitcount: 1534
- { id: sys_write [ 1] } hitcount: 2689
- { id: sys_setitimer [ 38] } hitcount: 2797
- { id: sys_read [ 0] } hitcount: 3202
- { id: sys_select [ 23] } hitcount: 3773
- { id: sys_writev [ 20] } hitcount: 4531
- { id: sys_poll [ 7] } hitcount: 8314
- { id: sys_recvmsg [ 47] } hitcount: 13738
- { id: sys_ioctl [ 16] } hitcount: 21843
-
- Totals:
- Hits: 67612
- Entries: 72
- Dropped: 0
-
- The syscall counts above provide a rough overall picture of system
- call activity on the system; we can see for example that the most
- popular system call on this system was the 'sys_ioctl' system call.
-
- We can use 'compound' keys to refine that number and provide some
- further insight as to which processes exactly contribute to the
- overall ioctl count.
-
- The command below keeps a hitcount for every unique combination of
- system call id and pid - the end result is essentially a table
- that keeps a per-pid sum of system call hits. The results are
- sorted using the system call id as the primary key, and the
- hitcount sum as the secondary key:
-
- # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount' > \
- /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
-
- # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
- # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 [active]
-
- { id: sys_read [ 0], common_pid: rtkit-daemon [ 1877] } hitcount: 1
- { id: sys_read [ 0], common_pid: gdbus [ 2976] } hitcount: 1
- { id: sys_read [ 0], common_pid: console-kit-dae [ 3400] } hitcount: 1
- { id: sys_read [ 0], common_pid: postgres [ 1865] } hitcount: 1
- { id: sys_read [ 0], common_pid: deja-dup-monito [ 3543] } hitcount: 2
- { id: sys_read [ 0], common_pid: NetworkManager [ 890] } hitcount: 2
- { id: sys_read [ 0], common_pid: evolution-calen [ 3048] } hitcount: 2
- { id: sys_read [ 0], common_pid: postgres [ 1864] } hitcount: 2
- { id: sys_read [ 0], common_pid: nm-applet [ 3022] } hitcount: 2
- { id: sys_read [ 0], common_pid: whoopsie [ 1212] } hitcount: 2
- .
- .
- .
- { id: sys_ioctl [ 16], common_pid: bash [ 8479] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: bash [ 3472] } hitcount: 12
- { id: sys_ioctl [ 16], common_pid: gnome-terminal [ 3199] } hitcount: 16
- { id: sys_ioctl [ 16], common_pid: Xorg [ 1267] } hitcount: 1808
- { id: sys_ioctl [ 16], common_pid: compiz [ 2994] } hitcount: 5580
- .
- .
- .
- { id: sys_waitid [247], common_pid: upstart-dbus-br [ 2690] } hitcount: 3
- { id: sys_waitid [247], common_pid: upstart-dbus-br [ 2688] } hitcount: 16
- { id: sys_inotify_add_watch [254], common_pid: gmain [ 975] } hitcount: 2
- { id: sys_inotify_add_watch [254], common_pid: gmain [ 3204] } hitcount: 4
- { id: sys_inotify_add_watch [254], common_pid: gmain [ 2888] } hitcount: 4
- { id: sys_inotify_add_watch [254], common_pid: gmain [ 3003] } hitcount: 4
- { id: sys_inotify_add_watch [254], common_pid: gmain [ 2873] } hitcount: 4
- { id: sys_inotify_add_watch [254], common_pid: gmain [ 3196] } hitcount: 6
- { id: sys_openat [257], common_pid: java [ 2623] } hitcount: 2
- { id: sys_eventfd2 [290], common_pid: ibus-ui-gtk3 [ 2760] } hitcount: 4
- { id: sys_eventfd2 [290], common_pid: compiz [ 2994] } hitcount: 6
-
- Totals:
- Hits: 31536
- Entries: 323
- Dropped: 0
-
- The above list does give us a breakdown of the ioctl syscall by
- pid, but it also gives us quite a bit more than that, which we
- don't really care about at the moment. Since we know the syscall
- id for sys_ioctl (16, displayed next to the sys_ioctl name), we
- can use that to filter out all the other syscalls:
-
- # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount if id == 16' > \
- /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
-
- # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
- # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 if id == 16 [active]
-
- { id: sys_ioctl [ 16], common_pid: gmain [ 2769] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: evolution-addre [ 8571] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: gmain [ 3003] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: gmain [ 2781] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: gmain [ 2829] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: bash [ 8726] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: bash [ 8508] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: gmain [ 2970] } hitcount: 1
- { id: sys_ioctl [ 16], common_pid: gmain [ 2768] } hitcount: 1
- .
- .
- .
- { id: sys_ioctl [ 16], common_pid: pool [ 8559] } hitcount: 45
- { id: sys_ioctl [ 16], common_pid: pool [ 8555] } hitcount: 48
- { id: sys_ioctl [ 16], common_pid: pool [ 8551] } hitcount: 48
- { id: sys_ioctl [ 16], common_pid: avahi-daemon [ 896] } hitcount: 66
- { id: sys_ioctl [ 16], common_pid: Xorg [ 1267] } hitcount: 26674
- { id: sys_ioctl [ 16], common_pid: compiz [ 2994] } hitcount: 73443
-
- Totals:
- Hits: 101162
- Entries: 103
- Dropped: 0
-
- The above output shows that 'compiz' and 'Xorg' are far and away
- the heaviest ioctl callers (which might lead to questions about
- whether they really need to be making all those calls and to
- possible avenues for further investigation.)
-
- The compound key examples used a key and a sum value (hitcount) to
- sort the output, but we can just as easily use two keys instead.
- Here's an example where we use a compound key composed of the the
- common_pid and size event fields. Sorting with pid as the primary
- key and 'size' as the secondary key allows us to display an
- ordered summary of the recvfrom sizes, with counts, received by
- each process:
-
- # echo 'hist:key=common_pid.execname,size:val=hitcount:sort=common_pid,size' > \
- /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/trigger
-
- # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/hist
- # trigger info: hist:keys=common_pid.execname,size:vals=hitcount:sort=common_pid.execname,size:size=2048 [active]
-
- { common_pid: smbd [ 784], size: 4 } hitcount: 1
- { common_pid: dnsmasq [ 1412], size: 4096 } hitcount: 672
- { common_pid: postgres [ 1796], size: 1000 } hitcount: 6
- { common_pid: postgres [ 1867], size: 1000 } hitcount: 10
- { common_pid: bamfdaemon [ 2787], size: 28 } hitcount: 2
- { common_pid: bamfdaemon [ 2787], size: 14360 } hitcount: 1
- { common_pid: compiz [ 2994], size: 8 } hitcount: 1
- { common_pid: compiz [ 2994], size: 20 } hitcount: 11
- { common_pid: gnome-terminal [ 3199], size: 4 } hitcount: 2
- { common_pid: firefox [ 8817], size: 4 } hitcount: 1
- { common_pid: firefox [ 8817], size: 8 } hitcount: 5
- { common_pid: firefox [ 8817], size: 588 } hitcount: 2
- { common_pid: firefox [ 8817], size: 628 } hitcount: 1
- { common_pid: firefox [ 8817], size: 6944 } hitcount: 1
- { common_pid: firefox [ 8817], size: 408880 } hitcount: 2
- { common_pid: firefox [ 8822], size: 8 } hitcount: 2
- { common_pid: firefox [ 8822], size: 160 } hitcount: 2
- { common_pid: firefox [ 8822], size: 320 } hitcount: 2
- { common_pid: firefox [ 8822], size: 352 } hitcount: 1
- .
- .
- .
- { common_pid: pool [ 8923], size: 1960 } hitcount: 10
- { common_pid: pool [ 8923], size: 2048 } hitcount: 10
- { common_pid: pool [ 8924], size: 1960 } hitcount: 10
- { common_pid: pool [ 8924], size: 2048 } hitcount: 10
- { common_pid: pool [ 8928], size: 1964 } hitcount: 4
- { common_pid: pool [ 8928], size: 1965 } hitcount: 2
- { common_pid: pool [ 8928], size: 2048 } hitcount: 6
- { common_pid: pool [ 8929], size: 1982 } hitcount: 1
- { common_pid: pool [ 8929], size: 2048 } hitcount: 1
-
- Totals:
- Hits: 2016
- Entries: 224
- Dropped: 0
-
- The above example also illustrates the fact that although a compound
- key is treated as a single entity for hashing purposes, the sub-keys
- it's composed of can be accessed independently.
-
- The next example uses a string field as the hash key and
- demonstrates how you can manually pause and continue a hist trigger.
- In this example, we'll aggregate fork counts and don't expect a
- large number of entries in the hash table, so we'll drop it to a
- much smaller number, say 256:
-
- # echo 'hist:key=child_comm:val=hitcount:size=256' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
-
- # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
- # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
-
- { child_comm: dconf worker } hitcount: 1
- { child_comm: ibus-daemon } hitcount: 1
- { child_comm: whoopsie } hitcount: 1
- { child_comm: smbd } hitcount: 1
- { child_comm: gdbus } hitcount: 1
- { child_comm: kthreadd } hitcount: 1
- { child_comm: dconf worker } hitcount: 1
- { child_comm: evolution-alarm } hitcount: 2
- { child_comm: Socket Thread } hitcount: 2
- { child_comm: postgres } hitcount: 2
- { child_comm: bash } hitcount: 3
- { child_comm: compiz } hitcount: 3
- { child_comm: evolution-sourc } hitcount: 4
- { child_comm: dhclient } hitcount: 4
- { child_comm: pool } hitcount: 5
- { child_comm: nm-dispatcher.a } hitcount: 8
- { child_comm: firefox } hitcount: 8
- { child_comm: dbus-daemon } hitcount: 8
- { child_comm: glib-pacrunner } hitcount: 10
- { child_comm: evolution } hitcount: 23
-
- Totals:
- Hits: 89
- Entries: 20
- Dropped: 0
-
- If we want to pause the hist trigger, we can simply append :pause to
- the command that started the trigger. Notice that the trigger info
- displays as [paused]:
-
- # echo 'hist:key=child_comm:val=hitcount:size=256:pause' >> \
- /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
-
- # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
- # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [paused]
-
- { child_comm: dconf worker } hitcount: 1
- { child_comm: kthreadd } hitcount: 1
- { child_comm: dconf worker } hitcount: 1
- { child_comm: gdbus } hitcount: 1
- { child_comm: ibus-daemon } hitcount: 1
- { child_comm: Socket Thread } hitcount: 2
- { child_comm: evolution-alarm } hitcount: 2
- { child_comm: smbd } hitcount: 2
- { child_comm: bash } hitcount: 3
- { child_comm: whoopsie } hitcount: 3
- { child_comm: compiz } hitcount: 3
- { child_comm: evolution-sourc } hitcount: 4
- { child_comm: pool } hitcount: 5
- { child_comm: postgres } hitcount: 6
- { child_comm: firefox } hitcount: 8
- { child_comm: dhclient } hitcount: 10
- { child_comm: emacs } hitcount: 12
- { child_comm: dbus-daemon } hitcount: 20
- { child_comm: nm-dispatcher.a } hitcount: 20
- { child_comm: evolution } hitcount: 35
- { child_comm: glib-pacrunner } hitcount: 59
-
- Totals:
- Hits: 199
- Entries: 21
- Dropped: 0
-
- To manually continue having the trigger aggregate events, append
- :cont instead. Notice that the trigger info displays as [active]
- again, and the data has changed:
-
- # echo 'hist:key=child_comm:val=hitcount:size=256:cont' >> \
- /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
-
- # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
- # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
-
- { child_comm: dconf worker } hitcount: 1
- { child_comm: dconf worker } hitcount: 1
- { child_comm: kthreadd } hitcount: 1
- { child_comm: gdbus } hitcount: 1
- { child_comm: ibus-daemon } hitcount: 1
- { child_comm: Socket Thread } hitcount: 2
- { child_comm: evolution-alarm } hitcount: 2
- { child_comm: smbd } hitcount: 2
- { child_comm: whoopsie } hitcount: 3
- { child_comm: compiz } hitcount: 3
- { child_comm: evolution-sourc } hitcount: 4
- { child_comm: bash } hitcount: 5
- { child_comm: pool } hitcount: 5
- { child_comm: postgres } hitcount: 6
- { child_comm: firefox } hitcount: 8
- { child_comm: dhclient } hitcount: 11
- { child_comm: emacs } hitcount: 12
- { child_comm: dbus-daemon } hitcount: 22
- { child_comm: nm-dispatcher.a } hitcount: 22
- { child_comm: evolution } hitcount: 35
- { child_comm: glib-pacrunner } hitcount: 59
-
- Totals:
- Hits: 206
- Entries: 21
- Dropped: 0
-
- The previous example showed how to start and stop a hist trigger by
- appending 'pause' and 'continue' to the hist trigger command. A
- hist trigger can also be started in a paused state by initially
- starting the trigger with ':pause' appended. This allows you to
- start the trigger only when you're ready to start collecting data
- and not before. For example, you could start the trigger in a
- paused state, then unpause it and do something you want to measure,
- then pause the trigger again when done.
-
- Of course, doing this manually can be difficult and error-prone, but
- it is possible to automatically start and stop a hist trigger based
- on some condition, via the enable_hist and disable_hist triggers.
-
- For example, suppose we wanted to take a look at the relative
- weights in terms of skb length for each callpath that leads to a
- netif_receieve_skb event when downloading a decent-sized file using
- wget.
-
- First we set up an initially paused stacktrace trigger on the
- netif_receive_skb event:
-
- # echo 'hist:key=stacktrace:vals=len:pause' > \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
-
- Next, we set up an 'enable_hist' trigger on the sched_process_exec
- event, with an 'if filename==/usr/bin/wget' filter. The effect of
- this new trigger is that it will 'unpause' the hist trigger we just
- set up on netif_receive_skb if and only if it sees a
- sched_process_exec event with a filename of '/usr/bin/wget'. When
- that happens, all netif_receive_skb events are aggregated into a
- hash table keyed on stacktrace:
-
- # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
-
- The aggregation continues until the netif_receive_skb is paused
- again, which is what the following disable_hist event does by
- creating a similar setup on the sched_process_exit event, using the
- filter 'comm==wget':
-
- # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
-
- Whenever a process exits and the comm field of the disable_hist
- trigger filter matches 'comm==wget', the netif_receive_skb hist
- trigger is disabled.
-
- The overall effect is that netif_receive_skb events are aggregated
- into the hash table for only the duration of the wget. Executing a
- wget command and then listing the 'hist' file will display the
- output generated by the wget command:
-
- $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
-
- # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
- # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
-
- { stacktrace:
- __netif_receive_skb_core+0x46d/0x990
- __netif_receive_skb+0x18/0x60
- netif_receive_skb_internal+0x23/0x90
- napi_gro_receive+0xc8/0x100
- ieee80211_deliver_skb+0xd6/0x270 [mac80211]
- ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
- ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
- ieee80211_rx+0x31d/0x900 [mac80211]
- iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
- iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
- iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
- irq_thread_fn+0x20/0x50
- irq_thread+0x11f/0x150
- kthread+0xd2/0xf0
- ret_from_fork+0x42/0x70
- } hitcount: 85 len: 28884
- { stacktrace:
- __netif_receive_skb_core+0x46d/0x990
- __netif_receive_skb+0x18/0x60
- netif_receive_skb_internal+0x23/0x90
- napi_gro_complete+0xa4/0xe0
- dev_gro_receive+0x23a/0x360
- napi_gro_receive+0x30/0x100
- ieee80211_deliver_skb+0xd6/0x270 [mac80211]
- ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
- ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
- ieee80211_rx+0x31d/0x900 [mac80211]
- iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
- iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
- iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
- irq_thread_fn+0x20/0x50
- irq_thread+0x11f/0x150
- kthread+0xd2/0xf0
- } hitcount: 98 len: 664329
- { stacktrace:
- __netif_receive_skb_core+0x46d/0x990
- __netif_receive_skb+0x18/0x60
- process_backlog+0xa8/0x150
- net_rx_action+0x15d/0x340
- __do_softirq+0x114/0x2c0
- do_softirq_own_stack+0x1c/0x30
- do_softirq+0x65/0x70
- __local_bh_enable_ip+0xb5/0xc0
- ip_finish_output+0x1f4/0x840
- ip_output+0x6b/0xc0
- ip_local_out_sk+0x31/0x40
- ip_send_skb+0x1a/0x50
- udp_send_skb+0x173/0x2a0
- udp_sendmsg+0x2bf/0x9f0
- inet_sendmsg+0x64/0xa0
- sock_sendmsg+0x3d/0x50
- } hitcount: 115 len: 13030
- { stacktrace:
- __netif_receive_skb_core+0x46d/0x990
- __netif_receive_skb+0x18/0x60
- netif_receive_skb_internal+0x23/0x90
- napi_gro_complete+0xa4/0xe0
- napi_gro_flush+0x6d/0x90
- iwl_pcie_irq_handler+0x92a/0x12f0 [iwlwifi]
- irq_thread_fn+0x20/0x50
- irq_thread+0x11f/0x150
- kthread+0xd2/0xf0
- ret_from_fork+0x42/0x70
- } hitcount: 934 len: 5512212
-
- Totals:
- Hits: 1232
- Entries: 4
- Dropped: 0
-
- The above shows all the netif_receive_skb callpaths and their total
- lengths for the duration of the wget command.
-
- The 'clear' hist trigger param can be used to clear the hash table.
- Suppose we wanted to try another run of the previous example but
- this time also wanted to see the complete list of events that went
- into the histogram. In order to avoid having to set everything up
- again, we can just clear the histogram first:
-
- # echo 'hist:key=stacktrace:vals=len:clear' >> \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
-
- Just to verify that it is in fact cleared, here's what we now see in
- the hist file:
-
- # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
- # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
-
- Totals:
- Hits: 0
- Entries: 0
- Dropped: 0
-
- Since we want to see the detailed list of every netif_receive_skb
- event occurring during the new run, which are in fact the same
- events being aggregated into the hash table, we add some additional
- 'enable_event' events to the triggering sched_process_exec and
- sched_process_exit events as such:
-
- # echo 'enable_event:net:netif_receive_skb if filename==/usr/bin/wget' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
-
- # echo 'disable_event:net:netif_receive_skb if comm==wget' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
-
- If you read the trigger files for the sched_process_exec and
- sched_process_exit triggers, you should see two triggers for each:
- one enabling/disabling the hist aggregation and the other
- enabling/disabling the logging of events:
-
- # cat /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
- enable_event:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
- enable_hist:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
-
- # cat /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
- enable_event:net:netif_receive_skb:unlimited if comm==wget
- disable_hist:net:netif_receive_skb:unlimited if comm==wget
-
- In other words, whenever either of the sched_process_exec or
- sched_process_exit events is hit and matches 'wget', it enables or
- disables both the histogram and the event log, and what you end up
- with is a hash table and set of events just covering the specified
- duration. Run the wget command again:
-
- $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
-
- Displaying the 'hist' file should show something similar to what you
- saw in the last run, but this time you should also see the
- individual events in the trace file:
-
- # cat /sys/kernel/debug/tracing/trace
-
- # tracer: nop
- #
- # entries-in-buffer/entries-written: 183/1426 #P:4
- #
- # _-----=> irqs-off
- # / _----=> need-resched
- # | / _---=> hardirq/softirq
- # || / _--=> preempt-depth
- # ||| / delay
- # TASK-PID CPU# |||| TIMESTAMP FUNCTION
- # | | | |||| | |
- wget-15108 [000] ..s1 31769.606929: netif_receive_skb: dev=lo skbaddr=ffff88009c353100 len=60
- wget-15108 [000] ..s1 31769.606999: netif_receive_skb: dev=lo skbaddr=ffff88009c353200 len=60
- dnsmasq-1382 [000] ..s1 31769.677652: netif_receive_skb: dev=lo skbaddr=ffff88009c352b00 len=130
- dnsmasq-1382 [000] ..s1 31769.685917: netif_receive_skb: dev=lo skbaddr=ffff88009c352200 len=138
- ##### CPU 2 buffer started ####
- irq/29-iwlwifi-559 [002] ..s. 31772.031529: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433d00 len=2948
- irq/29-iwlwifi-559 [002] ..s. 31772.031572: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432200 len=1500
- irq/29-iwlwifi-559 [002] ..s. 31772.032196: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433100 len=2948
- irq/29-iwlwifi-559 [002] ..s. 31772.032761: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433000 len=2948
- irq/29-iwlwifi-559 [002] ..s. 31772.033220: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432e00 len=1500
- .
- .
- .
-
- The following example demonstrates how multiple hist triggers can be
- attached to a given event. This capability can be useful for
- creating a set of different summaries derived from the same set of
- events, or for comparing the effects of different filters, among
- other things.
-
- # echo 'hist:keys=skbaddr.hex:vals=len if len < 0' >> \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
- # echo 'hist:keys=skbaddr.hex:vals=len if len > 4096' >> \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
- # echo 'hist:keys=skbaddr.hex:vals=len if len == 256' >> \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
- # echo 'hist:keys=skbaddr.hex:vals=len' >> \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
- # echo 'hist:keys=len:vals=common_preempt_count' >> \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
-
- The above set of commands create four triggers differing only in
- their filters, along with a completely different though fairly
- nonsensical trigger. Note that in order to append multiple hist
- triggers to the same file, you should use the '>>' operator to
- append them ('>' will also add the new hist trigger, but will remove
- any existing hist triggers beforehand).
-
- Displaying the contents of the 'hist' file for the event shows the
- contents of all five histograms:
-
- # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
-
- # event histogram
- #
- # trigger info: hist:keys=len:vals=hitcount,common_preempt_count:sort=hitcount:size=2048 [active]
- #
-
- { len: 176 } hitcount: 1 common_preempt_count: 0
- { len: 223 } hitcount: 1 common_preempt_count: 0
- { len: 4854 } hitcount: 1 common_preempt_count: 0
- { len: 395 } hitcount: 1 common_preempt_count: 0
- { len: 177 } hitcount: 1 common_preempt_count: 0
- { len: 446 } hitcount: 1 common_preempt_count: 0
- { len: 1601 } hitcount: 1 common_preempt_count: 0
- .
- .
- .
- { len: 1280 } hitcount: 66 common_preempt_count: 0
- { len: 116 } hitcount: 81 common_preempt_count: 40
- { len: 708 } hitcount: 112 common_preempt_count: 0
- { len: 46 } hitcount: 221 common_preempt_count: 0
- { len: 1264 } hitcount: 458 common_preempt_count: 0
-
- Totals:
- Hits: 1428
- Entries: 147
- Dropped: 0
-
-
- # event histogram
- #
- # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
- #
-
- { skbaddr: ffff8800baee5e00 } hitcount: 1 len: 130
- { skbaddr: ffff88005f3d5600 } hitcount: 1 len: 1280
- { skbaddr: ffff88005f3d4900 } hitcount: 1 len: 1280
- { skbaddr: ffff88009fed6300 } hitcount: 1 len: 115
- { skbaddr: ffff88009fe0ad00 } hitcount: 1 len: 115
- { skbaddr: ffff88008cdb1900 } hitcount: 1 len: 46
- { skbaddr: ffff880064b5ef00 } hitcount: 1 len: 118
- { skbaddr: ffff880044e3c700 } hitcount: 1 len: 60
- { skbaddr: ffff880100065900 } hitcount: 1 len: 46
- { skbaddr: ffff8800d46bd500 } hitcount: 1 len: 116
- { skbaddr: ffff88005f3d5f00 } hitcount: 1 len: 1280
- { skbaddr: ffff880100064700 } hitcount: 1 len: 365
- { skbaddr: ffff8800badb6f00 } hitcount: 1 len: 60
- .
- .
- .
- { skbaddr: ffff88009fe0be00 } hitcount: 27 len: 24677
- { skbaddr: ffff88009fe0a400 } hitcount: 27 len: 23052
- { skbaddr: ffff88009fe0b700 } hitcount: 31 len: 25589
- { skbaddr: ffff88009fe0b600 } hitcount: 32 len: 27326
- { skbaddr: ffff88006a462800 } hitcount: 68 len: 71678
- { skbaddr: ffff88006a463700 } hitcount: 70 len: 72678
- { skbaddr: ffff88006a462b00 } hitcount: 71 len: 77589
- { skbaddr: ffff88006a463600 } hitcount: 73 len: 71307
- { skbaddr: ffff88006a462200 } hitcount: 81 len: 81032
-
- Totals:
- Hits: 1451
- Entries: 318
- Dropped: 0
-
-
- # event histogram
- #
- # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len == 256 [active]
- #
-
-
- Totals:
- Hits: 0
- Entries: 0
- Dropped: 0
-
-
- # event histogram
- #
- # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len > 4096 [active]
- #
-
- { skbaddr: ffff88009fd2c300 } hitcount: 1 len: 7212
- { skbaddr: ffff8800d2bcce00 } hitcount: 1 len: 7212
- { skbaddr: ffff8800d2bcd700 } hitcount: 1 len: 7212
- { skbaddr: ffff8800d2bcda00 } hitcount: 1 len: 21492
- { skbaddr: ffff8800ae2e2d00 } hitcount: 1 len: 7212
- { skbaddr: ffff8800d2bcdb00 } hitcount: 1 len: 7212
- { skbaddr: ffff88006a4df500 } hitcount: 1 len: 4854
- { skbaddr: ffff88008ce47b00 } hitcount: 1 len: 18636
- { skbaddr: ffff8800ae2e2200 } hitcount: 1 len: 12924
- { skbaddr: ffff88005f3e1000 } hitcount: 1 len: 4356
- { skbaddr: ffff8800d2bcdc00 } hitcount: 2 len: 24420
- { skbaddr: ffff8800d2bcc200 } hitcount: 2 len: 12996
-
- Totals:
- Hits: 14
- Entries: 12
- Dropped: 0
-
-
- # event histogram
- #
- # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len < 0 [active]
- #
-
-
- Totals:
- Hits: 0
- Entries: 0
- Dropped: 0
-
- Named triggers can be used to have triggers share a common set of
- histogram data. This capability is mostly useful for combining the
- output of events generated by tracepoints contained inside inline
- functions, but names can be used in a hist trigger on any event.
- For example, these two triggers when hit will update the same 'len'
- field in the shared 'foo' histogram data:
-
- # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
- /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
- # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
- /sys/kernel/debug/tracing/events/net/netif_rx/trigger
-
- You can see that they're updating common histogram data by reading
- each event's hist files at the same time:
-
- # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist;
- cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
-
- # event histogram
- #
- # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
- #
-
- { skbaddr: ffff88000ad53500 } hitcount: 1 len: 46
- { skbaddr: ffff8800af5a1500 } hitcount: 1 len: 76
- { skbaddr: ffff8800d62a1900 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bccb00 } hitcount: 1 len: 468
- { skbaddr: ffff8800d3c69900 } hitcount: 1 len: 46
- { skbaddr: ffff88009ff09100 } hitcount: 1 len: 52
- { skbaddr: ffff88010f13ab00 } hitcount: 1 len: 168
- { skbaddr: ffff88006a54f400 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bcc500 } hitcount: 1 len: 260
- { skbaddr: ffff880064505000 } hitcount: 1 len: 46
- { skbaddr: ffff8800baf24e00 } hitcount: 1 len: 32
- { skbaddr: ffff88009fe0ad00 } hitcount: 1 len: 46
- { skbaddr: ffff8800d3edff00 } hitcount: 1 len: 44
- { skbaddr: ffff88009fe0b400 } hitcount: 1 len: 168
- { skbaddr: ffff8800a1c55a00 } hitcount: 1 len: 40
- { skbaddr: ffff8800d2bcd100 } hitcount: 1 len: 40
- { skbaddr: ffff880064505f00 } hitcount: 1 len: 174
- { skbaddr: ffff8800a8bff200 } hitcount: 1 len: 160
- { skbaddr: ffff880044e3cc00 } hitcount: 1 len: 76
- { skbaddr: ffff8800a8bfe700 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bcdc00 } hitcount: 1 len: 32
- { skbaddr: ffff8800a1f64800 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bcde00 } hitcount: 1 len: 988
- { skbaddr: ffff88006a5dea00 } hitcount: 1 len: 46
- { skbaddr: ffff88002e37a200 } hitcount: 1 len: 44
- { skbaddr: ffff8800a1f32c00 } hitcount: 2 len: 676
- { skbaddr: ffff88000ad52600 } hitcount: 2 len: 107
- { skbaddr: ffff8800a1f91e00 } hitcount: 2 len: 92
- { skbaddr: ffff8800af5a0200 } hitcount: 2 len: 142
- { skbaddr: ffff8800d2bcc600 } hitcount: 2 len: 220
- { skbaddr: ffff8800ba36f500 } hitcount: 2 len: 92
- { skbaddr: ffff8800d021f800 } hitcount: 2 len: 92
- { skbaddr: ffff8800a1f33600 } hitcount: 2 len: 675
- { skbaddr: ffff8800a8bfff00 } hitcount: 3 len: 138
- { skbaddr: ffff8800d62a1300 } hitcount: 3 len: 138
- { skbaddr: ffff88002e37a100 } hitcount: 4 len: 184
- { skbaddr: ffff880064504400 } hitcount: 4 len: 184
- { skbaddr: ffff8800a8bfec00 } hitcount: 4 len: 184
- { skbaddr: ffff88000ad53700 } hitcount: 5 len: 230
- { skbaddr: ffff8800d2bcdb00 } hitcount: 5 len: 196
- { skbaddr: ffff8800a1f90000 } hitcount: 6 len: 276
- { skbaddr: ffff88006a54f900 } hitcount: 6 len: 276
-
- Totals:
- Hits: 81
- Entries: 42
- Dropped: 0
- # event histogram
- #
- # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
- #
-
- { skbaddr: ffff88000ad53500 } hitcount: 1 len: 46
- { skbaddr: ffff8800af5a1500 } hitcount: 1 len: 76
- { skbaddr: ffff8800d62a1900 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bccb00 } hitcount: 1 len: 468
- { skbaddr: ffff8800d3c69900 } hitcount: 1 len: 46
- { skbaddr: ffff88009ff09100 } hitcount: 1 len: 52
- { skbaddr: ffff88010f13ab00 } hitcount: 1 len: 168
- { skbaddr: ffff88006a54f400 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bcc500 } hitcount: 1 len: 260
- { skbaddr: ffff880064505000 } hitcount: 1 len: 46
- { skbaddr: ffff8800baf24e00 } hitcount: 1 len: 32
- { skbaddr: ffff88009fe0ad00 } hitcount: 1 len: 46
- { skbaddr: ffff8800d3edff00 } hitcount: 1 len: 44
- { skbaddr: ffff88009fe0b400 } hitcount: 1 len: 168
- { skbaddr: ffff8800a1c55a00 } hitcount: 1 len: 40
- { skbaddr: ffff8800d2bcd100 } hitcount: 1 len: 40
- { skbaddr: ffff880064505f00 } hitcount: 1 len: 174
- { skbaddr: ffff8800a8bff200 } hitcount: 1 len: 160
- { skbaddr: ffff880044e3cc00 } hitcount: 1 len: 76
- { skbaddr: ffff8800a8bfe700 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bcdc00 } hitcount: 1 len: 32
- { skbaddr: ffff8800a1f64800 } hitcount: 1 len: 46
- { skbaddr: ffff8800d2bcde00 } hitcount: 1 len: 988
- { skbaddr: ffff88006a5dea00 } hitcount: 1 len: 46
- { skbaddr: ffff88002e37a200 } hitcount: 1 len: 44
- { skbaddr: ffff8800a1f32c00 } hitcount: 2 len: 676
- { skbaddr: ffff88000ad52600 } hitcount: 2 len: 107
- { skbaddr: ffff8800a1f91e00 } hitcount: 2 len: 92
- { skbaddr: ffff8800af5a0200 } hitcount: 2 len: 142
- { skbaddr: ffff8800d2bcc600 } hitcount: 2 len: 220
- { skbaddr: ffff8800ba36f500 } hitcount: 2 len: 92
- { skbaddr: ffff8800d021f800 } hitcount: 2 len: 92
- { skbaddr: ffff8800a1f33600 } hitcount: 2 len: 675
- { skbaddr: ffff8800a8bfff00 } hitcount: 3 len: 138
- { skbaddr: ffff8800d62a1300 } hitcount: 3 len: 138
- { skbaddr: ffff88002e37a100 } hitcount: 4 len: 184
- { skbaddr: ffff880064504400 } hitcount: 4 len: 184
- { skbaddr: ffff8800a8bfec00 } hitcount: 4 len: 184
- { skbaddr: ffff88000ad53700 } hitcount: 5 len: 230
- { skbaddr: ffff8800d2bcdb00 } hitcount: 5 len: 196
- { skbaddr: ffff8800a1f90000 } hitcount: 6 len: 276
- { skbaddr: ffff88006a54f900 } hitcount: 6 len: 276
-
- Totals:
- Hits: 81
- Entries: 42
- Dropped: 0
-
- And here's an example that shows how to combine histogram data from
- any two events even if they don't share any 'compatible' fields
- other than 'hitcount' and 'stacktrace'. These commands create a
- couple of triggers named 'bar' using those fields:
-
- # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
- /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
- # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
- /sys/kernel/debug/tracing/events/net/netif_rx/trigger
-
- And displaying the output of either shows some interesting if
- somewhat confusing output:
-
- # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
- # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
-
- # event histogram
- #
- # trigger info: hist:name=bar:keys=stacktrace:vals=hitcount:sort=hitcount:size=2048 [active]
- #
-
- { stacktrace:
- _do_fork+0x18e/0x330
- kernel_thread+0x29/0x30
- kthreadd+0x154/0x1b0
- ret_from_fork+0x3f/0x70
- } hitcount: 1
- { stacktrace:
- netif_rx_internal+0xb2/0xd0
- netif_rx_ni+0x20/0x70
- dev_loopback_xmit+0xaa/0xd0
- ip_mc_output+0x126/0x240
- ip_local_out_sk+0x31/0x40
- igmp_send_report+0x1e9/0x230
- igmp_timer_expire+0xe9/0x120
- call_timer_fn+0x39/0xf0
- run_timer_softirq+0x1e1/0x290
- __do_softirq+0xfd/0x290
- irq_exit+0x98/0xb0
- smp_apic_timer_interrupt+0x4a/0x60
- apic_timer_interrupt+0x6d/0x80
- cpuidle_enter+0x17/0x20
- call_cpuidle+0x3b/0x60
- cpu_startup_entry+0x22d/0x310
- } hitcount: 1
- { stacktrace:
- netif_rx_internal+0xb2/0xd0
- netif_rx_ni+0x20/0x70
- dev_loopback_xmit+0xaa/0xd0
- ip_mc_output+0x17f/0x240
- ip_local_out_sk+0x31/0x40
- ip_send_skb+0x1a/0x50
- udp_send_skb+0x13e/0x270
- udp_sendmsg+0x2bf/0x980
- inet_sendmsg+0x67/0xa0
- sock_sendmsg+0x38/0x50
- SYSC_sendto+0xef/0x170
- SyS_sendto+0xe/0x10
- entry_SYSCALL_64_fastpath+0x12/0x6a
- } hitcount: 2
- { stacktrace:
- netif_rx_internal+0xb2/0xd0
- netif_rx+0x1c/0x60
- loopback_xmit+0x6c/0xb0
- dev_hard_start_xmit+0x219/0x3a0
- __dev_queue_xmit+0x415/0x4f0
- dev_queue_xmit_sk+0x13/0x20
- ip_finish_output2+0x237/0x340
- ip_finish_output+0x113/0x1d0
- ip_output+0x66/0xc0
- ip_local_out_sk+0x31/0x40
- ip_send_skb+0x1a/0x50
- udp_send_skb+0x16d/0x270
- udp_sendmsg+0x2bf/0x980
- inet_sendmsg+0x67/0xa0
- sock_sendmsg+0x38/0x50
- ___sys_sendmsg+0x14e/0x270
- } hitcount: 76
- { stacktrace:
- netif_rx_internal+0xb2/0xd0
- netif_rx+0x1c/0x60
- loopback_xmit+0x6c/0xb0
- dev_hard_start_xmit+0x219/0x3a0
- __dev_queue_xmit+0x415/0x4f0
- dev_queue_xmit_sk+0x13/0x20
- ip_finish_output2+0x237/0x340
- ip_finish_output+0x113/0x1d0
- ip_output+0x66/0xc0
- ip_local_out_sk+0x31/0x40
- ip_send_skb+0x1a/0x50
- udp_send_skb+0x16d/0x270
- udp_sendmsg+0x2bf/0x980
- inet_sendmsg+0x67/0xa0
- sock_sendmsg+0x38/0x50
- ___sys_sendmsg+0x269/0x270
- } hitcount: 77
- { stacktrace:
- netif_rx_internal+0xb2/0xd0
- netif_rx+0x1c/0x60
- loopback_xmit+0x6c/0xb0
- dev_hard_start_xmit+0x219/0x3a0
- __dev_queue_xmit+0x415/0x4f0
- dev_queue_xmit_sk+0x13/0x20
- ip_finish_output2+0x237/0x340
- ip_finish_output+0x113/0x1d0
- ip_output+0x66/0xc0
- ip_local_out_sk+0x31/0x40
- ip_send_skb+0x1a/0x50
- udp_send_skb+0x16d/0x270
- udp_sendmsg+0x2bf/0x980
- inet_sendmsg+0x67/0xa0
- sock_sendmsg+0x38/0x50
- SYSC_sendto+0xef/0x170
- } hitcount: 88
- { stacktrace:
- _do_fork+0x18e/0x330
- SyS_clone+0x19/0x20
- entry_SYSCALL_64_fastpath+0x12/0x6a
- } hitcount: 244
-
- Totals:
- Hits: 489
- Entries: 7
- Dropped: 0
diff --git a/Documentation/trace/ftrace-design.rst b/Documentation/trace/ftrace-design.rst
new file mode 100644
index 000000000000..a8e22e0db63c
--- /dev/null
+++ b/Documentation/trace/ftrace-design.rst
@@ -0,0 +1,419 @@
+======================
+Function Tracer Design
+======================
+
+:Author: Mike Frysinger
+
+.. caution::
+ This document is out of date. Some of the description below doesn't
+ match current implementation now.
+
+Introduction
+------------
+
+Here we will cover the architecture pieces that the common function tracing
+code relies on for proper functioning. Things are broken down into increasing
+complexity so that you can start simple and at least get basic functionality.
+
+Note that this focuses on architecture implementation details only. If you
+want more explanation of a feature in terms of common code, review the common
+ftrace.txt file.
+
+Ideally, everyone who wishes to retain performance while supporting tracing in
+their kernel should make it all the way to dynamic ftrace support.
+
+
+Prerequisites
+-------------
+
+Ftrace relies on these features being implemented:
+ - STACKTRACE_SUPPORT - implement save_stack_trace()
+ - TRACE_IRQFLAGS_SUPPORT - implement include/asm/irqflags.h
+
+
+HAVE_FUNCTION_TRACER
+--------------------
+
+You will need to implement the mcount and the ftrace_stub functions.
+
+The exact mcount symbol name will depend on your toolchain. Some call it
+"mcount", "_mcount", or even "__mcount". You can probably figure it out by
+running something like::
+
+ $ echo 'main(){}' | gcc -x c -S -o - - -pg | grep mcount
+ call mcount
+
+We'll make the assumption below that the symbol is "mcount" just to keep things
+nice and simple in the examples.
+
+Keep in mind that the ABI that is in effect inside of the mcount function is
+*highly* architecture/toolchain specific. We cannot help you in this regard,
+sorry. Dig up some old documentation and/or find someone more familiar than
+you to bang ideas off of. Typically, register usage (argument/scratch/etc...)
+is a major issue at this point, especially in relation to the location of the
+mcount call (before/after function prologue). You might also want to look at
+how glibc has implemented the mcount function for your architecture. It might
+be (semi-)relevant.
+
+The mcount function should check the function pointer ftrace_trace_function
+to see if it is set to ftrace_stub. If it is, there is nothing for you to do,
+so return immediately. If it isn't, then call that function in the same way
+the mcount function normally calls __mcount_internal -- the first argument is
+the "frompc" while the second argument is the "selfpc" (adjusted to remove the
+size of the mcount call that is embedded in the function).
+
+For example, if the function foo() calls bar(), when the bar() function calls
+mcount(), the arguments mcount() will pass to the tracer are:
+
+ - "frompc" - the address bar() will use to return to foo()
+ - "selfpc" - the address bar() (with mcount() size adjustment)
+
+Also keep in mind that this mcount function will be called *a lot*, so
+optimizing for the default case of no tracer will help the smooth running of
+your system when tracing is disabled. So the start of the mcount function is
+typically the bare minimum with checking things before returning. That also
+means the code flow should usually be kept linear (i.e. no branching in the nop
+case). This is of course an optimization and not a hard requirement.
+
+Here is some pseudo code that should help (these functions should actually be
+implemented in assembly)::
+
+ void ftrace_stub(void)
+ {
+ return;
+ }
+
+ void mcount(void)
+ {
+ /* save any bare state needed in order to do initial checking */
+
+ extern void (*ftrace_trace_function)(unsigned long, unsigned long);
+ if (ftrace_trace_function != ftrace_stub)
+ goto do_trace;
+
+ /* restore any bare state */
+
+ return;
+
+ do_trace:
+
+ /* save all state needed by the ABI (see paragraph above) */
+
+ unsigned long frompc = ...;
+ unsigned long selfpc = <return address> - MCOUNT_INSN_SIZE;
+ ftrace_trace_function(frompc, selfpc);
+
+ /* restore all state needed by the ABI */
+ }
+
+Don't forget to export mcount for modules !
+::
+
+ extern void mcount(void);
+ EXPORT_SYMBOL(mcount);
+
+
+HAVE_FUNCTION_GRAPH_TRACER
+--------------------------
+
+Deep breath ... time to do some real work. Here you will need to update the
+mcount function to check ftrace graph function pointers, as well as implement
+some functions to save (hijack) and restore the return address.
+
+The mcount function should check the function pointers ftrace_graph_return
+(compare to ftrace_stub) and ftrace_graph_entry (compare to
+ftrace_graph_entry_stub). If either of those is not set to the relevant stub
+function, call the arch-specific function ftrace_graph_caller which in turn
+calls the arch-specific function prepare_ftrace_return. Neither of these
+function names is strictly required, but you should use them anyway to stay
+consistent across the architecture ports -- easier to compare & contrast
+things.
+
+The arguments to prepare_ftrace_return are slightly different than what are
+passed to ftrace_trace_function. The second argument "selfpc" is the same,
+but the first argument should be a pointer to the "frompc". Typically this is
+located on the stack. This allows the function to hijack the return address
+temporarily to have it point to the arch-specific function return_to_handler.
+That function will simply call the common ftrace_return_to_handler function and
+that will return the original return address with which you can return to the
+original call site.
+
+Here is the updated mcount pseudo code::
+
+ void mcount(void)
+ {
+ ...
+ if (ftrace_trace_function != ftrace_stub)
+ goto do_trace;
+
+ +#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ + extern void (*ftrace_graph_return)(...);
+ + extern void (*ftrace_graph_entry)(...);
+ + if (ftrace_graph_return != ftrace_stub ||
+ + ftrace_graph_entry != ftrace_graph_entry_stub)
+ + ftrace_graph_caller();
+ +#endif
+
+ /* restore any bare state */
+ ...
+
+Here is the pseudo code for the new ftrace_graph_caller assembly function::
+
+ #ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ void ftrace_graph_caller(void)
+ {
+ /* save all state needed by the ABI */
+
+ unsigned long *frompc = &...;
+ unsigned long selfpc = <return address> - MCOUNT_INSN_SIZE;
+ /* passing frame pointer up is optional -- see below */
+ prepare_ftrace_return(frompc, selfpc, frame_pointer);
+
+ /* restore all state needed by the ABI */
+ }
+ #endif
+
+For information on how to implement prepare_ftrace_return(), simply look at the
+x86 version (the frame pointer passing is optional; see the next section for
+more information). The only architecture-specific piece in it is the setup of
+the fault recovery table (the asm(...) code). The rest should be the same
+across architectures.
+
+Here is the pseudo code for the new return_to_handler assembly function. Note
+that the ABI that applies here is different from what applies to the mcount
+code. Since you are returning from a function (after the epilogue), you might
+be able to skimp on things saved/restored (usually just registers used to pass
+return values).
+::
+
+ #ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ void return_to_handler(void)
+ {
+ /* save all state needed by the ABI (see paragraph above) */
+
+ void (*original_return_point)(void) = ftrace_return_to_handler();
+
+ /* restore all state needed by the ABI */
+
+ /* this is usually either a return or a jump */
+ original_return_point();
+ }
+ #endif
+
+
+HAVE_FUNCTION_GRAPH_FP_TEST
+---------------------------
+
+An arch may pass in a unique value (frame pointer) to both the entering and
+exiting of a function. On exit, the value is compared and if it does not
+match, then it will panic the kernel. This is largely a sanity check for bad
+code generation with gcc. If gcc for your port sanely updates the frame
+pointer under different optimization levels, then ignore this option.
+
+However, adding support for it isn't terribly difficult. In your assembly code
+that calls prepare_ftrace_return(), pass the frame pointer as the 3rd argument.
+Then in the C version of that function, do what the x86 port does and pass it
+along to ftrace_push_return_trace() instead of a stub value of 0.
+
+Similarly, when you call ftrace_return_to_handler(), pass it the frame pointer.
+
+HAVE_FUNCTION_GRAPH_RET_ADDR_PTR
+--------------------------------
+
+An arch may pass in a pointer to the return address on the stack. This
+prevents potential stack unwinding issues where the unwinder gets out of
+sync with ret_stack and the wrong addresses are reported by
+ftrace_graph_ret_addr().
+
+Adding support for it is easy: just define the macro in asm/ftrace.h and
+pass the return address pointer as the 'retp' argument to
+ftrace_push_return_trace().
+
+HAVE_FTRACE_NMI_ENTER
+---------------------
+
+If you can't trace NMI functions, then skip this option.
+
+<details to be filled>
+
+
+HAVE_SYSCALL_TRACEPOINTS
+------------------------
+
+You need very few things to get the syscalls tracing in an arch.
+
+ - Support HAVE_ARCH_TRACEHOOK (see arch/Kconfig).
+ - Have a NR_syscalls variable in <asm/unistd.h> that provides the number
+ of syscalls supported by the arch.
+ - Support the TIF_SYSCALL_TRACEPOINT thread flags.
+ - Put the trace_sys_enter() and trace_sys_exit() tracepoints calls from ptrace
+ in the ptrace syscalls tracing path.
+ - If the system call table on this arch is more complicated than a simple array
+ of addresses of the system calls, implement an arch_syscall_addr to return
+ the address of a given system call.
+ - If the symbol names of the system calls do not match the function names on
+ this arch, define ARCH_HAS_SYSCALL_MATCH_SYM_NAME in asm/ftrace.h and
+ implement arch_syscall_match_sym_name with the appropriate logic to return
+ true if the function name corresponds with the symbol name.
+ - Tag this arch as HAVE_SYSCALL_TRACEPOINTS.
+
+
+HAVE_FTRACE_MCOUNT_RECORD
+-------------------------
+
+See scripts/recordmcount.pl for more info. Just fill in the arch-specific
+details for how to locate the addresses of mcount call sites via objdump.
+This option doesn't make much sense without also implementing dynamic ftrace.
+
+
+HAVE_DYNAMIC_FTRACE
+-------------------
+
+You will first need HAVE_FTRACE_MCOUNT_RECORD and HAVE_FUNCTION_TRACER, so
+scroll your reader back up if you got over eager.
+
+Once those are out of the way, you will need to implement:
+ - asm/ftrace.h:
+ - MCOUNT_ADDR
+ - ftrace_call_adjust()
+ - struct dyn_arch_ftrace{}
+ - asm code:
+ - mcount() (new stub)
+ - ftrace_caller()
+ - ftrace_call()
+ - ftrace_stub()
+ - C code:
+ - ftrace_dyn_arch_init()
+ - ftrace_make_nop()
+ - ftrace_make_call()
+ - ftrace_update_ftrace_func()
+
+First you will need to fill out some arch details in your asm/ftrace.h.
+
+Define MCOUNT_ADDR as the address of your mcount symbol similar to::
+
+ #define MCOUNT_ADDR ((unsigned long)mcount)
+
+Since no one else will have a decl for that function, you will need to::
+
+ extern void mcount(void);
+
+You will also need the helper function ftrace_call_adjust(). Most people
+will be able to stub it out like so::
+
+ static inline unsigned long ftrace_call_adjust(unsigned long addr)
+ {
+ return addr;
+ }
+
+<details to be filled>
+
+Lastly you will need the custom dyn_arch_ftrace structure. If you need
+some extra state when runtime patching arbitrary call sites, this is the
+place. For now though, create an empty struct::
+
+ struct dyn_arch_ftrace {
+ /* No extra data needed */
+ };
+
+With the header out of the way, we can fill out the assembly code. While we
+did already create a mcount() function earlier, dynamic ftrace only wants a
+stub function. This is because the mcount() will only be used during boot
+and then all references to it will be patched out never to return. Instead,
+the guts of the old mcount() will be used to create a new ftrace_caller()
+function. Because the two are hard to merge, it will most likely be a lot
+easier to have two separate definitions split up by #ifdefs. Same goes for
+the ftrace_stub() as that will now be inlined in ftrace_caller().
+
+Before we get confused anymore, let's check out some pseudo code so you can
+implement your own stuff in assembly::
+
+ void mcount(void)
+ {
+ return;
+ }
+
+ void ftrace_caller(void)
+ {
+ /* save all state needed by the ABI (see paragraph above) */
+
+ unsigned long frompc = ...;
+ unsigned long selfpc = <return address> - MCOUNT_INSN_SIZE;
+
+ ftrace_call:
+ ftrace_stub(frompc, selfpc);
+
+ /* restore all state needed by the ABI */
+
+ ftrace_stub:
+ return;
+ }
+
+This might look a little odd at first, but keep in mind that we will be runtime
+patching multiple things. First, only functions that we actually want to trace
+will be patched to call ftrace_caller(). Second, since we only have one tracer
+active at a time, we will patch the ftrace_caller() function itself to call the
+specific tracer in question. That is the point of the ftrace_call label.
+
+With that in mind, let's move on to the C code that will actually be doing the
+runtime patching. You'll need a little knowledge of your arch's opcodes in
+order to make it through the next section.
+
+Every arch has an init callback function. If you need to do something early on
+to initialize some state, this is the time to do that. Otherwise, this simple
+function below should be sufficient for most people::
+
+ int __init ftrace_dyn_arch_init(void)
+ {
+ return 0;
+ }
+
+There are two functions that are used to do runtime patching of arbitrary
+functions. The first is used to turn the mcount call site into a nop (which
+is what helps us retain runtime performance when not tracing). The second is
+used to turn the mcount call site into a call to an arbitrary location (but
+typically that is ftracer_caller()). See the general function definition in
+linux/ftrace.h for the functions::
+
+ ftrace_make_nop()
+ ftrace_make_call()
+
+The rec->ip value is the address of the mcount call site that was collected
+by the scripts/recordmcount.pl during build time.
+
+The last function is used to do runtime patching of the active tracer. This
+will be modifying the assembly code at the location of the ftrace_call symbol
+inside of the ftrace_caller() function. So you should have sufficient padding
+at that location to support the new function calls you'll be inserting. Some
+people will be using a "call" type instruction while others will be using a
+"branch" type instruction. Specifically, the function is::
+
+ ftrace_update_ftrace_func()
+
+
+HAVE_DYNAMIC_FTRACE + HAVE_FUNCTION_GRAPH_TRACER
+------------------------------------------------
+
+The function grapher needs a few tweaks in order to work with dynamic ftrace.
+Basically, you will need to:
+
+ - update:
+ - ftrace_caller()
+ - ftrace_graph_call()
+ - ftrace_graph_caller()
+ - implement:
+ - ftrace_enable_ftrace_graph_caller()
+ - ftrace_disable_ftrace_graph_caller()
+
+<details to be filled>
+
+Quick notes:
+
+ - add a nop stub after the ftrace_call location named ftrace_graph_call;
+ stub needs to be large enough to support a call to ftrace_graph_caller()
+ - update ftrace_graph_caller() to work with being called by the new
+ ftrace_caller() since some semantics may have changed
+ - ftrace_enable_ftrace_graph_caller() will runtime patch the
+ ftrace_graph_call location with a call to ftrace_graph_caller()
+ - ftrace_disable_ftrace_graph_caller() will runtime patch the
+ ftrace_graph_call location with nops
diff --git a/Documentation/trace/ftrace-design.txt b/Documentation/trace/ftrace-design.txt
deleted file mode 100644
index a273dd0bbaaa..000000000000
--- a/Documentation/trace/ftrace-design.txt
+++ /dev/null
@@ -1,393 +0,0 @@
- function tracer guts
- ====================
- By Mike Frysinger
-
-Introduction
-------------
-
-Here we will cover the architecture pieces that the common function tracing
-code relies on for proper functioning. Things are broken down into increasing
-complexity so that you can start simple and at least get basic functionality.
-
-Note that this focuses on architecture implementation details only. If you
-want more explanation of a feature in terms of common code, review the common
-ftrace.txt file.
-
-Ideally, everyone who wishes to retain performance while supporting tracing in
-their kernel should make it all the way to dynamic ftrace support.
-
-
-Prerequisites
--------------
-
-Ftrace relies on these features being implemented:
- STACKTRACE_SUPPORT - implement save_stack_trace()
- TRACE_IRQFLAGS_SUPPORT - implement include/asm/irqflags.h
-
-
-HAVE_FUNCTION_TRACER
---------------------
-
-You will need to implement the mcount and the ftrace_stub functions.
-
-The exact mcount symbol name will depend on your toolchain. Some call it
-"mcount", "_mcount", or even "__mcount". You can probably figure it out by
-running something like:
- $ echo 'main(){}' | gcc -x c -S -o - - -pg | grep mcount
- call mcount
-We'll make the assumption below that the symbol is "mcount" just to keep things
-nice and simple in the examples.
-
-Keep in mind that the ABI that is in effect inside of the mcount function is
-*highly* architecture/toolchain specific. We cannot help you in this regard,
-sorry. Dig up some old documentation and/or find someone more familiar than
-you to bang ideas off of. Typically, register usage (argument/scratch/etc...)
-is a major issue at this point, especially in relation to the location of the
-mcount call (before/after function prologue). You might also want to look at
-how glibc has implemented the mcount function for your architecture. It might
-be (semi-)relevant.
-
-The mcount function should check the function pointer ftrace_trace_function
-to see if it is set to ftrace_stub. If it is, there is nothing for you to do,
-so return immediately. If it isn't, then call that function in the same way
-the mcount function normally calls __mcount_internal -- the first argument is
-the "frompc" while the second argument is the "selfpc" (adjusted to remove the
-size of the mcount call that is embedded in the function).
-
-For example, if the function foo() calls bar(), when the bar() function calls
-mcount(), the arguments mcount() will pass to the tracer are:
- "frompc" - the address bar() will use to return to foo()
- "selfpc" - the address bar() (with mcount() size adjustment)
-
-Also keep in mind that this mcount function will be called *a lot*, so
-optimizing for the default case of no tracer will help the smooth running of
-your system when tracing is disabled. So the start of the mcount function is
-typically the bare minimum with checking things before returning. That also
-means the code flow should usually be kept linear (i.e. no branching in the nop
-case). This is of course an optimization and not a hard requirement.
-
-Here is some pseudo code that should help (these functions should actually be
-implemented in assembly):
-
-void ftrace_stub(void)
-{
- return;
-}
-
-void mcount(void)
-{
- /* save any bare state needed in order to do initial checking */
-
- extern void (*ftrace_trace_function)(unsigned long, unsigned long);
- if (ftrace_trace_function != ftrace_stub)
- goto do_trace;
-
- /* restore any bare state */
-
- return;
-
-do_trace:
-
- /* save all state needed by the ABI (see paragraph above) */
-
- unsigned long frompc = ...;
- unsigned long selfpc = <return address> - MCOUNT_INSN_SIZE;
- ftrace_trace_function(frompc, selfpc);
-
- /* restore all state needed by the ABI */
-}
-
-Don't forget to export mcount for modules !
-extern void mcount(void);
-EXPORT_SYMBOL(mcount);
-
-
-HAVE_FUNCTION_GRAPH_TRACER
---------------------------
-
-Deep breath ... time to do some real work. Here you will need to update the
-mcount function to check ftrace graph function pointers, as well as implement
-some functions to save (hijack) and restore the return address.
-
-The mcount function should check the function pointers ftrace_graph_return
-(compare to ftrace_stub) and ftrace_graph_entry (compare to
-ftrace_graph_entry_stub). If either of those is not set to the relevant stub
-function, call the arch-specific function ftrace_graph_caller which in turn
-calls the arch-specific function prepare_ftrace_return. Neither of these
-function names is strictly required, but you should use them anyway to stay
-consistent across the architecture ports -- easier to compare & contrast
-things.
-
-The arguments to prepare_ftrace_return are slightly different than what are
-passed to ftrace_trace_function. The second argument "selfpc" is the same,
-but the first argument should be a pointer to the "frompc". Typically this is
-located on the stack. This allows the function to hijack the return address
-temporarily to have it point to the arch-specific function return_to_handler.
-That function will simply call the common ftrace_return_to_handler function and
-that will return the original return address with which you can return to the
-original call site.
-
-Here is the updated mcount pseudo code:
-void mcount(void)
-{
-...
- if (ftrace_trace_function != ftrace_stub)
- goto do_trace;
-
-+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-+ extern void (*ftrace_graph_return)(...);
-+ extern void (*ftrace_graph_entry)(...);
-+ if (ftrace_graph_return != ftrace_stub ||
-+ ftrace_graph_entry != ftrace_graph_entry_stub)
-+ ftrace_graph_caller();
-+#endif
-
- /* restore any bare state */
-...
-
-Here is the pseudo code for the new ftrace_graph_caller assembly function:
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-void ftrace_graph_caller(void)
-{
- /* save all state needed by the ABI */
-
- unsigned long *frompc = &...;
- unsigned long selfpc = <return address> - MCOUNT_INSN_SIZE;
- /* passing frame pointer up is optional -- see below */
- prepare_ftrace_return(frompc, selfpc, frame_pointer);
-
- /* restore all state needed by the ABI */
-}
-#endif
-
-For information on how to implement prepare_ftrace_return(), simply look at the
-x86 version (the frame pointer passing is optional; see the next section for
-more information). The only architecture-specific piece in it is the setup of
-the fault recovery table (the asm(...) code). The rest should be the same
-across architectures.
-
-Here is the pseudo code for the new return_to_handler assembly function. Note
-that the ABI that applies here is different from what applies to the mcount
-code. Since you are returning from a function (after the epilogue), you might
-be able to skimp on things saved/restored (usually just registers used to pass
-return values).
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-void return_to_handler(void)
-{
- /* save all state needed by the ABI (see paragraph above) */
-
- void (*original_return_point)(void) = ftrace_return_to_handler();
-
- /* restore all state needed by the ABI */
-
- /* this is usually either a return or a jump */
- original_return_point();
-}
-#endif
-
-
-HAVE_FUNCTION_GRAPH_FP_TEST
----------------------------
-
-An arch may pass in a unique value (frame pointer) to both the entering and
-exiting of a function. On exit, the value is compared and if it does not
-match, then it will panic the kernel. This is largely a sanity check for bad
-code generation with gcc. If gcc for your port sanely updates the frame
-pointer under different optimization levels, then ignore this option.
-
-However, adding support for it isn't terribly difficult. In your assembly code
-that calls prepare_ftrace_return(), pass the frame pointer as the 3rd argument.
-Then in the C version of that function, do what the x86 port does and pass it
-along to ftrace_push_return_trace() instead of a stub value of 0.
-
-Similarly, when you call ftrace_return_to_handler(), pass it the frame pointer.
-
-HAVE_FUNCTION_GRAPH_RET_ADDR_PTR
---------------------------------
-
-An arch may pass in a pointer to the return address on the stack. This
-prevents potential stack unwinding issues where the unwinder gets out of
-sync with ret_stack and the wrong addresses are reported by
-ftrace_graph_ret_addr().
-
-Adding support for it is easy: just define the macro in asm/ftrace.h and
-pass the return address pointer as the 'retp' argument to
-ftrace_push_return_trace().
-
-HAVE_FTRACE_NMI_ENTER
----------------------
-
-If you can't trace NMI functions, then skip this option.
-
-<details to be filled>
-
-
-HAVE_SYSCALL_TRACEPOINTS
-------------------------
-
-You need very few things to get the syscalls tracing in an arch.
-
-- Support HAVE_ARCH_TRACEHOOK (see arch/Kconfig).
-- Have a NR_syscalls variable in <asm/unistd.h> that provides the number
- of syscalls supported by the arch.
-- Support the TIF_SYSCALL_TRACEPOINT thread flags.
-- Put the trace_sys_enter() and trace_sys_exit() tracepoints calls from ptrace
- in the ptrace syscalls tracing path.
-- If the system call table on this arch is more complicated than a simple array
- of addresses of the system calls, implement an arch_syscall_addr to return
- the address of a given system call.
-- If the symbol names of the system calls do not match the function names on
- this arch, define ARCH_HAS_SYSCALL_MATCH_SYM_NAME in asm/ftrace.h and
- implement arch_syscall_match_sym_name with the appropriate logic to return
- true if the function name corresponds with the symbol name.
-- Tag this arch as HAVE_SYSCALL_TRACEPOINTS.
-
-
-HAVE_FTRACE_MCOUNT_RECORD
--------------------------
-
-See scripts/recordmcount.pl for more info. Just fill in the arch-specific
-details for how to locate the addresses of mcount call sites via objdump.
-This option doesn't make much sense without also implementing dynamic ftrace.
-
-
-HAVE_DYNAMIC_FTRACE
--------------------
-
-You will first need HAVE_FTRACE_MCOUNT_RECORD and HAVE_FUNCTION_TRACER, so
-scroll your reader back up if you got over eager.
-
-Once those are out of the way, you will need to implement:
- - asm/ftrace.h:
- - MCOUNT_ADDR
- - ftrace_call_adjust()
- - struct dyn_arch_ftrace{}
- - asm code:
- - mcount() (new stub)
- - ftrace_caller()
- - ftrace_call()
- - ftrace_stub()
- - C code:
- - ftrace_dyn_arch_init()
- - ftrace_make_nop()
- - ftrace_make_call()
- - ftrace_update_ftrace_func()
-
-First you will need to fill out some arch details in your asm/ftrace.h.
-
-Define MCOUNT_ADDR as the address of your mcount symbol similar to:
- #define MCOUNT_ADDR ((unsigned long)mcount)
-Since no one else will have a decl for that function, you will need to:
- extern void mcount(void);
-
-You will also need the helper function ftrace_call_adjust(). Most people
-will be able to stub it out like so:
- static inline unsigned long ftrace_call_adjust(unsigned long addr)
- {
- return addr;
- }
-<details to be filled>
-
-Lastly you will need the custom dyn_arch_ftrace structure. If you need
-some extra state when runtime patching arbitrary call sites, this is the
-place. For now though, create an empty struct:
- struct dyn_arch_ftrace {
- /* No extra data needed */
- };
-
-With the header out of the way, we can fill out the assembly code. While we
-did already create a mcount() function earlier, dynamic ftrace only wants a
-stub function. This is because the mcount() will only be used during boot
-and then all references to it will be patched out never to return. Instead,
-the guts of the old mcount() will be used to create a new ftrace_caller()
-function. Because the two are hard to merge, it will most likely be a lot
-easier to have two separate definitions split up by #ifdefs. Same goes for
-the ftrace_stub() as that will now be inlined in ftrace_caller().
-
-Before we get confused anymore, let's check out some pseudo code so you can
-implement your own stuff in assembly:
-
-void mcount(void)
-{
- return;
-}
-
-void ftrace_caller(void)
-{
- /* save all state needed by the ABI (see paragraph above) */
-
- unsigned long frompc = ...;
- unsigned long selfpc = <return address> - MCOUNT_INSN_SIZE;
-
-ftrace_call:
- ftrace_stub(frompc, selfpc);
-
- /* restore all state needed by the ABI */
-
-ftrace_stub:
- return;
-}
-
-This might look a little odd at first, but keep in mind that we will be runtime
-patching multiple things. First, only functions that we actually want to trace
-will be patched to call ftrace_caller(). Second, since we only have one tracer
-active at a time, we will patch the ftrace_caller() function itself to call the
-specific tracer in question. That is the point of the ftrace_call label.
-
-With that in mind, let's move on to the C code that will actually be doing the
-runtime patching. You'll need a little knowledge of your arch's opcodes in
-order to make it through the next section.
-
-Every arch has an init callback function. If you need to do something early on
-to initialize some state, this is the time to do that. Otherwise, this simple
-function below should be sufficient for most people:
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
-
-There are two functions that are used to do runtime patching of arbitrary
-functions. The first is used to turn the mcount call site into a nop (which
-is what helps us retain runtime performance when not tracing). The second is
-used to turn the mcount call site into a call to an arbitrary location (but
-typically that is ftracer_caller()). See the general function definition in
-linux/ftrace.h for the functions:
- ftrace_make_nop()
- ftrace_make_call()
-The rec->ip value is the address of the mcount call site that was collected
-by the scripts/recordmcount.pl during build time.
-
-The last function is used to do runtime patching of the active tracer. This
-will be modifying the assembly code at the location of the ftrace_call symbol
-inside of the ftrace_caller() function. So you should have sufficient padding
-at that location to support the new function calls you'll be inserting. Some
-people will be using a "call" type instruction while others will be using a
-"branch" type instruction. Specifically, the function is:
- ftrace_update_ftrace_func()
-
-
-HAVE_DYNAMIC_FTRACE + HAVE_FUNCTION_GRAPH_TRACER
-------------------------------------------------
-
-The function grapher needs a few tweaks in order to work with dynamic ftrace.
-Basically, you will need to:
- - update:
- - ftrace_caller()
- - ftrace_graph_call()
- - ftrace_graph_caller()
- - implement:
- - ftrace_enable_ftrace_graph_caller()
- - ftrace_disable_ftrace_graph_caller()
-
-<details to be filled>
-Quick notes:
- - add a nop stub after the ftrace_call location named ftrace_graph_call;
- stub needs to be large enough to support a call to ftrace_graph_caller()
- - update ftrace_graph_caller() to work with being called by the new
- ftrace_caller() since some semantics may have changed
- - ftrace_enable_ftrace_graph_caller() will runtime patch the
- ftrace_graph_call location with a call to ftrace_graph_caller()
- - ftrace_disable_ftrace_graph_caller() will runtime patch the
- ftrace_graph_call location with nops
diff --git a/Documentation/trace/ftrace-uses.rst b/Documentation/trace/ftrace-uses.rst
index 3aed560a12ee..998a60a93015 100644
--- a/Documentation/trace/ftrace-uses.rst
+++ b/Documentation/trace/ftrace-uses.rst
@@ -21,13 +21,14 @@ how to use ftrace to implement your own function callbacks.
The ftrace context
==================
+.. warning::
-WARNING: The ability to add a callback to almost any function within the
-kernel comes with risks. A callback can be called from any context
-(normal, softirq, irq, and NMI). Callbacks can also be called just before
-going to idle, during CPU bring up and takedown, or going to user space.
-This requires extra care to what can be done inside a callback. A callback
-can be called outside the protective scope of RCU.
+ The ability to add a callback to almost any function within the
+ kernel comes with risks. A callback can be called from any context
+ (normal, softirq, irq, and NMI). Callbacks can also be called just before
+ going to idle, during CPU bring up and takedown, or going to user space.
+ This requires extra care to what can be done inside a callback. A callback
+ can be called outside the protective scope of RCU.
The ftrace infrastructure has some protections agains recursions and RCU
but one must still be very careful how they use the callbacks.
@@ -54,15 +55,15 @@ an ftrace_ops with ftrace:
Both .flags and .private are optional. Only .func is required.
-To enable tracing call::
+To enable tracing call:
.. c:function:: register_ftrace_function(&ops);
-To disable tracing call::
+To disable tracing call:
.. c:function:: unregister_ftrace_function(&ops);
-The above is defined by including the header::
+The above is defined by including the header:
.. c:function:: #include <linux/ftrace.h>
@@ -200,7 +201,7 @@ match a specific pattern.
See Filter Commands in :file:`Documentation/trace/ftrace.txt`.
-To just trace the schedule function::
+To just trace the schedule function:
.. code-block:: c
@@ -210,7 +211,7 @@ To add more functions, call the ftrace_set_filter() more than once with the
@reset parameter set to zero. To remove the current filter set and replace it
with new functions defined by @buf, have @reset be non-zero.
-To remove all the filtered functions and trace all functions::
+To remove all the filtered functions and trace all functions:
.. code-block:: c
diff --git a/Documentation/trace/ftrace.rst b/Documentation/trace/ftrace.rst
new file mode 100644
index 000000000000..e45f0786f3f9
--- /dev/null
+++ b/Documentation/trace/ftrace.rst
@@ -0,0 +1,3348 @@
+========================
+ftrace - Function Tracer
+========================
+
+Copyright 2008 Red Hat Inc.
+
+:Author: Steven Rostedt <srostedt@redhat.com>
+:License: The GNU Free Documentation License, Version 1.2
+ (dual licensed under the GPL v2)
+:Original Reviewers: Elias Oltmanns, Randy Dunlap, Andrew Morton,
+ John Kacur, and David Teigland.
+
+- Written for: 2.6.28-rc2
+- Updated for: 3.10
+- Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
+- Converted to rst format - Changbin Du <changbin.du@intel.com>
+
+Introduction
+------------
+
+Ftrace is an internal tracer designed to help out developers and
+designers of systems to find what is going on inside the kernel.
+It can be used for debugging or analyzing latencies and
+performance issues that take place outside of user-space.
+
+Although ftrace is typically considered the function tracer, it
+is really a frame work of several assorted tracing utilities.
+There's latency tracing to examine what occurs between interrupts
+disabled and enabled, as well as for preemption and from a time
+a task is woken to the task is actually scheduled in.
+
+One of the most common uses of ftrace is the event tracing.
+Through out the kernel is hundreds of static event points that
+can be enabled via the tracefs file system to see what is
+going on in certain parts of the kernel.
+
+See events.txt for more information.
+
+
+Implementation Details
+----------------------
+
+See :doc:`ftrace-design` for details for arch porters and such.
+
+
+The File System
+---------------
+
+Ftrace uses the tracefs file system to hold the control files as
+well as the files to display output.
+
+When tracefs is configured into the kernel (which selecting any ftrace
+option will do) the directory /sys/kernel/tracing will be created. To mount
+this directory, you can add to your /etc/fstab file::
+
+ tracefs /sys/kernel/tracing tracefs defaults 0 0
+
+Or you can mount it at run time with::
+
+ mount -t tracefs nodev /sys/kernel/tracing
+
+For quicker access to that directory you may want to make a soft link to
+it::
+
+ ln -s /sys/kernel/tracing /tracing
+
+.. attention::
+
+ Before 4.1, all ftrace tracing control files were within the debugfs
+ file system, which is typically located at /sys/kernel/debug/tracing.
+ For backward compatibility, when mounting the debugfs file system,
+ the tracefs file system will be automatically mounted at:
+
+ /sys/kernel/debug/tracing
+
+ All files located in the tracefs file system will be located in that
+ debugfs file system directory as well.
+
+.. attention::
+
+ Any selected ftrace option will also create the tracefs file system.
+ The rest of the document will assume that you are in the ftrace directory
+ (cd /sys/kernel/tracing) and will only concentrate on the files within that
+ directory and not distract from the content with the extended
+ "/sys/kernel/tracing" path name.
+
+That's it! (assuming that you have ftrace configured into your kernel)
+
+After mounting tracefs you will have access to the control and output files
+of ftrace. Here is a list of some of the key files:
+
+
+ Note: all time values are in microseconds.
+
+ current_tracer:
+
+ This is used to set or display the current tracer
+ that is configured.
+
+ available_tracers:
+
+ This holds the different types of tracers that
+ have been compiled into the kernel. The
+ tracers listed here can be configured by
+ echoing their name into current_tracer.
+
+ tracing_on:
+
+ This sets or displays whether writing to the trace
+ ring buffer is enabled. Echo 0 into this file to disable
+ the tracer or 1 to enable it. Note, this only disables
+ writing to the ring buffer, the tracing overhead may
+ still be occurring.
+
+ The kernel function tracing_off() can be used within the
+ kernel to disable writing to the ring buffer, which will
+ set this file to "0". User space can re-enable tracing by
+ echoing "1" into the file.
+
+ Note, the function and event trigger "traceoff" will also
+ set this file to zero and stop tracing. Which can also
+ be re-enabled by user space using this file.
+
+ trace:
+
+ This file holds the output of the trace in a human
+ readable format (described below). Note, tracing is temporarily
+ disabled while this file is being read (opened).
+
+ trace_pipe:
+
+ The output is the same as the "trace" file but this
+ file is meant to be streamed with live tracing.
+ Reads from this file will block until new data is
+ retrieved. Unlike the "trace" file, this file is a
+ consumer. This means reading from this file causes
+ sequential reads to display more current data. Once
+ data is read from this file, it is consumed, and
+ will not be read again with a sequential read. The
+ "trace" file is static, and if the tracer is not
+ adding more data, it will display the same
+ information every time it is read. This file will not
+ disable tracing while being read.
+
+ trace_options:
+
+ This file lets the user control the amount of data
+ that is displayed in one of the above output
+ files. Options also exist to modify how a tracer
+ or events work (stack traces, timestamps, etc).
+
+ options:
+
+ This is a directory that has a file for every available
+ trace option (also in trace_options). Options may also be set
+ or cleared by writing a "1" or "0" respectively into the
+ corresponding file with the option name.
+
+ tracing_max_latency:
+
+ Some of the tracers record the max latency.
+ For example, the maximum time that interrupts are disabled.
+ The maximum time is saved in this file. The max trace will also be
+ stored, and displayed by "trace". A new max trace will only be
+ recorded if the latency is greater than the value in this file
+ (in microseconds).
+
+ By echoing in a time into this file, no latency will be recorded
+ unless it is greater than the time in this file.
+
+ tracing_thresh:
+
+ Some latency tracers will record a trace whenever the
+ latency is greater than the number in this file.
+ Only active when the file contains a number greater than 0.
+ (in microseconds)
+
+ buffer_size_kb:
+
+ This sets or displays the number of kilobytes each CPU
+ buffer holds. By default, the trace buffers are the same size
+ for each CPU. The displayed number is the size of the
+ CPU buffer and not total size of all buffers. The
+ trace buffers are allocated in pages (blocks of memory
+ that the kernel uses for allocation, usually 4 KB in size).
+ If the last page allocated has room for more bytes
+ than requested, the rest of the page will be used,
+ making the actual allocation bigger than requested or shown.
+ ( Note, the size may not be a multiple of the page size
+ due to buffer management meta-data. )
+
+ Buffer sizes for individual CPUs may vary
+ (see "per_cpu/cpu0/buffer_size_kb" below), and if they do
+ this file will show "X".
+
+ buffer_total_size_kb:
+
+ This displays the total combined size of all the trace buffers.
+
+ free_buffer:
+
+ If a process is performing tracing, and the ring buffer should be
+ shrunk "freed" when the process is finished, even if it were to be
+ killed by a signal, this file can be used for that purpose. On close
+ of this file, the ring buffer will be resized to its minimum size.
+ Having a process that is tracing also open this file, when the process
+ exits its file descriptor for this file will be closed, and in doing so,
+ the ring buffer will be "freed".
+
+ It may also stop tracing if disable_on_free option is set.
+
+ tracing_cpumask:
+
+ This is a mask that lets the user only trace on specified CPUs.
+ The format is a hex string representing the CPUs.
+
+ set_ftrace_filter:
+
+ When dynamic ftrace is configured in (see the
+ section below "dynamic ftrace"), the code is dynamically
+ modified (code text rewrite) to disable calling of the
+ function profiler (mcount). This lets tracing be configured
+ in with practically no overhead in performance. This also
+ has a side effect of enabling or disabling specific functions
+ to be traced. Echoing names of functions into this file
+ will limit the trace to only those functions.
+
+ The functions listed in "available_filter_functions" are what
+ can be written into this file.
+
+ This interface also allows for commands to be used. See the
+ "Filter commands" section for more details.
+
+ set_ftrace_notrace:
+
+ This has an effect opposite to that of
+ set_ftrace_filter. Any function that is added here will not
+ be traced. If a function exists in both set_ftrace_filter
+ and set_ftrace_notrace, the function will _not_ be traced.
+
+ set_ftrace_pid:
+
+ Have the function tracer only trace the threads whose PID are
+ listed in this file.
+
+ If the "function-fork" option is set, then when a task whose
+ PID is listed in this file forks, the child's PID will
+ automatically be added to this file, and the child will be
+ traced by the function tracer as well. This option will also
+ cause PIDs of tasks that exit to be removed from the file.
+
+ set_event_pid:
+
+ Have the events only trace a task with a PID listed in this file.
+ Note, sched_switch and sched_wake_up will also trace events
+ listed in this file.
+
+ To have the PIDs of children of tasks with their PID in this file
+ added on fork, enable the "event-fork" option. That option will also
+ cause the PIDs of tasks to be removed from this file when the task
+ exits.
+
+ set_graph_function:
+
+ Functions listed in this file will cause the function graph
+ tracer to only trace these functions and the functions that
+ they call. (See the section "dynamic ftrace" for more details).
+
+ set_graph_notrace:
+
+ Similar to set_graph_function, but will disable function graph
+ tracing when the function is hit until it exits the function.
+ This makes it possible to ignore tracing functions that are called
+ by a specific function.
+
+ available_filter_functions:
+
+ This lists the functions that ftrace has processed and can trace.
+ These are the function names that you can pass to
+ "set_ftrace_filter" or "set_ftrace_notrace".
+ (See the section "dynamic ftrace" below for more details.)
+
+ dyn_ftrace_total_info:
+
+ This file is for debugging purposes. The number of functions that
+ have been converted to nops and are available to be traced.
+
+ enabled_functions:
+
+ This file is more for debugging ftrace, but can also be useful
+ in seeing if any function has a callback attached to it.
+ Not only does the trace infrastructure use ftrace function
+ trace utility, but other subsystems might too. This file
+ displays all functions that have a callback attached to them
+ as well as the number of callbacks that have been attached.
+ Note, a callback may also call multiple functions which will
+ not be listed in this count.
+
+ If the callback registered to be traced by a function with
+ the "save regs" attribute (thus even more overhead), a 'R'
+ will be displayed on the same line as the function that
+ is returning registers.
+
+ If the callback registered to be traced by a function with
+ the "ip modify" attribute (thus the regs->ip can be changed),
+ an 'I' will be displayed on the same line as the function that
+ can be overridden.
+
+ If the architecture supports it, it will also show what callback
+ is being directly called by the function. If the count is greater
+ than 1 it most likely will be ftrace_ops_list_func().
+
+ If the callback of the function jumps to a trampoline that is
+ specific to a the callback and not the standard trampoline,
+ its address will be printed as well as the function that the
+ trampoline calls.
+
+ function_profile_enabled:
+
+ When set it will enable all functions with either the function
+ tracer, or if configured, the function graph tracer. It will
+ keep a histogram of the number of functions that were called
+ and if the function graph tracer was configured, it will also keep
+ track of the time spent in those functions. The histogram
+ content can be displayed in the files:
+
+ trace_stats/function<cpu> ( function0, function1, etc).
+
+ trace_stats:
+
+ A directory that holds different tracing stats.
+
+ kprobe_events:
+
+ Enable dynamic trace points. See kprobetrace.txt.
+
+ kprobe_profile:
+
+ Dynamic trace points stats. See kprobetrace.txt.
+
+ max_graph_depth:
+
+ Used with the function graph tracer. This is the max depth
+ it will trace into a function. Setting this to a value of
+ one will show only the first kernel function that is called
+ from user space.
+
+ printk_formats:
+
+ This is for tools that read the raw format files. If an event in
+ the ring buffer references a string, only a pointer to the string
+ is recorded into the buffer and not the string itself. This prevents
+ tools from knowing what that string was. This file displays the string
+ and address for the string allowing tools to map the pointers to what
+ the strings were.
+
+ saved_cmdlines:
+
+ Only the pid of the task is recorded in a trace event unless
+ the event specifically saves the task comm as well. Ftrace
+ makes a cache of pid mappings to comms to try to display
+ comms for events. If a pid for a comm is not listed, then
+ "<...>" is displayed in the output.
+
+ If the option "record-cmd" is set to "0", then comms of tasks
+ will not be saved during recording. By default, it is enabled.
+
+ saved_cmdlines_size:
+
+ By default, 128 comms are saved (see "saved_cmdlines" above). To
+ increase or decrease the amount of comms that are cached, echo
+ in a the number of comms to cache, into this file.
+
+ saved_tgids:
+
+ If the option "record-tgid" is set, on each scheduling context switch
+ the Task Group ID of a task is saved in a table mapping the PID of
+ the thread to its TGID. By default, the "record-tgid" option is
+ disabled.
+
+ snapshot:
+
+ This displays the "snapshot" buffer and also lets the user
+ take a snapshot of the current running trace.
+ See the "Snapshot" section below for more details.
+
+ stack_max_size:
+
+ When the stack tracer is activated, this will display the
+ maximum stack size it has encountered.
+ See the "Stack Trace" section below.
+
+ stack_trace:
+
+ This displays the stack back trace of the largest stack
+ that was encountered when the stack tracer is activated.
+ See the "Stack Trace" section below.
+
+ stack_trace_filter:
+
+ This is similar to "set_ftrace_filter" but it limits what
+ functions the stack tracer will check.
+
+ trace_clock:
+
+ Whenever an event is recorded into the ring buffer, a
+ "timestamp" is added. This stamp comes from a specified
+ clock. By default, ftrace uses the "local" clock. This
+ clock is very fast and strictly per cpu, but on some
+ systems it may not be monotonic with respect to other
+ CPUs. In other words, the local clocks may not be in sync
+ with local clocks on other CPUs.
+
+ Usual clocks for tracing::
+
+ # cat trace_clock
+ [local] global counter x86-tsc
+
+ The clock with the square brackets around it is the one in effect.
+
+ local:
+ Default clock, but may not be in sync across CPUs
+
+ global:
+ This clock is in sync with all CPUs but may
+ be a bit slower than the local clock.
+
+ counter:
+ This is not a clock at all, but literally an atomic
+ counter. It counts up one by one, but is in sync
+ with all CPUs. This is useful when you need to
+ know exactly the order events occurred with respect to
+ each other on different CPUs.
+
+ uptime:
+ This uses the jiffies counter and the time stamp
+ is relative to the time since boot up.
+
+ perf:
+ This makes ftrace use the same clock that perf uses.
+ Eventually perf will be able to read ftrace buffers
+ and this will help out in interleaving the data.
+
+ x86-tsc:
+ Architectures may define their own clocks. For
+ example, x86 uses its own TSC cycle clock here.
+
+ ppc-tb:
+ This uses the powerpc timebase register value.
+ This is in sync across CPUs and can also be used
+ to correlate events across hypervisor/guest if
+ tb_offset is known.
+
+ mono:
+ This uses the fast monotonic clock (CLOCK_MONOTONIC)
+ which is monotonic and is subject to NTP rate adjustments.
+
+ mono_raw:
+ This is the raw monotonic clock (CLOCK_MONOTONIC_RAW)
+ which is montonic but is not subject to any rate adjustments
+ and ticks at the same rate as the hardware clocksource.
+
+ boot:
+ Same as mono. Used to be a separate clock which accounted
+ for the time spent in suspend while CLOCK_MONOTONIC did
+ not.
+
+ To set a clock, simply echo the clock name into this file::
+
+ # echo global > trace_clock
+
+ trace_marker:
+
+ This is a very useful file for synchronizing user space
+ with events happening in the kernel. Writing strings into
+ this file will be written into the ftrace buffer.
+
+ It is useful in applications to open this file at the start
+ of the application and just reference the file descriptor
+ for the file::
+
+ void trace_write(const char *fmt, ...)
+ {
+ va_list ap;
+ char buf[256];
+ int n;
+
+ if (trace_fd < 0)
+ return;
+
+ va_start(ap, fmt);
+ n = vsnprintf(buf, 256, fmt, ap);
+ va_end(ap);
+
+ write(trace_fd, buf, n);
+ }
+
+ start::
+
+ trace_fd = open("trace_marker", WR_ONLY);
+
+ trace_marker_raw:
+
+ This is similar to trace_marker above, but is meant for for binary data
+ to be written to it, where a tool can be used to parse the data
+ from trace_pipe_raw.
+
+ uprobe_events:
+
+ Add dynamic tracepoints in programs.
+ See uprobetracer.txt
+
+ uprobe_profile:
+
+ Uprobe statistics. See uprobetrace.txt
+
+ instances:
+
+ This is a way to make multiple trace buffers where different
+ events can be recorded in different buffers.
+ See "Instances" section below.
+
+ events:
+
+ This is the trace event directory. It holds event tracepoints
+ (also known as static tracepoints) that have been compiled
+ into the kernel. It shows what event tracepoints exist
+ and how they are grouped by system. There are "enable"
+ files at various levels that can enable the tracepoints
+ when a "1" is written to them.
+
+ See events.txt for more information.
+
+ set_event:
+
+ By echoing in the event into this file, will enable that event.
+
+ See events.txt for more information.
+
+ available_events:
+
+ A list of events that can be enabled in tracing.
+
+ See events.txt for more information.
+
+ timestamp_mode:
+
+ Certain tracers may change the timestamp mode used when
+ logging trace events into the event buffer. Events with
+ different modes can coexist within a buffer but the mode in
+ effect when an event is logged determines which timestamp mode
+ is used for that event. The default timestamp mode is
+ 'delta'.
+
+ Usual timestamp modes for tracing:
+
+ # cat timestamp_mode
+ [delta] absolute
+
+ The timestamp mode with the square brackets around it is the
+ one in effect.
+
+ delta: Default timestamp mode - timestamp is a delta against
+ a per-buffer timestamp.
+
+ absolute: The timestamp is a full timestamp, not a delta
+ against some other value. As such it takes up more
+ space and is less efficient.
+
+ hwlat_detector:
+
+ Directory for the Hardware Latency Detector.
+ See "Hardware Latency Detector" section below.
+
+ per_cpu:
+
+ This is a directory that contains the trace per_cpu information.
+
+ per_cpu/cpu0/buffer_size_kb:
+
+ The ftrace buffer is defined per_cpu. That is, there's a separate
+ buffer for each CPU to allow writes to be done atomically,
+ and free from cache bouncing. These buffers may have different
+ size buffers. This file is similar to the buffer_size_kb
+ file, but it only displays or sets the buffer size for the
+ specific CPU. (here cpu0).
+
+ per_cpu/cpu0/trace:
+
+ This is similar to the "trace" file, but it will only display
+ the data specific for the CPU. If written to, it only clears
+ the specific CPU buffer.
+
+ per_cpu/cpu0/trace_pipe
+
+ This is similar to the "trace_pipe" file, and is a consuming
+ read, but it will only display (and consume) the data specific
+ for the CPU.
+
+ per_cpu/cpu0/trace_pipe_raw
+
+ For tools that can parse the ftrace ring buffer binary format,
+ the trace_pipe_raw file can be used to extract the data
+ from the ring buffer directly. With the use of the splice()
+ system call, the buffer data can be quickly transferred to
+ a file or to the network where a server is collecting the
+ data.
+
+ Like trace_pipe, this is a consuming reader, where multiple
+ reads will always produce different data.
+
+ per_cpu/cpu0/snapshot:
+
+ This is similar to the main "snapshot" file, but will only
+ snapshot the current CPU (if supported). It only displays
+ the content of the snapshot for a given CPU, and if
+ written to, only clears this CPU buffer.
+
+ per_cpu/cpu0/snapshot_raw:
+
+ Similar to the trace_pipe_raw, but will read the binary format
+ from the snapshot buffer for the given CPU.
+
+ per_cpu/cpu0/stats:
+
+ This displays certain stats about the ring buffer:
+
+ entries:
+ The number of events that are still in the buffer.
+
+ overrun:
+ The number of lost events due to overwriting when
+ the buffer was full.
+
+ commit overrun:
+ Should always be zero.
+ This gets set if so many events happened within a nested
+ event (ring buffer is re-entrant), that it fills the
+ buffer and starts dropping events.
+
+ bytes:
+ Bytes actually read (not overwritten).
+
+ oldest event ts:
+ The oldest timestamp in the buffer
+
+ now ts:
+ The current timestamp
+
+ dropped events:
+ Events lost due to overwrite option being off.
+
+ read events:
+ The number of events read.
+
+The Tracers
+-----------
+
+Here is the list of current tracers that may be configured.
+
+ "function"
+
+ Function call tracer to trace all kernel functions.
+
+ "function_graph"
+
+ Similar to the function tracer except that the
+ function tracer probes the functions on their entry
+ whereas the function graph tracer traces on both entry
+ and exit of the functions. It then provides the ability
+ to draw a graph of function calls similar to C code
+ source.
+
+ "blk"
+
+ The block tracer. The tracer used by the blktrace user
+ application.
+
+ "hwlat"
+
+ The Hardware Latency tracer is used to detect if the hardware
+ produces any latency. See "Hardware Latency Detector" section
+ below.
+
+ "irqsoff"
+
+ Traces the areas that disable interrupts and saves
+ the trace with the longest max latency.
+ See tracing_max_latency. When a new max is recorded,
+ it replaces the old trace. It is best to view this
+ trace with the latency-format option enabled, which
+ happens automatically when the tracer is selected.
+
+ "preemptoff"
+
+ Similar to irqsoff but traces and records the amount of
+ time for which preemption is disabled.
+
+ "preemptirqsoff"
+
+ Similar to irqsoff and preemptoff, but traces and
+ records the largest time for which irqs and/or preemption
+ is disabled.
+
+ "wakeup"
+
+ Traces and records the max latency that it takes for
+ the highest priority task to get scheduled after
+ it has been woken up.
+ Traces all tasks as an average developer would expect.
+
+ "wakeup_rt"
+
+ Traces and records the max latency that it takes for just
+ RT tasks (as the current "wakeup" does). This is useful
+ for those interested in wake up timings of RT tasks.
+
+ "wakeup_dl"
+
+ Traces and records the max latency that it takes for
+ a SCHED_DEADLINE task to be woken (as the "wakeup" and
+ "wakeup_rt" does).
+
+ "mmiotrace"
+
+ A special tracer that is used to trace binary module.
+ It will trace all the calls that a module makes to the
+ hardware. Everything it writes and reads from the I/O
+ as well.
+
+ "branch"
+
+ This tracer can be configured when tracing likely/unlikely
+ calls within the kernel. It will trace when a likely and
+ unlikely branch is hit and if it was correct in its prediction
+ of being correct.
+
+ "nop"
+
+ This is the "trace nothing" tracer. To remove all
+ tracers from tracing simply echo "nop" into
+ current_tracer.
+
+
+Examples of using the tracer
+----------------------------
+
+Here are typical examples of using the tracers when controlling
+them only with the tracefs interface (without using any
+user-land utilities).
+
+Output format:
+--------------
+
+Here is an example of the output format of the file "trace"::
+
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 140080/250280 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ bash-1977 [000] .... 17284.993652: sys_close <-system_call_fastpath
+ bash-1977 [000] .... 17284.993653: __close_fd <-sys_close
+ bash-1977 [000] .... 17284.993653: _raw_spin_lock <-__close_fd
+ sshd-1974 [003] .... 17284.993653: __srcu_read_unlock <-fsnotify
+ bash-1977 [000] .... 17284.993654: add_preempt_count <-_raw_spin_lock
+ bash-1977 [000] ...1 17284.993655: _raw_spin_unlock <-__close_fd
+ bash-1977 [000] ...1 17284.993656: sub_preempt_count <-_raw_spin_unlock
+ bash-1977 [000] .... 17284.993657: filp_close <-__close_fd
+ bash-1977 [000] .... 17284.993657: dnotify_flush <-filp_close
+ sshd-1974 [003] .... 17284.993658: sys_select <-system_call_fastpath
+ ....
+
+A header is printed with the tracer name that is represented by
+the trace. In this case the tracer is "function". Then it shows the
+number of events in the buffer as well as the total number of entries
+that were written. The difference is the number of entries that were
+lost due to the buffer filling up (250280 - 140080 = 110200 events
+lost).
+
+The header explains the content of the events. Task name "bash", the task
+PID "1977", the CPU that it was running on "000", the latency format
+(explained below), the timestamp in <secs>.<usecs> format, the
+function name that was traced "sys_close" and the parent function that
+called this function "system_call_fastpath". The timestamp is the time
+at which the function was entered.
+
+Latency trace format
+--------------------
+
+When the latency-format option is enabled or when one of the latency
+tracers is set, the trace file gives somewhat more information to see
+why a latency happened. Here is a typical trace::
+
+ # tracer: irqsoff
+ #
+ # irqsoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 259 us, #4/4, CPU#2 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: ps-6143 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: __lock_task_sighand
+ # => ended at: _raw_spin_unlock_irqrestore
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ ps-6143 2d... 0us!: trace_hardirqs_off <-__lock_task_sighand
+ ps-6143 2d..1 259us+: trace_hardirqs_on <-_raw_spin_unlock_irqrestore
+ ps-6143 2d..1 263us+: time_hardirqs_on <-_raw_spin_unlock_irqrestore
+ ps-6143 2d..1 306us : <stack trace>
+ => trace_hardirqs_on_caller
+ => trace_hardirqs_on
+ => _raw_spin_unlock_irqrestore
+ => do_task_stat
+ => proc_tgid_stat
+ => proc_single_show
+ => seq_read
+ => vfs_read
+ => sys_read
+ => system_call_fastpath
+
+
+This shows that the current tracer is "irqsoff" tracing the time
+for which interrupts were disabled. It gives the trace version (which
+never changes) and the version of the kernel upon which this was executed on
+(3.8). Then it displays the max latency in microseconds (259 us). The number
+of trace entries displayed and the total number (both are four: #4/4).
+VP, KP, SP, and HP are always zero and are reserved for later use.
+#P is the number of online CPUs (#P:4).
+
+The task is the process that was running when the latency
+occurred. (ps pid: 6143).
+
+The start and stop (the functions in which the interrupts were
+disabled and enabled respectively) that caused the latencies:
+
+ - __lock_task_sighand is where the interrupts were disabled.
+ - _raw_spin_unlock_irqrestore is where they were enabled again.
+
+The next lines after the header are the trace itself. The header
+explains which is which.
+
+ cmd: The name of the process in the trace.
+
+ pid: The PID of that process.
+
+ CPU#: The CPU which the process was running on.
+
+ irqs-off: 'd' interrupts are disabled. '.' otherwise.
+ .. caution:: If the architecture does not support a way to
+ read the irq flags variable, an 'X' will always
+ be printed here.
+
+ need-resched:
+ - 'N' both TIF_NEED_RESCHED and PREEMPT_NEED_RESCHED is set,
+ - 'n' only TIF_NEED_RESCHED is set,
+ - 'p' only PREEMPT_NEED_RESCHED is set,
+ - '.' otherwise.
+
+ hardirq/softirq:
+ - 'Z' - NMI occurred inside a hardirq
+ - 'z' - NMI is running
+ - 'H' - hard irq occurred inside a softirq.
+ - 'h' - hard irq is running
+ - 's' - soft irq is running
+ - '.' - normal context.
+
+ preempt-depth: The level of preempt_disabled
+
+The above is mostly meaningful for kernel developers.
+
+ time:
+ When the latency-format option is enabled, the trace file
+ output includes a timestamp relative to the start of the
+ trace. This differs from the output when latency-format
+ is disabled, which includes an absolute timestamp.
+
+ delay:
+ This is just to help catch your eye a bit better. And
+ needs to be fixed to be only relative to the same CPU.
+ The marks are determined by the difference between this
+ current trace and the next trace.
+
+ - '$' - greater than 1 second
+ - '@' - greater than 100 milisecond
+ - '*' - greater than 10 milisecond
+ - '#' - greater than 1000 microsecond
+ - '!' - greater than 100 microsecond
+ - '+' - greater than 10 microsecond
+ - ' ' - less than or equal to 10 microsecond.
+
+ The rest is the same as the 'trace' file.
+
+ Note, the latency tracers will usually end with a back trace
+ to easily find where the latency occurred.
+
+trace_options
+-------------
+
+The trace_options file (or the options directory) is used to control
+what gets printed in the trace output, or manipulate the tracers.
+To see what is available, simply cat the file::
+
+ cat trace_options
+ print-parent
+ nosym-offset
+ nosym-addr
+ noverbose
+ noraw
+ nohex
+ nobin
+ noblock
+ trace_printk
+ annotate
+ nouserstacktrace
+ nosym-userobj
+ noprintk-msg-only
+ context-info
+ nolatency-format
+ record-cmd
+ norecord-tgid
+ overwrite
+ nodisable_on_free
+ irq-info
+ markers
+ noevent-fork
+ function-trace
+ nofunction-fork
+ nodisplay-graph
+ nostacktrace
+ nobranch
+
+To disable one of the options, echo in the option prepended with
+"no"::
+
+ echo noprint-parent > trace_options
+
+To enable an option, leave off the "no"::
+
+ echo sym-offset > trace_options
+
+Here are the available options:
+
+ print-parent
+ On function traces, display the calling (parent)
+ function as well as the function being traced.
+ ::
+
+ print-parent:
+ bash-4000 [01] 1477.606694: simple_strtoul <-kstrtoul
+
+ noprint-parent:
+ bash-4000 [01] 1477.606694: simple_strtoul
+
+
+ sym-offset
+ Display not only the function name, but also the
+ offset in the function. For example, instead of
+ seeing just "ktime_get", you will see
+ "ktime_get+0xb/0x20".
+ ::
+
+ sym-offset:
+ bash-4000 [01] 1477.606694: simple_strtoul+0x6/0xa0
+
+ sym-addr
+ This will also display the function address as well
+ as the function name.
+ ::
+
+ sym-addr:
+ bash-4000 [01] 1477.606694: simple_strtoul <c0339346>
+
+ verbose
+ This deals with the trace file when the
+ latency-format option is enabled.
+ ::
+
+ bash 4000 1 0 00000000 00010a95 [58127d26] 1720.415ms \
+ (+0.000ms): simple_strtoul (kstrtoul)
+
+ raw
+ This will display raw numbers. This option is best for
+ use with user applications that can translate the raw
+ numbers better than having it done in the kernel.
+
+ hex
+ Similar to raw, but the numbers will be in a hexadecimal format.
+
+ bin
+ This will print out the formats in raw binary.
+
+ block
+ When set, reading trace_pipe will not block when polled.
+
+ trace_printk
+ Can disable trace_printk() from writing into the buffer.
+
+ annotate
+ It is sometimes confusing when the CPU buffers are full
+ and one CPU buffer had a lot of events recently, thus
+ a shorter time frame, were another CPU may have only had
+ a few events, which lets it have older events. When
+ the trace is reported, it shows the oldest events first,
+ and it may look like only one CPU ran (the one with the
+ oldest events). When the annotate option is set, it will
+ display when a new CPU buffer started::
+
+ <idle>-0 [001] dNs4 21169.031481: wake_up_idle_cpu <-add_timer_on
+ <idle>-0 [001] dNs4 21169.031482: _raw_spin_unlock_irqrestore <-add_timer_on
+ <idle>-0 [001] .Ns4 21169.031484: sub_preempt_count <-_raw_spin_unlock_irqrestore
+ ##### CPU 2 buffer started ####
+ <idle>-0 [002] .N.1 21169.031484: rcu_idle_exit <-cpu_idle
+ <idle>-0 [001] .Ns3 21169.031484: _raw_spin_unlock <-clocksource_watchdog
+ <idle>-0 [001] .Ns3 21169.031485: sub_preempt_count <-_raw_spin_unlock
+
+ userstacktrace
+ This option changes the trace. It records a
+ stacktrace of the current user space thread after
+ each trace event.
+
+ sym-userobj
+ when user stacktrace are enabled, look up which
+ object the address belongs to, and print a
+ relative address. This is especially useful when
+ ASLR is on, otherwise you don't get a chance to
+ resolve the address to object/file/line after
+ the app is no longer running
+
+ The lookup is performed when you read
+ trace,trace_pipe. Example::
+
+ a.out-1623 [000] 40874.465068: /root/a.out[+0x480] <-/root/a.out[+0
+ x494] <- /root/a.out[+0x4a8] <- /lib/libc-2.7.so[+0x1e1a6]
+
+
+ printk-msg-only
+ When set, trace_printk()s will only show the format
+ and not their parameters (if trace_bprintk() or
+ trace_bputs() was used to save the trace_printk()).
+
+ context-info
+ Show only the event data. Hides the comm, PID,
+ timestamp, CPU, and other useful data.
+
+ latency-format
+ This option changes the trace output. When it is enabled,
+ the trace displays additional information about the
+ latency, as described in "Latency trace format".
+
+ record-cmd
+ When any event or tracer is enabled, a hook is enabled
+ in the sched_switch trace point to fill comm cache
+ with mapped pids and comms. But this may cause some
+ overhead, and if you only care about pids, and not the
+ name of the task, disabling this option can lower the
+ impact of tracing. See "saved_cmdlines".
+
+ record-tgid
+ When any event or tracer is enabled, a hook is enabled
+ in the sched_switch trace point to fill the cache of
+ mapped Thread Group IDs (TGID) mapping to pids. See
+ "saved_tgids".
+
+ overwrite
+ This controls what happens when the trace buffer is
+ full. If "1" (default), the oldest events are
+ discarded and overwritten. If "0", then the newest
+ events are discarded.
+ (see per_cpu/cpu0/stats for overrun and dropped)
+
+ disable_on_free
+ When the free_buffer is closed, tracing will
+ stop (tracing_on set to 0).
+
+ irq-info
+ Shows the interrupt, preempt count, need resched data.
+ When disabled, the trace looks like::
+
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 144405/9452052 #P:4
+ #
+ # TASK-PID CPU# TIMESTAMP FUNCTION
+ # | | | | |
+ <idle>-0 [002] 23636.756054: ttwu_do_activate.constprop.89 <-try_to_wake_up
+ <idle>-0 [002] 23636.756054: activate_task <-ttwu_do_activate.constprop.89
+ <idle>-0 [002] 23636.756055: enqueue_task <-activate_task
+
+
+ markers
+ When set, the trace_marker is writable (only by root).
+ When disabled, the trace_marker will error with EINVAL
+ on write.
+
+ event-fork
+ When set, tasks with PIDs listed in set_event_pid will have
+ the PIDs of their children added to set_event_pid when those
+ tasks fork. Also, when tasks with PIDs in set_event_pid exit,
+ their PIDs will be removed from the file.
+
+ function-trace
+ The latency tracers will enable function tracing
+ if this option is enabled (default it is). When
+ it is disabled, the latency tracers do not trace
+ functions. This keeps the overhead of the tracer down
+ when performing latency tests.
+
+ function-fork
+ When set, tasks with PIDs listed in set_ftrace_pid will
+ have the PIDs of their children added to set_ftrace_pid
+ when those tasks fork. Also, when tasks with PIDs in
+ set_ftrace_pid exit, their PIDs will be removed from the
+ file.
+
+ display-graph
+ When set, the latency tracers (irqsoff, wakeup, etc) will
+ use function graph tracing instead of function tracing.
+
+ stacktrace
+ When set, a stack trace is recorded after any trace event
+ is recorded.
+
+ branch
+ Enable branch tracing with the tracer. This enables branch
+ tracer along with the currently set tracer. Enabling this
+ with the "nop" tracer is the same as just enabling the
+ "branch" tracer.
+
+.. tip:: Some tracers have their own options. They only appear in this
+ file when the tracer is active. They always appear in the
+ options directory.
+
+
+Here are the per tracer options:
+
+Options for function tracer:
+
+ func_stack_trace
+ When set, a stack trace is recorded after every
+ function that is recorded. NOTE! Limit the functions
+ that are recorded before enabling this, with
+ "set_ftrace_filter" otherwise the system performance
+ will be critically degraded. Remember to disable
+ this option before clearing the function filter.
+
+Options for function_graph tracer:
+
+ Since the function_graph tracer has a slightly different output
+ it has its own options to control what is displayed.
+
+ funcgraph-overrun
+ When set, the "overrun" of the graph stack is
+ displayed after each function traced. The
+ overrun, is when the stack depth of the calls
+ is greater than what is reserved for each task.
+ Each task has a fixed array of functions to
+ trace in the call graph. If the depth of the
+ calls exceeds that, the function is not traced.
+ The overrun is the number of functions missed
+ due to exceeding this array.
+
+ funcgraph-cpu
+ When set, the CPU number of the CPU where the trace
+ occurred is displayed.
+
+ funcgraph-overhead
+ When set, if the function takes longer than
+ A certain amount, then a delay marker is
+ displayed. See "delay" above, under the
+ header description.
+
+ funcgraph-proc
+ Unlike other tracers, the process' command line
+ is not displayed by default, but instead only
+ when a task is traced in and out during a context
+ switch. Enabling this options has the command
+ of each process displayed at every line.
+
+ funcgraph-duration
+ At the end of each function (the return)
+ the duration of the amount of time in the
+ function is displayed in microseconds.
+
+ funcgraph-abstime
+ When set, the timestamp is displayed at each line.
+
+ funcgraph-irqs
+ When disabled, functions that happen inside an
+ interrupt will not be traced.
+
+ funcgraph-tail
+ When set, the return event will include the function
+ that it represents. By default this is off, and
+ only a closing curly bracket "}" is displayed for
+ the return of a function.
+
+ sleep-time
+ When running function graph tracer, to include
+ the time a task schedules out in its function.
+ When enabled, it will account time the task has been
+ scheduled out as part of the function call.
+
+ graph-time
+ When running function profiler with function graph tracer,
+ to include the time to call nested functions. When this is
+ not set, the time reported for the function will only
+ include the time the function itself executed for, not the
+ time for functions that it called.
+
+Options for blk tracer:
+
+ blk_classic
+ Shows a more minimalistic output.
+
+
+irqsoff
+-------
+
+When interrupts are disabled, the CPU can not react to any other
+external event (besides NMIs and SMIs). This prevents the timer
+interrupt from triggering or the mouse interrupt from letting
+the kernel know of a new mouse event. The result is a latency
+with the reaction time.
+
+The irqsoff tracer tracks the time for which interrupts are
+disabled. When a new maximum latency is hit, the tracer saves
+the trace leading up to that latency point so that every time a
+new maximum is reached, the old saved trace is discarded and the
+new trace is saved.
+
+To reset the maximum, echo 0 into tracing_max_latency. Here is
+an example::
+
+ # echo 0 > options/function-trace
+ # echo irqsoff > current_tracer
+ # echo 1 > tracing_on
+ # echo 0 > tracing_max_latency
+ # ls -ltr
+ [...]
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: irqsoff
+ #
+ # irqsoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 16 us, #4/4, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: swapper/0-0 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: run_timer_softirq
+ # => ended at: run_timer_softirq
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ <idle>-0 0d.s2 0us+: _raw_spin_lock_irq <-run_timer_softirq
+ <idle>-0 0dNs3 17us : _raw_spin_unlock_irq <-run_timer_softirq
+ <idle>-0 0dNs3 17us+: trace_hardirqs_on <-run_timer_softirq
+ <idle>-0 0dNs3 25us : <stack trace>
+ => _raw_spin_unlock_irq
+ => run_timer_softirq
+ => __do_softirq
+ => call_softirq
+ => do_softirq
+ => irq_exit
+ => smp_apic_timer_interrupt
+ => apic_timer_interrupt
+ => rcu_idle_exit
+ => cpu_idle
+ => rest_init
+ => start_kernel
+ => x86_64_start_reservations
+ => x86_64_start_kernel
+
+Here we see that that we had a latency of 16 microseconds (which is
+very good). The _raw_spin_lock_irq in run_timer_softirq disabled
+interrupts. The difference between the 16 and the displayed
+timestamp 25us occurred because the clock was incremented
+between the time of recording the max latency and the time of
+recording the function that had that latency.
+
+Note the above example had function-trace not set. If we set
+function-trace, we get a much larger output::
+
+ with echo 1 > options/function-trace
+
+ # tracer: irqsoff
+ #
+ # irqsoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 71 us, #168/168, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: bash-2042 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: ata_scsi_queuecmd
+ # => ended at: ata_scsi_queuecmd
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ bash-2042 3d... 0us : _raw_spin_lock_irqsave <-ata_scsi_queuecmd
+ bash-2042 3d... 0us : add_preempt_count <-_raw_spin_lock_irqsave
+ bash-2042 3d..1 1us : ata_scsi_find_dev <-ata_scsi_queuecmd
+ bash-2042 3d..1 1us : __ata_scsi_find_dev <-ata_scsi_find_dev
+ bash-2042 3d..1 2us : ata_find_dev.part.14 <-__ata_scsi_find_dev
+ bash-2042 3d..1 2us : ata_qc_new_init <-__ata_scsi_queuecmd
+ bash-2042 3d..1 3us : ata_sg_init <-__ata_scsi_queuecmd
+ bash-2042 3d..1 4us : ata_scsi_rw_xlat <-__ata_scsi_queuecmd
+ bash-2042 3d..1 4us : ata_build_rw_tf <-ata_scsi_rw_xlat
+ [...]
+ bash-2042 3d..1 67us : delay_tsc <-__delay
+ bash-2042 3d..1 67us : add_preempt_count <-delay_tsc
+ bash-2042 3d..2 67us : sub_preempt_count <-delay_tsc
+ bash-2042 3d..1 67us : add_preempt_count <-delay_tsc
+ bash-2042 3d..2 68us : sub_preempt_count <-delay_tsc
+ bash-2042 3d..1 68us+: ata_bmdma_start <-ata_bmdma_qc_issue
+ bash-2042 3d..1 71us : _raw_spin_unlock_irqrestore <-ata_scsi_queuecmd
+ bash-2042 3d..1 71us : _raw_spin_unlock_irqrestore <-ata_scsi_queuecmd
+ bash-2042 3d..1 72us+: trace_hardirqs_on <-ata_scsi_queuecmd
+ bash-2042 3d..1 120us : <stack trace>
+ => _raw_spin_unlock_irqrestore
+ => ata_scsi_queuecmd
+ => scsi_dispatch_cmd
+ => scsi_request_fn
+ => __blk_run_queue_uncond
+ => __blk_run_queue
+ => blk_queue_bio
+ => generic_make_request
+ => submit_bio
+ => submit_bh
+ => __ext3_get_inode_loc
+ => ext3_iget
+ => ext3_lookup
+ => lookup_real
+ => __lookup_hash
+ => walk_component
+ => lookup_last
+ => path_lookupat
+ => filename_lookup
+ => user_path_at_empty
+ => user_path_at
+ => vfs_fstatat
+ => vfs_stat
+ => sys_newstat
+ => system_call_fastpath
+
+
+Here we traced a 71 microsecond latency. But we also see all the
+functions that were called during that time. Note that by
+enabling function tracing, we incur an added overhead. This
+overhead may extend the latency times. But nevertheless, this
+trace has provided some very helpful debugging information.
+
+
+preemptoff
+----------
+
+When preemption is disabled, we may be able to receive
+interrupts but the task cannot be preempted and a higher
+priority task must wait for preemption to be enabled again
+before it can preempt a lower priority task.
+
+The preemptoff tracer traces the places that disable preemption.
+Like the irqsoff tracer, it records the maximum latency for
+which preemption was disabled. The control of preemptoff tracer
+is much like the irqsoff tracer.
+::
+
+ # echo 0 > options/function-trace
+ # echo preemptoff > current_tracer
+ # echo 1 > tracing_on
+ # echo 0 > tracing_max_latency
+ # ls -ltr
+ [...]
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: preemptoff
+ #
+ # preemptoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 46 us, #4/4, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: sshd-1991 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: do_IRQ
+ # => ended at: do_IRQ
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ sshd-1991 1d.h. 0us+: irq_enter <-do_IRQ
+ sshd-1991 1d..1 46us : irq_exit <-do_IRQ
+ sshd-1991 1d..1 47us+: trace_preempt_on <-do_IRQ
+ sshd-1991 1d..1 52us : <stack trace>
+ => sub_preempt_count
+ => irq_exit
+ => do_IRQ
+ => ret_from_intr
+
+
+This has some more changes. Preemption was disabled when an
+interrupt came in (notice the 'h'), and was enabled on exit.
+But we also see that interrupts have been disabled when entering
+the preempt off section and leaving it (the 'd'). We do not know if
+interrupts were enabled in the mean time or shortly after this
+was over.
+::
+
+ # tracer: preemptoff
+ #
+ # preemptoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 83 us, #241/241, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: bash-1994 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: wake_up_new_task
+ # => ended at: task_rq_unlock
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ bash-1994 1d..1 0us : _raw_spin_lock_irqsave <-wake_up_new_task
+ bash-1994 1d..1 0us : select_task_rq_fair <-select_task_rq
+ bash-1994 1d..1 1us : __rcu_read_lock <-select_task_rq_fair
+ bash-1994 1d..1 1us : source_load <-select_task_rq_fair
+ bash-1994 1d..1 1us : source_load <-select_task_rq_fair
+ [...]
+ bash-1994 1d..1 12us : irq_enter <-smp_apic_timer_interrupt
+ bash-1994 1d..1 12us : rcu_irq_enter <-irq_enter
+ bash-1994 1d..1 13us : add_preempt_count <-irq_enter
+ bash-1994 1d.h1 13us : exit_idle <-smp_apic_timer_interrupt
+ bash-1994 1d.h1 13us : hrtimer_interrupt <-smp_apic_timer_interrupt
+ bash-1994 1d.h1 13us : _raw_spin_lock <-hrtimer_interrupt
+ bash-1994 1d.h1 14us : add_preempt_count <-_raw_spin_lock
+ bash-1994 1d.h2 14us : ktime_get_update_offsets <-hrtimer_interrupt
+ [...]
+ bash-1994 1d.h1 35us : lapic_next_event <-clockevents_program_event
+ bash-1994 1d.h1 35us : irq_exit <-smp_apic_timer_interrupt
+ bash-1994 1d.h1 36us : sub_preempt_count <-irq_exit
+ bash-1994 1d..2 36us : do_softirq <-irq_exit
+ bash-1994 1d..2 36us : __do_softirq <-call_softirq
+ bash-1994 1d..2 36us : __local_bh_disable <-__do_softirq
+ bash-1994 1d.s2 37us : add_preempt_count <-_raw_spin_lock_irq
+ bash-1994 1d.s3 38us : _raw_spin_unlock <-run_timer_softirq
+ bash-1994 1d.s3 39us : sub_preempt_count <-_raw_spin_unlock
+ bash-1994 1d.s2 39us : call_timer_fn <-run_timer_softirq
+ [...]
+ bash-1994 1dNs2 81us : cpu_needs_another_gp <-rcu_process_callbacks
+ bash-1994 1dNs2 82us : __local_bh_enable <-__do_softirq
+ bash-1994 1dNs2 82us : sub_preempt_count <-__local_bh_enable
+ bash-1994 1dN.2 82us : idle_cpu <-irq_exit
+ bash-1994 1dN.2 83us : rcu_irq_exit <-irq_exit
+ bash-1994 1dN.2 83us : sub_preempt_count <-irq_exit
+ bash-1994 1.N.1 84us : _raw_spin_unlock_irqrestore <-task_rq_unlock
+ bash-1994 1.N.1 84us+: trace_preempt_on <-task_rq_unlock
+ bash-1994 1.N.1 104us : <stack trace>
+ => sub_preempt_count
+ => _raw_spin_unlock_irqrestore
+ => task_rq_unlock
+ => wake_up_new_task
+ => do_fork
+ => sys_clone
+ => stub_clone
+
+
+The above is an example of the preemptoff trace with
+function-trace set. Here we see that interrupts were not disabled
+the entire time. The irq_enter code lets us know that we entered
+an interrupt 'h'. Before that, the functions being traced still
+show that it is not in an interrupt, but we can see from the
+functions themselves that this is not the case.
+
+preemptirqsoff
+--------------
+
+Knowing the locations that have interrupts disabled or
+preemption disabled for the longest times is helpful. But
+sometimes we would like to know when either preemption and/or
+interrupts are disabled.
+
+Consider the following code::
+
+ local_irq_disable();
+ call_function_with_irqs_off();
+ preempt_disable();
+ call_function_with_irqs_and_preemption_off();
+ local_irq_enable();
+ call_function_with_preemption_off();
+ preempt_enable();
+
+The irqsoff tracer will record the total length of
+call_function_with_irqs_off() and
+call_function_with_irqs_and_preemption_off().
+
+The preemptoff tracer will record the total length of
+call_function_with_irqs_and_preemption_off() and
+call_function_with_preemption_off().
+
+But neither will trace the time that interrupts and/or
+preemption is disabled. This total time is the time that we can
+not schedule. To record this time, use the preemptirqsoff
+tracer.
+
+Again, using this trace is much like the irqsoff and preemptoff
+tracers.
+::
+
+ # echo 0 > options/function-trace
+ # echo preemptirqsoff > current_tracer
+ # echo 1 > tracing_on
+ # echo 0 > tracing_max_latency
+ # ls -ltr
+ [...]
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: preemptirqsoff
+ #
+ # preemptirqsoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 100 us, #4/4, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: ls-2230 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: ata_scsi_queuecmd
+ # => ended at: ata_scsi_queuecmd
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ ls-2230 3d... 0us+: _raw_spin_lock_irqsave <-ata_scsi_queuecmd
+ ls-2230 3...1 100us : _raw_spin_unlock_irqrestore <-ata_scsi_queuecmd
+ ls-2230 3...1 101us+: trace_preempt_on <-ata_scsi_queuecmd
+ ls-2230 3...1 111us : <stack trace>
+ => sub_preempt_count
+ => _raw_spin_unlock_irqrestore
+ => ata_scsi_queuecmd
+ => scsi_dispatch_cmd
+ => scsi_request_fn
+ => __blk_run_queue_uncond
+ => __blk_run_queue
+ => blk_queue_bio
+ => generic_make_request
+ => submit_bio
+ => submit_bh
+ => ext3_bread
+ => ext3_dir_bread
+ => htree_dirblock_to_tree
+ => ext3_htree_fill_tree
+ => ext3_readdir
+ => vfs_readdir
+ => sys_getdents
+ => system_call_fastpath
+
+
+The trace_hardirqs_off_thunk is called from assembly on x86 when
+interrupts are disabled in the assembly code. Without the
+function tracing, we do not know if interrupts were enabled
+within the preemption points. We do see that it started with
+preemption enabled.
+
+Here is a trace with function-trace set::
+
+ # tracer: preemptirqsoff
+ #
+ # preemptirqsoff latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 161 us, #339/339, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: ls-2269 (uid:0 nice:0 policy:0 rt_prio:0)
+ # -----------------
+ # => started at: schedule
+ # => ended at: mutex_unlock
+ #
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ kworker/-59 3...1 0us : __schedule <-schedule
+ kworker/-59 3d..1 0us : rcu_preempt_qs <-rcu_note_context_switch
+ kworker/-59 3d..1 1us : add_preempt_count <-_raw_spin_lock_irq
+ kworker/-59 3d..2 1us : deactivate_task <-__schedule
+ kworker/-59 3d..2 1us : dequeue_task <-deactivate_task
+ kworker/-59 3d..2 2us : update_rq_clock <-dequeue_task
+ kworker/-59 3d..2 2us : dequeue_task_fair <-dequeue_task
+ kworker/-59 3d..2 2us : update_curr <-dequeue_task_fair
+ kworker/-59 3d..2 2us : update_min_vruntime <-update_curr
+ kworker/-59 3d..2 3us : cpuacct_charge <-update_curr
+ kworker/-59 3d..2 3us : __rcu_read_lock <-cpuacct_charge
+ kworker/-59 3d..2 3us : __rcu_read_unlock <-cpuacct_charge
+ kworker/-59 3d..2 3us : update_cfs_rq_blocked_load <-dequeue_task_fair
+ kworker/-59 3d..2 4us : clear_buddies <-dequeue_task_fair
+ kworker/-59 3d..2 4us : account_entity_dequeue <-dequeue_task_fair
+ kworker/-59 3d..2 4us : update_min_vruntime <-dequeue_task_fair
+ kworker/-59 3d..2 4us : update_cfs_shares <-dequeue_task_fair
+ kworker/-59 3d..2 5us : hrtick_update <-dequeue_task_fair
+ kworker/-59 3d..2 5us : wq_worker_sleeping <-__schedule
+ kworker/-59 3d..2 5us : kthread_data <-wq_worker_sleeping
+ kworker/-59 3d..2 5us : put_prev_task_fair <-__schedule
+ kworker/-59 3d..2 6us : pick_next_task_fair <-pick_next_task
+ kworker/-59 3d..2 6us : clear_buddies <-pick_next_task_fair
+ kworker/-59 3d..2 6us : set_next_entity <-pick_next_task_fair
+ kworker/-59 3d..2 6us : update_stats_wait_end <-set_next_entity
+ ls-2269 3d..2 7us : finish_task_switch <-__schedule
+ ls-2269 3d..2 7us : _raw_spin_unlock_irq <-finish_task_switch
+ ls-2269 3d..2 8us : do_IRQ <-ret_from_intr
+ ls-2269 3d..2 8us : irq_enter <-do_IRQ
+ ls-2269 3d..2 8us : rcu_irq_enter <-irq_enter
+ ls-2269 3d..2 9us : add_preempt_count <-irq_enter
+ ls-2269 3d.h2 9us : exit_idle <-do_IRQ
+ [...]
+ ls-2269 3d.h3 20us : sub_preempt_count <-_raw_spin_unlock
+ ls-2269 3d.h2 20us : irq_exit <-do_IRQ
+ ls-2269 3d.h2 21us : sub_preempt_count <-irq_exit
+ ls-2269 3d..3 21us : do_softirq <-irq_exit
+ ls-2269 3d..3 21us : __do_softirq <-call_softirq
+ ls-2269 3d..3 21us+: __local_bh_disable <-__do_softirq
+ ls-2269 3d.s4 29us : sub_preempt_count <-_local_bh_enable_ip
+ ls-2269 3d.s5 29us : sub_preempt_count <-_local_bh_enable_ip
+ ls-2269 3d.s5 31us : do_IRQ <-ret_from_intr
+ ls-2269 3d.s5 31us : irq_enter <-do_IRQ
+ ls-2269 3d.s5 31us : rcu_irq_enter <-irq_enter
+ [...]
+ ls-2269 3d.s5 31us : rcu_irq_enter <-irq_enter
+ ls-2269 3d.s5 32us : add_preempt_count <-irq_enter
+ ls-2269 3d.H5 32us : exit_idle <-do_IRQ
+ ls-2269 3d.H5 32us : handle_irq <-do_IRQ
+ ls-2269 3d.H5 32us : irq_to_desc <-handle_irq
+ ls-2269 3d.H5 33us : handle_fasteoi_irq <-handle_irq
+ [...]
+ ls-2269 3d.s5 158us : _raw_spin_unlock_irqrestore <-rtl8139_poll
+ ls-2269 3d.s3 158us : net_rps_action_and_irq_enable.isra.65 <-net_rx_action
+ ls-2269 3d.s3 159us : __local_bh_enable <-__do_softirq
+ ls-2269 3d.s3 159us : sub_preempt_count <-__local_bh_enable
+ ls-2269 3d..3 159us : idle_cpu <-irq_exit
+ ls-2269 3d..3 159us : rcu_irq_exit <-irq_exit
+ ls-2269 3d..3 160us : sub_preempt_count <-irq_exit
+ ls-2269 3d... 161us : __mutex_unlock_slowpath <-mutex_unlock
+ ls-2269 3d... 162us+: trace_hardirqs_on <-mutex_unlock
+ ls-2269 3d... 186us : <stack trace>
+ => __mutex_unlock_slowpath
+ => mutex_unlock
+ => process_output
+ => n_tty_write
+ => tty_write
+ => vfs_write
+ => sys_write
+ => system_call_fastpath
+
+This is an interesting trace. It started with kworker running and
+scheduling out and ls taking over. But as soon as ls released the
+rq lock and enabled interrupts (but not preemption) an interrupt
+triggered. When the interrupt finished, it started running softirqs.
+But while the softirq was running, another interrupt triggered.
+When an interrupt is running inside a softirq, the annotation is 'H'.
+
+
+wakeup
+------
+
+One common case that people are interested in tracing is the
+time it takes for a task that is woken to actually wake up.
+Now for non Real-Time tasks, this can be arbitrary. But tracing
+it none the less can be interesting.
+
+Without function tracing::
+
+ # echo 0 > options/function-trace
+ # echo wakeup > current_tracer
+ # echo 1 > tracing_on
+ # echo 0 > tracing_max_latency
+ # chrt -f 5 sleep 1
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: wakeup
+ #
+ # wakeup latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 15 us, #4/4, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: kworker/3:1H-312 (uid:0 nice:-20 policy:0 rt_prio:0)
+ # -----------------
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ <idle>-0 3dNs7 0us : 0:120:R + [003] 312:100:R kworker/3:1H
+ <idle>-0 3dNs7 1us+: ttwu_do_activate.constprop.87 <-try_to_wake_up
+ <idle>-0 3d..3 15us : __schedule <-schedule
+ <idle>-0 3d..3 15us : 0:120:R ==> [003] 312:100:R kworker/3:1H
+
+The tracer only traces the highest priority task in the system
+to avoid tracing the normal circumstances. Here we see that
+the kworker with a nice priority of -20 (not very nice), took
+just 15 microseconds from the time it woke up, to the time it
+ran.
+
+Non Real-Time tasks are not that interesting. A more interesting
+trace is to concentrate only on Real-Time tasks.
+
+wakeup_rt
+---------
+
+In a Real-Time environment it is very important to know the
+wakeup time it takes for the highest priority task that is woken
+up to the time that it executes. This is also known as "schedule
+latency". I stress the point that this is about RT tasks. It is
+also important to know the scheduling latency of non-RT tasks,
+but the average schedule latency is better for non-RT tasks.
+Tools like LatencyTop are more appropriate for such
+measurements.
+
+Real-Time environments are interested in the worst case latency.
+That is the longest latency it takes for something to happen,
+and not the average. We can have a very fast scheduler that may
+only have a large latency once in a while, but that would not
+work well with Real-Time tasks. The wakeup_rt tracer was designed
+to record the worst case wakeups of RT tasks. Non-RT tasks are
+not recorded because the tracer only records one worst case and
+tracing non-RT tasks that are unpredictable will overwrite the
+worst case latency of RT tasks (just run the normal wakeup
+tracer for a while to see that effect).
+
+Since this tracer only deals with RT tasks, we will run this
+slightly differently than we did with the previous tracers.
+Instead of performing an 'ls', we will run 'sleep 1' under
+'chrt' which changes the priority of the task.
+::
+
+ # echo 0 > options/function-trace
+ # echo wakeup_rt > current_tracer
+ # echo 1 > tracing_on
+ # echo 0 > tracing_max_latency
+ # chrt -f 5 sleep 1
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: wakeup
+ #
+ # tracer: wakeup_rt
+ #
+ # wakeup_rt latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 5 us, #4/4, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: sleep-2389 (uid:0 nice:0 policy:1 rt_prio:5)
+ # -----------------
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ <idle>-0 3d.h4 0us : 0:120:R + [003] 2389: 94:R sleep
+ <idle>-0 3d.h4 1us+: ttwu_do_activate.constprop.87 <-try_to_wake_up
+ <idle>-0 3d..3 5us : __schedule <-schedule
+ <idle>-0 3d..3 5us : 0:120:R ==> [003] 2389: 94:R sleep
+
+
+Running this on an idle system, we see that it only took 5 microseconds
+to perform the task switch. Note, since the trace point in the schedule
+is before the actual "switch", we stop the tracing when the recorded task
+is about to schedule in. This may change if we add a new marker at the
+end of the scheduler.
+
+Notice that the recorded task is 'sleep' with the PID of 2389
+and it has an rt_prio of 5. This priority is user-space priority
+and not the internal kernel priority. The policy is 1 for
+SCHED_FIFO and 2 for SCHED_RR.
+
+Note, that the trace data shows the internal priority (99 - rtprio).
+::
+
+ <idle>-0 3d..3 5us : 0:120:R ==> [003] 2389: 94:R sleep
+
+The 0:120:R means idle was running with a nice priority of 0 (120 - 120)
+and in the running state 'R'. The sleep task was scheduled in with
+2389: 94:R. That is the priority is the kernel rtprio (99 - 5 = 94)
+and it too is in the running state.
+
+Doing the same with chrt -r 5 and function-trace set.
+::
+
+ echo 1 > options/function-trace
+
+ # tracer: wakeup_rt
+ #
+ # wakeup_rt latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 29 us, #85/85, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: sleep-2448 (uid:0 nice:0 policy:1 rt_prio:5)
+ # -----------------
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ <idle>-0 3d.h4 1us+: 0:120:R + [003] 2448: 94:R sleep
+ <idle>-0 3d.h4 2us : ttwu_do_activate.constprop.87 <-try_to_wake_up
+ <idle>-0 3d.h3 3us : check_preempt_curr <-ttwu_do_wakeup
+ <idle>-0 3d.h3 3us : resched_curr <-check_preempt_curr
+ <idle>-0 3dNh3 4us : task_woken_rt <-ttwu_do_wakeup
+ <idle>-0 3dNh3 4us : _raw_spin_unlock <-try_to_wake_up
+ <idle>-0 3dNh3 4us : sub_preempt_count <-_raw_spin_unlock
+ <idle>-0 3dNh2 5us : ttwu_stat <-try_to_wake_up
+ <idle>-0 3dNh2 5us : _raw_spin_unlock_irqrestore <-try_to_wake_up
+ <idle>-0 3dNh2 6us : sub_preempt_count <-_raw_spin_unlock_irqrestore
+ <idle>-0 3dNh1 6us : _raw_spin_lock <-__run_hrtimer
+ <idle>-0 3dNh1 6us : add_preempt_count <-_raw_spin_lock
+ <idle>-0 3dNh2 7us : _raw_spin_unlock <-hrtimer_interrupt
+ <idle>-0 3dNh2 7us : sub_preempt_count <-_raw_spin_unlock
+ <idle>-0 3dNh1 7us : tick_program_event <-hrtimer_interrupt
+ <idle>-0 3dNh1 7us : clockevents_program_event <-tick_program_event
+ <idle>-0 3dNh1 8us : ktime_get <-clockevents_program_event
+ <idle>-0 3dNh1 8us : lapic_next_event <-clockevents_program_event
+ <idle>-0 3dNh1 8us : irq_exit <-smp_apic_timer_interrupt
+ <idle>-0 3dNh1 9us : sub_preempt_count <-irq_exit
+ <idle>-0 3dN.2 9us : idle_cpu <-irq_exit
+ <idle>-0 3dN.2 9us : rcu_irq_exit <-irq_exit
+ <idle>-0 3dN.2 10us : rcu_eqs_enter_common.isra.45 <-rcu_irq_exit
+ <idle>-0 3dN.2 10us : sub_preempt_count <-irq_exit
+ <idle>-0 3.N.1 11us : rcu_idle_exit <-cpu_idle
+ <idle>-0 3dN.1 11us : rcu_eqs_exit_common.isra.43 <-rcu_idle_exit
+ <idle>-0 3.N.1 11us : tick_nohz_idle_exit <-cpu_idle
+ <idle>-0 3dN.1 12us : menu_hrtimer_cancel <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 12us : ktime_get <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 12us : tick_do_update_jiffies64 <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 13us : cpu_load_update_nohz <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 13us : _raw_spin_lock <-cpu_load_update_nohz
+ <idle>-0 3dN.1 13us : add_preempt_count <-_raw_spin_lock
+ <idle>-0 3dN.2 13us : __cpu_load_update <-cpu_load_update_nohz
+ <idle>-0 3dN.2 14us : sched_avg_update <-__cpu_load_update
+ <idle>-0 3dN.2 14us : _raw_spin_unlock <-cpu_load_update_nohz
+ <idle>-0 3dN.2 14us : sub_preempt_count <-_raw_spin_unlock
+ <idle>-0 3dN.1 15us : calc_load_nohz_stop <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 15us : touch_softlockup_watchdog <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 15us : hrtimer_cancel <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 15us : hrtimer_try_to_cancel <-hrtimer_cancel
+ <idle>-0 3dN.1 16us : lock_hrtimer_base.isra.18 <-hrtimer_try_to_cancel
+ <idle>-0 3dN.1 16us : _raw_spin_lock_irqsave <-lock_hrtimer_base.isra.18
+ <idle>-0 3dN.1 16us : add_preempt_count <-_raw_spin_lock_irqsave
+ <idle>-0 3dN.2 17us : __remove_hrtimer <-remove_hrtimer.part.16
+ <idle>-0 3dN.2 17us : hrtimer_force_reprogram <-__remove_hrtimer
+ <idle>-0 3dN.2 17us : tick_program_event <-hrtimer_force_reprogram
+ <idle>-0 3dN.2 18us : clockevents_program_event <-tick_program_event
+ <idle>-0 3dN.2 18us : ktime_get <-clockevents_program_event
+ <idle>-0 3dN.2 18us : lapic_next_event <-clockevents_program_event
+ <idle>-0 3dN.2 19us : _raw_spin_unlock_irqrestore <-hrtimer_try_to_cancel
+ <idle>-0 3dN.2 19us : sub_preempt_count <-_raw_spin_unlock_irqrestore
+ <idle>-0 3dN.1 19us : hrtimer_forward <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 20us : ktime_add_safe <-hrtimer_forward
+ <idle>-0 3dN.1 20us : ktime_add_safe <-hrtimer_forward
+ <idle>-0 3dN.1 20us : hrtimer_start_range_ns <-hrtimer_start_expires.constprop.11
+ <idle>-0 3dN.1 20us : __hrtimer_start_range_ns <-hrtimer_start_range_ns
+ <idle>-0 3dN.1 21us : lock_hrtimer_base.isra.18 <-__hrtimer_start_range_ns
+ <idle>-0 3dN.1 21us : _raw_spin_lock_irqsave <-lock_hrtimer_base.isra.18
+ <idle>-0 3dN.1 21us : add_preempt_count <-_raw_spin_lock_irqsave
+ <idle>-0 3dN.2 22us : ktime_add_safe <-__hrtimer_start_range_ns
+ <idle>-0 3dN.2 22us : enqueue_hrtimer <-__hrtimer_start_range_ns
+ <idle>-0 3dN.2 22us : tick_program_event <-__hrtimer_start_range_ns
+ <idle>-0 3dN.2 23us : clockevents_program_event <-tick_program_event
+ <idle>-0 3dN.2 23us : ktime_get <-clockevents_program_event
+ <idle>-0 3dN.2 23us : lapic_next_event <-clockevents_program_event
+ <idle>-0 3dN.2 24us : _raw_spin_unlock_irqrestore <-__hrtimer_start_range_ns
+ <idle>-0 3dN.2 24us : sub_preempt_count <-_raw_spin_unlock_irqrestore
+ <idle>-0 3dN.1 24us : account_idle_ticks <-tick_nohz_idle_exit
+ <idle>-0 3dN.1 24us : account_idle_time <-account_idle_ticks
+ <idle>-0 3.N.1 25us : sub_preempt_count <-cpu_idle
+ <idle>-0 3.N.. 25us : schedule <-cpu_idle
+ <idle>-0 3.N.. 25us : __schedule <-preempt_schedule
+ <idle>-0 3.N.. 26us : add_preempt_count <-__schedule
+ <idle>-0 3.N.1 26us : rcu_note_context_switch <-__schedule
+ <idle>-0 3.N.1 26us : rcu_sched_qs <-rcu_note_context_switch
+ <idle>-0 3dN.1 27us : rcu_preempt_qs <-rcu_note_context_switch
+ <idle>-0 3.N.1 27us : _raw_spin_lock_irq <-__schedule
+ <idle>-0 3dN.1 27us : add_preempt_count <-_raw_spin_lock_irq
+ <idle>-0 3dN.2 28us : put_prev_task_idle <-__schedule
+ <idle>-0 3dN.2 28us : pick_next_task_stop <-pick_next_task
+ <idle>-0 3dN.2 28us : pick_next_task_rt <-pick_next_task
+ <idle>-0 3dN.2 29us : dequeue_pushable_task <-pick_next_task_rt
+ <idle>-0 3d..3 29us : __schedule <-preempt_schedule
+ <idle>-0 3d..3 30us : 0:120:R ==> [003] 2448: 94:R sleep
+
+This isn't that big of a trace, even with function tracing enabled,
+so I included the entire trace.
+
+The interrupt went off while when the system was idle. Somewhere
+before task_woken_rt() was called, the NEED_RESCHED flag was set,
+this is indicated by the first occurrence of the 'N' flag.
+
+Latency tracing and events
+--------------------------
+As function tracing can induce a much larger latency, but without
+seeing what happens within the latency it is hard to know what
+caused it. There is a middle ground, and that is with enabling
+events.
+::
+
+ # echo 0 > options/function-trace
+ # echo wakeup_rt > current_tracer
+ # echo 1 > events/enable
+ # echo 1 > tracing_on
+ # echo 0 > tracing_max_latency
+ # chrt -f 5 sleep 1
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: wakeup_rt
+ #
+ # wakeup_rt latency trace v1.1.5 on 3.8.0-test+
+ # --------------------------------------------------------------------
+ # latency: 6 us, #12/12, CPU#2 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
+ # -----------------
+ # | task: sleep-5882 (uid:0 nice:0 policy:1 rt_prio:5)
+ # -----------------
+ #
+ # _------=> CPU#
+ # / _-----=> irqs-off
+ # | / _----=> need-resched
+ # || / _---=> hardirq/softirq
+ # ||| / _--=> preempt-depth
+ # |||| / delay
+ # cmd pid ||||| time | caller
+ # \ / ||||| \ | /
+ <idle>-0 2d.h4 0us : 0:120:R + [002] 5882: 94:R sleep
+ <idle>-0 2d.h4 0us : ttwu_do_activate.constprop.87 <-try_to_wake_up
+ <idle>-0 2d.h4 1us : sched_wakeup: comm=sleep pid=5882 prio=94 success=1 target_cpu=002
+ <idle>-0 2dNh2 1us : hrtimer_expire_exit: hrtimer=ffff88007796feb8
+ <idle>-0 2.N.2 2us : power_end: cpu_id=2
+ <idle>-0 2.N.2 3us : cpu_idle: state=4294967295 cpu_id=2
+ <idle>-0 2dN.3 4us : hrtimer_cancel: hrtimer=ffff88007d50d5e0
+ <idle>-0 2dN.3 4us : hrtimer_start: hrtimer=ffff88007d50d5e0 function=tick_sched_timer expires=34311211000000 softexpires=34311211000000
+ <idle>-0 2.N.2 5us : rcu_utilization: Start context switch
+ <idle>-0 2.N.2 5us : rcu_utilization: End context switch
+ <idle>-0 2d..3 6us : __schedule <-schedule
+ <idle>-0 2d..3 6us : 0:120:R ==> [002] 5882: 94:R sleep
+
+
+Hardware Latency Detector
+-------------------------
+
+The hardware latency detector is executed by enabling the "hwlat" tracer.
+
+NOTE, this tracer will affect the performance of the system as it will
+periodically make a CPU constantly busy with interrupts disabled.
+::
+
+ # echo hwlat > current_tracer
+ # sleep 100
+ # cat trace
+ # tracer: hwlat
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ <...>-3638 [001] d... 19452.055471: #1 inner/outer(us): 12/14 ts:1499801089.066141940
+ <...>-3638 [003] d... 19454.071354: #2 inner/outer(us): 11/9 ts:1499801091.082164365
+ <...>-3638 [002] dn.. 19461.126852: #3 inner/outer(us): 12/9 ts:1499801098.138150062
+ <...>-3638 [001] d... 19488.340960: #4 inner/outer(us): 8/12 ts:1499801125.354139633
+ <...>-3638 [003] d... 19494.388553: #5 inner/outer(us): 8/12 ts:1499801131.402150961
+ <...>-3638 [003] d... 19501.283419: #6 inner/outer(us): 0/12 ts:1499801138.297435289 nmi-total:4 nmi-count:1
+
+
+The above output is somewhat the same in the header. All events will have
+interrupts disabled 'd'. Under the FUNCTION title there is:
+
+ #1
+ This is the count of events recorded that were greater than the
+ tracing_threshold (See below).
+
+ inner/outer(us): 12/14
+
+ This shows two numbers as "inner latency" and "outer latency". The test
+ runs in a loop checking a timestamp twice. The latency detected within
+ the two timestamps is the "inner latency" and the latency detected
+ after the previous timestamp and the next timestamp in the loop is
+ the "outer latency".
+
+ ts:1499801089.066141940
+
+ The absolute timestamp that the event happened.
+
+ nmi-total:4 nmi-count:1
+
+ On architectures that support it, if an NMI comes in during the
+ test, the time spent in NMI is reported in "nmi-total" (in
+ microseconds).
+
+ All architectures that have NMIs will show the "nmi-count" if an
+ NMI comes in during the test.
+
+hwlat files:
+
+ tracing_threshold
+ This gets automatically set to "10" to represent 10
+ microseconds. This is the threshold of latency that
+ needs to be detected before the trace will be recorded.
+
+ Note, when hwlat tracer is finished (another tracer is
+ written into "current_tracer"), the original value for
+ tracing_threshold is placed back into this file.
+
+ hwlat_detector/width
+ The length of time the test runs with interrupts disabled.
+
+ hwlat_detector/window
+ The length of time of the window which the test
+ runs. That is, the test will run for "width"
+ microseconds per "window" microseconds
+
+ tracing_cpumask
+ When the test is started. A kernel thread is created that
+ runs the test. This thread will alternate between CPUs
+ listed in the tracing_cpumask between each period
+ (one "window"). To limit the test to specific CPUs
+ set the mask in this file to only the CPUs that the test
+ should run on.
+
+function
+--------
+
+This tracer is the function tracer. Enabling the function tracer
+can be done from the debug file system. Make sure the
+ftrace_enabled is set; otherwise this tracer is a nop.
+See the "ftrace_enabled" section below.
+::
+
+ # sysctl kernel.ftrace_enabled=1
+ # echo function > current_tracer
+ # echo 1 > tracing_on
+ # usleep 1
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 24799/24799 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ bash-1994 [002] .... 3082.063030: mutex_unlock <-rb_simple_write
+ bash-1994 [002] .... 3082.063031: __mutex_unlock_slowpath <-mutex_unlock
+ bash-1994 [002] .... 3082.063031: __fsnotify_parent <-fsnotify_modify
+ bash-1994 [002] .... 3082.063032: fsnotify <-fsnotify_modify
+ bash-1994 [002] .... 3082.063032: __srcu_read_lock <-fsnotify
+ bash-1994 [002] .... 3082.063032: add_preempt_count <-__srcu_read_lock
+ bash-1994 [002] ...1 3082.063032: sub_preempt_count <-__srcu_read_lock
+ bash-1994 [002] .... 3082.063033: __srcu_read_unlock <-fsnotify
+ [...]
+
+
+Note: function tracer uses ring buffers to store the above
+entries. The newest data may overwrite the oldest data.
+Sometimes using echo to stop the trace is not sufficient because
+the tracing could have overwritten the data that you wanted to
+record. For this reason, it is sometimes better to disable
+tracing directly from a program. This allows you to stop the
+tracing at the point that you hit the part that you are
+interested in. To disable the tracing directly from a C program,
+something like following code snippet can be used::
+
+ int trace_fd;
+ [...]
+ int main(int argc, char *argv[]) {
+ [...]
+ trace_fd = open(tracing_file("tracing_on"), O_WRONLY);
+ [...]
+ if (condition_hit()) {
+ write(trace_fd, "0", 1);
+ }
+ [...]
+ }
+
+
+Single thread tracing
+---------------------
+
+By writing into set_ftrace_pid you can trace a
+single thread. For example::
+
+ # cat set_ftrace_pid
+ no pid
+ # echo 3111 > set_ftrace_pid
+ # cat set_ftrace_pid
+ 3111
+ # echo function > current_tracer
+ # cat trace | head
+ # tracer: function
+ #
+ # TASK-PID CPU# TIMESTAMP FUNCTION
+ # | | | | |
+ yum-updatesd-3111 [003] 1637.254676: finish_task_switch <-thread_return
+ yum-updatesd-3111 [003] 1637.254681: hrtimer_cancel <-schedule_hrtimeout_range
+ yum-updatesd-3111 [003] 1637.254682: hrtimer_try_to_cancel <-hrtimer_cancel
+ yum-updatesd-3111 [003] 1637.254683: lock_hrtimer_base <-hrtimer_try_to_cancel
+ yum-updatesd-3111 [003] 1637.254685: fget_light <-do_sys_poll
+ yum-updatesd-3111 [003] 1637.254686: pipe_poll <-do_sys_poll
+ # echo > set_ftrace_pid
+ # cat trace |head
+ # tracer: function
+ #
+ # TASK-PID CPU# TIMESTAMP FUNCTION
+ # | | | | |
+ ##### CPU 3 buffer started ####
+ yum-updatesd-3111 [003] 1701.957688: free_poll_entry <-poll_freewait
+ yum-updatesd-3111 [003] 1701.957689: remove_wait_queue <-free_poll_entry
+ yum-updatesd-3111 [003] 1701.957691: fput <-free_poll_entry
+ yum-updatesd-3111 [003] 1701.957692: audit_syscall_exit <-sysret_audit
+ yum-updatesd-3111 [003] 1701.957693: path_put <-audit_syscall_exit
+
+If you want to trace a function when executing, you could use
+something like this simple program.
+::
+
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <sys/types.h>
+ #include <sys/stat.h>
+ #include <fcntl.h>
+ #include <unistd.h>
+ #include <string.h>
+
+ #define _STR(x) #x
+ #define STR(x) _STR(x)
+ #define MAX_PATH 256
+
+ const char *find_tracefs(void)
+ {
+ static char tracefs[MAX_PATH+1];
+ static int tracefs_found;
+ char type[100];
+ FILE *fp;
+
+ if (tracefs_found)
+ return tracefs;
+
+ if ((fp = fopen("/proc/mounts","r")) == NULL) {
+ perror("/proc/mounts");
+ return NULL;
+ }
+
+ while (fscanf(fp, "%*s %"
+ STR(MAX_PATH)
+ "s %99s %*s %*d %*d\n",
+ tracefs, type) == 2) {
+ if (strcmp(type, "tracefs") == 0)
+ break;
+ }
+ fclose(fp);
+
+ if (strcmp(type, "tracefs") != 0) {
+ fprintf(stderr, "tracefs not mounted");
+ return NULL;
+ }
+
+ strcat(tracefs, "/tracing/");
+ tracefs_found = 1;
+
+ return tracefs;
+ }
+
+ const char *tracing_file(const char *file_name)
+ {
+ static char trace_file[MAX_PATH+1];
+ snprintf(trace_file, MAX_PATH, "%s/%s", find_tracefs(), file_name);
+ return trace_file;
+ }
+
+ int main (int argc, char **argv)
+ {
+ if (argc < 1)
+ exit(-1);
+
+ if (fork() > 0) {
+ int fd, ffd;
+ char line[64];
+ int s;
+
+ ffd = open(tracing_file("current_tracer"), O_WRONLY);
+ if (ffd < 0)
+ exit(-1);
+ write(ffd, "nop", 3);
+
+ fd = open(tracing_file("set_ftrace_pid"), O_WRONLY);
+ s = sprintf(line, "%d\n", getpid());
+ write(fd, line, s);
+
+ write(ffd, "function", 8);
+
+ close(fd);
+ close(ffd);
+
+ execvp(argv[1], argv+1);
+ }
+
+ return 0;
+ }
+
+Or this simple script!
+::
+
+ #!/bin/bash
+
+ tracefs=`sed -ne 's/^tracefs \(.*\) tracefs.*/\1/p' /proc/mounts`
+ echo nop > $tracefs/tracing/current_tracer
+ echo 0 > $tracefs/tracing/tracing_on
+ echo $$ > $tracefs/tracing/set_ftrace_pid
+ echo function > $tracefs/tracing/current_tracer
+ echo 1 > $tracefs/tracing/tracing_on
+ exec "$@"
+
+
+function graph tracer
+---------------------------
+
+This tracer is similar to the function tracer except that it
+probes a function on its entry and its exit. This is done by
+using a dynamically allocated stack of return addresses in each
+task_struct. On function entry the tracer overwrites the return
+address of each function traced to set a custom probe. Thus the
+original return address is stored on the stack of return address
+in the task_struct.
+
+Probing on both ends of a function leads to special features
+such as:
+
+- measure of a function's time execution
+- having a reliable call stack to draw function calls graph
+
+This tracer is useful in several situations:
+
+- you want to find the reason of a strange kernel behavior and
+ need to see what happens in detail on any areas (or specific
+ ones).
+
+- you are experiencing weird latencies but it's difficult to
+ find its origin.
+
+- you want to find quickly which path is taken by a specific
+ function
+
+- you just want to peek inside a working kernel and want to see
+ what happens there.
+
+::
+
+ # tracer: function_graph
+ #
+ # CPU DURATION FUNCTION CALLS
+ # | | | | | | |
+
+ 0) | sys_open() {
+ 0) | do_sys_open() {
+ 0) | getname() {
+ 0) | kmem_cache_alloc() {
+ 0) 1.382 us | __might_sleep();
+ 0) 2.478 us | }
+ 0) | strncpy_from_user() {
+ 0) | might_fault() {
+ 0) 1.389 us | __might_sleep();
+ 0) 2.553 us | }
+ 0) 3.807 us | }
+ 0) 7.876 us | }
+ 0) | alloc_fd() {
+ 0) 0.668 us | _spin_lock();
+ 0) 0.570 us | expand_files();
+ 0) 0.586 us | _spin_unlock();
+
+
+There are several columns that can be dynamically
+enabled/disabled. You can use every combination of options you
+want, depending on your needs.
+
+- The cpu number on which the function executed is default
+ enabled. It is sometimes better to only trace one cpu (see
+ tracing_cpu_mask file) or you might sometimes see unordered
+ function calls while cpu tracing switch.
+
+ - hide: echo nofuncgraph-cpu > trace_options
+ - show: echo funcgraph-cpu > trace_options
+
+- The duration (function's time of execution) is displayed on
+ the closing bracket line of a function or on the same line
+ than the current function in case of a leaf one. It is default
+ enabled.
+
+ - hide: echo nofuncgraph-duration > trace_options
+ - show: echo funcgraph-duration > trace_options
+
+- The overhead field precedes the duration field in case of
+ reached duration thresholds.
+
+ - hide: echo nofuncgraph-overhead > trace_options
+ - show: echo funcgraph-overhead > trace_options
+ - depends on: funcgraph-duration
+
+ ie::
+
+ 3) # 1837.709 us | } /* __switch_to */
+ 3) | finish_task_switch() {
+ 3) 0.313 us | _raw_spin_unlock_irq();
+ 3) 3.177 us | }
+ 3) # 1889.063 us | } /* __schedule */
+ 3) ! 140.417 us | } /* __schedule */
+ 3) # 2034.948 us | } /* schedule */
+ 3) * 33998.59 us | } /* schedule_preempt_disabled */
+
+ [...]
+
+ 1) 0.260 us | msecs_to_jiffies();
+ 1) 0.313 us | __rcu_read_unlock();
+ 1) + 61.770 us | }
+ 1) + 64.479 us | }
+ 1) 0.313 us | rcu_bh_qs();
+ 1) 0.313 us | __local_bh_enable();
+ 1) ! 217.240 us | }
+ 1) 0.365 us | idle_cpu();
+ 1) | rcu_irq_exit() {
+ 1) 0.417 us | rcu_eqs_enter_common.isra.47();
+ 1) 3.125 us | }
+ 1) ! 227.812 us | }
+ 1) ! 457.395 us | }
+ 1) @ 119760.2 us | }
+
+ [...]
+
+ 2) | handle_IPI() {
+ 1) 6.979 us | }
+ 2) 0.417 us | scheduler_ipi();
+ 1) 9.791 us | }
+ 1) + 12.917 us | }
+ 2) 3.490 us | }
+ 1) + 15.729 us | }
+ 1) + 18.542 us | }
+ 2) $ 3594274 us | }
+
+Flags::
+
+ + means that the function exceeded 10 usecs.
+ ! means that the function exceeded 100 usecs.
+ # means that the function exceeded 1000 usecs.
+ * means that the function exceeded 10 msecs.
+ @ means that the function exceeded 100 msecs.
+ $ means that the function exceeded 1 sec.
+
+
+- The task/pid field displays the thread cmdline and pid which
+ executed the function. It is default disabled.
+
+ - hide: echo nofuncgraph-proc > trace_options
+ - show: echo funcgraph-proc > trace_options
+
+ ie::
+
+ # tracer: function_graph
+ #
+ # CPU TASK/PID DURATION FUNCTION CALLS
+ # | | | | | | | | |
+ 0) sh-4802 | | d_free() {
+ 0) sh-4802 | | call_rcu() {
+ 0) sh-4802 | | __call_rcu() {
+ 0) sh-4802 | 0.616 us | rcu_process_gp_end();
+ 0) sh-4802 | 0.586 us | check_for_new_grace_period();
+ 0) sh-4802 | 2.899 us | }
+ 0) sh-4802 | 4.040 us | }
+ 0) sh-4802 | 5.151 us | }
+ 0) sh-4802 | + 49.370 us | }
+
+
+- The absolute time field is an absolute timestamp given by the
+ system clock since it started. A snapshot of this time is
+ given on each entry/exit of functions
+
+ - hide: echo nofuncgraph-abstime > trace_options
+ - show: echo funcgraph-abstime > trace_options
+
+ ie::
+
+ #
+ # TIME CPU DURATION FUNCTION CALLS
+ # | | | | | | | |
+ 360.774522 | 1) 0.541 us | }
+ 360.774522 | 1) 4.663 us | }
+ 360.774523 | 1) 0.541 us | __wake_up_bit();
+ 360.774524 | 1) 6.796 us | }
+ 360.774524 | 1) 7.952 us | }
+ 360.774525 | 1) 9.063 us | }
+ 360.774525 | 1) 0.615 us | journal_mark_dirty();
+ 360.774527 | 1) 0.578 us | __brelse();
+ 360.774528 | 1) | reiserfs_prepare_for_journal() {
+ 360.774528 | 1) | unlock_buffer() {
+ 360.774529 | 1) | wake_up_bit() {
+ 360.774529 | 1) | bit_waitqueue() {
+ 360.774530 | 1) 0.594 us | __phys_addr();
+
+
+The function name is always displayed after the closing bracket
+for a function if the start of that function is not in the
+trace buffer.
+
+Display of the function name after the closing bracket may be
+enabled for functions whose start is in the trace buffer,
+allowing easier searching with grep for function durations.
+It is default disabled.
+
+ - hide: echo nofuncgraph-tail > trace_options
+ - show: echo funcgraph-tail > trace_options
+
+ Example with nofuncgraph-tail (default)::
+
+ 0) | putname() {
+ 0) | kmem_cache_free() {
+ 0) 0.518 us | __phys_addr();
+ 0) 1.757 us | }
+ 0) 2.861 us | }
+
+ Example with funcgraph-tail::
+
+ 0) | putname() {
+ 0) | kmem_cache_free() {
+ 0) 0.518 us | __phys_addr();
+ 0) 1.757 us | } /* kmem_cache_free() */
+ 0) 2.861 us | } /* putname() */
+
+You can put some comments on specific functions by using
+trace_printk() For example, if you want to put a comment inside
+the __might_sleep() function, you just have to include
+<linux/ftrace.h> and call trace_printk() inside __might_sleep()::
+
+ trace_printk("I'm a comment!\n")
+
+will produce::
+
+ 1) | __might_sleep() {
+ 1) | /* I'm a comment! */
+ 1) 1.449 us | }
+
+
+You might find other useful features for this tracer in the
+following "dynamic ftrace" section such as tracing only specific
+functions or tasks.
+
+dynamic ftrace
+--------------
+
+If CONFIG_DYNAMIC_FTRACE is set, the system will run with
+virtually no overhead when function tracing is disabled. The way
+this works is the mcount function call (placed at the start of
+every kernel function, produced by the -pg switch in gcc),
+starts of pointing to a simple return. (Enabling FTRACE will
+include the -pg switch in the compiling of the kernel.)
+
+At compile time every C file object is run through the
+recordmcount program (located in the scripts directory). This
+program will parse the ELF headers in the C object to find all
+the locations in the .text section that call mcount. Starting
+with gcc verson 4.6, the -mfentry has been added for x86, which
+calls "__fentry__" instead of "mcount". Which is called before
+the creation of the stack frame.
+
+Note, not all sections are traced. They may be prevented by either
+a notrace, or blocked another way and all inline functions are not
+traced. Check the "available_filter_functions" file to see what functions
+can be traced.
+
+A section called "__mcount_loc" is created that holds
+references to all the mcount/fentry call sites in the .text section.
+The recordmcount program re-links this section back into the
+original object. The final linking stage of the kernel will add all these
+references into a single table.
+
+On boot up, before SMP is initialized, the dynamic ftrace code
+scans this table and updates all the locations into nops. It
+also records the locations, which are added to the
+available_filter_functions list. Modules are processed as they
+are loaded and before they are executed. When a module is
+unloaded, it also removes its functions from the ftrace function
+list. This is automatic in the module unload code, and the
+module author does not need to worry about it.
+
+When tracing is enabled, the process of modifying the function
+tracepoints is dependent on architecture. The old method is to use
+kstop_machine to prevent races with the CPUs executing code being
+modified (which can cause the CPU to do undesirable things, especially
+if the modified code crosses cache (or page) boundaries), and the nops are
+patched back to calls. But this time, they do not call mcount
+(which is just a function stub). They now call into the ftrace
+infrastructure.
+
+The new method of modifying the function tracepoints is to place
+a breakpoint at the location to be modified, sync all CPUs, modify
+the rest of the instruction not covered by the breakpoint. Sync
+all CPUs again, and then remove the breakpoint with the finished
+version to the ftrace call site.
+
+Some archs do not even need to monkey around with the synchronization,
+and can just slap the new code on top of the old without any
+problems with other CPUs executing it at the same time.
+
+One special side-effect to the recording of the functions being
+traced is that we can now selectively choose which functions we
+wish to trace and which ones we want the mcount calls to remain
+as nops.
+
+Two files are used, one for enabling and one for disabling the
+tracing of specified functions. They are:
+
+ set_ftrace_filter
+
+and
+
+ set_ftrace_notrace
+
+A list of available functions that you can add to these files is
+listed in:
+
+ available_filter_functions
+
+::
+
+ # cat available_filter_functions
+ put_prev_task_idle
+ kmem_cache_create
+ pick_next_task_rt
+ get_online_cpus
+ pick_next_task_fair
+ mutex_lock
+ [...]
+
+If I am only interested in sys_nanosleep and hrtimer_interrupt::
+
+ # echo sys_nanosleep hrtimer_interrupt > set_ftrace_filter
+ # echo function > current_tracer
+ # echo 1 > tracing_on
+ # usleep 1
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 5/5 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ usleep-2665 [001] .... 4186.475355: sys_nanosleep <-system_call_fastpath
+ <idle>-0 [001] d.h1 4186.475409: hrtimer_interrupt <-smp_apic_timer_interrupt
+ usleep-2665 [001] d.h1 4186.475426: hrtimer_interrupt <-smp_apic_timer_interrupt
+ <idle>-0 [003] d.h1 4186.475426: hrtimer_interrupt <-smp_apic_timer_interrupt
+ <idle>-0 [002] d.h1 4186.475427: hrtimer_interrupt <-smp_apic_timer_interrupt
+
+To see which functions are being traced, you can cat the file:
+::
+
+ # cat set_ftrace_filter
+ hrtimer_interrupt
+ sys_nanosleep
+
+
+Perhaps this is not enough. The filters also allow glob(7) matching.
+
+ ``<match>*``
+ will match functions that begin with <match>
+ ``*<match>``
+ will match functions that end with <match>
+ ``*<match>*``
+ will match functions that have <match> in it
+ ``<match1>*<match2>``
+ will match functions that begin with <match1> and end with <match2>
+
+.. note::
+ It is better to use quotes to enclose the wild cards,
+ otherwise the shell may expand the parameters into names
+ of files in the local directory.
+
+::
+
+ # echo 'hrtimer_*' > set_ftrace_filter
+
+Produces::
+
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 897/897 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ <idle>-0 [003] dN.1 4228.547803: hrtimer_cancel <-tick_nohz_idle_exit
+ <idle>-0 [003] dN.1 4228.547804: hrtimer_try_to_cancel <-hrtimer_cancel
+ <idle>-0 [003] dN.2 4228.547805: hrtimer_force_reprogram <-__remove_hrtimer
+ <idle>-0 [003] dN.1 4228.547805: hrtimer_forward <-tick_nohz_idle_exit
+ <idle>-0 [003] dN.1 4228.547805: hrtimer_start_range_ns <-hrtimer_start_expires.constprop.11
+ <idle>-0 [003] d..1 4228.547858: hrtimer_get_next_event <-get_next_timer_interrupt
+ <idle>-0 [003] d..1 4228.547859: hrtimer_start <-__tick_nohz_idle_enter
+ <idle>-0 [003] d..2 4228.547860: hrtimer_force_reprogram <-__rem
+
+Notice that we lost the sys_nanosleep.
+::
+
+ # cat set_ftrace_filter
+ hrtimer_run_queues
+ hrtimer_run_pending
+ hrtimer_init
+ hrtimer_cancel
+ hrtimer_try_to_cancel
+ hrtimer_forward
+ hrtimer_start
+ hrtimer_reprogram
+ hrtimer_force_reprogram
+ hrtimer_get_next_event
+ hrtimer_interrupt
+ hrtimer_nanosleep
+ hrtimer_wakeup
+ hrtimer_get_remaining
+ hrtimer_get_res
+ hrtimer_init_sleeper
+
+
+This is because the '>' and '>>' act just like they do in bash.
+To rewrite the filters, use '>'
+To append to the filters, use '>>'
+
+To clear out a filter so that all functions will be recorded
+again::
+
+ # echo > set_ftrace_filter
+ # cat set_ftrace_filter
+ #
+
+Again, now we want to append.
+
+::
+
+ # echo sys_nanosleep > set_ftrace_filter
+ # cat set_ftrace_filter
+ sys_nanosleep
+ # echo 'hrtimer_*' >> set_ftrace_filter
+ # cat set_ftrace_filter
+ hrtimer_run_queues
+ hrtimer_run_pending
+ hrtimer_init
+ hrtimer_cancel
+ hrtimer_try_to_cancel
+ hrtimer_forward
+ hrtimer_start
+ hrtimer_reprogram
+ hrtimer_force_reprogram
+ hrtimer_get_next_event
+ hrtimer_interrupt
+ sys_nanosleep
+ hrtimer_nanosleep
+ hrtimer_wakeup
+ hrtimer_get_remaining
+ hrtimer_get_res
+ hrtimer_init_sleeper
+
+
+The set_ftrace_notrace prevents those functions from being
+traced.
+::
+
+ # echo '*preempt*' '*lock*' > set_ftrace_notrace
+
+Produces::
+
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 39608/39608 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ bash-1994 [000] .... 4342.324896: file_ra_state_init <-do_dentry_open
+ bash-1994 [000] .... 4342.324897: open_check_o_direct <-do_last
+ bash-1994 [000] .... 4342.324897: ima_file_check <-do_last
+ bash-1994 [000] .... 4342.324898: process_measurement <-ima_file_check
+ bash-1994 [000] .... 4342.324898: ima_get_action <-process_measurement
+ bash-1994 [000] .... 4342.324898: ima_match_policy <-ima_get_action
+ bash-1994 [000] .... 4342.324899: do_truncate <-do_last
+ bash-1994 [000] .... 4342.324899: should_remove_suid <-do_truncate
+ bash-1994 [000] .... 4342.324899: notify_change <-do_truncate
+ bash-1994 [000] .... 4342.324900: current_fs_time <-notify_change
+ bash-1994 [000] .... 4342.324900: current_kernel_time <-current_fs_time
+ bash-1994 [000] .... 4342.324900: timespec_trunc <-current_fs_time
+
+We can see that there's no more lock or preempt tracing.
+
+
+Dynamic ftrace with the function graph tracer
+---------------------------------------------
+
+Although what has been explained above concerns both the
+function tracer and the function-graph-tracer, there are some
+special features only available in the function-graph tracer.
+
+If you want to trace only one function and all of its children,
+you just have to echo its name into set_graph_function::
+
+ echo __do_fault > set_graph_function
+
+will produce the following "expanded" trace of the __do_fault()
+function::
+
+ 0) | __do_fault() {
+ 0) | filemap_fault() {
+ 0) | find_lock_page() {
+ 0) 0.804 us | find_get_page();
+ 0) | __might_sleep() {
+ 0) 1.329 us | }
+ 0) 3.904 us | }
+ 0) 4.979 us | }
+ 0) 0.653 us | _spin_lock();
+ 0) 0.578 us | page_add_file_rmap();
+ 0) 0.525 us | native_set_pte_at();
+ 0) 0.585 us | _spin_unlock();
+ 0) | unlock_page() {
+ 0) 0.541 us | page_waitqueue();
+ 0) 0.639 us | __wake_up_bit();
+ 0) 2.786 us | }
+ 0) + 14.237 us | }
+ 0) | __do_fault() {
+ 0) | filemap_fault() {
+ 0) | find_lock_page() {
+ 0) 0.698 us | find_get_page();
+ 0) | __might_sleep() {
+ 0) 1.412 us | }
+ 0) 3.950 us | }
+ 0) 5.098 us | }
+ 0) 0.631 us | _spin_lock();
+ 0) 0.571 us | page_add_file_rmap();
+ 0) 0.526 us | native_set_pte_at();
+ 0) 0.586 us | _spin_unlock();
+ 0) | unlock_page() {
+ 0) 0.533 us | page_waitqueue();
+ 0) 0.638 us | __wake_up_bit();
+ 0) 2.793 us | }
+ 0) + 14.012 us | }
+
+You can also expand several functions at once::
+
+ echo sys_open > set_graph_function
+ echo sys_close >> set_graph_function
+
+Now if you want to go back to trace all functions you can clear
+this special filter via::
+
+ echo > set_graph_function
+
+
+ftrace_enabled
+--------------
+
+Note, the proc sysctl ftrace_enable is a big on/off switch for the
+function tracer. By default it is enabled (when function tracing is
+enabled in the kernel). If it is disabled, all function tracing is
+disabled. This includes not only the function tracers for ftrace, but
+also for any other uses (perf, kprobes, stack tracing, profiling, etc).
+
+Please disable this with care.
+
+This can be disable (and enabled) with::
+
+ sysctl kernel.ftrace_enabled=0
+ sysctl kernel.ftrace_enabled=1
+
+ or
+
+ echo 0 > /proc/sys/kernel/ftrace_enabled
+ echo 1 > /proc/sys/kernel/ftrace_enabled
+
+
+Filter commands
+---------------
+
+A few commands are supported by the set_ftrace_filter interface.
+Trace commands have the following format::
+
+ <function>:<command>:<parameter>
+
+The following commands are supported:
+
+- mod:
+ This command enables function filtering per module. The
+ parameter defines the module. For example, if only the write*
+ functions in the ext3 module are desired, run:
+
+ echo 'write*:mod:ext3' > set_ftrace_filter
+
+ This command interacts with the filter in the same way as
+ filtering based on function names. Thus, adding more functions
+ in a different module is accomplished by appending (>>) to the
+ filter file. Remove specific module functions by prepending
+ '!'::
+
+ echo '!writeback*:mod:ext3' >> set_ftrace_filter
+
+ Mod command supports module globbing. Disable tracing for all
+ functions except a specific module::
+
+ echo '!*:mod:!ext3' >> set_ftrace_filter
+
+ Disable tracing for all modules, but still trace kernel::
+
+ echo '!*:mod:*' >> set_ftrace_filter
+
+ Enable filter only for kernel::
+
+ echo '*write*:mod:!*' >> set_ftrace_filter
+
+ Enable filter for module globbing::
+
+ echo '*write*:mod:*snd*' >> set_ftrace_filter
+
+- traceon/traceoff:
+ These commands turn tracing on and off when the specified
+ functions are hit. The parameter determines how many times the
+ tracing system is turned on and off. If unspecified, there is
+ no limit. For example, to disable tracing when a schedule bug
+ is hit the first 5 times, run::
+
+ echo '__schedule_bug:traceoff:5' > set_ftrace_filter
+
+ To always disable tracing when __schedule_bug is hit::
+
+ echo '__schedule_bug:traceoff' > set_ftrace_filter
+
+ These commands are cumulative whether or not they are appended
+ to set_ftrace_filter. To remove a command, prepend it by '!'
+ and drop the parameter::
+
+ echo '!__schedule_bug:traceoff:0' > set_ftrace_filter
+
+ The above removes the traceoff command for __schedule_bug
+ that have a counter. To remove commands without counters::
+
+ echo '!__schedule_bug:traceoff' > set_ftrace_filter
+
+- snapshot:
+ Will cause a snapshot to be triggered when the function is hit.
+ ::
+
+ echo 'native_flush_tlb_others:snapshot' > set_ftrace_filter
+
+ To only snapshot once:
+ ::
+
+ echo 'native_flush_tlb_others:snapshot:1' > set_ftrace_filter
+
+ To remove the above commands::
+
+ echo '!native_flush_tlb_others:snapshot' > set_ftrace_filter
+ echo '!native_flush_tlb_others:snapshot:0' > set_ftrace_filter
+
+- enable_event/disable_event:
+ These commands can enable or disable a trace event. Note, because
+ function tracing callbacks are very sensitive, when these commands
+ are registered, the trace point is activated, but disabled in
+ a "soft" mode. That is, the tracepoint will be called, but
+ just will not be traced. The event tracepoint stays in this mode
+ as long as there's a command that triggers it.
+ ::
+
+ echo 'try_to_wake_up:enable_event:sched:sched_switch:2' > \
+ set_ftrace_filter
+
+ The format is::
+
+ <function>:enable_event:<system>:<event>[:count]
+ <function>:disable_event:<system>:<event>[:count]
+
+ To remove the events commands::
+
+ echo '!try_to_wake_up:enable_event:sched:sched_switch:0' > \
+ set_ftrace_filter
+ echo '!schedule:disable_event:sched:sched_switch' > \
+ set_ftrace_filter
+
+- dump:
+ When the function is hit, it will dump the contents of the ftrace
+ ring buffer to the console. This is useful if you need to debug
+ something, and want to dump the trace when a certain function
+ is hit. Perhaps its a function that is called before a tripple
+ fault happens and does not allow you to get a regular dump.
+
+- cpudump:
+ When the function is hit, it will dump the contents of the ftrace
+ ring buffer for the current CPU to the console. Unlike the "dump"
+ command, it only prints out the contents of the ring buffer for the
+ CPU that executed the function that triggered the dump.
+
+trace_pipe
+----------
+
+The trace_pipe outputs the same content as the trace file, but
+the effect on the tracing is different. Every read from
+trace_pipe is consumed. This means that subsequent reads will be
+different. The trace is live.
+::
+
+ # echo function > current_tracer
+ # cat trace_pipe > /tmp/trace.out &
+ [1] 4153
+ # echo 1 > tracing_on
+ # usleep 1
+ # echo 0 > tracing_on
+ # cat trace
+ # tracer: function
+ #
+ # entries-in-buffer/entries-written: 0/0 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+
+ #
+ # cat /tmp/trace.out
+ bash-1994 [000] .... 5281.568961: mutex_unlock <-rb_simple_write
+ bash-1994 [000] .... 5281.568963: __mutex_unlock_slowpath <-mutex_unlock
+ bash-1994 [000] .... 5281.568963: __fsnotify_parent <-fsnotify_modify
+ bash-1994 [000] .... 5281.568964: fsnotify <-fsnotify_modify
+ bash-1994 [000] .... 5281.568964: __srcu_read_lock <-fsnotify
+ bash-1994 [000] .... 5281.568964: add_preempt_count <-__srcu_read_lock
+ bash-1994 [000] ...1 5281.568965: sub_preempt_count <-__srcu_read_lock
+ bash-1994 [000] .... 5281.568965: __srcu_read_unlock <-fsnotify
+ bash-1994 [000] .... 5281.568967: sys_dup2 <-system_call_fastpath
+
+
+Note, reading the trace_pipe file will block until more input is
+added.
+
+trace entries
+-------------
+
+Having too much or not enough data can be troublesome in
+diagnosing an issue in the kernel. The file buffer_size_kb is
+used to modify the size of the internal trace buffers. The
+number listed is the number of entries that can be recorded per
+CPU. To know the full size, multiply the number of possible CPUs
+with the number of entries.
+::
+
+ # cat buffer_size_kb
+ 1408 (units kilobytes)
+
+Or simply read buffer_total_size_kb
+::
+
+ # cat buffer_total_size_kb
+ 5632
+
+To modify the buffer, simple echo in a number (in 1024 byte segments).
+::
+
+ # echo 10000 > buffer_size_kb
+ # cat buffer_size_kb
+ 10000 (units kilobytes)
+
+It will try to allocate as much as possible. If you allocate too
+much, it can cause Out-Of-Memory to trigger.
+::
+
+ # echo 1000000000000 > buffer_size_kb
+ -bash: echo: write error: Cannot allocate memory
+ # cat buffer_size_kb
+ 85
+
+The per_cpu buffers can be changed individually as well:
+::
+
+ # echo 10000 > per_cpu/cpu0/buffer_size_kb
+ # echo 100 > per_cpu/cpu1/buffer_size_kb
+
+When the per_cpu buffers are not the same, the buffer_size_kb
+at the top level will just show an X
+::
+
+ # cat buffer_size_kb
+ X
+
+This is where the buffer_total_size_kb is useful:
+::
+
+ # cat buffer_total_size_kb
+ 12916
+
+Writing to the top level buffer_size_kb will reset all the buffers
+to be the same again.
+
+Snapshot
+--------
+CONFIG_TRACER_SNAPSHOT makes a generic snapshot feature
+available to all non latency tracers. (Latency tracers which
+record max latency, such as "irqsoff" or "wakeup", can't use
+this feature, since those are already using the snapshot
+mechanism internally.)
+
+Snapshot preserves a current trace buffer at a particular point
+in time without stopping tracing. Ftrace swaps the current
+buffer with a spare buffer, and tracing continues in the new
+current (=previous spare) buffer.
+
+The following tracefs files in "tracing" are related to this
+feature:
+
+ snapshot:
+
+ This is used to take a snapshot and to read the output
+ of the snapshot. Echo 1 into this file to allocate a
+ spare buffer and to take a snapshot (swap), then read
+ the snapshot from this file in the same format as
+ "trace" (described above in the section "The File
+ System"). Both reads snapshot and tracing are executable
+ in parallel. When the spare buffer is allocated, echoing
+ 0 frees it, and echoing else (positive) values clear the
+ snapshot contents.
+ More details are shown in the table below.
+
+ +--------------+------------+------------+------------+
+ |status\\input | 0 | 1 | else |
+ +==============+============+============+============+
+ |not allocated |(do nothing)| alloc+swap |(do nothing)|
+ +--------------+------------+------------+------------+
+ |allocated | free | swap | clear |
+ +--------------+------------+------------+------------+
+
+Here is an example of using the snapshot feature.
+::
+
+ # echo 1 > events/sched/enable
+ # echo 1 > snapshot
+ # cat snapshot
+ # tracer: nop
+ #
+ # entries-in-buffer/entries-written: 71/71 #P:8
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ <idle>-0 [005] d... 2440.603828: sched_switch: prev_comm=swapper/5 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=snapshot-test-2 next_pid=2242 next_prio=120
+ sleep-2242 [005] d... 2440.603846: sched_switch: prev_comm=snapshot-test-2 prev_pid=2242 prev_prio=120 prev_state=R ==> next_comm=kworker/5:1 next_pid=60 next_prio=120
+ [...]
+ <idle>-0 [002] d... 2440.707230: sched_switch: prev_comm=swapper/2 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=snapshot-test-2 next_pid=2229 next_prio=120
+
+ # cat trace
+ # tracer: nop
+ #
+ # entries-in-buffer/entries-written: 77/77 #P:8
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ <idle>-0 [007] d... 2440.707395: sched_switch: prev_comm=swapper/7 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=snapshot-test-2 next_pid=2243 next_prio=120
+ snapshot-test-2-2229 [002] d... 2440.707438: sched_switch: prev_comm=snapshot-test-2 prev_pid=2229 prev_prio=120 prev_state=S ==> next_comm=swapper/2 next_pid=0 next_prio=120
+ [...]
+
+
+If you try to use this snapshot feature when current tracer is
+one of the latency tracers, you will get the following results.
+::
+
+ # echo wakeup > current_tracer
+ # echo 1 > snapshot
+ bash: echo: write error: Device or resource busy
+ # cat snapshot
+ cat: snapshot: Device or resource busy
+
+
+Instances
+---------
+In the tracefs tracing directory is a directory called "instances".
+This directory can have new directories created inside of it using
+mkdir, and removing directories with rmdir. The directory created
+with mkdir in this directory will already contain files and other
+directories after it is created.
+::
+
+ # mkdir instances/foo
+ # ls instances/foo
+ buffer_size_kb buffer_total_size_kb events free_buffer per_cpu
+ set_event snapshot trace trace_clock trace_marker trace_options
+ trace_pipe tracing_on
+
+As you can see, the new directory looks similar to the tracing directory
+itself. In fact, it is very similar, except that the buffer and
+events are agnostic from the main director, or from any other
+instances that are created.
+
+The files in the new directory work just like the files with the
+same name in the tracing directory except the buffer that is used
+is a separate and new buffer. The files affect that buffer but do not
+affect the main buffer with the exception of trace_options. Currently,
+the trace_options affect all instances and the top level buffer
+the same, but this may change in future releases. That is, options
+may become specific to the instance they reside in.
+
+Notice that none of the function tracer files are there, nor is
+current_tracer and available_tracers. This is because the buffers
+can currently only have events enabled for them.
+::
+
+ # mkdir instances/foo
+ # mkdir instances/bar
+ # mkdir instances/zoot
+ # echo 100000 > buffer_size_kb
+ # echo 1000 > instances/foo/buffer_size_kb
+ # echo 5000 > instances/bar/per_cpu/cpu1/buffer_size_kb
+ # echo function > current_trace
+ # echo 1 > instances/foo/events/sched/sched_wakeup/enable
+ # echo 1 > instances/foo/events/sched/sched_wakeup_new/enable
+ # echo 1 > instances/foo/events/sched/sched_switch/enable
+ # echo 1 > instances/bar/events/irq/enable
+ # echo 1 > instances/zoot/events/syscalls/enable
+ # cat trace_pipe
+ CPU:2 [LOST 11745 EVENTS]
+ bash-2044 [002] .... 10594.481032: _raw_spin_lock_irqsave <-get_page_from_freelist
+ bash-2044 [002] d... 10594.481032: add_preempt_count <-_raw_spin_lock_irqsave
+ bash-2044 [002] d..1 10594.481032: __rmqueue <-get_page_from_freelist
+ bash-2044 [002] d..1 10594.481033: _raw_spin_unlock <-get_page_from_freelist
+ bash-2044 [002] d..1 10594.481033: sub_preempt_count <-_raw_spin_unlock
+ bash-2044 [002] d... 10594.481033: get_pageblock_flags_group <-get_pageblock_migratetype
+ bash-2044 [002] d... 10594.481034: __mod_zone_page_state <-get_page_from_freelist
+ bash-2044 [002] d... 10594.481034: zone_statistics <-get_page_from_freelist
+ bash-2044 [002] d... 10594.481034: __inc_zone_state <-zone_statistics
+ bash-2044 [002] d... 10594.481034: __inc_zone_state <-zone_statistics
+ bash-2044 [002] .... 10594.481035: arch_dup_task_struct <-copy_process
+ [...]
+
+ # cat instances/foo/trace_pipe
+ bash-1998 [000] d..4 136.676759: sched_wakeup: comm=kworker/0:1 pid=59 prio=120 success=1 target_cpu=000
+ bash-1998 [000] dN.4 136.676760: sched_wakeup: comm=bash pid=1998 prio=120 success=1 target_cpu=000
+ <idle>-0 [003] d.h3 136.676906: sched_wakeup: comm=rcu_preempt pid=9 prio=120 success=1 target_cpu=003
+ <idle>-0 [003] d..3 136.676909: sched_switch: prev_comm=swapper/3 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=rcu_preempt next_pid=9 next_prio=120
+ rcu_preempt-9 [003] d..3 136.676916: sched_switch: prev_comm=rcu_preempt prev_pid=9 prev_prio=120 prev_state=S ==> next_comm=swapper/3 next_pid=0 next_prio=120
+ bash-1998 [000] d..4 136.677014: sched_wakeup: comm=kworker/0:1 pid=59 prio=120 success=1 target_cpu=000
+ bash-1998 [000] dN.4 136.677016: sched_wakeup: comm=bash pid=1998 prio=120 success=1 target_cpu=000
+ bash-1998 [000] d..3 136.677018: sched_switch: prev_comm=bash prev_pid=1998 prev_prio=120 prev_state=R+ ==> next_comm=kworker/0:1 next_pid=59 next_prio=120
+ kworker/0:1-59 [000] d..4 136.677022: sched_wakeup: comm=sshd pid=1995 prio=120 success=1 target_cpu=001
+ kworker/0:1-59 [000] d..3 136.677025: sched_switch: prev_comm=kworker/0:1 prev_pid=59 prev_prio=120 prev_state=S ==> next_comm=bash next_pid=1998 next_prio=120
+ [...]
+
+ # cat instances/bar/trace_pipe
+ migration/1-14 [001] d.h3 138.732674: softirq_raise: vec=3 [action=NET_RX]
+ <idle>-0 [001] dNh3 138.732725: softirq_raise: vec=3 [action=NET_RX]
+ bash-1998 [000] d.h1 138.733101: softirq_raise: vec=1 [action=TIMER]
+ bash-1998 [000] d.h1 138.733102: softirq_raise: vec=9 [action=RCU]
+ bash-1998 [000] ..s2 138.733105: softirq_entry: vec=1 [action=TIMER]
+ bash-1998 [000] ..s2 138.733106: softirq_exit: vec=1 [action=TIMER]
+ bash-1998 [000] ..s2 138.733106: softirq_entry: vec=9 [action=RCU]
+ bash-1998 [000] ..s2 138.733109: softirq_exit: vec=9 [action=RCU]
+ sshd-1995 [001] d.h1 138.733278: irq_handler_entry: irq=21 name=uhci_hcd:usb4
+ sshd-1995 [001] d.h1 138.733280: irq_handler_exit: irq=21 ret=unhandled
+ sshd-1995 [001] d.h1 138.733281: irq_handler_entry: irq=21 name=eth0
+ sshd-1995 [001] d.h1 138.733283: irq_handler_exit: irq=21 ret=handled
+ [...]
+
+ # cat instances/zoot/trace
+ # tracer: nop
+ #
+ # entries-in-buffer/entries-written: 18996/18996 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ bash-1998 [000] d... 140.733501: sys_write -> 0x2
+ bash-1998 [000] d... 140.733504: sys_dup2(oldfd: a, newfd: 1)
+ bash-1998 [000] d... 140.733506: sys_dup2 -> 0x1
+ bash-1998 [000] d... 140.733508: sys_fcntl(fd: a, cmd: 1, arg: 0)
+ bash-1998 [000] d... 140.733509: sys_fcntl -> 0x1
+ bash-1998 [000] d... 140.733510: sys_close(fd: a)
+ bash-1998 [000] d... 140.733510: sys_close -> 0x0
+ bash-1998 [000] d... 140.733514: sys_rt_sigprocmask(how: 0, nset: 0, oset: 6e2768, sigsetsize: 8)
+ bash-1998 [000] d... 140.733515: sys_rt_sigprocmask -> 0x0
+ bash-1998 [000] d... 140.733516: sys_rt_sigaction(sig: 2, act: 7fff718846f0, oact: 7fff71884650, sigsetsize: 8)
+ bash-1998 [000] d... 140.733516: sys_rt_sigaction -> 0x0
+
+You can see that the trace of the top most trace buffer shows only
+the function tracing. The foo instance displays wakeups and task
+switches.
+
+To remove the instances, simply delete their directories:
+::
+
+ # rmdir instances/foo
+ # rmdir instances/bar
+ # rmdir instances/zoot
+
+Note, if a process has a trace file open in one of the instance
+directories, the rmdir will fail with EBUSY.
+
+
+Stack trace
+-----------
+Since the kernel has a fixed sized stack, it is important not to
+waste it in functions. A kernel developer must be conscience of
+what they allocate on the stack. If they add too much, the system
+can be in danger of a stack overflow, and corruption will occur,
+usually leading to a system panic.
+
+There are some tools that check this, usually with interrupts
+periodically checking usage. But if you can perform a check
+at every function call that will become very useful. As ftrace provides
+a function tracer, it makes it convenient to check the stack size
+at every function call. This is enabled via the stack tracer.
+
+CONFIG_STACK_TRACER enables the ftrace stack tracing functionality.
+To enable it, write a '1' into /proc/sys/kernel/stack_tracer_enabled.
+::
+
+ # echo 1 > /proc/sys/kernel/stack_tracer_enabled
+
+You can also enable it from the kernel command line to trace
+the stack size of the kernel during boot up, by adding "stacktrace"
+to the kernel command line parameter.
+
+After running it for a few minutes, the output looks like:
+::
+
+ # cat stack_max_size
+ 2928
+
+ # cat stack_trace
+ Depth Size Location (18 entries)
+ ----- ---- --------
+ 0) 2928 224 update_sd_lb_stats+0xbc/0x4ac
+ 1) 2704 160 find_busiest_group+0x31/0x1f1
+ 2) 2544 256 load_balance+0xd9/0x662
+ 3) 2288 80 idle_balance+0xbb/0x130
+ 4) 2208 128 __schedule+0x26e/0x5b9
+ 5) 2080 16 schedule+0x64/0x66
+ 6) 2064 128 schedule_timeout+0x34/0xe0
+ 7) 1936 112 wait_for_common+0x97/0xf1
+ 8) 1824 16 wait_for_completion+0x1d/0x1f
+ 9) 1808 128 flush_work+0xfe/0x119
+ 10) 1680 16 tty_flush_to_ldisc+0x1e/0x20
+ 11) 1664 48 input_available_p+0x1d/0x5c
+ 12) 1616 48 n_tty_poll+0x6d/0x134
+ 13) 1568 64 tty_poll+0x64/0x7f
+ 14) 1504 880 do_select+0x31e/0x511
+ 15) 624 400 core_sys_select+0x177/0x216
+ 16) 224 96 sys_select+0x91/0xb9
+ 17) 128 128 system_call_fastpath+0x16/0x1b
+
+Note, if -mfentry is being used by gcc, functions get traced before
+they set up the stack frame. This means that leaf level functions
+are not tested by the stack tracer when -mfentry is used.
+
+Currently, -mfentry is used by gcc 4.6.0 and above on x86 only.
+
+More
+----
+More details can be found in the source code, in the `kernel/trace/*.c` files.
diff --git a/Documentation/trace/ftrace.txt b/Documentation/trace/ftrace.txt
deleted file mode 100644
index d4601df6e72e..000000000000
--- a/Documentation/trace/ftrace.txt
+++ /dev/null
@@ -1,3220 +0,0 @@
- ftrace - Function Tracer
- ========================
-
-Copyright 2008 Red Hat Inc.
- Author: Steven Rostedt <srostedt@redhat.com>
- License: The GNU Free Documentation License, Version 1.2
- (dual licensed under the GPL v2)
-Original Reviewers: Elias Oltmanns, Randy Dunlap, Andrew Morton,
- John Kacur, and David Teigland.
-Written for: 2.6.28-rc2
-Updated for: 3.10
-Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
-
-Introduction
-------------
-
-Ftrace is an internal tracer designed to help out developers and
-designers of systems to find what is going on inside the kernel.
-It can be used for debugging or analyzing latencies and
-performance issues that take place outside of user-space.
-
-Although ftrace is typically considered the function tracer, it
-is really a frame work of several assorted tracing utilities.
-There's latency tracing to examine what occurs between interrupts
-disabled and enabled, as well as for preemption and from a time
-a task is woken to the task is actually scheduled in.
-
-One of the most common uses of ftrace is the event tracing.
-Through out the kernel is hundreds of static event points that
-can be enabled via the tracefs file system to see what is
-going on in certain parts of the kernel.
-
-See events.txt for more information.
-
-
-Implementation Details
-----------------------
-
-See ftrace-design.txt for details for arch porters and such.
-
-
-The File System
----------------
-
-Ftrace uses the tracefs file system to hold the control files as
-well as the files to display output.
-
-When tracefs is configured into the kernel (which selecting any ftrace
-option will do) the directory /sys/kernel/tracing will be created. To mount
-this directory, you can add to your /etc/fstab file:
-
- tracefs /sys/kernel/tracing tracefs defaults 0 0
-
-Or you can mount it at run time with:
-
- mount -t tracefs nodev /sys/kernel/tracing
-
-For quicker access to that directory you may want to make a soft link to
-it:
-
- ln -s /sys/kernel/tracing /tracing
-
- *** NOTICE ***
-
-Before 4.1, all ftrace tracing control files were within the debugfs
-file system, which is typically located at /sys/kernel/debug/tracing.
-For backward compatibility, when mounting the debugfs file system,
-the tracefs file system will be automatically mounted at:
-
- /sys/kernel/debug/tracing
-
-All files located in the tracefs file system will be located in that
-debugfs file system directory as well.
-
- *** NOTICE ***
-
-Any selected ftrace option will also create the tracefs file system.
-The rest of the document will assume that you are in the ftrace directory
-(cd /sys/kernel/tracing) and will only concentrate on the files within that
-directory and not distract from the content with the extended
-"/sys/kernel/tracing" path name.
-
-That's it! (assuming that you have ftrace configured into your kernel)
-
-After mounting tracefs you will have access to the control and output files
-of ftrace. Here is a list of some of the key files:
-
-
- Note: all time values are in microseconds.
-
- current_tracer:
-
- This is used to set or display the current tracer
- that is configured.
-
- available_tracers:
-
- This holds the different types of tracers that
- have been compiled into the kernel. The
- tracers listed here can be configured by
- echoing their name into current_tracer.
-
- tracing_on:
-
- This sets or displays whether writing to the trace
- ring buffer is enabled. Echo 0 into this file to disable
- the tracer or 1 to enable it. Note, this only disables
- writing to the ring buffer, the tracing overhead may
- still be occurring.
-
- The kernel function tracing_off() can be used within the
- kernel to disable writing to the ring buffer, which will
- set this file to "0". User space can re-enable tracing by
- echoing "1" into the file.
-
- Note, the function and event trigger "traceoff" will also
- set this file to zero and stop tracing. Which can also
- be re-enabled by user space using this file.
-
- trace:
-
- This file holds the output of the trace in a human
- readable format (described below). Note, tracing is temporarily
- disabled while this file is being read (opened).
-
- trace_pipe:
-
- The output is the same as the "trace" file but this
- file is meant to be streamed with live tracing.
- Reads from this file will block until new data is
- retrieved. Unlike the "trace" file, this file is a
- consumer. This means reading from this file causes
- sequential reads to display more current data. Once
- data is read from this file, it is consumed, and
- will not be read again with a sequential read. The
- "trace" file is static, and if the tracer is not
- adding more data, it will display the same
- information every time it is read. This file will not
- disable tracing while being read.
-
- trace_options:
-
- This file lets the user control the amount of data
- that is displayed in one of the above output
- files. Options also exist to modify how a tracer
- or events work (stack traces, timestamps, etc).
-
- options:
-
- This is a directory that has a file for every available
- trace option (also in trace_options). Options may also be set
- or cleared by writing a "1" or "0" respectively into the
- corresponding file with the option name.
-
- tracing_max_latency:
-
- Some of the tracers record the max latency.
- For example, the maximum time that interrupts are disabled.
- The maximum time is saved in this file. The max trace will also be
- stored, and displayed by "trace". A new max trace will only be
- recorded if the latency is greater than the value in this file
- (in microseconds).
-
- By echoing in a time into this file, no latency will be recorded
- unless it is greater than the time in this file.
-
- tracing_thresh:
-
- Some latency tracers will record a trace whenever the
- latency is greater than the number in this file.
- Only active when the file contains a number greater than 0.
- (in microseconds)
-
- buffer_size_kb:
-
- This sets or displays the number of kilobytes each CPU
- buffer holds. By default, the trace buffers are the same size
- for each CPU. The displayed number is the size of the
- CPU buffer and not total size of all buffers. The
- trace buffers are allocated in pages (blocks of memory
- that the kernel uses for allocation, usually 4 KB in size).
- If the last page allocated has room for more bytes
- than requested, the rest of the page will be used,
- making the actual allocation bigger than requested or shown.
- ( Note, the size may not be a multiple of the page size
- due to buffer management meta-data. )
-
- Buffer sizes for individual CPUs may vary
- (see "per_cpu/cpu0/buffer_size_kb" below), and if they do
- this file will show "X".
-
- buffer_total_size_kb:
-
- This displays the total combined size of all the trace buffers.
-
- free_buffer:
-
- If a process is performing tracing, and the ring buffer should be
- shrunk "freed" when the process is finished, even if it were to be
- killed by a signal, this file can be used for that purpose. On close
- of this file, the ring buffer will be resized to its minimum size.
- Having a process that is tracing also open this file, when the process
- exits its file descriptor for this file will be closed, and in doing so,
- the ring buffer will be "freed".
-
- It may also stop tracing if disable_on_free option is set.
-
- tracing_cpumask:
-
- This is a mask that lets the user only trace on specified CPUs.
- The format is a hex string representing the CPUs.
-
- set_ftrace_filter:
-
- When dynamic ftrace is configured in (see the
- section below "dynamic ftrace"), the code is dynamically
- modified (code text rewrite) to disable calling of the
- function profiler (mcount). This lets tracing be configured
- in with practically no overhead in performance. This also
- has a side effect of enabling or disabling specific functions
- to be traced. Echoing names of functions into this file
- will limit the trace to only those functions.
-
- The functions listed in "available_filter_functions" are what
- can be written into this file.
-
- This interface also allows for commands to be used. See the
- "Filter commands" section for more details.
-
- set_ftrace_notrace:
-
- This has an effect opposite to that of
- set_ftrace_filter. Any function that is added here will not
- be traced. If a function exists in both set_ftrace_filter
- and set_ftrace_notrace, the function will _not_ be traced.
-
- set_ftrace_pid:
-
- Have the function tracer only trace the threads whose PID are
- listed in this file.
-
- If the "function-fork" option is set, then when a task whose
- PID is listed in this file forks, the child's PID will
- automatically be added to this file, and the child will be
- traced by the function tracer as well. This option will also
- cause PIDs of tasks that exit to be removed from the file.
-
- set_event_pid:
-
- Have the events only trace a task with a PID listed in this file.
- Note, sched_switch and sched_wake_up will also trace events
- listed in this file.
-
- To have the PIDs of children of tasks with their PID in this file
- added on fork, enable the "event-fork" option. That option will also
- cause the PIDs of tasks to be removed from this file when the task
- exits.
-
- set_graph_function:
-
- Functions listed in this file will cause the function graph
- tracer to only trace these functions and the functions that
- they call. (See the section "dynamic ftrace" for more details).
-
- set_graph_notrace:
-
- Similar to set_graph_function, but will disable function graph
- tracing when the function is hit until it exits the function.
- This makes it possible to ignore tracing functions that are called
- by a specific function.
-
- available_filter_functions:
-
- This lists the functions that ftrace has processed and can trace.
- These are the function names that you can pass to
- "set_ftrace_filter" or "set_ftrace_notrace".
- (See the section "dynamic ftrace" below for more details.)
-
- dyn_ftrace_total_info:
-
- This file is for debugging purposes. The number of functions that
- have been converted to nops and are available to be traced.
-
- enabled_functions:
-
- This file is more for debugging ftrace, but can also be useful
- in seeing if any function has a callback attached to it.
- Not only does the trace infrastructure use ftrace function
- trace utility, but other subsystems might too. This file
- displays all functions that have a callback attached to them
- as well as the number of callbacks that have been attached.
- Note, a callback may also call multiple functions which will
- not be listed in this count.
-
- If the callback registered to be traced by a function with
- the "save regs" attribute (thus even more overhead), a 'R'
- will be displayed on the same line as the function that
- is returning registers.
-
- If the callback registered to be traced by a function with
- the "ip modify" attribute (thus the regs->ip can be changed),
- an 'I' will be displayed on the same line as the function that
- can be overridden.
-
- If the architecture supports it, it will also show what callback
- is being directly called by the function. If the count is greater
- than 1 it most likely will be ftrace_ops_list_func().
-
- If the callback of the function jumps to a trampoline that is
- specific to a the callback and not the standard trampoline,
- its address will be printed as well as the function that the
- trampoline calls.
-
- function_profile_enabled:
-
- When set it will enable all functions with either the function
- tracer, or if configured, the function graph tracer. It will
- keep a histogram of the number of functions that were called
- and if the function graph tracer was configured, it will also keep
- track of the time spent in those functions. The histogram
- content can be displayed in the files:
-
- trace_stats/function<cpu> ( function0, function1, etc).
-
- trace_stats:
-
- A directory that holds different tracing stats.
-
- kprobe_events:
-
- Enable dynamic trace points. See kprobetrace.txt.
-
- kprobe_profile:
-
- Dynamic trace points stats. See kprobetrace.txt.
-
- max_graph_depth:
-
- Used with the function graph tracer. This is the max depth
- it will trace into a function. Setting this to a value of
- one will show only the first kernel function that is called
- from user space.
-
- printk_formats:
-
- This is for tools that read the raw format files. If an event in
- the ring buffer references a string, only a pointer to the string
- is recorded into the buffer and not the string itself. This prevents
- tools from knowing what that string was. This file displays the string
- and address for the string allowing tools to map the pointers to what
- the strings were.
-
- saved_cmdlines:
-
- Only the pid of the task is recorded in a trace event unless
- the event specifically saves the task comm as well. Ftrace
- makes a cache of pid mappings to comms to try to display
- comms for events. If a pid for a comm is not listed, then
- "<...>" is displayed in the output.
-
- If the option "record-cmd" is set to "0", then comms of tasks
- will not be saved during recording. By default, it is enabled.
-
- saved_cmdlines_size:
-
- By default, 128 comms are saved (see "saved_cmdlines" above). To
- increase or decrease the amount of comms that are cached, echo
- in a the number of comms to cache, into this file.
-
- saved_tgids:
-
- If the option "record-tgid" is set, on each scheduling context switch
- the Task Group ID of a task is saved in a table mapping the PID of
- the thread to its TGID. By default, the "record-tgid" option is
- disabled.
-
- snapshot:
-
- This displays the "snapshot" buffer and also lets the user
- take a snapshot of the current running trace.
- See the "Snapshot" section below for more details.
-
- stack_max_size:
-
- When the stack tracer is activated, this will display the
- maximum stack size it has encountered.
- See the "Stack Trace" section below.
-
- stack_trace:
-
- This displays the stack back trace of the largest stack
- that was encountered when the stack tracer is activated.
- See the "Stack Trace" section below.
-
- stack_trace_filter:
-
- This is similar to "set_ftrace_filter" but it limits what
- functions the stack tracer will check.
-
- trace_clock:
-
- Whenever an event is recorded into the ring buffer, a
- "timestamp" is added. This stamp comes from a specified
- clock. By default, ftrace uses the "local" clock. This
- clock is very fast and strictly per cpu, but on some
- systems it may not be monotonic with respect to other
- CPUs. In other words, the local clocks may not be in sync
- with local clocks on other CPUs.
-
- Usual clocks for tracing:
-
- # cat trace_clock
- [local] global counter x86-tsc
-
- The clock with the square brackets around it is the one
- in effect.
-
- local: Default clock, but may not be in sync across CPUs
-
- global: This clock is in sync with all CPUs but may
- be a bit slower than the local clock.
-
- counter: This is not a clock at all, but literally an atomic
- counter. It counts up one by one, but is in sync
- with all CPUs. This is useful when you need to
- know exactly the order events occurred with respect to
- each other on different CPUs.
-
- uptime: This uses the jiffies counter and the time stamp
- is relative to the time since boot up.
-
- perf: This makes ftrace use the same clock that perf uses.
- Eventually perf will be able to read ftrace buffers
- and this will help out in interleaving the data.
-
- x86-tsc: Architectures may define their own clocks. For
- example, x86 uses its own TSC cycle clock here.
-
- ppc-tb: This uses the powerpc timebase register value.
- This is in sync across CPUs and can also be used
- to correlate events across hypervisor/guest if
- tb_offset is known.
-
- mono: This uses the fast monotonic clock (CLOCK_MONOTONIC)
- which is monotonic and is subject to NTP rate adjustments.
-
- mono_raw:
- This is the raw monotonic clock (CLOCK_MONOTONIC_RAW)
- which is montonic but is not subject to any rate adjustments
- and ticks at the same rate as the hardware clocksource.
-
- boot: This is the boot clock (CLOCK_BOOTTIME) and is based on the
- fast monotonic clock, but also accounts for time spent in
- suspend. Since the clock access is designed for use in
- tracing in the suspend path, some side effects are possible
- if clock is accessed after the suspend time is accounted before
- the fast mono clock is updated. In this case, the clock update
- appears to happen slightly sooner than it normally would have.
- Also on 32-bit systems, it's possible that the 64-bit boot offset
- sees a partial update. These effects are rare and post
- processing should be able to handle them. See comments in the
- ktime_get_boot_fast_ns() function for more information.
-
- To set a clock, simply echo the clock name into this file.
-
- echo global > trace_clock
-
- trace_marker:
-
- This is a very useful file for synchronizing user space
- with events happening in the kernel. Writing strings into
- this file will be written into the ftrace buffer.
-
- It is useful in applications to open this file at the start
- of the application and just reference the file descriptor
- for the file.
-
- void trace_write(const char *fmt, ...)
- {
- va_list ap;
- char buf[256];
- int n;
-
- if (trace_fd < 0)
- return;
-
- va_start(ap, fmt);
- n = vsnprintf(buf, 256, fmt, ap);
- va_end(ap);
-
- write(trace_fd, buf, n);
- }
-
- start:
-
- trace_fd = open("trace_marker", WR_ONLY);
-
- trace_marker_raw:
-
- This is similar to trace_marker above, but is meant for for binary data
- to be written to it, where a tool can be used to parse the data
- from trace_pipe_raw.
-
- uprobe_events:
-
- Add dynamic tracepoints in programs.
- See uprobetracer.txt
-
- uprobe_profile:
-
- Uprobe statistics. See uprobetrace.txt
-
- instances:
-
- This is a way to make multiple trace buffers where different
- events can be recorded in different buffers.
- See "Instances" section below.
-
- events:
-
- This is the trace event directory. It holds event tracepoints
- (also known as static tracepoints) that have been compiled
- into the kernel. It shows what event tracepoints exist
- and how they are grouped by system. There are "enable"
- files at various levels that can enable the tracepoints
- when a "1" is written to them.
-
- See events.txt for more information.
-
- set_event:
-
- By echoing in the event into this file, will enable that event.
-
- See events.txt for more information.
-
- available_events:
-
- A list of events that can be enabled in tracing.
-
- See events.txt for more information.
-
- hwlat_detector:
-
- Directory for the Hardware Latency Detector.
- See "Hardware Latency Detector" section below.
-
- per_cpu:
-
- This is a directory that contains the trace per_cpu information.
-
- per_cpu/cpu0/buffer_size_kb:
-
- The ftrace buffer is defined per_cpu. That is, there's a separate
- buffer for each CPU to allow writes to be done atomically,
- and free from cache bouncing. These buffers may have different
- size buffers. This file is similar to the buffer_size_kb
- file, but it only displays or sets the buffer size for the
- specific CPU. (here cpu0).
-
- per_cpu/cpu0/trace:
-
- This is similar to the "trace" file, but it will only display
- the data specific for the CPU. If written to, it only clears
- the specific CPU buffer.
-
- per_cpu/cpu0/trace_pipe
-
- This is similar to the "trace_pipe" file, and is a consuming
- read, but it will only display (and consume) the data specific
- for the CPU.
-
- per_cpu/cpu0/trace_pipe_raw
-
- For tools that can parse the ftrace ring buffer binary format,
- the trace_pipe_raw file can be used to extract the data
- from the ring buffer directly. With the use of the splice()
- system call, the buffer data can be quickly transferred to
- a file or to the network where a server is collecting the
- data.
-
- Like trace_pipe, this is a consuming reader, where multiple
- reads will always produce different data.
-
- per_cpu/cpu0/snapshot:
-
- This is similar to the main "snapshot" file, but will only
- snapshot the current CPU (if supported). It only displays
- the content of the snapshot for a given CPU, and if
- written to, only clears this CPU buffer.
-
- per_cpu/cpu0/snapshot_raw:
-
- Similar to the trace_pipe_raw, but will read the binary format
- from the snapshot buffer for the given CPU.
-
- per_cpu/cpu0/stats:
-
- This displays certain stats about the ring buffer:
-
- entries: The number of events that are still in the buffer.
-
- overrun: The number of lost events due to overwriting when
- the buffer was full.
-
- commit overrun: Should always be zero.
- This gets set if so many events happened within a nested
- event (ring buffer is re-entrant), that it fills the
- buffer and starts dropping events.
-
- bytes: Bytes actually read (not overwritten).
-
- oldest event ts: The oldest timestamp in the buffer
-
- now ts: The current timestamp
-
- dropped events: Events lost due to overwrite option being off.
-
- read events: The number of events read.
-
-The Tracers
------------
-
-Here is the list of current tracers that may be configured.
-
- "function"
-
- Function call tracer to trace all kernel functions.
-
- "function_graph"
-
- Similar to the function tracer except that the
- function tracer probes the functions on their entry
- whereas the function graph tracer traces on both entry
- and exit of the functions. It then provides the ability
- to draw a graph of function calls similar to C code
- source.
-
- "blk"
-
- The block tracer. The tracer used by the blktrace user
- application.
-
- "hwlat"
-
- The Hardware Latency tracer is used to detect if the hardware
- produces any latency. See "Hardware Latency Detector" section
- below.
-
- "irqsoff"
-
- Traces the areas that disable interrupts and saves
- the trace with the longest max latency.
- See tracing_max_latency. When a new max is recorded,
- it replaces the old trace. It is best to view this
- trace with the latency-format option enabled, which
- happens automatically when the tracer is selected.
-
- "preemptoff"
-
- Similar to irqsoff but traces and records the amount of
- time for which preemption is disabled.
-
- "preemptirqsoff"
-
- Similar to irqsoff and preemptoff, but traces and
- records the largest time for which irqs and/or preemption
- is disabled.
-
- "wakeup"
-
- Traces and records the max latency that it takes for
- the highest priority task to get scheduled after
- it has been woken up.
- Traces all tasks as an average developer would expect.
-
- "wakeup_rt"
-
- Traces and records the max latency that it takes for just
- RT tasks (as the current "wakeup" does). This is useful
- for those interested in wake up timings of RT tasks.
-
- "wakeup_dl"
-
- Traces and records the max latency that it takes for
- a SCHED_DEADLINE task to be woken (as the "wakeup" and
- "wakeup_rt" does).
-
- "mmiotrace"
-
- A special tracer that is used to trace binary module.
- It will trace all the calls that a module makes to the
- hardware. Everything it writes and reads from the I/O
- as well.
-
- "branch"
-
- This tracer can be configured when tracing likely/unlikely
- calls within the kernel. It will trace when a likely and
- unlikely branch is hit and if it was correct in its prediction
- of being correct.
-
- "nop"
-
- This is the "trace nothing" tracer. To remove all
- tracers from tracing simply echo "nop" into
- current_tracer.
-
-
-Examples of using the tracer
-----------------------------
-
-Here are typical examples of using the tracers when controlling
-them only with the tracefs interface (without using any
-user-land utilities).
-
-Output format:
---------------
-
-Here is an example of the output format of the file "trace"
-
- --------
-# tracer: function
-#
-# entries-in-buffer/entries-written: 140080/250280 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- bash-1977 [000] .... 17284.993652: sys_close <-system_call_fastpath
- bash-1977 [000] .... 17284.993653: __close_fd <-sys_close
- bash-1977 [000] .... 17284.993653: _raw_spin_lock <-__close_fd
- sshd-1974 [003] .... 17284.993653: __srcu_read_unlock <-fsnotify
- bash-1977 [000] .... 17284.993654: add_preempt_count <-_raw_spin_lock
- bash-1977 [000] ...1 17284.993655: _raw_spin_unlock <-__close_fd
- bash-1977 [000] ...1 17284.993656: sub_preempt_count <-_raw_spin_unlock
- bash-1977 [000] .... 17284.993657: filp_close <-__close_fd
- bash-1977 [000] .... 17284.993657: dnotify_flush <-filp_close
- sshd-1974 [003] .... 17284.993658: sys_select <-system_call_fastpath
- --------
-
-A header is printed with the tracer name that is represented by
-the trace. In this case the tracer is "function". Then it shows the
-number of events in the buffer as well as the total number of entries
-that were written. The difference is the number of entries that were
-lost due to the buffer filling up (250280 - 140080 = 110200 events
-lost).
-
-The header explains the content of the events. Task name "bash", the task
-PID "1977", the CPU that it was running on "000", the latency format
-(explained below), the timestamp in <secs>.<usecs> format, the
-function name that was traced "sys_close" and the parent function that
-called this function "system_call_fastpath". The timestamp is the time
-at which the function was entered.
-
-Latency trace format
---------------------
-
-When the latency-format option is enabled or when one of the latency
-tracers is set, the trace file gives somewhat more information to see
-why a latency happened. Here is a typical trace.
-
-# tracer: irqsoff
-#
-# irqsoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 259 us, #4/4, CPU#2 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: ps-6143 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: __lock_task_sighand
-# => ended at: _raw_spin_unlock_irqrestore
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- ps-6143 2d... 0us!: trace_hardirqs_off <-__lock_task_sighand
- ps-6143 2d..1 259us+: trace_hardirqs_on <-_raw_spin_unlock_irqrestore
- ps-6143 2d..1 263us+: time_hardirqs_on <-_raw_spin_unlock_irqrestore
- ps-6143 2d..1 306us : <stack trace>
- => trace_hardirqs_on_caller
- => trace_hardirqs_on
- => _raw_spin_unlock_irqrestore
- => do_task_stat
- => proc_tgid_stat
- => proc_single_show
- => seq_read
- => vfs_read
- => sys_read
- => system_call_fastpath
-
-
-This shows that the current tracer is "irqsoff" tracing the time
-for which interrupts were disabled. It gives the trace version (which
-never changes) and the version of the kernel upon which this was executed on
-(3.8). Then it displays the max latency in microseconds (259 us). The number
-of trace entries displayed and the total number (both are four: #4/4).
-VP, KP, SP, and HP are always zero and are reserved for later use.
-#P is the number of online CPUs (#P:4).
-
-The task is the process that was running when the latency
-occurred. (ps pid: 6143).
-
-The start and stop (the functions in which the interrupts were
-disabled and enabled respectively) that caused the latencies:
-
- __lock_task_sighand is where the interrupts were disabled.
- _raw_spin_unlock_irqrestore is where they were enabled again.
-
-The next lines after the header are the trace itself. The header
-explains which is which.
-
- cmd: The name of the process in the trace.
-
- pid: The PID of that process.
-
- CPU#: The CPU which the process was running on.
-
- irqs-off: 'd' interrupts are disabled. '.' otherwise.
- Note: If the architecture does not support a way to
- read the irq flags variable, an 'X' will always
- be printed here.
-
- need-resched:
- 'N' both TIF_NEED_RESCHED and PREEMPT_NEED_RESCHED is set,
- 'n' only TIF_NEED_RESCHED is set,
- 'p' only PREEMPT_NEED_RESCHED is set,
- '.' otherwise.
-
- hardirq/softirq:
- 'Z' - NMI occurred inside a hardirq
- 'z' - NMI is running
- 'H' - hard irq occurred inside a softirq.
- 'h' - hard irq is running
- 's' - soft irq is running
- '.' - normal context.
-
- preempt-depth: The level of preempt_disabled
-
-The above is mostly meaningful for kernel developers.
-
- time: When the latency-format option is enabled, the trace file
- output includes a timestamp relative to the start of the
- trace. This differs from the output when latency-format
- is disabled, which includes an absolute timestamp.
-
- delay: This is just to help catch your eye a bit better. And
- needs to be fixed to be only relative to the same CPU.
- The marks are determined by the difference between this
- current trace and the next trace.
- '$' - greater than 1 second
- '@' - greater than 100 milisecond
- '*' - greater than 10 milisecond
- '#' - greater than 1000 microsecond
- '!' - greater than 100 microsecond
- '+' - greater than 10 microsecond
- ' ' - less than or equal to 10 microsecond.
-
- The rest is the same as the 'trace' file.
-
- Note, the latency tracers will usually end with a back trace
- to easily find where the latency occurred.
-
-trace_options
--------------
-
-The trace_options file (or the options directory) is used to control
-what gets printed in the trace output, or manipulate the tracers.
-To see what is available, simply cat the file:
-
- cat trace_options
-print-parent
-nosym-offset
-nosym-addr
-noverbose
-noraw
-nohex
-nobin
-noblock
-trace_printk
-annotate
-nouserstacktrace
-nosym-userobj
-noprintk-msg-only
-context-info
-nolatency-format
-record-cmd
-norecord-tgid
-overwrite
-nodisable_on_free
-irq-info
-markers
-noevent-fork
-function-trace
-nofunction-fork
-nodisplay-graph
-nostacktrace
-nobranch
-
-To disable one of the options, echo in the option prepended with
-"no".
-
- echo noprint-parent > trace_options
-
-To enable an option, leave off the "no".
-
- echo sym-offset > trace_options
-
-Here are the available options:
-
- print-parent - On function traces, display the calling (parent)
- function as well as the function being traced.
-
- print-parent:
- bash-4000 [01] 1477.606694: simple_strtoul <-kstrtoul
-
- noprint-parent:
- bash-4000 [01] 1477.606694: simple_strtoul
-
-
- sym-offset - Display not only the function name, but also the
- offset in the function. For example, instead of
- seeing just "ktime_get", you will see
- "ktime_get+0xb/0x20".
-
- sym-offset:
- bash-4000 [01] 1477.606694: simple_strtoul+0x6/0xa0
-
- sym-addr - this will also display the function address as well
- as the function name.
-
- sym-addr:
- bash-4000 [01] 1477.606694: simple_strtoul <c0339346>
-
- verbose - This deals with the trace file when the
- latency-format option is enabled.
-
- bash 4000 1 0 00000000 00010a95 [58127d26] 1720.415ms \
- (+0.000ms): simple_strtoul (kstrtoul)
-
- raw - This will display raw numbers. This option is best for
- use with user applications that can translate the raw
- numbers better than having it done in the kernel.
-
- hex - Similar to raw, but the numbers will be in a hexadecimal
- format.
-
- bin - This will print out the formats in raw binary.
-
- block - When set, reading trace_pipe will not block when polled.
-
- trace_printk - Can disable trace_printk() from writing into the buffer.
-
- annotate - It is sometimes confusing when the CPU buffers are full
- and one CPU buffer had a lot of events recently, thus
- a shorter time frame, were another CPU may have only had
- a few events, which lets it have older events. When
- the trace is reported, it shows the oldest events first,
- and it may look like only one CPU ran (the one with the
- oldest events). When the annotate option is set, it will
- display when a new CPU buffer started:
-
- <idle>-0 [001] dNs4 21169.031481: wake_up_idle_cpu <-add_timer_on
- <idle>-0 [001] dNs4 21169.031482: _raw_spin_unlock_irqrestore <-add_timer_on
- <idle>-0 [001] .Ns4 21169.031484: sub_preempt_count <-_raw_spin_unlock_irqrestore
-##### CPU 2 buffer started ####
- <idle>-0 [002] .N.1 21169.031484: rcu_idle_exit <-cpu_idle
- <idle>-0 [001] .Ns3 21169.031484: _raw_spin_unlock <-clocksource_watchdog
- <idle>-0 [001] .Ns3 21169.031485: sub_preempt_count <-_raw_spin_unlock
-
- userstacktrace - This option changes the trace. It records a
- stacktrace of the current user space thread after
- each trace event.
-
- sym-userobj - when user stacktrace are enabled, look up which
- object the address belongs to, and print a
- relative address. This is especially useful when
- ASLR is on, otherwise you don't get a chance to
- resolve the address to object/file/line after
- the app is no longer running
-
- The lookup is performed when you read
- trace,trace_pipe. Example:
-
- a.out-1623 [000] 40874.465068: /root/a.out[+0x480] <-/root/a.out[+0
-x494] <- /root/a.out[+0x4a8] <- /lib/libc-2.7.so[+0x1e1a6]
-
-
- printk-msg-only - When set, trace_printk()s will only show the format
- and not their parameters (if trace_bprintk() or
- trace_bputs() was used to save the trace_printk()).
-
- context-info - Show only the event data. Hides the comm, PID,
- timestamp, CPU, and other useful data.
-
- latency-format - This option changes the trace output. When it is enabled,
- the trace displays additional information about the
- latency, as described in "Latency trace format".
-
- record-cmd - When any event or tracer is enabled, a hook is enabled
- in the sched_switch trace point to fill comm cache
- with mapped pids and comms. But this may cause some
- overhead, and if you only care about pids, and not the
- name of the task, disabling this option can lower the
- impact of tracing. See "saved_cmdlines".
-
- record-tgid - When any event or tracer is enabled, a hook is enabled
- in the sched_switch trace point to fill the cache of
- mapped Thread Group IDs (TGID) mapping to pids. See
- "saved_tgids".
-
- overwrite - This controls what happens when the trace buffer is
- full. If "1" (default), the oldest events are
- discarded and overwritten. If "0", then the newest
- events are discarded.
- (see per_cpu/cpu0/stats for overrun and dropped)
-
- disable_on_free - When the free_buffer is closed, tracing will
- stop (tracing_on set to 0).
-
- irq-info - Shows the interrupt, preempt count, need resched data.
- When disabled, the trace looks like:
-
-# tracer: function
-#
-# entries-in-buffer/entries-written: 144405/9452052 #P:4
-#
-# TASK-PID CPU# TIMESTAMP FUNCTION
-# | | | | |
- <idle>-0 [002] 23636.756054: ttwu_do_activate.constprop.89 <-try_to_wake_up
- <idle>-0 [002] 23636.756054: activate_task <-ttwu_do_activate.constprop.89
- <idle>-0 [002] 23636.756055: enqueue_task <-activate_task
-
-
- markers - When set, the trace_marker is writable (only by root).
- When disabled, the trace_marker will error with EINVAL
- on write.
-
- event-fork - When set, tasks with PIDs listed in set_event_pid will have
- the PIDs of their children added to set_event_pid when those
- tasks fork. Also, when tasks with PIDs in set_event_pid exit,
- their PIDs will be removed from the file.
-
- function-trace - The latency tracers will enable function tracing
- if this option is enabled (default it is). When
- it is disabled, the latency tracers do not trace
- functions. This keeps the overhead of the tracer down
- when performing latency tests.
-
- function-fork - When set, tasks with PIDs listed in set_ftrace_pid will
- have the PIDs of their children added to set_ftrace_pid
- when those tasks fork. Also, when tasks with PIDs in
- set_ftrace_pid exit, their PIDs will be removed from the
- file.
-
- display-graph - When set, the latency tracers (irqsoff, wakeup, etc) will
- use function graph tracing instead of function tracing.
-
- stacktrace - When set, a stack trace is recorded after any trace event
- is recorded.
-
- branch - Enable branch tracing with the tracer. This enables branch
- tracer along with the currently set tracer. Enabling this
- with the "nop" tracer is the same as just enabling the
- "branch" tracer.
-
- Note: Some tracers have their own options. They only appear in this
- file when the tracer is active. They always appear in the
- options directory.
-
-
-Here are the per tracer options:
-
-Options for function tracer:
-
- func_stack_trace - When set, a stack trace is recorded after every
- function that is recorded. NOTE! Limit the functions
- that are recorded before enabling this, with
- "set_ftrace_filter" otherwise the system performance
- will be critically degraded. Remember to disable
- this option before clearing the function filter.
-
-Options for function_graph tracer:
-
- Since the function_graph tracer has a slightly different output
- it has its own options to control what is displayed.
-
- funcgraph-overrun - When set, the "overrun" of the graph stack is
- displayed after each function traced. The
- overrun, is when the stack depth of the calls
- is greater than what is reserved for each task.
- Each task has a fixed array of functions to
- trace in the call graph. If the depth of the
- calls exceeds that, the function is not traced.
- The overrun is the number of functions missed
- due to exceeding this array.
-
- funcgraph-cpu - When set, the CPU number of the CPU where the trace
- occurred is displayed.
-
- funcgraph-overhead - When set, if the function takes longer than
- A certain amount, then a delay marker is
- displayed. See "delay" above, under the
- header description.
-
- funcgraph-proc - Unlike other tracers, the process' command line
- is not displayed by default, but instead only
- when a task is traced in and out during a context
- switch. Enabling this options has the command
- of each process displayed at every line.
-
- funcgraph-duration - At the end of each function (the return)
- the duration of the amount of time in the
- function is displayed in microseconds.
-
- funcgraph-abstime - When set, the timestamp is displayed at each
- line.
-
- funcgraph-irqs - When disabled, functions that happen inside an
- interrupt will not be traced.
-
- funcgraph-tail - When set, the return event will include the function
- that it represents. By default this is off, and
- only a closing curly bracket "}" is displayed for
- the return of a function.
-
- sleep-time - When running function graph tracer, to include
- the time a task schedules out in its function.
- When enabled, it will account time the task has been
- scheduled out as part of the function call.
-
- graph-time - When running function profiler with function graph tracer,
- to include the time to call nested functions. When this is
- not set, the time reported for the function will only
- include the time the function itself executed for, not the
- time for functions that it called.
-
-Options for blk tracer:
-
- blk_classic - Shows a more minimalistic output.
-
-
-irqsoff
--------
-
-When interrupts are disabled, the CPU can not react to any other
-external event (besides NMIs and SMIs). This prevents the timer
-interrupt from triggering or the mouse interrupt from letting
-the kernel know of a new mouse event. The result is a latency
-with the reaction time.
-
-The irqsoff tracer tracks the time for which interrupts are
-disabled. When a new maximum latency is hit, the tracer saves
-the trace leading up to that latency point so that every time a
-new maximum is reached, the old saved trace is discarded and the
-new trace is saved.
-
-To reset the maximum, echo 0 into tracing_max_latency. Here is
-an example:
-
- # echo 0 > options/function-trace
- # echo irqsoff > current_tracer
- # echo 1 > tracing_on
- # echo 0 > tracing_max_latency
- # ls -ltr
- [...]
- # echo 0 > tracing_on
- # cat trace
-# tracer: irqsoff
-#
-# irqsoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 16 us, #4/4, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: swapper/0-0 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: run_timer_softirq
-# => ended at: run_timer_softirq
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- <idle>-0 0d.s2 0us+: _raw_spin_lock_irq <-run_timer_softirq
- <idle>-0 0dNs3 17us : _raw_spin_unlock_irq <-run_timer_softirq
- <idle>-0 0dNs3 17us+: trace_hardirqs_on <-run_timer_softirq
- <idle>-0 0dNs3 25us : <stack trace>
- => _raw_spin_unlock_irq
- => run_timer_softirq
- => __do_softirq
- => call_softirq
- => do_softirq
- => irq_exit
- => smp_apic_timer_interrupt
- => apic_timer_interrupt
- => rcu_idle_exit
- => cpu_idle
- => rest_init
- => start_kernel
- => x86_64_start_reservations
- => x86_64_start_kernel
-
-Here we see that that we had a latency of 16 microseconds (which is
-very good). The _raw_spin_lock_irq in run_timer_softirq disabled
-interrupts. The difference between the 16 and the displayed
-timestamp 25us occurred because the clock was incremented
-between the time of recording the max latency and the time of
-recording the function that had that latency.
-
-Note the above example had function-trace not set. If we set
-function-trace, we get a much larger output:
-
- with echo 1 > options/function-trace
-
-# tracer: irqsoff
-#
-# irqsoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 71 us, #168/168, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: bash-2042 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: ata_scsi_queuecmd
-# => ended at: ata_scsi_queuecmd
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- bash-2042 3d... 0us : _raw_spin_lock_irqsave <-ata_scsi_queuecmd
- bash-2042 3d... 0us : add_preempt_count <-_raw_spin_lock_irqsave
- bash-2042 3d..1 1us : ata_scsi_find_dev <-ata_scsi_queuecmd
- bash-2042 3d..1 1us : __ata_scsi_find_dev <-ata_scsi_find_dev
- bash-2042 3d..1 2us : ata_find_dev.part.14 <-__ata_scsi_find_dev
- bash-2042 3d..1 2us : ata_qc_new_init <-__ata_scsi_queuecmd
- bash-2042 3d..1 3us : ata_sg_init <-__ata_scsi_queuecmd
- bash-2042 3d..1 4us : ata_scsi_rw_xlat <-__ata_scsi_queuecmd
- bash-2042 3d..1 4us : ata_build_rw_tf <-ata_scsi_rw_xlat
-[...]
- bash-2042 3d..1 67us : delay_tsc <-__delay
- bash-2042 3d..1 67us : add_preempt_count <-delay_tsc
- bash-2042 3d..2 67us : sub_preempt_count <-delay_tsc
- bash-2042 3d..1 67us : add_preempt_count <-delay_tsc
- bash-2042 3d..2 68us : sub_preempt_count <-delay_tsc
- bash-2042 3d..1 68us+: ata_bmdma_start <-ata_bmdma_qc_issue
- bash-2042 3d..1 71us : _raw_spin_unlock_irqrestore <-ata_scsi_queuecmd
- bash-2042 3d..1 71us : _raw_spin_unlock_irqrestore <-ata_scsi_queuecmd
- bash-2042 3d..1 72us+: trace_hardirqs_on <-ata_scsi_queuecmd
- bash-2042 3d..1 120us : <stack trace>
- => _raw_spin_unlock_irqrestore
- => ata_scsi_queuecmd
- => scsi_dispatch_cmd
- => scsi_request_fn
- => __blk_run_queue_uncond
- => __blk_run_queue
- => blk_queue_bio
- => generic_make_request
- => submit_bio
- => submit_bh
- => __ext3_get_inode_loc
- => ext3_iget
- => ext3_lookup
- => lookup_real
- => __lookup_hash
- => walk_component
- => lookup_last
- => path_lookupat
- => filename_lookup
- => user_path_at_empty
- => user_path_at
- => vfs_fstatat
- => vfs_stat
- => sys_newstat
- => system_call_fastpath
-
-
-Here we traced a 71 microsecond latency. But we also see all the
-functions that were called during that time. Note that by
-enabling function tracing, we incur an added overhead. This
-overhead may extend the latency times. But nevertheless, this
-trace has provided some very helpful debugging information.
-
-
-preemptoff
-----------
-
-When preemption is disabled, we may be able to receive
-interrupts but the task cannot be preempted and a higher
-priority task must wait for preemption to be enabled again
-before it can preempt a lower priority task.
-
-The preemptoff tracer traces the places that disable preemption.
-Like the irqsoff tracer, it records the maximum latency for
-which preemption was disabled. The control of preemptoff tracer
-is much like the irqsoff tracer.
-
- # echo 0 > options/function-trace
- # echo preemptoff > current_tracer
- # echo 1 > tracing_on
- # echo 0 > tracing_max_latency
- # ls -ltr
- [...]
- # echo 0 > tracing_on
- # cat trace
-# tracer: preemptoff
-#
-# preemptoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 46 us, #4/4, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: sshd-1991 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: do_IRQ
-# => ended at: do_IRQ
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- sshd-1991 1d.h. 0us+: irq_enter <-do_IRQ
- sshd-1991 1d..1 46us : irq_exit <-do_IRQ
- sshd-1991 1d..1 47us+: trace_preempt_on <-do_IRQ
- sshd-1991 1d..1 52us : <stack trace>
- => sub_preempt_count
- => irq_exit
- => do_IRQ
- => ret_from_intr
-
-
-This has some more changes. Preemption was disabled when an
-interrupt came in (notice the 'h'), and was enabled on exit.
-But we also see that interrupts have been disabled when entering
-the preempt off section and leaving it (the 'd'). We do not know if
-interrupts were enabled in the mean time or shortly after this
-was over.
-
-# tracer: preemptoff
-#
-# preemptoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 83 us, #241/241, CPU#1 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: bash-1994 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: wake_up_new_task
-# => ended at: task_rq_unlock
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- bash-1994 1d..1 0us : _raw_spin_lock_irqsave <-wake_up_new_task
- bash-1994 1d..1 0us : select_task_rq_fair <-select_task_rq
- bash-1994 1d..1 1us : __rcu_read_lock <-select_task_rq_fair
- bash-1994 1d..1 1us : source_load <-select_task_rq_fair
- bash-1994 1d..1 1us : source_load <-select_task_rq_fair
-[...]
- bash-1994 1d..1 12us : irq_enter <-smp_apic_timer_interrupt
- bash-1994 1d..1 12us : rcu_irq_enter <-irq_enter
- bash-1994 1d..1 13us : add_preempt_count <-irq_enter
- bash-1994 1d.h1 13us : exit_idle <-smp_apic_timer_interrupt
- bash-1994 1d.h1 13us : hrtimer_interrupt <-smp_apic_timer_interrupt
- bash-1994 1d.h1 13us : _raw_spin_lock <-hrtimer_interrupt
- bash-1994 1d.h1 14us : add_preempt_count <-_raw_spin_lock
- bash-1994 1d.h2 14us : ktime_get_update_offsets <-hrtimer_interrupt
-[...]
- bash-1994 1d.h1 35us : lapic_next_event <-clockevents_program_event
- bash-1994 1d.h1 35us : irq_exit <-smp_apic_timer_interrupt
- bash-1994 1d.h1 36us : sub_preempt_count <-irq_exit
- bash-1994 1d..2 36us : do_softirq <-irq_exit
- bash-1994 1d..2 36us : __do_softirq <-call_softirq
- bash-1994 1d..2 36us : __local_bh_disable <-__do_softirq
- bash-1994 1d.s2 37us : add_preempt_count <-_raw_spin_lock_irq
- bash-1994 1d.s3 38us : _raw_spin_unlock <-run_timer_softirq
- bash-1994 1d.s3 39us : sub_preempt_count <-_raw_spin_unlock
- bash-1994 1d.s2 39us : call_timer_fn <-run_timer_softirq
-[...]
- bash-1994 1dNs2 81us : cpu_needs_another_gp <-rcu_process_callbacks
- bash-1994 1dNs2 82us : __local_bh_enable <-__do_softirq
- bash-1994 1dNs2 82us : sub_preempt_count <-__local_bh_enable
- bash-1994 1dN.2 82us : idle_cpu <-irq_exit
- bash-1994 1dN.2 83us : rcu_irq_exit <-irq_exit
- bash-1994 1dN.2 83us : sub_preempt_count <-irq_exit
- bash-1994 1.N.1 84us : _raw_spin_unlock_irqrestore <-task_rq_unlock
- bash-1994 1.N.1 84us+: trace_preempt_on <-task_rq_unlock
- bash-1994 1.N.1 104us : <stack trace>
- => sub_preempt_count
- => _raw_spin_unlock_irqrestore
- => task_rq_unlock
- => wake_up_new_task
- => do_fork
- => sys_clone
- => stub_clone
-
-
-The above is an example of the preemptoff trace with
-function-trace set. Here we see that interrupts were not disabled
-the entire time. The irq_enter code lets us know that we entered
-an interrupt 'h'. Before that, the functions being traced still
-show that it is not in an interrupt, but we can see from the
-functions themselves that this is not the case.
-
-preemptirqsoff
---------------
-
-Knowing the locations that have interrupts disabled or
-preemption disabled for the longest times is helpful. But
-sometimes we would like to know when either preemption and/or
-interrupts are disabled.
-
-Consider the following code:
-
- local_irq_disable();
- call_function_with_irqs_off();
- preempt_disable();
- call_function_with_irqs_and_preemption_off();
- local_irq_enable();
- call_function_with_preemption_off();
- preempt_enable();
-
-The irqsoff tracer will record the total length of
-call_function_with_irqs_off() and
-call_function_with_irqs_and_preemption_off().
-
-The preemptoff tracer will record the total length of
-call_function_with_irqs_and_preemption_off() and
-call_function_with_preemption_off().
-
-But neither will trace the time that interrupts and/or
-preemption is disabled. This total time is the time that we can
-not schedule. To record this time, use the preemptirqsoff
-tracer.
-
-Again, using this trace is much like the irqsoff and preemptoff
-tracers.
-
- # echo 0 > options/function-trace
- # echo preemptirqsoff > current_tracer
- # echo 1 > tracing_on
- # echo 0 > tracing_max_latency
- # ls -ltr
- [...]
- # echo 0 > tracing_on
- # cat trace
-# tracer: preemptirqsoff
-#
-# preemptirqsoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 100 us, #4/4, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: ls-2230 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: ata_scsi_queuecmd
-# => ended at: ata_scsi_queuecmd
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- ls-2230 3d... 0us+: _raw_spin_lock_irqsave <-ata_scsi_queuecmd
- ls-2230 3...1 100us : _raw_spin_unlock_irqrestore <-ata_scsi_queuecmd
- ls-2230 3...1 101us+: trace_preempt_on <-ata_scsi_queuecmd
- ls-2230 3...1 111us : <stack trace>
- => sub_preempt_count
- => _raw_spin_unlock_irqrestore
- => ata_scsi_queuecmd
- => scsi_dispatch_cmd
- => scsi_request_fn
- => __blk_run_queue_uncond
- => __blk_run_queue
- => blk_queue_bio
- => generic_make_request
- => submit_bio
- => submit_bh
- => ext3_bread
- => ext3_dir_bread
- => htree_dirblock_to_tree
- => ext3_htree_fill_tree
- => ext3_readdir
- => vfs_readdir
- => sys_getdents
- => system_call_fastpath
-
-
-The trace_hardirqs_off_thunk is called from assembly on x86 when
-interrupts are disabled in the assembly code. Without the
-function tracing, we do not know if interrupts were enabled
-within the preemption points. We do see that it started with
-preemption enabled.
-
-Here is a trace with function-trace set:
-
-# tracer: preemptirqsoff
-#
-# preemptirqsoff latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 161 us, #339/339, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: ls-2269 (uid:0 nice:0 policy:0 rt_prio:0)
-# -----------------
-# => started at: schedule
-# => ended at: mutex_unlock
-#
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
-kworker/-59 3...1 0us : __schedule <-schedule
-kworker/-59 3d..1 0us : rcu_preempt_qs <-rcu_note_context_switch
-kworker/-59 3d..1 1us : add_preempt_count <-_raw_spin_lock_irq
-kworker/-59 3d..2 1us : deactivate_task <-__schedule
-kworker/-59 3d..2 1us : dequeue_task <-deactivate_task
-kworker/-59 3d..2 2us : update_rq_clock <-dequeue_task
-kworker/-59 3d..2 2us : dequeue_task_fair <-dequeue_task
-kworker/-59 3d..2 2us : update_curr <-dequeue_task_fair
-kworker/-59 3d..2 2us : update_min_vruntime <-update_curr
-kworker/-59 3d..2 3us : cpuacct_charge <-update_curr
-kworker/-59 3d..2 3us : __rcu_read_lock <-cpuacct_charge
-kworker/-59 3d..2 3us : __rcu_read_unlock <-cpuacct_charge
-kworker/-59 3d..2 3us : update_cfs_rq_blocked_load <-dequeue_task_fair
-kworker/-59 3d..2 4us : clear_buddies <-dequeue_task_fair
-kworker/-59 3d..2 4us : account_entity_dequeue <-dequeue_task_fair
-kworker/-59 3d..2 4us : update_min_vruntime <-dequeue_task_fair
-kworker/-59 3d..2 4us : update_cfs_shares <-dequeue_task_fair
-kworker/-59 3d..2 5us : hrtick_update <-dequeue_task_fair
-kworker/-59 3d..2 5us : wq_worker_sleeping <-__schedule
-kworker/-59 3d..2 5us : kthread_data <-wq_worker_sleeping
-kworker/-59 3d..2 5us : put_prev_task_fair <-__schedule
-kworker/-59 3d..2 6us : pick_next_task_fair <-pick_next_task
-kworker/-59 3d..2 6us : clear_buddies <-pick_next_task_fair
-kworker/-59 3d..2 6us : set_next_entity <-pick_next_task_fair
-kworker/-59 3d..2 6us : update_stats_wait_end <-set_next_entity
- ls-2269 3d..2 7us : finish_task_switch <-__schedule
- ls-2269 3d..2 7us : _raw_spin_unlock_irq <-finish_task_switch
- ls-2269 3d..2 8us : do_IRQ <-ret_from_intr
- ls-2269 3d..2 8us : irq_enter <-do_IRQ
- ls-2269 3d..2 8us : rcu_irq_enter <-irq_enter
- ls-2269 3d..2 9us : add_preempt_count <-irq_enter
- ls-2269 3d.h2 9us : exit_idle <-do_IRQ
-[...]
- ls-2269 3d.h3 20us : sub_preempt_count <-_raw_spin_unlock
- ls-2269 3d.h2 20us : irq_exit <-do_IRQ
- ls-2269 3d.h2 21us : sub_preempt_count <-irq_exit
- ls-2269 3d..3 21us : do_softirq <-irq_exit
- ls-2269 3d..3 21us : __do_softirq <-call_softirq
- ls-2269 3d..3 21us+: __local_bh_disable <-__do_softirq
- ls-2269 3d.s4 29us : sub_preempt_count <-_local_bh_enable_ip
- ls-2269 3d.s5 29us : sub_preempt_count <-_local_bh_enable_ip
- ls-2269 3d.s5 31us : do_IRQ <-ret_from_intr
- ls-2269 3d.s5 31us : irq_enter <-do_IRQ
- ls-2269 3d.s5 31us : rcu_irq_enter <-irq_enter
-[...]
- ls-2269 3d.s5 31us : rcu_irq_enter <-irq_enter
- ls-2269 3d.s5 32us : add_preempt_count <-irq_enter
- ls-2269 3d.H5 32us : exit_idle <-do_IRQ
- ls-2269 3d.H5 32us : handle_irq <-do_IRQ
- ls-2269 3d.H5 32us : irq_to_desc <-handle_irq
- ls-2269 3d.H5 33us : handle_fasteoi_irq <-handle_irq
-[...]
- ls-2269 3d.s5 158us : _raw_spin_unlock_irqrestore <-rtl8139_poll
- ls-2269 3d.s3 158us : net_rps_action_and_irq_enable.isra.65 <-net_rx_action
- ls-2269 3d.s3 159us : __local_bh_enable <-__do_softirq
- ls-2269 3d.s3 159us : sub_preempt_count <-__local_bh_enable
- ls-2269 3d..3 159us : idle_cpu <-irq_exit
- ls-2269 3d..3 159us : rcu_irq_exit <-irq_exit
- ls-2269 3d..3 160us : sub_preempt_count <-irq_exit
- ls-2269 3d... 161us : __mutex_unlock_slowpath <-mutex_unlock
- ls-2269 3d... 162us+: trace_hardirqs_on <-mutex_unlock
- ls-2269 3d... 186us : <stack trace>
- => __mutex_unlock_slowpath
- => mutex_unlock
- => process_output
- => n_tty_write
- => tty_write
- => vfs_write
- => sys_write
- => system_call_fastpath
-
-This is an interesting trace. It started with kworker running and
-scheduling out and ls taking over. But as soon as ls released the
-rq lock and enabled interrupts (but not preemption) an interrupt
-triggered. When the interrupt finished, it started running softirqs.
-But while the softirq was running, another interrupt triggered.
-When an interrupt is running inside a softirq, the annotation is 'H'.
-
-
-wakeup
-------
-
-One common case that people are interested in tracing is the
-time it takes for a task that is woken to actually wake up.
-Now for non Real-Time tasks, this can be arbitrary. But tracing
-it none the less can be interesting.
-
-Without function tracing:
-
- # echo 0 > options/function-trace
- # echo wakeup > current_tracer
- # echo 1 > tracing_on
- # echo 0 > tracing_max_latency
- # chrt -f 5 sleep 1
- # echo 0 > tracing_on
- # cat trace
-# tracer: wakeup
-#
-# wakeup latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 15 us, #4/4, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: kworker/3:1H-312 (uid:0 nice:-20 policy:0 rt_prio:0)
-# -----------------
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- <idle>-0 3dNs7 0us : 0:120:R + [003] 312:100:R kworker/3:1H
- <idle>-0 3dNs7 1us+: ttwu_do_activate.constprop.87 <-try_to_wake_up
- <idle>-0 3d..3 15us : __schedule <-schedule
- <idle>-0 3d..3 15us : 0:120:R ==> [003] 312:100:R kworker/3:1H
-
-The tracer only traces the highest priority task in the system
-to avoid tracing the normal circumstances. Here we see that
-the kworker with a nice priority of -20 (not very nice), took
-just 15 microseconds from the time it woke up, to the time it
-ran.
-
-Non Real-Time tasks are not that interesting. A more interesting
-trace is to concentrate only on Real-Time tasks.
-
-wakeup_rt
----------
-
-In a Real-Time environment it is very important to know the
-wakeup time it takes for the highest priority task that is woken
-up to the time that it executes. This is also known as "schedule
-latency". I stress the point that this is about RT tasks. It is
-also important to know the scheduling latency of non-RT tasks,
-but the average schedule latency is better for non-RT tasks.
-Tools like LatencyTop are more appropriate for such
-measurements.
-
-Real-Time environments are interested in the worst case latency.
-That is the longest latency it takes for something to happen,
-and not the average. We can have a very fast scheduler that may
-only have a large latency once in a while, but that would not
-work well with Real-Time tasks. The wakeup_rt tracer was designed
-to record the worst case wakeups of RT tasks. Non-RT tasks are
-not recorded because the tracer only records one worst case and
-tracing non-RT tasks that are unpredictable will overwrite the
-worst case latency of RT tasks (just run the normal wakeup
-tracer for a while to see that effect).
-
-Since this tracer only deals with RT tasks, we will run this
-slightly differently than we did with the previous tracers.
-Instead of performing an 'ls', we will run 'sleep 1' under
-'chrt' which changes the priority of the task.
-
- # echo 0 > options/function-trace
- # echo wakeup_rt > current_tracer
- # echo 1 > tracing_on
- # echo 0 > tracing_max_latency
- # chrt -f 5 sleep 1
- # echo 0 > tracing_on
- # cat trace
-# tracer: wakeup
-#
-# tracer: wakeup_rt
-#
-# wakeup_rt latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 5 us, #4/4, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: sleep-2389 (uid:0 nice:0 policy:1 rt_prio:5)
-# -----------------
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- <idle>-0 3d.h4 0us : 0:120:R + [003] 2389: 94:R sleep
- <idle>-0 3d.h4 1us+: ttwu_do_activate.constprop.87 <-try_to_wake_up
- <idle>-0 3d..3 5us : __schedule <-schedule
- <idle>-0 3d..3 5us : 0:120:R ==> [003] 2389: 94:R sleep
-
-
-Running this on an idle system, we see that it only took 5 microseconds
-to perform the task switch. Note, since the trace point in the schedule
-is before the actual "switch", we stop the tracing when the recorded task
-is about to schedule in. This may change if we add a new marker at the
-end of the scheduler.
-
-Notice that the recorded task is 'sleep' with the PID of 2389
-and it has an rt_prio of 5. This priority is user-space priority
-and not the internal kernel priority. The policy is 1 for
-SCHED_FIFO and 2 for SCHED_RR.
-
-Note, that the trace data shows the internal priority (99 - rtprio).
-
- <idle>-0 3d..3 5us : 0:120:R ==> [003] 2389: 94:R sleep
-
-The 0:120:R means idle was running with a nice priority of 0 (120 - 120)
-and in the running state 'R'. The sleep task was scheduled in with
-2389: 94:R. That is the priority is the kernel rtprio (99 - 5 = 94)
-and it too is in the running state.
-
-Doing the same with chrt -r 5 and function-trace set.
-
- echo 1 > options/function-trace
-
-# tracer: wakeup_rt
-#
-# wakeup_rt latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 29 us, #85/85, CPU#3 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: sleep-2448 (uid:0 nice:0 policy:1 rt_prio:5)
-# -----------------
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- <idle>-0 3d.h4 1us+: 0:120:R + [003] 2448: 94:R sleep
- <idle>-0 3d.h4 2us : ttwu_do_activate.constprop.87 <-try_to_wake_up
- <idle>-0 3d.h3 3us : check_preempt_curr <-ttwu_do_wakeup
- <idle>-0 3d.h3 3us : resched_curr <-check_preempt_curr
- <idle>-0 3dNh3 4us : task_woken_rt <-ttwu_do_wakeup
- <idle>-0 3dNh3 4us : _raw_spin_unlock <-try_to_wake_up
- <idle>-0 3dNh3 4us : sub_preempt_count <-_raw_spin_unlock
- <idle>-0 3dNh2 5us : ttwu_stat <-try_to_wake_up
- <idle>-0 3dNh2 5us : _raw_spin_unlock_irqrestore <-try_to_wake_up
- <idle>-0 3dNh2 6us : sub_preempt_count <-_raw_spin_unlock_irqrestore
- <idle>-0 3dNh1 6us : _raw_spin_lock <-__run_hrtimer
- <idle>-0 3dNh1 6us : add_preempt_count <-_raw_spin_lock
- <idle>-0 3dNh2 7us : _raw_spin_unlock <-hrtimer_interrupt
- <idle>-0 3dNh2 7us : sub_preempt_count <-_raw_spin_unlock
- <idle>-0 3dNh1 7us : tick_program_event <-hrtimer_interrupt
- <idle>-0 3dNh1 7us : clockevents_program_event <-tick_program_event
- <idle>-0 3dNh1 8us : ktime_get <-clockevents_program_event
- <idle>-0 3dNh1 8us : lapic_next_event <-clockevents_program_event
- <idle>-0 3dNh1 8us : irq_exit <-smp_apic_timer_interrupt
- <idle>-0 3dNh1 9us : sub_preempt_count <-irq_exit
- <idle>-0 3dN.2 9us : idle_cpu <-irq_exit
- <idle>-0 3dN.2 9us : rcu_irq_exit <-irq_exit
- <idle>-0 3dN.2 10us : rcu_eqs_enter_common.isra.45 <-rcu_irq_exit
- <idle>-0 3dN.2 10us : sub_preempt_count <-irq_exit
- <idle>-0 3.N.1 11us : rcu_idle_exit <-cpu_idle
- <idle>-0 3dN.1 11us : rcu_eqs_exit_common.isra.43 <-rcu_idle_exit
- <idle>-0 3.N.1 11us : tick_nohz_idle_exit <-cpu_idle
- <idle>-0 3dN.1 12us : menu_hrtimer_cancel <-tick_nohz_idle_exit
- <idle>-0 3dN.1 12us : ktime_get <-tick_nohz_idle_exit
- <idle>-0 3dN.1 12us : tick_do_update_jiffies64 <-tick_nohz_idle_exit
- <idle>-0 3dN.1 13us : cpu_load_update_nohz <-tick_nohz_idle_exit
- <idle>-0 3dN.1 13us : _raw_spin_lock <-cpu_load_update_nohz
- <idle>-0 3dN.1 13us : add_preempt_count <-_raw_spin_lock
- <idle>-0 3dN.2 13us : __cpu_load_update <-cpu_load_update_nohz
- <idle>-0 3dN.2 14us : sched_avg_update <-__cpu_load_update
- <idle>-0 3dN.2 14us : _raw_spin_unlock <-cpu_load_update_nohz
- <idle>-0 3dN.2 14us : sub_preempt_count <-_raw_spin_unlock
- <idle>-0 3dN.1 15us : calc_load_nohz_stop <-tick_nohz_idle_exit
- <idle>-0 3dN.1 15us : touch_softlockup_watchdog <-tick_nohz_idle_exit
- <idle>-0 3dN.1 15us : hrtimer_cancel <-tick_nohz_idle_exit
- <idle>-0 3dN.1 15us : hrtimer_try_to_cancel <-hrtimer_cancel
- <idle>-0 3dN.1 16us : lock_hrtimer_base.isra.18 <-hrtimer_try_to_cancel
- <idle>-0 3dN.1 16us : _raw_spin_lock_irqsave <-lock_hrtimer_base.isra.18
- <idle>-0 3dN.1 16us : add_preempt_count <-_raw_spin_lock_irqsave
- <idle>-0 3dN.2 17us : __remove_hrtimer <-remove_hrtimer.part.16
- <idle>-0 3dN.2 17us : hrtimer_force_reprogram <-__remove_hrtimer
- <idle>-0 3dN.2 17us : tick_program_event <-hrtimer_force_reprogram
- <idle>-0 3dN.2 18us : clockevents_program_event <-tick_program_event
- <idle>-0 3dN.2 18us : ktime_get <-clockevents_program_event
- <idle>-0 3dN.2 18us : lapic_next_event <-clockevents_program_event
- <idle>-0 3dN.2 19us : _raw_spin_unlock_irqrestore <-hrtimer_try_to_cancel
- <idle>-0 3dN.2 19us : sub_preempt_count <-_raw_spin_unlock_irqrestore
- <idle>-0 3dN.1 19us : hrtimer_forward <-tick_nohz_idle_exit
- <idle>-0 3dN.1 20us : ktime_add_safe <-hrtimer_forward
- <idle>-0 3dN.1 20us : ktime_add_safe <-hrtimer_forward
- <idle>-0 3dN.1 20us : hrtimer_start_range_ns <-hrtimer_start_expires.constprop.11
- <idle>-0 3dN.1 20us : __hrtimer_start_range_ns <-hrtimer_start_range_ns
- <idle>-0 3dN.1 21us : lock_hrtimer_base.isra.18 <-__hrtimer_start_range_ns
- <idle>-0 3dN.1 21us : _raw_spin_lock_irqsave <-lock_hrtimer_base.isra.18
- <idle>-0 3dN.1 21us : add_preempt_count <-_raw_spin_lock_irqsave
- <idle>-0 3dN.2 22us : ktime_add_safe <-__hrtimer_start_range_ns
- <idle>-0 3dN.2 22us : enqueue_hrtimer <-__hrtimer_start_range_ns
- <idle>-0 3dN.2 22us : tick_program_event <-__hrtimer_start_range_ns
- <idle>-0 3dN.2 23us : clockevents_program_event <-tick_program_event
- <idle>-0 3dN.2 23us : ktime_get <-clockevents_program_event
- <idle>-0 3dN.2 23us : lapic_next_event <-clockevents_program_event
- <idle>-0 3dN.2 24us : _raw_spin_unlock_irqrestore <-__hrtimer_start_range_ns
- <idle>-0 3dN.2 24us : sub_preempt_count <-_raw_spin_unlock_irqrestore
- <idle>-0 3dN.1 24us : account_idle_ticks <-tick_nohz_idle_exit
- <idle>-0 3dN.1 24us : account_idle_time <-account_idle_ticks
- <idle>-0 3.N.1 25us : sub_preempt_count <-cpu_idle
- <idle>-0 3.N.. 25us : schedule <-cpu_idle
- <idle>-0 3.N.. 25us : __schedule <-preempt_schedule
- <idle>-0 3.N.. 26us : add_preempt_count <-__schedule
- <idle>-0 3.N.1 26us : rcu_note_context_switch <-__schedule
- <idle>-0 3.N.1 26us : rcu_sched_qs <-rcu_note_context_switch
- <idle>-0 3dN.1 27us : rcu_preempt_qs <-rcu_note_context_switch
- <idle>-0 3.N.1 27us : _raw_spin_lock_irq <-__schedule
- <idle>-0 3dN.1 27us : add_preempt_count <-_raw_spin_lock_irq
- <idle>-0 3dN.2 28us : put_prev_task_idle <-__schedule
- <idle>-0 3dN.2 28us : pick_next_task_stop <-pick_next_task
- <idle>-0 3dN.2 28us : pick_next_task_rt <-pick_next_task
- <idle>-0 3dN.2 29us : dequeue_pushable_task <-pick_next_task_rt
- <idle>-0 3d..3 29us : __schedule <-preempt_schedule
- <idle>-0 3d..3 30us : 0:120:R ==> [003] 2448: 94:R sleep
-
-This isn't that big of a trace, even with function tracing enabled,
-so I included the entire trace.
-
-The interrupt went off while when the system was idle. Somewhere
-before task_woken_rt() was called, the NEED_RESCHED flag was set,
-this is indicated by the first occurrence of the 'N' flag.
-
-Latency tracing and events
---------------------------
-As function tracing can induce a much larger latency, but without
-seeing what happens within the latency it is hard to know what
-caused it. There is a middle ground, and that is with enabling
-events.
-
- # echo 0 > options/function-trace
- # echo wakeup_rt > current_tracer
- # echo 1 > events/enable
- # echo 1 > tracing_on
- # echo 0 > tracing_max_latency
- # chrt -f 5 sleep 1
- # echo 0 > tracing_on
- # cat trace
-# tracer: wakeup_rt
-#
-# wakeup_rt latency trace v1.1.5 on 3.8.0-test+
-# --------------------------------------------------------------------
-# latency: 6 us, #12/12, CPU#2 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
-# -----------------
-# | task: sleep-5882 (uid:0 nice:0 policy:1 rt_prio:5)
-# -----------------
-#
-# _------=> CPU#
-# / _-----=> irqs-off
-# | / _----=> need-resched
-# || / _---=> hardirq/softirq
-# ||| / _--=> preempt-depth
-# |||| / delay
-# cmd pid ||||| time | caller
-# \ / ||||| \ | /
- <idle>-0 2d.h4 0us : 0:120:R + [002] 5882: 94:R sleep
- <idle>-0 2d.h4 0us : ttwu_do_activate.constprop.87 <-try_to_wake_up
- <idle>-0 2d.h4 1us : sched_wakeup: comm=sleep pid=5882 prio=94 success=1 target_cpu=002
- <idle>-0 2dNh2 1us : hrtimer_expire_exit: hrtimer=ffff88007796feb8
- <idle>-0 2.N.2 2us : power_end: cpu_id=2
- <idle>-0 2.N.2 3us : cpu_idle: state=4294967295 cpu_id=2
- <idle>-0 2dN.3 4us : hrtimer_cancel: hrtimer=ffff88007d50d5e0
- <idle>-0 2dN.3 4us : hrtimer_start: hrtimer=ffff88007d50d5e0 function=tick_sched_timer expires=34311211000000 softexpires=34311211000000
- <idle>-0 2.N.2 5us : rcu_utilization: Start context switch
- <idle>-0 2.N.2 5us : rcu_utilization: End context switch
- <idle>-0 2d..3 6us : __schedule <-schedule
- <idle>-0 2d..3 6us : 0:120:R ==> [002] 5882: 94:R sleep
-
-
-Hardware Latency Detector
--------------------------
-
-The hardware latency detector is executed by enabling the "hwlat" tracer.
-
-NOTE, this tracer will affect the performance of the system as it will
-periodically make a CPU constantly busy with interrupts disabled.
-
- # echo hwlat > current_tracer
- # sleep 100
- # cat trace
-# tracer: hwlat
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- <...>-3638 [001] d... 19452.055471: #1 inner/outer(us): 12/14 ts:1499801089.066141940
- <...>-3638 [003] d... 19454.071354: #2 inner/outer(us): 11/9 ts:1499801091.082164365
- <...>-3638 [002] dn.. 19461.126852: #3 inner/outer(us): 12/9 ts:1499801098.138150062
- <...>-3638 [001] d... 19488.340960: #4 inner/outer(us): 8/12 ts:1499801125.354139633
- <...>-3638 [003] d... 19494.388553: #5 inner/outer(us): 8/12 ts:1499801131.402150961
- <...>-3638 [003] d... 19501.283419: #6 inner/outer(us): 0/12 ts:1499801138.297435289 nmi-total:4 nmi-count:1
-
-
-The above output is somewhat the same in the header. All events will have
-interrupts disabled 'd'. Under the FUNCTION title there is:
-
- #1 - This is the count of events recorded that were greater than the
- tracing_threshold (See below).
-
- inner/outer(us): 12/14
-
- This shows two numbers as "inner latency" and "outer latency". The test
- runs in a loop checking a timestamp twice. The latency detected within
- the two timestamps is the "inner latency" and the latency detected
- after the previous timestamp and the next timestamp in the loop is
- the "outer latency".
-
- ts:1499801089.066141940
-
- The absolute timestamp that the event happened.
-
- nmi-total:4 nmi-count:1
-
- On architectures that support it, if an NMI comes in during the
- test, the time spent in NMI is reported in "nmi-total" (in
- microseconds).
-
- All architectures that have NMIs will show the "nmi-count" if an
- NMI comes in during the test.
-
-hwlat files:
-
- tracing_threshold - This gets automatically set to "10" to represent 10
- microseconds. This is the threshold of latency that
- needs to be detected before the trace will be recorded.
-
- Note, when hwlat tracer is finished (another tracer is
- written into "current_tracer"), the original value for
- tracing_threshold is placed back into this file.
-
- hwlat_detector/width - The length of time the test runs with interrupts
- disabled.
-
- hwlat_detector/window - The length of time of the window which the test
- runs. That is, the test will run for "width"
- microseconds per "window" microseconds
-
- tracing_cpumask - When the test is started. A kernel thread is created that
- runs the test. This thread will alternate between CPUs
- listed in the tracing_cpumask between each period
- (one "window"). To limit the test to specific CPUs
- set the mask in this file to only the CPUs that the test
- should run on.
-
-function
---------
-
-This tracer is the function tracer. Enabling the function tracer
-can be done from the debug file system. Make sure the
-ftrace_enabled is set; otherwise this tracer is a nop.
-See the "ftrace_enabled" section below.
-
- # sysctl kernel.ftrace_enabled=1
- # echo function > current_tracer
- # echo 1 > tracing_on
- # usleep 1
- # echo 0 > tracing_on
- # cat trace
-# tracer: function
-#
-# entries-in-buffer/entries-written: 24799/24799 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- bash-1994 [002] .... 3082.063030: mutex_unlock <-rb_simple_write
- bash-1994 [002] .... 3082.063031: __mutex_unlock_slowpath <-mutex_unlock
- bash-1994 [002] .... 3082.063031: __fsnotify_parent <-fsnotify_modify
- bash-1994 [002] .... 3082.063032: fsnotify <-fsnotify_modify
- bash-1994 [002] .... 3082.063032: __srcu_read_lock <-fsnotify
- bash-1994 [002] .... 3082.063032: add_preempt_count <-__srcu_read_lock
- bash-1994 [002] ...1 3082.063032: sub_preempt_count <-__srcu_read_lock
- bash-1994 [002] .... 3082.063033: __srcu_read_unlock <-fsnotify
-[...]
-
-
-Note: function tracer uses ring buffers to store the above
-entries. The newest data may overwrite the oldest data.
-Sometimes using echo to stop the trace is not sufficient because
-the tracing could have overwritten the data that you wanted to
-record. For this reason, it is sometimes better to disable
-tracing directly from a program. This allows you to stop the
-tracing at the point that you hit the part that you are
-interested in. To disable the tracing directly from a C program,
-something like following code snippet can be used:
-
-int trace_fd;
-[...]
-int main(int argc, char *argv[]) {
- [...]
- trace_fd = open(tracing_file("tracing_on"), O_WRONLY);
- [...]
- if (condition_hit()) {
- write(trace_fd, "0", 1);
- }
- [...]
-}
-
-
-Single thread tracing
----------------------
-
-By writing into set_ftrace_pid you can trace a
-single thread. For example:
-
-# cat set_ftrace_pid
-no pid
-# echo 3111 > set_ftrace_pid
-# cat set_ftrace_pid
-3111
-# echo function > current_tracer
-# cat trace | head
- # tracer: function
- #
- # TASK-PID CPU# TIMESTAMP FUNCTION
- # | | | | |
- yum-updatesd-3111 [003] 1637.254676: finish_task_switch <-thread_return
- yum-updatesd-3111 [003] 1637.254681: hrtimer_cancel <-schedule_hrtimeout_range
- yum-updatesd-3111 [003] 1637.254682: hrtimer_try_to_cancel <-hrtimer_cancel
- yum-updatesd-3111 [003] 1637.254683: lock_hrtimer_base <-hrtimer_try_to_cancel
- yum-updatesd-3111 [003] 1637.254685: fget_light <-do_sys_poll
- yum-updatesd-3111 [003] 1637.254686: pipe_poll <-do_sys_poll
-# echo > set_ftrace_pid
-# cat trace |head
- # tracer: function
- #
- # TASK-PID CPU# TIMESTAMP FUNCTION
- # | | | | |
- ##### CPU 3 buffer started ####
- yum-updatesd-3111 [003] 1701.957688: free_poll_entry <-poll_freewait
- yum-updatesd-3111 [003] 1701.957689: remove_wait_queue <-free_poll_entry
- yum-updatesd-3111 [003] 1701.957691: fput <-free_poll_entry
- yum-updatesd-3111 [003] 1701.957692: audit_syscall_exit <-sysret_audit
- yum-updatesd-3111 [003] 1701.957693: path_put <-audit_syscall_exit
-
-If you want to trace a function when executing, you could use
-something like this simple program:
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <string.h>
-
-#define _STR(x) #x
-#define STR(x) _STR(x)
-#define MAX_PATH 256
-
-const char *find_tracefs(void)
-{
- static char tracefs[MAX_PATH+1];
- static int tracefs_found;
- char type[100];
- FILE *fp;
-
- if (tracefs_found)
- return tracefs;
-
- if ((fp = fopen("/proc/mounts","r")) == NULL) {
- perror("/proc/mounts");
- return NULL;
- }
-
- while (fscanf(fp, "%*s %"
- STR(MAX_PATH)
- "s %99s %*s %*d %*d\n",
- tracefs, type) == 2) {
- if (strcmp(type, "tracefs") == 0)
- break;
- }
- fclose(fp);
-
- if (strcmp(type, "tracefs") != 0) {
- fprintf(stderr, "tracefs not mounted");
- return NULL;
- }
-
- strcat(tracefs, "/tracing/");
- tracefs_found = 1;
-
- return tracefs;
-}
-
-const char *tracing_file(const char *file_name)
-{
- static char trace_file[MAX_PATH+1];
- snprintf(trace_file, MAX_PATH, "%s/%s", find_tracefs(), file_name);
- return trace_file;
-}
-
-int main (int argc, char **argv)
-{
- if (argc < 1)
- exit(-1);
-
- if (fork() > 0) {
- int fd, ffd;
- char line[64];
- int s;
-
- ffd = open(tracing_file("current_tracer"), O_WRONLY);
- if (ffd < 0)
- exit(-1);
- write(ffd, "nop", 3);
-
- fd = open(tracing_file("set_ftrace_pid"), O_WRONLY);
- s = sprintf(line, "%d\n", getpid());
- write(fd, line, s);
-
- write(ffd, "function", 8);
-
- close(fd);
- close(ffd);
-
- execvp(argv[1], argv+1);
- }
-
- return 0;
-}
-
-Or this simple script!
-
-------
-#!/bin/bash
-
-tracefs=`sed -ne 's/^tracefs \(.*\) tracefs.*/\1/p' /proc/mounts`
-echo nop > $tracefs/tracing/current_tracer
-echo 0 > $tracefs/tracing/tracing_on
-echo $$ > $tracefs/tracing/set_ftrace_pid
-echo function > $tracefs/tracing/current_tracer
-echo 1 > $tracefs/tracing/tracing_on
-exec "$@"
-------
-
-
-function graph tracer
----------------------------
-
-This tracer is similar to the function tracer except that it
-probes a function on its entry and its exit. This is done by
-using a dynamically allocated stack of return addresses in each
-task_struct. On function entry the tracer overwrites the return
-address of each function traced to set a custom probe. Thus the
-original return address is stored on the stack of return address
-in the task_struct.
-
-Probing on both ends of a function leads to special features
-such as:
-
-- measure of a function's time execution
-- having a reliable call stack to draw function calls graph
-
-This tracer is useful in several situations:
-
-- you want to find the reason of a strange kernel behavior and
- need to see what happens in detail on any areas (or specific
- ones).
-
-- you are experiencing weird latencies but it's difficult to
- find its origin.
-
-- you want to find quickly which path is taken by a specific
- function
-
-- you just want to peek inside a working kernel and want to see
- what happens there.
-
-# tracer: function_graph
-#
-# CPU DURATION FUNCTION CALLS
-# | | | | | | |
-
- 0) | sys_open() {
- 0) | do_sys_open() {
- 0) | getname() {
- 0) | kmem_cache_alloc() {
- 0) 1.382 us | __might_sleep();
- 0) 2.478 us | }
- 0) | strncpy_from_user() {
- 0) | might_fault() {
- 0) 1.389 us | __might_sleep();
- 0) 2.553 us | }
- 0) 3.807 us | }
- 0) 7.876 us | }
- 0) | alloc_fd() {
- 0) 0.668 us | _spin_lock();
- 0) 0.570 us | expand_files();
- 0) 0.586 us | _spin_unlock();
-
-
-There are several columns that can be dynamically
-enabled/disabled. You can use every combination of options you
-want, depending on your needs.
-
-- The cpu number on which the function executed is default
- enabled. It is sometimes better to only trace one cpu (see
- tracing_cpu_mask file) or you might sometimes see unordered
- function calls while cpu tracing switch.
-
- hide: echo nofuncgraph-cpu > trace_options
- show: echo funcgraph-cpu > trace_options
-
-- The duration (function's time of execution) is displayed on
- the closing bracket line of a function or on the same line
- than the current function in case of a leaf one. It is default
- enabled.
-
- hide: echo nofuncgraph-duration > trace_options
- show: echo funcgraph-duration > trace_options
-
-- The overhead field precedes the duration field in case of
- reached duration thresholds.
-
- hide: echo nofuncgraph-overhead > trace_options
- show: echo funcgraph-overhead > trace_options
- depends on: funcgraph-duration
-
- ie:
-
- 3) # 1837.709 us | } /* __switch_to */
- 3) | finish_task_switch() {
- 3) 0.313 us | _raw_spin_unlock_irq();
- 3) 3.177 us | }
- 3) # 1889.063 us | } /* __schedule */
- 3) ! 140.417 us | } /* __schedule */
- 3) # 2034.948 us | } /* schedule */
- 3) * 33998.59 us | } /* schedule_preempt_disabled */
-
- [...]
-
- 1) 0.260 us | msecs_to_jiffies();
- 1) 0.313 us | __rcu_read_unlock();
- 1) + 61.770 us | }
- 1) + 64.479 us | }
- 1) 0.313 us | rcu_bh_qs();
- 1) 0.313 us | __local_bh_enable();
- 1) ! 217.240 us | }
- 1) 0.365 us | idle_cpu();
- 1) | rcu_irq_exit() {
- 1) 0.417 us | rcu_eqs_enter_common.isra.47();
- 1) 3.125 us | }
- 1) ! 227.812 us | }
- 1) ! 457.395 us | }
- 1) @ 119760.2 us | }
-
- [...]
-
- 2) | handle_IPI() {
- 1) 6.979 us | }
- 2) 0.417 us | scheduler_ipi();
- 1) 9.791 us | }
- 1) + 12.917 us | }
- 2) 3.490 us | }
- 1) + 15.729 us | }
- 1) + 18.542 us | }
- 2) $ 3594274 us | }
-
- + means that the function exceeded 10 usecs.
- ! means that the function exceeded 100 usecs.
- # means that the function exceeded 1000 usecs.
- * means that the function exceeded 10 msecs.
- @ means that the function exceeded 100 msecs.
- $ means that the function exceeded 1 sec.
-
-
-- The task/pid field displays the thread cmdline and pid which
- executed the function. It is default disabled.
-
- hide: echo nofuncgraph-proc > trace_options
- show: echo funcgraph-proc > trace_options
-
- ie:
-
- # tracer: function_graph
- #
- # CPU TASK/PID DURATION FUNCTION CALLS
- # | | | | | | | | |
- 0) sh-4802 | | d_free() {
- 0) sh-4802 | | call_rcu() {
- 0) sh-4802 | | __call_rcu() {
- 0) sh-4802 | 0.616 us | rcu_process_gp_end();
- 0) sh-4802 | 0.586 us | check_for_new_grace_period();
- 0) sh-4802 | 2.899 us | }
- 0) sh-4802 | 4.040 us | }
- 0) sh-4802 | 5.151 us | }
- 0) sh-4802 | + 49.370 us | }
-
-
-- The absolute time field is an absolute timestamp given by the
- system clock since it started. A snapshot of this time is
- given on each entry/exit of functions
-
- hide: echo nofuncgraph-abstime > trace_options
- show: echo funcgraph-abstime > trace_options
-
- ie:
-
- #
- # TIME CPU DURATION FUNCTION CALLS
- # | | | | | | | |
- 360.774522 | 1) 0.541 us | }
- 360.774522 | 1) 4.663 us | }
- 360.774523 | 1) 0.541 us | __wake_up_bit();
- 360.774524 | 1) 6.796 us | }
- 360.774524 | 1) 7.952 us | }
- 360.774525 | 1) 9.063 us | }
- 360.774525 | 1) 0.615 us | journal_mark_dirty();
- 360.774527 | 1) 0.578 us | __brelse();
- 360.774528 | 1) | reiserfs_prepare_for_journal() {
- 360.774528 | 1) | unlock_buffer() {
- 360.774529 | 1) | wake_up_bit() {
- 360.774529 | 1) | bit_waitqueue() {
- 360.774530 | 1) 0.594 us | __phys_addr();
-
-
-The function name is always displayed after the closing bracket
-for a function if the start of that function is not in the
-trace buffer.
-
-Display of the function name after the closing bracket may be
-enabled for functions whose start is in the trace buffer,
-allowing easier searching with grep for function durations.
-It is default disabled.
-
- hide: echo nofuncgraph-tail > trace_options
- show: echo funcgraph-tail > trace_options
-
- Example with nofuncgraph-tail (default):
- 0) | putname() {
- 0) | kmem_cache_free() {
- 0) 0.518 us | __phys_addr();
- 0) 1.757 us | }
- 0) 2.861 us | }
-
- Example with funcgraph-tail:
- 0) | putname() {
- 0) | kmem_cache_free() {
- 0) 0.518 us | __phys_addr();
- 0) 1.757 us | } /* kmem_cache_free() */
- 0) 2.861 us | } /* putname() */
-
-You can put some comments on specific functions by using
-trace_printk() For example, if you want to put a comment inside
-the __might_sleep() function, you just have to include
-<linux/ftrace.h> and call trace_printk() inside __might_sleep()
-
-trace_printk("I'm a comment!\n")
-
-will produce:
-
- 1) | __might_sleep() {
- 1) | /* I'm a comment! */
- 1) 1.449 us | }
-
-
-You might find other useful features for this tracer in the
-following "dynamic ftrace" section such as tracing only specific
-functions or tasks.
-
-dynamic ftrace
---------------
-
-If CONFIG_DYNAMIC_FTRACE is set, the system will run with
-virtually no overhead when function tracing is disabled. The way
-this works is the mcount function call (placed at the start of
-every kernel function, produced by the -pg switch in gcc),
-starts of pointing to a simple return. (Enabling FTRACE will
-include the -pg switch in the compiling of the kernel.)
-
-At compile time every C file object is run through the
-recordmcount program (located in the scripts directory). This
-program will parse the ELF headers in the C object to find all
-the locations in the .text section that call mcount. Starting
-with gcc verson 4.6, the -mfentry has been added for x86, which
-calls "__fentry__" instead of "mcount". Which is called before
-the creation of the stack frame.
-
-Note, not all sections are traced. They may be prevented by either
-a notrace, or blocked another way and all inline functions are not
-traced. Check the "available_filter_functions" file to see what functions
-can be traced.
-
-A section called "__mcount_loc" is created that holds
-references to all the mcount/fentry call sites in the .text section.
-The recordmcount program re-links this section back into the
-original object. The final linking stage of the kernel will add all these
-references into a single table.
-
-On boot up, before SMP is initialized, the dynamic ftrace code
-scans this table and updates all the locations into nops. It
-also records the locations, which are added to the
-available_filter_functions list. Modules are processed as they
-are loaded and before they are executed. When a module is
-unloaded, it also removes its functions from the ftrace function
-list. This is automatic in the module unload code, and the
-module author does not need to worry about it.
-
-When tracing is enabled, the process of modifying the function
-tracepoints is dependent on architecture. The old method is to use
-kstop_machine to prevent races with the CPUs executing code being
-modified (which can cause the CPU to do undesirable things, especially
-if the modified code crosses cache (or page) boundaries), and the nops are
-patched back to calls. But this time, they do not call mcount
-(which is just a function stub). They now call into the ftrace
-infrastructure.
-
-The new method of modifying the function tracepoints is to place
-a breakpoint at the location to be modified, sync all CPUs, modify
-the rest of the instruction not covered by the breakpoint. Sync
-all CPUs again, and then remove the breakpoint with the finished
-version to the ftrace call site.
-
-Some archs do not even need to monkey around with the synchronization,
-and can just slap the new code on top of the old without any
-problems with other CPUs executing it at the same time.
-
-One special side-effect to the recording of the functions being
-traced is that we can now selectively choose which functions we
-wish to trace and which ones we want the mcount calls to remain
-as nops.
-
-Two files are used, one for enabling and one for disabling the
-tracing of specified functions. They are:
-
- set_ftrace_filter
-
-and
-
- set_ftrace_notrace
-
-A list of available functions that you can add to these files is
-listed in:
-
- available_filter_functions
-
- # cat available_filter_functions
-put_prev_task_idle
-kmem_cache_create
-pick_next_task_rt
-get_online_cpus
-pick_next_task_fair
-mutex_lock
-[...]
-
-If I am only interested in sys_nanosleep and hrtimer_interrupt:
-
- # echo sys_nanosleep hrtimer_interrupt > set_ftrace_filter
- # echo function > current_tracer
- # echo 1 > tracing_on
- # usleep 1
- # echo 0 > tracing_on
- # cat trace
-# tracer: function
-#
-# entries-in-buffer/entries-written: 5/5 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- usleep-2665 [001] .... 4186.475355: sys_nanosleep <-system_call_fastpath
- <idle>-0 [001] d.h1 4186.475409: hrtimer_interrupt <-smp_apic_timer_interrupt
- usleep-2665 [001] d.h1 4186.475426: hrtimer_interrupt <-smp_apic_timer_interrupt
- <idle>-0 [003] d.h1 4186.475426: hrtimer_interrupt <-smp_apic_timer_interrupt
- <idle>-0 [002] d.h1 4186.475427: hrtimer_interrupt <-smp_apic_timer_interrupt
-
-To see which functions are being traced, you can cat the file:
-
- # cat set_ftrace_filter
-hrtimer_interrupt
-sys_nanosleep
-
-
-Perhaps this is not enough. The filters also allow glob(7) matching.
-
- <match>* - will match functions that begin with <match>
- *<match> - will match functions that end with <match>
- *<match>* - will match functions that have <match> in it
- <match1>*<match2> - will match functions that begin with
- <match1> and end with <match2>
-
-Note: It is better to use quotes to enclose the wild cards,
- otherwise the shell may expand the parameters into names
- of files in the local directory.
-
- # echo 'hrtimer_*' > set_ftrace_filter
-
-Produces:
-
-# tracer: function
-#
-# entries-in-buffer/entries-written: 897/897 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- <idle>-0 [003] dN.1 4228.547803: hrtimer_cancel <-tick_nohz_idle_exit
- <idle>-0 [003] dN.1 4228.547804: hrtimer_try_to_cancel <-hrtimer_cancel
- <idle>-0 [003] dN.2 4228.547805: hrtimer_force_reprogram <-__remove_hrtimer
- <idle>-0 [003] dN.1 4228.547805: hrtimer_forward <-tick_nohz_idle_exit
- <idle>-0 [003] dN.1 4228.547805: hrtimer_start_range_ns <-hrtimer_start_expires.constprop.11
- <idle>-0 [003] d..1 4228.547858: hrtimer_get_next_event <-get_next_timer_interrupt
- <idle>-0 [003] d..1 4228.547859: hrtimer_start <-__tick_nohz_idle_enter
- <idle>-0 [003] d..2 4228.547860: hrtimer_force_reprogram <-__rem
-
-Notice that we lost the sys_nanosleep.
-
- # cat set_ftrace_filter
-hrtimer_run_queues
-hrtimer_run_pending
-hrtimer_init
-hrtimer_cancel
-hrtimer_try_to_cancel
-hrtimer_forward
-hrtimer_start
-hrtimer_reprogram
-hrtimer_force_reprogram
-hrtimer_get_next_event
-hrtimer_interrupt
-hrtimer_nanosleep
-hrtimer_wakeup
-hrtimer_get_remaining
-hrtimer_get_res
-hrtimer_init_sleeper
-
-
-This is because the '>' and '>>' act just like they do in bash.
-To rewrite the filters, use '>'
-To append to the filters, use '>>'
-
-To clear out a filter so that all functions will be recorded
-again:
-
- # echo > set_ftrace_filter
- # cat set_ftrace_filter
- #
-
-Again, now we want to append.
-
- # echo sys_nanosleep > set_ftrace_filter
- # cat set_ftrace_filter
-sys_nanosleep
- # echo 'hrtimer_*' >> set_ftrace_filter
- # cat set_ftrace_filter
-hrtimer_run_queues
-hrtimer_run_pending
-hrtimer_init
-hrtimer_cancel
-hrtimer_try_to_cancel
-hrtimer_forward
-hrtimer_start
-hrtimer_reprogram
-hrtimer_force_reprogram
-hrtimer_get_next_event
-hrtimer_interrupt
-sys_nanosleep
-hrtimer_nanosleep
-hrtimer_wakeup
-hrtimer_get_remaining
-hrtimer_get_res
-hrtimer_init_sleeper
-
-
-The set_ftrace_notrace prevents those functions from being
-traced.
-
- # echo '*preempt*' '*lock*' > set_ftrace_notrace
-
-Produces:
-
-# tracer: function
-#
-# entries-in-buffer/entries-written: 39608/39608 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- bash-1994 [000] .... 4342.324896: file_ra_state_init <-do_dentry_open
- bash-1994 [000] .... 4342.324897: open_check_o_direct <-do_last
- bash-1994 [000] .... 4342.324897: ima_file_check <-do_last
- bash-1994 [000] .... 4342.324898: process_measurement <-ima_file_check
- bash-1994 [000] .... 4342.324898: ima_get_action <-process_measurement
- bash-1994 [000] .... 4342.324898: ima_match_policy <-ima_get_action
- bash-1994 [000] .... 4342.324899: do_truncate <-do_last
- bash-1994 [000] .... 4342.324899: should_remove_suid <-do_truncate
- bash-1994 [000] .... 4342.324899: notify_change <-do_truncate
- bash-1994 [000] .... 4342.324900: current_fs_time <-notify_change
- bash-1994 [000] .... 4342.324900: current_kernel_time <-current_fs_time
- bash-1994 [000] .... 4342.324900: timespec_trunc <-current_fs_time
-
-We can see that there's no more lock or preempt tracing.
-
-
-Dynamic ftrace with the function graph tracer
----------------------------------------------
-
-Although what has been explained above concerns both the
-function tracer and the function-graph-tracer, there are some
-special features only available in the function-graph tracer.
-
-If you want to trace only one function and all of its children,
-you just have to echo its name into set_graph_function:
-
- echo __do_fault > set_graph_function
-
-will produce the following "expanded" trace of the __do_fault()
-function:
-
- 0) | __do_fault() {
- 0) | filemap_fault() {
- 0) | find_lock_page() {
- 0) 0.804 us | find_get_page();
- 0) | __might_sleep() {
- 0) 1.329 us | }
- 0) 3.904 us | }
- 0) 4.979 us | }
- 0) 0.653 us | _spin_lock();
- 0) 0.578 us | page_add_file_rmap();
- 0) 0.525 us | native_set_pte_at();
- 0) 0.585 us | _spin_unlock();
- 0) | unlock_page() {
- 0) 0.541 us | page_waitqueue();
- 0) 0.639 us | __wake_up_bit();
- 0) 2.786 us | }
- 0) + 14.237 us | }
- 0) | __do_fault() {
- 0) | filemap_fault() {
- 0) | find_lock_page() {
- 0) 0.698 us | find_get_page();
- 0) | __might_sleep() {
- 0) 1.412 us | }
- 0) 3.950 us | }
- 0) 5.098 us | }
- 0) 0.631 us | _spin_lock();
- 0) 0.571 us | page_add_file_rmap();
- 0) 0.526 us | native_set_pte_at();
- 0) 0.586 us | _spin_unlock();
- 0) | unlock_page() {
- 0) 0.533 us | page_waitqueue();
- 0) 0.638 us | __wake_up_bit();
- 0) 2.793 us | }
- 0) + 14.012 us | }
-
-You can also expand several functions at once:
-
- echo sys_open > set_graph_function
- echo sys_close >> set_graph_function
-
-Now if you want to go back to trace all functions you can clear
-this special filter via:
-
- echo > set_graph_function
-
-
-ftrace_enabled
---------------
-
-Note, the proc sysctl ftrace_enable is a big on/off switch for the
-function tracer. By default it is enabled (when function tracing is
-enabled in the kernel). If it is disabled, all function tracing is
-disabled. This includes not only the function tracers for ftrace, but
-also for any other uses (perf, kprobes, stack tracing, profiling, etc).
-
-Please disable this with care.
-
-This can be disable (and enabled) with:
-
- sysctl kernel.ftrace_enabled=0
- sysctl kernel.ftrace_enabled=1
-
- or
-
- echo 0 > /proc/sys/kernel/ftrace_enabled
- echo 1 > /proc/sys/kernel/ftrace_enabled
-
-
-Filter commands
----------------
-
-A few commands are supported by the set_ftrace_filter interface.
-Trace commands have the following format:
-
-<function>:<command>:<parameter>
-
-The following commands are supported:
-
-- mod
- This command enables function filtering per module. The
- parameter defines the module. For example, if only the write*
- functions in the ext3 module are desired, run:
-
- echo 'write*:mod:ext3' > set_ftrace_filter
-
- This command interacts with the filter in the same way as
- filtering based on function names. Thus, adding more functions
- in a different module is accomplished by appending (>>) to the
- filter file. Remove specific module functions by prepending
- '!':
-
- echo '!writeback*:mod:ext3' >> set_ftrace_filter
-
- Mod command supports module globbing. Disable tracing for all
- functions except a specific module:
-
- echo '!*:mod:!ext3' >> set_ftrace_filter
-
- Disable tracing for all modules, but still trace kernel:
-
- echo '!*:mod:*' >> set_ftrace_filter
-
- Enable filter only for kernel:
-
- echo '*write*:mod:!*' >> set_ftrace_filter
-
- Enable filter for module globbing:
-
- echo '*write*:mod:*snd*' >> set_ftrace_filter
-
-- traceon/traceoff
- These commands turn tracing on and off when the specified
- functions are hit. The parameter determines how many times the
- tracing system is turned on and off. If unspecified, there is
- no limit. For example, to disable tracing when a schedule bug
- is hit the first 5 times, run:
-
- echo '__schedule_bug:traceoff:5' > set_ftrace_filter
-
- To always disable tracing when __schedule_bug is hit:
-
- echo '__schedule_bug:traceoff' > set_ftrace_filter
-
- These commands are cumulative whether or not they are appended
- to set_ftrace_filter. To remove a command, prepend it by '!'
- and drop the parameter:
-
- echo '!__schedule_bug:traceoff:0' > set_ftrace_filter
-
- The above removes the traceoff command for __schedule_bug
- that have a counter. To remove commands without counters:
-
- echo '!__schedule_bug:traceoff' > set_ftrace_filter
-
-- snapshot
- Will cause a snapshot to be triggered when the function is hit.
-
- echo 'native_flush_tlb_others:snapshot' > set_ftrace_filter
-
- To only snapshot once:
-
- echo 'native_flush_tlb_others:snapshot:1' > set_ftrace_filter
-
- To remove the above commands:
-
- echo '!native_flush_tlb_others:snapshot' > set_ftrace_filter
- echo '!native_flush_tlb_others:snapshot:0' > set_ftrace_filter
-
-- enable_event/disable_event
- These commands can enable or disable a trace event. Note, because
- function tracing callbacks are very sensitive, when these commands
- are registered, the trace point is activated, but disabled in
- a "soft" mode. That is, the tracepoint will be called, but
- just will not be traced. The event tracepoint stays in this mode
- as long as there's a command that triggers it.
-
- echo 'try_to_wake_up:enable_event:sched:sched_switch:2' > \
- set_ftrace_filter
-
- The format is:
-
- <function>:enable_event:<system>:<event>[:count]
- <function>:disable_event:<system>:<event>[:count]
-
- To remove the events commands:
-
-
- echo '!try_to_wake_up:enable_event:sched:sched_switch:0' > \
- set_ftrace_filter
- echo '!schedule:disable_event:sched:sched_switch' > \
- set_ftrace_filter
-
-- dump
- When the function is hit, it will dump the contents of the ftrace
- ring buffer to the console. This is useful if you need to debug
- something, and want to dump the trace when a certain function
- is hit. Perhaps its a function that is called before a tripple
- fault happens and does not allow you to get a regular dump.
-
-- cpudump
- When the function is hit, it will dump the contents of the ftrace
- ring buffer for the current CPU to the console. Unlike the "dump"
- command, it only prints out the contents of the ring buffer for the
- CPU that executed the function that triggered the dump.
-
-trace_pipe
-----------
-
-The trace_pipe outputs the same content as the trace file, but
-the effect on the tracing is different. Every read from
-trace_pipe is consumed. This means that subsequent reads will be
-different. The trace is live.
-
- # echo function > current_tracer
- # cat trace_pipe > /tmp/trace.out &
-[1] 4153
- # echo 1 > tracing_on
- # usleep 1
- # echo 0 > tracing_on
- # cat trace
-# tracer: function
-#
-# entries-in-buffer/entries-written: 0/0 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
-
- #
- # cat /tmp/trace.out
- bash-1994 [000] .... 5281.568961: mutex_unlock <-rb_simple_write
- bash-1994 [000] .... 5281.568963: __mutex_unlock_slowpath <-mutex_unlock
- bash-1994 [000] .... 5281.568963: __fsnotify_parent <-fsnotify_modify
- bash-1994 [000] .... 5281.568964: fsnotify <-fsnotify_modify
- bash-1994 [000] .... 5281.568964: __srcu_read_lock <-fsnotify
- bash-1994 [000] .... 5281.568964: add_preempt_count <-__srcu_read_lock
- bash-1994 [000] ...1 5281.568965: sub_preempt_count <-__srcu_read_lock
- bash-1994 [000] .... 5281.568965: __srcu_read_unlock <-fsnotify
- bash-1994 [000] .... 5281.568967: sys_dup2 <-system_call_fastpath
-
-
-Note, reading the trace_pipe file will block until more input is
-added.
-
-trace entries
--------------
-
-Having too much or not enough data can be troublesome in
-diagnosing an issue in the kernel. The file buffer_size_kb is
-used to modify the size of the internal trace buffers. The
-number listed is the number of entries that can be recorded per
-CPU. To know the full size, multiply the number of possible CPUs
-with the number of entries.
-
- # cat buffer_size_kb
-1408 (units kilobytes)
-
-Or simply read buffer_total_size_kb
-
- # cat buffer_total_size_kb
-5632
-
-To modify the buffer, simple echo in a number (in 1024 byte segments).
-
- # echo 10000 > buffer_size_kb
- # cat buffer_size_kb
-10000 (units kilobytes)
-
-It will try to allocate as much as possible. If you allocate too
-much, it can cause Out-Of-Memory to trigger.
-
- # echo 1000000000000 > buffer_size_kb
--bash: echo: write error: Cannot allocate memory
- # cat buffer_size_kb
-85
-
-The per_cpu buffers can be changed individually as well:
-
- # echo 10000 > per_cpu/cpu0/buffer_size_kb
- # echo 100 > per_cpu/cpu1/buffer_size_kb
-
-When the per_cpu buffers are not the same, the buffer_size_kb
-at the top level will just show an X
-
- # cat buffer_size_kb
-X
-
-This is where the buffer_total_size_kb is useful:
-
- # cat buffer_total_size_kb
-12916
-
-Writing to the top level buffer_size_kb will reset all the buffers
-to be the same again.
-
-Snapshot
---------
-CONFIG_TRACER_SNAPSHOT makes a generic snapshot feature
-available to all non latency tracers. (Latency tracers which
-record max latency, such as "irqsoff" or "wakeup", can't use
-this feature, since those are already using the snapshot
-mechanism internally.)
-
-Snapshot preserves a current trace buffer at a particular point
-in time without stopping tracing. Ftrace swaps the current
-buffer with a spare buffer, and tracing continues in the new
-current (=previous spare) buffer.
-
-The following tracefs files in "tracing" are related to this
-feature:
-
- snapshot:
-
- This is used to take a snapshot and to read the output
- of the snapshot. Echo 1 into this file to allocate a
- spare buffer and to take a snapshot (swap), then read
- the snapshot from this file in the same format as
- "trace" (described above in the section "The File
- System"). Both reads snapshot and tracing are executable
- in parallel. When the spare buffer is allocated, echoing
- 0 frees it, and echoing else (positive) values clear the
- snapshot contents.
- More details are shown in the table below.
-
- status\input | 0 | 1 | else |
- --------------+------------+------------+------------+
- not allocated |(do nothing)| alloc+swap |(do nothing)|
- --------------+------------+------------+------------+
- allocated | free | swap | clear |
- --------------+------------+------------+------------+
-
-Here is an example of using the snapshot feature.
-
- # echo 1 > events/sched/enable
- # echo 1 > snapshot
- # cat snapshot
-# tracer: nop
-#
-# entries-in-buffer/entries-written: 71/71 #P:8
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- <idle>-0 [005] d... 2440.603828: sched_switch: prev_comm=swapper/5 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=snapshot-test-2 next_pid=2242 next_prio=120
- sleep-2242 [005] d... 2440.603846: sched_switch: prev_comm=snapshot-test-2 prev_pid=2242 prev_prio=120 prev_state=R ==> next_comm=kworker/5:1 next_pid=60 next_prio=120
-[...]
- <idle>-0 [002] d... 2440.707230: sched_switch: prev_comm=swapper/2 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=snapshot-test-2 next_pid=2229 next_prio=120
-
- # cat trace
-# tracer: nop
-#
-# entries-in-buffer/entries-written: 77/77 #P:8
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- <idle>-0 [007] d... 2440.707395: sched_switch: prev_comm=swapper/7 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=snapshot-test-2 next_pid=2243 next_prio=120
- snapshot-test-2-2229 [002] d... 2440.707438: sched_switch: prev_comm=snapshot-test-2 prev_pid=2229 prev_prio=120 prev_state=S ==> next_comm=swapper/2 next_pid=0 next_prio=120
-[...]
-
-
-If you try to use this snapshot feature when current tracer is
-one of the latency tracers, you will get the following results.
-
- # echo wakeup > current_tracer
- # echo 1 > snapshot
-bash: echo: write error: Device or resource busy
- # cat snapshot
-cat: snapshot: Device or resource busy
-
-
-Instances
----------
-In the tracefs tracing directory is a directory called "instances".
-This directory can have new directories created inside of it using
-mkdir, and removing directories with rmdir. The directory created
-with mkdir in this directory will already contain files and other
-directories after it is created.
-
- # mkdir instances/foo
- # ls instances/foo
-buffer_size_kb buffer_total_size_kb events free_buffer per_cpu
-set_event snapshot trace trace_clock trace_marker trace_options
-trace_pipe tracing_on
-
-As you can see, the new directory looks similar to the tracing directory
-itself. In fact, it is very similar, except that the buffer and
-events are agnostic from the main director, or from any other
-instances that are created.
-
-The files in the new directory work just like the files with the
-same name in the tracing directory except the buffer that is used
-is a separate and new buffer. The files affect that buffer but do not
-affect the main buffer with the exception of trace_options. Currently,
-the trace_options affect all instances and the top level buffer
-the same, but this may change in future releases. That is, options
-may become specific to the instance they reside in.
-
-Notice that none of the function tracer files are there, nor is
-current_tracer and available_tracers. This is because the buffers
-can currently only have events enabled for them.
-
- # mkdir instances/foo
- # mkdir instances/bar
- # mkdir instances/zoot
- # echo 100000 > buffer_size_kb
- # echo 1000 > instances/foo/buffer_size_kb
- # echo 5000 > instances/bar/per_cpu/cpu1/buffer_size_kb
- # echo function > current_trace
- # echo 1 > instances/foo/events/sched/sched_wakeup/enable
- # echo 1 > instances/foo/events/sched/sched_wakeup_new/enable
- # echo 1 > instances/foo/events/sched/sched_switch/enable
- # echo 1 > instances/bar/events/irq/enable
- # echo 1 > instances/zoot/events/syscalls/enable
- # cat trace_pipe
-CPU:2 [LOST 11745 EVENTS]
- bash-2044 [002] .... 10594.481032: _raw_spin_lock_irqsave <-get_page_from_freelist
- bash-2044 [002] d... 10594.481032: add_preempt_count <-_raw_spin_lock_irqsave
- bash-2044 [002] d..1 10594.481032: __rmqueue <-get_page_from_freelist
- bash-2044 [002] d..1 10594.481033: _raw_spin_unlock <-get_page_from_freelist
- bash-2044 [002] d..1 10594.481033: sub_preempt_count <-_raw_spin_unlock
- bash-2044 [002] d... 10594.481033: get_pageblock_flags_group <-get_pageblock_migratetype
- bash-2044 [002] d... 10594.481034: __mod_zone_page_state <-get_page_from_freelist
- bash-2044 [002] d... 10594.481034: zone_statistics <-get_page_from_freelist
- bash-2044 [002] d... 10594.481034: __inc_zone_state <-zone_statistics
- bash-2044 [002] d... 10594.481034: __inc_zone_state <-zone_statistics
- bash-2044 [002] .... 10594.481035: arch_dup_task_struct <-copy_process
-[...]
-
- # cat instances/foo/trace_pipe
- bash-1998 [000] d..4 136.676759: sched_wakeup: comm=kworker/0:1 pid=59 prio=120 success=1 target_cpu=000
- bash-1998 [000] dN.4 136.676760: sched_wakeup: comm=bash pid=1998 prio=120 success=1 target_cpu=000
- <idle>-0 [003] d.h3 136.676906: sched_wakeup: comm=rcu_preempt pid=9 prio=120 success=1 target_cpu=003
- <idle>-0 [003] d..3 136.676909: sched_switch: prev_comm=swapper/3 prev_pid=0 prev_prio=120 prev_state=R ==> next_comm=rcu_preempt next_pid=9 next_prio=120
- rcu_preempt-9 [003] d..3 136.676916: sched_switch: prev_comm=rcu_preempt prev_pid=9 prev_prio=120 prev_state=S ==> next_comm=swapper/3 next_pid=0 next_prio=120
- bash-1998 [000] d..4 136.677014: sched_wakeup: comm=kworker/0:1 pid=59 prio=120 success=1 target_cpu=000
- bash-1998 [000] dN.4 136.677016: sched_wakeup: comm=bash pid=1998 prio=120 success=1 target_cpu=000
- bash-1998 [000] d..3 136.677018: sched_switch: prev_comm=bash prev_pid=1998 prev_prio=120 prev_state=R+ ==> next_comm=kworker/0:1 next_pid=59 next_prio=120
- kworker/0:1-59 [000] d..4 136.677022: sched_wakeup: comm=sshd pid=1995 prio=120 success=1 target_cpu=001
- kworker/0:1-59 [000] d..3 136.677025: sched_switch: prev_comm=kworker/0:1 prev_pid=59 prev_prio=120 prev_state=S ==> next_comm=bash next_pid=1998 next_prio=120
-[...]
-
- # cat instances/bar/trace_pipe
- migration/1-14 [001] d.h3 138.732674: softirq_raise: vec=3 [action=NET_RX]
- <idle>-0 [001] dNh3 138.732725: softirq_raise: vec=3 [action=NET_RX]
- bash-1998 [000] d.h1 138.733101: softirq_raise: vec=1 [action=TIMER]
- bash-1998 [000] d.h1 138.733102: softirq_raise: vec=9 [action=RCU]
- bash-1998 [000] ..s2 138.733105: softirq_entry: vec=1 [action=TIMER]
- bash-1998 [000] ..s2 138.733106: softirq_exit: vec=1 [action=TIMER]
- bash-1998 [000] ..s2 138.733106: softirq_entry: vec=9 [action=RCU]
- bash-1998 [000] ..s2 138.733109: softirq_exit: vec=9 [action=RCU]
- sshd-1995 [001] d.h1 138.733278: irq_handler_entry: irq=21 name=uhci_hcd:usb4
- sshd-1995 [001] d.h1 138.733280: irq_handler_exit: irq=21 ret=unhandled
- sshd-1995 [001] d.h1 138.733281: irq_handler_entry: irq=21 name=eth0
- sshd-1995 [001] d.h1 138.733283: irq_handler_exit: irq=21 ret=handled
-[...]
-
- # cat instances/zoot/trace
-# tracer: nop
-#
-# entries-in-buffer/entries-written: 18996/18996 #P:4
-#
-# _-----=> irqs-off
-# / _----=> need-resched
-# | / _---=> hardirq/softirq
-# || / _--=> preempt-depth
-# ||| / delay
-# TASK-PID CPU# |||| TIMESTAMP FUNCTION
-# | | | |||| | |
- bash-1998 [000] d... 140.733501: sys_write -> 0x2
- bash-1998 [000] d... 140.733504: sys_dup2(oldfd: a, newfd: 1)
- bash-1998 [000] d... 140.733506: sys_dup2 -> 0x1
- bash-1998 [000] d... 140.733508: sys_fcntl(fd: a, cmd: 1, arg: 0)
- bash-1998 [000] d... 140.733509: sys_fcntl -> 0x1
- bash-1998 [000] d... 140.733510: sys_close(fd: a)
- bash-1998 [000] d... 140.733510: sys_close -> 0x0
- bash-1998 [000] d... 140.733514: sys_rt_sigprocmask(how: 0, nset: 0, oset: 6e2768, sigsetsize: 8)
- bash-1998 [000] d... 140.733515: sys_rt_sigprocmask -> 0x0
- bash-1998 [000] d... 140.733516: sys_rt_sigaction(sig: 2, act: 7fff718846f0, oact: 7fff71884650, sigsetsize: 8)
- bash-1998 [000] d... 140.733516: sys_rt_sigaction -> 0x0
-
-You can see that the trace of the top most trace buffer shows only
-the function tracing. The foo instance displays wakeups and task
-switches.
-
-To remove the instances, simply delete their directories:
-
- # rmdir instances/foo
- # rmdir instances/bar
- # rmdir instances/zoot
-
-Note, if a process has a trace file open in one of the instance
-directories, the rmdir will fail with EBUSY.
-
-
-Stack trace
------------
-Since the kernel has a fixed sized stack, it is important not to
-waste it in functions. A kernel developer must be conscience of
-what they allocate on the stack. If they add too much, the system
-can be in danger of a stack overflow, and corruption will occur,
-usually leading to a system panic.
-
-There are some tools that check this, usually with interrupts
-periodically checking usage. But if you can perform a check
-at every function call that will become very useful. As ftrace provides
-a function tracer, it makes it convenient to check the stack size
-at every function call. This is enabled via the stack tracer.
-
-CONFIG_STACK_TRACER enables the ftrace stack tracing functionality.
-To enable it, write a '1' into /proc/sys/kernel/stack_tracer_enabled.
-
- # echo 1 > /proc/sys/kernel/stack_tracer_enabled
-
-You can also enable it from the kernel command line to trace
-the stack size of the kernel during boot up, by adding "stacktrace"
-to the kernel command line parameter.
-
-After running it for a few minutes, the output looks like:
-
- # cat stack_max_size
-2928
-
- # cat stack_trace
- Depth Size Location (18 entries)
- ----- ---- --------
- 0) 2928 224 update_sd_lb_stats+0xbc/0x4ac
- 1) 2704 160 find_busiest_group+0x31/0x1f1
- 2) 2544 256 load_balance+0xd9/0x662
- 3) 2288 80 idle_balance+0xbb/0x130
- 4) 2208 128 __schedule+0x26e/0x5b9
- 5) 2080 16 schedule+0x64/0x66
- 6) 2064 128 schedule_timeout+0x34/0xe0
- 7) 1936 112 wait_for_common+0x97/0xf1
- 8) 1824 16 wait_for_completion+0x1d/0x1f
- 9) 1808 128 flush_work+0xfe/0x119
- 10) 1680 16 tty_flush_to_ldisc+0x1e/0x20
- 11) 1664 48 input_available_p+0x1d/0x5c
- 12) 1616 48 n_tty_poll+0x6d/0x134
- 13) 1568 64 tty_poll+0x64/0x7f
- 14) 1504 880 do_select+0x31e/0x511
- 15) 624 400 core_sys_select+0x177/0x216
- 16) 224 96 sys_select+0x91/0xb9
- 17) 128 128 system_call_fastpath+0x16/0x1b
-
-Note, if -mfentry is being used by gcc, functions get traced before
-they set up the stack frame. This means that leaf level functions
-are not tested by the stack tracer when -mfentry is used.
-
-Currently, -mfentry is used by gcc 4.6.0 and above on x86 only.
-
----------
-
-More details can be found in the source code, in the
-kernel/trace/*.c files.
diff --git a/Documentation/trace/histogram.txt b/Documentation/trace/histogram.txt
new file mode 100644
index 000000000000..6e05510afc28
--- /dev/null
+++ b/Documentation/trace/histogram.txt
@@ -0,0 +1,1995 @@
+ Event Histograms
+
+ Documentation written by Tom Zanussi
+
+1. Introduction
+===============
+
+ Histogram triggers are special event triggers that can be used to
+ aggregate trace event data into histograms. For information on
+ trace events and event triggers, see Documentation/trace/events.txt.
+
+
+2. Histogram Trigger Command
+============================
+
+ A histogram trigger command is an event trigger command that
+ aggregates event hits into a hash table keyed on one or more trace
+ event format fields (or stacktrace) and a set of running totals
+ derived from one or more trace event format fields and/or event
+ counts (hitcount).
+
+ The format of a hist trigger is as follows:
+
+ hist:keys=<field1[,field2,...]>[:values=<field1[,field2,...]>]
+ [:sort=<field1[,field2,...]>][:size=#entries][:pause][:continue]
+ [:clear][:name=histname1] [if <filter>]
+
+ When a matching event is hit, an entry is added to a hash table
+ using the key(s) and value(s) named. Keys and values correspond to
+ fields in the event's format description. Values must correspond to
+ numeric fields - on an event hit, the value(s) will be added to a
+ sum kept for that field. The special string 'hitcount' can be used
+ in place of an explicit value field - this is simply a count of
+ event hits. If 'values' isn't specified, an implicit 'hitcount'
+ value will be automatically created and used as the only value.
+ Keys can be any field, or the special string 'stacktrace', which
+ will use the event's kernel stacktrace as the key. The keywords
+ 'keys' or 'key' can be used to specify keys, and the keywords
+ 'values', 'vals', or 'val' can be used to specify values. Compound
+ keys consisting of up to two fields can be specified by the 'keys'
+ keyword. Hashing a compound key produces a unique entry in the
+ table for each unique combination of component keys, and can be
+ useful for providing more fine-grained summaries of event data.
+ Additionally, sort keys consisting of up to two fields can be
+ specified by the 'sort' keyword. If more than one field is
+ specified, the result will be a 'sort within a sort': the first key
+ is taken to be the primary sort key and the second the secondary
+ key. If a hist trigger is given a name using the 'name' parameter,
+ its histogram data will be shared with other triggers of the same
+ name, and trigger hits will update this common data. Only triggers
+ with 'compatible' fields can be combined in this way; triggers are
+ 'compatible' if the fields named in the trigger share the same
+ number and type of fields and those fields also have the same names.
+ Note that any two events always share the compatible 'hitcount' and
+ 'stacktrace' fields and can therefore be combined using those
+ fields, however pointless that may be.
+
+ 'hist' triggers add a 'hist' file to each event's subdirectory.
+ Reading the 'hist' file for the event will dump the hash table in
+ its entirety to stdout. If there are multiple hist triggers
+ attached to an event, there will be a table for each trigger in the
+ output. The table displayed for a named trigger will be the same as
+ any other instance having the same name. Each printed hash table
+ entry is a simple list of the keys and values comprising the entry;
+ keys are printed first and are delineated by curly braces, and are
+ followed by the set of value fields for the entry. By default,
+ numeric fields are displayed as base-10 integers. This can be
+ modified by appending any of the following modifiers to the field
+ name:
+
+ .hex display a number as a hex value
+ .sym display an address as a symbol
+ .sym-offset display an address as a symbol and offset
+ .syscall display a syscall id as a system call name
+ .execname display a common_pid as a program name
+ .log2 display log2 value rather than raw number
+ .usecs display a common_timestamp in microseconds
+
+ Note that in general the semantics of a given field aren't
+ interpreted when applying a modifier to it, but there are some
+ restrictions to be aware of in this regard:
+
+ - only the 'hex' modifier can be used for values (because values
+ are essentially sums, and the other modifiers don't make sense
+ in that context).
+ - the 'execname' modifier can only be used on a 'common_pid'. The
+ reason for this is that the execname is simply the 'comm' value
+ saved for the 'current' process when an event was triggered,
+ which is the same as the common_pid value saved by the event
+ tracing code. Trying to apply that comm value to other pid
+ values wouldn't be correct, and typically events that care save
+ pid-specific comm fields in the event itself.
+
+ A typical usage scenario would be the following to enable a hist
+ trigger, read its current contents, and then turn it off:
+
+ # echo 'hist:keys=skbaddr.hex:vals=len' > \
+ /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+
+ # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
+
+ # echo '!hist:keys=skbaddr.hex:vals=len' > \
+ /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+
+ The trigger file itself can be read to show the details of the
+ currently attached hist trigger. This information is also displayed
+ at the top of the 'hist' file when read.
+
+ By default, the size of the hash table is 2048 entries. The 'size'
+ parameter can be used to specify more or fewer than that. The units
+ are in terms of hashtable entries - if a run uses more entries than
+ specified, the results will show the number of 'drops', the number
+ of hits that were ignored. The size should be a power of 2 between
+ 128 and 131072 (any non- power-of-2 number specified will be rounded
+ up).
+
+ The 'sort' parameter can be used to specify a value field to sort
+ on. The default if unspecified is 'hitcount' and the default sort
+ order is 'ascending'. To sort in the opposite direction, append
+ .descending' to the sort key.
+
+ The 'pause' parameter can be used to pause an existing hist trigger
+ or to start a hist trigger but not log any events until told to do
+ so. 'continue' or 'cont' can be used to start or restart a paused
+ hist trigger.
+
+ The 'clear' parameter will clear the contents of a running hist
+ trigger and leave its current paused/active state.
+
+ Note that the 'pause', 'cont', and 'clear' parameters should be
+ applied using 'append' shell operator ('>>') if applied to an
+ existing trigger, rather than via the '>' operator, which will cause
+ the trigger to be removed through truncation.
+
+- enable_hist/disable_hist
+
+ The enable_hist and disable_hist triggers can be used to have one
+ event conditionally start and stop another event's already-attached
+ hist trigger. Any number of enable_hist and disable_hist triggers
+ can be attached to a given event, allowing that event to kick off
+ and stop aggregations on a host of other events.
+
+ The format is very similar to the enable/disable_event triggers:
+
+ enable_hist:<system>:<event>[:count]
+ disable_hist:<system>:<event>[:count]
+
+ Instead of enabling or disabling the tracing of the target event
+ into the trace buffer as the enable/disable_event triggers do, the
+ enable/disable_hist triggers enable or disable the aggregation of
+ the target event into a hash table.
+
+ A typical usage scenario for the enable_hist/disable_hist triggers
+ would be to first set up a paused hist trigger on some event,
+ followed by an enable_hist/disable_hist pair that turns the hist
+ aggregation on and off when conditions of interest are hit:
+
+ # echo 'hist:keys=skbaddr.hex:vals=len:pause' > \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+
+ # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+
+ # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+
+ The above sets up an initially paused hist trigger which is unpaused
+ and starts aggregating events when a given program is executed, and
+ which stops aggregating when the process exits and the hist trigger
+ is paused again.
+
+ The examples below provide a more concrete illustration of the
+ concepts and typical usage patterns discussed above.
+
+ 'special' event fields
+ ------------------------
+
+ There are a number of 'special event fields' available for use as
+ keys or values in a hist trigger. These look like and behave as if
+ they were actual event fields, but aren't really part of the event's
+ field definition or format file. They are however available for any
+ event, and can be used anywhere an actual event field could be.
+ They are:
+
+ common_timestamp u64 - timestamp (from ring buffer) associated
+ with the event, in nanoseconds. May be
+ modified by .usecs to have timestamps
+ interpreted as microseconds.
+ cpu int - the cpu on which the event occurred.
+
+ Extended error information
+ --------------------------
+
+ For some error conditions encountered when invoking a hist trigger
+ command, extended error information is available via the
+ corresponding event's 'hist' file. Reading the hist file after an
+ error will display more detailed information about what went wrong,
+ if information is available. This extended error information will
+ be available until the next hist trigger command for that event.
+
+ If available for a given error condition, the extended error
+ information and usage takes the following form:
+
+ # echo xxx > /sys/kernel/debug/tracing/events/sched/sched_wakeup/trigger
+ echo: write error: Invalid argument
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/hist
+ ERROR: Couldn't yyy: zzz
+ Last command: xxx
+
+6.2 'hist' trigger examples
+---------------------------
+
+ The first set of examples creates aggregations using the kmalloc
+ event. The fields that can be used for the hist trigger are listed
+ in the kmalloc event's format file:
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/format
+ name: kmalloc
+ ID: 374
+ format:
+ field:unsigned short common_type; offset:0; size:2; signed:0;
+ field:unsigned char common_flags; offset:2; size:1; signed:0;
+ field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
+ field:int common_pid; offset:4; size:4; signed:1;
+
+ field:unsigned long call_site; offset:8; size:8; signed:0;
+ field:const void * ptr; offset:16; size:8; signed:0;
+ field:size_t bytes_req; offset:24; size:8; signed:0;
+ field:size_t bytes_alloc; offset:32; size:8; signed:0;
+ field:gfp_t gfp_flags; offset:40; size:4; signed:0;
+
+ We'll start by creating a hist trigger that generates a simple table
+ that lists the total number of bytes requested for each function in
+ the kernel that made one or more calls to kmalloc:
+
+ # echo 'hist:key=call_site:val=bytes_req' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ This tells the tracing system to create a 'hist' trigger using the
+ call_site field of the kmalloc event as the key for the table, which
+ just means that each unique call_site address will have an entry
+ created for it in the table. The 'val=bytes_req' parameter tells
+ the hist trigger that for each unique entry (call_site) in the
+ table, it should keep a running total of the number of bytes
+ requested by that call_site.
+
+ We'll let it run for awhile and then dump the contents of the 'hist'
+ file in the kmalloc event's subdirectory (for readability, a number
+ of entries have been omitted):
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
+
+ { call_site: 18446744072106379007 } hitcount: 1 bytes_req: 176
+ { call_site: 18446744071579557049 } hitcount: 1 bytes_req: 1024
+ { call_site: 18446744071580608289 } hitcount: 1 bytes_req: 16384
+ { call_site: 18446744071581827654 } hitcount: 1 bytes_req: 24
+ { call_site: 18446744071580700980 } hitcount: 1 bytes_req: 8
+ { call_site: 18446744071579359876 } hitcount: 1 bytes_req: 152
+ { call_site: 18446744071580795365 } hitcount: 3 bytes_req: 144
+ { call_site: 18446744071581303129 } hitcount: 3 bytes_req: 144
+ { call_site: 18446744071580713234 } hitcount: 4 bytes_req: 2560
+ { call_site: 18446744071580933750 } hitcount: 4 bytes_req: 736
+ .
+ .
+ .
+ { call_site: 18446744072106047046 } hitcount: 69 bytes_req: 5576
+ { call_site: 18446744071582116407 } hitcount: 73 bytes_req: 2336
+ { call_site: 18446744072106054684 } hitcount: 136 bytes_req: 140504
+ { call_site: 18446744072106224230 } hitcount: 136 bytes_req: 19584
+ { call_site: 18446744072106078074 } hitcount: 153 bytes_req: 2448
+ { call_site: 18446744072106062406 } hitcount: 153 bytes_req: 36720
+ { call_site: 18446744071582507929 } hitcount: 153 bytes_req: 37088
+ { call_site: 18446744072102520590 } hitcount: 273 bytes_req: 10920
+ { call_site: 18446744071582143559 } hitcount: 358 bytes_req: 716
+ { call_site: 18446744072106465852 } hitcount: 417 bytes_req: 56712
+ { call_site: 18446744072102523378 } hitcount: 485 bytes_req: 27160
+ { call_site: 18446744072099568646 } hitcount: 1676 bytes_req: 33520
+
+ Totals:
+ Hits: 4610
+ Entries: 45
+ Dropped: 0
+
+ The output displays a line for each entry, beginning with the key
+ specified in the trigger, followed by the value(s) also specified in
+ the trigger. At the beginning of the output is a line that displays
+ the trigger info, which can also be displayed by reading the
+ 'trigger' file:
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+ hist:keys=call_site:vals=bytes_req:sort=hitcount:size=2048 [active]
+
+ At the end of the output are a few lines that display the overall
+ totals for the run. The 'Hits' field shows the total number of
+ times the event trigger was hit, the 'Entries' field shows the total
+ number of used entries in the hash table, and the 'Dropped' field
+ shows the number of hits that were dropped because the number of
+ used entries for the run exceeded the maximum number of entries
+ allowed for the table (normally 0, but if not a hint that you may
+ want to increase the size of the table using the 'size' parameter).
+
+ Notice in the above output that there's an extra field, 'hitcount',
+ which wasn't specified in the trigger. Also notice that in the
+ trigger info output, there's a parameter, 'sort=hitcount', which
+ wasn't specified in the trigger either. The reason for that is that
+ every trigger implicitly keeps a count of the total number of hits
+ attributed to a given entry, called the 'hitcount'. That hitcount
+ information is explicitly displayed in the output, and in the
+ absence of a user-specified sort parameter, is used as the default
+ sort field.
+
+ The value 'hitcount' can be used in place of an explicit value in
+ the 'values' parameter if you don't really need to have any
+ particular field summed and are mainly interested in hit
+ frequencies.
+
+ To turn the hist trigger off, simply call up the trigger in the
+ command history and re-execute it with a '!' prepended:
+
+ # echo '!hist:key=call_site:val=bytes_req' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ Finally, notice that the call_site as displayed in the output above
+ isn't really very useful. It's an address, but normally addresses
+ are displayed in hex. To have a numeric field displayed as a hex
+ value, simply append '.hex' to the field name in the trigger:
+
+ # echo 'hist:key=call_site.hex:val=bytes_req' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=call_site.hex:vals=bytes_req:sort=hitcount:size=2048 [active]
+
+ { call_site: ffffffffa026b291 } hitcount: 1 bytes_req: 433
+ { call_site: ffffffffa07186ff } hitcount: 1 bytes_req: 176
+ { call_site: ffffffff811ae721 } hitcount: 1 bytes_req: 16384
+ { call_site: ffffffff811c5134 } hitcount: 1 bytes_req: 8
+ { call_site: ffffffffa04a9ebb } hitcount: 1 bytes_req: 511
+ { call_site: ffffffff8122e0a6 } hitcount: 1 bytes_req: 12
+ { call_site: ffffffff8107da84 } hitcount: 1 bytes_req: 152
+ { call_site: ffffffff812d8246 } hitcount: 1 bytes_req: 24
+ { call_site: ffffffff811dc1e5 } hitcount: 3 bytes_req: 144
+ { call_site: ffffffffa02515e8 } hitcount: 3 bytes_req: 648
+ { call_site: ffffffff81258159 } hitcount: 3 bytes_req: 144
+ { call_site: ffffffff811c80f4 } hitcount: 4 bytes_req: 544
+ .
+ .
+ .
+ { call_site: ffffffffa06c7646 } hitcount: 106 bytes_req: 8024
+ { call_site: ffffffffa06cb246 } hitcount: 132 bytes_req: 31680
+ { call_site: ffffffffa06cef7a } hitcount: 132 bytes_req: 2112
+ { call_site: ffffffff8137e399 } hitcount: 132 bytes_req: 23232
+ { call_site: ffffffffa06c941c } hitcount: 185 bytes_req: 171360
+ { call_site: ffffffffa06f2a66 } hitcount: 185 bytes_req: 26640
+ { call_site: ffffffffa036a70e } hitcount: 265 bytes_req: 10600
+ { call_site: ffffffff81325447 } hitcount: 292 bytes_req: 584
+ { call_site: ffffffffa072da3c } hitcount: 446 bytes_req: 60656
+ { call_site: ffffffffa036b1f2 } hitcount: 526 bytes_req: 29456
+ { call_site: ffffffffa0099c06 } hitcount: 1780 bytes_req: 35600
+
+ Totals:
+ Hits: 4775
+ Entries: 46
+ Dropped: 0
+
+ Even that's only marginally more useful - while hex values do look
+ more like addresses, what users are typically more interested in
+ when looking at text addresses are the corresponding symbols
+ instead. To have an address displayed as symbolic value instead,
+ simply append '.sym' or '.sym-offset' to the field name in the
+ trigger:
+
+ # echo 'hist:key=call_site.sym:val=bytes_req' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=hitcount:size=2048 [active]
+
+ { call_site: [ffffffff810adcb9] syslog_print_all } hitcount: 1 bytes_req: 1024
+ { call_site: [ffffffff8154bc62] usb_control_msg } hitcount: 1 bytes_req: 8
+ { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid] } hitcount: 1 bytes_req: 7
+ { call_site: [ffffffff8154acbe] usb_alloc_urb } hitcount: 1 bytes_req: 192
+ { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid] } hitcount: 1 bytes_req: 7
+ { call_site: [ffffffff811e3a25] __seq_open_private } hitcount: 1 bytes_req: 40
+ { call_site: [ffffffff8109524a] alloc_fair_sched_group } hitcount: 2 bytes_req: 128
+ { call_site: [ffffffff811febd5] fsnotify_alloc_group } hitcount: 2 bytes_req: 528
+ { call_site: [ffffffff81440f58] __tty_buffer_request_room } hitcount: 2 bytes_req: 2624
+ { call_site: [ffffffff81200ba6] inotify_new_group } hitcount: 2 bytes_req: 96
+ { call_site: [ffffffffa05e19af] ieee80211_start_tx_ba_session [mac80211] } hitcount: 2 bytes_req: 464
+ { call_site: [ffffffff81672406] tcp_get_metrics } hitcount: 2 bytes_req: 304
+ { call_site: [ffffffff81097ec2] alloc_rt_sched_group } hitcount: 2 bytes_req: 128
+ { call_site: [ffffffff81089b05] sched_create_group } hitcount: 2 bytes_req: 1424
+ .
+ .
+ .
+ { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915] } hitcount: 1185 bytes_req: 123240
+ { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm] } hitcount: 1185 bytes_req: 104280
+ { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915] } hitcount: 1402 bytes_req: 190672
+ { call_site: [ffffffff812891ca] ext4_find_extent } hitcount: 1518 bytes_req: 146208
+ { call_site: [ffffffffa029070e] drm_vma_node_allow [drm] } hitcount: 1746 bytes_req: 69840
+ { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 2021 bytes_req: 792312
+ { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm] } hitcount: 2592 bytes_req: 145152
+ { call_site: [ffffffffa0489a66] intel_ring_begin [i915] } hitcount: 2629 bytes_req: 378576
+ { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915] } hitcount: 2629 bytes_req: 3783248
+ { call_site: [ffffffff81325607] apparmor_file_alloc_security } hitcount: 5192 bytes_req: 10384
+ { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid] } hitcount: 5529 bytes_req: 110584
+ { call_site: [ffffffff8131ebf7] aa_alloc_task_context } hitcount: 21943 bytes_req: 702176
+ { call_site: [ffffffff8125847d] ext4_htree_store_dirent } hitcount: 55759 bytes_req: 5074265
+
+ Totals:
+ Hits: 109928
+ Entries: 71
+ Dropped: 0
+
+ Because the default sort key above is 'hitcount', the above shows a
+ the list of call_sites by increasing hitcount, so that at the bottom
+ we see the functions that made the most kmalloc calls during the
+ run. If instead we we wanted to see the top kmalloc callers in
+ terms of the number of bytes requested rather than the number of
+ calls, and we wanted the top caller to appear at the top, we can use
+ the 'sort' parameter, along with the 'descending' modifier:
+
+ # echo 'hist:key=call_site.sym:val=bytes_req:sort=bytes_req.descending' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=call_site.sym:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
+
+ { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915] } hitcount: 2186 bytes_req: 3397464
+ { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 1790 bytes_req: 712176
+ { call_site: [ffffffff8125847d] ext4_htree_store_dirent } hitcount: 8132 bytes_req: 513135
+ { call_site: [ffffffff811e2a1b] seq_buf_alloc } hitcount: 106 bytes_req: 440128
+ { call_site: [ffffffffa0489a66] intel_ring_begin [i915] } hitcount: 2186 bytes_req: 314784
+ { call_site: [ffffffff812891ca] ext4_find_extent } hitcount: 2174 bytes_req: 208992
+ { call_site: [ffffffff811ae8e1] __kmalloc } hitcount: 8 bytes_req: 131072
+ { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915] } hitcount: 859 bytes_req: 116824
+ { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm] } hitcount: 1834 bytes_req: 102704
+ { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915] } hitcount: 972 bytes_req: 101088
+ { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl [drm] } hitcount: 972 bytes_req: 85536
+ { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid] } hitcount: 3333 bytes_req: 66664
+ { call_site: [ffffffff8137e559] sg_kmalloc } hitcount: 209 bytes_req: 61632
+ .
+ .
+ .
+ { call_site: [ffffffff81095225] alloc_fair_sched_group } hitcount: 2 bytes_req: 128
+ { call_site: [ffffffff81097ec2] alloc_rt_sched_group } hitcount: 2 bytes_req: 128
+ { call_site: [ffffffff812d8406] copy_semundo } hitcount: 2 bytes_req: 48
+ { call_site: [ffffffff81200ba6] inotify_new_group } hitcount: 1 bytes_req: 48
+ { call_site: [ffffffffa027121a] drm_getmagic [drm] } hitcount: 1 bytes_req: 48
+ { call_site: [ffffffff811e3a25] __seq_open_private } hitcount: 1 bytes_req: 40
+ { call_site: [ffffffff811c52f4] bprm_change_interp } hitcount: 2 bytes_req: 16
+ { call_site: [ffffffff8154bc62] usb_control_msg } hitcount: 1 bytes_req: 8
+ { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid] } hitcount: 1 bytes_req: 7
+ { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid] } hitcount: 1 bytes_req: 7
+
+ Totals:
+ Hits: 32133
+ Entries: 81
+ Dropped: 0
+
+ To display the offset and size information in addition to the symbol
+ name, just use 'sym-offset' instead:
+
+ # echo 'hist:key=call_site.sym-offset:val=bytes_req:sort=bytes_req.descending' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=call_site.sym-offset:vals=bytes_req:sort=bytes_req.descending:size=2048 [active]
+
+ { call_site: [ffffffffa046041c] i915_gem_execbuffer2+0x6c/0x2c0 [i915] } hitcount: 4569 bytes_req: 3163720
+ { call_site: [ffffffffa0489a66] intel_ring_begin+0xc6/0x1f0 [i915] } hitcount: 4569 bytes_req: 657936
+ { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23+0x694/0x1020 [i915] } hitcount: 1519 bytes_req: 472936
+ { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23+0x516/0x1020 [i915] } hitcount: 3050 bytes_req: 211832
+ { call_site: [ffffffff811e2a1b] seq_buf_alloc+0x1b/0x50 } hitcount: 34 bytes_req: 148384
+ { call_site: [ffffffffa04a580c] intel_crtc_page_flip+0xbc/0x870 [i915] } hitcount: 1385 bytes_req: 144040
+ { call_site: [ffffffff811ae8e1] __kmalloc+0x191/0x1b0 } hitcount: 8 bytes_req: 131072
+ { call_site: [ffffffffa0287592] drm_mode_page_flip_ioctl+0x282/0x360 [drm] } hitcount: 1385 bytes_req: 121880
+ { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc+0x32/0x100 [drm] } hitcount: 1848 bytes_req: 103488
+ { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state+0x2c/0xa0 [i915] } hitcount: 461 bytes_req: 62696
+ { call_site: [ffffffffa029070e] drm_vma_node_allow+0x2e/0xd0 [drm] } hitcount: 1541 bytes_req: 61640
+ { call_site: [ffffffff815f8d7b] sk_prot_alloc+0xcb/0x1b0 } hitcount: 57 bytes_req: 57456
+ .
+ .
+ .
+ { call_site: [ffffffff8109524a] alloc_fair_sched_group+0x5a/0x1a0 } hitcount: 2 bytes_req: 128
+ { call_site: [ffffffffa027b921] drm_vm_open_locked+0x31/0xa0 [drm] } hitcount: 3 bytes_req: 96
+ { call_site: [ffffffff8122e266] proc_self_follow_link+0x76/0xb0 } hitcount: 8 bytes_req: 96
+ { call_site: [ffffffff81213e80] load_elf_binary+0x240/0x1650 } hitcount: 3 bytes_req: 84
+ { call_site: [ffffffff8154bc62] usb_control_msg+0x42/0x110 } hitcount: 1 bytes_req: 8
+ { call_site: [ffffffffa00bf6fe] hidraw_send_report+0x7e/0x1a0 [hid] } hitcount: 1 bytes_req: 7
+ { call_site: [ffffffffa00bf1ca] hidraw_report_event+0x8a/0x120 [hid] } hitcount: 1 bytes_req: 7
+
+ Totals:
+ Hits: 26098
+ Entries: 64
+ Dropped: 0
+
+ We can also add multiple fields to the 'values' parameter. For
+ example, we might want to see the total number of bytes allocated
+ alongside bytes requested, and display the result sorted by bytes
+ allocated in a descending order:
+
+ # echo 'hist:keys=call_site.sym:values=bytes_req,bytes_alloc:sort=bytes_alloc.descending' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=call_site.sym:vals=bytes_req,bytes_alloc:sort=bytes_alloc.descending:size=2048 [active]
+
+ { call_site: [ffffffffa046041c] i915_gem_execbuffer2 [i915] } hitcount: 7403 bytes_req: 4084360 bytes_alloc: 5958016
+ { call_site: [ffffffff811e2a1b] seq_buf_alloc } hitcount: 541 bytes_req: 2213968 bytes_alloc: 2228224
+ { call_site: [ffffffffa0489a66] intel_ring_begin [i915] } hitcount: 7404 bytes_req: 1066176 bytes_alloc: 1421568
+ { call_site: [ffffffffa045e7c4] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 1565 bytes_req: 557368 bytes_alloc: 1037760
+ { call_site: [ffffffff8125847d] ext4_htree_store_dirent } hitcount: 9557 bytes_req: 595778 bytes_alloc: 695744
+ { call_site: [ffffffffa045e646] i915_gem_do_execbuffer.isra.23 [i915] } hitcount: 5839 bytes_req: 430680 bytes_alloc: 470400
+ { call_site: [ffffffffa04c4a3c] intel_plane_duplicate_state [i915] } hitcount: 2388 bytes_req: 324768 bytes_alloc: 458496
+ { call_site: [ffffffffa02911f2] drm_modeset_lock_crtc [drm] } hitcount: 3911 bytes_req: 219016 bytes_alloc: 250304
+ { call_site: [ffffffff815f8d7b] sk_prot_alloc } hitcount: 235 bytes_req: 236880 bytes_alloc: 240640
+ { call_site: [ffffffff8137e559] sg_kmalloc } hitcount: 557 bytes_req: 169024 bytes_alloc: 221760
+ { call_site: [ffffffffa00b7c06] hid_report_raw_event [hid] } hitcount: 9378 bytes_req: 187548 bytes_alloc: 206312
+ { call_site: [ffffffffa04a580c] intel_crtc_page_flip [i915] } hitcount: 1519 bytes_req: 157976 bytes_alloc: 194432
+ .
+ .
+ .
+ { call_site: [ffffffff8109bd3b] sched_autogroup_create_attach } hitcount: 2 bytes_req: 144 bytes_alloc: 192
+ { call_site: [ffffffff81097ee8] alloc_rt_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
+ { call_site: [ffffffff8109524a] alloc_fair_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
+ { call_site: [ffffffff81095225] alloc_fair_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
+ { call_site: [ffffffff81097ec2] alloc_rt_sched_group } hitcount: 2 bytes_req: 128 bytes_alloc: 128
+ { call_site: [ffffffff81213e80] load_elf_binary } hitcount: 3 bytes_req: 84 bytes_alloc: 96
+ { call_site: [ffffffff81079a2e] kthread_create_on_node } hitcount: 1 bytes_req: 56 bytes_alloc: 64
+ { call_site: [ffffffffa00bf6fe] hidraw_send_report [hid] } hitcount: 1 bytes_req: 7 bytes_alloc: 8
+ { call_site: [ffffffff8154bc62] usb_control_msg } hitcount: 1 bytes_req: 8 bytes_alloc: 8
+ { call_site: [ffffffffa00bf1ca] hidraw_report_event [hid] } hitcount: 1 bytes_req: 7 bytes_alloc: 8
+
+ Totals:
+ Hits: 66598
+ Entries: 65
+ Dropped: 0
+
+ Finally, to finish off our kmalloc example, instead of simply having
+ the hist trigger display symbolic call_sites, we can have the hist
+ trigger additionally display the complete set of kernel stack traces
+ that led to each call_site. To do that, we simply use the special
+ value 'stacktrace' for the key parameter:
+
+ # echo 'hist:keys=stacktrace:values=bytes_req,bytes_alloc:sort=bytes_alloc' > \
+ /sys/kernel/debug/tracing/events/kmem/kmalloc/trigger
+
+ The above trigger will use the kernel stack trace in effect when an
+ event is triggered as the key for the hash table. This allows the
+ enumeration of every kernel callpath that led up to a particular
+ event, along with a running total of any of the event fields for
+ that event. Here we tally bytes requested and bytes allocated for
+ every callpath in the system that led up to a kmalloc (in this case
+ every callpath to a kmalloc for a kernel compile):
+
+ # cat /sys/kernel/debug/tracing/events/kmem/kmalloc/hist
+ # trigger info: hist:keys=stacktrace:vals=bytes_req,bytes_alloc:sort=bytes_alloc:size=2048 [active]
+
+ { stacktrace:
+ __kmalloc_track_caller+0x10b/0x1a0
+ kmemdup+0x20/0x50
+ hidraw_report_event+0x8a/0x120 [hid]
+ hid_report_raw_event+0x3ea/0x440 [hid]
+ hid_input_report+0x112/0x190 [hid]
+ hid_irq_in+0xc2/0x260 [usbhid]
+ __usb_hcd_giveback_urb+0x72/0x120
+ usb_giveback_urb_bh+0x9e/0xe0
+ tasklet_hi_action+0xf8/0x100
+ __do_softirq+0x114/0x2c0
+ irq_exit+0xa5/0xb0
+ do_IRQ+0x5a/0xf0
+ ret_from_intr+0x0/0x30
+ cpuidle_enter+0x17/0x20
+ cpu_startup_entry+0x315/0x3e0
+ rest_init+0x7c/0x80
+ } hitcount: 3 bytes_req: 21 bytes_alloc: 24
+ { stacktrace:
+ __kmalloc_track_caller+0x10b/0x1a0
+ kmemdup+0x20/0x50
+ hidraw_report_event+0x8a/0x120 [hid]
+ hid_report_raw_event+0x3ea/0x440 [hid]
+ hid_input_report+0x112/0x190 [hid]
+ hid_irq_in+0xc2/0x260 [usbhid]
+ __usb_hcd_giveback_urb+0x72/0x120
+ usb_giveback_urb_bh+0x9e/0xe0
+ tasklet_hi_action+0xf8/0x100
+ __do_softirq+0x114/0x2c0
+ irq_exit+0xa5/0xb0
+ do_IRQ+0x5a/0xf0
+ ret_from_intr+0x0/0x30
+ } hitcount: 3 bytes_req: 21 bytes_alloc: 24
+ { stacktrace:
+ kmem_cache_alloc_trace+0xeb/0x150
+ aa_alloc_task_context+0x27/0x40
+ apparmor_cred_prepare+0x1f/0x50
+ security_prepare_creds+0x16/0x20
+ prepare_creds+0xdf/0x1a0
+ SyS_capset+0xb5/0x200
+ system_call_fastpath+0x12/0x6a
+ } hitcount: 1 bytes_req: 32 bytes_alloc: 32
+ .
+ .
+ .
+ { stacktrace:
+ __kmalloc+0x11b/0x1b0
+ i915_gem_execbuffer2+0x6c/0x2c0 [i915]
+ drm_ioctl+0x349/0x670 [drm]
+ do_vfs_ioctl+0x2f0/0x4f0
+ SyS_ioctl+0x81/0xa0
+ system_call_fastpath+0x12/0x6a
+ } hitcount: 17726 bytes_req: 13944120 bytes_alloc: 19593808
+ { stacktrace:
+ __kmalloc+0x11b/0x1b0
+ load_elf_phdrs+0x76/0xa0
+ load_elf_binary+0x102/0x1650
+ search_binary_handler+0x97/0x1d0
+ do_execveat_common.isra.34+0x551/0x6e0
+ SyS_execve+0x3a/0x50
+ return_from_execve+0x0/0x23
+ } hitcount: 33348 bytes_req: 17152128 bytes_alloc: 20226048
+ { stacktrace:
+ kmem_cache_alloc_trace+0xeb/0x150
+ apparmor_file_alloc_security+0x27/0x40
+ security_file_alloc+0x16/0x20
+ get_empty_filp+0x93/0x1c0
+ path_openat+0x31/0x5f0
+ do_filp_open+0x3a/0x90
+ do_sys_open+0x128/0x220
+ SyS_open+0x1e/0x20
+ system_call_fastpath+0x12/0x6a
+ } hitcount: 4766422 bytes_req: 9532844 bytes_alloc: 38131376
+ { stacktrace:
+ __kmalloc+0x11b/0x1b0
+ seq_buf_alloc+0x1b/0x50
+ seq_read+0x2cc/0x370
+ proc_reg_read+0x3d/0x80
+ __vfs_read+0x28/0xe0
+ vfs_read+0x86/0x140
+ SyS_read+0x46/0xb0
+ system_call_fastpath+0x12/0x6a
+ } hitcount: 19133 bytes_req: 78368768 bytes_alloc: 78368768
+
+ Totals:
+ Hits: 6085872
+ Entries: 253
+ Dropped: 0
+
+ If you key a hist trigger on common_pid, in order for example to
+ gather and display sorted totals for each process, you can use the
+ special .execname modifier to display the executable names for the
+ processes in the table rather than raw pids. The example below
+ keeps a per-process sum of total bytes read:
+
+ # echo 'hist:key=common_pid.execname:val=count:sort=count.descending' > \
+ /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/trigger
+
+ # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_read/hist
+ # trigger info: hist:keys=common_pid.execname:vals=count:sort=count.descending:size=2048 [active]
+
+ { common_pid: gnome-terminal [ 3196] } hitcount: 280 count: 1093512
+ { common_pid: Xorg [ 1309] } hitcount: 525 count: 256640
+ { common_pid: compiz [ 2889] } hitcount: 59 count: 254400
+ { common_pid: bash [ 8710] } hitcount: 3 count: 66369
+ { common_pid: dbus-daemon-lau [ 8703] } hitcount: 49 count: 47739
+ { common_pid: irqbalance [ 1252] } hitcount: 27 count: 27648
+ { common_pid: 01ifupdown [ 8705] } hitcount: 3 count: 17216
+ { common_pid: dbus-daemon [ 772] } hitcount: 10 count: 12396
+ { common_pid: Socket Thread [ 8342] } hitcount: 11 count: 11264
+ { common_pid: nm-dhcp-client. [ 8701] } hitcount: 6 count: 7424
+ { common_pid: gmain [ 1315] } hitcount: 18 count: 6336
+ .
+ .
+ .
+ { common_pid: postgres [ 1892] } hitcount: 2 count: 32
+ { common_pid: postgres [ 1891] } hitcount: 2 count: 32
+ { common_pid: gmain [ 8704] } hitcount: 2 count: 32
+ { common_pid: upstart-dbus-br [ 2740] } hitcount: 21 count: 21
+ { common_pid: nm-dispatcher.a [ 8696] } hitcount: 1 count: 16
+ { common_pid: indicator-datet [ 2904] } hitcount: 1 count: 16
+ { common_pid: gdbus [ 2998] } hitcount: 1 count: 16
+ { common_pid: rtkit-daemon [ 2052] } hitcount: 1 count: 8
+ { common_pid: init [ 1] } hitcount: 2 count: 2
+
+ Totals:
+ Hits: 2116
+ Entries: 51
+ Dropped: 0
+
+ Similarly, if you key a hist trigger on syscall id, for example to
+ gather and display a list of systemwide syscall hits, you can use
+ the special .syscall modifier to display the syscall names rather
+ than raw ids. The example below keeps a running total of syscall
+ counts for the system during the run:
+
+ # echo 'hist:key=id.syscall:val=hitcount' > \
+ /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
+
+ # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
+ # trigger info: hist:keys=id.syscall:vals=hitcount:sort=hitcount:size=2048 [active]
+
+ { id: sys_fsync [ 74] } hitcount: 1
+ { id: sys_newuname [ 63] } hitcount: 1
+ { id: sys_prctl [157] } hitcount: 1
+ { id: sys_statfs [137] } hitcount: 1
+ { id: sys_symlink [ 88] } hitcount: 1
+ { id: sys_sendmmsg [307] } hitcount: 1
+ { id: sys_semctl [ 66] } hitcount: 1
+ { id: sys_readlink [ 89] } hitcount: 3
+ { id: sys_bind [ 49] } hitcount: 3
+ { id: sys_getsockname [ 51] } hitcount: 3
+ { id: sys_unlink [ 87] } hitcount: 3
+ { id: sys_rename [ 82] } hitcount: 4
+ { id: unknown_syscall [ 58] } hitcount: 4
+ { id: sys_connect [ 42] } hitcount: 4
+ { id: sys_getpid [ 39] } hitcount: 4
+ .
+ .
+ .
+ { id: sys_rt_sigprocmask [ 14] } hitcount: 952
+ { id: sys_futex [202] } hitcount: 1534
+ { id: sys_write [ 1] } hitcount: 2689
+ { id: sys_setitimer [ 38] } hitcount: 2797
+ { id: sys_read [ 0] } hitcount: 3202
+ { id: sys_select [ 23] } hitcount: 3773
+ { id: sys_writev [ 20] } hitcount: 4531
+ { id: sys_poll [ 7] } hitcount: 8314
+ { id: sys_recvmsg [ 47] } hitcount: 13738
+ { id: sys_ioctl [ 16] } hitcount: 21843
+
+ Totals:
+ Hits: 67612
+ Entries: 72
+ Dropped: 0
+
+ The syscall counts above provide a rough overall picture of system
+ call activity on the system; we can see for example that the most
+ popular system call on this system was the 'sys_ioctl' system call.
+
+ We can use 'compound' keys to refine that number and provide some
+ further insight as to which processes exactly contribute to the
+ overall ioctl count.
+
+ The command below keeps a hitcount for every unique combination of
+ system call id and pid - the end result is essentially a table
+ that keeps a per-pid sum of system call hits. The results are
+ sorted using the system call id as the primary key, and the
+ hitcount sum as the secondary key:
+
+ # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount' > \
+ /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
+
+ # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
+ # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 [active]
+
+ { id: sys_read [ 0], common_pid: rtkit-daemon [ 1877] } hitcount: 1
+ { id: sys_read [ 0], common_pid: gdbus [ 2976] } hitcount: 1
+ { id: sys_read [ 0], common_pid: console-kit-dae [ 3400] } hitcount: 1
+ { id: sys_read [ 0], common_pid: postgres [ 1865] } hitcount: 1
+ { id: sys_read [ 0], common_pid: deja-dup-monito [ 3543] } hitcount: 2
+ { id: sys_read [ 0], common_pid: NetworkManager [ 890] } hitcount: 2
+ { id: sys_read [ 0], common_pid: evolution-calen [ 3048] } hitcount: 2
+ { id: sys_read [ 0], common_pid: postgres [ 1864] } hitcount: 2
+ { id: sys_read [ 0], common_pid: nm-applet [ 3022] } hitcount: 2
+ { id: sys_read [ 0], common_pid: whoopsie [ 1212] } hitcount: 2
+ .
+ .
+ .
+ { id: sys_ioctl [ 16], common_pid: bash [ 8479] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: bash [ 3472] } hitcount: 12
+ { id: sys_ioctl [ 16], common_pid: gnome-terminal [ 3199] } hitcount: 16
+ { id: sys_ioctl [ 16], common_pid: Xorg [ 1267] } hitcount: 1808
+ { id: sys_ioctl [ 16], common_pid: compiz [ 2994] } hitcount: 5580
+ .
+ .
+ .
+ { id: sys_waitid [247], common_pid: upstart-dbus-br [ 2690] } hitcount: 3
+ { id: sys_waitid [247], common_pid: upstart-dbus-br [ 2688] } hitcount: 16
+ { id: sys_inotify_add_watch [254], common_pid: gmain [ 975] } hitcount: 2
+ { id: sys_inotify_add_watch [254], common_pid: gmain [ 3204] } hitcount: 4
+ { id: sys_inotify_add_watch [254], common_pid: gmain [ 2888] } hitcount: 4
+ { id: sys_inotify_add_watch [254], common_pid: gmain [ 3003] } hitcount: 4
+ { id: sys_inotify_add_watch [254], common_pid: gmain [ 2873] } hitcount: 4
+ { id: sys_inotify_add_watch [254], common_pid: gmain [ 3196] } hitcount: 6
+ { id: sys_openat [257], common_pid: java [ 2623] } hitcount: 2
+ { id: sys_eventfd2 [290], common_pid: ibus-ui-gtk3 [ 2760] } hitcount: 4
+ { id: sys_eventfd2 [290], common_pid: compiz [ 2994] } hitcount: 6
+
+ Totals:
+ Hits: 31536
+ Entries: 323
+ Dropped: 0
+
+ The above list does give us a breakdown of the ioctl syscall by
+ pid, but it also gives us quite a bit more than that, which we
+ don't really care about at the moment. Since we know the syscall
+ id for sys_ioctl (16, displayed next to the sys_ioctl name), we
+ can use that to filter out all the other syscalls:
+
+ # echo 'hist:key=id.syscall,common_pid.execname:val=hitcount:sort=id,hitcount if id == 16' > \
+ /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/trigger
+
+ # cat /sys/kernel/debug/tracing/events/raw_syscalls/sys_enter/hist
+ # trigger info: hist:keys=id.syscall,common_pid.execname:vals=hitcount:sort=id.syscall,hitcount:size=2048 if id == 16 [active]
+
+ { id: sys_ioctl [ 16], common_pid: gmain [ 2769] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: evolution-addre [ 8571] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: gmain [ 3003] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: gmain [ 2781] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: gmain [ 2829] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: bash [ 8726] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: bash [ 8508] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: gmain [ 2970] } hitcount: 1
+ { id: sys_ioctl [ 16], common_pid: gmain [ 2768] } hitcount: 1
+ .
+ .
+ .
+ { id: sys_ioctl [ 16], common_pid: pool [ 8559] } hitcount: 45
+ { id: sys_ioctl [ 16], common_pid: pool [ 8555] } hitcount: 48
+ { id: sys_ioctl [ 16], common_pid: pool [ 8551] } hitcount: 48
+ { id: sys_ioctl [ 16], common_pid: avahi-daemon [ 896] } hitcount: 66
+ { id: sys_ioctl [ 16], common_pid: Xorg [ 1267] } hitcount: 26674
+ { id: sys_ioctl [ 16], common_pid: compiz [ 2994] } hitcount: 73443
+
+ Totals:
+ Hits: 101162
+ Entries: 103
+ Dropped: 0
+
+ The above output shows that 'compiz' and 'Xorg' are far and away
+ the heaviest ioctl callers (which might lead to questions about
+ whether they really need to be making all those calls and to
+ possible avenues for further investigation.)
+
+ The compound key examples used a key and a sum value (hitcount) to
+ sort the output, but we can just as easily use two keys instead.
+ Here's an example where we use a compound key composed of the the
+ common_pid and size event fields. Sorting with pid as the primary
+ key and 'size' as the secondary key allows us to display an
+ ordered summary of the recvfrom sizes, with counts, received by
+ each process:
+
+ # echo 'hist:key=common_pid.execname,size:val=hitcount:sort=common_pid,size' > \
+ /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/trigger
+
+ # cat /sys/kernel/debug/tracing/events/syscalls/sys_enter_recvfrom/hist
+ # trigger info: hist:keys=common_pid.execname,size:vals=hitcount:sort=common_pid.execname,size:size=2048 [active]
+
+ { common_pid: smbd [ 784], size: 4 } hitcount: 1
+ { common_pid: dnsmasq [ 1412], size: 4096 } hitcount: 672
+ { common_pid: postgres [ 1796], size: 1000 } hitcount: 6
+ { common_pid: postgres [ 1867], size: 1000 } hitcount: 10
+ { common_pid: bamfdaemon [ 2787], size: 28 } hitcount: 2
+ { common_pid: bamfdaemon [ 2787], size: 14360 } hitcount: 1
+ { common_pid: compiz [ 2994], size: 8 } hitcount: 1
+ { common_pid: compiz [ 2994], size: 20 } hitcount: 11
+ { common_pid: gnome-terminal [ 3199], size: 4 } hitcount: 2
+ { common_pid: firefox [ 8817], size: 4 } hitcount: 1
+ { common_pid: firefox [ 8817], size: 8 } hitcount: 5
+ { common_pid: firefox [ 8817], size: 588 } hitcount: 2
+ { common_pid: firefox [ 8817], size: 628 } hitcount: 1
+ { common_pid: firefox [ 8817], size: 6944 } hitcount: 1
+ { common_pid: firefox [ 8817], size: 408880 } hitcount: 2
+ { common_pid: firefox [ 8822], size: 8 } hitcount: 2
+ { common_pid: firefox [ 8822], size: 160 } hitcount: 2
+ { common_pid: firefox [ 8822], size: 320 } hitcount: 2
+ { common_pid: firefox [ 8822], size: 352 } hitcount: 1
+ .
+ .
+ .
+ { common_pid: pool [ 8923], size: 1960 } hitcount: 10
+ { common_pid: pool [ 8923], size: 2048 } hitcount: 10
+ { common_pid: pool [ 8924], size: 1960 } hitcount: 10
+ { common_pid: pool [ 8924], size: 2048 } hitcount: 10
+ { common_pid: pool [ 8928], size: 1964 } hitcount: 4
+ { common_pid: pool [ 8928], size: 1965 } hitcount: 2
+ { common_pid: pool [ 8928], size: 2048 } hitcount: 6
+ { common_pid: pool [ 8929], size: 1982 } hitcount: 1
+ { common_pid: pool [ 8929], size: 2048 } hitcount: 1
+
+ Totals:
+ Hits: 2016
+ Entries: 224
+ Dropped: 0
+
+ The above example also illustrates the fact that although a compound
+ key is treated as a single entity for hashing purposes, the sub-keys
+ it's composed of can be accessed independently.
+
+ The next example uses a string field as the hash key and
+ demonstrates how you can manually pause and continue a hist trigger.
+ In this example, we'll aggregate fork counts and don't expect a
+ large number of entries in the hash table, so we'll drop it to a
+ much smaller number, say 256:
+
+ # echo 'hist:key=child_comm:val=hitcount:size=256' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+ # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
+
+ { child_comm: dconf worker } hitcount: 1
+ { child_comm: ibus-daemon } hitcount: 1
+ { child_comm: whoopsie } hitcount: 1
+ { child_comm: smbd } hitcount: 1
+ { child_comm: gdbus } hitcount: 1
+ { child_comm: kthreadd } hitcount: 1
+ { child_comm: dconf worker } hitcount: 1
+ { child_comm: evolution-alarm } hitcount: 2
+ { child_comm: Socket Thread } hitcount: 2
+ { child_comm: postgres } hitcount: 2
+ { child_comm: bash } hitcount: 3
+ { child_comm: compiz } hitcount: 3
+ { child_comm: evolution-sourc } hitcount: 4
+ { child_comm: dhclient } hitcount: 4
+ { child_comm: pool } hitcount: 5
+ { child_comm: nm-dispatcher.a } hitcount: 8
+ { child_comm: firefox } hitcount: 8
+ { child_comm: dbus-daemon } hitcount: 8
+ { child_comm: glib-pacrunner } hitcount: 10
+ { child_comm: evolution } hitcount: 23
+
+ Totals:
+ Hits: 89
+ Entries: 20
+ Dropped: 0
+
+ If we want to pause the hist trigger, we can simply append :pause to
+ the command that started the trigger. Notice that the trigger info
+ displays as [paused]:
+
+ # echo 'hist:key=child_comm:val=hitcount:size=256:pause' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+ # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [paused]
+
+ { child_comm: dconf worker } hitcount: 1
+ { child_comm: kthreadd } hitcount: 1
+ { child_comm: dconf worker } hitcount: 1
+ { child_comm: gdbus } hitcount: 1
+ { child_comm: ibus-daemon } hitcount: 1
+ { child_comm: Socket Thread } hitcount: 2
+ { child_comm: evolution-alarm } hitcount: 2
+ { child_comm: smbd } hitcount: 2
+ { child_comm: bash } hitcount: 3
+ { child_comm: whoopsie } hitcount: 3
+ { child_comm: compiz } hitcount: 3
+ { child_comm: evolution-sourc } hitcount: 4
+ { child_comm: pool } hitcount: 5
+ { child_comm: postgres } hitcount: 6
+ { child_comm: firefox } hitcount: 8
+ { child_comm: dhclient } hitcount: 10
+ { child_comm: emacs } hitcount: 12
+ { child_comm: dbus-daemon } hitcount: 20
+ { child_comm: nm-dispatcher.a } hitcount: 20
+ { child_comm: evolution } hitcount: 35
+ { child_comm: glib-pacrunner } hitcount: 59
+
+ Totals:
+ Hits: 199
+ Entries: 21
+ Dropped: 0
+
+ To manually continue having the trigger aggregate events, append
+ :cont instead. Notice that the trigger info displays as [active]
+ again, and the data has changed:
+
+ # echo 'hist:key=child_comm:val=hitcount:size=256:cont' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+ # trigger info: hist:keys=child_comm:vals=hitcount:sort=hitcount:size=256 [active]
+
+ { child_comm: dconf worker } hitcount: 1
+ { child_comm: dconf worker } hitcount: 1
+ { child_comm: kthreadd } hitcount: 1
+ { child_comm: gdbus } hitcount: 1
+ { child_comm: ibus-daemon } hitcount: 1
+ { child_comm: Socket Thread } hitcount: 2
+ { child_comm: evolution-alarm } hitcount: 2
+ { child_comm: smbd } hitcount: 2
+ { child_comm: whoopsie } hitcount: 3
+ { child_comm: compiz } hitcount: 3
+ { child_comm: evolution-sourc } hitcount: 4
+ { child_comm: bash } hitcount: 5
+ { child_comm: pool } hitcount: 5
+ { child_comm: postgres } hitcount: 6
+ { child_comm: firefox } hitcount: 8
+ { child_comm: dhclient } hitcount: 11
+ { child_comm: emacs } hitcount: 12
+ { child_comm: dbus-daemon } hitcount: 22
+ { child_comm: nm-dispatcher.a } hitcount: 22
+ { child_comm: evolution } hitcount: 35
+ { child_comm: glib-pacrunner } hitcount: 59
+
+ Totals:
+ Hits: 206
+ Entries: 21
+ Dropped: 0
+
+ The previous example showed how to start and stop a hist trigger by
+ appending 'pause' and 'continue' to the hist trigger command. A
+ hist trigger can also be started in a paused state by initially
+ starting the trigger with ':pause' appended. This allows you to
+ start the trigger only when you're ready to start collecting data
+ and not before. For example, you could start the trigger in a
+ paused state, then unpause it and do something you want to measure,
+ then pause the trigger again when done.
+
+ Of course, doing this manually can be difficult and error-prone, but
+ it is possible to automatically start and stop a hist trigger based
+ on some condition, via the enable_hist and disable_hist triggers.
+
+ For example, suppose we wanted to take a look at the relative
+ weights in terms of skb length for each callpath that leads to a
+ netif_receieve_skb event when downloading a decent-sized file using
+ wget.
+
+ First we set up an initially paused stacktrace trigger on the
+ netif_receive_skb event:
+
+ # echo 'hist:key=stacktrace:vals=len:pause' > \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+
+ Next, we set up an 'enable_hist' trigger on the sched_process_exec
+ event, with an 'if filename==/usr/bin/wget' filter. The effect of
+ this new trigger is that it will 'unpause' the hist trigger we just
+ set up on netif_receive_skb if and only if it sees a
+ sched_process_exec event with a filename of '/usr/bin/wget'. When
+ that happens, all netif_receive_skb events are aggregated into a
+ hash table keyed on stacktrace:
+
+ # echo 'enable_hist:net:netif_receive_skb if filename==/usr/bin/wget' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+
+ The aggregation continues until the netif_receive_skb is paused
+ again, which is what the following disable_hist event does by
+ creating a similar setup on the sched_process_exit event, using the
+ filter 'comm==wget':
+
+ # echo 'disable_hist:net:netif_receive_skb if comm==wget' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+
+ Whenever a process exits and the comm field of the disable_hist
+ trigger filter matches 'comm==wget', the netif_receive_skb hist
+ trigger is disabled.
+
+ The overall effect is that netif_receive_skb events are aggregated
+ into the hash table for only the duration of the wget. Executing a
+ wget command and then listing the 'hist' file will display the
+ output generated by the wget command:
+
+ $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
+
+ # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
+ # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
+
+ { stacktrace:
+ __netif_receive_skb_core+0x46d/0x990
+ __netif_receive_skb+0x18/0x60
+ netif_receive_skb_internal+0x23/0x90
+ napi_gro_receive+0xc8/0x100
+ ieee80211_deliver_skb+0xd6/0x270 [mac80211]
+ ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
+ ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
+ ieee80211_rx+0x31d/0x900 [mac80211]
+ iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
+ iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
+ iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
+ irq_thread_fn+0x20/0x50
+ irq_thread+0x11f/0x150
+ kthread+0xd2/0xf0
+ ret_from_fork+0x42/0x70
+ } hitcount: 85 len: 28884
+ { stacktrace:
+ __netif_receive_skb_core+0x46d/0x990
+ __netif_receive_skb+0x18/0x60
+ netif_receive_skb_internal+0x23/0x90
+ napi_gro_complete+0xa4/0xe0
+ dev_gro_receive+0x23a/0x360
+ napi_gro_receive+0x30/0x100
+ ieee80211_deliver_skb+0xd6/0x270 [mac80211]
+ ieee80211_rx_handlers+0xccf/0x22f0 [mac80211]
+ ieee80211_prepare_and_rx_handle+0x4e7/0xc40 [mac80211]
+ ieee80211_rx+0x31d/0x900 [mac80211]
+ iwlagn_rx_reply_rx+0x3db/0x6f0 [iwldvm]
+ iwl_rx_dispatch+0x8e/0xf0 [iwldvm]
+ iwl_pcie_irq_handler+0xe3c/0x12f0 [iwlwifi]
+ irq_thread_fn+0x20/0x50
+ irq_thread+0x11f/0x150
+ kthread+0xd2/0xf0
+ } hitcount: 98 len: 664329
+ { stacktrace:
+ __netif_receive_skb_core+0x46d/0x990
+ __netif_receive_skb+0x18/0x60
+ process_backlog+0xa8/0x150
+ net_rx_action+0x15d/0x340
+ __do_softirq+0x114/0x2c0
+ do_softirq_own_stack+0x1c/0x30
+ do_softirq+0x65/0x70
+ __local_bh_enable_ip+0xb5/0xc0
+ ip_finish_output+0x1f4/0x840
+ ip_output+0x6b/0xc0
+ ip_local_out_sk+0x31/0x40
+ ip_send_skb+0x1a/0x50
+ udp_send_skb+0x173/0x2a0
+ udp_sendmsg+0x2bf/0x9f0
+ inet_sendmsg+0x64/0xa0
+ sock_sendmsg+0x3d/0x50
+ } hitcount: 115 len: 13030
+ { stacktrace:
+ __netif_receive_skb_core+0x46d/0x990
+ __netif_receive_skb+0x18/0x60
+ netif_receive_skb_internal+0x23/0x90
+ napi_gro_complete+0xa4/0xe0
+ napi_gro_flush+0x6d/0x90
+ iwl_pcie_irq_handler+0x92a/0x12f0 [iwlwifi]
+ irq_thread_fn+0x20/0x50
+ irq_thread+0x11f/0x150
+ kthread+0xd2/0xf0
+ ret_from_fork+0x42/0x70
+ } hitcount: 934 len: 5512212
+
+ Totals:
+ Hits: 1232
+ Entries: 4
+ Dropped: 0
+
+ The above shows all the netif_receive_skb callpaths and their total
+ lengths for the duration of the wget command.
+
+ The 'clear' hist trigger param can be used to clear the hash table.
+ Suppose we wanted to try another run of the previous example but
+ this time also wanted to see the complete list of events that went
+ into the histogram. In order to avoid having to set everything up
+ again, we can just clear the histogram first:
+
+ # echo 'hist:key=stacktrace:vals=len:clear' >> \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+
+ Just to verify that it is in fact cleared, here's what we now see in
+ the hist file:
+
+ # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
+ # trigger info: hist:keys=stacktrace:vals=len:sort=hitcount:size=2048 [paused]
+
+ Totals:
+ Hits: 0
+ Entries: 0
+ Dropped: 0
+
+ Since we want to see the detailed list of every netif_receive_skb
+ event occurring during the new run, which are in fact the same
+ events being aggregated into the hash table, we add some additional
+ 'enable_event' events to the triggering sched_process_exec and
+ sched_process_exit events as such:
+
+ # echo 'enable_event:net:netif_receive_skb if filename==/usr/bin/wget' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+
+ # echo 'disable_event:net:netif_receive_skb if comm==wget' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+
+ If you read the trigger files for the sched_process_exec and
+ sched_process_exit triggers, you should see two triggers for each:
+ one enabling/disabling the hist aggregation and the other
+ enabling/disabling the logging of events:
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_process_exec/trigger
+ enable_event:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
+ enable_hist:net:netif_receive_skb:unlimited if filename==/usr/bin/wget
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_process_exit/trigger
+ enable_event:net:netif_receive_skb:unlimited if comm==wget
+ disable_hist:net:netif_receive_skb:unlimited if comm==wget
+
+ In other words, whenever either of the sched_process_exec or
+ sched_process_exit events is hit and matches 'wget', it enables or
+ disables both the histogram and the event log, and what you end up
+ with is a hash table and set of events just covering the specified
+ duration. Run the wget command again:
+
+ $ wget https://www.kernel.org/pub/linux/kernel/v3.x/patch-3.19.xz
+
+ Displaying the 'hist' file should show something similar to what you
+ saw in the last run, but this time you should also see the
+ individual events in the trace file:
+
+ # cat /sys/kernel/debug/tracing/trace
+
+ # tracer: nop
+ #
+ # entries-in-buffer/entries-written: 183/1426 #P:4
+ #
+ # _-----=> irqs-off
+ # / _----=> need-resched
+ # | / _---=> hardirq/softirq
+ # || / _--=> preempt-depth
+ # ||| / delay
+ # TASK-PID CPU# |||| TIMESTAMP FUNCTION
+ # | | | |||| | |
+ wget-15108 [000] ..s1 31769.606929: netif_receive_skb: dev=lo skbaddr=ffff88009c353100 len=60
+ wget-15108 [000] ..s1 31769.606999: netif_receive_skb: dev=lo skbaddr=ffff88009c353200 len=60
+ dnsmasq-1382 [000] ..s1 31769.677652: netif_receive_skb: dev=lo skbaddr=ffff88009c352b00 len=130
+ dnsmasq-1382 [000] ..s1 31769.685917: netif_receive_skb: dev=lo skbaddr=ffff88009c352200 len=138
+ ##### CPU 2 buffer started ####
+ irq/29-iwlwifi-559 [002] ..s. 31772.031529: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433d00 len=2948
+ irq/29-iwlwifi-559 [002] ..s. 31772.031572: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432200 len=1500
+ irq/29-iwlwifi-559 [002] ..s. 31772.032196: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433100 len=2948
+ irq/29-iwlwifi-559 [002] ..s. 31772.032761: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d433000 len=2948
+ irq/29-iwlwifi-559 [002] ..s. 31772.033220: netif_receive_skb: dev=wlan0 skbaddr=ffff88009d432e00 len=1500
+ .
+ .
+ .
+
+ The following example demonstrates how multiple hist triggers can be
+ attached to a given event. This capability can be useful for
+ creating a set of different summaries derived from the same set of
+ events, or for comparing the effects of different filters, among
+ other things.
+
+ # echo 'hist:keys=skbaddr.hex:vals=len if len < 0' >> \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+ # echo 'hist:keys=skbaddr.hex:vals=len if len > 4096' >> \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+ # echo 'hist:keys=skbaddr.hex:vals=len if len == 256' >> \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+ # echo 'hist:keys=skbaddr.hex:vals=len' >> \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+ # echo 'hist:keys=len:vals=common_preempt_count' >> \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+
+ The above set of commands create four triggers differing only in
+ their filters, along with a completely different though fairly
+ nonsensical trigger. Note that in order to append multiple hist
+ triggers to the same file, you should use the '>>' operator to
+ append them ('>' will also add the new hist trigger, but will remove
+ any existing hist triggers beforehand).
+
+ Displaying the contents of the 'hist' file for the event shows the
+ contents of all five histograms:
+
+ # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist
+
+ # event histogram
+ #
+ # trigger info: hist:keys=len:vals=hitcount,common_preempt_count:sort=hitcount:size=2048 [active]
+ #
+
+ { len: 176 } hitcount: 1 common_preempt_count: 0
+ { len: 223 } hitcount: 1 common_preempt_count: 0
+ { len: 4854 } hitcount: 1 common_preempt_count: 0
+ { len: 395 } hitcount: 1 common_preempt_count: 0
+ { len: 177 } hitcount: 1 common_preempt_count: 0
+ { len: 446 } hitcount: 1 common_preempt_count: 0
+ { len: 1601 } hitcount: 1 common_preempt_count: 0
+ .
+ .
+ .
+ { len: 1280 } hitcount: 66 common_preempt_count: 0
+ { len: 116 } hitcount: 81 common_preempt_count: 40
+ { len: 708 } hitcount: 112 common_preempt_count: 0
+ { len: 46 } hitcount: 221 common_preempt_count: 0
+ { len: 1264 } hitcount: 458 common_preempt_count: 0
+
+ Totals:
+ Hits: 1428
+ Entries: 147
+ Dropped: 0
+
+
+ # event histogram
+ #
+ # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
+ #
+
+ { skbaddr: ffff8800baee5e00 } hitcount: 1 len: 130
+ { skbaddr: ffff88005f3d5600 } hitcount: 1 len: 1280
+ { skbaddr: ffff88005f3d4900 } hitcount: 1 len: 1280
+ { skbaddr: ffff88009fed6300 } hitcount: 1 len: 115
+ { skbaddr: ffff88009fe0ad00 } hitcount: 1 len: 115
+ { skbaddr: ffff88008cdb1900 } hitcount: 1 len: 46
+ { skbaddr: ffff880064b5ef00 } hitcount: 1 len: 118
+ { skbaddr: ffff880044e3c700 } hitcount: 1 len: 60
+ { skbaddr: ffff880100065900 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d46bd500 } hitcount: 1 len: 116
+ { skbaddr: ffff88005f3d5f00 } hitcount: 1 len: 1280
+ { skbaddr: ffff880100064700 } hitcount: 1 len: 365
+ { skbaddr: ffff8800badb6f00 } hitcount: 1 len: 60
+ .
+ .
+ .
+ { skbaddr: ffff88009fe0be00 } hitcount: 27 len: 24677
+ { skbaddr: ffff88009fe0a400 } hitcount: 27 len: 23052
+ { skbaddr: ffff88009fe0b700 } hitcount: 31 len: 25589
+ { skbaddr: ffff88009fe0b600 } hitcount: 32 len: 27326
+ { skbaddr: ffff88006a462800 } hitcount: 68 len: 71678
+ { skbaddr: ffff88006a463700 } hitcount: 70 len: 72678
+ { skbaddr: ffff88006a462b00 } hitcount: 71 len: 77589
+ { skbaddr: ffff88006a463600 } hitcount: 73 len: 71307
+ { skbaddr: ffff88006a462200 } hitcount: 81 len: 81032
+
+ Totals:
+ Hits: 1451
+ Entries: 318
+ Dropped: 0
+
+
+ # event histogram
+ #
+ # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len == 256 [active]
+ #
+
+
+ Totals:
+ Hits: 0
+ Entries: 0
+ Dropped: 0
+
+
+ # event histogram
+ #
+ # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len > 4096 [active]
+ #
+
+ { skbaddr: ffff88009fd2c300 } hitcount: 1 len: 7212
+ { skbaddr: ffff8800d2bcce00 } hitcount: 1 len: 7212
+ { skbaddr: ffff8800d2bcd700 } hitcount: 1 len: 7212
+ { skbaddr: ffff8800d2bcda00 } hitcount: 1 len: 21492
+ { skbaddr: ffff8800ae2e2d00 } hitcount: 1 len: 7212
+ { skbaddr: ffff8800d2bcdb00 } hitcount: 1 len: 7212
+ { skbaddr: ffff88006a4df500 } hitcount: 1 len: 4854
+ { skbaddr: ffff88008ce47b00 } hitcount: 1 len: 18636
+ { skbaddr: ffff8800ae2e2200 } hitcount: 1 len: 12924
+ { skbaddr: ffff88005f3e1000 } hitcount: 1 len: 4356
+ { skbaddr: ffff8800d2bcdc00 } hitcount: 2 len: 24420
+ { skbaddr: ffff8800d2bcc200 } hitcount: 2 len: 12996
+
+ Totals:
+ Hits: 14
+ Entries: 12
+ Dropped: 0
+
+
+ # event histogram
+ #
+ # trigger info: hist:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 if len < 0 [active]
+ #
+
+
+ Totals:
+ Hits: 0
+ Entries: 0
+ Dropped: 0
+
+ Named triggers can be used to have triggers share a common set of
+ histogram data. This capability is mostly useful for combining the
+ output of events generated by tracepoints contained inside inline
+ functions, but names can be used in a hist trigger on any event.
+ For example, these two triggers when hit will update the same 'len'
+ field in the shared 'foo' histogram data:
+
+ # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
+ /sys/kernel/debug/tracing/events/net/netif_receive_skb/trigger
+ # echo 'hist:name=foo:keys=skbaddr.hex:vals=len' > \
+ /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+
+ You can see that they're updating common histogram data by reading
+ each event's hist files at the same time:
+
+ # cat /sys/kernel/debug/tracing/events/net/netif_receive_skb/hist;
+ cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
+
+ # event histogram
+ #
+ # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
+ #
+
+ { skbaddr: ffff88000ad53500 } hitcount: 1 len: 46
+ { skbaddr: ffff8800af5a1500 } hitcount: 1 len: 76
+ { skbaddr: ffff8800d62a1900 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bccb00 } hitcount: 1 len: 468
+ { skbaddr: ffff8800d3c69900 } hitcount: 1 len: 46
+ { skbaddr: ffff88009ff09100 } hitcount: 1 len: 52
+ { skbaddr: ffff88010f13ab00 } hitcount: 1 len: 168
+ { skbaddr: ffff88006a54f400 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bcc500 } hitcount: 1 len: 260
+ { skbaddr: ffff880064505000 } hitcount: 1 len: 46
+ { skbaddr: ffff8800baf24e00 } hitcount: 1 len: 32
+ { skbaddr: ffff88009fe0ad00 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d3edff00 } hitcount: 1 len: 44
+ { skbaddr: ffff88009fe0b400 } hitcount: 1 len: 168
+ { skbaddr: ffff8800a1c55a00 } hitcount: 1 len: 40
+ { skbaddr: ffff8800d2bcd100 } hitcount: 1 len: 40
+ { skbaddr: ffff880064505f00 } hitcount: 1 len: 174
+ { skbaddr: ffff8800a8bff200 } hitcount: 1 len: 160
+ { skbaddr: ffff880044e3cc00 } hitcount: 1 len: 76
+ { skbaddr: ffff8800a8bfe700 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bcdc00 } hitcount: 1 len: 32
+ { skbaddr: ffff8800a1f64800 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bcde00 } hitcount: 1 len: 988
+ { skbaddr: ffff88006a5dea00 } hitcount: 1 len: 46
+ { skbaddr: ffff88002e37a200 } hitcount: 1 len: 44
+ { skbaddr: ffff8800a1f32c00 } hitcount: 2 len: 676
+ { skbaddr: ffff88000ad52600 } hitcount: 2 len: 107
+ { skbaddr: ffff8800a1f91e00 } hitcount: 2 len: 92
+ { skbaddr: ffff8800af5a0200 } hitcount: 2 len: 142
+ { skbaddr: ffff8800d2bcc600 } hitcount: 2 len: 220
+ { skbaddr: ffff8800ba36f500 } hitcount: 2 len: 92
+ { skbaddr: ffff8800d021f800 } hitcount: 2 len: 92
+ { skbaddr: ffff8800a1f33600 } hitcount: 2 len: 675
+ { skbaddr: ffff8800a8bfff00 } hitcount: 3 len: 138
+ { skbaddr: ffff8800d62a1300 } hitcount: 3 len: 138
+ { skbaddr: ffff88002e37a100 } hitcount: 4 len: 184
+ { skbaddr: ffff880064504400 } hitcount: 4 len: 184
+ { skbaddr: ffff8800a8bfec00 } hitcount: 4 len: 184
+ { skbaddr: ffff88000ad53700 } hitcount: 5 len: 230
+ { skbaddr: ffff8800d2bcdb00 } hitcount: 5 len: 196
+ { skbaddr: ffff8800a1f90000 } hitcount: 6 len: 276
+ { skbaddr: ffff88006a54f900 } hitcount: 6 len: 276
+
+ Totals:
+ Hits: 81
+ Entries: 42
+ Dropped: 0
+ # event histogram
+ #
+ # trigger info: hist:name=foo:keys=skbaddr.hex:vals=hitcount,len:sort=hitcount:size=2048 [active]
+ #
+
+ { skbaddr: ffff88000ad53500 } hitcount: 1 len: 46
+ { skbaddr: ffff8800af5a1500 } hitcount: 1 len: 76
+ { skbaddr: ffff8800d62a1900 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bccb00 } hitcount: 1 len: 468
+ { skbaddr: ffff8800d3c69900 } hitcount: 1 len: 46
+ { skbaddr: ffff88009ff09100 } hitcount: 1 len: 52
+ { skbaddr: ffff88010f13ab00 } hitcount: 1 len: 168
+ { skbaddr: ffff88006a54f400 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bcc500 } hitcount: 1 len: 260
+ { skbaddr: ffff880064505000 } hitcount: 1 len: 46
+ { skbaddr: ffff8800baf24e00 } hitcount: 1 len: 32
+ { skbaddr: ffff88009fe0ad00 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d3edff00 } hitcount: 1 len: 44
+ { skbaddr: ffff88009fe0b400 } hitcount: 1 len: 168
+ { skbaddr: ffff8800a1c55a00 } hitcount: 1 len: 40
+ { skbaddr: ffff8800d2bcd100 } hitcount: 1 len: 40
+ { skbaddr: ffff880064505f00 } hitcount: 1 len: 174
+ { skbaddr: ffff8800a8bff200 } hitcount: 1 len: 160
+ { skbaddr: ffff880044e3cc00 } hitcount: 1 len: 76
+ { skbaddr: ffff8800a8bfe700 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bcdc00 } hitcount: 1 len: 32
+ { skbaddr: ffff8800a1f64800 } hitcount: 1 len: 46
+ { skbaddr: ffff8800d2bcde00 } hitcount: 1 len: 988
+ { skbaddr: ffff88006a5dea00 } hitcount: 1 len: 46
+ { skbaddr: ffff88002e37a200 } hitcount: 1 len: 44
+ { skbaddr: ffff8800a1f32c00 } hitcount: 2 len: 676
+ { skbaddr: ffff88000ad52600 } hitcount: 2 len: 107
+ { skbaddr: ffff8800a1f91e00 } hitcount: 2 len: 92
+ { skbaddr: ffff8800af5a0200 } hitcount: 2 len: 142
+ { skbaddr: ffff8800d2bcc600 } hitcount: 2 len: 220
+ { skbaddr: ffff8800ba36f500 } hitcount: 2 len: 92
+ { skbaddr: ffff8800d021f800 } hitcount: 2 len: 92
+ { skbaddr: ffff8800a1f33600 } hitcount: 2 len: 675
+ { skbaddr: ffff8800a8bfff00 } hitcount: 3 len: 138
+ { skbaddr: ffff8800d62a1300 } hitcount: 3 len: 138
+ { skbaddr: ffff88002e37a100 } hitcount: 4 len: 184
+ { skbaddr: ffff880064504400 } hitcount: 4 len: 184
+ { skbaddr: ffff8800a8bfec00 } hitcount: 4 len: 184
+ { skbaddr: ffff88000ad53700 } hitcount: 5 len: 230
+ { skbaddr: ffff8800d2bcdb00 } hitcount: 5 len: 196
+ { skbaddr: ffff8800a1f90000 } hitcount: 6 len: 276
+ { skbaddr: ffff88006a54f900 } hitcount: 6 len: 276
+
+ Totals:
+ Hits: 81
+ Entries: 42
+ Dropped: 0
+
+ And here's an example that shows how to combine histogram data from
+ any two events even if they don't share any 'compatible' fields
+ other than 'hitcount' and 'stacktrace'. These commands create a
+ couple of triggers named 'bar' using those fields:
+
+ # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
+ /sys/kernel/debug/tracing/events/sched/sched_process_fork/trigger
+ # echo 'hist:name=bar:key=stacktrace:val=hitcount' > \
+ /sys/kernel/debug/tracing/events/net/netif_rx/trigger
+
+ And displaying the output of either shows some interesting if
+ somewhat confusing output:
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_process_fork/hist
+ # cat /sys/kernel/debug/tracing/events/net/netif_rx/hist
+
+ # event histogram
+ #
+ # trigger info: hist:name=bar:keys=stacktrace:vals=hitcount:sort=hitcount:size=2048 [active]
+ #
+
+ { stacktrace:
+ _do_fork+0x18e/0x330
+ kernel_thread+0x29/0x30
+ kthreadd+0x154/0x1b0
+ ret_from_fork+0x3f/0x70
+ } hitcount: 1
+ { stacktrace:
+ netif_rx_internal+0xb2/0xd0
+ netif_rx_ni+0x20/0x70
+ dev_loopback_xmit+0xaa/0xd0
+ ip_mc_output+0x126/0x240
+ ip_local_out_sk+0x31/0x40
+ igmp_send_report+0x1e9/0x230
+ igmp_timer_expire+0xe9/0x120
+ call_timer_fn+0x39/0xf0
+ run_timer_softirq+0x1e1/0x290
+ __do_softirq+0xfd/0x290
+ irq_exit+0x98/0xb0
+ smp_apic_timer_interrupt+0x4a/0x60
+ apic_timer_interrupt+0x6d/0x80
+ cpuidle_enter+0x17/0x20
+ call_cpuidle+0x3b/0x60
+ cpu_startup_entry+0x22d/0x310
+ } hitcount: 1
+ { stacktrace:
+ netif_rx_internal+0xb2/0xd0
+ netif_rx_ni+0x20/0x70
+ dev_loopback_xmit+0xaa/0xd0
+ ip_mc_output+0x17f/0x240
+ ip_local_out_sk+0x31/0x40
+ ip_send_skb+0x1a/0x50
+ udp_send_skb+0x13e/0x270
+ udp_sendmsg+0x2bf/0x980
+ inet_sendmsg+0x67/0xa0
+ sock_sendmsg+0x38/0x50
+ SYSC_sendto+0xef/0x170
+ SyS_sendto+0xe/0x10
+ entry_SYSCALL_64_fastpath+0x12/0x6a
+ } hitcount: 2
+ { stacktrace:
+ netif_rx_internal+0xb2/0xd0
+ netif_rx+0x1c/0x60
+ loopback_xmit+0x6c/0xb0
+ dev_hard_start_xmit+0x219/0x3a0
+ __dev_queue_xmit+0x415/0x4f0
+ dev_queue_xmit_sk+0x13/0x20
+ ip_finish_output2+0x237/0x340
+ ip_finish_output+0x113/0x1d0
+ ip_output+0x66/0xc0
+ ip_local_out_sk+0x31/0x40
+ ip_send_skb+0x1a/0x50
+ udp_send_skb+0x16d/0x270
+ udp_sendmsg+0x2bf/0x980
+ inet_sendmsg+0x67/0xa0
+ sock_sendmsg+0x38/0x50
+ ___sys_sendmsg+0x14e/0x270
+ } hitcount: 76
+ { stacktrace:
+ netif_rx_internal+0xb2/0xd0
+ netif_rx+0x1c/0x60
+ loopback_xmit+0x6c/0xb0
+ dev_hard_start_xmit+0x219/0x3a0
+ __dev_queue_xmit+0x415/0x4f0
+ dev_queue_xmit_sk+0x13/0x20
+ ip_finish_output2+0x237/0x340
+ ip_finish_output+0x113/0x1d0
+ ip_output+0x66/0xc0
+ ip_local_out_sk+0x31/0x40
+ ip_send_skb+0x1a/0x50
+ udp_send_skb+0x16d/0x270
+ udp_sendmsg+0x2bf/0x980
+ inet_sendmsg+0x67/0xa0
+ sock_sendmsg+0x38/0x50
+ ___sys_sendmsg+0x269/0x270
+ } hitcount: 77
+ { stacktrace:
+ netif_rx_internal+0xb2/0xd0
+ netif_rx+0x1c/0x60
+ loopback_xmit+0x6c/0xb0
+ dev_hard_start_xmit+0x219/0x3a0
+ __dev_queue_xmit+0x415/0x4f0
+ dev_queue_xmit_sk+0x13/0x20
+ ip_finish_output2+0x237/0x340
+ ip_finish_output+0x113/0x1d0
+ ip_output+0x66/0xc0
+ ip_local_out_sk+0x31/0x40
+ ip_send_skb+0x1a/0x50
+ udp_send_skb+0x16d/0x270
+ udp_sendmsg+0x2bf/0x980
+ inet_sendmsg+0x67/0xa0
+ sock_sendmsg+0x38/0x50
+ SYSC_sendto+0xef/0x170
+ } hitcount: 88
+ { stacktrace:
+ _do_fork+0x18e/0x330
+ SyS_clone+0x19/0x20
+ entry_SYSCALL_64_fastpath+0x12/0x6a
+ } hitcount: 244
+
+ Totals:
+ Hits: 489
+ Entries: 7
+ Dropped: 0
+
+
+2.2 Inter-event hist triggers
+-----------------------------
+
+Inter-event hist triggers are hist triggers that combine values from
+one or more other events and create a histogram using that data. Data
+from an inter-event histogram can in turn become the source for
+further combined histograms, thus providing a chain of related
+histograms, which is important for some applications.
+
+The most important example of an inter-event quantity that can be used
+in this manner is latency, which is simply a difference in timestamps
+between two events. Although latency is the most important
+inter-event quantity, note that because the support is completely
+general across the trace event subsystem, any event field can be used
+in an inter-event quantity.
+
+An example of a histogram that combines data from other histograms
+into a useful chain would be a 'wakeupswitch latency' histogram that
+combines a 'wakeup latency' histogram and a 'switch latency'
+histogram.
+
+Normally, a hist trigger specification consists of a (possibly
+compound) key along with one or more numeric values, which are
+continually updated sums associated with that key. A histogram
+specification in this case consists of individual key and value
+specifications that refer to trace event fields associated with a
+single event type.
+
+The inter-event hist trigger extension allows fields from multiple
+events to be referenced and combined into a multi-event histogram
+specification. In support of this overall goal, a few enabling
+features have been added to the hist trigger support:
+
+ - In order to compute an inter-event quantity, a value from one
+ event needs to saved and then referenced from another event. This
+ requires the introduction of support for histogram 'variables'.
+
+ - The computation of inter-event quantities and their combination
+ require some minimal amount of support for applying simple
+ expressions to variables (+ and -).
+
+ - A histogram consisting of inter-event quantities isn't logically a
+ histogram on either event (so having the 'hist' file for either
+ event host the histogram output doesn't really make sense). To
+ address the idea that the histogram is associated with a
+ combination of events, support is added allowing the creation of
+ 'synthetic' events that are events derived from other events.
+ These synthetic events are full-fledged events just like any other
+ and can be used as such, as for instance to create the
+ 'combination' histograms mentioned previously.
+
+ - A set of 'actions' can be associated with histogram entries -
+ these can be used to generate the previously mentioned synthetic
+ events, but can also be used for other purposes, such as for
+ example saving context when a 'max' latency has been hit.
+
+ - Trace events don't have a 'timestamp' associated with them, but
+ there is an implicit timestamp saved along with an event in the
+ underlying ftrace ring buffer. This timestamp is now exposed as a
+ a synthetic field named 'common_timestamp' which can be used in
+ histograms as if it were any other event field; it isn't an actual
+ field in the trace format but rather is a synthesized value that
+ nonetheless can be used as if it were an actual field. By default
+ it is in units of nanoseconds; appending '.usecs' to a
+ common_timestamp field changes the units to microseconds.
+
+A note on inter-event timestamps: If common_timestamp is used in a
+histogram, the trace buffer is automatically switched over to using
+absolute timestamps and the "global" trace clock, in order to avoid
+bogus timestamp differences with other clocks that aren't coherent
+across CPUs. This can be overridden by specifying one of the other
+trace clocks instead, using the "clock=XXX" hist trigger attribute,
+where XXX is any of the clocks listed in the tracing/trace_clock
+pseudo-file.
+
+These features are described in more detail in the following sections.
+
+2.2.1 Histogram Variables
+-------------------------
+
+Variables are simply named locations used for saving and retrieving
+values between matching events. A 'matching' event is defined as an
+event that has a matching key - if a variable is saved for a histogram
+entry corresponding to that key, any subsequent event with a matching
+key can access that variable.
+
+A variable's value is normally available to any subsequent event until
+it is set to something else by a subsequent event. The one exception
+to that rule is that any variable used in an expression is essentially
+'read-once' - once it's used by an expression in a subsequent event,
+it's reset to its 'unset' state, which means it can't be used again
+unless it's set again. This ensures not only that an event doesn't
+use an uninitialized variable in a calculation, but that that variable
+is used only once and not for any unrelated subsequent match.
+
+The basic syntax for saving a variable is to simply prefix a unique
+variable name not corresponding to any keyword along with an '=' sign
+to any event field.
+
+Either keys or values can be saved and retrieved in this way. This
+creates a variable named 'ts0' for a histogram entry with the key
+'next_pid':
+
+ # echo 'hist:keys=next_pid:vals=$ts0:ts0=common_timestamp ... >> \
+ event/trigger
+
+The ts0 variable can be accessed by any subsequent event having the
+same pid as 'next_pid'.
+
+Variable references are formed by prepending the variable name with
+the '$' sign. Thus for example, the ts0 variable above would be
+referenced as '$ts0' in expressions.
+
+Because 'vals=' is used, the common_timestamp variable value above
+will also be summed as a normal histogram value would (though for a
+timestamp it makes little sense).
+
+The below shows that a key value can also be saved in the same way:
+
+ # echo 'hist:timer_pid=common_pid:key=timer_pid ...' >> event/trigger
+
+If a variable isn't a key variable or prefixed with 'vals=', the
+associated event field will be saved in a variable but won't be summed
+as a value:
+
+ # echo 'hist:keys=next_pid:ts1=common_timestamp ... >> event/trigger
+
+Multiple variables can be assigned at the same time. The below would
+result in both ts0 and b being created as variables, with both
+common_timestamp and field1 additionally being summed as values:
+
+ # echo 'hist:keys=pid:vals=$ts0,$b:ts0=common_timestamp,b=field1 ... >> \
+ event/trigger
+
+Note that variable assignments can appear either preceding or
+following their use. The command below behaves identically to the
+command above:
+
+ # echo 'hist:keys=pid:ts0=common_timestamp,b=field1:vals=$ts0,$b ... >> \
+ event/trigger
+
+Any number of variables not bound to a 'vals=' prefix can also be
+assigned by simply separating them with colons. Below is the same
+thing but without the values being summed in the histogram:
+
+ # echo 'hist:keys=pid:ts0=common_timestamp:b=field1 ... >> event/trigger
+
+Variables set as above can be referenced and used in expressions on
+another event.
+
+For example, here's how a latency can be calculated:
+
+ # echo 'hist:keys=pid,prio:ts0=common_timestamp ... >> event1/trigger
+ # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp-$ts0 ... >> event2/trigger
+
+In the first line above, the event's timetamp is saved into the
+variable ts0. In the next line, ts0 is subtracted from the second
+event's timestamp to produce the latency, which is then assigned into
+yet another variable, 'wakeup_lat'. The hist trigger below in turn
+makes use of the wakeup_lat variable to compute a combined latency
+using the same key and variable from yet another event:
+
+ # echo 'hist:key=pid:wakeupswitch_lat=$wakeup_lat+$switchtime_lat ... >> event3/trigger
+
+2.2.2 Synthetic Events
+----------------------
+
+Synthetic events are user-defined events generated from hist trigger
+variables or fields associated with one or more other events. Their
+purpose is to provide a mechanism for displaying data spanning
+multiple events consistent with the existing and already familiar
+usage for normal events.
+
+To define a synthetic event, the user writes a simple specification
+consisting of the name of the new event along with one or more
+variables and their types, which can be any valid field type,
+separated by semicolons, to the tracing/synthetic_events file.
+
+For instance, the following creates a new event named 'wakeup_latency'
+with 3 fields: lat, pid, and prio. Each of those fields is simply a
+variable reference to a variable on another event:
+
+ # echo 'wakeup_latency \
+ u64 lat; \
+ pid_t pid; \
+ int prio' >> \
+ /sys/kernel/debug/tracing/synthetic_events
+
+Reading the tracing/synthetic_events file lists all the currently
+defined synthetic events, in this case the event defined above:
+
+ # cat /sys/kernel/debug/tracing/synthetic_events
+ wakeup_latency u64 lat; pid_t pid; int prio
+
+An existing synthetic event definition can be removed by prepending
+the command that defined it with a '!':
+
+ # echo '!wakeup_latency u64 lat pid_t pid int prio' >> \
+ /sys/kernel/debug/tracing/synthetic_events
+
+At this point, there isn't yet an actual 'wakeup_latency' event
+instantiated in the event subsytem - for this to happen, a 'hist
+trigger action' needs to be instantiated and bound to actual fields
+and variables defined on other events (see Section 6.3.3 below).
+
+Once that is done, an event instance is created, and a histogram can
+be defined using it:
+
+ # echo 'hist:keys=pid,prio,lat.log2:sort=pid,lat' >> \
+ /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/trigger
+
+The new event is created under the tracing/events/synthetic/ directory
+and looks and behaves just like any other event:
+
+ # ls /sys/kernel/debug/tracing/events/synthetic/wakeup_latency
+ enable filter format hist id trigger
+
+Like any other event, once a histogram is enabled for the event, the
+output can be displayed by reading the event's 'hist' file.
+
+2.2.3 Hist trigger 'actions'
+----------------------------
+
+A hist trigger 'action' is a function that's executed whenever a
+histogram entry is added or updated.
+
+The default 'action' if no special function is explicity specified is
+as it always has been, to simply update the set of values associated
+with an entry. Some applications, however, may want to perform
+additional actions at that point, such as generate another event, or
+compare and save a maximum.
+
+The following additional actions are available. To specify an action
+for a given event, simply specify the action between colons in the
+hist trigger specification.
+
+ - onmatch(matching.event).<synthetic_event_name>(param list)
+
+ The 'onmatch(matching.event).<synthetic_event_name>(params)' hist
+ trigger action is invoked whenever an event matches and the
+ histogram entry would be added or updated. It causes the named
+ synthetic event to be generated with the values given in the
+ 'param list'. The result is the generation of a synthetic event
+ that consists of the values contained in those variables at the
+ time the invoking event was hit.
+
+ The 'param list' consists of one or more parameters which may be
+ either variables or fields defined on either the 'matching.event'
+ or the target event. The variables or fields specified in the
+ param list may be either fully-qualified or unqualified. If a
+ variable is specified as unqualified, it must be unique between
+ the two events. A field name used as a param can be unqualified
+ if it refers to the target event, but must be fully qualified if
+ it refers to the matching event. A fully-qualified name is of the
+ form 'system.event_name.$var_name' or 'system.event_name.field'.
+
+ The 'matching.event' specification is simply the fully qualified
+ event name of the event that matches the target event for the
+ onmatch() functionality, in the form 'system.event_name'.
+
+ Finally, the number and type of variables/fields in the 'param
+ list' must match the number and types of the fields in the
+ synthetic event being generated.
+
+ As an example the below defines a simple synthetic event and uses
+ a variable defined on the sched_wakeup_new event as a parameter
+ when invoking the synthetic event. Here we define the synthetic
+ event:
+
+ # echo 'wakeup_new_test pid_t pid' >> \
+ /sys/kernel/debug/tracing/synthetic_events
+
+ # cat /sys/kernel/debug/tracing/synthetic_events
+ wakeup_new_test pid_t pid
+
+ The following hist trigger both defines the missing testpid
+ variable and specifies an onmatch() action that generates a
+ wakeup_new_test synthetic event whenever a sched_wakeup_new event
+ occurs, which because of the 'if comm == "cyclictest"' filter only
+ happens when the executable is cyclictest:
+
+ # echo 'hist:keys=$testpid:testpid=pid:onmatch(sched.sched_wakeup_new).\
+ wakeup_new_test($testpid) if comm=="cyclictest"' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_wakeup_new/trigger
+
+ Creating and displaying a histogram based on those events is now
+ just a matter of using the fields and new synthetic event in the
+ tracing/events/synthetic directory, as usual:
+
+ # echo 'hist:keys=pid:sort=pid' >> \
+ /sys/kernel/debug/tracing/events/synthetic/wakeup_new_test/trigger
+
+ Running 'cyclictest' should cause wakeup_new events to generate
+ wakeup_new_test synthetic events which should result in histogram
+ output in the wakeup_new_test event's hist file:
+
+ # cat /sys/kernel/debug/tracing/events/synthetic/wakeup_new_test/hist
+
+ A more typical usage would be to use two events to calculate a
+ latency. The following example uses a set of hist triggers to
+ produce a 'wakeup_latency' histogram:
+
+ First, we define a 'wakeup_latency' synthetic event:
+
+ # echo 'wakeup_latency u64 lat; pid_t pid; int prio' >> \
+ /sys/kernel/debug/tracing/synthetic_events
+
+ Next, we specify that whenever we see a sched_waking event for a
+ cyclictest thread, save the timestamp in a 'ts0' variable:
+
+ # echo 'hist:keys=$saved_pid:saved_pid=pid:ts0=common_timestamp.usecs \
+ if comm=="cyclictest"' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_waking/trigger
+
+ Then, when the corresponding thread is actually scheduled onto the
+ CPU by a sched_switch event, calculate the latency and use that
+ along with another variable and an event field to generate a
+ wakeup_latency synthetic event:
+
+ # echo 'hist:keys=next_pid:wakeup_lat=common_timestamp.usecs-$ts0:\
+ onmatch(sched.sched_waking).wakeup_latency($wakeup_lat,\
+ $saved_pid,next_prio) if next_comm=="cyclictest"' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+
+ We also need to create a histogram on the wakeup_latency synthetic
+ event in order to aggregate the generated synthetic event data:
+
+ # echo 'hist:keys=pid,prio,lat:sort=pid,lat' >> \
+ /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/trigger
+
+ Finally, once we've run cyclictest to actually generate some
+ events, we can see the output by looking at the wakeup_latency
+ synthetic event's hist file:
+
+ # cat /sys/kernel/debug/tracing/events/synthetic/wakeup_latency/hist
+
+ - onmax(var).save(field,.. .)
+
+ The 'onmax(var).save(field,...)' hist trigger action is invoked
+ whenever the value of 'var' associated with a histogram entry
+ exceeds the current maximum contained in that variable.
+
+ The end result is that the trace event fields specified as the
+ onmax.save() params will be saved if 'var' exceeds the current
+ maximum for that hist trigger entry. This allows context from the
+ event that exhibited the new maximum to be saved for later
+ reference. When the histogram is displayed, additional fields
+ displaying the saved values will be printed.
+
+ As an example the below defines a couple of hist triggers, one for
+ sched_waking and another for sched_switch, keyed on pid. Whenever
+ a sched_waking occurs, the timestamp is saved in the entry
+ corresponding to the current pid, and when the scheduler switches
+ back to that pid, the timestamp difference is calculated. If the
+ resulting latency, stored in wakeup_lat, exceeds the current
+ maximum latency, the values specified in the save() fields are
+ recoreded:
+
+ # echo 'hist:keys=pid:ts0=common_timestamp.usecs \
+ if comm=="cyclictest"' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_waking/trigger
+
+ # echo 'hist:keys=next_pid:\
+ wakeup_lat=common_timestamp.usecs-$ts0:\
+ onmax($wakeup_lat).save(next_comm,prev_pid,prev_prio,prev_comm) \
+ if next_comm=="cyclictest"' >> \
+ /sys/kernel/debug/tracing/events/sched/sched_switch/trigger
+
+ When the histogram is displayed, the max value and the saved
+ values corresponding to the max are displayed following the rest
+ of the fields:
+
+ # cat /sys/kernel/debug/tracing/events/sched/sched_switch/hist
+ { next_pid: 2255 } hitcount: 239
+ common_timestamp-ts0: 0
+ max: 27
+ next_comm: cyclictest
+ prev_pid: 0 prev_prio: 120 prev_comm: swapper/1
+
+ { next_pid: 2256 } hitcount: 2355
+ common_timestamp-ts0: 0
+ max: 49 next_comm: cyclictest
+ prev_pid: 0 prev_prio: 120 prev_comm: swapper/0
+
+ Totals:
+ Hits: 12970
+ Entries: 2
+ Dropped: 0
diff --git a/Documentation/trace/hwlat_detector.rst b/Documentation/trace/hwlat_detector.rst
new file mode 100644
index 000000000000..5739349649c8
--- /dev/null
+++ b/Documentation/trace/hwlat_detector.rst
@@ -0,0 +1,83 @@
+=========================
+Hardware Latency Detector
+=========================
+
+Introduction
+-------------
+
+The tracer hwlat_detector is a special purpose tracer that is used to
+detect large system latencies induced by the behavior of certain underlying
+hardware or firmware, independent of Linux itself. The code was developed
+originally to detect SMIs (System Management Interrupts) on x86 systems,
+however there is nothing x86 specific about this patchset. It was
+originally written for use by the "RT" patch since the Real Time
+kernel is highly latency sensitive.
+
+SMIs are not serviced by the Linux kernel, which means that it does not
+even know that they are occuring. SMIs are instead set up by BIOS code
+and are serviced by BIOS code, usually for "critical" events such as
+management of thermal sensors and fans. Sometimes though, SMIs are used for
+other tasks and those tasks can spend an inordinate amount of time in the
+handler (sometimes measured in milliseconds). Obviously this is a problem if
+you are trying to keep event service latencies down in the microsecond range.
+
+The hardware latency detector works by hogging one of the cpus for configurable
+amounts of time (with interrupts disabled), polling the CPU Time Stamp Counter
+for some period, then looking for gaps in the TSC data. Any gap indicates a
+time when the polling was interrupted and since the interrupts are disabled,
+the only thing that could do that would be an SMI or other hardware hiccup
+(or an NMI, but those can be tracked).
+
+Note that the hwlat detector should *NEVER* be used in a production environment.
+It is intended to be run manually to determine if the hardware platform has a
+problem with long system firmware service routines.
+
+Usage
+------
+
+Write the ASCII text "hwlat" into the current_tracer file of the tracing system
+(mounted at /sys/kernel/tracing or /sys/kernel/tracing). It is possible to
+redefine the threshold in microseconds (us) above which latency spikes will
+be taken into account.
+
+Example::
+
+ # echo hwlat > /sys/kernel/tracing/current_tracer
+ # echo 100 > /sys/kernel/tracing/tracing_thresh
+
+The /sys/kernel/tracing/hwlat_detector interface contains the following files:
+
+ - width - time period to sample with CPUs held (usecs)
+ must be less than the total window size (enforced)
+ - window - total period of sampling, width being inside (usecs)
+
+By default the width is set to 500,000 and window to 1,000,000, meaning that
+for every 1,000,000 usecs (1s) the hwlat detector will spin for 500,000 usecs
+(0.5s). If tracing_thresh contains zero when hwlat tracer is enabled, it will
+change to a default of 10 usecs. If any latencies that exceed the threshold is
+observed then the data will be written to the tracing ring buffer.
+
+The minimum sleep time between periods is 1 millisecond. Even if width
+is less than 1 millisecond apart from window, to allow the system to not
+be totally starved.
+
+If tracing_thresh was zero when hwlat detector was started, it will be set
+back to zero if another tracer is loaded. Note, the last value in
+tracing_thresh that hwlat detector had will be saved and this value will
+be restored in tracing_thresh if it is still zero when hwlat detector is
+started again.
+
+The following tracing directory files are used by the hwlat_detector:
+
+in /sys/kernel/tracing:
+
+ - tracing_threshold - minimum latency value to be considered (usecs)
+ - tracing_max_latency - maximum hardware latency actually observed (usecs)
+ - tracing_cpumask - the CPUs to move the hwlat thread across
+ - hwlat_detector/width - specified amount of time to spin within window (usecs)
+ - hwlat_detector/window - amount of time between (width) runs (usecs)
+
+The hwlat detector's kernel thread will migrate across each CPU specified in
+tracing_cpumask between each window. To limit the migration, either modify
+tracing_cpumask, or modify the hwlat kernel thread (named [hwlatd]) CPU
+affinity directly, and the migration will stop.
diff --git a/Documentation/trace/hwlat_detector.txt b/Documentation/trace/hwlat_detector.txt
deleted file mode 100644
index 3207717a0d1a..000000000000
--- a/Documentation/trace/hwlat_detector.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-Introduction:
--------------
-
-The tracer hwlat_detector is a special purpose tracer that is used to
-detect large system latencies induced by the behavior of certain underlying
-hardware or firmware, independent of Linux itself. The code was developed
-originally to detect SMIs (System Management Interrupts) on x86 systems,
-however there is nothing x86 specific about this patchset. It was
-originally written for use by the "RT" patch since the Real Time
-kernel is highly latency sensitive.
-
-SMIs are not serviced by the Linux kernel, which means that it does not
-even know that they are occuring. SMIs are instead set up by BIOS code
-and are serviced by BIOS code, usually for "critical" events such as
-management of thermal sensors and fans. Sometimes though, SMIs are used for
-other tasks and those tasks can spend an inordinate amount of time in the
-handler (sometimes measured in milliseconds). Obviously this is a problem if
-you are trying to keep event service latencies down in the microsecond range.
-
-The hardware latency detector works by hogging one of the cpus for configurable
-amounts of time (with interrupts disabled), polling the CPU Time Stamp Counter
-for some period, then looking for gaps in the TSC data. Any gap indicates a
-time when the polling was interrupted and since the interrupts are disabled,
-the only thing that could do that would be an SMI or other hardware hiccup
-(or an NMI, but those can be tracked).
-
-Note that the hwlat detector should *NEVER* be used in a production environment.
-It is intended to be run manually to determine if the hardware platform has a
-problem with long system firmware service routines.
-
-Usage:
-------
-
-Write the ASCII text "hwlat" into the current_tracer file of the tracing system
-(mounted at /sys/kernel/tracing or /sys/kernel/tracing). It is possible to
-redefine the threshold in microseconds (us) above which latency spikes will
-be taken into account.
-
-Example:
-
- # echo hwlat > /sys/kernel/tracing/current_tracer
- # echo 100 > /sys/kernel/tracing/tracing_thresh
-
-The /sys/kernel/tracing/hwlat_detector interface contains the following files:
-
-width - time period to sample with CPUs held (usecs)
- must be less than the total window size (enforced)
-window - total period of sampling, width being inside (usecs)
-
-By default the width is set to 500,000 and window to 1,000,000, meaning that
-for every 1,000,000 usecs (1s) the hwlat detector will spin for 500,000 usecs
-(0.5s). If tracing_thresh contains zero when hwlat tracer is enabled, it will
-change to a default of 10 usecs. If any latencies that exceed the threshold is
-observed then the data will be written to the tracing ring buffer.
-
-The minimum sleep time between periods is 1 millisecond. Even if width
-is less than 1 millisecond apart from window, to allow the system to not
-be totally starved.
-
-If tracing_thresh was zero when hwlat detector was started, it will be set
-back to zero if another tracer is loaded. Note, the last value in
-tracing_thresh that hwlat detector had will be saved and this value will
-be restored in tracing_thresh if it is still zero when hwlat detector is
-started again.
-
-The following tracing directory files are used by the hwlat_detector:
-
-in /sys/kernel/tracing:
-
- tracing_threshold - minimum latency value to be considered (usecs)
- tracing_max_latency - maximum hardware latency actually observed (usecs)
- tracing_cpumask - the CPUs to move the hwlat thread across
- hwlat_detector/width - specified amount of time to spin within window (usecs)
- hwlat_detector/window - amount of time between (width) runs (usecs)
-
-The hwlat detector's kernel thread will migrate across each CPU specified in
-tracing_cpumask between each window. To limit the migration, either modify
-tracing_cpumask, or modify the hwlat kernel thread (named [hwlatd]) CPU
-affinity directly, and the migration will stop.
diff --git a/Documentation/trace/index.rst b/Documentation/trace/index.rst
new file mode 100644
index 000000000000..b58c10b04e27
--- /dev/null
+++ b/Documentation/trace/index.rst
@@ -0,0 +1,23 @@
+==========================
+Linux Tracing Technologies
+==========================
+
+.. toctree::
+ :maxdepth: 2
+
+ ftrace-design
+ tracepoint-analysis
+ ftrace
+ ftrace-uses
+ kprobetrace
+ uprobetracer
+ tracepoints
+ events
+ events-kmem
+ events-power
+ events-nmi
+ events-msr
+ mmiotrace
+ hwlat_detector
+ intel_th
+ stm
diff --git a/Documentation/trace/intel_th.rst b/Documentation/trace/intel_th.rst
new file mode 100644
index 000000000000..990f13265178
--- /dev/null
+++ b/Documentation/trace/intel_th.rst
@@ -0,0 +1,122 @@
+=======================
+Intel(R) Trace Hub (TH)
+=======================
+
+Overview
+--------
+
+Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
+switch and output trace data from multiple hardware and software
+sources over several types of trace output ports encoded in System
+Trace Protocol (MIPI STPv2) and is intended to perform full system
+debugging. For more information on the hardware, see Intel(R) Trace
+Hub developer's manual [1].
+
+It consists of trace sources, trace destinations (outputs) and a
+switch (Global Trace Hub, GTH). These devices are placed on a bus of
+their own ("intel_th"), where they can be discovered and configured
+via sysfs attributes.
+
+Currently, the following Intel TH subdevices (blocks) are supported:
+ - Software Trace Hub (STH), trace source, which is a System Trace
+ Module (STM) device,
+ - Memory Storage Unit (MSU), trace output, which allows storing
+ trace hub output in system memory,
+ - Parallel Trace Interface output (PTI), trace output to an external
+ debug host via a PTI port,
+ - Global Trace Hub (GTH), which is a switch and a central component
+ of Intel(R) Trace Hub architecture.
+
+Common attributes for output devices are described in
+Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
+notable of them is "active", which enables or disables trace output
+into that particular output device.
+
+GTH allows directing different STP masters into different output ports
+via its "masters" attribute group. More detailed GTH interface
+description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
+
+STH registers an stm class device, through which it provides interface
+to userspace and kernelspace software trace sources. See
+Documentation/trace/stm.txt for more information on that.
+
+MSU can be configured to collect trace data into a system memory
+buffer, which can later on be read from its device nodes via read() or
+mmap() interface.
+
+On the whole, Intel(R) Trace Hub does not require any special
+userspace software to function; everything can be configured, started
+and collected via sysfs attributes, and device nodes.
+
+[1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
+
+Bus and Subdevices
+------------------
+
+For each Intel TH device in the system a bus of its own is
+created and assigned an id number that reflects the order in which TH
+devices were emumerated. All TH subdevices (devices on intel_th bus)
+begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
+followed by device's name and an optional index.
+
+Output devices also get a device node in /dev/intel_thN, where N is
+the Intel TH device id. For example, MSU's memory buffers, when
+allocated, are accessible via /dev/intel_th0/msc{0,1}.
+
+Quick example
+-------------
+
+# figure out which GTH port is the first memory controller::
+
+ $ cat /sys/bus/intel_th/devices/0-msc0/port
+ 0
+
+# looks like it's port 0, configure master 33 to send data to port 0::
+
+ $ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
+
+# allocate a 2-windowed multiblock buffer on the first memory
+# controller, each with 64 pages::
+
+ $ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
+ $ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages
+
+# enable wrapping for this controller, too::
+
+ $ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap
+
+# and enable tracing into this port::
+
+ $ echo 1 > /sys/bus/intel_th/devices/0-msc0/active
+
+# .. send data to master 33, see stm.txt for more details ..
+# .. wait for traces to pile up ..
+# .. and stop the trace::
+
+ $ echo 0 > /sys/bus/intel_th/devices/0-msc0/active
+
+# and now you can collect the trace from the device node::
+
+ $ cat /dev/intel_th0/msc0 > my_stp_trace
+
+Host Debugger Mode
+------------------
+
+It is possible to configure the Trace Hub and control its trace
+capture from a remote debug host, which should be connected via one of
+the hardware debugging interfaces, which will then be used to both
+control Intel Trace Hub and transfer its trace data to the debug host.
+
+The driver needs to be told that such an arrangement is taking place
+so that it does not touch any capture/port configuration and avoids
+conflicting with the debug host's configuration accesses. The only
+activity that the driver will perform in this mode is collecting
+software traces to the Software Trace Hub (an stm class device). The
+user is still responsible for setting up adequate master/channel
+mappings that the decoder on the receiving end would recognize.
+
+In order to enable the host mode, set the 'host_mode' parameter of the
+'intel_th' kernel module to 'y'. None of the virtual output devices
+will show up on the intel_th bus. Also, trace configuration and
+capture controlling attribute groups of the 'gth' device will not be
+exposed. The 'sth' device will operate as usual.
diff --git a/Documentation/trace/intel_th.txt b/Documentation/trace/intel_th.txt
deleted file mode 100644
index 7a57165c2492..000000000000
--- a/Documentation/trace/intel_th.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-Intel(R) Trace Hub (TH)
-=======================
-
-Overview
---------
-
-Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
-switch and output trace data from multiple hardware and software
-sources over several types of trace output ports encoded in System
-Trace Protocol (MIPI STPv2) and is intended to perform full system
-debugging. For more information on the hardware, see Intel(R) Trace
-Hub developer's manual [1].
-
-It consists of trace sources, trace destinations (outputs) and a
-switch (Global Trace Hub, GTH). These devices are placed on a bus of
-their own ("intel_th"), where they can be discovered and configured
-via sysfs attributes.
-
-Currently, the following Intel TH subdevices (blocks) are supported:
- - Software Trace Hub (STH), trace source, which is a System Trace
- Module (STM) device,
- - Memory Storage Unit (MSU), trace output, which allows storing
- trace hub output in system memory,
- - Parallel Trace Interface output (PTI), trace output to an external
- debug host via a PTI port,
- - Global Trace Hub (GTH), which is a switch and a central component
- of Intel(R) Trace Hub architecture.
-
-Common attributes for output devices are described in
-Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
-notable of them is "active", which enables or disables trace output
-into that particular output device.
-
-GTH allows directing different STP masters into different output ports
-via its "masters" attribute group. More detailed GTH interface
-description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
-
-STH registers an stm class device, through which it provides interface
-to userspace and kernelspace software trace sources. See
-Documentation/trace/stm.txt for more information on that.
-
-MSU can be configured to collect trace data into a system memory
-buffer, which can later on be read from its device nodes via read() or
-mmap() interface.
-
-On the whole, Intel(R) Trace Hub does not require any special
-userspace software to function; everything can be configured, started
-and collected via sysfs attributes, and device nodes.
-
-[1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
-
-Bus and Subdevices
-------------------
-
-For each Intel TH device in the system a bus of its own is
-created and assigned an id number that reflects the order in which TH
-devices were emumerated. All TH subdevices (devices on intel_th bus)
-begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
-followed by device's name and an optional index.
-
-Output devices also get a device node in /dev/intel_thN, where N is
-the Intel TH device id. For example, MSU's memory buffers, when
-allocated, are accessible via /dev/intel_th0/msc{0,1}.
-
-Quick example
--------------
-
-# figure out which GTH port is the first memory controller:
-
-$ cat /sys/bus/intel_th/devices/0-msc0/port
-0
-
-# looks like it's port 0, configure master 33 to send data to port 0:
-
-$ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
-
-# allocate a 2-windowed multiblock buffer on the first memory
-# controller, each with 64 pages:
-
-$ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
-$ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages
-
-# enable wrapping for this controller, too:
-
-$ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap
-
-# and enable tracing into this port:
-
-$ echo 1 > /sys/bus/intel_th/devices/0-msc0/active
-
-# .. send data to master 33, see stm.txt for more details ..
-# .. wait for traces to pile up ..
-# .. and stop the trace:
-
-$ echo 0 > /sys/bus/intel_th/devices/0-msc0/active
-
-# and now you can collect the trace from the device node:
-
-$ cat /dev/intel_th0/msc0 > my_stp_trace
-
-Host Debugger Mode
-==================
-
-It is possible to configure the Trace Hub and control its trace
-capture from a remote debug host, which should be connected via one of
-the hardware debugging interfaces, which will then be used to both
-control Intel Trace Hub and transfer its trace data to the debug host.
-
-The driver needs to be told that such an arrangement is taking place
-so that it does not touch any capture/port configuration and avoids
-conflicting with the debug host's configuration accesses. The only
-activity that the driver will perform in this mode is collecting
-software traces to the Software Trace Hub (an stm class device). The
-user is still responsible for setting up adequate master/channel
-mappings that the decoder on the receiving end would recognize.
-
-In order to enable the host mode, set the 'host_mode' parameter of the
-'intel_th' kernel module to 'y'. None of the virtual output devices
-will show up on the intel_th bus. Also, trace configuration and
-capture controlling attribute groups of the 'gth' device will not be
-exposed. The 'sth' device will operate as usual.
diff --git a/Documentation/trace/kprobetrace.rst b/Documentation/trace/kprobetrace.rst
new file mode 100644
index 000000000000..3e0f971b12de
--- /dev/null
+++ b/Documentation/trace/kprobetrace.rst
@@ -0,0 +1,190 @@
+==========================
+Kprobe-based Event Tracing
+==========================
+
+:Author: Masami Hiramatsu
+
+Overview
+--------
+These events are similar to tracepoint based events. Instead of Tracepoint,
+this is based on kprobes (kprobe and kretprobe). So it can probe wherever
+kprobes can probe (this means, all functions except those with
+__kprobes/nokprobe_inline annotation and those marked NOKPROBE_SYMBOL).
+Unlike the Tracepoint based event, this can be added and removed
+dynamically, on the fly.
+
+To enable this feature, build your kernel with CONFIG_KPROBE_EVENTS=y.
+
+Similar to the events tracer, this doesn't need to be activated via
+current_tracer. Instead of that, add probe points via
+/sys/kernel/debug/tracing/kprobe_events, and enable it via
+/sys/kernel/debug/tracing/events/kprobes/<EVENT>/enabled.
+
+
+Synopsis of kprobe_events
+-------------------------
+::
+
+ p[:[GRP/]EVENT] [MOD:]SYM[+offs]|MEMADDR [FETCHARGS] : Set a probe
+ r[MAXACTIVE][:[GRP/]EVENT] [MOD:]SYM[+0] [FETCHARGS] : Set a return probe
+ -:[GRP/]EVENT : Clear a probe
+
+ GRP : Group name. If omitted, use "kprobes" for it.
+ EVENT : Event name. If omitted, the event name is generated
+ based on SYM+offs or MEMADDR.
+ MOD : Module name which has given SYM.
+ SYM[+offs] : Symbol+offset where the probe is inserted.
+ MEMADDR : Address where the probe is inserted.
+ MAXACTIVE : Maximum number of instances of the specified function that
+ can be probed simultaneously, or 0 for the default value
+ as defined in Documentation/kprobes.txt section 1.3.1.
+
+ FETCHARGS : Arguments. Each probe can have up to 128 args.
+ %REG : Fetch register REG
+ @ADDR : Fetch memory at ADDR (ADDR should be in kernel)
+ @SYM[+|-offs] : Fetch memory at SYM +|- offs (SYM should be a data symbol)
+ $stackN : Fetch Nth entry of stack (N >= 0)
+ $stack : Fetch stack address.
+ $retval : Fetch return value.(*)
+ $comm : Fetch current task comm.
+ +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**)
+ NAME=FETCHARG : Set NAME as the argument name of FETCHARG.
+ FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types
+ (u8/u16/u32/u64/s8/s16/s32/s64), hexadecimal types
+ (x8/x16/x32/x64), "string" and bitfield are supported.
+
+ (*) only for return probe.
+ (**) this is useful for fetching a field of data structures.
+
+Types
+-----
+Several types are supported for fetch-args. Kprobe tracer will access memory
+by given type. Prefix 's' and 'u' means those types are signed and unsigned
+respectively. 'x' prefix implies it is unsigned. Traced arguments are shown
+in decimal ('s' and 'u') or hexadecimal ('x'). Without type casting, 'x32'
+or 'x64' is used depends on the architecture (e.g. x86-32 uses x32, and
+x86-64 uses x64).
+String type is a special type, which fetches a "null-terminated" string from
+kernel space. This means it will fail and store NULL if the string container
+has been paged out.
+Bitfield is another special type, which takes 3 parameters, bit-width, bit-
+offset, and container-size (usually 32). The syntax is::
+
+ b<bit-width>@<bit-offset>/<container-size>
+
+For $comm, the default type is "string"; any other type is invalid.
+
+
+Per-Probe Event Filtering
+-------------------------
+Per-probe event filtering feature allows you to set different filter on each
+probe and gives you what arguments will be shown in trace buffer. If an event
+name is specified right after 'p:' or 'r:' in kprobe_events, it adds an event
+under tracing/events/kprobes/<EVENT>, at the directory you can see 'id',
+'enabled', 'format' and 'filter'.
+
+enabled:
+ You can enable/disable the probe by writing 1 or 0 on it.
+
+format:
+ This shows the format of this probe event.
+
+filter:
+ You can write filtering rules of this event.
+
+id:
+ This shows the id of this probe event.
+
+
+Event Profiling
+---------------
+You can check the total number of probe hits and probe miss-hits via
+/sys/kernel/debug/tracing/kprobe_profile.
+The first column is event name, the second is the number of probe hits,
+the third is the number of probe miss-hits.
+
+
+Usage examples
+--------------
+To add a probe as a new event, write a new definition to kprobe_events
+as below::
+
+ echo 'p:myprobe do_sys_open dfd=%ax filename=%dx flags=%cx mode=+4($stack)' > /sys/kernel/debug/tracing/kprobe_events
+
+This sets a kprobe on the top of do_sys_open() function with recording
+1st to 4th arguments as "myprobe" event. Note, which register/stack entry is
+assigned to each function argument depends on arch-specific ABI. If you unsure
+the ABI, please try to use probe subcommand of perf-tools (you can find it
+under tools/perf/).
+As this example shows, users can choose more familiar names for each arguments.
+::
+
+ echo 'r:myretprobe do_sys_open $retval' >> /sys/kernel/debug/tracing/kprobe_events
+
+This sets a kretprobe on the return point of do_sys_open() function with
+recording return value as "myretprobe" event.
+You can see the format of these events via
+/sys/kernel/debug/tracing/events/kprobes/<EVENT>/format.
+::
+
+ cat /sys/kernel/debug/tracing/events/kprobes/myprobe/format
+ name: myprobe
+ ID: 780
+ format:
+ field:unsigned short common_type; offset:0; size:2; signed:0;
+ field:unsigned char common_flags; offset:2; size:1; signed:0;
+ field:unsigned char common_preempt_count; offset:3; size:1;signed:0;
+ field:int common_pid; offset:4; size:4; signed:1;
+
+ field:unsigned long __probe_ip; offset:12; size:4; signed:0;
+ field:int __probe_nargs; offset:16; size:4; signed:1;
+ field:unsigned long dfd; offset:20; size:4; signed:0;
+ field:unsigned long filename; offset:24; size:4; signed:0;
+ field:unsigned long flags; offset:28; size:4; signed:0;
+ field:unsigned long mode; offset:32; size:4; signed:0;
+
+
+ print fmt: "(%lx) dfd=%lx filename=%lx flags=%lx mode=%lx", REC->__probe_ip,
+ REC->dfd, REC->filename, REC->flags, REC->mode
+
+You can see that the event has 4 arguments as in the expressions you specified.
+::
+
+ echo > /sys/kernel/debug/tracing/kprobe_events
+
+This clears all probe points.
+
+Or,
+::
+
+ echo -:myprobe >> kprobe_events
+
+This clears probe points selectively.
+
+Right after definition, each event is disabled by default. For tracing these
+events, you need to enable it.
+::
+
+ echo 1 > /sys/kernel/debug/tracing/events/kprobes/myprobe/enable
+ echo 1 > /sys/kernel/debug/tracing/events/kprobes/myretprobe/enable
+
+And you can see the traced information via /sys/kernel/debug/tracing/trace.
+::
+
+ cat /sys/kernel/debug/tracing/trace
+ # tracer: nop
+ #
+ # TASK-PID CPU# TIMESTAMP FUNCTION
+ # | | | | |
+ <...>-1447 [001] 1038282.286875: myprobe: (do_sys_open+0x0/0xd6) dfd=3 filename=7fffd1ec4440 flags=8000 mode=0
+ <...>-1447 [001] 1038282.286878: myretprobe: (sys_openat+0xc/0xe <- do_sys_open) $retval=fffffffffffffffe
+ <...>-1447 [001] 1038282.286885: myprobe: (do_sys_open+0x0/0xd6) dfd=ffffff9c filename=40413c flags=8000 mode=1b6
+ <...>-1447 [001] 1038282.286915: myretprobe: (sys_open+0x1b/0x1d <- do_sys_open) $retval=3
+ <...>-1447 [001] 1038282.286969: myprobe: (do_sys_open+0x0/0xd6) dfd=ffffff9c filename=4041c6 flags=98800 mode=10
+ <...>-1447 [001] 1038282.286976: myretprobe: (sys_open+0x1b/0x1d <- do_sys_open) $retval=3
+
+
+Each line shows when the kernel hits an event, and <- SYMBOL means kernel
+returns from SYMBOL(e.g. "sys_open+0x1b/0x1d <- do_sys_open" means kernel
+returns from do_sys_open to sys_open+0x1b).
+
diff --git a/Documentation/trace/kprobetrace.txt b/Documentation/trace/kprobetrace.txt
deleted file mode 100644
index 1a3a3d6bc2a8..000000000000
--- a/Documentation/trace/kprobetrace.txt
+++ /dev/null
@@ -1,182 +0,0 @@
- Kprobe-based Event Tracing
- ==========================
-
- Documentation is written by Masami Hiramatsu
-
-
-Overview
---------
-These events are similar to tracepoint based events. Instead of Tracepoint,
-this is based on kprobes (kprobe and kretprobe). So it can probe wherever
-kprobes can probe (this means, all functions except those with
-__kprobes/nokprobe_inline annotation and those marked NOKPROBE_SYMBOL).
-Unlike the Tracepoint based event, this can be added and removed
-dynamically, on the fly.
-
-To enable this feature, build your kernel with CONFIG_KPROBE_EVENTS=y.
-
-Similar to the events tracer, this doesn't need to be activated via
-current_tracer. Instead of that, add probe points via
-/sys/kernel/debug/tracing/kprobe_events, and enable it via
-/sys/kernel/debug/tracing/events/kprobes/<EVENT>/enabled.
-
-
-Synopsis of kprobe_events
--------------------------
- p[:[GRP/]EVENT] [MOD:]SYM[+offs]|MEMADDR [FETCHARGS] : Set a probe
- r[MAXACTIVE][:[GRP/]EVENT] [MOD:]SYM[+0] [FETCHARGS] : Set a return probe
- -:[GRP/]EVENT : Clear a probe
-
- GRP : Group name. If omitted, use "kprobes" for it.
- EVENT : Event name. If omitted, the event name is generated
- based on SYM+offs or MEMADDR.
- MOD : Module name which has given SYM.
- SYM[+offs] : Symbol+offset where the probe is inserted.
- MEMADDR : Address where the probe is inserted.
- MAXACTIVE : Maximum number of instances of the specified function that
- can be probed simultaneously, or 0 for the default value
- as defined in Documentation/kprobes.txt section 1.3.1.
-
- FETCHARGS : Arguments. Each probe can have up to 128 args.
- %REG : Fetch register REG
- @ADDR : Fetch memory at ADDR (ADDR should be in kernel)
- @SYM[+|-offs] : Fetch memory at SYM +|- offs (SYM should be a data symbol)
- $stackN : Fetch Nth entry of stack (N >= 0)
- $stack : Fetch stack address.
- $retval : Fetch return value.(*)
- $comm : Fetch current task comm.
- +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**)
- NAME=FETCHARG : Set NAME as the argument name of FETCHARG.
- FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types
- (u8/u16/u32/u64/s8/s16/s32/s64), hexadecimal types
- (x8/x16/x32/x64), "string" and bitfield are supported.
-
- (*) only for return probe.
- (**) this is useful for fetching a field of data structures.
-
-Types
------
-Several types are supported for fetch-args. Kprobe tracer will access memory
-by given type. Prefix 's' and 'u' means those types are signed and unsigned
-respectively. 'x' prefix implies it is unsigned. Traced arguments are shown
-in decimal ('s' and 'u') or hexadecimal ('x'). Without type casting, 'x32'
-or 'x64' is used depends on the architecture (e.g. x86-32 uses x32, and
-x86-64 uses x64).
-String type is a special type, which fetches a "null-terminated" string from
-kernel space. This means it will fail and store NULL if the string container
-has been paged out.
-Bitfield is another special type, which takes 3 parameters, bit-width, bit-
-offset, and container-size (usually 32). The syntax is;
-
- b<bit-width>@<bit-offset>/<container-size>
-
-For $comm, the default type is "string"; any other type is invalid.
-
-
-Per-Probe Event Filtering
--------------------------
- Per-probe event filtering feature allows you to set different filter on each
-probe and gives you what arguments will be shown in trace buffer. If an event
-name is specified right after 'p:' or 'r:' in kprobe_events, it adds an event
-under tracing/events/kprobes/<EVENT>, at the directory you can see 'id',
-'enabled', 'format' and 'filter'.
-
-enabled:
- You can enable/disable the probe by writing 1 or 0 on it.
-
-format:
- This shows the format of this probe event.
-
-filter:
- You can write filtering rules of this event.
-
-id:
- This shows the id of this probe event.
-
-
-Event Profiling
----------------
- You can check the total number of probe hits and probe miss-hits via
-/sys/kernel/debug/tracing/kprobe_profile.
- The first column is event name, the second is the number of probe hits,
-the third is the number of probe miss-hits.
-
-
-Usage examples
---------------
-To add a probe as a new event, write a new definition to kprobe_events
-as below.
-
- echo 'p:myprobe do_sys_open dfd=%ax filename=%dx flags=%cx mode=+4($stack)' > /sys/kernel/debug/tracing/kprobe_events
-
- This sets a kprobe on the top of do_sys_open() function with recording
-1st to 4th arguments as "myprobe" event. Note, which register/stack entry is
-assigned to each function argument depends on arch-specific ABI. If you unsure
-the ABI, please try to use probe subcommand of perf-tools (you can find it
-under tools/perf/).
-As this example shows, users can choose more familiar names for each arguments.
-
- echo 'r:myretprobe do_sys_open $retval' >> /sys/kernel/debug/tracing/kprobe_events
-
- This sets a kretprobe on the return point of do_sys_open() function with
-recording return value as "myretprobe" event.
- You can see the format of these events via
-/sys/kernel/debug/tracing/events/kprobes/<EVENT>/format.
-
- cat /sys/kernel/debug/tracing/events/kprobes/myprobe/format
-name: myprobe
-ID: 780
-format:
- field:unsigned short common_type; offset:0; size:2; signed:0;
- field:unsigned char common_flags; offset:2; size:1; signed:0;
- field:unsigned char common_preempt_count; offset:3; size:1;signed:0;
- field:int common_pid; offset:4; size:4; signed:1;
-
- field:unsigned long __probe_ip; offset:12; size:4; signed:0;
- field:int __probe_nargs; offset:16; size:4; signed:1;
- field:unsigned long dfd; offset:20; size:4; signed:0;
- field:unsigned long filename; offset:24; size:4; signed:0;
- field:unsigned long flags; offset:28; size:4; signed:0;
- field:unsigned long mode; offset:32; size:4; signed:0;
-
-
-print fmt: "(%lx) dfd=%lx filename=%lx flags=%lx mode=%lx", REC->__probe_ip,
-REC->dfd, REC->filename, REC->flags, REC->mode
-
- You can see that the event has 4 arguments as in the expressions you specified.
-
- echo > /sys/kernel/debug/tracing/kprobe_events
-
- This clears all probe points.
-
- Or,
-
- echo -:myprobe >> kprobe_events
-
- This clears probe points selectively.
-
- Right after definition, each event is disabled by default. For tracing these
-events, you need to enable it.
-
- echo 1 > /sys/kernel/debug/tracing/events/kprobes/myprobe/enable
- echo 1 > /sys/kernel/debug/tracing/events/kprobes/myretprobe/enable
-
- And you can see the traced information via /sys/kernel/debug/tracing/trace.
-
- cat /sys/kernel/debug/tracing/trace
-# tracer: nop
-#
-# TASK-PID CPU# TIMESTAMP FUNCTION
-# | | | | |
- <...>-1447 [001] 1038282.286875: myprobe: (do_sys_open+0x0/0xd6) dfd=3 filename=7fffd1ec4440 flags=8000 mode=0
- <...>-1447 [001] 1038282.286878: myretprobe: (sys_openat+0xc/0xe <- do_sys_open) $retval=fffffffffffffffe
- <...>-1447 [001] 1038282.286885: myprobe: (do_sys_open+0x0/0xd6) dfd=ffffff9c filename=40413c flags=8000 mode=1b6
- <...>-1447 [001] 1038282.286915: myretprobe: (sys_open+0x1b/0x1d <- do_sys_open) $retval=3
- <...>-1447 [001] 1038282.286969: myprobe: (do_sys_open+0x0/0xd6) dfd=ffffff9c filename=4041c6 flags=98800 mode=10
- <...>-1447 [001] 1038282.286976: myretprobe: (sys_open+0x1b/0x1d <- do_sys_open) $retval=3
-
-
- Each line shows when the kernel hits an event, and <- SYMBOL means kernel
-returns from SYMBOL(e.g. "sys_open+0x1b/0x1d <- do_sys_open" means kernel
-returns from do_sys_open to sys_open+0x1b).
-
diff --git a/Documentation/trace/mmiotrace.rst b/Documentation/trace/mmiotrace.rst
new file mode 100644
index 000000000000..5116e8ca27b4
--- /dev/null
+++ b/Documentation/trace/mmiotrace.rst
@@ -0,0 +1,184 @@
+===================================
+In-kernel memory-mapped I/O tracing
+===================================
+
+
+Home page and links to optional user space tools:
+
+ http://nouveau.freedesktop.org/wiki/MmioTrace
+
+MMIO tracing was originally developed by Intel around 2003 for their Fault
+Injection Test Harness. In Dec 2006 - Jan 2007, using the code from Intel,
+Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
+project in mind. Since then many people have contributed.
+
+Mmiotrace was built for reverse engineering any memory-mapped IO device with
+the Nouveau project as the first real user. Only x86 and x86_64 architectures
+are supported.
+
+Out-of-tree mmiotrace was originally modified for mainline inclusion and
+ftrace framework by Pekka Paalanen <pq@iki.fi>.
+
+
+Preparation
+-----------
+
+Mmiotrace feature is compiled in by the CONFIG_MMIOTRACE option. Tracing is
+disabled by default, so it is safe to have this set to yes. SMP systems are
+supported, but tracing is unreliable and may miss events if more than one CPU
+is on-line, therefore mmiotrace takes all but one CPU off-line during run-time
+activation. You can re-enable CPUs by hand, but you have been warned, there
+is no way to automatically detect if you are losing events due to CPUs racing.
+
+
+Usage Quick Reference
+---------------------
+::
+
+ $ mount -t debugfs debugfs /sys/kernel/debug
+ $ echo mmiotrace > /sys/kernel/debug/tracing/current_tracer
+ $ cat /sys/kernel/debug/tracing/trace_pipe > mydump.txt &
+ Start X or whatever.
+ $ echo "X is up" > /sys/kernel/debug/tracing/trace_marker
+ $ echo nop > /sys/kernel/debug/tracing/current_tracer
+ Check for lost events.
+
+
+Usage
+-----
+
+Make sure debugfs is mounted to /sys/kernel/debug.
+If not (requires root privileges)::
+
+ $ mount -t debugfs debugfs /sys/kernel/debug
+
+Check that the driver you are about to trace is not loaded.
+
+Activate mmiotrace (requires root privileges)::
+
+ $ echo mmiotrace > /sys/kernel/debug/tracing/current_tracer
+
+Start storing the trace::
+
+ $ cat /sys/kernel/debug/tracing/trace_pipe > mydump.txt &
+
+The 'cat' process should stay running (sleeping) in the background.
+
+Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
+accesses to areas that are ioremapped while mmiotrace is active.
+
+During tracing you can place comments (markers) into the trace by
+$ echo "X is up" > /sys/kernel/debug/tracing/trace_marker
+This makes it easier to see which part of the (huge) trace corresponds to
+which action. It is recommended to place descriptive markers about what you
+do.
+
+Shut down mmiotrace (requires root privileges)::
+
+ $ echo nop > /sys/kernel/debug/tracing/current_tracer
+
+The 'cat' process exits. If it does not, kill it by issuing 'fg' command and
+pressing ctrl+c.
+
+Check that mmiotrace did not lose events due to a buffer filling up. Either::
+
+ $ grep -i lost mydump.txt
+
+which tells you exactly how many events were lost, or use::
+
+ $ dmesg
+
+to view your kernel log and look for "mmiotrace has lost events" warning. If
+events were lost, the trace is incomplete. You should enlarge the buffers and
+try again. Buffers are enlarged by first seeing how large the current buffers
+are::
+
+ $ cat /sys/kernel/debug/tracing/buffer_size_kb
+
+gives you a number. Approximately double this number and write it back, for
+instance::
+
+ $ echo 128000 > /sys/kernel/debug/tracing/buffer_size_kb
+
+Then start again from the top.
+
+If you are doing a trace for a driver project, e.g. Nouveau, you should also
+do the following before sending your results::
+
+ $ lspci -vvv > lspci.txt
+ $ dmesg > dmesg.txt
+ $ tar zcf pciid-nick-mmiotrace.tar.gz mydump.txt lspci.txt dmesg.txt
+
+and then send the .tar.gz file. The trace compresses considerably. Replace
+"pciid" and "nick" with the PCI ID or model name of your piece of hardware
+under investigation and your nickname.
+
+
+How Mmiotrace Works
+-------------------
+
+Access to hardware IO-memory is gained by mapping addresses from PCI bus by
+calling one of the ioremap_*() functions. Mmiotrace is hooked into the
+__ioremap() function and gets called whenever a mapping is created. Mapping is
+an event that is recorded into the trace log. Note that ISA range mappings
+are not caught, since the mapping always exists and is returned directly.
+
+MMIO accesses are recorded via page faults. Just before __ioremap() returns,
+the mapped pages are marked as not present. Any access to the pages causes a
+fault. The page fault handler calls mmiotrace to handle the fault. Mmiotrace
+marks the page present, sets TF flag to achieve single stepping and exits the
+fault handler. The instruction that faulted is executed and debug trap is
+entered. Here mmiotrace again marks the page as not present. The instruction
+is decoded to get the type of operation (read/write), data width and the value
+read or written. These are stored to the trace log.
+
+Setting the page present in the page fault handler has a race condition on SMP
+machines. During the single stepping other CPUs may run freely on that page
+and events can be missed without a notice. Re-enabling other CPUs during
+tracing is discouraged.
+
+
+Trace Log Format
+----------------
+
+The raw log is text and easily filtered with e.g. grep and awk. One record is
+one line in the log. A record starts with a keyword, followed by keyword-
+dependent arguments. Arguments are separated by a space, or continue until the
+end of line. The format for version 20070824 is as follows:
+
+Explanation Keyword Space-separated arguments
+---------------------------------------------------------------------------
+
+read event R width, timestamp, map id, physical, value, PC, PID
+write event W width, timestamp, map id, physical, value, PC, PID
+ioremap event MAP timestamp, map id, physical, virtual, length, PC, PID
+iounmap event UNMAP timestamp, map id, PC, PID
+marker MARK timestamp, text
+version VERSION the string "20070824"
+info for reader LSPCI one line from lspci -v
+PCI address map PCIDEV space-separated /proc/bus/pci/devices data
+unk. opcode UNKNOWN timestamp, map id, physical, data, PC, PID
+
+Timestamp is in seconds with decimals. Physical is a PCI bus address, virtual
+is a kernel virtual address. Width is the data width in bytes and value is the
+data value. Map id is an arbitrary id number identifying the mapping that was
+used in an operation. PC is the program counter and PID is process id. PC is
+zero if it is not recorded. PID is always zero as tracing MMIO accesses
+originating in user space memory is not yet supported.
+
+For instance, the following awk filter will pass all 32-bit writes that target
+physical addresses in the range [0xfb73ce40, 0xfb800000]
+::
+
+ $ awk '/W 4 / { adr=strtonum($5); if (adr >= 0xfb73ce40 &&
+ adr < 0xfb800000) print; }'
+
+
+Tools for Developers
+--------------------
+
+The user space tools include utilities for:
+ - replacing numeric addresses and values with hardware register names
+ - replaying MMIO logs, i.e., re-executing the recorded writes
+
+
diff --git a/Documentation/trace/mmiotrace.txt b/Documentation/trace/mmiotrace.txt
deleted file mode 100644
index 664e7386d89e..000000000000
--- a/Documentation/trace/mmiotrace.txt
+++ /dev/null
@@ -1,164 +0,0 @@
- In-kernel memory-mapped I/O tracing
-
-
-Home page and links to optional user space tools:
-
- http://nouveau.freedesktop.org/wiki/MmioTrace
-
-MMIO tracing was originally developed by Intel around 2003 for their Fault
-Injection Test Harness. In Dec 2006 - Jan 2007, using the code from Intel,
-Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
-project in mind. Since then many people have contributed.
-
-Mmiotrace was built for reverse engineering any memory-mapped IO device with
-the Nouveau project as the first real user. Only x86 and x86_64 architectures
-are supported.
-
-Out-of-tree mmiotrace was originally modified for mainline inclusion and
-ftrace framework by Pekka Paalanen <pq@iki.fi>.
-
-
-Preparation
------------
-
-Mmiotrace feature is compiled in by the CONFIG_MMIOTRACE option. Tracing is
-disabled by default, so it is safe to have this set to yes. SMP systems are
-supported, but tracing is unreliable and may miss events if more than one CPU
-is on-line, therefore mmiotrace takes all but one CPU off-line during run-time
-activation. You can re-enable CPUs by hand, but you have been warned, there
-is no way to automatically detect if you are losing events due to CPUs racing.
-
-
-Usage Quick Reference
----------------------
-
-$ mount -t debugfs debugfs /sys/kernel/debug
-$ echo mmiotrace > /sys/kernel/debug/tracing/current_tracer
-$ cat /sys/kernel/debug/tracing/trace_pipe > mydump.txt &
-Start X or whatever.
-$ echo "X is up" > /sys/kernel/debug/tracing/trace_marker
-$ echo nop > /sys/kernel/debug/tracing/current_tracer
-Check for lost events.
-
-
-Usage
------
-
-Make sure debugfs is mounted to /sys/kernel/debug.
-If not (requires root privileges):
-$ mount -t debugfs debugfs /sys/kernel/debug
-
-Check that the driver you are about to trace is not loaded.
-
-Activate mmiotrace (requires root privileges):
-$ echo mmiotrace > /sys/kernel/debug/tracing/current_tracer
-
-Start storing the trace:
-$ cat /sys/kernel/debug/tracing/trace_pipe > mydump.txt &
-The 'cat' process should stay running (sleeping) in the background.
-
-Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
-accesses to areas that are ioremapped while mmiotrace is active.
-
-During tracing you can place comments (markers) into the trace by
-$ echo "X is up" > /sys/kernel/debug/tracing/trace_marker
-This makes it easier to see which part of the (huge) trace corresponds to
-which action. It is recommended to place descriptive markers about what you
-do.
-
-Shut down mmiotrace (requires root privileges):
-$ echo nop > /sys/kernel/debug/tracing/current_tracer
-The 'cat' process exits. If it does not, kill it by issuing 'fg' command and
-pressing ctrl+c.
-
-Check that mmiotrace did not lose events due to a buffer filling up. Either
-$ grep -i lost mydump.txt
-which tells you exactly how many events were lost, or use
-$ dmesg
-to view your kernel log and look for "mmiotrace has lost events" warning. If
-events were lost, the trace is incomplete. You should enlarge the buffers and
-try again. Buffers are enlarged by first seeing how large the current buffers
-are:
-$ cat /sys/kernel/debug/tracing/buffer_size_kb
-gives you a number. Approximately double this number and write it back, for
-instance:
-$ echo 128000 > /sys/kernel/debug/tracing/buffer_size_kb
-Then start again from the top.
-
-If you are doing a trace for a driver project, e.g. Nouveau, you should also
-do the following before sending your results:
-$ lspci -vvv > lspci.txt
-$ dmesg > dmesg.txt
-$ tar zcf pciid-nick-mmiotrace.tar.gz mydump.txt lspci.txt dmesg.txt
-and then send the .tar.gz file. The trace compresses considerably. Replace
-"pciid" and "nick" with the PCI ID or model name of your piece of hardware
-under investigation and your nickname.
-
-
-How Mmiotrace Works
--------------------
-
-Access to hardware IO-memory is gained by mapping addresses from PCI bus by
-calling one of the ioremap_*() functions. Mmiotrace is hooked into the
-__ioremap() function and gets called whenever a mapping is created. Mapping is
-an event that is recorded into the trace log. Note that ISA range mappings
-are not caught, since the mapping always exists and is returned directly.
-
-MMIO accesses are recorded via page faults. Just before __ioremap() returns,
-the mapped pages are marked as not present. Any access to the pages causes a
-fault. The page fault handler calls mmiotrace to handle the fault. Mmiotrace
-marks the page present, sets TF flag to achieve single stepping and exits the
-fault handler. The instruction that faulted is executed and debug trap is
-entered. Here mmiotrace again marks the page as not present. The instruction
-is decoded to get the type of operation (read/write), data width and the value
-read or written. These are stored to the trace log.
-
-Setting the page present in the page fault handler has a race condition on SMP
-machines. During the single stepping other CPUs may run freely on that page
-and events can be missed without a notice. Re-enabling other CPUs during
-tracing is discouraged.
-
-
-Trace Log Format
-----------------
-
-The raw log is text and easily filtered with e.g. grep and awk. One record is
-one line in the log. A record starts with a keyword, followed by keyword-
-dependent arguments. Arguments are separated by a space, or continue until the
-end of line. The format for version 20070824 is as follows:
-
-Explanation Keyword Space-separated arguments
----------------------------------------------------------------------------
-
-read event R width, timestamp, map id, physical, value, PC, PID
-write event W width, timestamp, map id, physical, value, PC, PID
-ioremap event MAP timestamp, map id, physical, virtual, length, PC, PID
-iounmap event UNMAP timestamp, map id, PC, PID
-marker MARK timestamp, text
-version VERSION the string "20070824"
-info for reader LSPCI one line from lspci -v
-PCI address map PCIDEV space-separated /proc/bus/pci/devices data
-unk. opcode UNKNOWN timestamp, map id, physical, data, PC, PID
-
-Timestamp is in seconds with decimals. Physical is a PCI bus address, virtual
-is a kernel virtual address. Width is the data width in bytes and value is the
-data value. Map id is an arbitrary id number identifying the mapping that was
-used in an operation. PC is the program counter and PID is process id. PC is
-zero if it is not recorded. PID is always zero as tracing MMIO accesses
-originating in user space memory is not yet supported.
-
-For instance, the following awk filter will pass all 32-bit writes that target
-physical addresses in the range [0xfb73ce40, 0xfb800000[
-
-$ awk '/W 4 / { adr=strtonum($5); if (adr >= 0xfb73ce40 &&
-adr < 0xfb800000) print; }'
-
-
-Tools for Developers
---------------------
-
-The user space tools include utilities for:
-- replacing numeric addresses and values with hardware register names
-- replaying MMIO logs, i.e., re-executing the recorded writes
-
-
diff --git a/Documentation/trace/postprocess/trace-vmscan-postprocess.pl b/Documentation/trace/postprocess/trace-vmscan-postprocess.pl
index ba976805853a..66bfd8396877 100644
--- a/Documentation/trace/postprocess/trace-vmscan-postprocess.pl
+++ b/Documentation/trace/postprocess/trace-vmscan-postprocess.pl
@@ -111,7 +111,7 @@ my $regex_direct_begin_default = 'order=([0-9]*) may_writepage=([0-9]*) gfp_flag
my $regex_direct_end_default = 'nr_reclaimed=([0-9]*)';
my $regex_kswapd_wake_default = 'nid=([0-9]*) order=([0-9]*)';
my $regex_kswapd_sleep_default = 'nid=([0-9]*)';
-my $regex_wakeup_kswapd_default = 'nid=([0-9]*) zid=([0-9]*) order=([0-9]*)';
+my $regex_wakeup_kswapd_default = 'nid=([0-9]*) zid=([0-9]*) order=([0-9]*) gfp_flags=([A-Z_|]*)';
my $regex_lru_isolate_default = 'isolate_mode=([0-9]*) classzone_idx=([0-9]*) order=([0-9]*) nr_requested=([0-9]*) nr_scanned=([0-9]*) nr_skipped=([0-9]*) nr_taken=([0-9]*) lru=([a-z_]*)';
my $regex_lru_shrink_inactive_default = 'nid=([0-9]*) nr_scanned=([0-9]*) nr_reclaimed=([0-9]*) nr_dirty=([0-9]*) nr_writeback=([0-9]*) nr_congested=([0-9]*) nr_immediate=([0-9]*) nr_activate=([0-9]*) nr_ref_keep=([0-9]*) nr_unmap_fail=([0-9]*) priority=([0-9]*) flags=([A-Z_|]*)';
my $regex_lru_shrink_active_default = 'lru=([A-Z_]*) nr_scanned=([0-9]*) nr_rotated=([0-9]*) priority=([0-9]*)';
@@ -201,7 +201,7 @@ $regex_kswapd_sleep = generate_traceevent_regex(
$regex_wakeup_kswapd = generate_traceevent_regex(
"vmscan/mm_vmscan_wakeup_kswapd",
$regex_wakeup_kswapd_default,
- "nid", "zid", "order");
+ "nid", "zid", "order", "gfp_flags");
$regex_lru_isolate = generate_traceevent_regex(
"vmscan/mm_vmscan_lru_isolate",
$regex_lru_isolate_default,
diff --git a/Documentation/trace/stm.rst b/Documentation/trace/stm.rst
new file mode 100644
index 000000000000..2c22ddb7fd3e
--- /dev/null
+++ b/Documentation/trace/stm.rst
@@ -0,0 +1,123 @@
+===================
+System Trace Module
+===================
+
+System Trace Module (STM) is a device described in MIPI STP specs as
+STP trace stream generator. STP (System Trace Protocol) is a trace
+protocol multiplexing data from multiple trace sources, each one of
+which is assigned a unique pair of master and channel. While some of
+these masters and channels are statically allocated to certain
+hardware trace sources, others are available to software. Software
+trace sources are usually free to pick for themselves any
+master/channel combination from this pool.
+
+On the receiving end of this STP stream (the decoder side), trace
+sources can only be identified by master/channel combination, so in
+order for the decoder to be able to make sense of the trace that
+involves multiple trace sources, it needs to be able to map those
+master/channel pairs to the trace sources that it understands.
+
+For instance, it is helpful to know that syslog messages come on
+master 7 channel 15, while arbitrary user applications can use masters
+48 to 63 and channels 0 to 127.
+
+To solve this mapping problem, stm class provides a policy management
+mechanism via configfs, that allows defining rules that map string
+identifiers to ranges of masters and channels. If these rules (policy)
+are consistent with what decoder expects, it will be able to properly
+process the trace data.
+
+This policy is a tree structure containing rules (policy_node) that
+have a name (string identifier) and a range of masters and channels
+associated with it, located in "stp-policy" subsystem directory in
+configfs. The topmost directory's name (the policy) is formatted as
+the STM device name to which this policy applies and and arbitrary
+string identifier separated by a stop. From the examle above, a rule
+may look like this::
+
+ $ ls /config/stp-policy/dummy_stm.my-policy/user
+ channels masters
+ $ cat /config/stp-policy/dummy_stm.my-policy/user/masters
+ 48 63
+ $ cat /config/stp-policy/dummy_stm.my-policy/user/channels
+ 0 127
+
+which means that the master allocation pool for this rule consists of
+masters 48 through 63 and channel allocation pool has channels 0
+through 127 in it. Now, any producer (trace source) identifying itself
+with "user" identification string will be allocated a master and
+channel from within these ranges.
+
+These rules can be nested, for example, one can define a rule "dummy"
+under "user" directory from the example above and this new rule will
+be used for trace sources with the id string of "user/dummy".
+
+Trace sources have to open the stm class device's node and write their
+trace data into its file descriptor. In order to identify themselves
+to the policy, they need to do a STP_POLICY_ID_SET ioctl on this file
+descriptor providing their id string. Otherwise, they will be
+automatically allocated a master/channel pair upon first write to this
+file descriptor according to the "default" rule of the policy, if such
+exists.
+
+Some STM devices may allow direct mapping of the channel mmio regions
+to userspace for zero-copy writing. One mappable page (in terms of
+mmu) will usually contain multiple channels' mmios, so the user will
+need to allocate that many channels to themselves (via the
+aforementioned ioctl() call) to be able to do this. That is, if your
+stm device's channel mmio region is 64 bytes and hardware page size is
+4096 bytes, after a successful STP_POLICY_ID_SET ioctl() call with
+width==64, you should be able to mmap() one page on this file
+descriptor and obtain direct access to an mmio region for 64 channels.
+
+Examples of STM devices are Intel(R) Trace Hub [1] and Coresight STM
+[2].
+
+stm_source
+==========
+
+For kernel-based trace sources, there is "stm_source" device
+class. Devices of this class can be connected and disconnected to/from
+stm devices at runtime via a sysfs attribute called "stm_source_link"
+by writing the name of the desired stm device there, for example::
+
+ $ echo dummy_stm.0 > /sys/class/stm_source/console/stm_source_link
+
+For examples on how to use stm_source interface in the kernel, refer
+to stm_console, stm_heartbeat or stm_ftrace drivers.
+
+Each stm_source device will need to assume a master and a range of
+channels, depending on how many channels it requires. These are
+allocated for the device according to the policy configuration. If
+there's a node in the root of the policy directory that matches the
+stm_source device's name (for example, "console"), this node will be
+used to allocate master and channel numbers. If there's no such policy
+node, the stm core will pick the first contiguous chunk of channels
+within the first available master. Note that the node must exist
+before the stm_source device is connected to its stm device.
+
+stm_console
+===========
+
+One implementation of this interface also used in the example above is
+the "stm_console" driver, which basically provides a one-way console
+for kernel messages over an stm device.
+
+To configure the master/channel pair that will be assigned to this
+console in the STP stream, create a "console" policy entry (see the
+beginning of this text on how to do that). When initialized, it will
+consume one channel.
+
+stm_ftrace
+==========
+
+This is another "stm_source" device, once the stm_ftrace has been
+linked with an stm device, and if "function" tracer is enabled,
+function address and parent function address which Ftrace subsystem
+would store into ring buffer will be exported via the stm device at
+the same time.
+
+Currently only Ftrace "function" tracer is supported.
+
+* [1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
+* [2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0444b/index.html
diff --git a/Documentation/trace/stm.txt b/Documentation/trace/stm.txt
deleted file mode 100644
index 03765750104b..000000000000
--- a/Documentation/trace/stm.txt
+++ /dev/null
@@ -1,122 +0,0 @@
-System Trace Module
-===================
-
-System Trace Module (STM) is a device described in MIPI STP specs as
-STP trace stream generator. STP (System Trace Protocol) is a trace
-protocol multiplexing data from multiple trace sources, each one of
-which is assigned a unique pair of master and channel. While some of
-these masters and channels are statically allocated to certain
-hardware trace sources, others are available to software. Software
-trace sources are usually free to pick for themselves any
-master/channel combination from this pool.
-
-On the receiving end of this STP stream (the decoder side), trace
-sources can only be identified by master/channel combination, so in
-order for the decoder to be able to make sense of the trace that
-involves multiple trace sources, it needs to be able to map those
-master/channel pairs to the trace sources that it understands.
-
-For instance, it is helpful to know that syslog messages come on
-master 7 channel 15, while arbitrary user applications can use masters
-48 to 63 and channels 0 to 127.
-
-To solve this mapping problem, stm class provides a policy management
-mechanism via configfs, that allows defining rules that map string
-identifiers to ranges of masters and channels. If these rules (policy)
-are consistent with what decoder expects, it will be able to properly
-process the trace data.
-
-This policy is a tree structure containing rules (policy_node) that
-have a name (string identifier) and a range of masters and channels
-associated with it, located in "stp-policy" subsystem directory in
-configfs. The topmost directory's name (the policy) is formatted as
-the STM device name to which this policy applies and and arbitrary
-string identifier separated by a stop. From the examle above, a rule
-may look like this:
-
-$ ls /config/stp-policy/dummy_stm.my-policy/user
-channels masters
-$ cat /config/stp-policy/dummy_stm.my-policy/user/masters
-48 63
-$ cat /config/stp-policy/dummy_stm.my-policy/user/channels
-0 127
-
-which means that the master allocation pool for this rule consists of
-masters 48 through 63 and channel allocation pool has channels 0
-through 127 in it. Now, any producer (trace source) identifying itself
-with "user" identification string will be allocated a master and
-channel from within these ranges.
-
-These rules can be nested, for example, one can define a rule "dummy"
-under "user" directory from the example above and this new rule will
-be used for trace sources with the id string of "user/dummy".
-
-Trace sources have to open the stm class device's node and write their
-trace data into its file descriptor. In order to identify themselves
-to the policy, they need to do a STP_POLICY_ID_SET ioctl on this file
-descriptor providing their id string. Otherwise, they will be
-automatically allocated a master/channel pair upon first write to this
-file descriptor according to the "default" rule of the policy, if such
-exists.
-
-Some STM devices may allow direct mapping of the channel mmio regions
-to userspace for zero-copy writing. One mappable page (in terms of
-mmu) will usually contain multiple channels' mmios, so the user will
-need to allocate that many channels to themselves (via the
-aforementioned ioctl() call) to be able to do this. That is, if your
-stm device's channel mmio region is 64 bytes and hardware page size is
-4096 bytes, after a successful STP_POLICY_ID_SET ioctl() call with
-width==64, you should be able to mmap() one page on this file
-descriptor and obtain direct access to an mmio region for 64 channels.
-
-Examples of STM devices are Intel(R) Trace Hub [1] and Coresight STM
-[2].
-
-stm_source
-==========
-
-For kernel-based trace sources, there is "stm_source" device
-class. Devices of this class can be connected and disconnected to/from
-stm devices at runtime via a sysfs attribute called "stm_source_link"
-by writing the name of the desired stm device there, for example:
-
-$ echo dummy_stm.0 > /sys/class/stm_source/console/stm_source_link
-
-For examples on how to use stm_source interface in the kernel, refer
-to stm_console, stm_heartbeat or stm_ftrace drivers.
-
-Each stm_source device will need to assume a master and a range of
-channels, depending on how many channels it requires. These are
-allocated for the device according to the policy configuration. If
-there's a node in the root of the policy directory that matches the
-stm_source device's name (for example, "console"), this node will be
-used to allocate master and channel numbers. If there's no such policy
-node, the stm core will pick the first contiguous chunk of channels
-within the first available master. Note that the node must exist
-before the stm_source device is connected to its stm device.
-
-stm_console
-===========
-
-One implementation of this interface also used in the example above is
-the "stm_console" driver, which basically provides a one-way console
-for kernel messages over an stm device.
-
-To configure the master/channel pair that will be assigned to this
-console in the STP stream, create a "console" policy entry (see the
-beginning of this text on how to do that). When initialized, it will
-consume one channel.
-
-stm_ftrace
-==========
-
-This is another "stm_source" device, once the stm_ftrace has been
-linked with an stm device, and if "function" tracer is enabled,
-function address and parent function address which Ftrace subsystem
-would store into ring buffer will be exported via the stm device at
-the same time.
-
-Currently only Ftrace "function" tracer is supported.
-
-[1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
-[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0444b/index.html
diff --git a/Documentation/trace/tracepoint-analysis.rst b/Documentation/trace/tracepoint-analysis.rst
new file mode 100644
index 000000000000..a4d3ff2e5efb
--- /dev/null
+++ b/Documentation/trace/tracepoint-analysis.rst
@@ -0,0 +1,338 @@
+=========================================================
+Notes on Analysing Behaviour Using Events and Tracepoints
+=========================================================
+:Author: Mel Gorman (PCL information heavily based on email from Ingo Molnar)
+
+1. Introduction
+===============
+
+Tracepoints (see Documentation/trace/tracepoints.txt) can be used without
+creating custom kernel modules to register probe functions using the event
+tracing infrastructure.
+
+Simplistically, tracepoints represent important events that can be
+taken in conjunction with other tracepoints to build a "Big Picture" of
+what is going on within the system. There are a large number of methods for
+gathering and interpreting these events. Lacking any current Best Practises,
+this document describes some of the methods that can be used.
+
+This document assumes that debugfs is mounted on /sys/kernel/debug and that
+the appropriate tracing options have been configured into the kernel. It is
+assumed that the PCL tool tools/perf has been installed and is in your path.
+
+2. Listing Available Events
+===========================
+
+2.1 Standard Utilities
+----------------------
+
+All possible events are visible from /sys/kernel/debug/tracing/events. Simply
+calling::
+
+ $ find /sys/kernel/debug/tracing/events -type d
+
+will give a fair indication of the number of events available.
+
+2.2 PCL (Performance Counters for Linux)
+----------------------------------------
+
+Discovery and enumeration of all counters and events, including tracepoints,
+are available with the perf tool. Getting a list of available events is a
+simple case of::
+
+ $ perf list 2>&1 | grep Tracepoint
+ ext4:ext4_free_inode [Tracepoint event]
+ ext4:ext4_request_inode [Tracepoint event]
+ ext4:ext4_allocate_inode [Tracepoint event]
+ ext4:ext4_write_begin [Tracepoint event]
+ ext4:ext4_ordered_write_end [Tracepoint event]
+ [ .... remaining output snipped .... ]
+
+
+3. Enabling Events
+==================
+
+3.1 System-Wide Event Enabling
+------------------------------
+
+See Documentation/trace/events.txt for a proper description on how events
+can be enabled system-wide. A short example of enabling all events related
+to page allocation would look something like::
+
+ $ for i in `find /sys/kernel/debug/tracing/events -name "enable" | grep mm_`; do echo 1 > $i; done
+
+3.2 System-Wide Event Enabling with SystemTap
+---------------------------------------------
+
+In SystemTap, tracepoints are accessible using the kernel.trace() function
+call. The following is an example that reports every 5 seconds what processes
+were allocating the pages.
+::
+
+ global page_allocs
+
+ probe kernel.trace("mm_page_alloc") {
+ page_allocs[execname()]++
+ }
+
+ function print_count() {
+ printf ("%-25s %-s\n", "#Pages Allocated", "Process Name")
+ foreach (proc in page_allocs-)
+ printf("%-25d %s\n", page_allocs[proc], proc)
+ printf ("\n")
+ delete page_allocs
+ }
+
+ probe timer.s(5) {
+ print_count()
+ }
+
+3.3 System-Wide Event Enabling with PCL
+---------------------------------------
+
+By specifying the -a switch and analysing sleep, the system-wide events
+for a duration of time can be examined.
+::
+
+ $ perf stat -a \
+ -e kmem:mm_page_alloc -e kmem:mm_page_free \
+ -e kmem:mm_page_free_batched \
+ sleep 10
+ Performance counter stats for 'sleep 10':
+
+ 9630 kmem:mm_page_alloc
+ 2143 kmem:mm_page_free
+ 7424 kmem:mm_page_free_batched
+
+ 10.002577764 seconds time elapsed
+
+Similarly, one could execute a shell and exit it as desired to get a report
+at that point.
+
+3.4 Local Event Enabling
+------------------------
+
+Documentation/trace/ftrace.txt describes how to enable events on a per-thread
+basis using set_ftrace_pid.
+
+3.5 Local Event Enablement with PCL
+-----------------------------------
+
+Events can be activated and tracked for the duration of a process on a local
+basis using PCL such as follows.
+::
+
+ $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free \
+ -e kmem:mm_page_free_batched ./hackbench 10
+ Time: 0.909
+
+ Performance counter stats for './hackbench 10':
+
+ 17803 kmem:mm_page_alloc
+ 12398 kmem:mm_page_free
+ 4827 kmem:mm_page_free_batched
+
+ 0.973913387 seconds time elapsed
+
+4. Event Filtering
+==================
+
+Documentation/trace/ftrace.txt covers in-depth how to filter events in
+ftrace. Obviously using grep and awk of trace_pipe is an option as well
+as any script reading trace_pipe.
+
+5. Analysing Event Variances with PCL
+=====================================
+
+Any workload can exhibit variances between runs and it can be important
+to know what the standard deviation is. By and large, this is left to the
+performance analyst to do it by hand. In the event that the discrete event
+occurrences are useful to the performance analyst, then perf can be used.
+::
+
+ $ perf stat --repeat 5 -e kmem:mm_page_alloc -e kmem:mm_page_free
+ -e kmem:mm_page_free_batched ./hackbench 10
+ Time: 0.890
+ Time: 0.895
+ Time: 0.915
+ Time: 1.001
+ Time: 0.899
+
+ Performance counter stats for './hackbench 10' (5 runs):
+
+ 16630 kmem:mm_page_alloc ( +- 3.542% )
+ 11486 kmem:mm_page_free ( +- 4.771% )
+ 4730 kmem:mm_page_free_batched ( +- 2.325% )
+
+ 0.982653002 seconds time elapsed ( +- 1.448% )
+
+In the event that some higher-level event is required that depends on some
+aggregation of discrete events, then a script would need to be developed.
+
+Using --repeat, it is also possible to view how events are fluctuating over
+time on a system-wide basis using -a and sleep.
+::
+
+ $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free \
+ -e kmem:mm_page_free_batched \
+ -a --repeat 10 \
+ sleep 1
+ Performance counter stats for 'sleep 1' (10 runs):
+
+ 1066 kmem:mm_page_alloc ( +- 26.148% )
+ 182 kmem:mm_page_free ( +- 5.464% )
+ 890 kmem:mm_page_free_batched ( +- 30.079% )
+
+ 1.002251757 seconds time elapsed ( +- 0.005% )
+
+6. Higher-Level Analysis with Helper Scripts
+============================================
+
+When events are enabled the events that are triggering can be read from
+/sys/kernel/debug/tracing/trace_pipe in human-readable format although binary
+options exist as well. By post-processing the output, further information can
+be gathered on-line as appropriate. Examples of post-processing might include
+
+ - Reading information from /proc for the PID that triggered the event
+ - Deriving a higher-level event from a series of lower-level events.
+ - Calculating latencies between two events
+
+Documentation/trace/postprocess/trace-pagealloc-postprocess.pl is an example
+script that can read trace_pipe from STDIN or a copy of a trace. When used
+on-line, it can be interrupted once to generate a report without exiting
+and twice to exit.
+
+Simplistically, the script just reads STDIN and counts up events but it
+also can do more such as
+
+ - Derive high-level events from many low-level events. If a number of pages
+ are freed to the main allocator from the per-CPU lists, it recognises
+ that as one per-CPU drain even though there is no specific tracepoint
+ for that event
+ - It can aggregate based on PID or individual process number
+ - In the event memory is getting externally fragmented, it reports
+ on whether the fragmentation event was severe or moderate.
+ - When receiving an event about a PID, it can record who the parent was so
+ that if large numbers of events are coming from very short-lived
+ processes, the parent process responsible for creating all the helpers
+ can be identified
+
+7. Lower-Level Analysis with PCL
+================================
+
+There may also be a requirement to identify what functions within a program
+were generating events within the kernel. To begin this sort of analysis, the
+data must be recorded. At the time of writing, this required root:
+::
+
+ $ perf record -c 1 \
+ -e kmem:mm_page_alloc -e kmem:mm_page_free \
+ -e kmem:mm_page_free_batched \
+ ./hackbench 10
+ Time: 0.894
+ [ perf record: Captured and wrote 0.733 MB perf.data (~32010 samples) ]
+
+Note the use of '-c 1' to set the event period to sample. The default sample
+period is quite high to minimise overhead but the information collected can be
+very coarse as a result.
+
+This record outputted a file called perf.data which can be analysed using
+perf report.
+::
+
+ $ perf report
+ # Samples: 30922
+ #
+ # Overhead Command Shared Object
+ # ........ ......... ................................
+ #
+ 87.27% hackbench [vdso]
+ 6.85% hackbench /lib/i686/cmov/libc-2.9.so
+ 2.62% hackbench /lib/ld-2.9.so
+ 1.52% perf [vdso]
+ 1.22% hackbench ./hackbench
+ 0.48% hackbench [kernel]
+ 0.02% perf /lib/i686/cmov/libc-2.9.so
+ 0.01% perf /usr/bin/perf
+ 0.01% perf /lib/ld-2.9.so
+ 0.00% hackbench /lib/i686/cmov/libpthread-2.9.so
+ #
+ # (For more details, try: perf report --sort comm,dso,symbol)
+ #
+
+According to this, the vast majority of events triggered on events
+within the VDSO. With simple binaries, this will often be the case so let's
+take a slightly different example. In the course of writing this, it was
+noticed that X was generating an insane amount of page allocations so let's look
+at it:
+::
+
+ $ perf record -c 1 -f \
+ -e kmem:mm_page_alloc -e kmem:mm_page_free \
+ -e kmem:mm_page_free_batched \
+ -p `pidof X`
+
+This was interrupted after a few seconds and
+::
+
+ $ perf report
+ # Samples: 27666
+ #
+ # Overhead Command Shared Object
+ # ........ ....... .......................................
+ #
+ 51.95% Xorg [vdso]
+ 47.95% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1
+ 0.09% Xorg /lib/i686/cmov/libc-2.9.so
+ 0.01% Xorg [kernel]
+ #
+ # (For more details, try: perf report --sort comm,dso,symbol)
+ #
+
+So, almost half of the events are occurring in a library. To get an idea which
+symbol:
+::
+
+ $ perf report --sort comm,dso,symbol
+ # Samples: 27666
+ #
+ # Overhead Command Shared Object Symbol
+ # ........ ....... ....................................... ......
+ #
+ 51.95% Xorg [vdso] [.] 0x000000ffffe424
+ 47.93% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1 [.] pixmanFillsse2
+ 0.09% Xorg /lib/i686/cmov/libc-2.9.so [.] _int_malloc
+ 0.01% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1 [.] pixman_region32_copy_f
+ 0.01% Xorg [kernel] [k] read_hpet
+ 0.01% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1 [.] get_fast_path
+ 0.00% Xorg [kernel] [k] ftrace_trace_userstack
+
+To see where within the function pixmanFillsse2 things are going wrong:
+::
+
+ $ perf annotate pixmanFillsse2
+ [ ... ]
+ 0.00 : 34eeb: 0f 18 08 prefetcht0 (%eax)
+ : }
+ :
+ : extern __inline void __attribute__((__gnu_inline__, __always_inline__, _
+ : _mm_store_si128 (__m128i *__P, __m128i __B) : {
+ : *__P = __B;
+ 12.40 : 34eee: 66 0f 7f 80 40 ff ff movdqa %xmm0,-0xc0(%eax)
+ 0.00 : 34ef5: ff
+ 12.40 : 34ef6: 66 0f 7f 80 50 ff ff movdqa %xmm0,-0xb0(%eax)
+ 0.00 : 34efd: ff
+ 12.39 : 34efe: 66 0f 7f 80 60 ff ff movdqa %xmm0,-0xa0(%eax)
+ 0.00 : 34f05: ff
+ 12.67 : 34f06: 66 0f 7f 80 70 ff ff movdqa %xmm0,-0x90(%eax)
+ 0.00 : 34f0d: ff
+ 12.58 : 34f0e: 66 0f 7f 40 80 movdqa %xmm0,-0x80(%eax)
+ 12.31 : 34f13: 66 0f 7f 40 90 movdqa %xmm0,-0x70(%eax)
+ 12.40 : 34f18: 66 0f 7f 40 a0 movdqa %xmm0,-0x60(%eax)
+ 12.31 : 34f1d: 66 0f 7f 40 b0 movdqa %xmm0,-0x50(%eax)
+
+At a glance, it looks like the time is being spent copying pixmaps to
+the card. Further investigation would be needed to determine why pixmaps
+are being copied around so much but a starting point would be to take an
+ancient build of libpixmap out of the library path where it was totally
+forgotten about from months ago!
diff --git a/Documentation/trace/tracepoint-analysis.txt b/Documentation/trace/tracepoint-analysis.txt
deleted file mode 100644
index 058cc6c9dc56..000000000000
--- a/Documentation/trace/tracepoint-analysis.txt
+++ /dev/null
@@ -1,327 +0,0 @@
- Notes on Analysing Behaviour Using Events and Tracepoints
-
- Documentation written by Mel Gorman
- PCL information heavily based on email from Ingo Molnar
-
-1. Introduction
-===============
-
-Tracepoints (see Documentation/trace/tracepoints.txt) can be used without
-creating custom kernel modules to register probe functions using the event
-tracing infrastructure.
-
-Simplistically, tracepoints represent important events that can be
-taken in conjunction with other tracepoints to build a "Big Picture" of
-what is going on within the system. There are a large number of methods for
-gathering and interpreting these events. Lacking any current Best Practises,
-this document describes some of the methods that can be used.
-
-This document assumes that debugfs is mounted on /sys/kernel/debug and that
-the appropriate tracing options have been configured into the kernel. It is
-assumed that the PCL tool tools/perf has been installed and is in your path.
-
-2. Listing Available Events
-===========================
-
-2.1 Standard Utilities
-----------------------
-
-All possible events are visible from /sys/kernel/debug/tracing/events. Simply
-calling
-
- $ find /sys/kernel/debug/tracing/events -type d
-
-will give a fair indication of the number of events available.
-
-2.2 PCL (Performance Counters for Linux)
--------
-
-Discovery and enumeration of all counters and events, including tracepoints,
-are available with the perf tool. Getting a list of available events is a
-simple case of:
-
- $ perf list 2>&1 | grep Tracepoint
- ext4:ext4_free_inode [Tracepoint event]
- ext4:ext4_request_inode [Tracepoint event]
- ext4:ext4_allocate_inode [Tracepoint event]
- ext4:ext4_write_begin [Tracepoint event]
- ext4:ext4_ordered_write_end [Tracepoint event]
- [ .... remaining output snipped .... ]
-
-
-3. Enabling Events
-==================
-
-3.1 System-Wide Event Enabling
-------------------------------
-
-See Documentation/trace/events.txt for a proper description on how events
-can be enabled system-wide. A short example of enabling all events related
-to page allocation would look something like:
-
- $ for i in `find /sys/kernel/debug/tracing/events -name "enable" | grep mm_`; do echo 1 > $i; done
-
-3.2 System-Wide Event Enabling with SystemTap
----------------------------------------------
-
-In SystemTap, tracepoints are accessible using the kernel.trace() function
-call. The following is an example that reports every 5 seconds what processes
-were allocating the pages.
-
- global page_allocs
-
- probe kernel.trace("mm_page_alloc") {
- page_allocs[execname()]++
- }
-
- function print_count() {
- printf ("%-25s %-s\n", "#Pages Allocated", "Process Name")
- foreach (proc in page_allocs-)
- printf("%-25d %s\n", page_allocs[proc], proc)
- printf ("\n")
- delete page_allocs
- }
-
- probe timer.s(5) {
- print_count()
- }
-
-3.3 System-Wide Event Enabling with PCL
----------------------------------------
-
-By specifying the -a switch and analysing sleep, the system-wide events
-for a duration of time can be examined.
-
- $ perf stat -a \
- -e kmem:mm_page_alloc -e kmem:mm_page_free \
- -e kmem:mm_page_free_batched \
- sleep 10
- Performance counter stats for 'sleep 10':
-
- 9630 kmem:mm_page_alloc
- 2143 kmem:mm_page_free
- 7424 kmem:mm_page_free_batched
-
- 10.002577764 seconds time elapsed
-
-Similarly, one could execute a shell and exit it as desired to get a report
-at that point.
-
-3.4 Local Event Enabling
-------------------------
-
-Documentation/trace/ftrace.txt describes how to enable events on a per-thread
-basis using set_ftrace_pid.
-
-3.5 Local Event Enablement with PCL
------------------------------------
-
-Events can be activated and tracked for the duration of a process on a local
-basis using PCL such as follows.
-
- $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free \
- -e kmem:mm_page_free_batched ./hackbench 10
- Time: 0.909
-
- Performance counter stats for './hackbench 10':
-
- 17803 kmem:mm_page_alloc
- 12398 kmem:mm_page_free
- 4827 kmem:mm_page_free_batched
-
- 0.973913387 seconds time elapsed
-
-4. Event Filtering
-==================
-
-Documentation/trace/ftrace.txt covers in-depth how to filter events in
-ftrace. Obviously using grep and awk of trace_pipe is an option as well
-as any script reading trace_pipe.
-
-5. Analysing Event Variances with PCL
-=====================================
-
-Any workload can exhibit variances between runs and it can be important
-to know what the standard deviation is. By and large, this is left to the
-performance analyst to do it by hand. In the event that the discrete event
-occurrences are useful to the performance analyst, then perf can be used.
-
- $ perf stat --repeat 5 -e kmem:mm_page_alloc -e kmem:mm_page_free
- -e kmem:mm_page_free_batched ./hackbench 10
- Time: 0.890
- Time: 0.895
- Time: 0.915
- Time: 1.001
- Time: 0.899
-
- Performance counter stats for './hackbench 10' (5 runs):
-
- 16630 kmem:mm_page_alloc ( +- 3.542% )
- 11486 kmem:mm_page_free ( +- 4.771% )
- 4730 kmem:mm_page_free_batched ( +- 2.325% )
-
- 0.982653002 seconds time elapsed ( +- 1.448% )
-
-In the event that some higher-level event is required that depends on some
-aggregation of discrete events, then a script would need to be developed.
-
-Using --repeat, it is also possible to view how events are fluctuating over
-time on a system-wide basis using -a and sleep.
-
- $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free \
- -e kmem:mm_page_free_batched \
- -a --repeat 10 \
- sleep 1
- Performance counter stats for 'sleep 1' (10 runs):
-
- 1066 kmem:mm_page_alloc ( +- 26.148% )
- 182 kmem:mm_page_free ( +- 5.464% )
- 890 kmem:mm_page_free_batched ( +- 30.079% )
-
- 1.002251757 seconds time elapsed ( +- 0.005% )
-
-6. Higher-Level Analysis with Helper Scripts
-============================================
-
-When events are enabled the events that are triggering can be read from
-/sys/kernel/debug/tracing/trace_pipe in human-readable format although binary
-options exist as well. By post-processing the output, further information can
-be gathered on-line as appropriate. Examples of post-processing might include
-
- o Reading information from /proc for the PID that triggered the event
- o Deriving a higher-level event from a series of lower-level events.
- o Calculating latencies between two events
-
-Documentation/trace/postprocess/trace-pagealloc-postprocess.pl is an example
-script that can read trace_pipe from STDIN or a copy of a trace. When used
-on-line, it can be interrupted once to generate a report without exiting
-and twice to exit.
-
-Simplistically, the script just reads STDIN and counts up events but it
-also can do more such as
-
- o Derive high-level events from many low-level events. If a number of pages
- are freed to the main allocator from the per-CPU lists, it recognises
- that as one per-CPU drain even though there is no specific tracepoint
- for that event
- o It can aggregate based on PID or individual process number
- o In the event memory is getting externally fragmented, it reports
- on whether the fragmentation event was severe or moderate.
- o When receiving an event about a PID, it can record who the parent was so
- that if large numbers of events are coming from very short-lived
- processes, the parent process responsible for creating all the helpers
- can be identified
-
-7. Lower-Level Analysis with PCL
-================================
-
-There may also be a requirement to identify what functions within a program
-were generating events within the kernel. To begin this sort of analysis, the
-data must be recorded. At the time of writing, this required root:
-
- $ perf record -c 1 \
- -e kmem:mm_page_alloc -e kmem:mm_page_free \
- -e kmem:mm_page_free_batched \
- ./hackbench 10
- Time: 0.894
- [ perf record: Captured and wrote 0.733 MB perf.data (~32010 samples) ]
-
-Note the use of '-c 1' to set the event period to sample. The default sample
-period is quite high to minimise overhead but the information collected can be
-very coarse as a result.
-
-This record outputted a file called perf.data which can be analysed using
-perf report.
-
- $ perf report
- # Samples: 30922
- #
- # Overhead Command Shared Object
- # ........ ......... ................................
- #
- 87.27% hackbench [vdso]
- 6.85% hackbench /lib/i686/cmov/libc-2.9.so
- 2.62% hackbench /lib/ld-2.9.so
- 1.52% perf [vdso]
- 1.22% hackbench ./hackbench
- 0.48% hackbench [kernel]
- 0.02% perf /lib/i686/cmov/libc-2.9.so
- 0.01% perf /usr/bin/perf
- 0.01% perf /lib/ld-2.9.so
- 0.00% hackbench /lib/i686/cmov/libpthread-2.9.so
- #
- # (For more details, try: perf report --sort comm,dso,symbol)
- #
-
-According to this, the vast majority of events triggered on events
-within the VDSO. With simple binaries, this will often be the case so let's
-take a slightly different example. In the course of writing this, it was
-noticed that X was generating an insane amount of page allocations so let's look
-at it:
-
- $ perf record -c 1 -f \
- -e kmem:mm_page_alloc -e kmem:mm_page_free \
- -e kmem:mm_page_free_batched \
- -p `pidof X`
-
-This was interrupted after a few seconds and
-
- $ perf report
- # Samples: 27666
- #
- # Overhead Command Shared Object
- # ........ ....... .......................................
- #
- 51.95% Xorg [vdso]
- 47.95% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1
- 0.09% Xorg /lib/i686/cmov/libc-2.9.so
- 0.01% Xorg [kernel]
- #
- # (For more details, try: perf report --sort comm,dso,symbol)
- #
-
-So, almost half of the events are occurring in a library. To get an idea which
-symbol:
-
- $ perf report --sort comm,dso,symbol
- # Samples: 27666
- #
- # Overhead Command Shared Object Symbol
- # ........ ....... ....................................... ......
- #
- 51.95% Xorg [vdso] [.] 0x000000ffffe424
- 47.93% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1 [.] pixmanFillsse2
- 0.09% Xorg /lib/i686/cmov/libc-2.9.so [.] _int_malloc
- 0.01% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1 [.] pixman_region32_copy_f
- 0.01% Xorg [kernel] [k] read_hpet
- 0.01% Xorg /opt/gfx-test/lib/libpixman-1.so.0.13.1 [.] get_fast_path
- 0.00% Xorg [kernel] [k] ftrace_trace_userstack
-
-To see where within the function pixmanFillsse2 things are going wrong:
-
- $ perf annotate pixmanFillsse2
- [ ... ]
- 0.00 : 34eeb: 0f 18 08 prefetcht0 (%eax)
- : }
- :
- : extern __inline void __attribute__((__gnu_inline__, __always_inline__, _
- : _mm_store_si128 (__m128i *__P, __m128i __B) : {
- : *__P = __B;
- 12.40 : 34eee: 66 0f 7f 80 40 ff ff movdqa %xmm0,-0xc0(%eax)
- 0.00 : 34ef5: ff
- 12.40 : 34ef6: 66 0f 7f 80 50 ff ff movdqa %xmm0,-0xb0(%eax)
- 0.00 : 34efd: ff
- 12.39 : 34efe: 66 0f 7f 80 60 ff ff movdqa %xmm0,-0xa0(%eax)
- 0.00 : 34f05: ff
- 12.67 : 34f06: 66 0f 7f 80 70 ff ff movdqa %xmm0,-0x90(%eax)
- 0.00 : 34f0d: ff
- 12.58 : 34f0e: 66 0f 7f 40 80 movdqa %xmm0,-0x80(%eax)
- 12.31 : 34f13: 66 0f 7f 40 90 movdqa %xmm0,-0x70(%eax)
- 12.40 : 34f18: 66 0f 7f 40 a0 movdqa %xmm0,-0x60(%eax)
- 12.31 : 34f1d: 66 0f 7f 40 b0 movdqa %xmm0,-0x50(%eax)
-
-At a glance, it looks like the time is being spent copying pixmaps to
-the card. Further investigation would be needed to determine why pixmaps
-are being copied around so much but a starting point would be to take an
-ancient build of libpixmap out of the library path where it was totally
-forgotten about from months ago!
diff --git a/Documentation/trace/tracepoints.rst b/Documentation/trace/tracepoints.rst
new file mode 100644
index 000000000000..6e3ce3bf3593
--- /dev/null
+++ b/Documentation/trace/tracepoints.rst
@@ -0,0 +1,148 @@
+==================================
+Using the Linux Kernel Tracepoints
+==================================
+
+:Author: Mathieu Desnoyers
+
+
+This document introduces Linux Kernel Tracepoints and their use. It
+provides examples of how to insert tracepoints in the kernel and
+connect probe functions to them and provides some examples of probe
+functions.
+
+
+Purpose of tracepoints
+----------------------
+A tracepoint placed in code provides a hook to call a function (probe)
+that you can provide at runtime. A tracepoint can be "on" (a probe is
+connected to it) or "off" (no probe is attached). When a tracepoint is
+"off" it has no effect, except for adding a tiny time penalty
+(checking a condition for a branch) and space penalty (adding a few
+bytes for the function call at the end of the instrumented function
+and adds a data structure in a separate section). When a tracepoint
+is "on", the function you provide is called each time the tracepoint
+is executed, in the execution context of the caller. When the function
+provided ends its execution, it returns to the caller (continuing from
+the tracepoint site).
+
+You can put tracepoints at important locations in the code. They are
+lightweight hooks that can pass an arbitrary number of parameters,
+which prototypes are described in a tracepoint declaration placed in a
+header file.
+
+They can be used for tracing and performance accounting.
+
+
+Usage
+-----
+Two elements are required for tracepoints :
+
+- A tracepoint definition, placed in a header file.
+- The tracepoint statement, in C code.
+
+In order to use tracepoints, you should include linux/tracepoint.h.
+
+In include/trace/events/subsys.h::
+
+ #undef TRACE_SYSTEM
+ #define TRACE_SYSTEM subsys
+
+ #if !defined(_TRACE_SUBSYS_H) || defined(TRACE_HEADER_MULTI_READ)
+ #define _TRACE_SUBSYS_H
+
+ #include <linux/tracepoint.h>
+
+ DECLARE_TRACE(subsys_eventname,
+ TP_PROTO(int firstarg, struct task_struct *p),
+ TP_ARGS(firstarg, p));
+
+ #endif /* _TRACE_SUBSYS_H */
+
+ /* This part must be outside protection */
+ #include <trace/define_trace.h>
+
+In subsys/file.c (where the tracing statement must be added)::
+
+ #include <trace/events/subsys.h>
+
+ #define CREATE_TRACE_POINTS
+ DEFINE_TRACE(subsys_eventname);
+
+ void somefct(void)
+ {
+ ...
+ trace_subsys_eventname(arg, task);
+ ...
+ }
+
+Where :
+ - subsys_eventname is an identifier unique to your event
+
+ - subsys is the name of your subsystem.
+ - eventname is the name of the event to trace.
+
+ - `TP_PROTO(int firstarg, struct task_struct *p)` is the prototype of the
+ function called by this tracepoint.
+
+ - `TP_ARGS(firstarg, p)` are the parameters names, same as found in the
+ prototype.
+
+ - if you use the header in multiple source files, `#define CREATE_TRACE_POINTS`
+ should appear only in one source file.
+
+Connecting a function (probe) to a tracepoint is done by providing a
+probe (function to call) for the specific tracepoint through
+register_trace_subsys_eventname(). Removing a probe is done through
+unregister_trace_subsys_eventname(); it will remove the probe.
+
+tracepoint_synchronize_unregister() must be called before the end of
+the module exit function to make sure there is no caller left using
+the probe. This, and the fact that preemption is disabled around the
+probe call, make sure that probe removal and module unload are safe.
+
+The tracepoint mechanism supports inserting multiple instances of the
+same tracepoint, but a single definition must be made of a given
+tracepoint name over all the kernel to make sure no type conflict will
+occur. Name mangling of the tracepoints is done using the prototypes
+to make sure typing is correct. Verification of probe type correctness
+is done at the registration site by the compiler. Tracepoints can be
+put in inline functions, inlined static functions, and unrolled loops
+as well as regular functions.
+
+The naming scheme "subsys_event" is suggested here as a convention
+intended to limit collisions. Tracepoint names are global to the
+kernel: they are considered as being the same whether they are in the
+core kernel image or in modules.
+
+If the tracepoint has to be used in kernel modules, an
+EXPORT_TRACEPOINT_SYMBOL_GPL() or EXPORT_TRACEPOINT_SYMBOL() can be
+used to export the defined tracepoints.
+
+If you need to do a bit of work for a tracepoint parameter, and
+that work is only used for the tracepoint, that work can be encapsulated
+within an if statement with the following::
+
+ if (trace_foo_bar_enabled()) {
+ int i;
+ int tot = 0;
+
+ for (i = 0; i < count; i++)
+ tot += calculate_nuggets();
+
+ trace_foo_bar(tot);
+ }
+
+All trace_<tracepoint>() calls have a matching trace_<tracepoint>_enabled()
+function defined that returns true if the tracepoint is enabled and
+false otherwise. The trace_<tracepoint>() should always be within the
+block of the if (trace_<tracepoint>_enabled()) to prevent races between
+the tracepoint being enabled and the check being seen.
+
+The advantage of using the trace_<tracepoint>_enabled() is that it uses
+the static_key of the tracepoint to allow the if statement to be implemented
+with jump labels and avoid conditional branches.
+
+.. note:: The convenience macro TRACE_EVENT provides an alternative way to
+ define tracepoints. Check http://lwn.net/Articles/379903,
+ http://lwn.net/Articles/381064 and http://lwn.net/Articles/383362
+ for a series of articles with more details.
diff --git a/Documentation/trace/tracepoints.txt b/Documentation/trace/tracepoints.txt
deleted file mode 100644
index a3efac621c5a..000000000000
--- a/Documentation/trace/tracepoints.txt
+++ /dev/null
@@ -1,145 +0,0 @@
- Using the Linux Kernel Tracepoints
-
- Mathieu Desnoyers
-
-
-This document introduces Linux Kernel Tracepoints and their use. It
-provides examples of how to insert tracepoints in the kernel and
-connect probe functions to them and provides some examples of probe
-functions.
-
-
-* Purpose of tracepoints
-
-A tracepoint placed in code provides a hook to call a function (probe)
-that you can provide at runtime. A tracepoint can be "on" (a probe is
-connected to it) or "off" (no probe is attached). When a tracepoint is
-"off" it has no effect, except for adding a tiny time penalty
-(checking a condition for a branch) and space penalty (adding a few
-bytes for the function call at the end of the instrumented function
-and adds a data structure in a separate section). When a tracepoint
-is "on", the function you provide is called each time the tracepoint
-is executed, in the execution context of the caller. When the function
-provided ends its execution, it returns to the caller (continuing from
-the tracepoint site).
-
-You can put tracepoints at important locations in the code. They are
-lightweight hooks that can pass an arbitrary number of parameters,
-which prototypes are described in a tracepoint declaration placed in a
-header file.
-
-They can be used for tracing and performance accounting.
-
-
-* Usage
-
-Two elements are required for tracepoints :
-
-- A tracepoint definition, placed in a header file.
-- The tracepoint statement, in C code.
-
-In order to use tracepoints, you should include linux/tracepoint.h.
-
-In include/trace/events/subsys.h :
-
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM subsys
-
-#if !defined(_TRACE_SUBSYS_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _TRACE_SUBSYS_H
-
-#include <linux/tracepoint.h>
-
-DECLARE_TRACE(subsys_eventname,
- TP_PROTO(int firstarg, struct task_struct *p),
- TP_ARGS(firstarg, p));
-
-#endif /* _TRACE_SUBSYS_H */
-
-/* This part must be outside protection */
-#include <trace/define_trace.h>
-
-In subsys/file.c (where the tracing statement must be added) :
-
-#include <trace/events/subsys.h>
-
-#define CREATE_TRACE_POINTS
-DEFINE_TRACE(subsys_eventname);
-
-void somefct(void)
-{
- ...
- trace_subsys_eventname(arg, task);
- ...
-}
-
-Where :
-- subsys_eventname is an identifier unique to your event
- - subsys is the name of your subsystem.
- - eventname is the name of the event to trace.
-
-- TP_PROTO(int firstarg, struct task_struct *p) is the prototype of the
- function called by this tracepoint.
-
-- TP_ARGS(firstarg, p) are the parameters names, same as found in the
- prototype.
-
-- if you use the header in multiple source files, #define CREATE_TRACE_POINTS
- should appear only in one source file.
-
-Connecting a function (probe) to a tracepoint is done by providing a
-probe (function to call) for the specific tracepoint through
-register_trace_subsys_eventname(). Removing a probe is done through
-unregister_trace_subsys_eventname(); it will remove the probe.
-
-tracepoint_synchronize_unregister() must be called before the end of
-the module exit function to make sure there is no caller left using
-the probe. This, and the fact that preemption is disabled around the
-probe call, make sure that probe removal and module unload are safe.
-
-The tracepoint mechanism supports inserting multiple instances of the
-same tracepoint, but a single definition must be made of a given
-tracepoint name over all the kernel to make sure no type conflict will
-occur. Name mangling of the tracepoints is done using the prototypes
-to make sure typing is correct. Verification of probe type correctness
-is done at the registration site by the compiler. Tracepoints can be
-put in inline functions, inlined static functions, and unrolled loops
-as well as regular functions.
-
-The naming scheme "subsys_event" is suggested here as a convention
-intended to limit collisions. Tracepoint names are global to the
-kernel: they are considered as being the same whether they are in the
-core kernel image or in modules.
-
-If the tracepoint has to be used in kernel modules, an
-EXPORT_TRACEPOINT_SYMBOL_GPL() or EXPORT_TRACEPOINT_SYMBOL() can be
-used to export the defined tracepoints.
-
-If you need to do a bit of work for a tracepoint parameter, and
-that work is only used for the tracepoint, that work can be encapsulated
-within an if statement with the following:
-
- if (trace_foo_bar_enabled()) {
- int i;
- int tot = 0;
-
- for (i = 0; i < count; i++)
- tot += calculate_nuggets();
-
- trace_foo_bar(tot);
- }
-
-All trace_<tracepoint>() calls have a matching trace_<tracepoint>_enabled()
-function defined that returns true if the tracepoint is enabled and
-false otherwise. The trace_<tracepoint>() should always be within the
-block of the if (trace_<tracepoint>_enabled()) to prevent races between
-the tracepoint being enabled and the check being seen.
-
-The advantage of using the trace_<tracepoint>_enabled() is that it uses
-the static_key of the tracepoint to allow the if statement to be implemented
-with jump labels and avoid conditional branches.
-
-Note: The convenience macro TRACE_EVENT provides an alternative way to
- define tracepoints. Check http://lwn.net/Articles/379903,
- http://lwn.net/Articles/381064 and http://lwn.net/Articles/383362
- for a series of articles with more details.
diff --git a/Documentation/trace/uprobetracer.rst b/Documentation/trace/uprobetracer.rst
new file mode 100644
index 000000000000..98d3f692957a
--- /dev/null
+++ b/Documentation/trace/uprobetracer.rst
@@ -0,0 +1,173 @@
+=========================================
+Uprobe-tracer: Uprobe-based Event Tracing
+=========================================
+
+:Author: Srikar Dronamraju
+
+
+Overview
+--------
+Uprobe based trace events are similar to kprobe based trace events.
+To enable this feature, build your kernel with CONFIG_UPROBE_EVENTS=y.
+
+Similar to the kprobe-event tracer, this doesn't need to be activated via
+current_tracer. Instead of that, add probe points via
+/sys/kernel/debug/tracing/uprobe_events, and enable it via
+/sys/kernel/debug/tracing/events/uprobes/<EVENT>/enabled.
+
+However unlike kprobe-event tracer, the uprobe event interface expects the
+user to calculate the offset of the probepoint in the object.
+
+Synopsis of uprobe_tracer
+-------------------------
+::
+
+ p[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a uprobe
+ r[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a return uprobe (uretprobe)
+ -:[GRP/]EVENT : Clear uprobe or uretprobe event
+
+ GRP : Group name. If omitted, "uprobes" is the default value.
+ EVENT : Event name. If omitted, the event name is generated based
+ on PATH+OFFSET.
+ PATH : Path to an executable or a library.
+ OFFSET : Offset where the probe is inserted.
+
+ FETCHARGS : Arguments. Each probe can have up to 128 args.
+ %REG : Fetch register REG
+ @ADDR : Fetch memory at ADDR (ADDR should be in userspace)
+ @+OFFSET : Fetch memory at OFFSET (OFFSET from same file as PATH)
+ $stackN : Fetch Nth entry of stack (N >= 0)
+ $stack : Fetch stack address.
+ $retval : Fetch return value.(*)
+ $comm : Fetch current task comm.
+ +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**)
+ NAME=FETCHARG : Set NAME as the argument name of FETCHARG.
+ FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types
+ (u8/u16/u32/u64/s8/s16/s32/s64), hexadecimal types
+ (x8/x16/x32/x64), "string" and bitfield are supported.
+
+ (*) only for return probe.
+ (**) this is useful for fetching a field of data structures.
+
+Types
+-----
+Several types are supported for fetch-args. Uprobe tracer will access memory
+by given type. Prefix 's' and 'u' means those types are signed and unsigned
+respectively. 'x' prefix implies it is unsigned. Traced arguments are shown
+in decimal ('s' and 'u') or hexadecimal ('x'). Without type casting, 'x32'
+or 'x64' is used depends on the architecture (e.g. x86-32 uses x32, and
+x86-64 uses x64).
+String type is a special type, which fetches a "null-terminated" string from
+user space.
+Bitfield is another special type, which takes 3 parameters, bit-width, bit-
+offset, and container-size (usually 32). The syntax is::
+
+ b<bit-width>@<bit-offset>/<container-size>
+
+For $comm, the default type is "string"; any other type is invalid.
+
+
+Event Profiling
+---------------
+You can check the total number of probe hits and probe miss-hits via
+/sys/kernel/debug/tracing/uprobe_profile.
+The first column is event name, the second is the number of probe hits,
+the third is the number of probe miss-hits.
+
+Usage examples
+--------------
+ * Add a probe as a new uprobe event, write a new definition to uprobe_events
+ as below (sets a uprobe at an offset of 0x4245c0 in the executable /bin/bash)::
+
+ echo 'p /bin/bash:0x4245c0' > /sys/kernel/debug/tracing/uprobe_events
+
+ * Add a probe as a new uretprobe event::
+
+ echo 'r /bin/bash:0x4245c0' > /sys/kernel/debug/tracing/uprobe_events
+
+ * Unset registered event::
+
+ echo '-:p_bash_0x4245c0' >> /sys/kernel/debug/tracing/uprobe_events
+
+ * Print out the events that are registered::
+
+ cat /sys/kernel/debug/tracing/uprobe_events
+
+ * Clear all events::
+
+ echo > /sys/kernel/debug/tracing/uprobe_events
+
+Following example shows how to dump the instruction pointer and %ax register
+at the probed text address. Probe zfree function in /bin/zsh::
+
+ # cd /sys/kernel/debug/tracing/
+ # cat /proc/`pgrep zsh`/maps | grep /bin/zsh | grep r-xp
+ 00400000-0048a000 r-xp 00000000 08:03 130904 /bin/zsh
+ # objdump -T /bin/zsh | grep -w zfree
+ 0000000000446420 g DF .text 0000000000000012 Base zfree
+
+0x46420 is the offset of zfree in object /bin/zsh that is loaded at
+0x00400000. Hence the command to uprobe would be::
+
+ # echo 'p:zfree_entry /bin/zsh:0x46420 %ip %ax' > uprobe_events
+
+And the same for the uretprobe would be::
+
+ # echo 'r:zfree_exit /bin/zsh:0x46420 %ip %ax' >> uprobe_events
+
+.. note:: User has to explicitly calculate the offset of the probe-point
+ in the object.
+
+We can see the events that are registered by looking at the uprobe_events file.
+::
+
+ # cat uprobe_events
+ p:uprobes/zfree_entry /bin/zsh:0x00046420 arg1=%ip arg2=%ax
+ r:uprobes/zfree_exit /bin/zsh:0x00046420 arg1=%ip arg2=%ax
+
+Format of events can be seen by viewing the file events/uprobes/zfree_entry/format.
+::
+
+ # cat events/uprobes/zfree_entry/format
+ name: zfree_entry
+ ID: 922
+ format:
+ field:unsigned short common_type; offset:0; size:2; signed:0;
+ field:unsigned char common_flags; offset:2; size:1; signed:0;
+ field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
+ field:int common_pid; offset:4; size:4; signed:1;
+ field:int common_padding; offset:8; size:4; signed:1;
+
+ field:unsigned long __probe_ip; offset:12; size:4; signed:0;
+ field:u32 arg1; offset:16; size:4; signed:0;
+ field:u32 arg2; offset:20; size:4; signed:0;
+
+ print fmt: "(%lx) arg1=%lx arg2=%lx", REC->__probe_ip, REC->arg1, REC->arg2
+
+Right after definition, each event is disabled by default. For tracing these
+events, you need to enable it by::
+
+ # echo 1 > events/uprobes/enable
+
+Lets disable the event after sleeping for some time.
+::
+
+ # sleep 20
+ # echo 0 > events/uprobes/enable
+
+And you can see the traced information via /sys/kernel/debug/tracing/trace.
+::
+
+ # cat trace
+ # tracer: nop
+ #
+ # TASK-PID CPU# TIMESTAMP FUNCTION
+ # | | | | |
+ zsh-24842 [006] 258544.995456: zfree_entry: (0x446420) arg1=446420 arg2=79
+ zsh-24842 [007] 258545.000270: zfree_exit: (0x446540 <- 0x446420) arg1=446540 arg2=0
+ zsh-24842 [002] 258545.043929: zfree_entry: (0x446420) arg1=446420 arg2=79
+ zsh-24842 [004] 258547.046129: zfree_exit: (0x446540 <- 0x446420) arg1=446540 arg2=0
+
+Output shows us uprobe was triggered for a pid 24842 with ip being 0x446420
+and contents of ax register being 79. And uretprobe was triggered with ip at
+0x446540 with counterpart function entry at 0x446420.
diff --git a/Documentation/trace/uprobetracer.txt b/Documentation/trace/uprobetracer.txt
deleted file mode 100644
index bf526a7c5559..000000000000
--- a/Documentation/trace/uprobetracer.txt
+++ /dev/null
@@ -1,165 +0,0 @@
- Uprobe-tracer: Uprobe-based Event Tracing
- =========================================
-
- Documentation written by Srikar Dronamraju
-
-
-Overview
---------
-Uprobe based trace events are similar to kprobe based trace events.
-To enable this feature, build your kernel with CONFIG_UPROBE_EVENTS=y.
-
-Similar to the kprobe-event tracer, this doesn't need to be activated via
-current_tracer. Instead of that, add probe points via
-/sys/kernel/debug/tracing/uprobe_events, and enable it via
-/sys/kernel/debug/tracing/events/uprobes/<EVENT>/enabled.
-
-However unlike kprobe-event tracer, the uprobe event interface expects the
-user to calculate the offset of the probepoint in the object.
-
-Synopsis of uprobe_tracer
--------------------------
- p[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a uprobe
- r[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a return uprobe (uretprobe)
- -:[GRP/]EVENT : Clear uprobe or uretprobe event
-
- GRP : Group name. If omitted, "uprobes" is the default value.
- EVENT : Event name. If omitted, the event name is generated based
- on PATH+OFFSET.
- PATH : Path to an executable or a library.
- OFFSET : Offset where the probe is inserted.
-
- FETCHARGS : Arguments. Each probe can have up to 128 args.
- %REG : Fetch register REG
- @ADDR : Fetch memory at ADDR (ADDR should be in userspace)
- @+OFFSET : Fetch memory at OFFSET (OFFSET from same file as PATH)
- $stackN : Fetch Nth entry of stack (N >= 0)
- $stack : Fetch stack address.
- $retval : Fetch return value.(*)
- $comm : Fetch current task comm.
- +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**)
- NAME=FETCHARG : Set NAME as the argument name of FETCHARG.
- FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types
- (u8/u16/u32/u64/s8/s16/s32/s64), hexadecimal types
- (x8/x16/x32/x64), "string" and bitfield are supported.
-
- (*) only for return probe.
- (**) this is useful for fetching a field of data structures.
-
-Types
------
-Several types are supported for fetch-args. Uprobe tracer will access memory
-by given type. Prefix 's' and 'u' means those types are signed and unsigned
-respectively. 'x' prefix implies it is unsigned. Traced arguments are shown
-in decimal ('s' and 'u') or hexadecimal ('x'). Without type casting, 'x32'
-or 'x64' is used depends on the architecture (e.g. x86-32 uses x32, and
-x86-64 uses x64).
-String type is a special type, which fetches a "null-terminated" string from
-user space.
-Bitfield is another special type, which takes 3 parameters, bit-width, bit-
-offset, and container-size (usually 32). The syntax is;
-
- b<bit-width>@<bit-offset>/<container-size>
-
-For $comm, the default type is "string"; any other type is invalid.
-
-
-Event Profiling
----------------
-You can check the total number of probe hits and probe miss-hits via
-/sys/kernel/debug/tracing/uprobe_profile.
-The first column is event name, the second is the number of probe hits,
-the third is the number of probe miss-hits.
-
-Usage examples
---------------
- * Add a probe as a new uprobe event, write a new definition to uprobe_events
-as below: (sets a uprobe at an offset of 0x4245c0 in the executable /bin/bash)
-
- echo 'p /bin/bash:0x4245c0' > /sys/kernel/debug/tracing/uprobe_events
-
- * Add a probe as a new uretprobe event:
-
- echo 'r /bin/bash:0x4245c0' > /sys/kernel/debug/tracing/uprobe_events
-
- * Unset registered event:
-
- echo '-:p_bash_0x4245c0' >> /sys/kernel/debug/tracing/uprobe_events
-
- * Print out the events that are registered:
-
- cat /sys/kernel/debug/tracing/uprobe_events
-
- * Clear all events:
-
- echo > /sys/kernel/debug/tracing/uprobe_events
-
-Following example shows how to dump the instruction pointer and %ax register
-at the probed text address. Probe zfree function in /bin/zsh:
-
- # cd /sys/kernel/debug/tracing/
- # cat /proc/`pgrep zsh`/maps | grep /bin/zsh | grep r-xp
- 00400000-0048a000 r-xp 00000000 08:03 130904 /bin/zsh
- # objdump -T /bin/zsh | grep -w zfree
- 0000000000446420 g DF .text 0000000000000012 Base zfree
-
- 0x46420 is the offset of zfree in object /bin/zsh that is loaded at
- 0x00400000. Hence the command to uprobe would be:
-
- # echo 'p:zfree_entry /bin/zsh:0x46420 %ip %ax' > uprobe_events
-
- And the same for the uretprobe would be:
-
- # echo 'r:zfree_exit /bin/zsh:0x46420 %ip %ax' >> uprobe_events
-
-Please note: User has to explicitly calculate the offset of the probe-point
-in the object. We can see the events that are registered by looking at the
-uprobe_events file.
-
- # cat uprobe_events
- p:uprobes/zfree_entry /bin/zsh:0x00046420 arg1=%ip arg2=%ax
- r:uprobes/zfree_exit /bin/zsh:0x00046420 arg1=%ip arg2=%ax
-
-Format of events can be seen by viewing the file events/uprobes/zfree_entry/format
-
- # cat events/uprobes/zfree_entry/format
- name: zfree_entry
- ID: 922
- format:
- field:unsigned short common_type; offset:0; size:2; signed:0;
- field:unsigned char common_flags; offset:2; size:1; signed:0;
- field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
- field:int common_pid; offset:4; size:4; signed:1;
- field:int common_padding; offset:8; size:4; signed:1;
-
- field:unsigned long __probe_ip; offset:12; size:4; signed:0;
- field:u32 arg1; offset:16; size:4; signed:0;
- field:u32 arg2; offset:20; size:4; signed:0;
-
- print fmt: "(%lx) arg1=%lx arg2=%lx", REC->__probe_ip, REC->arg1, REC->arg2
-
-Right after definition, each event is disabled by default. For tracing these
-events, you need to enable it by:
-
- # echo 1 > events/uprobes/enable
-
-Lets disable the event after sleeping for some time.
-
- # sleep 20
- # echo 0 > events/uprobes/enable
-
-And you can see the traced information via /sys/kernel/debug/tracing/trace.
-
- # cat trace
- # tracer: nop
- #
- # TASK-PID CPU# TIMESTAMP FUNCTION
- # | | | | |
- zsh-24842 [006] 258544.995456: zfree_entry: (0x446420) arg1=446420 arg2=79
- zsh-24842 [007] 258545.000270: zfree_exit: (0x446540 <- 0x446420) arg1=446540 arg2=0
- zsh-24842 [002] 258545.043929: zfree_entry: (0x446420) arg1=446420 arg2=79
- zsh-24842 [004] 258547.046129: zfree_exit: (0x446540 <- 0x446420) arg1=446540 arg2=0
-
-Output shows us uprobe was triggered for a pid 24842 with ip being 0x446420
-and contents of ax register being 79. And uretprobe was triggered with ip at
-0x446540 with counterpart function entry at 0x446420.
diff --git a/Documentation/virtual/kvm/00-INDEX b/Documentation/virtual/kvm/00-INDEX
index 3da73aabff5a..3492458a4ae8 100644
--- a/Documentation/virtual/kvm/00-INDEX
+++ b/Documentation/virtual/kvm/00-INDEX
@@ -1,7 +1,12 @@
00-INDEX
- this file.
+amd-memory-encryption.rst
+ - notes on AMD Secure Encrypted Virtualization feature and SEV firmware
+ command description
api.txt
- KVM userspace API.
+arm
+ - internal ABI between the kernel and HYP (for arm/arm64)
cpuid.txt
- KVM-specific cpuid leaves (x86).
devices/
@@ -26,6 +31,5 @@ s390-diag.txt
- Diagnose hypercall description (for IBM S/390)
timekeeping.txt
- timekeeping virtualization for x86-based architectures.
-amd-memory-encryption.txt
- - notes on AMD Secure Encrypted Virtualization feature and SEV firmware
- command description
+vcpu-requests.rst
+ - internal VCPU request API
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index d6b3ff51a14f..1c7958b57fe9 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -3480,7 +3480,7 @@ encrypted VMs.
Currently, this ioctl is used for issuing Secure Encrypted Virtualization
(SEV) commands on AMD Processors. The SEV commands are defined in
-Documentation/virtual/kvm/amd-memory-encryption.txt.
+Documentation/virtual/kvm/amd-memory-encryption.rst.
4.111 KVM_MEMORY_ENCRYPT_REG_REGION
@@ -3516,6 +3516,38 @@ Returns: 0 on success; -1 on error
This ioctl can be used to unregister the guest memory region registered
with KVM_MEMORY_ENCRYPT_REG_REGION ioctl above.
+4.113 KVM_HYPERV_EVENTFD
+
+Capability: KVM_CAP_HYPERV_EVENTFD
+Architectures: x86
+Type: vm ioctl
+Parameters: struct kvm_hyperv_eventfd (in)
+
+This ioctl (un)registers an eventfd to receive notifications from the guest on
+the specified Hyper-V connection id through the SIGNAL_EVENT hypercall, without
+causing a user exit. SIGNAL_EVENT hypercall with non-zero event flag number
+(bits 24-31) still triggers a KVM_EXIT_HYPERV_HCALL user exit.
+
+struct kvm_hyperv_eventfd {
+ __u32 conn_id;
+ __s32 fd;
+ __u32 flags;
+ __u32 padding[3];
+};
+
+The conn_id field should fit within 24 bits:
+
+#define KVM_HYPERV_CONN_ID_MASK 0x00ffffff
+
+The acceptable values for the flags field are:
+
+#define KVM_HYPERV_EVENTFD_DEASSIGN (1 << 0)
+
+Returns: 0 on success,
+ -EINVAL if conn_id or flags is outside the allowed range
+ -ENOENT on deassign if the conn_id isn't registered
+ -EEXIST on assign if the conn_id is already registered
+
5. The kvm_run structure
------------------------
@@ -3873,7 +3905,7 @@ in userspace.
__u64 kvm_dirty_regs;
union {
struct kvm_sync_regs regs;
- char padding[1024];
+ char padding[SYNC_REGS_SIZE_BYTES];
} s;
If KVM_CAP_SYNC_REGS is defined, these fields allow userspace to access
@@ -4078,6 +4110,46 @@ Once this is done the KVM_REG_MIPS_VEC_* and KVM_REG_MIPS_MSA_* registers can be
accessed, and the Config5.MSAEn bit is accessible via the KVM API and also from
the guest.
+6.74 KVM_CAP_SYNC_REGS
+Architectures: s390, x86
+Target: s390: always enabled, x86: vcpu
+Parameters: none
+Returns: x86: KVM_CHECK_EXTENSION returns a bit-array indicating which register
+sets are supported (bitfields defined in arch/x86/include/uapi/asm/kvm.h).
+
+As described above in the kvm_sync_regs struct info in section 5 (kvm_run):
+KVM_CAP_SYNC_REGS "allow[s] userspace to access certain guest registers
+without having to call SET/GET_*REGS". This reduces overhead by eliminating
+repeated ioctl calls for setting and/or getting register values. This is
+particularly important when userspace is making synchronous guest state
+modifications, e.g. when emulating and/or intercepting instructions in
+userspace.
+
+For s390 specifics, please refer to the source code.
+
+For x86:
+- the register sets to be copied out to kvm_run are selectable
+ by userspace (rather that all sets being copied out for every exit).
+- vcpu_events are available in addition to regs and sregs.
+
+For x86, the 'kvm_valid_regs' field of struct kvm_run is overloaded to
+function as an input bit-array field set by userspace to indicate the
+specific register sets to be copied out on the next exit.
+
+To indicate when userspace has modified values that should be copied into
+the vCPU, the all architecture bitarray field, 'kvm_dirty_regs' must be set.
+This is done using the same bitflags as for the 'kvm_valid_regs' field.
+If the dirty bit is not set, then the register set values will not be copied
+into the vCPU even if they've been modified.
+
+Unused bitfields in the bitarrays must be set to zero.
+
+struct kvm_sync_regs {
+ struct kvm_regs regs;
+ struct kvm_sregs sregs;
+ struct kvm_vcpu_events events;
+};
+
7. Capabilities that can be enabled on VMs
------------------------------------------
@@ -4286,6 +4358,26 @@ enables QEMU to build error log and branch to guest kernel registered
machine check handling routine. Without this capability KVM will
branch to guests' 0x200 interrupt vector.
+7.13 KVM_CAP_X86_DISABLE_EXITS
+
+Architectures: x86
+Parameters: args[0] defines which exits are disabled
+Returns: 0 on success, -EINVAL when args[0] contains invalid exits
+
+Valid bits in args[0] are
+
+#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
+#define KVM_X86_DISABLE_EXITS_HLT (1 << 1)
+
+Enabling this capability on a VM provides userspace with a way to no
+longer intercept some instructions for improved latency in some
+workloads, and is suggested when vCPUs are associated to dedicated
+physical CPUs. More bits can be added in the future; userspace can
+just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable
+all such vmexits.
+
+Do not enable KVM_FEATURE_PV_UNHALT if you disable HLT exits.
+
8. Other capabilities.
----------------------
@@ -4398,15 +4490,6 @@ reserved.
Both registers and addresses are 64-bits wide.
It will be possible to run 64-bit or 32-bit guest code.
-8.8 KVM_CAP_X86_GUEST_MWAIT
-
-Architectures: x86
-
-This capability indicates that guest using memory monotoring instructions
-(MWAIT/MWAITX) to stop the virtual CPU will not cause a VM exit. As such time
-spent while virtual CPU is halted in this way will then be accounted for as
-guest running time on the host (as opposed to e.g. HLT).
-
8.9 KVM_CAP_ARM_USER_IRQ
Architectures: arm, arm64
@@ -4483,3 +4566,33 @@ Parameters: none
This capability indicates if the flic device will be able to get/set the
AIS states for migration via the KVM_DEV_FLIC_AISM_ALL attribute and allows
to discover this without having to create a flic device.
+
+8.14 KVM_CAP_S390_PSW
+
+Architectures: s390
+
+This capability indicates that the PSW is exposed via the kvm_run structure.
+
+8.15 KVM_CAP_S390_GMAP
+
+Architectures: s390
+
+This capability indicates that the user space memory used as guest mapping can
+be anywhere in the user memory address space, as long as the memory slots are
+aligned and sized to a segment (1MB) boundary.
+
+8.16 KVM_CAP_S390_COW
+
+Architectures: s390
+
+This capability indicates that the user space memory used as guest mapping can
+use copy-on-write semantics as well as dirty pages tracking via read-only page
+tables.
+
+8.17 KVM_CAP_S390_BPB
+
+Architectures: s390
+
+This capability indicates that kvm will implement the interfaces to handle
+reset, migration and nested KVM for branch prediction blocking. The stfle
+facility 82 should not be provided to the guest without this capability.
diff --git a/Documentation/virtual/kvm/cpuid.txt b/Documentation/virtual/kvm/cpuid.txt
index 87a7506f31c2..d4f33eb805dd 100644
--- a/Documentation/virtual/kvm/cpuid.txt
+++ b/Documentation/virtual/kvm/cpuid.txt
@@ -23,8 +23,8 @@ This function queries the presence of KVM cpuid leafs.
function: define KVM_CPUID_FEATURES (0x40000001)
-returns : ebx, ecx, edx = 0
- eax = and OR'ed group of (1 << flag), where each flags is:
+returns : ebx, ecx
+ eax = an OR'ed group of (1 << flag), where each flags is:
flag || value || meaning
@@ -66,3 +66,14 @@ KVM_FEATURE_CLOCKSOURCE_STABLE_BIT || 24 || host will warn if no guest-side
|| || per-cpu warps are expected in
|| || kvmclock.
------------------------------------------------------------------------------
+
+ edx = an OR'ed group of (1 << flag), where each flags is:
+
+
+flag || value || meaning
+==================================================================================
+KVM_HINTS_DEDICATED || 0 || guest checks this feature bit to
+ || || determine if there is vCPU pinning
+ || || and there is no vCPU over-commitment,
+ || || allowing optimizations
+----------------------------------------------------------------------------------
diff --git a/Documentation/vm/00-INDEX b/Documentation/vm/00-INDEX
index 11d3d8dcb449..0278f2c85efb 100644
--- a/Documentation/vm/00-INDEX
+++ b/Documentation/vm/00-INDEX
@@ -10,6 +10,8 @@ frontswap.txt
- Outline frontswap, part of the transcendent memory frontend.
highmem.txt
- Outline of highmem and common issues.
+hmm.txt
+ - Documentation of heterogeneous memory management
hugetlbpage.txt
- a brief summary of hugetlbpage support in the Linux kernel.
hugetlbfs_reserv.txt
@@ -20,25 +22,41 @@ idle_page_tracking.txt
- description of the idle page tracking feature.
ksm.txt
- how to use the Kernel Samepage Merging feature.
+mmu_notifier.txt
+ - a note about clearing pte/pmd and mmu notifications
numa
- information about NUMA specific code in the Linux vm.
numa_memory_policy.txt
- documentation of concepts and APIs of the 2.6 memory policy support.
overcommit-accounting
- description of the Linux kernels overcommit handling modes.
+page_frags
+ - description of page fragments allocator
page_migration
- description of page migration in NUMA systems.
pagemap.txt
- pagemap, from the userspace perspective
+page_owner.txt
+ - tracking about who allocated each page
+remap_file_pages.txt
+ - a note about remap_file_pages() system call
slub.txt
- a short users guide for SLUB.
soft-dirty.txt
- short explanation for soft-dirty PTEs
split_page_table_lock
- Separate per-table lock to improve scalability of the old page_table_lock.
+swap_numa.txt
+ - automatic binding of swap device to numa node
transhuge.txt
- Transparent Hugepage Support, alternative way of using hugepages.
unevictable-lru.txt
- Unevictable LRU infrastructure
+userfaultfd.txt
+ - description of userfaultfd system call
+z3fold.txt
+ - outline of z3fold allocator for storing compressed pages
+zsmalloc.txt
+ - outline of zsmalloc allocator for storing compressed pages
zswap.txt
- Intro to compressed cache for swap pages
diff --git a/Documentation/vm/hmm.txt b/Documentation/vm/hmm.txt
index 4d3aac9f4a5d..2d1d6f69e91b 100644
--- a/Documentation/vm/hmm.txt
+++ b/Documentation/vm/hmm.txt
@@ -1,152 +1,160 @@
Heterogeneous Memory Management (HMM)
-Transparently allow any component of a program to use any memory region of said
-program with a device without using device specific memory allocator. This is
-becoming a requirement to simplify the use of advance heterogeneous computing
-where GPU, DSP or FPGA are use to perform various computations.
-
-This document is divided as follow, in the first section i expose the problems
-related to the use of a device specific allocator. The second section i expose
-the hardware limitations that are inherent to many platforms. The third section
-gives an overview of HMM designs. The fourth section explains how CPU page-
-table mirroring works and what is HMM purpose in this context. Fifth section
-deals with how device memory is represented inside the kernel. Finaly the last
-section present the new migration helper that allow to leverage the device DMA
-engine.
-
-
-1) Problems of using device specific memory allocator:
-2) System bus, device memory characteristics
-3) Share address space and migration
+Provide infrastructure and helpers to integrate non-conventional memory (device
+memory like GPU on board memory) into regular kernel path, with the cornerstone
+of this being specialized struct page for such memory (see sections 5 to 7 of
+this document).
+
+HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
+allowing a device to transparently access program address coherently with the
+CPU meaning that any valid pointer on the CPU is also a valid pointer for the
+device. This is becoming mandatory to simplify the use of advanced hetero-
+geneous computing where GPU, DSP, or FPGA are used to perform various
+computations on behalf of a process.
+
+This document is divided as follows: in the first section I expose the problems
+related to using device specific memory allocators. In the second section, I
+expose the hardware limitations that are inherent to many platforms. The third
+section gives an overview of the HMM design. The fourth section explains how
+CPU page-table mirroring works and the purpose of HMM in this context. The
+fifth section deals with how device memory is represented inside the kernel.
+Finally, the last section presents a new migration helper that allows lever-
+aging the device DMA engine.
+
+
+1) Problems of using a device specific memory allocator:
+2) I/O bus, device memory characteristics
+3) Shared address space and migration
4) Address space mirroring implementation and API
5) Represent and manage device memory from core kernel point of view
-6) Migrate to and from device memory
+6) Migration to and from device memory
7) Memory cgroup (memcg) and rss accounting
-------------------------------------------------------------------------------
-1) Problems of using device specific memory allocator:
-
-Device with large amount of on board memory (several giga bytes) like GPU have
-historically manage their memory through dedicated driver specific API. This
-creates a disconnect between memory allocated and managed by device driver and
-regular application memory (private anonymous, share memory or regular file
-back memory). From here on i will refer to this aspect as split address space.
-I use share address space to refer to the opposite situation ie one in which
-any memory region can be use by device transparently.
-
-Split address space because device can only access memory allocated through the
-device specific API. This imply that all memory object in a program are not
-equal from device point of view which complicate large program that rely on a
-wide set of libraries.
-
-Concretly this means that code that wants to leverage device like GPU need to
-copy object between genericly allocated memory (malloc, mmap private/share/)
-and memory allocated through the device driver API (this still end up with an
-mmap but of the device file).
-
-For flat dataset (array, grid, image, ...) this isn't too hard to achieve but
-complex data-set (list, tree, ...) are hard to get right. Duplicating a complex
-data-set need to re-map all the pointer relations between each of its elements.
-This is error prone and program gets harder to debug because of the duplicate
-data-set.
-
-Split address space also means that library can not transparently use data they
-are getting from core program or other library and thus each library might have
-to duplicate its input data-set using specific memory allocator. Large project
-suffer from this and waste resources because of the various memory copy.
-
-Duplicating each library API to accept as input or output memory allocted by
+1) Problems of using a device specific memory allocator:
+
+Devices with a large amount of on board memory (several gigabytes) like GPUs
+have historically managed their memory through dedicated driver specific APIs.
+This creates a disconnect between memory allocated and managed by a device
+driver and regular application memory (private anonymous, shared memory, or
+regular file backed memory). From here on I will refer to this aspect as split
+address space. I use shared address space to refer to the opposite situation:
+i.e., one in which any application memory region can be used by a device
+transparently.
+
+Split address space happens because device can only access memory allocated
+through device specific API. This implies that all memory objects in a program
+are not equal from the device point of view which complicates large programs
+that rely on a wide set of libraries.
+
+Concretely this means that code that wants to leverage devices like GPUs needs
+to copy object between generically allocated memory (malloc, mmap private, mmap
+share) and memory allocated through the device driver API (this still ends up
+with an mmap but of the device file).
+
+For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
+complex data sets (list, tree, ...) are hard to get right. Duplicating a
+complex data set needs to re-map all the pointer relations between each of its
+elements. This is error prone and program gets harder to debug because of the
+duplicate data set and addresses.
+
+Split address space also means that libraries cannot transparently use data
+they are getting from the core program or another library and thus each library
+might have to duplicate its input data set using the device specific memory
+allocator. Large projects suffer from this and waste resources because of the
+various memory copies.
+
+Duplicating each library API to accept as input or output memory allocated by
each device specific allocator is not a viable option. It would lead to a
-combinatorial explosions in the library entry points.
+combinatorial explosion in the library entry points.
-Finaly with the advance of high level language constructs (in C++ but in other
-language too) it is now possible for compiler to leverage GPU or other devices
-without even the programmer knowledge. Some of compiler identified patterns are
-only do-able with a share address. It is as well more reasonable to use a share
-address space for all the other patterns.
+Finally, with the advance of high level language constructs (in C++ but in
+other languages too) it is now possible for the compiler to leverage GPUs and
+other devices without programmer knowledge. Some compiler identified patterns
+are only do-able with a shared address space. It is also more reasonable to use
+a shared address space for all other patterns.
-------------------------------------------------------------------------------
-2) System bus, device memory characteristics
+2) I/O bus, device memory characteristics
-System bus cripple share address due to few limitations. Most system bus only
-allow basic memory access from device to main memory, even cache coherency is
-often optional. Access to device memory from CPU is even more limited, most
-often than not it is not cache coherent.
+I/O buses cripple shared address spaces due to a few limitations. Most I/O
+buses only allow basic memory access from device to main memory; even cache
+coherency is often optional. Access to device memory from CPU is even more
+limited. More often than not, it is not cache coherent.
-If we only consider the PCIE bus than device can access main memory (often
-through an IOMMU) and be cache coherent with the CPUs. However it only allows
-a limited set of atomic operation from device on main memory. This is worse
-in the other direction the CPUs can only access a limited range of the device
-memory and can not perform atomic operations on it. Thus device memory can not
-be consider like regular memory from kernel point of view.
+If we only consider the PCIE bus, then a device can access main memory (often
+through an IOMMU) and be cache coherent with the CPUs. However, it only allows
+a limited set of atomic operations from device on main memory. This is worse
+in the other direction: the CPU can only access a limited range of the device
+memory and cannot perform atomic operations on it. Thus device memory cannot
+be considered the same as regular memory from the kernel point of view.
Another crippling factor is the limited bandwidth (~32GBytes/s with PCIE 4.0
-and 16 lanes). This is 33 times less that fastest GPU memory (1 TBytes/s).
-The final limitation is latency, access to main memory from the device has an
-order of magnitude higher latency than when the device access its own memory.
+and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
+The final limitation is latency. Access to main memory from the device has an
+order of magnitude higher latency than when the device accesses its own memory.
-Some platform are developing new system bus or additions/modifications to PCIE
-to address some of those limitations (OpenCAPI, CCIX). They mainly allow two
+Some platforms are developing new I/O buses or additions/modifications to PCIE
+to address some of these limitations (OpenCAPI, CCIX). They mainly allow two-
way cache coherency between CPU and device and allow all atomic operations the
-architecture supports. Saddly not all platform are following this trends and
-some major architecture are left without hardware solutions to those problems.
+architecture supports. Sadly, not all platforms are following this trend and
+some major architectures are left without hardware solutions to these problems.
-So for share address space to make sense not only we must allow device to
-access any memory memory but we must also permit any memory to be migrated to
-device memory while device is using it (blocking CPU access while it happens).
+So for shared address space to make sense, not only must we allow devices to
+access any memory but we must also permit any memory to be migrated to device
+memory while device is using it (blocking CPU access while it happens).
-------------------------------------------------------------------------------
-3) Share address space and migration
+3) Shared address space and migration
HMM intends to provide two main features. First one is to share the address
-space by duplication the CPU page table into the device page table so same
-address point to same memory and this for any valid main memory address in
+space by duplicating the CPU page table in the device page table so the same
+address points to the same physical memory for any valid main memory address in
the process address space.
-To achieve this, HMM offer a set of helpers to populate the device page table
+To achieve this, HMM offers a set of helpers to populate the device page table
while keeping track of CPU page table updates. Device page table updates are
-not as easy as CPU page table updates. To update the device page table you must
-allow a buffer (or use a pool of pre-allocated buffer) and write GPU specifics
-commands in it to perform the update (unmap, cache invalidations and flush,
-...). This can not be done through common code for all device. Hence why HMM
-provides helpers to factor out everything that can be while leaving the gory
-details to the device driver.
-
-The second mechanism HMM provide is a new kind of ZONE_DEVICE memory that does
-allow to allocate a struct page for each page of the device memory. Those page
-are special because the CPU can not map them. They however allow to migrate
-main memory to device memory using exhisting migration mechanism and everything
-looks like if page was swap out to disk from CPU point of view. Using a struct
-page gives the easiest and cleanest integration with existing mm mechanisms.
-Again here HMM only provide helpers, first to hotplug new ZONE_DEVICE memory
-for the device memory and second to perform migration. Policy decision of what
-and when to migrate things is left to the device driver.
-
-Note that any CPU access to a device page trigger a page fault and a migration
-back to main memory ie when a page backing an given address A is migrated from
-a main memory page to a device page then any CPU access to address A trigger a
-page fault and initiate a migration back to main memory.
-
-
-With this two features, HMM not only allow a device to mirror a process address
-space and keeps both CPU and device page table synchronize, but also allow to
-leverage device memory by migrating part of data-set that is actively use by a
-device.
+not as easy as CPU page table updates. To update the device page table, you must
+allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
+specific commands in it to perform the update (unmap, cache invalidations, and
+flush, ...). This cannot be done through common code for all devices. Hence
+why HMM provides helpers to factor out everything that can be while leaving the
+hardware specific details to the device driver.
+
+The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
+allows allocating a struct page for each page of the device memory. Those pages
+are special because the CPU cannot map them. However, they allow migrating
+main memory to device memory using existing migration mechanisms and everything
+looks like a page is swapped out to disk from the CPU point of view. Using a
+struct page gives the easiest and cleanest integration with existing mm mech-
+anisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
+memory for the device memory and second to perform migration. Policy decisions
+of what and when to migrate things is left to the device driver.
+
+Note that any CPU access to a device page triggers a page fault and a migration
+back to main memory. For example, when a page backing a given CPU address A is
+migrated from a main memory page to a device page, then any CPU access to
+address A triggers a page fault and initiates a migration back to main memory.
+
+With these two features, HMM not only allows a device to mirror process address
+space and keeping both CPU and device page table synchronized, but also lever-
+ages device memory by migrating the part of the data set that is actively being
+used by the device.
-------------------------------------------------------------------------------
4) Address space mirroring implementation and API
-Address space mirroring main objective is to allow to duplicate range of CPU
-page table into a device page table and HMM helps keeping both synchronize. A
-device driver that want to mirror a process address space must start with the
+Address space mirroring's main objective is to allow duplication of a range of
+CPU page table into a device page table; HMM helps keep both synchronized. A
+device driver that wants to mirror a process address space must start with the
registration of an hmm_mirror struct:
int hmm_mirror_register(struct hmm_mirror *mirror,
@@ -154,9 +162,9 @@ registration of an hmm_mirror struct:
int hmm_mirror_register_locked(struct hmm_mirror *mirror,
struct mm_struct *mm);
-The locked variant is to be use when the driver is already holding the mmap_sem
-of the mm in write mode. The mirror struct has a set of callback that are use
-to propagate CPU page table:
+The locked variant is to be used when the driver is already holding mmap_sem
+of the mm in write mode. The mirror struct has a set of callbacks that are used
+to propagate CPU page tables:
struct hmm_mirror_ops {
/* sync_cpu_device_pagetables() - synchronize page tables
@@ -181,13 +189,13 @@ to propagate CPU page table:
unsigned long end);
};
-Device driver must perform update to the range following action (turn range
-read only, or fully unmap, ...). Once driver callback returns the device must
-be done with the update.
+The device driver must perform the update action to the range (mark range
+read only, or fully unmap, ...). The device must be done with the update before
+the driver callback returns.
-When device driver wants to populate a range of virtual address it can use
-either:
+When the device driver wants to populate a range of virtual addresses, it can
+use either:
int hmm_vma_get_pfns(struct vm_area_struct *vma,
struct hmm_range *range,
unsigned long start,
@@ -201,17 +209,19 @@ either:
bool write,
bool block);
-First one (hmm_vma_get_pfns()) will only fetch present CPU page table entry and
-will not trigger a page fault on missing or non present entry. The second one
-do trigger page fault on missing or read only entry if write parameter is true.
-Page fault use the generic mm page fault code path just like a CPU page fault.
+The first one (hmm_vma_get_pfns()) will only fetch present CPU page table
+entries and will not trigger a page fault on missing or non-present entries.
+The second one does trigger a page fault on missing or read-only entry if the
+write parameter is true. Page faults use the generic mm page fault code path
+just like a CPU page fault.
-Both function copy CPU page table into their pfns array argument. Each entry in
-that array correspond to an address in the virtual range. HMM provide a set of
-flags to help driver identify special CPU page table entries.
+Both functions copy CPU page table entries into their pfns array argument. Each
+entry in that array corresponds to an address in the virtual range. HMM
+provides a set of flags to help the driver identify special CPU page table
+entries.
Locking with the update() callback is the most important aspect the driver must
-respect in order to keep things properly synchronize. The usage pattern is :
+respect in order to keep things properly synchronized. The usage pattern is:
int driver_populate_range(...)
{
@@ -233,43 +243,44 @@ respect in order to keep things properly synchronize. The usage pattern is :
return 0;
}
-The driver->update lock is the same lock that driver takes inside its update()
-callback. That lock must be call before hmm_vma_range_done() to avoid any race
-with a concurrent CPU page table update.
+The driver->update lock is the same lock that the driver takes inside its
+update() callback. That lock must be held before hmm_vma_range_done() to avoid
+any race with a concurrent CPU page table update.
-HMM implements all this on top of the mmu_notifier API because we wanted to a
-simpler API and also to be able to perform optimization latter own like doing
-concurrent device update in multi-devices scenario.
+HMM implements all this on top of the mmu_notifier API because we wanted a
+simpler API and also to be able to perform optimizations latter on like doing
+concurrent device updates in multi-devices scenario.
-HMM also serve as an impedence missmatch between how CPU page table update are
-done (by CPU write to the page table and TLB flushes) from how device update
-their own page table. Device update is a multi-step process, first appropriate
-commands are write to a buffer, then this buffer is schedule for execution on
-the device. It is only once the device has executed commands in the buffer that
-the update is done. Creating and scheduling update command buffer can happen
-concurrently for multiple devices. Waiting for each device to report commands
-as executed is serialize (there is no point in doing this concurrently).
+HMM also serves as an impedance mismatch between how CPU page table updates
+are done (by CPU write to the page table and TLB flushes) and how devices
+update their own page table. Device updates are a multi-step process. First,
+appropriate commands are written to a buffer, then this buffer is scheduled for
+execution on the device. It is only once the device has executed commands in
+the buffer that the update is done. Creating and scheduling the update command
+buffer can happen concurrently for multiple devices. Waiting for each device to
+report commands as executed is serialized (there is no point in doing this
+concurrently).
-------------------------------------------------------------------------------
5) Represent and manage device memory from core kernel point of view
-Several differents design were try to support device memory. First one use
-device specific data structure to keep information about migrated memory and
-HMM hooked itself in various place of mm code to handle any access to address
-that were back by device memory. It turns out that this ended up replicating
-most of the fields of struct page and also needed many kernel code path to be
-updated to understand this new kind of memory.
+Several different designs were tried to support device memory. First one used
+a device specific data structure to keep information about migrated memory and
+HMM hooked itself in various places of mm code to handle any access to
+addresses that were backed by device memory. It turns out that this ended up
+replicating most of the fields of struct page and also needed many kernel code
+paths to be updated to understand this new kind of memory.
-Thing is most kernel code path never try to access the memory behind a page
-but only care about struct page contents. Because of this HMM switchted to
-directly using struct page for device memory which left most kernel code path
-un-aware of the difference. We only need to make sure that no one ever try to
-map those page from the CPU side.
+Most kernel code paths never try to access the memory behind a page
+but only care about struct page contents. Because of this, HMM switched to
+directly using struct page for device memory which left most kernel code paths
+unaware of the difference. We only need to make sure that no one ever tries to
+map those pages from the CPU side.
-HMM provide a set of helpers to register and hotplug device memory as a new
-region needing struct page. This is offer through a very simple API:
+HMM provides a set of helpers to register and hotplug device memory as a new
+region needing a struct page. This is offered through a very simple API:
struct hmm_devmem *hmm_devmem_add(const struct hmm_devmem_ops *ops,
struct device *device,
@@ -289,18 +300,19 @@ The hmm_devmem_ops is where most of the important things are:
};
The first callback (free()) happens when the last reference on a device page is
-drop. This means the device page is now free and no longer use by anyone. The
-second callback happens whenever CPU try to access a device page which it can
-not do. This second callback must trigger a migration back to system memory.
+dropped. This means the device page is now free and no longer used by anyone.
+The second callback happens whenever the CPU tries to access a device page
+which it cannot do. This second callback must trigger a migration back to
+system memory.
-------------------------------------------------------------------------------
-6) Migrate to and from device memory
+6) Migration to and from device memory
-Because CPU can not access device memory, migration must use device DMA engine
-to perform copy from and to device memory. For this we need a new migration
-helper:
+Because the CPU cannot access device memory, migration must use the device DMA
+engine to perform copy from and to device memory. For this we need a new
+migration helper:
int migrate_vma(const struct migrate_vma_ops *ops,
struct vm_area_struct *vma,
@@ -311,15 +323,15 @@ helper:
unsigned long *dst,
void *private);
-Unlike other migration function it works on a range of virtual address, there
-is two reasons for that. First device DMA copy has a high setup overhead cost
+Unlike other migration functions it works on a range of virtual address, there
+are two reasons for that. First, device DMA copy has a high setup overhead cost
and thus batching multiple pages is needed as otherwise the migration overhead
-make the whole excersie pointless. The second reason is because driver trigger
-such migration base on range of address the device is actively accessing.
+makes the whole exercise pointless. The second reason is because the
+migration might be for a range of addresses the device is actively accessing.
-The migrate_vma_ops struct define two callbacks. First one (alloc_and_copy())
-control destination memory allocation and copy operation. Second one is there
-to allow device driver to perform cleanup operation after migration.
+The migrate_vma_ops struct defines two callbacks. First one (alloc_and_copy())
+controls destination memory allocation and copy operation. Second one is there
+to allow the device driver to perform cleanup operations after migration.
struct migrate_vma_ops {
void (*alloc_and_copy)(struct vm_area_struct *vma,
@@ -336,19 +348,19 @@ to allow device driver to perform cleanup operation after migration.
void *private);
};
-It is important to stress that this migration helpers allow for hole in the
+It is important to stress that these migration helpers allow for holes in the
virtual address range. Some pages in the range might not be migrated for all
-the usual reasons (page is pin, page is lock, ...). This helper does not fail
-but just skip over those pages.
+the usual reasons (page is pinned, page is locked, ...). This helper does not
+fail but just skips over those pages.
-The alloc_and_copy() might as well decide to not migrate all pages in the
-range (for reasons under the callback control). For those the callback just
-have to leave the corresponding dst entry empty.
+The alloc_and_copy() might decide to not migrate all pages in the
+range (for reasons under the callback control). For those, the callback just
+has to leave the corresponding dst entry empty.
-Finaly the migration of the struct page might fails (for file back page) for
+Finally, the migration of the struct page might fail (for file backed page) for
various reasons (failure to freeze reference, or update page cache, ...). If
-that happens then the finalize_and_map() can catch any pages that was not
-migrated. Note those page were still copied to new page and thus we wasted
+that happens, then the finalize_and_map() can catch any pages that were not
+migrated. Note those pages were still copied to a new page and thus we wasted
bandwidth but this is considered as a rare event and a price that we are
willing to pay to keep all the code simpler.
@@ -358,27 +370,27 @@ willing to pay to keep all the code simpler.
7) Memory cgroup (memcg) and rss accounting
For now device memory is accounted as any regular page in rss counters (either
-anonymous if device page is use for anonymous, file if device page is use for
-file back page or shmem if device page is use for share memory). This is a
-deliberate choice to keep existing application that might start using device
-memory without knowing about it to keep runing unimpacted.
-
-Drawbacks is that OOM killer might kill an application using a lot of device
-memory and not a lot of regular system memory and thus not freeing much system
-memory. We want to gather more real world experience on how application and
-system react under memory pressure in the presence of device memory before
+anonymous if device page is used for anonymous, file if device page is used for
+file backed page or shmem if device page is used for shared memory). This is a
+deliberate choice to keep existing applications, that might start using device
+memory without knowing about it, running unimpacted.
+
+A drawback is that the OOM killer might kill an application using a lot of
+device memory and not a lot of regular system memory and thus not freeing much
+system memory. We want to gather more real world experience on how applications
+and system react under memory pressure in the presence of device memory before
deciding to account device memory differently.
-Same decision was made for memory cgroup. Device memory page are accounted
+Same decision was made for memory cgroup. Device memory pages are accounted
against same memory cgroup a regular page would be accounted to. This does
simplify migration to and from device memory. This also means that migration
-back from device memory to regular memory can not fail because it would
+back from device memory to regular memory cannot fail because it would
go above memory cgroup limit. We might revisit this choice latter on once we
-get more experience in how device memory is use and its impact on memory
+get more experience in how device memory is used and its impact on memory
resource control.
-Note that device memory can never be pin nor by device driver nor through GUP
+Note that device memory can never be pinned by device driver nor through GUP
and thus such memory is always free upon process exit. Or when last reference
-is drop in case of share memory or file back memory.
+is dropped in case of shared memory or file backed memory.
diff --git a/Documentation/vm/page_migration b/Documentation/vm/page_migration
index 0478ae2ad44a..496868072e24 100644
--- a/Documentation/vm/page_migration
+++ b/Documentation/vm/page_migration
@@ -90,7 +90,7 @@ Steps:
1. Lock the page to be migrated
-2. Insure that writeback is complete.
+2. Ensure that writeback is complete.
3. Lock the new page that we want to move to. It is locked so that accesses to
this (not yet uptodate) page immediately lock while the move is in progress.
@@ -100,8 +100,8 @@ Steps:
mapcount is not zero then we do not migrate the page. All user space
processes that attempt to access the page will now wait on the page lock.
-5. The radix tree lock is taken. This will cause all processes trying
- to access the page via the mapping to block on the radix tree spinlock.
+5. The i_pages lock is taken. This will cause all processes trying
+ to access the page via the mapping to block on the spinlock.
6. The refcount of the page is examined and we back out if references remain
otherwise we know that we are the only one referencing this page.
@@ -114,12 +114,12 @@ Steps:
9. The radix tree is changed to point to the new page.
-10. The reference count of the old page is dropped because the radix tree
+10. The reference count of the old page is dropped because the address space
reference is gone. A reference to the new page is established because
- the new page is referenced to by the radix tree.
+ the new page is referenced by the address space.
-11. The radix tree lock is dropped. With that lookups in the mapping
- become possible again. Processes will move from spinning on the tree_lock
+11. The i_pages lock is dropped. With that lookups in the mapping
+ become possible again. Processes will move from spinning on the lock
to sleeping on the locked new page.
12. The page contents are copied to the new page.
diff --git a/Documentation/watchdog/watchdog-parameters.txt b/Documentation/watchdog/watchdog-parameters.txt
index beea975980f6..6d6200ea27b8 100644
--- a/Documentation/watchdog/watchdog-parameters.txt
+++ b/Documentation/watchdog/watchdog-parameters.txt
@@ -55,11 +55,6 @@ wdt_time: Watchdog time in seconds. (default=30)
nowayout: Watchdog cannot be stopped once started
(default=kernel config parameter)
-------------------------------------------------
-bfin_wdt:
-timeout: Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=20)
-nowayout: Watchdog cannot be stopped once started
- (default=kernel config parameter)
--------------------------------------------------
coh901327_wdt:
margin: Watchdog margin in seconds (default 60s)
-------------------------------------------------
diff --git a/Documentation/x86/00-INDEX b/Documentation/x86/00-INDEX
index 692264456f0f..3bb2ee3edcd1 100644
--- a/Documentation/x86/00-INDEX
+++ b/Documentation/x86/00-INDEX
@@ -2,14 +2,14 @@
- this file
boot.txt
- List of boot protocol versions
-early-microcode.txt
- - How to load microcode from an initrd-CPIO archive early to fix CPU issues.
earlyprintk.txt
- Using earlyprintk with a USB2 debug port key.
entry_64.txt
- Describe (some of the) kernel entry points for x86.
exception-tables.txt
- why and how Linux kernel uses exception tables on x86
+microcode.txt
+ - How to load microcode from an initrd-CPIO archive early to fix CPU issues.
mtrr.txt
- how to use x86 Memory Type Range Registers to increase performance
pat.txt
diff --git a/Documentation/x86/x86_64/5level-paging.txt b/Documentation/x86/x86_64/5level-paging.txt
index 087251a0d99c..2432a5ef86d9 100644
--- a/Documentation/x86/x86_64/5level-paging.txt
+++ b/Documentation/x86/x86_64/5level-paging.txt
@@ -20,12 +20,9 @@ Documentation/x86/x86_64/mm.txt
CONFIG_X86_5LEVEL=y enables the feature.
-So far, a kernel compiled with the option enabled will be able to boot
-only on machines that supports the feature -- see for 'la57' flag in
-/proc/cpuinfo.
-
-The plan is to implement boot-time switching between 4- and 5-level paging
-in the future.
+Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
+In this case additional page table level -- p4d -- will be folded at
+runtime.
== User-space and large virtual address space ==
diff --git a/Documentation/x86/x86_64/mm.txt b/Documentation/x86/x86_64/mm.txt
index ea91cb61a602..5432a96d31ff 100644
--- a/Documentation/x86/x86_64/mm.txt
+++ b/Documentation/x86/x86_64/mm.txt
@@ -20,7 +20,7 @@ ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks
ffffffef00000000 - fffffffeffffffff (=64 GB) EFI region mapping space
... unused hole ...
ffffffff80000000 - ffffffff9fffffff (=512 MB) kernel text mapping, from phys 0
-ffffffffa0000000 - [fixmap start] (~1526 MB) module mapping space (variable)
+ffffffffa0000000 - fffffffffeffffff (1520 MB) module mapping space
[fixmap start] - ffffffffff5fffff kernel-internal fixmap range
ffffffffff600000 - ffffffffff600fff (=4 kB) legacy vsyscall ABI
ffffffffffe00000 - ffffffffffffffff (=2 MB) unused hole
diff --git a/MAINTAINERS b/MAINTAINERS
index 2b62e6cf6b1c..eaee45919cb9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -766,6 +766,8 @@ F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
F: drivers/gpu/drm/amd/amdkfd/
F: drivers/gpu/drm/amd/include/cik_structs.h
F: drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -859,7 +861,17 @@ F: drivers/iio/*/ad*
F: drivers/iio/adc/ltc2497*
X: drivers/iio/*/adjd*
F: drivers/staging/iio/*/ad*
-F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c
+
+ANDES ARCHITECTURE
+M: Greentime Hu <green.hu@gmail.com>
+M: Vincent Chen <deanbo422@gmail.com>
+T: git https://github.com/andestech/linux.git
+S: Supported
+F: arch/nds32/
+F: Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
+F: Documentation/devicetree/bindings/nds32/
+K: nds32
+N: nds32
ANDROID CONFIG FRAGMENTS
M: Rob Herring <robh@kernel.org>
@@ -922,8 +934,8 @@ F: drivers/char/apm-emulation.c
APPARMOR SECURITY MODULE
M: John Johansen <john.johansen@canonical.com>
L: apparmor@lists.ubuntu.com (subscribers-only, general discussion)
-W: apparmor.wiki.kernel.org
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jj/apparmor-dev.git
+W: wiki.apparmor.net
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor
S: Supported
F: security/apparmor/
F: Documentation/admin-guide/LSM/apparmor.rst
@@ -1053,41 +1065,42 @@ ARM PORT
M: Russell King <linux@armlinux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.armlinux.org.uk/
-S: Maintained
+S: Odd Fixes
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git
F: arch/arm/
+X: arch/arm/boot/dts/
ARM PRIMECELL AACI PL041 DRIVER
M: Russell King <linux@armlinux.org.uk>
-S: Maintained
+S: Odd Fixes
F: sound/arm/aaci.*
ARM PRIMECELL BUS SUPPORT
M: Russell King <linux@armlinux.org.uk>
-S: Maintained
+S: Odd Fixes
F: drivers/amba/
F: include/linux/amba/bus.h
ARM PRIMECELL CLCD PL110 DRIVER
M: Russell King <linux@armlinux.org.uk>
-S: Maintained
+S: Odd Fixes
F: drivers/video/fbdev/amba-clcd.*
ARM PRIMECELL KMI PL050 DRIVER
M: Russell King <linux@armlinux.org.uk>
-S: Maintained
+S: Odd Fixes
F: drivers/input/serio/ambakmi.*
F: include/linux/amba/kmi.h
ARM PRIMECELL MMCI PL180/1 DRIVER
M: Russell King <linux@armlinux.org.uk>
-S: Maintained
+S: Odd Fixes
F: drivers/mmc/host/mmci.*
F: include/linux/amba/mmci.h
ARM PRIMECELL UART PL010 AND PL011 DRIVERS
M: Russell King <linux@armlinux.org.uk>
-S: Maintained
+S: Odd Fixes
F: drivers/tty/serial/amba-pl01*.c
F: include/linux/amba/serial.h
@@ -1145,7 +1158,7 @@ S: Maintained
F: drivers/clk/sunxi/
ARM/Allwinner sunXi SoC support
-M: Maxime Ripard <maxime.ripard@free-electrons.com>
+M: Maxime Ripard <maxime.ripard@bootlin.com>
M: Chen-Yu Tsai <wens@csie.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
@@ -1219,37 +1232,21 @@ F: Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
ARM/ASPEED MACHINE SUPPORT
M: Joel Stanley <joel@jms.id.au>
-S: Maintained
+R: Andrew Jeffery <andrew@aj.id.au>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+Q: https://patchwork.ozlabs.org/project/linux-aspeed/list/
+S: Supported
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git
F: arch/arm/mach-aspeed/
F: arch/arm/boot/dts/aspeed-*
-F: drivers/*/*aspeed*
+N: aspeed
ARM/ATMEL AT91 Clock Support
-M: Boris Brezillon <boris.brezillon@free-electrons.com>
+M: Boris Brezillon <boris.brezillon@bootlin.com>
S: Maintained
F: drivers/clk/at91
-ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
-M: Nicolas Ferre <nicolas.ferre@microchip.com>
-M: Alexandre Belloni <alexandre.belloni@bootlin.com>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W: http://www.linux4sam.org
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
-S: Supported
-N: at91
-N: atmel
-F: arch/arm/mach-at91/
-F: include/soc/at91/
-F: arch/arm/boot/dts/at91*.dts
-F: arch/arm/boot/dts/at91*.dtsi
-F: arch/arm/boot/dts/sama*.dts
-F: arch/arm/boot/dts/sama*.dtsi
-F: arch/arm/include/debug/at91.S
-F: drivers/memory/atmel*
-F: drivers/watchdog/sama5d4_wdt.c
-X: drivers/input/touchscreen/atmel_mxt_ts.c
-X: drivers/net/wireless/atmel/
-
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <robh@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1570,15 +1567,6 @@ ARM/MAGICIAN MACHINE SUPPORT
M: Philipp Zabel <philipp.zabel@gmail.com>
S: Maintained
-ARM/Marvell Berlin SoC support
-M: Jisheng Zhang <jszhang@marvell.com>
-M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-F: arch/arm/mach-berlin/
-F: arch/arm/boot/dts/berlin*
-F: arch/arm64/boot/dts/marvell/berlin*
-
ARM/Marvell Dove/MV78xx0/Orion SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>
@@ -1649,6 +1637,27 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
F: arch/arm/mach-ks8695/
S: Odd Fixes
+ARM/Microchip (AT91) SoC support
+M: Nicolas Ferre <nicolas.ferre@microchip.com>
+M: Alexandre Belloni <alexandre.belloni@bootlin.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+W: http://www.linux4sam.org
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
+S: Supported
+N: at91
+N: atmel
+F: arch/arm/mach-at91/
+F: include/soc/at91/
+F: arch/arm/boot/dts/at91*.dts
+F: arch/arm/boot/dts/at91*.dtsi
+F: arch/arm/boot/dts/sama*.dts
+F: arch/arm/boot/dts/sama*.dtsi
+F: arch/arm/include/debug/at91.S
+F: drivers/memory/atmel*
+F: drivers/watchdog/sama5d4_wdt.c
+X: drivers/input/touchscreen/atmel_mxt_ts.c
+X: drivers/net/wireless/atmel/
+
ARM/MIOA701 MACHINE SUPPORT
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1693,6 +1702,20 @@ F: Documentation/devicetree/bindings/arm/ste-*
F: Documentation/devicetree/bindings/arm/ux500/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
+ARM/NUVOTON NPCM ARCHITECTURE
+M: Avi Fishman <avifishman70@gmail.com>
+M: Tomer Maimon <tmaimon77@gmail.com>
+R: Patrick Venture <venture@google.com>
+R: Nancy Yuen <yuenn@google.com>
+R: Brendan Higgins <brendanhiggins@google.com>
+L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
+S: Supported
+F: arch/arm/mach-npcm/
+F: arch/arm/boot/dts/nuvoton-npcm*
+F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F: drivers/*/*npcm*
+F: Documentation/*/*npcm*
+
ARM/NUVOTON W90X900 ARM ARCHITECTURE
M: Wan ZongShun <mcuos.com@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1703,7 +1726,7 @@ F: drivers/input/keyboard/w90p910_keypad.c
F: drivers/input/touchscreen/w90p910_ts.c
F: drivers/watchdog/nuc900_wdt.c
F: drivers/net/ethernet/nuvoton/w90p910_ether.c
-F: drivers/mtd/nand/nuc900_nand.c
+F: drivers/mtd/nand/raw/nuc900_nand.c
F: drivers/rtc/rtc-nuc900.c
F: drivers/spi/spi-nuc900.c
F: drivers/usb/host/ehci-w90x900.c
@@ -1725,7 +1748,7 @@ F: arch/arm/mach-orion5x/ts78xx-*
ARM/OXNAS platform support
M: Neil Armstrong <narmstrong@baylibre.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-L: linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers)
+L: linux-oxnas@groups.io (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-oxnas/
F: arch/arm/boot/dts/ox8*.dts*
@@ -1856,7 +1879,6 @@ Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
S: Maintained
F: arch/arm/boot/dts/s3c*
F: arch/arm/boot/dts/s5p*
-F: arch/arm/boot/dts/samsung*
F: arch/arm/boot/dts/exynos*
F: arch/arm64/boot/dts/exynos/
F: arch/arm/plat-samsung/
@@ -1956,6 +1978,14 @@ M: Thor Thayer <thor.thayer@linux.intel.com>
S: Maintained
F: drivers/edac/altera_edac.
+ARM/SPREADTRUM SoC SUPPORT
+M: Orson Zhai <orsonzhai@gmail.com>
+M: Baolin Wang <baolin.wang@linaro.org>
+M: Chunyan Zhang <zhang.lyra@gmail.com>
+S: Maintained
+F: arch/arm64/boot/dts/sprd
+N: sprd
+
ARM/STI ARCHITECTURE
M: Patrice Chotard <patrice.chotard@st.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1998,6 +2028,15 @@ F: arch/arm/boot/dts/stm32*
F: arch/arm/mach-stm32/
F: drivers/clocksource/armv7m_systick.c
+ARM/Synaptics Berlin SoC support
+M: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
+M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/mach-berlin/
+F: arch/arm/boot/dts/berlin*
+F: arch/arm64/boot/dts/marvell/berlin*
+
ARM/TANGO ARCHITECTURE
M: Marc Gonzalez <marc.w.gonzalez@free.fr>
M: Mans Rullgard <mans@mansr.com>
@@ -2387,7 +2426,6 @@ T: git git://github.com/ndyer/linux.git
S: Maintained
F: Documentation/devicetree/bindings/input/atmel,maxtouch.txt
F: drivers/input/touchscreen/atmel_mxt_ts.c
-F: include/linux/platform_data/atmel_mxt_ts.h
ATMEL SAMA5D2 ADC DRIVER
M: Ludovic Desroches <ludovic.desroches@microchip.com>
@@ -2470,7 +2508,6 @@ M: Paul Moore <paul@paul-moore.com>
M: Eric Paris <eparis@redhat.com>
L: linux-audit@redhat.com (moderated for non-subscribers)
W: https://github.com/linux-audit
-W: https://people.redhat.com/sgrubb/audit
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit.git
S: Supported
F: include/linux/audit.h
@@ -2622,51 +2659,6 @@ F: Documentation/filesystems/bfs.txt
F: fs/bfs/
F: include/uapi/linux/bfs_fs.h
-BLACKFIN ARCHITECTURE
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-T: git git://git.code.sf.net/p/adi-linux/code
-W: http://blackfin.uclinux.org
-S: Orphan
-F: arch/blackfin/
-
-BLACKFIN EMAC DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/net/ethernet/adi/
-
-BLACKFIN MEDIA DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org/
-S: Orphan
-F: drivers/media/platform/blackfin/
-F: drivers/media/i2c/adv7183*
-F: drivers/media/i2c/vs6624*
-
-BLACKFIN RTC DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/rtc/rtc-bfin.c
-
-BLACKFIN SDH DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/mmc/host/bfin_sdh.c
-
-BLACKFIN SERIAL DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/tty/serial/bfin_uart.c
-
-BLACKFIN WATCHDOG DRIVER
-L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/watchdog/bfin_wdt.c
-
BLINKM RGB LED DRIVER
M: Jan-Simon Moeller <jansimon.moeller@gmx.de>
S: Maintained
@@ -2678,6 +2670,7 @@ L: linux-block@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git
S: Maintained
F: block/
+F: drivers/block/
F: kernel/trace/blktrace.c
F: lib/sbitmap.c
@@ -3009,7 +3002,7 @@ M: Kamal Dasu <kdasu.kdev@gmail.com>
L: linux-mtd@lists.infradead.org
L: bcm-kernel-feedback-list@broadcom.com
S: Maintained
-F: drivers/mtd/nand/brcmnand/
+F: drivers/mtd/nand/raw/brcmnand/
BROADCOM STB DPFE DRIVER
M: Markus Mayer <mmayer@broadcom.com>
@@ -3277,12 +3270,11 @@ F: drivers/net/ieee802154/cc2520.c
F: include/linux/spi/cc2520.h
F: Documentation/devicetree/bindings/net/ieee802154/cc2520.txt
-CCREE ARM TRUSTZONE CRYPTOCELL 700 REE DRIVER
+CCREE ARM TRUSTZONE CRYPTOCELL REE DRIVER
M: Gilad Ben-Yossef <gilad@benyossef.com>
L: linux-crypto@vger.kernel.org
-L: driverdev-devel@linuxdriverproject.org
S: Supported
-F: drivers/staging/ccree/
+F: drivers/crypto/ccree/
W: https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
CEC FRAMEWORK
@@ -3300,6 +3292,7 @@ F: include/media/cec-notifier.h
F: include/uapi/linux/cec.h
F: include/uapi/linux/cec-funcs.h
F: Documentation/devicetree/bindings/media/cec.txt
+F: Documentation/ABI/testing/debugfs-cec-error-inj
CEC GPIO DRIVER
M: Hans Verkuil <hans.verkuil@cisco.com>
@@ -3742,16 +3735,6 @@ S: Maintained
F: Documentation/filesystems/cramfs.txt
F: fs/cramfs/
-CRIS PORT
-M: Mikael Starvik <starvik@axis.com>
-M: Jesper Nilsson <jesper.nilsson@axis.com>
-L: linux-cris-kernel@axis.com
-W: http://developer.axis.com
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris.git
-S: Maintained
-F: arch/cris/
-F: drivers/tty/serial/crisv10.*
-
CRYPTO API
M: Herbert Xu <herbert@gondor.apana.org.au>
M: "David S. Miller" <davem@davemloft.net>
@@ -4111,10 +4094,10 @@ DENALI NAND DRIVER
M: Masahiro Yamada <yamada.masahiro@socionext.com>
L: linux-mtd@lists.infradead.org
S: Supported
-F: drivers/mtd/nand/denali*
+F: drivers/mtd/nand/raw/denali*
DESIGNWARE USB2 DRD IP DRIVER
-M: John Youn <johnyoun@synopsys.com>
+M: Minas Harutyunyan <hminas@synopsys.com>
L: linux-usb@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
S: Maintained
@@ -4328,6 +4311,7 @@ Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
S: Maintained
F: drivers/dma/
F: include/linux/dmaengine.h
+F: include/linux/of_dma.h
F: Documentation/devicetree/bindings/dma/
F: Documentation/driver-api/dmaengine/
T: git git://git.infradead.org/users/vkoul/slave-dma.git
@@ -4405,8 +4389,14 @@ L: linux-kernel@vger.kernel.org
S: Maintained
F: drivers/staging/fsl-dpaa2/ethernet
+DPAA2 ETHERNET SWITCH DRIVER
+M: Razvan Stefanescu <razvan.stefanescu@nxp.com>
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: drivers/staging/fsl-dpaa2/ethsw
+
DPT_I2O SCSI RAID DRIVER
-M: Adaptec OEM Raid Solutions <aacraid@adaptec.com>
+M: Adaptec OEM Raid Solutions <aacraid@microsemi.com>
L: linux-scsi@vger.kernel.org
W: http://www.adaptec.com/
S: Maintained
@@ -4451,6 +4441,13 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
S: Supported
F: drivers/gpu/drm/pl111/
+DRM DRIVER FOR ARM VERSATILE TFT PANELS
+M: Linus Walleij <linus.walleij@linaro.org>
+T: git git://anongit.freedesktop.org/drm/drm-misc
+S: Maintained
+F: drivers/gpu/drm/panel/panel-arm-versatile.c
+F: Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt
+
DRM DRIVER FOR AST SERVER GRAPHICS CHIPS
M: Dave Airlie <airlied@redhat.com>
S: Odd Fixes
@@ -4605,8 +4602,8 @@ F: include/uapi/drm/
F: include/linux/vga*
DRM DRIVERS AND MISC GPU PATCHES
-M: Daniel Vetter <daniel.vetter@intel.com>
M: Gustavo Padovan <gustavo@padovan.org>
+M: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
M: Sean Paul <seanpaul@chromium.org>
W: https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html
S: Maintained
@@ -4619,7 +4616,7 @@ F: include/uapi/drm/drm*
F: include/linux/vga*
DRM DRIVERS FOR ALLWINNER A10
-M: Maxime Ripard <maxime.ripard@free-electrons.com>
+M: Maxime Ripard <maxime.ripard@bootlin.com>
L: dri-devel@lists.freedesktop.org
S: Supported
F: drivers/gpu/drm/sun4i/
@@ -4639,7 +4636,7 @@ F: Documentation/gpu/meson.rst
T: git git://anongit.freedesktop.org/drm/drm-misc
DRM DRIVERS FOR ATMEL HLCDC
-M: Boris Brezillon <boris.brezillon@free-electrons.com>
+M: Boris Brezillon <boris.brezillon@bootlin.com>
L: dri-devel@lists.freedesktop.org
S: Supported
F: drivers/gpu/drm/atmel-hlcdc/
@@ -4732,6 +4729,7 @@ F: drivers/gpu/drm/rcar-du/
F: drivers/gpu/drm/shmobile/
F: include/linux/platform_data/shmob_drm.h
F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
+F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
F: Documentation/devicetree/bindings/display/renesas,du.txt
DRM DRIVERS FOR ROCKCHIP
@@ -4998,12 +4996,6 @@ T: git git://linuxtv.org/anttip/media_tree.git
S: Maintained
F: drivers/media/tuners/e4000*
-EATA ISA/EISA/PCI SCSI DRIVER
-M: Dario Ballabio <ballabio_dario@emc.com>
-L: linux-scsi@vger.kernel.org
-S: Maintained
-F: drivers/scsi/eata.c
-
EC100 MEDIA DRIVER
M: Antti Palosaari <crope@iki.fi>
L: linux-media@vger.kernel.org
@@ -5545,7 +5537,7 @@ M: Luis R. Rodriguez <mcgrof@kernel.org>
L: linux-kernel@vger.kernel.org
S: Maintained
F: Documentation/firmware_class/
-F: drivers/base/firmware*.c
+F: drivers/base/firmware_loader/
F: include/linux/firmware.h
FLASH ADAPTER DRIVER (IBM Flash Adapter 900GB Full Height PCI Flash Card)
@@ -5630,7 +5622,7 @@ S: Maintained
F: drivers/dma/fsldma.*
FREESCALE eTSEC ETHERNET DRIVER (GIANFAR)
-M: Claudiu Manoil <claudiu.manoil@freescale.com>
+M: Claudiu Manoil <claudiu.manoil@nxp.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/freescale/gianfar*
@@ -5641,7 +5633,7 @@ FREESCALE GPMI NAND DRIVER
M: Han Xu <han.xu@nxp.com>
L: linux-mtd@lists.infradead.org
S: Maintained
-F: drivers/mtd/nand/gpmi-nand/*
+F: drivers/mtd/nand/raw/gpmi-nand/*
FREESCALE I2C CPM DRIVER
M: Jochen Friedrich <jochen@scram.de>
@@ -5792,10 +5784,6 @@ F: fs/crypto/
F: include/linux/fscrypt*.h
F: Documentation/filesystems/fscrypt.rst
-FUJITSU FR-V (FRV) PORT
-S: Orphan
-F: arch/frv/
-
FUJITSU LAPTOP EXTRAS
M: Jonathan Woithe <jwoithe@just42.net>
L: platform-driver-x86@vger.kernel.org
@@ -5843,12 +5831,6 @@ F: tools/testing/selftests/futex/
F: tools/perf/bench/futex*
F: Documentation/*futex*
-FUTURE DOMAIN TMC-16x0 SCSI DRIVER (16-bit)
-M: Rik Faith <faith@cs.unc.edu>
-L: linux-scsi@vger.kernel.org
-S: Odd Fixes (e.g., new signatures)
-F: drivers/scsi/fdomain.*
-
GCC PLUGINS
M: Kees Cook <keescook@chromium.org>
R: Emese Revfy <re.emese@gmail.com>
@@ -5860,7 +5842,7 @@ F: scripts/Makefile.gcc-plugins
F: Documentation/gcc-plugins.txt
GCOV BASED KERNEL PROFILING
-M: Peter Oberparleiter <oberpar@linux.vnet.ibm.com>
+M: Peter Oberparleiter <oberpar@linux.ibm.com>
S: Maintained
F: kernel/gcov/
F: Documentation/dev-tools/gcov.rst
@@ -5928,6 +5910,11 @@ S: Supported
F: drivers/phy/
F: include/linux/phy/
+GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER
+M: Wolfram Sang <wsa+renesas@sang-engineering.com>
+S: Supported
+F: drivers/i2c/muxes/i2c-demux-pinctrl.c
+
GENERIC PM DOMAINS
M: "Rafael J. Wysocki" <rjw@rjwysocki.net>
M: Kevin Hilman <khilman@kernel.org>
@@ -6009,7 +5996,7 @@ S: Maintained
F: drivers/media/rc/gpio-ir-tx.c
GPIO MOCKUP DRIVER
-M: Bamvor Jian Zhang <bamvor.zhangjian@linaro.org>
+M: Bamvor Jian Zhang <bamv2005@gmail.com>
R: Bartosz Golaszewski <brgl@bgdev.pl>
L: linux-gpio@vger.kernel.org
S: Maintained
@@ -6022,12 +6009,14 @@ L: linux-gpio@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
S: Maintained
F: Documentation/devicetree/bindings/gpio/
+F: Documentation/driver-api/gpio/
F: Documentation/gpio/
F: Documentation/ABI/testing/gpio-cdev
F: Documentation/ABI/obsolete/sysfs-gpio
F: drivers/gpio/
F: include/linux/gpio/
F: include/linux/gpio.h
+F: include/linux/of_gpio.h
F: include/asm-generic/gpio.h
F: include/uapi/linux/gpio.h
F: tools/gpio/
@@ -6237,6 +6226,11 @@ F: Documentation/hw_random.txt
F: drivers/char/hw_random/
F: include/linux/hw_random.h
+HARDWARE TRACING FACILITIES
+M: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+S: Maintained
+F: drivers/hwtracing/
+
HARDWARE SPINLOCK CORE
M: Ohad Ben-Cohen <ohad@wizery.com>
M: Bjorn Andersson <bjorn.andersson@linaro.org>
@@ -6381,6 +6375,13 @@ W: http://www.hisilicon.com
S: Maintained
F: drivers/net/ethernet/hisilicon/hns3/
+HISILICON LPC BUS DRIVER
+M: john.garry@huawei.com
+W: http://www.hisilicon.com
+S: Maintained
+F: drivers/bus/hisi_lpc.c
+F: Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
+
HISILICON NETWORK SUBSYSTEM DRIVER
M: Yisen Zhuang <yisen.zhuang@huawei.com>
M: Salil Mehta <salil.mehta@huawei.com>
@@ -6418,6 +6419,7 @@ L: linux-mm@kvack.org
S: Maintained
F: mm/hmm*
F: include/linux/hmm*
+F: Documentation/vm/hmm.txt
HOST AP DRIVER
M: Jouni Malinen <j@w1.fi>
@@ -6524,7 +6526,7 @@ S: Maintained
F: Documentation/networking/netvsc.txt
F: arch/x86/include/asm/mshyperv.h
F: arch/x86/include/asm/trace/hyperv.h
-F: arch/x86/include/uapi/asm/hyperv.h
+F: arch/x86/include/asm/hyperv-tlfs.h
F: arch/x86/kernel/cpu/mshyperv.c
F: arch/x86/hyperv
F: drivers/hid/hid-hyperv.c
@@ -6567,7 +6569,7 @@ F: drivers/i2c/muxes/
F: include/linux/i2c-mux.h
I2C MV64XXX MARVELL AND ALLWINNER DRIVER
-M: Gregory CLEMENT <gregory.clement@free-electrons.com>
+M: Gregory CLEMENT <gregory.clement@bootlin.com>
L: linux-i2c@vger.kernel.org
S: Maintained
F: drivers/i2c/busses/i2c-mv64xxx.c
@@ -6588,15 +6590,25 @@ W: https://i2c.wiki.kernel.org/
Q: https://patchwork.ozlabs.org/project/linux-i2c/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
S: Maintained
-F: Documentation/devicetree/bindings/i2c/
+F: Documentation/devicetree/bindings/i2c/i2c.txt
F: Documentation/i2c/
-F: drivers/i2c/
-F: drivers/i2c/*/
+F: drivers/i2c/*
F: include/linux/i2c.h
-F: include/linux/i2c-*.h
+F: include/linux/i2c-dev.h
+F: include/linux/i2c-smbus.h
F: include/uapi/linux/i2c.h
F: include/uapi/linux/i2c-*.h
+I2C SUBSYSTEM HOST DRIVERS
+L: linux-i2c@vger.kernel.org
+W: https://i2c.wiki.kernel.org/
+Q: https://patchwork.ozlabs.org/project/linux-i2c/list/
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
+S: Odd Fixes
+F: Documentation/devicetree/bindings/i2c/
+F: drivers/i2c/algos/
+F: drivers/i2c/busses/
+
I2C-TAOS-EVM DRIVER
M: Jean Delvare <jdelvare@suse.com>
L: linux-i2c@vger.kernel.org
@@ -6896,6 +6908,13 @@ M: James Hogan <jhogan@kernel.org>
S: Maintained
F: drivers/media/rc/img-ir/
+IMON SOUNDGRAPH USB IR RECEIVER
+M: Sean Young <sean@mess.org>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: drivers/media/rc/imon_raw.c
+F: drivers/media/rc/imon.c
+
IMS TWINTURBO FRAMEBUFFER DRIVER
L: linux-fbdev@vger.kernel.org
S: Orphan
@@ -6950,7 +6969,7 @@ INGENIC JZ4780 NAND DRIVER
M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mtd@lists.infradead.org
S: Maintained
-F: drivers/mtd/nand/jz4780_*
+F: drivers/mtd/nand/raw/jz4780_*
INOTIFY
M: Jan Kara <jack@suse.cz>
@@ -6985,7 +7004,7 @@ F: drivers/input/input-mt.c
K: \b(ABS|SYN)_MT_
INSIDE SECURE CRYPTO DRIVER
-M: Antoine Tenart <antoine.tenart@free-electrons.com>
+M: Antoine Tenart <antoine.tenart@bootlin.com>
F: drivers/crypto/inside-secure/
S: Maintained
L: linux-crypto@vger.kernel.org
@@ -7056,6 +7075,7 @@ F: Documentation/networking/ixgbe.txt
F: Documentation/networking/ixgbevf.txt
F: Documentation/networking/i40e.txt
F: Documentation/networking/i40evf.txt
+F: Documentation/networking/ice.txt
F: drivers/net/ethernet/intel/
F: drivers/net/ethernet/intel/*/
F: include/linux/avf/virtchnl.h
@@ -7221,6 +7241,15 @@ M: Shiraz Saleem <shiraz.saleem@intel.com>
L: linux-rdma@vger.kernel.org
S: Supported
F: drivers/infiniband/hw/i40iw/
+F: include/uapi/rdma/i40iw-abi.h
+
+INTEL SHA MULTIBUFFER DRIVER
+M: Megha Dey <megha.dey@linux.intel.com>
+R: Tim Chen <tim.c.chen@linux.intel.com>
+L: linux-crypto@vger.kernel.org
+S: Supported
+F: arch/x86/crypto/sha*-mb
+F: crypto/mcryptd.c
INTEL TELEMETRY DRIVER
M: Souvik Kumar Chakravarty <souvik.k.chakravarty@intel.com>
@@ -7316,6 +7345,7 @@ S: Maintained
F: Documentation/devicetree/bindings/iommu/
F: drivers/iommu/
F: include/linux/iommu.h
+F: include/linux/of_iommu.h
F: include/linux/iova.h
IP MASQUERADING
@@ -7334,7 +7364,7 @@ F: include/linux/ipmi*
F: include/uapi/linux/ipmi*
IPS SCSI RAID DRIVER
-M: Adaptec OEM Raid Solutions <aacraid@adaptec.com>
+M: Adaptec OEM Raid Solutions <aacraid@microsemi.com>
L: linux-scsi@vger.kernel.org
W: http://www.adaptec.com/
S: Maintained
@@ -7516,6 +7546,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
S: Maintained
F: drivers/media/dvb-frontends/ix2505v*
+JAILHOUSE HYPERVISOR INTERFACE
+M: Jan Kiszka <jan.kiszka@siemens.com>
+L: jailhouse-dev@googlegroups.com
+S: Maintained
+F: arch/x86/kernel/jailhouse.c
+F: arch/x86/include/asm/jailhouse_para.h
+
JC42.4 TEMPERATURE SENSOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org
@@ -7745,7 +7782,7 @@ F: arch/powerpc/kernel/kvm*
KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
M: Christian Borntraeger <borntraeger@de.ibm.com>
-M: Janosch Frank <frankja@linux.vnet.ibm.com>
+M: Janosch Frank <frankja@linux.ibm.com>
R: David Hildenbrand <david@redhat.com>
R: Cornelia Huck <cohuck@redhat.com>
L: linux-s390@vger.kernel.org
@@ -7902,7 +7939,10 @@ F: drivers/scsi/53c700*
LEAKING_ADDRESSES
M: Tobin C. Harding <me@tobin.cc>
+M: Tycho Andersen <tycho@tycho.ws>
+L: kernel-hardening@lists.openwall.com
S: Maintained
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/tobin/leaks.git
F: scripts/leaking_addresses.pl
LED SUBSYSTEM
@@ -8028,6 +8068,14 @@ Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
S: Supported
F: drivers/nvdimm/pmem*
+LIBNVDIMM: DEVICETREE BINDINGS
+M: Oliver O'Halloran <oohall@gmail.com>
+L: linux-nvdimm@lists.01.org
+Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
+S: Supported
+F: drivers/nvdimm/of_pmem.c
+F: Documentation/devicetree/bindings/pmem/pmem-region.txt
+
LIBNVDIMM: NON-VOLATILE MEMORY DEVICE SUBSYSTEM
M: Dan Williams <dan.j.williams@intel.com>
L: linux-nvdimm@lists.01.org
@@ -8142,7 +8190,25 @@ F: drivers/*/*/*pasemi*
LINUX KERNEL DUMP TEST MODULE (LKDTM)
M: Kees Cook <keescook@chromium.org>
S: Maintained
-F: drivers/misc/lkdtm*
+F: drivers/misc/lkdtm/*
+
+LINUX KERNEL MEMORY CONSISTENCY MODEL (LKMM)
+M: Alan Stern <stern@rowland.harvard.edu>
+M: Andrea Parri <parri.andrea@gmail.com>
+M: Will Deacon <will.deacon@arm.com>
+M: Peter Zijlstra <peterz@infradead.org>
+M: Boqun Feng <boqun.feng@gmail.com>
+M: Nicholas Piggin <npiggin@gmail.com>
+M: David Howells <dhowells@redhat.com>
+M: Jade Alglave <j.alglave@ucl.ac.uk>
+M: Luc Maranget <luc.maranget@inria.fr>
+M: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
+R: Akira Yokosawa <akiyks@gmail.com>
+L: linux-kernel@vger.kernel.org
+S: Supported
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
+F: tools/memory-model/
+F: Documentation/memory-barriers.txt
LINUX SECURITY MODULE (LSM) FRAMEWORK
M: Chris Wright <chrisw@sous-sol.org>
@@ -8305,11 +8371,6 @@ W: http://linux-test-project.github.io/
T: git git://github.com/linux-test-project/ltp.git
S: Maintained
-M32R ARCHITECTURE
-W: http://www.linux-m32r.org/
-S: Orphan
-F: arch/m32r/
-
M68K ARCHITECTURE
M: Geert Uytterhoeven <geert@linux-m68k.org>
L: linux-m68k@lists.linux-m68k.org
@@ -8408,7 +8469,7 @@ F: include/uapi/drm/armada_drm.h
F: Documentation/devicetree/bindings/display/armada/
MARVELL CRYPTO DRIVER
-M: Boris Brezillon <boris.brezillon@free-electrons.com>
+M: Boris Brezillon <boris.brezillon@bootlin.com>
M: Arnaud Ebalard <arno@natisbad.org>
F: drivers/crypto/marvell/
S: Maintained
@@ -8427,7 +8488,7 @@ S: Orphan
F: drivers/net/wireless/marvell/libertas/
MARVELL MACCHIATOBIN SUPPORT
-M: Russell King <rmk@armlinux.org.uk>
+M: Russell King <linux@armlinux.org.uk>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -8440,7 +8501,7 @@ F: drivers/net/ethernet/marvell/mv643xx_eth.*
F: include/linux/mv643xx.h
MARVELL MV88X3310 PHY DRIVER
-M: Russell King <rmk@armlinux.org.uk>
+M: Russell King <linux@armlinux.org.uk>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/marvell10g.c
@@ -8467,10 +8528,10 @@ S: Odd Fixes
F: drivers/net/wireless/marvell/mwl8k.c
MARVELL NAND CONTROLLER DRIVER
-M: Miquel Raynal <miquel.raynal@free-electrons.com>
+M: Miquel Raynal <miquel.raynal@bootlin.com>
L: linux-mtd@lists.infradead.org
S: Maintained
-F: drivers/mtd/nand/marvell_nand.c
+F: drivers/mtd/nand/raw/marvell_nand.c
F: Documentation/devicetree/bindings/mtd/marvell-nand.txt
MARVELL SOC MMC/SD/SDIO CONTROLLER DRIVER
@@ -8582,13 +8643,23 @@ W: https://linuxtv.org
S: Maintained
F: drivers/media/radio/radio-maxiradio*
-MCP4531 MICROCHIP DIGITAL POTENTIOMETER DRIVER
+MCP4018 AND MCP4531 MICROCHIP DIGITAL POTENTIOMETER DRIVERS
M: Peter Rosin <peda@axentia.se>
L: linux-iio@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-iio-potentiometer-mcp4531
+F: drivers/iio/potentiometer/mcp4018.c
F: drivers/iio/potentiometer/mcp4531.c
+MCR20A IEEE-802.15.4 RADIO DRIVER
+M: Xue Liu <liuxuenetmail@gmail.com>
+L: linux-wpan@vger.kernel.org
+W: https://github.com/xueliu/mcr20a-linux
+S: Maintained
+F: drivers/net/ieee802154/mcr20a.c
+F: drivers/net/ieee802154/mcr20a.h
+F: Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt
+
MEASUREMENT COMPUTING CIO-DAC IIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
@@ -8605,6 +8676,14 @@ T: git git://linuxtv.org/media_tree.git
S: Supported
F: drivers/media/dvb-frontends/ascot2e*
+MEDIA DRIVERS FOR CXD2099AR CI CONTROLLERS
+M: Jasmin Jessich <jasmin@anw.at>
+L: linux-media@vger.kernel.org
+W: https://linuxtv.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/dvb-frontends/cxd2099*
+
MEDIA DRIVERS FOR CXD2841ER
M: Sergey Kozlov <serjk@netup.ru>
M: Abylay Ospan <aospan@netup.ru>
@@ -8615,6 +8694,15 @@ T: git git://linuxtv.org/media_tree.git
S: Supported
F: drivers/media/dvb-frontends/cxd2841er*
+MEDIA DRIVERS FOR CXD2880
+M: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com>
+L: linux-media@vger.kernel.org
+W: http://linuxtv.org/
+T: git git://linuxtv.org/media_tree.git
+S: Supported
+F: drivers/media/dvb-frontends/cxd2880/*
+F: drivers/media/spi/cxd2880*
+
MEDIA DRIVERS FOR DIGITAL DEVICES PCIE DEVICES
M: Daniel Scheller <d.scheller.oss@gmail.com>
L: linux-media@vger.kernel.org
@@ -8682,6 +8770,16 @@ T: git git://linuxtv.org/media_tree.git
S: Supported
F: drivers/media/pci/netup_unidvb/*
+MEDIA DRIVERS FOR RENESAS - CEU
+M: Jacopo Mondi <jacopo@jmondi.org>
+L: linux-media@vger.kernel.org
+L: linux-renesas-soc@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Supported
+F: Documentation/devicetree/bindings/media/renesas,ceu.txt
+F: drivers/media/platform/renesas-ceu.c
+F: include/media/drv-intf/renesas-ceu.h
+
MEDIA DRIVERS FOR RENESAS - DRIF
M: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
L: linux-media@vger.kernel.org
@@ -8781,6 +8879,15 @@ M: Sean Wang <sean.wang@mediatek.com>
S: Maintained
F: drivers/media/rc/mtk-cir.c
+MEDIATEK DMA DRIVER
+M: Sean Wang <sean.wang@mediatek.com>
+L: dmaengine@vger.kernel.org
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/dma/mtk-*
+F: drivers/dma/mediatek/
+
MEDIATEK PMIC LED DRIVER
M: Sean Wang <sean.wang@mediatek.com>
S: Maintained
@@ -8874,6 +8981,13 @@ W: http://www.melexis.com
S: Supported
F: drivers/iio/temperature/mlx90614.c
+MELEXIS MLX90632 DRIVER
+M: Crt Mori <cmo@melexis.com>
+L: linux-iio@vger.kernel.org
+W: http://www.melexis.com
+S: Supported
+F: drivers/iio/temperature/mlx90632.c
+
MELFAS MIP4 TOUCHSCREEN DRIVER
M: Sangwon Jee <jeesw@melfas.com>
W: http://www.melfas.com
@@ -8999,6 +9113,7 @@ M: Vadim Pasternak <vadimp@mellanox.com>
L: linux-leds@vger.kernel.org
S: Supported
F: drivers/leds/leds-mlxcpld.c
+F: drivers/leds/leds-mlxreg.c
F: Documentation/leds/leds-mlxcpld.txt
MELLANOX PLATFORM DRIVER
@@ -9030,10 +9145,9 @@ F: mm/
MEMORY TECHNOLOGY DEVICES (MTD)
M: David Woodhouse <dwmw2@infradead.org>
M: Brian Norris <computersforpeace@gmail.com>
-M: Boris Brezillon <boris.brezillon@free-electrons.com>
+M: Boris Brezillon <boris.brezillon@bootlin.com>
M: Marek Vasut <marek.vasut@gmail.com>
M: Richard Weinberger <richard@nod.at>
-M: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/
Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
@@ -9077,20 +9191,6 @@ F: drivers/media/platform/meson/ao-cec.c
F: Documentation/devicetree/bindings/media/meson-ao-cec.txt
T: git git://linuxtv.org/media_tree.git
-METAG ARCHITECTURE
-M: James Hogan <jhogan@kernel.org>
-L: linux-metag@vger.kernel.org
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag.git
-S: Odd Fixes
-F: arch/metag/
-F: Documentation/metag/
-F: Documentation/devicetree/bindings/metag/
-F: Documentation/devicetree/bindings/interrupt-controller/img,*
-F: drivers/clocksource/metag_generic.c
-F: drivers/irqchip/irq-metag.c
-F: drivers/irqchip/irq-metag-ext.c
-F: drivers/tty/metag_da.c
-
MICROBLAZE ARCHITECTURE
M: Michal Simek <monstr@monstr.eu>
W: http://www.monstr.eu/fdt/
@@ -9132,7 +9232,7 @@ M: Wenyou Yang <wenyou.yang@microchip.com>
M: Josh Wu <rainyfeeling@outlook.com>
L: linux-mtd@lists.infradead.org
S: Supported
-F: drivers/mtd/nand/atmel/*
+F: drivers/mtd/nand/raw/atmel/*
F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
MICROCHIP KSZ SERIES ETHERNET SWITCH DRIVER
@@ -9145,6 +9245,13 @@ F: drivers/net/dsa/microchip/*
F: include/linux/platform_data/microchip-ksz.h
F: Documentation/devicetree/bindings/net/dsa/ksz.txt
+MICROCHIP LAN743X ETHERNET DRIVER
+M: Bryan Whitehead <bryan.whitehead@microchip.com>
+M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: drivers/net/ethernet/microchip/lan743x_*
+
MICROCHIP USB251XB DRIVER
M: Richard Leitner <richard.leitner@skidata.com>
L: linux-usb@vger.kernel.org
@@ -9152,6 +9259,15 @@ S: Maintained
F: drivers/usb/misc/usb251xb.c
F: Documentation/devicetree/bindings/usb/usb251xb.txt
+MICROSEMI MIPS SOCS
+M: Alexandre Belloni <alexandre.belloni@bootlin.com>
+L: linux-mips@linux-mips.org
+S: Maintained
+F: arch/mips/generic/board-ocelot.c
+F: arch/mips/configs/generic/board-ocelot.config
+F: arch/mips/boot/dts/mscc/
+F: Documentation/devicetree/bindings/mips/mscc.txt
+
MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
M: Don Brace <don.brace@microsemi.com>
L: esc.storagedev@microsemi.com
@@ -9372,6 +9488,14 @@ S: Maintained
F: drivers/media/i2c/mt9t001.c
F: include/media/i2c/mt9t001.h
+MT9T112 APTINA CAMERA SENSOR
+M: Jacopo Mondi <jacopo@jmondi.org>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Odd Fixes
+F: drivers/media/i2c/mt9t112.c
+F: include/media/i2c/mt9t112.h
+
MT9V032 APTINA CAMERA SENSOR
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
L: linux-media@vger.kernel.org
@@ -9449,7 +9573,7 @@ S: Supported
F: drivers/net/ethernet/myricom/myri10ge/
NAND FLASH SUBSYSTEM
-M: Boris Brezillon <boris.brezillon@free-electrons.com>
+M: Boris Brezillon <boris.brezillon@bootlin.com>
R: Richard Weinberger <richard@nod.at>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/
@@ -10177,6 +10301,13 @@ T: git git://linuxtv.org/media_tree.git
S: Maintained
F: drivers/media/i2c/ov13858.c
+OMNIVISION OV2685 SENSOR DRIVER
+M: Shunqian Zheng <zhengsq@rock-chips.com>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/i2c/ov2685.c
+
OMNIVISION OV5640 SENSOR DRIVER
M: Steve Longerbeam <slongerbeam@gmail.com>
L: linux-media@vger.kernel.org
@@ -10191,6 +10322,13 @@ T: git git://linuxtv.org/media_tree.git
S: Maintained
F: drivers/media/i2c/ov5647.c
+OMNIVISION OV5695 SENSOR DRIVER
+M: Shunqian Zheng <zhengsq@rock-chips.com>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/i2c/ov5695.c
+
OMNIVISION OV7670 SENSOR DRIVER
M: Jonathan Corbet <corbet@lwn.net>
L: linux-media@vger.kernel.org
@@ -10199,6 +10337,14 @@ S: Maintained
F: drivers/media/i2c/ov7670.c
F: Documentation/devicetree/bindings/media/i2c/ov7670.txt
+OMNIVISION OV772x SENSOR DRIVER
+M: Jacopo Mondi <jacopo@jmondi.org>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Odd fixes
+F: drivers/media/i2c/ov772x.c
+F: include/media/i2c/ov772x.h
+
OMNIVISION OV7740 SENSOR DRIVER
M: Wenyou Yang <wenyou.yang@microchip.com>
L: linux-media@vger.kernel.org
@@ -10207,11 +10353,21 @@ S: Maintained
F: drivers/media/i2c/ov7740.c
F: Documentation/devicetree/bindings/media/i2c/ov7740.txt
+OMNIVISION OV9650 SENSOR DRIVER
+M: Sakari Ailus <sakari.ailus@linux.intel.com>
+R: Akinobu Mita <akinobu.mita@gmail.com>
+R: Sylwester Nawrocki <s.nawrocki@samsung.com>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/i2c/ov9650.c
+F: Documentation/devicetree/bindings/media/i2c/ov9650.txt
+
ONENAND FLASH DRIVER
M: Kyungmin Park <kyungmin.park@samsung.com>
L: linux-mtd@lists.infradead.org
S: Maintained
-F: drivers/mtd/onenand/
+F: drivers/mtd/nand/onenand/
F: include/linux/mtd/onenand*.h
ONSTREAM SCSI TAPE DRIVER
@@ -10408,14 +10564,6 @@ L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/panasonic-laptop.c
-PANASONIC MN10300/AM33/AM34 PORT
-M: David Howells <dhowells@redhat.com>
-L: linux-am33-list@redhat.com (moderated for non-subscribers)
-W: ftp://ftp.redhat.com/pub/redhat/gnupro/AM33/
-S: Maintained
-F: Documentation/mn10300/
-F: arch/mn10300/
-
PARALLEL LCD/KEYPAD PANEL DRIVER
M: Willy Tarreau <willy@haproxy.com>
M: Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
@@ -10716,6 +10864,7 @@ F: drivers/acpi/pci*
F: drivers/pci/
F: include/asm-generic/pci*
F: include/linux/pci*
+F: include/linux/of_pci.h
F: include/uapi/linux/pci*
F: lib/pci*
F: arch/x86/pci/
@@ -10727,6 +10876,7 @@ L: linux-pci@vger.kernel.org
Q: http://patchwork.ozlabs.org/project/linux-pci/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
S: Supported
+F: drivers/pci/cadence/
F: drivers/pci/host/
F: drivers/pci/dwc/
@@ -11018,7 +11168,7 @@ F: include/linux/pktcdvd.h
F: include/uapi/linux/pktcdvd.h
PKUNITY SOC DRIVERS
-M: Guan Xuetao <gxt@mprc.pku.edu.cn>
+M: Guan Xuetao <gxt@pku.edu.cn>
W: http://mprc.pku.edu.cn/~guanxuetao/linux
S: Maintained
T: git git://github.com/gxt/linux.git
@@ -11344,12 +11494,6 @@ F: include/sound/pxa2xx-lib.h
F: sound/arm/pxa*
F: sound/soc/pxa/
-PXA3xx NAND FLASH DRIVER
-M: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-L: linux-mtd@lists.infradead.org
-S: Maintained
-F: drivers/mtd/nand/pxa3xx_nand.c
-
QAT DRIVER
M: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
L: qat-linux@intel.com
@@ -11369,6 +11513,7 @@ M: "Michael S. Tsirkin" <mst@redhat.com>
L: qemu-devel@nongnu.org
S: Maintained
F: drivers/firmware/qemu_fw_cfg.c
+F: include/uapi/linux/qemu_fw_cfg.h
QIB DRIVER
M: Dennis Dalessandro <dennis.dalessandro@intel.com>
@@ -11462,8 +11607,9 @@ M: Stuart Yoder <stuyoder@gmail.com>
M: Laurentiu Tudor <laurentiu.tudor@nxp.com>
L: linux-kernel@vger.kernel.org
S: Maintained
-F: drivers/staging/fsl-mc/
+F: drivers/bus/fsl-mc/
F: Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
+F: Documentation/networking/dpaa2/overview.rst
QT1010 MEDIA DRIVER
M: Antti Palosaari <crope@iki.fi>
@@ -11636,7 +11782,7 @@ F: drivers/char/random.c
RAPIDIO SUBSYSTEM
M: Matt Porter <mporter@kernel.crashing.org>
-M: Alexandre Bounine <alexandre.bounine@idt.com>
+M: Alexandre Bounine <alex.bou9@gmail.com>
S: Maintained
F: drivers/rapidio/
@@ -11710,7 +11856,7 @@ X: kernel/torture.c
REAL TIME CLOCK (RTC) SUBSYSTEM
M: Alessandro Zummo <a.zummo@towertech.it>
-M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+M: Alexandre Belloni <alexandre.belloni@bootlin.com>
L: linux-rtc@vger.kernel.org
Q: http://patchwork.ozlabs.org/project/rtc-linux/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git
@@ -11774,6 +11920,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git c
S: Supported
F: drivers/clk/renesas/
+RENESAS EMEV2 I2C DRIVER
+M: Wolfram Sang <wsa+renesas@sang-engineering.com>
+S: Supported
+F: drivers/i2c/busses/i2c-emev2.c
+
RENESAS ETHERNET DRIVERS
R: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
L: netdev@vger.kernel.org
@@ -11789,6 +11940,12 @@ L: linux-iio@vger.kernel.org
S: Supported
F: drivers/iio/adc/rcar_gyro_adc.c
+RENESAS R-CAR I2C DRIVERS
+M: Wolfram Sang <wsa+renesas@sang-engineering.com>
+S: Supported
+F: drivers/i2c/busses/i2c-rcar.c
+F: drivers/i2c/busses/i2c-sh_mobile.c
+
RENESAS USB PHY DRIVER
M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
L: linux-renesas-soc@vger.kernel.org
@@ -11832,8 +11989,8 @@ F: drivers/memstick/host/r592.*
RICOH SMARTMEDIA/XD DRIVER
M: Maxim Levitsky <maximlevitsky@gmail.com>
S: Maintained
-F: drivers/mtd/nand/r852.c
-F: drivers/mtd/nand/r852.h
+F: drivers/mtd/nand/raw/r852.c
+F: drivers/mtd/nand/raw/r852.h
RISC-V ARCHITECTURE
M: Palmer Dabbelt <palmer@sifive.com>
@@ -11992,16 +12149,16 @@ F: Documentation/s390/
F: Documentation/driver-api/s390-drivers.rst
S390 COMMON I/O LAYER
-M: Sebastian Ott <sebott@linux.vnet.ibm.com>
-M: Peter Oberparleiter <oberpar@linux.vnet.ibm.com>
+M: Sebastian Ott <sebott@linux.ibm.com>
+M: Peter Oberparleiter <oberpar@linux.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
S: Supported
F: drivers/s390/cio/
S390 DASD DRIVER
-M: Stefan Haberland <sth@linux.vnet.ibm.com>
-M: Jan Hoeppner <hoeppner@linux.vnet.ibm.com>
+M: Stefan Haberland <sth@linux.ibm.com>
+M: Jan Hoeppner <hoeppner@linux.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
S: Supported
@@ -12016,8 +12173,8 @@ S: Supported
F: drivers/iommu/s390-iommu.c
S390 IUCV NETWORK LAYER
-M: Julian Wiedmann <jwi@linux.vnet.ibm.com>
-M: Ursula Braun <ubraun@linux.vnet.ibm.com>
+M: Julian Wiedmann <jwi@linux.ibm.com>
+M: Ursula Braun <ubraun@linux.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
S: Supported
@@ -12026,15 +12183,15 @@ F: include/net/iucv/
F: net/iucv/
S390 NETWORK DRIVERS
-M: Julian Wiedmann <jwi@linux.vnet.ibm.com>
-M: Ursula Braun <ubraun@linux.vnet.ibm.com>
+M: Julian Wiedmann <jwi@linux.ibm.com>
+M: Ursula Braun <ubraun@linux.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
S: Supported
F: drivers/s390/net/
S390 PCI SUBSYSTEM
-M: Sebastian Ott <sebott@linux.vnet.ibm.com>
+M: Sebastian Ott <sebott@linux.ibm.com>
M: Gerald Schaefer <gerald.schaefer@de.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
@@ -12044,8 +12201,8 @@ F: drivers/pci/hotplug/s390_pci_hpc.c
S390 VFIO-CCW DRIVER
M: Cornelia Huck <cohuck@redhat.com>
-M: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com>
-M: Halil Pasic <pasic@linux.vnet.ibm.com>
+M: Dong Jia Shi <bjsdjshi@linux.ibm.com>
+M: Halil Pasic <pasic@linux.ibm.com>
L: linux-s390@vger.kernel.org
L: kvm@vger.kernel.org
S: Supported
@@ -12061,8 +12218,8 @@ S: Supported
F: drivers/s390/crypto/
S390 ZFCP DRIVER
-M: Steffen Maier <maier@linux.vnet.ibm.com>
-M: Benjamin Block <bblock@linux.vnet.ibm.com>
+M: Steffen Maier <maier@linux.ibm.com>
+M: Benjamin Block <bblock@linux.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
S: Supported
@@ -12207,6 +12364,7 @@ M: Tomasz Figa <tomasz.figa@gmail.com>
M: Chanwoo Choi <cw00.choi@samsung.com>
S: Supported
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
F: Documentation/devicetree/bindings/clock/exynos*.txt
@@ -12214,7 +12372,7 @@ F: Documentation/devicetree/bindings/clock/exynos*.txt
SAMSUNG SPI DRIVERS
M: Kukjin Kim <kgene@kernel.org>
M: Krzysztof Kozlowski <krzk@kernel.org>
-M: Andi Shyti <andi.shyti@samsung.com>
+M: Andi Shyti <andi@etezian.org>
L: linux-spi@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
S: Maintained
@@ -12268,13 +12426,6 @@ F: include/linux/sched.h
F: include/uapi/linux/sched.h
F: include/linux/wait.h
-SCORE ARCHITECTURE
-M: Chen Liqin <liqin.linux@gmail.com>
-M: Lennox Wu <lennox.wu@gmail.com>
-W: http://www.sunplus.com
-S: Supported
-F: arch/score/
-
SCR24X CHIP CARD INTERFACE DRIVER
M: Lubomir Rintel <lkundrak@v3.sk>
S: Supported
@@ -12505,7 +12656,7 @@ S: Maintained
F: drivers/misc/sgi-xp/
SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
-M: Ursula Braun <ubraun@linux.vnet.ibm.com>
+M: Ursula Braun <ubraun@linux.ibm.com>
L: linux-s390@vger.kernel.org
W: http://www.ibm.com/developerworks/linux/linux390/
S: Supported
@@ -12802,14 +12953,20 @@ S: Maintained
F: drivers/net/ethernet/smsc/smsc9420.*
SOC-CAMERA V4L2 SUBSYSTEM
-M: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
L: linux-media@vger.kernel.org
T: git git://linuxtv.org/media_tree.git
-S: Maintained
+S: Orphan
F: include/media/soc*
F: drivers/media/i2c/soc_camera/
F: drivers/media/platform/soc_camera/
+SOCIONEXT SYNQUACER I2C DRIVER
+M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+L: linux-i2c@vger.kernel.org
+S: Maintained
+F: drivers/i2c/busses/i2c-synquacer.c
+F: Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
+
SOCIONEXT UNIPHIER SOUND DRIVER
M: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
@@ -12868,6 +13025,19 @@ S: Maintained
F: drivers/net/ethernet/socionext/netsec.c
F: Documentation/devicetree/bindings/net/socionext-netsec.txt
+SOLIDRUN CLEARFOG SUPPORT
+M: Russell King <linux@armlinux.org.uk>
+S: Maintained
+F: arch/arm/boot/dts/armada-388-clearfog*
+F: arch/arm/boot/dts/armada-38x-solidrun-*
+
+SOLIDRUN CUBOX-I/HUMMINGBOARD SUPPORT
+M: Russell King <linux@armlinux.org.uk>
+S: Maintained
+F: arch/arm/boot/dts/imx6*-cubox-i*
+F: arch/arm/boot/dts/imx6*-hummingboard*
+F: arch/arm/boot/dts/imx6*-sr-*
+
SONIC NETWORK DRIVER
M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
L: netdev@vger.kernel.org
@@ -13024,7 +13194,6 @@ F: arch/arm/boot/dts/spear*
F: arch/arm/mach-spear/
SPI NOR SUBSYSTEM
-M: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
M: Marek Vasut <marek.vasut@gmail.com>
L: linux-mtd@lists.infradead.org
W: http://www.linux-mtd.infradead.org/
@@ -13354,6 +13523,12 @@ S: Maintained
F: drivers/gpio/gpio-dwapb.c
F: Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
+SYNOPSYS DESIGNWARE AXI DMAC DRIVER
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Maintained
+F: drivers/dma/dwi-axi-dmac/
+F: Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+
SYNOPSYS DESIGNWARE DMAC DRIVER
M: Viresh Kumar <vireshk@kernel.org>
R: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
@@ -13397,15 +13572,16 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
S: Supported
F: drivers/mfd/syscon.c
-SYSTEM CONTROL & POWER INTERFACE (SCPI) Message Protocol drivers
+SYSTEM CONTROL & POWER/MANAGEMENT INTERFACE (SCPI/SCMI) Message Protocol drivers
M: Sudeep Holla <sudeep.holla@arm.com>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
-F: Documentation/devicetree/bindings/arm/arm,scpi.txt
-F: drivers/clk/clk-scpi.c
-F: drivers/cpufreq/scpi-cpufreq.c
+F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt
+F: drivers/clk/clk-sc[mp]i.c
+F: drivers/cpufreq/sc[mp]i-cpufreq.c
F: drivers/firmware/arm_scpi.c
-F: include/linux/scpi_protocol.h
+F: drivers/firmware/arm_scmi/
+F: include/linux/sc[mp]i_protocol.h
SYSTEM RESET/SHUTDOWN DRIVERS
M: Sebastian Reichel <sre@kernel.org>
@@ -13521,6 +13697,14 @@ T: git git://linuxtv.org/mkrufky/tuners.git
S: Maintained
F: drivers/media/tuners/tda18271*
+TDA1997x MEDIA DRIVER
+M: Tim Harvey <tharvey@gateworks.com>
+L: linux-media@vger.kernel.org
+W: https://linuxtv.org
+Q: http://patchwork.linuxtv.org/project/linux-media/list/
+S: Maintained
+F: drivers/media/i2c/tda1997x.*
+
TDA827x MEDIA DRIVER
M: Michael Krufky <mkrufky@linuxtv.org>
L: linux-media@vger.kernel.org
@@ -13602,6 +13786,12 @@ L: linux-media@vger.kernel.org
S: Maintained
F: drivers/media/rc/ttusbir.c
+TECHWELL TW9910 VIDEO DECODER
+L: linux-media@vger.kernel.org
+S: Orphan
+F: drivers/media/i2c/tw9910.c
+F: include/media/i2c/tw9910.h
+
TEE SUBSYSTEM
M: Jens Wiklander <jens.wiklander@linaro.org>
S: Maintained
@@ -13637,7 +13827,8 @@ S: Supported
F: drivers/i2c/busses/i2c-tegra.c
TEGRA IOMMU DRIVERS
-M: Hiroshi Doyu <hdoyu@nvidia.com>
+M: Thierry Reding <thierry.reding@gmail.com>
+L: linux-tegra@vger.kernel.org
S: Supported
F: drivers/iommu/tegra*
@@ -13810,6 +14001,13 @@ F: arch/arm/mach-davinci/
F: drivers/i2c/busses/i2c-davinci.c
F: arch/arm/boot/dts/da850*
+TI DAVINCI SERIES CLOCK DRIVER
+M: David Lechner <david@lechnology.com>
+R: Sekhar Nori <nsekhar@ti.com>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/ti/davinci/
+F: drivers/clk/davinci/
+
TI DAVINCI SERIES GPIO DRIVER
M: Keerthy <j-keerthy@ti.com>
L: linux-gpio@vger.kernel.org
@@ -13925,19 +14123,6 @@ S: Orphan
F: drivers/net/wireless/ti/
F: include/linux/wl12xx.h
-TILE ARCHITECTURE
-W: http://www.mellanox.com/repository/solutions/tile-scm/
-S: Orphan
-F: arch/tile/
-F: drivers/char/tile-srom.c
-F: drivers/edac/tile_edac.c
-F: drivers/net/ethernet/tile/
-F: drivers/rtc/rtc-tile.c
-F: drivers/tty/hvc/hvc_tile.c
-F: drivers/tty/serial/tilegx.c
-F: drivers/usb/host/*-tilegx.c
-F: include/linux/usb/tilegx.h
-
TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
M: John Stultz <john.stultz@linaro.org>
M: Thomas Gleixner <tglx@linutronix.de>
@@ -14263,7 +14448,7 @@ F: include/linux/uwb.h
F: include/linux/uwb/
UNICORE32 ARCHITECTURE:
-M: Guan Xuetao <gxt@mprc.pku.edu.cn>
+M: Guan Xuetao <gxt@pku.edu.cn>
W: http://mprc.pku.edu.cn/~guanxuetao/linux
S: Maintained
T: git git://github.com/gxt/linux.git
@@ -14402,6 +14587,12 @@ S: Maintained
F: Documentation/hid/hiddev.txt
F: drivers/hid/usbhid/
+USB INTEL XHCI ROLE MUX DRIVER
+M: Hans de Goede <hdegoede@redhat.com>
+L: linux-usb@vger.kernel.org
+S: Maintained
+F: drivers/usb/roles/intel-xhci-usb-role-switch.c
+
USB ISP116X DRIVER
M: Olav Kongas <ok@artecdesign.ee>
L: linux-usb@vger.kernel.org
@@ -14532,6 +14723,12 @@ F: drivers/usb/
F: include/linux/usb.h
F: include/linux/usb/
+USB TYPEC PI3USB30532 MUX DRIVER
+M: Hans de Goede <hdegoede@redhat.com>
+L: linux-usb@vger.kernel.org
+S: Maintained
+F: drivers/usb/typec/mux/pi3usb30532.c
+
USB TYPEC SUBSYSTEM
M: Heikki Krogerus <heikki.krogerus@linux.intel.com>
L: linux-usb@vger.kernel.org
@@ -14653,7 +14850,7 @@ VF610 NAND DRIVER
M: Stefan Agner <stefan@agner.ch>
L: linux-mtd@lists.infradead.org
S: Supported
-F: drivers/mtd/nand/vf610_nfc.c
+F: drivers/mtd/nand/raw/vf610_nfc.c
VFAT/FAT/MSDOS FILESYSTEM
M: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
@@ -14681,7 +14878,7 @@ F: include/linux/mdev.h
F: samples/vfio-mdev/
VFIO PLATFORM DRIVER
-M: Baptiste Reynal <b.reynal@virtualopensystems.com>
+M: Eric Auger <eric.auger@redhat.com>
L: kvm@vger.kernel.org
S: Maintained
F: drivers/vfio/platform/
@@ -14801,7 +14998,7 @@ F: include/uapi/linux/virtio_crypto.h
VIRTIO DRIVERS FOR S390
M: Cornelia Huck <cohuck@redhat.com>
-M: Halil Pasic <pasic@linux.vnet.ibm.com>
+M: Halil Pasic <pasic@linux.ibm.com>
L: linux-s390@vger.kernel.org
L: virtualization@lists.linux-foundation.org
L: kvm@vger.kernel.org
@@ -14916,7 +15113,7 @@ F: drivers/input/mouse/vmmouse.c
F: drivers/input/mouse/vmmouse.h
VMWARE VMXNET3 ETHERNET DRIVER
-M: Shrikrishna Khare <skhare@vmware.com>
+M: Ronak Doshi <doshir@vmware.com>
M: "VMware, Inc." <pv-drivers@vmware.com>
L: netdev@vger.kernel.org
S: Maintained
diff --git a/Makefile b/Makefile
index 7ba478ab8c82..e811e0c509c5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
-PATCHLEVEL = 16
+PATCHLEVEL = 17
SUBLEVEL = 0
-EXTRAVERSION = -rc7
+EXTRAVERSION = -rc1
NAME = Fearless Coyote
# *DOCUMENTATION*
@@ -35,7 +35,7 @@ unexport GREP_OPTIONS
# Most importantly: sub-Makefiles should only ever modify files in
# their own directory. If in some directory we have a dependency on
# a file in another dir (which doesn't happen often, but it's often
-# unavoidable when linking the built-in.o targets which finally
+# unavoidable when linking the built-in.a targets which finally
# turn into vmlinux), we will call a sub make in that other dir, and
# after that we are sure that everything which is in that other dir
# is now up to date.
@@ -220,7 +220,8 @@ export srctree objtree VPATH
version_h := include/generated/uapi/linux/version.h
old_version_h := include/linux/version.h
-no-dot-config-targets := clean mrproper distclean \
+clean-targets := %clean mrproper cleandocs
+no-dot-config-targets := $(clean-targets) \
cscope gtags TAGS tags help% %docs check% coccicheck \
$(version_h) headers_% archheaders archscripts \
kernelversion %src-pkg
@@ -243,6 +244,14 @@ ifeq ($(KBUILD_EXTMOD),)
endif
endif
endif
+
+# For "make -j clean all", "make -j mrproper defconfig all", etc.
+ifneq ($(filter $(clean-targets),$(MAKECMDGOALS)),)
+ ifneq ($(filter-out $(clean-targets),$(MAKECMDGOALS)),)
+ mixed-targets := 1
+ endif
+endif
+
# install and modules_install need also be processed one by one
ifneq ($(filter install,$(MAKECMDGOALS)),)
ifneq ($(filter modules_install,$(MAKECMDGOALS)),)
@@ -339,14 +348,6 @@ ifeq ($(ARCH),sh64)
SRCARCH := sh
endif
-# Additional ARCH settings for tile
-ifeq ($(ARCH),tilepro)
- SRCARCH := tile
-endif
-ifeq ($(ARCH),tilegx)
- SRCARCH := tile
-endif
-
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
@@ -385,6 +386,8 @@ INSTALLKERNEL := installkernel
DEPMOD = /sbin/depmod
PERL = perl
PYTHON = python
+PYTHON2 = python2
+PYTHON3 = python3
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@@ -426,11 +429,12 @@ KBUILD_CFLAGS_KERNEL :=
KBUILD_AFLAGS_MODULE := -DMODULE
KBUILD_CFLAGS_MODULE := -DMODULE
KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds
+LDFLAGS :=
GCC_PLUGINS_CFLAGS :=
export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM STRIP OBJCOPY OBJDUMP HOSTLDFLAGS HOST_LOADLIBES
-export MAKE LEX YACC AWK GENKSYMS INSTALLKERNEL PERL PYTHON UTS_MACHINE
+export MAKE LEX YACC AWK GENKSYMS INSTALLKERNEL PERL PYTHON PYTHON2 PYTHON3 UTS_MACHINE
export HOSTCXX HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS LDFLAGS
@@ -487,6 +491,8 @@ CLANG_GCC_TC := --gcc-toolchain=$(GCC_TOOLCHAIN)
endif
KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC)
KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC)
+KBUILD_CFLAGS += $(call cc-option, -no-integrated-as)
+KBUILD_AFLAGS += $(call cc-option, -no-integrated-as)
endif
RETPOLINE_CFLAGS_GCC := -mindirect-branch=thunk-extern -mindirect-branch-register
@@ -494,6 +500,13 @@ RETPOLINE_CFLAGS_CLANG := -mretpoline-external-thunk
RETPOLINE_CFLAGS := $(call cc-option,$(RETPOLINE_CFLAGS_GCC),$(call cc-option,$(RETPOLINE_CFLAGS_CLANG)))
export RETPOLINE_CFLAGS
+# check for 'asm goto'
+ifeq ($(call shell-cached,$(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC) $(KBUILD_CFLAGS)), y)
+ CC_HAVE_ASM_GOTO := 1
+ KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
+ KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
+endif
+
ifeq ($(config-targets),1)
# ===========================================================================
# *config targets only - make sure prerequisites are updated, and descend
@@ -555,14 +568,6 @@ endif
export KBUILD_MODULES KBUILD_BUILTIN
ifeq ($(KBUILD_EXTMOD),)
-# Additional helpers built in scripts/
-# Carefully list dependencies so we do not try to build scripts twice
-# in parallel
-PHONY += scripts
-scripts: scripts_basic include/config/auto.conf include/config/tristate.conf \
- asm-generic gcc-plugins
- $(Q)$(MAKE) $(build)=$(@)
-
# Objects we will link into vmlinux / subdirs we need to visit
init-y := init/
drivers-y := drivers/ sound/ firmware/
@@ -588,7 +593,7 @@ $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ;
# include/generated/ and include/config/. Update them if .config is newer than
# include/config/auto.conf (which mirrors .config).
include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
- $(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig
+ $(Q)$(MAKE) -f $(srctree)/Makefile syncconfig
else
# external modules needs include/generated/autoconf.h and include/config/auto.conf
# but do not care if they are up-to-date. Use auto.conf to trigger the test
@@ -610,13 +615,6 @@ else
include/config/auto.conf: ;
endif # $(dot-config)
-# For the kernel to actually contain only the needed exported symbols,
-# we have to build modules as well to determine what those symbols are.
-# (this can be evaluated only once include/config/auto.conf has been included)
-ifdef CONFIG_TRIM_UNUSED_KSYMS
- KBUILD_MODULES := 1
-endif
-
# The all: target is the default when no target is given on the
# command line.
# This allow a user to issue only 'make' to build a kernel including modules
@@ -658,12 +656,6 @@ KBUILD_CFLAGS += $(call cc-ifversion, -lt, 0409, \
# Tell gcc to never replace conditional load with a non-conditional one
KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0)
-# check for 'asm goto'
-ifeq ($(call shell-cached,$(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC) $(KBUILD_CFLAGS)), y)
- KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
- KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
-endif
-
include scripts/Makefile.kcov
include scripts/Makefile.gcc-plugins
@@ -743,8 +735,6 @@ KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
# See modpost pattern 2
KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
-KBUILD_CFLAGS += $(call cc-option, -no-integrated-as)
-KBUILD_AFLAGS += $(call cc-option, -no-integrated-as)
else
# These warnings generated too much noise in a regular build.
@@ -856,6 +846,9 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types)
# Require designated initializers for all marked structures
KBUILD_CFLAGS += $(call cc-option,-Werror=designated-init)
+# change __FILE__ to the relative path from the srctree
+KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
+
# use the deterministic mode of AR if available
KBUILD_ARFLAGS := $(call ar-option,D)
@@ -991,13 +984,13 @@ vmlinux-dirs := $(patsubst %/,%,$(filter %/, $(init-y) $(init-m) \
vmlinux-alldirs := $(sort $(vmlinux-dirs) $(patsubst %/,%,$(filter %/, \
$(init-) $(core-) $(drivers-) $(net-) $(libs-) $(virt-))))
-init-y := $(patsubst %/, %/built-in.o, $(init-y))
-core-y := $(patsubst %/, %/built-in.o, $(core-y))
-drivers-y := $(patsubst %/, %/built-in.o, $(drivers-y))
-net-y := $(patsubst %/, %/built-in.o, $(net-y))
+init-y := $(patsubst %/, %/built-in.a, $(init-y))
+core-y := $(patsubst %/, %/built-in.a, $(core-y))
+drivers-y := $(patsubst %/, %/built-in.a, $(drivers-y))
+net-y := $(patsubst %/, %/built-in.a, $(net-y))
libs-y1 := $(patsubst %/, %/lib.a, $(libs-y))
-libs-y2 := $(filter-out %.a, $(patsubst %/, %/built-in.o, $(libs-y)))
-virt-y := $(patsubst %/, %/built-in.o, $(virt-y))
+libs-y2 := $(patsubst %/, %/built-in.a, $(filter-out %.a, $(libs-y)))
+virt-y := $(patsubst %/, %/built-in.a, $(virt-y))
# Externally visible symbols (used by link-vmlinux.sh)
export KBUILD_VMLINUX_INIT := $(head-y) $(init-y)
@@ -1010,25 +1003,26 @@ export KBUILD_ALLDIRS := $(sort $(filter-out arch/%,$(vmlinux-alldirs)) arch Doc
vmlinux-deps := $(KBUILD_LDS) $(KBUILD_VMLINUX_INIT) $(KBUILD_VMLINUX_MAIN) $(KBUILD_VMLINUX_LIBS)
-# Include targets which we want to execute sequentially if the rest of the
-# kernel build went well. If CONFIG_TRIM_UNUSED_KSYMS is set, this might be
-# evaluated more than once.
-PHONY += vmlinux_prereq
-vmlinux_prereq: $(vmlinux-deps) FORCE
-ifdef CONFIG_HEADERS_CHECK
- $(Q)$(MAKE) -f $(srctree)/Makefile headers_check
-endif
-ifdef CONFIG_GDB_SCRIPTS
- $(Q)ln -fsn $(abspath $(srctree)/scripts/gdb/vmlinux-gdb.py)
-endif
+# Recurse until adjust_autoksyms.sh is satisfied
+PHONY += autoksyms_recursive
+autoksyms_recursive: $(vmlinux-deps)
ifdef CONFIG_TRIM_UNUSED_KSYMS
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/adjust_autoksyms.sh \
"$(MAKE) -f $(srctree)/Makefile vmlinux"
endif
-# standalone target for easier testing
-include/generated/autoksyms.h: FORCE
- $(Q)$(CONFIG_SHELL) $(srctree)/scripts/adjust_autoksyms.sh true
+# For the kernel to actually contain only the needed exported symbols,
+# we have to build modules as well to determine what those symbols are.
+# (this can be evaluated only once include/config/auto.conf has been included)
+ifdef CONFIG_TRIM_UNUSED_KSYMS
+ KBUILD_MODULES := 1
+endif
+
+autoksyms_h := $(if $(CONFIG_TRIM_UNUSED_KSYMS), include/generated/autoksyms.h)
+
+$(autoksyms_h):
+ $(Q)mkdir -p $(dir $@)
+ $(Q)touch $@
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(SRCARCH)/Makefile.postlink)
@@ -1037,7 +1031,13 @@ cmd_link-vmlinux = \
$(CONFIG_SHELL) $< $(LD) $(LDFLAGS) $(LDFLAGS_vmlinux) ; \
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
-vmlinux: scripts/link-vmlinux.sh vmlinux_prereq $(vmlinux-deps) FORCE
+vmlinux: scripts/link-vmlinux.sh autoksyms_recursive $(vmlinux-deps) FORCE
+ifdef CONFIG_HEADERS_CHECK
+ $(Q)$(MAKE) -f $(srctree)/Makefile headers_check
+endif
+ifdef CONFIG_GDB_SCRIPTS
+ $(Q)ln -fsn $(abspath $(srctree)/scripts/gdb/vmlinux-gdb.py)
+endif
+$(call if_changed,link-vmlinux)
# Build samples along the rest of the kernel
@@ -1067,6 +1067,13 @@ endef
include/config/kernel.release: include/config/auto.conf FORCE
$(call filechk,kernel.release)
+# Additional helpers built in scripts/
+# Carefully list dependencies so we do not try to build scripts twice
+# in parallel
+PHONY += scripts
+scripts: scripts_basic include/config/auto.conf include/config/tristate.conf \
+ asm-generic gcc-plugins $(autoksyms_h)
+ $(Q)$(MAKE) $(build)=$(@)
# Things we need to do before we recursively start building the kernel
# or the modules are listed in "prepare".
@@ -1095,7 +1102,7 @@ endif
# that need to depend on updated CONFIG_* values can be checked here.
prepare2: prepare3 prepare-compiler-check outputmakefile asm-generic
-prepare1: prepare2 $(version_h) include/generated/utsrelease.h \
+prepare1: prepare2 $(version_h) $(autoksyms_h) include/generated/utsrelease.h \
include/config/auto.conf
$(cmd_crmodverdir)
@@ -1334,7 +1341,7 @@ endif # CONFIG_MODULES
# make distclean Remove editor backup files, patch leftover files and the like
# Directories & files removed with 'make clean'
-CLEAN_DIRS += $(MODVERDIR)
+CLEAN_DIRS += $(MODVERDIR) include/ksym
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config usr/include include/generated \
@@ -1611,6 +1618,8 @@ clean: $(clean-dirs)
-o -name '*.dwo' -o -name '*.lst' \
-o -name '*.su' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+ -o -name '*.lex.c' -o -name '*.tab.[ch]' \
+ -o -name '*.asn1.[ch]' \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name .cache.mk \
diff --git a/README b/README
index b2ba4aaa3a71..2c927ccbd970 100644
--- a/README
+++ b/README
@@ -1,13 +1,14 @@
Linux kernel
============
-This file was moved to Documentation/admin-guide/README.rst
-
-Please notice that there are several guides for kernel developers and users.
-These guides can be rendered in a number of formats, like HTML and PDF.
+There are several guides for kernel developers and users. These guides can
+be rendered in a number of formats, like HTML and PDF. Please read
+Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
-``make pdfdocs``.
+``make pdfdocs``. The formatted documentation can also be read online at:
+
+ https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
diff --git a/arch/Kconfig b/arch/Kconfig
index 76c0b54443b1..8e0d665c8d53 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -596,12 +596,6 @@ config CC_STACKPROTECTOR_AUTO
endchoice
-config THIN_ARCHIVES
- def_bool y
- help
- Select this if the architecture wants to use thin archives
- instead of ld -r to create the built-in.o files.
-
config LD_DEAD_CODE_DATA_ELIMINATION
bool
help
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index e96adcbcab41..b2022885ced8 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -18,6 +18,7 @@ config ALPHA
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select AUDIT_ARCH
select GENERIC_CLOCKEVENTS
+ select GENERIC_CPU_VULNERABILITIES
select GENERIC_SMP_IDLE_THREAD
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h
index 8a2b331e43fe..6c7c39452471 100644
--- a/arch/alpha/include/asm/cmpxchg.h
+++ b/arch/alpha/include/asm/cmpxchg.h
@@ -38,19 +38,31 @@
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
#include <asm/xchg.h>
+/*
+ * The leading and the trailing memory barriers guarantee that these
+ * operations are fully ordered.
+ */
#define xchg(ptr, x) \
({ \
+ __typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
- sizeof(*(ptr))); \
+ smp_mb(); \
+ __ret = (__typeof__(*(ptr))) \
+ __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
+ smp_mb(); \
+ __ret; \
})
#define cmpxchg(ptr, o, n) \
({ \
+ __typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
- (unsigned long)_n_, sizeof(*(ptr)));\
+ smp_mb(); \
+ __ret = (__typeof__(*(ptr))) __cmpxchg((ptr), \
+ (unsigned long)_o_, (unsigned long)_n_, sizeof(*(ptr)));\
+ smp_mb(); \
+ __ret; \
})
#define cmpxchg64(ptr, o, n) \
diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h
index d123ff90f7a8..4c533fc94d62 100644
--- a/arch/alpha/include/asm/io.h
+++ b/arch/alpha/include/asm/io.h
@@ -341,14 +341,14 @@ extern inline unsigned int ioread16(void __iomem *addr)
extern inline void iowrite8(u8 b, void __iomem *addr)
{
- IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr);
mb();
+ IO_CONCAT(__IO_PREFIX, iowrite8)(b, addr);
}
extern inline void iowrite16(u16 b, void __iomem *addr)
{
- IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr);
mb();
+ IO_CONCAT(__IO_PREFIX, iowrite16)(b, addr);
}
extern inline u8 inb(unsigned long port)
@@ -382,8 +382,8 @@ extern inline unsigned int ioread32(void __iomem *addr)
extern inline void iowrite32(u32 b, void __iomem *addr)
{
- IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
mb();
+ IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr);
}
extern inline u32 inl(unsigned long port)
@@ -434,14 +434,14 @@ extern inline u16 readw(const volatile void __iomem *addr)
extern inline void writeb(u8 b, volatile void __iomem *addr)
{
- __raw_writeb(b, addr);
mb();
+ __raw_writeb(b, addr);
}
extern inline void writew(u16 b, volatile void __iomem *addr)
{
- __raw_writew(b, addr);
mb();
+ __raw_writew(b, addr);
}
#endif
@@ -482,14 +482,14 @@ extern inline u64 readq(const volatile void __iomem *addr)
extern inline void writel(u32 b, volatile void __iomem *addr)
{
- __raw_writel(b, addr);
mb();
+ __raw_writel(b, addr);
}
extern inline void writeq(u64 b, volatile void __iomem *addr)
{
- __raw_writeq(b, addr);
mb();
+ __raw_writeq(b, addr);
}
#endif
diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h
index e2b59fac5257..7adb80c6746a 100644
--- a/arch/alpha/include/asm/xchg.h
+++ b/arch/alpha/include/asm/xchg.h
@@ -12,10 +12,6 @@
* Atomic exchange.
* Since it can be used to implement critical sections
* it must clobber "memory" (also for interrupts in UP).
- *
- * The leading and the trailing memory barriers guarantee that these
- * operations are fully ordered.
- *
*/
static inline unsigned long
@@ -23,7 +19,6 @@ ____xchg(_u8, volatile char *m, unsigned long val)
{
unsigned long ret, tmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %4,7,%3\n"
" insbl %1,%4,%1\n"
@@ -38,7 +33,6 @@ ____xchg(_u8, volatile char *m, unsigned long val)
".previous"
: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
: "r" ((long)m), "1" (val) : "memory");
- smp_mb();
return ret;
}
@@ -48,7 +42,6 @@ ____xchg(_u16, volatile short *m, unsigned long val)
{
unsigned long ret, tmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %4,7,%3\n"
" inswl %1,%4,%1\n"
@@ -63,7 +56,6 @@ ____xchg(_u16, volatile short *m, unsigned long val)
".previous"
: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
: "r" ((long)m), "1" (val) : "memory");
- smp_mb();
return ret;
}
@@ -73,7 +65,6 @@ ____xchg(_u32, volatile int *m, unsigned long val)
{
unsigned long dummy;
- smp_mb();
__asm__ __volatile__(
"1: ldl_l %0,%4\n"
" bis $31,%3,%1\n"
@@ -84,7 +75,6 @@ ____xchg(_u32, volatile int *m, unsigned long val)
".previous"
: "=&r" (val), "=&r" (dummy), "=m" (*m)
: "rI" (val), "m" (*m) : "memory");
- smp_mb();
return val;
}
@@ -94,7 +84,6 @@ ____xchg(_u64, volatile long *m, unsigned long val)
{
unsigned long dummy;
- smp_mb();
__asm__ __volatile__(
"1: ldq_l %0,%4\n"
" bis $31,%3,%1\n"
@@ -105,7 +94,6 @@ ____xchg(_u64, volatile long *m, unsigned long val)
".previous"
: "=&r" (val), "=&r" (dummy), "=m" (*m)
: "rI" (val), "m" (*m) : "memory");
- smp_mb();
return val;
}
@@ -135,13 +123,6 @@ ____xchg(, volatile void *ptr, unsigned long x, int size)
* Atomic compare and exchange. Compare OLD with MEM, if identical,
* store NEW in MEM. Return the initial value in MEM. Success is
* indicated by comparing RETURN with OLD.
- *
- * The leading and the trailing memory barriers guarantee that these
- * operations are fully ordered.
- *
- * The trailing memory barrier is placed in SMP unconditionally, in
- * order to guarantee that dependency ordering is preserved when a
- * dependency is headed by an unsuccessful operation.
*/
static inline unsigned long
@@ -149,7 +130,6 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
{
unsigned long prev, tmp, cmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %5,7,%4\n"
" insbl %1,%5,%1\n"
@@ -167,7 +147,6 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
".previous"
: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
: "r" ((long)m), "Ir" (old), "1" (new) : "memory");
- smp_mb();
return prev;
}
@@ -177,7 +156,6 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
{
unsigned long prev, tmp, cmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %5,7,%4\n"
" inswl %1,%5,%1\n"
@@ -195,7 +173,6 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
".previous"
: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
: "r" ((long)m), "Ir" (old), "1" (new) : "memory");
- smp_mb();
return prev;
}
@@ -205,7 +182,6 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
{
unsigned long prev, cmp;
- smp_mb();
__asm__ __volatile__(
"1: ldl_l %0,%5\n"
" cmpeq %0,%3,%1\n"
@@ -219,7 +195,6 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
".previous"
: "=&r"(prev), "=&r"(cmp), "=m"(*m)
: "r"((long) old), "r"(new), "m"(*m) : "memory");
- smp_mb();
return prev;
}
@@ -229,7 +204,6 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
{
unsigned long prev, cmp;
- smp_mb();
__asm__ __volatile__(
"1: ldq_l %0,%5\n"
" cmpeq %0,%3,%1\n"
@@ -243,7 +217,6 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
".previous"
: "=&r"(prev), "=&r"(cmp), "=m"(*m)
: "r"((long) old), "r"(new), "m"(*m) : "memory");
- smp_mb();
return prev;
}
diff --git a/arch/alpha/include/uapi/asm/mman.h b/arch/alpha/include/uapi/asm/mman.h
index 2dbdf59258d9..f9d4e6b6d4bd 100644
--- a/arch/alpha/include/uapi/asm/mman.h
+++ b/arch/alpha/include/uapi/asm/mman.h
@@ -32,6 +32,7 @@
#define MAP_NONBLOCK 0x40000 /* do not block on IO */
#define MAP_STACK 0x80000 /* give out an address that is best suited for process/thread stacks */
#define MAP_HUGETLB 0x100000 /* create a huge page mapping */
+#define MAP_FIXED_NOREPLACE 0x200000/* MAP_FIXED which doesn't unmap underlying mapping */
#define MS_ASYNC 1 /* sync memory asynchronously */
#define MS_SYNC 2 /* synchronous memory sync */
diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile
index bf7b41fa7b01..5a74581bf0ee 100644
--- a/arch/alpha/kernel/Makefile
+++ b/arch/alpha/kernel/Makefile
@@ -9,7 +9,7 @@ ccflags-y := -Wno-sign-compare
obj-y := entry.o traps.o process.o osf_sys.o irq.o \
irq_alpha.o signal.o setup.o ptrace.o time.o \
- systbls.o err_common.o io.o
+ systbls.o err_common.o io.o bugs.o
obj-$(CONFIG_VGA_HOSE) += console.o
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/alpha/kernel/bugs.c b/arch/alpha/kernel/bugs.c
new file mode 100644
index 000000000000..08cc10d7fa17
--- /dev/null
+++ b/arch/alpha/kernel/bugs.c
@@ -0,0 +1,45 @@
+
+#include <asm/hwrpb.h>
+#include <linux/device.h>
+
+
+#ifdef CONFIG_SYSFS
+
+static int cpu_is_ev6_or_later(void)
+{
+ struct percpu_struct *cpu;
+ unsigned long cputype;
+
+ cpu = (struct percpu_struct *)((char *)hwrpb + hwrpb->processor_offset);
+ cputype = cpu->type & 0xffffffff;
+ /* Include all of EV6, EV67, EV68, EV7, EV79 and EV69. */
+ return (cputype == EV6_CPU) || ((cputype >= EV67_CPU) && (cputype <= EV69_CPU));
+}
+
+ssize_t cpu_show_meltdown(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (cpu_is_ev6_or_later())
+ return sprintf(buf, "Vulnerable\n");
+ else
+ return sprintf(buf, "Not affected\n");
+}
+
+ssize_t cpu_show_spectre_v1(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (cpu_is_ev6_or_later())
+ return sprintf(buf, "Vulnerable\n");
+ else
+ return sprintf(buf, "Not affected\n");
+}
+
+ssize_t cpu_show_spectre_v2(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (cpu_is_ev6_or_later())
+ return sprintf(buf, "Vulnerable\n");
+ else
+ return sprintf(buf, "Not affected\n");
+}
+#endif
diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S
index d92abb01c249..c64806a2daf5 100644
--- a/arch/alpha/kernel/entry.S
+++ b/arch/alpha/kernel/entry.S
@@ -785,7 +785,6 @@ ret_from_kernel_thread:
mov $9, $27
mov $10, $16
jsr $26, ($9)
- mov $31, $19 /* to disable syscall restarts */
br $31, ret_to_user
.end ret_from_kernel_thread
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index fa1a392ca9a2..89faa6f4de47 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -189,7 +189,7 @@ SYSCALL_DEFINE6(osf_mmap, unsigned long, addr, unsigned long, len,
goto out;
if (off & ~PAGE_MASK)
goto out;
- ret = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ ret = ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
out:
return ret;
}
diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c
index b995987b1557..b6ebb65127a8 100644
--- a/arch/alpha/kernel/pci-noop.c
+++ b/arch/alpha/kernel/pci-noop.c
@@ -15,6 +15,7 @@
#include <linux/sched.h>
#include <linux/dma-mapping.h>
#include <linux/scatterlist.h>
+#include <linux/syscalls.h>
#include "proto.h"
@@ -46,8 +47,8 @@ alloc_resource(void)
return alloc_bootmem(sizeof(struct resource));
}
-asmlinkage long
-sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
+SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
+ unsigned long, dfn)
{
struct pci_controller *hose;
@@ -84,9 +85,8 @@ sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
return -EOPNOTSUPP;
}
-asmlinkage long
-sys_pciconfig_read(unsigned long bus, unsigned long dfn,
- unsigned long off, unsigned long len, void *buf)
+SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn,
+ unsigned long, off, unsigned long, len, void __user *, buf)
{
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
@@ -94,9 +94,8 @@ sys_pciconfig_read(unsigned long bus, unsigned long dfn,
return -ENODEV;
}
-asmlinkage long
-sys_pciconfig_write(unsigned long bus, unsigned long dfn,
- unsigned long off, unsigned long len, void *buf)
+SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn,
+ unsigned long, off, unsigned long, len, void __user *, buf)
{
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 2e86ebb680ae..c668c3b7a167 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/cache.h>
#include <linux/slab.h>
+#include <linux/syscalls.h>
#include <asm/machvec.h>
#include "proto.h"
@@ -409,8 +410,8 @@ alloc_resource(void)
/* Provide information on locations of various I/O regions in physical
memory. Do this on a per-card basis so that we choose the right hose. */
-asmlinkage long
-sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
+SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
+ unsigned long, dfn)
{
struct pci_controller *hose;
struct pci_dev *dev;
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index a1f6bc7f1e4c..5613aa378a83 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -351,7 +351,7 @@ static int collect_events(struct perf_event *group, int max_count,
evtype[n] = group->hw.event_base;
current_idx[n++] = PMC_NO_INDEX;
}
- list_for_each_entry(pe, &group->sibling_list, group_entry) {
+ for_each_sibling_event(pe, group) {
if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) {
if (n >= max_count)
return -1;
diff --git a/arch/alpha/kernel/rtc.c b/arch/alpha/kernel/rtc.c
index b3da0dcda47d..1376a2867048 100644
--- a/arch/alpha/kernel/rtc.c
+++ b/arch/alpha/kernel/rtc.c
@@ -97,7 +97,7 @@ alpha_rtc_read_time(struct device *dev, struct rtc_time *tm)
tm->tm_year = year;
}
- return rtc_valid_tm(tm);
+ return 0;
}
static int
@@ -115,83 +115,6 @@ alpha_rtc_set_time(struct device *dev, struct rtc_time *tm)
}
static int
-alpha_rtc_set_mmss(struct device *dev, time64_t nowtime)
-{
- int retval = 0;
- int real_seconds, real_minutes, cmos_minutes;
- unsigned char save_control, save_freq_select;
-
- /* Note: This code only updates minutes and seconds. Comments
- indicate this was to avoid messing with unknown time zones,
- and with the epoch nonsense described above. In order for
- this to work, the existing clock cannot be off by more than
- 15 minutes.
-
- ??? This choice is may be out of date. The x86 port does
- not have problems with timezones, and the epoch processing has
- now been fixed in alpha_set_rtc_time.
-
- In either case, one can always force a full rtc update with
- the userland hwclock program, so surely 15 minute accuracy
- is no real burden. */
-
- /* In order to set the CMOS clock precisely, we have to be called
- 500 ms after the second nowtime has started, because when
- nowtime is written into the registers of the CMOS clock, it will
- jump to the next second precisely 500 ms later. Check the Motorola
- MC146818A or Dallas DS12887 data sheet for details. */
-
- /* irq are locally disabled here */
- spin_lock(&rtc_lock);
- /* Tell the clock it's being set */
- save_control = CMOS_READ(RTC_CONTROL);
- CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
-
- /* Stop and reset prescaler */
- save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
- CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
-
- cmos_minutes = CMOS_READ(RTC_MINUTES);
- if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
- cmos_minutes = bcd2bin(cmos_minutes);
-
- real_seconds = nowtime % 60;
- real_minutes = nowtime / 60;
- if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1) {
- /* correct for half hour time zone */
- real_minutes += 30;
- }
- real_minutes %= 60;
-
- if (abs(real_minutes - cmos_minutes) < 30) {
- if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
- real_seconds = bin2bcd(real_seconds);
- real_minutes = bin2bcd(real_minutes);
- }
- CMOS_WRITE(real_seconds,RTC_SECONDS);
- CMOS_WRITE(real_minutes,RTC_MINUTES);
- } else {
- printk_once(KERN_NOTICE
- "set_rtc_mmss: can't update from %d to %d\n",
- cmos_minutes, real_minutes);
- retval = -1;
- }
-
- /* The following flags have to be released exactly in this order,
- * otherwise the DS12887 (popular MC146818A clone with integrated
- * battery and quartz) will not reset the oscillator and will not
- * update precisely 500 ms later. You won't find this mentioned in
- * the Dallas Semiconductor data sheets, but who believes data
- * sheets anyway ... -- Markus Kuhn
- */
- CMOS_WRITE(save_control, RTC_CONTROL);
- CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
- spin_unlock(&rtc_lock);
-
- return retval;
-}
-
-static int
alpha_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
@@ -210,7 +133,6 @@ alpha_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
static const struct rtc_class_ops alpha_rtc_ops = {
.read_time = alpha_rtc_read_time,
.set_time = alpha_rtc_set_time,
- .set_mmss64 = alpha_rtc_set_mmss,
.ioctl = alpha_rtc_ioctl,
};
@@ -225,7 +147,6 @@ static const struct rtc_class_ops alpha_rtc_ops = {
union remote_data {
struct rtc_time *tm;
- unsigned long now;
long retval;
};
@@ -267,29 +188,9 @@ remote_set_time(struct device *dev, struct rtc_time *tm)
return alpha_rtc_set_time(NULL, tm);
}
-static void
-do_remote_mmss(void *data)
-{
- union remote_data *x = data;
- x->retval = alpha_rtc_set_mmss(NULL, x->now);
-}
-
-static int
-remote_set_mmss(struct device *dev, time64_t now)
-{
- union remote_data x;
- if (smp_processor_id() != boot_cpuid) {
- x.now = now;
- smp_call_function_single(boot_cpuid, do_remote_mmss, &x, 1);
- return x.retval;
- }
- return alpha_rtc_set_mmss(NULL, now);
-}
-
static const struct rtc_class_ops remote_rtc_ops = {
.read_time = remote_read_time,
.set_time = remote_set_time,
- .set_mmss64 = remote_set_mmss,
.ioctl = alpha_rtc_ioctl,
};
#endif
diff --git a/arch/arc/boot/dts/Makefile b/arch/arc/boot/dts/Makefile
index 22a4c5d4702f..a83c4f5e928b 100644
--- a/arch/arc/boot/dts/Makefile
+++ b/arch/arc/boot/dts/Makefile
@@ -9,8 +9,6 @@ endif
obj-y += $(builtindtb-y).dtb.o
dtb-y := $(builtindtb-y).dtb
-.SECONDARY: $(obj)/$(builtindtb-y).dtb.S
-
# for CONFIG_OF_ALL_DTBS test
dtstree := $(srctree)/$(src)
dtb- := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index 6e9a0a9a6a04..783b20354f8b 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -10,7 +10,6 @@
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/kdev_t.h>
-#include <linux/fs_struct.h>
#include <linux/proc_fs.h>
#include <linux/file.h>
#include <linux/sched/mm.h>
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 2072f3451e9c..9dbe645ee127 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -833,7 +833,7 @@ void flush_dcache_page(struct page *page)
}
/* don't handle anon pages here */
- mapping = page_mapping(page);
+ mapping = page_mapping_file(page);
if (!mapping)
return;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7e3d53575486..a7f8e7f4b88f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -7,6 +7,7 @@ config ARM
select ARCH_HAS_DEBUG_VIRTUAL if MMU
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
+ select ARCH_HAS_FORTIFY_SOURCE
select ARCH_HAS_SET_MEMORY
select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
@@ -709,8 +710,6 @@ config ARCH_VIRT
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
-source "arch/arm/mach-mvebu/Kconfig"
-
source "arch/arm/mach-actions/Kconfig"
source "arch/arm/mach-alpine/Kconfig"
@@ -719,6 +718,8 @@ source "arch/arm/mach-artpec/Kconfig"
source "arch/arm/mach-asm9260/Kconfig"
+source "arch/arm/mach-aspeed/Kconfig"
+
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-axxia/Kconfig"
@@ -739,6 +740,9 @@ source "arch/arm/mach-dove/Kconfig"
source "arch/arm/mach-ep93xx/Kconfig"
+source "arch/arm/mach-exynos/Kconfig"
+source "arch/arm/plat-samsung/Kconfig"
+
source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
@@ -747,31 +751,33 @@ source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
+
source "arch/arm/mach-integrator/Kconfig"
+source "arch/arm/mach-iop13xx/Kconfig"
+
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-iop33x/Kconfig"
-source "arch/arm/mach-iop13xx/Kconfig"
-
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
+source "arch/arm/mach-mediatek/Kconfig"
+
source "arch/arm/mach-meson/Kconfig"
-source "arch/arm/mach-moxart/Kconfig"
+source "arch/arm/mach-mmp/Kconfig"
-source "arch/arm/mach-aspeed/Kconfig"
+source "arch/arm/mach-moxart/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
-source "arch/arm/mach-imx/Kconfig"
-
-source "arch/arm/mach-mediatek/Kconfig"
+source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
@@ -779,6 +785,8 @@ source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/mach-npcm/Kconfig"
+
source "arch/arm/mach-nspire/Kconfig"
source "arch/arm/plat-omap/Kconfig"
@@ -789,23 +797,31 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
+source "arch/arm/mach-oxnas/Kconfig"
+
source "arch/arm/mach-picoxcell/Kconfig"
+source "arch/arm/mach-prima2/Kconfig"
+
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
-source "arch/arm/mach-mmp/Kconfig"
-
-source "arch/arm/mach-oxnas/Kconfig"
-
source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
+source "arch/arm/mach-s3c24xx/Kconfig"
+
+source "arch/arm/mach-s3c64xx/Kconfig"
+
+source "arch/arm/mach-s5pv210/Kconfig"
+
source "arch/arm/mach-sa1100/Kconfig"
+source "arch/arm/mach-shmobile/Kconfig"
+
source "arch/arm/mach-socfpga/Kconfig"
source "arch/arm/mach-spear/Kconfig"
@@ -814,21 +830,8 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
-source "arch/arm/mach-s3c24xx/Kconfig"
-
-source "arch/arm/mach-s3c64xx/Kconfig"
-
-source "arch/arm/mach-s5pv210/Kconfig"
-
-source "arch/arm/mach-exynos/Kconfig"
-source "arch/arm/plat-samsung/Kconfig"
-
-source "arch/arm/mach-shmobile/Kconfig"
-
source "arch/arm/mach-sunxi/Kconfig"
-source "arch/arm/mach-prima2/Kconfig"
-
source "arch/arm/mach-tango/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 78a647080ebc..199ebc1c4538 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -22,6 +22,7 @@ config ARM_PTDUMP_DEBUGFS
config DEBUG_WX
bool "Warn on W+X mappings at boot"
+ depends on MMU
select ARM_PTDUMP_CORE
---help---
Generate a warning if any W+X mappings are found at boot.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e83f5161fdd8..e4e537f27339 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -196,6 +196,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX) += netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
+machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_NSPIRE) += nspire
machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index a2ac3fe7dbf8..c16c1829a5e4 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -6,10 +6,7 @@
#include <linux/stddef.h> /* for NULL */
#include <linux/linkage.h>
#include <asm/string.h>
-
-extern unsigned long free_mem_ptr;
-extern unsigned long free_mem_end_ptr;
-extern void error(char *);
+#include "misc.h"
#define STATIC static
#define STATIC_RW_DATA /* non-static please */
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 16a8a804e958..e1e9a5dde853 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -22,9 +22,9 @@ unsigned int __machine_arch_type;
#include <linux/compiler.h> /* for inline */
#include <linux/types.h>
#include <linux/linkage.h>
+#include "misc.h"
static void putstr(const char *ptr);
-extern void error(char *x);
#include CONFIG_UNCOMPRESS_INCLUDE
@@ -128,12 +128,7 @@ asmlinkage void __div0(void)
error("Attempting division by 0!");
}
-unsigned long __stack_chk_guard;
-
-void __stack_chk_guard_setup(void)
-{
- __stack_chk_guard = 0x000a0dff;
-}
+const unsigned long __stack_chk_guard = 0x000a0dff;
void __stack_chk_fail(void)
{
@@ -150,8 +145,6 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
{
int ret;
- __stack_chk_guard_setup();
-
output_data = (unsigned char *)output_start;
free_mem_ptr = free_mem_ptr_p;
free_mem_end_ptr = free_mem_ptr_end_p;
@@ -167,3 +160,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
else
putstr(" done, booting the kernel.\n");
}
+
+void fortify_panic(const char *name)
+{
+ error("detected buffer overflow");
+}
diff --git a/arch/arm/boot/compressed/misc.h b/arch/arm/boot/compressed/misc.h
new file mode 100644
index 000000000000..c958dccd1d97
--- /dev/null
+++ b/arch/arm/boot/compressed/misc.h
@@ -0,0 +1,10 @@
+#ifndef MISC_H
+#define MISC_H
+
+#include <linux/compiler.h>
+
+void error(char *x) __noreturn;
+extern unsigned long free_mem_ptr;
+extern unsigned long free_mem_end_ptr;
+
+#endif
diff --git a/arch/arm/boot/compressed/string.c b/arch/arm/boot/compressed/string.c
index 13c90abc68d6..ade5079bebbf 100644
--- a/arch/arm/boot/compressed/string.c
+++ b/arch/arm/boot/compressed/string.c
@@ -121,6 +121,16 @@ char *strchr(const char *s, int c)
return (char *)s;
}
+char *strrchr(const char *s, int c)
+{
+ const char *last = NULL;
+ do {
+ if (*s == (char)c)
+ last = s;
+ } while (*s++);
+ return (char *)last;
+}
+
#undef memset
void *memset(void *s, int c, size_t count)
diff --git a/arch/arm/boot/deflate_xip_data.sh b/arch/arm/boot/deflate_xip_data.sh
index 1189598a25eb..b7fa67d2d9e3 100755
--- a/arch/arm/boot/deflate_xip_data.sh
+++ b/arch/arm/boot/deflate_xip_data.sh
@@ -30,7 +30,7 @@ esac
sym_val() {
# extract hex value for symbol in $1
- local val=$($NM "$VMLINUX" | sed -n "/ $1$/{s/ .*$//p;q}")
+ local val=$($NM "$VMLINUX" 2>/dev/null | sed -n "/ $1\$/{s/ .*$//p;q}")
[ "$val" ] || { echo "can't find $1 in $VMLINUX" 1>&2; exit 1; }
# convert from hex to decimal
echo $((0x$val))
@@ -45,15 +45,15 @@ data_start=$(($__data_loc - $base_offset))
data_end=$(($_edata_loc - $base_offset))
# Make sure data occupies the last part of the file.
-file_end=$(stat -c "%s" "$XIPIMAGE")
+file_end=$(${CONFIG_SHELL} "${srctree}/scripts/file-size.sh" "$XIPIMAGE")
if [ "$file_end" != "$data_end" ]; then
printf "end of xipImage doesn't match with _edata_loc (%#x vs %#x)\n" \
- $(($file_end + $base_offset)) $_edata_loc 2>&1
+ $(($file_end + $base_offset)) $_edata_loc 1>&2
exit 1;
fi
# be ready to clean up
-trap 'rm -f "$XIPIMAGE.tmp"' 0 1 2 3
+trap 'rm -f "$XIPIMAGE.tmp"; exit 1' 1 2 3
# substitute the data section by a compressed version
$DD if="$XIPIMAGE" count=$data_start iflag=count_bytes of="$XIPIMAGE.tmp"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ade7a38543dc..7e2424957809 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -163,7 +163,10 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
+ exynos4412-i9300.dtb \
+ exynos4412-i9305.dtb \
exynos4412-itop-elite.dtb \
+ exynos4412-n710x.dtb \
exynos4412-odroidu3.dtb \
exynos4412-odroidx.dtb \
exynos4412-odroidx2.dtb \
@@ -304,6 +307,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
+dtb-$(CONFIG_ARCH_NPCM7XX) += \
+ nuvoton-npcm750-evb.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_MACH_MESON8) += \
@@ -396,6 +401,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-icore-rqs.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
+ imx6dl-phytec-mira-rdk-nand.dtb \
imx6dl-phytec-pbab01.dtb \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
@@ -435,6 +441,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-dfi-fs700-m60.dtb \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
+ imx6q-dms-ba16.dtb \
imx6q-evi.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
@@ -465,6 +472,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-nitrogen6_max.dtb \
imx6q-nitrogen6_som2.dtb \
imx6q-novena.dtb \
+ imx6q-phytec-mira-rdk-emmc.dtb \
+ imx6q-phytec-mira-rdk-nand.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-pistachio.dtb \
imx6q-rex-pro.dtb \
@@ -494,6 +503,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-zii-rdu2.dtb \
imx6qp-nitrogen6_max.dtb \
imx6qp-nitrogen6_som2.dtb \
+ imx6qp-phytec-mira-rdk-nand.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb \
imx6qp-tx6qp-8037.dtb \
@@ -526,7 +536,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
- imx6ull-14x14-evk.dtb
+ imx6ull-14x14-evk.dtb \
+ imx6ull-colibri-eval-v3.dtb \
+ imx6ull-colibri-wifi-eval-v3.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
@@ -673,6 +685,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-lxm.dtb \
am335x-moxa-uc-8100-me-t.dtb \
am335x-nano.dtb \
+ am335x-pdu001.dtb \
am335x-pepper.dtb \
am335x-phycore-rdk.dtb \
am335x-shc.dtb \
@@ -752,6 +765,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
+ qcom-msm8974-samsung-klte.dtb \
qcom-msm8974-sony-xperia-castor.dtb \
qcom-msm8974-sony-xperia-honami.dtb \
qcom-mdm9615-wp8548-mangoh-green.dtb
@@ -784,6 +798,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
+ r8a7790-stout.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7792-blanche.dtb \
@@ -863,7 +878,7 @@ dtb-$(CONFIG_ARCH_STI) += \
stih410-b2120.dtb \
stih410-b2260.dtb \
stih418-b2199.dtb
-dtb-$(CONFIG_ARCH_STM32)+= \
+dtb-$(CONFIG_ARCH_STM32) += \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
stm32f746-disco.dtb \
@@ -871,7 +886,9 @@ dtb-$(CONFIG_ARCH_STM32)+= \
stm32429i-eval.dtb \
stm32746g-eval.dtb \
stm32h743i-eval.dtb \
- stm32h743i-disco.dtb
+ stm32h743i-disco.dtb \
+ stm32mp157c-ed1.dtb \
+ stm32mp157c-ev1.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
@@ -942,6 +959,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+ sun7i-a20-olimex-som204-evb.dtb \
+ sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
@@ -974,6 +993,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dtb \
sun8i-h2-plus-orangepi-r1.dtb \
+ sun8i-h2-plus-bananapi-m2-zero.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-beelink-x2.dtb \
@@ -1022,6 +1042,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
tegra114-tn7.dtb
dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-apalis-eval.dtb \
+ tegra124-apalis-v1.2-eval.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-nyan-blaze.dtb \
@@ -1047,6 +1068,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-sld8-ref.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += \
versatile-ab.dtb \
+ versatile-ab-ib2.dtb \
versatile-pb.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += \
vexpress-v2p-ca5s.dtb \
@@ -1062,12 +1084,18 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8750-apc8750.dtb \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
+ zynq-cc108.dtb \
zynq-microzed.dtb \
zynq-parallella.dtb \
zynq-zc702.dtb \
zynq-zc706.dtb \
+ zynq-zc770-xm010.dtb \
+ zynq-zc770-xm011.dtb \
+ zynq-zc770-xm012.dtb \
+ zynq-zc770-xm013.dtb \
zynq-zed.dtb \
- zynq-zybo.dtb
+ zynq-zybo.dtb \
+ zynq-zybo-z7.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \
armada-370-db.dtb \
armada-370-dlink-dns327l.dtb \
@@ -1129,6 +1157,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
+ aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-bmc-opp-witherspoon.dtb \
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 3f2480d05a3b..58baee158e64 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -342,7 +342,7 @@
};
baseboard_eeprom: baseboard_eeprom@50 {
- compatible = "at,24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts
new file mode 100644
index 000000000000..1ad530a39a95
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-pdu001.dts
@@ -0,0 +1,595 @@
+/*
+ * pdu001.dts
+ *
+ * EETS GmbH PDU001 board device tree file
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/leds-pca9532.h>
+
+/ {
+ model = "EETS,PDU001";
+ compatible = "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ };
+
+ lis3_reg: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lis3_reg";
+ regulator-boot-on;
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins_s0>;
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <16>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+
+ display-timings {
+ 240x320p16 {
+ clock-frequency = <6500000>;
+ hactive = <240>;
+ vactive = <320>;
+ hfront-porch = <6>;
+ hback-porch = <6>;
+ hsync-len = <1>;
+ vback-porch = <6>;
+ vfront-porch = <6>;
+ vsync-len = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <1>;
+ de-active = <0>;
+ };
+ };
+ };
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
+ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */
+ >;
+ };
+
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
+ AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
+ AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
+ AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */
+ AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Port 1 (emac0) */
+ AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */
+ AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */
+ AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */
+ AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
+ AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+ AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+ AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */
+ AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
+ AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
+ AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
+
+ /* Port 2 (emac1) */
+ AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */
+ AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */
+ AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */
+ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */
+ AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */
+ AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
+ AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
+ AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
+ AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
+ AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
+ AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */
+ AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */
+ AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ /* eMMC */
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ /* SD cardcage */
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ /* card change signal for frontpanel SD cardcage */
+ AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+ >;
+ };
+
+ lcd_pins_s0: lcd_pins_s0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
+ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
+ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
+ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
+ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
+ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
+ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
+ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
+ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
+ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
+ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
+ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
+ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
+ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
+ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
+ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
+ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
+ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
+ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
+ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
+ >;
+ };
+
+ dcan0_pins: pinmux_dcan0_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
+ AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ rs485-rts-active-high;
+ rs485-rts-delay = <0 0>;
+ linux,rs485-enabled-at-boot-time;
+
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+
+ m2_eeprom: m2_eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ status = "okay";
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+ clock-frequency = <100000>;
+
+ board_24aa025e48: board_24aa025e48@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ backplane_24aa025e48: backplane_24aa025e48@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+
+ pca9532: pca9532@60 {
+ compatible = "nxp,pca9532";
+ reg = <0x60>;
+ psc0 = <0x97>;
+ pwm0 = <0x80>;
+ psc1 = <0x97>;
+ pwm1 = <0x10>;
+
+ run.red@0 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ run.green@1 {
+ type = <PCA9532_TYPE_LED>;
+ default-state = "on";
+ };
+ s2.red@2 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ s2.green@3 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ s1.yellow@4 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ s1.green@5 {
+ type = <PCA9532_TYPE_LED>;
+ };
+ };
+
+ pca9530: pca9530@61 {
+ compatible = "nxp,pca9530";
+ reg = <0x61>;
+
+ tft-panel@0 {
+ type = <PCA9532_TYPE_LED>;
+ linux,default-trigger = "backlight";
+ default-state = "on";
+ };
+ };
+
+ mcp79400: mcp79400@6f {
+ compatible = "microchip,mcp7940x";
+ reg = <0x6f>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ ti,pindir-d0-out-d1-in;
+ status = "okay";
+
+ cfaf240320a032t {
+ compatible = "orisetech,otm3225a";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ // SPI mode 3
+ spi-cpol;
+ spi-cpha;
+ status = "okay";
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+/*
+ * Disable soc's rtc as we have no VBAT for it. This makes the board
+ * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
+ */
+&rtc {
+ status = "disabled";
+};
+
+&lcdc {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-name = "ldo_vrtc";
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-name = "buck_vdd_ddr";
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits */
+ regulator-name = "buck_vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits */
+ regulator-name = "buck_vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-name = "boost_res";
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-name = "ldo_vdig1";
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-name = "ldo_vdig2";
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-name = "ldo_vpll";
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-name = "ldo_vdac";
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-name = "ldo_vaux1";
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-name = "ldo_vaux2";
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-name = "ldo_vaux33";
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-name = "ldo_vmmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vbb_reg: regulator@13 {
+ regulator-name = "bat_vbb";
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+ dual_emac; /* no switch, two distinct MACs */
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <2>;
+};
+
+&tscadc {
+ status = "okay";
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,coordinate-readouts = <5>;
+ ti,wire-config = <0x01 0x10 0x22 0x33>;
+ ti,charge-delay = <0x400>;
+ };
+
+ adc {
+ ti,adc-channels = <4 5 6 7>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ non-removable;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&dcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan0_pins>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 628c77b0b386..9cd62bc2ca35 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -147,6 +147,8 @@
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
+ pm-sram = <&pm_sram_code
+ &pm_sram_data>;
};
};
@@ -905,6 +907,21 @@
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
+ ranges = <0x0 0x40300000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm_sram_code: pm-sram-code@0 {
+ compatible = "ti,sram";
+ reg = <0x0 0x1000>;
+ protect-exec;
+ };
+
+ pm_sram_data: pm-sram-data@1000 {
+ compatible = "ti,sram";
+ reg = <0x1000 0x1000>;
+ pool;
+ };
};
elm: elm@48080000 {
@@ -945,6 +962,10 @@
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
+ interrupts = <101>;
+ sram = <&pm_sram_code
+ &pm_sram_data>;
+ ti,no-idle;
};
gpmc: gpmc@50000000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 964f3ef79728..f0cbd86312dc 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -92,6 +92,16 @@
};
};
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap4-mpu";
+ ti,hwmods = "mpu";
+ pm-sram = <&pm_sram_code
+ &pm_sram_data>;
+ };
+ };
+
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
@@ -143,6 +153,7 @@
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
+ ti,no-idle;
reg = <0x44000000 0x400000
0x44800000 0x400000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
@@ -237,6 +248,10 @@
compatible = "ti,emif-am4372";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ ti,no-idle;
+ sram = <&pm_sram_code
+ &pm_sram_data>;
};
edma: edma@49000000 {
@@ -1141,6 +1156,21 @@
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */
+ ranges = <0x0 0x40300000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm_sram_code: pm-sram-code@0 {
+ compatible = "ti,sram";
+ reg = <0x0 0x1000>;
+ protect-exec;
+ };
+
+ pm_sram_data: pm-sram-data@1000 {
+ compatible = "ti,sram";
+ reg = <0x1000 0x1000>;
+ pool;
+ };
};
dcan0: can@481cc000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index c3b1a3fb5a2e..8fe95cd7232a 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -805,7 +805,7 @@
};
&usb1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
status = "okay";
};
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 3fa3b226995d..4118802b7fea 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -600,7 +600,7 @@
};
&usb1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 00c3d1de384f..a66941885c11 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -856,7 +856,7 @@
};
&usb1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
status = "okay";
};
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index 6d3c83743156..a2555140babc 100644
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -10,8 +10,8 @@
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include "am57xx-idk-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
+#include "am57xx-idk-common.dtsi"
/ {
model = "TI AM5718 IDK";
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index 9ab0af5017df..3a02ed720957 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -9,9 +9,8 @@
/dts-v1/;
#include "dra74x.dtsi"
-#include "am572x-idk-common.dtsi"
-#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
+#include "am572x-idk-common.dtsi"
/ {
model = "TI AM5728 IDK";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index ab60035bc50c..6204a266212a 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -442,6 +442,7 @@
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_3v3>;
bus-width = <8>;
ti,non-removable;
cap-mmc-dual-data-rate;
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 97aa8e6a56da..43cdf523a8a0 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -115,6 +115,17 @@
DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
>;
};
+
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
};
&i2c1 {
@@ -410,6 +421,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&v3_3d>;
+ vqmmc-supply = <&v3_3d>;
bus-width = <8>;
ti,non-removable;
max-frequency = <96000000>;
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index b67a75179784..d7c841932701 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -24,7 +24,7 @@
};
chosen {
- linux,stdout-path = &usart2;
+ stdout-path = &usart2;
};
memory {
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index e2e9599596e2..a917cf8825ca 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -143,6 +143,43 @@
port1-otg;
};
+ bridge {
+ compatible = "ti,ths8134a", "ti,ths8134";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+
/* These peripherals are inside the FPGA */
fpga {
#address-cells = <1>;
@@ -409,36 +446,15 @@
interrupt-names = "combined";
clocks = <&oscclk0>, <&pclk>;
clock-names = "clcdclk", "apb_pclk";
+ /* 1024x768 16bpp @65MHz works fine */
+ max-memory-bandwidth = <95000000>;
port {
clcd_pads: endpoint {
- remote-endpoint = <&clcd_panel>;
+ remote-endpoint = <&vga_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
-
- panel {
- compatible = "panel-dpi";
-
- port {
- clcd_panel: endpoint {
- remote-endpoint = <&clcd_pads>;
- };
- };
-
- /* Standard 640x480 VGA timings */
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- hback-porch = <48>;
- hfront-porch = <16>;
- hsync-len = <96>;
- vactive = <480>;
- vback-porch = <33>;
- vfront-porch = <10>;
- vsync-len = <2>;
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index c789564f2803..f935b72d3d96 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -161,6 +161,43 @@
port1-otg;
};
+ bridge {
+ compatible = "ti,ths8134a", "ti,ths8134";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -403,36 +440,15 @@
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk0>, <&pclk>;
clock-names = "clcdclk", "apb_pclk";
+ /* 1024x768 16bpp @65MHz works fine */
+ max-memory-bandwidth = <95000000>;
port {
clcd_pads: endpoint {
- remote-endpoint = <&clcd_panel>;
+ remote-endpoint = <&vga_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
-
- panel {
- compatible = "panel-dpi";
-
- port {
- clcd_panel: endpoint {
- remote-endpoint = <&clcd_pads>;
- };
- };
-
- /* Standard 640x480 VGA timings */
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- hback-porch = <48>;
- hfront-porch = <16>;
- hsync-len = <96>;
- vactive = <480>;
- vback-porch = <33>;
- vfront-porch = <10>;
- vsync-len = <2>;
- };
- };
};
};
@@ -564,7 +580,5 @@
clocks = <&pclk>;
clock-names = "apb_pclk";
};
-
-
};
};
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index 3944765ac4b0..36203288de42 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -242,6 +242,49 @@
bank-width = <4>;
};
+ bridge {
+ compatible = "ti,ths8134a", "ti,ths8134";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ /*
+ * This DDC I2C is connected directly to the DVI portions
+ * of the connector, so it's not really working when the
+ * monitor is connected to the VGA connector.
+ */
+ compatible = "vga-connector";
+ ddc-i2c-bus = <&i2c1>;
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -575,6 +618,13 @@
clock-names = "apb_pclk";
};
+ i2c1: i2c@10016000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "arm,versatile-i2c";
+ reg = <0x10016000 0x1000>;
+ };
+
rtc: rtc@10017000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x10017000 0x1000>;
@@ -609,37 +659,15 @@
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk4>, <&pclk>;
clock-names = "clcdclk", "apb_pclk";
- max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
+ /* 1024x768 16bpp @65MHz works fine */
+ max-memory-bandwidth = <95000000>;
port {
clcd_pads: endpoint {
- remote-endpoint = <&clcd_panel>;
+ remote-endpoint = <&vga_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
-
- panel {
- compatible = "panel-dpi";
-
- port {
- clcd_panel: endpoint {
- remote-endpoint = <&clcd_pads>;
- };
- };
-
- /* Standard 640x480 VGA timings */
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- hback-porch = <48>;
- hfront-porch = <16>;
- hsync-len = <96>;
- vactive = <480>;
- vback-porch = <33>;
- vfront-porch = <10>;
- vsync-len = <2>;
- };
- };
};
/*
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index aeb49c4bd773..10868ba3277f 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -34,7 +34,8 @@
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
- i2c0 = &i2c;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
};
memory {
@@ -158,6 +159,49 @@
port1-otg;
};
+ bridge {
+ compatible = "ti,ths8134a", "ti,ths8134";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ /*
+ * This DDC I2C is connected directly to the DVI portions
+ * of the connector, so it's not really working when the
+ * monitor is connected to the VGA connector.
+ */
+ compatible = "vga-connector";
+ ddc-i2c-bus = <&i2c1>;
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+
soc: soc@0 {
compatible = "arm,realview-pbx-soc", "simple-bus";
#address-cells = <1>;
@@ -285,7 +329,7 @@
<&timclk>;
};
- i2c: i2c@10002000 {
+ i2c0: i2c@10002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,versatile-i2c";
@@ -396,7 +440,12 @@
clock-names = "apb_pclk";
};
- /* DVI serial bus control is at 10016000 */
+ i2c1: i2c@10016000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "arm,versatile-i2c";
+ reg = <0x10016000 0x1000>;
+ };
rtc: rtc@10017000 {
compatible = "arm,pl031", "arm,primecell";
@@ -506,36 +555,15 @@
interrupt-names = "combined";
clocks = <&oscclk4>, <&pclk>;
clock-names = "clcdclk", "apb_pclk";
+ /* 1024x768 16bpp @65MHz works fine */
+ max-memory-bandwidth = <95000000>;
port {
clcd_pads: endpoint {
- remote-endpoint = <&clcd_panel>;
+ remote-endpoint = <&vga_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
-
- panel {
- compatible = "panel-dpi";
-
- port {
- clcd_panel: endpoint {
- remote-endpoint = <&clcd_pads>;
- };
- };
-
- /* Standard 640x480 VGA timings */
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- hback-porch = <48>;
- hfront-porch = <16>;
- hsync-len = <96>;
- vactive = <480>;
- vback-porch = <33>;
- vfront-porch = <10>;
- vsync-len = <2>;
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index c4eef7323367..afe46097a403 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 370 evaluation board
* (DB-88F6710-BP-DDR3)
@@ -8,44 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
index db7f3aa38670..8e46f63cbaa1 100644
--- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
+++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for D-Link DNS-327L
*
* Copyright (C) 2015, Andrew Andrianov <andrew@ncrmnt.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/* Remaining unsolved:
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 702f58c9642d..996f31b00729 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Mirabox
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index b1a96e95e921..56634803e16b 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NETGEAR ReadyNAS 102
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -103,7 +66,7 @@
status = "okay";
- isl12057: isl12057@68 {
+ isl12057: rtc@68 {
compatible = "isil,isl12057";
reg = <0x68>;
wakeup-source;
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index d67e7aa42b54..16d0307f786a 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NETGEAR ReadyNAS 104
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -105,7 +68,7 @@
status = "okay";
- isl12057: isl12057@68 {
+ isl12057: rtc@68 {
compatible = "isil,isl12057";
reg = <0x68>;
wakeup-source;
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 8b2fa9a49967..cc2f774eb267 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 370 Reference Design board
* (RD-88F6710-A1)
@@ -6,44 +7,6 @@
*
* Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
@@ -56,6 +19,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"
@@ -243,6 +207,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
ports {
#address-cells = <1>;
@@ -278,6 +244,35 @@
};
};
};
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switchphy0: switchphy@0 {
+ reg = <0>;
+ interrupt-parent = <&switch>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy1: switchphy@1 {
+ reg = <1>;
+ interrupt-parent = <&switch>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy2: switchphy@2 {
+ reg = <2>;
+ interrupt-parent = <&switch>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switchphy3: switchphy@3 {
+ reg = <3>;
+ interrupt-parent = <&switch>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
index fef0110a8d8a..8dd242e668e6 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/*
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
index eb6af53b4954..3cf70c72c5ca 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/*
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
index e9a5b952afc0..a5206db0ebbd 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/*
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
index 3c91f9821c89..5ee572dc9242 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/*
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
index aad39e97af43..578b54b39c8f 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/*
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
index d079a89ee5a2..a624b2371fb6 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
* (Armada 370 SoC).
@@ -5,10 +6,6 @@
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/*
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index 95040810c094..64f2ce254fb6 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Synology DS213j
*
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 09495e87b038..11fc3271dad4 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
*
@@ -8,44 +9,6 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* This file contains the definitions that are common to the Armada
* 370 and Armada XP SoC.
*/
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index b1cf5a26f3c2..46e6d3ed8f35 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 370 family SoC
*
@@ -7,44 +8,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada 370 SoC that are not
* common to all Armada SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index bcdbb8ba1d65..e4ecd7e75644 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 375 evaluation board
* (DB-88F6720)
@@ -6,44 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 2cb1bcd30976..53ead6f26a0e 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 375 family SoC
*
@@ -5,44 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index 132596fd0860..cff1269f3fbf 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
index 678aa023335d..d294f24281a5 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 385 Access Point Development board
* (DB-88F6820-AP)
@@ -5,38 +6,6 @@
* Copyright (C) 2014 Marvell
*
* Nadav Haklai <nadavh@marvell.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
index ee669ae61011..1f30993af405 100644
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -1,40 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree include for the Linksys WRT1200AC (Caiman)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
index 5169ca89c55a..bc34802ce6bc 100644
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -1,40 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for the Linksys WRT1900ACv2 (Cobra)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/armada-385-linksys-rango.dts
index da8a0f3d432b..5b745a0ccce5 100644
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -1,40 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for the Linksys WRT3200ACM (Rango)
*
* Copyright (C) 2016 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
index 94aa35bc0bff..44f5aeb5fc33 100644
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -1,40 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for the Linksys WRT1900ACS (Shelby)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index 434dc9aaa5e4..4a0d7360110b 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -1,40 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree include file for Armada 385 based Linksys boards
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -282,3 +250,8 @@
status = "okay";
usb-phy = <&usb3_1_phy>;
};
+
+&rtc {
+ /* No crystal connected to the internal RTC */
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts
index 0a3552ebda3b..6782ce481ac9 100644
--- a/arch/arm/boot/dts/armada-385-synology-ds116.dts
+++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts
@@ -1,39 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Synology DS116 NAS
*
* Copyright (C) 2017 Willy Tarreau <w@1wt.eu>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
index 06831e1e3f80..768b6c5d2129 100644
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -1,43 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for the Turris Omnia
*
* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
*/
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 74863aff01c6..f0022d10c715 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
index 22ed07fc2979..50ed4ae5c621 100644
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
*
@@ -7,43 +8,6 @@
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/armada-388-clearfog-pro.dts
index bd85870bbdbb..24e4b5a509be 100644
--- a/arch/arm/boot/dts/armada-388-clearfog-pro.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-pro.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
*
@@ -7,43 +8,6 @@
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-388-clearfog.dts"
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index ee7b0089eff0..5fd0f6f61e77 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
*
@@ -7,43 +8,6 @@
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 68acfc968706..0d9dfdfe977e 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree include file for SolidRun Clearfog 88F6828 based boards
*
@@ -7,43 +8,6 @@
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-388.dtsi"
@@ -117,6 +81,16 @@
};
};
};
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
};
&eth1 {
@@ -133,18 +107,14 @@
bm,pool-long = <3>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
+ managed = "in-band-status";
phy-mode = "sgmii";
+ sfp = <&sfp>;
status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
};
&i2c0 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
@@ -209,43 +179,13 @@
output-low;
line-name = "m.2 devslp";
};
- sfp_los {
- /* SFP loss of signal */
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-los";
- };
- sfp_tx_fault {
- /* SFP laser fault */
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-tx-fault";
- };
- sfp_tx_disable {
- /* SFP transmit disable */
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "sfp-tx-disable";
- };
- sfp_mod_def0 {
- /* SFP module present */
- gpio-hog;
- gpios = <15 GPIO_ACTIVE_LOW>;
- input;
- line-name = "sfp-mod-def0";
- };
};
- /* The MCP3021 is 100kHz clock only */
+ /* The MCP3021 supports standard and fast modes */
mikrobus_adc: mcp3021@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
-
- /* Also something at 0x64 */
};
&i2c1 {
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index a4ec1fa37529..05250d426dc4 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 388 evaluation board
* (DB-88F6820)
@@ -5,44 +6,6 @@
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 51b4ee6df130..9d873257ac45 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 385 development board
* (RD-88F6820-GP)
@@ -5,38 +6,6 @@
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index 9cc3ca0376b9..328a4d6afd2c 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 388 Reference Design board
* (RD-88F6820-AP)
@@ -6,44 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
index 1c0d151b2aaa..f3a020ff577e 100644
--- a/arch/arm/boot/dts/armada-388.dtsi
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 388 SoC.
*
@@ -5,39 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- *
* The main difference with the Armada 385 is that the 388 can handle two more
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
* property and the name of the SoC, and add the second SATA host which control
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 9b508a8161f5..2d1cea131e71 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for SolidRun Armada 38x Microsom
*
@@ -7,43 +8,6 @@
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index a6cc568f74f7..4cc09e43eea2 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts
index c718a5242595..1b2362e4c831 100644
--- a/arch/arm/boot/dts/armada-390-db.dts
+++ b/arch/arm/boot/dts/armada-390-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 390 Development Board
* (DB-88F6920)
@@ -5,44 +6,6 @@
* Copyright (C) 2016 Marvell
*
* Grzegorz Jaszczyk <jaz@semihalf.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
index 0d8a54ad007c..aa2057d4d6f8 100644
--- a/arch/arm/boot/dts/armada-390.dtsi
+++ b/arch/arm/boot/dts/armada-390.dtsi
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 390 SoC.
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-39x.dtsi"
diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/armada-395-gp.dts
index ef491b524fd6..2a9de192b423 100644
--- a/arch/arm/boot/dts/armada-395-gp.dts
+++ b/arch/arm/boot/dts/armada-395-gp.dts
@@ -1,41 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 395 GP board
*
* Copyright (C) 2016 Marvell
*
* Grzegorz Jaszczyk <jaz@semihalf.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-395.dtsi b/arch/arm/boot/dts/armada-395.dtsi
index bf7e4335e36a..e18a7d9cd7d4 100644
--- a/arch/arm/boot/dts/armada-395.dtsi
+++ b/arch/arm/boot/dts/armada-395.dtsi
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 395 SoC.
*
* Copyright (C) 2016 Marvell
*
* Grzegorz Jaszczyk <jaz@semihalf.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-39x.dtsi"
diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
index f0e0379f7619..2337f24784f7 100644
--- a/arch/arm/boot/dts/armada-398-db.dts
+++ b/arch/arm/boot/dts/armada-398-db.dts
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 398 Development Board
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
index 1f4e113fc821..c5ac89399ce1 100644
--- a/arch/arm/boot/dts/armada-398.dtsi
+++ b/arch/arm/boot/dts/armada-398.dtsi
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 398 SoC.
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-395.dtsi"
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index 5218bd2a248d..c1737c0a8325 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 39x family of SoCs.
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index bdd4c7a45fbf..a5da44fb35ed 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx3236 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the 98dx3236 SoC that are not
* common to all Armada XP SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
index a0d81bd7312b..2f5fc67dd6dc 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx3336 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the 98dx3236 SoC that are not
* common to all Armada XP SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index bc9f824020eb..7a9e8839880b 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx4521 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the 98dx4521 SoC that are not
* common to all Armada XP SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index d0c6a01f48a6..606fd3476a59 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell RD-AXPWiFiAP.
*
@@ -9,44 +10,6 @@
* Copyright (C) 2013 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
index 1b1ff17fdd9c..4c64923f1c52 100644
--- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
+++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for DB-DXBC2 board
*
@@ -5,44 +6,6 @@
*
* Based on armada-xp-db.dts
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 06fce35d7491..a0ebb52683f1 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for DB-XC3-24G4XG board
*
@@ -5,44 +6,6 @@
*
* Based on armada-xp-db.dts
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 065282c21789..73d3f5cb9828 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada XP evaluation board
* (DB-78460-BP)
@@ -8,43 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index ac9eab8ac186..c143556bbb7b 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada XP development board
* (DB-MV784MP-GP)
@@ -8,44 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index ce0afba1ce58..def62e9e835b 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Lenovo Iomega ix4-300d
*
* Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 6d705f518254..f8b60d937818 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for the Linksys WRT1900AC (Mamba).
*
@@ -13,38 +14,6 @@
* Copyright (C) 2013 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 977f6b3fc1f8..1395cea12759 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada XP Matrix board
*
* Copyright (C) 2013 Marvell
*
* Lior Amsalem <alior@marvell.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 129738f7973d..8558bf6bb54c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP MV78230 SoC that are not
* common to all Armada XP SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index e58d597e37b9..2d85fe8ac327 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP MV78260 SoC that are not
* common to all Armada XP SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index a5c961cee7de..230a3fd36b30 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP MV78460 SoC that are not
* common to all Armada XP SoCs.
*/
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 40c6fe21e720..c350b1cf5201 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NETGEAR ReadyNAS 2120
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -115,7 +78,7 @@
reg = <0x4c>;
};
- isl12057: isl12057@68 {
+ isl12057: rtc@68 {
compatible = "isil,isl12057";
reg = <0x68>;
wakeup-source;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 66b78131a038..0efcc166dabf 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for OpenBlocks AX3-4 board
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index d7228a5461c8..809e821d7399 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Synology DS414
*
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index fa1e881266ac..ee15c77d3689 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -8,44 +9,6 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP SoC that are not
* common to all Armada SoCs.
*/
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
index 9dfe845694cf..d20d95359b28 100644
--- a/arch/arm/boot/dts/artpec6-devboard.dts
+++ b/arch/arm/boot/dts/artpec6-devboard.dts
@@ -26,7 +26,7 @@
memory {
device_type = "memory";
- reg = <0x0 0x10000000>;
+ reg = <0x0 0x40000000>;
};
};
@@ -59,6 +59,7 @@
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
+ compatible = "snps,dwmac-mdio";
phy1: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 2ed11773048d..3e4115c2cd75 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -41,6 +41,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/dma/nbpfaxi.h>
#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
#include "skeleton.dtsi"
@@ -98,7 +99,7 @@
clock-frequency = <125000000>;
};
- clkctrl: clkctrl@0xf8000000 {
+ clkctrl: clkctrl@f8000000 {
#clock-cells = <1>;
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
@@ -153,6 +154,10 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+ /*
+ * Both pci nodes cannot be enabled at the same time,
+ * leave the unwanted node as disabled.
+ */
pcie: pcie@f8050000 {
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
reg = <0xf8050000 0x2000
@@ -180,28 +185,146 @@
status = "disabled";
};
+ pcie_ep: pcie_ep@f8050000 {
+ compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
+ reg = <0xf8050000 0x2000
+ 0xf8051000 0x2000
+ 0xf8040000 0x1000
+ 0xc0000000 0x20000000>;
+ reg-names = "dbi", "dbi2", "phy", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ num-lanes = <2>;
+ axis,syscon-pcie = <&syscon>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@f801d000 {
+ compatible = "axis,artpec6-pinctrl";
+ reg = <0xf801d000 0x400>;
+
+ pinctrl_uart0: uart0grp {
+ function = "uart0";
+ groups = "uart0grp2";
+ bias-pull-up;
+ };
+ pinctrl_uart1: uart1grp {
+ function = "uart1";
+ groups = "uart1grp0";
+ bias-pull-up;
+ };
+ pinctrl_uart2: uart2grp {
+ function = "uart2";
+ groups = "uart2grp1";
+ bias-pull-up;
+ };
+ pinctrl_uart3: uart3grp {
+ function = "uart3";
+ groups = "uart3grp0";
+ bias-pull-up;
+ };
+ };
+
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
- dma-ranges = <0x80000000 0x00000000 0x40000000>;
- dma-coherent;
+ dma-ranges;
+
+ crypto@f4264000 {
+ compatible = "axis,artpec6-crypto";
+ reg = <0xf4264000 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma0: dma@f8019000 {
+ compatible = "renesas,nbpfaxi64dmac8b16";
+ reg = <0xf8019000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch12",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
+ #dma-cells = <2>;
+ dma-channels = <8>;
+ dma-requests = <8>;
+ };
+ dma1: dma@f8019400 {
+ compatible = "renesas,nbpfaxi64dmac8b16";
+ reg = <0xf8019400 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch12",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
+ #dma-cells = <2>;
+ dma-channels = <8>;
+ dma-requests = <8>;
+ };
ethernet: ethernet@f8010000 {
- clock-names = "phy_ref_clk", "apb_pclk";
- clocks = <&eth_phy_ref_clk>,
- <&clkctrl ARTPEC6_CLK_ETH_ACLK>;
- compatible = "snps,dwc-qos-ethernet-4.10";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "stmmaceth", "ptp_ref";
+ clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
+ <&clkctrl ARTPEC6_CLK_PTP_REF>;
+ compatible = "snps,dwmac-4.10a", "snps,dwmac";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
reg = <0xf8010000 0x4000>;
- snps,write-requests = <2>;
- snps,read-requests = <16>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+
snps,txpbl = <8>;
snps,rxpbl = <2>;
+ snps,aal;
+ snps,tso;
status = "disabled";
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <1>;
+ snps,rd_osr_lmt = <15>;
+ /* If FB is disabled, the AXI master chooses
+ * a burst length of any value less than the
+ * maximum enabled burst length
+ * (all lesser burst length enables are redundant).
+ */
+ snps,blen = <0 0 0 0 16 0 0>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
};
uart0: serial@f8036000 {
@@ -211,6 +334,11 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+ <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+ dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@f8037000 {
@@ -220,6 +348,11 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+ <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+ dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@f8038000 {
@@ -229,6 +362,11 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+ <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+ dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@f8039000 {
@@ -238,6 +376,11 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+ <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+ dma-names = "rx", "tx";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
new file mode 100644
index 000000000000..df1227613d48
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Qualcomm Centriq 2400 REP AST2520";
+ compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 7>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ uid_led {
+ label = "UID_LED";
+ gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ ras_error_led {
+ label = "RAS_ERROR_LED";
+ gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ system_fault {
+ label = "System_fault";
+ gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+ flash@0 {
+ status = "okay";
+ };
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2ck_default
+ &pinctrl_spi2miso_default
+ &pinctrl_spi2mosi_default
+ &pinctrl_spi2cs0_default>;
+};
+
+&uart3 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
+ current-speed = <115200>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ tmp421@1e {
+ compatible = "ti,tmp421";
+ reg = <0x1e>;
+ };
+ tmp421@2a {
+ compatible = "ti,tmp421";
+ reg = <0x2a>;
+ };
+ tmp421@4e {
+ compatible = "ti,tmp421";
+ reg = <0x4e>;
+ };
+ tmp421@1c {
+ compatible = "ti,tmp421";
+ reg = <0x1c>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ tmp421@1d {
+ compatible = "ti,tmp421";
+ reg = <0x1d>;
+ };
+ tmp421@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ tmp421@4d {
+ compatible = "ti,tmp421";
+ reg = <0x4d>;
+ };
+ tmp421@4f {
+ compatible = "ti,tmp421";
+ reg = <0x4f>;
+ };
+ nvt210@4c {
+ compatible = "nvt210";
+ reg = <0x4c>;
+ };
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+
+ pca9641@70 {
+ compatible = "nxp,pca9641";
+ reg = <0x70>;
+ i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ tmp421@1d {
+ compatible = "tmp421";
+ reg = <0x1d>;
+ };
+ adm1278@12 {
+ compatible = "adi,adm1278";
+ reg = <0x12>;
+ Rsense = <500>;
+ };
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+ ds1100@58 {
+ compatible = "ds1100";
+ reg = <0x58>;
+ };
+ };
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&gpio {
+ pin_gpio_c7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "BIOS_SPI_MUX_S";
+ };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 4379d09a261f..c7084a819dc6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "aspeed-g4.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Palmetto BMC";
@@ -26,6 +27,32 @@
reg = <0x5f000000 0x01000000>; /* 16M */
};
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ power {
+ gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(P, 5)>;
+ };
+ };
};
&fmc {
@@ -40,6 +67,9 @@
&spi {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1debug_default>;
+
flash@0 {
status = "okay";
m25p,fast-read;
@@ -47,6 +77,29 @@
};
};
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
+
+ &pinctrl_vgahs_default &pinctrl_vgavs_default
+ &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
&uart5 {
status = "okay";
};
@@ -111,3 +164,156 @@
&vuart {
status = "okay";
};
+
+&ibt {
+ status = "okay";
+};
+
+&gpio {
+ pin_func_mode0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(C, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "func_mode0";
+ };
+
+ pin_func_mode1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(C, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "func_mode1";
+ };
+
+ pin_func_mode2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "func_mode2";
+ };
+
+ pin_gpio_a0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_FAN_RESERVED_N";
+ };
+
+ pin_gpio_a1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "APSS_WDT_N";
+ };
+
+ pin_gpio_b1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "APSS_BOOT_MODE";
+ };
+
+ pin_gpio_b2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "APSS_RESET_N";
+ };
+
+ pin_gpio_b7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SPIVID_STBY_RESET_N";
+ };
+
+ pin_gpio_d1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_POWER_UP";
+ };
+
+ pin_gpio_f1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_BATTERY_TEST";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "AST_HW_FAULT_N";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "AST_SYS_FAULT_N";
+ };
+
+ pin_gpio_f7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_FULL_SPEED_N";
+ };
+
+ pin_gpio_g3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_FAN_ERROR_N";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_WDT_RST1_P";
+ };
+
+ pin_gpio_g5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_WDT_RST2_P";
+ };
+
+ pin_gpio_h0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "PE_SLOT_TEST_EN_N";
+ };
+
+ pin_gpio_h1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "BMC_RTCRST_N";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SYS_PWROK_BMC";
+ };
+
+ pin_gpio_h6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SCM1_FSI0_DATA_EN";
+ };
+
+ pin_gpio_h7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_TPM_INT_N";
+ };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 623b6ab42021..51bc6a2e9dd5 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -184,9 +184,9 @@
&i2c12 {
status = "okay";
- max31785@52 {
- compatible = "maxim,max31785";
- reg = <0x52>;
+ w83773g@4c {
+ compatible = "nuvoton,w83773g";
+ reg = <0x4c>;
};
};
@@ -203,6 +203,12 @@
output-low;
line-name = "nic_func_mode1";
};
+ seq_cont {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "seq_cont";
+ };
};
&vuart {
@@ -257,3 +263,7 @@
aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
};
};
+
+&ibt {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 5f9049d2c4c3..7056231cbee6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -546,3 +546,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
};
+
+&ibt {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index c881484a85cf..ebe726a0d311 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -424,3 +424,7 @@
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
};
+
+&ibt {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b0d8431a3700..518d2bc7c7fc 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -42,6 +42,11 @@
};
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0>;
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -162,6 +167,7 @@
reg-shift = <2>;
interrupts = <9>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
+ resets = <&lpc_reset 4>;
no-loopback-test;
status = "disabled";
};
@@ -233,6 +239,7 @@
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@@ -247,6 +254,19 @@
compatible = "aspeed,ast2400-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
+
+ lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2400-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@c0 {
+ compatible = "aspeed,ast2400-ibt-bmc";
+ reg = <0xc0 0x18>;
+ interrupts = <8>;
+ status = "disabled";
+ };
};
};
@@ -256,6 +276,7 @@
reg-shift = <2>;
interrupts = <32>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
+ resets = <&lpc_reset 5>;
no-loopback-test;
status = "disabled";
};
@@ -266,6 +287,7 @@
reg-shift = <2>;
interrupts = <33>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
+ resets = <&lpc_reset 6>;
no-loopback-test;
status = "disabled";
};
@@ -276,6 +298,7 @@
reg-shift = <2>;
interrupts = <34>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
+ resets = <&lpc_reset 7>;
no-loopback-test;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 40de3b66c33f..f9917717dd08 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -42,6 +42,11 @@
};
};
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>;
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -205,6 +210,7 @@
reg-shift = <2>;
interrupts = <9>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
+ resets = <&lpc_reset 4>;
no-loopback-test;
status = "disabled";
};
@@ -264,7 +270,7 @@
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x1e789000 0x1000>;
+ ranges = <0x0 0x1e789000 0x1000>;
lpc_bmc: lpc-bmc@0 {
compatible = "aspeed,ast2500-lpc-bmc";
@@ -274,16 +280,16 @@
lpc_host: lpc-host@80 {
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x80 0x1e0>;
-
- reg-io-width = <4>;
+ ranges = <0x0 0x80 0x1e0>;
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@@ -298,6 +304,19 @@
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
+
+ lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@c0 {
+ compatible = "aspeed,ast2500-ibt-bmc";
+ reg = <0xc0 0x18>;
+ interrupts = <8>;
+ status = "disabled";
+ };
};
};
@@ -307,6 +326,7 @@
reg-shift = <2>;
interrupts = <32>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
+ resets = <&lpc_reset 5>;
no-loopback-test;
status = "disabled";
};
@@ -317,6 +337,7 @@
reg-shift = <2>;
interrupts = <33>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
+ resets = <&lpc_reset 6>;
no-loopback-test;
status = "disabled";
};
@@ -327,6 +348,7 @@
reg-shift = <2>;
interrupts = <34>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
+ resets = <&lpc_reset 7>;
no-loopback-test;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index 3ea1d26e1c68..af9f38456d04 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -109,7 +109,32 @@
port {
panel_input: endpoint {
- remote-endpoint = <&hlcdc_panel_output>;
+ remote-endpoint = <&lvds_encoder_output>;
+ };
+ };
+ };
+
+ lvds-encoder {
+ compatible = "lvds-encoder";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_encoder_input: endpoint {
+ remote-endpoint = <&hlcdc_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_encoder_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
};
};
};
@@ -146,7 +171,7 @@
};
eeprom@50 {
- compatible = "nxp,24c02";
+ compatible = "nxp,se97b", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
@@ -176,8 +201,8 @@
&pinctrl_lcd_hipow0>;
port@0 {
- hlcdc_panel_output: endpoint {
- remote-endpoint = <&panel_input>;
+ hlcdc_output: endpoint {
+ remote-endpoint = <&lvds_encoder_input>;
};
};
};
@@ -216,29 +241,34 @@
reg = <0x0 0x40000>;
};
- bootloader@40000 {
- label = "bootloader";
- reg = <0x40000 0x80000>;
+ barebox@40000 {
+ label = "barebox";
+ reg = <0x40000 0x60000>;
+ };
+
+ bareboxenv@c0000 {
+ label = "bareboxenv";
+ reg = <0xc0000 0x40000>;
};
- bootloaderenv@c0000 {
- label = "bootloader env";
- reg = <0xc0000 0xc0000>;
+ bareboxenv2@100000 {
+ label = "bareboxenv2";
+ reg = <0x100000 0x40000>;
};
- dtb@180000 {
- label = "device tree";
- reg = <0x180000 0x80000>;
+ oftree@180000 {
+ label = "oftree";
+ reg = <0x180000 0x20000>;
};
kernel@200000 {
label = "kernel";
- reg = <0x200000 0x600000>;
+ reg = <0x200000 0x500000>;
};
rootfs@800000 {
label = "rootfs";
- reg = <0x800000 0x0f800000>;
+ reg = <0x800000 0x1f800000>;
};
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index e603a267bdf1..b10dccd0958f 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -230,7 +230,7 @@
status = "okay";
at24@50 {
- compatible = "24c02";
+ compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <8>;
};
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
index 9b82cc8843e1..2fbec69d9cd6 100644
--- a/arch/arm/boot/dts/at91-tse850-3.dts
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -234,6 +234,7 @@
compatible = "ti,pcm5142";
reg = <0x4c>;
+ #sound-dai-cells = <0>;
AVDD-supply = <&reg_3v3>;
DVDD-supply = <&reg_3v3>;
@@ -246,7 +247,7 @@
};
eeprom@50 {
- compatible = "nxp,24c02", "atmel,24c02";
+ compatible = "nxp,se97b", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index ba61893a02a0..2ad69a7fbc00 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -493,8 +493,8 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
- <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
- AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
+ <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_uart0_cts: uart0_cts-0 {
@@ -511,8 +511,8 @@
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
- AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
+ <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_uart1_rts: uart1_rts-0 {
@@ -545,8 +545,8 @@
uart2 {
pinctrl_uart2: uart2-0 {
atmel,pins =
- <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
- AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
+ <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_uart2_rts: uart2_rts-0 {
@@ -563,8 +563,8 @@
uart3 {
pinctrl_uart3: uart3-0 {
atmel,pins =
- <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
- AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
+ <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
pinctrl_uart3_rts: uart3_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 655f06cd716a..9118e29b6d6a 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -434,8 +434,8 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart0_rts: usart0_rts-0 {
@@ -468,8 +468,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -486,8 +486,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart2_rts: usart2_rts-0 {
@@ -504,8 +504,8 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
+ <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart3_rts: usart3_rts-0 {
@@ -522,16 +522,16 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
- <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */
- AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
+ <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index e16c706d91ef..d2b865f60293 100644
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -201,7 +201,7 @@
status = "okay";
24c512@50 {
- compatible = "24c512";
+ compatible = "atmel,24c512";
reg = <0x50>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index ddfc63b8fd4e..53c63d0a418a 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -328,8 +328,8 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
- <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart0_rts: usart0_rts-0 {
@@ -346,8 +346,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
- <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -364,8 +364,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
- <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart2_rts: usart2_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index f2405671e3bd..87fb0660ab5d 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -437,8 +437,8 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
- AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
+ <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart0_rts: usart0_rts-0 {
@@ -455,8 +455,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
- AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -473,8 +473,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
- AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
+ <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart2_rts: usart2_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index e9a7c70830a8..727096f24f7c 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -250,7 +250,7 @@
status = "okay";
24c512@50 {
- compatible = "24c512";
+ compatible = "atmel,24c512";
reg = <0x50>;
pagesize = <128>;
};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 50561b7b7939..71df3adfc7ca 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -211,7 +211,7 @@
status = "okay";
24c512@50 {
- compatible = "24c512";
+ compatible = "atmel,24c512";
reg = <0x50>;
};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index a7da0dd0c98f..0898213f3bb2 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -21,7 +21,7 @@
atmel,mux-mask = <
/* A B C */
0xffffffff 0xffe0399f 0xc000001c /* pioA */
- 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
+ 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
0x80000000 0x07c0ffff 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3a30eec7f508..1ee25a475be8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -555,8 +555,8 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
- AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart0_rts: usart0_rts-0 {
@@ -573,8 +573,8 @@
uart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -591,8 +591,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart2_rts: usart2_rts-0 {
@@ -609,8 +609,8 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart3_rts: usart3_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 4b62f4f963f6..37cb81f457b5 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -641,8 +641,8 @@
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
- AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
+ <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE
+ AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 3cae687dccbd..bd001cca25a4 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -1,7 +1,8 @@
/*
* at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
*
- * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ * Copyright (C) 2014 Microchip
+ * Alexandre Belloni <alexandre.belloni@free-electrons.com>
*
* Licensed under GPLv2 or later.
*/
@@ -719,8 +720,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
- <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -742,8 +743,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
- <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart2_rts: usart2_rts-0 {
@@ -765,8 +766,8 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
- <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart3_rts: usart3_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index 4bde9f245e61..27d8a1f44233 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -1,7 +1,8 @@
/*
* at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board
*
- * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ * Copyright (C) 2014 Microchip
+ * Alexandre Belloni <alexandre.belloni@free-electrons.com>
*
* Licensed under GPLv2 only
*/
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index fee4fe51a97e..a3c3c3128148 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -520,8 +520,8 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
- AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart0_rts: usart0_rts-0 {
@@ -543,8 +543,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
- AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
+ <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -566,8 +566,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
- AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
+ <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart2_rts: usart2_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 43bb5b51caa6..a32d12b406a3 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -21,8 +21,8 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
- AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
+ <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
pinctrl_usart3_rts: usart3_rts-0 {
diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts
index 1e9cd1a8508e..900e03b7a7b2 100644
--- a/arch/arm/boot/dts/atlas7-evb.dts
+++ b/arch/arm/boot/dts/atlas7-evb.dts
@@ -73,7 +73,7 @@
btm {
uart6: uart@11000000 {
status = "okay";
- sirf,uart-has-rtscts;
+ uart-has-rtscts;
};
};
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
index 897103e0a79b..0d9ff12bdf28 100644
--- a/arch/arm/boot/dts/axp209.dtsi
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -58,6 +58,11 @@
status = "disabled";
};
+ axp_adc: adc {
+ compatible = "x-powers,axp209-adc";
+ #io-channel-cells = <1>;
+ };
+
axp_gpio: gpio {
compatible = "x-powers,axp209-gpio";
gpio-controller;
diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi
index 87fb08e812ec..65a07a67aca9 100644
--- a/arch/arm/boot/dts/axp22x.dtsi
+++ b/arch/arm/boot/dts/axp22x.dtsi
@@ -57,6 +57,11 @@
status = "disabled";
};
+ axp_adc: adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+
battery_power_supply: battery-power-supply {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index fd55b896afa1..043c717dcef1 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -48,7 +48,12 @@
interrupt-controller;
#interrupt-cells = <1>;
- axp_gpio: axp-gpio {
+ axp_adc: adc {
+ compatible = "x-powers,axp813-adc";
+ #io-channel-cells = <1>;
+ };
+
+ axp_gpio: gpio {
compatible = "x-powers,axp813-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -64,6 +69,11 @@
};
};
+ battery_power_supply: battery-power-supply {
+ compatible = "x-powers,axp813-battery-power-supply";
+ status = "disabled";
+ };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index b8565fc33eea..b7f79f1c431a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -12,7 +12,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
-#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-usb-otg.dtsi"
/ {
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
@@ -131,6 +131,18 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_gpio14>;
+ pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index e36c392a2b8f..6c3cfaa77f3d 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -18,7 +18,9 @@
soc {
firmware: firmware {
- compatible = "raspberrypi,bcm2835-firmware";
+ compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+ #address-cells = <0>;
+ #size-cells = <0>;
mboxes = <&mailbox>;
};
@@ -27,6 +29,12 @@
firmware = <&firmware>;
#power-domain-cells = <1>;
};
+
+ mailbox@7e00b840 {
+ compatible = "brcm,bcm2835-vchiq";
+ reg = <0x7e00b840 0xf>;
+ interrupts = <0 2>;
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 3e4ed7c5b0b3..0b31d995a066 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -25,6 +25,23 @@
};
};
+&firmware {
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "STATUS_LED",
+ "LAN_RUN",
+ "HPD_N",
+ "CAM_GPIO0",
+ "CAM_GPIO1",
+ "PWR_LOW_N";
+ status = "okay";
+ };
+};
+
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 9d293decf8d3..ac00e730f898 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -223,6 +223,7 @@
gpclk2_gpio43: gpclk2_gpio43 {
brcm,pins = <43>;
brcm,function = <BCM2835_FSEL_ALT0>;
+ brcm,pull = <BCM2835_PUD_OFF>;
};
i2c0_gpio0: i2c0_gpio0 {
@@ -252,7 +253,7 @@
jtag_gpio4: jtag_gpio4 {
brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT4>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
};
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
@@ -335,10 +336,12 @@
uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
};
uart0_gpio32: uart0_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
};
uart0_gpio36: uart0_gpio36 {
brcm,pins = <36 37>;
@@ -397,8 +400,8 @@
i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = <0x7e203000 0x20>,
- <0x7e101098 0x02>;
+ reg = <0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
@@ -438,6 +441,17 @@
interrupts = <2 14>; /* pwa1 */
};
+ dpi: dpi@7e208000 {
+ compatible = "brcm,bcm2835-dpi";
+ reg = <0x7e208000 0x8c>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>,
+ <&clocks BCM2835_CLOCK_DPI>;
+ clock-names = "core", "pixel";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
dsi0: dsi@7e209000 {
compatible = "brcm,bcm2835-dsi0";
reg = <0x7e209000 0x78>;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 8bef6429feee..87ea6ba664f5 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -35,6 +35,74 @@
0x88000000 0x08000000>;
};
+ spi {
+ compatible = "spi-gpio";
+ num-chipselects = <1>;
+ gpio-sck = <&chipcommon 7 0>;
+ gpio-mosi = <&chipcommon 4 0>;
+ cs-gpios = <&chipcommon 6 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hc595: gpio_spi@0 {
+ compatible = "fairchild,74hc595";
+ reg = <0>;
+ registers-number = <1>;
+ spi-max-frequency = <100000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ usb {
+ label = "bcm53xx:green:usb";
+ gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ power0 {
+ label = "bcm53xx:green:power";
+ gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ power1 {
+ label = "bcm53xx:red:power";
+ gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ router0 {
+ label = "bcm53xx:green:router";
+ gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ router1 {
+ label = "bcm53xx:amber:router";
+ gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan {
+ label = "bcm53xx:green:wan";
+ gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ wireless0 {
+ label = "bcm53xx:green:wireless";
+ gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ wireless1 {
+ label = "bcm53xx:amber:wireless";
+ gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index fd8b8c689ffe..ecd05e26c262 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -204,10 +204,10 @@
reg = <4>;
};
- port@5 {
- ethernet = <&amac0>;
+ port@8 {
+ ethernet = <&amac2>;
label = "cpu";
- reg = <5>;
+ reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index b8bde13de90a..f5e85b301497 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -208,10 +208,10 @@
reg = <4>;
};
- port@5 {
- ethernet = <&amac0>;
+ port@8 {
+ ethernet = <&amac2>;
label = "cpu";
- reg = <5>;
+ reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index f0e2008f7490..ea3fc194f8f3 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -210,10 +210,10 @@
reg = <4>;
};
- port@5 {
- ethernet = <&amac0>;
+ port@8 {
+ ethernet = <&amac2>;
label = "cpu";
- reg = <5>;
+ reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 2cf2392483b2..3ea5f739e90b 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -245,10 +245,10 @@
reg = <4>;
};
- port@5 {
- ethernet = <&amac0>;
+ port@8 {
+ ethernet = <&amac2>;
label = "cpu";
- reg = <5>;
+ reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index bce251a68591..ea9a0806b446 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -216,10 +216,10 @@
reg = <4>;
};
- port@5 {
- ethernet = <&amac0>;
+ port@8 {
+ ethernet = <&amac2>;
label = "cpu";
- reg = <5>;
+ reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c75507922f7d..3962fa4b07f5 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -15,11 +15,16 @@
compatible = "ti,da850-evm", "ti,da850";
model = "DA850/AM1808/OMAP-L138 EVM";
+ chosen {
+ stdout-path = &serial2;
+ };
+
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
ethernet0 = &eth0;
+ spi0 = &spi1;
};
soc@1c00000 {
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts
index 81942ae83e1f..1ffd87796cac 100644
--- a/arch/arm/boot/dts/da850-lego-ev3.dts
+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
@@ -184,6 +184,23 @@
io-channel-names = "voltage", "current";
rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>;
};
+
+ /* ARM local RAM */
+ memory@ffff0000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0xffff0000 0x2000>; /* 8k */
+
+ /*
+ * The I2C bootloader looks for this magic value to either
+ * boot normally or boot into a firmware update mode.
+ */
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x1ffc>;
+ mode-normal = <0x00000000>;
+ mode-loader = <0x5555aaaa>;
+ };
+ };
};
&pmx_core {
@@ -293,7 +310,7 @@
* EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC.
*/
eeprom@50 {
- compatible = "microchip,24c128";
+ compatible = "microchip,24c128", "atmel,24c128";
pagesize = <64>;
read-only;
reg = <0x50>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index a7385c338ee9..f1425b0f3a54 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -87,33 +87,6 @@
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
-
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
};
&i2c1 {
@@ -350,6 +323,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&evm_1v8_sw>;
+ vqmmc-supply = <&evm_1v8_sw>;
bus-width = <8>;
pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e4a420f16800..f4ddd86f2c77 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -92,8 +92,6 @@
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
- cooling-min-level = <0>;
- cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
vbb-supply = <&abb_mpu>;
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index 41c9132eb550..ebc4bbae981e 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -24,13 +24,13 @@
regulator-name = "vddshv8";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&evm_5v0>;
gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0
- 3000000 0x1>;
+ 3300000 0x1>;
};
evm_1v8_sw: fixedregulator-evm_1v8 {
@@ -50,6 +50,19 @@
};
};
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+};
+
&i2c1 {
status = "okay";
clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index c4fe7f8ef72a..2deb96405d06 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -9,6 +9,7 @@
#include "dra76x.dtsi"
#include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -100,46 +101,6 @@
};
};
-&dra7_pmx_core {
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-};
-
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -353,16 +314,21 @@
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&vio_1v8>;
+ vqmmc-supply = <&vio_1v8>;
bus-width = <8>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_default>;
+ pinctrl-2 = <&mmc2_pins_default>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
};
/* No RTC on this device */
diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 000000000000..baba7b00eca7
--- /dev/null
+++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Texas Instruments
+// MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+// Author: Sekhar Nori <nsekhar@ti.com>
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc3_pins_default: mmc3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc4_pins_hs: mmc4_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
+ 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL2 in datamanual */
+ mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 60d0a732833a..c238407133bf 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -38,28 +38,28 @@
#size-cells = <0>;
one {
- debounce_interval = <50>;
+ debounce-interval = <50>;
wakeup-source;
label = "DSW2-1";
linux,code = <KEY_1>;
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
two {
- debounce_interval = <50>;
+ debounce-interval = <50>;
wakeup-source;
label = "DSW2-2";
linux,code = <KEY_2>;
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
three {
- debounce_interval = <50>;
+ debounce-interval = <50>;
wakeup-source;
label = "DSW2-3";
linux,code = <KEY_3>;
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
};
four {
- debounce_interval = <50>;
+ debounce-interval = <50>;
wakeup-source;
label = "DSW2-4";
linux,code = <KEY_4>;
diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
index 25186ac4188d..1dbf3bbff8d3 100644
--- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
+++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition.
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/ {
diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
index 09a2040054ed..4b3dd0549a54 100644
--- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi
+++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/ {
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 0aa577fe9f95..620b50c19ead 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -245,6 +245,7 @@
regulator-name = "VLDO23_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
ldo24_reg: LDO24 {
@@ -316,6 +317,41 @@
status = "okay";
};
+&mshc_1 {
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ non-removable;
+ keep-power-in-suspend;
+ fifo-depth = <0x40>;
+ vqmmc-supply = <&ldo11_reg>;
+ /*
+ * Voltage negotiation is broken for the SDIO periph so we
+ * can't actually set the voltage here.
+ * vmmc-supply = <&ldo23_reg>;
+ */
+ card-detect-delay = <500>;
+ clock-frequency = <100000000>;
+ max-frequency = <100000000>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&pinctrl_1 {
+ wlanen: wlanen {
+ samsung,pins = "gpx2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV3>;
+ samsung,pin-val = <1>;
+ };
+};
+
&rtc {
clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
clock-names = "rtc", "rtc_src";
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index b8fb94f5daa8..0a5f989d963b 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -161,34 +161,39 @@
syscon = <&pmu_system_controller>;
};
- pd_cam: cam-power-domain@10023c00 {
+ pd_cam: power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
+ label = "CAM";
};
- pd_mfc: mfc-power-domain@10023c40 {
+ pd_mfc: power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
+ label = "MFC";
};
- pd_g3d: g3d-power-domain@10023c60 {
+ pd_g3d: power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
+ label = "G3D";
};
- pd_lcd0: lcd0-power-domain@10023c80 {
+ pd_lcd0: power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
+ label = "LCD0";
};
- pd_isp: isp-power-domain@10023ca0 {
+ pd_isp: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
+ label = "ISP";
};
cmu: clock-controller@10030000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 6d59cc827649..909a9f2bf5be 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -52,961 +52,976 @@
serial3 = &serial_3;
};
- clock_audss: clock-controller@3810000 {
- compatible = "samsung,exynos4210-audss-clock";
- reg = <0x03810000 0x0C>;
- #clock-cells = <1>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
- <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
- clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
- };
-
- i2s0: i2s@3830000 {
- compatible = "samsung,s5pv210-i2s";
- reg = <0x03830000 0x100>;
- clocks = <&clock_audss EXYNOS_I2S_BUS>,
- <&clock_audss EXYNOS_DOUT_AUD_BUS>,
- <&clock_audss EXYNOS_SCLK_I2S>;
- clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
- #clock-cells = <1>;
- clock-output-names = "i2s_cdclk0";
- dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
- dma-names = "tx", "rx", "tx-sec";
- samsung,idma-addr = <0x03000000>;
- #sound-dai-cells = <1>;
- status = "disabled";
- };
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
+ clock_audss: clock-controller@3810000 {
+ compatible = "samsung,exynos4210-audss-clock";
+ reg = <0x03810000 0x0C>;
+ #clock-cells = <1>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+ <&clock CLK_SCLK_AUDIO0>,
+ <&clock CLK_SCLK_AUDIO0>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio",
+ "sclk_pcm_in";
+ };
- scu: snoop-control-unit@10500000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x10500000 0x2000>;
- };
+ i2s0: i2s@3830000 {
+ compatible = "samsung,s5pv210-i2s";
+ reg = <0x03830000 0x100>;
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ #clock-cells = <1>;
+ clock-output-names = "i2s_cdclk0";
+ dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
+ dma-names = "tx", "rx", "tx-sec";
+ samsung,idma-addr = <0x03000000>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
- memory-controller@12570000 {
- compatible = "samsung,exynos4210-srom";
- reg = <0x12570000 0x14>;
- };
+ chipid@10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
- mipi_phy: video-phy {
- compatible = "samsung,s5pv210-mipi-video-phy";
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
- };
+ scu: snoop-control-unit@10500000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x10500000 0x2000>;
+ };
- pd_mfc: mfc-power-domain@10023c40 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023C40 0x20>;
- #power-domain-cells = <0>;
- label = "MFC";
- };
+ memory-controller@12570000 {
+ compatible = "samsung,exynos4210-srom";
+ reg = <0x12570000 0x14>;
+ };
- pd_g3d: g3d-power-domain@10023c60 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023C60 0x20>;
- #power-domain-cells = <0>;
- label = "G3D";
- };
+ mipi_phy: video-phy {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ #phy-cells = <1>;
+ syscon = <&pmu_system_controller>;
+ };
- pd_lcd0: lcd0-power-domain@10023c80 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023C80 0x20>;
- #power-domain-cells = <0>;
- label = "LCD0";
- };
+ pd_mfc: mfc-power-domain@10023c40 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C40 0x20>;
+ #power-domain-cells = <0>;
+ label = "MFC";
+ };
- pd_tv: tv-power-domain@10023c20 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023C20 0x20>;
- #power-domain-cells = <0>;
- power-domains = <&pd_lcd0>;
- label = "TV";
- };
+ pd_g3d: g3d-power-domain@10023c60 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C60 0x20>;
+ #power-domain-cells = <0>;
+ label = "G3D";
+ };
- pd_cam: cam-power-domain@10023c00 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023C00 0x20>;
- #power-domain-cells = <0>;
- label = "CAM";
- };
+ pd_lcd0: lcd0-power-domain@10023c80 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C80 0x20>;
+ #power-domain-cells = <0>;
+ label = "LCD0";
+ };
- pd_gps: gps-power-domain@10023ce0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023CE0 0x20>;
- #power-domain-cells = <0>;
- label = "GPS";
- };
+ pd_tv: tv-power-domain@10023c20 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C20 0x20>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lcd0>;
+ label = "TV";
+ };
- pd_gps_alive: gps-alive-power-domain@10023d00 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023D00 0x20>;
- #power-domain-cells = <0>;
- label = "GPS alive";
- };
+ pd_cam: cam-power-domain@10023c00 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C00 0x20>;
+ #power-domain-cells = <0>;
+ label = "CAM";
+ };
- gic: interrupt-controller@10490000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
- };
+ pd_gps: gps-power-domain@10023ce0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023CE0 0x20>;
+ #power-domain-cells = <0>;
+ label = "GPS";
+ };
- combiner: interrupt-controller@10440000 {
- compatible = "samsung,exynos4210-combiner";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0x10440000 0x1000>;
- };
+ pd_gps_alive: gps-alive-power-domain@10023d00 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023D00 0x20>;
+ #power-domain-cells = <0>;
+ label = "GPS alive";
+ };
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <2 2>, <3 2>;
- };
+ gic: interrupt-controller@10490000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
+ };
- sys_reg: syscon@10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
- };
+ combiner: interrupt-controller@10440000 {
+ compatible = "samsung,exynos4210-combiner";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x10440000 0x1000>;
+ };
- pmu_system_controller: system-controller@10020000 {
- compatible = "samsung,exynos4210-pmu", "syscon";
- reg = <0x10020000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- };
+ pmu: pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <2 2>, <3 2>;
+ };
- dsi_0: dsi@11c80000 {
- compatible = "samsung,exynos4210-mipi-dsi";
- reg = <0x11C80000 0x10000>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_lcd0>;
- phys = <&mipi_phy 1>;
- phy-names = "dsim";
- clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
- clock-names = "bus_clk", "sclk_mipi";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
+ sys_reg: syscon@10010000 {
+ compatible = "samsung,exynos4-sysreg", "syscon";
+ reg = <0x10010000 0x400>;
+ };
- camera {
- compatible = "samsung,fimc", "simple-bus";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- #clock-cells = <1>;
- clock-output-names = "cam_a_clkout", "cam_b_clkout";
- ranges;
+ pmu_system_controller: system-controller@10020000 {
+ compatible = "samsung,exynos4210-pmu", "syscon";
+ reg = <0x10020000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
- fimc_0: fimc@11800000 {
- compatible = "samsung,exynos4210-fimc";
- reg = <0x11800000 0x1000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
- clock-names = "fimc", "sclk_fimc";
- power-domains = <&pd_cam>;
- samsung,sysreg = <&sys_reg>;
- iommus = <&sysmmu_fimc0>;
+ dsi_0: dsi@11c80000 {
+ compatible = "samsung,exynos4210-mipi-dsi";
+ reg = <0x11C80000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_lcd0>;
+ phys = <&mipi_phy 1>;
+ phy-names = "dsim";
+ clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
+ clock-names = "bus_clk", "sclk_mipi";
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- fimc_1: fimc@11810000 {
- compatible = "samsung,exynos4210-fimc";
- reg = <0x11810000 0x1000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
- clock-names = "fimc", "sclk_fimc";
- power-domains = <&pd_cam>;
- samsung,sysreg = <&sys_reg>;
- iommus = <&sysmmu_fimc1>;
+ camera: camera {
+ compatible = "samsung,fimc", "simple-bus";
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #clock-cells = <1>;
+ clock-output-names = "cam_a_clkout", "cam_b_clkout";
+ ranges;
+
+ fimc_0: fimc@11800000 {
+ compatible = "samsung,exynos4210-fimc";
+ reg = <0x11800000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ clock-names = "fimc", "sclk_fimc";
+ power-domains = <&pd_cam>;
+ samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc0>;
+ status = "disabled";
+ };
+
+ fimc_1: fimc@11810000 {
+ compatible = "samsung,exynos4210-fimc";
+ reg = <0x11810000 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_FIMC1>,
+ <&clock CLK_SCLK_FIMC1>;
+ clock-names = "fimc", "sclk_fimc";
+ power-domains = <&pd_cam>;
+ samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc1>;
+ status = "disabled";
+ };
+
+ fimc_2: fimc@11820000 {
+ compatible = "samsung,exynos4210-fimc";
+ reg = <0x11820000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_FIMC2>,
+ <&clock CLK_SCLK_FIMC2>;
+ clock-names = "fimc", "sclk_fimc";
+ power-domains = <&pd_cam>;
+ samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc2>;
+ status = "disabled";
+ };
+
+ fimc_3: fimc@11830000 {
+ compatible = "samsung,exynos4210-fimc";
+ reg = <0x11830000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_FIMC3>,
+ <&clock CLK_SCLK_FIMC3>;
+ clock-names = "fimc", "sclk_fimc";
+ power-domains = <&pd_cam>;
+ samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc3>;
+ status = "disabled";
+ };
+
+ csis_0: csis@11880000 {
+ compatible = "samsung,exynos4210-csis";
+ reg = <0x11880000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_CSIS0>,
+ <&clock CLK_SCLK_CSIS0>;
+ clock-names = "csis", "sclk_csis";
+ bus-width = <4>;
+ power-domains = <&pd_cam>;
+ phys = <&mipi_phy 0>;
+ phy-names = "csis";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ csis_1: csis@11890000 {
+ compatible = "samsung,exynos4210-csis";
+ reg = <0x11890000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_CSIS1>,
+ <&clock CLK_SCLK_CSIS1>;
+ clock-names = "csis", "sclk_csis";
+ bus-width = <2>;
+ power-domains = <&pd_cam>;
+ phys = <&mipi_phy 2>;
+ phy-names = "csis";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
- fimc_2: fimc@11820000 {
- compatible = "samsung,exynos4210-fimc";
- reg = <0x11820000 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
- clock-names = "fimc", "sclk_fimc";
- power-domains = <&pd_cam>;
- samsung,sysreg = <&sys_reg>;
- iommus = <&sysmmu_fimc2>;
+ rtc: rtc@10070000 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x10070000 0x100>;
+ interrupt-parent = <&pmu_system_controller>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_RTC>;
+ clock-names = "rtc";
status = "disabled";
};
- fimc_3: fimc@11830000 {
- compatible = "samsung,exynos4210-fimc";
- reg = <0x11830000 0x1000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
- clock-names = "fimc", "sclk_fimc";
- power-domains = <&pd_cam>;
- samsung,sysreg = <&sys_reg>;
- iommus = <&sysmmu_fimc3>;
+ keypad: keypad@100a0000 {
+ compatible = "samsung,s5pv210-keypad";
+ reg = <0x100A0000 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_KEYIF>;
+ clock-names = "keypad";
status = "disabled";
};
- csis_0: csis@11880000 {
- compatible = "samsung,exynos4210-csis";
- reg = <0x11880000 0x4000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
- clock-names = "csis", "sclk_csis";
- bus-width = <4>;
- power-domains = <&pd_cam>;
- phys = <&mipi_phy 0>;
- phy-names = "csis";
+ sdhci_0: sdhci@12510000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12510000 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- csis_1: csis@11890000 {
- compatible = "samsung,exynos4210-csis";
- reg = <0x11890000 0x4000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
- clock-names = "csis", "sclk_csis";
- bus-width = <2>;
- power-domains = <&pd_cam>;
- phys = <&mipi_phy 2>;
- phy-names = "csis";
+ sdhci_1: sdhci@12520000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12520000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- };
-
- rtc: rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupt-parent = <&pmu_system_controller>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_RTC>;
- clock-names = "rtc";
- status = "disabled";
- };
-
- keypad: keypad@100a0000 {
- compatible = "samsung,s5pv210-keypad";
- reg = <0x100A0000 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_KEYIF>;
- clock-names = "keypad";
- status = "disabled";
- };
-
- sdhci_0: sdhci@12510000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12510000 0x100>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
- clock-names = "hsmmc", "mmc_busclk.2";
- status = "disabled";
- };
- sdhci_1: sdhci@12520000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12520000 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
- clock-names = "hsmmc", "mmc_busclk.2";
- status = "disabled";
- };
-
- sdhci_2: sdhci@12530000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12530000 0x100>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
- clock-names = "hsmmc", "mmc_busclk.2";
- status = "disabled";
- };
-
- sdhci_3: sdhci@12540000 {
- compatible = "samsung,exynos4210-sdhci";
- reg = <0x12540000 0x100>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
- clock-names = "hsmmc", "mmc_busclk.2";
- status = "disabled";
- };
-
- exynos_usbphy: exynos-usbphy@125b0000 {
- compatible = "samsung,exynos4210-usb2-phy";
- reg = <0x125B0000 0x100>;
- samsung,pmureg-phandle = <&pmu_system_controller>;
- clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
- clock-names = "phy", "ref";
- #phy-cells = <1>;
- status = "disabled";
- };
-
- hsotg: hsotg@12480000 {
- compatible = "samsung,s3c6400-hsotg";
- reg = <0x12480000 0x20000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_USB_DEVICE>;
- clock-names = "otg";
- phys = <&exynos_usbphy 0>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
+ sdhci_2: sdhci@12530000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12530000 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
+ clock-names = "hsmmc", "mmc_busclk.2";
+ status = "disabled";
+ };
- ehci: ehci@12580000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12580000 0x100>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_USB_HOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
+ sdhci_3: sdhci@12540000 {
+ compatible = "samsung,exynos4210-sdhci";
+ reg = <0x12540000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
+ clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
- port@1 {
- reg = <1>;
- phys = <&exynos_usbphy 2>;
+
+ exynos_usbphy: exynos-usbphy@125b0000 {
+ compatible = "samsung,exynos4210-usb2-phy";
+ reg = <0x125B0000 0x100>;
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+ clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
status = "disabled";
};
- port@2 {
- reg = <2>;
- phys = <&exynos_usbphy 3>;
+
+ hsotg: hsotg@12480000 {
+ compatible = "samsung,s3c6400-hsotg";
+ reg = <0x12480000 0x20000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USB_DEVICE>;
+ clock-names = "otg";
+ phys = <&exynos_usbphy 0>;
+ phy-names = "usb2-phy";
status = "disabled";
};
- };
- ohci: ohci@12590000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12590000 0x100>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_USB_HOST>;
- clock-names = "usbhost";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- phys = <&exynos_usbphy 1>;
+ ehci: ehci@12580000 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x12580000 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USB_HOST>;
+ clock-names = "usbhost";
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&exynos_usbphy 1>;
+ status = "disabled";
+ };
+ port@1 {
+ reg = <1>;
+ phys = <&exynos_usbphy 2>;
+ status = "disabled";
+ };
+ port@2 {
+ reg = <2>;
+ phys = <&exynos_usbphy 3>;
+ status = "disabled";
+ };
};
- };
- i2s1: i2s@13960000 {
- compatible = "samsung,s3c6410-i2s";
- reg = <0x13960000 0x100>;
- clocks = <&clock CLK_I2S1>;
- clock-names = "iis";
- #clock-cells = <1>;
- clock-output-names = "i2s_cdclk1";
- dmas = <&pdma1 12>, <&pdma1 11>;
- dma-names = "tx", "rx";
- #sound-dai-cells = <1>;
- status = "disabled";
- };
+ ohci: ohci@12590000 {
+ compatible = "samsung,exynos4210-ohci";
+ reg = <0x12590000 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USB_HOST>;
+ clock-names = "usbhost";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&exynos_usbphy 1>;
+ status = "disabled";
+ };
+ };
- i2s2: i2s@13970000 {
- compatible = "samsung,s3c6410-i2s";
- reg = <0x13970000 0x100>;
- clocks = <&clock CLK_I2S2>;
- clock-names = "iis";
- #clock-cells = <1>;
- clock-output-names = "i2s_cdclk2";
- dmas = <&pdma0 14>, <&pdma0 13>;
- dma-names = "tx", "rx";
- #sound-dai-cells = <1>;
- status = "disabled";
- };
+ i2s1: i2s@13960000 {
+ compatible = "samsung,s3c6410-i2s";
+ reg = <0x13960000 0x100>;
+ clocks = <&clock CLK_I2S1>;
+ clock-names = "iis";
+ #clock-cells = <1>;
+ clock-output-names = "i2s_cdclk1";
+ dmas = <&pdma1 12>, <&pdma1 11>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
- mfc: codec@13400000 {
- compatible = "samsung,mfc-v5";
- reg = <0x13400000 0x10000>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_mfc>;
- clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
- clock-names = "mfc", "sclk_mfc";
- iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
- iommu-names = "left", "right";
- };
+ i2s2: i2s@13970000 {
+ compatible = "samsung,s3c6410-i2s";
+ reg = <0x13970000 0x100>;
+ clocks = <&clock CLK_I2S2>;
+ clock-names = "iis";
+ #clock-cells = <1>;
+ clock-output-names = "i2s_cdclk2";
+ dmas = <&pdma0 14>, <&pdma0 13>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
- serial_0: serial@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- dmas = <&pdma0 15>, <&pdma0 16>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ mfc: codec@13400000 {
+ compatible = "samsung,mfc-v5";
+ reg = <0x13400000 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_mfc>;
+ clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
+ clock-names = "mfc", "sclk_mfc";
+ iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+ iommu-names = "left", "right";
+ };
- serial_1: serial@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
- clock-names = "uart", "clk_uart_baud0";
- dmas = <&pdma1 15>, <&pdma1 16>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ serial_0: serial@13800000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13800000 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma0 15>, <&pdma0 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- serial_2: serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- dmas = <&pdma0 17>, <&pdma0 18>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ serial_1: serial@13810000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13810000 0x100>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma1 15>, <&pdma1 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- serial_3: serial@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
- clock-names = "uart", "clk_uart_baud0";
- dmas = <&pdma1 17>, <&pdma1 18>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ serial_2: serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma0 17>, <&pdma0 18>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- i2c_0: i2c@13860000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C0>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_bus>;
- status = "disabled";
- };
+ serial_3: serial@13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+ clock-names = "uart", "clk_uart_baud0";
+ dmas = <&pdma1 17>, <&pdma1 18>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- i2c_1: i2c@13870000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C1>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_bus>;
- status = "disabled";
- };
+ i2c_0: i2c@13860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13860000 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C0>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_bus>;
+ status = "disabled";
+ };
- i2c_2: i2c@13880000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C2>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_bus>;
- status = "disabled";
- };
+ i2c_1: i2c@13870000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13870000 0x100>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C1>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_bus>;
+ status = "disabled";
+ };
- i2c_3: i2c@13890000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C3>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_bus>;
- status = "disabled";
- };
+ i2c_2: i2c@13880000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13880000 0x100>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C2>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_bus>;
+ status = "disabled";
+ };
- i2c_4: i2c@138a0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C4>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_bus>;
- status = "disabled";
- };
+ i2c_3: i2c@13890000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13890000 0x100>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C3>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_bus>;
+ status = "disabled";
+ };
- i2c_5: i2c@138b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C5>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_bus>;
- status = "disabled";
- };
+ i2c_4: i2c@138a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138A0000 0x100>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C4>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_bus>;
+ status = "disabled";
+ };
- i2c_6: i2c@138c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C6>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_bus>;
- status = "disabled";
- };
+ i2c_5: i2c@138b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138B0000 0x100>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C5>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_bus>;
+ status = "disabled";
+ };
- i2c_7: i2c@138d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C7>;
- clock-names = "i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7_bus>;
- status = "disabled";
- };
+ i2c_6: i2c@138c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138C0000 0x100>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C6>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_bus>;
+ status = "disabled";
+ };
- i2c_8: i2c@138e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "samsung,s3c2440-hdmiphy-i2c";
- reg = <0x138E0000 0x100>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C_HDMI>;
- clock-names = "i2c";
- status = "disabled";
-
- hdmi_i2c_phy: hdmiphy@38 {
- compatible = "exynos4210-hdmiphy";
- reg = <0x38>;
+ i2c_7: i2c@138d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138D0000 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C7>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_bus>;
+ status = "disabled";
};
- };
- spi_0: spi@13920000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13920000 0x100>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma0 7>, <&pdma0 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_bus>;
- status = "disabled";
- };
+ i2c_8: i2c@138e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-hdmiphy-i2c";
+ reg = <0x138E0000 0x100>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C_HDMI>;
+ clock-names = "i2c";
+ status = "disabled";
- spi_1: spi@13930000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13930000 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma1 7>, <&pdma1 6>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_bus>;
- status = "disabled";
- };
+ hdmi_i2c_phy: hdmiphy@38 {
+ compatible = "exynos4210-hdmiphy";
+ reg = <0x38>;
+ };
+ };
- spi_2: spi@13940000 {
- compatible = "samsung,exynos4210-spi";
- reg = <0x13940000 0x100>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma0 9>, <&pdma0 8>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_bus>;
- status = "disabled";
- };
+ spi_0: spi@13920000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13920000 0x100>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma0 7>, <&pdma0 6>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
- pwm: pwm@139d0000 {
- compatible = "samsung,exynos4210-pwm";
- reg = <0x139D0000 0x1000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PWM>;
- clock-names = "timers";
- #pwm-cells = <3>;
- status = "disabled";
- };
+ spi_1: spi@13930000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13930000 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 7>, <&pdma1 6>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ status = "disabled";
+ };
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
+ spi_2: spi@13940000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x13940000 0x100>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma0 9>, <&pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_bus>;
+ status = "disabled";
+ };
- pdma0: pdma@12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- mdma1: mdma@12850000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12850000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
+ pwm: pwm@139d0000 {
+ compatible = "samsung,exynos4210-pwm";
+ reg = <0x139D0000 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PWM>;
+ clock-names = "timers";
+ #pwm-cells = <3>;
+ status = "disabled";
};
- };
- fimd: fimd@11c00000 {
- compatible = "samsung,exynos4210-fimd";
- interrupt-parent = <&combiner>;
- reg = <0x11c00000 0x20000>;
- interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <11 0>, <11 1>, <11 2>;
- clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
- clock-names = "sclk_fimd", "fimd";
- power-domains = <&pd_lcd0>;
- iommus = <&sysmmu_fimd0>;
- samsung,sysreg = <&sys_reg>;
- status = "disabled";
- };
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma@12680000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12680000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@12690000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12690000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ mdma1: mdma@12850000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12850000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ };
+ };
- tmu: tmu@100c0000 {
- #include "exynos4412-tmu-sensor-conf.dtsi"
- };
+ fimd: fimd@11c00000 {
+ compatible = "samsung,exynos4210-fimd";
+ interrupt-parent = <&combiner>;
+ reg = <0x11c00000 0x20000>;
+ interrupt-names = "fifo", "vsync", "lcd_sys";
+ interrupts = <11 0>, <11 1>, <11 2>;
+ clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
+ clock-names = "sclk_fimd", "fimd";
+ power-domains = <&pd_lcd0>;
+ iommus = <&sysmmu_fimd0>;
+ samsung,sysreg = <&sys_reg>;
+ status = "disabled";
+ };
- jpeg_codec: jpeg-codec@11840000 {
- compatible = "samsung,exynos4210-jpeg";
- reg = <0x11840000 0x1000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_JPEG>;
- clock-names = "jpeg";
- power-domains = <&pd_cam>;
- iommus = <&sysmmu_jpeg>;
- };
+ tmu: tmu@100c0000 {
+ interrupt-parent = <&combiner>;
+ reg = <0x100C0000 0x100>;
+ interrupts = <2 4>;
+ status = "disabled";
+ #include "exynos4412-tmu-sensor-conf.dtsi"
+ };
- rotator: rotator@12810000 {
- compatible = "samsung,exynos4210-rotator";
- reg = <0x12810000 0x64>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_ROTATOR>;
- clock-names = "rotator";
- iommus = <&sysmmu_rotator>;
- };
+ jpeg_codec: jpeg-codec@11840000 {
+ compatible = "samsung,exynos4210-jpeg";
+ reg = <0x11840000 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_JPEG>;
+ clock-names = "jpeg";
+ power-domains = <&pd_cam>;
+ iommus = <&sysmmu_jpeg>;
+ };
- hdmi: hdmi@12d00000 {
- compatible = "samsung,exynos4210-hdmi";
- reg = <0x12D00000 0x70000>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
- "mout_hdmi";
- clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
- <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
- <&clock CLK_MOUT_HDMI>;
- phy = <&hdmi_i2c_phy>;
- power-domains = <&pd_tv>;
- samsung,syscon-phandle = <&pmu_system_controller>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
+ rotator: rotator@12810000 {
+ compatible = "samsung,exynos4210-rotator";
+ reg = <0x12810000 0x64>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_ROTATOR>;
+ clock-names = "rotator";
+ iommus = <&sysmmu_rotator>;
+ };
- hdmicec: cec@100b0000 {
- compatible = "samsung,s5p-cec";
- reg = <0x100B0000 0x200>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_HDMI_CEC>;
- clock-names = "hdmicec";
- samsung,syscon-phandle = <&pmu_system_controller>;
- hdmi-phandle = <&hdmi>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "disabled";
- };
+ hdmi: hdmi@12d00000 {
+ compatible = "samsung,exynos4210-hdmi";
+ reg = <0x12D00000 0x70000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+ "sclk_hdmiphy", "mout_hdmi";
+ clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
+ <&clock CLK_SCLK_PIXEL>,
+ <&clock CLK_SCLK_HDMIPHY>,
+ <&clock CLK_MOUT_HDMI>;
+ phy = <&hdmi_i2c_phy>;
+ power-domains = <&pd_tv>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
- mixer: mixer@12c10000 {
- compatible = "samsung,exynos4210-mixer";
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
- power-domains = <&pd_tv>;
- iommus = <&sysmmu_tv>;
- status = "disabled";
- };
+ hdmicec: cec@100b0000 {
+ compatible = "samsung,s5p-cec";
+ reg = <0x100B0000 0x200>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_HDMI_CEC>;
+ clock-names = "hdmicec";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ hdmi-phandle = <&hdmi>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "disabled";
+ };
- ppmu_dmc0: ppmu_dmc0@106a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106a0000 0x2000>;
- clocks = <&clock CLK_PPMUDMC0>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ mixer: mixer@12c10000 {
+ compatible = "samsung,exynos4210-mixer";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
+ power-domains = <&pd_tv>;
+ iommus = <&sysmmu_tv>;
+ status = "disabled";
+ };
- ppmu_dmc1: ppmu_dmc1@106b0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106b0000 0x2000>;
- clocks = <&clock CLK_PPMUDMC1>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_dmc0: ppmu_dmc0@106a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106a0000 0x2000>;
+ clocks = <&clock CLK_PPMUDMC0>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_cpu: ppmu_cpu@106c0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106c0000 0x2000>;
- clocks = <&clock CLK_PPMUCPU>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_dmc1: ppmu_dmc1@106b0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106b0000 0x2000>;
+ clocks = <&clock CLK_PPMUDMC1>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_acp: ppmu_acp@10ae0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106e0000 0x2000>;
- status = "disabled";
- };
+ ppmu_cpu: ppmu_cpu@106c0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x106c0000 0x2000>;
+ clocks = <&clock CLK_PPMUCPU>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_rightbus: ppmu_rightbus@112a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x112a0000 0x2000>;
- clocks = <&clock CLK_PPMURIGHT>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_rightbus: ppmu_rightbus@112a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x112a0000 0x2000>;
+ clocks = <&clock CLK_PPMURIGHT>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_leftbus: ppmu_leftbus0@116a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x116a0000 0x2000>;
- clocks = <&clock CLK_PPMULEFT>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_leftbus: ppmu_leftbus0@116a0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x116a0000 0x2000>;
+ clocks = <&clock CLK_PPMULEFT>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_camif: ppmu_camif@11ac0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x11ac0000 0x2000>;
- clocks = <&clock CLK_PPMUCAMIF>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_camif: ppmu_camif@11ac0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x11ac0000 0x2000>;
+ clocks = <&clock CLK_PPMUCAMIF>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_lcd0: ppmu_lcd0@11e40000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x11e40000 0x2000>;
- clocks = <&clock CLK_PPMULCD0>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_lcd0: ppmu_lcd0@11e40000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x11e40000 0x2000>;
+ clocks = <&clock CLK_PPMULCD0>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_fsys: ppmu_g3d@12630000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x12630000 0x2000>;
- status = "disabled";
- };
+ ppmu_fsys: ppmu_g3d@12630000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x12630000 0x2000>;
+ status = "disabled";
+ };
- ppmu_image: ppmu_image@12aa0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x12aa0000 0x2000>;
- clocks = <&clock CLK_PPMUIMAGE>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_image: ppmu_image@12aa0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x12aa0000 0x2000>;
+ clocks = <&clock CLK_PPMUIMAGE>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_tv: ppmu_tv@12e40000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x12e40000 0x2000>;
- clocks = <&clock CLK_PPMUTV>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_tv: ppmu_tv@12e40000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x12e40000 0x2000>;
+ clocks = <&clock CLK_PPMUTV>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_g3d: ppmu_g3d@13220000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x13220000 0x2000>;
- clocks = <&clock CLK_PPMUG3D>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_g3d: ppmu_g3d@13220000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x13220000 0x2000>;
+ clocks = <&clock CLK_PPMUG3D>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_mfc_left: ppmu_mfc_left@13660000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x13660000 0x2000>;
- clocks = <&clock CLK_PPMUMFC_L>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_mfc_left: ppmu_mfc_left@13660000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x13660000 0x2000>;
+ clocks = <&clock CLK_PPMUMFC_L>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- ppmu_mfc_right: ppmu_mfc_right@13670000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x13670000 0x2000>;
- clocks = <&clock CLK_PPMUMFC_R>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ ppmu_mfc_right: ppmu_mfc_right@13670000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x13670000 0x2000>;
+ clocks = <&clock CLK_PPMUMFC_R>;
+ clock-names = "ppmu";
+ status = "disabled";
+ };
- sysmmu_mfc_l: sysmmu@13620000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x13620000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <5 5>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
- power-domains = <&pd_mfc>;
- #iommu-cells = <0>;
- };
+ sysmmu_mfc_l: sysmmu@13620000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13620000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+ power-domains = <&pd_mfc>;
+ #iommu-cells = <0>;
+ };
- sysmmu_mfc_r: sysmmu@13630000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x13630000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <5 6>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
- power-domains = <&pd_mfc>;
- #iommu-cells = <0>;
- };
+ sysmmu_mfc_r: sysmmu@13630000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13630000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+ power-domains = <&pd_mfc>;
+ #iommu-cells = <0>;
+ };
- sysmmu_tv: sysmmu@12e20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12E20000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <5 4>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
- power-domains = <&pd_tv>;
- #iommu-cells = <0>;
- };
+ sysmmu_tv: sysmmu@12e20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12E20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
+ power-domains = <&pd_tv>;
+ #iommu-cells = <0>;
+ };
- sysmmu_fimc0: sysmmu@11a20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11A20000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 2>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
- power-domains = <&pd_cam>;
- #iommu-cells = <0>;
- };
+ sysmmu_fimc0: sysmmu@11a20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
- sysmmu_fimc1: sysmmu@11a30000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11A30000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 3>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
- power-domains = <&pd_cam>;
- #iommu-cells = <0>;
- };
+ sysmmu_fimc1: sysmmu@11a30000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A30000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 3>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
- sysmmu_fimc2: sysmmu@11a40000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11A40000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 4>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
- power-domains = <&pd_cam>;
- #iommu-cells = <0>;
- };
+ sysmmu_fimc2: sysmmu@11a40000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
- sysmmu_fimc3: sysmmu@11a50000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11A50000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 5>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
- power-domains = <&pd_cam>;
- #iommu-cells = <0>;
- };
+ sysmmu_fimc3: sysmmu@11a50000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A50000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
- sysmmu_jpeg: sysmmu@11a60000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11A60000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 6>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
- power-domains = <&pd_cam>;
- #iommu-cells = <0>;
- };
+ sysmmu_jpeg: sysmmu@11a60000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A60000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
- sysmmu_rotator: sysmmu@12a30000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12A30000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <5 0>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
- #iommu-cells = <0>;
- };
+ sysmmu_rotator: sysmmu@12a30000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12A30000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_ROTATOR>,
+ <&clock CLK_ROTATOR>;
+ #iommu-cells = <0>;
+ };
- sysmmu_fimd0: sysmmu@11e20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x11E20000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <5 2>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
- power-domains = <&pd_lcd0>;
- #iommu-cells = <0>;
- };
+ sysmmu_fimd0: sysmmu@11e20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11E20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
+ power-domains = <&pd_lcd0>;
+ #iommu-cells = <0>;
+ };
- sss: sss@10830000 {
- compatible = "samsung,exynos4210-secss";
- reg = <0x10830000 0x300>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SSS>;
- clock-names = "secss";
- };
+ sss: sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x300>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SSS>;
+ clock-names = "secss";
+ };
- prng: rng@10830400 {
- compatible = "samsung,exynos4-rng";
- reg = <0x10830400 0x200>;
- clocks = <&clock CLK_SSS>;
- clock-names = "secss";
+ prng: rng@10830400 {
+ compatible = "samsung,exynos4-rng";
+ reg = <0x10830400 0x200>;
+ clocks = <&clock CLK_SSS>;
+ clock-names = "secss";
+ };
};
};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index dbe6c052d8c1..520c5934a8d4 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -13,853 +13,851 @@
#include <dt-bindings/pinctrl/samsung.h>
-/ {
- pinctrl@11400000 {
- gpa0: gpa0 {
- gpio-controller;
- #gpio-cells = <2>;
+&pinctrl_0 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe2: gpe2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe3: gpe3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe4: gpe4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa0-4", "gpa0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart_audio_b: uart-audio-b {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = "gpb-2", "gpb-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c5_bus: i2c5-bus {
+ samsung,pins = "gpb-6", "gpb-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ ac97_bus: ac97-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2s2_bus: i2s2-bus {
+ samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+ "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pcm2_bus: pcm2-bus {
+ samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+ "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = "gpc1-0", "gpc1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c6_bus: i2c6-bus {
+ samsung,pins = "gpc1-3", "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c7_bus: i2c7-bus {
+ samsung,pins = "gpd0-2", "gpd0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c0_bus: i2c0-bus {
+ samsung,pins = "gpd1-0", "gpd1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c1_bus: i2c1-bus {
+ samsung,pins = "gpd1-2", "gpd1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm0_out: pwm0-out {
+ samsung,pins = "gpd0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm1_out: pwm1-out {
+ samsung,pins = "gpd0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm2_out: pwm2-out {
+ samsung,pins = "gpd0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm3_out: pwm3-out {
+ samsung,pins = "gpd0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_ctrl: lcd-ctrl {
+ samsung,pins = "gpd0-0", "gpd0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_sync: lcd-sync {
+ samsung,pins = "gpf0-0", "gpf0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_en: lcd-en {
+ samsung,pins = "gpe3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_clk: lcd-clk {
+ samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_data16: lcd-data-width16 {
+ samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+ "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+ "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+ "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_data18: lcd-data-width18 {
+ samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+ "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+ "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+ "gpf3-2", "gpf3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_data24: lcd-data-width24 {
+ samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+ "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+ "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+ "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+ "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_1 {
+ gpj0: gpj0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpj1: gpj1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk1: gpk1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk2: gpk2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk3: gpk3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl0: gpl0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl1: gpl1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl2: gpl2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpy0: gpy0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy1: gpy1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy2: gpy2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
- gpa1: gpa1 {
- gpio-controller;
- #gpio-cells = <2>;
+ gpy3: gpy3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy4: gpy4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy5: gpy5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy6: gpy6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = <2>;
- gpb: gpb {
- gpio-controller;
- #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpk0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
- gpc0: gpc0 {
- gpio-controller;
- #gpio-cells = <2>;
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpk0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_cd: sd0-cd {
+ samsung,pins = "gpk0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpk0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_clk: sd4-clk {
+ samsung,pins = "gpk0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_cmd: sd4-cmd {
+ samsung,pins = "gpk0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_cd: sd4-cd {
+ samsung,pins = "gpk0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_bus1: sd4-bus-width1 {
+ samsung,pins = "gpk0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_bus4: sd4-bus-width4 {
+ samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_bus8: sd4-bus-width8 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpk1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpk1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_cd: sd1-cd {
+ samsung,pins = "gpk1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpk1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_bus8: sd2-bus-width8 {
+ samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_clk: sd3-clk {
+ samsung,pins = "gpk3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_cmd: sd3-cmd {
+ samsung,pins = "gpk3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_cd: sd3-cd {
+ samsung,pins = "gpk3-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_bus1: sd3-bus-width1 {
+ samsung,pins = "gpk3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_bus4: sd3-bus-width4 {
+ samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ eint0: ext-int0 {
+ samsung,pins = "gpx0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint8: ext-int8 {
+ samsung,pins = "gpx1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint15: ext-int15 {
+ samsung,pins = "gpx1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint16: ext-int16 {
+ samsung,pins = "gpx2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint31: ext-int31 {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ cam_port_a_io: cam-port-a-io {
+ samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
+ "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
+ "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ cam_port_a_clk_active: cam-port-a-clk-active {
+ samsung,pins = "gpj1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ cam_port_a_clk_idle: cam-port-a-clk-idle {
+ samsung,pins = "gpj1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hdmi_cec: hdmi-cec {
+ samsung,pins = "gpx3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_2 {
+ gpz: gpz {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4", "gpz-5", "gpz-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd0: gpd0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd1: gpd1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpe0: gpe0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpe1: gpe1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpe2: gpe2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpe3: gpe3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpe4: gpe4 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf0: gpf0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf2: gpf2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf3: gpf3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart0_data: uart0-data {
- samsung,pins = "gpa0-0", "gpa0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart0_fctl: uart0-fctl {
- samsung,pins = "gpa0-2", "gpa0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_data: uart1-data {
- samsung,pins = "gpa0-4", "gpa0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_fctl: uart1-fctl {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c2_bus: i2c2-bus {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_data: uart2-data {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_fctl: uart2-fctl {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart_audio_a: uart-audio-a {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c3_bus: i2c3-bus {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart_audio_b: uart-audio-b {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi0_bus: spi0-bus {
- samsung,pins = "gpb-0", "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c4_bus: i2c4-bus {
- samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi1_bus: spi1-bus {
- samsung,pins = "gpb-4", "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c5_bus: i2c5-bus {
- samsung,pins = "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s1_bus: i2s1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm1_bus: pcm1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- ac97_bus: ac97-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s2_bus: i2s2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm2_bus: pcm2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spdif_bus: spdif-bus {
- samsung,pins = "gpc1-0", "gpc1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c6_bus: i2c6-bus {
- samsung,pins = "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi2_bus: spi2-bus {
- samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c7_bus: i2c7-bus {
- samsung,pins = "gpd0-2", "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c0_bus: i2c0-bus {
- samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c1_bus: i2c1-bus {
- samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm0_out: pwm0-out {
- samsung,pins = "gpd0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm1_out: pwm1-out {
- samsung,pins = "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm2_out: pwm2-out {
- samsung,pins = "gpd0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm3_out: pwm3-out {
- samsung,pins = "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_ctrl: lcd-ctrl {
- samsung,pins = "gpd0-0", "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_sync: lcd-sync {
- samsung,pins = "gpf0-0", "gpf0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_en: lcd-en {
- samsung,pins = "gpe3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_clk: lcd-clk {
- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_data16: lcd-data-width16 {
- samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
- "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
- "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_data18: lcd-data-width18 {
- samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
- "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
- "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
- "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_data24: lcd-data-width24 {
- samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
- "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
- "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
- };
-
- pinctrl@11000000 {
- gpj0: gpj0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpj1: gpj1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk0: gpk0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk1: gpk1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk2: gpk2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk3: gpk3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl0: gpl0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl1: gpl1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl2: gpl2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpy0: gpy0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy1: gpy1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy2: gpy2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy3: gpy3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy4: gpy4 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy5: gpy5 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy6: gpy6 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpx0: gpx0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- };
-
- gpx1: gpx1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- };
-
- gpx2: gpx2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx3: gpx3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk: sd0-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cmd: sd0-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cd: sd0-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus1: sd0-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus4: sd0-bus-width4 {
- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus8: sd0-bus-width8 {
- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_clk: sd4-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_cmd: sd4-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_cd: sd4-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_bus1: sd4-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_bus4: sd4-bus-width4 {
- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_bus8: sd4-bus-width8 {
- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_clk: sd1-clk {
- samsung,pins = "gpk1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cmd: sd1-cmd {
- samsung,pins = "gpk1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cd: sd1-cd {
- samsung,pins = "gpk1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus1: sd1-bus-width1 {
- samsung,pins = "gpk1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus4: sd1-bus-width4 {
- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_clk: sd2-clk {
- samsung,pins = "gpk2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cmd: sd2-cmd {
- samsung,pins = "gpk2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cd: sd2-cd {
- samsung,pins = "gpk2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus1: sd2-bus-width1 {
- samsung,pins = "gpk2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus4: sd2-bus-width4 {
- samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus8: sd2-bus-width8 {
- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_clk: sd3-clk {
- samsung,pins = "gpk3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_cmd: sd3-cmd {
- samsung,pins = "gpk3-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_cd: sd3-cd {
- samsung,pins = "gpk3-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_bus1: sd3-bus-width1 {
- samsung,pins = "gpk3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_bus4: sd3-bus-width4 {
- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- eint0: ext-int0 {
- samsung,pins = "gpx0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint8: ext-int8 {
- samsung,pins = "gpx1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint15: ext-int15 {
- samsung,pins = "gpx1-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint16: ext-int16 {
- samsung,pins = "gpx2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint31: ext-int31 {
- samsung,pins = "gpx3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_a_io: cam-port-a-io {
- samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
- "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
- "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_a_clk_active: cam-port-a-clk-active {
- samsung,pins = "gpj1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_a_clk_idle: cam-port-a-clk-idle {
- samsung,pins = "gpj1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- hdmi_cec: hdmi-cec {
- samsung,pins = "gpx3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
- };
-
- pinctrl@3860000 {
- gpz: gpz {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- i2s0_bus: i2s0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4", "gpz-5", "gpz-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm0_bus: pcm0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
+ pcm0_bus: pcm0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index aaade17b140e..eaeeb4f6b84a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -148,43 +148,12 @@
};
};
- camera {
- pinctrl-names = "default";
- pinctrl-0 = <>;
- status = "okay";
-
- fimc_0: fimc@11800000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC0>,
- <&clock CLK_SCLK_FIMC0>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
-
- fimc_1: fimc@11810000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC1>,
- <&clock CLK_SCLK_FIMC1>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
-
- fimc_2: fimc@11820000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC2>,
- <&clock CLK_SCLK_FIMC2>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
+};
- fimc_3: fimc@11830000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC3>,
- <&clock CLK_SCLK_FIMC3>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
- };
+&camera {
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ status = "okay";
};
&cpu0 {
@@ -234,6 +203,38 @@
vbus-supply = <&safe1_sreg>;
};
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_1 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+ <&clock CLK_SCLK_FIMC1>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_2 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+ <&clock CLK_SCLK_FIMC2>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_3 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+ <&clock CLK_SCLK_FIMC3>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
&fimd {
status = "okay";
};
@@ -275,6 +276,7 @@
max8997_pmic@66 {
compatible = "maxim,max8997-pmic";
+ interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>;
reg = <0x66>;
interrupt-parent = <&gpx0>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 21fff7cd3aa4..4e6ff97e1ec4 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,24 +28,6 @@
stdout-path = &serial_2;
};
- sysram@2020000 {
- smp-sysram@0 {
- status = "disabled";
- };
-
- smp-sysram@5000 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x5000 0x1000>;
- };
-
- smp-sysram@1f000 {
- status = "disabled";
- };
- };
-
- mct@10050000 {
- compatible = "none";
- };
fixed-rate-clocks {
xxti {
@@ -173,45 +155,6 @@
};
};
- camera {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <>;
-
- fimc_0: fimc@11800000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC0>,
- <&clock CLK_SCLK_FIMC0>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
-
- fimc_1: fimc@11810000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC1>,
- <&clock CLK_SCLK_FIMC1>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
-
- fimc_2: fimc@11820000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC2>,
- <&clock CLK_SCLK_FIMC2>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
-
- fimc_3: fimc@11830000 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC3>,
- <&clock CLK_SCLK_FIMC3>;
- assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
- assigned-clock-rates = <0>, <160000000>;
- };
- };
-
hdmi_en: voltage-regulator-hdmi-5v {
compatible = "regulator-fixed";
regulator-name = "HDMI_5V";
@@ -234,6 +177,13 @@
};
};
+&camera {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+};
+
&cpu0 {
cpu0-supply = <&vdd_arm_reg>;
};
@@ -250,6 +200,38 @@
vbus-supply = <&safeout1_reg>;
};
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_1 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+ <&clock CLK_SCLK_FIMC1>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_2 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+ <&clock CLK_SCLK_FIMC2>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_3 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+ <&clock CLK_SCLK_FIMC3>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
&fimd {
pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
pinctrl-names = "default";
@@ -501,6 +483,10 @@
status = "okay";
};
+&mct {
+ compatible = "none";
+};
+
&mdma1 {
reg = <0x12840000 0x1000>;
};
@@ -579,3 +565,18 @@
/delete-property/dmas;
/delete-property/dma-names;
};
+
+&sysram {
+ smp-sysram@0 {
+ status = "disabled";
+ };
+
+ smp-sysram@5000 {
+ compatible = "samsung,exynos4210-sysram";
+ reg = <0x5000 0x1000>;
+ };
+
+ smp-sysram@1f000 {
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index cc978cf28267..88fb47cef9a8 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -17,7 +17,6 @@
*/
#include "exynos4.dtsi"
-#include "exynos4210-pinctrl.dtsi"
#include "exynos4-cpu-thermal.dtsi"
/ {
@@ -49,8 +48,6 @@
400000 975000
200000 950000
>;
- cooling-min-level = <4>;
- cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -61,365 +58,323 @@
};
};
- sysram: sysram@2020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x20000>;
+ soc: soc {
+ sysram: sysram@2020000 {
+ compatible = "mmio-sram";
+ reg = <0x02020000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x02020000 0x20000>;
- smp-sysram@0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
+ smp-sysram@0 {
+ compatible = "samsung,exynos4210-sysram";
+ reg = <0x0 0x1000>;
+ };
- smp-sysram@1f000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x1f000 0x1000>;
+ smp-sysram@1f000 {
+ compatible = "samsung,exynos4210-sysram-ns";
+ reg = <0x1f000 0x1000>;
+ };
};
- };
- pd_lcd1: lcd1-power-domain@10023ca0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023CA0 0x20>;
- #power-domain-cells = <0>;
- label = "LCD1";
- };
+ pd_lcd1: lcd1-power-domain@10023ca0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023CA0 0x20>;
+ #power-domain-cells = <0>;
+ label = "LCD1";
+ };
- l2c: l2-cache-controller@10502000 {
- compatible = "arm,pl310-cache";
- reg = <0x10502000 0x1000>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <2 2 1>;
- arm,data-latency = <2 2 1>;
- };
+ l2c: l2-cache-controller@10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <2 2 1>;
+ arm,data-latency = <2 2 1>;
+ };
- mct: mct@10050000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+ mct: mct@10050000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map =
+ <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
- };
- watchdog: watchdog@10060000 {
- compatible = "samsung,s3c6410-wdt";
- reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_WDT>;
- clock-names = "watchdog";
- };
-
- clock: clock-controller@10030000 {
- compatible = "samsung,exynos4210-clock";
- reg = <0x10030000 0x20000>;
- #clock-cells = <1>;
- };
-
- pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,exynos4210-pinctrl";
- reg = <0x11400000 0x1000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_1: pinctrl@11000000 {
- compatible = "samsung,exynos4210-pinctrl";
- reg = <0x11000000 0x1000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-
- wakup_eint: wakeup-interrupt-controller {
- compatible = "samsung,exynos4210-wakeup-eint";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ watchdog: watchdog@10060000 {
+ compatible = "samsung,s3c6410-wdt";
+ reg = <0x10060000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_WDT>;
+ clock-names = "watchdog";
};
- };
- pinctrl_2: pinctrl@3860000 {
- compatible = "samsung,exynos4210-pinctrl";
- reg = <0x03860000 0x1000>;
- };
+ clock: clock-controller@10030000 {
+ compatible = "samsung,exynos4210-clock";
+ reg = <0x10030000 0x20000>;
+ #clock-cells = <1>;
+ };
- tmu: tmu@100c0000 {
- compatible = "samsung,exynos4210-tmu";
- interrupt-parent = <&combiner>;
- reg = <0x100C0000 0x100>;
- interrupts = <2 4>;
- clocks = <&clock CLK_TMU_APBIF>;
- clock-names = "tmu_apbif";
- samsung,tmu_gain = <15>;
- samsung,tmu_reference_voltage = <7>;
- status = "disabled";
- };
+ pinctrl_0: pinctrl@11400000 {
+ compatible = "samsung,exynos4210-pinctrl";
+ reg = <0x11400000 0x1000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&tmu 0>;
+ pinctrl_1: pinctrl@11000000 {
+ compatible = "samsung,exynos4210-pinctrl";
+ reg = <0x11000000 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- trips {
- cpu_alert0: cpu-alert-0 {
- temperature = <85000>; /* millicelsius */
- };
- cpu_alert1: cpu-alert-1 {
- temperature = <100000>; /* millicelsius */
- };
- cpu_alert2: cpu-alert-2 {
- temperature = <110000>; /* millicelsius */
- };
+ wakup_eint: wakeup-interrupt-controller {
+ compatible = "samsung,exynos4210-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
- };
-
- g2d: g2d@12800000 {
- compatible = "samsung,s5pv210-g2d";
- reg = <0x12800000 0x1000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
- clock-names = "sclk_fimg2d", "fimg2d";
- power-domains = <&pd_lcd0>;
- iommus = <&sysmmu_g2d>;
- };
- camera {
- clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
- <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
- clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+ pinctrl_2: pinctrl@3860000 {
+ compatible = "samsung,exynos4210-pinctrl";
+ reg = <0x03860000 0x1000>;
+ };
- fimc_0: fimc@11800000 {
- samsung,pix-limits = <4224 8192 1920 4224>;
- samsung,mainscaler-ext;
- samsung,cam-if;
+ g2d: g2d@12800000 {
+ compatible = "samsung,s5pv210-g2d";
+ reg = <0x12800000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
+ clock-names = "sclk_fimg2d", "fimg2d";
+ power-domains = <&pd_lcd0>;
+ iommus = <&sysmmu_g2d>;
};
- fimc_1: fimc@11810000 {
- samsung,pix-limits = <4224 8192 1920 4224>;
- samsung,mainscaler-ext;
- samsung,cam-if;
+ ppmu_acp: ppmu_acp@10ae0000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10ae0000 0x2000>;
+ status = "disabled";
};
- fimc_2: fimc@11820000 {
- samsung,pix-limits = <4224 8192 1920 4224>;
- samsung,mainscaler-ext;
- samsung,lcd-wb;
+ ppmu_lcd1: ppmu_lcd1@12240000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x12240000 0x2000>;
+ clocks = <&clock CLK_PPMULCD1>;
+ clock-names = "ppmu";
+ status = "disabled";
};
- fimc_3: fimc@11830000 {
- samsung,pix-limits = <1920 8192 1366 1920>;
- samsung,rotators = <0>;
- samsung,mainscaler-ext;
- samsung,lcd-wb;
+ sysmmu_g2d: sysmmu@12a20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12A20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 7>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+ power-domains = <&pd_lcd0>;
+ #iommu-cells = <0>;
};
- };
- mixer: mixer@12c10000 {
- clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
- "sclk_mixer";
- clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
- <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
- <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
- };
+ sysmmu_fimd1: sysmmu@12220000 {
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ reg = <0x12220000 0x1000>;
+ interrupts = <5 3>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
+ power-domains = <&pd_lcd1>;
+ #iommu-cells = <0>;
+ };
- ppmu_lcd1: ppmu_lcd1@12240000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x12240000 0x2000>;
- clocks = <&clock CLK_PPMULCD1>;
- clock-names = "ppmu";
- status = "disabled";
- };
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
- sysmmu_g2d: sysmmu@12a20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12A20000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 7>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
- power-domains = <&pd_lcd0>;
- #iommu-cells = <0>;
- };
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_acp_opp_table>;
+ status = "disabled";
+ };
- sysmmu_fimd1: sysmmu@12220000 {
- compatible = "samsung,exynos-sysmmu";
- interrupt-parent = <&combiner>;
- reg = <0x12220000 0x1000>;
- interrupts = <5 3>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
- power-domains = <&pd_lcd1>;
- #iommu-cells = <0>;
- };
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_peri_opp_table>;
+ status = "disabled";
+ };
- bus_dmc: bus_dmc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_DMC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- status = "disabled";
- };
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_fsys_opp_table>;
+ status = "disabled";
+ };
- bus_acp: bus_acp {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_ACP>;
- clock-names = "bus";
- operating-points-v2 = <&bus_acp_opp_table>;
- status = "disabled";
- };
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_display_opp_table>;
+ status = "disabled";
+ };
- bus_peri: bus_peri {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK100>;
- clock-names = "bus";
- operating-points-v2 = <&bus_peri_opp_table>;
- status = "disabled";
- };
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK200>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
- bus_fsys: bus_fsys {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK133>;
- clock-names = "bus";
- operating-points-v2 = <&bus_fsys_opp_table>;
- status = "disabled";
- };
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
- bus_display: bus_display {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK160>;
- clock-names = "bus";
- operating-points-v2 = <&bus_display_opp_table>;
- status = "disabled";
- };
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
- bus_lcd0: bus_lcd0 {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK200>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
- bus_leftbus: bus_leftbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDL>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
- bus_rightbus: bus_rightbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDR>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_mfc: bus_mfc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_SCLK_MFC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1150000>;
+ };
+ };
- bus_dmc_opp_table: opp_table1 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <1025000>;
- };
- opp-267000000 {
- opp-hz = /bits/ 64 <267000000>;
- opp-microvolt = <1050000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1150000>;
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
};
- };
- bus_acp_opp_table: opp_table2 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_peri_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
};
- };
- bus_peri_opp_table: opp_table3 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_fsys_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-5000000 {
- opp-hz = /bits/ 64 <5000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
};
- };
- bus_fsys_opp_table: opp_table4 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_display_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-10000000 {
- opp-hz = /bits/ 64 <10000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
};
- };
- bus_display_opp_table: opp_table5 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_leftbus_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
};
};
- bus_leftbus_opp_table: opp_table6 {
- compatible = "operating-points-v2";
- opp-shared;
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu 0>;
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
+ trips {
+ cpu_alert0: cpu-alert-0 {
+ temperature = <85000>; /* millicelsius */
+ };
+ cpu_alert1: cpu-alert-1 {
+ temperature = <100000>; /* millicelsius */
+ };
+ cpu_alert2: cpu-alert-2 {
+ temperature = <110000>; /* millicelsius */
+ };
+ };
};
};
};
@@ -428,6 +383,12 @@
cpu-offset = <0x8000>;
};
+&camera {
+ clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
+ <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
+ clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+};
+
&combiner {
samsung,combiner-nr = <16>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -448,10 +409,43 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
+&fimc_0 {
+ samsung,pix-limits = <4224 8192 1920 4224>;
+ samsung,mainscaler-ext;
+ samsung,cam-if;
+};
+
+&fimc_1 {
+ samsung,pix-limits = <4224 8192 1920 4224>;
+ samsung,mainscaler-ext;
+ samsung,cam-if;
+};
+
+&fimc_2 {
+ samsung,pix-limits = <4224 8192 1920 4224>;
+ samsung,mainscaler-ext;
+ samsung,lcd-wb;
+};
+
+&fimc_3 {
+ samsung,pix-limits = <1920 8192 1366 1920>;
+ samsung,rotators = <0>;
+ samsung,mainscaler-ext;
+ samsung,lcd-wb;
+};
+
&mdma1 {
power-domains = <&pd_lcd0>;
};
+&mixer {
+ clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
+ "sclk_mixer";
+ clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
+ <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
+ <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
+};
+
&pmu_system_controller {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
@@ -468,3 +462,13 @@
&sysmmu_rotator {
power-domains = <&pd_lcd0>;
};
+
+&tmu {
+ compatible = "samsung,exynos4210-tmu";
+ clocks = <&clock CLK_TMU_APBIF>;
+ clock-names = "tmu_apbif";
+ samsung,tmu_gain = <15>;
+ samsung,tmu_reference_voltage = <7>;
+};
+
+#include "exynos4210-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
new file mode 100644
index 000000000000..ee8e1f445370
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4412 based Galaxy S3 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ */
+
+/dts-v1/;
+#include "exynos4412-midas.dtsi"
+
+/ {
+ aliases {
+ i2c9 = &i2c_ak8975;
+ i2c10 = &i2c_cm36651;
+ };
+
+ regulators {
+ lcd_vdd3_reg: voltage-regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_VDD_2.2V";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ ps_als_reg: voltage-regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_A_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ i2c_ak8975: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ak8975@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+ gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c_cm36651: i2c-gpio-2 {
+ compatible = "i2c-gpio";
+ gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cm36651@18 {
+ compatible = "capella,cm36651";
+ reg = <0x18>;
+ interrupt-parent = <&gpx0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vled-supply = <&ps_als_reg>;
+ };
+ };
+};
+
+&buck9_reg {
+ maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
+};
+
+&cam_af_reg {
+ gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&cam_io_reg {
+ gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&dsi_0 {
+ status = "okay";
+
+ panel@0 {
+ compatible = "samsung,s6e8aa0";
+ reg = <0>;
+ vdd3-supply = <&lcd_vdd3_reg>;
+ vci-supply = <&ldo25_reg>;
+ reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
+ power-on-delay= <50>;
+ reset-delay = <100>;
+ init-delay = <100>;
+ flip-horizontal;
+ flip-vertical;
+ panel-width-mm = <58>;
+ panel-height-mm = <103>;
+
+ display-timings {
+ timing-0 {
+ clock-frequency = <57153600>;
+ hactive = <720>;
+ vactive = <1280>;
+ hfront-porch = <5>;
+ hback-porch = <5>;
+ hsync-len = <5>;
+ vfront-porch = <13>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+ };
+};
+
+&i2c_3 {
+ mms114-touchscreen@48 {
+ compatible = "melfas,mms114";
+ reg = <0x48>;
+ interrupt-parent = <&gpm2>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ x-size = <720>;
+ y-size = <1280>;
+ avdd-supply = <&ldo23_reg>;
+ vdd-supply = <&ldo24_reg>;
+ };
+};
+
+&ldo25_reg {
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
+&s5c73m3 {
+ standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */
+ vdda-supply = <&ldo17_reg>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts
new file mode 100644
index 000000000000..f8125a945f8d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-i9300.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ */
+
+/dts-v1/;
+#include "exynos4412-galaxy-s3.dtsi"
+
+/ {
+ model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412";
+ compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+
+ /* bootargs are passed in by bootloader */
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/exynos4412-i9305.dts
new file mode 100644
index 000000000000..54a2a55dbf70
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-i9305.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "exynos4412-galaxy-s3.dtsi"
+
+/ {
+ model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412";
+ compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+
+ /* bootargs are passed in by bootloader */
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+};
+
+&i2c0_bus {
+ /* SCL and SDA pins are swapped */
+ samsung,pins = "gpd1-1", "gpd1-0";
+};
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
index a4cd4939fe9a..0dedeba89b5f 100644
--- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -116,14 +116,6 @@
compatible = "pwm-beeper";
pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
};
-
- camera: camera {
- pinctrl-0 = <&cam_port_a_clk_active>;
- pinctrl-names = "default";
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_CAM0>;
- assigned-clock-parents = <&clock CLK_XUSBXTI>;
- };
};
&adc {
@@ -131,6 +123,14 @@
status = "okay";
};
+&camera {
+ pinctrl-0 = <&cam_port_a_clk_active>;
+ pinctrl-names = "default";
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_CAM0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+};
+
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
new file mode 100644
index 000000000000..76f2b30f1731
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -0,0 +1,1308 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4412 based Trats 2 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Trats 2 board which is based on
+ * Samsung's Exynos4412 SoC.
+ */
+
+/dts-v1/;
+#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77686.h>
+#include <dt-bindings/pinctrl/samsung.h>
+
+/ {
+ compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+
+ aliases {
+ i2c11 = &i2c_max77693;
+ i2c12 = &i2c_max77693_fuel;
+ };
+
+ chosen {
+ stdout-path = &serial_2;
+ };
+
+ firmware@204f000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0204F000 0x1000>;
+ };
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti", "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cam_io_reg: voltage-regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM_SENSOR_A";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ cam_af_reg: voltage-regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM_AF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vsil12: voltage-regulator-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSIL_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&buck7_reg>;
+ };
+
+ vcc33mhl: voltage-regulator-7 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3.3_MHL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc18mhl: voltage-regulator-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1.8_MHL";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-down {
+ gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
+ linux,code = <114>;
+ label = "volume down";
+ debounce-interval = <10>;
+ };
+
+ key-up {
+ gpios = <&gpx2 2 GPIO_ACTIVE_LOW>;
+ linux,code = <115>;
+ label = "volume up";
+ debounce-interval = <10>;
+ };
+
+ key-power {
+ gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
+ linux,code = <116>;
+ label = "power";
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+
+ key-ok {
+ gpios = <&gpx0 1 GPIO_ACTIVE_LOW>;
+ linux,code = <139>;
+ label = "ok";
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ i2c_max77693: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ max77693@66 {
+ compatible = "maxim,max77693";
+ interrupt-parent = <&gpx1>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0x66>;
+
+ regulators {
+ esafeout1_reg: ESAFEOUT1 {
+ regulator-name = "ESAFEOUT1";
+ };
+ esafeout2_reg: ESAFEOUT2 {
+ regulator-name = "ESAFEOUT2";
+ };
+ charger_reg: CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <60000>;
+ regulator-max-microamp = <2580000>;
+ };
+ };
+
+ max77693_haptic {
+ compatible = "maxim,max77693-haptic";
+ haptic-supply = <&ldo26_reg>;
+ pwms = <&pwm 0 38022 0>;
+ };
+
+ charger {
+ compatible = "maxim,max77693-charger";
+
+ maxim,constant-microvolt = <4350000>;
+ maxim,min-system-microvolt = <3600000>;
+ maxim,thermal-regulation-celsius = <100>;
+ maxim,battery-overcurrent-microamp = <3500000>;
+ maxim,charge-input-threshold-microvolt = <4300000>;
+ };
+ };
+ };
+
+ i2c_max77693_fuel: i2c-gpio-3 {
+ compatible = "i2c-gpio";
+ gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ max77693-fuel-gauge@36 {
+ compatible = "maxim,max17047";
+ interrupt-parent = <&gpx2>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0x36>;
+
+ maxim,over-heat-temp = <700>;
+ maxim,over-volt = <4500>;
+ };
+ };
+
+ i2c-mhl {
+ compatible = "i2c-gpio";
+ gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
+ i2c-gpio,delay-us = <100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&i2c_mhl_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ sii9234: hdmi-bridge@39 {
+ compatible = "sil,sii9234";
+ avcc33-supply = <&vcc33mhl>;
+ iovcc18-supply = <&vcc18mhl>;
+ avcc12-supply = <&vsil12>;
+ cvcc12-supply = <&vsil12>;
+ reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpf3>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x39>;
+
+ port {
+ mhl_to_hdmi: endpoint {
+ remote-endpoint = <&hdmi_to_mhl>;
+ };
+ };
+ };
+ };
+
+ wlan_pwrseq: sdhci3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>;
+ clocks = <&max77686 MAX77686_CLK_PMIC>;
+ clock-names = "ext_clock";
+ };
+
+ sound {
+ compatible = "samsung,trats2-audio";
+ samsung,i2s-controller = <&i2s0>;
+ samsung,model = "Trats2";
+ samsung,audio-codec = <&wm1811>;
+ samsung,audio-routing =
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+ "SPK", "SPKOUTRN",
+ "SPK", "SPKOUTRP";
+ };
+
+ thermistor-ap {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>; /* VCC_1.8V_AP */
+ pullup-ohm = <100000>; /* 100K */
+ pulldown-ohm = <100000>; /* 100K */
+ io-channels = <&adc 1>; /* AP temperature */
+ };
+
+ thermistor-battery {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>; /* VCC_1.8V_AP */
+ pullup-ohm = <100000>; /* 100K */
+ pulldown-ohm = <100000>; /* 100K */
+ io-channels = <&adc 2>; /* Battery temperature */
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>;
+ };
+ };
+ };
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&bus_dmc {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&bus_acp {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_c2c {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_leftbus {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-supply = <&buck3_reg>;
+ status = "okay";
+};
+
+&bus_rightbus {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_display {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&camera {
+ pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
+ pinctrl-names = "default";
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_CAM0>,
+ <&clock CLK_MOUT_CAM1>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>,
+ <&clock CLK_XUSBXTI>;
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
+};
+
+&csis_0 {
+ status = "okay";
+ vddcore-supply = <&ldo8_reg>;
+ vddio-supply = <&ldo10_reg>;
+ assigned-clocks = <&clock CLK_MOUT_CSIS0>,
+ <&clock CLK_SCLK_CSIS0>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+
+ /* Camera C (3) MIPI CSI-2 (CSIS0) */
+ port@3 {
+ reg = <3>;
+ csis0_ep: endpoint {
+ remote-endpoint = <&s5c73m3_ep>;
+ data-lanes = <1 2 3 4>;
+ samsung,csis-hs-settle = <12>;
+ };
+ };
+};
+
+&csis_1 {
+ status = "okay";
+ vddcore-supply = <&ldo8_reg>;
+ vddio-supply = <&ldo10_reg>;
+ assigned-clocks = <&clock CLK_MOUT_CSIS1>,
+ <&clock CLK_SCLK_CSIS1>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+
+ /* Camera D (4) MIPI CSI-2 (CSIS1) */
+ port@4 {
+ reg = <4>;
+ csis1_ep: endpoint {
+ remote-endpoint = <&is_s5k6a3_ep>;
+ data-lanes = <1>;
+ samsung,csis-hs-settle = <18>;
+ samsung,csis-wclk;
+ };
+ };
+};
+
+&dsi_0 {
+ vddcore-supply = <&ldo8_reg>;
+ vddio-supply = <&ldo10_reg>;
+ samsung,burst-clock-frequency = <500000000>;
+ samsung,esc-clock-frequency = <20000000>;
+ samsung,pll-clock-frequency = <24000000>;
+};
+
+&exynos_usbphy {
+ vbus-supply = <&esafeout1_reg>;
+ status = "okay";
+};
+
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_1 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+ <&clock CLK_SCLK_FIMC1>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_2 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+ <&clock CLK_SCLK_FIMC2>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_3 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+ <&clock CLK_SCLK_FIMC3>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_is {
+ pinctrl-0 = <&fimc_is_uart>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ };
+
+&fimc_lite_0 {
+ status = "okay";
+};
+
+&fimc_lite_1 {
+ status = "okay";
+};
+
+&fimd {
+ status = "okay";
+};
+
+&hdmi {
+ hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_hpd>;
+ vdd-supply = <&ldo3_reg>;
+ vdd_osc-supply = <&ldo4_reg>;
+ vdd_pll-supply = <&ldo3_reg>;
+ ddc = <&i2c_5>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ hdmi_to_mhl: endpoint {
+ remote-endpoint = <&mhl_to_hdmi>;
+ };
+ };
+ };
+};
+
+&hsotg {
+ vusb_d-supply = <&ldo15_reg>;
+ vusb_a-supply = <&ldo12_reg>;
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&i2c_0 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ s5c73m3: s5c73m3@3c {
+ compatible = "samsung,s5c73m3";
+ reg = <0x3c>;
+ xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */
+ vdd-int-supply = <&buck9_reg>;
+ vddio-cis-supply = <&ldo9_reg>;
+ vddio-host-supply = <&ldo18_reg>;
+ vdd-af-supply = <&cam_af_reg>;
+ vdd-reg-supply = <&cam_io_reg>;
+ clock-frequency = <24000000>;
+ /* CAM_A_CLKOUT */
+ clocks = <&camera 0>;
+ clock-names = "cis_extclk";
+ status = "disabled";
+ port {
+ s5c73m3_ep: endpoint {
+ remote-endpoint = <&csis0_ep>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+ };
+};
+
+&i2c1_isp {
+ pinctrl-0 = <&fimc_is_i2c1>;
+ pinctrl-names = "default";
+
+ s5k6a3@10 {
+ compatible = "samsung,s5k6a3";
+ reg = <0x10>;
+ svdda-supply = <&cam_io_reg>;
+ svddio-supply = <&ldo19_reg>;
+ afvdd-supply = <&ldo19_reg>;
+ clock-frequency = <24000000>;
+ /* CAM_B_CLKOUT */
+ clocks = <&camera 1>;
+ clock-names = "extclk";
+ samsung,camclk-out = <1>;
+ gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
+
+ port {
+ is_s5k6a3_ep: endpoint {
+ remote-endpoint = <&csis1_ep>;
+ data-lanes = <1>;
+ };
+ };
+ };
+};
+
+&i2c_3 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c3_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ pinctrl-0 = <&i2c4_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ wm1811: wm1811@1a {
+ compatible = "wlf,wm1811";
+ reg = <0x1a>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "MCLK1";
+ DCVDD-supply = <&ldo3_reg>;
+ DBVDD1-supply = <&ldo3_reg>;
+ wlf,ldo1ena = <&gpj0 4 0>;
+ };
+};
+
+&i2c_5 {
+ status = "okay";
+};
+
+&i2c_7 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ pinctrl-0 = <&i2c7_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ max77686: max77686_pmic@9 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx0>;
+ interrupts = <7 IRQ_TYPE_NONE>;
+ reg = <0x09>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "LDO25";
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
+};
+
+&i2c_8 {
+ status = "okay";
+};
+
+&i2s0 {
+ pinctrl-0 = <&i2s0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mixer {
+ status = "okay";
+};
+
+&mshc_0 {
+ broken-cd;
+ non-removable;
+ card-detect-delay = <200>;
+ vmmc-supply = <&ldo22_reg>;
+ clock-frequency = <400000000>;
+ samsung,dw-mshc-ciu-div = <0>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+ pinctrl-names = "default";
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+};
+
+&pmu_system_controller {
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+};
+
+&pinctrl_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep0>;
+
+ mhl_int: mhl-int {
+ samsung,pins = "gpf3-5";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i2c_mhl_bus: i2c-mhl-bus {
+ samsung,pins = "gpf0-4", "gpf0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ sleep0: sleep-states {
+ PIN_SLP(gpa0-0, INPUT, NONE);
+ PIN_SLP(gpa0-1, OUT0, NONE);
+ PIN_SLP(gpa0-2, INPUT, NONE);
+ PIN_SLP(gpa0-3, INPUT, UP);
+ PIN_SLP(gpa0-4, INPUT, NONE);
+ PIN_SLP(gpa0-5, INPUT, DOWN);
+ PIN_SLP(gpa0-6, INPUT, DOWN);
+ PIN_SLP(gpa0-7, INPUT, UP);
+
+ PIN_SLP(gpa1-0, INPUT, DOWN);
+ PIN_SLP(gpa1-1, INPUT, DOWN);
+ PIN_SLP(gpa1-2, INPUT, DOWN);
+ PIN_SLP(gpa1-3, INPUT, DOWN);
+ PIN_SLP(gpa1-4, INPUT, DOWN);
+ PIN_SLP(gpa1-5, INPUT, DOWN);
+
+ PIN_SLP(gpb-0, INPUT, NONE);
+ PIN_SLP(gpb-1, INPUT, NONE);
+ PIN_SLP(gpb-2, INPUT, NONE);
+ PIN_SLP(gpb-3, INPUT, NONE);
+ PIN_SLP(gpb-4, INPUT, DOWN);
+ PIN_SLP(gpb-5, INPUT, UP);
+ PIN_SLP(gpb-6, INPUT, DOWN);
+ PIN_SLP(gpb-7, INPUT, DOWN);
+
+ PIN_SLP(gpc0-0, INPUT, DOWN);
+ PIN_SLP(gpc0-1, INPUT, DOWN);
+ PIN_SLP(gpc0-2, INPUT, DOWN);
+ PIN_SLP(gpc0-3, INPUT, DOWN);
+ PIN_SLP(gpc0-4, INPUT, DOWN);
+
+ PIN_SLP(gpc1-0, INPUT, NONE);
+ PIN_SLP(gpc1-1, PREV, NONE);
+ PIN_SLP(gpc1-2, INPUT, NONE);
+ PIN_SLP(gpc1-3, INPUT, NONE);
+ PIN_SLP(gpc1-4, INPUT, NONE);
+
+ PIN_SLP(gpd0-0, INPUT, DOWN);
+ PIN_SLP(gpd0-1, INPUT, DOWN);
+ PIN_SLP(gpd0-2, INPUT, NONE);
+ PIN_SLP(gpd0-3, INPUT, NONE);
+
+ PIN_SLP(gpd1-0, INPUT, DOWN);
+ PIN_SLP(gpd1-1, INPUT, DOWN);
+ PIN_SLP(gpd1-2, INPUT, NONE);
+ PIN_SLP(gpd1-3, INPUT, NONE);
+
+ PIN_SLP(gpf0-0, INPUT, NONE);
+ PIN_SLP(gpf0-1, INPUT, NONE);
+ PIN_SLP(gpf0-2, INPUT, DOWN);
+ PIN_SLP(gpf0-3, INPUT, DOWN);
+ PIN_SLP(gpf0-4, INPUT, NONE);
+ PIN_SLP(gpf0-5, INPUT, DOWN);
+ PIN_SLP(gpf0-6, INPUT, NONE);
+ PIN_SLP(gpf0-7, INPUT, DOWN);
+
+ PIN_SLP(gpf1-0, INPUT, DOWN);
+ PIN_SLP(gpf1-1, INPUT, DOWN);
+ PIN_SLP(gpf1-2, INPUT, DOWN);
+ PIN_SLP(gpf1-3, INPUT, DOWN);
+ PIN_SLP(gpf1-4, INPUT, NONE);
+ PIN_SLP(gpf1-5, INPUT, NONE);
+ PIN_SLP(gpf1-6, INPUT, DOWN);
+ PIN_SLP(gpf1-7, PREV, NONE);
+
+ PIN_SLP(gpf2-0, PREV, NONE);
+ PIN_SLP(gpf2-1, INPUT, DOWN);
+ PIN_SLP(gpf2-2, INPUT, DOWN);
+ PIN_SLP(gpf2-3, INPUT, DOWN);
+ PIN_SLP(gpf2-4, INPUT, DOWN);
+ PIN_SLP(gpf2-5, INPUT, DOWN);
+ PIN_SLP(gpf2-6, INPUT, NONE);
+ PIN_SLP(gpf2-7, INPUT, NONE);
+
+ PIN_SLP(gpf3-0, INPUT, NONE);
+ PIN_SLP(gpf3-1, PREV, NONE);
+ PIN_SLP(gpf3-2, PREV, NONE);
+ PIN_SLP(gpf3-3, PREV, NONE);
+ PIN_SLP(gpf3-4, OUT1, NONE);
+ PIN_SLP(gpf3-5, INPUT, DOWN);
+
+ PIN_SLP(gpj0-0, PREV, NONE);
+ PIN_SLP(gpj0-1, PREV, NONE);
+ PIN_SLP(gpj0-2, PREV, NONE);
+ PIN_SLP(gpj0-3, INPUT, DOWN);
+ PIN_SLP(gpj0-4, PREV, NONE);
+ PIN_SLP(gpj0-5, PREV, NONE);
+ PIN_SLP(gpj0-6, INPUT, DOWN);
+ PIN_SLP(gpj0-7, INPUT, DOWN);
+
+ PIN_SLP(gpj1-0, INPUT, DOWN);
+ PIN_SLP(gpj1-1, PREV, NONE);
+ PIN_SLP(gpj1-2, PREV, NONE);
+ PIN_SLP(gpj1-3, INPUT, DOWN);
+ PIN_SLP(gpj1-4, INPUT, DOWN);
+ };
+};
+
+&pinctrl_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep1>;
+
+ hdmi_hpd: hdmi-hpd {
+ samsung,pins = "gpx3-7";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ sleep1: sleep-states {
+ PIN_SLP(gpk0-0, PREV, NONE);
+ PIN_SLP(gpk0-1, PREV, NONE);
+ PIN_SLP(gpk0-2, OUT0, NONE);
+ PIN_SLP(gpk0-3, PREV, NONE);
+ PIN_SLP(gpk0-4, PREV, NONE);
+ PIN_SLP(gpk0-5, PREV, NONE);
+ PIN_SLP(gpk0-6, PREV, NONE);
+
+ PIN_SLP(gpk1-0, INPUT, DOWN);
+ PIN_SLP(gpk1-1, INPUT, DOWN);
+ PIN_SLP(gpk1-2, INPUT, DOWN);
+ PIN_SLP(gpk1-3, PREV, NONE);
+ PIN_SLP(gpk1-4, PREV, NONE);
+ PIN_SLP(gpk1-5, PREV, NONE);
+ PIN_SLP(gpk1-6, PREV, NONE);
+
+ PIN_SLP(gpk2-0, INPUT, DOWN);
+ PIN_SLP(gpk2-1, INPUT, DOWN);
+ PIN_SLP(gpk2-2, INPUT, DOWN);
+ PIN_SLP(gpk2-3, INPUT, DOWN);
+ PIN_SLP(gpk2-4, INPUT, DOWN);
+ PIN_SLP(gpk2-5, INPUT, DOWN);
+ PIN_SLP(gpk2-6, INPUT, DOWN);
+
+ PIN_SLP(gpk3-0, OUT0, NONE);
+ PIN_SLP(gpk3-1, INPUT, NONE);
+ PIN_SLP(gpk3-2, INPUT, DOWN);
+ PIN_SLP(gpk3-3, INPUT, NONE);
+ PIN_SLP(gpk3-4, INPUT, NONE);
+ PIN_SLP(gpk3-5, INPUT, NONE);
+ PIN_SLP(gpk3-6, INPUT, NONE);
+
+ PIN_SLP(gpl0-0, INPUT, DOWN);
+ PIN_SLP(gpl0-1, INPUT, DOWN);
+ PIN_SLP(gpl0-2, INPUT, DOWN);
+ PIN_SLP(gpl0-3, INPUT, DOWN);
+ PIN_SLP(gpl0-4, PREV, NONE);
+ PIN_SLP(gpl0-6, PREV, NONE);
+
+ PIN_SLP(gpl1-0, INPUT, DOWN);
+ PIN_SLP(gpl1-1, INPUT, DOWN);
+ PIN_SLP(gpl2-0, INPUT, DOWN);
+ PIN_SLP(gpl2-1, INPUT, DOWN);
+ PIN_SLP(gpl2-2, INPUT, DOWN);
+ PIN_SLP(gpl2-3, INPUT, DOWN);
+ PIN_SLP(gpl2-4, INPUT, DOWN);
+ PIN_SLP(gpl2-5, INPUT, DOWN);
+ PIN_SLP(gpl2-6, PREV, NONE);
+ PIN_SLP(gpl2-7, INPUT, DOWN);
+
+ PIN_SLP(gpm0-0, INPUT, DOWN);
+ PIN_SLP(gpm0-1, INPUT, DOWN);
+ PIN_SLP(gpm0-2, INPUT, DOWN);
+ PIN_SLP(gpm0-3, INPUT, DOWN);
+ PIN_SLP(gpm0-4, INPUT, DOWN);
+ PIN_SLP(gpm0-5, INPUT, DOWN);
+ PIN_SLP(gpm0-6, INPUT, DOWN);
+ PIN_SLP(gpm0-7, INPUT, DOWN);
+
+ PIN_SLP(gpm1-0, INPUT, DOWN);
+ PIN_SLP(gpm1-1, INPUT, DOWN);
+ PIN_SLP(gpm1-2, INPUT, NONE);
+ PIN_SLP(gpm1-3, INPUT, NONE);
+ PIN_SLP(gpm1-4, INPUT, NONE);
+ PIN_SLP(gpm1-5, INPUT, NONE);
+ PIN_SLP(gpm1-6, INPUT, DOWN);
+
+ PIN_SLP(gpm2-0, INPUT, NONE);
+ PIN_SLP(gpm2-1, INPUT, NONE);
+ PIN_SLP(gpm2-2, INPUT, DOWN);
+ PIN_SLP(gpm2-3, INPUT, DOWN);
+ PIN_SLP(gpm2-4, INPUT, DOWN);
+
+ PIN_SLP(gpm3-0, PREV, NONE);
+ PIN_SLP(gpm3-1, PREV, NONE);
+ PIN_SLP(gpm3-2, PREV, NONE);
+ PIN_SLP(gpm3-3, OUT1, NONE);
+ PIN_SLP(gpm3-4, INPUT, DOWN);
+ PIN_SLP(gpm3-5, INPUT, DOWN);
+ PIN_SLP(gpm3-6, INPUT, DOWN);
+ PIN_SLP(gpm3-7, INPUT, DOWN);
+
+ PIN_SLP(gpm4-0, INPUT, DOWN);
+ PIN_SLP(gpm4-1, INPUT, DOWN);
+ PIN_SLP(gpm4-2, INPUT, DOWN);
+ PIN_SLP(gpm4-3, INPUT, DOWN);
+ PIN_SLP(gpm4-4, INPUT, DOWN);
+ PIN_SLP(gpm4-5, INPUT, DOWN);
+ PIN_SLP(gpm4-6, INPUT, DOWN);
+ PIN_SLP(gpm4-7, INPUT, DOWN);
+
+ PIN_SLP(gpy0-0, INPUT, DOWN);
+ PIN_SLP(gpy0-1, INPUT, DOWN);
+ PIN_SLP(gpy0-2, INPUT, DOWN);
+ PIN_SLP(gpy0-3, INPUT, DOWN);
+ PIN_SLP(gpy0-4, INPUT, DOWN);
+ PIN_SLP(gpy0-5, INPUT, DOWN);
+
+ PIN_SLP(gpy1-0, INPUT, DOWN);
+ PIN_SLP(gpy1-1, INPUT, DOWN);
+ PIN_SLP(gpy1-2, INPUT, DOWN);
+ PIN_SLP(gpy1-3, INPUT, DOWN);
+
+ PIN_SLP(gpy2-0, PREV, NONE);
+ PIN_SLP(gpy2-1, INPUT, DOWN);
+ PIN_SLP(gpy2-2, INPUT, NONE);
+ PIN_SLP(gpy2-3, INPUT, NONE);
+ PIN_SLP(gpy2-4, INPUT, NONE);
+ PIN_SLP(gpy2-5, INPUT, NONE);
+
+ PIN_SLP(gpy3-0, INPUT, DOWN);
+ PIN_SLP(gpy3-1, INPUT, DOWN);
+ PIN_SLP(gpy3-2, INPUT, DOWN);
+ PIN_SLP(gpy3-3, INPUT, DOWN);
+ PIN_SLP(gpy3-4, INPUT, DOWN);
+ PIN_SLP(gpy3-5, INPUT, DOWN);
+ PIN_SLP(gpy3-6, INPUT, DOWN);
+ PIN_SLP(gpy3-7, INPUT, DOWN);
+
+ PIN_SLP(gpy4-0, INPUT, DOWN);
+ PIN_SLP(gpy4-1, INPUT, DOWN);
+ PIN_SLP(gpy4-2, INPUT, DOWN);
+ PIN_SLP(gpy4-3, INPUT, DOWN);
+ PIN_SLP(gpy4-4, INPUT, DOWN);
+ PIN_SLP(gpy4-5, INPUT, DOWN);
+ PIN_SLP(gpy4-6, INPUT, DOWN);
+ PIN_SLP(gpy4-7, INPUT, DOWN);
+
+ PIN_SLP(gpy5-0, INPUT, DOWN);
+ PIN_SLP(gpy5-1, INPUT, DOWN);
+ PIN_SLP(gpy5-2, INPUT, DOWN);
+ PIN_SLP(gpy5-3, INPUT, DOWN);
+ PIN_SLP(gpy5-4, INPUT, DOWN);
+ PIN_SLP(gpy5-5, INPUT, DOWN);
+ PIN_SLP(gpy5-6, INPUT, DOWN);
+ PIN_SLP(gpy5-7, INPUT, DOWN);
+
+ PIN_SLP(gpy6-0, INPUT, DOWN);
+ PIN_SLP(gpy6-1, INPUT, DOWN);
+ PIN_SLP(gpy6-2, INPUT, DOWN);
+ PIN_SLP(gpy6-3, INPUT, DOWN);
+ PIN_SLP(gpy6-4, INPUT, DOWN);
+ PIN_SLP(gpy6-5, INPUT, DOWN);
+ PIN_SLP(gpy6-6, INPUT, DOWN);
+ PIN_SLP(gpy6-7, INPUT, DOWN);
+ };
+};
+
+&pinctrl_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep2>;
+
+ sleep2: sleep-states {
+ PIN_SLP(gpz-0, INPUT, DOWN);
+ PIN_SLP(gpz-1, INPUT, DOWN);
+ PIN_SLP(gpz-2, INPUT, DOWN);
+ PIN_SLP(gpz-3, INPUT, DOWN);
+ PIN_SLP(gpz-4, INPUT, DOWN);
+ PIN_SLP(gpz-5, INPUT, DOWN);
+ PIN_SLP(gpz-6, INPUT, DOWN);
+ };
+};
+
+&pinctrl_3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep3>;
+
+ sleep3: sleep-states {
+ PIN_SLP(gpv0-0, INPUT, DOWN);
+ PIN_SLP(gpv0-1, INPUT, DOWN);
+ PIN_SLP(gpv0-2, INPUT, DOWN);
+ PIN_SLP(gpv0-3, INPUT, DOWN);
+ PIN_SLP(gpv0-4, INPUT, DOWN);
+ PIN_SLP(gpv0-5, INPUT, DOWN);
+ PIN_SLP(gpv0-6, INPUT, DOWN);
+ PIN_SLP(gpv0-7, INPUT, DOWN);
+
+ PIN_SLP(gpv1-0, INPUT, DOWN);
+ PIN_SLP(gpv1-1, INPUT, DOWN);
+ PIN_SLP(gpv1-2, INPUT, DOWN);
+ PIN_SLP(gpv1-3, INPUT, DOWN);
+ PIN_SLP(gpv1-4, INPUT, DOWN);
+ PIN_SLP(gpv1-5, INPUT, DOWN);
+ PIN_SLP(gpv1-6, INPUT, DOWN);
+ PIN_SLP(gpv1-7, INPUT, DOWN);
+
+ PIN_SLP(gpv2-0, INPUT, DOWN);
+ PIN_SLP(gpv2-1, INPUT, DOWN);
+ PIN_SLP(gpv2-2, INPUT, DOWN);
+ PIN_SLP(gpv2-3, INPUT, DOWN);
+ PIN_SLP(gpv2-4, INPUT, DOWN);
+ PIN_SLP(gpv2-5, INPUT, DOWN);
+ PIN_SLP(gpv2-6, INPUT, DOWN);
+ PIN_SLP(gpv2-7, INPUT, DOWN);
+
+ PIN_SLP(gpv3-0, INPUT, DOWN);
+ PIN_SLP(gpv3-1, INPUT, DOWN);
+ PIN_SLP(gpv3-2, INPUT, DOWN);
+ PIN_SLP(gpv3-3, INPUT, DOWN);
+ PIN_SLP(gpv3-4, INPUT, DOWN);
+ PIN_SLP(gpv3-5, INPUT, DOWN);
+ PIN_SLP(gpv3-6, INPUT, DOWN);
+ PIN_SLP(gpv3-7, INPUT, DOWN);
+
+ PIN_SLP(gpv4-0, INPUT, DOWN);
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm0_out>;
+ pinctrl-names = "default";
+ samsung,pwm-outputs = <0>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&sdhci_2 {
+ bus-width = <4>;
+ cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+ pinctrl-names = "default";
+ vmmc-supply = <&ldo21_reg>;
+ status = "okay";
+};
+
+&sdhci_3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ non-removable;
+ bus-width = <4>;
+
+ mmc-pwrseq = <&wlan_pwrseq>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpx2>;
+ interrupts = <5 IRQ_TYPE_NONE>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&serial_0 {
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
+
+&serial_3 {
+ status = "okay";
+};
+
+&spi_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ s5c73m3_spi: s5c73m3@0 {
+ compatible = "samsung,s5c73m3";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ controller-data {
+ samsung,spi-feedback-delay = <2>;
+ };
+ };
+};
+
+&tmu {
+ vtmu-supply = <&ldo10_reg>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts
new file mode 100644
index 000000000000..eb402a0d6651
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-n710x.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "exynos4412-midas.dtsi"
+
+/ {
+ compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+ model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
+ /* bootargs are passed in by bootloader */
+
+ regulators {
+ cam_vdda_reg: voltage-regulator-9 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+};
+
+&buck9_reg {
+ maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>;
+};
+
+&cam_af_reg {
+ gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&cam_io_reg {
+ gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c_3 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c3_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mms152-touchscreen@48 {
+ compatible = "melfas,mms152";
+ reg = <0x48>;
+ interrupt-parent = <&gpm2>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ x-size = <720>;
+ y-size = <1280>;
+ avdd-supply = <&ldo23_reg>;
+ vdd-supply = <&ldo24_reg>;
+ };
+};
+
+&ldo13_reg {
+ regulator-name = "VCC_1.8V_LCD";
+ regulator-always-on;
+};
+
+&ldo25_reg {
+ regulator-name = "VCI_3.0V_LCD";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+};
+
+&s5c73m3 {
+ standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */
+ vdda-supply = <&cam_vdda_reg>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 556ea78b8e32..d7ad07fd48f9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -61,12 +61,6 @@
reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>;
};
- camera {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <>;
- };
-
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
@@ -142,6 +136,12 @@
status = "okay";
};
+&camera {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+};
+
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
index e8dd5f2d976f..d7d5fdc230d8 100644
--- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
@@ -18,964 +18,962 @@
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
}
-/ {
- pinctrl_0: pinctrl@11400000 {
- gpa0: gpa0 {
- gpio-controller;
- #gpio-cells = <2>;
+&pinctrl_0 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpa1: gpa1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpb: gpb {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc0: gpc0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd0: gpd0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpd1: gpd1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf0: gpf0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf2: gpf2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf3: gpf3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpj0: gpj0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpj1: gpj1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart0_data: uart0-data {
- samsung,pins = "gpa0-0", "gpa0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart0_fctl: uart0-fctl {
- samsung,pins = "gpa0-2", "gpa0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_data: uart1-data {
- samsung,pins = "gpa0-4", "gpa0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart1_fctl: uart1-fctl {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c2_bus: i2c2-bus {
- samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_data: uart2-data {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart2_fctl: uart2-fctl {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart_audio_a: uart-audio-a {
- samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c3_bus: i2c3-bus {
- samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- uart_audio_b: uart-audio-b {
- samsung,pins = "gpa1-4", "gpa1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi0_bus: spi0-bus {
- samsung,pins = "gpb-0", "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c4_bus: i2c4-bus {
- samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi1_bus: spi1-bus {
- samsung,pins = "gpb-4", "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c5_bus: i2c5-bus {
- samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s1_bus: i2s1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm1_bus: pcm1-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- ac97_bus: ac97-bus {
- samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
- "gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2s2_bus: i2s2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm2_bus: pcm2-bus {
- samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
- "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spdif_bus: spdif-bus {
- samsung,pins = "gpc1-0", "gpc1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c6_bus: i2c6-bus {
- samsung,pins = "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- spi2_bus: spi2-bus {
- samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm0_out: pwm0-out {
- samsung,pins = "gpd0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm1_out: pwm1-out {
- samsung,pins = "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_ctrl: lcd-ctrl {
- samsung,pins = "gpd0-0", "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c7_bus: i2c7-bus {
- samsung,pins = "gpd0-2", "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm2_out: pwm2-out {
- samsung,pins = "gpd0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pwm3_out: pwm3-out {
- samsung,pins = "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c0_bus: i2c0-bus {
- samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- mipi0_clk: mipi0-clk {
- samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- i2c1_bus: i2c1-bus {
- samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- mipi1_clk: mipi1-clk {
- samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_clk: lcd-clk {
- samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_data16: lcd-data-width16 {
- samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
- "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
- "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_data18: lcd-data-width18 {
- samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
- "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
- "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
- "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_data24: lcd-data-width24 {
- samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
- "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
- "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
- "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
- "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
- "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- lcd_ldi: lcd-ldi {
- samsung,pins = "gpf3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_a_io: cam-port-a-io {
- samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
- "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
- "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_a_clk_active: cam-port-a-clk-active {
- samsung,pins = "gpj1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_a_clk_idle: cam-port-a-clk-idle {
- samsung,pins = "gpj1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
- };
-
- pinctrl_1: pinctrl@11000000 {
- gpk0: gpk0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk1: gpk1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk2: gpk2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpk3: gpk3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl0: gpl0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl1: gpl1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpl2: gpl2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm0: gpm0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm1: gpm1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm2: gpm2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm3: gpm3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpm4: gpm4 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpy0: gpy0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy1: gpy1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy2: gpy2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy3: gpy3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy4: gpy4 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy5: gpy5 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpy6: gpy6 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpx0: gpx0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- };
-
- gpx1: gpx1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- };
-
- gpx2: gpx2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpx3: gpx3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk: sd0-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cmd: sd0-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_cd: sd0-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus1: sd0-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus4: sd0-bus-width4 {
- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd0_bus8: sd0-bus-width8 {
- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_clk: sd4-clk {
- samsung,pins = "gpk0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_cmd: sd4-cmd {
- samsung,pins = "gpk0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_cd: sd4-cd {
- samsung,pins = "gpk0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_bus1: sd4-bus-width1 {
- samsung,pins = "gpk0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_bus4: sd4-bus-width4 {
- samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd4_bus8: sd4-bus-width8 {
- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_clk: sd1-clk {
- samsung,pins = "gpk1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cmd: sd1-cmd {
- samsung,pins = "gpk1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_cd: sd1-cd {
- samsung,pins = "gpk1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus1: sd1-bus-width1 {
- samsung,pins = "gpk1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd1_bus4: sd1-bus-width4 {
- samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_clk: sd2-clk {
- samsung,pins = "gpk2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cmd: sd2-cmd {
- samsung,pins = "gpk2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_cd: sd2-cd {
- samsung,pins = "gpk2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus1: sd2-bus-width1 {
- samsung,pins = "gpk2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus4: sd2-bus-width4 {
- samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd2_bus8: sd2-bus-width8 {
- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_clk: sd3-clk {
- samsung,pins = "gpk3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_cmd: sd3-cmd {
- samsung,pins = "gpk3-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_cd: sd3-cd {
- samsung,pins = "gpk3-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_bus1: sd3-bus-width1 {
- samsung,pins = "gpk3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- sd3_bus4: sd3-bus-width4 {
- samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_io: cam-port-b-io {
- samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
- "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
- "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- cam_port_b_clk_active: cam-port-b-clk-active {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
- };
-
- cam_port_b_clk_idle: cam-port-b-clk-idle {
- samsung,pins = "gpm2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint0: ext-int0 {
- samsung,pins = "gpx0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint8: ext-int8 {
- samsung,pins = "gpx1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint15: ext-int15 {
- samsung,pins = "gpx1-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint16: ext-int16 {
- samsung,pins = "gpx2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- eint31: ext-int31 {
- samsung,pins = "gpx3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c0: fimc-is-i2c0 {
- samsung,pins = "gpm4-0", "gpm4-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_i2c1: fimc-is-i2c1 {
- samsung,pins = "gpm4-2", "gpm4-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- fimc_is_uart: fimc-is-uart {
- samsung,pins = "gpm3-5", "gpm3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- hdmi_cec: hdmi-cec {
- samsung,pins = "gpx3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
- };
-
- pinctrl_2: pinctrl@3860000 {
- gpz: gpz {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- i2s0_bus: i2s0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4", "gpz-5", "gpz-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- pcm0_bus: pcm0-bus {
- samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
- "gpz-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
- };
-
- pinctrl_3: pinctrl@106e0000 {
- gpv0: gpv0 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpv1: gpv1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpv2: gpv2 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpv3: gpv3 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpv4: gpv4 {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- c2c_bus: c2c-bus {
- samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
- "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
- "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
- "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
- "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
- "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
- "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
- "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
- "gpv4-0", "gpv4-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpj0: gpj0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpj1: gpj1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa0-4", "gpa0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart_audio_b: uart-audio-b {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = "gpb-0", "gpb-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c5_bus: i2c5-bus {
+ samsung,pins = "gpb-2", "gpb-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ ac97_bus: ac97-bus {
+ samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+ "gpc0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2s2_bus: i2s2-bus {
+ samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+ "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pcm2_bus: pcm2-bus {
+ samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+ "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spdif_bus: spdif-bus {
+ samsung,pins = "gpc1-0", "gpc1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c6_bus: i2c6-bus {
+ samsung,pins = "gpc1-3", "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm0_out: pwm0-out {
+ samsung,pins = "gpd0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm1_out: pwm1-out {
+ samsung,pins = "gpd0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_ctrl: lcd-ctrl {
+ samsung,pins = "gpd0-0", "gpd0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c7_bus: i2c7-bus {
+ samsung,pins = "gpd0-2", "gpd0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm2_out: pwm2-out {
+ samsung,pins = "gpd0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pwm3_out: pwm3-out {
+ samsung,pins = "gpd0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c0_bus: i2c0-bus {
+ samsung,pins = "gpd1-0", "gpd1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ mipi0_clk: mipi0-clk {
+ samsung,pins = "gpd1-0", "gpd1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ i2c1_bus: i2c1-bus {
+ samsung,pins = "gpd1-2", "gpd1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ mipi1_clk: mipi1-clk {
+ samsung,pins = "gpd1-2", "gpd1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_clk: lcd-clk {
+ samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_data16: lcd-data-width16 {
+ samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+ "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+ "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+ "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_data18: lcd-data-width18 {
+ samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+ "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+ "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+ "gpf3-2", "gpf3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_data24: lcd-data-width24 {
+ samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+ "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+ "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+ "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+ "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_ldi: lcd-ldi {
+ samsung,pins = "gpf3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ cam_port_a_io: cam-port-a-io {
+ samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
+ "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
+ "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ cam_port_a_clk_active: cam-port-a-clk-active {
+ samsung,pins = "gpj1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ cam_port_a_clk_idle: cam-port-a-clk-idle {
+ samsung,pins = "gpj1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_1 {
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk1: gpk1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk2: gpk2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk3: gpk3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl0: gpl0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl1: gpl1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl2: gpl2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpm0: gpm0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpm1: gpm1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpm2: gpm2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpm3: gpm3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpm4: gpm4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpy0: gpy0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy1: gpy1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy2: gpy2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy3: gpy3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy4: gpy4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy5: gpy5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy6: gpy6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpk0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpk0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_cd: sd0-cd {
+ samsung,pins = "gpk0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpk0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_clk: sd4-clk {
+ samsung,pins = "gpk0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_cmd: sd4-cmd {
+ samsung,pins = "gpk0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_cd: sd4-cd {
+ samsung,pins = "gpk0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_bus1: sd4-bus-width1 {
+ samsung,pins = "gpk0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_bus4: sd4-bus-width4 {
+ samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd4_bus8: sd4-bus-width8 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpk1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpk1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_cd: sd1-cd {
+ samsung,pins = "gpk1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpk1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd2_bus8: sd2-bus-width8 {
+ samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_clk: sd3-clk {
+ samsung,pins = "gpk3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_cmd: sd3-cmd {
+ samsung,pins = "gpk3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_cd: sd3-cd {
+ samsung,pins = "gpk3-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_bus1: sd3-bus-width1 {
+ samsung,pins = "gpk3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ sd3_bus4: sd3-bus-width4 {
+ samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ cam_port_b_io: cam-port-b-io {
+ samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+ "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+ "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ cam_port_b_clk_active: cam-port-b-clk-active {
+ samsung,pins = "gpm2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+
+ cam_port_b_clk_idle: cam-port-b-clk-idle {
+ samsung,pins = "gpm2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint0: ext-int0 {
+ samsung,pins = "gpx0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint8: ext-int8 {
+ samsung,pins = "gpx1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint15: ext-int15 {
+ samsung,pins = "gpx1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint16: ext-int16 {
+ samsung,pins = "gpx2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ eint31: ext-int31 {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ fimc_is_i2c0: fimc-is-i2c0 {
+ samsung,pins = "gpm4-0", "gpm4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ fimc_is_i2c1: fimc-is-i2c1 {
+ samsung,pins = "gpm4-2", "gpm4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ fimc_is_uart: fimc-is-uart {
+ samsung,pins = "gpm3-5", "gpm3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hdmi_cec: hdmi-cec {
+ samsung,pins = "gpx3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_2 {
+ gpz: gpz {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2s0_bus: i2s0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4", "gpz-5", "gpz-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pcm0_bus: pcm0-bus {
+ samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+ "gpz-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_3 {
+ gpv0: gpv0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpv1: gpv1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpv2: gpv2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpv3: gpv3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpv4: gpv4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ c2c_bus: c2c-bus {
+ samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
+ "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
+ "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
+ "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
+ "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
+ "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
+ "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
+ "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
+ "gpv4-0", "gpv4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
};
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 5504398e6e37..01f37b5ac9c4 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* FriendlyARM's Exynos4412 based TINY4412 board device tree source
*
@@ -5,11 +6,7 @@
*
* Device tree source file for FriendlyARM's TINY4412 board which is based on
* Samsung's Exynos4412 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
/dts-v1/;
#include "exynos4412.dtsi"
diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
index e3f7934d19d0..489b58c619ee 100644
--- a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
+++ b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device tree sources for Exynos4412 TMU sensor configuration
*
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#include <dt-bindings/thermal/thermal_exynos.h>
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index f285790e8e04..327ee980d3a5 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's Exynos4412 based Trats 2 board device tree source
*
@@ -6,30 +7,14 @@
*
* Device tree source file for Samsung's Trats 2 board which is based on
* Samsung's Exynos4412 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
/dts-v1/;
-#include "exynos4412.dtsi"
-#include "exynos4412-ppmu-common.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/clock/maxim,max77686.h>
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos4412-galaxy-s3.dtsi"
/ {
model = "Samsung Trats 2 based on Exynos4412";
- compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
-
- aliases {
- i2c9 = &i2c_ak8975;
- i2c10 = &i2c_cm36651;
- i2c11 = &i2c_max77693;
- i2c12 = &i2c_max77693_fuel;
- };
+ compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
memory@40000000 {
device_type = "memory";
@@ -38,1378 +23,5 @@
chosen {
bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
- stdout-path = &serial_2;
- };
-
- firmware@204f000 {
- compatible = "samsung,secure-firmware";
- reg = <0x0204F000 0x1000>;
- };
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti", "fixed-clock";
- clock-frequency = <0>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti", "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- cam_io_reg: voltage-regulator-1 {
- compatible = "regulator-fixed";
- regulator-name = "CAM_SENSOR_A";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- lcd_vdd3_reg: voltage-regulator-2 {
- compatible = "regulator-fixed";
- regulator-name = "LCD_VDD_2.2V";
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- cam_af_reg: voltage-regulator-3 {
- compatible = "regulator-fixed";
- regulator-name = "CAM_AF";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- ps_als_reg: voltage-regulator-5 {
- compatible = "regulator-fixed";
- regulator-name = "LED_A_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vsil12: voltage-regulator-6 {
- compatible = "regulator-fixed";
- regulator-name = "VSIL_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&buck7_reg>;
- };
-
- vcc33mhl: voltage-regulator-7 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3.3_MHL";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc18mhl: voltage-regulator-8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1.8_MHL";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-down {
- gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
- linux,code = <114>;
- label = "volume down";
- debounce-interval = <10>;
- };
-
- key-up {
- gpios = <&gpx2 2 GPIO_ACTIVE_LOW>;
- linux,code = <115>;
- label = "volume up";
- debounce-interval = <10>;
- };
-
- key-power {
- gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
- linux,code = <116>;
- label = "power";
- debounce-interval = <10>;
- wakeup-source;
- };
-
- key-ok {
- gpios = <&gpx0 1 GPIO_ACTIVE_LOW>;
- linux,code = <139>;
- label = "ok";
- debounce-inteval = <10>;
- wakeup-source;
- };
- };
-
- i2c_max77693: i2c-gpio-1 {
- compatible = "i2c-gpio";
- gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- max77693@66 {
- compatible = "maxim,max77693";
- interrupt-parent = <&gpx1>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- reg = <0x66>;
-
- regulators {
- esafeout1_reg: ESAFEOUT1 {
- regulator-name = "ESAFEOUT1";
- };
- esafeout2_reg: ESAFEOUT2 {
- regulator-name = "ESAFEOUT2";
- };
- charger_reg: CHARGER {
- regulator-name = "CHARGER";
- regulator-min-microamp = <60000>;
- regulator-max-microamp = <2580000>;
- };
- };
-
- max77693_haptic {
- compatible = "maxim,max77693-haptic";
- haptic-supply = <&ldo26_reg>;
- pwms = <&pwm 0 38022 0>;
- };
-
- charger {
- compatible = "maxim,max77693-charger";
-
- maxim,constant-microvolt = <4350000>;
- maxim,min-system-microvolt = <3600000>;
- maxim,thermal-regulation-celsius = <100>;
- maxim,battery-overcurrent-microamp = <3500000>;
- maxim,charge-input-threshold-microvolt = <4300000>;
- };
- };
- };
-
- i2c_max77693_fuel: i2c-gpio-3 {
- compatible = "i2c-gpio";
- gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- max77693-fuel-gauge@36 {
- compatible = "maxim,max17047";
- interrupt-parent = <&gpx2>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- reg = <0x36>;
-
- maxim,over-heat-temp = <700>;
- maxim,over-volt = <4500>;
- };
- };
-
- i2c_ak8975: i2c-gpio-0 {
- compatible = "i2c-gpio";
- gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- ak8975@c {
- compatible = "asahi-kasei,ak8975";
- reg = <0x0c>;
- gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>;
- };
- };
-
- i2c_cm36651: i2c-gpio-2 {
- compatible = "i2c-gpio";
- gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- cm36651@18 {
- compatible = "capella,cm36651";
- reg = <0x18>;
- interrupt-parent = <&gpx0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- vled-supply = <&ps_als_reg>;
- };
- };
-
- i2c-mhl {
- compatible = "i2c-gpio";
- gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <100>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pinctrl-0 = <&i2c_mhl_bus>;
- pinctrl-names = "default";
- status = "okay";
-
- sii9234: hdmi-bridge@39 {
- compatible = "sil,sii9234";
- avcc33-supply = <&vcc33mhl>;
- iovcc18-supply = <&vcc18mhl>;
- avcc12-supply = <&vsil12>;
- cvcc12-supply = <&vsil12>;
- reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpf3>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x39>;
-
- port {
- mhl_to_hdmi: endpoint {
- remote-endpoint = <&hdmi_to_mhl>;
- };
- };
- };
- };
-
- camera: camera {
- pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
- pinctrl-names = "default";
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_CAM0>,
- <&clock CLK_MOUT_CAM1>;
- assigned-clock-parents = <&clock CLK_XUSBXTI>,
- <&clock CLK_XUSBXTI>;
-
-
- };
-
- wlan_pwrseq: sdhci3-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>;
- clocks = <&max77686 MAX77686_CLK_PMIC>;
- clock-names = "ext_clock";
- };
-
- sound {
- compatible = "samsung,trats2-audio";
- samsung,i2s-controller = <&i2s0>;
- samsung,model = "Trats2";
- samsung,audio-codec = <&wm1811>;
- samsung,audio-routing =
- "SPK", "SPKOUTLN",
- "SPK", "SPKOUTLP",
- "SPK", "SPKOUTRN",
- "SPK", "SPKOUTRP";
- };
-
- thermistor-ap {
- compatible = "murata,ncp15wb473";
- pullup-uv = <1800000>; /* VCC_1.8V_AP */
- pullup-ohm = <100000>; /* 100K */
- pulldown-ohm = <100000>; /* 100K */
- io-channels = <&adc 1>; /* AP temperature */
- };
-
- thermistor-battery {
- compatible = "murata,ncp15wb473";
- pullup-uv = <1800000>; /* VCC_1.8V_AP */
- pullup-ohm = <100000>; /* 100K */
- pulldown-ohm = <100000>; /* 100K */
- io-channels = <&adc 2>; /* Battery temperature */
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>;
- };
- };
- };
- };
-};
-
-&adc {
- vdd-supply = <&ldo3_reg>;
- status = "okay";
-};
-
-&bus_dmc {
- devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
- vdd-supply = <&buck1_reg>;
- status = "okay";
-};
-
-&bus_acp {
- devfreq = <&bus_dmc>;
- status = "okay";
-};
-
-&bus_c2c {
- devfreq = <&bus_dmc>;
- status = "okay";
-};
-
-&bus_leftbus {
- devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
- vdd-supply = <&buck3_reg>;
- status = "okay";
-};
-
-&bus_rightbus {
- devfreq = <&bus_leftbus>;
- status = "okay";
-};
-
-&bus_display {
- devfreq = <&bus_leftbus>;
- status = "okay";
-};
-
-&bus_fsys {
- devfreq = <&bus_leftbus>;
- status = "okay";
-};
-
-&bus_peri {
- devfreq = <&bus_leftbus>;
- status = "okay";
-};
-
-&bus_mfc {
- devfreq = <&bus_leftbus>;
- status = "okay";
-};
-
-&cpu0 {
- cpu0-supply = <&buck2_reg>;
-};
-
-&csis_0 {
- status = "okay";
- vddcore-supply = <&ldo8_reg>;
- vddio-supply = <&ldo10_reg>;
- assigned-clocks = <&clock CLK_MOUT_CSIS0>,
- <&clock CLK_SCLK_CSIS0>;
- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
- assigned-clock-rates = <0>, <176000000>;
-
- /* Camera C (3) MIPI CSI-2 (CSIS0) */
- port@3 {
- reg = <3>;
- csis0_ep: endpoint {
- remote-endpoint = <&s5c73m3_ep>;
- data-lanes = <1 2 3 4>;
- samsung,csis-hs-settle = <12>;
- };
- };
-};
-
-&csis_1 {
- status = "okay";
- vddcore-supply = <&ldo8_reg>;
- vddio-supply = <&ldo10_reg>;
- assigned-clocks = <&clock CLK_MOUT_CSIS1>,
- <&clock CLK_SCLK_CSIS1>;
- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
- assigned-clock-rates = <0>, <176000000>;
-
- /* Camera D (4) MIPI CSI-2 (CSIS1) */
- port@4 {
- reg = <4>;
- csis1_ep: endpoint {
- remote-endpoint = <&is_s5k6a3_ep>;
- data-lanes = <1>;
- samsung,csis-hs-settle = <18>;
- samsung,csis-wclk;
- };
- };
-};
-
-&dsi_0 {
- vddcore-supply = <&ldo8_reg>;
- vddio-supply = <&ldo10_reg>;
- samsung,burst-clock-frequency = <500000000>;
- samsung,esc-clock-frequency = <20000000>;
- samsung,pll-clock-frequency = <24000000>;
- status = "okay";
-
- panel@0 {
- compatible = "samsung,s6e8aa0";
- reg = <0>;
- vdd3-supply = <&lcd_vdd3_reg>;
- vci-supply = <&ldo25_reg>;
- reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
- power-on-delay= <50>;
- reset-delay = <100>;
- init-delay = <100>;
- flip-horizontal;
- flip-vertical;
- panel-width-mm = <58>;
- panel-height-mm = <103>;
-
- display-timings {
- timing-0 {
- clock-frequency = <57153600>;
- hactive = <720>;
- vactive = <1280>;
- hfront-porch = <5>;
- hback-porch = <5>;
- hsync-len = <5>;
- vfront-porch = <13>;
- vback-porch = <1>;
- vsync-len = <2>;
- };
- };
- };
-};
-
-&exynos_usbphy {
- vbus-supply = <&esafeout1_reg>;
- status = "okay";
-};
-
-&fimc_0 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC0>,
- <&clock CLK_SCLK_FIMC0>;
- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
- assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_1 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC1>,
- <&clock CLK_SCLK_FIMC1>;
- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
- assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_2 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC2>,
- <&clock CLK_SCLK_FIMC2>;
- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
- assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_3 {
- status = "okay";
- assigned-clocks = <&clock CLK_MOUT_FIMC3>,
- <&clock CLK_SCLK_FIMC3>;
- assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
- assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_is {
- pinctrl-0 = <&fimc_is_uart>;
- pinctrl-names = "default";
- status = "okay";
-
- i2c1_isp: i2c-isp@12140000 {
- pinctrl-0 = <&fimc_is_i2c1>;
- pinctrl-names = "default";
-
- s5k6a3@10 {
- compatible = "samsung,s5k6a3";
- reg = <0x10>;
- svdda-supply = <&cam_io_reg>;
- svddio-supply = <&ldo19_reg>;
- afvdd-supply = <&ldo19_reg>;
- clock-frequency = <24000000>;
- /* CAM_B_CLKOUT */
- clocks = <&camera 1>;
- clock-names = "extclk";
- samsung,camclk-out = <1>;
- gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
-
- port {
- is_s5k6a3_ep: endpoint {
- remote-endpoint = <&csis1_ep>;
- data-lanes = <1>;
- };
- };
- };
- };
-};
-
-&fimc_lite_0 {
- status = "okay";
-};
-
-&fimc_lite_1 {
- status = "okay";
-};
-
-&fimd {
- status = "okay";
-};
-
-&hdmi {
- hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_hpd>;
- vdd-supply = <&ldo3_reg>;
- vdd_osc-supply = <&ldo4_reg>;
- vdd_pll-supply = <&ldo3_reg>;
- ddc = <&i2c_5>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- hdmi_to_mhl: endpoint {
- remote-endpoint = <&mhl_to_hdmi>;
- };
- };
- };
-};
-
-&hsotg {
- vusb_d-supply = <&ldo15_reg>;
- vusb_a-supply = <&ldo12_reg>;
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&i2c_0 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <400000>;
- pinctrl-0 = <&i2c0_bus>;
- pinctrl-names = "default";
- status = "okay";
-
- s5c73m3@3c {
- compatible = "samsung,s5c73m3";
- reg = <0x3c>;
- standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */
- xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */
- vdd-int-supply = <&buck9_reg>;
- vddio-cis-supply = <&ldo9_reg>;
- vdda-supply = <&ldo17_reg>;
- vddio-host-supply = <&ldo18_reg>;
- vdd-af-supply = <&cam_af_reg>;
- vdd-reg-supply = <&cam_io_reg>;
- clock-frequency = <24000000>;
- /* CAM_A_CLKOUT */
- clocks = <&camera 0>;
- clock-names = "cis_extclk";
- port {
- s5c73m3_ep: endpoint {
- remote-endpoint = <&csis0_ep>;
- data-lanes = <1 2 3 4>;
- };
- };
- };
-};
-
-&i2c_3 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <400000>;
- pinctrl-0 = <&i2c3_bus>;
- pinctrl-names = "default";
- status = "okay";
-
- mms114-touchscreen@48 {
- compatible = "melfas,mms114";
- reg = <0x48>;
- interrupt-parent = <&gpm2>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- x-size = <720>;
- y-size = <1280>;
- avdd-supply = <&ldo23_reg>;
- vdd-supply = <&ldo24_reg>;
- };
-};
-
-&i2c_4 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- pinctrl-0 = <&i2c4_bus>;
- pinctrl-names = "default";
- status = "okay";
-
- wm1811: wm1811@1a {
- compatible = "wlf,wm1811";
- reg = <0x1a>;
- clocks = <&pmu_system_controller 0>;
- clock-names = "MCLK1";
- DCVDD-supply = <&ldo3_reg>;
- DBVDD1-supply = <&ldo3_reg>;
- wlf,ldo1ena = <&gpj0 4 0>;
};
};
-
-&i2c_5 {
- status = "okay";
-};
-
-&i2c_7 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- pinctrl-0 = <&i2c7_bus>;
- pinctrl-names = "default";
- status = "okay";
-
- max77686: max77686_pmic@9 {
- compatible = "maxim,max77686";
- interrupt-parent = <&gpx0>;
- interrupts = <7 IRQ_TYPE_NONE>;
- reg = <0x09>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VALIVE_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VM1M2_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VCC_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VCC_1.8V_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VMPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VMIPI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo9_reg: LDO9 {
- regulator-name = "CAM_ISP_MIPI_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VMIPI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VABB1_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VUOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "NFC_AVDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VABB2_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VHSIC_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VHSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "CAM_SENSOR_CORE_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo18_reg: LDO18 {
- regulator-name = "CAM_ISP_SEN_IO_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo19_reg: LDO19 {
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VDDQ_PRE_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "VTF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>;
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
- };
-
- ldo23_reg: LDO23 {
- regulator-name = "TSP_AVDD_3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo24_reg: LDO24 {
- regulator-name = "TSP_VDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo25_reg: LDO25 {
- regulator-name = "LCD_VCC_3.3V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo26_reg: LDO26 {
- regulator-name = "MOTOR_VCC_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "VMEM_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "VCC_SUB_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "VCC_SUB_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "VMEM_VDDF_3.0V";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
- };
-
- buck9_reg: BUCK9 {
- regulator-name = "CAM_ISP_CORE_1.2V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1200000>;
- maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
- };
- };
- };
-};
-
-&i2c_8 {
- status = "okay";
-};
-
-&i2s0 {
- pinctrl-0 = <&i2s0_bus>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&mixer {
- status = "okay";
-};
-
-&mshc_0 {
- broken-cd;
- non-removable;
- card-detect-delay = <200>;
- vmmc-supply = <&ldo22_reg>;
- clock-frequency = <400000000>;
- samsung,dw-mshc-ciu-div = <0>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
- pinctrl-names = "default";
- status = "okay";
- bus-width = <8>;
- cap-mmc-highspeed;
-};
-
-&pmu_system_controller {
- assigned-clocks = <&pmu_system_controller 0>;
- assigned-clock-parents = <&clock CLK_XUSBXTI>;
-};
-
-&pinctrl_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&sleep0>;
-
- mhl_int: mhl-int {
- samsung,pins = "gpf3-5";
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- i2c_mhl_bus: i2c-mhl-bus {
- samsung,pins = "gpf0-4", "gpf0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
- };
-
- sleep0: sleep-states {
- PIN_SLP(gpa0-0, INPUT, NONE);
- PIN_SLP(gpa0-1, OUT0, NONE);
- PIN_SLP(gpa0-2, INPUT, NONE);
- PIN_SLP(gpa0-3, INPUT, UP);
- PIN_SLP(gpa0-4, INPUT, NONE);
- PIN_SLP(gpa0-5, INPUT, DOWN);
- PIN_SLP(gpa0-6, INPUT, DOWN);
- PIN_SLP(gpa0-7, INPUT, UP);
-
- PIN_SLP(gpa1-0, INPUT, DOWN);
- PIN_SLP(gpa1-1, INPUT, DOWN);
- PIN_SLP(gpa1-2, INPUT, DOWN);
- PIN_SLP(gpa1-3, INPUT, DOWN);
- PIN_SLP(gpa1-4, INPUT, DOWN);
- PIN_SLP(gpa1-5, INPUT, DOWN);
-
- PIN_SLP(gpb-0, INPUT, NONE);
- PIN_SLP(gpb-1, INPUT, NONE);
- PIN_SLP(gpb-2, INPUT, NONE);
- PIN_SLP(gpb-3, INPUT, NONE);
- PIN_SLP(gpb-4, INPUT, DOWN);
- PIN_SLP(gpb-5, INPUT, UP);
- PIN_SLP(gpb-6, INPUT, DOWN);
- PIN_SLP(gpb-7, INPUT, DOWN);
-
- PIN_SLP(gpc0-0, INPUT, DOWN);
- PIN_SLP(gpc0-1, INPUT, DOWN);
- PIN_SLP(gpc0-2, INPUT, DOWN);
- PIN_SLP(gpc0-3, INPUT, DOWN);
- PIN_SLP(gpc0-4, INPUT, DOWN);
-
- PIN_SLP(gpc1-0, INPUT, NONE);
- PIN_SLP(gpc1-1, PREV, NONE);
- PIN_SLP(gpc1-2, INPUT, NONE);
- PIN_SLP(gpc1-3, INPUT, NONE);
- PIN_SLP(gpc1-4, INPUT, NONE);
-
- PIN_SLP(gpd0-0, INPUT, DOWN);
- PIN_SLP(gpd0-1, INPUT, DOWN);
- PIN_SLP(gpd0-2, INPUT, NONE);
- PIN_SLP(gpd0-3, INPUT, NONE);
-
- PIN_SLP(gpd1-0, INPUT, DOWN);
- PIN_SLP(gpd1-1, INPUT, DOWN);
- PIN_SLP(gpd1-2, INPUT, NONE);
- PIN_SLP(gpd1-3, INPUT, NONE);
-
- PIN_SLP(gpf0-0, INPUT, NONE);
- PIN_SLP(gpf0-1, INPUT, NONE);
- PIN_SLP(gpf0-2, INPUT, DOWN);
- PIN_SLP(gpf0-3, INPUT, DOWN);
- PIN_SLP(gpf0-4, INPUT, NONE);
- PIN_SLP(gpf0-5, INPUT, DOWN);
- PIN_SLP(gpf0-6, INPUT, NONE);
- PIN_SLP(gpf0-7, INPUT, DOWN);
-
- PIN_SLP(gpf1-0, INPUT, DOWN);
- PIN_SLP(gpf1-1, INPUT, DOWN);
- PIN_SLP(gpf1-2, INPUT, DOWN);
- PIN_SLP(gpf1-3, INPUT, DOWN);
- PIN_SLP(gpf1-4, INPUT, NONE);
- PIN_SLP(gpf1-5, INPUT, NONE);
- PIN_SLP(gpf1-6, INPUT, DOWN);
- PIN_SLP(gpf1-7, PREV, NONE);
-
- PIN_SLP(gpf2-0, PREV, NONE);
- PIN_SLP(gpf2-1, INPUT, DOWN);
- PIN_SLP(gpf2-2, INPUT, DOWN);
- PIN_SLP(gpf2-3, INPUT, DOWN);
- PIN_SLP(gpf2-4, INPUT, DOWN);
- PIN_SLP(gpf2-5, INPUT, DOWN);
- PIN_SLP(gpf2-6, INPUT, NONE);
- PIN_SLP(gpf2-7, INPUT, NONE);
-
- PIN_SLP(gpf3-0, INPUT, NONE);
- PIN_SLP(gpf3-1, PREV, NONE);
- PIN_SLP(gpf3-2, PREV, NONE);
- PIN_SLP(gpf3-3, PREV, NONE);
- PIN_SLP(gpf3-4, OUT1, NONE);
- PIN_SLP(gpf3-5, INPUT, DOWN);
-
- PIN_SLP(gpj0-0, PREV, NONE);
- PIN_SLP(gpj0-1, PREV, NONE);
- PIN_SLP(gpj0-2, PREV, NONE);
- PIN_SLP(gpj0-3, INPUT, DOWN);
- PIN_SLP(gpj0-4, PREV, NONE);
- PIN_SLP(gpj0-5, PREV, NONE);
- PIN_SLP(gpj0-6, INPUT, DOWN);
- PIN_SLP(gpj0-7, INPUT, DOWN);
-
- PIN_SLP(gpj1-0, INPUT, DOWN);
- PIN_SLP(gpj1-1, PREV, NONE);
- PIN_SLP(gpj1-2, PREV, NONE);
- PIN_SLP(gpj1-3, INPUT, DOWN);
- PIN_SLP(gpj1-4, INPUT, DOWN);
- };
-};
-
-&pinctrl_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&sleep1>;
-
- hdmi_hpd: hdmi-hpd {
- samsung,pins = "gpx3-7";
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- sleep1: sleep-states {
- PIN_SLP(gpk0-0, PREV, NONE);
- PIN_SLP(gpk0-1, PREV, NONE);
- PIN_SLP(gpk0-2, OUT0, NONE);
- PIN_SLP(gpk0-3, PREV, NONE);
- PIN_SLP(gpk0-4, PREV, NONE);
- PIN_SLP(gpk0-5, PREV, NONE);
- PIN_SLP(gpk0-6, PREV, NONE);
-
- PIN_SLP(gpk1-0, INPUT, DOWN);
- PIN_SLP(gpk1-1, INPUT, DOWN);
- PIN_SLP(gpk1-2, INPUT, DOWN);
- PIN_SLP(gpk1-3, PREV, NONE);
- PIN_SLP(gpk1-4, PREV, NONE);
- PIN_SLP(gpk1-5, PREV, NONE);
- PIN_SLP(gpk1-6, PREV, NONE);
-
- PIN_SLP(gpk2-0, INPUT, DOWN);
- PIN_SLP(gpk2-1, INPUT, DOWN);
- PIN_SLP(gpk2-2, INPUT, DOWN);
- PIN_SLP(gpk2-3, INPUT, DOWN);
- PIN_SLP(gpk2-4, INPUT, DOWN);
- PIN_SLP(gpk2-5, INPUT, DOWN);
- PIN_SLP(gpk2-6, INPUT, DOWN);
-
- PIN_SLP(gpk3-0, OUT0, NONE);
- PIN_SLP(gpk3-1, INPUT, NONE);
- PIN_SLP(gpk3-2, INPUT, DOWN);
- PIN_SLP(gpk3-3, INPUT, NONE);
- PIN_SLP(gpk3-4, INPUT, NONE);
- PIN_SLP(gpk3-5, INPUT, NONE);
- PIN_SLP(gpk3-6, INPUT, NONE);
-
- PIN_SLP(gpl0-0, INPUT, DOWN);
- PIN_SLP(gpl0-1, INPUT, DOWN);
- PIN_SLP(gpl0-2, INPUT, DOWN);
- PIN_SLP(gpl0-3, INPUT, DOWN);
- PIN_SLP(gpl0-4, PREV, NONE);
- PIN_SLP(gpl0-6, PREV, NONE);
-
- PIN_SLP(gpl1-0, INPUT, DOWN);
- PIN_SLP(gpl1-1, INPUT, DOWN);
- PIN_SLP(gpl2-0, INPUT, DOWN);
- PIN_SLP(gpl2-1, INPUT, DOWN);
- PIN_SLP(gpl2-2, INPUT, DOWN);
- PIN_SLP(gpl2-3, INPUT, DOWN);
- PIN_SLP(gpl2-4, INPUT, DOWN);
- PIN_SLP(gpl2-5, INPUT, DOWN);
- PIN_SLP(gpl2-6, PREV, NONE);
- PIN_SLP(gpl2-7, INPUT, DOWN);
-
- PIN_SLP(gpm0-0, INPUT, DOWN);
- PIN_SLP(gpm0-1, INPUT, DOWN);
- PIN_SLP(gpm0-2, INPUT, DOWN);
- PIN_SLP(gpm0-3, INPUT, DOWN);
- PIN_SLP(gpm0-4, INPUT, DOWN);
- PIN_SLP(gpm0-5, INPUT, DOWN);
- PIN_SLP(gpm0-6, INPUT, DOWN);
- PIN_SLP(gpm0-7, INPUT, DOWN);
-
- PIN_SLP(gpm1-0, INPUT, DOWN);
- PIN_SLP(gpm1-1, INPUT, DOWN);
- PIN_SLP(gpm1-2, INPUT, NONE);
- PIN_SLP(gpm1-3, INPUT, NONE);
- PIN_SLP(gpm1-4, INPUT, NONE);
- PIN_SLP(gpm1-5, INPUT, NONE);
- PIN_SLP(gpm1-6, INPUT, DOWN);
-
- PIN_SLP(gpm2-0, INPUT, NONE);
- PIN_SLP(gpm2-1, INPUT, NONE);
- PIN_SLP(gpm2-2, INPUT, DOWN);
- PIN_SLP(gpm2-3, INPUT, DOWN);
- PIN_SLP(gpm2-4, INPUT, DOWN);
-
- PIN_SLP(gpm3-0, PREV, NONE);
- PIN_SLP(gpm3-1, PREV, NONE);
- PIN_SLP(gpm3-2, PREV, NONE);
- PIN_SLP(gpm3-3, OUT1, NONE);
- PIN_SLP(gpm3-4, INPUT, DOWN);
- PIN_SLP(gpm3-5, INPUT, DOWN);
- PIN_SLP(gpm3-6, INPUT, DOWN);
- PIN_SLP(gpm3-7, INPUT, DOWN);
-
- PIN_SLP(gpm4-0, INPUT, DOWN);
- PIN_SLP(gpm4-1, INPUT, DOWN);
- PIN_SLP(gpm4-2, INPUT, DOWN);
- PIN_SLP(gpm4-3, INPUT, DOWN);
- PIN_SLP(gpm4-4, INPUT, DOWN);
- PIN_SLP(gpm4-5, INPUT, DOWN);
- PIN_SLP(gpm4-6, INPUT, DOWN);
- PIN_SLP(gpm4-7, INPUT, DOWN);
-
- PIN_SLP(gpy0-0, INPUT, DOWN);
- PIN_SLP(gpy0-1, INPUT, DOWN);
- PIN_SLP(gpy0-2, INPUT, DOWN);
- PIN_SLP(gpy0-3, INPUT, DOWN);
- PIN_SLP(gpy0-4, INPUT, DOWN);
- PIN_SLP(gpy0-5, INPUT, DOWN);
-
- PIN_SLP(gpy1-0, INPUT, DOWN);
- PIN_SLP(gpy1-1, INPUT, DOWN);
- PIN_SLP(gpy1-2, INPUT, DOWN);
- PIN_SLP(gpy1-3, INPUT, DOWN);
-
- PIN_SLP(gpy2-0, PREV, NONE);
- PIN_SLP(gpy2-1, INPUT, DOWN);
- PIN_SLP(gpy2-2, INPUT, NONE);
- PIN_SLP(gpy2-3, INPUT, NONE);
- PIN_SLP(gpy2-4, INPUT, NONE);
- PIN_SLP(gpy2-5, INPUT, NONE);
-
- PIN_SLP(gpy3-0, INPUT, DOWN);
- PIN_SLP(gpy3-1, INPUT, DOWN);
- PIN_SLP(gpy3-2, INPUT, DOWN);
- PIN_SLP(gpy3-3, INPUT, DOWN);
- PIN_SLP(gpy3-4, INPUT, DOWN);
- PIN_SLP(gpy3-5, INPUT, DOWN);
- PIN_SLP(gpy3-6, INPUT, DOWN);
- PIN_SLP(gpy3-7, INPUT, DOWN);
-
- PIN_SLP(gpy4-0, INPUT, DOWN);
- PIN_SLP(gpy4-1, INPUT, DOWN);
- PIN_SLP(gpy4-2, INPUT, DOWN);
- PIN_SLP(gpy4-3, INPUT, DOWN);
- PIN_SLP(gpy4-4, INPUT, DOWN);
- PIN_SLP(gpy4-5, INPUT, DOWN);
- PIN_SLP(gpy4-6, INPUT, DOWN);
- PIN_SLP(gpy4-7, INPUT, DOWN);
-
- PIN_SLP(gpy5-0, INPUT, DOWN);
- PIN_SLP(gpy5-1, INPUT, DOWN);
- PIN_SLP(gpy5-2, INPUT, DOWN);
- PIN_SLP(gpy5-3, INPUT, DOWN);
- PIN_SLP(gpy5-4, INPUT, DOWN);
- PIN_SLP(gpy5-5, INPUT, DOWN);
- PIN_SLP(gpy5-6, INPUT, DOWN);
- PIN_SLP(gpy5-7, INPUT, DOWN);
-
- PIN_SLP(gpy6-0, INPUT, DOWN);
- PIN_SLP(gpy6-1, INPUT, DOWN);
- PIN_SLP(gpy6-2, INPUT, DOWN);
- PIN_SLP(gpy6-3, INPUT, DOWN);
- PIN_SLP(gpy6-4, INPUT, DOWN);
- PIN_SLP(gpy6-5, INPUT, DOWN);
- PIN_SLP(gpy6-6, INPUT, DOWN);
- PIN_SLP(gpy6-7, INPUT, DOWN);
- };
-};
-
-&pinctrl_2 {
- pinctrl-names = "default";
- pinctrl-0 = <&sleep2>;
-
- sleep2: sleep-states {
- PIN_SLP(gpz-0, INPUT, DOWN);
- PIN_SLP(gpz-1, INPUT, DOWN);
- PIN_SLP(gpz-2, INPUT, DOWN);
- PIN_SLP(gpz-3, INPUT, DOWN);
- PIN_SLP(gpz-4, INPUT, DOWN);
- PIN_SLP(gpz-5, INPUT, DOWN);
- PIN_SLP(gpz-6, INPUT, DOWN);
- };
-};
-
-&pinctrl_3 {
- pinctrl-names = "default";
- pinctrl-0 = <&sleep3>;
-
- sleep3: sleep-states {
- PIN_SLP(gpv0-0, INPUT, DOWN);
- PIN_SLP(gpv0-1, INPUT, DOWN);
- PIN_SLP(gpv0-2, INPUT, DOWN);
- PIN_SLP(gpv0-3, INPUT, DOWN);
- PIN_SLP(gpv0-4, INPUT, DOWN);
- PIN_SLP(gpv0-5, INPUT, DOWN);
- PIN_SLP(gpv0-6, INPUT, DOWN);
- PIN_SLP(gpv0-7, INPUT, DOWN);
-
- PIN_SLP(gpv1-0, INPUT, DOWN);
- PIN_SLP(gpv1-1, INPUT, DOWN);
- PIN_SLP(gpv1-2, INPUT, DOWN);
- PIN_SLP(gpv1-3, INPUT, DOWN);
- PIN_SLP(gpv1-4, INPUT, DOWN);
- PIN_SLP(gpv1-5, INPUT, DOWN);
- PIN_SLP(gpv1-6, INPUT, DOWN);
- PIN_SLP(gpv1-7, INPUT, DOWN);
-
- PIN_SLP(gpv2-0, INPUT, DOWN);
- PIN_SLP(gpv2-1, INPUT, DOWN);
- PIN_SLP(gpv2-2, INPUT, DOWN);
- PIN_SLP(gpv2-3, INPUT, DOWN);
- PIN_SLP(gpv2-4, INPUT, DOWN);
- PIN_SLP(gpv2-5, INPUT, DOWN);
- PIN_SLP(gpv2-6, INPUT, DOWN);
- PIN_SLP(gpv2-7, INPUT, DOWN);
-
- PIN_SLP(gpv3-0, INPUT, DOWN);
- PIN_SLP(gpv3-1, INPUT, DOWN);
- PIN_SLP(gpv3-2, INPUT, DOWN);
- PIN_SLP(gpv3-3, INPUT, DOWN);
- PIN_SLP(gpv3-4, INPUT, DOWN);
- PIN_SLP(gpv3-5, INPUT, DOWN);
- PIN_SLP(gpv3-6, INPUT, DOWN);
- PIN_SLP(gpv3-7, INPUT, DOWN);
-
- PIN_SLP(gpv4-0, INPUT, DOWN);
- };
-};
-
-&pwm {
- pinctrl-0 = <&pwm0_out>;
- pinctrl-names = "default";
- samsung,pwm-outputs = <0>;
- status = "okay";
-};
-
-&rtc {
- status = "okay";
- clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
- clock-names = "rtc", "rtc_src";
-};
-
-&sdhci_2 {
- bus-width = <4>;
- cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
- cd-inverted;
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
- pinctrl-names = "default";
- vmmc-supply = <&ldo21_reg>;
- status = "okay";
-};
-
-&sdhci_3 {
- #address-cells = <1>;
- #size-cells = <0>;
- non-removable;
- bus-width = <4>;
-
- mmc-pwrseq = <&wlan_pwrseq>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&gpx2>;
- interrupts = <5 IRQ_TYPE_NONE>;
- interrupt-names = "host-wake";
- };
-};
-
-&serial_0 {
- status = "okay";
-};
-
-&serial_1 {
- status = "okay";
-};
-
-&serial_2 {
- status = "okay";
-};
-
-&serial_3 {
- status = "okay";
-};
-
-&spi_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_bus>;
- cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- s5c73m3_spi: s5c73m3@0 {
- compatible = "samsung,s5c73m3";
- spi-max-frequency = <50000000>;
- reg = <0>;
- controller-data {
- samsung,spi-feedback-delay = <2>;
- };
- };
-};
-
-&tmu {
- vtmu-supply = <&ldo10_reg>;
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index e4ad2fc0329e..2ae1ab602f4b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -15,7 +15,7 @@
*/
#include "exynos4.dtsi"
-#include "exynos4412-pinctrl.dtsi"
+
#include "exynos4-cpu-thermal.dtsi"
/ {
@@ -42,8 +42,6 @@
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
- cooling-min-level = <13>;
- cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
};
@@ -147,463 +145,410 @@
};
};
- sysram@2020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x40000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x02020000 0x40000>;
- smp-sysram@0 {
- compatible = "samsung,exynos4210-sysram";
- reg = <0x0 0x1000>;
- };
+ soc: soc {
- smp-sysram@2f000 {
- compatible = "samsung,exynos4210-sysram-ns";
- reg = <0x2f000 0x1000>;
+ pinctrl_0: pinctrl@11400000 {
+ compatible = "samsung,exynos4x12-pinctrl";
+ reg = <0x11400000 0x1000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
- };
-
- pd_isp: isp-power-domain@10023ca0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10023CA0 0x20>;
- #power-domain-cells = <0>;
- label = "ISP";
- };
-
- l2c: l2-cache-controller@10502000 {
- compatible = "arm,pl310-cache";
- reg = <0x10502000 0x1000>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <2 2 1>;
- arm,data-latency = <3 2 1>;
- arm,double-linefill = <1>;
- arm,double-linefill-incr = <0>;
- arm,double-linefill-wrap = <1>;
- arm,prefetch-drop = <1>;
- arm,prefetch-offset = <7>;
- };
- clock: clock-controller@10030000 {
- compatible = "samsung,exynos4412-clock";
- reg = <0x10030000 0x18000>;
- #clock-cells = <1>;
- };
-
- isp_clock: clock-controller@10048000 {
- compatible = "samsung,exynos4412-isp-clock";
- reg = <0x10048000 0x1000>;
- #clock-cells = <1>;
- power-domains = <&pd_isp>;
- clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
- clock-names = "aclk200", "aclk400_mcuisp";
- };
+ pinctrl_1: pinctrl@11000000 {
+ compatible = "samsung,exynos4x12-pinctrl";
+ reg = <0x11000000 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- mct@10050000 {
- compatible = "samsung,exynos4412-mct";
- reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
- <1 &combiner 12 5>,
- <2 &combiner 12 6>,
- <3 &combiner 12 7>,
- <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
+ wakup_eint: wakeup-interrupt-controller {
+ compatible = "samsung,exynos4210-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
- };
-
- watchdog: watchdog@10060000 {
- compatible = "samsung,exynos5250-wdt";
- reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_WDT>;
- clock-names = "watchdog";
- samsung,syscon-phandle = <&pmu_system_controller>;
- };
-
- adc: adc@126c0000 {
- compatible = "samsung,exynos-adc-v1";
- reg = <0x126C0000 0x100>;
- interrupt-parent = <&combiner>;
- interrupts = <10 3>;
- clocks = <&clock CLK_TSADC>;
- clock-names = "adc";
- #io-channel-cells = <1>;
- io-channel-ranges;
- samsung,syscon-phandle = <&pmu_system_controller>;
- status = "disabled";
- };
-
- g2d: g2d@10800000 {
- compatible = "samsung,exynos4212-g2d";
- reg = <0x10800000 0x1000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
- clock-names = "sclk_fimg2d", "fimg2d";
- iommus = <&sysmmu_g2d>;
- };
-
- camera {
- clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
- <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
- clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
- /* fimc_[0-3] are configured outside, under phandles */
- fimc_lite_0: fimc-lite@12390000 {
- compatible = "samsung,exynos4212-fimc-lite";
- reg = <0x12390000 0x1000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_isp>;
- clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
- clock-names = "flite";
- iommus = <&sysmmu_fimc_lite0>;
- status = "disabled";
+ pinctrl_2: pinctrl@3860000 {
+ compatible = "samsung,exynos4x12-pinctrl";
+ reg = <0x03860000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <10 0>;
};
- fimc_lite_1: fimc-lite@123a0000 {
- compatible = "samsung,exynos4212-fimc-lite";
- reg = <0x123A0000 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_isp>;
- clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
- clock-names = "flite";
- iommus = <&sysmmu_fimc_lite1>;
- status = "disabled";
+ pinctrl_3: pinctrl@106e0000 {
+ compatible = "samsung,exynos4x12-pinctrl";
+ reg = <0x106E0000 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
- fimc_is: fimc-is@12000000 {
- compatible = "samsung,exynos4212-fimc-is";
- reg = <0x12000000 0x260000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_isp>;
- clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
- <&isp_clock CLK_ISP_FIMC_LITE1>,
- <&isp_clock CLK_ISP_PPMUISPX>,
- <&isp_clock CLK_ISP_PPMUISPMX>,
- <&isp_clock CLK_ISP_FIMC_ISP>,
- <&isp_clock CLK_ISP_FIMC_DRC>,
- <&isp_clock CLK_ISP_FIMC_FD>,
- <&isp_clock CLK_ISP_MCUISP>,
- <&isp_clock CLK_ISP_GICISP>,
- <&isp_clock CLK_ISP_MCUCTL_ISP>,
- <&isp_clock CLK_ISP_PWM_ISP>,
- <&isp_clock CLK_ISP_DIV_ISP0>,
- <&isp_clock CLK_ISP_DIV_ISP1>,
- <&isp_clock CLK_ISP_DIV_MCUISP0>,
- <&isp_clock CLK_ISP_DIV_MCUISP1>,
- <&clock CLK_MOUT_MPLL_USER_T>,
- <&clock CLK_ACLK200>,
- <&clock CLK_ACLK400_MCUISP>,
- <&clock CLK_DIV_ACLK200>,
- <&clock CLK_DIV_ACLK400_MCUISP>,
- <&clock CLK_UART_ISP_SCLK>;
- clock-names = "lite0", "lite1", "ppmuispx",
- "ppmuispmx", "isp",
- "drc", "fd", "mcuisp",
- "gicisp", "mcuctl_isp", "pwm_isp",
- "ispdiv0", "ispdiv1", "mcuispdiv0",
- "mcuispdiv1", "mpll", "aclk200",
- "aclk400mcuisp", "div_aclk200",
- "div_aclk400mcuisp", "uart";
- iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
- <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
- iommu-names = "isp", "drc", "fd", "mcuctl";
+ sysram@2020000 {
+ compatible = "mmio-sram";
+ reg = <0x02020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
- status = "disabled";
+ ranges = <0 0x02020000 0x40000>;
- pmu@10020000 {
- reg = <0x10020000 0x3000>;
+ smp-sysram@0 {
+ compatible = "samsung,exynos4210-sysram";
+ reg = <0x0 0x1000>;
};
- i2c1_isp: i2c-isp@12140000 {
- compatible = "samsung,exynos4212-i2c-isp";
- reg = <0x12140000 0x100>;
- clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
- clock-names = "i2c_isp";
- #address-cells = <1>;
- #size-cells = <0>;
+ smp-sysram@2f000 {
+ compatible = "samsung,exynos4210-sysram-ns";
+ reg = <0x2f000 0x1000>;
};
};
- };
-
- mshc_0: mmc@12550000 {
- compatible = "samsung,exynos4412-dw-mshc";
- reg = <0x12550000 0x1000>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- fifo-depth = <0x80>;
- clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
- clock-names = "biu", "ciu";
- status = "disabled";
- };
-
- sysmmu_g2d: sysmmu@10A40000{
- compatible = "samsung,exynos-sysmmu";
- reg = <0x10A40000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <4 7>;
- clock-names = "sysmmu", "master";
- clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
- #iommu-cells = <0>;
- };
-
- sysmmu_fimc_isp: sysmmu@12260000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12260000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <16 2>;
- power-domains = <&pd_isp>;
- clock-names = "sysmmu";
- clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
- #iommu-cells = <0>;
- };
-
- sysmmu_fimc_drc: sysmmu@12270000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12270000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <16 3>;
- power-domains = <&pd_isp>;
- clock-names = "sysmmu";
- clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
- #iommu-cells = <0>;
- };
-
- sysmmu_fimc_fd: sysmmu@122a0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x122A0000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <16 4>;
- power-domains = <&pd_isp>;
- clock-names = "sysmmu";
- clocks = <&isp_clock CLK_ISP_SMMU_FD>;
- #iommu-cells = <0>;
- };
-
- sysmmu_fimc_mcuctl: sysmmu@122b0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x122B0000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <16 5>;
- power-domains = <&pd_isp>;
- clock-names = "sysmmu";
- clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
- #iommu-cells = <0>;
- };
- sysmmu_fimc_lite0: sysmmu@123b0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x123B0000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <16 0>;
- power-domains = <&pd_isp>;
- clock-names = "sysmmu", "master";
- clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
- <&isp_clock CLK_ISP_FIMC_LITE0>;
- #iommu-cells = <0>;
- };
+ pd_isp: isp-power-domain@10023ca0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023CA0 0x20>;
+ #power-domain-cells = <0>;
+ label = "ISP";
+ };
- sysmmu_fimc_lite1: sysmmu@123c0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x123C0000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <16 1>;
- power-domains = <&pd_isp>;
- clock-names = "sysmmu", "master";
- clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
- <&isp_clock CLK_ISP_FIMC_LITE1>;
- #iommu-cells = <0>;
- };
+ l2c: l2-cache-controller@10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <2 2 1>;
+ arm,data-latency = <3 2 1>;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <1>;
+ arm,prefetch-offset = <7>;
+ };
- bus_dmc: bus_dmc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_DMC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- status = "disabled";
- };
+ clock: clock-controller@10030000 {
+ compatible = "samsung,exynos4412-clock";
+ reg = <0x10030000 0x18000>;
+ #clock-cells = <1>;
+ };
- bus_acp: bus_acp {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_ACP>;
- clock-names = "bus";
- operating-points-v2 = <&bus_acp_opp_table>;
- status = "disabled";
- };
+ isp_clock: clock-controller@10048000 {
+ compatible = "samsung,exynos4412-isp-clock";
+ reg = <0x10048000 0x1000>;
+ #clock-cells = <1>;
+ power-domains = <&pd_isp>;
+ clocks = <&clock CLK_ACLK200>,
+ <&clock CLK_ACLK400_MCUISP>;
+ clock-names = "aclk200", "aclk400_mcuisp";
+ };
+
+ mct@10050000 {
+ compatible = "samsung,exynos4412-mct";
+ reg = <0x10050000 0x800>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0>, <1>, <2>, <3>, <4>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map =
+ <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+ <1 &combiner 12 5>,
+ <2 &combiner 12 6>,
+ <3 &combiner 12 7>,
+ <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
- bus_c2c: bus_c2c {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_C2C>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- status = "disabled";
- };
+ watchdog: watchdog@10060000 {
+ compatible = "samsung,exynos5250-wdt";
+ reg = <0x10060000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_WDT>;
+ clock-names = "watchdog";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ };
+
+ adc: adc@126c0000 {
+ compatible = "samsung,exynos-adc-v1";
+ reg = <0x126C0000 0x100>;
+ interrupt-parent = <&combiner>;
+ interrupts = <10 3>;
+ clocks = <&clock CLK_TSADC>;
+ clock-names = "adc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ status = "disabled";
+ };
- bus_dmc_opp_table: opp_table1 {
- compatible = "operating-points-v2";
- opp-shared;
+ g2d: g2d@10800000 {
+ compatible = "samsung,exynos4212-g2d";
+ reg = <0x10800000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
+ clock-names = "sclk_fimg2d", "fimg2d";
+ iommus = <&sysmmu_g2d>;
+ };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <900000>;
+ mshc_0: mmc@12550000 {
+ compatible = "samsung,exynos4412-dw-mshc";
+ reg = <0x12550000 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fifo-depth = <0x80>;
+ clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
};
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <900000>;
+
+ sysmmu_g2d: sysmmu@10A40000{
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x10A40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 7>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+ #iommu-cells = <0>;
};
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- opp-microvolt = <900000>;
+
+ sysmmu_fimc_isp: sysmmu@12260000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12260000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 2>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
+ #iommu-cells = <0>;
};
- opp-267000000 {
- opp-hz = /bits/ 64 <267000000>;
- opp-microvolt = <950000>;
+
+ sysmmu_fimc_drc: sysmmu@12270000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12270000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 3>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
+ #iommu-cells = <0>;
};
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1050000>;
+
+ sysmmu_fimc_fd: sysmmu@122a0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x122A0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 4>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&isp_clock CLK_ISP_SMMU_FD>;
+ #iommu-cells = <0>;
};
- };
- bus_acp_opp_table: opp_table2 {
- compatible = "operating-points-v2";
- opp-shared;
+ sysmmu_fimc_mcuctl: sysmmu@122b0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x122B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 5>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
+ #iommu-cells = <0>;
+ };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
+ sysmmu_fimc_lite0: sysmmu@123b0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x123B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu", "master";
+ clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
+ <&isp_clock CLK_ISP_FIMC_LITE0>;
+ #iommu-cells = <0>;
};
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
+
+ sysmmu_fimc_lite1: sysmmu@123c0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x123C0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 1>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu", "master";
+ clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
+ <&isp_clock CLK_ISP_FIMC_LITE1>;
+ #iommu-cells = <0>;
};
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
};
- opp-267000000 {
- opp-hz = /bits/ 64 <267000000>;
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_acp_opp_table>;
+ status = "disabled";
};
- };
- bus_leftbus: bus_leftbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDL>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
+ bus_c2c: bus_c2c {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_C2C>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
- bus_rightbus: bus_rightbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDR>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
- bus_display: bus_display {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK160>;
- clock-names = "bus";
- operating-points-v2 = <&bus_display_opp_table>;
- status = "disabled";
- };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
- bus_fsys: bus_fsys {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK133>;
- clock-names = "bus";
- operating-points-v2 = <&bus_fsys_opp_table>;
- status = "disabled";
- };
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
- bus_peri: bus_peri {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK100>;
- clock-names = "bus";
- operating-points-v2 = <&bus_peri_opp_table>;
- status = "disabled";
- };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ };
+ };
- bus_mfc: bus_mfc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_SCLK_MFC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
- bus_leftbus_opp_table: opp_table3 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <900000>;
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_display_opp_table>;
+ status = "disabled";
};
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <925000>;
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_fsys_opp_table>;
+ status = "disabled";
};
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- opp-microvolt = <950000>;
+
+ bus_peri: bus_peri {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_peri_opp_table>;
+ status = "disabled";
};
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <1000000>;
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
};
- };
- bus_display_opp_table: opp_table4 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_leftbus_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <925000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1000000>;
+ };
};
- };
- bus_fsys_opp_table: opp_table5 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_display_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
};
- };
- bus_peri_opp_table: opp_table6 {
- compatible = "operating-points-v2";
- opp-shared;
+ bus_fsys_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
};
- };
- pmu {
- interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
+ bus_peri_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ };
};
};
@@ -631,6 +576,92 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
+&camera {
+ clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
+ <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
+ clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+
+ /* fimc_[0-3] are configured outside, under phandles */
+ fimc_lite_0: fimc-lite@12390000 {
+ compatible = "samsung,exynos4212-fimc-lite";
+ reg = <0x12390000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_isp>;
+ clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
+ clock-names = "flite";
+ iommus = <&sysmmu_fimc_lite0>;
+ status = "disabled";
+ };
+
+ fimc_lite_1: fimc-lite@123a0000 {
+ compatible = "samsung,exynos4212-fimc-lite";
+ reg = <0x123A0000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_isp>;
+ clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
+ clock-names = "flite";
+ iommus = <&sysmmu_fimc_lite1>;
+ status = "disabled";
+ };
+
+ fimc_is: fimc-is@12000000 {
+ compatible = "samsung,exynos4212-fimc-is";
+ reg = <0x12000000 0x260000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_isp>;
+ clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
+ <&isp_clock CLK_ISP_FIMC_LITE1>,
+ <&isp_clock CLK_ISP_PPMUISPX>,
+ <&isp_clock CLK_ISP_PPMUISPMX>,
+ <&isp_clock CLK_ISP_FIMC_ISP>,
+ <&isp_clock CLK_ISP_FIMC_DRC>,
+ <&isp_clock CLK_ISP_FIMC_FD>,
+ <&isp_clock CLK_ISP_MCUISP>,
+ <&isp_clock CLK_ISP_GICISP>,
+ <&isp_clock CLK_ISP_MCUCTL_ISP>,
+ <&isp_clock CLK_ISP_PWM_ISP>,
+ <&isp_clock CLK_ISP_DIV_ISP0>,
+ <&isp_clock CLK_ISP_DIV_ISP1>,
+ <&isp_clock CLK_ISP_DIV_MCUISP0>,
+ <&isp_clock CLK_ISP_DIV_MCUISP1>,
+ <&clock CLK_MOUT_MPLL_USER_T>,
+ <&clock CLK_ACLK200>,
+ <&clock CLK_ACLK400_MCUISP>,
+ <&clock CLK_DIV_ACLK200>,
+ <&clock CLK_DIV_ACLK400_MCUISP>,
+ <&clock CLK_UART_ISP_SCLK>;
+ clock-names = "lite0", "lite1", "ppmuispx",
+ "ppmuispmx", "isp",
+ "drc", "fd", "mcuisp",
+ "gicisp", "mcuctl_isp", "pwm_isp",
+ "ispdiv0", "ispdiv1", "mcuispdiv0",
+ "mcuispdiv1", "mpll", "aclk200",
+ "aclk400mcuisp", "div_aclk200",
+ "div_aclk400mcuisp", "uart";
+ iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
+ <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
+ iommu-names = "isp", "drc", "fd", "mcuctl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pmu@10020000 {
+ reg = <0x10020000 0x3000>;
+ };
+
+ i2c1_isp: i2c-isp@12140000 {
+ compatible = "samsung,exynos4212-i2c-isp";
+ reg = <0x12140000 0x100>;
+ clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
+ clock-names = "i2c_isp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
&exynos_usbphy {
compatible = "samsung,exynos4x12-usb2-phy";
samsung,sysreg-phandle = <&sys_reg>;
@@ -693,35 +724,8 @@
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
};
-&pinctrl_0 {
- compatible = "samsung,exynos4x12-pinctrl";
- reg = <0x11400000 0x1000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&pinctrl_1 {
- compatible = "samsung,exynos4x12-pinctrl";
- reg = <0x11000000 0x1000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-
- wakup_eint: wakeup-interrupt-controller {
- compatible = "samsung,exynos4210-wakeup-eint";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
-
-&pinctrl_2 {
- compatible = "samsung,exynos4x12-pinctrl";
- reg = <0x03860000 0x1000>;
- interrupt-parent = <&combiner>;
- interrupts = <10 0>;
-};
-
-&pinctrl_3 {
- compatible = "samsung,exynos4x12-pinctrl";
- reg = <0x106E0000 0x1000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+&pmu {
+ interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
};
&pmu_system_controller {
@@ -743,3 +747,5 @@
clock-names = "tmu_apbif";
status = "disabled";
};
+
+#include "exynos4412-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 59cf1b202849..fd9226d3b207 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/maxim,max77686.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5250.dtsi"
/ {
@@ -225,6 +226,16 @@
};
};
+&clock {
+ assigned-clocks = <&clock CLK_FOUT_EPLL>;
+ assigned-clock-rates = <49152000>;
+};
+
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -513,6 +524,8 @@
};
&i2s0 {
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
@@ -649,6 +662,11 @@
};
};
+&pmu_system_controller {
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_FIN_PLL>;
+};
+
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 4827cb506fa3..75fdc5e6d423 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -18,6 +18,14 @@
samsung,model = "Snow-I2S-MAX98095";
samsung,audio-codec = <&max98095>;
+
+ cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ codec {
+ sound-dai = <&max98095 0>, <&hdmi>;
+ };
};
};
@@ -27,6 +35,9 @@
reg = <0x11>;
pinctrl-names = "default";
pinctrl-0 = <&max98095_en>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "mclk";
+ #sound-dai-cells = <1>;
};
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 56626d1a4235..45283a6c5eee 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -77,8 +77,6 @@
300000 937500
200000 925000
>;
- cooling-min-level = <15>;
- cooling-max-level = <9>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
@@ -500,6 +498,8 @@
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
power-domains = <&pd_mau>;
+ #clock-cells = <1>;
+ #sound-dai-cells = <1>;
};
i2s1: i2s@12d60000 {
@@ -514,6 +514,7 @@
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
power-domains = <&pd_mau>;
+ #sound-dai-cells = <1>;
};
i2s2: i2s@12d70000 {
@@ -528,6 +529,7 @@
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
power-domains = <&pd_mau>;
+ #sound-dai-cells = <1>;
};
usb_dwc3 {
@@ -655,7 +657,7 @@
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
- iommu = <&sysmmu_gsc0>;
+ iommus = <&sysmmu_gsc0>;
};
gsc_1: gsc@13e10000 {
@@ -665,7 +667,7 @@
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
- iommu = <&sysmmu_gsc1>;
+ iommus = <&sysmmu_gsc1>;
};
gsc_2: gsc@13e20000 {
@@ -675,7 +677,7 @@
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL2>;
clock-names = "gscl";
- iommu = <&sysmmu_gsc2>;
+ iommus = <&sysmmu_gsc2>;
};
gsc_3: gsc@13e30000 {
@@ -685,7 +687,7 @@
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL3>;
clock-names = "gscl";
- iommu = <&sysmmu_gsc3>;
+ iommus = <&sysmmu_gsc3>;
};
hdmi: hdmi@14530000 {
@@ -700,6 +702,7 @@
"sclk_hdmiphy", "mout_hdmi";
samsung,syscon-phandle = <&pmu_system_controller>;
phy = <&hdmiphy>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 442eb0353f29..fa19c59b2fb6 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -65,7 +65,6 @@
&mmc_0 {
status = "okay";
broken-cd;
- bypass-smu;
cap-mmc-highspeed;
supports-hs200-mode; /* 200 MHz */
card-detect-delay = <200>;
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 1886aa00b2db..55509c690328 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -11,7 +11,6 @@
*/
#include "exynos54xx.dtsi"
-#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos5410.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -197,9 +196,9 @@
interrupt-parent = <&gic>;
ranges;
- pdma0: pdma@12680000 {
+ pdma0: pdma@121a0000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x121A0000 0x1000>;
+ reg = <0x121a0000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
@@ -208,9 +207,9 @@
#dma-requests = <32>;
};
- pdma1: pdma@12690000 {
+ pdma1: pdma@121b0000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x121B0000 0x1000>;
+ reg = <0x121b0000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 123f0cef658d..a8e449471304 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -30,8 +30,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -43,8 +41,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -56,8 +52,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -69,8 +63,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -83,8 +75,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -96,8 +86,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -109,8 +97,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -122,8 +108,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 5a76ed77dda1..244f0091c21f 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/regulator/maxim,max77802.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
@@ -86,6 +87,14 @@
samsung,model = "Peach-Pit-I2S-MAX98090";
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&max98090>;
+
+ cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ codec {
+ sound-dai = <&max98090>, <&hdmi>;
+ };
};
usb300_vbus_reg: regulator-usb300 {
@@ -142,6 +151,11 @@
vdd-supply = <&ldo9_reg>;
};
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
&cpu0 {
cpu-supply = <&buck2_reg>;
};
@@ -606,6 +620,7 @@
pinctrl-0 = <&max98090_irq>;
clocks = <&pmu_system_controller 0>;
clock-names = "mclk";
+ #sound-dai-cells = <0>;
};
light-sensor@44 {
@@ -690,6 +705,8 @@
};
&i2s0 {
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index c593809c7f08..7c130a00d1a8 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -29,8 +29,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -42,8 +40,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -55,8 +51,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -68,8 +62,6 @@
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
};
@@ -82,8 +74,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -95,8 +85,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -108,8 +96,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
@@ -121,8 +107,6 @@
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
- cooling-min-level = <0>;
- cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index fce9e26b5930..f3abecc44657 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -26,24 +26,6 @@
tmuctrl2 = &tmuctrl_2;
};
- clock: clock-controller@160000 {
- compatible = "samsung,exynos5440-clock";
- reg = <0x160000 0x1000>;
- #clock-cells = <1>;
- };
-
- gic: interrupt-controller@2e0000 {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x2E1000 0x1000>,
- <0x2E2000 0x2000>,
- <0x2E4000 0x2000>,
- <0x2E6000 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -70,182 +52,290 @@
};
};
- arm-pmu {
- compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- };
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- timer {
- compatible = "arm,cortex-a15-timer",
- "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <50000000>;
- };
+ clock: clock-controller@160000 {
+ compatible = "samsung,exynos5440-clock";
+ reg = <0x160000 0x1000>;
+ #clock-cells = <1>;
+ };
- cpufreq@160000 {
- compatible = "samsung,exynos5440-cpufreq";
- reg = <0x160000 0x1000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- operating-points = <
- /* KHz uV */
- 1500000 1100000
- 1400000 1075000
- 1300000 1050000
- 1200000 1025000
- 1100000 1000000
- 1000000 975000
- 900000 950000
- 800000 925000
- >;
- };
+ gic: interrupt-controller@2e0000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x2E1000 0x1000>,
+ <0x2E2000 0x2000>,
+ <0x2E4000 0x2000>,
+ <0x2E6000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
- serial_0: serial@b0000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0xB0000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
- clock-names = "uart", "clk_uart_baud0";
- };
- serial_1: serial@c0000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0xC0000 0x1000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
- clock-names = "uart", "clk_uart_baud0";
- };
+ arm-pmu {
+ compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ };
- spi_0: spi@d0000 {
- compatible = "samsung,exynos5440-spi";
- reg = <0xD0000 0x100>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- samsung,spi-src-clk = <0>;
- num-cs = <1>;
- clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
- clock-names = "spi", "spi_busclk0";
- };
+ timer {
+ compatible = "arm,cortex-a15-timer",
+ "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <50000000>;
+ };
- pin_ctrl: pinctrl@e0000 {
- compatible = "samsung,exynos5440-pinctrl";
- reg = <0xE0000 0x1000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- #gpio-cells = <2>;
+ cpufreq@160000 {
+ compatible = "samsung,exynos5440-cpufreq";
+ reg = <0x160000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points = <
+ /* KHz uV */
+ 1500000 1100000
+ 1400000 1075000
+ 1300000 1050000
+ 1200000 1025000
+ 1100000 1000000
+ 1000000 975000
+ 900000 950000
+ 800000 925000
+ >;
+ };
- fan: fan {
- samsung,exynos5440-pin-function = <1>;
+ serial_0: serial@b0000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0xB0000 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
+ clock-names = "uart", "clk_uart_baud0";
};
- hdd_led0: hdd_led0 {
- samsung,exynos5440-pin-function = <2>;
+ serial_1: serial@c0000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0xC0000 0x1000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
+ clock-names = "uart", "clk_uart_baud0";
};
- hdd_led1: hdd_led1 {
- samsung,exynos5440-pin-function = <3>;
+ spi_0: spi@d0000 {
+ compatible = "samsung,exynos5440-spi";
+ reg = <0xD0000 0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,spi-src-clk = <0>;
+ num-cs = <1>;
+ clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
+ clock-names = "spi", "spi_busclk0";
};
- uart1: uart1 {
- samsung,exynos5440-pin-function = <4>;
+ pin_ctrl: pinctrl@e0000 {
+ compatible = "samsung,exynos5440-pinctrl";
+ reg = <0xE0000 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+
+ fan: fan {
+ samsung,exynos5440-pin-function = <1>;
+ };
+
+ hdd_led0: hdd_led0 {
+ samsung,exynos5440-pin-function = <2>;
+ };
+
+ hdd_led1: hdd_led1 {
+ samsung,exynos5440-pin-function = <3>;
+ };
+
+ uart1: uart1 {
+ samsung,exynos5440-pin-function = <4>;
+ };
};
- };
- i2c@f0000 {
- compatible = "samsung,exynos5440-i2c";
- reg = <0xF0000 0x1000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock CLK_B_125>;
- clock-names = "i2c";
- };
+ i2c@f0000 {
+ compatible = "samsung,exynos5440-i2c";
+ reg = <0xF0000 0x1000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "i2c";
+ };
- i2c@100000 {
- compatible = "samsung,exynos5440-i2c";
- reg = <0x100000 0x1000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock CLK_B_125>;
- clock-names = "i2c";
- };
+ i2c@100000 {
+ compatible = "samsung,exynos5440-i2c";
+ reg = <0x100000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "i2c";
+ };
- watchdog@110000 {
- compatible = "samsung,s3c6410-wdt";
- reg = <0x110000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>;
- clock-names = "watchdog";
- };
+ watchdog@110000 {
+ compatible = "samsung,s3c6410-wdt";
+ reg = <0x110000 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "watchdog";
+ };
- gmac: ethernet@230000 {
- compatible = "snps,dwmac-3.70a", "snps,dwmac";
- reg = <0x00230000 0x8000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- phy-mode = "sgmii";
- clocks = <&clock CLK_GMAC0>;
- clock-names = "stmmaceth";
- };
+ gmac: ethernet@230000 {
+ compatible = "snps,dwmac-3.70a", "snps,dwmac";
+ reg = <0x00230000 0x8000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ phy-mode = "sgmii";
+ clocks = <&clock CLK_GMAC0>;
+ clock-names = "stmmaceth";
+ };
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
- };
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+ };
- rtc@130000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x130000 0x1000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>;
- clock-names = "rtc";
- };
+ rtc@130000 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x130000 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "rtc";
+ };
- tmuctrl_0: tmuctrl@160118 {
- compatible = "samsung,exynos5440-tmu";
- reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>;
- clock-names = "tmu_apbif";
- #include "exynos5440-tmu-sensor-conf.dtsi"
- };
+ tmuctrl_0: tmuctrl@160118 {
+ compatible = "samsung,exynos5440-tmu";
+ reg = <0x160118 0x230>, <0x160368 0x10>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "tmu_apbif";
+ #include "exynos5440-tmu-sensor-conf.dtsi"
+ };
- tmuctrl_1: tmuctrl@16011c {
- compatible = "samsung,exynos5440-tmu";
- reg = <0x16011C 0x230>, <0x160368 0x10>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>;
- clock-names = "tmu_apbif";
- #include "exynos5440-tmu-sensor-conf.dtsi"
- };
+ tmuctrl_1: tmuctrl@16011c {
+ compatible = "samsung,exynos5440-tmu";
+ reg = <0x16011C 0x230>, <0x160368 0x10>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "tmu_apbif";
+ #include "exynos5440-tmu-sensor-conf.dtsi"
+ };
+
+ tmuctrl_2: tmuctrl@160120 {
+ compatible = "samsung,exynos5440-tmu";
+ reg = <0x160120 0x230>, <0x160368 0x10>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_B_125>;
+ clock-names = "tmu_apbif";
+ #include "exynos5440-tmu-sensor-conf.dtsi"
+ };
- tmuctrl_2: tmuctrl@160120 {
- compatible = "samsung,exynos5440-tmu";
- reg = <0x160120 0x230>, <0x160368 0x10>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_B_125>;
- clock-names = "tmu_apbif";
- #include "exynos5440-tmu-sensor-conf.dtsi"
+ sata@210000 {
+ compatible = "snps,exynos5440-ahci";
+ reg = <0x210000 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_SATA>;
+ clock-names = "sata";
+ };
+
+ ohci@220000 {
+ compatible = "samsung,exynos5440-ohci";
+ reg = <0x220000 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USB>;
+ clock-names = "usbhost";
+ };
+
+ ehci@221000 {
+ compatible = "samsung,exynos5440-ehci";
+ reg = <0x221000 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_USB>;
+ clock-names = "usbhost";
+ };
+
+ pcie_phy0: pcie-phy@270000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x270000 0x1000>, <0x271000 0x40>;
+ };
+
+ pcie_phy1: pcie-phy@272000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x272000 0x1000>, <0x271040 0x40>;
+ };
+
+ pcie_0: pcie@290000 {
+ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+ reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+ reg-names = "elbi", "config";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
+ clock-names = "pcie", "pcie_bus";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy0>;
+ ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 53>;
+ num-lanes = <4>;
+ status = "disabled";
+ };
+
+ pcie_1: pcie@2a0000 {
+ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+ reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
+ reg-names = "elbi", "config";
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
+ clock-names = "pcie", "pcie_bus";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy1>;
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 56>;
+ num-lanes = <4>;
+ status = "disabled";
+ };
};
thermal-zones {
@@ -262,86 +352,4 @@
#include "exynos5440-trip-points.dtsi"
};
};
-
- sata@210000 {
- compatible = "snps,exynos5440-ahci";
- reg = <0x210000 0x10000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_SATA>;
- clock-names = "sata";
- };
-
- ohci@220000 {
- compatible = "samsung,exynos5440-ohci";
- reg = <0x220000 0x1000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_USB>;
- clock-names = "usbhost";
- };
-
- ehci@221000 {
- compatible = "samsung,exynos5440-ehci";
- reg = <0x221000 0x1000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_USB>;
- clock-names = "usbhost";
- };
-
- pcie_phy0: pcie-phy@270000 {
- #phy-cells = <0>;
- compatible = "samsung,exynos5440-pcie-phy";
- reg = <0x270000 0x1000>, <0x271000 0x40>;
- };
-
- pcie_phy1: pcie-phy@272000 {
- #phy-cells = <0>;
- compatible = "samsung,exynos5440-pcie-phy";
- reg = <0x272000 0x1000>, <0x271040 0x40>;
- };
-
- pcie_0: pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000>, <0x40000000 0x1000>;
- reg-names = "elbi", "config";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- phys = <&pcie_phy0>;
- ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
- bus-range = <0x00 0xff>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 53>;
- num-lanes = <4>;
- status = "disabled";
- };
-
- pcie_1: pcie@2a0000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
- reg-names = "elbi", "config";
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- phys = <&pcie_phy1>;
- ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
- bus-range = <0x00 0xff>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0x0 0 &gic 56>;
- num-lanes = <4>;
- status = "disabled";
- };
};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 0029ec27819c..2f8df9244f72 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Google Peach Pi Rev 10+ board device tree source
*
* Copyright (c) 2014 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/dts-v1/;
@@ -14,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/regulator/maxim,max77802.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5800.dtsi"
#include "exynos5420-cpus.dtsi"
@@ -89,6 +87,14 @@
samsung,model = "Peach-Pi-I2S-MAX98091";
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&max98091>;
+
+ cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ codec {
+ sound-dai = <&max98091>, <&hdmi>;
+ };
};
usb300_vbus_reg: regulator-usb300 {
@@ -145,6 +151,11 @@
vdd-supply = <&ldo9_reg>;
};
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
&cpu0 {
cpu-supply = <&buck2_reg>;
};
@@ -609,6 +620,7 @@
pinctrl-0 = <&max98091_irq>;
clocks = <&pmu_system_controller 0>;
clock-names = "mclk";
+ #sound-dai-cells = <0>;
};
light-sensor@44 {
@@ -661,6 +673,8 @@
};
&i2s0 {
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 9ddb6bacac5a..57d3b319fd65 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5800 SoC device tree source
*
@@ -7,10 +8,6 @@
* SAMSUNG EXYNOS5800 SoC device nodes are listed in this file.
* EXYNOS5800 based board files can include this file and provide
* values for board specfic bindings.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include "exynos5420.dtsi"
diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
index da8bb9d60f99..403364a7aab9 100644
--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
@@ -78,8 +78,6 @@
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
<&gpio0 12 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>;
- cooling-min-level = <0>;
- cooling-max-level = <2>;
#cooling-cells = <2>;
};
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
index 5ea28ee07cf4..6354e4c87313 100644
--- a/arch/arm/boot/dts/imx1-ads.dts
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -20,7 +20,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@8000000 {
reg = <0x08000000 0x04000000>;
};
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
index e8b4b52c2418..11515c0cb195 100644
--- a/arch/arm/boot/dts/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -20,7 +20,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@8000000 {
reg = <0x08000000 0x00800000>;
};
};
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 20f6565c337d..f7b9edf93f5e 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -25,7 +25,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 57e29977ba06..9d92ece82560 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -16,7 +16,7 @@
model = "Freescale i.MX23 Evaluation Kit";
compatible = "fsl,imx23-evk", "fsl,imx23";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index a8b1c53ebe46..e9351774c619 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -19,7 +19,7 @@
model = "i.MX23 Olinuxino Low Cost Board";
compatible = "olimex,imx23-olinuxino", "fsl,imx23";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x04000000>;
};
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
index 221fd55e967e..67de7863ad79 100644
--- a/arch/arm/boot/dts/imx23-sansa.dts
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -49,7 +49,7 @@
model = "SanDisk Sansa Fuze+";
compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x04000000>;
};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 455169e99d49..95c7b918f6d6 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -16,7 +16,7 @@
model = "Freescale STMP378x Development Board";
compatible = "fsl,stmp378x-devb", "fsl,imx23";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x04000000>;
};
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index 025cf949662d..9616e500b996 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -48,7 +48,7 @@
model = "Creative ZEN X-Fi3";
compatible = "creative,x-fi3", "fsl,imx23";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x04000000>;
};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 10d57f9cbb42..cb0a3fe32718 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,7 +23,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
gpio0 = &gpio0;
@@ -222,7 +222,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_pins_fixup: gpmi-pins-fixup {
+ gpmi_pins_fixup: gpmi-pins-fixup@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
@@ -266,7 +267,8 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_pins_fixup: mmc0-pins-fixup {
+ mmc0_pins_fixup: mmc0-pins-fixup@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
index d6f27641c0ef..e316fe08837a 100644
--- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -17,7 +17,7 @@
model = "Eukrea CPUIMX25";
compatible = "eukrea,cpuimx25", "fsl,imx25";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x4000000>; /* 64M */
};
};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 0f053721d80f..6273a1f243ed 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -88,12 +88,12 @@
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
- MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0
- MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0
- MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0
- MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0
- MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0
- MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0
+ MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0
+ MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0
+ MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0
+ MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0
+ MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0
+ MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0
>;
};
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index 30a62d4be8d9..5cb6967866c0 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -36,7 +36,7 @@
};
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
};
};
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 2d15ce72d006..7f9bd052b84e 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -18,7 +18,7 @@
model = "Freescale i.MX25 Product Development Kit";
compatible = "fsl,imx25-pdk", "fsl,imx25";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x4000000>;
};
@@ -165,12 +165,12 @@
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
- MX25_PAD_SD1_CMD__SD1_CMD 0x80000000
- MX25_PAD_SD1_CLK__SD1_CLK 0x80000000
- MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000
- MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000
- MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000
- MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000
+ MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
+ MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
+ MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
+ MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
+ MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
+ MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX25_PAD_A14__GPIO_2_0 0x80000000
MX25_PAD_A15__GPIO_2_1 0x80000000
>;
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 6c63dca1b9b8..a4807062a90f 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -151,21 +151,21 @@
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
-#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
+#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
-#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
+#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
-#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
+#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
-#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
+#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
@@ -236,12 +236,13 @@
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000
#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000
-#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000
#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001
-#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
+#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000
#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000
@@ -250,7 +251,7 @@
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000
#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001
-#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
+#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
@@ -316,12 +317,13 @@
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000
-#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000
-#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x02 0x001
+#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000
@@ -336,22 +338,22 @@
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000
-#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001
+#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000
-#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001
+#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000
-#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001
+#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000
-#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001
+#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000
@@ -419,37 +421,37 @@
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000
/*
- * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
+ * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
* card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
* Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
- * bug that configuring the SD1_CMD function doesn't enable the input path for
- * this pin.
+ * bug that configuring the ESDHCn_CMD function doesn't enable the input path
+ * for this pin.
* This might have side effects for other hardware units that are connected to
* that pin and use the respective function as input.
*/
-#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000
-#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x00 0x000
+#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000
#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000
-#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000
-#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000
-#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000
-#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000
@@ -496,6 +498,8 @@
#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000
#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002
#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001
#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000
@@ -601,4 +605,28 @@
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
+/*
+ * Compatibility defines for out-of-tree users. You should update if you make
+ * use of one of them.
+ */
+#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7
+#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6
+#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5
+#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4
+#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD
+#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK
+#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1
+#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3
+#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD
+#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK
+#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0
+#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1
+#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2
+#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3
+
#endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 9445f8e1473c..cf70df20b19c 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -22,7 +22,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
@@ -269,6 +269,7 @@
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
status = "disabled";
};
@@ -329,6 +330,7 @@
dmas = <&sdma 28 1 0>,
<&sdma 29 1 0>;
dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index 73aae4f5e539..66941cdbf244 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -19,7 +19,7 @@
model = "Armadeus Systems APF27 module";
compatible = "armadeus,imx27-apf27", "fsl,imx27";
- memory {
+ memory@a0000000 {
reg = <0xa0000000 0x04000000>;
};
diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
index 2cf896c505f9..9c455dcbe6eb 100644
--- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
@@ -16,21 +16,14 @@
model = "Eukrea CPUIMX27";
compatible = "eukrea,cpuimx27", "fsl,imx27";
- memory {
+ memory@a0000000 {
reg = <0xa0000000 0x04000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "simple-bus";
-
- clk14745600: clock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <14745600>;
- reg = <0>;
- };
+ clk14745600: clk-uart {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <14745600>;
};
};
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
index f56535768ee8..15145e7f9778 100644
--- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -84,7 +84,7 @@
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
- ads7846 {
+ ads7846@0 {
compatible = "ti,ads7846";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 2a140c8ae6d2..924b90c9985d 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -16,7 +16,7 @@
model = "Freescale i.MX27 Product Development Kit";
compatible = "fsl,imx27-pdk", "fsl,imx27";
- memory {
+ memory@a0000000 {
reg = <0xa0000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
index 0b8490b21a38..cbad7c88c58c 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -17,7 +17,7 @@
model = "Phytec pca100";
compatible = "phytec,imx27-pca100", "fsl,imx27";
- memory {
+ memory@a0000000 {
reg = <0xa0000000 0x08000000>; /* 128MB */
};
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index c9095b7654c6..ec466b4bfd41 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -16,7 +16,7 @@
model = "Phytec pcm038";
compatible = "phytec,imx27-pcm038", "fsl,imx27";
- memory {
+ memory@a0000000 {
reg = <0xa0000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 15d85f1f85fd..6585b00c3917 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -26,7 +26,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 070e59cbdd8b..bab78346fa9f 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -16,7 +16,7 @@
model = "Armadeus Systems APF28 module";
compatible = "armadeus,imx28-apf28", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index ae078341fb60..96faa53ba44c 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -6,7 +6,7 @@
model = "Bluegiga APX4 Development Kit";
compatible = "bluegiga,apx4devkit", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x04000000>;
};
@@ -82,7 +82,8 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
+ mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
@@ -146,6 +147,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 570aa339a05e..e54f5aba7091 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -16,7 +16,7 @@
model = "Crystalfontz CFA-10036 Board";
compatible = "crystalfontz,cfa10036", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 4cd52d53cf00..60e5c7fd5035 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -19,6 +19,71 @@
model = "Crystalfontz CFA-10049 Board";
compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2cmux_pins_cfa10049>;
+ mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
+ i2c-parent = <&i2c1>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ adc0: nau7802@2a {
+ compatible = "nuvoton,nau7802";
+ reg = <0x2a>;
+ nuvoton,vldo = <3000>;
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ adc1: nau7802@2a {
+ compatible = "nuvoton,nau7802";
+ reg = <0x2a>;
+ nuvoton,vldo = <3000>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ adc2: nau7802@2a {
+ compatible = "nuvoton,nau7802";
+ reg = <0x2a>;
+ nuvoton,vldo = <3000>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pca_pins_cfa10049>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <19 0x2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ };
+
apb@80000000 {
apbh@80000000 {
pinctrl@80018000 {
@@ -219,71 +284,6 @@
status = "okay";
};
- i2cmux {
- compatible = "i2c-mux-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2cmux_pins_cfa10049>;
- mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
- i2c-parent = <&i2c1>;
-
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- adc0: nau7802@2a {
- compatible = "nuvoton,nau7802";
- reg = <0x2a>;
- nuvoton,vldo = <3000>;
- };
- };
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- adc1: nau7802@2a {
- compatible = "nuvoton,nau7802";
- reg = <0x2a>;
- nuvoton,vldo = <3000>;
- };
- };
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- adc2: nau7802@2a {
- compatible = "nuvoton,nau7802";
- reg = <0x2a>;
- nuvoton,vldo = <3000>;
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- pinctrl-0 = <&pca_pins_cfa10049>;
- interrupt-parent = <&gpio2>;
- interrupts = <19 0x2>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x20>;
- };
- };
- };
-
usbphy1: usbphy@8007e000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index bd3fd470f9c3..97084e463d7c 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -19,7 +19,7 @@
model = "I2SE Duckbill 2 485";
compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index 4450047885eb..7f8d40a9c67e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -20,7 +20,7 @@
model = "I2SE Duckbill 2 EnOcean";
compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 927732efca98..13e7b134da9e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -23,7 +23,7 @@
ethernet1 = &qca7000;
};
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 7fa3d759505c..88556c93b00f 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -19,7 +19,7 @@
model = "I2SE Duckbill 2";
compatible = "i2se,duckbill-2", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index 3e4385d4ed78..f286bfe699be 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -18,7 +18,7 @@
model = "I2SE Duckbill";
compatible = "i2se,duckbill", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
index 7c1572c5a4fb..b70f3349c350 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
@@ -23,7 +23,7 @@
model = "Eukrea Electromatique MBMX283LC";
compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x04000000>;
};
};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
index b61fd61eb1c7..65efb78ac040 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
@@ -22,7 +22,7 @@
model = "Eukrea Electromatique MBMX287LC";
compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
index 49ab40838e69..ff1328ce7d37 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -151,6 +151,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 7f5b80402c54..b0d39654aeb3 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -16,7 +16,7 @@
model = "Freescale i.MX28 Evaluation Kit";
compatible = "fsl,imx28-evk", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
@@ -197,6 +197,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index a69856e41ba4..0ec415e1ff58 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -15,7 +15,7 @@
model = "Aries/DENX M28";
compatible = "aries,m28", "denx,m28", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 9d6c8fe28d74..3bb5ffc644d6 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -16,7 +16,7 @@
model = "MSR M28CU3";
compatible = "msr,m28cu3", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 22aa025cab1e..7d97a0ce74a3 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -140,6 +140,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 0ce3cb8e7914..2393e83979e0 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -16,7 +16,7 @@
model = "SchulerControl GmbH, SC SPS 1";
compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index 1e391c9f1b7a..f8a09a8c2c36 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -19,7 +19,7 @@
model = "Technologic Systems i.MX28 TS-4600";
compatible = "technologic,imx28-ts4600", "fsl,imx28";
- memory {
+ memory@40000000 {
reg = <0x40000000 0x10000000>; /* 256MB */
};
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 152621ea37db..687186358c18 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -65,8 +65,8 @@
usbotg = &usb0;
};
- memory {
- reg = <0 0>; /* will be filled in by U-Boot */
+ memory@40000000 {
+ reg = <0x40000000 0>; /* will be filled in by U-Boot */
};
onewire {
@@ -531,7 +531,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins {
+ tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */
MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */
@@ -542,7 +543,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins {
+ tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__GPIO_1_0
>;
@@ -551,7 +553,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_lcdif_23bit_pins: tx28-lcdif-23bit {
+ tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 {
+ reg = <0>;
fsl,pinmux-ids = <
/* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */
MX28_PAD_LCD_D01__LCD_D1
@@ -583,7 +586,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl {
+ tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */
MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */
@@ -593,7 +597,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_mac0_pins_gpio: tx28-mac0-gpio-pins {
+ tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__GPIO_4_0
MX28_PAD_ENET0_MDIO__GPIO_4_1
@@ -610,7 +615,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_pca9554_pins: tx28-pca9554-pins {
+ tx28_pca9554_pins: tx28-pca9554-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_PWM3__GPIO_3_28
>;
@@ -619,7 +625,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_spi_gpio_pins: spi-gpiogrp {
+ tx28_spi_gpio_pins: spi-gpiogrp@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__GPIO_3_8
MX28_PAD_AUART2_TX__GPIO_3_9
@@ -633,7 +640,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_tsc2007_pins: tx28-tsc2007-pins {
+ tx28_tsc2007_pins: tx28-tsc2007-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
>;
@@ -643,7 +651,8 @@
};
- tx28_usbphy0_pins: tx28-usbphy0-pins {
+ tx28_usbphy0_pins: tx28-usbphy0-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */
MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
@@ -653,7 +662,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_usbphy1_pins: tx28-usbphy1-pins {
+ tx28_usbphy1_pins: tx28-usbphy1-pins@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */
MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e52e05c0fe56..9ad8d3556859 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -24,7 +24,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &mac0;
@@ -283,7 +283,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_status_cfg: gpmi-status-cfg {
+ gpmi_status_cfg: gpmi-status-cfg@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDN__GPMI_RDN
MX28_PAD_GPMI_WRN__GPMI_WRN
@@ -527,14 +528,16 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_cd_cfg: mmc0-cd-cfg {
+ mmc0_cd_cfg: mmc0-cd-cfg@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc0_sck_cfg: mmc0-sck-cfg {
+ mmc0_sck_cfg: mmc0-sck-cfg@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_SCK__SSP0_SCK
>;
@@ -558,14 +561,16 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc1_cd_cfg: mmc1-cd-cfg {
+ mmc1_cd_cfg: mmc1-cd-cfg@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc1_sck_cfg: mmc1-sck-cfg {
+ mmc1_sck_cfg: mmc1-sck-cfg@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
@@ -606,7 +611,8 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc2_cd_cfg: mmc2-cd-cfg {
+ mmc2_cd_cfg: mmc2-cd-cfg@0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
>;
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index ae6cebbed84b..6ee4ff8e4e8f 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -16,7 +16,7 @@
model = "Buglabs i.MX31 Bug 1.x";
compatible = "buglabs,imx31-bug", "fsl,imx31";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x8000000>; /* 128M */
};
};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index a72031407ebd..ebc3f2dbb6fd 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -19,7 +19,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
serial0 = &uart1;
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
index 9c2b715ab8bf..ba39d938f289 100644
--- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -17,7 +17,7 @@
model = "Eukrea CPUIMX35";
compatible = "eukrea,cpuimx35", "fsl,imx35";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x8000000>; /* 128M */
};
};
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts
index 9bb628f22502..646b1257bba2 100644
--- a/arch/arm/boot/dts/imx35-pdk.dts
+++ b/arch/arm/boot/dts/imx35-pdk.dts
@@ -17,7 +17,7 @@
model = "Freescale i.MX35 Product Development Kit";
compatible = "fsl,imx35-pdk", "fsl,imx35";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x8000000>,
<0x90000000 0x8000000>;
};
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index e08c0c193767..bf343195697e 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -20,7 +20,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 98b5faa06e27..23f1833e23fa 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -18,7 +18,7 @@
model = "Freescale i.MX50 Evaluation Kit";
compatible = "fsl,imx50-evk", "fsl,imx50";
- memory {
+ memory@70000000 {
reg = <0x70000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 35955e63d6c5..7954e79d0a16 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -25,7 +25,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index c83ac1600322..79d80036f74d 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -21,7 +21,7 @@
model = "Armadeus Systems APF51 module";
compatible = "armadeus,imx51-apf51", "fsl,imx51";
- memory {
+ memory@90000000 {
reg = <0x90000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 4ac5ab614a7f..cf7a1963df25 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,7 +21,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@90000000 {
reg = <0x90000000 0x20000000>;
};
@@ -369,6 +369,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clk_audio>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
index 1db517d3d497..2967a748d859 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
@@ -17,7 +17,7 @@
"digi,connectcore-ccxmx51-som", "fsl,imx51";
chosen {
- linux,stdout-path = &uart1;
+ stdout-path = &uart1;
};
};
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index b821066a0d2a..5761a66e8a0d 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -16,7 +16,7 @@
model = "Digi ConnectCore CC(W)-MX51";
compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
- memory {
+ memory@90000000 {
reg = <0x90000000 0x08000000>;
};
};
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
index 63164266af83..f8902a338e49 100644
--- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -22,7 +22,7 @@
model = "Eukrea CPUIMX51";
compatible = "eukrea,cpuimx51", "fsl,imx51";
- memory {
+ memory@90000000 {
reg = <0x90000000 0x10000000>; /* 256M */
};
};
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index f59b02bae68d..39eb067904c3 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -17,7 +17,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@90000000 {
reg = <0x90000000 0x10000000>;
};
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 5306b78de0ca..0c99ac04ad08 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -51,6 +51,11 @@
stdout-path = &uart1;
};
+ /* Will be filled by the bootloader */
+ memory@90000000 {
+ reg = <0x90000000 0>;
+ };
+
aliases {
mdio-gpio0 = &mdio_gpio;
rtc0 = &ds1341;
@@ -568,6 +573,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+ };
};
&usbh1 {
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 00d30bd70068..5d390a64e976 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -26,7 +26,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 4486bc47d140..80fc00705d92 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -17,7 +17,7 @@
model = "Freescale i.MX53 Automotive Reference Design Board";
compatible = "fsl,imx53-ard", "fsl,imx53";
- memory {
+ memory@70000000 {
reg = <0x70000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts
index 5e67e43004e7..cf70ebc4399a 100644
--- a/arch/arm/boot/dts/imx53-cx9020.dts
+++ b/arch/arm/boot/dts/imx53-cx9020.dts
@@ -21,7 +21,7 @@
stdout-path = &uart2;
};
- memory {
+ memory@70000000 {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index 7ce69c63510c..3da6dd5edb79 100644
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -15,7 +15,7 @@
model = "Aries/DENX M53";
compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
- memory {
+ memory@70000000 {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index e48525763b1b..3935fe6490ed 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -153,6 +153,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index cce959438a79..d5628af2e301 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -132,6 +132,14 @@
enable-active-high;
};
+ reg_tsiref: regulator-tsiref {
+ compatible = "regulator-fixed";
+ regulator-name = "tsiref";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
pwm_bl: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000>;
@@ -294,6 +302,8 @@
interrupt-parent = <&gpio3>;
interrupts = <12 0x8>;
spi-max-frequency = <1000000>;
+ dlg,tsi-as-adc;
+ tsiref-supply = <&reg_tsiref>;
regulators {
buck1_reg: buck1 {
@@ -436,6 +446,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0xa>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_sgtl5k>;
VDDIO-supply = <&reg_sgtl5k>;
clocks = <&cko2_11M>;
@@ -525,6 +536,7 @@
touchscreen@4b {
compatible = "atmel,maxtouch";
+ reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
reg = <0x4b>;
interrupt-parent = <&gpio5>;
interrupts = <4 0x8>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 41a2e2a2b079..485a69d45e1c 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -17,7 +17,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@70000000 {
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
@@ -317,6 +317,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 51f4a42a55e2..fd030128666c 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -17,7 +17,7 @@
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
compatible = "fsl,imx53-smd", "fsl,imx53";
- memory {
+ memory@70000000 {
reg = <0x70000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index eecdc1c55eef..a72b8981fc3b 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -16,7 +16,7 @@
model = "TQ TQMa53";
compatible = "tq,tqma53", "fsl,imx53";
- memory {
+ memory@70000000 {
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
};
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index fe15c9555d6e..af8ec5e4417b 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -230,6 +230,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
index f2b2ad3ce9e5..6cdf2082c742 100644
--- a/arch/arm/boot/dts/imx53-tx53-x13x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -131,6 +131,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index a22e461fc168..69a2af7d6c11 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -49,6 +49,11 @@
model = "Ka-Ro electronics TX53 module";
compatible = "karo,tx53", "fsl,imx53";
+ /* Will be filled by the bootloader */
+ memory@70000000 {
+ reg = <0x70000000 0>;
+ };
+
aliases {
can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
can1 = &can1;
diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts
index 6782d7fc5961..f6268d0ded29 100644
--- a/arch/arm/boot/dts/imx53-usbarmory.dts
+++ b/arch/arm/boot/dts/imx53-usbarmory.dts
@@ -57,7 +57,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@70000000 {
reg = <0x70000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index 25c78f19826c..957053755c3c 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -133,6 +133,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&clks 150>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 1040251f2951..7d647d043f52 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -26,7 +26,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/imx6dl-apf6dev.dts
index df26e542ab3a..4a7f86de6c39 100644
--- a/arch/arm/boot/dts/imx6dl-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -54,7 +54,7 @@
model = "Armadeus APF6 Solo Module on APF6Dev Board";
compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
index 5f0d196495d0..7128c76d5721 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
@@ -48,7 +48,7 @@
model = "aristainetos2 i.MX6 Dual Lite Board 4";
compatible = "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
index 805b1318b7f7..240f3661469f 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
@@ -48,7 +48,7 @@
model = "aristainetos2 i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 3c9f4af9e9ff..ad7733662fe5 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -27,7 +27,7 @@
status = "okay";
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index 96cd835ccbf6..64ed84e3c512 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -16,7 +16,7 @@
model = "aristainetos i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index dcf9206f3e0d..ea184d108491 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -53,6 +53,11 @@
compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
"fsl,imx6dl";
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
aliases {
i2c0 = &i2c2;
i2c1 = &i2c3;
@@ -63,6 +68,10 @@
rtc1 = &snvs_rtc;
};
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
clocks {
/* Fixed crystal dedicated to mcp251x */
clk16m: clk@1 {
diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
index 994f96a3fb54..89384cb618f6 100644
--- a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
+++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
@@ -20,4 +20,9 @@
/ {
model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..9f7f9f98139d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
+ compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06",
+ "phytec,imx6qdl-pcm058", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&ethphy {
+ max-speed = <100>;
+};
+
+&fec {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
index 964bc2ad3c5d..7d9888937f12 100644
--- a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
@@ -16,7 +16,7 @@
model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts
index c3a14a4330a2..3fb7f4ee2496 100644
--- a/arch/arm/boot/dts/imx6dl-rex-basic.dts
+++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts
@@ -16,7 +16,7 @@
model = "Rex Basic i.MX6 Dual Lite Board";
compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 23e108204e1e..2e98c92adff7 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -15,7 +15,7 @@
model = "RIoTboard i.MX6S";
compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts
index 6ea0b780677d..cc01a7a22e30 100644
--- a/arch/arm/boot/dts/imx6dl-ts4900.dts
+++ b/arch/arm/boot/dts/imx6dl-ts4900.dts
@@ -46,4 +46,9 @@
/ {
model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)";
compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts
index d104daf305d9..82435d5bf33f 100644
--- a/arch/arm/boot/dts/imx6dl-ts7970.dts
+++ b/arch/arm/boot/dts/imx6dl-ts7970.dts
@@ -47,4 +47,9 @@
/ {
model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)";
compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
index 8c314eee4fdd..5727fa48cfd5 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 Dual Lite Board rev B1";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
index aa4d4faaaec4..a72c07db7dda 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 Dual Lite Board revD1";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index bbb616723097..a09f274cd1f4 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 Dual Lite Board";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index c01674fa098a..558bce81209d 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -80,11 +80,6 @@
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
-
- lcdif: lcdif@20f8000 {
- reg = <0x020f8000 0x4000>;
- interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
- };
};
aips2: aips-bus@2100000 {
@@ -109,11 +104,6 @@
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
};
-
- gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu_2d>, <&gpu_3d>;
- };
};
&gpio1 {
diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/imx6q-apf6dev.dts
index 4e4de821d9e5..5e72f81cdf8b 100644
--- a/arch/arm/boot/dts/imx6q-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -54,7 +54,7 @@
model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board";
compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 4989d0bff10f..953a5b5a8ea4 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -18,7 +18,7 @@
model = "Freescale i.MX6 Quad Armadillo2 Board";
compatible = "fsl,imx6q-arm2", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index 5fcb0372d58b..bf4bdb385de9 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -46,7 +46,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index 916ea94d75ca..990e411cbca0 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -353,6 +353,14 @@
};
};
+&pmu {
+ secure-reg-access;
+};
+
+&usdhc2 {
+ status = "disabled";
+};
+
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index bc7587c383f6..65ef4cacbc71 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -50,7 +50,7 @@
model = "CompuLab CM-FX6";
compatible = "compulab,cm-fx6", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
index fd0ad9a8866c..ad12d76bbb89 100644
--- a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
+++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
@@ -20,4 +20,9 @@
/ {
model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi
index 09085fde3341..85232c7c36a0 100644
--- a/arch/arm/boot/dts/imx6q-display5.dtsi
+++ b/arch/arm/boot/dts/imx6q-display5.dtsi
@@ -47,7 +47,7 @@
model = "Liebherr (LWN) display5 i.MX6 Quad Board";
compatible = "lwn,display5", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index f0316ea96898..b3c6a4a7897d 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -29,7 +29,7 @@
stmpe-i2c1 = &stmpe2;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts
new file mode 100644
index 000000000000..57761f3172fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q-ba16.dtsi"
+
+/ {
+ model = "Advantech DMS-BA16";
+ compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ reg_usb_otg_vbus: regulator-usbotgvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotgvbus>;
+ gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sys_mclk: clock-sys-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-ba16-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-ba16-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
+};
+
+&ecspi5 {
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi5>;
+ status = "okay";
+
+ m25_eeprom: m25p80@0 {
+ compatible = "atmel,at25256B", "atmel,at25";
+ spi-max-frequency = <20000000>;
+ size = <0x8000>;
+ pagesize = <64>;
+ reg = <0>;
+ address-width = <16>;
+ };
+};
+
+&iomuxc {
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotgvbus: usbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&sys_mclk>;
+ lrclk-strength = <0x3>;
+ VDDA-supply = <&reg_1p8v>;
+ VDDIO-supply = <&reg_3p3v>;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&sata {
+ fsl,no-spread-spectrum;
+ fsl,transmit-atten-16ths = <12>;
+ fsl,transmit-boost-mdB = <3330>;
+ fsl,transmit-level-mV = <1133>;
+ fsl,receive-dpll-mode = <1>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index e0aea782c666..fcd257bc5ac3 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -50,7 +50,7 @@
model = "Uniwest Evi";
compatible = "uniwest,imx6q-evi", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index b715deb4ea46..0be375611382 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -18,7 +18,7 @@
stdout-path = &uart4;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 29adaa7c72f8..a8f70b4266ef 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -60,7 +60,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts
index 8a2ea6c58902..714e09e04dcb 100644
--- a/arch/arm/boot/dts/imx6q-h100.dts
+++ b/arch/arm/boot/dts/imx6q-h100.dts
@@ -49,6 +49,11 @@
model = "Auvidea H100";
compatible = "auvidea,h100", "fsl,imx6q";
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
@@ -161,7 +166,7 @@
status = "okay";
eeprom: 24c02@51 {
- compatible = "microchip,24c02", "at24";
+ compatible = "microchip,24c02", "atmel,24c02";
reg = <0x51>;
};
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index 432291bedcf1..dd763f205819 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -47,7 +47,7 @@
model = "Embest MarS Board i.MX6Dual";
compatible = "embest,imx6q-marsboard", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
index cab36f48d5f1..b7e9f38cec72 100644
--- a/arch/arm/boot/dts/imx6q-mccmon6.dts
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -19,7 +19,7 @@
model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
compatible = "lwn,mccmon6", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 7d7dc59507cf..52f39371188d 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -55,6 +55,11 @@
model = "Kosagi Novena Dual/Quad";
compatible = "kosagi,imx6q-novena", "fsl,imx6q";
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
chosen {
stdout-path = &uart2;
};
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
new file mode 100644
index 000000000000..2e70ea5623c6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
+ compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06",
+ "phytec,imx6qdl-pcm058", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fec {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&m25p80 {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc4 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..65d2e483c136
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
+ compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
+ "phytec,imx6qdl-pcm058", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fec {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&m25p80 {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index cd20d0a948de..fad858c30fe9 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -16,7 +16,7 @@
model = "Phytec phyFLEX-i.MX6 Quad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
index 1effb58f304c..bd57b3b74db7 100644
--- a/arch/arm/boot/dts/imx6q-pistachio.dts
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -56,7 +56,7 @@
stdout-path = &uart4;
};
- memory: memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts
index 90ea61ae04e9..d6cae73b1927 100644
--- a/arch/arm/boot/dts/imx6q-rex-pro.dts
+++ b/arch/arm/boot/dts/imx6q-rex-pro.dts
@@ -16,7 +16,7 @@
model = "Rex Pro i.MX6 Quad Board";
compatible = "rex,imx6q-rex-pro", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index 255733063ea4..b7aa2f0b9f53 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -12,7 +12,7 @@
model = "MicroSys sbc6x board";
compatible = "microsys,sbc6x", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index a3cd7afac20a..505cba776a2d 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -59,7 +59,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts
index fab76f8cd076..e655107edc56 100644
--- a/arch/arm/boot/dts/imx6q-ts4900.dts
+++ b/arch/arm/boot/dts/imx6q-ts4900.dts
@@ -46,6 +46,11 @@
/ {
model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)";
compatible = "technologic,imx6q-ts4900", "fsl,imx6q";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
&sata {
diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts
index f19e18995e68..c615ac4feede 100644
--- a/arch/arm/boot/dts/imx6q-ts7970.dts
+++ b/arch/arm/boot/dts/imx6q-ts7970.dts
@@ -47,6 +47,11 @@
/ {
model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)";
compatible = "technologic,imx6q-ts7970", "fsl,imx6q";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
&sata {
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
index 9207d80f9cfb..b763352cddae 100644
--- a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 Quad Board rev B1";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
index e87ddb168669..8691fab21058 100644
--- a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 Quad Board revD1";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
index 4a8a6ee13e9f..2a3d98c1489a 100644
--- a/arch/arm/boot/dts/imx6q-wandboard.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 Quad Board";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
index 6be8a1eea895..7da6dde9c857 100644
--- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
@@ -47,4 +47,9 @@
/ {
model = "ZII RDU2 Board";
compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bc581aa5cf17..ae7b3f107893 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -215,11 +215,6 @@
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
};
-
- gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
- };
};
&gpio1 {
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 4e776e036cbc..8206683172d2 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -47,6 +47,11 @@
model = "Toradex Apalis iMX6Q/D Module";
compatible = "toradex,apalis_imx6q", "fsl,imx6q";
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index d1cfdc264126..9332a31e6c8b 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -42,6 +42,11 @@
#include <dt-bindings/gpio/gpio.h>
/ {
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio3 9 1>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index dea8fc43c692..17a7b9c083d0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -44,7 +44,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 363a44394dad..b8044681006c 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -59,7 +59,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index c75385c0cad0..629908fbaa32 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -59,7 +59,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index eab75f3dbaf3..a1a6fb5541e1 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -59,7 +59,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 30d4662d4480..4e21b3849394 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -74,7 +74,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index c67c10605070..81dae5b5bc87 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -51,7 +51,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
index 1a0faa1a14c8..c5d95e8d2e09 100644
--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
@@ -80,7 +80,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
index d894dde6e85d..b5986efe1090 100644
--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
@@ -288,6 +288,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
index 444425153fc7..368132274a91 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -83,7 +83,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
index fd4b68be9fe9..58124adfd65b 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -93,7 +93,7 @@
};
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 92583238ca4a..7e20b47de839 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -40,6 +40,11 @@
*/
/ {
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
chosen {
stdout-path = &uart1;
};
@@ -239,10 +244,9 @@
pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
/*
- * Similar to pinctrl_usbotg_2, but we want it
- * pulled down for a fixed host connection.
+ * We want it pulled down for a fixed host connection.
*/
- fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+ fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
};
pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
index dffbc92e0023..98241acb08a6 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
@@ -40,6 +40,11 @@
*/
/ {
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
+
chosen {
stdout-path = &uart1;
};
@@ -191,6 +196,7 @@
sgtl5000: codec@a {
clocks = <&clks IMX6QDL_CLK_CKO>;
compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>;
reg = <0x0a>;
@@ -409,8 +415,7 @@
pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id {
/*
- * Similar to pinctrl_usbotg_2, but we want it
- * pulled down for a fixed host connection.
+ * We want it pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index b6220d62f6de..acc3b11fba2a 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -44,7 +44,7 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
@@ -200,7 +200,11 @@
status = "okay";
mdio {
- eth_phy: ethernet-phy {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ reg = <0x0>;
rxc-skew-ps = <1140>;
txc-skew-ps = <1140>;
txen-skew-ps = <600>;
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index a1b469c142f1..b3a463a5908b 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -45,7 +45,7 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 4cc4e23cf99c..aab088f318e8 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -46,7 +46,7 @@
stdout-path = &uart2;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index fd05f7caa472..87ca6ead4098 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -46,7 +46,7 @@
stdout-path = &uart2;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0xF0000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index 40942d6b94b3..f5b763d39285 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -46,7 +46,7 @@
stdout-path = &uart2;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 919b6b7619a4..596866b0a0d2 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -48,7 +48,7 @@
stdout-path = &uart2;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
new file mode 100644
index 000000000000..9ebd438dce7d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+
+/ {
+ aliases {
+ rtc0 = &i2c_rtc;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <&reg_backlight>;
+ pwms = <&pwm1 0 5000000>;
+ status = "okay";
+ };
+
+ gpio_leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpioleds>;
+ status = "disabled";
+
+ red {
+ label = "phyboard-mira:red";
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "phyboard-mira:green";
+ gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "phyboard-mira:blue";
+ gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ reg_backlight: regulator-backlight {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_en_switch: regulator-en-switch {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_en_switch>;
+ regulator-name = "Enable Switch";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ };
+
+ reg_flexcan1: regulator-flexcan1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1_en>;
+ regulator-name = "flexcan1-reg";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_panel: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-power-supply";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ reg_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_reg>;
+ regulator-name = "mPCIe_1V5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_h1_vbus: usb-h1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_vbus>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg_vbus: usbotg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel {
+ compatible = "auo,g104sn02";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel_en>;
+ power-supply = <&reg_panel>;
+ enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_flexcan1>;
+ status = "disabled";
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmicec>;
+ ddc-i2c-bus = <&i2c2>;
+ status = "disabled";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "disabled";
+
+ stmpe: touchctrl@44 {
+ compatible = "st,stmpe811";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_stmpe>;
+ reg = <0x44>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <12 IRQ_TYPE_NONE>;
+ status = "disabled";
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ st,sample-time = <4>;
+ st,mod-12b = <1>;
+ st,ref-sel = <0>;
+ st,adc-freq = <1>;
+ st,ave-ctrl = <1>;
+ st,touch-det-delay = <2>;
+ st,settling = <2>;
+ st,fraction-z = <7>;
+ st,i-drive = <1>;
+ };
+ };
+
+ i2c_rtc: rtc@68 {
+ compatible = "microcrystal,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_int>;
+ reg = <0x68>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "disabled";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "disabled";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <&reg_pcie>;
+ status = "disabled";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <&reg_usbotg_vbus>;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_panel_en: panelen1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
+ >;
+ };
+
+ pinctrl_en_switch: enswitchgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1_en: flexcan1engrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1
+ >;
+ };
+
+ pinctrl_gpioleds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0
+ >;
+ };
+
+ pinctrl_hdmicec: hdmicecgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1
+ >;
+ };
+
+ pinctrl_pcie_reg: pciereggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
+ >;
+ };
+
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1_vbus: usbh1vbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usbotg_vbus: usbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 585b4f6986c1..7ba317ae899b 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -13,7 +13,7 @@
/ {
chosen {
- linux,stdout-path = &uart4;
+ stdout-path = &uart4;
};
regulators {
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index d81b0078a100..c58f3443d55d 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -15,7 +15,7 @@
model = "Phytec phyFLEX-i.MX6 Quad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..6486df3e2942
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ rtc1 = &da9062_rtc;
+ rtc2 = &snvs_rtc;
+ };
+
+ /*
+ * Set the minimum memory size here and
+ * let the bootloader set the real size.
+ */
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x8000000>;
+ };
+
+ gpio_leds_som: somleds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpioleds_som>;
+
+ som-led-green {
+ label = "phycore:green";
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ m25p80: flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ status = "disabled";
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-handle = <&ethphy>;
+ phy-mode = "rgmii";
+ phy-supply = <&vdd_eth_io>;
+ phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@3 {
+ reg = <3>;
+ txc-skew-ps = <1680>;
+ rxc-skew-ps = <1860>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "disabled";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9062";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x58>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ da9062_rtc: rtc {
+ compatible = "dlg,da9062-rtc";
+ };
+
+ watchdog {
+ compatible = "dlg,da9062-watchdog";
+ };
+
+ regulators {
+ vdd_arm: buck1 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vdd_soc: buck2 {
+ regulator-name = "vdd_soc";
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vdd_ddr3_1p5: buck3 {
+ regulator-name = "vdd_ddr3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_eth_1p2: buck4 {
+ regulator-name = "vdd_eth";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd_snvs: ldo1 {
+ regulator-name = "vdd_snvs";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_high: ldo2 {
+ regulator-name = "vdd_high";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_eth_io: ldo3 {
+ regulator-name = "vdd_eth_io";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ vdd_emmc_1p8: ldo4 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&reg_arm {
+ vin-supply = <&vdd_arm>;
+};
+
+&reg_pu {
+ vin-supply = <&vdd_soc>;
+};
+
+&reg_soc {
+ vin-supply = <&vdd_soc>;
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <&vdd_emmc_1p8>;
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpioleds_som: gpioledssomgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index 6e9549ff11da..039e3b8306c4 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -137,7 +137,7 @@
status = "okay";
eeprom@57 {
- compatible = "at,24c02";
+ compatible = "atmel,24c02";
reg = <0x57>;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 82d6ccb46982..54b0139e978d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -13,7 +13,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 35de7adc997b..18b65052553d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -49,7 +49,7 @@
stdout-path = &uart2;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 0a50705b9c18..f019f9900369 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -19,7 +19,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 6abb66cd7d4a..f015e2d1cf35 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -61,8 +61,8 @@
sdhc1 = &usdhc2;
};
- memory {
- reg = <0 0>; /* will be filled by U-Boot */
+ memory@10000000 {
+ reg = <0x10000000 0>; /* will be filled by U-Boot */
};
clocks {
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index 4161b7d4323a..906387915dc5 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -35,7 +35,7 @@
pinctrl-names = "default";
};
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
index 421d6f527609..38080c1dfaec 100644
--- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
@@ -10,7 +10,7 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
- memory {
+ memory@10000000 {
reg = <0x10000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 72f52fcecee1..911f7f0e3cea 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -305,6 +305,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+ };
};
&ecspi1 {
@@ -498,7 +507,7 @@
};
eeprom@54 {
- compatible = "at,24c128";
+ compatible = "atmel,24c128";
reg = <0x54>;
};
@@ -602,6 +611,8 @@
wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v_sd>;
vqmmc-supply = <&reg_3p3v>;
+ no-1-8-v;
+ no-sdio;
status = "okay";
};
@@ -613,6 +624,8 @@
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v_sd>;
vqmmc-supply = <&reg_3p3v>;
+ no-1-8-v;
+ no-sdio;
status = "okay";
};
@@ -622,7 +635,10 @@
bus-width = <8>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
+ no-1-8-v;
non-removable;
+ no-sdio;
+ no-sd;
status = "okay";
};
@@ -805,6 +821,10 @@
};
};
+&wdog1 {
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_accel: accelgrp {
fsl,pins = <
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 59ff86695a14..c003e62bf290 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -23,7 +23,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
@@ -143,7 +143,7 @@
};
};
- pmu {
+ pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&gpc>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..f27d7ab42626
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
+ */
+
+/dts-v1/;
+#include "imx6qp.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+ model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
+ compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
+ "phytec,imx6qdl-pcm058", "fsl,imx6qp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fec {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
+
+&m25p80 {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
index f7badd82ce8a..907ba0c74ba6 100644
--- a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
@@ -16,7 +16,7 @@
model = "Wandboard i.MX6 QuadPlus Board revD1";
compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";
- memory {
+ memory@10000000 {
reg = <0x10000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
index 547a76677ab3..de5b50df833c 100644
--- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
@@ -47,4 +47,9 @@
/ {
model = "ZII RDU2+ Board";
compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp";
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ reg = <0x10000000 0>;
+ };
};
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 2844ab541759..37e792fdc160 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -16,7 +16,7 @@
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
index 72c7745f51d3..404e602e6781 100644
--- a/arch/arm/boot/dts/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -54,7 +54,7 @@
model = "WaRP Board";
compatible = "warp,imx6sl-warp", "fsl,imx6sl";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ae8df3cf687e..ab6a7e2e7e8f 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -21,7 +21,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index f9d40ee14982..b58f770c40d9 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -52,7 +52,7 @@
t_lcd = &t_lcd;
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 240a2864d044..72da5acf35a2 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -14,7 +14,7 @@
model = "Freescale i.MX6 SoloX Sabre Auto Board";
compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index d35aa858f9db..f8f31872fa14 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -20,7 +20,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
index 4d8c6521845f..252175b59247 100644
--- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
@@ -20,7 +20,7 @@
stdout-path = &uart1;
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
index 0c1fc1a8f913..40ccdf43dffc 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
@@ -48,7 +48,7 @@
model = "UDOO Neo Basic";
compatible = "udoo,neobasic", "fsl,imx6sx";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
index 5d6c2274ee2b..42bfc8f8f7f6 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
@@ -48,7 +48,7 @@
model = "UDOO Neo Extended";
compatible = "udoo,neoextended", "fsl,imx6sx";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
index 653ceb29e28b..c84c877f09d4 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
@@ -48,7 +48,7 @@
model = "UDOO Neo Full";
compatible = "udoo,neofull", "fsl,imx6sx";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index fd7879342d0d..49c7205b8db8 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -22,7 +22,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
can0 = &flexcan1;
@@ -188,6 +188,7 @@
<&clks IMX6SX_CLK_GPU>,
<&clks IMX6SX_CLK_GPU>;
clock-names = "bus", "core", "shader";
+ power-domains = <&pd_pu>;
};
dma_apbh: dma-apbh@1804000 {
@@ -767,6 +768,18 @@
#address-cells = <1>;
#size-cells = <0>;
+ power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_pu: power-domain@1 {
+ reg = <1>;
+ #power-domain-cells = <0>;
+ power-supply = <&reg_soc>;
+ clocks = <&clks IMX6SX_CLK_GPU>;
+ };
+
pd_pci: power-domain@3 {
reg = <3>;
#power-domain-cells = <0>;
@@ -1355,9 +1368,4 @@
status = "disabled";
};
};
-
- gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu>;
- };
};
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index 18fdb088ba1e..6d720b20e7ed 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -9,487 +9,9 @@
/dts-v1/;
#include "imx6ul.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
/ {
model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
-
- chosen {
- stdout-path = &uart1;
- };
-
- memory {
- reg = <0x80000000 0x20000000>;
- };
-
- backlight_display: backlight-display {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- status = "okay";
- };
-
-
- reg_sd1_vmmc: regulator-sd1-vmmc {
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "mx6ul-wm8960";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&dailink_master>;
- simple-audio-card,frame-master = <&dailink_master>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Line", "Line In",
- "Line", "Line Out",
- "Speaker", "Speaker",
- "Headphone", "Headphone Jack";
- simple-audio-card,routing =
- "Headphone Jack", "HP_L",
- "Headphone Jack", "HP_R",
- "Speaker", "SPK_LP",
- "Speaker", "SPK_LN",
- "Speaker", "SPK_RP",
- "Speaker", "SPK_RN",
- "LINPUT1", "Mic Jack",
- "LINPUT3", "Mic Jack",
- "RINPUT1", "Mic Jack",
- "RINPUT2", "Mic Jack";
-
- simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
-
- dailink_master: simple-audio-card,codec {
- sound-dai = <&codec>;
- clocks = <&clks IMX6UL_CLK_SAI2>;
- };
- };
-
- panel {
- compatible = "innolux,at043tn24";
- backlight = <&backlight_display>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
-};
-
-&clks {
- assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
- assigned-clock-rates = <786432000>;
-};
-
-&i2c2 {
- clock_frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- codec: wm8960@1a {
- #sound-dai-cells = <0>;
- compatible = "wlf,wm8960";
- reg = <0x1a>;
- wlf,shared-lrclk;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- phy-mode = "rmii";
- phy-handle = <&ethphy0>;
- status = "okay";
-};
-
-&fec2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet2>;
- phy-mode = "rmii";
- phy-handle = <&ethphy1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@2 {
- reg = <2>;
- micrel,led-mode = <1>;
- clocks = <&clks IMX6UL_CLK_ENET_REF>;
- clock-names = "rmii-ref";
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <1>;
- clocks = <&clks IMX6UL_CLK_ENET2_REF>;
- clock-names = "rmii-ref";
- };
- };
-};
-
-
-&lcdif {
- assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
- assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif_dat
- &pinctrl_lcdif_ctrl>;
- status = "okay";
-
- port {
- display_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi>;
- status = "okay";
-
- flash0: n25q256a@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a";
- spi-max-frequency = <29000000>;
- reg = <0>;
- };
-};
-
-&sai2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
- <&clks IMX6UL_CLK_SAI2>;
- assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
- assigned-clock-rates = <0>, <12288000>;
- fsl,sai-mclk-direction-output;
- status = "okay";
-};
-
-&snvs_poweroff {
- status = "okay";
-};
-
-&tsc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- measure-delay-time = <0xffff>;
- pre-charge-time = <0xfff>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usbphy1 {
- fsl,tx-d-cal = <106>;
-};
-
-&usbphy2 {
- fsl,tx-d-cal = <106>;
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <&reg_sd1_vmmc>;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- no-1-8-v;
- keep-power-in-suspend;
- wakeup-source;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
-};
-
-&iomuxc {
- pinctrl-names = "default";
-
- pinctrl_csi1: csi1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
- MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
- MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
- MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
- MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
- MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
- MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
- MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
- MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
- MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
- MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
- MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
- >;
- };
-
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
- >;
- };
-
- pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp{
- fsl,pins = <
- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp{
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
- >;
- };
-
- pinctrl_lcdif_dat: lcdifdatgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
- MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
- MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
- MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
- MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
- MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
- MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
- >;
- };
-
- pinctrl_lcdif_ctrl: lcdifctrlgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
- /* used for lcd reset */
- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
- >;
- };
-
- pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
- MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
- MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
- MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
- MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
- MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
- >;
- };
-
- pinctrl_sai2: sai2grp {
- fsl,pins = <
- MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
- MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
- MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
- MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
- MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
- >;
- };
-
- pinctrl_sim2: sim2grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
- MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
- MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
- MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
- MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
- >;
- };
-
- pinctrl_tsc: tscgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
- MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
- MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
- MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
-
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
new file mode 100644
index 000000000000..32a07232c034
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ backlight_display: backlight-display {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "mx6ul-wm8960";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Speaker", "SPK_LP",
+ "Speaker", "SPK_LN",
+ "Speaker", "SPK_RP",
+ "Speaker", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "RINPUT1", "Mic Jack",
+ "RINPUT2", "Mic Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ };
+ };
+
+ panel {
+ compatible = "innolux,at043tn24";
+ backlight = <&backlight_display>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ codec: wm8960@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ wlf,shared-lrclk;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <1>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ mag3110@e {
+ compatible = "fsl,mag3110";
+ reg = <0x0e>;
+ };
+};
+
+&lcdif {
+ assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: n25q256a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a";
+ spi-max-frequency = <29000000>;
+ reg = <0>;
+ };
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+ <&clks IMX6UL_CLK_SAI2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xfff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <&reg_sd1_vmmc>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
+ MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
+ MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
+ MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
+ MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
+ MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
+ MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
+ MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
+ MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
+ MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
+ MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
+ MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp{
+ fsl,pins = <
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+ MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+ MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+ MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+ MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ /* used for lcd reset */
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
+ MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_sim2: sim2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
+ MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
+ MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
+ MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
+ MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
+ MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
+ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
index 571eea7f1c6b..d81d20f8fc8d 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/imx6ul-geam.dts
@@ -50,7 +50,7 @@
model = "Engicam GEAM6UL Starter Kit";
compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x08000000>;
};
@@ -181,6 +181,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clks IMX6UL_CLK_OSC>;
clock-names = "mclk";
VDDA-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index 950fb28b630a..921e12c69a00 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -45,7 +45,7 @@
#include "imx6ul.dtsi"
/ {
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
@@ -142,6 +142,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clks IMX6UL_CLK_OSC>;
clock-names = "mclk";
VDDA-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi
index 039721d3dcb4..8f775f6974d1 100644
--- a/arch/arm/boot/dts/imx6ul-litesom.dtsi
+++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi
@@ -47,7 +47,7 @@
model = "Grinn i.MX6UL liteSOM";
compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
index aec5ccce0321..a031bee311df 100644
--- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -48,7 +48,7 @@
#include "imx6ul.dtsi"
/ {
- memory {
+ memory@80000000 {
reg = <0x80000000 0>; /* will be filled by U-Boot */
};
diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
index 3bf26ebd4df9..47682b8c023c 100644
--- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
@@ -51,7 +51,7 @@
model = "Technexion Pico i.MX6UL Board";
compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x10000000>;
};
diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h
index 0034eeb84542..7b9a4dc38456 100644
--- a/arch/arm/boot/dts/imx6ul-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ul-pinfunc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -34,14 +34,14 @@
#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0
#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0
#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0
-#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0
#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0
#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0
-#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0
#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0
#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0
#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0
#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0
#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0
#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0
@@ -63,12 +63,14 @@
#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0
#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0
#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0
+#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0
#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0
#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0
#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0
#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0
#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0
#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0
#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1
#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0
@@ -94,22 +96,24 @@
#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0
#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1
#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0
#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1
#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0
#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1
#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0
@@ -200,7 +204,7 @@
#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0
#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1
#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0
-#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0
#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1
#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0
#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0
@@ -232,7 +236,7 @@
#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0
#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0
#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0
-#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0
#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0
#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2
#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0
@@ -242,7 +246,7 @@
#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0
#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0
#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0
-#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0
#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3
#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0
#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0
@@ -251,7 +255,7 @@
#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0
#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0
#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0
-#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0
#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0
#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0
#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0
@@ -259,7 +263,7 @@
#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0
#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0
#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0
-#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0
#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0
#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0
#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0
@@ -267,7 +271,7 @@
#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0
#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0
#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1
-#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0
#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0
#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0
#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1
@@ -275,23 +279,23 @@
#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0
#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0
#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2
-#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0
#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0
#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0
-#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1
#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0
#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0
#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0
#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4
#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0
#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2
-#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0
#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0
#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5
#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0
#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0
#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2
-#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0
#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0
#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0
#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1
@@ -299,59 +303,61 @@
#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0
#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0
#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0
#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0
#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0
#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0
#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1
#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0
#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1
#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0
#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0
#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0
#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3
#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0
#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0
#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0
#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4
-#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0
#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1
#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0
#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2
#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0
#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1
#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0
#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3
#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0
#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0
#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0
#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0
#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0
#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0
#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0
#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0
#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2
#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0
#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0
@@ -360,7 +366,7 @@
#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1
#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0
#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0
#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0
#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0
#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0
@@ -377,7 +383,7 @@
#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0
#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2
#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0
#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1
#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0
#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0
@@ -400,6 +406,7 @@
#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0
#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0
#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0
#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0
#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0
#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0
@@ -412,7 +419,7 @@
#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0
#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1
#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0
#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0
#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0
#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0
@@ -431,7 +438,7 @@
#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1
#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0
#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0
#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0
#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0
#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0
@@ -440,7 +447,7 @@
#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0
#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0
#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2
-#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0
#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0
#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0
#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0
@@ -464,7 +471,7 @@
#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1
#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3
#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0
-#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0
#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0
#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0
#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0
@@ -477,13 +484,15 @@
#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0
#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0
#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2
#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1
#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0
#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2
#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0
@@ -491,6 +500,7 @@
#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0
#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0
#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0
#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0
#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2
#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0
@@ -498,14 +508,16 @@
#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0
#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0
#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2
#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0
#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2
+#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0
#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0
#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0
@@ -514,6 +526,7 @@
#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3
#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0
#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0
#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0
@@ -522,6 +535,7 @@
#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0
#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2
+#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0
#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0
#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0
@@ -530,6 +544,7 @@
#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3
#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0
#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0
#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0
#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0
@@ -537,56 +552,64 @@
#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0
#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2
-#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1
#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0
#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1
+#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1
#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2
#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1
#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0
#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0
#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1
#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0
#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0
#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2
#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1
-#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1
#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0
#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0
#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1
-#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1
#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0
#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0
#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1
+#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1
#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0
#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0
#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1
#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0
#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0
#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0
@@ -594,7 +617,8 @@
#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0
#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2
-#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1
#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0
@@ -602,7 +626,8 @@
#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3
#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1
#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0
@@ -610,7 +635,7 @@
#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0
#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0
#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1
#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0
#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0
#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0
@@ -622,7 +647,7 @@
#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0
#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0
#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1
#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0
#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0
#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0
@@ -631,12 +656,12 @@
#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0
#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2
#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0
-#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1
#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0
#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3
#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1
#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0
#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0
#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0
@@ -644,7 +669,7 @@
#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0
#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0
#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0
-#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1
#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0
#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0
#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0
@@ -652,7 +677,7 @@
#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0
#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0
#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0
-#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1
#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0
#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0
#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0
@@ -660,42 +685,42 @@
#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0
#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2
#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0
-#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1
#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0
#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0
#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0
#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0
#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2
#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0
-#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1
#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0
#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0
#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0
#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0
#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2
#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1
#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0
#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0
#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0
#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0
#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2
#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1
#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0
#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0
#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0
#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0
#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1
#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1
#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0
#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0
#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0
#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0
#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2
#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1
#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0
#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0
#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0
@@ -726,7 +751,7 @@
#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0
#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1
#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1
#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0
#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0
#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5
@@ -748,7 +773,7 @@
#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0
#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0
#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0
-#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1
#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0
#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0
#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0
@@ -783,7 +808,7 @@
#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0
#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0
#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0
-#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1
#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1
#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0
#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0
@@ -791,11 +816,11 @@
#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0
#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0
#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0
-#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2
#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0
#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0
#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0
-#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1
#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3
#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0
#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0
@@ -878,10 +903,10 @@
#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0
#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0
#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0
#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0
#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0
#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1
#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0
#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1
@@ -913,7 +938,7 @@
#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1
#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2
#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1
#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0
#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0
#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1
@@ -924,7 +949,7 @@
#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1
#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0
#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1
#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0
#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1
#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 65111f9843f4..f678d18ad44a 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -70,8 +70,8 @@
stdout-path = &uart1;
};
- memory {
- reg = <0 0>; /* will be filled by U-Boot */
+ memory@80000000 {
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
};
clocks {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 5d6c3ba36cd1..1241972b16ba 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -22,7 +22,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
ethernet0 = &fec1;
@@ -86,15 +86,10 @@
<&clks IMX6UL_CA7_SECONDARY_SEL>,
<&clks IMX6UL_CLK_STEP>,
<&clks IMX6UL_CLK_PLL1_SW>,
- <&clks IMX6UL_CLK_PLL1_SYS>,
- <&clks IMX6UL_PLL1_BYPASS>,
- <&clks IMX6UL_CLK_PLL1>,
- <&clks IMX6UL_PLL1_BYPASS_SRC>,
- <&clks IMX6UL_CLK_OSC>;
+ <&clks IMX6UL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
"secondary_sel", "step", "pll1_sw",
- "pll1_sys", "pll1_bypass", "pll1",
- "pll1_bypass_src", "osc";
+ "pll1_sys";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
};
@@ -102,14 +97,26 @@
intc: interrupt-controller@a01000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <&intc>;
reg = <0x00a01000 0x1000>,
<0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ status = "disabled";
+ };
+
ckil: clock-cli {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -924,6 +931,14 @@
status = "disabled";
};
+ wdog3: wdog@21e4000 {
+ compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+ reg = <0x021e4000 0x4000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_WDOG3>;
+ status = "disabled";
+ };
+
uart2: serial@21e8000 {
compatible = "fsl,imx6ul-uart",
"fsl,imx6q-uart";
diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
index 4741871434dd..30ef60344af3 100644
--- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -39,7 +39,10 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "imx6ul-14x14-evk.dts"
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
/ {
model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
new file mode 100644
index 000000000000..08669a18349e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..006690ea98c0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 Toradex AG
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* fixed crystal dedicated to mcp2515 */
+ clk16m: clk16m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
+ panel: panel {
+ compatible = "edt,et057090dhu";
+ backlight = <&bl>;
+ power-supply = <&reg_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&bl {
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ power-supply = <&reg_3v3>;
+ pwms = <&pwm4 0 5000000 1>;
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ mcp2515: can@0 {
+ compatible = "microchip,mcp2515";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_int>;
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&reg_3v3>;
+ xceiver-supply = <&reg_5v0>;
+ status = "okay";
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&lcdif {
+ status = "okay";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+ no-1-8-v;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ wakeup-source;
+ keep-power-in-suspend;
+ vmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
new file mode 100644
index 000000000000..10ab4697950f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+ &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
new file mode 100644
index 000000000000..df72ce1ae2cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
new file mode 100644
index 000000000000..3dffbcd50bf6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ wifi_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_wifi_pdn>;
+ reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ clock-frequency = <792000000>;
+ operating-points = <
+ /* kHz uV */
+ 792000 1225000
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 792000 1175000
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+ &pinctrl_gpio4 &pinctrl_gpio5>;
+
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <&reg_module_3v3>;
+ wakeup-source;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
new file mode 100644
index 000000000000..6c63a7384611
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -0,0 +1,553 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &fec2;
+ ethernet1 = &fec1;
+ };
+
+ bl: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_module_3v3_avdd: regulator-module-3v3-avdd {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-name = "+V3.3_AVDD_AUDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-gpio";
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_reg_sd>;
+ regulator-always-on;
+ regulator-name = "+V3.3_1.8_SD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <1800000 0x1 3300000 0x0>;
+ vin-supply = <&reg_module_3v3>;
+ };
+};
+
+&adc1 {
+ num-channels = <10>;
+ vref-supply = <&reg_module_3v3_avdd>;
+};
+
+/* Colibri SPI */
+&ecspi1 {
+ cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ reg = <2>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ ad7879@2c {
+ compatible = "adi,ad7879-1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
+ reg = <0x2c>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-max-pressure = <4096>;
+ adi,resistance-plate-x = <120>;
+ adi,first-conversion-delay = /bits/ 8 <3>;
+ adi,acquisition-time = /bits/ 8 <1>;
+ adi,median-filter-size = /bits/ 8 <2>;
+ adi,averaging = /bits/ 8 <1>;
+ adi,conversion-interval = /bits/ 8 <255>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ #pwm-cells = <3>;
+};
+
+&pwm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm5>;
+ #pwm-cells = <3>;
+};
+
+&pwm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm6>;
+ #pwm-cells = <3>;
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ #pwm-cells = <3>;
+};
+
+&sdma {
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ fsl,dte-mode;
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+};
+
+&usbotg2 {
+ dr_mode = "host";
+};
+
+&usdhc1 {
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+ pinctrl_can_int: canint-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
+ >;
+ };
+
+ pinctrl_enet2: enet2-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpio-bl-on-grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
+ >;
+ };
+
+ pinctrl_gpio1: gpio1-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
+ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
+ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
+ MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
+ MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
+ MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
+ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
+ >;
+ };
+
+ pinctrl_gpio2: gpio2-grp { /* Camera */
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
+ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
+ MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
+ >;
+ };
+
+ pinctrl_gpio3: gpio3-grp { /* CAN2 */
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
+ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
+ >;
+ };
+
+ pinctrl_gpio4: gpio4-grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
+ >;
+ };
+
+ pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
+ fsl,pins = <
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
+ >;
+ };
+
+ pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
+ MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpmi-nand-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdif-dat-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
+ >;
+ };
+
+ pinctrl_pwm4: pwm4-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
+ >;
+ };
+
+ pinctrl_pwm5: pwm5-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
+ >;
+ };
+
+ pinctrl_pwm6: pwm6-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
+ >;
+ };
+
+ pinctrl_pwm7: pwm7-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
+ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
+ >;
+ };
+
+ pinctrl_uart2: uart2-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+ MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
+ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
+ >;
+ };
+ pinctrl_uart5: uart5-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
+ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh_reg: gpio-usbh-reg {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
+
+ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
+ >;
+ };
+};
+
+&iomuxc_snvs {
+ pinctrl_snvs_gpio1: snvs-gpio1-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
+ >;
+ };
+
+ pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
+ >;
+ };
+
+ pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+ fsl,pins = <
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
+ >;
+ };
+
+ pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
+ >;
+ };
+
+ pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
+ >;
+ };
+
+ pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
+ >;
+ };
+
+ pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+ fsl,pins = <
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
new file mode 100644
index 000000000000..f6fb6783c193
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 0c182917b863..571ddd71cdba 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -41,3 +41,35 @@
#include "imx6ul.dtsi"
#include "imx6ull-pinfunc.h"
+#include "imx6ull-pinfunc-snvs.h"
+
+/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
+/delete-node/ &uart8;
+
+/ {
+ soc {
+ aips3: aips-bus@2200000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02200000 0x100000>;
+ ranges;
+
+ iomuxc_snvs: iomuxc-snvs@2290000 {
+ compatible = "fsl,imx6ull-iomuxc-snvs";
+ reg = <0x02290000 0x4000>;
+ };
+
+ uart8: serial@2288000 {
+ compatible = "fsl,imx6ul-uart",
+ "fsl,imx6q-uart";
+ reg = <0x02288000 0x4000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_UART8_IPG>,
+ <&clks IMX6UL_CLK_UART8_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index ae45af1ad062..7f645683f53b 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -18,7 +18,7 @@
model = "CompuLab CL-SOM-iMX7";
compatible = "compulab,cl-som-imx7", "fsl,imx7d";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
};
@@ -213,37 +213,37 @@
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
- MX7D_PAD_SD2_WP__ENET1_MDC 0x3
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
+ MX7D_PAD_SD2_WP__ENET1_MDC 0x30
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
>;
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
index 9b63b9c89e4b..04d24ee17b14 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -7,7 +7,7 @@
#include "imx7-colibri.dtsi"
/ {
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index 6f2bb70c1fbd..d9f8fb69511b 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -44,7 +44,7 @@
#include "imx7-colibri.dtsi"
/ {
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index 2b05898bb3f6..52167298984d 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -53,7 +53,7 @@
t_lcd = &t_lcd;
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index e307462a48ec..21973eb55671 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -48,7 +48,7 @@
model = "Technexion Pico i.MX7D Board";
compatible = "technexion,imx7d-pico", "fsl,imx7d";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x80000000>;
};
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index a7a5dc7b2700..5d6a08be397f 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -48,7 +48,7 @@
model = "Freescale i.MX7 SabreSD Board";
compatible = "fsl,imx7d-sdb", "fsl,imx7d";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x80000000>;
};
@@ -82,7 +82,7 @@
enable-active-high;
};
- reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
@@ -336,6 +336,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+
+ mpl3115@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
};
&i2c3 {
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index b81013455b21..fe8344cee864 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -44,7 +44,7 @@
#include "imx7-colibri.dtsi"
/ {
- memory {
+ memory@80000000 {
reg = <0x80000000 0x10000000>;
};
};
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 9bdf121f7e43..8a30b148534d 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -50,7 +50,7 @@
model = "Warp i.MX7 Board";
compatible = "warp,imx7s-warp", "fsl,imx7s";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
@@ -271,6 +271,15 @@
status = "okay";
};
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ fsl,dte-mode;
+ status = "okay";
+};
+
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
@@ -379,6 +388,13 @@
>;
};
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
+ MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 9aa2bb998552..4d42335c0dee 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -58,7 +58,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
gpio0 = &gpio1;
@@ -130,6 +130,12 @@
#phy-cells = <0>;
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
replicator {
/*
@@ -499,6 +505,14 @@
status = "disabled";
};
+ kpp: kpp@30320000 {
+ compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+ reg = <0x30320000 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+ status = "disabled";
+ };
+
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
@@ -511,9 +525,29 @@
};
ocotp: ocotp-ctrl@30350000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clks IMX7D_OCOTP_CLK>;
+
+ tempmon_calib: calib@3c {
+ reg = <0x3c 0x4>;
+ };
+
+ tempmon_temp_grade: temp-grade@10 {
+ reg = <0x10 0x4>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx7d-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon =<&anatop>;
+ nvmem-cells = <&tempmon_calib>,
+ <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
anatop: anatop@30360000 {
@@ -551,6 +585,8 @@
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs_poweroff: snvs-poweroff {
@@ -708,118 +744,156 @@
reg = <0x30800000 0x400000>;
ranges;
- ecspi1: ecspi@30820000 {
+ spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
- <&clks IMX7D_ECSPI1_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
- ecspi2: ecspi@30830000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
- <&clks IMX7D_ECSPI2_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi1: ecspi@30820000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+ <&clks IMX7D_ECSPI1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- ecspi3: ecspi@30840000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
- <&clks IMX7D_ECSPI3_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi2: ecspi@30830000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+ <&clks IMX7D_ECSPI2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART1_ROOT_CLK>,
- <&clks IMX7D_UART1_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi3: ecspi@30840000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+ <&clks IMX7D_ECSPI3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART2_ROOT_CLK>,
- <&clks IMX7D_UART2_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+ <&clks IMX7D_UART1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART3_ROOT_CLK>,
- <&clks IMX7D_UART3_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ uart2: serial@30890000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+ <&clks IMX7D_UART2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- sai1: sai@308a0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308a0000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI1_IPG_CLK>,
- <&clks IMX7D_SAI1_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
- status = "disabled";
- };
+ uart3: serial@30880000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+ <&clks IMX7D_UART3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- sai2: sai@308b0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308b0000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI2_IPG_CLK>,
- <&clks IMX7D_SAI2_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
- status = "disabled";
+ sai1: sai@308a0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308a0000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+ <&clks IMX7D_SAI1_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+ status = "disabled";
+ };
+
+ sai2: sai@308b0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308b0000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+ <&clks IMX7D_SAI2_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+ status = "disabled";
+ };
+
+ sai3: sai@308c0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308c0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+ <&clks IMX7D_SAI3_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+ status = "disabled";
+ };
};
- sai3: sai@308c0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308c0000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI3_IPG_CLK>,
- <&clks IMX7D_SAI3_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
- status = "disabled";
+ crypto: caam@30900000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30900000 0x40000>;
+ ranges = <0 0x30900000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CAAM_CLK>,
+ <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+ clock-names = "ipg", "aclk";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr1@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
flexcan1: can@30a00000 {
diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
index 5e0e7d232161..f7592155a740 100644
--- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
@@ -42,7 +42,7 @@ clocks {
domain-id = <0>;
};
- clkhyperlink0: clkhyperlink02350030 {
+ clkhyperlink0: clkhyperlink0@2350030 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index 0bcd3f8a9c45..085e7326ea8e 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -109,11 +109,14 @@
};
};
- dspgpio0: keystone_dsp_gpio@2620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
+ devctrl: device-state-control@2620000 {
+ dspgpio0: keystone_dsp_gpio@240 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x240 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
};
dsp0: dsp@10800000 {
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index fd061718dc0a..da78c0034427 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -69,6 +69,24 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
};
+ usbphy {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-bus";
+
+ usb0_phy: usb-phy@0 {
+ compatible = "usb-nop-xceiv";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ usb1_phy: usb-phy@1 {
+ compatible = "usb-nop-xceiv";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
soc0: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -97,8 +115,28 @@
};
devctrl: device-state-control@2620000 {
- compatible = "ti,keystone-devctrl", "syscon";
+ compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
reg = <0x02620000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x02620000 0x1000>;
+
+ kirq0: keystone_irq@2a0 {
+ compatible = "ti,keystone-irq";
+ reg = <0x2a0 0x10>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,syscon-dev = <&devctrl 0x2a0>;
+ };
+
+ dspgpio0: keystone_dsp_gpio@240 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x240 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
};
uart0: serial@2530c00 {
@@ -113,7 +151,7 @@
status = "disabled";
};
- uart1: serial@02531000 {
+ uart1: serial@2531000 {
compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
@@ -125,7 +163,7 @@
status = "disabled";
};
- uart2: serial@02531400 {
+ uart2: serial@2531400 {
compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
@@ -188,21 +226,6 @@
status = "disabled";
};
- kirq0: keystone_irq@26202a0 {
- compatible = "ti,keystone-irq";
- interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- ti,syscon-dev = <&devctrl 0x2a0>;
- };
-
- dspgpio0: keystone_dsp_gpio@2620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
dsp0: dsp@10800000 {
compatible = "ti,k2g-dsp";
reg = <0x10800000 0x00100000>,
@@ -460,11 +483,6 @@
status = "disabled";
};
- usb0_phy: usb-phy@0 {
- compatible = "usb-nop-xceiv";
- status = "disabled";
- };
-
keystone_usb0: keystone-dwc3@2680000 {
compatible = "ti,keystone-dwc3";
#address-cells = <1>;
@@ -488,11 +506,6 @@
};
};
- usb1_phy: usb-phy@1 {
- compatible = "usb-nop-xceiv";
- status = "disabled";
- };
-
keystone_usb1: keystone-dwc3@2580000 {
compatible = "ti,keystone-dwc3";
#address-cells = <1>;
@@ -583,5 +596,18 @@
power-domains = <&k2g_pds 0x0013>;
clocks = <&k2g_clks 0x0013 0>;
};
+
+ wdt: wdt@02250000 {
+ compatible = "ti,keystone-wdt", "ti,davinci-wdt";
+ reg = <0x02250000 0x80>;
+ power-domains = <&k2g_pds 0x22>;
+ clocks = <&k2g_clks 0x22 0>;
+ };
+
+ emif: emif@21010000 {
+ compatible = "ti,emif-keystone";
+ reg = <0x21010000 0x200>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
+ };
};
};
diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
index ed59474522cb..ca0f198ba627 100644
--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
@@ -87,60 +87,70 @@
};
};
- dspgpio0: keystone_dsp_gpio@2620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
+ devctrl: device-state-control@2620000 {
+ dspgpio0: keystone_dsp_gpio@240 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x240 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
+ dspgpio1: keystone_dsp_gpio@244 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x244 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x244>;
+ };
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
+ dspgpio2: keystone_dsp_gpio@248 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x248 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x248>;
+ };
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
+ dspgpio3: keystone_dsp_gpio@24c {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x24c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x24c>;
+ };
- dspgpio4: keystone_dsp_gpio@2620250 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x250>;
- };
+ dspgpio4: keystone_dsp_gpio@250 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x250 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x250>;
+ };
- dspgpio5: keystone_dsp_gpio@2620254 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x254>;
- };
+ dspgpio5: keystone_dsp_gpio@254 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x254 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x254>;
+ };
- dspgpio6: keystone_dsp_gpio@2620258 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x258>;
- };
+ dspgpio6: keystone_dsp_gpio@258 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x258 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x258>;
+ };
- dspgpio7: keystone_dsp_gpio@262025c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x25c>;
+ dspgpio7: keystone_dsp_gpio@25c {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x25c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x25c>;
+ };
};
dsp0: dsp@10800000 {
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index b61a830f4a4d..374c80124c4e 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -289,32 +289,38 @@
clocks = <&clkosr>;
};
- dspgpio0: keystone_dsp_gpio@2620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
+ devctrl: device-state-control@2620000 {
+ dspgpio0: keystone_dsp_gpio@240 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x240 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
+ dspgpio1: keystone_dsp_gpio@244 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x244 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x244>;
+ };
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
+ dspgpio2: keystone_dsp_gpio@248 {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x248 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x248>;
+ };
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
+ dspgpio3: keystone_dsp_gpio@24c {
+ compatible = "ti,keystone-dsp-gpio";
+ reg = <0x24c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x24c>;
+ };
};
dsp0: dsp@10800000 {
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 93ea5c69ea77..c298675a29a5 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -87,15 +87,28 @@
};
devctrl: device-state-control@2620000 {
- compatible = "ti,keystone-devctrl", "syscon";
+ compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
reg = <0x02620000 0x1000>;
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x02620000 0x1000>;
+
+ kirq0: keystone_irq@2a0 {
+ compatible = "ti,keystone-irq";
+ reg = <0x2a0 0x4>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,syscon-dev = <&devctrl 0x2a0>;
+ };
- rstctrl: reset-controller {
- compatible = "ti,keystone-reset";
- ti,syscon-pll = <&pllctrl 0xe4>;
- ti,syscon-dev = <&devctrl 0x328>;
- ti,wdt-list = <0>;
+ rstctrl: reset-controller@328 {
+ compatible = "ti,keystone-reset";
+ reg = <0x328 0x10>;
+ ti,syscon-pll = <&pllctrl 0xe4>;
+ ti,syscon-dev = <&devctrl 0x328>;
+ ti,wdt-list = <0>;
+ };
};
/include/ "keystone-clocks.dtsi"
@@ -282,14 +295,6 @@
1 0 0x21000A00 0x00000100>;
};
- kirq0: keystone_irq@26202a0 {
- compatible = "ti,keystone-irq";
- interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- ti,syscon-dev = <&devctrl 0x2a0>;
- };
-
pcie0: pcie@21800000 {
compatible = "ti,keystone-pcie", "snps,dw-pcie";
clocks = <&clkpcie>;
@@ -338,5 +343,12 @@
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
};
};
+
+ emif: emif@21010000 {
+ compatible = "ti,emif-keystone";
+ reg = <0x21010000 0x200>;
+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gic>;
+ };
};
};
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts
index d091ecb61cd2..17f48f88a983 100644
--- a/arch/arm/boot/dts/kirkwood-b3.dts
+++ b/arch/arm/boot/dts/kirkwood-b3.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for Excito Bubba B3
*
* Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*
* Note: This requires a new'ish version of u-boot, which disables the
* L2 cache. If your B3 silently fails to boot, u-boot is probably too
diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
index f16a73e49a88..07fbfca444d5 100644
--- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
+++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for Seagate Blackarmor NAS220
*
* Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
- *
- * Licensed under GPLv2 or later.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/kirkwood-d2net.dts
index e1c25c35e9ce..bd3b266dd766 100644
--- a/arch/arm/boot/dts/kirkwood-d2net.dts
+++ b/arch/arm/boot/dts/kirkwood-d2net.dts
@@ -1,11 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for d2 Network v2
*
* Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index aee6f02b1c80..2adb17c955aa 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell DB-88F6281-BP Development Board Setup
*
* Saeed Bishara <saeed@marvell.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index e8b23e13ec0c..f84a48539917 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell DB-88F6282-BP Development Board Setup
*
* Saeed Bishara <saeed@marvell.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index 812df691ae3d..6fe2e31534af 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell DB-{88F6281,88F6282}-BP Development Board Setup
*
* Saeed Bishara <saeed@marvell.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are common between the 6281
* and 6282 variants of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
index 4d2b15d6244a..31ceacd841de 100644
--- a/arch/arm/boot/dts/kirkwood-dir665.dts
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014 Claudio Leite <leitec@staticky.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts
index d4bcc1c7f6b3..29982e7acb7f 100644
--- a/arch/arm/boot/dts/kirkwood-ds109.dts
+++ b/arch/arm/boot/dts/kirkwood-ds109.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
index 95bf83b91b4a..d68c616e9309 100644
--- a/arch/arm/boot/dts/kirkwood-ds110jv10.dts
+++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts
index a85a4664431b..e1420cbcd7e4 100644
--- a/arch/arm/boot/dts/kirkwood-ds111.dts
+++ b/arch/arm/boot/dts/kirkwood-ds111.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts
index 6cef4bdbc01b..f48609e95afe 100644
--- a/arch/arm/boot/dts/kirkwood-ds112.dts
+++ b/arch/arm/boot/dts/kirkwood-ds112.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts
index 6d25093a9ac4..f41fe95e055f 100644
--- a/arch/arm/boot/dts/kirkwood-ds209.dts
+++ b/arch/arm/boot/dts/kirkwood-ds209.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts
index 2f1933efcac1..729f959a7838 100644
--- a/arch/arm/boot/dts/kirkwood-ds210.dts
+++ b/arch/arm/boot/dts/kirkwood-ds210.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts
index 7f32e7abffac..416bab50d170 100644
--- a/arch/arm/boot/dts/kirkwood-ds212.dts
+++ b/arch/arm/boot/dts/kirkwood-ds212.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts
index f5c4213fc67c..14cf4d8afaf3 100644
--- a/arch/arm/boot/dts/kirkwood-ds212j.dts
+++ b/arch/arm/boot/dts/kirkwood-ds212j.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts
index e80a962ebba0..a8650f9e3eb7 100644
--- a/arch/arm/boot/dts/kirkwood-ds409.dts
+++ b/arch/arm/boot/dts/kirkwood-ds409.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts
index cae5af4b88b5..27a1d840bd15 100644
--- a/arch/arm/boot/dts/kirkwood-ds409slim.dts
+++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts
index 72e58307416d..86907be70cf9 100644
--- a/arch/arm/boot/dts/kirkwood-ds411.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts
index 3348e330f074..bb3200daea1e 100644
--- a/arch/arm/boot/dts/kirkwood-ds411j.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411j.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts
index aaaf31b81522..9c5364a4e0a8 100644
--- a/arch/arm/boot/dts/kirkwood-ds411slim.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts
index 1b0f070c2676..6158214a939a 100644
--- a/arch/arm/boot/dts/kirkwood-laplug.dts
+++ b/arch/arm/boot/dts/kirkwood-laplug.dts
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 Maxime Hadjinlian <maxime.hadjinlian@gmail.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi b/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi
index b9125e5ed076..377b6e970259 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree common file for kirkwood-6282 based Buffalo Linkstation
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "kirkwood.dtsi"
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi b/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi
index 29d929535453..ba629e02ba31 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "kirkwood.dtsi"
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts
index 9cc05203baee..8bb381088910 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts
+++ b/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Buffalo Linkstation LS-QVL
*
@@ -6,44 +7,6 @@
* Based on kirkwood-linkstation-lswvl.dts,
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts
index ff37e76ab551..3f2a0bfe03ed 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts
+++ b/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Buffalo Linkstation LS-VL
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts
index f602c059c718..c42d0da38fe7 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts
+++ b/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Buffalo Linkstation LS-WSXL
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts
index ef8fc1a077f8..e0f62adc0d5d 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts
+++ b/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Buffalo Linkstation LS-WVL
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts b/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts
index ce41d553b693..c6024b569423 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts
+++ b/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Buffalo Linkstation LS-WXL
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/kirkwood-linkstation.dtsi
index b459042a904a..407d6d8b3a7f 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation.dtsi
+++ b/arch/arm/boot/dts/kirkwood-linkstation.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree common file for kirkwood based Buffalo Linkstation
*
* Copyright (C) 2015, 2016
* Roger Shimizu <rogershimizu@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
index f21a50dd9869..a7d659b7145a 100644
--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts
+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500)
*
@@ -6,9 +7,6 @@
* (c) 2014 Luka Perkov <luka@openwrt.org>
* (c) 2014 Randy C. Will <randall.will@gmail.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 327023a477b8..86d532916d56 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell 88F6281 GTW GE Board
*
* Lennert Buytenhek <buytenh@marvell.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are common between the 6281
* and 6282 variants of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts
index f53bcacf6b63..6a2934b7d0ce 100644
--- a/arch/arm/boot/dts/kirkwood-nas2big.dts
+++ b/arch/arm/boot/dts/kirkwood-nas2big.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for LaCie 2Big NAS
*
@@ -5,9 +6,6 @@
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts
index 13a44773b6df..3e3ac289e5b0 100644
--- a/arch/arm/boot/dts/kirkwood-net2big.dts
+++ b/arch/arm/boot/dts/kirkwood-net2big.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for LaCie 2Big Network v2
*
@@ -8,9 +9,6 @@
* Based on netxbig_v2-setup.c,
* Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts
index d2d44df9c8c0..cba8a2b6f6d9 100644
--- a/arch/arm/boot/dts/kirkwood-net5big.dts
+++ b/arch/arm/boot/dts/kirkwood-net5big.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for LaCie 5Big Network v2
*
@@ -8,9 +9,6 @@
* Based on netxbig_v2-setup.c,
* Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index c0413b63cf2e..cb564c3bcdc4 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for NETGEAR ReadyNAS Duo v2
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
index 2bfc6cfa151d..8cc8550242ef 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for NETGEAR ReadyNAS NV+ v2
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/kirkwood-netxbig.dtsi
index 52b58fe0c4fe..b5737026e244 100644
--- a/arch/arm/boot/dts/kirkwood-netxbig.dtsi
+++ b/arch/arm/boot/dts/kirkwood-netxbig.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree common file for LaCie 2Big and 5Big Network v2
*
@@ -8,9 +9,6 @@
* Based on netxbig_v2-setup.c,
* Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <dt-bindings/leds/leds-netxbig.h>
diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts
index 6ab104b4bb42..b69b096f267b 100644
--- a/arch/arm/boot/dts/kirkwood-nsa320.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa320.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/* Device tree file for the Zyxel NSA 320 NAS box.
*
* Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*
* Based upon the board setup file created by Peter Schildmann */
diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/kirkwood-nsa325.dts
index 36c64816bf7f..6f8085dbb1f4 100644
--- a/arch/arm/boot/dts/kirkwood-nsa325.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa325.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/* Device tree file for the Zyxel NSA 325 NAS box.
*
* Copyright (c) 2015, Hans Ulli Kroll <ulli.kroll@googlemail.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*
* Based upon the board setup file created by Peter Schildmann
*/
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
index 27cc913ca0f5..946f0f453dd1 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for OpenBlocks A7 board
*
@@ -5,9 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/kirkwood-openrd-base.dts
index 8af58999606d..094191ece3d7 100644
--- a/arch/arm/boot/dts/kirkwood-openrd-base.dts
+++ b/arch/arm/boot/dts/kirkwood-openrd-base.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell OpenRD Base Board Description
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are specific to OpenRD
* base variant of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/kirkwood-openrd-client.dts
index 96ff59d68f44..d4e0b8150a84 100644
--- a/arch/arm/boot/dts/kirkwood-openrd-client.dts
+++ b/arch/arm/boot/dts/kirkwood-openrd-client.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell OpenRD Client Board Description
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are specific to OpenRD
* client variant of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts
index 9f12f8b53e24..888e13320c19 100644
--- a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts
+++ b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell OpenRD Ultimate Board Description
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are specific to OpenRD
* ultimate variant of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/kirkwood-openrd.dtsi
index 7175511a92da..47f03c69c55a 100644
--- a/arch/arm/boot/dts/kirkwood-openrd.dtsi
+++ b/arch/arm/boot/dts/kirkwood-openrd.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell OpenRD (Base|Client|Ultimate) Board Description
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are common between the three
* variants of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/kirkwood-pogo_e02.dts
index a190080c9c4f..f9e95e55f36d 100644
--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts
+++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02
*
@@ -7,9 +8,6 @@
* Arch Linux ARM by Oleg Rakhmanov <moonman.ca@gmail.com>
* OpenWrt by Felix Kaechele <heffer@fedoraproject.org>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts
index 5ce220ac9611..5aa4669ae254 100644
--- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts
+++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts
@@ -35,7 +35,7 @@
pinctrl-names = "default";
eject {
- debounce_interval = <50>;
+ debounce-interval = <50>;
wakeup-source;
linux,code = <KEY_EJECTCD>;
label = "Eject Button";
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
index b8af907249fb..712d6042b132 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell RD88F6192 Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are common between the three
* variants of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
index 9ec5a65561e9..5da163591bbf 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell RD88F6181 A Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions for the board with the A0 or
* higher stepping of the SoC. The ethernet switch does not have a
* "wan" port.
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
index 6a4a65ec7944..a9fee2c2bcaf 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell RD88F6181 Z0 stepping descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions for the board using the Z0
* stepping of the SoC. The ethernet switch has a "wan" port.
*/
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index 91f5da5dae5f..0f22f0e6f56b 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Marvell RD88F6181 Common Board descrition
*
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file contains the definitions that are common between the two
* variants of the Marvell Kirkwood Development Board.
*/
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts
index 2c722ecd5331..c51cea883215 100644
--- a/arch/arm/boot/dts/kirkwood-rs212.dts
+++ b/arch/arm/boot/dts/kirkwood-rs212.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts
index 921ca49e85a4..43673b03cb35 100644
--- a/arch/arm/boot/dts/kirkwood-rs409.dts
+++ b/arch/arm/boot/dts/kirkwood-rs409.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts
index 02852b0c809f..41fa63cec839 100644
--- a/arch/arm/boot/dts/kirkwood-rs411.dts
+++ b/arch/arm/boot/dts/kirkwood-rs411.dts
@@ -1,10 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index 7196c7f3e109..0a698d3b7393 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
*
* Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
- *
- * Licensed under GPLv2
*/
#include "kirkwood.dtsi"
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index e2b4ea4f9e10..ae8f493c9a0f 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
*
* Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
- *
- * Licensed under GPLv2
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index 82f6abf120fd..c73cc904e5c4 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
*
* Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
- *
- * Licensed under GPLv2
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index 210d21a65bd1..c97ed29a0a0b 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Nodes for Marvell 628x Synology devices
*
* Andrew Lunn <andrew@lunn.ch>
* Ben Peddell <klightspeed@killerwolves.net>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/ {
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts
index 3500f4738fb0..fe63b3a03a72 100644
--- a/arch/arm/boot/dts/kirkwood-t5325.dts
+++ b/arch/arm/boot/dts/kirkwood-t5325.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for HP t5325 Thin Client"
*
@@ -6,9 +7,6 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Andrew Lunn <andrew@lunn.ch>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/kirkwood-ts419-6281.dts
index aa22aa862857..4a42ebcca4f0 100644
--- a/arch/arm/boot/dts/kirkwood-ts419-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts419-6281.dts
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for QNAP TS41X with 6281 SoC
*
* Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/kirkwood-ts419-6282.dts
index e3e71f48acc8..be772e194c2b 100644
--- a/arch/arm/boot/dts/kirkwood-ts419-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts419-6282.dts
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for QNAP TS41X with 6282 SoC
*
* Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi
index 02bd53762705..717236853e45 100644
--- a/arch/arm/boot/dts/kirkwood-ts419.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree include file for QNAP TS41X
*
* Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
/ {
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index eb2bf7409655..81c7eda2c442 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -382,7 +382,7 @@
audio0: audio-controller@a0000 {
compatible = "marvell,kirkwood-audio";
- #sound-dai-cells = <1>;
+ #sound-dai-cells = <0>;
reg = <0xa0000 0x2210>;
interrupts = <24>;
clocks = <&gate_clk 9>;
diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi
index a30ee9fcb3ae..b47cac23a04b 100644
--- a/arch/arm/boot/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi
@@ -88,10 +88,14 @@
};
&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
};
@@ -213,6 +217,18 @@
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
>;
};
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
+ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 47915447a826..3e174e474d3d 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -83,10 +83,14 @@
};
&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
at24@50 {
compatible = "atmel,24c64";
@@ -144,6 +148,18 @@
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
+ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
};
&uart2 {
diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi
index 7cae9c5e27db..10b8249b8ab6 100644
--- a/arch/arm/boot/dts/lpc18xx.dtsi
+++ b/arch/arm/boot/dts/lpc18xx.dtsi
@@ -115,7 +115,6 @@
compatible = "snps,dw-mshc";
reg = <0x40004000 0x1000>;
interrupts = <6>;
- num-slots = <1>;
clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
clock-names = "ciu", "biu";
resets = <&rgu 20>;
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c31dad98f989..c55d479971cc 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -587,7 +587,8 @@
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x0 0x2d24000 0x0 0x4000>;
+ reg = <0x0 0x2d24000 0x0 0x4000>,
+ <0x0 0x2d10030 0x0 0x4>;
};
ptp_clock@2d10e00 {
@@ -788,5 +789,21 @@
clock-names = "ipg", "per";
big-endian;
};
+
+ ocram1: sram@10000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x10000000 0x10000>;
+ };
+
+ ocram2: sram@10010000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x10010000 0x10000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index d2e3eeaa1a5f..dcc9292d2ffa 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -46,6 +46,7 @@
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
+#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include "meson.dtsi"
/ {
@@ -187,6 +188,12 @@
reg = <0x8000 0x4>, <0x4000 0x460>;
};
+ reset: reset-controller@4404 {
+ compatible = "amlogic,meson8b-reset";
+ reg = <0x4404 0x9c>;
+ #reset-cells = <1>;
+ };
+
analog_top: analog-top@81a8 {
compatible = "amlogic,meson8-analog-top", "syscon";
reg = <0x81a8 0x14>;
@@ -383,10 +390,12 @@
compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
clock-names = "usb_general", "usb";
+ resets = <&reset RESET_USB_OTG>;
};
&usb1_phy {
compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
clock-names = "usb_general", "usb";
+ resets = <&reset RESET_USB_OTG>;
};
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 9ff6ca4e20d0..3a5603d95b70 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart_AO;
+ mmc0 = &sd_card_slot;
};
memory {
@@ -69,6 +70,37 @@
default-state = "off";
};
};
+
+ tflash_vdd: regulator-tflash_vdd {
+ /*
+ * signal name from schematics: TFLASH_VDD_EN
+ */
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ /*
+ * signal name from schematics: TF_3V3N_1V8_EN
+ */
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0
+ 1800000 1>;
+ };
};
&uart_AO {
@@ -99,3 +131,59 @@
&usb1 {
status = "okay";
};
+
+&sdio {
+ status = "okay";
+
+ pinctrl-0 = <&sd_b_pins>;
+ pinctrl-names = "default";
+
+ /* SD card */
+ sd_card_slot: slot@1 {
+ compatible = "mmc-slot";
+ reg = <1>;
+ status = "okay";
+
+ bus-width = <4>;
+ no-sdio;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+ };
+};
+
+&ethmac {
+ status = "okay";
+
+ snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+
+ pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+
+ phy-mode = "rgmii";
+ phy-handle = <&eth_phy>;
+ amlogic,tx-delay-ns = <4>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Realtek RTL8211F (0x001cc916) */
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+ eee-broken-1000t;
+ interrupt-parent = <&gpio_intc>;
+ /* GPIOH_3 */
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 7cd03ed3742e..553b82174604 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -152,7 +152,7 @@
reset: reset-controller@4404 {
compatible = "amlogic,meson8b-reset";
- reg = <0x4404 0x20>;
+ reg = <0x4404 0x9c>;
#reset-cells = <1>;
};
@@ -183,7 +183,36 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_cbus 0 0 130>;
+ gpio-ranges = <&pinctrl_cbus 0 0 83>;
+ };
+
+ eth_rgmii_pins: eth-rgmii {
+ mux {
+ groups = "eth_tx_clk",
+ "eth_tx_en",
+ "eth_txd1_0",
+ "eth_txd1_1",
+ "eth_txd0_0",
+ "eth_txd0_1",
+ "eth_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd1",
+ "eth_rxd0",
+ "eth_mdio_en",
+ "eth_mdc",
+ "eth_ref_clk",
+ "eth_txd2",
+ "eth_txd3";
+ function = "ethernet";
+ };
+ };
+
+ sd_b_pins: sd-b {
+ mux {
+ groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+ "sd_d3_b", "sd_clk_b", "sd_cmd_b";
+ function = "sd_b";
+ };
};
};
};
@@ -203,8 +232,18 @@
};
&ethmac {
- clocks = <&clkc CLKID_ETH>;
- clock-names = "stmmaceth";
+ compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
+
+ reg = <0xc9410000 0x10000
+ 0xc1108140 0x4>;
+
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ resets = <&reset RESET_ETHERNET>;
+ reset-names = "stmmaceth";
};
&gpio_intc {
@@ -219,6 +258,18 @@
clock-names = "core";
};
+&i2c_AO {
+ clocks = <&clkc CLKID_CLK81>;
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
&L2 {
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
index 4d61e5b1334a..ddc7a7bb33c0 100644
--- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
+++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
@@ -68,6 +68,19 @@
};
};
+ cpcap_audio: audio-codec {
+ #sound-dai-cells = <1>;
+
+ port@0 {
+ cpcap_audio_codec0: endpoint {
+ };
+ };
+ port@1 {
+ cpcap_audio_codec1: endpoint {
+ };
+ };
+ };
+
cpcap_rtc: rtc {
compatible = "motorola,cpcap-rtc";
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index b750da5362f7..e10c03496524 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -28,7 +28,7 @@
compatible = "mediatek,mt7623";
interrupt-parent = <&sysirq>;
- cpu_opp_table: opp_table {
+ cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
@@ -87,8 +87,6 @@
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
clock-frequency = <1300000000>;
};
@@ -96,6 +94,9 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
clock-frequency = <1300000000>;
};
@@ -104,6 +105,9 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
clock-frequency = <1300000000>;
};
@@ -112,6 +116,9 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
clock-frequency = <1300000000>;
};
@@ -138,32 +145,32 @@
};
thermal-zones {
- cpu_thermal: cpu_thermal {
+ cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
- cpu_passive: cpu_passive {
+ cpu_passive: cpu-passive {
temperature = <47000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_active: cpu_active {
+ cpu_active: cpu-active {
temperature = <67000>;
hysteresis = <2000>;
type = "active";
};
- cpu_hot: cpu_hot {
+ cpu_hot: cpu-hot {
temperature = <87000>;
hysteresis = <2000>;
type = "hot";
};
- cpu_crit {
+ cpu-crit {
temperature = <107000>;
hysteresis = <2000>;
type = "critical";
@@ -670,6 +677,111 @@
#reset-cells = <1>;
};
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+ reg-names = "subsys", "port0", "port1", "port2";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&hifsys CLK_HIFSYS_PCIE0>,
+ <&hifsys CLK_HIFSYS_PCIE1>,
+ <&hifsys CLK_HIFSYS_PCIE2>;
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+ phys = <&pcie0_port PHY_TYPE_PCIE>,
+ <&pcie1_port PHY_TYPE_PCIE>,
+ <&u3port1 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ status = "disabled";
+ };
+
+ pcie@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ num-lanes = <1>;
+ status = "disabled";
+ };
+ };
+
+ pcie0_phy: pcie-phy@1a149000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0 0x1a149000 0 0x0700>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ pcie0_port: pcie-phy@1a149900 {
+ reg = <0 0x1a149900 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ pcie1_phy: pcie-phy@1a14a000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0 0x1a14a000 0 0x0700>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ pcie1_port: pcie-phy@1a14a900 {
+ reg = <0 0x1a14a900 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
usb1: usb@1a1c0000 {
compatible = "mediatek,mt7623-xhci",
"mediatek,mt8173-xhci";
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
index 7bf5aa2237c9..bbf56f855e46 100644
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -39,7 +39,34 @@
};
};
- gpio_keys {
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
@@ -120,7 +147,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- pinctrl-names = "default";
reset-gpios = <&pio 33 0>;
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
@@ -191,8 +217,8 @@
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
- vmmc-supply = <&mt6323_vemc3v3_reg>;
- vqmmc-supply = <&mt6323_vio18_reg>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
non-removable;
};
@@ -205,20 +231,42 @@
max-frequency = <50000000>;
cap-sd-highspeed;
cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&mt6323_vmch_reg>;
- vqmmc-supply = <&mt6323_vio18_reg>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_3p3v>;
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_default>;
+ status = "okay";
+
+ pcie@0,0 {
+ status = "okay";
+ };
+
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
};
&pio {
cir_pins_a:cir@0 {
- pins_cir {
+ pins-cir {
pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
bias-disable;
};
};
i2c0_pins_a: i2c@0 {
- pins_i2c0 {
+ pins-i2c0 {
pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
<MT7623_PIN_76_SCL0_FUNC_SCL0>;
bias-disable;
@@ -226,7 +274,7 @@
};
i2c1_pins_a: i2c@1 {
- pin_i2c1 {
+ pin-i2c1 {
pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
<MT7623_PIN_58_SCL1_FUNC_SCL1>;
bias-disable;
@@ -234,7 +282,7 @@
};
i2s0_pins_a: i2s@0 {
- pin_i2s0 {
+ pin-i2s0 {
pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
<MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
<MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
@@ -246,7 +294,7 @@
};
i2s1_pins_a: i2s@1 {
- pin_i2s1 {
+ pin-i2s1 {
pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
<MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
<MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
@@ -258,7 +306,7 @@
};
key_pins_a: keys@0 {
- pins_keys {
+ pins-keys {
pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
<MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
input-enable;
@@ -266,7 +314,7 @@
};
led_pins_a: leds@0 {
- pins_leds {
+ pins-leds {
pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
<MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
<MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
@@ -274,7 +322,7 @@
};
mmc0_pins_default: mmc0default {
- pins_cmd_dat {
+ pins-cmd-dat {
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
@@ -288,19 +336,19 @@
bias-pull-up;
};
- pins_clk {
+ pins-clk {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
bias-pull-down;
};
- pins_rst {
+ pins-rst {
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc0_pins_uhs: mmc0 {
- pins_cmd_dat {
+ pins-cmd-dat {
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
@@ -315,20 +363,20 @@
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_2mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
- pins_rst {
+ pins-rst {
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc1_pins_default: mmc1default {
- pins_cmd_dat {
+ pins-cmd-dat {
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
@@ -339,26 +387,26 @@
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
bias-pull-down;
drive-strength = <MTK_DRIVE_4mA>;
};
- pins_wp {
+ pins-wp {
pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
input-enable;
bias-pull-up;
};
- pins_insert {
+ pins-insert {
pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
bias-pull-up;
};
};
mmc1_pins_uhs: mmc1 {
- pins_cmd_dat {
+ pins-cmd-dat {
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
@@ -369,15 +417,23 @@
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
+ pcie_default: pcie_pin_default {
+ pins_cmd_dat {
+ pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
+ <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
+ bias-disable;
+ };
+ };
+
pwm_pins_a: pwm@0 {
- pins_pwm {
+ pins-pwm {
pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
<MT7623_PIN_204_PWM1_FUNC_PWM1>,
<MT7623_PIN_205_PWM2_FUNC_PWM2>,
@@ -387,7 +443,7 @@
};
spi0_pins_a: spi@0 {
- pins_spi {
+ pins-spi {
pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
@@ -397,18 +453,25 @@
};
uart0_pins_a: uart@0 {
- pins_dat {
+ pins-dat {
pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
<MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
};
};
uart1_pins_a: uart@1 {
- pins_dat {
+ pins-dat {
pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
<MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
};
};
+
+ uart2_pins_a: uart@2 {
+ pins-dat {
+ pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
+ <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
+ };
+ };
};
&pwm {
@@ -454,26 +517,30 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
- status = "disabled";
+ status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
- status = "disabled";
+ status = "okay";
};
&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_a>;
status = "okay";
};
&usb1 {
- vusb33-supply = <&mt6323_vusb_reg>;
+ vusb33-supply = <&reg_3p3v>;
+ vbus-supply = <&reg_5v>;
status = "okay";
};
&usb2 {
- vusb33-supply = <&mt6323_vusb_reg>;
+ vusb33-supply = <&reg_3p3v>;
+ vbus-supply = <&reg_5v>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
index e66de8611650..f729c718aba1 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -81,13 +81,13 @@
&pio {
nand_pins_default: nanddefault {
- pins_ale {
+ pins-ale {
pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
- pins_dat {
+ pins-dat {
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
<MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
<MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
@@ -102,7 +102,7 @@
bias-pull-up;
};
- pins_we {
+ pins-we {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
new file mode 100644
index 000000000000..d2d0761295a4
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
+// Copyright 2018 Google, Inc.
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ /* external reference clock */
+ clk_refclk: clk_refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "refclk";
+ };
+
+ /* external reference clock for cpu. float in normal operation */
+ clk_sysbypck: clk_sysbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sysbypck";
+ };
+
+ /* external reference clock for MC. float in normal operation */
+ clk_mcbypck: clk_mcbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "mcbypck";
+ };
+
+ /* external clock signal rg1refck, supplied by the phy */
+ clk_rg1refck: clk_rg1refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg1refck";
+ };
+
+ /* external clock signal rg2refck, supplied by the phy */
+ clk_rg2refck: clk_rg2refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg2refck";
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clk_xin";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0xf0000000 0x00900000>;
+
+ gcr: gcr@800000 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
+ "simple-mfd";
+ reg = <0x800000 0x1000>;
+ };
+
+ scu: scu@3fe000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x3fe000 0x1000>;
+ };
+
+ l2: cache-controller@3fc000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x3fc000 0x1000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ clocks = <&clk 10>;
+ arm,shared-override;
+ };
+
+ gic: interrupt-controller@3ff000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x3ff000 0x1000>,
+ <0x3fe100 0x100>;
+ };
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm750-clk", "syscon";
+ #clock-cells = <1>;
+ clock-controller;
+ reg = <0xf0801000 0x1000>;
+ clock-names = "refclk", "sysbypck", "mcbypck";
+ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0xf0000000 0x00300000>;
+
+ timer0: timer@8000 {
+ compatible = "nuvoton,npcm750-timer";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x8000 0x50>;
+ clocks = <&clk 5>;
+ };
+
+ watchdog0: watchdog@801C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x801C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ watchdog1: watchdog@901C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x901C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ watchdog2: watchdog@a01C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xa01C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ serial0: serial@1000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial1: serial@2000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial2: serial@3000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial3: serial@4000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
new file mode 100644
index 000000000000..15f744f1beea
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
+// Copyright 2018 Google, Inc.
+
+/dts-v1/;
+#include "nuvoton-npcm750.dtsi"
+
+/ {
+ model = "Nuvoton npcm750 Development Board (Device Tree)";
+ compatible = "nuvoton,npcm750";
+
+ chosen {
+ stdout-path = &serial3;
+ };
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+};
+
+&watchdog1 {
+ status = "okay";
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&serial3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..6ac340533587
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
+// Copyright 2018 Google, Inc.
+
+#include "nuvoton-common-npcm7xx.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk 0>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk 0>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&l2>;
+ };
+ };
+ soc {
+ timer@3fe600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x3fe600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&clk 5>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index e44d93fc644c..ded5fcf084eb 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -39,6 +39,13 @@
};
};
+&i2c3 {
+ ak8975@0f {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0f>;
+ };
+};
+
&isp {
vdd-csiphy1-supply = <&vaux2>;
vdd-csiphy2-supply = <&vaux2>;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index ab930581fc7a..182a53991c90 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -673,6 +673,7 @@
bq27200: bq27200@55 {
compatible = "ti,bq27200";
reg = <0x55>;
+ power-supplies = <&bq24150a>;
};
/* Stereo headphone amplifier */
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a005802cd52b..4043ecb38016 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -557,6 +557,7 @@
dma-names = "tx", "rx";
clocks = <&mcbsp4_fck>;
clock-names = "fck";
+ #sound-dai-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index b21084da490b..bdf73cbcec3a 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -70,8 +70,30 @@
regulator-always-on;
};
- /* HS USB Host PHY on PORT 1 */
- hsusb1_phy: hsusb1_phy {
+ /* FS USB Host PHY on port 1 for mdm6600 */
+ fsusb1_phy: usb-phy@1 {
+ compatible = "motorola,mapphone-mdm6600";
+ pinctrl-0 = <&usb_mdm6600_pins>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
+ /* mode: gpio_148 gpio_149 */
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ /* cmd: gpio_103 gpio_104 gpio_142 */
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ /* status: gpio_52 gpio_53 gpio_55 */
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+ };
+
+ /* HS USB host TLL nop-phy on port 2 for w3glte */
+ hsusb2_phy: usb-phy@2 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
@@ -117,6 +139,26 @@
};
};
+
+ soundcard {
+ compatible = "audio-graph-card";
+ label = "Droid 4 Audio";
+
+ simple-graph-card,widgets =
+ "Speaker", "Earpiece",
+ "Speaker", "Loudspeaker",
+ "Headphone", "Headphone Jack",
+ "Microphone", "Internal Mic";
+
+ simple-graph-card,routing =
+ "Earpiece", "EP",
+ "Loudspeaker", "SPKR",
+ "Headphone Jack", "HSL",
+ "Headphone Jack", "HSR",
+ "MICR", "Internal Mic";
+
+ dais = <&mcbsp2_port>, <&mcbsp3_port>;
+ };
};
&dss {
@@ -124,13 +166,6 @@
};
&gpio6 {
- touchscreen_reset {
- gpio-hog;
- gpios = <13 0>;
- output-high;
- line-name = "touchscreen-reset";
- };
-
pwm8: dmtimer-pwm-8 {
pinctrl-names = "default";
pinctrl-0 = <&vibrator_direction_pin>;
@@ -362,22 +397,18 @@
};
};
-/*
- * REVISIT: Add gpio173 reset pin handling to the driver, see gpio-hog above.
- * If the GPIO reset is used, we probably need to have /lib/firmware/maxtouch.fw
- * available. See "mxt-app" and "droid4-touchscreen-firmware" tools for more
- * information.
- */
&i2c2 {
- tsp@4a {
+ touchscreen@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
+ reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */
+
/* gpio_183 with sys_nirq2 pad as wakeup */
- interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING
- &omap4_pmx_core 0x160>;
+ interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>,
+ <&omap4_pmx_core 0x160>;
interrupt-names = "irq", "wakeup";
wakeup-source;
};
@@ -435,6 +466,7 @@
touchscreen_pins: pinmux_touchscreen_pins {
pinctrl-single,pins = <
+ OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
>;
};
@@ -445,6 +477,43 @@
>;
};
+ usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
+ pinctrl-single,pins = <
+ /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+
+ /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+
+ /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
+ OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
+ OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+
+ /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
+ OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+
+ /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+
+ /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+
+ /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
+ OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
+ OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
usb_ulpi_pins: pinmux_usb_ulpi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x196, MUX_MODE7)
@@ -484,6 +553,28 @@
>;
};
+ /*
+ * Note that the v3.0.8 stock userspace dynamically remuxes uart1
+ * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7
+ * when not used. If needed, we can add rts pin remux later based
+ * on power measurements.
+ */
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
+ OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
+ OMAP4_IOPAD(0x13e, MUX_MODE1)
+
+ /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
+ OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1)
+
+ /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
+ OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2)
+ >;
+ };
+
/* uart3_tx_irtx and uart3_rx_irrx */
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
@@ -512,6 +603,24 @@
OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */
>;
};
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */
+ OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */
+ OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */
+ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */
+ >;
+ };
+
+ mcbsp3_pins: pinmux_mcbsp3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */
+ OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */
+ OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */
+ OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */
+ >;
+ };
};
&omap4_pmx_wkup {
@@ -535,6 +644,17 @@
};
};
+/*
+ * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
+ * uart1 wakeirq.
+ */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xfc>;
+};
+
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x17c>;
@@ -551,8 +671,13 @@
};
};
+&usbhsohci {
+ phys = <&fsusb1_phy>;
+ phy-names = "usb";
+};
+
&usbhsehci {
- phys = <&hsusb1_phy>;
+ phys = <&hsusb2_phy>;
};
&usbhshost {
@@ -597,3 +722,43 @@
"0", "0", "1";
};
};
+
+&mcbsp2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+
+ mcbsp2_port: port {
+ cpu_dai2: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&cpcap_audio_codec0>;
+ frame-master = <&cpcap_audio_codec0>;
+ bitclock-master = <&cpcap_audio_codec0>;
+ };
+ };
+};
+
+&mcbsp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp3_pins>;
+ status = "okay";
+
+ mcbsp3_port: port {
+ cpu_dai3: endpoint {
+ dai-format = "dsp_a";
+ frame-master = <&cpcap_audio_codec1>;
+ bitclock-master = <&cpcap_audio_codec1>;
+ remote-endpoint = <&cpcap_audio_codec1>;
+ };
+ };
+};
+
+&cpcap_audio_codec0 {
+ remote-endpoint = <&cpu_dai2>;
+};
+
+&cpcap_audio_codec1 {
+ remote-endpoint = <&cpu_dai3>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 03c8ad91ddac..cbcdcb4e7d1c 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -24,8 +24,6 @@
clock-latency = <300000>; /* From legacy driver */
/* cooling options */
- cooling-min-level = <0>;
- cooling-max-level = <3>;
#cooling-cells = <2>; /* min followed by max */
};
};
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c43f2a2d0a1e..ad97493e4e46 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -22,8 +22,6 @@
clock-latency = <300000>; /* From legacy driver */
/* cooling options */
- cooling-min-level = <0>;
- cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index 1b20838bb9a4..3b2244560c28 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -659,8 +659,8 @@
v2v1-supply = <&smps9_reg>;
enable-active-high;
- clocks = <&clk32kgaudio>;
- clock-names = "clk32k";
+ clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
+ clock-names = "clk32k", "mclk";
};
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 35d4298da83d..732b61a0e990 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -55,8 +55,6 @@
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
- cooling-min-level = <0>;
- cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
@@ -289,6 +287,28 @@
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
+
+ omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
+ compatible = "ti,omap5-scm-wkup-pad-conf",
+ "simple-bus";
+ reg = <0xcda0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xcda0 0x60>;
+
+ scm_wkup_pad_conf: scm_conf@0 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x60>;
+
+ scm_wkup_pad_conf_clocks: clocks@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
};
ocmcram: ocmcram@40300000 {
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 9619a746d657..ecc5573d264c 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -1179,3 +1179,13 @@
};
};
};
+
+&scm_wkup_pad_conf_clocks {
+ fref_xtal_ck: fref_xtal_ck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin>;
+ ti,bit-shift = <28>;
+ reg = <0x14>;
+ };
+};
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
index c701e8d16bbb..8c2449da6f00 100644
--- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -24,7 +24,7 @@
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
soc {
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 89ff404a528c..b545d0f228a5 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -30,7 +30,7 @@
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
soc {
diff --git a/arch/arm/boot/dts/orion5x-linkstation.dtsi b/arch/arm/boot/dts/orion5x-linkstation.dtsi
index e9991c83d7b7..ebd93df5d07a 100644
--- a/arch/arm/boot/dts/orion5x-linkstation.dtsi
+++ b/arch/arm/boot/dts/orion5x-linkstation.dtsi
@@ -48,7 +48,7 @@
/ {
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
soc {
diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts
index ea966ec03dd0..0d97ded66257 100644
--- a/arch/arm/boot/dts/orion5x-lswsgl.dts
+++ b/arch/arm/boot/dts/orion5x-lswsgl.dts
@@ -60,7 +60,7 @@
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
soc {
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
index ff3484904294..0324cb54939d 100644
--- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -24,7 +24,7 @@
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
soc {
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
index 6fb052507b36..d1817af53e0b 100644
--- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -21,7 +21,7 @@
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
soc {
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
index 1297414dd649..0c9729306089 100644
--- a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
@@ -23,7 +23,7 @@
};
chosen {
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
clocks {
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
index 9e317a4f431c..86f26715b619 100644
--- a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
@@ -23,7 +23,7 @@
};
chosen {
- linux,stdout-path = &uart0;
+ stdout-path = &uart0;
};
clocks {
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index 55c75b67351c..982d1a62661d 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -117,15 +117,15 @@
status = "disabled";
};
- nand0: nand@43100000 {
- compatible = "marvell,pxa3xx-nand";
+ nand_controller: nand-controller@43100000 {
+ compatible = "marvell,pxa3xx-nand-controller";
reg = <0x43100000 90>;
interrupts = <45>;
clocks = <&clks CLK_NAND>;
dmas = <&pdma 97 3>;
dma-names = "data";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index b818ebce0978..209eb21cea00 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -133,7 +133,7 @@
clock-frequency = <200000>;
eeprom@50 {
- compatible = "24c02";
+ compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <32>;
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 3ca96e361878..5341a39c0392 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -316,6 +316,23 @@
};
};
+
+ /*
+ * These channels from the ADC are simply hardware monitors.
+ * That is why the ADC is referred to as "HKADC" - HouseKeeping
+ * ADC.
+ */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&xoadc 0x00 0x01>, /* Battery */
+ <&xoadc 0x00 0x02>, /* DC in (charger) */
+ <&xoadc 0x00 0x04>, /* VPH the main system voltage */
+ <&xoadc 0x00 0x0b>, /* Die temperature */
+ <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
+ <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
+ <&xoadc 0x00 0x0e>; /* Charger temperature */
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -770,6 +787,52 @@
debounce = <15625>;
pull-up;
};
+
+ xoadc: xoadc@197 {
+ compatible = "qcom,pm8921-adc";
+ reg = <197>;
+ interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@00 {
+ reg = <0x00 0x00>;
+ };
+ vbat: adc-channel@01 {
+ reg = <0x00 0x01>;
+ };
+ dcin: adc-channel@02 {
+ reg = <0x00 0x02>;
+ };
+ vph_pwr: adc-channel@04 {
+ reg = <0x00 0x04>;
+ };
+ batt_therm: adc-channel@08 {
+ reg = <0x00 0x08>;
+ };
+ batt_id: adc-channel@09 {
+ reg = <0x00 0x09>;
+ };
+ usb_vbus: adc-channel@0a {
+ reg = <0x00 0x0a>;
+ };
+ die_temp: adc-channel@0b {
+ reg = <0x00 0x0b>;
+ };
+ ref_625mv: adc-channel@0c {
+ reg = <0x00 0x0c>;
+ };
+ ref_1250mv: adc-channel@0d {
+ reg = <0x00 0x0d>;
+ };
+ chg_temp: adc-channel@0e {
+ reg = <0x00 0x0e>;
+ };
+ ref_muxoff: adc-channel@0f {
+ reg = <0x00 0x0f>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
new file mode 100644
index 000000000000..eaa1001d0a46
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
+
+/ {
+ model = "Samsung Galaxy S5";
+ compatible = "samsung,klte", "qcom,msm8974";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&soc {
+ serial@f991e000 {
+ status = "ok";
+ };
+
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
index e87f2c99060d..701b396719c7 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
@@ -491,7 +491,7 @@
pinctrl-0 = <&i2c8_pins>;
synaptics@2c {
- compatible = "syna,rmi-i2c";
+ compatible = "syna,rmi4-i2c";
reg = <0x2c>;
interrupt-parent = <&msmgpio>;
@@ -506,6 +506,8 @@
pinctrl-names = "default";
pinctrl-0 = <&ts_int_pin>;
+ syna,startup-delay-ms = <10>;
+
rmi-f01@1 {
reg = <0x1>;
syna,nosleep = <1>;
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 75a8ca571846..1d3e9503c5bd 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -34,6 +34,10 @@
};
};
+&cmt0 {
+ status = "okay";
+};
+
&extal_clk {
clock-frequency = <20000000>;
};
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 0b74c6c7d21d..1d9073ba0ce0 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -141,29 +141,6 @@
#size-cells = <2>;
ranges;
- apmu@e6152000 {
- compatible = "renesas,r8a7743-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7743",
"renesas,rcar-gen2-gpio";
@@ -284,6 +261,48 @@
resets = <&cpg 904>;
};
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7743";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7743", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7743-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7743-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7743-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7743", "renesas,irqc";
#interrupt-cells = <2>;
@@ -316,227 +335,89 @@
#thermal-sensor-cells = <0>;
};
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7743-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7743",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
status = "disabled";
};
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7743-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7743",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
status = "disabled";
};
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7743-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7743-rst";
- reg = <0 0xe6160000 0 0x100>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7743-sysc";
- reg = <0 0xe6180000 0 0x200>;
- #power-domain-cells = <1>;
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7743",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
};
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7743";
- reg = <0 0xe6060000 0 0x250>;
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7743",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
};
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7743",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7743",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
};
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7743",
- "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7743",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
};
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7743",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
};
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7743",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7743-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
};
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7743-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
};
- /* The memory map in the User's Manual maps the cores to bus
- * numbers
+ /* The memory map in the User's Manual maps the cores to
+ * bus numbers
*/
i2c0: i2c@e6508000 {
#address-cells = <1>;
@@ -675,6 +556,168 @@
status = "disabled";
};
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7743",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7743",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7743-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7743-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7743",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7743", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&cpg 917>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7743",
"renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -954,88 +997,6 @@
status = "disabled";
};
- icram2: sram@e6300000 {
- compatible = "mmio-sram";
- reg = <0 0xe6300000 0 0x40000>;
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
- };
- };
-
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7743",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7743",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7743",
- "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- max-frequency = <97500000>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7743", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- resets = <&cpg 917>;
- status = "disabled";
- };
-
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7743",
"renesas,rcar-gen2-msiof";
@@ -1084,26 +1045,6 @@
status = "disabled";
};
- /*
- * pci1 and xhci share the same phy, therefore only one of them
- * can be active at any one time. If both of them are enabled,
- * a race condition will determine who'll control the phy.
- * A firmware file is needed by the xhci driver in order for
- * USB 3.0 to work properly.
- */
- xhci: usb@ee000000 {
- compatible = "renesas,xhci-r8a7743",
- "renesas,rcar-gen2-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- phys = <&usb2 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
@@ -1174,98 +1115,32 @@
status = "disabled";
};
- tpu: pwm@e60f0000 {
- compatible = "renesas,tpu-r8a7743", "renesas,tpu";
- reg = <0 0xe60f0000 0 0x148>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7743",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7743",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi2: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7743",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7743",
- "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7743",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7743_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
+ resets = <&cpg 916>;
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
- compatible = "renesas,usb-phy-r8a7743",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7743",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A7743_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
+ resets = <&cpg 915>;
status = "disabled";
-
- usb0: usb-channel@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
- usb2: usb-channel@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
};
vin0: video@e6ef0000 {
@@ -1301,162 +1176,6 @@
status = "disabled";
};
- du: display@feb00000 {
- compatible = "renesas,du-r8a7743";
- reg = <0 0xfeb00000 0 0x40000>,
- <0 0xfeb90000 0 0x1c>;
- reg-names = "du", "lvds.0";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 726>;
- clock-names = "du.0", "du.1", "lvds.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- };
- };
- };
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7743",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A7743_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7743",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A7743_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7743",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
- };
-
- pci1: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7743",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x10800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x11000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
- };
-
- pciec: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7743",
- "renesas,pcie-rcar-gen2";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- status = "disabled";
- };
-
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
@@ -1641,6 +1360,369 @@
};
};
};
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7743",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ /*
+ * pci1 and xhci share the same phy, therefore only one of them
+ * can be active at any one time. If both of them are enabled,
+ * a race condition will determine who'll control the phy.
+ * A firmware file is needed by the xhci driver in order for
+ * USB 3.0 to work properly.
+ */
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7743",
+ "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7743",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7743",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7743",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7743",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7743",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7743",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ max-frequency = <97500000>;
+ status = "disabled";
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7743",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7743",
+ "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7743";
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfeb90000 0 0x1c>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 726>;
+ clock-names = "du.0", "du.1", "lvds.0";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ };
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7743-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7743-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+ status = "disabled";
+ };
};
thermal-zones {
diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index ed9a8cf3fe36..8d0a392b6811 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -29,6 +29,10 @@
};
};
+&cmt0 {
+ status = "okay";
+};
+
&extal_clk {
clock-frequency = <20000000>;
};
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index ae918e9cce21..dd49a8b48f3e 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -121,29 +121,6 @@
#size-cells = <2>;
ranges;
- apmu@e6151000 {
- compatible = "renesas,r8a7745-apmu", "renesas,apmu";
- reg = <0 0xe6151000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
@@ -249,6 +226,48 @@
resets = <&cpg 905>;
};
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7745";
+ reg = <0 0xe6060000 0 0x11c>;
+ };
+
+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7745", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7745-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ apmu@e6151000 {
+ compatible = "renesas,r8a7745-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7745-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7745-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7745", "renesas,irqc";
#interrupt-cells = <2>;
@@ -269,67 +288,269 @@
resets = <&cpg 407>;
};
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7745-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7745",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7745",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7745",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7745",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7745",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7745",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ };
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7745",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7745-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7745",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7745-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7745",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7745",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7745-rst";
- reg = <0 0xe6160000 0 0x100>;
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7745",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7745-sysc";
- reg = <0 0xe6180000 0 0x200>;
- #power-domain-cells = <1>;
+ i2c5: i2c@e6528000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7745",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7745";
- reg = <0 0xe6060000 0 0x11c>;
+ iic0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7745",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ iic1: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7745",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
+
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7745",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7745",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7745-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7745-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
};
dmac0: dma-controller@e6700000 {
@@ -353,10 +574,10 @@
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -386,75 +607,45 @@
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7745",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
+ resets = <&cpg 218>;
#dma-cells = <1>;
- dma-channels = <13>;
+ dma-channels = <15>;
};
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7745-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7745",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7745-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7745", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&cpg 917>;
+ status = "disabled";
};
scifa0: serial@e6c40000 {
@@ -736,255 +927,6 @@
status = "disabled";
};
- icram2: sram@e6300000 {
- compatible = "mmio-sram";
- reg = <0 0xe6300000 0 0x40000>;
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
- };
- };
-
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7745",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7745",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7745",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7745",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7745",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7745",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c4: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7745",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c5: i2c@e6528000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7745",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- iic0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7745",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
-
- iic1: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7745",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7745",
- "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- max-frequency = <97500000>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7745", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- resets = <&cpg 917>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7745",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7745",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7745";
- reg = <0 0xfeb00000 0 0x40000>;
- reg-names = "du";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb0: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_rgb1: endpoint {
- };
- };
- };
- };
-
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7745",
"renesas,rcar-gen2-msiof";
@@ -1103,170 +1045,6 @@
status = "disabled";
};
- tpu: pwm@e60f0000 {
- compatible = "renesas,tpu-r8a7745", "renesas,tpu";
- reg = <0 0xe60f0000 0 0x148>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7745",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7745",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi2: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7745",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7745",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
- };
-
- pci1: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7745",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x10800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x11000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7745",
- "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usbphy: usb-phy@e6590100 {
- compatible = "renesas,usb-phy-r8a7745",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
-
- usb0: usb-channel@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
- usb2: usb-channel@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
- };
-
can0: can@e6e80000 {
compatible = "renesas,can-r8a7745",
"renesas,rcar-gen2-can";
@@ -1295,6 +1073,28 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7745",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7745",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
@@ -1474,6 +1274,278 @@
};
};
};
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7745",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7745",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7745",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7745",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7745",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7745",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ max-frequency = <97500000>;
+ status = "disabled";
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7745",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7745";
+ reg = <0 0xfeb00000 0 0x40000>;
+ reg-names = "du";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb0: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_rgb1: endpoint {
+ };
+ };
+ };
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7745-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7745-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+ status = "disabled";
+ };
};
timer {
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 9412a86f9b30..4b9006bac3cb 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -42,6 +42,19 @@
regulator-always-on;
};
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
ethernet@18000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18000000 0x100>;
@@ -243,6 +256,7 @@
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
+ vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index f2ea632381e7..063fdb65dc60 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -51,8 +51,11 @@
serial0 = &scif0;
serial1 = &scifa1;
i2c8 = &gpioi2c1;
+ i2c9 = &gpioi2c2;
i2c10 = &i2cexio0;
i2c11 = &i2cexio1;
+ i2c12 = &i2chdmi;
+ i2c13 = &i2cpwr;
};
chosen {
@@ -244,6 +247,12 @@
};
};
+ cec_clock: cec-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
hdmi-out {
compatible = "hdmi-connector";
type = "a";
@@ -272,8 +281,18 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
- sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ gpioi2c2: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
@@ -308,6 +327,138 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ /*
+ * IIC2 and I2C2 may be switched using pinmux.
+ * A fallback to GPIO is also provided.
+ */
+ i2chdmi: i2c-12 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep0>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
+ };
+ };
+ };
+ };
+ };
+
+ /*
+ * IIC3 and I2C3 may be switched using pinmux.
+ * IIC3/I2C3 does not appear to support fallback to GPIO.
+ */
+ i2cpwr: i2c-13 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic3>, <&i2c3>;
+ i2c-bus-name = "i2c-pwr";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ wdt {
+ compatible = "dlg,da9063-watchdog";
+ };
+ };
+
+ vdd_dvfs: regulator@68 {
+ compatible = "dlg,da9210";
+ reg = <0x68>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
};
&du {
@@ -437,11 +588,21 @@
function = "iic1";
};
+ i2c2_pins: i2c2 {
+ groups = "i2c2";
+ function = "i2c2";
+ };
+
iic2_pins: iic2 {
groups = "iic2";
function = "iic2";
};
+ i2c3_pins: i2c3 {
+ groups = "i2c3";
+ function = "i2c3";
+ };
+
iic3_pins: iic3 {
groups = "iic3";
function = "iic3";
@@ -643,124 +804,28 @@
pinctrl-names = "i2c-exio1";
};
-&iic2 {
- status = "okay";
- pinctrl-0 = <&iic2_pins>;
- pinctrl-names = "default";
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "i2c-hdmi";
clock-frequency = <100000>;
+};
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
- remote = <&vin1>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep0>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-in@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- interrupt-parent = <&gpio1>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- default-input = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+&iic2 {
+ pinctrl-0 = <&iic2_pins>;
+ pinctrl-names = "i2c-hdmi";
- port@0 {
- reg = <0>;
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
+ clock-frequency = <100000>;
+};
- port@2 {
- reg = <2>;
- adv7612_out: endpoint {
- remote-endpoint = <&vin0ep2>;
- };
- };
- };
- };
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "i2c-pwr";
};
-&iic3 {
- pinctrl-names = "default";
+&iic3 {
pinctrl-0 = <&iic3_pins>;
- status = "okay";
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- wdt {
- compatible = "dlg,da9063-watchdog";
- };
- };
-
- vdd_dvfs: regulator@68 {
- compatible = "dlg,da9210";
- reg = <0x68>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
+ pinctrl-names = "i2c-pwr";
};
&pci0 {
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
new file mode 100644
index 000000000000..a13a92c26645
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Stout board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+/dts-v1/;
+#include "r8a7790.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Stout";
+ compatible = "renesas,stout", "renesas,r8a7790";
+
+ aliases {
+ serial0 = &scifa0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led1 {
+ gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ };
+ led2 {
+ gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
+ };
+ led3 {
+ gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+ };
+ led5 {
+ gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fixedregulator3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ osc1_clk: osc1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ osc4_clk: osc4-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
+ <&osc1_clk>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ port@1 {
+ lvds_connector0: endpoint {
+ };
+ };
+ port@2 {
+ lvds_connector1: endpoint {
+ };
+ };
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&pfc {
+
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
+ function = "du";
+ };
+
+ scifa0_pins: scifa0 {
+ groups = "scifa0_data_b";
+ function = "scifa0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq1";
+ function = "intc";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data4";
+ function = "qspi";
+ };
+
+ iic2_pins: iic2 {
+ groups = "iic2_b";
+ function = "iic2";
+ };
+
+ iic3_pins: iic3 {
+ groups = "iic3";
+ function = "iic3";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+};
+
+&ether {
+ pinctrl-0 = <&ether_pins &phy1_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&cmt0 {
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpha;
+ spi-cpol;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "loader";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "uboot";
+ reg = <0x00080000 0x00040000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "uboot-env";
+ reg = <0x000c0000 0x00040000>;
+ read-only;
+ };
+ partition@100000 {
+ label = "flash";
+ reg = <0x00100000 0x03f00000>;
+ };
+ };
+ };
+};
+
+&scifa0 {
+ pinctrl-0 = <&scifa0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_dvfs>;
+};
+
+&iic2 {
+ status = "okay";
+ pinctrl-0 = <&iic2_pins>;
+ pinctrl-names = "default";
+
+ clock-frequency = <100000>;
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&osc4_clk>;
+ clock-names = "cec";
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+};
+
+&iic3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&iic3_pins>;
+ status = "okay";
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ wdt {
+ compatible = "dlg,da9063-watchdog";
+ };
+ };
+
+ vdd_dvfs: regulator@68 {
+ compatible = "dlg,da9210";
+ reg = <0x68>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd: regulator@70 {
+ compatible = "dlg,da9210";
+ reg = <0x70>;
+ interrupt-parent = <&irqc0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pci0 {
+ status = "okay";
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ed9a68538a55..e4367cecad18 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -17,7 +17,6 @@
/ {
compatible = "renesas,r8a7790";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -41,6 +40,35 @@
vin3 = &vin3;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -159,1510 +187,1553 @@
};
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
- };
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- apmu@e6151000 {
- compatible = "renesas,r8a7790-apmu", "renesas,apmu";
- reg = <0 0xe6151000 0 0x188>;
- cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
};
- apmu@e6152000 {
- compatible = "renesas,r8a7790-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7790",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7790",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7790",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7790",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7790",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7790",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
- thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7790",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7790";
+ reg = <0 0xe6060000 0 0x250>;
+ };
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7790-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
+ apmu@e6151000 {
+ compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
+ apmu@e6152000 {
+ compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7790", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7790-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7790-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7790",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7790",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7790",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7790",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7790",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a7790",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xffc80000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
- iic0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
- iic1: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
- iic2: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6520000 0 0x425>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
- <&dmac1 0x69>, <&dmac1 0x6a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
- iic3: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- mmcif1: mmc@ee220000 {
- compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
- reg = <0 0xee220000 0 0x80>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 305>;
- dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
- <&dmac1 0xe1>, <&dmac1 0xe2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 305>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7790",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7790";
- reg = <0 0xe6060000 0 0x250>;
- };
+ iic0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
+ iic1: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
- sdhi1: sd@ee120000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee120000 0 0x328>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>;
- dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
- <&dmac1 0xc9>, <&dmac1 0xca>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- status = "disabled";
- };
+ iic2: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6520000 0 0x425>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+ <&dmac1 0x69>, <&dmac1 0x6a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
- sdhi2: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
+ iic3: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
- sdhi3: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7790",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7790",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7790-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7790",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7790-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7790",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7790",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7790",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7790",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7790",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- scif2: serial@e6e56000 {
- compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e56000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7790",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7790",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7790",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7790",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7790",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7790",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7790",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7790",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
};
- };
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7790",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7790",
+ "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7790",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7790",
+ "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
- sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
- reg = <0 0xee300000 0 0x2000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- };
+ scif2: serial@e6e56000 {
+ compatible = "renesas,scif-r8a7790",
+ "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e56000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
- sata1: sata@ee500000 {
- compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
- reg = <0 0xee500000 0 0x2000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 814>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 814>;
- status = "disabled";
- };
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7790",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7790",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
- usbphy: usb-phy@e6590100 {
- compatible = "renesas,usb-phy-r8a7790",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- usb0: usb-channel@0 {
- reg = <0>;
- #phy-cells = <1>;
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- usb2: usb-channel@2 {
- reg = <2>;
- #phy-cells = <1>;
+
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 205>;
+ dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ <&dmac1 0x41>, <&dmac1 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 205>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- };
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
+ msiof3: spi@e6c90000 {
+ compatible = "renesas,msiof-r8a7790",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6c90000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 215>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+ <&dmac1 0x45>, <&dmac1 0x46>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 215>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7790",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7790",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- status = "disabled";
- };
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7790",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
- vsp@fe920000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe920000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 130>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 130>;
- };
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7790",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7790",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a7790",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+ };
- vsp@fe938000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe938000 0 0x8000>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 127>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 127>;
- };
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7790",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7790_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
- du: display@feb00000 {
- compatible = "renesas,du-r8a7790";
- reg = <0 0xfeb00000 0 0x70000>,
- <0 0xfeb90000 0 0x1c>,
- <0 0xfeb94000 0 0x1c>;
- reg-names = "du", "lvds.0", "lvds.1";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
- <&cpg CPG_MOD 725>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
};
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
};
};
- port@2 {
- reg = <2>;
- du_out_lvds1: endpoint {
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>,
+ <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>,
+ <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>,
+ <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>,
+ <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>,
+ <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+ <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+ <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>,
+ <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>,
+ <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>,
+ <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
};
};
};
- };
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- jpu: jpeg-codec@fe980000 {
- compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
- reg = <0 0xfe980000 0 0x10300>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 106>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 106>;
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7790",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7790",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7790",
+ "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7790",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7790-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
+ pci1: pci@ee0b0000 {
+ compatible = "renesas,pci-r8a7790",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0b0000 0 0xc00>,
+ <0 0xee0a0000 0 0x1100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
+ pci2: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7790",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <2 2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x20800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7790-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
+ usb@2,0 {
+ reg = <0x21000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7790-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7790",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7790", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ sdhi1: sd@ee120000 {
+ compatible = "renesas,sdhi-r8a7790",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee120000 0 0x328>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+ <&dmac1 0xc9>, <&dmac1 0xca>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
+ };
- msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 0>;
- dmas = <&dmac0 0x51>, <&dmac0 0x52>,
- <&dmac1 0x51>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ sdhi2: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7790",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
- msiof1: spi@e6e10000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e10000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x55>, <&dmac0 0x56>,
- <&dmac1 0x55>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ sdhi3: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7790",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
- msiof2: spi@e6e00000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 205>;
- dmas = <&dmac0 0x41>, <&dmac0 0x42>,
- <&dmac1 0x41>, <&dmac1 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 205>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7790",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
- msiof3: spi@e6c90000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6c90000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 215>;
- dmas = <&dmac0 0x45>, <&dmac0 0x46>,
- <&dmac1 0x45>, <&dmac1 0x46>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 215>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ mmcif1: mmc@ee220000 {
+ compatible = "renesas,mmcif-r8a7790",
+ "renesas,sh-mmcif";
+ reg = <0 0xee220000 0 0x80>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 305>;
+ dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+ <&dmac1 0xe1>, <&dmac1 0xe2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 305>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
- xhci: usb@ee000000 {
- compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- phys = <&usb2 1>;
- phy-names = "usb";
- status = "disabled";
- };
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7790",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x2000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7790",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x2000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 814>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 814>;
+ status = "disabled";
};
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7790",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
- };
- pci1: pci@ee0b0000 {
- compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0b0000 0 0xc00>,
- <0 0xee0a0000 0 0x1100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- };
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
- pci2: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
- device_type = "pci";
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- bus-range = <2 2>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x20800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7790",
+ "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
};
- usb@2,0 {
- reg = <0x21000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
+ vsp@fe920000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 130>;
};
- };
- pciec: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- status = "disabled";
- };
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A7790_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6", "src.5",
- "src.4", "src.3", "src.2", "src.1", "src.0",
- "ctu.0", "ctu.1",
- "mix.0", "mix.1",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
};
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
};
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
+ jpu: jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7790",
+ "renesas,rcar-gen2-jpu";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 106>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 106>;
};
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7790";
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfeb90000 0 0x1c>,
+ <0 0xfeb94000 0 0x1c>;
+ reg-names = "du", "lvds.0", "lvds.1";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+ <&cpg CPG_MOD 725>;
+ clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ "lvds.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ };
+ };
};
};
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
};
- };
- ipmmu_sy0: mmu@e6280000 {
- compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7790-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ status = "disabled";
+ };
- ipmmu_sy1: mmu@e6290000 {
- compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7790-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ status = "disabled";
+ };
};
- ipmmu_ds: mmu@e6740000 {
- compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
- ipmmu_mp: mmu@ec680000 {
- compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
};
- ipmmu_mx: mmu@fe951000 {
- compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
- ipmmu_rt: mmu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
- reg = <0 0xffc80000 0 0x1000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
};
};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index a50924d12b6f..f40321a1c917 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -51,7 +51,11 @@
serial0 = &scif0;
serial1 = &scif1;
i2c9 = &gpioi2c1;
+ i2c10 = &gpioi2c2;
+ i2c11 = &gpioi2c4;
i2c12 = &i2cexio1;
+ i2c13 = &i2chdmi;
+ i2c14 = &i2cexio4;
};
chosen {
@@ -312,8 +316,28 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
- sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ gpioi2c2: i2c-10 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ gpioi2c4: i2c-11 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
@@ -328,6 +352,115 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ /*
+ * A fallback to GPIO is provided for I2C2.
+ */
+ i2chdmi: i2c-13 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c2>, <&gpioi2c2>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
+ };
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "renesas,r1ex24002", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+ };
+
+ /*
+ * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
+ * A fallback to GPIO is provided.
+ */
+ i2cexio4: i2c-14 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c4>, <&gpioi2c4>;
+ i2c-bus-name = "i2c-exio4";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&du {
@@ -371,6 +504,11 @@
function = "i2c2";
};
+ i2c4_pins: i2c4 {
+ groups = "i2c4_c";
+ function = "i2c4";
+ };
+
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
@@ -621,96 +759,14 @@
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-hdmi";
- status = "okay";
clock-frequency = <100000>;
+};
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
- remote = <&vin1>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cec_clock>;
- clock-names = "cec";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-in@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- interrupt-parent = <&gpio4>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- default-input = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- adv7612_out: endpoint {
- remote-endpoint = <&vin0ep2>;
- };
- };
- };
- };
-
- eeprom@50 {
- compatible = "renesas,r1ex24002", "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
+&i2c4 {
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "i2c-exio4";
};
&i2c6 {
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index eb374956294f..c14e6fe9e4f6 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -29,6 +29,8 @@
aliases {
serial0 = &scif0;
+ i2c9 = &gpioi2c2;
+ i2c10 = &i2chdmi;
};
chosen {
@@ -135,6 +137,78 @@
clocks = <&x14_clk>;
};
};
+
+ gpioi2c2: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * A fallback to GPIO is provided for I2C2.
+ */
+ i2chdmi: i2c-10 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c2>, <&gpioi2c2>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ak4642: codec@12 {
+ compatible = "asahi-kasei,ak4642";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin0>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+ };
};
&extal_clk {
@@ -296,61 +370,9 @@
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-hdmi";
- status = "okay";
clock-frequency = <400000>;
-
- ak4642: codec@12 {
- compatible = "asahi-kasei,ak4642";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
- remote = <&vin0>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
};
&sata0 {
@@ -425,7 +447,7 @@
"dclkin.0", "dclkin.1";
ports {
- port@1 {
+ port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 008a260f86a5..f11dab71b03a 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -17,7 +17,6 @@
/ {
compatible = "renesas,r8a7791";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -40,6 +39,35 @@
vin2 = &vin2;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -83,1585 +111,1627 @@
};
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
- };
- };
-
- apmu@e6152000 {
- compatible = "renesas,r8a7791-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
};
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 904>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 904>;
- };
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
- thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7791",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7791", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7791",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
+ };
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7791";
+ reg = <0 0xe6060000 0 0x250>;
+ };
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7791-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ apmu@e6152000 {
+ compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7791-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7791-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
- /* The memory map in the User's Manual maps the cores to bus numbers */
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7791", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7791",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c4: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c5: i2c@e6528000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c6: i2c@e60b0000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c7: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xffc80000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c8: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7791",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7791";
- reg = <0 0xe6060000 0 0x250>;
- };
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7791",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
- sdhi1: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7791",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
+ /* The memory map in the User's Manual maps the cores to
+ * bus numbers
+ */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- sdhi2: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7791",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scifa3: serial@e6c70000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c70000 0 64>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1106>;
- clock-names = "fck";
- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
- <&dmac1 0x1b>, <&dmac1 0x1c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1106>;
- status = "disabled";
- };
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
- scifa4: serial@e6c78000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c78000 0 64>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1107>;
- clock-names = "fck";
- dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
- <&dmac1 0x1f>, <&dmac1 0x20>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1107>;
- status = "disabled";
- };
+ i2c6: i2c@e60b0000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7791",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
- scifa5: serial@e6c80000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c80000 0 64>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1108>;
- clock-names = "fck";
- dmas = <&dmac0 0x23>, <&dmac0 0x24>,
- <&dmac1 0x23>, <&dmac1 0x24>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1108>;
- status = "disabled";
- };
+ i2c7: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7791",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7791",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
+ i2c8: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7791",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7791",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7791",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7791",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7791",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7791-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
- adc: adc@e6e54000 {
- compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
- reg = <0 0xe6e54000 0 64>;
- clocks = <&cpg CPG_MOD 901>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 901>;
- status = "disabled";
- };
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7791-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7791",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7791",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- scif4: serial@e6ee0000 {
- compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ee0000 0 64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
- <&dmac1 0xfb>, <&dmac1 0xfc>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7791",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- scif5: serial@e6ee8000 {
- compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ee8000 0 64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
- <&dmac1 0xfd>, <&dmac1 0xfe>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7791",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7791",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
- hscif2: serial@e62d0000 {
- compatible = "renesas,hscif-r8a7791",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62d0000 0 96>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
- <&dmac1 0x3b>, <&dmac1 0x3c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1106>;
+ status = "disabled";
+ };
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1107>;
+ status = "disabled";
+ };
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7791",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1108>;
+ status = "disabled";
};
- };
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7791",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7791",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7791",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7791",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
- sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
- reg = <0 0xee300000 0 0x2000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- };
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7791",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
- sata1: sata@ee500000 {
- compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
- reg = <0 0xee500000 0 0x2000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 814>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 814>;
- status = "disabled";
- };
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7791",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7791",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
- usbphy: usb-phy@e6590100 {
- compatible = "renesas,usb-phy-r8a7791",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7791",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
- usb0: usb-channel@0 {
- reg = <0>;
- #phy-cells = <1>;
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7791",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
};
- usb2: usb-channel@2 {
- reg = <2>;
- #phy-cells = <1>;
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7791",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
};
- };
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7791",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7791",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7791",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7791",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
+ };
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 000>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- vsp@fe938000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe938000 0 0x8000>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 127>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 127>;
- };
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- du: display@feb00000 {
- compatible = "renesas,du-r8a7791";
- reg = <0 0xfeb00000 0 0x40000>,
- <0 0xfeb90000 0 0x1c>;
- reg-names = "du", "lvds.0";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 726>;
- clock-names = "du.0", "du.1", "lvds.0";
- status = "disabled";
-
- ports {
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7791",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 205>;
+ dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ <&dmac1 0x41>, <&dmac1 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 205>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+ };
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- };
- };
+ adc: adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc",
+ "renesas,rcar-gyroadc";
+ reg = <0 0xe6e54000 0 64>;
+ clocks = <&cpg CPG_MOD 901>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 901>;
+ status = "disabled";
};
- };
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7791",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7791",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
- jpu: jpeg-codec@fe980000 {
- compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
- reg = <0 0xfe980000 0 0x10300>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 106>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 106>;
- };
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7791",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7791",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7791",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7791",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7791_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0", "src.9", "src.8",
+ "src.7", "src.6", "src.5", "src.4",
+ "src.3", "src.2", "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7791-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>,
+ <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>,
+ <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>,
+ <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>,
+ <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>,
+ <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+ <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+ <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>,
+ <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>,
+ <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>,
+ <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7791-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7791",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7791",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7791-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7791",
+ "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7791", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7791",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
- msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 000>;
- dmas = <&dmac0 0x51>, <&dmac0 0x52>,
- <&dmac1 0x51>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
- msiof1: spi@e6e10000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e10000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x55>, <&dmac0 0x56>,
- <&dmac1 0x55>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7791",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
- msiof2: spi@e6e00000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 205>;
- dmas = <&dmac0 0x41>, <&dmac0 0x42>,
- <&dmac1 0x41>, <&dmac1 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 205>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
- xhci: usb@ee000000 {
- compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- phys = <&usb2 1>;
- phy-names = "usb";
- status = "disabled";
- };
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7791",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7791",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
};
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7791",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
};
- };
- pci1: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x10800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7791",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
};
- usb@2,0 {
- reg = <0x11000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7791",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x2000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
};
- };
- pciec: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- status = "disabled";
- };
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7791",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x2000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 814>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 814>;
+ status = "disabled";
+ };
- ipmmu_sy0: mmu@e6280000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7791",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- ipmmu_sy1: mmu@e6290000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
- ipmmu_ds: mmu@e6740000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7791",
+ "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
- ipmmu_mp: mmu@ec680000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
- ipmmu_mx: mmu@fe951000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
- ipmmu_rt: mmu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xffc80000 0 0x1000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
+ };
- ipmmu_gp: mmu@e62a0000 {
- compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
- reg = <0 0xe62a0000 0 0x1000>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ jpu: jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7791",
+ "renesas,rcar-gen2-jpu";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 106>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 106>;
+ };
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A7791_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6", "src.5",
- "src.4", "src.3", "src.2", "src.1", "src.0",
- "ctu.0", "ctu.1",
- "mix.0", "mix.1",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7791";
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfeb90000 0 0x1c>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 726>;
+ clock-names = "du.0", "du.1", "lvds.0";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
};
};
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
};
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7791-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ status = "disabled";
};
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7791-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ status = "disabled";
};
+ };
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
};
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
+ cooling-maps {
};
};
};
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
};
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 3be15a158bad..268987ff0201 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -101,63 +101,6 @@
#size-cells = <2>;
ranges;
- apmu@e6152000 {
- compatible = "renesas,r8a7792-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- irqc: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7792", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7792-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7792-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7792";
- reg = <0 0xe6060000 0 0x144>;
- };
-
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7792",
"renesas,rcar-gen2-gpio";
@@ -338,6 +281,155 @@
resets = <&cpg 913>;
};
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7792";
+ reg = <0 0xe6060000 0 0x144>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7792-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7792-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7792-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7792-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
+
+ /* I2C doesn't need pinmux */
+ i2c0: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e6520000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e6528000 {
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
@@ -404,6 +496,35 @@
dma-channels = <15>;
};
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7792",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7792", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
@@ -500,162 +621,6 @@
status = "disabled";
};
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
- };
- };
-
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7792",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- clocks = <&cpg CPG_MOD 314>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- jpu: jpeg-codec@fe980000 {
- compatible = "renesas,jpu-r8a7792",
- "renesas,rcar-gen2-jpu";
- reg = <0 0xfe980000 0 0x10300>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 106>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 106>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7792",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- /* I2C doesn't need pinmux */
- i2c0: i2c@e6508000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e6520000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@e6528000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7792", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7792",
"renesas,rcar-gen2-msiof";
@@ -688,34 +653,6 @@
status = "disabled";
};
- du: display@feb00000 {
- compatible = "renesas,du-r8a7792";
- reg = <0 0xfeb00000 0 0x40000>;
- reg-names = "du";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb0: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_rgb1: endpoint {
- };
- };
- };
- };
-
can0: can@e6e80000 {
compatible = "renesas,can-r8a7792",
"renesas,rcar-gen2-can";
@@ -808,6 +745,36 @@
status = "disabled";
};
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7792",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ clocks = <&cpg CPG_MOD 314>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
@@ -835,14 +802,47 @@
resets = <&cpg 127>;
};
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7792-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>;
- clock-names = "extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
+ jpu: jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7792",
+ "renesas,rcar-gen2-jpu";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 106>;
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 106>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7792";
+ reg = <0 0xfeb00000 0 0x40000>;
+ reg-names = "du";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb0: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_rgb1: endpoint {
+ };
+ };
+ };
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
};
};
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 51b3ffac8efa..9ed6961f2d9a 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -48,6 +48,10 @@
aliases {
serial0 = &scif0;
serial1 = &scif1;
+ i2c9 = &gpioi2c2;
+ i2c10 = &gpioi2c4;
+ i2c11 = &i2chdmi;
+ i2c12 = &i2cexio4;
};
chosen {
@@ -296,6 +300,146 @@
#clock-cells = <0>;
clock-frequency = <148500000>;
};
+
+ gpioi2c2: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ gpioi2c4: i2c-10 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * A fallback to GPIO is provided for I2C2.
+ */
+ i2chdmi: i2c-11 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c2>, <&gpioi2c2>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180cp";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7180_in: endpoint {
+ remote-endpoint = <&composite_con_in>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ adv7180_out: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ hdmi-in@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ default-input = <0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7612_in: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7612_out: endpoint {
+ remote-endpoint = <&vin0ep2>;
+ };
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "renesas,r1ex24002", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+ };
+
+ /*
+ * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
+ * A fallback to GPIO is provided.
+ */
+ i2cexio4: i2c-12 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c4>, <&gpioi2c4>;
+ i2c-bus-name = "i2c-exio4";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&du {
@@ -334,6 +478,11 @@
function = "i2c2";
};
+ i2c4_pins: i2c4 {
+ groups = "i2c4_c";
+ function = "i2c4";
+ };
+
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
@@ -544,107 +693,11 @@
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-hdmi";
status = "okay";
clock-frequency = <100000>;
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180cp";
- reg = <0x20>;
- remote = <&vin1>;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7180_in: endpoint {
- remote-endpoint = <&composite_con_in>;
- };
- };
-
- port@3 {
- reg = <3>;
- adv7180_out: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep>;
- };
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-in@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- interrupt-parent = <&gpio4>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- default-input = <0>;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- adv7612_out: endpoint {
- remote-endpoint = <&vin0ep2>;
- };
- };
- };
- };
-
- eeprom@50 {
- compatible = "renesas,r1ex24002", "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
};
&i2c6 {
@@ -668,6 +721,11 @@
};
};
+&i2c4 {
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "i2c-exio4";
+};
+
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 039b22517526..f9c5a557107d 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -15,7 +15,6 @@
/ {
compatible = "renesas,r8a7793";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -32,6 +31,35 @@
spi0 = &qspi;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -74,1261 +102,1295 @@
};
};
- apmu@e6152000 {
- compatible = "renesas,r8a7793-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
- thermal-sensors = <&thermal>;
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
};
- };
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7793",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
+ };
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7793";
+ reg = <0 0xe6060000 0 0x250>;
+ };
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
+ /* Special CPG clocks */
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7793-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 904>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 904>;
- };
+ apmu@e6152000 {
+ compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
- thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7793",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7793-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7793-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7793", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7793",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7793", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- /* The memory map in the User's Manual maps the cores to bus numbers */
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xffc80000 0 0x1000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7793",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
- i2c4: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
- i2c5: i2c@e6528000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
+ /* The memory map in the User's Manual maps the cores to
+ * bus numbers
+ */
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- i2c6: i2c@e60b0000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- i2c7: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- i2c8: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7793";
- reg = <0 0xe6060000 0 0x250>;
- };
+ i2c4: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7793",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7793",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
- sdhi1: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7793",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
+ i2c6: i2c@e60b0000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
- sdhi2: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7793",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
+ i2c7: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
+ i2c8: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7793",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7793",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7793",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- scifa3: serial@e6c70000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c70000 0 64>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1106>;
- clock-names = "fck";
- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
- <&dmac1 0x1b>, <&dmac1 0x1c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1106>;
- status = "disabled";
- };
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
- scifa4: serial@e6c78000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c78000 0 64>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1107>;
- clock-names = "fck";
- dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
- <&dmac1 0x1f>, <&dmac1 0x20>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1107>;
- status = "disabled";
- };
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
- scifa5: serial@e6c80000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c80000 0 64>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1108>;
- clock-names = "fck";
- dmas = <&dmac0 0x23>, <&dmac0 0x24>,
- <&dmac1 0x23>, <&dmac1 0x24>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1108>;
- status = "disabled";
- };
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7793",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1106>;
+ status = "disabled";
+ };
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7793",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1107>;
+ status = "disabled";
+ };
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7793",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7793",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1108>;
+ status = "disabled";
+ };
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7793",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7793",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7793",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7793",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
- scif4: serial@e6ee0000 {
- compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ee0000 0 64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
- <&dmac1 0xfb>, <&dmac1 0xfc>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7793",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
- scif5: serial@e6ee8000 {
- compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ee8000 0 64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
- <&dmac1 0xfd>, <&dmac1 0xfe>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7793",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7793",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7793",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7793",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7793",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
- hscif2: serial@e62d0000 {
- compatible = "renesas,hscif-r8a7793",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62d0000 0 96>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
- <&dmac1 0x3b>, <&dmac1 0x3c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7793",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7793",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7793",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7793",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
};
- };
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7793",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7793",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7793",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7793",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7793",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7793", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7793",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
- du: display@feb00000 {
- compatible = "renesas,du-r8a7793";
- reg = <0 0xfeb00000 0 0x40000>,
- <0 0xfeb90000 0 0x1c>;
- reg-names = "du", "lvds.0";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 726>;
- clock-names = "du.0", "du.1", "lvds.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7793",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7793_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
};
};
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>,
+ <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>,
+ <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>,
+ <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>,
+ <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>,
+ <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+ <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+ <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>,
+ <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>,
+ <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>,
+ <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
};
};
};
- };
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7793",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7793",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7793",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
- /* Special CPG clocks */
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7793-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7793",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7793-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7793",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7793",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7793-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7793",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- ipmmu_sy0: mmu@e6280000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
- ipmmu_sy1: mmu@e6290000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7793";
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfeb90000 0 0x1c>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 726>;
+ clock-names = "du.0", "du.1", "lvds.0";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ };
+ };
- ipmmu_ds: mmu@e6740000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
- ipmmu_mp: mmu@ec680000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7793-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ status = "disabled";
+ };
- ipmmu_mx: mmu@fe951000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7793-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ status = "disabled";
+ };
};
- ipmmu_rt: mmu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xffc80000 0 0x1000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
- ipmmu_gp: mmu@e62a0000 {
- compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
- reg = <0 0xe62a0000 0 0x1000>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ thermal-sensors = <&thermal>;
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A7793_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6", "src.5",
- "src.4", "src.3", "src.2", "src.1", "src.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
};
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
+ cooling-maps {
};
};
+ };
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
};
};
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 60c6515c4996..26a883484ea8 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -18,7 +18,9 @@
aliases {
serial0 = &scif2;
+ i2c9 = &gpioi2c1;
i2c10 = &gpioi2c4;
+ i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
};
@@ -138,17 +140,50 @@
clock-frequency = <148500000>;
};
+ gpioi2c1: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ };
+
gpioi2c4: i2c-10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
- sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
/*
+ * A fallback to GPIO is provided for I2C1.
+ */
+ i2chdmi: i2c-11 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c1>, <&gpioi2c1>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin0>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+ };
+
+ /*
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
* A fallback to GPIO is provided.
*/
@@ -324,23 +359,9 @@
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-hdmi";
- status = "okay";
clock-frequency = <400000>;
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
- remote = <&vin0>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
};
&i2c4 {
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index edfad0e5ac53..351cb3b3d966 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -24,6 +24,7 @@
/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "SILK";
@@ -31,6 +32,8 @@
aliases {
serial0 = &scif2;
+ i2c9 = &gpioi2c1;
+ i2c10 = &i2chdmi;
};
chosen {
@@ -43,6 +46,60 @@
reg = <0 0x40000000 0 0x40000000>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-3 {
+ gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-6 {
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_6>;
+ label = "SW6";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "SW12-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "SW12-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "SW12-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-d {
+ gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_D>;
+ label = "SW12-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
d3_3v: regulator-d3-3v {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
@@ -153,6 +210,84 @@
clocks = <&x9_clk>;
};
};
+
+ gpioi2c1: i2c-9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+ };
+
+ /*
+ * A fallback to GPIO is provided for I2C1.
+ */
+ i2chdmi: i2c-10 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&i2c1>, <&gpioi2c1>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin0>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_rgb0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "renesas,r1ex24002", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+ };
};
&extal_clk {
@@ -268,61 +403,9 @@
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-hdmi";
- status = "okay";
clock-frequency = <400000>;
-
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
- remote = <&vin0>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio5>;
- interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb0>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
};
&mmcif0 {
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 106b4e1649ff..d588efa6aeaa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -16,7 +16,6 @@
/ {
compatible = "renesas,r8a7794";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -34,6 +33,35 @@
vin1 = &vin1;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clka: audio_clka {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clkb: audio_clkb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clkc: audio_clkc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -67,1290 +95,1313 @@
};
};
- apmu@e6151000 {
- compatible = "renesas,r8a7794-apmu", "renesas,apmu";
- reg = <0 0xe6151000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 28>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 28>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7794",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7794";
+ reg = <0 0xe6060000 0 0x11c>;
+ };
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7794", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7794-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
- pfc: pin-controller@e6060000 {
- compatible = "renesas,pfc-r8a7794";
- reg = <0 0xe6060000 0 0x11c>;
- };
+ apmu@e6151000 {
+ compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7794-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7794-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
- "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
+ irqc0: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7794", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
+ ipmmu_sy0: mmu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7794",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
+ ipmmu_sy1: mmu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7794",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
+ ipmmu_ds: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7794",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- scifa3: serial@e6c70000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c70000 0 64>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1106>;
- clock-names = "fck";
- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
- <&dmac1 0x1b>, <&dmac1 0x1c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1106>;
- status = "disabled";
- };
+ ipmmu_mp: mmu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7794",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- scifa4: serial@e6c78000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c78000 0 64>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1107>;
- clock-names = "fck";
- dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
- <&dmac1 0x1f>, <&dmac1 0x20>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1107>;
- status = "disabled";
- };
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7794",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- scifa5: serial@e6c80000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c80000 0 64>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1108>;
- clock-names = "fck";
- dmas = <&dmac0 0x23>, <&dmac0 0x24>,
- <&dmac1 0x23>, <&dmac1 0x24>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1108>;
- status = "disabled";
- };
+ ipmmu_gp: mmu@e62a0000 {
+ compatible = "renesas,ipmmu-r8a7794",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe62a0000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7794",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7794",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7794",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x10>;
+ };
+ };
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
+ /* The memory map in the User's Manual maps the cores to
+ * bus numbers
+ */
+ i2c0: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a7794",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
+ i2c1: i2c@e6518000 {
+ compatible = "renesas,i2c-r8a7794",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
+ i2c2: i2c@e6530000 {
+ compatible = "renesas,i2c-r8a7794",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
+ i2c3: i2c@e6540000 {
+ compatible = "renesas,i2c-r8a7794",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scif4: serial@e6ee0000 {
- compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ee0000 0 64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
- <&dmac1 0xfb>, <&dmac1 0xfc>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
+ i2c4: i2c@e6520000 {
+ compatible = "renesas,i2c-r8a7794",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6520000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- scif5: serial@e6ee8000 {
- compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6ee8000 0 64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
- <&dmac1 0xfd>, <&dmac1 0xfe>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
+ i2c5: i2c@e6528000 {
+ compatible = "renesas,i2c-r8a7794",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6528000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 925>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 925>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7794",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
+ i2c6: i2c@e6500000 {
+ compatible = "renesas,iic-r8a7794",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7794",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
+ i2c7: i2c@e6510000 {
+ compatible = "renesas,iic-r8a7794",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- hscif2: serial@e62d0000 {
- compatible = "renesas,hscif-r8a7794",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62d0000 0 96>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
- <&dmac1 0x3b>, <&dmac1 0x3c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7794",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- };
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7794",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7794",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
};
- };
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7794",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7794",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7794",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7794",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- /* The memory map in the User's Manual maps the cores to bus numbers */
- i2c0: i2c@e6508000 {
- compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- i2c1: i2c@e6518000 {
- compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
- i2c2: i2c@e6530000 {
- compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
- i2c3: i2c@e6540000 {
- compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 64>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
- i2c4: i2c@e6520000 {
- compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 64>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1106>;
+ status = "disabled";
+ };
- i2c5: i2c@e6528000 {
- compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 64>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1107>;
+ status = "disabled";
+ };
- i2c6: i2c@e6500000 {
- compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7794",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 64>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1108>;
+ status = "disabled";
+ };
- i2c7: i2c@e6510000 {
- compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7794",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- };
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7794",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7794",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7794",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
- sdhi1: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7794",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7794",
+ "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
- sdhi2: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7794",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7794",
+ "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7794", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7794",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7794",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7794",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 64>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7794",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 64>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
};
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7794",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
};
- };
- pci1: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x10800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7794",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
};
- usb@2,0 {
- reg = <0x11000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7794",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 96>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
};
- };
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7794",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
- usbphy: usb-phy@e6590100 {
- compatible = "renesas,usb-phy-r8a7794",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7794",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
- usb0: usb-channel@0 {
- reg = <0>;
- #phy-cells = <1>;
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7794",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
};
- usb2: usb-channel@2 {
- reg = <2>;
- #phy-cells = <1>;
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7794",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
};
- };
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7794",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+ <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+ <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+ <&cpg CPG_CORE R8A7794_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.6", "src.5", "src.4", "src.3",
+ "src.2", "src.1",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma0 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma0 0xbe>;
+ dma-names = "tx";
+ };
+ };
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
- du: display@feb00000 {
- compatible = "renesas,du-r8a7794";
- reg = <0 0xfeb00000 0 0x40000>;
- reg-names = "du";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
- port@0 {
- reg = <0>;
- du_out_rgb0: endpoint {
+ rcar_sound,src {
+ src-0 {
+ status = "disabled";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma0 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma0 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma0 0xb4>;
+ dma-names = "rx", "tx";
};
};
- port@1 {
- reg = <1>;
- du_out_rgb1: endpoint {
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma0 0x02>,
+ <&audma0 0x15>, <&audma0 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma0 0x04>,
+ <&audma0 0x49>, <&audma0 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma0 0x06>,
+ <&audma0 0x63>, <&audma0 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma0 0x08>,
+ <&audma0 0x6f>, <&audma0 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma0 0x0a>,
+ <&audma0 0x71>, <&audma0 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+ <&audma0 0x73>, <&audma0 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+ <&audma0 0x75>, <&audma0 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma0 0x10>,
+ <&audma0 0x79>, <&audma0 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma0 0x12>,
+ <&audma0 0x7b>, <&audma0 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma0 0x14>,
+ <&audma0 0x7d>, <&audma0 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
};
};
};
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7794",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3", "ch4",
+ "ch5", "ch6", "ch7", "ch8", "ch9",
+ "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7794",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
- /*
- * The external audio clocks are configured as 0 Hz fixed
- * frequency clocks by default. Boards that provide audio
- * clocks should override them.
- */
- audio_clka: audio_clka {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clkb: audio_clkb {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clkc: audio_clkc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7794-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
+ pci1: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7794",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xff00 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7794-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
+ usb@2,0 {
+ reg = <0x11000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7794",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7794-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
+ sdhi1: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7794",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
- ipmmu_sy0: mmu@e6280000 {
- compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ sdhi2: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7794",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
- ipmmu_sy1: mmu@e6290000 {
- compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7794",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
- ipmmu_ds: mmu@e6740000 {
- compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7794",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- ipmmu_mp: mmu@ec680000 {
- compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
- ipmmu_mx: mmu@fe951000 {
- compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
- ipmmu_gp: mmu@e62a0000 {
- compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
- reg = <0 0xe62a0000 0 0x1000>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7794",
- "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
- <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
- <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
- <&cpg CPG_CORE R8A7794_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
- "src.6", "src.5", "src.4", "src.3", "src.2",
- "src.1",
- "ctu.0", "ctu.1",
- "mix.0", "mix.1",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
- dma-names = "tx";
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7794";
+ reg = <0 0xfeb00000 0 0x40000>;
+ reg-names = "du";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb0: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_rgb1: endpoint {
+ };
+ };
};
};
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
};
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7794-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ status = "disabled";
};
- rcar_sound,src {
- src-0 {
- status = "disabled";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma0 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma0 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma0 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma0 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma0 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma0 0xb4>;
- dma-names = "rx", "tx";
- };
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7794-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ status = "disabled";
};
+ };
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma0 0x02>,
- <&audma0 0x15>, <&audma0 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma0 0x04>,
- <&audma0 0x49>, <&audma0 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma0 0x06>,
- <&audma0 0x63>, <&audma0 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma0 0x08>,
- <&audma0 0x6f>, <&audma0 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma0 0x0a>,
- <&audma0 0x71>, <&audma0 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma0 0x0c>,
- <&audma0 0x73>, <&audma0 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma0 0x0e>,
- <&audma0 0x75>, <&audma0 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma0 0x10>,
- <&audma0 0x79>, <&audma0 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma0 0x12>,
- <&audma0 0x7b>, <&audma0 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma0 0x14>,
- <&audma0 0x7d>, <&audma0 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
};
};
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 341deaf62ff6..df1e47858675 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -233,7 +233,7 @@
};
grf: syscon@11000000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index 1241cbcfc16f..985743fa134c 100644
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -265,7 +265,11 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vdd_io_sd>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 5eae4776ffde..f13bcb1cd3d9 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -336,11 +336,10 @@
regulator-name = "vdd_io_sd";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
+ regulator-off-in-suspend;
};
};
};
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index b9c471fcbd42..51f36a1b698e 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -280,6 +280,10 @@
};
};
+&saradc {
+ vref-supply = <&vcc_18>;
+};
+
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index 0e084b8a86ac..8ccc89dbdfaf 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -39,6 +39,7 @@
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "rk3288-rock2-som.dtsi"
/ {
@@ -49,6 +50,32 @@
stdout-path = "serial2:115200n8";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+ wakeup-source;
+ };
+ };
+
gpio-leds {
compatible = "gpio-leds";
@@ -220,6 +247,12 @@
};
};
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -261,6 +294,10 @@
};
};
+&saradc {
+ status = "okay";
+};
+
&spdif {
status = "okay";
};
@@ -284,3 +321,7 @@
&usb_host1 {
status = "okay";
};
+
+&usb_otg {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index d752a315f884..be487111d025 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -92,7 +92,6 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
- backlight-boot-off;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index 9842a006e823..14c896bfc639 100644
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -155,6 +155,17 @@
cpu0-supply = <&vdd_cpu>;
};
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ status = "okay";
+};
+
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6102e4e7f35c..354aff45c1af 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -927,6 +927,7 @@
i2s: i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1176,6 +1177,7 @@
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>;
+ #sound-dai-cells = <0>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index b9c05b57735e..eae5e1ee9cd8 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -861,24 +861,24 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
- <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */
- AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */
+ <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with PWMFI2, ISI_D8 */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */
- AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */
+ <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with TWD0, ISI_VSYNC */
+ AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */
};
};
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
- AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
+ <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
@@ -891,8 +891,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
- AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
+ <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
@@ -905,8 +905,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
- AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
+ <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with A25 */
+ AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts NCS0 */
};
pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
@@ -919,8 +919,8 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
- AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
+ <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with A18 */
+ AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with A19 */
};
pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index c8b8449fdc3e..15d5c46013a4 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -38,7 +38,7 @@
status = "okay";
24c256@50 {
- compatible = "24c256";
+ compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 186377d41c91..f599f8a5f664 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -23,16 +23,16 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
- <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
- AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+ <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with PWMFI2, ISI_D8 */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
- AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+ <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* conflicts with TWD0, ISI_VSYNC */
+ AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */
};
};
};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 373b3621b536..0cf9beddd556 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1379,7 +1379,7 @@
pinctrl@fc06a000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+ compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
ranges = <0xfc068000 0xfc068000 0x100
0xfc06a000 0xfc06a000 0x4000>;
/* WARNING: revisit as pin spec has changed */
@@ -1926,8 +1926,8 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
- <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
- AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
+ <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
+ AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
>;
};
};
@@ -1935,8 +1935,8 @@
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */
- AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */
+ <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
+ AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
>;
};
};
@@ -1944,8 +1944,8 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
- AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
+ <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
+ AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
>;
};
pinctrl_usart0_rts: usart0_rts-0 {
@@ -1959,8 +1959,8 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
- AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
+ <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
+ AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
>;
};
pinctrl_usart1_rts: usart1_rts-0 {
@@ -1974,8 +1974,8 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
- AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
+ <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
+ AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
>;
};
pinctrl_usart2_rts: usart2_rts-0 {
@@ -1989,8 +1989,8 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
- AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
+ <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
+ AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
>;
};
};
@@ -1998,8 +1998,8 @@
usart4 {
pinctrl_usart4: usart4-0 {
atmel,pins =
- <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
- AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
+ <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
+ AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
>;
};
pinctrl_usart4_rts: usart4_rts-0 {
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
deleted file mode 100644
index dbdda36179ee..000000000000
--- a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Timings and Geometry for Samsung K3PE0E000B memory part
- */
-
-/ {
- samsung_K3PE0E000B: lpddr2 {
- compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
- density = <4096>;
- io-width = <32>;
-
- tRPab-min-tck = <3>;
- tRCD-min-tck = <3>;
- tWR-min-tck = <3>;
- tRASmin-min-tck = <3>;
- tRRD-min-tck = <2>;
- tWTR-min-tck = <2>;
- tXP-min-tck = <2>;
- tRTP-min-tck = <2>;
- tCKE-min-tck = <3>;
- tCKESR-min-tck = <3>;
- tFAW-min-tck = <8>;
-
- timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
- compatible = "jedec,lpddr2-timings";
- min-freq = <10000000>;
- max-freq = <533333333>;
- tRPab = <21000>;
- tRCD = <18000>;
- tWR = <15000>;
- tRAS-min = <42000>;
- tRRD = <10000>;
- tWTR = <7500>;
- tXP = <7500>;
- tRTP = <7500>;
- tCKESR = <15000>;
- tDQSCK-max = <5500>;
- tFAW = <50000>;
- tZQCS = <90000>;
- tZQCL = <360000>;
- tZQinit = <1000000>;
- tRAS-max-ns = <70000>;
- tDQSCK-max-derated = <6000>;
- };
-
- timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
- compatible = "jedec,lpddr2-timings";
- min-freq = <10000000>;
- max-freq = <266666666>;
- tRPab = <21000>;
- tRCD = <18000>;
- tWR = <15000>;
- tRAS-min = <42000>;
- tRRD = <10000>;
- tWTR = <7500>;
- tXP = <7500>;
- tRTP = <7500>;
- tCKESR = <15000>;
- tDQSCK-max = <5500>;
- tFAW = <50000>;
- tZQCS = <90000>;
- tZQCL = <360000>;
- tZQinit = <1000000>;
- tRAS-max-ns = <70000>;
- tDQSCK-max-derated = <6000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index c42ca7022e8c..486d4e7433ed 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -831,7 +831,7 @@
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfffec600 0x100>;
- interrupts = <1 13 0xf04>;
+ interrupts = <1 13 0xf01>;
clocks = <&mpu_periph_clk>;
};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
index 040a164ba148..5822fd2085db 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -20,7 +20,6 @@
&mmc {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 8c037297296c..e59461f5416e 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -30,7 +30,6 @@
};
mmc0: dwmmc0@ff704000 {
- num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index a05e3df23103..68ced67f8bfb 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -31,7 +31,6 @@
};
mmc0: dwmmc0@ff704000 {
- num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index dfe2193cd4d5..547c38632c68 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -42,7 +42,6 @@
};
dwmmc0@ff704000 {
- num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index c8ad905d0309..62ce1cecbb1f 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -14,17 +14,17 @@
compatible = "st,stih407-b2120", "st,stih407";
chosen {
- bootargs = "console=ttyAS0,115200 clk_ignore_unused";
- linux,stdout-path = &sbc_serial0;
+ bootargs = "clk_ignore_unused";
+ stdout-path = &sbc_serial0;
};
- memory {
+ memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
aliases {
- ttyAS0 = &sbc_serial0;
+ serial0 = &sbc_serial0;
ethernet0 = &ethernet0;
};
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index d0a24d9e517a..ea7833489832 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -7,33 +7,27 @@
*/
#include <dt-bindings/clock/stih407-clks.h>
/ {
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
* A9 PLL.
*/
clockgen-a9@92b0000 {
@@ -62,32 +56,19 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
- };
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
- clock-div = <2>;
- clock-mult = <1>;
- };
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
- /*
- * Bootloader initialized system infrastructure clock for
- * serial devices.
- */
- clk_ext2f_a9: clockgen-c0@13 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- clock-output-names = "clk-s-icn-reg-0";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
clockgen-a@90ff000 {
@@ -204,6 +185,21 @@
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -254,13 +250,7 @@
"clk-s-d2-fs0-ch3";
};
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen-d2@x9106000 {
+ clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index cf3756976c39..f7362c31de29 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -92,7 +92,7 @@
clocks = <&arm_periph_clk>;
};
- l2: cache-controller {
+ l2: cache-controller@8762000 {
compatible = "arm,pl310-cache";
reg = <0x08762000 0x1000>;
arm,data-latency = <3 3 3>;
@@ -125,24 +125,28 @@
ranges;
compatible = "simple-bus";
- restart {
+ restart: restart-controller@0 {
compatible = "st,stih407-restart";
+ reg = <0 0>;
st,syscfg = <&syscfg_sbc_reg>;
status = "okay";
};
- powerdown: powerdown-controller {
+ powerdown: powerdown-controller@0 {
compatible = "st,stih407-powerdown";
+ reg = <0 0>;
#reset-cells = <1>;
};
- softreset: softreset-controller {
+ softreset: softreset-controller@0 {
compatible = "st,stih407-softreset";
+ reg = <0 0>;
#reset-cells = <1>;
};
- picophyreset: picophyreset-controller {
+ picophyreset: picophyreset-controller@0 {
compatible = "st,stih407-picophyreset";
+ reg = <0 0>;
#reset-cells = <1>;
};
@@ -174,6 +178,13 @@
syscfg_core: core-syscfg@92b0000 {
compatible = "st,stih407-core-syscfg", "syscon";
reg = <0x92b0000 0x1000>;
+
+ sti_sasg_codec: sti-sasg-codec {
+ compatible = "st,stih407-sas-codec";
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ st,syscfg = <&syscfg_core>;
+ };
};
syscfg_lpm: lpm-syscfg@94b5100 {
@@ -181,8 +192,9 @@
reg = <0x94b5100 0x1000>;
};
- irq-syscfg {
+ irq-syscfg@0 {
compatible = "st,stih407-irq-syscfg";
+ reg = <0 0>;
st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
@@ -380,8 +392,9 @@
status = "disabled";
};
- usb2_picophy0: phy1 {
+ usb2_picophy0: phy1@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0x100 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -389,12 +402,13 @@
reset-names = "global", "port";
};
- miphy28lp_phy: miphy28lp@9b22000 {
+ miphy28lp_phy: miphy28lp@0 {
compatible = "st,miphy28lp-phy";
st,syscfg = <&syscfg_core>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ reg = <0 0>;
phy_port0: port@9b22000 {
reg = <0x9b22000 0xff>,
@@ -805,6 +819,7 @@
st231_gp0: st231-gp0@0 {
compatible = "st,st231-rproc";
+ reg = <0 0>;
memory-region = <&gp0_reserved>;
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
reset-names = "sw_reset";
@@ -818,6 +833,7 @@
st231_delta: st231-delta@0 {
compatible = "st,st231-rproc";
+ reg = <0 0>;
memory-region = <&delta_reserved>;
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
reset-names = "sw_reset";
@@ -885,13 +901,6 @@
status = "disabled";
};
- sti_sasg_codec: sti-sasg-codec {
- compatible = "st,stih407-sas-codec";
- #sound-dai-cells = <1>;
- status = "disabled";
- st,syscfg = <&syscfg_core>;
- };
-
sti_uni_player0: sti-uni-player@8d80000 {
compatible = "st,stih407-uni-player-hdmi";
#sound-dai-cells = <0>;
@@ -980,8 +989,9 @@
status = "disabled";
};
- delta0 {
+ delta0@0 {
compatible = "st,st-delta";
+ reg = <0 0>;
clock-names = "delta",
"delta-st231",
"delta-flash-promip";
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index a29090077fdf..53c6888d1fc0 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -45,7 +45,7 @@
};
soc {
- pin-controller-sbc {
+ pin-controller-sbc@961f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-sbc-pinctrl";
@@ -369,7 +369,7 @@
};
};
- pin-controller-front0 {
+ pin-controller-front0@920f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
@@ -929,7 +929,7 @@
};
};
- pin-controller-front1 {
+ pin-controller-front1@921f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
@@ -962,7 +962,7 @@
};
};
- pin-controller-rear {
+ pin-controller-rear@922f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-rear-pinctrl";
@@ -1157,7 +1157,7 @@
};
};
- pin-controller-flash {
+ pin-controller-flash@923f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-flash-pinctrl";
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 11fdecd9312e..57efc87dec2b 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -11,11 +11,11 @@
#include <dt-bindings/gpio/gpio.h>
/ {
soc {
- sti-display-subsystem {
+ sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
-
+ reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
@@ -107,6 +107,7 @@
compatible = "st,stih407-hdmi";
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
interrupt-names = "irq";
clock-names = "pix",
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 9830be577433..2a5a9802a5ec 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -14,17 +14,17 @@
compatible = "st,stih410-b2120", "st,stih410";
chosen {
- bootargs = "console=ttyAS0,115200 clk_ignore_unused";
- linux,stdout-path = &sbc_serial0;
+ bootargs = "clk_ignore_unused";
+ stdout-path = &sbc_serial0;
};
- memory {
+ memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
aliases {
- ttyAS0 = &sbc_serial0;
+ serial0 = &sbc_serial0;
ethernet0 = &ethernet0;
};
@@ -37,11 +37,11 @@
sd-uhs-ddr50;
};
- usb2_picophy1: phy2 {
+ usb2_picophy1: phy2@0 {
status = "okay";
};
- usb2_picophy2: phy3 {
+ usb2_picophy2: phy3@0 {
status = "okay";
};
@@ -61,7 +61,7 @@
status = "okay";
};
- sti-display-subsystem {
+ sti-display-subsystem@0 {
sti-hda@8d02000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index c663b70c43a7..155caa8c002a 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -15,50 +15,68 @@
compatible = "st,stih410-b2260", "st,stih410";
chosen {
- bootargs = "console=ttyAS1,115200 clk_ignore_unused";
- linux,stdout-path = &uart1;
+ bootargs = "clk_ignore_unused";
+ stdout-path = &uart1;
};
- memory {
+ memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
aliases {
- ttyAS1 = &uart1;
+ serial1 = &uart1;
ethernet0 = &ethernet0;
};
- soc {
+ leds {
+ compatible = "gpio-leds";
+ user_green_1 {
+ label = "User_green_1";
+ gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
- leds {
- compatible = "gpio-leds";
- user_green_1 {
- label = "User_green_1";
- gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
+ user_green_2 {
+ label = "User_green_2";
+ gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
- user_green_2 {
- label = "User_green_2";
- gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
+ user_green_3 {
+ label = "User_green_3";
+ gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ user_green_4 {
+ label = "User_green_4";
+ gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
- user_green_3 {
- label = "User_green_3";
- gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
+ sound: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "STI-B2260";
+ status = "okay";
+
+ simple-audio-card,dai-link0 {
+ /* DAC */
+ format = "i2s";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player0>;
};
- user_green_4 {
- label = "User_green_4";
- gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
+ codec {
+ sound-dai = <&sti_hdmi>;
};
};
+ };
+ soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
label = "LS-UART0";
@@ -128,11 +146,11 @@
status = "okay";
};
- usb2_picophy1: phy2 {
+ usb2_picophy1: phy2@0 {
status = "okay";
};
- usb2_picophy2: phy3 {
+ usb2_picophy2: phy3@0 {
status = "okay";
};
@@ -182,26 +200,7 @@
status = "okay";
};
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "STI-B2260";
- status = "okay";
-
- simple-audio-card,dai-link@0 {
- /* DAC */
- format = "i2s";
- mclk-fs = <128>;
- cpu {
- sound-dai = <&sti_uni_player0>;
- };
-
- codec {
- sound-dai = <&sti_hdmi>;
- };
- };
- };
-
- miphy28lp_phy: miphy28lp@9b22000 {
+ miphy28lp_phy: miphy28lp@0 {
phy_port1: port@9b2a000 {
st,osc-force-ext;
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index fde5df17f575..5f11d09cb030 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -7,6 +7,22 @@
*/
#include <dt-bindings/clock/stih410-clks.h>
/ {
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
@@ -15,27 +31,6 @@
compatible = "st,stih410-clk", "simple-bus";
/*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- clock-output-names = "CLK_SYSIN";
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
* A9 PLL.
*/
clockgen-a9@92b0000 {
@@ -64,32 +59,16 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
- * Bootloader initialized system infrastructure clock for
- * serial devices.
- */
- clk_ext2f_a9: clockgen-c0@13 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- clock-output-names = "clk-s-icn-reg-0";
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
clockgen-a@90ff000 {
@@ -214,6 +193,21 @@
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -266,13 +260,7 @@
"clk-s-d2-fs0-ch3";
};
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen-d2@x9106000 {
+ clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
index b3e9dfc81c07..5ae1fd66c0b8 100644
--- a/arch/arm/boot/dts/stih410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -10,7 +10,7 @@
/ {
soc {
- pin-controller-rear {
+ pin-controller-rear@922f080 {
usb0 {
pinctrl_usb0: usb2-0 {
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 68b5ff91d6a7..3313005ee15c 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -16,8 +16,9 @@
};
soc {
- usb2_picophy1: phy2 {
+ usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -27,8 +28,9 @@
status = "disabled";
};
- usb2_picophy2: phy3 {
+ usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -102,11 +104,12 @@
status = "disabled";
};
- sti-display-subsystem {
+ sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
+ reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
@@ -198,6 +201,7 @@
compatible = "st,stih407-hdmi";
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
interrupt-names = "irq";
clock-names = "pix",
@@ -235,7 +239,7 @@
<&clk_s_d2_quadfs 1>;
};
- sti-hqvdp@9c000000 {
+ sti-hqvdp@9c00000 {
compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main";
@@ -273,7 +277,7 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
- delta0 {
+ delta0@0 {
compatible = "st,st-delta";
clock-names = "delta",
"delta-st231",
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
index 4e6d915c85ff..cd0d719e31b7 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -14,38 +14,38 @@
compatible = "st,stih418-b2199", "st,stih418";
chosen {
- bootargs = "console=ttyAS0,115200 clk_ignore_unused";
- linux,stdout-path = &sbc_serial0;
+ bootargs = "clk_ignore_unused";
+ stdout-path = &sbc_serial0;
};
- memory {
+ memory@40000000 {
device_type = "memory";
reg = <0x40000000 0xc0000000>;
};
aliases {
- ttyAS0 = &sbc_serial0;
+ serial0 = &sbc_serial0;
ethernet0 = &ethernet0;
};
+ leds {
+ compatible = "gpio-leds";
+ red {
+ label = "Front Panel LED";
+ gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ green {
+ gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
- leds {
- compatible = "gpio-leds";
- red {
- label = "Front Panel LED";
- gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- green {
- gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
i2c@9842000 {
status = "okay";
};
@@ -88,7 +88,7 @@
non-removable;
};
- miphy28lp_phy: miphy28lp@9b22000 {
+ miphy28lp_phy: miphy28lp@0 {
phy_port0: port@9b22000 {
st,osc-rdy;
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 9a157c1a99b1..13fb8db52fc1 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -7,6 +7,22 @@
*/
#include <dt-bindings/clock/stih418-clks.h>
/ {
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
@@ -15,27 +31,6 @@
compatible = "st,stih418-clk", "simple-bus";
/*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- clock-output-names = "CLK_SYSIN";
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
* A9 PLL.
*/
clockgen-a9@92b0000 {
@@ -64,32 +59,17 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
- * Bootloader initialized system infrastructure clock for
- * serial devices.
- */
- clk_ext2f_a9: clockgen-c0@13 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- clock-output-names = "clk-s-icn-reg-0";
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
clockgen-a@90ff000 {
@@ -207,6 +187,21 @@
"clk-proc-mixer",
"clk-proc-sc",
"clk-avsp-hevc";
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -259,13 +254,7 @@
"clk-s-d2-fs0-ch3";
};
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen-d2@x9106000 {
+ clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index e6525ab4d9bb..0efb3cd6a86e 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -30,8 +30,9 @@
};
soc {
- usb2_picophy1: phy2 {
+ usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -39,8 +40,9 @@
reset-names = "global", "port";
};
- usb2_picophy2: phy3 {
+ usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 7f80c2c414c8..c67edb1a8121 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -10,23 +10,69 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/c8sectpfe.h>
/ {
- soc {
- sbc_serial0: serial@9530000 {
- status = "okay";
+ leds {
+ compatible = "gpio-leds";
+ red {
+ label = "Front Panel LED";
+ gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ green {
+ gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ sound: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "STI-B2120";
+ status = "okay";
+
+ simple-audio-card,dai-link0 {
+ /* HDMI */
+ format = "i2s";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player0>;
+ };
+
+ codec {
+ sound-dai = <&sti_hdmi>;
+ };
+ };
+
+ simple-audio-card,dai-link1 {
+ /* DAC */
+ format = "i2s";
+ mclk-fs = <256>;
+ frame-inversion = <1>;
+ cpu {
+ sound-dai = <&sti_uni_player2>;
+ };
+
+ codec {
+ sound-dai = <&sti_sasg_codec 1>;
+ };
};
- leds {
- compatible = "gpio-leds";
- red {
- label = "Front Panel LED";
- gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
+ simple-audio-card,dai-link2 {
+ /* SPDIF */
+ format = "left_j";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player3>;
};
- green {
- gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
+
+ codec {
+ sound-dai = <&sti_sasg_codec 0>;
};
};
+ };
+
+ soc {
+ sbc_serial0: serial@9530000 {
+ status = "okay";
+ };
pwm0: pwm@9810000 {
status = "okay";
@@ -80,7 +126,7 @@
st,i2c-min-sda-pulse-width-us = <5>;
};
- miphy28lp_phy: miphy28lp@9b22000 {
+ miphy28lp_phy: miphy28lp@0 {
phy_port0: port@9b22000 {
st,osc-rdy;
@@ -126,7 +172,7 @@
clock-names = "c8sectpfe";
/* tsin0 is TSA on NIMA */
- tsin0: port@0 {
+ tsin0: port {
tsin-num = <0>;
serial-not-parallel;
i2c-bus = <&ssc2>;
@@ -147,53 +193,11 @@
status = "okay";
};
- sti_sasg_codec: sti-sasg-codec {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spdif_out>;
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "STI-B2120";
- status = "okay";
-
- simple-audio-card,dai-link@0 {
- /* HDMI */
- format = "i2s";
- mclk-fs = <128>;
- cpu {
- sound-dai = <&sti_uni_player0>;
- };
-
- codec {
- sound-dai = <&sti_hdmi>;
- };
- };
- simple-audio-card,dai-link@1 {
- /* DAC */
- format = "i2s";
- mclk-fs = <256>;
- frame-inversion = <1>;
- cpu {
- sound-dai = <&sti_uni_player2>;
- };
-
- codec {
- sound-dai = <&sti_sasg_codec 1>;
- };
- };
- simple-audio-card,dai-link@2 {
- /* SPDIF */
- format = "left_j";
- mclk-fs = <128>;
- cpu {
- sound-dai = <&sti_uni_player3>;
- };
-
- codec {
- sound-dai = <&sti_sasg_codec 0>;
- };
+ syscfg_core: core-syscfg@92b0000 {
+ sti_sasg_codec: sti-sasg-codec {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif_out>;
};
};
};
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 293ecb957227..7eb786a2d624 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,13 @@
};
};
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&adc {
@@ -254,6 +261,18 @@
status = "okay";
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <12500000>;
+};
+
&timers1 {
status = "okay";
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 2d4e71717694..8c081eaf20fe 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -42,6 +42,7 @@
/dts-v1/;
#include "stm32f746.dtsi"
+#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
/ {
@@ -90,6 +91,13 @@
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&clk_hse {
@@ -112,6 +120,16 @@
status = "okay";
};
+&sdio1 {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins_a>;
+ pinctrl-1 = <&sdio_pins_od_a>;
+ bus-width = <4>;
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
@@ -119,7 +137,7 @@
};
&usbotg_hs {
- dr_mode = "host";
+ dr_mode = "otg";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_a>;
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index ae94d86c53c4..35202896c093 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -338,6 +338,37 @@
slew-rate = <3>;
};
};
+
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 10099df8b73e..ede77e0f1c41 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -511,6 +511,17 @@
};
};
+ sdio: sdio@40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index c18acbe4cf4e..2f76726bf335 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -48,6 +48,8 @@
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f469-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32F469i-DISCO board";
@@ -66,10 +68,46 @@
serial0 = &usart3;
};
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
+ leds {
+ compatible = "gpio-leds";
+ green {
+ gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ orange {
+ gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
+ };
+ red {
+ gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+ };
+ blue {
+ gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "User";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
/* This turns on vbus for otg for host mode (dwc2) */
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
@@ -120,6 +158,18 @@
};
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
new file mode 100644
index 000000000000..9314128df185
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
+ st,bank-name = "GPIOA";
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
+ st,bank-name = "GPIOB";
+ };
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
+ st,bank-name = "GPIOC";
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
+ st,bank-name = "GPIOD";
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
+ st,bank-name = "GPIOE";
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1400 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
+ st,bank-name = "GPIOF";
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1800 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
+ st,bank-name = "GPIOG";
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
+ st,bank-name = "GPIOH";
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
+ st,bank-name = "GPIOI";
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2400 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
+ st,bank-name = "GPIOJ";
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2800 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
+ st,bank-name = "GPIOK";
+ };
+
+ cec_pins_a: cec@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
+ slew-rate = <0>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ usart1_pins_b: usart1@1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_b: i2c1@0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
+ <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ usbotg_hs_pins_a: usbotg-hs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+ <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+ <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+ <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+ <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+ <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+ <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+ <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+ <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+ <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+ <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+ <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_hs_pins_b: usbotg-hs@1 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+ <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
+ <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+ <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+ <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+ <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+ <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+ <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+ <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+ <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+ <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+ <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_a: usbotg-fs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
+ <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_a: sdio_pins_a@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od_a: sdio_pins_od_a@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_b: sdio_pins_b@0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
+ <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
+ <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
+ <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
+ <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od_b: sdio_pins_od_b@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
+ <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
+ <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
+ <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
index 4d85dba59e1d..be94c6ad7e94 100644
--- a/arch/arm/boot/dts/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -42,7 +42,9 @@
/dts-v1/;
#include "stm32f746.dtsi"
+#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F746-DISCO board";
@@ -75,12 +77,30 @@
regulator-name = "vcc5_host1";
regulator-always-on;
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&clk_hse {
clock-frequency = <25000000>;
};
+&sdio1 {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins_a>;
+ pinctrl-1 = <&sdio_pins_od_a>;
+ bus-width = <4>;
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_b>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi
new file mode 100644
index 000000000000..fcfd2ac7239b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32f7-pinctrl.dtsi"
+
+&pinctrl{
+ compatible = "st,stm32f746-pinctrl";
+};
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 5f66d151eedb..4be2ee575b19 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -42,7 +42,6 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -429,6 +428,28 @@
status = "disabled";
};
+ sdio2: sdio2@40011c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
+ clock-names = "apb_pclk";
+ interrupts = <103>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ sdio1: sdio1@40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
@@ -498,222 +519,6 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32f746-pinctrl";
- ranges = <0 0x40020000 0x3000>;
- interrupt-parent = <&exti>;
- st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
-
- gpioa: gpio@40020000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
- st,bank-name = "GPIOA";
- };
-
- gpiob: gpio@40020400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
- st,bank-name = "GPIOB";
- };
-
- gpioc: gpio@40020800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
- st,bank-name = "GPIOC";
- };
-
- gpiod: gpio@40020c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xc00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
- st,bank-name = "GPIOD";
- };
-
- gpioe: gpio@40021000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
- st,bank-name = "GPIOE";
- };
-
- gpiof: gpio@40021400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
- st,bank-name = "GPIOF";
- };
-
- gpiog: gpio@40021800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
- st,bank-name = "GPIOG";
- };
-
- gpioh: gpio@40021c00 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1c00 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
- st,bank-name = "GPIOH";
- };
-
- gpioi: gpio@40022000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
- st,bank-name = "GPIOI";
- };
-
- gpioj: gpio@40022400 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2400 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
- st,bank-name = "GPIOJ";
- };
-
- gpiok: gpio@40022800 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2800 0x400>;
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
- st,bank-name = "GPIOK";
- };
-
- cec_pins_a: cec@0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
- slew-rate = <0>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- usart1_pins_a: usart1@0 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- usart1_pins_b: usart1@1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
- bias-disable;
- };
- };
-
- i2c1_pins_b: i2c1@0 {
- pins {
- pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
- <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- usbotg_hs_pins_a: usbotg-hs@0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_hs_pins_b: usbotg-hs@1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
- <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
- <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
- <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
- <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
- <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
- <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
- <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
- <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
- <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
- <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
- <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
-
- usbotg_fs_pins_a: usbotg-fs@0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
- <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
- <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- };
- };
-
crc: crc@40023000 {
compatible = "st,stm32f7-crc";
reg = <0x40023000 0x400>;
@@ -771,6 +576,9 @@
interrupts = <77>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
clock-names = "otg";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 4463ca13a740..2241eecdabfe 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -42,11 +42,13 @@
/dts-v1/;
#include "stm32f746.dtsi"
+#include "stm32f769-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F769-DISCO board";
- compatible = "st,stm32f769-disco", "st,stm32f7";
+ compatible = "st,stm32f769-disco", "st,stm32f769";
chosen {
bootargs = "root=/dev/ram";
@@ -61,6 +63,42 @@
serial0 = &usart1;
};
+ leds {
+ compatible = "gpio-leds";
+ green {
+ gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ red {
+ gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@0 {
+ label = "User";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ usbotg_hs_phy: usb-phy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
+ clock-names = "main_clk";
+ };
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&cec {
@@ -73,8 +111,33 @@
clock-frequency = <25000000>;
};
+&rtc {
+ status = "okay";
+};
+
+&sdio2 {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpioi 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins_b>;
+ pinctrl-1 = <&sdio_pins_od_b>;
+ bus-width = <4>;
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ dr_mode = "otg";
+ phys = <&usbotg_hs_phy>;
+ phy-names = "usb2-phy";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi
new file mode 100644
index 000000000000..31005dd9929c
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32f7-pinctrl.dtsi"
+
+&pinctrl{
+ compatible = "st,stm32f769-pinctrl";
+};
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 65c1cd043987..0f15dfb98381 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -49,6 +49,8 @@
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
@@ -57,6 +59,8 @@
reg = <0x0 0x400>;
clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
@@ -65,6 +69,8 @@
reg = <0x400 0x400>;
clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
@@ -73,6 +79,8 @@
reg = <0x800 0x400>;
clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
@@ -81,6 +89,8 @@
reg = <0xc00 0x400>;
clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
@@ -89,6 +99,8 @@
reg = <0x1000 0x400>;
clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
@@ -97,6 +109,8 @@
reg = <0x1400 0x400>;
clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
@@ -105,6 +119,8 @@
reg = <0x1800 0x400>;
clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
@@ -113,6 +129,8 @@
reg = <0x1c00 0x400>;
clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
@@ -121,6 +139,8 @@
reg = <0x2000 0x400>;
clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
@@ -129,6 +149,8 @@
reg = <0x2400 0x400>;
clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
@@ -137,6 +159,8 @@
reg = <0x2800 0x400>;
clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
usart1_pins: usart1@0 {
@@ -164,6 +188,26 @@
bias-disable;
};
};
+
+ usbotg_hs_pins_a: usbotg-hs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
+ <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+ <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
+ <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
+ <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
+ <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
+ <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
+ <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+ <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+ <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+ <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+ <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index bbfcbaca0b36..2bb103e1194d 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -44,6 +44,7 @@
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
#include <dt-bindings/mfd/stm32h7-rcc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
clocks {
@@ -100,6 +101,27 @@
};
};
+ spi2: spi@40003800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40003800 0x400>;
+ interrupts = <36>;
+ clocks = <&rcc SPI2_CK>;
+ status = "disabled";
+
+ };
+
+ spi3: spi@40003c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40003c00 0x400>;
+ interrupts = <51>;
+ clocks = <&rcc SPI3_CK>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
@@ -140,6 +162,36 @@
clocks = <&rcc USART1_CK>;
};
+ spi1: spi@40013000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40013000 0x400>;
+ interrupts = <35>;
+ clocks = <&rcc SPI1_CK>;
+ status = "disabled";
+ };
+
+ spi4: spi@40013400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40013400 0x400>;
+ interrupts = <84>;
+ clocks = <&rcc SPI4_CK>;
+ status = "disabled";
+ };
+
+ spi5: spi@40015000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40015000 0x400>;
+ interrupts = <85>;
+ clocks = <&rcc SPI5_CK>;
+ status = "disabled";
+ };
+
dma1: dma@40020000 {
compatible = "st,stm32-dma";
reg = <0x40020000 0x400>;
@@ -217,6 +269,27 @@
};
};
+ usbotg_hs: usb@40040000 {
+ compatible = "st,stm32f7-hsotg";
+ reg = <0x40040000 0x40000>;
+ interrupts = <77>;
+ clocks = <&rcc USB1OTG_CK>;
+ clock-names = "otg";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ usbotg_fs: usb@40080000 {
+ compatible = "st,stm32f4x9-fsotg";
+ reg = <0x40080000 0x40000>;
+ interrupts = <101>;
+ clocks = <&rcc USB2OTG_CK>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
mdma1: dma@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
@@ -227,6 +300,29 @@
dma-requests = <32>;
};
+ exti: interrupt-controller@58000000 {
+ compatible = "st,stm32h7-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x58000000 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
+ };
+
+ syscfg: system-config@58000400 {
+ compatible = "syscon";
+ reg = <0x58000400 0x400>;
+ };
+
+ spi6: spi@58001400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x58001400 0x400>;
+ interrupts = <86>;
+ clocks = <&rcc SPI6_CK>;
+ status = "disabled";
+ };
+
lptimer2: timer@58002400 {
#address-cells = <1>;
#size-cells = <0>;
@@ -304,7 +400,7 @@
};
};
- vrefbuf: regulator@58003C00 {
+ vrefbuf: regulator@58003c00 {
compatible = "st,stm32-vrefbuf";
reg = <0x58003C00 0x8>;
clocks = <&rcc VREF_CK>;
@@ -313,6 +409,20 @@
status = "disabled";
};
+ rtc: rtc@58004000 {
+ compatible = "st,stm32h7-rtc";
+ reg = <0x58004000 0x400>;
+ clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
+ clock-names = "pclk", "rtc_ck";
+ assigned-clocks = <&rcc RTC_CK>;
+ assigned-clock-parents = <&rcc LSE_CK>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg>;
+ status = "disabled";
+ };
+
rcc: reset-clock-controller@58024400 {
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
reg = <0x58024400 0x400>;
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 79e841d94079..45e088c55741 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -63,7 +63,7 @@
};
&clk_hse {
- clock-frequency = <125000000>;
+ clock-frequency = <25000000>;
};
&usart2 {
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 9f0e72c67219..c7187e18ea16 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -68,6 +68,14 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
+
+ usbotg_hs_phy: usb-phy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&rcc USB1ULPI_CK>;
+ clock-names = "main_clk";
+ };
+
};
&adc_12 {
@@ -84,9 +92,21 @@
clock-frequency = <25000000>;
};
+&rtc {
+ status = "okay";
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins>;
pinctrl-names = "default";
status = "okay";
};
+&usbotg_hs {
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phys = <&usbotg_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "otg";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
new file mode 100644
index 000000000000..c0743305f31b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-pinctrl";
+ ranges = <0 0x50002000 0xa400>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOH";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOI";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOJ";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOK";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+
+ uart4_pins_a: uart4@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+ };
+
+ pinctrl_z: pin-controller-z {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-z-pinctrl";
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+ status = "disabled";
+
+ gpioz: gpio@54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&clk_pll2_p>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
new file mode 100644
index 000000000000..9f90337a22e3
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157C eval daughter";
+ compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x40000000>;
+ };
+
+ aliases {
+ serial0 = &uart4;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
new file mode 100644
index 000000000000..57e6dbc52e09
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157c-ed1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
+ compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart4;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
new file mode 100644
index 000000000000..9e17e42b02b2
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_pll_per: clk-pll-per {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+
+ clk_pclk1: clk-pclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <86000000>;
+ };
+
+ clk_pll3_p: clk-pll3_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <172000000>;
+ };
+
+ clk_pll2_p: clk-pll2_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <264000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ usart2: serial@4000e000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4000e000 0x400>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ usart3: serial@4000f000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4000f000 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ uart5: serial@40011000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ uart7: serial@40018000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40018000 0x400>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ uart8: serial@40019000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40019000 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ usart6: serial@44003000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x44003000 0x400>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+
+ usart1: serial@5c000000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x5c000000 0x400>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 09e909576c61..6c254ec4c85b 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -164,8 +164,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 39ba4ccb9e2e..38a2c4134952 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -106,8 +106,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
index dfc88aee4fe3..cf7b392dff31 100644
--- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -123,8 +123,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 1982c8c238c5..197a1f2b75ff 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -162,8 +162,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
index 147cbc5e08ac..896e27a08727 100644
--- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -150,8 +150,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
index 41ca8bded89f..ea7a59dcf8f9 100644
--- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
@@ -141,8 +141,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index f33e42d6ce8b..cc988ccd5ca7 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -106,8 +106,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
index 35c57d065dd8..f63767cddd8e 100644
--- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
@@ -78,8 +78,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts
index 9482e831a9a1..26d0c1d6a02b 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts
@@ -152,8 +152,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 4b5c91c8e85b..5d096528e75a 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -142,8 +142,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
index 13224f5ac166..221acd10f6c8 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
@@ -300,8 +300,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
index d22bd79562d8..80ecd78247ac 100644
--- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
@@ -106,8 +106,7 @@
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
index 879141ca6027..247fa27ef717 100644
--- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
@@ -133,8 +133,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
index 435c551aef0f..0dbf69576512 100644
--- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
@@ -132,8 +132,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 1b639e5f9172..f9d74e21031d 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -96,8 +96,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts
index 7198b34e2e50..059fe9c5d024 100644
--- a/arch/arm/boot/dts/sun4i-a10-mk802.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts
@@ -56,12 +56,27 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&codec {
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -70,11 +85,20 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
index e460da2eb139..17dcdf031118 100644
--- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
@@ -82,8 +82,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index 49247fbe6acd..b74a61496537 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -97,7 +97,6 @@
864000 1300000
624000 1250000
>;
- cooling-max-level = <2>;
};
&de {
@@ -165,8 +164,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 6e140547b638..b97a0f2f20b9 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -140,8 +140,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
index 5081303f79e7..84b25be1ac94 100644
--- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -138,8 +138,7 @@
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 4f2f2eea0755..77e8436beed4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -123,8 +123,6 @@
624000 1250000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <3>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
index d2dee8d434bf..39504d720efc 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
@@ -93,8 +93,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index 16f839df4227..8d4fb9331212 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -104,8 +104,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
index 020aa9d6c31d..dd7fd5c3d76f 100644
--- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
@@ -92,8 +92,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index da95118af4dc..2c902ed2c87a 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -201,8 +201,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
@@ -211,8 +210,7 @@
pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
- cd-inverted;
+ cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 262b3669f04d..034853d1c08f 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -80,8 +80,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 5482be174e12..3f68ef5d92a0 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -130,8 +130,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
- cd-inverted;
+ cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index 3dbb0d7c2f8c..378214d8316e 100644
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -125,8 +125,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 584fa579ded2..7ee0c3f6d7a1 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -120,8 +120,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 3a831eaf1dfc..aa4b34fd9126 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -99,8 +99,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 4b9af423c6d5..437ad913a373 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -194,8 +194,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 4e830f5cb7f1..b1d827765530 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -116,8 +116,6 @@
432000 1200000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <5>;
};
&pio {
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 558c16a30543..5f0adc0f7bb4 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -236,8 +236,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 49229b3d5492..8acbaab14fe5 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -127,8 +127,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 85eff0307ca4..939c497a6f70 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -117,8 +117,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 19e382a11297..ce4f9e9834bf 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -218,8 +218,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts
index 010a84c7c012..d659be9dbc50 100644
--- a/arch/arm/boot/dts/sun6i-a31-i7.dts
+++ b/arch/arm/boot/dts/sun6i-a31-i7.dts
@@ -58,6 +58,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -93,6 +104,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -113,6 +128,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -124,8 +149,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
- cd-inverted;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
@@ -161,6 +185,10 @@
status = "okay";
};
+&tcon0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 50605fd4449e..9698f6d38d03 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -107,8 +107,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
- cd-inverted;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
index 5219556e9f73..bb14b171b160 100644
--- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -107,8 +107,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
- cd-inverted;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 72d3fe44ecaf..c72992556a86 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -113,8 +113,6 @@
480000 1000000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <3>;
};
cpu@1 {
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index 0cdb38ab3377..4cb9664cdb29 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -151,8 +151,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index 298476485bb4..da0ccf5a2c44 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -167,8 +167,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
- cd-inverted;
+ cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..b8b79c0e9ee0 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -42,7 +42,6 @@
/dts-v1/;
#include "sun6i-a31s.dtsi"
-#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -99,6 +98,7 @@
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
phy = <&phy1>;
phy-mode = "rgmii";
+ phy-supply = <&reg_dldo1>;
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
@@ -118,10 +118,9 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
- vmmc-supply = <&reg_vcc3v0>;
+ vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
- cd-inverted;
+ cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
status = "okay";
};
@@ -132,7 +131,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_a>;
- vmmc-supply = <&reg_vcc3v0>;
+ vmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
non-removable;
@@ -163,6 +162,8 @@
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <&reg_dcdc1>;
+ x-powers,drive-vbus-en;
};
};
@@ -193,7 +194,28 @@
#include "axp22x.dtsi"
+&reg_aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-gmac";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
&reg_dc5ldo {
+ regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd-cpus";
@@ -233,6 +255,40 @@
regulator-name = "vcc-dram";
};
+&reg_dldo1 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-mac";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+&reg_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pb";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vdd-csi";
+ status = "okay";
+};
+
+&reg_ldo_io1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pm-cpus";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
index f3edf9ca435c..aab6c1720ef7 100644
--- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -102,8 +102,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
index 3cc4046b904a..4e72e4f3ef96 100644
--- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
@@ -69,8 +69,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index 4ed3162e3e5a..763cb03033c4 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -184,8 +184,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 88a1c2363c6c..70dfc4ac0bb5 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -63,6 +63,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -109,6 +120,10 @@
>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -130,6 +145,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -159,8 +184,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
index e7af1b7c33d5..0898eb6162f5 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
@@ -158,8 +158,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 39f43e4eb742..942ac9dfd4a5 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -165,8 +165,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8c9bedc602ec..5649161de1d7 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -206,8 +206,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
index 6e6264cd69f8..1f0e5ecbf0c4 100644
--- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -163,8 +163,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 55809973a568..2e3f2f29d124 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -160,8 +160,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
index 794e7617f545..926fa194eb1b 100644
--- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
+++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
@@ -107,8 +107,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */
- cd-inverted;
+ cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
index 8a8a6dbcd414..1b05ba466e7d 100644
--- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
@@ -124,8 +124,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index 442f3c755f36..b1ab7c1c33e3 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -227,8 +227,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
index 43c94787ef07..e91a209850bc 100644
--- a/arch/arm/boot/dts/sun7i-a20-m3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -120,8 +120,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
index f7413094183c..6109f794a9c1 100644
--- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
+++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
@@ -66,12 +66,27 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&codec {
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -80,6 +95,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -112,8 +137,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index 64c8ef9a2756..f080f82b58ef 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -79,6 +90,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -107,6 +122,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -190,8 +215,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
@@ -200,8 +224,7 @@
pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
- cd-inverted;
+ cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts
new file mode 100644
index 000000000000..c56620a8fb20
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+ model = "Olimex A20-SOM204-EVB-eMMC";
+ compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: mmc2_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
new file mode 100644
index 000000000000..eae8e267b9ef
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Olimex A20-SOM204-EVB";
+ compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart4;
+ serial2 = &uart7;
+ spi0 = &spi1;
+ spi1 = &spi2;
+ ethernet1 = &rtl8723bs;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ stat {
+ label = "a20-som204-evb:green:stat";
+ gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led1 {
+ label = "a20-som204-evb:green:led1";
+ gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led2 {
+ label = "a20-som204-evb:yellow:led2";
+ gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ rtl_pwrseq: rtl_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ahci {
+ target-supply = <&reg_ahci_5v>;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy3>;
+ phy-mode = "rgmii";
+ phy-supply = <&reg_vcc3v3>;
+
+ snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* Exposed to UEXT1 */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/* Exposed to UEXT2 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&rtl_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ bt_uart_pins: bt_uart_pins@0 {
+ pins = "PG6", "PG7", "PG8";
+ function = "uart3";
+ };
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&reg_ahci_5v {
+ gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pg";
+};
+
+&reg_usb0_vbus {
+ gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&reg_usb1_vbus {
+ status = "okay";
+};
+
+&reg_usb2_vbus {
+ status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>,
+ <&spi1_cs0_pins_a>;
+ status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>,
+ <&spi2_cs0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+/* Used for RTL8723BS bluetooth */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_uart_pins>;
+ status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ usb2_vbus-supply = <&reg_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index edf9c3c6c0d7..d20fd03596e9 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -158,8 +158,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index ba250189d07f..b828677f331d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -159,8 +159,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index dffbaa24b3ee..866d230593be 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -226,8 +226,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
@@ -236,8 +235,7 @@
pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
- cd-inverted;
+ cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
index 7af4c8fc1865..f5c7178eb063 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -98,6 +109,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -119,6 +134,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -144,8 +169,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
@@ -154,8 +178,7 @@
pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
- cd-inverted;
+ cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
index 0a8d4a05e8a0..7a4244e57589 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
@@ -135,8 +135,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index fb591f32252c..bfca960b03e0 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -158,8 +158,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 777152a3df0f..c576f101fbde 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -159,8 +159,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index f8d0aafb9f88..8202c87ca6a3 100644
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
@@ -154,8 +154,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
index 7f8405a0dd0f..ff5c1086585c 100644
--- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
@@ -123,8 +123,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index bd0cd3204273..e529e4ff2174 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -47,7 +47,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/clock/sun4i-a10-ccu.h>
+#include <dt-bindings/clock/sun7i-a20-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
/ {
@@ -116,8 +116,6 @@
144000 1000000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <6>;
};
cpu@1 {
@@ -1217,6 +1215,31 @@
#size-cells = <0>;
};
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+
gmac: ethernet@1c50000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c50000 0x10000>;
diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts
index 87289a60c520..8a93697df3a5 100644
--- a/arch/arm/boot/dts/sun8i-a23-evb.dts
+++ b/arch/arm/boot/dts/sun8i-a23-evb.dts
@@ -107,8 +107,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
index be9a6b8d7a1e..a1a1eb64caeb 100644
--- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
+++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
@@ -43,7 +43,6 @@
/dts-v1/;
#include "sun8i-a33.dtsi"
-#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -62,8 +61,6 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pin_olinuxino>;
green {
label = "a33-olinuxino:green:usr";
@@ -72,17 +69,24 @@
};
};
+&codec {
+ status = "okay";
+};
+
+&dai {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
@@ -90,23 +94,6 @@
status = "okay";
};
-&pio {
- led_pin_olinuxino: led_pins@0 {
- pins = "PB7";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
- pins = "PB4";
- function = "gpio_in";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PB3";
- function = "gpio_in";
- };
-};
-
&r_rsb {
status = "okay";
@@ -122,6 +109,14 @@
#include "axp223.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
@@ -195,6 +190,21 @@
vcc-lcd-supply = <&reg_dc1sw>;
};
+&sound {
+ /* Board level jack widgets */
+ simple-audio-card,widgets = "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack";
+ /* Board level routing. First 2 routes copied from SoC level */
+ simple-audio-card,routing =
+ "Left DAC", "AIF1 Slot 0 Left",
+ "Right DAC", "AIF1 Slot 0 Right",
+ "HP", "HPCOM",
+ "Headphone Jack", "HP",
+ "MIC1", "Microphone Jack",
+ "Microphone Jack", "MBIAS";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
@@ -211,8 +221,6 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_drivevbus>;
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 433cf2a2a9a2..541acb4d2b91 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -144,8 +144,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 50eb84fa246a..a21f2ed07a52 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -289,7 +289,6 @@
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_FE>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 5091cecbcd1e..36ecebaff3c0 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -87,9 +87,8 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
- cd-inverted;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..3b579d7567c8 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -60,6 +60,31 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "bananapi-m3:blue:usr";
+ gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "bananapi-m3:green:usr";
+ gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
@@ -82,6 +107,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
@@ -100,6 +129,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -112,8 +151,7 @@
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 6da08cd0e107..88decb0747ac 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -176,8 +176,7 @@
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 511fca491fe8..1537ce148cc1 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -128,6 +128,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu100 {
+ cpu-supply = <&reg_dcdc3>;
+};
+
&de {
status = "okay";
};
@@ -231,6 +239,10 @@
#include "axp81x.dtsi"
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_aldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..568307639be8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -60,51 +60,63 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
+ clocks = <&ccu CLK_C0CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <1>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <2>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <3>;
};
- cpu@100 {
+ cpu100: cpu@100 {
+ clocks = <&ccu CLK_C1CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x100>;
};
cpu@101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x101>;
};
cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x102>;
};
cpu@103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x103>;
};
};
@@ -155,7 +167,7 @@
de: display-engine {
compatible = "allwinner,sun8i-a83t-display-engine";
- allwinner,pipelines = <&mixer0>;
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
status = "disabled";
};
@@ -164,6 +176,112 @@
device_type = "memory";
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1128000000 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
+ cpu1_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1128000000 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -208,6 +326,29 @@
};
};
+ mixer1: mixer@1200000 {
+ compatible = "allwinner,sun8i-a83t-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint {
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+ };
+
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
@@ -256,6 +397,40 @@
};
};
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ reg = <0>;
+
+ tcon1_in_mixer1: endpoint {
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ };
+ };
+ };
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-a83t-mmc",
"allwinner,sun7i-a20-mmc";
@@ -427,6 +602,11 @@
drive-strength = <40>;
};
+ hdmi_pins: hdmi-pins {
+ pins = "PH6", "PH7", "PH8";
+ function = "hdmi";
+ };
+
i2c0_pins: i2c0-pins {
pins = "PH0", "PH1";
function = "i2c0";
@@ -685,6 +865,50 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon1: endpoint {
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@1ef0000 {
+ compatible = "allwinner,sun8i-a83t-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
r_intc: interrupt-controller@1f00c00 {
compatible = "allwinner,sun8i-a83t-r-intc",
"allwinner,sun6i-a31-r-intc";
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
new file mode 100644
index 000000000000..7d01f9322658
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Banana Pi BPI-M2-Zero";
+ compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+
+ pwr_led {
+ label = "bananapi-m2-zero:red:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+
+ sw4 {
+ label = "power";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ /*
+ * On the production batch of this board the card detect GPIO is
+ * high active (card inserted), although on the early samples it's
+ * low active.
+ */
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ /*
+ * There're two micro-USB connectors, one is power-only and another is
+ * OTG. The Vbus of these two connectors are connected together, so
+ * the external USB device will be powered just by the power input
+ * from the power-only USB port.
+ */
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
index 112f09c67d67..3356f4210d45 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
@@ -68,6 +68,14 @@
};
};
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
+ };
+};
+
&ohci1 {
/*
* RTL8152B USB-Ethernet adapter is connected to USB1,
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 6713d0f2b3f4..0bc031fe4c56 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -112,18 +112,13 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc_wifi>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -139,10 +134,6 @@
};
};
-&mmc1_pins_a {
- bias-pull-up;
-};
-
&ohci0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index f1c3f1cc4d97..30540dc8e0c5 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -100,6 +111,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -129,6 +144,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -136,18 +161,13 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 10da56e86ab8..cf1f970b0c6f 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -100,6 +111,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -108,6 +123,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -115,18 +140,13 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
index d406571a0dd6..b20a710da7bc 100644
--- a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -23,6 +23,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -120,6 +131,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -143,6 +158,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -150,12 +175,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc_io>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index a6e61915d648..65cba1050802 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -101,8 +101,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
@@ -119,6 +117,16 @@
};
};
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
index c77fbca4f227..9412668bb888 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -49,6 +49,21 @@
aliases {
ethernet0 = &emac;
};
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+};
+
+&de {
+ status = "okay";
};
&ehci1 {
@@ -66,6 +81,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
index 03ff6f8b93ff..6246d3eff39d 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -72,16 +72,35 @@
gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
};
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ };
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
};
&uart0 {
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
index 7646e331bd29..f110ee382239 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -95,10 +95,7 @@
&mmc0 {
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
vmmc-supply = <&reg_vcc3v3>;
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index b20be95b49d5..f1fc6bdca8be 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -62,6 +62,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -114,6 +125,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -125,6 +140,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -132,18 +157,13 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index a70a1daf4e2c..476ae8e387ca 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -91,6 +102,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -99,6 +114,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -106,18 +131,13 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 82e5d28cd698..3328fe583c9b 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -90,6 +101,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -102,16 +117,22 @@
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
+};
+
+&hdmi {
status = "okay";
};
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
index a10281b455f5..71fb73208939 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -59,8 +59,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index d22546df1b82..cea4d647ecbf 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -98,6 +109,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -121,6 +136,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -128,12 +153,9 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 8495deecedad..10da8ed7db81 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -79,6 +79,33 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ soc {
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+ };
};
&ccu {
diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index eaf09666720d..0dbdb29a8fff 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -150,8 +150,7 @@
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 8c5efe2a9881..27d9ccd0ef2f 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -164,8 +164,7 @@
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
- cd-inverted;
+ cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index d6bd15898db6..880096c7e252 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -85,8 +85,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
@@ -125,6 +124,14 @@
#include "axp223.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index fe16fc0eb518..a26d72c3f9b5 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -150,8 +150,7 @@
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
- cd-inverted;
+ cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 4024639aa005..85da85faf869 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -74,6 +74,52 @@
};
};
+ vga-connector {
+ compatible = "vga-connector";
+ label = "vga";
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_dac_out>;
+ };
+ };
+ };
+
+ vga-dac {
+ compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
+ vdd-supply = <&reg_dcdc1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vga_dac_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vga_dac_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
@@ -83,13 +129,22 @@
};
};
+&de {
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */
- cd-inverted;
+ cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */
status = "okay";
};
@@ -403,6 +458,18 @@
#include "axp809.dtsi"
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd0_rgb888_pins>;
+};
+
+&tcon0_out {
+ tcon0_out_vga: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_dac_in>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index a9b807be99a0..58a199b0e494 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -125,8 +125,7 @@
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
- cd-inverted;
+ cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 90eac0b2a193..25591d6883ef 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -63,48 +63,72 @@
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ cci-control-port = <&cci_control0>;
+ clock-frequency = <12000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x3>;
};
cpu4: cpu@100 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x100>;
};
cpu5: cpu@101 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x101>;
};
cpu6: cpu@102 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x102>;
};
cpu7: cpu@103 {
compatible = "arm,cortex-a15";
device_type = "cpu";
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <18000000>;
+ enable-method = "allwinner,sun9i-a80-smp";
reg = <0x103>;
};
};
@@ -224,6 +248,12 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun9i-a80-display-engine";
+ allwinner,pipelines = <&fe0>, <&fe1>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -234,6 +264,25 @@
*/
ranges = <0 0 0 0x20000000>;
+ sram_b: sram@20000 {
+ /* 256 KiB secure SRAM at 0x20000 */
+ compatible = "mmio-sram";
+ reg = <0x00020000 0x40000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00020000 0x40000>;
+
+ smp-sram@1000 {
+ /*
+ * This is checked by BROM to determine if
+ * cpu0 should jump to SMP entry vector
+ */
+ compatible = "allwinner,sun9i-a80-smp-sram";
+ reg = <0x1000 0x8>;
+ };
+ };
+
ehci0: usb@a00000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>;
@@ -347,6 +396,11 @@
#reset-cells = <1>;
};
+ cpucfg@1700000 {
+ compatible = "allwinner,sun9i-a80-cpucfg";
+ reg = <0x01700000 0x100>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>;
@@ -431,6 +485,36 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ cci: cci@1c90000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01c90000 0x1000>;
+ ranges = <0x0 0x01c90000 0x10000>;
+
+ cci_control0: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control1: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
@@ -445,6 +529,381 @@
#reset-cells = <1>;
};
+ fe0: display-frontend@3100000 {
+ compatible = "allwinner,sun9i-a80-display-frontend";
+ reg = <0x03100000 0x40000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
+ <&de_clocks CLK_DRAM_FE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_deu0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ fe1: display-frontend@3140000 {
+ compatible = "allwinner,sun9i-a80-display-frontend";
+ reg = <0x03140000 0x40000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
+ <&de_clocks CLK_DRAM_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_deu1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu1_in_fe1>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@3200000 {
+ compatible = "allwinner,sun9i-a80-display-backend";
+ reg = <0x03200000 0x40000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
+ <&de_clocks CLK_DRAM_BE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_BE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_deu0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu0_out_be0>;
+ };
+
+ be0_in_deu1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&deu1_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_in_be0>;
+ };
+ };
+ };
+ };
+
+ be1: display-backend@3240000 {
+ compatible = "allwinner,sun9i-a80-display-backend";
+ reg = <0x03240000 0x40000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
+ <&de_clocks CLK_DRAM_BE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_clocks RST_BE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be1_in_deu0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&deu0_out_be1>;
+ };
+
+ be1_in_deu1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&deu1_out_be1>;
+ };
+ };
+
+ be1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be1_out_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc1_in_be1>;
+ };
+ };
+ };
+ };
+
+ deu0: deu@3300000 {
+ compatible = "allwinner,sun9i-a80-deu";
+ reg = <0x03300000 0x40000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DEU0>,
+ <&de_clocks CLK_IEP_DEU0>,
+ <&de_clocks CLK_DRAM_DEU0>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DEU0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deu0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deu0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_deu0>;
+ };
+ };
+
+ deu0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ deu0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_deu0>;
+ };
+
+ deu0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_deu0>;
+ };
+ };
+ };
+ };
+
+ deu1: deu@3340000 {
+ compatible = "allwinner,sun9i-a80-deu";
+ reg = <0x03340000 0x40000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DEU1>,
+ <&de_clocks CLK_IEP_DEU1>,
+ <&de_clocks CLK_DRAM_DEU1>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DEU1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deu1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ deu1_in_fe1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe1_out_deu1>;
+ };
+ };
+
+ deu1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ deu1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_deu1>;
+ };
+
+ deu1_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_deu1>;
+ };
+ };
+ };
+ };
+
+ drc0: drc@3400000 {
+ compatible = "allwinner,sun9i-a80-drc";
+ reg = <0x03400000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DRC0>,
+ <&de_clocks CLK_IEP_DRC0>,
+ <&de_clocks CLK_DRAM_DRC0>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DRC0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_drc0>;
+ };
+ };
+
+ drc0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_drc0>;
+ };
+ };
+ };
+ };
+
+ drc1: drc@3440000 {
+ compatible = "allwinner,sun9i-a80-drc";
+ reg = <0x03440000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&de_clocks CLK_BUS_DRC1>,
+ <&de_clocks CLK_IEP_DRC1>,
+ <&de_clocks CLK_DRAM_DRC1>;
+ clock-names = "ahb",
+ "mod",
+ "ram";
+ resets = <&de_clocks RST_DRC1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc1_in_be1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be1_out_drc1>;
+ };
+ };
+
+ drc1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc1_out_tcon1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_in_drc1>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@3c00000 {
+ compatible = "allwinner,sun9i-a80-tcon-lcd";
+ reg = <0x03c00000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
+ clock-names = "ahb", "tcon-ch0";
+ resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
+ reset-names = "lcd", "edp";
+ clock-output-names = "tcon0-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ tcon1: lcd-controller@3c10000 {
+ compatible = "allwinner,sun9i-a80-tcon-tv";
+ reg = <0x03c10000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
+ reset-names = "lcd", "edp";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_drc1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
ccu: clock@6000000 {
compatible = "allwinner,sun9i-a80-ccu";
reg = <0x06000000 0x800>;
@@ -494,6 +953,17 @@
function = "i2c3";
};
+ lcd0_rgb888_pins: lcd0-rgb888-pins {
+ pins = "PD0", "PD1", "PD2", "PD3",
+ "PD4", "PD5", "PD6", "PD7",
+ "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1" ,"PF2", "PF3",
"PF4", "PF5";
@@ -658,6 +1128,11 @@
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
+ prcm@8001400 {
+ compatible = "allwinner,sun9i-a80-prcm";
+ reg = <0x08001400 0x200>;
+ };
+
apbs_rst: reset@80014b0 {
reg = <0x080014b0 0x4>;
compatible = "allwinner,sun6i-a31-clock-reset";
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 7a83b15225c7..1be1a02d6df2 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -105,6 +105,12 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-h3-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -123,6 +129,29 @@
#reset-cells = <1>;
};
+ mixer0: mixer@1100000 {
+ compatible = "allwinner,sun8i-h3-de2-mixer-0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint {
+ remote-endpoint = <&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-h3-system-controller",
"syscon";
@@ -138,9 +167,46 @@
#dma-cells = <1>;
};
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-h3-tcon-tv",
+ "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint {
+ remote-endpoint = <&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ };
+ };
+ };
+ };
+
mmc0: mmc@1c0f000 {
/* compatible and clocks are in per SoC .dtsi file */
reg = <0x01c0f000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -152,6 +218,8 @@
mmc1: mmc@1c10000 {
/* compatible and clocks are in per SoC .dtsi file */
reg = <0x01c10000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -348,7 +416,7 @@
function = "i2c2";
};
- mmc0_pins_a: mmc0 {
+ mmc0_pins: mmc0 {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
@@ -356,13 +424,7 @@
bias-pull-up;
};
- mmc0_cd_pin: mmc0_cd_pin {
- pins = "PF6";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc1_pins_a: mmc1 {
+ mmc1_pins: mmc1 {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
@@ -684,6 +746,50 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,sun8i-h3-dw-hdmi",
+ "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@1ef0000 {
+ compatible = "allwinner,sun8i-h3-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+ <&ccu 6>;
+ clock-names = "bus", "mod", "pll-0";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index acd6cf51b15b..eafff16765b4 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -780,7 +780,7 @@
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index ecffcd115fa7..a6ad759dddb4 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2018 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -105,7 +105,7 @@
*/
i2c@7000c000 {
status = "okay";
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
pcie-switch@58 {
compatible = "plx,pex8605";
@@ -114,7 +114,7 @@
/* M41T0M6 real time clock on carrier board */
rtc@68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
@@ -124,7 +124,6 @@
*/
hdmi_ddc: i2c@7000c400 {
status = "okay";
- clock-frequency = <100000>;
};
/*
@@ -133,7 +132,7 @@
*/
i2c@7000c500 {
status = "okay";
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
};
/* I2C4 (DDC): unused */
@@ -226,9 +225,7 @@
backlight: backlight {
compatible = "pwm-backlight";
-
- /* BKL1_PWM */
- pwms = <&pwm 3 5000000>;
+ pwms = <&pwm 3 5000000>; /* BKL1_PWM */
brightness-levels = <255 231 223 207 191 159 127 0>;
default-brightness-level = <6>;
/* BKL1_ON */
@@ -276,3 +273,13 @@
vin-supply = <&reg_5v0>;
};
};
+
+&gpio {
+ /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+ pex_perst_n {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PEX_PERST_N";
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
new file mode 100644
index 000000000000..8a8d5fa0ecd1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2016-2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124-apalis-v1.2.dtsi"
+
+/ {
+ model = "Toradex Apalis TK1 on Apalis Evaluation Board";
+ compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval",
+ "toradex,apalis-tk1", "nvidia,tegra124";
+
+ aliases {
+ rtc0 = "/i2c@7000c000/rtc@68";
+ rtc1 = "/i2c@7000d000/pmic@40";
+ rtc2 = "/rtc@7000e000";
+ serial0 = &uarta;
+ serial1 = &uartb;
+ serial2 = &uartc;
+ serial3 = &uartd;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ pcie@1003000 {
+ pci@1,0 {
+ status = "okay";
+ };
+ };
+
+ host1x@50000000 {
+ hdmi@54280000 {
+ status = "okay";
+ };
+ };
+
+ /* Apalis UART1 */
+ serial@70006000 {
+ status = "okay";
+ };
+
+ /* Apalis UART2 */
+ serial@70006040 {
+ status = "okay";
+ };
+
+ /* Apalis UART3 */
+ serial@70006200 {
+ status = "okay";
+ };
+
+ /* Apalis UART4 */
+ serial@70006300 {
+ status = "okay";
+ };
+
+ pwm@7000a000 {
+ status = "okay";
+ };
+
+ /*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+ * board)
+ */
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pcie-switch@58 {
+ compatible = "plx,pex8605";
+ reg = <0x58>;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+ };
+
+ /* GEN2_I2C: unused */
+
+ /*
+ * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
+ * on carrier board)
+ */
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ /*
+ * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
+ * (e.g. display EDID)
+ */
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ };
+
+ /* SPI1: Apalis SPI1 */
+ spi@7000d400 {
+ status = "okay";
+ spi-max-frequency = <50000000>;
+
+ spidev0: spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ /* SPI4: Apalis SPI2 */
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <50000000>;
+
+ spidev1: spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ /* Apalis Serial ATA */
+ sata@70020000 {
+ status = "okay";
+ };
+
+ hda@70030000 {
+ status = "okay";
+ };
+
+ usb@70090000 {
+ status = "okay";
+ };
+
+ /* Apalis MMC1 */
+ sdhci@700b0000 {
+ status = "okay";
+ /* MMC1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vqmmc-supply = <&vddio_sdmmc1>;
+ };
+
+ /* Apalis SD1 */
+ sdhci@700b0400 {
+ status = "okay";
+ /* SD1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vqmmc-supply = <&vddio_sdmmc3>;
+ };
+
+ /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ vbus-supply = <&reg_usbo1_vbus>;
+ };
+
+ /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+ usb@7d004000 {
+ status = "okay";
+ };
+
+ usb-phy@7d004000 {
+ status = "okay";
+ vbus-supply = <&reg_usbh_vbus>;
+ };
+
+ /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */
+ usb@7d008000 {
+ status = "okay";
+ };
+
+ usb-phy@7d008000 {
+ status = "okay";
+ vbus-supply = <&reg_usbh_vbus>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 3 5000000>; /* BKL1_PWM */
+ brightness-levels = <255 231 223 207 191 159 127 0>;
+ default-brightness-level = <6>;
+ /* BKL1_ON */
+ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup {
+ label = "WAKE1_MICO";
+ gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /* USBO1_EN */
+ reg_usbo1_vbus: regulator-usbo1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USBO1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&reg_5v0>;
+ };
+
+ /* USBH_EN */
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&gpio {
+ /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+ pex_perst_n {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PEX_PERST_N";
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
new file mode 100644
index 000000000000..bb67edb016c5
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -0,0 +1,2052 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2016-2018 Toradex AG
+ */
+
+#include "tegra124.dtsi"
+#include "tegra124-apalis-emc.dtsi"
+
+/*
+ * Toradex Apalis TK1 Module Device Tree
+ * Compatible for Revisions 2GB: V1.2A
+ */
+/ {
+ model = "Toradex Apalis TK1";
+ compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
+ "nvidia,tegra124";
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ pcie@1003000 {
+ status = "okay";
+ avddio-pex-supply = <&vdd_1v05>;
+ avdd-pex-pll-supply = <&vdd_1v05>;
+ avdd-pll-erefe-supply = <&avdd_1v05>;
+ dvddio-pex-supply = <&vdd_1v05>;
+ hvdd-pex-pll-e-supply = <&reg_3v3>;
+ hvdd-pex-supply = <&reg_3v3>;
+ vddio-pex-ctl-supply = <&reg_3v3>;
+
+ /* Apalis PCIe (additional lane Apalis type specific) */
+ pci@1,0 {
+ /* PCIE1_RX/TX and TS_DIFF1/2 */
+ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
+ phy-names = "pcie-0", "pcie-1";
+ };
+
+ /* I210 Gigabit Ethernet Controller (On-module) */
+ pci@2,0 {
+ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
+ phy-names = "pcie-0";
+ status = "okay";
+ };
+ };
+
+ host1x@50000000 {
+ hdmi@54280000 {
+ pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+ vdd-supply = <&reg_3v3_avdd_hdmi>;
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio =
+ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpu@0,57000000 {
+ /*
+ * Node left disabled on purpose - the bootloader will enable
+ * it after having set the VPR up
+ */
+ vdd-supply = <&vdd_gpu>;
+ };
+
+ pinmux: pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* Analogue Audio (On-module) */
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_dout_pp2 {
+ nvidia,pins = "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_sclk_pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap_mclk1_pw4 {
+ nvidia,pins = "dap_mclk1_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis BKL1_ON */
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis BKL1_PWM */
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis CAM1_MCLK */
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis Digital Audio */
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_sclk_pa3 {
+ nvidia,pins = "dap2_sclk_pa3";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_din_pa4 {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_dout_pa5 {
+ nvidia,pins = "dap2_dout_pa5";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb3 { /* DAP1_RESET */
+ nvidia,pins = "pbb3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis GPIO */
+ usb_vbus_en0_pn4 {
+ nvidia,pins = "usb_vbus_en0_pn4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ usb_vbus_en1_pn5 {
+ nvidia,pins = "usb_vbus_en1_pn5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ pex_l0_rst_n_pdd1 {
+ nvidia,pins = "pex_l0_rst_n_pdd1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l0_clkreq_n_pdd2 {
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l1_rst_n_pdd5 {
+ nvidia,pins = "pex_l1_rst_n_pdd5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l1_clkreq_n_pdd6 {
+ nvidia,pins = "pex_l1_clkreq_n_pdd6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dp_hpd_pff0 {
+ nvidia,pins = "dp_hpd_pff0";
+ nvidia,function = "dp";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pff2 {
+ nvidia,pins = "pff2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis HDMI1_CEC */
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis HDMI1_HPD */
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis I2C1 */
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen1_i2c_sda_pc5 {
+ nvidia,pins = "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C3 (CAM) */
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ cam_i2c_sda_pbb2 {
+ nvidia,pins = "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C4 (DDC) */
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+ };
+ ddc_sda_pv5 {
+ nvidia,pins = "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis MMC1 */
+ sdmmc1_cd_n_pv3 { /* CD# GPIO */
+ nvidia,pins = "sdmmc1_wp_n_pv3";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out_pw5 { /* D5 GPIO */
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat2_py5 {
+ nvidia,pins = "sdmmc1_dat2_py5";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat1_py6 {
+ nvidia,pins = "sdmmc1_dat1_py6";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat0_py7 {
+ nvidia,pins = "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_req_pcc5 { /* D4 GPIO */
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+ nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ usb_vbus_en2_pff1 { /* D7 GPIO */
+ nvidia,pins = "usb_vbus_en2_pff1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis PWM */
+ ph0 {
+ nvidia,pins = "ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph1 {
+ nvidia,pins = "ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph2 {
+ nvidia,pins = "ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
+ ph3 {
+ nvidia,pins = "ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SATA1_ACT# */
+ dap1_dout_pn2 {
+ nvidia,pins = "dap1_dout_pn2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SD1 */
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat3_pb4 {
+ nvidia,pins = "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat2_pb5 {
+ nvidia,pins = "sdmmc3_dat2_pb5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat1_pb6 {
+ nvidia,pins = "sdmmc3_dat1_pb6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat0_pb7 {
+ nvidia,pins = "sdmmc3_dat0_pb7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cd_n_pv2 { /* CD# GPIO */
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis SPDIF */
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis SPI1 */
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_dir_py1 {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SPI2 */
+ pg5 {
+ nvidia,pins = "pg5";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg6 {
+ nvidia,pins = "pg6";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg7 {
+ nvidia,pins = "pg7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pi3 {
+ nvidia,pins = "pi3";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART1 */
+ pb1 { /* DCD GPIO */
+ nvidia,pins = "pb1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pk7 { /* RI GPIO */
+ nvidia,pins = "pk7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart1_txd_pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart1_rxd_pu1 {
+ nvidia,pins = "pu1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart1_cts_n_pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart1_rts_n_pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_cts_n_pa1 { /* DSR GPIO */
+ nvidia,pins = "uart3_cts_n_pa1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_rts_n_pc0 { /* DTR GPIO */
+ nvidia,pins = "uart3_rts_n_pc0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART2 */
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart2_cts_n_pj5 {
+ nvidia,pins = "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart2_rts_n_pj6 {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART3 */
+ uart3_txd_pw6 {
+ nvidia,pins = "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_rxd_pw7 {
+ nvidia,pins = "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis UART4 */
+ uart4_rxd_pb0 {
+ nvidia,pins = "pb0";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart4_txd_pj7 {
+ nvidia,pins = "pj7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_EN */
+ gen2_i2c_sda_pt6 {
+ nvidia,pins = "gen2_i2c_sda_pt6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_OC# */
+ pbb0 {
+ nvidia,pins = "pbb0";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis USBO1_EN */
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBO1_OC# */
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis WAKE1_MICO */
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* CORE_PWR_REQ */
+ core_pwr_req {
+ nvidia,pins = "core_pwr_req";
+ nvidia,function = "pwron";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* CPU_PWR_REQ */
+ cpu_pwr_req {
+ nvidia,pins = "cpu_pwr_req";
+ nvidia,function = "cpu";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* DVFS */
+ dvfs_pwm_px0 {
+ nvidia,pins = "dvfs_pwm_px0";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dvfs_clk_px2 {
+ nvidia,pins = "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* eMMC */
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat1_paa1 {
+ nvidia,pins = "sdmmc4_dat1_paa1";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat2_paa2 {
+ nvidia,pins = "sdmmc4_dat2_paa2";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat3_paa3 {
+ nvidia,pins = "sdmmc4_dat3_paa3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat4_paa4 {
+ nvidia,pins = "sdmmc4_dat4_paa4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat5_paa5 {
+ nvidia,pins = "sdmmc4_dat5_paa5";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat6_paa6 {
+ nvidia,pins = "sdmmc4_dat6_paa6";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat7_paa7 {
+ nvidia,pins = "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* JTAG_RTCK */
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN_DEV_OFF# */
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN_RESET# */
+ kb_row10_ps2 {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN_WAKE# */
+ ulpi_data4_po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT1# */
+ pk2 {
+ nvidia,pins = "pk2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT2# */
+ pj2 {
+ nvidia,pins = "pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT3# */
+ pi5 {
+ nvidia,pins = "pi5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT4# */
+ pj0 {
+ nvidia,pins = "pj0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_RESET */
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* MCU SPI */
+ gpio_x4_aud_px4 {
+ nvidia,pins = "gpio_x4_aud_px4";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x5_aud_px5 {
+ nvidia,pins = "gpio_x5_aud_px5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x6_aud_px6 { /* MCU_CS */
+ nvidia,pins = "gpio_x6_aud_px6";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x7_aud_px7 {
+ nvidia,pins = "gpio_x7_aud_px7";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gpio_w2_aud_pw2 { /* MCU_CSEZP */
+ nvidia,pins = "gpio_w2_aud_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PMIC_CLK_32K */
+ clk_32k_in {
+ nvidia,pins = "clk_32k_in";
+ nvidia,function = "clk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PMIC_CPU_OC_INT */
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "soc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PWR_I2C */
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pwr_i2c_sda_pz7 {
+ nvidia,pins = "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PWR_INT_N */
+ pwr_int_n {
+ nvidia,pins = "pwr_int_n";
+ nvidia,function = "pmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* RESET_MOCI_CTRL */
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* RESET_OUT_N */
+ reset_out_n {
+ nvidia,pins = "reset_out_n";
+ nvidia,function = "reset_out_n";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SHIFT_CTRL_DIR_IN */
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row1_pr1 {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Configure level-shifter as output for HDA */
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SHIFT_CTRL_DIR_OUT */
+ kb_col5_pq5 {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col6_pq6 {
+ nvidia,pins = "kb_col6_pq6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col7_pq7 {
+ nvidia,pins = "kb_col7_pq7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SHIFT_CTRL_OE */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col1_pq1 {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row2_pr2 {
+ nvidia,pins = "kb_row2_pr2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
+ pi6 {
+ nvidia,pins = "pi6";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* TOUCH_INT */
+ gpio_w3_aud_pw3 {
+ nvidia,pins = "gpio_w3_aud_pw3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pc7 { /* NC */
+ nvidia,pins = "pc7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg0 { /* NC */
+ nvidia,pins = "pg0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg1 { /* NC */
+ nvidia,pins = "pg1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg2 { /* NC */
+ nvidia,pins = "pg2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg3 { /* NC */
+ nvidia,pins = "pg3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg4 { /* NC */
+ nvidia,pins = "pg4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph4 { /* NC */
+ nvidia,pins = "ph4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph5 { /* NC */
+ nvidia,pins = "ph5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph6 { /* NC */
+ nvidia,pins = "ph6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph7 { /* NC */
+ nvidia,pins = "ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi0 { /* NC */
+ nvidia,pins = "pi0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi1 { /* NC */
+ nvidia,pins = "pi1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi2 { /* NC */
+ nvidia,pins = "pi2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi4 { /* NC */
+ nvidia,pins = "pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi7 { /* NC */
+ nvidia,pins = "pi7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk0 { /* NC */
+ nvidia,pins = "pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk1 { /* NC */
+ nvidia,pins = "pk1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk3 { /* NC */
+ nvidia,pins = "pk3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk4 { /* NC */
+ nvidia,pins = "pk4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_fs_pn0 { /* NC */
+ nvidia,pins = "dap1_fs_pn0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_din_pn1 { /* NC */
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_sclk_pn3 { /* NC */
+ nvidia,pins = "dap1_sclk_pn3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data7_po0 { /* NC */
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data0_po1 { /* NC */
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 { /* NC */
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data2_po3 { /* NC */
+ nvidia,pins = "ulpi_data2_po3";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data3_po4 { /* NC */
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data6_po7 { /* NC */
+ nvidia,pins = "ulpi_data6_po7";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_fs_pp4 { /* NC */
+ nvidia,pins = "dap4_fs_pp4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_din_pp5 { /* NC */
+ nvidia,pins = "dap4_din_pp5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_dout_pp6 { /* NC */
+ nvidia,pins = "dap4_dout_pp6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_sclk_pp7 { /* NC */
+ nvidia,pins = "dap4_sclk_pp7";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col3_pq3 { /* NC */
+ nvidia,pins = "kb_col3_pq3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 { /* NC */
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row4_pr4 { /* NC */
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row5_pr5 { /* NC */
+ nvidia,pins = "kb_row5_pr5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row6_pr6 { /* NC */
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row7_pr7 { /* NC */
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row8_ps0 { /* NC */
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row9_ps1 { /* NC */
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row12_ps4 { /* NC */
+ nvidia,pins = "kb_row12_ps4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row13_ps5 { /* NC */
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row14_ps6 { /* NC */
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row15_ps7 { /* NC */
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row16_pt0 { /* NC */
+ nvidia,pins = "kb_row16_pt0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row17_pt1 { /* NC */
+ nvidia,pins = "kb_row17_pt1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu5 { /* NC */
+ nvidia,pins = "pu5";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /*
+ * PCB Version Indication: V1.2 and later have GPIO_PV0
+ * wired to GND, was NC before
+ */
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv1 { /* NC */
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x1_aud_px1 { /* NC */
+ nvidia,pins = "gpio_x1_aud_px1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x3_aud_px3 { /* NC */
+ nvidia,pins = "gpio_x3_aud_px3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb7 { /* NC */
+ nvidia,pins = "pbb7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 { /* NC */
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc2 { /* NC */
+ nvidia,pins = "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_req_pee1 { /* NC */
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap_mclk1_req_pee2 { /* NC */
+ nvidia,pins = "dap_mclk1_req_pee2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /*
+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+ * driver enabled aka not tristated and input driver
+ * enabled as well as it features some magic properties
+ * even though the external loopback is disabled and the
+ * internal loopback used as per
+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+ * bits being set to 0xfffd according to the TRM!
+ */
+ sdmmc3_clk_lb_out_pee4 { /* NC */
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ serial@70006040 {
+ compatible = "nvidia,tegra124-hsuart";
+ };
+
+ serial@70006200 {
+ compatible = "nvidia,tegra124-hsuart";
+ };
+
+ serial@70006300 {
+ compatible = "nvidia,tegra124-hsuart";
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ clock-frequency = <10000>;
+ };
+
+ /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* SGTL5000 audio codec */
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <&reg_3v3>;
+ VDDIO-supply = <&vddio_1v8>;
+ clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
+ };
+
+ pmic: pmic@40 {
+ compatible = "ams,as3722";
+ reg = <0x40>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ ams,system-power-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&as3722_default>;
+
+ as3722_default: pinmux {
+ gpio2_7 {
+ pins = "gpio2", /* PWR_EN_+V3.3 */
+ "gpio7"; /* +V1.6_LPO */
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio0_1_3_4_5_6 {
+ pins = "gpio0", "gpio1", "gpio3",
+ "gpio4", "gpio5", "gpio6";
+ bias-high-impedance;
+ };
+ };
+
+ regulators {
+ vsup-sd2-supply = <&reg_3v3>;
+ vsup-sd3-supply = <&reg_3v3>;
+ vsup-sd4-supply = <&reg_3v3>;
+ vsup-sd5-supply = <&reg_3v3>;
+ vin-ldo0-supply = <&vddio_ddr_1v35>;
+ vin-ldo1-6-supply = <&reg_3v3>;
+ vin-ldo2-5-7-supply = <&vddio_1v8>;
+ vin-ldo3-4-supply = <&reg_3v3>;
+ vin-ldo9-10-supply = <&reg_3v3>;
+ vin-ldo11-supply = <&reg_3v3>;
+
+ vdd_cpu: sd0 {
+ regulator-name = "+VDD_CPU_AP";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <2>;
+ };
+
+ sd1 {
+ regulator-name = "+VDD_CORE";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <4000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <1>;
+ };
+
+ vddio_ddr_1v35: sd2 {
+ regulator-name =
+ "+V1.35_VDDIO_DDR(sd2)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd3 {
+ regulator-name =
+ "+V1.35_VDDIO_DDR(sd3)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v05: sd4 {
+ regulator-name = "+V1.05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vddio_1v8: sd5 {
+ regulator-name = "+V1.8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_gpu: sd6 {
+ regulator-name = "+VDD_GPU_AP";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ avdd_1v05: ldo0 {
+ regulator-name = "+V1.05_AVDD";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,ext-control = <1>;
+ };
+
+ vddio_sdmmc1: ldo1 {
+ regulator-name = "VDDIO_SDMMC1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo2 {
+ regulator-name = "+V1.2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3 {
+ regulator-name = "+V1.05_RTC";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,enable-tracking;
+ };
+
+ /* 1.8V for LVDS, 3.3V for eDP */
+ ldo4 {
+ regulator-name = "AVDD_LVDS0_PLL";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ /* LDO5 not used */
+
+ vddio_sdmmc3: ldo6 {
+ regulator-name = "VDDIO_SDMMC3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* LDO7 not used */
+
+ ldo9 {
+ regulator-name = "+V3.3_ETH(ldo9)";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo10 {
+ regulator-name = "+V3.3_ETH(ldo10)";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo11 {
+ regulator-name = "+V1.8_VPP_FUSE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+
+ /*
+ * TMP451 temperature sensor
+ * Note: THERM_N directly connected to AS3722 PMIC THERM
+ */
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ /* SPI2: MCU SPI */
+ spi@7000d600 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <500>;
+ nvidia,cpu-pwr-off-time = <300>;
+ nvidia,core-pwr-good-time = <641 3845>;
+ nvidia,core-pwr-off-time = <61036>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+
+ /* Set power_off bit in ResetControl register of AS3722 PMIC */
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x40>;
+ nvidia,reg-addr = <0x36>;
+ nvidia,reg-data = <0x2>;
+ };
+ };
+
+ sata@70020000 {
+ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+ phy-names = "sata-0";
+ avdd-supply = <&vdd_1v05>;
+ hvdd-supply = <&reg_3v3>;
+ vddio-supply = <&vdd_1v05>;
+ };
+
+ usb@70090000 {
+ /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
+ phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
+ <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
+ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
+ phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
+ avddio-pex-supply = <&vdd_1v05>;
+ avdd-pll-erefe-supply = <&avdd_1v05>;
+ avdd-pll-utmip-supply = <&vddio_1v8>;
+ avdd-usb-ss-pll-supply = <&vdd_1v05>;
+ avdd-usb-supply = <&reg_3v3>;
+ dvddio-pex-supply = <&vdd_1v05>;
+ hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
+ hvdd-usb-ss-supply = <&reg_3v3>;
+ };
+
+ padctl@7009f000 {
+ pads {
+ usb2 {
+ status = "okay";
+
+ lanes {
+ usb2-0 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb2-1 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb2-2 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+ };
+ };
+
+ pcie {
+ status = "okay";
+
+ lanes {
+ pcie-0 {
+ nvidia,function = "usb3-ss";
+ status = "okay";
+ };
+
+ pcie-1 {
+ nvidia,function = "usb3-ss";
+ status = "okay";
+ };
+
+ pcie-2 {
+ nvidia,function = "pcie";
+ status = "okay";
+ };
+
+ pcie-3 {
+ nvidia,function = "pcie";
+ status = "okay";
+ };
+
+ pcie-4 {
+ nvidia,function = "pcie";
+ status = "okay";
+ };
+ };
+ };
+
+ sata {
+ status = "okay";
+
+ lanes {
+ sata-0 {
+ nvidia,function = "sata";
+ status = "okay";
+ };
+ };
+ };
+ };
+
+ ports {
+ /* USBO1 */
+ usb2-0 {
+ status = "okay";
+ mode = "otg";
+
+ vbus-supply = <&reg_usbo1_vbus>;
+ };
+
+ /* USBH2 */
+ usb2-1 {
+ status = "okay";
+ mode = "host";
+
+ vbus-supply = <&reg_usbh_vbus>;
+ };
+
+ /* USBH4 */
+ usb2-2 {
+ status = "okay";
+ mode = "host";
+
+ vbus-supply = <&reg_usbh_vbus>;
+ };
+
+ usb3-0 {
+ nvidia,usb2-companion = <2>;
+ status = "okay";
+ };
+
+ usb3-1 {
+ nvidia,usb2-companion = <0>;
+ status = "okay";
+ };
+ };
+ };
+
+ /* eMMC */
+ sdhci@700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ };
+
+ /* CPU DFLL clock */
+ clock@70110000 {
+ status = "okay";
+ vdd-cpu-supply = <&vdd_cpu>;
+ nvidia,i2c-fs-rate = <400000>;
+ };
+
+ ahub@70300000 {
+ i2s@70301200 {
+ status = "okay";
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ cpus {
+ cpu@0 {
+ vdd-cpu-supply = <&vdd_cpu>;
+ };
+ };
+
+ reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
+ compatible = "regulator-fixed";
+ regulator-name = "+V1.05_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05>;
+ };
+
+ reg_3v3_mxm: regulator-3v3-mxm {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_MXM";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ /* PWR_EN_+V3.3 */
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&reg_3v3_mxm>;
+ };
+
+ reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_AVDD_HDMI";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_1v05>;
+ };
+
+ sound {
+ compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
+ "nvidia,tegra-audio-sgtl5000";
+ nvidia,model = "Toradex Apalis TK1";
+ nvidia,audio-routing =
+ "Headphone Jack", "HP_OUT",
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack";
+ nvidia,i2s-controller = <&tegra_i2s2>;
+ nvidia,audio-codec = <&sgtl5000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
+
+ thermal-zones {
+ cpu {
+ trips {
+ cpu-shutdown-trip {
+ temperature = <101000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mem {
+ trips {
+ mem-shutdown-trip {
+ temperature = <101000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu {
+ trips {
+ gpu-shutdown-trip {
+ temperature = <101000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&gpio {
+ /* I210 Gigabit Ethernet Controller Reset */
+ lan_reset_n {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LAN_RESET_N";
+ };
+
+ /* Control MXM3 pin 26 Reset Module Output Carrier Input */
+ reset_moci_ctrl {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RESET_MOCI_CTRL";
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 5d9b18ef5af6..65a2161b9b8e 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2018 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -56,7 +56,6 @@
pcie@1003000 {
status = "okay";
-
avddio-pex-supply = <&vdd_1v05>;
avdd-pex-pll-supply = <&vdd_1v05>;
avdd-pll-erefe-supply = <&avdd_1v05>;
@@ -85,7 +84,6 @@
hdmi@54280000 {
pll-supply = <&reg_1v05_avdd_hdmi_pll>;
vdd-supply = <&reg_3v3_avdd_hdmi>;
-
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@@ -453,12 +451,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- /* PWM3 active on pu6 being Apalis BKL1_PWM */
+ /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
ph3 {
nvidia,pins = "ph3";
- nvidia,function = "gmi";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
@@ -1579,7 +1577,7 @@
};
hdmi_ddc: i2c@7000c400 {
- clock-frequency = <100000>;
+ clock-frequency = <10000>;
};
/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
@@ -1600,15 +1598,11 @@
compatible = "ams,as3722";
reg = <0x40>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-
ams,system-power-controller;
-
#interrupt-cells = <2>;
interrupt-controller;
-
gpio-controller;
#gpio-cells = <2>;
-
pinctrl-names = "default";
pinctrl-0 = <&as3722_default>;
@@ -1620,9 +1614,9 @@
bias-pull-up;
};
- gpio1_3_4_5_6 {
- pins = "gpio1", "gpio3", "gpio4",
- "gpio5", "gpio6";
+ gpio0_1_3_4_5_6 {
+ pins = "gpio0", "gpio1", "gpio3",
+ "gpio4", "gpio5", "gpio6";
bias-high-impedance;
};
};
@@ -1783,7 +1777,6 @@
reg = <0x4c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
-
#thermal-sensor-cells = <1>;
};
};
@@ -1816,7 +1809,6 @@
sata@70020000 {
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
phy-names = "sata-0";
-
avdd-supply = <&vdd_1v05>;
hvdd-supply = <&reg_3v3>;
vddio-supply = <&vdd_1v05>;
@@ -1830,7 +1822,6 @@
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
-
avddio-pex-supply = <&vdd_1v05>;
avdd-pll-erefe-supply = <&avdd_1v05>;
avdd-pll-utmip-supply = <&vddio_1v8>;
@@ -2041,53 +2032,50 @@
thermal-zones {
cpu {
trips {
- trip@0 {
+ cpu-shutdown-trip {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
-
- cooling-maps {
- /*
- * There are currently no cooling maps because
- * there are no cooling devices
- */
- };
};
mem {
trips {
- trip@0 {
+ mem-shutdown-trip {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
-
- cooling-maps {
- /*
- * There are currently no cooling maps because
- * there are no cooling devices
- */
- };
};
gpu {
trips {
- trip@0 {
+ gpu-shutdown-trip {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
-
- cooling-maps {
- /*
- * There are currently no cooling maps because
- * there are no cooling devices
- */
- };
};
};
};
+
+&gpio {
+ /* I210 Gigabit Ethernet Controller Reset */
+ lan_reset_n {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LAN_RESET_N";
+ };
+
+ /* Control MXM3 pin 26 Reset Module Output Carrier Input */
+ reset_moci_ctrl {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RESET_MOCI_CTRL";
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index d112f85e66ed..6dbcf84dafbc 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1418,7 +1418,7 @@
compatible = "realtek,rt5639";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 32d9079f025b..89bcc178994d 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -613,7 +613,7 @@
compatible = "maxim,max98090";
reg = <0x10>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
};
};
@@ -859,7 +859,7 @@
reg = <0x9>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(J, 0)
- GPIO_ACTIVE_HIGH>;
+ IRQ_TYPE_EDGE_BOTH>;
ti,ac-detect-gpios = <&gpio
TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
@@ -956,11 +956,6 @@
nvidia,function = "usb3-ss";
status = "okay";
};
-
- pcie-1 {
- nvidia,function = "usb3-ss";
- status = "okay";
- };
};
};
};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 813ae34edd6a..5c202b3e3bb1 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -213,21 +213,27 @@
GPIO_ACTIVE_HIGH>;
};
+ /*
+ * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+ * board)
+ */
i2c@7000c000 {
clock-frequency = <400000>;
};
+ /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
i2c_ddc: i2c@7000c400 {
- clock-frequency = <100000>;
+ clock-frequency = <10000>;
};
- i2c@7000c500 {
- clock-frequency = <400000>;
- };
+ /* GEN2_I2C: unused */
+ /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
+
+ /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
i2c@7000d000 {
status = "okay";
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 864a95872b8d..0a7136462a1a 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -17,7 +17,7 @@
#size-cells = <1>;
ranges = <0 0x40000000 0x40000>;
- vde_pool: vde {
+ vde_pool: vde@400 {
reg = <0x400 0x3fc00>;
pool;
};
@@ -741,7 +741,7 @@
phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
- <&tegra_car TEGRA20_CLK_CDEV2>;
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT4>;
clock-names = "reg", "pll_u", "ulpi-link";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 07b945b0391a..0dc85a20bd45 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -79,7 +79,7 @@
*/
i2c@7000c000 {
status = "okay";
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
pcie-switch@58 {
compatible = "plx,pex8605";
@@ -88,7 +88,7 @@
/* M41T0M6 real time clock on carrier board */
rtc@68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index faa8cd2914e8..d1d21ec2a844 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -437,7 +437,7 @@
};
hdmiddc: i2c@7000c700 {
- clock-frequency = <100000>;
+ clock-frequency = <10000>;
};
/*
@@ -597,7 +597,6 @@
stmpe_touchscreen@0 {
compatible = "st,stmpe-ts";
- reg = <0>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 8 sample average control */
@@ -657,7 +656,7 @@
reg = <1>;
clocks = <&clk16m>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <10000000>;
};
};
@@ -672,7 +671,7 @@
reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <10000000>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 5331a8f7dcf8..ae52a5039506 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -260,14 +260,14 @@
};
sdmmc3_dat6_pd3 {
nvidia,pins = "sdmmc3_dat6_pd3";
- nvidia,function = "rsvd1";
+ nvidia,function = "spdif";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc3_dat7_pd4 {
nvidia,pins = "sdmmc3_dat7_pd4";
- nvidia,function = "rsvd1";
+ nvidia,function = "spdif";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -281,14 +281,14 @@
};
vi_vsync_pd6 {
nvidia,pins = "vi_vsync_pd6";
- nvidia,function = "rsvd1";
+ nvidia,function = "ddr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
vi_hsync_pd7 {
nvidia,pins = "vi_hsync_pd7";
- nvidia,function = "rsvd1";
+ nvidia,function = "ddr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -806,7 +806,7 @@
};
hdmi_int_pn7 {
nvidia,pins = "hdmi_int_pn7";
- nvidia,function = "rsvd1";
+ nvidia,function = "hdmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -841,7 +841,7 @@
};
ulpi_data3_po4 {
nvidia,pins = "ulpi_data3_po4";
- nvidia,function = "rsvd1";
+ nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1107,21 +1107,21 @@
};
vi_d10_pt2 {
nvidia,pins = "vi_d10_pt2";
- nvidia,function = "rsvd1";
+ nvidia,function = "ddr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
vi_d11_pt3 {
nvidia,pins = "vi_d11_pt3";
- nvidia,function = "rsvd1";
+ nvidia,function = "ddr";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
vi_d0_pt4 {
nvidia,pins = "vi_d0_pt4";
- nvidia,function = "rsvd1";
+ nvidia,function = "ddr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1151,7 +1151,7 @@
};
pu0 {
nvidia,pins = "pu0";
- nvidia,function = "rsvd1";
+ nvidia,function = "owr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1172,7 +1172,7 @@
};
pu3 {
nvidia,pins = "pu3";
- nvidia,function = "rsvd1";
+ nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1193,7 +1193,7 @@
};
pu6 {
nvidia,pins = "pu6";
- nvidia,function = "rsvd1";
+ nvidia,function = "pwm3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1221,7 +1221,7 @@
};
pv3 {
nvidia,pins = "pv3";
- nvidia,function = "rsvd1";
+ nvidia,function = "clk_12m_out";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1510,7 +1510,7 @@
};
pbb0 {
nvidia,pins = "pbb0";
- nvidia,function = "rsvd1";
+ nvidia,function = "i2s4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1575,7 +1575,7 @@
};
pcc1 {
nvidia,pins = "pcc1";
- nvidia,function = "rsvd1";
+ nvidia,function = "i2s4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1762,7 +1762,7 @@
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_FALLING>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 3c5fb2430212..16e1f387aa6d 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -56,11 +56,11 @@
*/
i2c@7000c000 {
status = "okay";
- clock-frequency = <100000>;
+ clock-frequency = <400000>;
/* M41T0M6 real time clock on carrier board */
rtc@68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
@@ -79,7 +79,7 @@
reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <10000000>;
};
spidev0: spi@1 {
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 139bfa028b04..c44d8c40c410 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -215,7 +215,7 @@
};
hdmiddc: i2c@7000c700 {
- clock-frequency = <100000>;
+ clock-frequency = <10000>;
};
/*
@@ -363,7 +363,6 @@
stmpe_touchscreen {
compatible = "st,stmpe-ts";
- reg = <0>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 8 sample average control */
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c3e9f1e847db..a110cf84d85f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -91,6 +91,19 @@
};
};
+ iram@40000000 {
+ compatible = "mmio-sram";
+ reg = <0x40000000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000000 0x40000>;
+
+ vde_pool: vde@400 {
+ reg = <0x400 0x3fc00>;
+ pool;
+ };
+ };
+
host1x@50000000 {
compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
@@ -358,6 +371,28 @@
*/
};
+ vde@6001a000 {
+ compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
+ reg = <0x6001a000 0x1000 /* Syntax Engine */
+ 0x6001b000 0x1000 /* Video Bitstream Engine */
+ 0x6001c000 0x100 /* Macroblock Engine */
+ 0x6001c200 0x100 /* Post-processing Engine */
+ 0x6001c400 0x100 /* Motion Compensation Engine */
+ 0x6001c600 0x100 /* Transform Engine */
+ 0x6001c800 0x100 /* Pixel prediction block */
+ 0x6001ca00 0x100 /* Video DMA */
+ 0x6001d800 0x400>; /* Video frame controls */
+ reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
+ "tfe", "ppb", "vdma", "frameid";
+ iram = <&vde_pool>; /* IRAM region */
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
+ interrupt-names = "sync-token", "bsev", "sxe";
+ clocks = <&tegra_car TEGRA30_CLK_VDE>;
+ resets = <&tegra_car 61>;
+ };
+
apbmisc@70000800 {
compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64 /* Chip revision */
diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
index a3afd0cda42f..21407e159bf7 100644
--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD4 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD4 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld4.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 0459e84d4d8e..37950ad2de7c 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD4 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD4 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
index 811b999800ed..a0a44a422e12 100644
--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD6b Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD6b Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld6b.dtsi"
@@ -67,6 +65,17 @@
status = "okay";
};
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@0 {
+ reg = <0>;
+ };
+};
+
&nand {
status = "okay";
};
diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi
index 9a7b25cc8233..4d07a94c6b34 100644
--- a/arch/arm/boot/dts/uniphier-ld6b.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld6b.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD6b SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD6b SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/*
* LD6b consists of two silicon dies: D-chip and A-chip.
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index de481c372467..51f0e69f49fd 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier SoCs default pinctrl settings
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier SoCs default pinctrl settings
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&pinctrl {
pinctrl_aout: aout {
@@ -13,6 +11,46 @@
function = "aout";
};
+ pinctrl_ain1: ain1 {
+ groups = "ain1";
+ function = "ain1";
+ };
+
+ pinctrl_ain2: ain2 {
+ groups = "ain2";
+ function = "ain2";
+ };
+
+ pinctrl_ainiec1: ainiec1 {
+ groups = "ainiec1";
+ function = "ainiec1";
+ };
+
+ pinctrl_aout1: aout1 {
+ groups = "aout1";
+ function = "aout1";
+ };
+
+ pinctrl_aout2: aout2 {
+ groups = "aout2";
+ function = "aout2";
+ };
+
+ pinctrl_aout3: aout3 {
+ groups = "aout3";
+ function = "aout3";
+ };
+
+ pinctrl_aoutiec1: aoutiec1 {
+ groups = "aoutiec1";
+ function = "aoutiec1";
+ };
+
+ pinctrl_aoutiec2: aoutiec2 {
+ groups = "aoutiec2";
+ function = "aoutiec2";
+ };
+
pinctrl_emmc: emmc {
groups = "emmc", "emmc_dat8";
function = "emmc";
@@ -33,6 +71,16 @@
function = "ether_rmii";
};
+ pinctrl_ether1_rgmii: ether1-rgmii {
+ groups = "ether1_rgmii";
+ function = "ether1_rgmii";
+ };
+
+ pinctrl_ether1_rmii: ether1-rmii {
+ groups = "ether1_rmii";
+ function = "ether1_rmii";
+ };
+
pinctrl_i2c0: i2c0 {
groups = "i2c0";
function = "i2c0";
diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
index 089419cee273..db1b08935ae5 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 Ace Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Ace Board
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
@@ -77,3 +75,14 @@
&usb3 {
status = "okay";
};
+
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
index 6a004e5cf786..efb084983b82 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
@@ -75,6 +73,17 @@
status = "okay";
};
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@0 {
+ reg = <0>;
+ };
+};
+
&nand {
status = "okay";
};
diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
index adef212b45b2..dac4d6679a32 100644
--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 Sanji Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Sanji Board
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
@@ -72,3 +70,14 @@
&usb3 {
status = "okay";
};
+
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 1a29a8619856..844124bc9c9c 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -366,6 +364,24 @@
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-pro4-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index f291dd63de9c..06c2cef91ec7 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro5 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro5 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/ {
compatible = "socionext,uniphier-pro5";
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index 7dfae2667f50..bed26b8ed9a3 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs2 Gentil Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 Gentil Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs2.dtsi"
@@ -34,6 +32,12 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier PXs2";
+ dais = <&i2s_port2>;
+ };
};
&serial2 {
@@ -50,6 +54,35 @@
};
};
+&i2s_aux {
+ dai-format = "i2s";
+ remote-endpoint = <&wm_speaker>;
+};
+
&i2c2 {
status = "okay";
+
+ wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ wm_speaker: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&i2s_aux>;
+ };
+ };
+ };
+};
+
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
};
diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
index 0cf615463a82..b13d2d16ddad 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs2 Vodka Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 Vodka Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs2.dtsi"
@@ -32,12 +30,60 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier PXs2";
+ dais = <&spdif_port0
+ &comp_spdif_port0>;
+ };
+
+ spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ spdif_tx: endpoint {
+ remote-endpoint = <&spdif_hiecout1>;
+ };
+ };
+ };
+
+ comp-spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ comp_spdif_tx: endpoint {
+ remote-endpoint = <&comp_spdif_hiecout1>;
+ };
+ };
+ };
};
&serial2 {
status = "okay";
};
+&spdif_hiecout1 {
+ remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+ remote-endpoint = <&comp_spdif_tx>;
+};
+
&i2c0 {
status = "okay";
};
+
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index c083468c17db..debcbd15c24b 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs2 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>
@@ -227,6 +225,61 @@
<21 217 3>;
};
+ audio@56000000 {
+ compatible = "socionext,uniphier-pxs2-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ain1>,
+ <&pinctrl_ain2>,
+ <&pinctrl_ainiec1>,
+ <&pinctrl_aout2>,
+ <&pinctrl_aout3>,
+ <&pinctrl_aoutiec1>,
+ <&pinctrl_aoutiec2>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_line: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_aux: endpoint {
+ };
+ };
+
+ spdif_port0: port@3 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ spdif_port1: port@4 {
+ spdif_iecout1: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@5 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+
+ comp_spdif_port1: port@6 {
+ comp_spdif_iecout1: endpoint {
+ };
+ };
+ };
+
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
@@ -366,7 +419,7 @@
};
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -446,6 +499,24 @@
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-pxs2-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
index 7a1c29b558d5..04e60c295319 100644
--- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Reference Daughter Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Reference Daughter Board
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&i2c0 {
eeprom@50 {
diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
index e052ea3b4020..fe386fa2ea4b 100644
--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier sLD8 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier sLD8 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-sld8.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index bc8c24078faa..e9b9b4f3c558 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier sLD8 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier sLD8 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index e4e7e1bb9172..bf441c2eff79 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Support Card (Expansion Board)
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Support Card (Expansion Board)
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&system_bus {
status = "okay";
diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts
new file mode 100644
index 000000000000..5890cb974f78
--- /dev/null
+++ b/arch/arm/boot/dts/versatile-ab-ib2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The Versatile AB with the IB2 expansion board mounted.
+ * This works as a superset of the Versatile AB.
+ */
+
+#include "versatile-ab.dts"
+
+/ {
+ model = "ARM Versatile AB + IB2 board";
+
+ /* Special IB2 control register */
+ ib2_syscon@27000000 {
+ compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd";
+ reg = <0x27000000 0x4>;
+
+ led@00.4 {
+ compatible = "register-bit-led";
+ offset = <0x00>;
+ mask = <0x10>;
+ label = "versatile-ib2:0";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 4a51612996bc..5f61d3609027 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -30,6 +30,43 @@
clock-frequency = <24000000>;
};
+ bridge {
+ compatible = "ti,ths8134b", "ti,ths8134";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&clcd_pads_vga_dac>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+
core-module@10000000 {
compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
reg = <0x10000000 0x200>;
@@ -230,7 +267,39 @@
reg = <0x10120000 0x1000>;
interrupts = <16>;
clocks = <&osc1>, <&pclk>;
- clock-names = "clcd", "apb_pclk";
+ clock-names = "clcdclk", "apb_pclk";
+ /* 800x600 16bpp @ 36MHz works fine */
+ max-memory-bandwidth = <54000000>;
+
+ /*
+ * This port is routed through a PLD (Programmable
+ * Logic Device) that routes the output from the CLCD
+ * (after transformations) to the VGA DAC and also an
+ * external panel connector. The PLD is essential for
+ * supporting RGB565/BGR565.
+ *
+ * The signals from the port thus reaches two endpoints.
+ * The PLD is managed through a few special bits in the
+ * FPGA "sysreg".
+ *
+ * This arrangement can be clearly seen in
+ * ARM DUI 0225D, page 3-41, figure 3-19.
+ */
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clcd_pads_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in>;
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+ };
+ clcd_pads_vga_dac: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vga_bridge_in>;
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+ };
+ };
};
sctl@101e0000 {
@@ -319,8 +388,18 @@
ranges = <0 0x10000000 0x10000>;
sysreg@0 {
- compatible = "arm,versatile-sysreg", "syscon";
+ compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
reg = <0x00000 0x1000>;
+
+ panel: display@0 {
+ compatible = "arm,versatile-tft-panel";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&clcd_pads_panel>;
+ };
+ };
+ };
};
aaci@4000 {
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
index 515c4d2f28b0..2e7e3cebba1c 100644
--- a/arch/arm/boot/dts/vf500-colibri.dtsi
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -46,7 +46,7 @@
model = "Toradex Colibri VF50 COM";
compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x8000000>;
};
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 348bcd30c0f7..bbff0115e2fb 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -39,11 +39,16 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include "vfxxx.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 395812c52933..aeaf99f1f0fc 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -46,7 +46,7 @@
model = "Toradex Colibri VF61 COM";
compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
- memory {
+ memory@80000000 {
reg = <0x80000000 0x10000000>;
};
};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 5447f2594659..a3014e8d97a9 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyLP1,115200";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x10000000>;
};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 6f787e67bd2e..6be7a828ae64 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -50,7 +50,7 @@
bootargs = "console=ttyLP1,115200";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x8000000>;
};
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index aadd36db0092..4890b8a5aa44 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -49,7 +49,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts
index 7198e8cceb0d..41ec66a96990 100644
--- a/arch/arm/boot/dts/vf610m4-colibri.dts
+++ b/arch/arm/boot/dts/vf610m4-colibri.dts
@@ -51,10 +51,10 @@
chosen {
bootargs = "console=ttyLP2,115200 clk_ignore_unused init=/linuxrc rw";
- linux,stdout-path = "&uart2";
+ stdout-path = "&uart2";
};
- memory {
+ memory@8c000000 {
reg = <0x8c000000 0x3000000>;
};
};
diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi
index 1474bd34d0f1..8293276b55a6 100644
--- a/arch/arm/boot/dts/vf610m4.dtsi
+++ b/arch/arm/boot/dts/vf610m4.dtsi
@@ -42,10 +42,17 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include "vfxxx.dtsi"
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; };
+};
+
&mscm_ir {
interrupt-parent = <&nvic>;
};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 0f79fe1ccd9d..e22507e23303 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2011 - 2014 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * Copyright (C) 2011 - 2014 Xilinx
*/
/ {
diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/zynq-cc108.dts
new file mode 100644
index 000000000000..1a0f631c1d8d
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-cc108.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CC108 board DTS
+ *
+ * (C) Copyright 2007-2018 Xilinx, Inc.
+ * (C) Copyright 2007-2013 Michal Simek
+ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: phy1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ ethernet_phy: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&sdhci1 {
+ status = "okay";
+ broken-cd ;
+ wp-inverted ;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy1>;
+};
diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
index b9376a4904b4..aa4a0b6defb8 100644
--- a/arch/arm/boot/dts/zynq-microzed.dts
+++ b/arch/arm/boot/dts/zynq-microzed.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
@@ -23,7 +15,7 @@
serial0 = &uart1;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 0144acfa9793..c05f4b67d4c1 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014 SUSE LINUX Products GmbH
*
@@ -6,15 +7,6 @@
* Copyright (C) 2011 Xilinx
* Copyright (C) 2012 National Instruments Corp.
* Copyright (C) 2013 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 70a5de76b7db..f2330b0cb63d 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -112,7 +104,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
- i2cswitch@74 {
+ i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index cdc326ec3335..3ad1260ff2a1 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
@@ -68,7 +60,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
- i2cswitch@74 {
+ i2c-mux@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts
new file mode 100644
index 000000000000..6884f1ad66b7
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm010.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM010 board DTS
+ *
+ * Copyright (C) 2013-2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
+ serial0 = &uart1;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ ethernet_phy: ethernet-phy@7 {
+ reg = <7>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ flash@0 {
+ compatible = "sst25wf080", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "data";
+ reg = <0x0 0x100000>;
+ };
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts
new file mode 100644
index 000000000000..b78883cee96a
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013-2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ i2c0 = &i2c1;
+ serial0 = &uart1;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ usb_phy1: phy1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy1>;
+};
diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/zynq-zc770-xm012.dts
new file mode 100644
index 000000000000..c3169d63600d
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm012.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM012 board DTS
+ *
+ * Copyright (C) 2013-2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ serial0 = &uart1;
+ spi0 = &spi1;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom0: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom1: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts
new file mode 100644
index 000000000000..8bb66859d774
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ ethernet0 = &gem1;
+ i2c0 = &i2c1;
+ serial0 = &uart0;
+ spi1 = &spi0;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ ethernet_phy: ethernet-phy@7 {
+ reg = <7>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ si570: clock-generator@55 {
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ temperature-stability = <50>;
+ reg = <0x55>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ eeprom: eeprom@0 {
+ at25,byte-len = <8192>;
+ at25,addr-mode = <2>;
+ at25,page-size = <32>;
+
+ compatible = "atmel,at25";
+ reg = <2>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 5e44dc12fd60..53c6883ce1f6 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts
new file mode 100644
index 000000000000..1e713dc98920
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo-z7.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZYBO Z7 Development Board";
+ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 46 1>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
index e40cafc5ee5b..a6c00e7fa767 100644
--- a/arch/arm/boot/dts/zynq-zybo.dts
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2011 - 2014 Xilinx
* Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 43dab4890ad3..8682b15336b9 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -49,6 +49,9 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NETFILTER=y
+CONFIG_BT=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_DEVTMPFS=y
@@ -74,6 +77,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_BCM2835AUX=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
CONFIG_TTY_PRINTK=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_BCM2835=y
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
index c0418e03d180..5e349c625b71 100644
--- a/arch/arm/configs/cm_x300_defconfig
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -49,7 +49,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PXA3xx=y
+CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 026154c1d55a..c302a04e8cbc 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -126,9 +126,10 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
+CONFIG_SYSCON_REBOOT_MODE=m
CONFIG_BATTERY_LEGO_EV3=m
CONFIG_WATCHDOG=y
-CONFIG_DAVINCI_WATCHDOG=m
+CONFIG_DAVINCI_WATCHDOG=y
CONFIG_MFD_DM355EVM_MSP=y
CONFIG_TPS6507X=y
CONFIG_REGULATOR=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index ca0f13cafe38..054591dc9a00 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -1,7 +1,6 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
-CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
@@ -78,7 +77,6 @@ CONFIG_SMC91X=y
CONFIG_SMC911X=y
CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
-# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_IMX=y
@@ -105,8 +103,8 @@ CONFIG_HWMON=m
CONFIG_SENSORS_MC13783_ADC=m
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
-CONFIG_MFD_MX25_TSADC=y
CONFIG_MFD_MC13XXX_SPI=y
+CONFIG_MFD_MX25_TSADC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
@@ -116,10 +114,8 @@ CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
-CONFIG_VIDEO_MX2=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=y
-CONFIG_SOC_CAMERA_OV2640=y
CONFIG_FB=y
CONFIG_FB_IMX=y
CONFIG_LCD_L4F00242T03=y
@@ -134,8 +130,9 @@ CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_MX27VIS_AIC32X4=y
CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_EUKREA_TLV320=y
-CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_MC13783=y
+CONFIG_SND_SOC_FSL_ASOC_CARD=y
+CONFIG_SND_SOC_SGTL5000=y
CONFIG_USB_HID=m
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 4cb9829fccd1..3a308437b088 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -48,9 +48,7 @@ CONFIG_PCI_IMX6=y
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_KEXEC=y
@@ -60,6 +58,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
@@ -81,7 +80,6 @@ CONFIG_CAN=y
CONFIG_CAN_FLEXCAN=y
CONFIG_BT=y
CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_LL=y
CONFIG_CFG80211=y
@@ -92,7 +90,6 @@ CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
-CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
@@ -170,9 +167,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2007=y
@@ -181,7 +178,6 @@ CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
-CONFIG_HID_MULTITOUCH=y
CONFIG_SERIO_SERPORT=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_IMX=y
@@ -189,7 +185,6 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
@@ -209,19 +204,19 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_74X164=y
CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_IMX=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_IIO_HWMON=y
-CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_CPU_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_WATCHDOG=y
+CONFIG_DA9062_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_DA9052_I2C=y
+CONFIG_MFD_DA9062=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_MFD_STMPE=y
@@ -229,17 +224,18 @@ CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ANATOP=y
CONFIG_REGULATOR_DA9052=y
+CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_RC_CORE=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_RC_DEVICES=y
-CONFIG_IR_GPIO_CIR=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -250,7 +246,6 @@ CONFIG_VIDEO_CODA=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_OV5640=m
-CONFIG_SOC_CAMERA_OV2640=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_LVDS=y
@@ -285,10 +280,13 @@ CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_SPDIF=y
CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_SOC_FSL_ASOC_CARD=y
+CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_MULTITOUCH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
@@ -354,6 +352,7 @@ CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_PCF8523=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_M41T80=y
+CONFIG_RTC_DRV_DA9063=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_MXC_V2=y
@@ -369,11 +368,14 @@ CONFIG_COMMON_CLK_PWM=y
CONFIG_IIO=y
CONFIG_IMX7D_ADC=y
CONFIG_VF610_ADC=y
+CONFIG_MAG3110=y
CONFIG_MPL3115=y
CONFIG_PWM=y
CONFIG_PWM_FSL_FTM=y
CONFIG_PWM_IMX=y
CONFIG_NVMEM_IMX_OCOTP=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
CONFIG_MUX_MMIO=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index da7387689b88..e6b3c96d4c09 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -80,6 +80,7 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
CONFIG_ARCH_STI=y
+CONFIG_ARCH_STM32=y
CONFIG_ARCH_EXYNOS=y
CONFIG_EXYNOS5420_MCPM=y
CONFIG_ARCH_RENESAS=y
@@ -174,6 +175,7 @@ CONFIG_CAN_RAW=y
CONFIG_CAN_BCM=y
CONFIG_CAN_DEV=y
CONFIG_CAN_AT91=m
+CONFIG_CAN_FLEXCAN=m
CONFIG_CAN_RCAR=m
CONFIG_CAN_XILINXCAN=y
CONFIG_CAN_MCP251X=y
@@ -208,6 +210,7 @@ CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_BRCMNAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_DAVINCI=y
@@ -307,11 +310,15 @@ CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MAX77693_HAPTIC=m
CONFIG_INPUT_MAX8997_HAPTIC=m
+CONFIG_INPUT_CPCAP_PWRBUTTON=m
CONFIG_INPUT_AXP20X_PEK=m
CONFIG_INPUT_ADXL34X=m
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_BCM2835AUX=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_8250_MT6577=y
@@ -351,6 +358,8 @@ CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
CONFIG_SERIAL_ST_ASC=y
CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_SERIAL_STM32=y
+CONFIG_SERIAL_STM32_CONSOLE=y
CONFIG_HVC_DRIVER=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_I2C_CHARDEV=y
@@ -368,7 +377,7 @@ CONFIG_I2C_DIGICOLOR=m
CONFIG_I2C_EMEV2=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_EXYNOS5=y
-CONFIG_I2C_IMX=m
+CONFIG_I2C_IMX=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_RIIC=y
CONFIG_I2C_RK3X=y
@@ -438,9 +447,11 @@ CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_BATTERY_ACT8945A=y
+CONFIG_BATTERY_CPCAP=m
CONFIG_BATTERY_SBS=y
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=m
+CONFIG_CHARGER_CPCAP=m
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_MAX8997=m
@@ -462,7 +473,9 @@ CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_PWM_FAN=m
CONFIG_SENSORS_INA2XX=m
CONFIG_CPU_THERMAL=y
+CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
+CONFIG_IMX_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
@@ -476,6 +489,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_SAMA5D4_WATCHDOG=y
CONFIG_ORION_WATCHDOG=y
+CONFIG_RN5T618_WATCHDOG=y
CONFIG_ST_LPC_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
CONFIG_IMX2_WDT=y
@@ -508,9 +522,11 @@ CONFIG_MFD_MAX8907=y
CONFIG_MFD_MAX8997=y
CONFIG_MFD_MAX8998=y
CONFIG_MFD_RK808=y
+CONFIG_MFD_CPCAP=y
CONFIG_MFD_PM8XXX=y
CONFIG_MFD_QCOM_RPM=y
CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_RN5T618=y
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_PALMAS=y
@@ -527,6 +543,7 @@ CONFIG_REGULATOR_AS3711=y
CONFIG_REGULATOR_AS3722=y
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BCM590XX=y
+CONFIG_REGULATOR_CPCAP=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_RK808=y
@@ -547,6 +564,7 @@ CONFIG_REGULATOR_PBIAS=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_RPM=y
CONFIG_REGULATOR_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_RN5T618=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_TI_ABB=y
@@ -617,6 +635,7 @@ CONFIG_DRM_ATMEL_HLCDC=m
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_RCAR_LVDS=y
CONFIG_DRM_SUN4I=m
+CONFIG_DRM_FSL_DCU=m
CONFIG_DRM_TEGRA=y
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
@@ -624,6 +643,8 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_SII9234=m
CONFIG_DRM_STI=m
CONFIG_DRM_VC4=y
+CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_MXSFB=m
CONFIG_FB_ARMCLCD=y
CONFIG_FB_EFI=y
CONFIG_FB_WM8505=y
@@ -674,6 +695,7 @@ CONFIG_SND_SOC_TEGRA_WM8903=m
CONFIG_SND_SOC_TEGRA_WM9712=m
CONFIG_SND_SOC_TEGRA_TRIMSLICE=m
CONFIG_SND_SOC_TEGRA_ALC5632=m
+CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SOC_TEGRA_MAX98090=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_SGTL5000=m
@@ -683,6 +705,7 @@ CONFIG_SND_SOC_STI=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_USB=y
+CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_RCAR=m
@@ -704,6 +727,15 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=m
CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_SUNXI=m
+CONFIG_USB_MUSB_TUSB6010=m
+CONFIG_USB_MUSB_OMAP2PLUS=m
+CONFIG_USB_MUSB_AM35X=m
+CONFIG_USB_MUSB_DSPS=m
+CONFIG_USB_MUSB_UX500=m
+CONFIG_USB_UX500_DMA=y
+CONFIG_USB_INVENTRA_DMA=y
+CONFIG_USB_TI_CPPI41_DMA=y
+CONFIG_USB_TUSB_OMAP_DMA=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC2=y
CONFIG_USB_HSIC_USB3503=y
@@ -712,6 +744,9 @@ CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_AB8500_USB=y
CONFIG_KEYSTONE_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_AM335X_PHY_USB=m
+CONFIG_TWL6030_USB=m
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=y
CONFIG_USB_MSM_OTG=m
@@ -719,6 +754,25 @@ CONFIG_USB_MXS_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_FSL_USB2=y
CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
@@ -751,9 +805,11 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_MAX77693=m
@@ -804,6 +860,7 @@ CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_SUNXI=y
CONFIG_RTC_DRV_MV=y
CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_CPCAP=m
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_AT_HDMAC=y
@@ -876,6 +933,7 @@ CONFIG_IIO_SW_TRIGGER=y
CONFIG_AT91_ADC=m
CONFIG_AT91_SAMA5D2_ADC=m
CONFIG_BERLIN2_ADC=m
+CONFIG_CPCAP_ADC=m
CONFIG_EXYNOS_ADC=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=y
@@ -901,9 +959,12 @@ CONFIG_E1000E=y
CONFIG_PWM_STI=y
CONFIG_PWM_BCM2835=y
CONFIG_PWM_BRCMSTB=m
+CONFIG_PHY_DM816X_USB=m
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
+CONFIG_TWL4030_USB=m
CONFIG_PHY_BERLIN_USB=y
+CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_BERLIN_SATA=y
CONFIG_PHY_ROCKCHIP_DP=m
CONFIG_PHY_ROCKCHIP_USB=y
@@ -917,7 +978,9 @@ CONFIG_PHY_SAMSUNG_USB2=m
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_PHY_BRCM_SATA=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_BCM2835_MBOX=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_EFI_VARS=m
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index bbfb6759447b..a508eb302e7a 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,5 +1,4 @@
CONFIG_SYSVIPC=y
-CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TASKSTATS=y
@@ -62,14 +61,13 @@ CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_ENC28J60=y
-CONFIG_SMSC_PHY=y
CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
CONFIG_MICREL_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_SMSC_PHY=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC95XX=y
# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
@@ -77,9 +75,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_MXS_LRADC=y
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_SERIO is not set
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_MXS_AUART=y
@@ -138,11 +134,10 @@ CONFIG_RTC_DRV_STMP=y
CONFIG_DMADEVICES=y
CONFIG_MXS_DMA=y
CONFIG_IIO=y
-CONFIG_IIO_SYSFS_TRIGGER=y
CONFIG_MXS_LRADC_ADC=y
+CONFIG_IIO_SYSFS_TRIGGER=y
CONFIG_PWM=y
CONFIG_PWM_MXS=y
-CONFIG_NVMEM=y
CONFIG_NVMEM_MXS_OCOTP=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
@@ -172,8 +167,7 @@ CONFIG_FRAME_WARN=2048
CONFIG_UNUSED_SYMBOLS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_TIMER_STATS=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_PROVE_LOCKING=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_STRICT_DEVMEM=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 92674f247a12..6491419b1dad 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -50,7 +50,6 @@ CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
-CONFIG_PCI_DRA7XX=y
CONFIG_PCI_DRA7XX_EP=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
@@ -71,9 +70,10 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPUFREQ_DT=m
-CONFIG_ARM_TI_CPUFREQ=y
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
+CONFIG_ARM_TI_CPUFREQ=y
CONFIG_CPU_IDLE=y
+CONFIG_KERNEL_MODE_NEON=y
CONFIG_BINFMT_MISC=y
CONFIG_PM_DEBUG=y
CONFIG_NET=y
@@ -103,9 +103,11 @@ CONFIG_BT_HIDP=m
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
@@ -232,7 +234,9 @@ CONFIG_INPUT_MISC=y
CONFIG_INPUT_CPCAP_PWRBUTTON=m
CONFIG_INPUT_TPS65218_PWRBUTTON=m
CONFIG_INPUT_TWL4030_PWRBUTTON=m
+CONFIG_INPUT_UINPUT=m
CONFIG_INPUT_PALMAS_PWRBUTTON=m
+CONFIG_INPUT_PWM_VIBRA=m
CONFIG_SERIO=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
@@ -244,9 +248,11 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_OMAP=y
CONFIG_SERIAL_OMAP_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SPI_OMAP24XX=y
@@ -291,6 +297,7 @@ CONFIG_OMAP_WATCHDOG=m
CONFIG_TWL4030_WATCHDOG=m
CONFIG_MFD_CPCAP=y
CONFIG_MFD_TI_AM335X_TSCADC=m
+CONFIG_MFD_TI_LMU=m
CONFIG_MFD_PALMAS=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TI_LP873X=y
@@ -314,40 +321,47 @@ CONFIG_REGULATOR_TPS65217=y
CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_TWL4030=y
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_RC_CORE=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_LIRC=y
CONFIG_RC_DEVICES=y
+CONFIG_IR_SPI=m
CONFIG_IR_RX51=m
+CONFIG_IR_GPIO_TX=m
+CONFIG_IR_PWM_TX=m
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_OMAP3=m
+CONFIG_CEC_PLATFORM_DRIVERS=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_TVP5150=m
+CONFIG_DRM=m
+CONFIG_DRM_OMAP=m
+CONFIG_OMAP5_DSS_HDMI=y
+CONFIG_OMAP2_DSS_SDI=y
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_DRM_OMAP_ENCODER_OPA362=m
+CONFIG_DRM_OMAP_ENCODER_TFP410=m
+CONFIG_DRM_OMAP_ENCODER_TPD12S015=m
+CONFIG_DRM_OMAP_CONNECTOR_DVI=m
+CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
+CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
+CONFIG_DRM_OMAP_PANEL_DPI=m
+CONFIG_DRM_OMAP_PANEL_DSI_CM=m
+CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
+CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
+CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
+CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
+CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
+CONFIG_DRM_TILCDC=m
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_OMAP2=m
-CONFIG_FB_OMAP5_DSS_HDMI=y
-CONFIG_FB_OMAP2_DSS_SDI=y
-CONFIG_FB_OMAP2_DSS_DSI=y
-CONFIG_FB_OMAP2_ENCODER_TFP410=m
-CONFIG_FB_OMAP2_ENCODER_TPD12S015=m
-CONFIG_FB_OMAP2_CONNECTOR_DVI=m
-CONFIG_FB_OMAP2_CONNECTOR_HDMI=m
-CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV=m
-CONFIG_FB_OMAP2_PANEL_DPI=m
-CONFIG_FB_OMAP2_PANEL_DSI_CM=m
-CONFIG_FB_OMAP2_PANEL_SONY_ACX565AKM=m
-CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02=m
-CONFIG_FB_OMAP2_PANEL_SHARP_LS037V7DW01=m
-CONFIG_FB_OMAP2_PANEL_TPO_TD028TTEC1=m
-CONFIG_FB_OMAP2_PANEL_TPO_TD043MTEA1=m
-CONFIG_FB_OMAP2_PANEL_NEC_NL8048HL11=m
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -356,11 +370,11 @@ CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_PANDORA=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
+CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_VERBOSE_PRINTK=y
@@ -374,7 +388,9 @@ CONFIG_SND_OMAP_SOC_HDMI_AUDIO=m
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
+CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_HID_GENERIC=m
CONFIG_USB_HIDDEV=y
CONFIG_USB_KBD=m
@@ -385,7 +401,6 @@ CONFIG_USB_MON=m
CONFIG_USB_XHCI_HCD=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_WDM=m
CONFIG_USB_ACM=m
CONFIG_USB_STORAGE=m
CONFIG_USB_MUSB_HDRC=m
@@ -431,8 +446,11 @@ CONFIG_USB_ZERO=m
CONFIG_USB_G_NOKIA=m
CONFIG_MMC=y
CONFIG_SDIO_UART=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CPCAP=m
@@ -459,10 +477,16 @@ CONFIG_DMADEVICES=y
CONFIG_DMA_OMAP=y
CONFIG_TI_EDMA=y
CONFIG_OMAP_IOMMU=y
-CONFIG_EXTCON=m
+CONFIG_REMOTEPROC=m
+CONFIG_OMAP_REMOTEPROC=m
+CONFIG_WKUP_M3_RPROC=m
+CONFIG_SOC_TI=y
+CONFIG_AMX3_PM=m
+CONFIG_WKUP_M3_IPC=m
CONFIG_EXTCON_PALMAS=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_TI_EMIF=m
+CONFIG_TI_EMIF_SRAM=m
CONFIG_IIO=m
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
@@ -477,6 +501,7 @@ CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_TWL=m
CONFIG_PWM_TWL_LED=m
CONFIG_PHY_CPCAP_USB=m
+CONFIG_PHY_MAPPHONE_MDM6600=m
CONFIG_PHY_DM816X_USB=m
CONFIG_OMAP_USB2=m
CONFIG_TI_PIPE3=y
@@ -491,7 +516,6 @@ CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
@@ -512,11 +536,18 @@ CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
CONFIG_PROVE_LOCKING=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_SECURITY=y
CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRC_CCITT=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
@@ -525,13 +556,3 @@ CONFIG_LIBCRC32C=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
-CONFIG_KERNEL_MODE_NEON=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM=m
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA256_ARM=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
diff --git a/arch/arm/configs/oxnas_v6_defconfig b/arch/arm/configs/oxnas_v6_defconfig
new file mode 100644
index 000000000000..f6ba32c9d173
--- /dev/null
+++ b/arch/arm/configs/oxnas_v6_defconfig
@@ -0,0 +1,93 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_ARCH_MULTI_V6=y
+CONFIG_ARCH_OXNAS=y
+CONFIG_MACH_OX820=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=16
+CONFIG_CMA=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_SECCOMP=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+CONFIG_EFI=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_VFP=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=64
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_OXNAS=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+CONFIG_REALTEK_PHY=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index bfea6874b0a1..3e0de035ab77 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -32,8 +32,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PXA3xx=y
-CONFIG_MTD_NAND_PXA3xx_BUILTIN=y
+CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y
diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig
index 837d0c9c8b0e..5655a1cee87d 100644
--- a/arch/arm/configs/pxa_defconfig
+++ b/arch/arm/configs/pxa_defconfig
@@ -197,7 +197,7 @@ CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
CONFIG_MTD_NAND_SHARPSL=m
-CONFIG_MTD_NAND_PXA3xx=m
+CONFIG_MTD_NAND_MARVELL=m
CONFIG_MTD_NAND_CM_X270=m
CONFIG_MTD_NAND_TMIO=m
CONFIG_MTD_NAND_BRCMNAND=m
diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig
index 77a56c23c6ef..2dd56e9a484e 100644
--- a/arch/arm/configs/raumfeld_defconfig
+++ b/arch/arm/configs/raumfeld_defconfig
@@ -33,7 +33,7 @@ CONFIG_NFTL=y
CONFIG_NFTL_RW=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PXA3xx=y
+CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_ISL29003=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 2a6d69d896bd..cc9fa24d4b8f 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -11,19 +11,17 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_REALVIEW=y
-CONFIG_REALVIEW_DT=y
CONFIG_MACH_REALVIEW_EB=y
CONFIG_REALVIEW_EB_ARM1136=y
CONFIG_REALVIEW_EB_ARM1176=y
CONFIG_REALVIEW_EB_A9MP=y
CONFIG_REALVIEW_EB_ARM11MP=y
-CONFIG_REALVIEW_EB_ARM11MP_REVB=y
CONFIG_MACH_REALVIEW_PB11MP=y
CONFIG_MACH_REALVIEW_PB1176=y
CONFIG_MACH_REALVIEW_PBA8=y
CONFIG_MACH_REALVIEW_PBX=y
CONFIG_SMP=y
-CONFIG_AEABI=y
+CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M"
@@ -46,7 +44,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y
CONFIG_MTD_PHYSMAP=y
-CONFIG_ARM_CHARLCD=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
@@ -59,21 +57,21 @@ CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
CONFIG_I2C_VERSATILE=y
CONFIG_SPI=y
CONFIG_GPIOLIB=y
# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PL111=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_ARMAACI=y
CONFIG_USB=y
@@ -83,13 +81,14 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_VERSATILE=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_PL031=y
+CONFIG_AUXDISPLAY=y
+CONFIG_ARM_CHARLCD=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 578434cfd1a0..a701601fbd76 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -5,8 +5,6 @@ CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_ARCH_RENESAS=y
@@ -34,7 +32,6 @@ CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_NR_CPUS=8
-CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -104,9 +101,6 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=20
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-CONFIG_SERIAL_SH_SCI_DMA=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_DEMUX_PINCTRL=y
@@ -120,6 +114,7 @@ CONFIG_SPI=y
CONFIG_SPI_RSPI=y
CONFIG_SPI_SH_MSIOF=y
CONFIG_SPI_SH_HSPI=y
+CONFIG_PINCTRL_RZA1=y
CONFIG_GPIO_EM=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_PCF857X=y
@@ -166,7 +161,6 @@ CONFIG_FB_SH_MOBILE_MERAM=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
@@ -227,4 +221,5 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index bb358ffde7d2..ba805b757a8d 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -57,6 +57,8 @@ CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
@@ -71,6 +73,7 @@ CONFIG_STM32_MDMA=y
CONFIG_IIO=y
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
+CONFIG_EXT3_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 295408ea9dc7..df68dc4056e5 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -12,6 +12,7 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_VERSATILE=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
+CONFIG_CMA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 mem=32M"
@@ -32,7 +33,9 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_RAM=y
CONFIG_EEPROM_LEGACY=m
CONFIG_NETDEVICES=y
@@ -47,21 +50,22 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_VERSATILE=y
CONFIG_SPI=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_ARM_VERSATILE=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PL111=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
CONFIG_SND_ARMAACI=m
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
index b8e69fe282b8..925d1364727a 100644
--- a/arch/arm/crypto/Kconfig
+++ b/arch/arm/crypto/Kconfig
@@ -121,4 +121,10 @@ config CRYPTO_CHACHA20_NEON
select CRYPTO_BLKCIPHER
select CRYPTO_CHACHA20
+config CRYPTO_SPECK_NEON
+ tristate "NEON accelerated Speck cipher algorithms"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_SPECK
+
endif
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index 30ef8e291271..8de542c48ade 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o
obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha20-neon.o
+obj-$(CONFIG_CRYPTO_SPECK_NEON) += speck-neon.o
ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
@@ -53,7 +54,9 @@ ghash-arm-ce-y := ghash-ce-core.o ghash-ce-glue.o
crct10dif-arm-ce-y := crct10dif-ce-core.o crct10dif-ce-glue.o
crc32-arm-ce-y:= crc32-ce-core.o crc32-ce-glue.o
chacha20-neon-y := chacha20-neon-core.o chacha20-neon-glue.o
+speck-neon-y := speck-neon-core.o speck-neon-glue.o
+ifdef REGENERATE_ARM_CRYPTO
quiet_cmd_perl = PERL $@
cmd_perl = $(PERL) $(<) > $(@)
@@ -62,5 +65,6 @@ $(src)/sha256-core.S_shipped: $(src)/sha256-armv4.pl
$(src)/sha512-core.S_shipped: $(src)/sha512-armv4.pl
$(call cmd,perl)
+endif
-.PRECIOUS: $(obj)/sha256-core.S $(obj)/sha512-core.S
+targets += sha256-core.S sha512-core.S
diff --git a/arch/arm/crypto/aes-cipher-core.S b/arch/arm/crypto/aes-cipher-core.S
index 54b384084637..184d6c2d15d5 100644
--- a/arch/arm/crypto/aes-cipher-core.S
+++ b/arch/arm/crypto/aes-cipher-core.S
@@ -174,6 +174,16 @@
.ltorg
.endm
+ENTRY(__aes_arm_encrypt)
+ do_crypt fround, crypto_ft_tab, crypto_ft_tab + 1, 2
+ENDPROC(__aes_arm_encrypt)
+
+ .align 5
+ENTRY(__aes_arm_decrypt)
+ do_crypt iround, crypto_it_tab, __aes_arm_inverse_sbox, 0
+ENDPROC(__aes_arm_decrypt)
+
+ .section ".rodata", "a"
.align L1_CACHE_SHIFT
.type __aes_arm_inverse_sbox, %object
__aes_arm_inverse_sbox:
@@ -210,12 +220,3 @@ __aes_arm_inverse_sbox:
.byte 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
.byte 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
.size __aes_arm_inverse_sbox, . - __aes_arm_inverse_sbox
-
-ENTRY(__aes_arm_encrypt)
- do_crypt fround, crypto_ft_tab, crypto_ft_tab + 1, 2
-ENDPROC(__aes_arm_encrypt)
-
- .align 5
-ENTRY(__aes_arm_decrypt)
- do_crypt iround, crypto_it_tab, __aes_arm_inverse_sbox, 0
-ENDPROC(__aes_arm_decrypt)
diff --git a/arch/arm/crypto/speck-neon-core.S b/arch/arm/crypto/speck-neon-core.S
new file mode 100644
index 000000000000..3c1e203e53b9
--- /dev/null
+++ b/arch/arm/crypto/speck-neon-core.S
@@ -0,0 +1,432 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NEON-accelerated implementation of Speck128-XTS and Speck64-XTS
+ *
+ * Copyright (c) 2018 Google, Inc
+ *
+ * Author: Eric Biggers <ebiggers@google.com>
+ */
+
+#include <linux/linkage.h>
+
+ .text
+ .fpu neon
+
+ // arguments
+ ROUND_KEYS .req r0 // const {u64,u32} *round_keys
+ NROUNDS .req r1 // int nrounds
+ DST .req r2 // void *dst
+ SRC .req r3 // const void *src
+ NBYTES .req r4 // unsigned int nbytes
+ TWEAK .req r5 // void *tweak
+
+ // registers which hold the data being encrypted/decrypted
+ X0 .req q0
+ X0_L .req d0
+ X0_H .req d1
+ Y0 .req q1
+ Y0_H .req d3
+ X1 .req q2
+ X1_L .req d4
+ X1_H .req d5
+ Y1 .req q3
+ Y1_H .req d7
+ X2 .req q4
+ X2_L .req d8
+ X2_H .req d9
+ Y2 .req q5
+ Y2_H .req d11
+ X3 .req q6
+ X3_L .req d12
+ X3_H .req d13
+ Y3 .req q7
+ Y3_H .req d15
+
+ // the round key, duplicated in all lanes
+ ROUND_KEY .req q8
+ ROUND_KEY_L .req d16
+ ROUND_KEY_H .req d17
+
+ // index vector for vtbl-based 8-bit rotates
+ ROTATE_TABLE .req d18
+
+ // multiplication table for updating XTS tweaks
+ GF128MUL_TABLE .req d19
+ GF64MUL_TABLE .req d19
+
+ // current XTS tweak value(s)
+ TWEAKV .req q10
+ TWEAKV_L .req d20
+ TWEAKV_H .req d21
+
+ TMP0 .req q12
+ TMP0_L .req d24
+ TMP0_H .req d25
+ TMP1 .req q13
+ TMP2 .req q14
+ TMP3 .req q15
+
+ .align 4
+.Lror64_8_table:
+ .byte 1, 2, 3, 4, 5, 6, 7, 0
+.Lror32_8_table:
+ .byte 1, 2, 3, 0, 5, 6, 7, 4
+.Lrol64_8_table:
+ .byte 7, 0, 1, 2, 3, 4, 5, 6
+.Lrol32_8_table:
+ .byte 3, 0, 1, 2, 7, 4, 5, 6
+.Lgf128mul_table:
+ .byte 0, 0x87
+ .fill 14
+.Lgf64mul_table:
+ .byte 0, 0x1b, (0x1b << 1), (0x1b << 1) ^ 0x1b
+ .fill 12
+
+/*
+ * _speck_round_128bytes() - Speck encryption round on 128 bytes at a time
+ *
+ * Do one Speck encryption round on the 128 bytes (8 blocks for Speck128, 16 for
+ * Speck64) stored in X0-X3 and Y0-Y3, using the round key stored in all lanes
+ * of ROUND_KEY. 'n' is the lane size: 64 for Speck128, or 32 for Speck64.
+ *
+ * The 8-bit rotates are implemented using vtbl instead of vshr + vsli because
+ * the vtbl approach is faster on some processors and the same speed on others.
+ */
+.macro _speck_round_128bytes n
+
+ // x = ror(x, 8)
+ vtbl.8 X0_L, {X0_L}, ROTATE_TABLE
+ vtbl.8 X0_H, {X0_H}, ROTATE_TABLE
+ vtbl.8 X1_L, {X1_L}, ROTATE_TABLE
+ vtbl.8 X1_H, {X1_H}, ROTATE_TABLE
+ vtbl.8 X2_L, {X2_L}, ROTATE_TABLE
+ vtbl.8 X2_H, {X2_H}, ROTATE_TABLE
+ vtbl.8 X3_L, {X3_L}, ROTATE_TABLE
+ vtbl.8 X3_H, {X3_H}, ROTATE_TABLE
+
+ // x += y
+ vadd.u\n X0, Y0
+ vadd.u\n X1, Y1
+ vadd.u\n X2, Y2
+ vadd.u\n X3, Y3
+
+ // x ^= k
+ veor X0, ROUND_KEY
+ veor X1, ROUND_KEY
+ veor X2, ROUND_KEY
+ veor X3, ROUND_KEY
+
+ // y = rol(y, 3)
+ vshl.u\n TMP0, Y0, #3
+ vshl.u\n TMP1, Y1, #3
+ vshl.u\n TMP2, Y2, #3
+ vshl.u\n TMP3, Y3, #3
+ vsri.u\n TMP0, Y0, #(\n - 3)
+ vsri.u\n TMP1, Y1, #(\n - 3)
+ vsri.u\n TMP2, Y2, #(\n - 3)
+ vsri.u\n TMP3, Y3, #(\n - 3)
+
+ // y ^= x
+ veor Y0, TMP0, X0
+ veor Y1, TMP1, X1
+ veor Y2, TMP2, X2
+ veor Y3, TMP3, X3
+.endm
+
+/*
+ * _speck_unround_128bytes() - Speck decryption round on 128 bytes at a time
+ *
+ * This is the inverse of _speck_round_128bytes().
+ */
+.macro _speck_unround_128bytes n
+
+ // y ^= x
+ veor TMP0, Y0, X0
+ veor TMP1, Y1, X1
+ veor TMP2, Y2, X2
+ veor TMP3, Y3, X3
+
+ // y = ror(y, 3)
+ vshr.u\n Y0, TMP0, #3
+ vshr.u\n Y1, TMP1, #3
+ vshr.u\n Y2, TMP2, #3
+ vshr.u\n Y3, TMP3, #3
+ vsli.u\n Y0, TMP0, #(\n - 3)
+ vsli.u\n Y1, TMP1, #(\n - 3)
+ vsli.u\n Y2, TMP2, #(\n - 3)
+ vsli.u\n Y3, TMP3, #(\n - 3)
+
+ // x ^= k
+ veor X0, ROUND_KEY
+ veor X1, ROUND_KEY
+ veor X2, ROUND_KEY
+ veor X3, ROUND_KEY
+
+ // x -= y
+ vsub.u\n X0, Y0
+ vsub.u\n X1, Y1
+ vsub.u\n X2, Y2
+ vsub.u\n X3, Y3
+
+ // x = rol(x, 8);
+ vtbl.8 X0_L, {X0_L}, ROTATE_TABLE
+ vtbl.8 X0_H, {X0_H}, ROTATE_TABLE
+ vtbl.8 X1_L, {X1_L}, ROTATE_TABLE
+ vtbl.8 X1_H, {X1_H}, ROTATE_TABLE
+ vtbl.8 X2_L, {X2_L}, ROTATE_TABLE
+ vtbl.8 X2_H, {X2_H}, ROTATE_TABLE
+ vtbl.8 X3_L, {X3_L}, ROTATE_TABLE
+ vtbl.8 X3_H, {X3_H}, ROTATE_TABLE
+.endm
+
+.macro _xts128_precrypt_one dst_reg, tweak_buf, tmp
+
+ // Load the next source block
+ vld1.8 {\dst_reg}, [SRC]!
+
+ // Save the current tweak in the tweak buffer
+ vst1.8 {TWEAKV}, [\tweak_buf:128]!
+
+ // XOR the next source block with the current tweak
+ veor \dst_reg, TWEAKV
+
+ /*
+ * Calculate the next tweak by multiplying the current one by x,
+ * modulo p(x) = x^128 + x^7 + x^2 + x + 1.
+ */
+ vshr.u64 \tmp, TWEAKV, #63
+ vshl.u64 TWEAKV, #1
+ veor TWEAKV_H, \tmp\()_L
+ vtbl.8 \tmp\()_H, {GF128MUL_TABLE}, \tmp\()_H
+ veor TWEAKV_L, \tmp\()_H
+.endm
+
+.macro _xts64_precrypt_two dst_reg, tweak_buf, tmp
+
+ // Load the next two source blocks
+ vld1.8 {\dst_reg}, [SRC]!
+
+ // Save the current two tweaks in the tweak buffer
+ vst1.8 {TWEAKV}, [\tweak_buf:128]!
+
+ // XOR the next two source blocks with the current two tweaks
+ veor \dst_reg, TWEAKV
+
+ /*
+ * Calculate the next two tweaks by multiplying the current ones by x^2,
+ * modulo p(x) = x^64 + x^4 + x^3 + x + 1.
+ */
+ vshr.u64 \tmp, TWEAKV, #62
+ vshl.u64 TWEAKV, #2
+ vtbl.8 \tmp\()_L, {GF64MUL_TABLE}, \tmp\()_L
+ vtbl.8 \tmp\()_H, {GF64MUL_TABLE}, \tmp\()_H
+ veor TWEAKV, \tmp
+.endm
+
+/*
+ * _speck_xts_crypt() - Speck-XTS encryption/decryption
+ *
+ * Encrypt or decrypt NBYTES bytes of data from the SRC buffer to the DST buffer
+ * using Speck-XTS, specifically the variant with a block size of '2n' and round
+ * count given by NROUNDS. The expanded round keys are given in ROUND_KEYS, and
+ * the current XTS tweak value is given in TWEAK. It's assumed that NBYTES is a
+ * nonzero multiple of 128.
+ */
+.macro _speck_xts_crypt n, decrypting
+ push {r4-r7}
+ mov r7, sp
+
+ /*
+ * The first four parameters were passed in registers r0-r3. Load the
+ * additional parameters, which were passed on the stack.
+ */
+ ldr NBYTES, [sp, #16]
+ ldr TWEAK, [sp, #20]
+
+ /*
+ * If decrypting, modify the ROUND_KEYS parameter to point to the last
+ * round key rather than the first, since for decryption the round keys
+ * are used in reverse order.
+ */
+.if \decrypting
+.if \n == 64
+ add ROUND_KEYS, ROUND_KEYS, NROUNDS, lsl #3
+ sub ROUND_KEYS, #8
+.else
+ add ROUND_KEYS, ROUND_KEYS, NROUNDS, lsl #2
+ sub ROUND_KEYS, #4
+.endif
+.endif
+
+ // Load the index vector for vtbl-based 8-bit rotates
+.if \decrypting
+ ldr r12, =.Lrol\n\()_8_table
+.else
+ ldr r12, =.Lror\n\()_8_table
+.endif
+ vld1.8 {ROTATE_TABLE}, [r12:64]
+
+ // One-time XTS preparation
+
+ /*
+ * Allocate stack space to store 128 bytes worth of tweaks. For
+ * performance, this space is aligned to a 16-byte boundary so that we
+ * can use the load/store instructions that declare 16-byte alignment.
+ */
+ sub sp, #128
+ bic sp, #0xf
+
+.if \n == 64
+ // Load first tweak
+ vld1.8 {TWEAKV}, [TWEAK]
+
+ // Load GF(2^128) multiplication table
+ ldr r12, =.Lgf128mul_table
+ vld1.8 {GF128MUL_TABLE}, [r12:64]
+.else
+ // Load first tweak
+ vld1.8 {TWEAKV_L}, [TWEAK]
+
+ // Load GF(2^64) multiplication table
+ ldr r12, =.Lgf64mul_table
+ vld1.8 {GF64MUL_TABLE}, [r12:64]
+
+ // Calculate second tweak, packing it together with the first
+ vshr.u64 TMP0_L, TWEAKV_L, #63
+ vtbl.u8 TMP0_L, {GF64MUL_TABLE}, TMP0_L
+ vshl.u64 TWEAKV_H, TWEAKV_L, #1
+ veor TWEAKV_H, TMP0_L
+.endif
+
+.Lnext_128bytes_\@:
+
+ /*
+ * Load the source blocks into {X,Y}[0-3], XOR them with their XTS tweak
+ * values, and save the tweaks on the stack for later. Then
+ * de-interleave the 'x' and 'y' elements of each block, i.e. make it so
+ * that the X[0-3] registers contain only the second halves of blocks,
+ * and the Y[0-3] registers contain only the first halves of blocks.
+ * (Speck uses the order (y, x) rather than the more intuitive (x, y).)
+ */
+ mov r12, sp
+.if \n == 64
+ _xts128_precrypt_one X0, r12, TMP0
+ _xts128_precrypt_one Y0, r12, TMP0
+ _xts128_precrypt_one X1, r12, TMP0
+ _xts128_precrypt_one Y1, r12, TMP0
+ _xts128_precrypt_one X2, r12, TMP0
+ _xts128_precrypt_one Y2, r12, TMP0
+ _xts128_precrypt_one X3, r12, TMP0
+ _xts128_precrypt_one Y3, r12, TMP0
+ vswp X0_L, Y0_H
+ vswp X1_L, Y1_H
+ vswp X2_L, Y2_H
+ vswp X3_L, Y3_H
+.else
+ _xts64_precrypt_two X0, r12, TMP0
+ _xts64_precrypt_two Y0, r12, TMP0
+ _xts64_precrypt_two X1, r12, TMP0
+ _xts64_precrypt_two Y1, r12, TMP0
+ _xts64_precrypt_two X2, r12, TMP0
+ _xts64_precrypt_two Y2, r12, TMP0
+ _xts64_precrypt_two X3, r12, TMP0
+ _xts64_precrypt_two Y3, r12, TMP0
+ vuzp.32 Y0, X0
+ vuzp.32 Y1, X1
+ vuzp.32 Y2, X2
+ vuzp.32 Y3, X3
+.endif
+
+ // Do the cipher rounds
+
+ mov r12, ROUND_KEYS
+ mov r6, NROUNDS
+
+.Lnext_round_\@:
+.if \decrypting
+.if \n == 64
+ vld1.64 ROUND_KEY_L, [r12]
+ sub r12, #8
+ vmov ROUND_KEY_H, ROUND_KEY_L
+.else
+ vld1.32 {ROUND_KEY_L[],ROUND_KEY_H[]}, [r12]
+ sub r12, #4
+.endif
+ _speck_unround_128bytes \n
+.else
+.if \n == 64
+ vld1.64 ROUND_KEY_L, [r12]!
+ vmov ROUND_KEY_H, ROUND_KEY_L
+.else
+ vld1.32 {ROUND_KEY_L[],ROUND_KEY_H[]}, [r12]!
+.endif
+ _speck_round_128bytes \n
+.endif
+ subs r6, r6, #1
+ bne .Lnext_round_\@
+
+ // Re-interleave the 'x' and 'y' elements of each block
+.if \n == 64
+ vswp X0_L, Y0_H
+ vswp X1_L, Y1_H
+ vswp X2_L, Y2_H
+ vswp X3_L, Y3_H
+.else
+ vzip.32 Y0, X0
+ vzip.32 Y1, X1
+ vzip.32 Y2, X2
+ vzip.32 Y3, X3
+.endif
+
+ // XOR the encrypted/decrypted blocks with the tweaks we saved earlier
+ mov r12, sp
+ vld1.8 {TMP0, TMP1}, [r12:128]!
+ vld1.8 {TMP2, TMP3}, [r12:128]!
+ veor X0, TMP0
+ veor Y0, TMP1
+ veor X1, TMP2
+ veor Y1, TMP3
+ vld1.8 {TMP0, TMP1}, [r12:128]!
+ vld1.8 {TMP2, TMP3}, [r12:128]!
+ veor X2, TMP0
+ veor Y2, TMP1
+ veor X3, TMP2
+ veor Y3, TMP3
+
+ // Store the ciphertext in the destination buffer
+ vst1.8 {X0, Y0}, [DST]!
+ vst1.8 {X1, Y1}, [DST]!
+ vst1.8 {X2, Y2}, [DST]!
+ vst1.8 {X3, Y3}, [DST]!
+
+ // Continue if there are more 128-byte chunks remaining, else return
+ subs NBYTES, #128
+ bne .Lnext_128bytes_\@
+
+ // Store the next tweak
+.if \n == 64
+ vst1.8 {TWEAKV}, [TWEAK]
+.else
+ vst1.8 {TWEAKV_L}, [TWEAK]
+.endif
+
+ mov sp, r7
+ pop {r4-r7}
+ bx lr
+.endm
+
+ENTRY(speck128_xts_encrypt_neon)
+ _speck_xts_crypt n=64, decrypting=0
+ENDPROC(speck128_xts_encrypt_neon)
+
+ENTRY(speck128_xts_decrypt_neon)
+ _speck_xts_crypt n=64, decrypting=1
+ENDPROC(speck128_xts_decrypt_neon)
+
+ENTRY(speck64_xts_encrypt_neon)
+ _speck_xts_crypt n=32, decrypting=0
+ENDPROC(speck64_xts_encrypt_neon)
+
+ENTRY(speck64_xts_decrypt_neon)
+ _speck_xts_crypt n=32, decrypting=1
+ENDPROC(speck64_xts_decrypt_neon)
diff --git a/arch/arm/crypto/speck-neon-glue.c b/arch/arm/crypto/speck-neon-glue.c
new file mode 100644
index 000000000000..f012c3ea998f
--- /dev/null
+++ b/arch/arm/crypto/speck-neon-glue.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NEON-accelerated implementation of Speck128-XTS and Speck64-XTS
+ *
+ * Copyright (c) 2018 Google, Inc
+ *
+ * Note: the NIST recommendation for XTS only specifies a 128-bit block size,
+ * but a 64-bit version (needed for Speck64) is fairly straightforward; the math
+ * is just done in GF(2^64) instead of GF(2^128), with the reducing polynomial
+ * x^64 + x^4 + x^3 + x + 1 from the original XEX paper (Rogaway, 2004:
+ * "Efficient Instantiations of Tweakable Blockciphers and Refinements to Modes
+ * OCB and PMAC"), represented as 0x1B.
+ */
+
+#include <asm/hwcap.h>
+#include <asm/neon.h>
+#include <asm/simd.h>
+#include <crypto/algapi.h>
+#include <crypto/gf128mul.h>
+#include <crypto/internal/skcipher.h>
+#include <crypto/speck.h>
+#include <crypto/xts.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+/* The assembly functions only handle multiples of 128 bytes */
+#define SPECK_NEON_CHUNK_SIZE 128
+
+/* Speck128 */
+
+struct speck128_xts_tfm_ctx {
+ struct speck128_tfm_ctx main_key;
+ struct speck128_tfm_ctx tweak_key;
+};
+
+asmlinkage void speck128_xts_encrypt_neon(const u64 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+asmlinkage void speck128_xts_decrypt_neon(const u64 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+typedef void (*speck128_crypt_one_t)(const struct speck128_tfm_ctx *,
+ u8 *, const u8 *);
+typedef void (*speck128_xts_crypt_many_t)(const u64 *, int, void *,
+ const void *, unsigned int, void *);
+
+static __always_inline int
+__speck128_xts_crypt(struct skcipher_request *req,
+ speck128_crypt_one_t crypt_one,
+ speck128_xts_crypt_many_t crypt_many)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ const struct speck128_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ struct skcipher_walk walk;
+ le128 tweak;
+ int err;
+
+ err = skcipher_walk_virt(&walk, req, true);
+
+ crypto_speck128_encrypt(&ctx->tweak_key, (u8 *)&tweak, walk.iv);
+
+ while (walk.nbytes > 0) {
+ unsigned int nbytes = walk.nbytes;
+ u8 *dst = walk.dst.virt.addr;
+ const u8 *src = walk.src.virt.addr;
+
+ if (nbytes >= SPECK_NEON_CHUNK_SIZE && may_use_simd()) {
+ unsigned int count;
+
+ count = round_down(nbytes, SPECK_NEON_CHUNK_SIZE);
+ kernel_neon_begin();
+ (*crypt_many)(ctx->main_key.round_keys,
+ ctx->main_key.nrounds,
+ dst, src, count, &tweak);
+ kernel_neon_end();
+ dst += count;
+ src += count;
+ nbytes -= count;
+ }
+
+ /* Handle any remainder with generic code */
+ while (nbytes >= sizeof(tweak)) {
+ le128_xor((le128 *)dst, (const le128 *)src, &tweak);
+ (*crypt_one)(&ctx->main_key, dst, dst);
+ le128_xor((le128 *)dst, (const le128 *)dst, &tweak);
+ gf128mul_x_ble(&tweak, &tweak);
+
+ dst += sizeof(tweak);
+ src += sizeof(tweak);
+ nbytes -= sizeof(tweak);
+ }
+ err = skcipher_walk_done(&walk, nbytes);
+ }
+
+ return err;
+}
+
+static int speck128_xts_encrypt(struct skcipher_request *req)
+{
+ return __speck128_xts_crypt(req, crypto_speck128_encrypt,
+ speck128_xts_encrypt_neon);
+}
+
+static int speck128_xts_decrypt(struct skcipher_request *req)
+{
+ return __speck128_xts_crypt(req, crypto_speck128_decrypt,
+ speck128_xts_decrypt_neon);
+}
+
+static int speck128_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct speck128_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ int err;
+
+ err = xts_verify_key(tfm, key, keylen);
+ if (err)
+ return err;
+
+ keylen /= 2;
+
+ err = crypto_speck128_setkey(&ctx->main_key, key, keylen);
+ if (err)
+ return err;
+
+ return crypto_speck128_setkey(&ctx->tweak_key, key + keylen, keylen);
+}
+
+/* Speck64 */
+
+struct speck64_xts_tfm_ctx {
+ struct speck64_tfm_ctx main_key;
+ struct speck64_tfm_ctx tweak_key;
+};
+
+asmlinkage void speck64_xts_encrypt_neon(const u32 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+asmlinkage void speck64_xts_decrypt_neon(const u32 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+typedef void (*speck64_crypt_one_t)(const struct speck64_tfm_ctx *,
+ u8 *, const u8 *);
+typedef void (*speck64_xts_crypt_many_t)(const u32 *, int, void *,
+ const void *, unsigned int, void *);
+
+static __always_inline int
+__speck64_xts_crypt(struct skcipher_request *req, speck64_crypt_one_t crypt_one,
+ speck64_xts_crypt_many_t crypt_many)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ const struct speck64_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ struct skcipher_walk walk;
+ __le64 tweak;
+ int err;
+
+ err = skcipher_walk_virt(&walk, req, true);
+
+ crypto_speck64_encrypt(&ctx->tweak_key, (u8 *)&tweak, walk.iv);
+
+ while (walk.nbytes > 0) {
+ unsigned int nbytes = walk.nbytes;
+ u8 *dst = walk.dst.virt.addr;
+ const u8 *src = walk.src.virt.addr;
+
+ if (nbytes >= SPECK_NEON_CHUNK_SIZE && may_use_simd()) {
+ unsigned int count;
+
+ count = round_down(nbytes, SPECK_NEON_CHUNK_SIZE);
+ kernel_neon_begin();
+ (*crypt_many)(ctx->main_key.round_keys,
+ ctx->main_key.nrounds,
+ dst, src, count, &tweak);
+ kernel_neon_end();
+ dst += count;
+ src += count;
+ nbytes -= count;
+ }
+
+ /* Handle any remainder with generic code */
+ while (nbytes >= sizeof(tweak)) {
+ *(__le64 *)dst = *(__le64 *)src ^ tweak;
+ (*crypt_one)(&ctx->main_key, dst, dst);
+ *(__le64 *)dst ^= tweak;
+ tweak = cpu_to_le64((le64_to_cpu(tweak) << 1) ^
+ ((tweak & cpu_to_le64(1ULL << 63)) ?
+ 0x1B : 0));
+ dst += sizeof(tweak);
+ src += sizeof(tweak);
+ nbytes -= sizeof(tweak);
+ }
+ err = skcipher_walk_done(&walk, nbytes);
+ }
+
+ return err;
+}
+
+static int speck64_xts_encrypt(struct skcipher_request *req)
+{
+ return __speck64_xts_crypt(req, crypto_speck64_encrypt,
+ speck64_xts_encrypt_neon);
+}
+
+static int speck64_xts_decrypt(struct skcipher_request *req)
+{
+ return __speck64_xts_crypt(req, crypto_speck64_decrypt,
+ speck64_xts_decrypt_neon);
+}
+
+static int speck64_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct speck64_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ int err;
+
+ err = xts_verify_key(tfm, key, keylen);
+ if (err)
+ return err;
+
+ keylen /= 2;
+
+ err = crypto_speck64_setkey(&ctx->main_key, key, keylen);
+ if (err)
+ return err;
+
+ return crypto_speck64_setkey(&ctx->tweak_key, key + keylen, keylen);
+}
+
+static struct skcipher_alg speck_algs[] = {
+ {
+ .base.cra_name = "xts(speck128)",
+ .base.cra_driver_name = "xts-speck128-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = SPECK128_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct speck128_xts_tfm_ctx),
+ .base.cra_alignmask = 7,
+ .base.cra_module = THIS_MODULE,
+ .min_keysize = 2 * SPECK128_128_KEY_SIZE,
+ .max_keysize = 2 * SPECK128_256_KEY_SIZE,
+ .ivsize = SPECK128_BLOCK_SIZE,
+ .walksize = SPECK_NEON_CHUNK_SIZE,
+ .setkey = speck128_xts_setkey,
+ .encrypt = speck128_xts_encrypt,
+ .decrypt = speck128_xts_decrypt,
+ }, {
+ .base.cra_name = "xts(speck64)",
+ .base.cra_driver_name = "xts-speck64-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = SPECK64_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct speck64_xts_tfm_ctx),
+ .base.cra_alignmask = 7,
+ .base.cra_module = THIS_MODULE,
+ .min_keysize = 2 * SPECK64_96_KEY_SIZE,
+ .max_keysize = 2 * SPECK64_128_KEY_SIZE,
+ .ivsize = SPECK64_BLOCK_SIZE,
+ .walksize = SPECK_NEON_CHUNK_SIZE,
+ .setkey = speck64_xts_setkey,
+ .encrypt = speck64_xts_encrypt,
+ .decrypt = speck64_xts_decrypt,
+ }
+};
+
+static int __init speck_neon_module_init(void)
+{
+ if (!(elf_hwcap & HWCAP_NEON))
+ return -ENODEV;
+ return crypto_register_skciphers(speck_algs, ARRAY_SIZE(speck_algs));
+}
+
+static void __exit speck_neon_module_exit(void)
+{
+ crypto_unregister_skciphers(speck_algs, ARRAY_SIZE(speck_algs));
+}
+
+module_init(speck_neon_module_init);
+module_exit(speck_neon_module_exit);
+
+MODULE_DESCRIPTION("Speck block cipher (NEON-accelerated)");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Eric Biggers <ebiggers@google.com>");
+MODULE_ALIAS_CRYPTO("xts(speck128)");
+MODULE_ALIAS_CRYPTO("xts-speck128-neon");
+MODULE_ALIAS_CRYPTO("xts(speck64)");
+MODULE_ALIAS_CRYPTO("xts-speck64-neon");
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 1070044f5c3f..0bd530702118 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -35,6 +35,18 @@
#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
+#define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
+#define ICC_AP0R0 __ICC_AP0Rx(0)
+#define ICC_AP0R1 __ICC_AP0Rx(1)
+#define ICC_AP0R2 __ICC_AP0Rx(2)
+#define ICC_AP0R3 __ICC_AP0Rx(3)
+
+#define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
+#define ICC_AP1R0 __ICC_AP1Rx(0)
+#define ICC_AP1R1 __ICC_AP1Rx(1)
+#define ICC_AP1R2 __ICC_AP1Rx(2)
+#define ICC_AP1R3 __ICC_AP1Rx(3)
+
#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
#define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
@@ -86,17 +98,17 @@
#define ICH_LRC14 __LRC8(6)
#define ICH_LRC15 __LRC8(7)
-#define __AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
-#define ICH_AP0R0 __AP0Rx(0)
-#define ICH_AP0R1 __AP0Rx(1)
-#define ICH_AP0R2 __AP0Rx(2)
-#define ICH_AP0R3 __AP0Rx(3)
+#define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
+#define ICH_AP0R0 __ICH_AP0Rx(0)
+#define ICH_AP0R1 __ICH_AP0Rx(1)
+#define ICH_AP0R2 __ICH_AP0Rx(2)
+#define ICH_AP0R3 __ICH_AP0Rx(3)
-#define __AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
-#define ICH_AP1R0 __AP1Rx(0)
-#define ICH_AP1R1 __AP1Rx(1)
-#define ICH_AP1R2 __AP1Rx(2)
-#define ICH_AP1R3 __AP1Rx(3)
+#define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
+#define ICH_AP1R0 __ICH_AP1Rx(0)
+#define ICH_AP1R1 __ICH_AP1Rx(1)
+#define ICH_AP1R2 __ICH_AP1Rx(2)
+#define ICH_AP1R3 __ICH_AP1Rx(3)
/* A32-to-A64 mappings used by VGIC save/restore */
@@ -125,6 +137,16 @@ static inline u64 read_ ## a64(void) \
return val; \
}
+CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
+CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
+CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
+CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
+CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
+CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
+CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
+CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
+CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
+
CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
@@ -185,11 +207,6 @@ static inline u32 gic_read_iar(void)
return irqstat;
}
-static inline void gic_write_pmr(u32 val)
-{
- write_sysreg(val, ICC_PMR);
-}
-
static inline void gic_write_ctlr(u32 val)
{
write_sysreg(val, ICC_CTLR);
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 74504b154256..869080bedb89 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -318,10 +318,8 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
extern void flush_kernel_dcache_page(struct page *);
-#define flush_dcache_mmap_lock(mapping) \
- spin_lock_irq(&(mapping)->tree_lock)
-#define flush_dcache_mmap_unlock(mapping) \
- spin_unlock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages)
+#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages)
#define flush_icache_user_range(vma,page,addr,len) \
flush_dcache_page(page)
diff --git a/arch/arm/include/asm/dma-direct.h b/arch/arm/include/asm/dma-direct.h
index 5b0a8a421894..b67e5fc1fe43 100644
--- a/arch/arm/include/asm/dma-direct.h
+++ b/arch/arm/include/asm/dma-direct.h
@@ -2,13 +2,13 @@
#ifndef ASM_ARM_DMA_DIRECT_H
#define ASM_ARM_DMA_DIRECT_H 1
-static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
unsigned int offset = paddr & ~PAGE_MASK;
return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset;
}
-static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
+static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr)
{
unsigned int offset = dev_addr & ~PAGE_MASK;
return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset;
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 36dd2962a42d..5a953ecb0d78 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -70,7 +70,10 @@ extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);
extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
-extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+/* no VHE on 32-bit :( */
+static inline int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) { BUG(); return 0; }
+
+extern int __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu);
extern void __init_stage2_translation(void);
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 9003bd19cb70..6493bd479ddc 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -41,7 +41,17 @@ static inline unsigned long *vcpu_reg32(struct kvm_vcpu *vcpu, u8 reg_num)
return vcpu_reg(vcpu, reg_num);
}
-unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
+unsigned long *__vcpu_spsr(struct kvm_vcpu *vcpu);
+
+static inline unsigned long vpcu_read_spsr(struct kvm_vcpu *vcpu)
+{
+ return *__vcpu_spsr(vcpu);
+}
+
+static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
+{
+ *__vcpu_spsr(vcpu) = v;
+}
static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu,
u8 reg_num)
@@ -92,14 +102,9 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
vcpu->arch.hcr = HCR_GUEST_MASK;
}
-static inline unsigned long vcpu_get_hcr(const struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.hcr;
-}
-
-static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
+static inline unsigned long *vcpu_hcr(const struct kvm_vcpu *vcpu)
{
- vcpu->arch.hcr = hcr;
+ return (unsigned long *)&vcpu->arch.hcr;
}
static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 248b930563e5..c6a749568dd6 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -155,9 +155,6 @@ struct kvm_vcpu_arch {
/* HYP trapping configuration */
u32 hcr;
- /* Interrupt related fields */
- u32 irq_lines; /* IRQ and FIQ levels */
-
/* Exception Information */
struct kvm_vcpu_fault_info fault;
@@ -315,4 +312,7 @@ static inline bool kvm_arm_harden_branch_predictor(void)
return false;
}
+static inline void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu) {}
+static inline void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu) {}
+
#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h
index 1ab8329e9ff7..e93a0cac9add 100644
--- a/arch/arm/include/asm/kvm_hyp.h
+++ b/arch/arm/include/asm/kvm_hyp.h
@@ -110,6 +110,10 @@ void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
+void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu);
+void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu);
+void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu);
+void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu);
asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp);
asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp);
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index de1b919404e4..707a1f06dc5d 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -28,6 +28,13 @@
*/
#define kern_hyp_va(kva) (kva)
+/* Contrary to arm64, there is no need to generate a PC-relative address */
+#define hyp_symbol_addr(s) \
+ ({ \
+ typeof(s) *addr = &(s); \
+ addr; \
+ })
+
/*
* KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels.
*/
@@ -42,8 +49,15 @@
#include <asm/pgalloc.h>
#include <asm/stage2_pgtable.h>
+/* Ensure compatibility with arm64 */
+#define VA_BITS 32
+
int create_hyp_mappings(void *from, void *to, pgprot_t prot);
-int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
+ void __iomem **kaddr,
+ void __iomem **haddr);
+int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
+ void **haddr);
void free_hyp_pgds(void);
void stage2_unmap_vm(struct kvm *kvm);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 496667703693..ed8fd0d19a3e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -22,12 +22,6 @@
#include <mach/memory.h>
#endif
-/*
- * Allow for constants defined here to be used from assembly code
- * by prepending the UL suffix only with actual C code compilation.
- */
-#define UL(x) _AC(x, UL)
-
/* PAGE_OFFSET - the virtual address of the start of the kernel image */
#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
diff --git a/arch/arm/include/asm/vdso.h b/arch/arm/include/asm/vdso.h
index 9c99e817535e..5b85889f82ee 100644
--- a/arch/arm/include/asm/vdso.h
+++ b/arch/arm/include/asm/vdso.h
@@ -12,8 +12,6 @@ struct mm_struct;
void arm_install_vdso(struct mm_struct *mm, unsigned long addr);
-extern char vdso_start, vdso_end;
-
extern unsigned int vdso_total_pages;
#else /* CONFIG_VDSO */
diff --git a/arch/arm/include/debug/exynos.S b/arch/arm/include/debug/exynos.S
index 60bf3c23200d..74b56769f9cb 100644
--- a/arch/arm/include/debug/exynos.S
+++ b/arch/arm/include/debug/exynos.S
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
/* pull in the relevant register and map files. */
diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index f4eeed2a1981..69201d7fb48f 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -1,13 +1,9 @@
-/* arch/arm/plat-samsung/include/plat/debug-macro.S
- *
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
* Copyright 2005, 2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
#include <linux/serial_s3c.h>
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index 6edd177bb1c7..2ba95d6fe852 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -135,6 +135,15 @@ struct kvm_arch_memory_slot {
#define KVM_REG_ARM_CRM_SHIFT 7
#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
#define KVM_REG_ARM_32_CRN_SHIFT 11
+/*
+ * For KVM currently all guest registers are nonsecure, but we reserve a bit
+ * in the encoding to distinguish secure from nonsecure for AArch32 system
+ * registers that are banked by security. This is 1 for the secure banked
+ * register, and 0 for the nonsecure banked register or if the register is
+ * not banked by security.
+ */
+#define KVM_REG_ARM_SECURE_MASK 0x0000000010000000
+#define KVM_REG_ARM_SECURE_SHIFT 28
#define ARM_CP15_REG_SHIFT_MASK(x,n) \
(((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 3151f5623d0e..bdf7514204ab 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -35,5 +35,5 @@
asmlinkage long sys_arm_fadvise64_64(int fd, int advice,
loff_t offset, loff_t len)
{
- return sys_fadvise64_64(fd, offset, len, advice);
+ return ksys_fadvise64_64(fd, offset, len, advice);
}
diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
index a4d6dc0f2427..f4dd7f9663c1 100644
--- a/arch/arm/kernel/vdso.c
+++ b/arch/arm/kernel/vdso.c
@@ -39,6 +39,8 @@
static struct page **vdso_text_pagelist;
+extern char vdso_start[], vdso_end[];
+
/* Total number of pages needed for the data and text portions of the VDSO. */
unsigned int vdso_total_pages __ro_after_init;
@@ -197,13 +199,13 @@ static int __init vdso_init(void)
unsigned int text_pages;
int i;
- if (memcmp(&vdso_start, "\177ELF", 4)) {
+ if (memcmp(vdso_start, "\177ELF", 4)) {
pr_err("VDSO is not a valid ELF object!\n");
return -ENOEXEC;
}
- text_pages = (&vdso_end - &vdso_start) >> PAGE_SHIFT;
- pr_debug("vdso: %i text pages at base %p\n", text_pages, &vdso_start);
+ text_pages = (vdso_end - vdso_start) >> PAGE_SHIFT;
+ pr_debug("vdso: %i text pages at base %p\n", text_pages, vdso_start);
/* Allocate the VDSO text pagelist */
vdso_text_pagelist = kcalloc(text_pages, sizeof(struct page *),
@@ -218,7 +220,7 @@ static int __init vdso_init(void)
for (i = 0; i < text_pages; i++) {
struct page *page;
- page = virt_to_page(&vdso_start + i * PAGE_SIZE);
+ page = virt_to_page(vdso_start + i * PAGE_SIZE);
vdso_text_pagelist[i] = page;
}
@@ -229,7 +231,7 @@ static int __init vdso_init(void)
cntvct_ok = cntvct_functional();
- patch_vdso(&vdso_start);
+ patch_vdso(vdso_start);
return 0;
}
diff --git a/arch/arm/kernel/vmlinux-xip.lds.S b/arch/arm/kernel/vmlinux-xip.lds.S
index 12b87591eb7c..d32f5d35f602 100644
--- a/arch/arm/kernel/vmlinux-xip.lds.S
+++ b/arch/arm/kernel/vmlinux-xip.lds.S
@@ -15,38 +15,7 @@
#include <asm/memory.h>
#include <asm/page.h>
-#define PROC_INFO \
- . = ALIGN(4); \
- VMLINUX_SYMBOL(__proc_info_begin) = .; \
- *(.proc.info.init) \
- VMLINUX_SYMBOL(__proc_info_end) = .;
-
-#define IDMAP_TEXT \
- ALIGN_FUNCTION(); \
- VMLINUX_SYMBOL(__idmap_text_start) = .; \
- *(.idmap.text) \
- VMLINUX_SYMBOL(__idmap_text_end) = .; \
- . = ALIGN(PAGE_SIZE); \
- VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \
- *(.hyp.idmap.text) \
- VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
-
-#ifdef CONFIG_HOTPLUG_CPU
-#define ARM_CPU_DISCARD(x)
-#define ARM_CPU_KEEP(x) x
-#else
-#define ARM_CPU_DISCARD(x) x
-#define ARM_CPU_KEEP(x)
-#endif
-
-#if (defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)) || \
- defined(CONFIG_GENERIC_BUG)
-#define ARM_EXIT_KEEP(x) x
-#define ARM_EXIT_DISCARD(x)
-#else
-#define ARM_EXIT_KEEP(x)
-#define ARM_EXIT_DISCARD(x) x
-#endif
+#include "vmlinux.lds.h"
OUTPUT_ARCH(arm)
ENTRY(stext)
@@ -69,20 +38,9 @@ SECTIONS
* unwind sections get included.
*/
/DISCARD/ : {
- *(.ARM.exidx.exit.text)
- *(.ARM.extab.exit.text)
- ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
- ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
- ARM_EXIT_DISCARD(EXIT_TEXT)
- ARM_EXIT_DISCARD(EXIT_DATA)
- EXIT_CALL
-#ifndef CONFIG_MMU
- *(.text.fixup)
- *(__ex_table)
-#endif
+ ARM_DISCARD
*(.alt.smp.init)
- *(.discard)
- *(.discard.*)
+ *(.pv_table)
}
. = XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR);
@@ -95,22 +53,7 @@ SECTIONS
.text : { /* Real text segment */
_stext = .; /* Text and read-only data */
- IDMAP_TEXT
- __entry_text_start = .;
- *(.entry.text)
- __entry_text_end = .;
- IRQENTRY_TEXT
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- KPROBES_TEXT
- *(.gnu.warning)
- *(.glue_7)
- *(.glue_7t)
- . = ALIGN(4);
- *(.got) /* Global offset table */
- ARM_CPU_KEEP(PROC_INFO)
+ ARM_TEXT
}
RO_DATA(PAGE_SIZE)
@@ -118,53 +61,19 @@ SECTIONS
. = ALIGN(4);
__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
__start___ex_table = .;
-#ifdef CONFIG_MMU
- *(__ex_table)
-#endif
+ ARM_MMU_KEEP(*(__ex_table))
__stop___ex_table = .;
}
#ifdef CONFIG_ARM_UNWIND
- /*
- * Stack unwinding tables
- */
- . = ALIGN(8);
- .ARM.unwind_idx : {
- __start_unwind_idx = .;
- *(.ARM.exidx*)
- __stop_unwind_idx = .;
- }
- .ARM.unwind_tab : {
- __start_unwind_tab = .;
- *(.ARM.extab*)
- __stop_unwind_tab = .;
- }
+ ARM_UNWIND_SECTIONS
#endif
NOTES
_etext = .; /* End of text and rodata section */
- /*
- * The vectors and stubs are relocatable code, and the
- * only thing that matters is their relative offsets
- */
- __vectors_start = .;
- .vectors 0xffff0000 : AT(__vectors_start) {
- *(.vectors)
- }
- . = __vectors_start + SIZEOF(.vectors);
- __vectors_end = .;
-
- __stubs_start = .;
- .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) {
- *(.stubs)
- }
- . = __stubs_start + SIZEOF(.stubs);
- __stubs_end = .;
-
- PROVIDE(vector_fiq_offset = vector_fiq - ADDR(.vectors));
-
+ ARM_VECTORS
INIT_TEXT_SECTION(8)
.exit.text : {
ARM_EXIT_KEEP(EXIT_TEXT)
@@ -223,6 +132,10 @@ SECTIONS
PERCPU_SECTION(L1_CACHE_BYTES)
#endif
+#ifdef CONFIG_HAVE_TCM
+ ARM_TCM
+#endif
+
/*
* End of copied data. We need a dummy section to get its LMA.
* Also located before final ALIGN() as trailing padding is not stored
@@ -234,63 +147,6 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
__init_end = .;
-#ifdef CONFIG_HAVE_TCM
- /*
- * We align everything to a page boundary so we can
- * free it after init has commenced and TCM contents have
- * been copied to its destination.
- */
- .tcm_start : {
- . = ALIGN(PAGE_SIZE);
- __tcm_start = .;
- __itcm_start = .;
- }
-
- /*
- * Link these to the ITCM RAM
- * Put VMA to the TCM address and LMA to the common RAM
- * and we'll upload the contents from RAM to TCM and free
- * the used RAM after that.
- */
- .text_itcm ITCM_OFFSET : AT(__itcm_start)
- {
- __sitcm_text = .;
- *(.tcm.text)
- *(.tcm.rodata)
- . = ALIGN(4);
- __eitcm_text = .;
- }
-
- /*
- * Reset the dot pointer, this is needed to create the
- * relative __dtcm_start below (to be used as extern in code).
- */
- . = ADDR(.tcm_start) + SIZEOF(.tcm_start) + SIZEOF(.text_itcm);
-
- .dtcm_start : {
- __dtcm_start = .;
- }
-
- /* TODO: add remainder of ITCM as well, that can be used for data! */
- .data_dtcm DTCM_OFFSET : AT(__dtcm_start)
- {
- . = ALIGN(4);
- __sdtcm_data = .;
- *(.tcm.data)
- . = ALIGN(4);
- __edtcm_data = .;
- }
-
- /* Reset the dot pointer or the linker gets confused */
- . = ADDR(.dtcm_start) + SIZEOF(.data_dtcm);
-
- /* End marker for freeing TCM copy in linked object */
- .tcm_end : AT(ADDR(.dtcm_start) + SIZEOF(.data_dtcm)){
- . = ALIGN(PAGE_SIZE);
- __tcm_end = .;
- }
-#endif
-
BSS_SECTION(0, 0, 8)
_end = .;
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 84a1ae3ce46e..b77dc675ae55 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -15,43 +15,7 @@
#include <asm/page.h>
#include <asm/pgtable.h>
-#define PROC_INFO \
- . = ALIGN(4); \
- VMLINUX_SYMBOL(__proc_info_begin) = .; \
- *(.proc.info.init) \
- VMLINUX_SYMBOL(__proc_info_end) = .;
-
-#define HYPERVISOR_TEXT \
- VMLINUX_SYMBOL(__hyp_text_start) = .; \
- *(.hyp.text) \
- VMLINUX_SYMBOL(__hyp_text_end) = .;
-
-#define IDMAP_TEXT \
- ALIGN_FUNCTION(); \
- VMLINUX_SYMBOL(__idmap_text_start) = .; \
- *(.idmap.text) \
- VMLINUX_SYMBOL(__idmap_text_end) = .; \
- . = ALIGN(PAGE_SIZE); \
- VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \
- *(.hyp.idmap.text) \
- VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
-
-#ifdef CONFIG_HOTPLUG_CPU
-#define ARM_CPU_DISCARD(x)
-#define ARM_CPU_KEEP(x) x
-#else
-#define ARM_CPU_DISCARD(x) x
-#define ARM_CPU_KEEP(x)
-#endif
-
-#if (defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)) || \
- defined(CONFIG_GENERIC_BUG) || defined(CONFIG_JUMP_LABEL)
-#define ARM_EXIT_KEEP(x) x
-#define ARM_EXIT_DISCARD(x)
-#else
-#define ARM_EXIT_KEEP(x)
-#define ARM_EXIT_DISCARD(x) x
-#endif
+#include "vmlinux.lds.h"
OUTPUT_ARCH(arm)
ENTRY(stext)
@@ -74,22 +38,10 @@ SECTIONS
* unwind sections get included.
*/
/DISCARD/ : {
- *(.ARM.exidx.exit.text)
- *(.ARM.extab.exit.text)
- ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
- ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
- ARM_EXIT_DISCARD(EXIT_TEXT)
- ARM_EXIT_DISCARD(EXIT_DATA)
- EXIT_CALL
-#ifndef CONFIG_MMU
- *(.text.fixup)
- *(__ex_table)
-#endif
+ ARM_DISCARD
#ifndef CONFIG_SMP_ON_UP
*(.alt.smp.init)
#endif
- *(.discard)
- *(.discard.*)
}
. = PAGE_OFFSET + TEXT_OFFSET;
@@ -104,24 +56,7 @@ SECTIONS
.text : { /* Real text segment */
_stext = .; /* Text and read-only data */
- IDMAP_TEXT
- __entry_text_start = .;
- *(.entry.text)
- __entry_text_end = .;
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- HYPERVISOR_TEXT
- KPROBES_TEXT
- *(.gnu.warning)
- *(.glue_7)
- *(.glue_7t)
- . = ALIGN(4);
- *(.got) /* Global offset table */
- ARM_CPU_KEEP(PROC_INFO)
+ ARM_TEXT
}
#ifdef CONFIG_DEBUG_ALIGN_RODATA
@@ -134,27 +69,12 @@ SECTIONS
. = ALIGN(4);
__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
__start___ex_table = .;
-#ifdef CONFIG_MMU
- *(__ex_table)
-#endif
+ ARM_MMU_KEEP(*(__ex_table))
__stop___ex_table = .;
}
#ifdef CONFIG_ARM_UNWIND
- /*
- * Stack unwinding tables
- */
- . = ALIGN(8);
- .ARM.unwind_idx : {
- __start_unwind_idx = .;
- *(.ARM.exidx*)
- __stop_unwind_idx = .;
- }
- .ARM.unwind_tab : {
- __start_unwind_tab = .;
- *(.ARM.extab*)
- __stop_unwind_tab = .;
- }
+ ARM_UNWIND_SECTIONS
#endif
NOTES
@@ -166,26 +86,7 @@ SECTIONS
#endif
__init_begin = .;
- /*
- * The vectors and stubs are relocatable code, and the
- * only thing that matters is their relative offsets
- */
- __vectors_start = .;
- .vectors 0xffff0000 : AT(__vectors_start) {
- *(.vectors)
- }
- . = __vectors_start + SIZEOF(.vectors);
- __vectors_end = .;
-
- __stubs_start = .;
- .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) {
- *(.stubs)
- }
- . = __stubs_start + SIZEOF(.stubs);
- __stubs_end = .;
-
- PROVIDE(vector_fiq_offset = vector_fiq - ADDR(.vectors));
-
+ ARM_VECTORS
INIT_TEXT_SECTION(8)
.exit.text : {
ARM_EXIT_KEEP(EXIT_TEXT)
@@ -226,6 +127,10 @@ SECTIONS
PERCPU_SECTION(L1_CACHE_BYTES)
#endif
+#ifdef CONFIG_HAVE_TCM
+ ARM_TCM
+#endif
+
#ifdef CONFIG_STRICT_KERNEL_RWX
. = ALIGN(1<<SECTION_SHIFT);
#else
@@ -237,63 +142,6 @@ SECTIONS
RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
_edata = .;
-#ifdef CONFIG_HAVE_TCM
- /*
- * We align everything to a page boundary so we can
- * free it after init has commenced and TCM contents have
- * been copied to its destination.
- */
- .tcm_start : {
- . = ALIGN(PAGE_SIZE);
- __tcm_start = .;
- __itcm_start = .;
- }
-
- /*
- * Link these to the ITCM RAM
- * Put VMA to the TCM address and LMA to the common RAM
- * and we'll upload the contents from RAM to TCM and free
- * the used RAM after that.
- */
- .text_itcm ITCM_OFFSET : AT(__itcm_start)
- {
- __sitcm_text = .;
- *(.tcm.text)
- *(.tcm.rodata)
- . = ALIGN(4);
- __eitcm_text = .;
- }
-
- /*
- * Reset the dot pointer, this is needed to create the
- * relative __dtcm_start below (to be used as extern in code).
- */
- . = ADDR(.tcm_start) + SIZEOF(.tcm_start) + SIZEOF(.text_itcm);
-
- .dtcm_start : {
- __dtcm_start = .;
- }
-
- /* TODO: add remainder of ITCM as well, that can be used for data! */
- .data_dtcm DTCM_OFFSET : AT(__dtcm_start)
- {
- . = ALIGN(4);
- __sdtcm_data = .;
- *(.tcm.data)
- . = ALIGN(4);
- __edtcm_data = .;
- }
-
- /* Reset the dot pointer or the linker gets confused */
- . = ADDR(.dtcm_start) + SIZEOF(.data_dtcm);
-
- /* End marker for freeing TCM copy in linked object */
- .tcm_end : AT(ADDR(.dtcm_start) + SIZEOF(.data_dtcm)){
- . = ALIGN(PAGE_SIZE);
- __tcm_end = .;
- }
-#endif
-
BSS_SECTION(0, 0, 0)
_end = .;
diff --git a/arch/arm/kernel/vmlinux.lds.h b/arch/arm/kernel/vmlinux.lds.h
new file mode 100644
index 000000000000..71281e08e1d4
--- /dev/null
+++ b/arch/arm/kernel/vmlinux.lds.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_HOTPLUG_CPU
+#define ARM_CPU_DISCARD(x)
+#define ARM_CPU_KEEP(x) x
+#else
+#define ARM_CPU_DISCARD(x) x
+#define ARM_CPU_KEEP(x)
+#endif
+
+#if (defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)) || \
+ defined(CONFIG_GENERIC_BUG) || defined(CONFIG_JUMP_LABEL)
+#define ARM_EXIT_KEEP(x) x
+#define ARM_EXIT_DISCARD(x)
+#else
+#define ARM_EXIT_KEEP(x)
+#define ARM_EXIT_DISCARD(x) x
+#endif
+
+#ifdef CONFIG_MMU
+#define ARM_MMU_KEEP(x) x
+#define ARM_MMU_DISCARD(x)
+#else
+#define ARM_MMU_KEEP(x)
+#define ARM_MMU_DISCARD(x) x
+#endif
+
+#define PROC_INFO \
+ . = ALIGN(4); \
+ VMLINUX_SYMBOL(__proc_info_begin) = .; \
+ *(.proc.info.init) \
+ VMLINUX_SYMBOL(__proc_info_end) = .;
+
+#define HYPERVISOR_TEXT \
+ VMLINUX_SYMBOL(__hyp_text_start) = .; \
+ *(.hyp.text) \
+ VMLINUX_SYMBOL(__hyp_text_end) = .;
+
+#define IDMAP_TEXT \
+ ALIGN_FUNCTION(); \
+ VMLINUX_SYMBOL(__idmap_text_start) = .; \
+ *(.idmap.text) \
+ VMLINUX_SYMBOL(__idmap_text_end) = .; \
+ . = ALIGN(PAGE_SIZE); \
+ VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \
+ *(.hyp.idmap.text) \
+ VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
+
+#define ARM_DISCARD \
+ *(.ARM.exidx.exit.text) \
+ *(.ARM.extab.exit.text) \
+ ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) \
+ ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) \
+ ARM_EXIT_DISCARD(EXIT_TEXT) \
+ ARM_EXIT_DISCARD(EXIT_DATA) \
+ EXIT_CALL \
+ ARM_MMU_DISCARD(*(.text.fixup)) \
+ ARM_MMU_DISCARD(*(__ex_table)) \
+ *(.discard) \
+ *(.discard.*)
+
+#define ARM_TEXT \
+ IDMAP_TEXT \
+ __entry_text_start = .; \
+ *(.entry.text) \
+ __entry_text_end = .; \
+ IRQENTRY_TEXT \
+ SOFTIRQENTRY_TEXT \
+ TEXT_TEXT \
+ SCHED_TEXT \
+ CPUIDLE_TEXT \
+ LOCK_TEXT \
+ HYPERVISOR_TEXT \
+ KPROBES_TEXT \
+ *(.gnu.warning) \
+ *(.glue_7) \
+ *(.glue_7t) \
+ . = ALIGN(4); \
+ *(.got) /* Global offset table */ \
+ ARM_CPU_KEEP(PROC_INFO)
+
+/* Stack unwinding tables */
+#define ARM_UNWIND_SECTIONS \
+ . = ALIGN(8); \
+ .ARM.unwind_idx : { \
+ __start_unwind_idx = .; \
+ *(.ARM.exidx*) \
+ __stop_unwind_idx = .; \
+ } \
+ .ARM.unwind_tab : { \
+ __start_unwind_tab = .; \
+ *(.ARM.extab*) \
+ __stop_unwind_tab = .; \
+ }
+
+/*
+ * The vectors and stubs are relocatable code, and the
+ * only thing that matters is their relative offsets
+ */
+#define ARM_VECTORS \
+ __vectors_start = .; \
+ .vectors 0xffff0000 : AT(__vectors_start) { \
+ *(.vectors) \
+ } \
+ . = __vectors_start + SIZEOF(.vectors); \
+ __vectors_end = .; \
+ \
+ __stubs_start = .; \
+ .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) { \
+ *(.stubs) \
+ } \
+ . = __stubs_start + SIZEOF(.stubs); \
+ __stubs_end = .; \
+ \
+ PROVIDE(vector_fiq_offset = vector_fiq - ADDR(.vectors));
+
+#define ARM_TCM \
+ __itcm_start = ALIGN(4); \
+ .text_itcm ITCM_OFFSET : AT(__itcm_start - LOAD_OFFSET) { \
+ __sitcm_text = .; \
+ *(.tcm.text) \
+ *(.tcm.rodata) \
+ . = ALIGN(4); \
+ __eitcm_text = .; \
+ } \
+ . = __itcm_start + SIZEOF(.text_itcm); \
+ \
+ __dtcm_start = .; \
+ .data_dtcm DTCM_OFFSET : AT(__dtcm_start - LOAD_OFFSET) { \
+ __sdtcm_data = .; \
+ *(.tcm.data) \
+ . = ALIGN(4); \
+ __edtcm_data = .; \
+ } \
+ . = __dtcm_start + SIZEOF(.data_dtcm);
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 6d1d2e26dfe5..3a02e76699a6 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -270,6 +270,60 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu,
return true;
}
+static bool access_cntp_tval(struct kvm_vcpu *vcpu,
+ const struct coproc_params *p,
+ const struct coproc_reg *r)
+{
+ u64 now = kvm_phys_timer_read();
+ u64 val;
+
+ if (p->is_write) {
+ val = *vcpu_reg(vcpu, p->Rt1);
+ kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val + now);
+ } else {
+ val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
+ *vcpu_reg(vcpu, p->Rt1) = val - now;
+ }
+
+ return true;
+}
+
+static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
+ const struct coproc_params *p,
+ const struct coproc_reg *r)
+{
+ u32 val;
+
+ if (p->is_write) {
+ val = *vcpu_reg(vcpu, p->Rt1);
+ kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, val);
+ } else {
+ val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL);
+ *vcpu_reg(vcpu, p->Rt1) = val;
+ }
+
+ return true;
+}
+
+static bool access_cntp_cval(struct kvm_vcpu *vcpu,
+ const struct coproc_params *p,
+ const struct coproc_reg *r)
+{
+ u64 val;
+
+ if (p->is_write) {
+ val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
+ val |= *vcpu_reg(vcpu, p->Rt1);
+ kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val);
+ } else {
+ val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
+ *vcpu_reg(vcpu, p->Rt1) = val;
+ *vcpu_reg(vcpu, p->Rt2) = val >> 32;
+ }
+
+ return true;
+}
+
/*
* We could trap ID_DFR0 and tell the guest we don't support performance
* monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
@@ -423,10 +477,17 @@ static const struct coproc_reg cp15_regs[] = {
{ CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
NULL, reset_unknown, c13_TID_PRIV },
+ /* CNTP */
+ { CRm64(14), Op1( 2), is64, access_cntp_cval},
+
/* CNTKCTL: swapped by interrupt.S. */
{ CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
NULL, reset_val, c14_CNTKCTL, 0x00000000 },
+ /* CNTP */
+ { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval },
+ { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl },
+
/* The Configuration Base Address Register. */
{ CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
};
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index cdff963f133a..9046b53d87c1 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -142,7 +142,7 @@ unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
/*
* Return the SPSR for the current mode of the virtual CPU.
*/
-unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
+unsigned long *__vcpu_spsr(struct kvm_vcpu *vcpu)
{
unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
switch (mode) {
@@ -174,5 +174,5 @@ unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
*/
void kvm_inject_vabt(struct kvm_vcpu *vcpu)
{
- vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) | HCR_VA);
+ *vcpu_hcr(vcpu) |= HCR_VA;
}
diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile
index 63d6b404d88e..7fc0638f263a 100644
--- a/arch/arm/kvm/hyp/Makefile
+++ b/arch/arm/kvm/hyp/Makefile
@@ -9,7 +9,6 @@ KVM=../../../../virt/kvm
CFLAGS_ARMV7VE :=$(call cc-option, -march=armv7ve)
-obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c
index ae45ae96aac2..acf1c37fa49c 100644
--- a/arch/arm/kvm/hyp/switch.c
+++ b/arch/arm/kvm/hyp/switch.c
@@ -44,7 +44,7 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host)
isb();
}
- write_sysreg(vcpu->arch.hcr | vcpu->arch.irq_lines, HCR);
+ write_sysreg(vcpu->arch.hcr, HCR);
/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
write_sysreg(HSTR_T(15), HSTR);
write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR);
@@ -90,18 +90,18 @@ static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
{
- if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
__vgic_v3_save_state(vcpu);
- else
- __vgic_v2_save_state(vcpu);
+ __vgic_v3_deactivate_traps(vcpu);
+ }
}
static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
{
- if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
+ __vgic_v3_activate_traps(vcpu);
__vgic_v3_restore_state(vcpu);
- else
- __vgic_v2_restore_state(vcpu);
+ }
}
static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
@@ -154,7 +154,7 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
return true;
}
-int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
+int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
{
struct kvm_cpu_context *host_ctxt;
struct kvm_cpu_context *guest_ctxt;
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6d870421a7a6..1254bf9d91b4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,5 @@
menuconfig ARCH_AT91
- bool "Atmel SoCs"
+ bool "AT91/Microchip SoCs"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
select COMMON_CLK_AT91
@@ -13,7 +13,7 @@ config SOC_SAMV7
select COMMON_CLK_AT91
select PINCTRL_AT91
help
- Select this if you are using an SoC from Atmel's SAME7, SAMS7 or SAMV7
+ Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
families.
config SOC_SAMA5D2
@@ -29,7 +29,7 @@ config SOC_SAMA5D2
select HAVE_AT91_AUDIO_PLL
select PINCTRL_AT91PIO4
help
- Select this if ou are using one of Atmel's SAMA5D2 family SoC.
+ Select this if ou are using one of Microchip's SAMA5D2 family SoC.
config SOC_SAMA5D3
bool "SAMA5D3 family"
@@ -41,7 +41,7 @@ config SOC_SAMA5D3
select HAVE_AT91_USB_CLK
select PINCTRL_AT91
help
- Select this if you are using one of Atmel's SAMA5D3 family SoC.
+ Select this if you are using one of Microchip's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
config SOC_SAMA5D4
@@ -56,7 +56,7 @@ config SOC_SAMA5D4
select HAVE_AT91_H32MX
select PINCTRL_AT91
help
- Select this if you are using one of Atmel's SAMA5D4 family SoC.
+ Select this if you are using one of Microchip's SAMA5D4 family SoC.
config SOC_AT91RM9200
bool "AT91RM9200"
@@ -70,7 +70,7 @@ config SOC_AT91RM9200
select SOC_SAM_V4_V5
select SRAM if PM
help
- Select this if you are using Atmel's AT91RM9200 SoC.
+ Select this if you are using Microchip's AT91RM9200 SoC.
config SOC_AT91SAM9
bool "AT91SAM9"
@@ -88,7 +88,7 @@ config SOC_AT91SAM9
select SOC_SAM_V4_V5
select SRAM if PM
help
- Select this if you are using one of those Atmel SoC:
+ Select this if you are using one of those Microchip SoC:
AT91SAM9260
AT91SAM9261
AT91SAM9263
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index f673cd7a6766..004f9c8de032 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -239,20 +239,6 @@ static inline void da830_evm_init_mmc(void)
}
}
-/*
- * UI board NAND/NOR flashes only use 8-bit data bus.
- */
-static const short da830_evm_emif25_pins[] = {
- DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
- DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
- DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
- DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
- DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
- DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
- DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
- -1
-};
-
#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
#ifdef CONFIG_DA830_UI_NAND
@@ -357,6 +343,20 @@ static struct platform_device da830_evm_nand_device = {
.resource = da830_evm_nand_resources,
};
+/*
+ * UI board NAND/NOR flashes only use 8-bit data bus.
+ */
+static const short da830_evm_emif25_pins[] = {
+ DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
+ DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
+ DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
+ DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
+ DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
+ DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
+ DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
+ -1
+};
+
static inline void da830_evm_init_nand(int mux_mode)
{
int ret;
@@ -551,10 +551,6 @@ static __init void da830_evm_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
int ret;
- ret = da8xx_register_cfgchip();
- if (ret)
- pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
-
ret = da830_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@@ -638,9 +634,8 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
.atag_offset = 0x100,
.map_io = da830_evm_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da830_init_time,
.init_machine = da830_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = da8xx_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index d898a94f6eae..3063478bcc36 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1334,10 +1334,6 @@ static __init void da850_evm_init(void)
{
int ret;
- ret = da8xx_register_cfgchip();
- if (ret)
- pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
-
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@@ -1481,10 +1477,9 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.atag_offset = 0x100,
.map_io = da850_evm_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = da850_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = da8xx_restart,
.reserve = da8xx_rproc_reserve_cma,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index d6b11907380c..cb30637d9eaf 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -427,9 +427,8 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.atag_offset = 0x100,
.map_io = dm355_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm355_init_time,
.init_machine = dm355_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index fad9a5611a5d..59743bd76793 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -271,9 +271,8 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.atag_offset = 0x100,
.map_io = dm355_leopard_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm355_init_time,
.init_machine = dm355_leopard_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index e3780986d2a3..0ac085b58a2b 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -774,10 +774,9 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.atag_offset = 0x100,
.map_io = dm365_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm365_init_time,
.init_machine = dm365_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 85e6fb33b1ee..95b55aae1366 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -828,9 +828,8 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
.atag_offset = 0x100,
.map_io = davinci_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index cb0a41e83582..2d37f5b0e1f5 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -44,10 +44,8 @@
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/serial.h>
-#include <mach/clock.h>
#include "davinci.h"
-#include "clock.h"
#define NAND_BLOCK_SIZE SZ_128K
@@ -716,14 +714,23 @@ static void __init evm_init_i2c(void)
}
#endif
+#define DM646X_REF_FREQ 27000000
+#define DM646X_AUX_FREQ 24000000
#define DM6467T_EVM_REF_FREQ 33000000
static void __init davinci_map_io(void)
{
dm646x_init();
+}
- if (machine_is_davinci_dm6467tevm())
- davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
+static void __init dm646x_evm_init_time(void)
+{
+ dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ);
+}
+
+static void __init dm6467t_evm_init_time(void)
+{
+ dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ);
}
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
@@ -797,21 +804,19 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm646x_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm6467t_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index b73ce7bae81f..d1c85484c2e2 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -502,10 +502,6 @@ static void __init mityomapl138_init(void)
{
int ret;
- ret = da8xx_register_cfgchip();
- if (ret)
- pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
-
/* for now, no special EDMA channels are reserved */
ret = da850_register_edma(NULL);
if (ret)
@@ -570,9 +566,8 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
.atag_offset = 0x100,
.map_io = mityomapl138_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = mityomapl138_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = da8xx_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 4da210a1a110..f2875770fbff 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -227,9 +227,8 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
.atag_offset = 0x100,
.map_io = davinci_ntosd2_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_ntosd2_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index a3e78074be70..0d32042b728f 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -127,8 +127,8 @@ static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
- GPIO_LOOKUP("davinci_gpio.1", 28, "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio.1", 29, "wp", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("davinci_gpio.0", 28, "cd", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("davinci_gpio.0", 29, "wp", GPIO_ACTIVE_LOW),
},
};
@@ -281,10 +281,6 @@ static __init void omapl138_hawk_init(void)
{
int ret;
- ret = da8xx_register_cfgchip();
- if (ret)
- pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
-
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@@ -334,10 +330,9 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.atag_offset = 0x100,
.map_io = omapl138_hawk_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = omapl138_hawk_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = da8xx_restart,
.reserve = da8xx_rproc_reserve_cma,
MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index d85accf7f760..2922da9d1684 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -150,9 +150,8 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.atag_offset = 0x100,
.map_io = davinci_sffsdr_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_sffsdr_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
- .restart = davinci_restart,
MACHINE_END
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index fa2b83752e03..d7894d5aaa25 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -135,9 +135,6 @@ int davinci_clk_reset(struct clk *clk, bool reset);
void davinci_clk_enable(struct clk *clk);
void davinci_clk_disable(struct clk *clk);
-extern struct platform_device davinci_wdt_device;
-extern void davinci_watchdog_reset(struct platform_device *);
-
#endif
#endif
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 57ab18cf2a89..350d7673aa4d 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1200,7 +1200,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da830_ids,
.ids_num = ARRAY_SIZE(da830_ids),
- .cpu_clks = da830_clks,
.psc_bases = da830_psc_bases,
.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
@@ -1220,6 +1219,10 @@ void __init da830_init(void)
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
+}
- davinci_clk_init(davinci_soc_info_da830.cpu_clks);
+void __init da830_init_time(void)
+{
+ davinci_clk_init(da830_clks);
+ davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index aa37cbdf7d4d..34117e614e08 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1353,7 +1353,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da850_ids,
.ids_num = ARRAY_SIZE(da850_ids),
- .cpu_clks = da850_clks,
.psc_bases = da850_psc_bases,
.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
@@ -1392,6 +1391,10 @@ void __init da850_init(void)
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+}
- davinci_clk_init(davinci_soc_info_da850.cpu_clks);
+void __init da850_init_time(void)
+{
+ davinci_clk_init(da850_clks);
+ davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index f06db6700ab2..ab199f4b9ce4 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -96,11 +96,10 @@ static const char *const da850_boards_compat[] __initconst = {
DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
.map_io = da850_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = da850_init_machine,
.dt_compat = da850_boards_compat,
.init_late = davinci_init_late,
- .restart = da8xx_restart,
MACHINE_END
#endif
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index c62b90c6118a..270cef85750a 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -83,6 +83,7 @@ int davinci_init_wdt(void);
/* DM355 function declarations */
void dm355_init(void);
+void dm355_init_time(void);
void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len);
void dm355_init_asp1(u32 evt_enable);
@@ -91,6 +92,7 @@ int dm355_gpio_register(void);
/* DM365 function declarations */
void dm365_init(void);
+void dm365_init_time(void);
void dm365_init_asp(void);
void dm365_init_vc(void);
void dm365_init_ks(struct davinci_ks_platform_data *pdata);
@@ -102,12 +104,14 @@ int dm365_gpio_register(void);
/* DM644x function declarations */
void dm644x_init(void);
+void dm644x_init_time(void);
void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
int dm644x_gpio_register(void);
/* DM646x function declarations */
void dm646x_init(void);
+void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index e1c40e73d30a..78390c64e6ca 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -11,7 +11,6 @@
* (at your option) any later version.
*/
#include <linux/init.h>
-#include <linux/platform_data/syscon.h>
#include <linux/platform_device.h>
#include <linux/dma-contiguous.h>
#include <linux/serial_8250.h>
@@ -371,19 +370,6 @@ static struct platform_device da8xx_wdt_device = {
.resource = da8xx_watchdog_resources,
};
-void da8xx_restart(enum reboot_mode mode, const char *cmd)
-{
- struct device *dev;
-
- dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
- if (!dev) {
- pr_err("%s: failed to find watchdog device\n", __func__);
- return;
- }
-
- davinci_watchdog_reset(to_platform_device(dev));
-}
-
int __init da8xx_register_watchdog(void)
{
return platform_device_register(&da8xx_wdt_device);
@@ -1118,29 +1104,30 @@ int __init da850_register_sata(unsigned long refclkpn)
}
#endif
-static struct syscon_platform_data da8xx_cfgchip_platform_data = {
- .label = "cfgchip",
-};
-
-static struct resource da8xx_cfgchip_resources[] = {
- {
- .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG,
- .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3,
- .flags = IORESOURCE_MEM,
- },
-};
+static struct regmap *da8xx_cfgchip;
-static struct platform_device da8xx_cfgchip_device = {
- .name = "syscon",
- .id = -1,
- .dev = {
- .platform_data = &da8xx_cfgchip_platform_data,
- },
- .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources),
- .resource = da8xx_cfgchip_resources,
+static const struct regmap_config da8xx_cfgchip_config __initconst = {
+ .name = "cfgchip",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
};
-int __init da8xx_register_cfgchip(void)
+/**
+ * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
+ *
+ * This is for use on non-DT boards only. For DT boards, use
+ * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
+ *
+ * Returns: Pointer to the CFGCHIP regmap or negative error code.
+ */
+struct regmap * __init da8xx_get_cfgchip(void)
{
- return platform_device_register(&da8xx_cfgchip_device);
+ if (IS_ERR_OR_NULL(da8xx_cfgchip))
+ da8xx_cfgchip = regmap_init_mmio(NULL,
+ DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
+ &da8xx_cfgchip_config);
+
+ return da8xx_cfgchip;
}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3ae70f2909b0..0edda4093e47 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -282,18 +282,13 @@ static struct resource wdt_resources[] = {
},
};
-struct platform_device davinci_wdt_device = {
+static struct platform_device davinci_wdt_device = {
.name = "davinci-wdt",
.id = -1,
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
};
-void davinci_restart(enum reboot_mode mode, const char *cmd)
-{
- davinci_watchdog_reset(&davinci_wdt_device);
-}
-
int davinci_init_wdt(void)
{
return platform_device_register(&davinci_wdt_device);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 938747f20c22..f29480495c18 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1012,7 +1012,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
.jtag_id_reg = 0x01c40028,
.ids = dm355_ids,
.ids_num = ARRAY_SIZE(dm355_ids),
- .cpu_clks = dm355_clks,
.psc_bases = dm355_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -1043,7 +1042,12 @@ void __init dm355_init(void)
{
davinci_common_init(&davinci_soc_info_dm355);
davinci_map_sysmod();
- davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
+}
+
+void __init dm355_init_time(void)
+{
+ davinci_clk_init(dm355_clks);
+ davinci_timer_init();
}
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 5d9f96df08e9..1e3df9df1e10 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1116,7 +1116,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
.jtag_id_reg = 0x01c40028,
.ids = dm365_ids,
.ids_num = ARRAY_SIZE(dm365_ids),
- .cpu_clks = dm365_clks,
.psc_bases = dm365_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -1168,7 +1167,12 @@ void __init dm365_init(void)
{
davinci_common_init(&davinci_soc_info_dm365);
davinci_map_sysmod();
- davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
+}
+
+void __init dm365_init_time(void)
+{
+ davinci_clk_init(dm365_clks);
+ davinci_timer_init();
}
static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 6b41e1ca511e..b409801649e1 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -905,7 +905,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.jtag_id_reg = 0x01c40028,
.ids = dm644x_ids,
.ids_num = ARRAY_SIZE(dm644x_ids),
- .cpu_clks = dm644x_clks,
.psc_bases = dm644x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -931,7 +930,12 @@ void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_map_sysmod();
- davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
+}
+
+void __init dm644x_init_time(void)
+{
+ davinci_clk_init(dm644x_clks);
+ davinci_timer_init();
}
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 6fc06a6ad4f8..109ab1fa0d2c 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -39,12 +39,6 @@
#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
BIT_MASK(8))
-/*
- * Device specific clocks
- */
-#define DM646X_REF_FREQ 27000000
-#define DM646X_AUX_FREQ 24000000
-
#define DM646X_EMAC_BASE 0x01c80000
#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
#define DM646X_EMAC_CNTRL_OFFSET 0x0000
@@ -64,13 +58,12 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = {
.name = "ref_clk",
- .rate = DM646X_REF_FREQ,
- .set_rate = davinci_simple_set_rate,
+ /* rate is initialized in dm646x_init_time() */
};
static struct clk aux_clkin = {
.name = "aux_clkin",
- .rate = DM646X_AUX_FREQ,
+ /* rate is initialized in dm646x_init_time() */
};
static struct clk pll1_clk = {
@@ -888,7 +881,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
.jtag_id_reg = 0x01c40028,
.ids = dm646x_ids,
.ids_num = ARRAY_SIZE(dm646x_ids),
- .cpu_clks = dm646x_clks,
.psc_bases = dm646x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -956,7 +948,15 @@ void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_map_sysmod();
- davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
+}
+
+void __init dm646x_init_time(unsigned long ref_clk_rate,
+ unsigned long aux_clkin_rate)
+{
+ ref_clk.rate = ref_clk_rate;
+ aux_clkin.rate = aux_clkin_rate;
+ davinci_clk_init(dm646x_clks);
+ davinci_timer_init();
}
static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 433a008ff796..f0d5e858f158 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -53,7 +53,6 @@ struct davinci_soc_info {
u32 jtag_id_reg;
struct davinci_id *ids;
unsigned long ids_num;
- struct clk_lookup *cpu_clks;
u32 *psc_bases;
unsigned long psc_bases_num;
u32 pinmux_base;
@@ -81,7 +80,6 @@ extern struct davinci_soc_info davinci_soc_info;
extern void davinci_common_init(const struct davinci_soc_info *soc_info);
extern void davinci_init_ide(void);
-void davinci_restart(enum reboot_mode mode, const char *cmd);
void davinci_init_late(void);
#ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 93ff1569cee5..9fd6d0125762 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -18,6 +18,7 @@
#include <linux/spi/spi.h>
#include <linux/platform_data/davinci_asp.h>
#include <linux/reboot.h>
+#include <linux/regmap.h>
#include <linux/videodev2.h>
#include <mach/serial.h>
@@ -87,7 +88,10 @@ extern unsigned int da850_max_speed;
#define DA8XX_ARM_RAM_BASE 0xffff0000
void da830_init(void);
+void da830_init_time(void);
+
void da850_init(void);
+void da850_init_time(void);
int da830_register_edma(struct edma_rsv_info *rsv);
int da850_register_edma(struct edma_rsv_info *rsv[2]);
@@ -118,12 +122,11 @@ int da850_register_vpif_display
(struct vpif_display_config *display_config);
int da850_register_vpif_capture
(struct vpif_capture_config *capture_config);
-void da8xx_restart(enum reboot_mode mode, const char *cmd);
void da8xx_rproc_reserve_cma(void);
int da8xx_register_rproc(void);
int da850_register_gpio(void);
int da830_register_gpio(void);
-int da8xx_register_cfgchip(void);
+struct regmap *da8xx_get_cfgchip(void);
extern struct platform_device da8xx_serial_device[];
extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 034f865fe78e..1bb991ad9c1e 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -80,13 +80,6 @@ enum {
#define TGCR_UNRESET 0x1
#define TGCR_RESET_MASK 0x3
-#define WDTCR_WDEN_SHIFT 14
-#define WDTCR_WDEN_DISABLE 0x0
-#define WDTCR_WDEN_ENABLE 0x1
-#define WDTCR_WDKEY_SHIFT 16
-#define WDTCR_WDKEY_SEQ0 0xa5c6
-#define WDTCR_WDKEY_SEQ1 0xda7e
-
struct timer_s {
char *name;
unsigned int id;
@@ -409,53 +402,3 @@ void __init davinci_timer_init(void)
for (i=0; i< ARRAY_SIZE(timers); i++)
timer32_config(&timers[i]);
}
-
-/* reset board using watchdog timer */
-void davinci_watchdog_reset(struct platform_device *pdev)
-{
- u32 tgcr, wdtcr;
- void __iomem *base;
- struct clk *wd_clk;
-
- base = ioremap(pdev->resource[0].start, SZ_4K);
- if (WARN_ON(!base))
- return;
-
- wd_clk = clk_get(&pdev->dev, NULL);
- if (WARN_ON(IS_ERR(wd_clk)))
- return;
- clk_prepare_enable(wd_clk);
-
- /* disable, internal clock source */
- __raw_writel(0, base + TCR);
-
- /* reset timer, set mode to 64-bit watchdog, and unreset */
- tgcr = 0;
- __raw_writel(tgcr, base + TGCR);
- tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
- tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
- (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
- __raw_writel(tgcr, base + TGCR);
-
- /* clear counter and period regs */
- __raw_writel(0, base + TIM12);
- __raw_writel(0, base + TIM34);
- __raw_writel(0, base + PRD12);
- __raw_writel(0, base + PRD34);
-
- /* put watchdog in pre-active state */
- wdtcr = __raw_readl(base + WDTCR);
- wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
- (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
- __raw_writel(wdtcr, base + WDTCR);
-
- /* put watchdog in active state */
- wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
- (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
- __raw_writel(wdtcr, base + WDTCR);
-
- /* write an invalid value to the WDKEY field to trigger
- * a watchdog reset */
- wdtcr = 0x00004000;
- __raw_writel(wdtcr, base + WDTCR);
-}
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
index d480a02e1298..50445f0e98de 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -8,6 +8,7 @@
#include <linux/init.h>
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/phy/phy.h>
+#include <linux/platform_data/phy-da8xx-usb.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_device.h>
#include <linux/usb/musb.h>
@@ -25,6 +26,8 @@
static struct clk *usb20_clk;
+static struct da8xx_usb_phy_platform_data da8xx_usb_phy_pdata;
+
static struct platform_device da8xx_usb_phy = {
.name = "da8xx-usb-phy",
.id = -1,
@@ -35,11 +38,14 @@ static struct platform_device da8xx_usb_phy = {
* registered yet.
*/
.init_name = "da8xx-usb-phy",
+ .platform_data = &da8xx_usb_phy_pdata,
},
};
int __init da8xx_register_usb_phy(void)
{
+ da8xx_usb_phy_pdata.cfgchip = da8xx_get_cfgchip();
+
return platform_device_register(&da8xx_usb_phy);
}
@@ -256,14 +262,14 @@ static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent)
}
static struct clk usb20_phy_clk = {
- .name = "usb20_phy",
+ .name = "usb0_clk48",
.clk_enable = usb20_phy_clk_enable,
.clk_disable = usb20_phy_clk_disable,
.set_parent = usb20_phy_clk_set_parent,
};
static struct clk_lookup usb20_phy_clk_lookup =
- CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk);
+ CLK("da8xx-usb-phy", "usb0_clk48", &usb20_phy_clk);
/**
* da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
@@ -320,18 +326,18 @@ static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent)
}
static struct clk usb11_phy_clk = {
- .name = "usb11_phy",
+ .name = "usb1_clk48",
.set_parent = usb11_phy_clk_set_parent,
};
static struct clk_lookup usb11_phy_clk_lookup =
- CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk);
+ CLK("da8xx-usb-phy", "usb1_clk48", &usb11_phy_clk);
/**
* da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
*
* @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
- * or "usb20_phy" if false.
+ * or "usb0_clk48" if false.
*/
int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
{
@@ -341,7 +347,7 @@ int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
if (use_usb_refclkin)
parent = clk_get(NULL, "usb_refclkin");
else
- parent = clk_get(&da8xx_usb_phy.dev, "usb20_phy");
+ parent = clk_get(&da8xx_usb_phy.dev, "usb0_clk48");
if (IS_ERR(parent))
return PTR_ERR(parent);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fbd108ce8745..8c4f5e342dc1 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -192,7 +192,8 @@ static void __init exynos_dt_machine_init(void)
#endif
if (of_machine_is_compatible("samsung,exynos4210") ||
(of_machine_is_compatible("samsung,exynos4412") &&
- of_machine_is_compatible("samsung,trats2")) ||
+ (of_machine_is_compatible("samsung,trats2") ||
+ of_machine_is_compatible("samsung,midas"))) ||
of_machine_is_compatible("samsung,exynos3250") ||
of_machine_is_compatible("samsung,exynos5250"))
platform_device_register(&exynos_cpuidle);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index dc4346ecf16d..a822c5073715 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -163,7 +163,7 @@ void exynos_enter_aftr(void)
exynos_pm_central_suspend();
- if (of_machine_is_compatible("samsung,exynos4412")) {
+ if (soc_is_exynos4412()) {
/* Setting SEQ_OPTION register */
pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
S5P_CENTRAL_SEQ_OPTION);
@@ -271,11 +271,7 @@ abort:
goto fail;
call_firmware_op(cpu_boot, 1);
-
- if (soc_is_exynos3250())
- dsb_sev();
- else
- arch_send_wakeup_ipi_mask(cpumask_of(1));
+ dsb_sev();
}
}
fail:
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 782699e67600..e47fa13f4b0c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -32,18 +32,6 @@ config MXC_DEBUG_BOARD
data/address de-multiplexing and decode, signal level shift,
interrupt control and various board functions.
-config HAVE_EPIT
- bool
-
-config MXC_USE_EPIT
- bool "Use EPIT instead of GPT"
- depends on HAVE_EPIT
- help
- Use EPIT as the system timer on systems that have it. Normally you
- don't have a reason to do so as the EPIT has the same features and
- uses the same clocks as the GPT. Anyway, on some systems the GPT
- may be in use for other purposes.
-
config HAVE_IMX_ANATOP
bool
@@ -85,7 +73,6 @@ config SOC_IMX31
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
- select HAVE_EPIT
select MXC_AVIC
select PINCTRL_IMX35
@@ -482,7 +469,7 @@ config SOC_IMX53
config SOC_IMX6
bool
- select ARM_CPU_SUSPEND if PM
+ select ARM_CPU_SUSPEND if (PM || CPU_IDLE)
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select ARM_GIC
@@ -512,6 +499,13 @@ config SOC_IMX6SL
help
This enables support for Freescale i.MX6 SoloLite processor.
+config SOC_IMX6SLL
+ bool "i.MX6 SoloLiteLite support"
+ select SOC_IMX6
+
+ help
+ This enables support for Freescale i.MX6 SoloLiteLite processor.
+
config SOC_IMX6SX
bool "i.MX6 SoloX support"
select PINCTRL_IMX6SX
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ff71058207d..2327e3e876d8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -20,13 +20,13 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_MXC_AVIC) += avic.o
-obj-$(CONFIG_MXC_USE_EPIT) += epit.o
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
+obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o
endif
@@ -78,6 +78,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
endif
obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
+obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 649a84c251ad..61f3d94f1633 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@@ -116,6 +117,7 @@ void __init imx_init_revision_from_anatop(void)
unsigned int revision;
u32 digprog;
u16 offset = ANADIG_DIGPROG;
+ u8 major_part, minor_part;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
@@ -127,45 +129,25 @@ void __init imx_init_revision_from_anatop(void)
digprog = readl_relaxed(anatop_base + offset);
iounmap(anatop_base);
- switch (digprog & 0xff) {
- case 0:
- /*
- * For i.MX6QP, most of the code for i.MX6Q can be resued,
- * so internally, we identify it as i.MX6Q Rev 2.0
- */
- if (digprog >> 8 & 0x01)
- revision = IMX_CHIP_REVISION_2_0;
- else
- revision = IMX_CHIP_REVISION_1_0;
- break;
- case 1:
- revision = IMX_CHIP_REVISION_1_1;
- break;
- case 2:
- revision = IMX_CHIP_REVISION_1_2;
- break;
- case 3:
- revision = IMX_CHIP_REVISION_1_3;
- break;
- case 4:
- revision = IMX_CHIP_REVISION_1_4;
- break;
- case 5:
- /*
- * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
- * as 'D' in Part Number last character.
- */
- revision = IMX_CHIP_REVISION_1_5;
- break;
- default:
+ /*
+ * On i.MX7D digprog value match linux version format, so
+ * it needn't map again and we can use register value directly.
+ */
+ if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
+ revision = digprog & 0xff;
+ } else {
/*
- * Fail back to return raw register value instead of 0xff.
- * It will be easy to know version information in SOC if it
- * can't be recognized by known version. And some chip's (i.MX7D)
- * digprog value match linux version format, so it needn't map
- * again and we can use register value directly.
+ * MAJOR: [15:8], the major silicon revison;
+ * MINOR: [7: 0], the minor silicon revison;
+ *
+ * please refer to the i.MX RM for the detailed
+ * silicon revison bit define.
+ * format the major part and minor part to match the
+ * linux kernel soc version format.
*/
- revision = digprog & 0xff;
+ major_part = (digprog >> 8) & 0xf;
+ minor_part = digprog & 0xf;
+ revision = ((major_part + 1) << 4) | minor_part;
}
mxc_set_cpu_type(digprog >> 16 & 0xff);
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 1afccae0420c..c0434a36687a 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -22,6 +22,7 @@
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
@@ -51,7 +52,12 @@
#define AVIC_NUM_IRQS 64
+/* low power interrupt mask registers */
+#define MX25_CCM_LPIMR0 0x68
+#define MX25_CCM_LPIMR1 0x6C
+
static void __iomem *avic_base;
+static void __iomem *mx25_ccm_base;
static struct irq_domain *domain;
#ifdef CONFIG_FIQ
@@ -93,6 +99,18 @@ static void avic_irq_suspend(struct irq_data *d)
avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
imx_writel(gc->wake_active, avic_base + ct->regs.mask);
+
+ if (mx25_ccm_base) {
+ u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
+ MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
+ /*
+ * The interrupts which are still enabled will be used as wakeup
+ * sources. Allow those interrupts in low-power mode.
+ * The LPIMR registers use 0 to allow an interrupt, the AVIC
+ * registers use 1.
+ */
+ imx_writel(~gc->wake_active, mx25_ccm_base + offs);
+ }
}
static void avic_irq_resume(struct irq_data *d)
@@ -102,6 +120,13 @@ static void avic_irq_resume(struct irq_data *d)
int idx = d->hwirq >> 5;
imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
+
+ if (mx25_ccm_base) {
+ u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
+ MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
+
+ imx_writel(0xffffffff, mx25_ccm_base + offs);
+ }
}
#else
@@ -158,6 +183,18 @@ void __init mxc_init_irq(void __iomem *irqbase)
avic_base = irqbase;
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
+ mx25_ccm_base = of_iomap(np, 0);
+
+ if (mx25_ccm_base) {
+ /*
+ * By default, we mask all interrupts. We set the actual mask
+ * before we go into low-power mode.
+ */
+ imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
+ imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
+ }
+
/* put the AVIC into the reset value with
* all interrupts disabled
*/
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d4e55f2a897e..32969f34486a 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -135,6 +135,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX6ULL:
soc_id = "i.MX6ULL";
break;
+ case MXC_CPU_IMX6SLL:
+ soc_id = "i.MX6SLL";
+ break;
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
index 8d866fb674a8..fa8ead145d17 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sl.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -12,6 +12,7 @@
#include "common.h"
#include "cpuidle.h"
+#include "hardware.h"
static int imx6sl_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
@@ -21,9 +22,11 @@ static int imx6sl_enter_wait(struct cpuidle_device *dev,
* Software workaround for ERR005311, see function
* description for details.
*/
- imx6sl_set_wait_clk(true);
+ if (cpu_is_imx6sl())
+ imx6sl_set_wait_clk(true);
cpu_do_idle();
- imx6sl_set_wait_clk(false);
+ if (cpu_is_imx6sl())
+ imx6sl_set_wait_clk(false);
imx6_set_lpm(WAIT_CLOCKED);
return index;
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c
index c5a5c3a70ab1..d0f14b761ff7 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -89,6 +89,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = {
*/
.exit_latency = 300,
.target_residency = 500,
+ .flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sx_enter_wait,
.name = "LOW-POWER-IDLE",
.desc = "ARM power off",
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
deleted file mode 100644
index fb9a73a57d00..000000000000
--- a/arch/arm/mach-imx/epit.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * linux/arch/arm/plat-mxc/epit.c
- *
- * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#define EPITCR 0x00
-#define EPITSR 0x04
-#define EPITLR 0x08
-#define EPITCMPR 0x0c
-#define EPITCNR 0x10
-
-#define EPITCR_EN (1 << 0)
-#define EPITCR_ENMOD (1 << 1)
-#define EPITCR_OCIEN (1 << 2)
-#define EPITCR_RLD (1 << 3)
-#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
-#define EPITCR_SWR (1 << 16)
-#define EPITCR_IOVW (1 << 17)
-#define EPITCR_DBGEN (1 << 18)
-#define EPITCR_WAITEN (1 << 19)
-#define EPITCR_RES (1 << 20)
-#define EPITCR_STOPEN (1 << 21)
-#define EPITCR_OM_DISCON (0 << 22)
-#define EPITCR_OM_TOGGLE (1 << 22)
-#define EPITCR_OM_CLEAR (2 << 22)
-#define EPITCR_OM_SET (3 << 22)
-#define EPITCR_CLKSRC_OFF (0 << 24)
-#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
-#define EPITCR_CLKSRC_REF_HIGH (1 << 24)
-#define EPITCR_CLKSRC_REF_LOW (3 << 24)
-
-#define EPITSR_OCIF (1 << 0)
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "hardware.h"
-
-static struct clock_event_device clockevent_epit;
-
-static void __iomem *timer_base;
-
-static inline void epit_irq_disable(void)
-{
- u32 val;
-
- val = imx_readl(timer_base + EPITCR);
- val &= ~EPITCR_OCIEN;
- imx_writel(val, timer_base + EPITCR);
-}
-
-static inline void epit_irq_enable(void)
-{
- u32 val;
-
- val = imx_readl(timer_base + EPITCR);
- val |= EPITCR_OCIEN;
- imx_writel(val, timer_base + EPITCR);
-}
-
-static void epit_irq_acknowledge(void)
-{
- imx_writel(EPITSR_OCIF, timer_base + EPITSR);
-}
-
-static int __init epit_clocksource_init(struct clk *timer_clk)
-{
- unsigned int c = clk_get_rate(timer_clk);
-
- return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32,
- clocksource_mmio_readl_down);
-}
-
-/* clock event */
-
-static int epit_set_next_event(unsigned long evt,
- struct clock_event_device *unused)
-{
- unsigned long tcmp;
-
- tcmp = imx_readl(timer_base + EPITCNR);
-
- imx_writel(tcmp - evt, timer_base + EPITCMPR);
-
- return 0;
-}
-
-/* Left event sources disabled, no more interrupts appear */
-static int epit_shutdown(struct clock_event_device *evt)
-{
- unsigned long flags;
-
- /*
- * The timer interrupt generation is disabled at least
- * for enough time to call epit_set_next_event()
- */
- local_irq_save(flags);
-
- /* Disable interrupt in GPT module */
- epit_irq_disable();
-
- /* Clear pending interrupt */
- epit_irq_acknowledge();
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-static int epit_set_oneshot(struct clock_event_device *evt)
-{
- unsigned long flags;
-
- /*
- * The timer interrupt generation is disabled at least
- * for enough time to call epit_set_next_event()
- */
- local_irq_save(flags);
-
- /* Disable interrupt in GPT module */
- epit_irq_disable();
-
- /* Clear pending interrupt, only while switching mode */
- if (!clockevent_state_oneshot(evt))
- epit_irq_acknowledge();
-
- /*
- * Do not put overhead of interrupt enable/disable into
- * epit_set_next_event(), the core has about 4 minutes
- * to call epit_set_next_event() or shutdown clock after
- * mode switching
- */
- epit_irq_enable();
- local_irq_restore(flags);
-
- return 0;
-}
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = &clockevent_epit;
-
- epit_irq_acknowledge();
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction epit_timer_irq = {
- .name = "i.MX EPIT Timer Tick",
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .handler = epit_timer_interrupt,
-};
-
-static struct clock_event_device clockevent_epit = {
- .name = "epit",
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .set_state_shutdown = epit_shutdown,
- .tick_resume = epit_shutdown,
- .set_state_oneshot = epit_set_oneshot,
- .set_next_event = epit_set_next_event,
- .rating = 200,
-};
-
-static int __init epit_clockevent_init(struct clk *timer_clk)
-{
- clockevent_epit.cpumask = cpumask_of(0);
- clockevents_config_and_register(&clockevent_epit,
- clk_get_rate(timer_clk),
- 0x800, 0xfffffffe);
-
- return 0;
-}
-
-void __init epit_timer_init(void __iomem *base, int irq)
-{
- struct clk *timer_clk;
-
- timer_clk = clk_get_sys("imx-epit.0", NULL);
- if (IS_ERR(timer_clk)) {
- pr_err("i.MX epit: unable to get clk\n");
- return;
- }
-
- clk_prepare_enable(timer_clk);
-
- timer_base = base;
-
- /*
- * Initialise to a known state (all timers off, and timing reset)
- */
- imx_writel(0x0, timer_base + EPITCR);
-
- imx_writel(0xffffffff, timer_base + EPITLR);
- imx_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
- timer_base + EPITCR);
-
- /* init and register the timer to the framework */
- epit_clocksource_init(timer_clk);
- epit_clockevent_init(timer_clk);
-
- /* Make irqs happen */
- setup_irq(irq, &epit_timer_irq);
-}
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 04084900d810..c7a1ef180dda 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -18,6 +18,7 @@
#include "common.h"
#include "cpuidle.h"
+#include "hardware.h"
static void __init imx6sl_fec_init(void)
{
@@ -54,7 +55,8 @@ static void __init imx6sl_init_machine(void)
of_platform_default_populate(NULL, NULL, parent);
- imx6sl_fec_init();
+ if (cpu_is_imx6sl())
+ imx6sl_fec_init();
imx_anatop_init();
imx6sl_pm_init();
}
@@ -66,11 +68,15 @@ static void __init imx6sl_init_irq(void)
imx_init_l2cache();
imx_src_init();
irqchip_init();
- imx6_pm_ccm_init("fsl,imx6sl-ccm");
+ if (cpu_is_imx6sl())
+ imx6_pm_ccm_init("fsl,imx6sl-ccm");
+ else
+ imx6_pm_ccm_init("fsl,imx6sll-ccm");
}
static const char * const imx6sl_dt_compat[] __initconst = {
"fsl,imx6sl",
+ "fsl,imx6sll",
NULL,
};
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index 5fb1d2254b5e..04b3bf71de94 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -269,7 +269,7 @@ static bool mmdc_pmu_group_is_valid(struct perf_event *event)
return false;
}
- list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(sibling, leader) {
if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
return false;
}
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index e00d6260c3df..026e2ca45f1e 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -40,6 +40,7 @@
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
+#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define IMX_DDR_TYPE_LPDDR2 1
@@ -79,6 +80,11 @@ static inline bool cpu_is_imx6ull(void)
return __mxc_cpu_type == MXC_CPU_IMX6ULL;
}
+static inline bool cpu_is_imx6sll(void)
+{
+ return __mxc_cpu_type == MXC_CPU_IMX6SLL;
+}
+
static inline bool cpu_is_imx6q(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6Q;
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index ecdf071653d4..017539dd712b 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -428,10 +428,8 @@ static int __init imx6_pm_get_base(struct imx6_pm_base *base,
int ret = 0;
node = of_find_compatible_node(NULL, NULL, compat);
- if (!node) {
- ret = -ENODEV;
- goto out;
- }
+ if (!node)
+ return -ENODEV;
ret = of_address_to_resource(node, 0, &res);
if (ret)
@@ -444,7 +442,6 @@ static int __init imx6_pm_get_base(struct imx6_pm_base *base,
put_node:
of_node_put(node);
-out:
return ret;
}
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index d2283009a5ff..6c2ebf01893a 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -172,10 +172,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data aspenite_nand_info = {
- .enable_arbiter = 1,
- .num_cs = 1,
- .parts[0] = aspenite_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(aspenite_nand_partitions),
+ .parts = aspenite_nand_partitions,
+ .nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
};
static struct i2c_board_info aspenite_i2c_info[] __initdata = {
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index d90c74fa614d..c7897fb2b6da 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -178,11 +178,8 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
#endif
#endif
-#if IS_ENABLED(CONFIG_MTD_NAND_PXA3xx)
-static struct pxa3xx_nand_platform_data dkb_nand_info = {
- .enable_arbiter = 1,
- .num_cs = 1,
-};
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
+static struct pxa3xx_nand_platform_data dkb_nand_info = {};
#endif
#if IS_ENABLED(CONFIG_MMP_DISP)
@@ -275,7 +272,7 @@ static void __init ttc_dkb_init(void)
/* on-chip devices */
pxa910_add_uart(1);
-#if IS_ENABLED(CONFIG_MTD_NAND_PXA3xx)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
pxa910_add_nand(&dkb_nand_info);
#endif
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
new file mode 100644
index 000000000000..684c9c9a32bd
--- /dev/null
+++ b/arch/arm/mach-npcm/Kconfig
@@ -0,0 +1,30 @@
+menuconfig ARCH_NPCM
+ bool "Nuvoton NPCM Architecture"
+ depends on ARCH_MULTI_V7
+ select PINCTRL
+
+if ARCH_NPCM
+
+config ARCH_NPCM7XX
+ bool "Support for NPCM7xx BMC (Poleg)"
+ depends on ARCH_MULTI_V7
+ select PINCTRL_NPCM7XX
+ select NPCM7XX_TIMER
+ select ARCH_REQUIRE_GPIOLIB
+ select CACHE_L2X0
+ select ARM_GIC
+ select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU if SMP
+ select ARM_ERRATA_764369 if SMP
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_794072
+ select PL310_ERRATA_588369
+ select PL310_ERRATA_727915
+ select MFD_SYSCON
+ help
+ General support for NPCM7xx BMC (Poleg).
+
+ Nuvoton NPCM7xx BMC based on the Cortex A9.
+
+endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
new file mode 100644
index 000000000000..f5f67201419f
--- /dev/null
+++ b/arch/arm/mach-npcm/Makefile
@@ -0,0 +1,4 @@
+AFLAGS_headsmp.o += -march=armv7-a
+
+obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
new file mode 100644
index 000000000000..c083fe09a07b
--- /dev/null
+++ b/arch/arm/mach-npcm/headsmp.S
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+/*
+ * The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
+ * here.
+ */
+ENTRY(npcm7xx_secondary_startup)
+ safe_svcmode_maskall r0
+
+ b secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
new file mode 100644
index 000000000000..c5f77d854c4f
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static const char *const npcm7xx_dt_match[] = {
+ "nuvoton,npcm750",
+ NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
+ .atag_offset = 0x100,
+ .dt_compat = npcm7xx_dt_match,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
+MACHINE_END
diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
new file mode 100644
index 000000000000..21633c70fe7f
--- /dev/null
+++ b/arch/arm/mach-npcm/platsmp.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define NPCM7XX_SCRPAD_REG 0x13c
+
+extern void npcm7xx_secondary_startup(void);
+
+static int npcm7xx_smp_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ struct device_node *gcr_np;
+ void __iomem *gcr_base;
+ int ret = 0;
+
+ gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
+ if (!gcr_np) {
+ pr_err("no gcr device node\n");
+ ret = -ENODEV;
+ goto out;
+ }
+ gcr_base = of_iomap(gcr_np, 0);
+ if (!gcr_base) {
+ pr_err("could not iomap gcr");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* give boot ROM kernel start address. */
+ iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
+ NPCM7XX_SCRPAD_REG);
+ /* make sure the previous write is seen by all observers. */
+ dsb_sev();
+
+ iounmap(gcr_base);
+out:
+ return ret;
+}
+
+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *scu_np;
+ void __iomem *scu_base;
+
+ scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+ if (!scu_np) {
+ pr_err("no scu device node\n");
+ return;
+ }
+ scu_base = of_iomap(scu_np, 0);
+ if (!scu_base) {
+ pr_err("could not iomap scu");
+ return;
+ }
+
+ scu_enable(scu_base);
+
+ iounmap(scu_base);
+}
+
+static struct smp_operations npcm7xx_smp_ops __initdata = {
+ .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
+ .smp_boot_secondary = npcm7xx_smp_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
index f0808fcc5acc..8584cdd1c827 100644
--- a/arch/arm/mach-nspire/nspire.c
+++ b/arch/arm/mach-nspire/nspire.c
@@ -33,11 +33,6 @@ static const char *const nspire_dt_match[] __initconst = {
NULL,
};
-static void __init nspire_map_io(void)
-{
- debug_ll_io_init();
-}
-
static struct clcd_board nspire_clcd_data = {
.name = "LCD",
.caps = CLCD_CAP_5551 | CLCD_CAP_565,
@@ -71,7 +66,6 @@ static void nspire_restart(enum reboot_mode mode, const char *cmd)
DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
.dt_compat = nspire_dt_match,
- .map_io = nspire_map_io,
.init_machine = nspire_init,
.restart = nspire_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 45c6b733c881..c4694f26b5c4 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -30,6 +30,7 @@ config ARCH_OMAP16XX
bool "OMAP16xx Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
+ select OMAP_DM_TIMER
config OMAP_MUX
bool "OMAP multiplexing support"
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 65bb6e8085de..d83ff257eaa8 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -32,11 +32,10 @@
#include <asm/exception.h>
-#include <plat/i2c.h>
-
#include <mach/irqs.h>
#include "soc.h"
+#include "i2c.h"
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
void omap7xx_map_io(void);
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 32f6c53367bf..5bdf3c4190f9 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -24,8 +24,6 @@
#include <mach/mux.h>
#include "soc.h"
-#include <plat/i2c.h>
-
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800
diff --git a/arch/arm/mach-omap1/i2c.h b/arch/arm/mach-omap1/i2c.h
new file mode 100644
index 000000000000..54a2bce7879e
--- /dev/null
+++ b/arch/arm/mach-omap1/i2c.h
@@ -0,0 +1,50 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP1_I2C_H
+#define __ARCH_ARM_MACH_OMAP1_I2C_H
+
+struct i2c_board_info;
+struct omap_i2c_bus_platform_data;
+
+int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
+ int bus_id);
+
+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+ struct i2c_board_info const *info,
+ unsigned len);
+extern int omap_register_i2c_bus_cmdline(void);
+#else
+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+ struct i2c_board_info const *info,
+ unsigned len)
+{
+ return 0;
+}
+
+static inline int omap_register_i2c_bus_cmdline(void)
+{
+ return 0;
+}
+#endif
+
+#endif /* __ARCH_ARM_MACH_OMAP1_I2C_H */
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index f1135bf8940e..3e1de14805e4 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -55,7 +55,7 @@
#include <mach/tc.h>
#include <mach/mux.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
+#include <clocksource/timer-ti-dm.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 8fb1ec6fa999..4447210c9b0d 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -27,7 +27,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
-#include <plat/dmtimer.h>
+#include <clocksource/timer-ti-dm.h>
#include "soc.h"
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 00b1f17f8d44..9f27b486a536 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -72,6 +72,7 @@ config SOC_AM43XX
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select OMAP_INTERCONNECT
+ select ARM_CPU_SUSPEND if PM
config SOC_DRA7XX
bool "TI DRA7XX"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c15bbcad5f67..4603c30fef73 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -88,6 +88,8 @@ omap-4-5-pm-common += pm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common)
+obj-$(CONFIG_SOC_AM33XX) += pm33xx-core.o sleep33xx.o
+obj-$(CONFIG_SOC_AM43XX) += pm33xx-core.o sleep43xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
@@ -95,6 +97,8 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec)
endif
@@ -232,3 +236,15 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
obj-y += omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
+
+arch/arm/mach-omap2/pm-asm-offsets.s: arch/arm/mach-omap2/pm-asm-offsets.c
+ $(call if_changed_dep,cc_s_c)
+
+include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE
+ $(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__)
+
+# For rule to generate ti-emif-asm-offsets.h dependency
+include drivers/memory/Makefile.asm-offsets
+
+arch/arm/mach-omap2/sleep33xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h
+arch/arm/mach-omap2/sleep43xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 20f25539d572..75bc18646df6 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -566,11 +566,11 @@ static int n8x0_menelaus_late_init(struct device *dev)
}
#endif
-struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
+struct menelaus_platform_data n8x0_menelaus_platform_data = {
.late_init = n8x0_menelaus_late_init,
};
-struct aic3x_pdata n810_aic33_data __initdata = {
+struct aic3x_pdata n810_aic33_data = {
.gpio_reset = 118,
};
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index bc202835371b..fbe0b78bf489 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -77,6 +77,13 @@ static inline int omap4_pm_init_early(void)
}
#endif
+#if defined(CONFIG_PM) && (defined(CONFIG_SOC_AM33XX) || \
+ defined(CONFIG_SOC_AM43XX))
+void amx3_common_pm_init(void);
+#else
+static inline void amx3_common_pm_init(void) { }
+#endif
+
extern void omap2_init_common_infrastructure(void);
extern void omap_init_time(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index bd8089ff929f..180da403639e 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -623,6 +623,7 @@ void __init omap3_ctrl_init(void)
struct control_init_data {
int index;
+ void __iomem *mem;
s16 offset;
};
@@ -635,6 +636,10 @@ static const struct control_init_data omap2_ctrl_data = {
.offset = -OMAP2_CONTROL_GENERAL,
};
+static const struct control_init_data ctrl_aux_data = {
+ .index = TI_CLKM_CTRL_AUX,
+};
+
static const struct of_device_id omap_scrm_dt_match_table[] = {
{ .compatible = "ti,am3-scm", .data = &ctrl_data },
{ .compatible = "ti,am4-scm", .data = &ctrl_data },
@@ -644,6 +649,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
+ { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data },
{ .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
{ }
};
@@ -660,15 +666,21 @@ int __init omap2_control_base_init(void)
struct device_node *np;
const struct of_device_id *match;
struct control_init_data *data;
+ void __iomem *mem;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
data = (struct control_init_data *)match->data;
- omap2_ctrl_base = of_iomap(np, 0);
- if (!omap2_ctrl_base)
+ mem = of_iomap(np, 0);
+ if (!mem)
return -ENOMEM;
- omap2_ctrl_offset = data->offset;
+ if (data->index == TI_CLKM_CTRL) {
+ omap2_ctrl_base = mem;
+ omap2_ctrl_offset = data->offset;
+ }
+
+ data->mem = mem;
}
return 0;
@@ -713,7 +725,7 @@ int __init omap_control_init(void)
} else {
/* No scm_conf found, direct access */
ret = omap2_clk_provider_init(np, data->index, NULL,
- omap2_ctrl_base);
+ data->mem);
if (ret)
return ret;
}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 93057fb65f44..ed6f074ea672 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -8,7 +8,7 @@
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
-#include <linux/gpio.h>
+
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 6d28aa20a7d3..b064066d431c 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -13,9 +13,7 @@
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
-#include <linux/gpio.h>
#include <linux/mmc/host.h>
-#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include "soc.h"
diff --git a/arch/arm/mach-omap2/i2c.h b/arch/arm/mach-omap2/i2c.h
index 42b6f2e7d190..4d085c7ad425 100644
--- a/arch/arm/mach-omap2/i2c.h
+++ b/arch/arm/mach-omap2/i2c.h
@@ -19,23 +19,10 @@
*
*/
-#include <plat/i2c.h>
-
#ifndef __MACH_OMAP2_I2C_H
#define __MACH_OMAP2_I2C_H
-/**
- * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
- * @fifo_depth: total controller FIFO size (in bytes)
- * @flags: differences in hardware support capability
- *
- * @fifo_depth represents what exists on the hardware, not what is
- * actually configured at runtime by the device driver.
- */
-struct omap_i2c_dev_attr {
- u8 fifo_depth;
- u32 flags;
-};
+struct omap_hwmod;
int omap_i2c_reset(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cb5d7314cf99..cf546dfe3b32 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -622,6 +622,7 @@ void __init am33xx_init_early(void)
void __init am33xx_init_late(void)
{
omap_common_late_init();
+ amx3_common_pm_init();
}
#endif
@@ -646,6 +647,7 @@ void __init am43xx_init_late(void)
{
omap_common_late_init();
omap2_clk_enable_autoidle_all();
+ amx3_common_pm_init();
}
#endif
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 5a3bc3de58d0..978fba722b82 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -23,7 +23,6 @@
#include <linux/kernel.h>
#include <linux/err.h>
-#include <linux/platform_data/gpio-omap.h>
#include "prm.h"
#include "common.h"
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 5b2966a0f733..9fc4e2643ce7 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -28,7 +28,7 @@
#define L2X0_AUXCTRL_OFFSET 0xff8
#define L2X0_PREFETCH_CTRL_OFFSET 0xffc
-/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
+/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */
#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index f0388058b7da..3b829a50d1db 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -140,6 +140,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
struct omap_device *od;
struct omap_hwmod *oh;
struct device_node *node = pdev->dev.of_node;
+ struct resource res;
const char *oh_name;
int oh_cnt, i, ret = 0;
bool device_active = false;
@@ -150,6 +151,10 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
return -ENODEV;
}
+ /* Use ti-sysc driver instead of omap_device? */
+ if (!omap_hwmod_parse_module_range(NULL, node, &res))
+ return -ENODEV;
+
hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
if (!hwmods) {
ret = -ENOMEM;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 34156eca8e23..e7d23e200ecc 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -145,6 +145,8 @@
#include <linux/platform_data/ti-sysc.h>
+#include <dt-bindings/bus/ti-sysc.h>
+
#include <asm/system_misc.h>
#include "clock.h"
@@ -2498,7 +2500,7 @@ static void __init _setup_postsetup(struct omap_hwmod *oh)
* affects the IP block hardware, or system integration hardware
* associated with the IP block. Returns 0.
*/
-static int __init _setup(struct omap_hwmod *oh, void *data)
+static int _setup(struct omap_hwmod *oh, void *data)
{
if (oh->_state != _HWMOD_STATE_INITIALIZED)
return 0;
@@ -3060,6 +3062,414 @@ int __init omap_hwmod_setup_one(const char *oh_name)
return 0;
}
+static void omap_hwmod_check_one(struct device *dev,
+ const char *name, s8 v1, u8 v2)
+{
+ if (v1 < 0)
+ return;
+
+ if (v1 != v2)
+ dev_warn(dev, "%s %d != %d\n", name, v1, v2);
+}
+
+/**
+ * omap_hwmod_check_sysc - check sysc against platform sysc
+ * @dev: struct device
+ * @data: module data
+ * @sysc_fields: new sysc configuration
+ */
+static int omap_hwmod_check_sysc(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ struct sysc_regbits *sysc_fields)
+{
+ const struct sysc_regbits *regbits = data->cap->regbits;
+
+ omap_hwmod_check_one(dev, "dmadisable_shift",
+ regbits->dmadisable_shift,
+ sysc_fields->dmadisable_shift);
+ omap_hwmod_check_one(dev, "midle_shift",
+ regbits->midle_shift,
+ sysc_fields->midle_shift);
+ omap_hwmod_check_one(dev, "sidle_shift",
+ regbits->sidle_shift,
+ sysc_fields->sidle_shift);
+ omap_hwmod_check_one(dev, "clkact_shift",
+ regbits->clkact_shift,
+ sysc_fields->clkact_shift);
+ omap_hwmod_check_one(dev, "enwkup_shift",
+ regbits->enwkup_shift,
+ sysc_fields->enwkup_shift);
+ omap_hwmod_check_one(dev, "srst_shift",
+ regbits->srst_shift,
+ sysc_fields->srst_shift);
+ omap_hwmod_check_one(dev, "autoidle_shift",
+ regbits->autoidle_shift,
+ sysc_fields->autoidle_shift);
+
+ return 0;
+}
+
+/**
+ * omap_hwmod_init_regbits - init sysconfig specific register bits
+ * @dev: struct device
+ * @data: module data
+ * @sysc_fields: new sysc configuration
+ */
+static int omap_hwmod_init_regbits(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ struct sysc_regbits **sysc_fields)
+{
+ *sysc_fields = NULL;
+
+ switch (data->cap->type) {
+ case TI_SYSC_OMAP2:
+ case TI_SYSC_OMAP2_TIMER:
+ *sysc_fields = &omap_hwmod_sysc_type1;
+ break;
+ case TI_SYSC_OMAP3_SHAM:
+ *sysc_fields = &omap3_sham_sysc_fields;
+ break;
+ case TI_SYSC_OMAP3_AES:
+ *sysc_fields = &omap3xxx_aes_sysc_fields;
+ break;
+ case TI_SYSC_OMAP4:
+ case TI_SYSC_OMAP4_TIMER:
+ *sysc_fields = &omap_hwmod_sysc_type2;
+ break;
+ case TI_SYSC_OMAP4_SIMPLE:
+ *sysc_fields = &omap_hwmod_sysc_type3;
+ break;
+ case TI_SYSC_OMAP34XX_SR:
+ *sysc_fields = &omap34xx_sr_sysc_fields;
+ break;
+ case TI_SYSC_OMAP36XX_SR:
+ *sysc_fields = &omap36xx_sr_sysc_fields;
+ break;
+ case TI_SYSC_OMAP4_SR:
+ *sysc_fields = &omap36xx_sr_sysc_fields;
+ break;
+ case TI_SYSC_OMAP4_MCASP:
+ *sysc_fields = &omap_hwmod_sysc_type_mcasp;
+ break;
+ case TI_SYSC_OMAP4_USB_HOST_FS:
+ *sysc_fields = &omap_hwmod_sysc_type_usb_host_fs;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return omap_hwmod_check_sysc(dev, data, *sysc_fields);
+}
+
+/**
+ * omap_hwmod_init_reg_offs - initialize sysconfig register offsets
+ * @dev: struct device
+ * @data: module data
+ * @rev_offs: revision register offset
+ * @sysc_offs: sysc register offset
+ * @syss_offs: syss register offset
+ */
+int omap_hwmod_init_reg_offs(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ u32 *rev_offs, u32 *sysc_offs, u32 *syss_offs)
+{
+ *rev_offs = 0;
+ *sysc_offs = 0;
+ *syss_offs = 0;
+
+ if (data->offsets[SYSC_REVISION] > 0)
+ *rev_offs = data->offsets[SYSC_REVISION];
+
+ if (data->offsets[SYSC_SYSCONFIG] > 0)
+ *sysc_offs = data->offsets[SYSC_SYSCONFIG];
+
+ if (data->offsets[SYSC_SYSSTATUS] > 0)
+ *syss_offs = data->offsets[SYSC_SYSSTATUS];
+
+ return 0;
+}
+
+/**
+ * omap_hwmod_init_sysc_flags - initialize sysconfig features
+ * @dev: struct device
+ * @data: module data
+ * @sysc_flags: module configuration
+ */
+int omap_hwmod_init_sysc_flags(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ u32 *sysc_flags)
+{
+ *sysc_flags = 0;
+
+ switch (data->cap->type) {
+ case TI_SYSC_OMAP2:
+ case TI_SYSC_OMAP2_TIMER:
+ /* See SYSC_OMAP2_* in include/dt-bindings/bus/ti-sysc.h */
+ if (data->cfg->sysc_val & SYSC_OMAP2_CLOCKACTIVITY)
+ *sysc_flags |= SYSC_HAS_CLOCKACTIVITY;
+ if (data->cfg->sysc_val & SYSC_OMAP2_EMUFREE)
+ *sysc_flags |= SYSC_HAS_EMUFREE;
+ if (data->cfg->sysc_val & SYSC_OMAP2_ENAWAKEUP)
+ *sysc_flags |= SYSC_HAS_ENAWAKEUP;
+ if (data->cfg->sysc_val & SYSC_OMAP2_SOFTRESET)
+ *sysc_flags |= SYSC_HAS_SOFTRESET;
+ if (data->cfg->sysc_val & SYSC_OMAP2_AUTOIDLE)
+ *sysc_flags |= SYSC_HAS_AUTOIDLE;
+ break;
+ case TI_SYSC_OMAP4:
+ case TI_SYSC_OMAP4_TIMER:
+ /* See SYSC_OMAP4_* in include/dt-bindings/bus/ti-sysc.h */
+ if (data->cfg->sysc_val & SYSC_OMAP4_DMADISABLE)
+ *sysc_flags |= SYSC_HAS_DMADISABLE;
+ if (data->cfg->sysc_val & SYSC_OMAP4_FREEEMU)
+ *sysc_flags |= SYSC_HAS_EMUFREE;
+ if (data->cfg->sysc_val & SYSC_OMAP4_SOFTRESET)
+ *sysc_flags |= SYSC_HAS_SOFTRESET;
+ break;
+ case TI_SYSC_OMAP34XX_SR:
+ case TI_SYSC_OMAP36XX_SR:
+ /* See SYSC_OMAP3_SR_* in include/dt-bindings/bus/ti-sysc.h */
+ if (data->cfg->sysc_val & SYSC_OMAP3_SR_ENAWAKEUP)
+ *sysc_flags |= SYSC_HAS_ENAWAKEUP;
+ break;
+ default:
+ if (data->cap->regbits->emufree_shift >= 0)
+ *sysc_flags |= SYSC_HAS_EMUFREE;
+ if (data->cap->regbits->enwkup_shift >= 0)
+ *sysc_flags |= SYSC_HAS_ENAWAKEUP;
+ if (data->cap->regbits->srst_shift >= 0)
+ *sysc_flags |= SYSC_HAS_SOFTRESET;
+ if (data->cap->regbits->autoidle_shift >= 0)
+ *sysc_flags |= SYSC_HAS_AUTOIDLE;
+ break;
+ }
+
+ if (data->cap->regbits->midle_shift >= 0 &&
+ data->cfg->midlemodes)
+ *sysc_flags |= SYSC_HAS_MIDLEMODE;
+
+ if (data->cap->regbits->sidle_shift >= 0 &&
+ data->cfg->sidlemodes)
+ *sysc_flags |= SYSC_HAS_SIDLEMODE;
+
+ if (data->cfg->quirks & SYSC_QUIRK_UNCACHED)
+ *sysc_flags |= SYSC_NO_CACHE;
+ if (data->cfg->quirks & SYSC_QUIRK_RESET_STATUS)
+ *sysc_flags |= SYSC_HAS_RESET_STATUS;
+
+ if (data->cfg->syss_mask & 1)
+ *sysc_flags |= SYSS_HAS_RESET_STATUS;
+
+ return 0;
+}
+
+/**
+ * omap_hwmod_init_idlemodes - initialize module idle modes
+ * @dev: struct device
+ * @data: module data
+ * @idlemodes: module supported idle modes
+ */
+int omap_hwmod_init_idlemodes(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ u32 *idlemodes)
+{
+ *idlemodes = 0;
+
+ if (data->cfg->midlemodes & BIT(SYSC_IDLE_FORCE))
+ *idlemodes |= MSTANDBY_FORCE;
+ if (data->cfg->midlemodes & BIT(SYSC_IDLE_NO))
+ *idlemodes |= MSTANDBY_NO;
+ if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART))
+ *idlemodes |= MSTANDBY_SMART;
+ if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART_WKUP))
+ *idlemodes |= MSTANDBY_SMART_WKUP;
+
+ if (data->cfg->sidlemodes & BIT(SYSC_IDLE_FORCE))
+ *idlemodes |= SIDLE_FORCE;
+ if (data->cfg->sidlemodes & BIT(SYSC_IDLE_NO))
+ *idlemodes |= SIDLE_NO;
+ if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART))
+ *idlemodes |= SIDLE_SMART;
+ if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART_WKUP))
+ *idlemodes |= SIDLE_SMART_WKUP;
+
+ return 0;
+}
+
+/**
+ * omap_hwmod_check_module - check new module against platform data
+ * @dev: struct device
+ * @oh: module
+ * @data: new module data
+ * @sysc_fields: sysc register bits
+ * @rev_offs: revision register offset
+ * @sysc_offs: sysconfig register offset
+ * @syss_offs: sysstatus register offset
+ * @sysc_flags: sysc specific flags
+ * @idlemodes: sysc supported idlemodes
+ */
+static int omap_hwmod_check_module(struct device *dev,
+ struct omap_hwmod *oh,
+ const struct ti_sysc_module_data *data,
+ struct sysc_regbits *sysc_fields,
+ u32 rev_offs, u32 sysc_offs,
+ u32 syss_offs, u32 sysc_flags,
+ u32 idlemodes)
+{
+ if (!oh->class->sysc)
+ return -ENODEV;
+
+ if (sysc_fields != oh->class->sysc->sysc_fields)
+ dev_warn(dev, "sysc_fields %p != %p\n", sysc_fields,
+ oh->class->sysc->sysc_fields);
+
+ if (rev_offs != oh->class->sysc->rev_offs)
+ dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs,
+ oh->class->sysc->rev_offs);
+ if (sysc_offs != oh->class->sysc->sysc_offs)
+ dev_warn(dev, "sysc_offs %08x != %08x\n", sysc_offs,
+ oh->class->sysc->sysc_offs);
+ if (syss_offs != oh->class->sysc->syss_offs)
+ dev_warn(dev, "syss_offs %08x != %08x\n", syss_offs,
+ oh->class->sysc->syss_offs);
+
+ if (sysc_flags != oh->class->sysc->sysc_flags)
+ dev_warn(dev, "sysc_flags %08x != %08x\n", sysc_flags,
+ oh->class->sysc->sysc_flags);
+
+ if (idlemodes != oh->class->sysc->idlemodes)
+ dev_warn(dev, "idlemodes %08x != %08x\n", idlemodes,
+ oh->class->sysc->idlemodes);
+
+ if (data->cfg->srst_udelay != oh->class->sysc->srst_udelay)
+ dev_warn(dev, "srst_udelay %i != %i\n",
+ data->cfg->srst_udelay,
+ oh->class->sysc->srst_udelay);
+
+ return 0;
+}
+
+/**
+ * omap_hwmod_allocate_module - allocate new module
+ * @dev: struct device
+ * @oh: module
+ * @sysc_fields: sysc register bits
+ * @rev_offs: revision register offset
+ * @sysc_offs: sysconfig register offset
+ * @syss_offs: sysstatus register offset
+ * @sysc_flags: sysc specific flags
+ * @idlemodes: sysc supported idlemodes
+ *
+ * Note that the allocations here cannot use devm as ti-sysc can rebind.
+ */
+int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
+ const struct ti_sysc_module_data *data,
+ struct sysc_regbits *sysc_fields,
+ u32 rev_offs, u32 sysc_offs, u32 syss_offs,
+ u32 sysc_flags, u32 idlemodes)
+{
+ struct omap_hwmod_class_sysconfig *sysc;
+ struct omap_hwmod_class *class;
+ void __iomem *regs = NULL;
+ unsigned long flags;
+
+ sysc = kzalloc(sizeof(*sysc), GFP_KERNEL);
+ if (!sysc)
+ return -ENOMEM;
+
+ sysc->sysc_fields = sysc_fields;
+ sysc->rev_offs = rev_offs;
+ sysc->sysc_offs = sysc_offs;
+ sysc->syss_offs = syss_offs;
+ sysc->sysc_flags = sysc_flags;
+ sysc->idlemodes = idlemodes;
+ sysc->srst_udelay = data->cfg->srst_udelay;
+
+ if (!oh->_mpu_rt_va) {
+ regs = ioremap(data->module_pa,
+ data->module_size);
+ if (!regs)
+ return -ENOMEM;
+ }
+
+ /*
+ * We need new oh->class as the other devices in the same class
+ * may not yet have ioremapped their registers.
+ */
+ class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
+ if (!class)
+ return -ENOMEM;
+
+ class->sysc = sysc;
+
+ spin_lock_irqsave(&oh->_lock, flags);
+ if (regs)
+ oh->_mpu_rt_va = regs;
+ oh->class = class;
+ oh->_state = _HWMOD_STATE_INITIALIZED;
+ _setup(oh, NULL);
+ spin_unlock_irqrestore(&oh->_lock, flags);
+
+ return 0;
+}
+
+/**
+ * omap_hwmod_init_module - initialize new module
+ * @dev: struct device
+ * @data: module data
+ * @cookie: cookie for the caller to use for later calls
+ */
+int omap_hwmod_init_module(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ struct ti_sysc_cookie *cookie)
+{
+ struct omap_hwmod *oh;
+ struct sysc_regbits *sysc_fields;
+ u32 rev_offs, sysc_offs, syss_offs, sysc_flags, idlemodes;
+ int error;
+
+ if (!dev || !data)
+ return -EINVAL;
+
+ oh = _lookup(data->name);
+ if (!oh)
+ return -ENODEV;
+
+ cookie->data = oh;
+
+ error = omap_hwmod_init_regbits(dev, data, &sysc_fields);
+ if (error)
+ return error;
+
+ error = omap_hwmod_init_reg_offs(dev, data, &rev_offs,
+ &sysc_offs, &syss_offs);
+ if (error)
+ return error;
+
+ error = omap_hwmod_init_sysc_flags(dev, data, &sysc_flags);
+ if (error)
+ return error;
+
+ error = omap_hwmod_init_idlemodes(dev, data, &idlemodes);
+ if (error)
+ return error;
+
+ if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE_ON_INIT)
+ oh->flags |= HWMOD_INIT_NO_IDLE;
+ if (data->cfg->quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
+ oh->flags |= HWMOD_INIT_NO_RESET;
+
+ error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
+ rev_offs, sysc_offs, syss_offs,
+ sysc_flags, idlemodes);
+ if (!error)
+ return error;
+
+ return omap_hwmod_allocate_module(dev, oh, data, sysc_fields,
+ rev_offs, sysc_offs, syss_offs,
+ sysc_flags, idlemodes);
+}
+
/**
* omap_hwmod_setup_earlycon_flags - set up flags for early console
*
@@ -3082,6 +3492,12 @@ static void __init omap_hwmod_setup_earlycon_flags(void)
if (np) {
uart = of_get_property(np, "ti,hwmods", NULL);
oh = omap_hwmod_lookup(uart);
+ if (!oh) {
+ uart = of_get_property(np->parent,
+ "ti,hwmods",
+ NULL);
+ oh = omap_hwmod_lookup(uart);
+ }
if (oh)
oh->flags |= DEBUG_OMAPUART_FLAGS;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0b8e19f40402..c7122abbf977 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -620,6 +620,13 @@ int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
struct device_node *np,
struct resource *res);
+struct ti_sysc_module_data;
+struct ti_sysc_cookie;
+
+int omap_hwmod_init_module(struct device *dev,
+ const struct ti_sysc_module_data *data,
+ struct ti_sysc_cookie *cookie);
+
int omap_hwmod_enable(struct omap_hwmod *oh);
int omap_hwmod_idle(struct omap_hwmod *oh);
int omap_hwmod_shutdown(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 0afb014b211f..fe66cf247874 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -14,9 +14,7 @@
*/
#include <linux/i2c-omap.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
@@ -97,13 +95,6 @@ static struct omap_hwmod_class i2c_class = {
.reset = &omap_i2c_reset,
};
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_NO_FIFO |
- OMAP_I2C_FLAG_SIMPLE_CLOCK |
- OMAP_I2C_FLAG_16BIT_DATA_REG |
- OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-
/* I2C1 */
static struct omap_hwmod omap2420_i2c1_hwmod = {
.name = "i2c1",
@@ -116,7 +107,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
/*
* From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
* while a transfer is active seems to cause the I2C block to
@@ -137,7 +127,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
.flags = HWMOD_16BIT_REG,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 013b26b305d2..74eefd30518c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -14,11 +14,8 @@
*/
#include <linux/i2c-omap.h>
-#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
@@ -75,12 +72,6 @@ static struct omap_hwmod_class i2c_class = {
.reset = &omap_i2c_reset,
};
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
- OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
-};
-
/* I2C1 */
static struct omap_hwmod omap2430_i2c1_hwmod = {
.name = "i2c1",
@@ -102,7 +93,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
};
/* I2C2 */
@@ -118,7 +108,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c_dev_attr,
};
/* gpio5 */
@@ -134,7 +123,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
},
},
.class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &omap2xxx_gpio_dev_attr,
};
/* dma attributes */
@@ -167,10 +155,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
};
/* mcspi3 */
-static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap2430_mcspi3_hwmod = {
.name = "mcspi3",
.main_clk = "mcspi3_fck",
@@ -182,7 +166,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
},
},
.class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi3_dev_attr,
};
/* usbhsotg */
@@ -239,7 +222,6 @@ static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap2430_mcbsp_sysc,
- .rev = MCBSP_CONFIG_TYPE2,
};
static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 4b094cb384cb..5345919a81f8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -9,10 +9,8 @@
* published by the Free Software Foundation.
*/
-#include <linux/platform_data/gpio-omap.h>
+#include <linux/types.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -159,7 +157,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
struct omap_hwmod_class omap2xxx_mcspi_class = {
.name = "mcspi",
.sysc = &omap2xxx_mcspi_sysc,
- .rev = OMAP2_MCSPI_REV,
};
/*
@@ -220,23 +217,7 @@ struct omap_hwmod omap2xxx_iva_hwmod = {
.class = &iva_hwmod_class,
};
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
-};
-
/* timer1 */
-
struct omap_hwmod omap2xxx_timer1_hwmod = {
.name = "timer1",
.main_clk = "gpt1_fck",
@@ -247,13 +228,11 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer2 */
-
struct omap_hwmod omap2xxx_timer2_hwmod = {
.name = "timer2",
.main_clk = "gpt2_fck",
@@ -269,7 +248,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
};
/* timer3 */
-
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",
.main_clk = "gpt3_fck",
@@ -285,7 +263,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
};
/* timer4 */
-
struct omap_hwmod omap2xxx_timer4_hwmod = {
.name = "timer4",
.main_clk = "gpt4_fck",
@@ -301,7 +278,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
};
/* timer5 */
-
struct omap_hwmod omap2xxx_timer5_hwmod = {
.name = "timer5",
.main_clk = "gpt5_fck",
@@ -312,13 +288,11 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer6 */
-
struct omap_hwmod omap2xxx_timer6_hwmod = {
.name = "timer6",
.main_clk = "gpt6_fck",
@@ -329,13 +303,11 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer7 */
-
struct omap_hwmod omap2xxx_timer7_hwmod = {
.name = "timer7",
.main_clk = "gpt7_fck",
@@ -346,13 +318,11 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer8 */
-
struct omap_hwmod omap2xxx_timer8_hwmod = {
.name = "timer8",
.main_clk = "gpt8_fck",
@@ -363,13 +333,11 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer9 */
-
struct omap_hwmod omap2xxx_timer9_hwmod = {
.name = "timer9",
.main_clk = "gpt9_fck",
@@ -380,13 +348,11 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer10 */
-
struct omap_hwmod omap2xxx_timer10_hwmod = {
.name = "timer10",
.main_clk = "gpt10_fck",
@@ -397,13 +363,11 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer11 */
-
struct omap_hwmod omap2xxx_timer11_hwmod = {
.name = "timer11",
.main_clk = "gpt11_fck",
@@ -414,13 +378,11 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
-
struct omap_hwmod omap2xxx_timer12_hwmod = {
.name = "timer12",
.main_clk = "gpt12_fck",
@@ -431,7 +393,6 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -568,12 +529,6 @@ struct omap_hwmod omap2xxx_dss_venc_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/* gpio dev_attr */
-struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = false,
-};
-
/* gpio1 */
struct omap_hwmod omap2xxx_gpio1_hwmod = {
.name = "gpio1",
@@ -587,7 +542,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
},
},
.class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &omap2xxx_gpio_dev_attr,
};
/* gpio2 */
@@ -603,7 +557,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
},
},
.class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &omap2xxx_gpio_dev_attr,
};
/* gpio3 */
@@ -619,7 +572,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
},
},
.class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &omap2xxx_gpio_dev_attr,
};
/* gpio4 */
@@ -635,14 +587,9 @@ struct omap_hwmod omap2xxx_gpio4_hwmod = {
},
},
.class = &omap2xxx_gpio_hwmod_class,
- .dev_attr = &omap2xxx_gpio_dev_attr,
};
/* mcspi1 */
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
struct omap_hwmod omap2xxx_mcspi1_hwmod = {
.name = "mcspi1",
.main_clk = "mcspi1_fck",
@@ -654,14 +601,9 @@ struct omap_hwmod omap2xxx_mcspi1_hwmod = {
},
},
.class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
};
/* mcspi2 */
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
struct omap_hwmod omap2xxx_mcspi2_hwmod = {
.name = "mcspi2",
.main_clk = "mcspi2_fck",
@@ -673,7 +615,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
},
},
.class = &omap2xxx_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
};
static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index 434bd1a77229..6f81d7a4fec1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -139,9 +139,6 @@ extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
extern struct omap_hwmod_class am33xx_spi_hwmod_class;
-extern struct omap_gpio_dev_attr gpio_dev_attr;
-extern struct omap2_mcspi_dev_attr mcspi_attrib;
-
void omap_hwmod_am33xx_reg(void);
void omap_hwmod_am43xx_reg(void);
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 4bcf9f3e1544..5efe91c6e95b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -14,9 +14,9 @@
* GNU General Public License for more details.
*/
-#include <linux/platform_data/gpio-omap.h>
+#include <linux/types.h>
+
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
#include "i2c.h"
#include "wd_timer.h"
@@ -537,11 +537,6 @@ struct omap_hwmod_class am33xx_gpio_hwmod_class = {
.rev = 2,
};
-struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
-};
-
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
@@ -560,7 +555,6 @@ struct omap_hwmod am33xx_gpio1_hwmod = {
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio2 */
@@ -581,7 +575,6 @@ struct omap_hwmod am33xx_gpio2_hwmod = {
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio3 */
@@ -602,7 +595,6 @@ struct omap_hwmod am33xx_gpio3_hwmod = {
},
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpmc */
@@ -654,10 +646,6 @@ static struct omap_hwmod_class i2c_class = {
.reset = &omap_i2c_reset,
};
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
-};
-
/* i2c1 */
struct omap_hwmod am33xx_i2c1_hwmod = {
.name = "i2c1",
@@ -670,7 +658,6 @@ struct omap_hwmod am33xx_i2c1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c1 */
@@ -685,7 +672,6 @@ struct omap_hwmod am33xx_i2c2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c3 */
@@ -700,7 +686,6 @@ struct omap_hwmod am33xx_i2c3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/*
@@ -893,13 +878,9 @@ static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
struct omap_hwmod_class am33xx_spi_hwmod_class = {
.name = "mcspi",
.sysc = &am33xx_mcspi_sysc,
- .rev = OMAP4_MCSPI_REV,
};
/* spi0 */
-struct omap2_mcspi_dev_attr mcspi_attrib = {
- .num_chipselect = 2,
-};
struct omap_hwmod am33xx_spi0_hwmod = {
.name = "spi0",
.class = &am33xx_spi_hwmod_class,
@@ -910,7 +891,6 @@ struct omap_hwmod am33xx_spi0_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi_attrib,
};
/* spi1 */
@@ -924,7 +904,6 @@ struct omap_hwmod am33xx_spi1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi_attrib,
};
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 4d16b15bb0cf..53e1ac3724f2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -17,9 +17,6 @@
#include <linux/i2c-omap.h>
#include "omap_hwmod.h"
-#include <linux/platform_data/gpio-omap.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-
#include "omap_hwmod_common_data.h"
#include "control.h"
@@ -252,7 +249,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
},
.opt_clks = gpio0_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* lcdc */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 1a2f2242e31b..23336b6c7125 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,15 +17,11 @@
#include <linux/i2c-omap.h>
#include <linux/power/smartreflex.h>
-#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/omap-dma.h>
#include "l3_3xxx.h"
#include "l4_3xxx.h"
-#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
#include "soc.h"
#include "omap_hwmod.h"
@@ -155,31 +151,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
.sysc = &omap3xxx_timer_sysc,
};
-/* secure timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
-};
-
-/* pwm timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
-};
-
/* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1",
@@ -191,7 +162,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -252,7 +222,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -268,7 +237,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -284,7 +252,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -300,7 +267,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
},
},
- .dev_attr = &capability_dsp_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -316,7 +282,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -332,7 +297,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -348,13 +312,11 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
-
static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12",
.main_clk = "gpt12_fck",
@@ -365,7 +327,6 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
},
},
- .dev_attr = &capability_secure_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
@@ -683,11 +644,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
};
/* I2C1 */
-static struct omap_i2c_dev_attr i2c1_dev_attr = {
- .fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-
static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.name = "i2c1",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -700,15 +656,9 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c1_dev_attr,
};
/* I2C2 */
-static struct omap_i2c_dev_attr i2c2_dev_attr = {
- .fifo_depth = 8, /* bytes */
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-
static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.name = "i2c2",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -721,17 +671,9 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c2_dev_attr,
};
/* I2C3 */
-static struct omap_i2c_dev_attr i2c3_dev_attr = {
- .fifo_depth = 64, /* bytes */
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-
-
-
static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.name = "i2c3",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -744,7 +686,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
},
},
.class = &i2c_class,
- .dev_attr = &i2c3_dev_attr,
};
/*
@@ -769,12 +710,6 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
.rev = 1,
};
-/* gpio_dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
-};
-
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbck", },
@@ -794,7 +729,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
},
},
.class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
};
/* gpio2 */
@@ -816,7 +750,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
},
},
.class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
};
/* gpio3 */
@@ -838,7 +771,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
},
},
.class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
};
/* gpio4 */
@@ -860,7 +792,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
},
},
.class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
};
/* gpio5 */
@@ -883,7 +814,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
},
},
.class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
};
/* gpio6 */
@@ -906,7 +836,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
},
},
.class = &omap3xxx_gpio_hwmod_class,
- .dev_attr = &gpio_dev_attr,
};
/* dma attributes */
@@ -966,7 +895,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap3xxx_mcbsp_sysc,
- .rev = MCBSP_CONFIG_TYPE3,
};
/* McBSP functional clock mapping */
@@ -981,7 +909,6 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
};
/* mcbsp1 */
-
static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap3xxx_mcbsp_hwmod_class,
@@ -998,11 +925,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
};
/* mcbsp2 */
-
-static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
- .sidetone = "mcbsp2_sidetone",
-};
-
static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap3xxx_mcbsp_hwmod_class,
@@ -1016,15 +938,9 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
},
.opt_clks = mcbsp234_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
- .dev_attr = &omap34xx_mcbsp2_dev_attr,
};
/* mcbsp3 */
-
-static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
- .sidetone = "mcbsp3_sidetone",
-};
-
static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap3xxx_mcbsp_hwmod_class,
@@ -1038,12 +954,9 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
},
.opt_clks = mcbsp234_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
- .dev_attr = &omap34xx_mcbsp3_dev_attr,
};
/* mcbsp4 */
-
-
static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap3xxx_mcbsp_hwmod_class,
@@ -1060,8 +973,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
};
/* mcbsp5 */
-
-
static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.name = "mcbsp5",
.class = &omap3xxx_mcbsp_hwmod_class,
@@ -1090,7 +1001,6 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
};
/* mcbsp2_sidetone */
-
static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
.name = "mcbsp2_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -1099,7 +1009,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
};
/* mcbsp3_sidetone */
-
static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
.name = "mcbsp3_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -1258,14 +1167,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
static struct omap_hwmod_class omap34xx_mcspi_class = {
.name = "mcspi",
.sysc = &omap34xx_mcspi_sysc,
- .rev = OMAP3_MCSPI_REV,
};
/* mcspi1 */
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
static struct omap_hwmod omap34xx_mcspi1 = {
.name = "mcspi1",
.main_clk = "mcspi1_fck",
@@ -1277,14 +1181,9 @@ static struct omap_hwmod omap34xx_mcspi1 = {
},
},
.class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
};
/* mcspi2 */
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap34xx_mcspi2 = {
.name = "mcspi2",
.main_clk = "mcspi2_fck",
@@ -1296,16 +1195,9 @@ static struct omap_hwmod omap34xx_mcspi2 = {
},
},
.class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
};
/* mcspi3 */
-
-
-static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap34xx_mcspi3 = {
.name = "mcspi3",
.main_clk = "mcspi3_fck",
@@ -1317,16 +1209,9 @@ static struct omap_hwmod omap34xx_mcspi3 = {
},
},
.class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi3_dev_attr,
};
/* mcspi4 */
-
-
-static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
- .num_chipselect = 1,
-};
-
static struct omap_hwmod omap34xx_mcspi4 = {
.name = "mcspi4",
.main_clk = "mcspi4_fck",
@@ -1338,7 +1223,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
},
},
.class = &omap34xx_mcspi_class,
- .dev_attr = &omap_mcspi4_dev_attr,
};
/* usbhsotg */
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index afbce1f6f641..5f73b730d4fc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -14,8 +14,6 @@
* GNU General Public License for more details.
*/
-#include <linux/platform_data/gpio-omap.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
@@ -107,7 +105,6 @@ static struct omap_hwmod am43xx_gpio0_hwmod = {
},
.opt_clks = gpio0_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
@@ -239,7 +236,6 @@ static struct omap_hwmod am43xx_spi2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi_attrib,
};
static struct omap_hwmod am43xx_spi3_hwmod = {
@@ -253,7 +249,6 @@ static struct omap_hwmod am43xx_spi3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi_attrib,
};
static struct omap_hwmod am43xx_spi4_hwmod = {
@@ -267,7 +262,6 @@ static struct omap_hwmod am43xx_spi4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi_attrib,
};
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
@@ -288,7 +282,6 @@ static struct omap_hwmod am43xx_gpio4_hwmod = {
},
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -309,7 +302,6 @@ static struct omap_hwmod am43xx_gpio5_hwmod = {
},
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index a1901c22a0f0..e4f8ae9cd637 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,17 +21,12 @@
*/
#include <linux/io.h>
-#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/i2c-omap.h>
#include <linux/omap-dma.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
-
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_44xx.h"
@@ -1083,12 +1078,6 @@ static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
.rev = 2,
};
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
-};
-
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
@@ -1108,7 +1097,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio2 */
@@ -1131,7 +1119,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio3 */
@@ -1154,7 +1141,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
},
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio4 */
@@ -1177,7 +1163,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
},
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio5 */
@@ -1200,7 +1185,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
},
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio6 */
@@ -1223,7 +1207,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
},
.opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/*
@@ -1394,10 +1377,6 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
.reset = &omap_i2c_reset,
};
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
-};
-
/* i2c1 */
static struct omap_hwmod omap44xx_i2c1_hwmod = {
.name = "i2c1",
@@ -1412,7 +1391,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c2 */
@@ -1429,7 +1407,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c3 */
@@ -1446,7 +1423,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c4 */
@@ -1463,7 +1439,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/*
@@ -1702,7 +1677,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap44xx_mcbsp_sysc,
- .rev = MCBSP_CONFIG_TYPE4,
};
/* mcbsp1 */
@@ -1860,14 +1834,9 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
.name = "mcspi",
.sysc = &omap44xx_mcspi_sysc,
- .rev = OMAP4_MCSPI_REV,
};
/* mcspi1 */
-static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap44xx_mcspi_hwmod_class,
@@ -1880,14 +1849,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi1_dev_attr,
};
/* mcspi2 */
-static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap44xx_mcspi_hwmod_class,
@@ -1900,14 +1864,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi2_dev_attr,
};
/* mcspi3 */
-static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap44xx_mcspi_hwmod_class,
@@ -1920,14 +1879,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi3_dev_attr,
};
/* mcspi4 */
-static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
- .num_chipselect = 1,
-};
-
static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap44xx_mcspi_hwmod_class,
@@ -1940,7 +1894,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi4_dev_attr,
};
/*
@@ -2547,26 +2500,6 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
.sysc = &omap44xx_timer_sysc,
};
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
-};
-
-/* pwm timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
-};
-
/* timer1 */
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
@@ -2581,7 +2514,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
};
/* timer2 */
@@ -2643,7 +2575,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_dev_attr,
};
/* timer6 */
@@ -2659,7 +2590,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_dev_attr,
};
/* timer7 */
@@ -2675,7 +2605,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_dev_attr,
};
/* timer8 */
@@ -2691,7 +2620,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_pwm_dev_attr,
};
/* timer9 */
@@ -2707,7 +2635,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
};
/* timer10 */
@@ -2724,7 +2651,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
};
/* timer11 */
@@ -2740,7 +2666,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
};
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 988e7eaa1330..c72cd84b07ec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -18,15 +18,11 @@
*/
#include <linux/io.h>
-#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/i2c-omap.h>
#include <linux/omap-dma.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -627,12 +623,6 @@ static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
.rev = 2,
};
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
-};
-
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
@@ -652,7 +642,6 @@ static struct omap_hwmod omap54xx_gpio1_hwmod = {
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio2 */
@@ -675,7 +664,6 @@ static struct omap_hwmod omap54xx_gpio2_hwmod = {
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio3 */
@@ -698,7 +686,6 @@ static struct omap_hwmod omap54xx_gpio3_hwmod = {
},
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio4 */
@@ -721,7 +708,6 @@ static struct omap_hwmod omap54xx_gpio4_hwmod = {
},
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio5 */
@@ -744,7 +730,6 @@ static struct omap_hwmod omap54xx_gpio5_hwmod = {
},
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio6 */
@@ -767,7 +752,6 @@ static struct omap_hwmod omap54xx_gpio6_hwmod = {
},
.opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio7 */
@@ -790,7 +774,6 @@ static struct omap_hwmod omap54xx_gpio7_hwmod = {
},
.opt_clks = gpio7_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio8 */
@@ -813,7 +796,6 @@ static struct omap_hwmod omap54xx_gpio8_hwmod = {
},
.opt_clks = gpio8_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/*
@@ -839,11 +821,6 @@ static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
.rev = OMAP_I2C_IP_VERSION_2,
};
-/* i2c dev_attr */
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
-};
-
/* i2c1 */
static struct omap_hwmod omap54xx_i2c1_hwmod = {
.name = "i2c1",
@@ -858,7 +835,6 @@ static struct omap_hwmod omap54xx_i2c1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c2 */
@@ -875,7 +851,6 @@ static struct omap_hwmod omap54xx_i2c2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c3 */
@@ -892,7 +867,6 @@ static struct omap_hwmod omap54xx_i2c3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c4 */
@@ -909,7 +883,6 @@ static struct omap_hwmod omap54xx_i2c4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c5 */
@@ -926,7 +899,6 @@ static struct omap_hwmod omap54xx_i2c5_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/*
@@ -1012,7 +984,6 @@ static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap54xx_mcbsp_sysc,
- .rev = MCBSP_CONFIG_TYPE4,
};
/* mcbsp1 */
@@ -1149,15 +1120,9 @@ static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
.name = "mcspi",
.sysc = &omap54xx_mcspi_sysc,
- .rev = OMAP4_MCSPI_REV,
};
/* mcspi1 */
-/* mcspi1 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
static struct omap_hwmod omap54xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap54xx_mcspi_hwmod_class,
@@ -1170,15 +1135,9 @@ static struct omap_hwmod omap54xx_mcspi1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi1_dev_attr,
};
/* mcspi2 */
-/* mcspi2 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap54xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap54xx_mcspi_hwmod_class,
@@ -1191,15 +1150,9 @@ static struct omap_hwmod omap54xx_mcspi2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi2_dev_attr,
};
/* mcspi3 */
-/* mcspi3 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod omap54xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap54xx_mcspi_hwmod_class,
@@ -1212,15 +1165,9 @@ static struct omap_hwmod omap54xx_mcspi3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi3_dev_attr,
};
/* mcspi4 */
-/* mcspi4 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
- .num_chipselect = 1,
-};
-
static struct omap_hwmod omap54xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap54xx_mcspi_hwmod_class,
@@ -1233,7 +1180,6 @@ static struct omap_hwmod omap54xx_mcspi4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi4_dev_attr,
};
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 4c2a05b1bd19..62352d1e6361 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -18,15 +18,11 @@
*/
#include <linux/io.h>
-#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/power/smartreflex.h>
#include <linux/i2c-omap.h>
#include <linux/omap-dma.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -818,12 +814,6 @@ static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
.rev = 2,
};
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
-};
-
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
@@ -844,7 +834,6 @@ static struct omap_hwmod dra7xx_gpio1_hwmod = {
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio2 */
@@ -867,7 +856,6 @@ static struct omap_hwmod dra7xx_gpio2_hwmod = {
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio3 */
@@ -890,7 +878,6 @@ static struct omap_hwmod dra7xx_gpio3_hwmod = {
},
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio4 */
@@ -913,7 +900,6 @@ static struct omap_hwmod dra7xx_gpio4_hwmod = {
},
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio5 */
@@ -936,7 +922,6 @@ static struct omap_hwmod dra7xx_gpio5_hwmod = {
},
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio6 */
@@ -959,7 +944,6 @@ static struct omap_hwmod dra7xx_gpio6_hwmod = {
},
.opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio7 */
@@ -982,7 +966,6 @@ static struct omap_hwmod dra7xx_gpio7_hwmod = {
},
.opt_clks = gpio7_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/* gpio8 */
@@ -1005,7 +988,6 @@ static struct omap_hwmod dra7xx_gpio8_hwmod = {
},
.opt_clks = gpio8_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
/*
@@ -1105,11 +1087,6 @@ static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
.rev = OMAP_I2C_IP_VERSION_2,
};
-/* i2c dev_attr */
-static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
-};
-
/* i2c1 */
static struct omap_hwmod dra7xx_i2c1_hwmod = {
.name = "i2c1",
@@ -1124,7 +1101,6 @@ static struct omap_hwmod dra7xx_i2c1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c2 */
@@ -1141,7 +1117,6 @@ static struct omap_hwmod dra7xx_i2c2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c3 */
@@ -1158,7 +1133,6 @@ static struct omap_hwmod dra7xx_i2c3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c4 */
@@ -1175,7 +1149,6 @@ static struct omap_hwmod dra7xx_i2c4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/* i2c5 */
@@ -1192,7 +1165,6 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &i2c_dev_attr,
};
/*
@@ -1401,15 +1373,9 @@ static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
.name = "mcspi",
.sysc = &dra7xx_mcspi_sysc,
- .rev = OMAP4_MCSPI_REV,
};
/* mcspi1 */
-/* mcspi1 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
- .num_chipselect = 4,
-};
-
static struct omap_hwmod dra7xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &dra7xx_mcspi_hwmod_class,
@@ -1422,15 +1388,9 @@ static struct omap_hwmod dra7xx_mcspi1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi1_dev_attr,
};
/* mcspi2 */
-/* mcspi2 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod dra7xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &dra7xx_mcspi_hwmod_class,
@@ -1443,15 +1403,9 @@ static struct omap_hwmod dra7xx_mcspi2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi2_dev_attr,
};
/* mcspi3 */
-/* mcspi3 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
- .num_chipselect = 2,
-};
-
static struct omap_hwmod dra7xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &dra7xx_mcspi_hwmod_class,
@@ -1464,15 +1418,9 @@ static struct omap_hwmod dra7xx_mcspi3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi3_dev_attr,
};
/* mcspi4 */
-/* mcspi4 dev_attr */
-static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
- .num_chipselect = 1,
-};
-
static struct omap_hwmod dra7xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &dra7xx_mcspi_hwmod_class,
@@ -1485,7 +1433,6 @@ static struct omap_hwmod dra7xx_mcspi4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &mcspi4_dev_attr,
};
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 84f118280a0e..686655f884c1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -15,10 +15,9 @@
*
*/
-#include <linux/platform_data/gpio-omap.h>
+#include <linux/types.h>
+
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod_common_data.h"
#include "cm81xx.h"
@@ -488,11 +487,6 @@ static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
.rev = 2,
};
-static struct omap_gpio_dev_attr gpio_dev_attr = {
- .bank_width = 32,
- .dbck_flag = true,
-};
-
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "sysclk18_ck" },
};
@@ -510,7 +504,6 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = {
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
@@ -537,7 +530,6 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = {
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
- .dev_attr = &gpio_dev_attr,
};
static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
@@ -654,15 +646,10 @@ static struct omap_hwmod_class dm816x_timer_hwmod_class = {
.sysc = &dm816x_timer_sysc,
};
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
static struct omap_hwmod dm814x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer1_fck",
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
@@ -684,7 +671,6 @@ static struct omap_hwmod dm816x_timer1_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -699,7 +685,6 @@ static struct omap_hwmod dm814x_timer2_hwmod = {
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer2_fck",
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
@@ -721,7 +706,6 @@ static struct omap_hwmod dm816x_timer2_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -742,7 +726,6 @@ static struct omap_hwmod dm816x_timer3_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -763,7 +746,6 @@ static struct omap_hwmod dm816x_timer4_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -784,7 +766,6 @@ static struct omap_hwmod dm816x_timer5_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -805,7 +786,6 @@ static struct omap_hwmod dm816x_timer6_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -826,7 +806,6 @@ static struct omap_hwmod dm816x_timer7_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
@@ -1138,11 +1117,6 @@ static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
static struct omap_hwmod_class dm816x_mcspi_class = {
.name = "mcspi",
.sysc = &dm816x_mcspi_sysc,
- .rev = OMAP3_MCSPI_REV,
-};
-
-static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
- .num_chipselect = 4,
};
static struct omap_hwmod dm81xx_mcspi1_hwmod = {
@@ -1156,7 +1130,6 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = {
},
},
.class = &dm816x_mcspi_class,
- .dev_attr = &dm816x_mcspi1_dev_attr,
};
static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 29a52df2de26..56dbaca9a728 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,7 +19,6 @@
#include "display.h"
/* Common IP block data across OMAP2xxx */
-extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
extern struct omap_hwmod omap2xxx_l3_main_hwmod;
extern struct omap_hwmod omap2xxx_l4_core_hwmod;
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 6b433fce65a5..6459816c2879 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -17,17 +17,17 @@
#include <linux/wl12xx.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
+#include <linux/power/smartreflex.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/platform_data/pinctrl-single.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/iommu-omap.h>
+#include <linux/platform_data/ti-sysc.h>
#include <linux/platform_data/wkup_m3.h>
-#include <linux/platform_data/pwm_omap_dmtimer.h>
#include <linux/platform_data/media/ir-rx51.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
#include "common.h"
#include "common-board-devices.h"
@@ -454,6 +454,43 @@ static void __init dra7x_evm_mmc_quirk(void)
}
#endif
+static int ti_sysc_enable_module(struct device *dev,
+ const struct ti_sysc_cookie *cookie)
+{
+ if (!cookie->data)
+ return -EINVAL;
+
+ return omap_hwmod_enable(cookie->data);
+}
+
+static int ti_sysc_idle_module(struct device *dev,
+ const struct ti_sysc_cookie *cookie)
+{
+ if (!cookie->data)
+ return -EINVAL;
+
+ return omap_hwmod_idle(cookie->data);
+}
+
+static int ti_sysc_shutdown_module(struct device *dev,
+ const struct ti_sysc_cookie *cookie)
+{
+ if (!cookie->data)
+ return -EINVAL;
+
+ return omap_hwmod_shutdown(cookie->data);
+}
+
+static struct of_dev_auxdata omap_auxdata_lookup[];
+
+static struct ti_sysc_platform_data ti_sysc_pdata = {
+ .auxdata = omap_auxdata_lookup,
+ .init_module = omap_hwmod_init_module,
+ .enable_module = ti_sysc_enable_module,
+ .idle_module = ti_sysc_idle_module,
+ .shutdown_module = ti_sysc_shutdown_module,
+};
+
static struct pcs_pdata pcs_pdata;
void omap_pcs_legacy_init(int irq, void (*rearm)(void))
@@ -477,33 +514,6 @@ void omap_auxdata_legacy_init(struct device *dev)
dev->platform_data = &twl_gpio_auxdata;
}
-/* Dual mode timer PWM callbacks platdata */
-#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
-static struct pwm_omap_dmtimer_pdata pwm_dmtimer_pdata = {
- .request_by_node = omap_dm_timer_request_by_node,
- .request_specific = omap_dm_timer_request_specific,
- .request = omap_dm_timer_request,
- .set_source = omap_dm_timer_set_source,
- .get_irq = omap_dm_timer_get_irq,
- .set_int_enable = omap_dm_timer_set_int_enable,
- .set_int_disable = omap_dm_timer_set_int_disable,
- .free = omap_dm_timer_free,
- .enable = omap_dm_timer_enable,
- .disable = omap_dm_timer_disable,
- .get_fclk = omap_dm_timer_get_fclk,
- .start = omap_dm_timer_start,
- .stop = omap_dm_timer_stop,
- .set_load = omap_dm_timer_set_load,
- .set_match = omap_dm_timer_set_match,
- .set_pwm = omap_dm_timer_set_pwm,
- .set_prescaler = omap_dm_timer_set_prescaler,
- .read_counter = omap_dm_timer_read_counter,
- .write_counter = omap_dm_timer_write_counter,
- .read_status = omap_dm_timer_read_status,
- .write_status = omap_dm_timer_write_status,
-};
-#endif
-
static struct ir_rx51_platform_data __maybe_unused rx51_ir_data = {
.set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
};
@@ -542,7 +552,9 @@ static struct pdata_init auxdata_quirks[] __initdata = {
{ /* sentinel */ },
};
-static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
+struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR];
+
+static struct of_dev_auxdata omap_auxdata_lookup[] = {
#ifdef CONFIG_MACH_NOKIA_N8X0
OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
@@ -551,6 +563,10 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
&omap3_iommu_pdata),
+ OF_DEV_AUXDATA("ti,omap3-smartreflex-core", 0x480cb000,
+ "480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
+ OF_DEV_AUXDATA("ti,omap3-smartreflex-mpu-iva", 0x480c9000,
+ "480c9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]),
OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x4809c000, "4809c000.mmc", &mmc_pdata[0]),
OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]),
OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_ir_data),
@@ -572,14 +588,17 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
&wkup_m3_data),
#endif
-#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
- OF_DEV_AUXDATA("ti,omap-dmtimer-pwm", 0, NULL, &pwm_dmtimer_pdata),
-#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
&omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
&omap4_iommu_pdata),
+ OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000,
+ "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]),
+ OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000,
+ "4a0dd000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
+ OF_DEV_AUXDATA("ti,omap4-smartreflex-mpu", 0x4a0d9000,
+ "4a0d9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]),
#endif
#ifdef CONFIG_SOC_DRA7XX
OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc",
@@ -590,6 +609,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
&dra7_hsmmc_data_mmc3),
#endif
/* Common auxdata */
+ OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
{ /* sentinel */ },
};
diff --git a/arch/arm/mach-omap2/pm-asm-offsets.c b/arch/arm/mach-omap2/pm-asm-offsets.c
new file mode 100644
index 000000000000..6d4392da7c11
--- /dev/null
+++ b/arch/arm/mach-omap2/pm-asm-offsets.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI AM33XX and AM43XX PM Assembly Offsets
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Inc.
+ */
+
+#include <linux/kbuild.h>
+#include <linux/platform_data/pm33xx.h>
+
+int main(void)
+{
+ DEFINE(AMX3_PM_WFI_FLAGS_OFFSET,
+ offsetof(struct am33xx_pm_sram_data, wfi_flags));
+ DEFINE(AMX3_PM_L2_AUX_CTRL_VAL_OFFSET,
+ offsetof(struct am33xx_pm_sram_data, l2_aux_ctrl_val));
+ DEFINE(AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET,
+ offsetof(struct am33xx_pm_sram_data, l2_prefetch_ctrl_val));
+ DEFINE(AMX3_PM_SRAM_DATA_SIZE, sizeof(struct am33xx_pm_sram_data));
+
+ BLANK();
+
+ DEFINE(AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET,
+ offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_virt));
+ DEFINE(AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET,
+ offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_phys));
+ DEFINE(AMX3_PM_RO_SRAM_DATA_SIZE,
+ sizeof(struct am33xx_pm_ro_sram_data));
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8e30772cfe32..c73776b82348 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -81,6 +81,9 @@ extern unsigned int omap3_do_wfi_sz;
/* ... and its pointer from SRAM after copy */
extern void (*omap3_do_wfi_sram)(void);
+extern struct am33xx_pm_sram_addr am33xx_pm_sram;
+extern struct am33xx_pm_sram_addr am43xx_pm_sram;
+
extern void omap3_save_scratchpad_contents(void);
#define PM_RTA_ERRATUM_i608 (1 << 0)
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
new file mode 100644
index 000000000000..93c0b5ba9f09
--- /dev/null
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM33XX Arch Power Management Routines
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Dave Gerlach
+ */
+
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <linux/errno.h>
+#include <linux/platform_data/pm33xx.h>
+
+#include "cm33xx.h"
+#include "common.h"
+#include "control.h"
+#include "clockdomain.h"
+#include "iomap.h"
+#include "omap_hwmod.h"
+#include "pm.h"
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "soc.h"
+#include "sram.h"
+
+static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
+static struct clockdomain *gfx_l4ls_clkdm;
+static void __iomem *scu_base;
+
+static int __init am43xx_map_scu(void)
+{
+ scu_base = ioremap(scu_a9_get_base(), SZ_256);
+
+ if (!scu_base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int amx3_common_init(void)
+{
+ gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
+ per_pwrdm = pwrdm_lookup("per_pwrdm");
+ mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
+
+ if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm))
+ return -ENODEV;
+
+ (void)clkdm_for_each(omap_pm_clkdms_setup, NULL);
+
+ /* CEFUSE domain can be turned off post bootup */
+ cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
+ if (cefuse_pwrdm)
+ omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
+ else
+ pr_err("PM: Failed to get cefuse_pwrdm\n");
+
+ return 0;
+}
+
+static int am33xx_suspend_init(void)
+{
+ int ret;
+
+ gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
+
+ if (!gfx_l4ls_clkdm) {
+ pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n");
+ return -ENODEV;
+ }
+
+ ret = amx3_common_init();
+
+ return ret;
+}
+
+static int am43xx_suspend_init(void)
+{
+ int ret = 0;
+
+ ret = am43xx_map_scu();
+ if (ret) {
+ pr_err("PM: Could not ioremap SCU\n");
+ return ret;
+ }
+
+ ret = amx3_common_init();
+
+ return ret;
+}
+
+static void amx3_pre_suspend_common(void)
+{
+ omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
+}
+
+static void amx3_post_suspend_common(void)
+{
+ int status;
+ /*
+ * Because gfx_pwrdm is the only one under MPU control,
+ * comment on transition status
+ */
+ status = pwrdm_read_pwrst(gfx_pwrdm);
+ if (status != PWRDM_POWER_OFF)
+ pr_err("PM: GFX domain did not transition: %x\n", status);
+}
+
+static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long))
+{
+ int ret = 0;
+
+ amx3_pre_suspend_common();
+ ret = cpu_suspend(0, fn);
+ amx3_post_suspend_common();
+
+ /*
+ * BUG: GFX_L4LS clock domain needs to be woken up to
+ * ensure thet L4LS clock domain does not get stuck in
+ * transition. If that happens L3 module does not get
+ * disabled, thereby leading to PER power domain
+ * transition failing
+ */
+
+ clkdm_wakeup(gfx_l4ls_clkdm);
+ clkdm_sleep(gfx_l4ls_clkdm);
+
+ return ret;
+}
+
+static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long))
+{
+ int ret = 0;
+
+ amx3_pre_suspend_common();
+ scu_power_mode(scu_base, SCU_PM_POWEROFF);
+ ret = cpu_suspend(0, fn);
+ scu_power_mode(scu_base, SCU_PM_NORMAL);
+ amx3_post_suspend_common();
+
+ return ret;
+}
+
+static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
+{
+ if (soc_is_am33xx())
+ return &am33xx_pm_sram;
+ else if (soc_is_am437x())
+ return &am43xx_pm_sram;
+ else
+ return NULL;
+}
+
+static struct am33xx_pm_platform_data am33xx_ops = {
+ .init = am33xx_suspend_init,
+ .soc_suspend = am33xx_suspend,
+ .get_sram_addrs = amx3_get_sram_addrs,
+};
+
+static struct am33xx_pm_platform_data am43xx_ops = {
+ .init = am43xx_suspend_init,
+ .soc_suspend = am43xx_suspend,
+ .get_sram_addrs = amx3_get_sram_addrs,
+};
+
+static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
+{
+ if (soc_is_am33xx())
+ return &am33xx_ops;
+ else if (soc_is_am437x())
+ return &am43xx_ops;
+ else
+ return NULL;
+}
+
+void __init amx3_common_pm_init(void)
+{
+ struct am33xx_pm_platform_data *pdata;
+ struct platform_device_info devinfo;
+
+ pdata = am33xx_pm_get_pdata();
+
+ memset(&devinfo, 0, sizeof(devinfo));
+ devinfo.name = "pm33xx";
+ devinfo.data = pdata;
+ devinfo.size_data = sizeof(*pdata);
+ devinfo.id = -1;
+ platform_device_register_full(&devinfo);
+}
diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
new file mode 100644
index 000000000000..218d79930b04
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep33xx.S
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Low level suspend code for AM33XX SoCs
+ *
+ * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Dave Gerlach, Vaibhav Bedia
+ */
+
+#include <generated/ti-emif-asm-offsets.h>
+#include <generated/ti-pm-asm-offsets.h>
+#include <linux/linkage.h>
+#include <linux/ti-emif-sram.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+#include "iomap.h"
+#include "cm33xx.h"
+
+#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
+#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
+#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
+
+ .arm
+ .align 3
+
+ENTRY(am33xx_do_wfi)
+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
+
+ /*
+ * Flush all data from the L1 and L2 data cache before disabling
+ * SCTLR.C bit.
+ */
+ ldr r1, kernel_flush
+ blx r1
+
+ /*
+ * Clear the SCTLR.C bit to prevent further data cache
+ * allocation. Clearing SCTLR.C would make all the data accesses
+ * strongly ordered and would not hit the cache.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #(1 << 2) @ Disable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ /*
+ * Invalidate L1 and L2 data cache.
+ */
+ ldr r1, kernel_flush
+ blx r1
+
+ adr r9, am33xx_emif_sram_table
+
+ ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
+ blx r3
+
+ ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
+ blx r3
+
+ /* Disable EMIF */
+ ldr r1, virt_emif_clkctrl
+ ldr r2, [r1]
+ bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
+ str r2, [r1]
+
+ ldr r1, virt_emif_clkctrl
+wait_emif_disable:
+ ldr r2, [r1]
+ mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
+ cmp r2, r3
+ bne wait_emif_disable
+
+ /*
+ * For the MPU WFI to be registered as an interrupt
+ * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
+ * to DISABLED
+ */
+ ldr r1, virt_mpu_clkctrl
+ ldr r2, [r1]
+ bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
+ str r2, [r1]
+
+ /*
+ * Execute an ISB instruction to ensure that all of the
+ * CP15 register changes have been committed.
+ */
+ isb
+
+ /*
+ * Execute a barrier instruction to ensure that all cache,
+ * TLB and branch predictor maintenance operations issued
+ * have completed.
+ */
+ dsb
+ dmb
+
+ /*
+ * Execute a WFI instruction and wait until the
+ * STANDBYWFI output is asserted to indicate that the
+ * CPU is in idle and low power state. CPU can specualatively
+ * prefetch the instructions so add NOPs after WFI. Thirteen
+ * NOPs as per Cortex-A8 pipeline.
+ */
+ wfi
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* We come here in case of an abort due to a late interrupt */
+
+ /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
+ ldr r1, virt_mpu_clkctrl
+ mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
+ str r2, [r1]
+
+ /* Re-enable EMIF */
+ ldr r1, virt_emif_clkctrl
+ mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
+ str r2, [r1]
+wait_emif_enable:
+ ldr r3, [r1]
+ cmp r2, r3
+ bne wait_emif_enable
+
+
+ ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
+ blx r1
+
+ /*
+ * Set SCTLR.C bit to allow data cache allocation
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #(1 << 2) @ Enable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ /* Let the suspend code know about the abort */
+ mov r0, #1
+ ldmfd sp!, {r4 - r11, pc} @ restore regs and return
+ENDPROC(am33xx_do_wfi)
+
+ .align
+ENTRY(am33xx_resume_offset)
+ .word . - am33xx_do_wfi
+
+ENTRY(am33xx_resume_from_deep_sleep)
+ /* Re-enable EMIF */
+ ldr r0, phys_emif_clkctrl
+ mov r1, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
+ str r1, [r0]
+wait_emif_enable1:
+ ldr r2, [r0]
+ cmp r1, r2
+ bne wait_emif_enable1
+
+ adr r9, am33xx_emif_sram_table
+
+ ldr r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
+ blx r1
+
+ ldr r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
+ blx r1
+
+resume_to_ddr:
+ /* We are back. Branch to the common CPU resume routine */
+ mov r0, #0
+ ldr pc, resume_addr
+ENDPROC(am33xx_resume_from_deep_sleep)
+
+/*
+ * Local variables
+ */
+ .align
+resume_addr:
+ .word cpu_resume - PAGE_OFFSET + 0x80000000
+kernel_flush:
+ .word v7_flush_dcache_all
+virt_mpu_clkctrl:
+ .word AM33XX_CM_MPU_MPU_CLKCTRL
+virt_emif_clkctrl:
+ .word AM33XX_CM_PER_EMIF_CLKCTRL
+phys_emif_clkctrl:
+ .word (AM33XX_CM_BASE + AM33XX_CM_PER_MOD + \
+ AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET)
+
+.align 3
+/* DDR related defines */
+am33xx_emif_sram_table:
+ .space EMIF_PM_FUNCTIONS_SIZE
+
+ENTRY(am33xx_pm_sram)
+ .word am33xx_do_wfi
+ .word am33xx_do_wfi_sz
+ .word am33xx_resume_offset
+ .word am33xx_emif_sram_table
+ .word am33xx_pm_ro_sram_data
+
+.align 3
+ENTRY(am33xx_pm_ro_sram_data)
+ .space AMX3_PM_RO_SRAM_DATA_SIZE
+
+ENTRY(am33xx_do_wfi_sz)
+ .word . - am33xx_do_wfi
diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S
new file mode 100644
index 000000000000..b24be624e8b9
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep43xx.S
@@ -0,0 +1,391 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Low level suspend code for AM43XX SoCs
+ *
+ * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Dave Gerlach, Vaibhav Bedia
+ */
+
+#include <generated/ti-emif-asm-offsets.h>
+#include <generated/ti-pm-asm-offsets.h>
+#include <linux/linkage.h>
+#include <linux/ti-emif-sram.h>
+
+#include <asm/assembler.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/memory.h>
+
+#include "cm33xx.h"
+#include "common.h"
+#include "iomap.h"
+#include "omap-secure.h"
+#include "omap44xx.h"
+#include "prm33xx.h"
+#include "prcm43xx.h"
+
+#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
+#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
+#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
+
+#define AM43XX_EMIF_POWEROFF_ENABLE 0x1
+#define AM43XX_EMIF_POWEROFF_DISABLE 0x0
+
+#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP 0x1
+#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO 0x3
+
+#define AM43XX_CM_BASE 0x44DF0000
+
+#define AM43XX_CM_REGADDR(inst, reg) \
+ AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg))
+
+#define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \
+ AM43XX_CM_MPU_MPU_CDOFFS)
+#define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \
+ AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET)
+#define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_PER_INST, \
+ AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
+#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
+
+ .arm
+ .align 3
+
+ENTRY(am43xx_do_wfi)
+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
+
+#ifdef CONFIG_CACHE_L2X0
+ /* Retrieve l2 cache virt address BEFORE we shut off EMIF */
+ ldr r1, get_l2cache_base
+ blx r1
+ mov r8, r0
+#endif
+
+ /*
+ * Flush all data from the L1 and L2 data cache before disabling
+ * SCTLR.C bit.
+ */
+ ldr r1, kernel_flush
+ blx r1
+
+ /*
+ * Clear the SCTLR.C bit to prevent further data cache
+ * allocation. Clearing SCTLR.C would make all the data accesses
+ * strongly ordered and would not hit the cache.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #(1 << 2) @ Disable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+ dsb
+
+ /*
+ * Invalidate L1 and L2 data cache.
+ */
+ ldr r1, kernel_flush
+ blx r1
+
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * Clean and invalidate the L2 cache.
+ */
+#ifdef CONFIG_PL310_ERRATA_727915
+ mov r0, #0x03
+ mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+ dsb
+ smc #0
+ dsb
+#endif
+ mov r0, r8
+ adr r4, am43xx_pm_ro_sram_data
+ ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
+
+ mov r2, r0
+ ldr r0, [r2, #L2X0_AUX_CTRL]
+ str r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
+ ldr r0, [r2, #L310_PREFETCH_CTRL]
+ str r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
+
+ ldr r0, l2_val
+ str r0, [r2, #L2X0_CLEAN_INV_WAY]
+wait:
+ ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
+ ldr r1, l2_val
+ ands r0, r0, r1
+ bne wait
+#ifdef CONFIG_PL310_ERRATA_727915
+ mov r0, #0x00
+ mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+ dsb
+ smc #0
+ dsb
+#endif
+l2x_sync:
+ mov r0, r8
+ mov r2, r0
+ mov r0, #0x0
+ str r0, [r2, #L2X0_CACHE_SYNC]
+sync:
+ ldr r0, [r2, #L2X0_CACHE_SYNC]
+ ands r0, r0, #0x1
+ bne sync
+#endif
+
+ adr r9, am43xx_emif_sram_table
+
+ ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
+ blx r3
+
+ ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
+ blx r3
+
+ /* Disable EMIF */
+ ldr r1, am43xx_virt_emif_clkctrl
+ ldr r2, [r1]
+ bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
+ str r2, [r1]
+
+wait_emif_disable:
+ ldr r2, [r1]
+ mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
+ cmp r2, r3
+ bne wait_emif_disable
+
+ /*
+ * For the MPU WFI to be registered as an interrupt
+ * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
+ * to DISABLED
+ */
+ ldr r1, am43xx_virt_mpu_clkctrl
+ ldr r2, [r1]
+ bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
+ str r2, [r1]
+
+ /*
+ * Put MPU CLKDM to SW_SLEEP
+ */
+ ldr r1, am43xx_virt_mpu_clkstctrl
+ mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
+ str r2, [r1]
+
+ /*
+ * Execute a barrier instruction to ensure that all cache,
+ * TLB and branch predictor maintenance operations issued
+ * have completed.
+ */
+ dsb
+ dmb
+
+ /*
+ * Execute a WFI instruction and wait until the
+ * STANDBYWFI output is asserted to indicate that the
+ * CPU is in idle and low power state. CPU can specualatively
+ * prefetch the instructions so add NOPs after WFI. Sixteen
+ * NOPs as per Cortex-A9 pipeline.
+ */
+ wfi
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* We come here in case of an abort due to a late interrupt */
+ ldr r1, am43xx_virt_mpu_clkstctrl
+ mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
+ str r2, [r1]
+
+ /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
+ ldr r1, am43xx_virt_mpu_clkctrl
+ mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
+ str r2, [r1]
+
+ /* Re-enable EMIF */
+ ldr r1, am43xx_virt_emif_clkctrl
+ mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
+ str r2, [r1]
+wait_emif_enable:
+ ldr r3, [r1]
+ cmp r2, r3
+ bne wait_emif_enable
+
+ /*
+ * Set SCTLR.C bit to allow data cache allocation
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #(1 << 2) @ Enable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
+ blx r1
+
+ /* Let the suspend code know about the abort */
+ mov r0, #1
+ ldmfd sp!, {r4 - r11, pc} @ restore regs and return
+ENDPROC(am43xx_do_wfi)
+
+ .align
+ENTRY(am43xx_resume_offset)
+ .word . - am43xx_do_wfi
+
+ENTRY(am43xx_resume_from_deep_sleep)
+ /* Set MPU CLKSTCTRL to HW AUTO so that CPUidle works properly */
+ ldr r1, am43xx_virt_mpu_clkstctrl
+ mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
+ str r2, [r1]
+
+ /* For AM43xx, use EMIF power down until context is restored */
+ ldr r2, am43xx_phys_emif_poweroff
+ mov r1, #AM43XX_EMIF_POWEROFF_ENABLE
+ str r1, [r2, #0x0]
+
+ /* Re-enable EMIF */
+ ldr r1, am43xx_phys_emif_clkctrl
+ mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
+ str r2, [r1]
+wait_emif_enable1:
+ ldr r3, [r1]
+ cmp r2, r3
+ bne wait_emif_enable1
+
+ adr r9, am43xx_emif_sram_table
+
+ ldr r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
+ blx r1
+
+ ldr r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
+ blx r1
+
+ ldr r2, am43xx_phys_emif_poweroff
+ mov r1, #AM43XX_EMIF_POWEROFF_DISABLE
+ str r1, [r2, #0x0]
+
+#ifdef CONFIG_CACHE_L2X0
+ ldr r2, l2_cache_base
+ ldr r0, [r2, #L2X0_CTRL]
+ and r0, #0x0f
+ cmp r0, #1
+ beq skip_l2en @ Skip if already enabled
+
+ adr r4, am43xx_pm_ro_sram_data
+ ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET]
+ ldr r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
+
+ ldr r12, l2_smc1
+ dsb
+ smc #0
+ dsb
+set_aux_ctrl:
+ ldr r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
+ ldr r12, l2_smc2
+ dsb
+ smc #0
+ dsb
+
+ /* L2 invalidate on resume */
+ ldr r0, l2_val
+ ldr r2, l2_cache_base
+ str r0, [r2, #L2X0_INV_WAY]
+wait2:
+ ldr r0, [r2, #L2X0_INV_WAY]
+ ldr r1, l2_val
+ ands r0, r0, r1
+ bne wait2
+#ifdef CONFIG_PL310_ERRATA_727915
+ mov r0, #0x00
+ mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+ dsb
+ smc #0
+ dsb
+#endif
+l2x_sync2:
+ ldr r2, l2_cache_base
+ mov r0, #0x0
+ str r0, [r2, #L2X0_CACHE_SYNC]
+sync2:
+ ldr r0, [r2, #L2X0_CACHE_SYNC]
+ ands r0, r0, #0x1
+ bne sync2
+
+ mov r0, #0x1
+ ldr r12, l2_smc3
+ dsb
+ smc #0
+ dsb
+#endif
+skip_l2en:
+ /* We are back. Branch to the common CPU resume routine */
+ mov r0, #0
+ ldr pc, resume_addr
+ENDPROC(am43xx_resume_from_deep_sleep)
+
+/*
+ * Local variables
+ */
+ .align
+resume_addr:
+ .word cpu_resume - PAGE_OFFSET + 0x80000000
+kernel_flush:
+ .word v7_flush_dcache_all
+ddr_start:
+ .word PAGE_OFFSET
+
+am43xx_phys_emif_poweroff:
+ .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \
+ AM43XX_PRM_EMIF_CTRL_OFFSET)
+am43xx_virt_mpu_clkstctrl:
+ .word (AM43XX_CM_MPU_CLKSTCTRL)
+am43xx_virt_mpu_clkctrl:
+ .word (AM43XX_CM_MPU_MPU_CLKCTRL)
+am43xx_virt_emif_clkctrl:
+ .word (AM43XX_CM_PER_EMIF_CLKCTRL)
+am43xx_phys_emif_clkctrl:
+ .word (AM43XX_CM_BASE + AM43XX_CM_PER_INST + \
+ AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
+
+#ifdef CONFIG_CACHE_L2X0
+/* L2 cache related defines for AM437x */
+get_l2cache_base:
+ .word omap4_get_l2cache_base
+l2_cache_base:
+ .word OMAP44XX_L2CACHE_BASE
+l2_smc1:
+ .word OMAP4_MON_L2X0_PREFETCH_INDEX
+l2_smc2:
+ .word OMAP4_MON_L2X0_AUXCTRL_INDEX
+l2_smc3:
+ .word OMAP4_MON_L2X0_CTRL_INDEX
+l2_val:
+ .word 0xffff
+#endif
+
+.align 3
+/* DDR related defines */
+ENTRY(am43xx_emif_sram_table)
+ .space EMIF_PM_FUNCTIONS_SIZE
+
+ENTRY(am43xx_pm_sram)
+ .word am43xx_do_wfi
+ .word am43xx_do_wfi_sz
+ .word am43xx_resume_offset
+ .word am43xx_emif_sram_table
+ .word am43xx_pm_ro_sram_data
+
+.align 3
+
+ENTRY(am43xx_pm_ro_sram_data)
+ .space AMX3_PM_RO_SRAM_DATA_SIZE
+
+ENTRY(am43xx_do_wfi_sz)
+ .word . - am43xx_do_wfi
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 56dfa2d5d0a8..0cae3b070208 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -90,12 +90,7 @@ skip_secure_l1_clean:
mcr p15, 0, r0, c1, c0, 0
isb
- /*
- * Invalidate L1 data cache. Even though only invalidate is
- * necessary exported flush API is used here. Doing clean
- * on already clean cache would be almost NOP.
- */
- bl v7_flush_dcache_all
+ bl v7_invalidate_l1
/*
* Switch the CPU from Symmetric Multiprocessing (SMP) mode
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index eef6935e0403..0854ed9ff379 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -89,18 +89,27 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
sr_data->nvalue_count = j;
}
+extern struct omap_sr_data omap_sr_pdata[];
+
static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
{
- struct omap_sr_data *sr_data;
- struct platform_device *pdev;
+ struct omap_sr_data *sr_data = NULL;
struct omap_volt_data *volt_data;
struct omap_smartreflex_dev_attr *sr_dev_attr;
- char *name = "smartreflex";
static int i;
- sr_data = kzalloc(sizeof(*sr_data), GFP_KERNEL);
- if (!sr_data)
- return -ENOMEM;
+ if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) ||
+ !strncmp(oh->name, "smartreflex_mpu", 16))
+ sr_data = &omap_sr_pdata[OMAP_SR_MPU];
+ else if (!strncmp(oh->name, "smartreflex_core", 17))
+ sr_data = &omap_sr_pdata[OMAP_SR_CORE];
+ else if (!strncmp(oh->name, "smartreflex_iva", 16))
+ sr_data = &omap_sr_pdata[OMAP_SR_IVA];
+
+ if (!sr_data) {
+ pr_err("%s: Unknown instance %s\n", __func__, oh->name);
+ return -EINVAL;
+ }
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
@@ -145,13 +154,9 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
sr_data->enable_on_init = sr_enable_on_init;
- pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
- if (IS_ERR(pdev))
- pr_warn("%s: Could not build omap_device for %s: %s\n",
- __func__, name, oh->name);
exit:
i++;
- kfree(sr_data);
+
return 0;
}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index d61fbd7a2840..4fb4dc24e5e9 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -49,7 +49,7 @@
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/counter-32k.h>
-#include <plat/dmtimer.h>
+#include <clocksource/timer-ti-dm.h>
#include "omap-pm.h"
#include "soc.h"
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index c487401b6fdb..c5c0ab8ac9f9 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -23,6 +23,7 @@
#include <linux/clk.h>
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/dm9000.h>
#include <linux/leds.h>
#include <linux/platform_data/rtc-v3020.h>
@@ -343,9 +344,6 @@ static inline void cm_x300_init_bl(void) {}
#define LCD_SPI_BUS_NUM (1)
static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = {
- .sck = GPIO_LCD_SCL,
- .mosi = GPIO_LCD_DIN,
- .miso = GPIO_LCD_DOUT,
.num_chipselect = 1,
};
@@ -357,6 +355,21 @@ static struct platform_device cm_x300_spi_gpio = {
},
};
+static struct gpiod_lookup_table cm_x300_spi_gpiod_table = {
+ .dev_id = "spi_gpio",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_LCD_SCL,
+ "sck", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DIN,
+ "mosi", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DOUT,
+ "miso", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO_LCD_CS,
+ "cs", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct tdo24m_platform_data cm_x300_tdo24m_pdata = {
.model = TDO35S,
};
@@ -367,7 +380,6 @@ static struct spi_board_info cm_x300_spi_devices[] __initdata = {
.max_speed_hz = 1000000,
.bus_num = LCD_SPI_BUS_NUM,
.chip_select = 0,
- .controller_data = (void *) GPIO_LCD_CS,
.platform_data = &cm_x300_tdo24m_pdata,
},
};
@@ -376,6 +388,7 @@ static void __init cm_x300_init_spi(void)
{
spi_register_board_info(cm_x300_spi_devices,
ARRAY_SIZE(cm_x300_spi_devices));
+ gpiod_add_lookup_table(&cm_x300_spi_gpiod_table);
platform_device_register(&cm_x300_spi_gpio);
}
#else
@@ -391,7 +404,7 @@ static void __init cm_x300_init_ac97(void)
static inline void cm_x300_init_ac97(void) {}
#endif
-#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct mtd_partition cm_x300_nand_partitions[] = {
[0] = {
.name = "OBM",
@@ -429,11 +442,9 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
- .enable_arbiter = 1,
.keep_config = 1,
- .num_cs = 1,
- .parts[0] = cm_x300_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(cm_x300_nand_partitions),
+ .parts = cm_x300_nand_partitions,
+ .nr_parts = ARRAY_SIZE(cm_x300_nand_partitions),
};
static void __init cm_x300_init_nand(void)
@@ -509,7 +520,7 @@ static int cm_x300_ulpi_phy_reset(void)
return 0;
}
-static inline int cm_x300_u2d_init(struct device *dev)
+static int cm_x300_u2d_init(struct device *dev)
{
int err = 0;
@@ -521,7 +532,7 @@ static inline int cm_x300_u2d_init(struct device *dev)
pr_err("failed to get CLK_POUT: %d\n", err);
return err;
}
- clk_enable(pout_clk);
+ clk_prepare_enable(pout_clk);
err = cm_x300_ulpi_phy_reset();
if (err) {
@@ -536,7 +547,7 @@ static inline int cm_x300_u2d_init(struct device *dev)
static void cm_x300_u2d_exit(struct device *dev)
{
if (cpu_is_pxa310()) {
- clk_disable(pout_clk);
+ clk_disable_unprepare(pout_clk);
clk_put(pout_clk);
}
}
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index b04431bb4ba7..e31a591e949f 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -110,7 +110,7 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin)
}
#endif
-#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct mtd_partition colibri_nand_partitions[] = {
{
.name = "bootloader",
@@ -138,11 +138,9 @@ static struct mtd_partition colibri_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data colibri_nand_info = {
- .enable_arbiter = 1,
.keep_config = 1,
- .num_cs = 1,
- .parts[0] = colibri_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(colibri_nand_partitions),
+ .parts = colibri_nand_partitions,
+ .nr_parts = ARRAY_SIZE(colibri_nand_partitions),
};
void __init colibri_pxa3xx_init_nand(void)
diff --git a/arch/arm/mach-pxa/colibri.h b/arch/arm/mach-pxa/colibri.h
index 673a131da875..85525d49e321 100644
--- a/arch/arm/mach-pxa/colibri.h
+++ b/arch/arm/mach-pxa/colibri.h
@@ -46,7 +46,7 @@ static inline void colibri_pxa3xx_init_lcd(int bl_pin) {}
extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data);
#endif
-#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
extern void colibri_pxa3xx_init_nand(void);
#else
static inline void colibri_pxa3xx_init_nand(void) {}
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 4105614cc38e..9e132b3e48c6 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -291,7 +291,7 @@ static void __init littleton_init_mmc(void)
static inline void littleton_init_mmc(void) {}
#endif
-#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct mtd_partition littleton_nand_partitions[] = {
[0] = {
.name = "Bootloader",
@@ -329,10 +329,8 @@ static struct mtd_partition littleton_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data littleton_nand_info = {
- .enable_arbiter = 1,
- .num_cs = 1,
- .parts[0] = littleton_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(littleton_nand_partitions),
+ .parts = littleton_nand_partitions,
+ .nr_parts = ARRAY_SIZE(littleton_nand_partitions),
};
static void __init littleton_init_nand(void)
@@ -341,7 +339,7 @@ static void __init littleton_init_nand(void)
}
#else
static inline void littleton_init_nand(void) {}
-#endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
+#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */
#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
static struct led_info littleton_da9034_leds[] = {
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index f9e3d41a4609..616b22397d73 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -359,7 +359,7 @@ void __init mxm_8x10_ac97_init(void)
}
/* NAND flash Support */
-#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
#define NAND_BLOCK_SIZE SZ_128K
#define NB(x) (NAND_BLOCK_SIZE * (x))
static struct mtd_partition mxm_8x10_nand_partitions[] = {
@@ -389,11 +389,9 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
- .enable_arbiter = 1,
.keep_config = 1,
- .num_cs = 1,
- .parts[0] = mxm_8x10_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(mxm_8x10_nand_partitions)
+ .parts = mxm_8x10_nand_partitions,
+ .nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions)
};
static void __init mxm_8x10_nand_init(void)
@@ -402,7 +400,7 @@ static void __init mxm_8x10_nand_init(void)
}
#else
static inline void mxm_8x10_nand_init(void) {}
-#endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
+#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */
/* Ethernet support: Davicom DM9000 */
static struct resource dm9k_resources[] = {
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index 60cb59a7ebd1..b3e2016f24b1 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -256,7 +256,7 @@ int pxa3xx_u2d_start_hc(struct usb_bus *host)
if (!u2d)
return 0;
- clk_enable(u2d->clk);
+ clk_prepare_enable(u2d->clk);
if (cpu_is_pxa310()) {
pxa310_u2d_setup_otg_hc();
@@ -276,7 +276,7 @@ void pxa3xx_u2d_stop_hc(struct usb_bus *host)
if (cpu_is_pxa310())
pxa310_stop_otg_hc();
- clk_disable(u2d->clk);
+ clk_disable_unprepare(u2d->clk);
}
EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc);
@@ -331,7 +331,7 @@ static int pxa3xx_u2d_probe(struct platform_device *pdev)
goto err_free_plat;
}
- platform_set_drvdata(pdev, &u2d);
+ platform_set_drvdata(pdev, u2d);
return 0;
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 4d5d05cf87d6..034345546f84 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -346,11 +346,9 @@ static struct mtd_partition raumfeld_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
- .enable_arbiter = 1,
.keep_config = 1,
- .num_cs = 1,
- .parts[0] = raumfeld_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(raumfeld_nand_partitions),
+ .parts = raumfeld_nand_partitions,
+ .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions),
};
/**
@@ -378,9 +376,9 @@ static struct gpiod_lookup_table raumfeld_rotary_gpios_table = {
};
static const struct property_entry raumfeld_rotary_properties[] __initconst = {
- PROPERTY_ENTRY_INTEGER("rotary-encoder,steps-per-period", u32, 24),
- PROPERTY_ENTRY_INTEGER("linux,axis", u32, REL_X),
- PROPERTY_ENTRY_INTEGER("rotary-encoder,relative_axis", u32, 1),
+ PROPERTY_ENTRY_U32("rotary-encoder,steps-per-period", 24),
+ PROPERTY_ENTRY_U32("linux,axis", REL_X),
+ PROPERTY_ENTRY_U32("rotary-encoder,relative_axis", 1),
{ },
};
@@ -646,9 +644,6 @@ static void __init raumfeld_lcd_init(void)
*/
static struct spi_gpio_platform_data raumfeld_spi_platform_data = {
- .sck = GPIO_SPI_CLK,
- .mosi = GPIO_SPI_MOSI,
- .miso = GPIO_SPI_MISO,
.num_chipselect = 3,
};
@@ -660,6 +655,25 @@ static struct platform_device raumfeld_spi_device = {
}
};
+static struct gpiod_lookup_table raumfeld_spi_gpiod_table = {
+ .dev_id = "spi_gpio",
+ .table = {
+ GPIO_LOOKUP("gpio-0", GPIO_SPI_CLK,
+ "sck", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-0", GPIO_SPI_MOSI,
+ "mosi", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-0", GPIO_SPI_MISO,
+ "miso", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("gpio-0", GPIO_SPDIF_CS,
+ "cs", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("gpio-0", GPIO_ACCEL_CS,
+ "cs", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("gpio-0", GPIO_MCLK_DAC_CS,
+ "cs", 2, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct lis3lv02d_platform_data lis3_pdata = {
.click_flags = LIS3_CLICK_SINGLE_X |
LIS3_CLICK_SINGLE_Y |
@@ -680,7 +694,6 @@ static struct lis3lv02d_platform_data lis3_pdata = {
.max_speed_hz = 10000, \
.bus_num = 0, \
.chip_select = 0, \
- .controller_data = (void *) GPIO_SPDIF_CS, \
}
#define SPI_LIS3 \
@@ -689,7 +702,6 @@ static struct lis3lv02d_platform_data lis3_pdata = {
.max_speed_hz = 1000000, \
.bus_num = 0, \
.chip_select = 1, \
- .controller_data = (void *) GPIO_ACCEL_CS, \
.platform_data = &lis3_pdata, \
.irq = PXA_GPIO_TO_IRQ(GPIO_ACCEL_IRQ), \
}
@@ -700,7 +712,6 @@ static struct lis3lv02d_platform_data lis3_pdata = {
.max_speed_hz = 1000000, \
.bus_num = 0, \
.chip_select = 2, \
- .controller_data = (void *) GPIO_MCLK_DAC_CS, \
}
static struct spi_board_info connector_spi_devices[] __initdata = {
@@ -1066,6 +1077,7 @@ static void __init raumfeld_common_init(void)
else
gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0);
+ gpiod_add_lookup_table(&raumfeld_spi_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(raumfeld_common_devices));
i2c_register_board_info(1, &raumfeld_pwri2c_board_info, 1);
}
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 4268552d600d..d69de312d8d9 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -338,7 +338,7 @@ static void __init zylonite_init_keypad(void)
static inline void zylonite_init_keypad(void) {}
#endif
-#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct mtd_partition zylonite_nand_partitions[] = {
[0] = {
.name = "Bootloader",
@@ -376,10 +376,8 @@ static struct mtd_partition zylonite_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data zylonite_nand_info = {
- .enable_arbiter = 1,
- .num_cs = 1,
- .parts[0] = zylonite_nand_partitions,
- .nr_parts[0] = ARRAY_SIZE(zylonite_nand_partitions),
+ .parts = zylonite_nand_partitions,
+ .nr_parts = ARRAY_SIZE(zylonite_nand_partitions),
};
static void __init zylonite_init_nand(void)
@@ -388,7 +386,7 @@ static void __init zylonite_init_nand(void)
}
#else
static inline void zylonite_init_nand(void) {}
-#endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
+#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static struct pxaohci_platform_data zylonite_ohci_info = {
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index ecec340ca345..51984a40b097 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -208,6 +208,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
}
static const struct regmap_config rockchip_pmu_regmap_config = {
+ .name = "rockchip-pmu",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index a3ddbbbd6d92..59589a4a0d4b 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -12,6 +12,7 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
@@ -388,32 +389,53 @@ static struct ili9320_platdata jive_lcm_config = {
/* LCD SPI support */
static struct spi_gpio_platform_data jive_lcd_spi = {
- .sck = S3C2410_GPG(8),
- .mosi = S3C2410_GPB(8),
- .miso = SPI_GPIO_NO_MISO,
+ .num_chipselect = 1,
};
static struct platform_device jive_device_lcdspi = {
- .name = "spi-gpio",
+ .name = "spi_gpio",
.id = 1,
.dev.platform_data = &jive_lcd_spi,
};
+static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
+ .dev_id = "spi_gpio",
+ .table = {
+ GPIO_LOOKUP("GPIOG", 8,
+ "sck", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOB", 8,
+ "mosi", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOB", 7,
+ "cs", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
/* WM8750 audio code SPI definition */
static struct spi_gpio_platform_data jive_wm8750_spi = {
- .sck = S3C2410_GPB(4),
- .mosi = S3C2410_GPB(9),
- .miso = SPI_GPIO_NO_MISO,
+ .num_chipselect = 1,
};
static struct platform_device jive_device_wm8750 = {
- .name = "spi-gpio",
+ .name = "spi_gpio",
.id = 2,
.dev.platform_data = &jive_wm8750_spi,
};
+static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
+ .dev_id = "spi_gpio",
+ .table = {
+ GPIO_LOOKUP("GPIOB", 4,
+ "gpio-sck", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOB", 9,
+ "gpio-mosi", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOH", 10,
+ "cs", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
/* JIVE SPI devices. */
static struct spi_board_info __initdata jive_spi_devs[] = {
@@ -424,14 +446,12 @@ static struct spi_board_info __initdata jive_spi_devs[] = {
.mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
.max_speed_hz = 100000,
.platform_data = &jive_lcm_config,
- .controller_data = (void *)S3C2410_GPB(7),
}, {
.modalias = "WM8750",
.bus_num = 2,
.chip_select = 0,
.mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
.max_speed_hz = 100000,
- .controller_data = (void *)S3C2410_GPH(10),
},
};
@@ -619,25 +639,12 @@ static void __init jive_machine_init(void)
/** TODO - check that this is after the cmdline option! */
s3c_nand_set_platdata(&jive_nand_info);
- /* initialise the spi */
-
gpio_request(S3C2410_GPG(13), "lcm reset");
gpio_direction_output(S3C2410_GPG(13), 0);
- gpio_request(S3C2410_GPB(7), "jive spi");
- gpio_direction_output(S3C2410_GPB(7), 1);
-
gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
gpio_free(S3C2410_GPB(6));
- gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPG(8));
-
- /* initialise the WM8750 spi */
-
- gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
- gpio_direction_output(S3C2410_GPH(10), 1);
-
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
@@ -655,6 +662,8 @@ static void __init jive_machine_init(void)
pm_power_off = jive_power_off;
+ gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
+ gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
}
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 9c8373b8d9c3..5d48e5b6e738 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -11,6 +11,7 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
@@ -194,17 +195,30 @@ static struct platform_device qt2410_led = {
/* SPI */
static struct spi_gpio_platform_data spi_gpio_cfg = {
- .sck = S3C2410_GPG(7),
- .mosi = S3C2410_GPG(6),
- .miso = S3C2410_GPG(5),
+ .num_chipselect = 1,
};
static struct platform_device qt2410_spi = {
- .name = "spi-gpio",
+ .name = "spi_gpio",
.id = 1,
.dev.platform_data = &spi_gpio_cfg,
};
+static struct gpiod_lookup_table qt2410_spi_gpiod_table = {
+ .dev_id = "spi_gpio",
+ .table = {
+ GPIO_LOOKUP("GPIOG", 7,
+ "sck", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOG", 6,
+ "mosi", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOG", 5,
+ "miso", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOB", 5,
+ "cs", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
/* Board devices */
static struct platform_device *qt2410_devices[] __initdata = {
@@ -323,9 +337,7 @@ static void __init qt2410_machine_init(void)
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
s3c_i2c0_set_platdata(NULL);
- WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
- gpio_direction_output(S3C2410_GPB(5), 1);
-
+ gpiod_add_lookup_table(&qt2410_spi_gpiod_table);
platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
s3c_pm_init();
}
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 5655fe968b1f..951208f168e7 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -206,17 +206,30 @@ static int __init smartq_lcd_setup_gpio(void)
/* GPM0 -> CS */
static struct spi_gpio_platform_data smartq_lcd_control = {
- .sck = S3C64XX_GPM(1),
- .mosi = S3C64XX_GPM(2),
- .miso = S3C64XX_GPM(2),
+ .num_chipselect = 1,
};
static struct platform_device smartq_lcd_control_device = {
- .name = "spi-gpio",
+ .name = "spi_gpio",
.id = 1,
.dev.platform_data = &smartq_lcd_control,
};
+static struct gpiod_lookup_table smartq_lcd_control_gpiod_table = {
+ .dev_id = "spi_gpio",
+ .table = {
+ GPIO_LOOKUP("GPIOM", 1,
+ "sck", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOM", 2,
+ "mosi", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOM", 3,
+ "miso", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOM", 0,
+ "cs", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
{
gpio_direction_output(S3C64XX_GPM(3), power);
@@ -404,6 +417,7 @@ void __init smartq_machine_init(void)
WARN_ON(smartq_wifi_init());
pwm_add_table(smartq_pwm_lookup, ARRAY_SIZE(smartq_pwm_lookup));
+ gpiod_add_lookup_table(&smartq_lcd_control_gpiod_table);
platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
gpiod_add_lookup_table(&smartq_audio_gpios);
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 07df3a59b13f..fde7ef1ab192 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -6,6 +6,8 @@ config SA1100_ASSABET
bool "Assabet"
select ARM_SA1110_CPUFREQ
select GPIO_REG
+ select REGULATOR
+ select REGULATOR_FIXED_VOLTAGE
help
Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
Microprocessor Development Board (also known as the Assabet).
@@ -137,6 +139,8 @@ config SA1100_PLEB
config SA1100_SHANNON
bool "Shannon"
select ARM_SA1100_CPUFREQ
+ select REGULATOR
+ select REGULATOR_FIXED_VOLTAGE
help
The Shannon (also known as a Tuxscreen, and also as a IS2630) was a
limited edition webphone produced by Philips. The Shannon is a SA1100
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index f68241d995f2..575ec085cffa 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -14,8 +14,11 @@
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/gpio/gpio-reg.h>
+#include <linux/gpio/machine.h>
#include <linux/ioport.h>
#include <linux/platform_data/sa11x0-serial.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/mfd/ucb1x00.h>
@@ -445,6 +448,29 @@ static struct resource neponset_resources[] = {
};
#endif
+static struct gpiod_lookup_table assabet_cf_gpio_table = {
+ .dev_id = "sa11x0-pcmcia.1",
+ .table = {
+ GPIO_LOOKUP("gpio", 21, "ready", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 22, "detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", 24, "bvd2", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 25, "bvd1", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("assabet", 1, "reset", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("assabet", 7, "bus-enable", GPIO_ACTIVE_LOW),
+ { },
+ },
+};
+
+static struct regulator_consumer_supply assabet_cf_vcc_consumers[] = {
+ REGULATOR_SUPPLY("vcc", "sa11x0-pcmcia.1"),
+};
+
+static struct fixed_voltage_config assabet_cf_vcc_pdata __initdata = {
+ .supply_name = "cf-power",
+ .microvolts = 3300000,
+ .enable_high = 1,
+};
+
static void __init assabet_init(void)
{
/*
@@ -490,6 +516,11 @@ static void __init assabet_init(void)
platform_device_register_simple("neponset", 0,
neponset_resources, ARRAY_SIZE(neponset_resources));
#endif
+ } else {
+ sa11x0_register_fixed_regulator(0, &assabet_cf_vcc_pdata,
+ assabet_cf_vcc_consumers,
+ ARRAY_SIZE(assabet_cf_vcc_consumers));
+
}
#ifndef ASSABET_PAL_VIDEO
@@ -501,6 +532,9 @@ static void __init assabet_init(void)
ARRAY_SIZE(assabet_flash_resources));
sa11x0_register_irda(&assabet_irda_data);
sa11x0_register_mcp(&assabet_mcp_data);
+
+ if (!machine_has_neponset())
+ sa11x0_register_pcmcia(1, &assabet_cf_gpio_table);
}
/*
@@ -768,6 +802,7 @@ fs_initcall(assabet_leds_init);
void __init assabet_init_irq(void)
{
+ unsigned int assabet_gpio_base;
u32 def_val;
sa1100_init_irq();
@@ -782,7 +817,9 @@ void __init assabet_init_irq(void)
*
* This must precede any driver calls to BCR_set() or BCR_clear().
*/
- assabet_init_gpio((void *)&ASSABET_BCR, def_val);
+ assabet_gpio_base = assabet_init_gpio((void *)&ASSABET_BCR, def_val);
+
+ assabet_cf_vcc_pdata.gpio = assabet_gpio_base + 0;
}
MACHINE_START(ASSABET, "Intel-Assabet")
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 2d25ececb415..b2a4b41626ef 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -11,6 +11,7 @@
*/
#include <linux/init.h>
+#include <linux/gpio/machine.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/platform_data/sa11x0-serial.h>
@@ -45,6 +46,19 @@ static struct platform_device cerfuart2_device = {
.resource = cerfuart2_resources,
};
+/* Compact Flash */
+static struct gpiod_lookup_table cerf_cf_gpio_table = {
+ .dev_id = "sa11x0-pcmcia.1",
+ .table = {
+ GPIO_LOOKUP("gpio", 19, "bvd2", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 20, "bvd1", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 21, "reset", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 22, "ready", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 23, "detect", GPIO_ACTIVE_LOW),
+ { },
+ },
+};
+
/* LEDs */
struct gpio_led cerf_gpio_leds[] = {
{
@@ -151,9 +165,6 @@ static void __init cerf_map_io(void)
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 2); /* disable this and the uart2 device for sa1100_fir */
sa1100_register_uart(2, 1);
-
- /* set some GPDR bits here while it's safe */
- GPDR |= CERF_GPIO_CF_RESET;
}
static struct mcp_plat_data cerf_mcp_data = {
@@ -167,6 +178,7 @@ static void __init cerf_init(void)
platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
sa11x0_register_mcp(&cerf_mcp_data);
+ sa11x0_register_pcmcia(1, &cerf_cf_gpio_table);
}
MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index b2eb3d232e39..6199e87447ca 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -163,6 +163,8 @@ static struct clk_lookup sa11xx_clkregs[] = {
CLKDEV_INIT("sa1100-rtc", NULL, NULL),
CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
+ CLKDEV_INIT("sa11x0-pcmcia.0", NULL, &clk_cpu),
+ CLKDEV_INIT("sa11x0-pcmcia.1", NULL, &clk_cpu),
/* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
CLKDEV_INIT("1800", NULL, &clk_cpu),
CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 2eb00691b07d..7167ddf84a0e 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
@@ -20,6 +21,8 @@
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
#include <linux/irqchip/irq-sa11x0.h>
#include <video/sa1100fb.h>
@@ -232,11 +235,20 @@ void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
sa11x0_register_device(&sa11x0fb_device, inf);
}
+static bool sa11x0pcmcia_legacy = true;
static struct platform_device sa11x0pcmcia_device = {
.name = "sa11x0-pcmcia",
.id = -1,
};
+void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *table)
+{
+ if (table)
+ gpiod_add_lookup_table(table);
+ platform_device_register_simple("sa11x0-pcmcia", socket, NULL, 0);
+ sa11x0pcmcia_legacy = false;
+}
+
static struct platform_device sa11x0mtd_device = {
.name = "sa1100-mtd",
.id = -1,
@@ -311,7 +323,6 @@ static struct platform_device *sa11x0_devices[] __initdata = {
&sa11x0uart1_device,
&sa11x0uart3_device,
&sa11x0ssp_device,
- &sa11x0pcmcia_device,
&sa11x0rtc_device,
&sa11x0dma_device,
};
@@ -319,6 +330,12 @@ static struct platform_device *sa11x0_devices[] __initdata = {
static int __init sa1100_init(void)
{
pm_power_off = sa1100_power_off;
+
+ if (sa11x0pcmcia_legacy)
+ platform_device_register(&sa11x0pcmcia_device);
+
+ regulator_has_full_constraints();
+
return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
}
@@ -329,6 +346,31 @@ void __init sa11x0_init_late(void)
sa11x0_pm_init();
}
+int __init sa11x0_register_fixed_regulator(int n,
+ struct fixed_voltage_config *cfg,
+ struct regulator_consumer_supply *supplies, unsigned num_supplies)
+{
+ struct regulator_init_data *id;
+
+ cfg->init_data = id = kzalloc(sizeof(*cfg->init_data), GFP_KERNEL);
+ if (!cfg->init_data)
+ return -ENOMEM;
+
+ if (cfg->gpio < 0)
+ id->constraints.always_on = 1;
+ id->constraints.name = cfg->supply_name;
+ id->constraints.min_uV = cfg->microvolts;
+ id->constraints.max_uV = cfg->microvolts;
+ id->constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
+ id->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
+ id->consumer_supplies = supplies;
+ id->num_consumer_supplies = num_supplies;
+
+ platform_device_register_resndata(NULL, "reg-fixed-voltage", n,
+ NULL, 0, cfg, sizeof(*cfg));
+ return 0;
+}
+
/*
* Common I/O mapping:
*
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 97502922a15d..5f3cb52fa6ab 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -47,3 +47,11 @@ static inline int sa11x0_pm_init(void) { return 0; }
#endif
int sa11xx_clk_init(void);
+
+struct gpiod_lookup_table;
+void sa11x0_register_pcmcia(int socket, struct gpiod_lookup_table *);
+
+struct fixed_voltage_config;
+struct regulator_consumer_supply;
+int sa11x0_register_fixed_regulator(int n, struct fixed_voltage_config *cfg,
+ struct regulator_consumer_supply *supplies, unsigned num_supplies);
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index b69e76614d5b..36a78b0c106f 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -11,6 +11,7 @@
*/
#include <linux/kernel.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
@@ -264,8 +265,24 @@ static struct platform_device *h3xxx_devices[] = {
&h3xxx_micro_asic,
};
+static struct gpiod_lookup_table h3xxx_pcmcia_gpio_table = {
+ .dev_id = "sa11x0-pcmcia",
+ .table = {
+ GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_CD0,
+ "pcmcia0-detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_IRQ0,
+ "pcmcia0-ready", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_CD1,
+ "pcmcia1-detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", H3XXX_GPIO_PCMCIA_IRQ1,
+ "pcmcia1-ready", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
void __init h3xxx_mach_init(void)
{
+ gpiod_add_lookup_table(&h3xxx_pcmcia_gpio_table);
sa1100_register_uart_fns(&h3xxx_port_fns);
sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 558b45323a2d..641a961653af 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -96,10 +96,4 @@ extern void assabet_uda1341_reset(int set);
#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
-/* These are gpiolib GPIO numbers, not bitmasks */
-#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */
-#define ASSABET_GPIO_CF_CD 22 /* CF CD */
-#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */
-#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
-
#endif
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index f1cb3784d525..4d35258a7b32 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -12,6 +12,7 @@
*/
#include <linux/init.h>
+#include <linux/gpio/machine.h>
#include <linux/kernel.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/mtd/mtd.h>
@@ -99,8 +100,30 @@ static void __init nanoengine_map_io(void)
Ser2HSCR0 = 0;
}
+static struct gpiod_lookup_table nanoengine_pcmcia0_gpio_table = {
+ .dev_id = "sa11x0-pcmcia.0",
+ .table = {
+ GPIO_LOOKUP("gpio", 11, "ready", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 13, "detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", 15, "reset", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table nanoengine_pcmcia1_gpio_table = {
+ .dev_id = "sa11x0-pcmcia.1",
+ .table = {
+ GPIO_LOOKUP("gpio", 12, "ready", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", 14, "detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", 16, "reset", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static void __init nanoengine_init(void)
{
+ sa11x0_register_pcmcia(0, &nanoengine_pcmcia0_gpio_table);
+ sa11x0_register_pcmcia(1, &nanoengine_pcmcia1_gpio_table);
sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
ARRAY_SIZE(nanoengine_flash_resources));
}
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 856664c783d9..22f7fe0b809f 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -5,11 +5,14 @@
#include <linux/init.h>
#include <linux/device.h>
+#include <linux/gpio/machine.h>
#include <linux/kernel.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/tty.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
#include <video/sa1100fb.h>
@@ -72,8 +75,43 @@ static struct sa1100fb_mach_info shannon_lcd_info = {
.lccr3 = LCCR3_ACBsDiv(512),
};
+static struct gpiod_lookup_table shannon_pcmcia0_gpio_table = {
+ .dev_id = "sa11x0-pcmcia.0",
+ .table = {
+ GPIO_LOOKUP("gpio", 24, "detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", 26, "ready", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table shannon_pcmcia1_gpio_table = {
+ .dev_id = "sa11x0-pcmcia.1",
+ .table = {
+ GPIO_LOOKUP("gpio", 25, "detect", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio", 27, "ready", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct regulator_consumer_supply shannon_cf_vcc_consumers[] = {
+ REGULATOR_SUPPLY("vcc", "sa11x0-pcmcia.0"),
+ REGULATOR_SUPPLY("vcc", "sa11x0-pcmcia.1"),
+};
+
+static struct fixed_voltage_config shannon_cf_vcc_pdata __initdata = {
+ .supply_name = "cf-power",
+ .microvolts = 3300000,
+ .enabled_at_boot = 1,
+ .gpio = -EINVAL,
+};
+
static void __init shannon_init(void)
{
+ sa11x0_register_fixed_regulator(0, &shannon_cf_vcc_pdata,
+ shannon_cf_vcc_consumers,
+ ARRAY_SIZE(shannon_cf_vcc_consumers));
+ sa11x0_register_pcmcia(0, &shannon_pcmcia0_gpio_table);
+ sa11x0_register_pcmcia(1, &shannon_pcmcia1_gpio_table);
sa11x0_ppc_configure_mcp();
sa11x0_register_lcd(&shannon_lcd_info);
sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 7d4feb8a49ac..ace010479eb6 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -4,6 +4,7 @@
*/
#include <linux/module.h>
+#include <linux/gpio/machine.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/tty.h>
@@ -364,6 +365,15 @@ static struct platform_device *devices[] __initdata = {
&simpad_i2c,
};
+/* Compact Flash */
+static struct gpiod_lookup_table simpad_cf_gpio_table = {
+ .dev_id = "sa11x0-pcmcia",
+ .table = {
+ GPIO_LOOKUP("gpio", GPIO_CF_IRQ, "cf-ready", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio", GPIO_CF_CD, "cf-detect", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
static int __init simpad_init(void)
@@ -385,6 +395,7 @@ static int __init simpad_init(void)
pm_power_off = simpad_power_off;
+ sa11x0_register_pcmcia(-1, &simpad_cf_gpio_table);
sa11x0_ppc_configure_mcp();
sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
ARRAY_SIZE(simpad_flash_resources));
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index a8fa4f7e1f60..43c1ac696274 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -7,6 +7,10 @@ extern void shmobile_init_delay(void);
extern void shmobile_boot_vector(void);
extern unsigned long shmobile_boot_fn;
extern unsigned long shmobile_boot_size;
+extern void shmobile_boot_vector_gen2(void);
+extern unsigned long shmobile_boot_fn_gen2;
+extern unsigned long shmobile_boot_cpu_gen2;
+extern unsigned long shmobile_boot_size_gen2;
extern void shmobile_smp_boot(void);
extern void shmobile_smp_sleep(void);
extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 32e0bf6e3ccb..cef8e8c555f8 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,6 +16,11 @@
#include <asm/assembler.h>
#include <asm/memory.h>
+#define SCTLR_MMU 0x01
+#define BOOTROM_ADDRESS 0xE6340000
+#define RWTCSRA_ADDRESS 0xE6020004
+#define RWTCSRA_WOVF 0x10
+
/*
* Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register.
@@ -37,6 +42,56 @@ shmobile_boot_fn:
shmobile_boot_size:
.long . - shmobile_boot_vector
+#ifdef CONFIG_ARCH_RCAR_GEN2
+/*
+ * Reset vector for R-Car Gen2 and RZ/G1 secondary CPUs.
+ * This will be mapped at address 0 by SBAR register.
+ */
+ENTRY(shmobile_boot_vector_gen2)
+ mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR
+ ldr r1, shmobile_boot_cpu_gen2
+ cmp r0, r1
+ bne shmobile_smp_continue_gen2
+
+ mrc p15, 0, r1, c1, c0, 0 @ r1 = SCTLR
+ and r0, r1, #SCTLR_MMU
+ cmp r0, #SCTLR_MMU
+ beq shmobile_smp_continue_gen2
+
+ ldr r0, rwtcsra
+ mov r1, #0
+ ldrb r1, [r0]
+ and r0, r1, #RWTCSRA_WOVF
+ cmp r0, #RWTCSRA_WOVF
+ bne shmobile_smp_continue_gen2
+
+ ldr r0, bootrom
+ bx r0
+
+shmobile_smp_continue_gen2:
+ ldr r1, shmobile_boot_fn_gen2
+ bx r1
+
+ENDPROC(shmobile_boot_vector_gen2)
+
+ .align 4
+rwtcsra:
+ .word RWTCSRA_ADDRESS
+bootrom:
+ .word BOOTROM_ADDRESS
+ .globl shmobile_boot_cpu_gen2
+shmobile_boot_cpu_gen2:
+ .word 0x00000000
+
+ .align 2
+ .globl shmobile_boot_fn_gen2
+shmobile_boot_fn_gen2:
+ .space 4
+ .globl shmobile_boot_size_gen2
+shmobile_boot_size_gen2:
+ .long . - shmobile_boot_vector_gen2
+#endif /* CONFIG_ARCH_RCAR_GEN2 */
+
/*
* Per-CPU SMP boot function/argument selection code based on MPIDR
*/
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 4422b615a6ee..ba732effc90b 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -191,6 +191,7 @@ static void __init shmobile_smp_apmu_setup_boot(void)
{
/* install boot code shared by all CPUs */
shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
+ shmobile_boot_fn_gen2 = shmobile_boot_fn;
}
void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index e5f215c8b218..5a798b406af0 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -17,6 +17,7 @@
#include <linux/smp.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/io.h>
+#include <asm/cputype.h>
#include "common.h"
#include "rcar-gen2.h"
@@ -37,7 +38,6 @@
#define CA7RESCNT_CODE 0x5a5a0000
#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
-
/* On-chip RAM */
#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
@@ -119,8 +119,17 @@ map:
p = ioremap(res.start, resource_size(&res));
if (!p)
return;
-
- memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+ /*
+ * install the reset vector, use the largest version if we have enough
+ * memory available
+ */
+ if (resource_size(&res) >= shmobile_boot_size_gen2) {
+ shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
+ memcpy_toio(p, shmobile_boot_vector_gen2,
+ shmobile_boot_size_gen2);
+ } else {
+ memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+ }
iounmap(p);
/* setup reset vectors */
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index 44438f344dc8..93f628acfd94 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -1,9 +1,9 @@
/*
* R-Car Generation 2 da9063/da9210 regulator quirk
*
- * The r8a7790/lager and r8a7791/koelsch development boards have da9063 and
- * da9210 regulators. Both regulators have their interrupt request lines tied
- * to the same interrupt pin (IRQ2) on the SoC.
+ * Certain Gen2 development boards have an da9063 and one or more da9210
+ * regulators. All of these regulators have their interrupt request lines
+ * tied to the same interrupt pin (IRQ2) on the SoC.
*
* After cold boot or da9063-induced restart, both the da9063 and da9210 seem
* to assert their interrupt request lines. Hence as soon as one driver
@@ -50,7 +50,7 @@ static void __iomem *irqc;
static u8 da9063_irq_clr[] = { DA9063_REG_IRQ_MASK_A, 0xff, 0xff, 0xff, 0xff };
static u8 da9210_irq_clr[] = { DA9210_REG_MASK_A, 0xff, 0xff };
-static struct i2c_msg da9xxx_msgs[2] = {
+static struct i2c_msg da9xxx_msgs[3] = {
{
.addr = 0x58,
.len = ARRAY_SIZE(da9063_irq_clr),
@@ -59,6 +59,10 @@ static struct i2c_msg da9xxx_msgs[2] = {
.addr = 0x68,
.len = ARRAY_SIZE(da9210_irq_clr),
.buf = da9210_irq_clr,
+ }, {
+ .addr = 0x70,
+ .len = ARRAY_SIZE(da9210_irq_clr),
+ .buf = da9210_irq_clr,
},
};
@@ -85,12 +89,16 @@ static int regulator_quirk_notify(struct notifier_block *nb,
dev_dbg(dev, "Detected %s\n", client->name);
if ((client->addr == 0x58 && !strcmp(client->name, "da9063")) ||
- (client->addr == 0x68 && !strcmp(client->name, "da9210"))) {
- int ret;
+ (client->addr == 0x68 && !strcmp(client->name, "da9210")) ||
+ (client->addr == 0x70 && !strcmp(client->name, "da9210"))) {
+ int ret, len;
+
+ /* There are two DA9210 on Stout, one on the other boards. */
+ len = of_machine_is_compatible("renesas,stout") ? 3 : 2;
dev_info(&client->dev, "clearing da9063/da9210 interrupts\n");
- ret = i2c_transfer(client->adapter, da9xxx_msgs, ARRAY_SIZE(da9xxx_msgs));
- if (ret != ARRAY_SIZE(da9xxx_msgs))
+ ret = i2c_transfer(client->adapter, da9xxx_msgs, len);
+ if (ret != len)
dev_err(&client->dev, "i2c error %d\n", ret);
}
@@ -118,6 +126,7 @@ static int __init rcar_gen2_regulator_quirk(void)
if (!of_machine_is_compatible("renesas,koelsch") &&
!of_machine_is_compatible("renesas,lager") &&
+ !of_machine_is_compatible("renesas,stout") &&
!of_machine_is_compatible("renesas,gose"))
return -ENODEV;
diff --git a/arch/arm/mach-socfpga/pm.c b/arch/arm/mach-socfpga/pm.c
index c378ab0c2431..d4866788702c 100644
--- a/arch/arm/mach-socfpga/pm.c
+++ b/arch/arm/mach-socfpga/pm.c
@@ -116,7 +116,6 @@ static int socfpga_pm_suspend(unsigned long arg)
static int socfpga_pm_enter(suspend_state_t state)
{
switch (state) {
- case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
outer_disable();
cpu_suspend(0, socfpga_pm_suspend);
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 0d1889bbde58..713c068b953f 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -1,8 +1,10 @@
-config ARCH_STM32
- bool "STMicrolectronics STM32"
- depends on ARM_SINGLE_ARMV7M
+menuconfig ARCH_STM32
+ bool "STMicroelectronics STM32 family" if ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
+ select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
+ select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
+ select ARM_GIC if ARCH_MULTI_V7
+ select ARM_PSCI if ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
- select ARMV7M_SYSTICK
select CLKSRC_STM32
select PINCTRL
select RESET_CONTROLLER
@@ -10,22 +12,42 @@ config ARCH_STM32
help
Support for STMicroelectronics STM32 processors.
+if ARCH_STM32
+
+if ARM_SINGLE_ARMV7M
+
config MACH_STM32F429
- bool "STMicrolectronics STM32F429"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32F429"
+ select ARM_AMBA
default y
config MACH_STM32F469
- bool "STMicrolectronics STM32F469"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32F469"
+ select ARM_AMBA
default y
config MACH_STM32F746
- bool "STMicrolectronics STM32F746"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32F746"
+ select ARM_AMBA
+ default y
+
+config MACH_STM32F769
+ bool "STMicroelectronics STM32F769"
+ select ARM_AMBA
default y
config MACH_STM32H743
- bool "STMicrolectronics STM32H743"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32H743"
+ default y
+
+endif # ARMv7-M
+
+if ARCH_MULTI_V7
+
+config MACH_STM32MP157
+ bool "STMicroelectronics STM32MP157"
default y
+
+endif # ARMv7-A
+
+endif
diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index e918686e4191..011d57b488c2 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -1,22 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
+ * Copyright (C) STMicroelectronics 2017
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
- * License terms: GNU General Public License (GPL), version 2
*/
#include <linux/kernel.h>
-#include <asm/v7m.h>
#include <asm/mach/arch.h>
+#ifdef CONFIG_ARM_SINGLE_ARMV7M
+#include <asm/v7m.h>
+#endif
static const char *const stm32_compat[] __initconst = {
"st,stm32f429",
"st,stm32f469",
"st,stm32f746",
+ "st,stm32f769",
"st,stm32h743",
+ "st,stm32mp157",
NULL
};
DT_MACHINE_START(STM32DT, "STM32 (Device Tree Support)")
.dt_compat = stm32_compat,
+#ifdef CONFIG_ARM_SINGLE_ARMV7M
.restart = armv7m_restart,
+#endif
MACHINE_END
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 58153cdf025b..ce53ceaf4cc5 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -48,4 +48,11 @@ config MACH_SUN9I
default ARCH_SUNXI
select ARM_GIC
+config ARCH_SUNXI_MC_SMP
+ bool
+ depends on SMP
+ default MACH_SUN9I
+ select ARM_CCI400_PORT_CTRL
+ select ARM_CPU_SUSPEND
+
endif
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 27b168f121a1..7de9cc286d53 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,2 +1,5 @@
+CFLAGS_mc_smp.o += -march=armv7-a
+
obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
new file mode 100644
index 000000000000..c0246ec54a0a
--- /dev/null
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -0,0 +1,856 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * arch/arm/mach-sunxi/mc_smp.c
+ *
+ * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
+ * arch/arm/mach-hisi/platmcpm.c
+ * Cluster cache enable trampoline code adapted from MCPM framework
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/cpu_pm.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/cputype.h>
+#include <asm/idmap.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
+
+#define SUNXI_CPUS_PER_CLUSTER 4
+#define SUNXI_NR_CLUSTERS 2
+
+#define POLL_USEC 100
+#define TIMEOUT_USEC 100000
+
+#define CPUCFG_CX_CTRL_REG0(c) (0x10 * (c))
+#define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n) BIT(n)
+#define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL 0xf
+#define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7 BIT(4)
+#define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15 BIT(0)
+#define CPUCFG_CX_CTRL_REG1(c) (0x10 * (c) + 0x4)
+#define CPUCFG_CX_CTRL_REG1_ACINACTM BIT(0)
+#define CPUCFG_CX_STATUS(c) (0x30 + 0x4 * (c))
+#define CPUCFG_CX_STATUS_STANDBYWFI(n) BIT(16 + (n))
+#define CPUCFG_CX_STATUS_STANDBYWFIL2 BIT(0)
+#define CPUCFG_CX_RST_CTRL(c) (0x80 + 0x4 * (c))
+#define CPUCFG_CX_RST_CTRL_DBG_SOC_RST BIT(24)
+#define CPUCFG_CX_RST_CTRL_ETM_RST(n) BIT(20 + (n))
+#define CPUCFG_CX_RST_CTRL_ETM_RST_ALL (0xf << 20)
+#define CPUCFG_CX_RST_CTRL_DBG_RST(n) BIT(16 + (n))
+#define CPUCFG_CX_RST_CTRL_DBG_RST_ALL (0xf << 16)
+#define CPUCFG_CX_RST_CTRL_H_RST BIT(12)
+#define CPUCFG_CX_RST_CTRL_L2_RST BIT(8)
+#define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n))
+#define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+
+#define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c))
+#define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n)
+#define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf
+#define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c))
+#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
+#define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu))
+#define PRCM_CPU_SOFT_ENTRY_REG 0x164
+
+#define CPU0_SUPPORT_HOTPLUG_MAGIC0 0xFA50392F
+#define CPU0_SUPPORT_HOTPLUG_MAGIC1 0x790DCA3A
+
+static void __iomem *cpucfg_base;
+static void __iomem *prcm_base;
+static void __iomem *sram_b_smp_base;
+
+static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
+{
+ struct device_node *node;
+ int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
+
+ node = of_cpu_device_node_get(cpu);
+
+ /* In case of_cpu_device_node_get fails */
+ if (!node)
+ node = of_get_cpu_node(cpu, NULL);
+
+ if (!node) {
+ /*
+ * There's no point in returning an error, since we
+ * would be mid way in a core or cluster power sequence.
+ */
+ pr_err("%s: Couldn't get CPU cluster %u core %u device node\n",
+ __func__, cluster, core);
+
+ return false;
+ }
+
+ return of_device_is_compatible(node, "arm,cortex-a15");
+}
+
+static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ u32 reg;
+
+ /* control sequence from Allwinner A80 user manual v1.2 PRCM section */
+ reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ if (enable) {
+ if (reg == 0x00) {
+ pr_debug("power clamp for cluster %u cpu %u already open\n",
+ cluster, cpu);
+ return 0;
+ }
+
+ writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ udelay(10);
+ writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ udelay(10);
+ writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ udelay(10);
+ writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ udelay(10);
+ writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ udelay(10);
+ } else {
+ writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
+ udelay(10);
+ }
+
+ return 0;
+}
+
+static void sunxi_cpu0_hotplug_support_set(bool enable)
+{
+ if (enable) {
+ writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
+ writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
+ } else {
+ writel(0x0, sram_b_smp_base);
+ writel(0x0, sram_b_smp_base + 0x4);
+ }
+}
+
+static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
+{
+ u32 reg;
+
+ pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
+ if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
+ return -EINVAL;
+
+ /* Set hotplug support magic flags for cpu0 */
+ if (cluster == 0 && cpu == 0)
+ sunxi_cpu0_hotplug_support_set(true);
+
+ /* assert processor power-on reset */
+ reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+ reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
+ writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+
+ /* Cortex-A7: hold L1 reset disable signal low */
+ if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
+ reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
+ reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu);
+ writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
+ }
+
+ /* assert processor related resets */
+ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+ reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
+
+ /*
+ * Allwinner code also asserts resets for NEON on A15. According
+ * to ARM manuals, asserting power-on reset is sufficient.
+ */
+ if (!sunxi_core_is_cortex_a15(cpu, cluster))
+ reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
+
+ writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+
+ /* open power switch */
+ sunxi_cpu_power_switch_set(cpu, cluster, true);
+
+ /* clear processor power gate */
+ reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
+ writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ udelay(20);
+
+ /* de-assert processor power-on reset */
+ reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+ reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
+ writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+
+ /* de-assert all processor resets */
+ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+ reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
+ reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu);
+ if (!sunxi_core_is_cortex_a15(cpu, cluster))
+ reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
+ else
+ reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu); /* NEON */
+ writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+
+ return 0;
+}
+
+static int sunxi_cluster_powerup(unsigned int cluster)
+{
+ u32 reg;
+
+ pr_debug("%s: cluster %u\n", __func__, cluster);
+ if (cluster >= SUNXI_NR_CLUSTERS)
+ return -EINVAL;
+
+ /* assert ACINACTM */
+ reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
+ reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
+ writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
+
+ /* assert cluster processor power-on resets */
+ reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+ reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
+ writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
+
+ /* assert cluster resets */
+ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+ reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
+ reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL;
+ reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
+ reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
+
+ /*
+ * Allwinner code also asserts resets for NEON on A15. According
+ * to ARM manuals, asserting power-on reset is sufficient.
+ */
+ if (!sunxi_core_is_cortex_a15(0, cluster))
+ reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL;
+
+ writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+
+ /* hold L1/L2 reset disable signals low */
+ reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
+ if (sunxi_core_is_cortex_a15(0, cluster)) {
+ /* Cortex-A15: hold L2RSTDISABLE low */
+ reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15;
+ } else {
+ /* Cortex-A7: hold L1RSTDISABLE and L2RSTDISABLE low */
+ reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL;
+ reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7;
+ }
+ writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
+
+ /* clear cluster power gate */
+ reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+ writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ udelay(20);
+
+ /* de-assert cluster resets */
+ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+ reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
+ reg |= CPUCFG_CX_RST_CTRL_H_RST;
+ reg |= CPUCFG_CX_RST_CTRL_L2_RST;
+ writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+
+ /* de-assert ACINACTM */
+ reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
+ reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM;
+ writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
+
+ return 0;
+}
+
+/*
+ * This bit is shared between the initial nocache_trampoline call to
+ * enable CCI-400 and proper cluster cache disable before power down.
+ */
+static void sunxi_cluster_cache_disable_without_axi(void)
+{
+ if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
+ /*
+ * On the Cortex-A15 we need to disable
+ * L2 prefetching before flushing the cache.
+ */
+ asm volatile(
+ "mcr p15, 1, %0, c15, c0, 3\n"
+ "isb\n"
+ "dsb"
+ : : "r" (0x400));
+ }
+
+ /* Flush all cache levels for this cluster. */
+ v7_exit_coherency_flush(all);
+
+ /*
+ * Disable cluster-level coherency by masking
+ * incoming snoops and DVM messages:
+ */
+ cci_disable_port_by_cpu(read_cpuid_mpidr());
+}
+
+static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
+static int sunxi_mc_smp_first_comer;
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ *
+ * Also enable regional clock gating and L2 data latency settings for
+ * Cortex-A15. These settings are from the vendor kernel.
+ */
+static void __naked sunxi_mc_smp_cluster_cache_enable(void)
+{
+ asm volatile (
+ "mrc p15, 0, r1, c0, c0, 0\n"
+ "movw r2, #" __stringify(ARM_CPU_PART_MASK & 0xffff) "\n"
+ "movt r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
+ "and r1, r1, r2\n"
+ "movw r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xffff) "\n"
+ "movt r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
+ "cmp r1, r2\n"
+ "bne not_a15\n"
+
+ /* The following is Cortex-A15 specific */
+
+ /* ACTLR2: Enable CPU regional clock gates */
+ "mrc p15, 1, r1, c15, c0, 4\n"
+ "orr r1, r1, #(0x1<<31)\n"
+ "mcr p15, 1, r1, c15, c0, 4\n"
+
+ /* L2ACTLR */
+ "mrc p15, 1, r1, c15, c0, 0\n"
+ /* Enable L2, GIC, and Timer regional clock gates */
+ "orr r1, r1, #(0x1<<26)\n"
+ /* Disable clean/evict from being pushed to external */
+ "orr r1, r1, #(0x1<<3)\n"
+ "mcr p15, 1, r1, c15, c0, 0\n"
+
+ /* L2CTRL: L2 data RAM latency */
+ "mrc p15, 1, r1, c9, c0, 2\n"
+ "bic r1, r1, #(0x7<<0)\n"
+ "orr r1, r1, #(0x3<<0)\n"
+ "mcr p15, 1, r1, c9, c0, 2\n"
+
+ /* End of Cortex-A15 specific setup */
+ "not_a15:\n"
+
+ /* Get value of sunxi_mc_smp_first_comer */
+ "adr r1, first\n"
+ "ldr r0, [r1]\n"
+ "ldr r0, [r1, r0]\n"
+
+ /* Skip cci_enable_port_for_self if not first comer */
+ "cmp r0, #0\n"
+ "bxeq lr\n"
+ "b cci_enable_port_for_self\n"
+
+ ".align 2\n"
+ "first: .word sunxi_mc_smp_first_comer - .\n"
+ );
+}
+
+static void __naked sunxi_mc_smp_secondary_startup(void)
+{
+ asm volatile(
+ "bl sunxi_mc_smp_cluster_cache_enable\n"
+ "b secondary_startup"
+ /* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
+ :: "i" (sunxi_mc_smp_cluster_cache_enable)
+ );
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
+{
+ int i;
+
+ for (i = 0; i < SUNXI_CPUS_PER_CLUSTER; i++)
+ if (sunxi_mc_smp_cpu_table[cluster][i])
+ return false;
+ return true;
+}
+
+static void sunxi_mc_smp_secondary_init(unsigned int cpu)
+{
+ /* Clear hotplug support magic flags for cpu0 */
+ if (cpu == 0)
+ sunxi_cpu0_hotplug_support_set(false);
+}
+
+static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ if (!cpucfg_base)
+ return -ENODEV;
+ if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
+ return -EINVAL;
+
+ spin_lock_irq(&boot_lock);
+
+ if (sunxi_mc_smp_cpu_table[cluster][cpu])
+ goto out;
+
+ if (sunxi_mc_smp_cluster_is_down(cluster)) {
+ sunxi_mc_smp_first_comer = true;
+ sunxi_cluster_powerup(cluster);
+ } else {
+ sunxi_mc_smp_first_comer = false;
+ }
+
+ /* This is read by incoming CPUs with their cache and MMU disabled */
+ sync_cache_w(&sunxi_mc_smp_first_comer);
+ sunxi_cpu_powerup(cpu, cluster);
+
+out:
+ sunxi_mc_smp_cpu_table[cluster][cpu]++;
+ spin_unlock_irq(&boot_lock);
+
+ return 0;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void sunxi_cluster_cache_disable(void)
+{
+ unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+ u32 reg;
+
+ pr_debug("%s: cluster %u\n", __func__, cluster);
+
+ sunxi_cluster_cache_disable_without_axi();
+
+ /* last man standing, assert ACINACTM */
+ reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
+ reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
+ writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
+}
+
+static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
+
+ spin_lock(&boot_lock);
+ sunxi_mc_smp_cpu_table[cluster][cpu]--;
+ if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
+ /* A power_up request went ahead of us. */
+ pr_debug("%s: aborting due to a power up request\n",
+ __func__);
+ spin_unlock(&boot_lock);
+ return;
+ } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
+ pr_err("Cluster %d CPU%d boots multiple times\n",
+ cluster, cpu);
+ BUG();
+ }
+
+ last_man = sunxi_mc_smp_cluster_is_down(cluster);
+ spin_unlock(&boot_lock);
+
+ gic_cpu_if_down(0);
+ if (last_man)
+ sunxi_cluster_cache_disable();
+ else
+ v7_exit_coherency_flush(louis);
+
+ for (;;)
+ wfi();
+}
+
+static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
+{
+ u32 reg;
+
+ pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
+ if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
+ return -EINVAL;
+
+ /* gate processor power */
+ reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ reg |= PRCM_PWROFF_GATING_REG_CORE(cpu);
+ writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ udelay(20);
+
+ /* close power switch */
+ sunxi_cpu_power_switch_set(cpu, cluster, false);
+
+ return 0;
+}
+
+static int sunxi_cluster_powerdown(unsigned int cluster)
+{
+ u32 reg;
+
+ pr_debug("%s: cluster %u\n", __func__, cluster);
+ if (cluster >= SUNXI_NR_CLUSTERS)
+ return -EINVAL;
+
+ /* assert cluster resets or system will hang */
+ pr_debug("%s: assert cluster reset\n", __func__);
+ reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+ reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
+ reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
+ reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
+ writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+
+ /* gate cluster power */
+ pr_debug("%s: gate cluster power\n", __func__);
+ reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+ writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
+ udelay(20);
+
+ return 0;
+}
+
+static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
+{
+ unsigned int mpidr, cpu, cluster;
+ unsigned int tries, count;
+ int ret = 0;
+ u32 reg;
+
+ mpidr = cpu_logical_map(l_cpu);
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ /* This should never happen */
+ if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS ||
+ cpu >= SUNXI_CPUS_PER_CLUSTER))
+ return 0;
+
+ /* wait for CPU core to die and enter WFI */
+ count = TIMEOUT_USEC / POLL_USEC;
+ spin_lock_irq(&boot_lock);
+ for (tries = 0; tries < count; tries++) {
+ spin_unlock_irq(&boot_lock);
+ usleep_range(POLL_USEC / 2, POLL_USEC);
+ spin_lock_irq(&boot_lock);
+
+ /*
+ * If the user turns off a bunch of cores at the same
+ * time, the kernel might call cpu_kill before some of
+ * them are ready. This is because boot_lock serializes
+ * both cpu_die and cpu_kill callbacks. Either one could
+ * run first. We should wait for cpu_die to complete.
+ */
+ if (sunxi_mc_smp_cpu_table[cluster][cpu])
+ continue;
+
+ reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster));
+ if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu))
+ break;
+ }
+
+ if (tries >= count) {
+ ret = ETIMEDOUT;
+ goto out;
+ }
+
+ /* power down CPU core */
+ sunxi_cpu_powerdown(cpu, cluster);
+
+ if (!sunxi_mc_smp_cluster_is_down(cluster))
+ goto out;
+
+ /* wait for cluster L2 WFI */
+ ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg,
+ reg & CPUCFG_CX_STATUS_STANDBYWFIL2,
+ POLL_USEC, TIMEOUT_USEC);
+ if (ret) {
+ /*
+ * Ignore timeout on the cluster. Leaving the cluster on
+ * will not affect system execution, just use a bit more
+ * power. But returning an error here will only confuse
+ * the user as the CPU has already been shutdown.
+ */
+ ret = 0;
+ goto out;
+ }
+
+ /* Power down cluster */
+ sunxi_cluster_powerdown(cluster);
+
+out:
+ spin_unlock_irq(&boot_lock);
+ pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
+ __func__, cluster, cpu, ret);
+ return !ret;
+}
+
+static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
+{
+ return true;
+}
+#endif
+
+static const struct smp_operations sunxi_mc_smp_smp_ops __initconst = {
+ .smp_secondary_init = sunxi_mc_smp_secondary_init,
+ .smp_boot_secondary = sunxi_mc_smp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = sunxi_mc_smp_cpu_die,
+ .cpu_kill = sunxi_mc_smp_cpu_kill,
+ .cpu_can_disable = sunxi_mc_smp_cpu_can_disable,
+#endif
+};
+
+static bool __init sunxi_mc_smp_cpu_table_init(void)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) {
+ pr_err("%s: boot CPU is out of bounds!\n", __func__);
+ return false;
+ }
+ sunxi_mc_smp_cpu_table[cluster][cpu] = 1;
+ return true;
+}
+
+/*
+ * Adapted from arch/arm/common/mc_smp_entry.c
+ *
+ * We need the trampoline code to enable CCI-400 on the first cluster
+ */
+typedef typeof(cpu_reset) phys_reset_t;
+
+static void __init __naked sunxi_mc_smp_resume(void)
+{
+ asm volatile(
+ "bl sunxi_mc_smp_cluster_cache_enable\n"
+ "b cpu_resume"
+ /* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
+ :: "i" (sunxi_mc_smp_cluster_cache_enable)
+ );
+}
+
+static int __init nocache_trampoline(unsigned long __unused)
+{
+ phys_reset_t phys_reset;
+
+ setup_mm_for_reboot();
+ sunxi_cluster_cache_disable_without_axi();
+
+ phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+ phys_reset(__pa_symbol(sunxi_mc_smp_resume), false);
+ BUG();
+}
+
+static int __init sunxi_mc_smp_loopback(void)
+{
+ int ret;
+
+ /*
+ * We're going to soft-restart the current CPU through the
+ * low-level MCPM code by leveraging the suspend/resume
+ * infrastructure. Let's play it safe by using cpu_pm_enter()
+ * in case the CPU init code path resets the VFP or similar.
+ */
+ sunxi_mc_smp_first_comer = true;
+ local_irq_disable();
+ local_fiq_disable();
+ ret = cpu_pm_enter();
+ if (!ret) {
+ ret = cpu_suspend(0, nocache_trampoline);
+ cpu_pm_exit();
+ }
+ local_fiq_enable();
+ local_irq_enable();
+ sunxi_mc_smp_first_comer = false;
+
+ return ret;
+}
+
+/*
+ * This holds any device nodes that we requested resources for,
+ * so that we may easily release resources in the error path.
+ */
+struct sunxi_mc_smp_nodes {
+ struct device_node *prcm_node;
+ struct device_node *cpucfg_node;
+ struct device_node *sram_node;
+};
+
+/* This structure holds SoC-specific bits tied to an enable-method string. */
+struct sunxi_mc_smp_data {
+ const char *enable_method;
+ int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+};
+
+static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
+{
+ of_node_put(nodes->prcm_node);
+ of_node_put(nodes->cpucfg_node);
+ of_node_put(nodes->sram_node);
+ memset(nodes, 0, sizeof(*nodes));
+}
+
+static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
+{
+ nodes->prcm_node = of_find_compatible_node(NULL, NULL,
+ "allwinner,sun9i-a80-prcm");
+ if (!nodes->prcm_node) {
+ pr_err("%s: PRCM not available\n", __func__);
+ return -ENODEV;
+ }
+
+ nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
+ "allwinner,sun9i-a80-cpucfg");
+ if (!nodes->cpucfg_node) {
+ pr_err("%s: CPUCFG not available\n", __func__);
+ return -ENODEV;
+ }
+
+ nodes->sram_node = of_find_compatible_node(NULL, NULL,
+ "allwinner,sun9i-a80-smp-sram");
+ if (!nodes->sram_node) {
+ pr_err("%s: Secure SRAM not available\n", __func__);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
+ {
+ .enable_method = "allwinner,sun9i-a80-smp",
+ .get_smp_nodes = sun9i_a80_get_smp_nodes,
+ },
+};
+
+static int __init sunxi_mc_smp_init(void)
+{
+ struct sunxi_mc_smp_nodes nodes = { 0 };
+ struct device_node *node;
+ struct resource res;
+ int i, ret;
+
+ /*
+ * Don't bother checking the "cpus" node, as an enable-method
+ * property in that node is undocumented.
+ */
+ node = of_cpu_device_node_get(0);
+ if (!node)
+ return -ENODEV;
+
+ /*
+ * We can't actually use the enable-method magic in the kernel.
+ * Our loopback / trampoline code uses the CPU suspend framework,
+ * which requires the identity mapping be available. It would not
+ * yet be available if we used the .init_cpus or .prepare_cpus
+ * callbacks in smp_operations, which we would use if we were to
+ * use CPU_METHOD_OF_DECLARE
+ */
+ for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) {
+ ret = of_property_match_string(node, "enable-method",
+ sunxi_mc_smp_data[i].enable_method);
+ if (!ret)
+ break;
+ }
+
+ of_node_put(node);
+ if (ret)
+ return -ENODEV;
+
+ if (!sunxi_mc_smp_cpu_table_init())
+ return -EINVAL;
+
+ if (!cci_probed()) {
+ pr_err("%s: CCI-400 not available\n", __func__);
+ return -ENODEV;
+ }
+
+ /* Get needed device tree nodes */
+ ret = sunxi_mc_smp_data[i].get_smp_nodes(&nodes);
+ if (ret)
+ goto err_put_nodes;
+
+ /*
+ * Unfortunately we can not request the I/O region for the PRCM.
+ * It is shared with the PRCM clock.
+ */
+ prcm_base = of_iomap(nodes.prcm_node, 0);
+ if (!prcm_base) {
+ pr_err("%s: failed to map PRCM registers\n", __func__);
+ ret = -ENOMEM;
+ goto err_put_nodes;
+ }
+
+ cpucfg_base = of_io_request_and_map(nodes.cpucfg_node, 0,
+ "sunxi-mc-smp");
+ if (IS_ERR(cpucfg_base)) {
+ ret = PTR_ERR(cpucfg_base);
+ pr_err("%s: failed to map CPUCFG registers: %d\n",
+ __func__, ret);
+ goto err_unmap_prcm;
+ }
+
+ sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
+ "sunxi-mc-smp");
+ if (IS_ERR(sram_b_smp_base)) {
+ ret = PTR_ERR(sram_b_smp_base);
+ pr_err("%s: failed to map secure SRAM\n", __func__);
+ goto err_unmap_release_cpucfg;
+ }
+
+ /* Configure CCI-400 for boot cluster */
+ ret = sunxi_mc_smp_loopback();
+ if (ret) {
+ pr_err("%s: failed to configure boot cluster: %d\n",
+ __func__, ret);
+ goto err_unmap_release_secure_sram;
+ }
+
+ /* We don't need the device nodes anymore */
+ sunxi_mc_smp_put_nodes(&nodes);
+
+ /* Set the hardware entry point address */
+ writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
+ prcm_base + PRCM_CPU_SOFT_ENTRY_REG);
+
+ /* Actually enable multi cluster SMP */
+ smp_set_ops(&sunxi_mc_smp_smp_ops);
+
+ pr_info("sunxi multi cluster SMP support installed\n");
+
+ return 0;
+
+err_unmap_release_secure_sram:
+ iounmap(sram_b_smp_base);
+ of_address_to_resource(nodes.sram_node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+err_unmap_release_cpucfg:
+ iounmap(cpucfg_base);
+ of_address_to_resource(nodes.cpucfg_node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+err_unmap_prcm:
+ iounmap(prcm_base);
+err_put_nodes:
+ sunxi_mc_smp_put_nodes(&nodes);
+ return ret;
+}
+
+early_initcall(sunxi_mc_smp_init);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7e5d7a083707..36cd23c8be9b 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -133,6 +133,9 @@ static void __init u8500_init_machine(void)
if (of_machine_is_compatible("st-ericsson,u8540"))
of_platform_populate(NULL, u8500_local_bus_nodes,
u8540_auxdata_lookup, NULL);
+ else
+ of_platform_populate(NULL, u8500_local_bus_nodes,
+ NULL, NULL);
}
static const char * stericsson_dt_platform_compat[] = {
diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c
index 0a1e2280141f..afe5b4c7b164 100644
--- a/arch/arm/mm/cache-l2x0-pmu.c
+++ b/arch/arm/mm/cache-l2x0-pmu.c
@@ -293,7 +293,7 @@ static bool l2x0_pmu_group_is_valid(struct perf_event *event)
else if (!is_software_event(leader))
return false;
- list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(sibling, leader) {
if (sibling->pmu == pmu)
num_hw++;
else if (!is_software_event(sibling))
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 1267e64133b9..0224416cba3c 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -70,7 +70,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
void *kto = kmap_atomic(to);
if (!test_and_set_bit(PG_dcache_clean, &from->flags))
- __flush_dcache_page(page_mapping(from), from);
+ __flush_dcache_page(page_mapping_file(from), from);
raw_spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 70423345da26..a698e575e321 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -76,7 +76,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
unsigned long kfrom, kto;
if (!test_and_set_bit(PG_dcache_clean, &from->flags))
- __flush_dcache_page(page_mapping(from), from);
+ __flush_dcache_page(page_mapping_file(from), from);
/* FIXME: not highmem safe */
discard_old_kernel_data(page_address(to));
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 0fb85025344d..97972379f4d6 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -90,7 +90,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
void *kto = kmap_atomic(to);
if (!test_and_set_bit(PG_dcache_clean, &from->flags))
- __flush_dcache_page(page_mapping(from), from);
+ __flush_dcache_page(page_mapping_file(from), from);
raw_spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ada8eb206a90..8c398fedbbb6 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -466,6 +466,12 @@ void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
void __init dma_contiguous_remap(void)
{
int i;
+
+ if (!dma_mmu_remap_num)
+ return;
+
+ /* call flush_cache_all() since CMA area would be large enough */
+ flush_cache_all();
for (i = 0; i < dma_mmu_remap_num; i++) {
phys_addr_t start = dma_mmu_remap[i].base;
phys_addr_t end = start + dma_mmu_remap[i].size;
@@ -498,7 +504,15 @@ void __init dma_contiguous_remap(void)
flush_tlb_kernel_range(__phys_to_virt(start),
__phys_to_virt(end));
- iotable_init(&map, 1);
+ /*
+ * All the memory in CMA region will be on ZONE_MOVABLE.
+ * If that zone is considered as highmem, the memory in CMA
+ * region is also considered as highmem even if it's
+ * physical address belong to lowmem. In this case,
+ * re-mapping isn't required.
+ */
+ if (!is_highmem_idx(ZONE_MOVABLE))
+ iotable_init(&map, 1);
}
}
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index d9e0d00a6699..4d75dae5ac96 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -195,7 +195,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
if (page == ZERO_PAGE(0))
return;
- mapping = page_mapping(page);
+ mapping = page_mapping_file(page);
if (!test_and_set_bit(PG_dcache_clean, &page->flags))
__flush_dcache_page(mapping, page);
if (mapping) {
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index f1e6190aa7ea..58469623b015 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -285,7 +285,7 @@ void __sync_icache_dcache(pte_t pteval)
page = pfn_to_page(pfn);
if (cache_is_vipt_aliasing())
- mapping = page_mapping(page);
+ mapping = page_mapping_file(page);
else
mapping = NULL;
@@ -333,7 +333,7 @@ void flush_dcache_page(struct page *page)
return;
}
- mapping = page_mapping(page);
+ mapping = page_mapping_file(page);
if (!cache_ops_need_broadcast() &&
mapping && !page_mapcount(page))
@@ -363,7 +363,7 @@ void flush_kernel_dcache_page(struct page *page)
if (cache_is_vivt() || cache_is_vipt_aliasing()) {
struct address_space *mapping;
- mapping = page_mapping(page);
+ mapping = page_mapping_file(page);
if (!mapping || mapping_mapped(mapping)) {
void *addr;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index bd6f4513539a..c186474422f3 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -758,20 +758,9 @@ void set_kernel_text_ro(void)
static inline void fix_kernmem_perms(void) { }
#endif /* CONFIG_STRICT_KERNEL_RWX */
-void free_tcmmem(void)
-{
-#ifdef CONFIG_HAVE_TCM
- extern char __tcm_start, __tcm_end;
-
- poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
- free_reserved_area(&__tcm_start, &__tcm_end, -1, "TCM link");
-#endif
-}
-
void free_initmem(void)
{
fix_kernmem_perms();
- free_tcmmem();
poison_init_mem(__init_begin, __init_end - __init_begin);
if (!machine_is_integrator() && !machine_is_cintegrator())
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index eb1de66517d5..f866870db749 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -21,20 +21,20 @@
#define MIN_GAP (128*1024*1024UL)
#define MAX_GAP ((TASK_SIZE)/6*5)
-static int mmap_is_legacy(void)
+static int mmap_is_legacy(struct rlimit *rlim_stack)
{
if (current->personality & ADDR_COMPAT_LAYOUT)
return 1;
- if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
+ if (rlim_stack->rlim_cur == RLIM_INFINITY)
return 1;
return sysctl_legacy_va_layout;
}
-static unsigned long mmap_base(unsigned long rnd)
+static unsigned long mmap_base(unsigned long rnd, struct rlimit *rlim_stack)
{
- unsigned long gap = rlimit(RLIMIT_STACK);
+ unsigned long gap = rlim_stack->rlim_cur;
if (gap < MIN_GAP)
gap = MIN_GAP;
@@ -180,18 +180,18 @@ unsigned long arch_mmap_rnd(void)
return rnd << PAGE_SHIFT;
}
-void arch_pick_mmap_layout(struct mm_struct *mm)
+void arch_pick_mmap_layout(struct mm_struct *mm, struct rlimit *rlim_stack)
{
unsigned long random_factor = 0UL;
if (current->flags & PF_RANDOMIZE)
random_factor = arch_mmap_rnd();
- if (mmap_is_legacy()) {
+ if (mmap_is_legacy(rlim_stack)) {
mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
mm->get_unmapped_area = arch_get_unmapped_area;
} else {
- mm->mmap_base = mmap_base(random_factor);
+ mm->mmap_base = mmap_base(random_factor, rlim_stack);
mm->get_unmapped_area = arch_get_unmapped_area_topdown;
}
}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d55d493f9a1e..b528a15f460d 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -272,6 +272,7 @@ ENDPROC(cpu_pj4b_do_resume)
__v7_ca5mp_setup:
__v7_ca9mp_setup:
__v7_cr7mp_setup:
+__v7_cr8mp_setup:
mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
b 1f
__v7_ca7mp_setup:
@@ -642,6 +643,16 @@ __v7_cr7mp_proc_info:
.size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
/*
+ * ARM Ltd. Cortex R8 processor.
+ */
+ .type __v7_cr8mp_proc_info, #object
+__v7_cr8mp_proc_info:
+ .long 0x410fc180
+ .long 0xff0ffff0
+ __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
+ .size __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
+
+ /*
* ARM Ltd. Cortex A7 processor.
*/
.type __v7_ca7mp_proc_info, #object
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 7276afee30b3..afc1a1d4f7a5 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -106,12 +106,6 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
help
PPA routine service ID for setting L2 auxiliary control register.
-config OMAP_DM_TIMER
- bool "Use dual-mode timer"
- depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
- help
- Select this option if you want to use OMAP Dual-Mode timers.
-
config OMAP_SERIAL_WAKE
bool "Enable wake-up events for serial ports"
depends on ARCH_OMAP1 && OMAP_MUX
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 47e186729d44..7215ada707e4 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,5 +9,4 @@ obj-y := sram.o dma.o counter_32k.o
# omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
deleted file mode 100644
index d443e481c3e9..000000000000
--- a/arch/arm/plat-omap/dmtimer.c
+++ /dev/null
@@ -1,1003 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/dmtimer.c
- *
- * OMAP Dual-Mode Timers
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Tarun Kanti DebBarma <tarun.kanti@ti.com>
- * Thara Gopinath <thara@ti.com>
- *
- * dmtimer adaptation to platform_driver.
- *
- * Copyright (C) 2005 Nokia Corporation
- * OMAP2 support by Juha Yrjola
- * API improvements and OMAP2 clock framework support by Timo Teras
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/pm_runtime.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/dmtimer-omap.h>
-
-#include <plat/dmtimer.h>
-
-static u32 omap_reserved_systimers;
-static LIST_HEAD(omap_timer_list);
-static DEFINE_SPINLOCK(dm_timer_lock);
-
-enum {
- REQUEST_ANY = 0,
- REQUEST_BY_ID,
- REQUEST_BY_CAP,
- REQUEST_BY_NODE,
-};
-
-/**
- * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
- * @timer: timer pointer over which read operation to perform
- * @reg: lowest byte holds the register offset
- *
- * The posted mode bit is encoded in reg. Note that in posted mode write
- * pending bit must be checked. Otherwise a read of a non completed write
- * will produce an error.
- */
-static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
-{
- WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
- return __omap_dm_timer_read(timer, reg, timer->posted);
-}
-
-/**
- * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
- * @timer: timer pointer over which write operation is to perform
- * @reg: lowest byte holds the register offset
- * @value: data to write into the register
- *
- * The posted mode bit is encoded in reg. Note that in posted mode the write
- * pending bit must be checked. Otherwise a write on a register which has a
- * pending write will be lost.
- */
-static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
- u32 value)
-{
- WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
- __omap_dm_timer_write(timer, reg, value, timer->posted);
-}
-
-static void omap_timer_restore_context(struct omap_dm_timer *timer)
-{
- omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
- timer->context.twer);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
- timer->context.tcrr);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
- timer->context.tldr);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
- timer->context.tmar);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
- timer->context.tsicr);
- writel_relaxed(timer->context.tier, timer->irq_ena);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
- timer->context.tclr);
-}
-
-static int omap_dm_timer_reset(struct omap_dm_timer *timer)
-{
- u32 l, timeout = 100000;
-
- if (timer->revision != 1)
- return -EINVAL;
-
- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
-
- do {
- l = __omap_dm_timer_read(timer,
- OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
- } while (!l && timeout--);
-
- if (!timeout) {
- dev_err(&timer->pdev->dev, "Timer failed to reset\n");
- return -ETIMEDOUT;
- }
-
- /* Configure timer for smart-idle mode */
- l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
- l |= 0x2 << 0x3;
- __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
-
- timer->posted = 0;
-
- return 0;
-}
-
-static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
-{
- int ret;
- struct clk *parent;
-
- /*
- * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
- * do not call clk_get() for these devices.
- */
- if (!timer->fclk)
- return -ENODEV;
-
- parent = clk_get(&timer->pdev->dev, NULL);
- if (IS_ERR(parent))
- return -ENODEV;
-
- ret = clk_set_parent(timer->fclk, parent);
- if (ret < 0)
- pr_err("%s: failed to set parent\n", __func__);
-
- clk_put(parent);
-
- return ret;
-}
-
-static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
-{
- int rc;
-
- /*
- * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
- * do not call clk_get() for these devices.
- */
- if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
- timer->fclk = clk_get(&timer->pdev->dev, "fck");
- if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
- dev_err(&timer->pdev->dev, ": No fclk handle.\n");
- return -EINVAL;
- }
- }
-
- omap_dm_timer_enable(timer);
-
- if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
- rc = omap_dm_timer_reset(timer);
- if (rc) {
- omap_dm_timer_disable(timer);
- return rc;
- }
- }
-
- __omap_dm_timer_enable_posted(timer);
- omap_dm_timer_disable(timer);
-
- rc = omap_dm_timer_of_set_source(timer);
- if (rc == -ENODEV)
- return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
-
- return rc;
-}
-
-static inline u32 omap_dm_timer_reserved_systimer(int id)
-{
- return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
-}
-
-int omap_dm_timer_reserve_systimer(int id)
-{
- if (omap_dm_timer_reserved_systimer(id))
- return -ENODEV;
-
- omap_reserved_systimers |= (1 << (id - 1));
-
- return 0;
-}
-
-static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
-{
- struct omap_dm_timer *timer = NULL, *t;
- struct device_node *np = NULL;
- unsigned long flags;
- u32 cap = 0;
- int id = 0;
-
- switch (req_type) {
- case REQUEST_BY_ID:
- id = *(int *)data;
- break;
- case REQUEST_BY_CAP:
- cap = *(u32 *)data;
- break;
- case REQUEST_BY_NODE:
- np = (struct device_node *)data;
- break;
- default:
- /* REQUEST_ANY */
- break;
- }
-
- spin_lock_irqsave(&dm_timer_lock, flags);
- list_for_each_entry(t, &omap_timer_list, node) {
- if (t->reserved)
- continue;
-
- switch (req_type) {
- case REQUEST_BY_ID:
- if (id == t->pdev->id) {
- timer = t;
- timer->reserved = 1;
- goto found;
- }
- break;
- case REQUEST_BY_CAP:
- if (cap == (t->capability & cap)) {
- /*
- * If timer is not NULL, we have already found
- * one timer. But it was not an exact match
- * because it had more capabilities than what
- * was required. Therefore, unreserve the last
- * timer found and see if this one is a better
- * match.
- */
- if (timer)
- timer->reserved = 0;
- timer = t;
- timer->reserved = 1;
-
- /* Exit loop early if we find an exact match */
- if (t->capability == cap)
- goto found;
- }
- break;
- case REQUEST_BY_NODE:
- if (np == t->pdev->dev.of_node) {
- timer = t;
- timer->reserved = 1;
- goto found;
- }
- break;
- default:
- /* REQUEST_ANY */
- timer = t;
- timer->reserved = 1;
- goto found;
- }
- }
-found:
- spin_unlock_irqrestore(&dm_timer_lock, flags);
-
- if (timer && omap_dm_timer_prepare(timer)) {
- timer->reserved = 0;
- timer = NULL;
- }
-
- if (!timer)
- pr_debug("%s: timer request failed!\n", __func__);
-
- return timer;
-}
-
-struct omap_dm_timer *omap_dm_timer_request(void)
-{
- return _omap_dm_timer_request(REQUEST_ANY, NULL);
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request);
-
-struct omap_dm_timer *omap_dm_timer_request_specific(int id)
-{
- /* Requesting timer by ID is not supported when device tree is used */
- if (of_have_populated_dt()) {
- pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n",
- __func__);
- return NULL;
- }
-
- return _omap_dm_timer_request(REQUEST_BY_ID, &id);
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
-
-/**
- * omap_dm_timer_request_by_cap - Request a timer by capability
- * @cap: Bit mask of capabilities to match
- *
- * Find a timer based upon capabilities bit mask. Callers of this function
- * should use the definitions found in the plat/dmtimer.h file under the
- * comment "timer capabilities used in hwmod database". Returns pointer to
- * timer handle on success and a NULL pointer on failure.
- */
-struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
-{
- return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
-
-/**
- * omap_dm_timer_request_by_node - Request a timer by device-tree node
- * @np: Pointer to device-tree timer node
- *
- * Request a timer based upon a device node pointer. Returns pointer to
- * timer handle on success and a NULL pointer on failure.
- */
-struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
-{
- if (!np)
- return NULL;
-
- return _omap_dm_timer_request(REQUEST_BY_NODE, np);
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_node);
-
-int omap_dm_timer_free(struct omap_dm_timer *timer)
-{
- if (unlikely(!timer))
- return -EINVAL;
-
- clk_put(timer->fclk);
-
- WARN_ON(!timer->reserved);
- timer->reserved = 0;
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_free);
-
-void omap_dm_timer_enable(struct omap_dm_timer *timer)
-{
- int c;
-
- pm_runtime_get_sync(&timer->pdev->dev);
-
- if (!(timer->capability & OMAP_TIMER_ALWON)) {
- if (timer->get_context_loss_count) {
- c = timer->get_context_loss_count(&timer->pdev->dev);
- if (c != timer->ctx_loss_count) {
- omap_timer_restore_context(timer);
- timer->ctx_loss_count = c;
- }
- } else {
- omap_timer_restore_context(timer);
- }
- }
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
-
-void omap_dm_timer_disable(struct omap_dm_timer *timer)
-{
- pm_runtime_put_sync(&timer->pdev->dev);
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
-
-int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
-{
- if (timer)
- return timer->irq;
- return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
-
-#if defined(CONFIG_ARCH_OMAP1)
-#include <mach/hardware.h>
-/**
- * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
- * @inputmask: current value of idlect mask
- */
-__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
-{
- int i = 0;
- struct omap_dm_timer *timer = NULL;
- unsigned long flags;
-
- /* If ARMXOR cannot be idled this function call is unnecessary */
- if (!(inputmask & (1 << 1)))
- return inputmask;
-
- /* If any active timer is using ARMXOR return modified mask */
- spin_lock_irqsave(&dm_timer_lock, flags);
- list_for_each_entry(timer, &omap_timer_list, node) {
- u32 l;
-
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- if (l & OMAP_TIMER_CTRL_ST) {
- if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
- inputmask &= ~(1 << 1);
- else
- inputmask &= ~(1 << 2);
- }
- i++;
- }
- spin_unlock_irqrestore(&dm_timer_lock, flags);
-
- return inputmask;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
-
-#else
-
-struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
-{
- if (timer && !IS_ERR(timer->fclk))
- return timer->fclk;
- return NULL;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
-
-__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
-{
- BUG();
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
-
-#endif
-
-int omap_dm_timer_trigger(struct omap_dm_timer *timer)
-{
- if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- pr_err("%s: timer not available or enabled.\n", __func__);
- return -EINVAL;
- }
-
- omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
-
-int omap_dm_timer_start(struct omap_dm_timer *timer)
-{
- u32 l;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
-
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- if (!(l & OMAP_TIMER_CTRL_ST)) {
- l |= OMAP_TIMER_CTRL_ST;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- }
-
- /* Save the context */
- timer->context.tclr = l;
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_start);
-
-int omap_dm_timer_stop(struct omap_dm_timer *timer)
-{
- unsigned long rate = 0;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
- rate = clk_get_rate(timer->fclk);
-
- __omap_dm_timer_stop(timer, timer->posted, rate);
-
- /*
- * Since the register values are computed and written within
- * __omap_dm_timer_stop, we need to use read to retrieve the
- * context.
- */
- timer->context.tclr =
- omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
-
-int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
-{
- int ret;
- char *parent_name = NULL;
- struct clk *parent;
- struct dmtimer_platform_data *pdata;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- pdata = timer->pdev->dev.platform_data;
-
- if (source < 0 || source >= 3)
- return -EINVAL;
-
- /*
- * FIXME: Used for OMAP1 devices only because they do not currently
- * use the clock framework to set the parent clock. To be removed
- * once OMAP1 migrated to using clock framework for dmtimers
- */
- if (pdata && pdata->set_timer_src)
- return pdata->set_timer_src(timer->pdev, source);
-
- if (IS_ERR(timer->fclk))
- return -EINVAL;
-
-#if defined(CONFIG_COMMON_CLK)
- /* Check if the clock has configurable parents */
- if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
- return 0;
-#endif
-
- switch (source) {
- case OMAP_TIMER_SRC_SYS_CLK:
- parent_name = "timer_sys_ck";
- break;
-
- case OMAP_TIMER_SRC_32_KHZ:
- parent_name = "timer_32k_ck";
- break;
-
- case OMAP_TIMER_SRC_EXT_CLK:
- parent_name = "timer_ext_ck";
- break;
- }
-
- parent = clk_get(&timer->pdev->dev, parent_name);
- if (IS_ERR(parent)) {
- pr_err("%s: %s not found\n", __func__, parent_name);
- return -EINVAL;
- }
-
- ret = clk_set_parent(timer->fclk, parent);
- if (ret < 0)
- pr_err("%s: failed to set %s as parent\n", __func__,
- parent_name);
-
- clk_put(parent);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
-
-int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
- unsigned int load)
-{
- u32 l;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- if (autoreload)
- l |= OMAP_TIMER_CTRL_AR;
- else
- l &= ~OMAP_TIMER_CTRL_AR;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
-
- omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
- /* Save the context */
- timer->context.tclr = l;
- timer->context.tldr = load;
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
-
-/* Optimized set_load which removes costly spin wait in timer_start */
-int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
- unsigned int load)
-{
- u32 l;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
-
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- if (autoreload) {
- l |= OMAP_TIMER_CTRL_AR;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
- } else {
- l &= ~OMAP_TIMER_CTRL_AR;
- }
- l |= OMAP_TIMER_CTRL_ST;
-
- __omap_dm_timer_load_start(timer, l, load, timer->posted);
-
- /* Save the context */
- timer->context.tclr = l;
- timer->context.tldr = load;
- timer->context.tcrr = load;
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
-
-int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
- unsigned int match)
-{
- u32 l;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- if (enable)
- l |= OMAP_TIMER_CTRL_CE;
- else
- l &= ~OMAP_TIMER_CTRL_CE;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
-
- /* Save the context */
- timer->context.tclr = l;
- timer->context.tmar = match;
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
-
-int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
- int toggle, int trigger)
-{
- u32 l;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
- OMAP_TIMER_CTRL_PT | (0x03 << 10));
- if (def_on)
- l |= OMAP_TIMER_CTRL_SCPWM;
- if (toggle)
- l |= OMAP_TIMER_CTRL_PT;
- l |= trigger << 10;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
-
- /* Save the context */
- timer->context.tclr = l;
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
-
-int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
-{
- u32 l;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
- if (prescaler >= 0x00 && prescaler <= 0x07) {
- l |= OMAP_TIMER_CTRL_PRE;
- l |= prescaler << 2;
- }
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
-
- /* Save the context */
- timer->context.tclr = l;
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
-
-int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
- unsigned int value)
-{
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
- __omap_dm_timer_int_enable(timer, value);
-
- /* Save the context */
- timer->context.tier = value;
- timer->context.twer = value;
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
-
-/**
- * omap_dm_timer_set_int_disable - disable timer interrupts
- * @timer: pointer to timer handle
- * @mask: bit mask of interrupts to be disabled
- *
- * Disables the specified timer interrupts for a timer.
- */
-int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
-{
- u32 l = mask;
-
- if (unlikely(!timer))
- return -EINVAL;
-
- omap_dm_timer_enable(timer);
-
- if (timer->revision == 1)
- l = readl_relaxed(timer->irq_ena) & ~mask;
-
- writel_relaxed(l, timer->irq_dis);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
-
- /* Save the context */
- timer->context.tier &= ~mask;
- timer->context.twer &= ~mask;
- omap_dm_timer_disable(timer);
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
-
-unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
-{
- unsigned int l;
-
- if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- pr_err("%s: timer not available or enabled.\n", __func__);
- return 0;
- }
-
- l = readl_relaxed(timer->irq_stat);
-
- return l;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
-
-int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
-{
- if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
- return -EINVAL;
-
- __omap_dm_timer_write_status(timer, value);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
-
-unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
-{
- if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- pr_err("%s: timer not iavailable or enabled.\n", __func__);
- return 0;
- }
-
- return __omap_dm_timer_read_counter(timer, timer->posted);
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
-
-int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
-{
- if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
- pr_err("%s: timer not available or enabled.\n", __func__);
- return -EINVAL;
- }
-
- omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
-
- /* Save the context */
- timer->context.tcrr = value;
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
-
-int omap_dm_timers_active(void)
-{
- struct omap_dm_timer *timer;
-
- list_for_each_entry(timer, &omap_timer_list, node) {
- if (!timer->reserved)
- continue;
-
- if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
- OMAP_TIMER_CTRL_ST) {
- return 1;
- }
- }
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_dm_timers_active);
-
-static const struct of_device_id omap_timer_match[];
-
-/**
- * omap_dm_timer_probe - probe function called for every registered device
- * @pdev: pointer to current timer platform device
- *
- * Called by driver framework at the end of device registration for all
- * timer devices.
- */
-static int omap_dm_timer_probe(struct platform_device *pdev)
-{
- unsigned long flags;
- struct omap_dm_timer *timer;
- struct resource *mem, *irq;
- struct device *dev = &pdev->dev;
- const struct of_device_id *match;
- const struct dmtimer_platform_data *pdata;
- int ret;
-
- match = of_match_device(of_match_ptr(omap_timer_match), dev);
- pdata = match ? match->data : dev->platform_data;
-
- if (!pdata && !dev->of_node) {
- dev_err(dev, "%s: no platform data.\n", __func__);
- return -ENODEV;
- }
-
- irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (unlikely(!irq)) {
- dev_err(dev, "%s: no IRQ resource.\n", __func__);
- return -ENODEV;
- }
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (unlikely(!mem)) {
- dev_err(dev, "%s: no memory resource.\n", __func__);
- return -ENODEV;
- }
-
- timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
- if (!timer)
- return -ENOMEM;
-
- timer->fclk = ERR_PTR(-ENODEV);
- timer->io_base = devm_ioremap_resource(dev, mem);
- if (IS_ERR(timer->io_base))
- return PTR_ERR(timer->io_base);
-
- if (dev->of_node) {
- if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
- timer->capability |= OMAP_TIMER_ALWON;
- if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
- timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
- if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
- timer->capability |= OMAP_TIMER_HAS_PWM;
- if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
- timer->capability |= OMAP_TIMER_SECURE;
- } else {
- timer->id = pdev->id;
- timer->capability = pdata->timer_capability;
- timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
- timer->get_context_loss_count = pdata->get_context_loss_count;
- }
-
- if (pdata)
- timer->errata = pdata->timer_errata;
-
- timer->irq = irq->start;
- timer->pdev = pdev;
-
- /* Skip pm_runtime_enable for OMAP1 */
- if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
- pm_runtime_enable(dev);
- pm_runtime_irq_safe(dev);
- }
-
- if (!timer->reserved) {
- ret = pm_runtime_get_sync(dev);
- if (ret < 0) {
- dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
- __func__);
- goto err_get_sync;
- }
- __omap_dm_timer_init_regs(timer);
- pm_runtime_put(dev);
- }
-
- /* add the timer element to the list */
- spin_lock_irqsave(&dm_timer_lock, flags);
- list_add_tail(&timer->node, &omap_timer_list);
- spin_unlock_irqrestore(&dm_timer_lock, flags);
-
- dev_dbg(dev, "Device Probed.\n");
-
- return 0;
-
-err_get_sync:
- pm_runtime_put_noidle(dev);
- pm_runtime_disable(dev);
- return ret;
-}
-
-/**
- * omap_dm_timer_remove - cleanup a registered timer device
- * @pdev: pointer to current timer platform device
- *
- * Called by driver framework whenever a timer device is unregistered.
- * In addition to freeing platform resources it also deletes the timer
- * entry from the local list.
- */
-static int omap_dm_timer_remove(struct platform_device *pdev)
-{
- struct omap_dm_timer *timer;
- unsigned long flags;
- int ret = -EINVAL;
-
- spin_lock_irqsave(&dm_timer_lock, flags);
- list_for_each_entry(timer, &omap_timer_list, node)
- if (!strcmp(dev_name(&timer->pdev->dev),
- dev_name(&pdev->dev))) {
- list_del(&timer->node);
- ret = 0;
- break;
- }
- spin_unlock_irqrestore(&dm_timer_lock, flags);
-
- pm_runtime_disable(&pdev->dev);
-
- return ret;
-}
-
-static const struct dmtimer_platform_data omap3plus_pdata = {
- .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
-};
-
-static const struct of_device_id omap_timer_match[] = {
- {
- .compatible = "ti,omap2420-timer",
- },
- {
- .compatible = "ti,omap3430-timer",
- .data = &omap3plus_pdata,
- },
- {
- .compatible = "ti,omap4430-timer",
- .data = &omap3plus_pdata,
- },
- {
- .compatible = "ti,omap5430-timer",
- .data = &omap3plus_pdata,
- },
- {
- .compatible = "ti,am335x-timer",
- .data = &omap3plus_pdata,
- },
- {
- .compatible = "ti,am335x-timer-1ms",
- .data = &omap3plus_pdata,
- },
- {
- .compatible = "ti,dm816-timer",
- .data = &omap3plus_pdata,
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, omap_timer_match);
-
-static struct platform_driver omap_dm_timer_driver = {
- .probe = omap_dm_timer_probe,
- .remove = omap_dm_timer_remove,
- .driver = {
- .name = "omap_timer",
- .of_match_table = of_match_ptr(omap_timer_match),
- },
-};
-
-early_platform_init("earlytimer", &omap_dm_timer_driver);
-module_platform_driver(omap_dm_timer_driver);
-
-MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRIVER_NAME);
-MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
deleted file mode 100644
index dd79f3005cdf..000000000000
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * arch/arm/plat-omap/include/plat/dmtimer.h
- *
- * OMAP Dual-Mode Timers
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Tarun Kanti DebBarma <tarun.kanti@ti.com>
- * Thara Gopinath <thara@ti.com>
- *
- * Platform device conversion and hwmod support.
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
- * PWM and clock framwork support by Timo Teras.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-
-#ifndef __ASM_ARCH_DMTIMER_H
-#define __ASM_ARCH_DMTIMER_H
-
-/* clock sources */
-#define OMAP_TIMER_SRC_SYS_CLK 0x00
-#define OMAP_TIMER_SRC_32_KHZ 0x01
-#define OMAP_TIMER_SRC_EXT_CLK 0x02
-
-/* timer interrupt enable bits */
-#define OMAP_TIMER_INT_CAPTURE (1 << 2)
-#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
-#define OMAP_TIMER_INT_MATCH (1 << 0)
-
-/* trigger types */
-#define OMAP_TIMER_TRIGGER_NONE 0x00
-#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
-#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
-
-/* posted mode types */
-#define OMAP_TIMER_NONPOSTED 0x00
-#define OMAP_TIMER_POSTED 0x01
-
-/* timer capabilities used in hwmod database */
-#define OMAP_TIMER_SECURE 0x80000000
-#define OMAP_TIMER_ALWON 0x40000000
-#define OMAP_TIMER_HAS_PWM 0x20000000
-#define OMAP_TIMER_NEEDS_RESET 0x10000000
-#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
-
-/*
- * timer errata flags
- *
- * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
- * errata prevents us from using posted mode on these devices, unless the
- * timer counter register is never read. For more details please refer to
- * the OMAP3/4/5 errata documents.
- */
-#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
-
-struct omap_timer_capability_dev_attr {
- u32 timer_capability;
-};
-
-struct timer_regs {
- u32 tidr;
- u32 tier;
- u32 twer;
- u32 tclr;
- u32 tcrr;
- u32 tldr;
- u32 ttrg;
- u32 twps;
- u32 tmar;
- u32 tcar1;
- u32 tsicr;
- u32 tcar2;
- u32 tpir;
- u32 tnir;
- u32 tcvr;
- u32 tocr;
- u32 towr;
-};
-
-struct omap_dm_timer {
- int id;
- int irq;
- struct clk *fclk;
-
- void __iomem *io_base;
- void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
- void __iomem *irq_ena; /* irq enable */
- void __iomem *irq_dis; /* irq disable, only on v2 ip */
- void __iomem *pend; /* write pending */
- void __iomem *func_base; /* function register base */
-
- unsigned long rate;
- unsigned reserved:1;
- unsigned posted:1;
- struct timer_regs context;
- int (*get_context_loss_count)(struct device *);
- int ctx_loss_count;
- int revision;
- u32 capability;
- u32 errata;
- struct platform_device *pdev;
- struct list_head node;
-};
-
-int omap_dm_timer_reserve_systimer(int id);
-struct omap_dm_timer *omap_dm_timer_request(void);
-struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
-struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np);
-int omap_dm_timer_free(struct omap_dm_timer *timer);
-void omap_dm_timer_enable(struct omap_dm_timer *timer);
-void omap_dm_timer_disable(struct omap_dm_timer *timer);
-
-int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
-
-u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
-struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
-
-int omap_dm_timer_trigger(struct omap_dm_timer *timer);
-int omap_dm_timer_start(struct omap_dm_timer *timer);
-int omap_dm_timer_stop(struct omap_dm_timer *timer);
-
-int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
-
-int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
-int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
-
-unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
-unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
-
-int omap_dm_timers_active(void);
-
-/*
- * Do not use the defines below, they are not needed. They should be only
- * used by dmtimer.c and sys_timer related code.
- */
-
-/*
- * The interrupt registers are different between v1 and v2 ip.
- * These registers are offsets from timer->iobase.
- */
-#define OMAP_TIMER_ID_OFFSET 0x00
-#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
-
-#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
-#define OMAP_TIMER_V1_STAT_OFFSET 0x18
-#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
-
-#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
-#define OMAP_TIMER_V2_IRQSTATUS 0x28
-#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
-#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
-
-/*
- * The functional registers have a different base on v1 and v2 ip.
- * These registers are offsets from timer->func_base. The func_base
- * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
- *
- */
-#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
-
-#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
-#define _OMAP_TIMER_CTRL_OFFSET 0x24
-#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
-#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
-#define OMAP_TIMER_CTRL_PT (1 << 12)
-#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
-#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
-#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
-#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
-#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
-#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
-#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
-#define OMAP_TIMER_CTRL_POSTED (1 << 2)
-#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
-#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
-#define _OMAP_TIMER_COUNTER_OFFSET 0x28
-#define _OMAP_TIMER_LOAD_OFFSET 0x2c
-#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
-#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
-#define WP_NONE 0 /* no write pending bit */
-#define WP_TCLR (1 << 0)
-#define WP_TCRR (1 << 1)
-#define WP_TLDR (1 << 2)
-#define WP_TTGR (1 << 3)
-#define WP_TMAR (1 << 4)
-#define WP_TPIR (1 << 5)
-#define WP_TNIR (1 << 6)
-#define WP_TCVR (1 << 7)
-#define WP_TOCR (1 << 8)
-#define WP_TOWR (1 << 9)
-#define _OMAP_TIMER_MATCH_OFFSET 0x38
-#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
-#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
-#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
-#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
-#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
-#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
-
-/* register offsets with the write pending bit encoded */
-#define WPSHIFT 16
-
-#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
- | (WP_TCLR << WPSHIFT))
-
-#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
- | (WP_TCRR << WPSHIFT))
-
-#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
- | (WP_TLDR << WPSHIFT))
-
-#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
- | (WP_TTGR << WPSHIFT))
-
-#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
- | (WP_TMAR << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
- | (WP_TPIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
- | (WP_TNIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
- | (WP_TCVR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
- (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
- (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
-
-static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
- int posted)
-{
- if (posted)
- while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
- cpu_relax();
-
- return readl_relaxed(timer->func_base + (reg & 0xff));
-}
-
-static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
- u32 reg, u32 val, int posted)
-{
- if (posted)
- while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
- cpu_relax();
-
- writel_relaxed(val, timer->func_base + (reg & 0xff));
-}
-
-static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
-{
- u32 tidr;
-
- /* Assume v1 ip if bits [31:16] are zero */
- tidr = readl_relaxed(timer->io_base);
- if (!(tidr >> 16)) {
- timer->revision = 1;
- timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
- timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
- timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
- timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
- timer->func_base = timer->io_base;
- } else {
- timer->revision = 2;
- timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
- timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
- timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
- timer->pend = timer->io_base +
- _OMAP_TIMER_WRITE_PEND_OFFSET +
- OMAP_TIMER_V2_FUNC_OFFSET;
- timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
- }
-}
-
-/*
- * __omap_dm_timer_enable_posted - enables write posted mode
- * @timer: pointer to timer instance handle
- *
- * Enables the write posted mode for the timer. When posted mode is enabled
- * writes to certain timer registers are immediately acknowledged by the
- * internal bus and hence prevents stalling the CPU waiting for the write to
- * complete. Enabling this feature can improve performance for writing to the
- * timer registers.
- */
-static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
-{
- if (timer->posted)
- return;
-
- if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
- timer->posted = OMAP_TIMER_NONPOSTED;
- __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
- return;
- }
-
- __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
- OMAP_TIMER_CTRL_POSTED, 0);
- timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
- timer->posted = OMAP_TIMER_POSTED;
-}
-
-/**
- * __omap_dm_timer_override_errata - override errata flags for a timer
- * @timer: pointer to timer handle
- * @errata: errata flags to be ignored
- *
- * For a given timer, override a timer errata by clearing the flags
- * specified by the errata argument. A specific erratum should only be
- * overridden for a timer if the timer is used in such a way the erratum
- * has no impact.
- */
-static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
- u32 errata)
-{
- timer->errata &= ~errata;
-}
-
-static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
- int posted, unsigned long rate)
-{
- u32 l;
-
- l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
- if (l & OMAP_TIMER_CTRL_ST) {
- l &= ~0x1;
- __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
-#ifdef CONFIG_ARCH_OMAP2PLUS
- /* Readback to make sure write has completed */
- __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
- /*
- * Wait for functional clock period x 3.5 to make sure that
- * timer is stopped
- */
- udelay(3500000 / rate + 1);
-#endif
- }
-
- /* Ack possibly pending interrupt */
- writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
-}
-
-static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
- u32 ctrl, unsigned int load,
- int posted)
-{
- __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
- __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
-}
-
-static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
- unsigned int value)
-{
- writel_relaxed(value, timer->irq_ena);
- __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
-}
-
-static inline unsigned int
-__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
-{
- return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
-}
-
-static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
- unsigned int value)
-{
- writel_relaxed(value, timer->irq_stat);
-}
-
-#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
deleted file mode 100644
index 810629d79668..000000000000
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Helper module for board specific I2C bus registration
- *
- * Copyright (C) 2009 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef __PLAT_OMAP_I2C_H
-#define __PLAT_OMAP_I2C_H
-
-struct i2c_board_info;
-struct omap_i2c_bus_platform_data;
-
-int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
- int bus_id);
-
-#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
- struct i2c_board_info const *info,
- unsigned len);
-extern int omap_register_i2c_bus_cmdline(void);
-#else
-static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
- struct i2c_board_info const *info,
- unsigned len)
-{
- return 0;
-}
-
-static inline int omap_register_i2c_bus_cmdline(void)
-{
- return 0;
-}
-#endif
-
-struct omap_hwmod;
-int omap_i2c_reset(struct omap_hwmod *oh);
-
-#endif /* __PLAT_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index fb061cf0d736..30a07730807a 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -5,13 +5,4 @@ void omap_map_sram(unsigned long start, unsigned long size,
unsigned long skip, int cached);
void omap_sram_reset(void);
-extern void *omap_sram_push_address(unsigned long size);
-
-/* Macro to push a function to the internal SRAM, using the fncpy API */
-#define omap_sram_push(funcp, size) ({ \
- typeof(&(funcp)) _res = NULL; \
- void *_sram_address = omap_sram_push_address(size); \
- if (_sram_address) \
- _res = fncpy(_sram_address, &(funcp), size); \
- _res; \
-})
+extern void *omap_sram_push(void *funcp, unsigned long size);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a5bc92d7e476..921840acf65c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -23,6 +23,7 @@
#include <asm/fncpy.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
+#include <asm/set_memory.h>
#include <asm/mach/map.h>
@@ -42,7 +43,7 @@ static void __iomem *omap_sram_ceil;
* Note that fncpy requires the returned address to be aligned
* to an 8-byte boundary.
*/
-void *omap_sram_push_address(unsigned long size)
+static void *omap_sram_push_address(unsigned long size)
{
unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
@@ -60,6 +61,30 @@ void *omap_sram_push_address(unsigned long size)
return (void *)omap_sram_ceil;
}
+void *omap_sram_push(void *funcp, unsigned long size)
+{
+ void *sram;
+ unsigned long base;
+ int pages;
+ void *dst = NULL;
+
+ sram = omap_sram_push_address(size);
+ if (!sram)
+ return NULL;
+
+ base = (unsigned long)sram & PAGE_MASK;
+ pages = PAGE_ALIGN(size) / PAGE_SIZE;
+
+ set_memory_rw(base, pages);
+
+ dst = fncpy(sram, funcp, size);
+
+ set_memory_ro(base, pages);
+ set_memory_x(base, pages);
+
+ return dst;
+}
+
/*
* The SRAM context is lost during off-idle and stack
* needs to be reset.
@@ -75,6 +100,9 @@ void omap_sram_reset(void)
void __init omap_map_sram(unsigned long start, unsigned long size,
unsigned long skip, int cached)
{
+ unsigned long base;
+ int pages;
+
if (size == 0)
return;
@@ -95,4 +123,10 @@ void __init omap_map_sram(unsigned long start, unsigned long size,
*/
memset_io(omap_sram_base + omap_sram_skip, 0,
omap_sram_size - omap_sram_skip);
+
+ base = (unsigned long)omap_sram_base;
+ pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
+
+ set_memory_ro(base, pages);
+ set_memory_x(base, pages);
}
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 03c6a3c72f9c..4c375e11ae95 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -648,7 +648,7 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
*/
static int vfp_dying_cpu(unsigned int cpu)
{
- vfp_force_reload(cpu, current_thread_info());
+ vfp_current_hw_state[cpu] = NULL;
return 0;
}
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7381eeb7ef8e..eb2cf4938f6d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -132,6 +132,7 @@ config ARM64
select IRQ_DOMAIN
select IRQ_FORCED_THREADING
select MODULES_USE_ELF_RELA
+ select MULTI_IRQ_HANDLER
select NO_BOOTMEM
select OF
select OF_EARLY_FLATTREE
@@ -275,6 +276,9 @@ config ARCH_SUPPORTS_UPROBES
config ARCH_PROC_KCORE_TEXT
def_bool y
+config MULTI_IRQ_HANDLER
+ def_bool y
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
@@ -455,12 +459,26 @@ config ARM64_ERRATUM_845719
config ARM64_ERRATUM_843419
bool "Cortex-A53: 843419: A load or store might access an incorrect address"
default y
- select ARM64_MODULE_CMODEL_LARGE if MODULES
+ select ARM64_MODULE_PLTS if MODULES
help
This option links the kernel with '--fix-cortex-a53-843419' and
- builds modules using the large memory model in order to avoid the use
- of the ADRP instruction, which can cause a subsequent memory access
- to use an incorrect address on Cortex-A53 parts up to r0p4.
+ enables PLT support to replace certain ADRP instructions, which can
+ cause subsequent memory accesses to use an incorrect address on
+ Cortex-A53 parts up to r0p4.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_1024718
+ bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
+ default y
+ help
+ This option adds work around for Arm Cortex-A55 Erratum 1024718.
+
+ Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+ update of the hardware dirty bit when the DBM/AP bits are updated
+ without a break-before-make. The work around is to disable the usage
+ of hardware DBM locally on the affected cores. CPUs not affected by
+ erratum will continue to use the feature.
If unsure, say Y.
@@ -904,6 +922,22 @@ config HARDEN_BRANCH_PREDICTOR
If unsure, say Y.
+config HARDEN_EL2_VECTORS
+ bool "Harden EL2 vector mapping against system register leak" if EXPERT
+ default y
+ help
+ Speculation attacks against some high-performance processors can
+ be used to leak privileged information such as the vector base
+ register, resulting in a potential defeat of the EL2 layout
+ randomization.
+
+ This config option will map the vectors to a fixed location,
+ independent of the EL2 code mapping, so that revealing VBAR_EL2
+ to an attacker does not give away any extra information. This
+ only gets enabled on affected CPUs.
+
+ If unsure, say Y.
+
menuconfig ARMV8_DEPRECATED
bool "Emulate deprecated/obsolete ARMv8 instructions"
depends on COMPAT
@@ -1104,12 +1138,25 @@ config ARM64_SVE
To enable use of this extension on CPUs that implement it, say Y.
-config ARM64_MODULE_CMODEL_LARGE
- bool
+ Note that for architectural reasons, firmware _must_ implement SVE
+ support when running on SVE capable hardware. The required support
+ is present in:
+
+ * version 1.5 and later of the ARM Trusted Firmware
+ * the AArch64 boot wrapper since commit 5e1261e08abf
+ ("bootwrapper: SVE: Enable SVE for EL2 and below").
+
+ For other firmware implementations, consult the firmware documentation
+ or vendor.
+
+ If you need the kernel to boot on SVE-capable hardware with broken
+ firmware, you may need to say N here until you get your firmware
+ fixed. Otherwise, you may experience firmware panics or lockups when
+ booting the kernel. If unsure and you are not observing these
+ symptoms, you should assume that it is safe to say Y.
config ARM64_MODULE_PLTS
bool
- select ARM64_MODULE_CMODEL_LARGE
select HAVE_MOD_ARCH_SPECIFIC
config RELOCATABLE
@@ -1143,12 +1190,12 @@ config RANDOMIZE_BASE
If unsure, say N.
config RANDOMIZE_MODULE_REGION_FULL
- bool "Randomize the module region independently from the core kernel"
+ bool "Randomize the module region over a 4 GB range"
depends on RANDOMIZE_BASE
default y
help
- Randomizes the location of the module region without considering the
- location of the core kernel. This way, it is impossible for modules
+ Randomizes the location of the module region inside a 4 GB window
+ covering the core kernel. This way, it is less likely for modules
to leak information about the location of core kernel data structures
but it does imply that function calls between modules and the core
kernel will need to be resolved via veneers in the module PLT.
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index fbedbd8f619a..2b1535cdeb7c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -190,12 +190,24 @@ config ARCH_R8A7796
help
This enables support for the Renesas R-Car M3-W SoC.
+config ARCH_R8A77965
+ bool "Renesas R-Car M3-N SoC Platform"
+ depends on ARCH_RENESAS
+ help
+ This enables support for the Renesas R-Car M3-N SoC.
+
config ARCH_R8A77970
bool "Renesas R-Car V3M SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car V3M SoC.
+config ARCH_R8A77980
+ bool "Renesas R-Car V3H SoC Platform"
+ depends on ARCH_RENESAS
+ help
+ This enables support for the Renesas R-Car V3H SoC.
+
config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform"
depends on ARCH_RENESAS
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index b481b4a7c011..15402861bb59 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -51,7 +51,6 @@ endif
KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst)
KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
-KBUILD_CFLAGS += $(call cc-option, -mpc-relative-literal-loads)
KBUILD_AFLAGS += $(lseinstr) $(brokengasinst)
KBUILD_CFLAGS += $(call cc-option,-mabi=lp64)
@@ -77,10 +76,6 @@ endif
CHECKFLAGS += -D__aarch64__ -m64
-ifeq ($(CONFIG_ARM64_MODULE_CMODEL_LARGE), y)
-KBUILD_CFLAGS_MODULE += -mcmodel=large
-endif
-
ifeq ($(CONFIG_ARM64_MODULE_PLTS),y)
KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/arm64/kernel/module.lds
endif
@@ -97,12 +92,14 @@ else
TEXT_OFFSET := 0x00080000
endif
-# KASAN_SHADOW_OFFSET = VA_START + (1 << (VA_BITS - 3)) - (1 << 61)
+# KASAN_SHADOW_OFFSET = VA_START + (1 << (VA_BITS - KASAN_SHADOW_SCALE_SHIFT))
+# - (1 << (64 - KASAN_SHADOW_SCALE_SHIFT))
# in 32-bit arithmetic
+KASAN_SHADOW_SCALE_SHIFT := 3
KASAN_SHADOW_OFFSET := $(shell printf "0x%08x00000000\n" $$(( \
- (0xffffffff & (-1 << ($(CONFIG_ARM64_VA_BITS) - 32))) \
- + (1 << ($(CONFIG_ARM64_VA_BITS) - 32 - 3)) \
- - (1 << (64 - 32 - 3)) )) )
+ (0xffffffff & (-1 << ($(CONFIG_ARM64_VA_BITS) - 32))) \
+ + (1 << ($(CONFIG_ARM64_VA_BITS) - 32 - $(KASAN_SHADOW_SCALE_SHIFT))) \
+ - (1 << (64 - 32 - $(KASAN_SHADOW_SCALE_SHIFT))) )) )
export TEXT_OFFSET GZFLAGS
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index f505227b0250..8bebe7da5ed9 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -5,8 +5,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index a6975670cd1c..2250dec9974c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -120,8 +120,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index 2beef9e6cb88..e2dce48fa29a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -82,8 +82,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 8807664f363a..3b3081b10ecb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -68,8 +68,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 240d35731d10..bf42690a3361 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -67,8 +67,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 604cdaedac38..a75825798a71 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -103,8 +103,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
@@ -230,6 +229,11 @@
regulator-name = "vcc-rtc";
};
+/* On Euler connector */
+&spdif {
+ status = "disabled";
+};
+
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
new file mode 100644
index 000000000000..d9baab3dc96b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) Harald Geyer <harald@ccbib.org>
+ * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Olimex A64 Teres-I";
+ compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ framebuffer-lcd {
+ eDP25-supply = <&reg_dldo2>;
+ eDP12-supply = <&reg_dldo3>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ lid-switch {
+ label = "Lid Switch";
+ gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ capslock {
+ label = "teres-i:green:capslock";
+ gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+ };
+
+ numlock {
+ label = "teres-i:green:numlock";
+ gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+ };
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ status = "okay";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+
+/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
+ * driver for this chip at the moment, the bootloader initializes it.
+ * However it can be accessed with the i2c-dev driver from user space.
+ */
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_aldo2>;
+ vqmmc-supply = <&reg_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-ddr3";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pd";
+};
+
+&reg_dldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "eDP12";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_eldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dvdd-csi";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d783d164b9c3..1b2ef28c42bd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -52,6 +52,26 @@
#address-cells = <1>;
#size-cells = <1>;
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+/*
+ * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
+ * However there is no support for this clock on A64 yet, so we depend
+ * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
+ */
+ simplefb_lcd: framebuffer-lcd {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "mixer0-lcd0";
+ clocks = <&ccu CLK_TCON0>,
+ <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+ status = "disabled";
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -112,6 +132,24 @@
method = "smc";
};
+ sound_spdif {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@@ -291,6 +329,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ i2c0_pins: i2c0_pins {
+ pins = "PH0", "PH1";
+ function = "i2c0";
+ };
+
i2c1_pins: i2c1_pins {
pins = "PH2", "PH3";
function = "i2c1";
@@ -336,6 +379,11 @@
drive-strength = <40>;
};
+ spdif_tx_pin: spdif {
+ pins = "PH8";
+ function = "spdif";
+ };
+
spi0_pins: spi0 {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
@@ -382,6 +430,50 @@
};
};
+ spdif: spdif@1c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-spdif",
+ "allwinner,sun8i-h3-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+ resets = <&ccu RST_BUS_SPDIF>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma 2>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S0>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 3>, <&dma 3>;
+ status = "disabled";
+ };
+
+ i2s1: i2s@1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-a64-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S1>;
+ dma-names = "rx", "tx";
+ dmas = <&dma 4>, <&dma 4>;
+ status = "disabled";
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -593,5 +685,12 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ wdt0: watchdog@1c20ca0 {
+ compatible = "allwinner,sun50i-a64-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
index 1ed9f219deaf..506e25ba028a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
@@ -151,8 +151,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -160,8 +158,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
index f1447003ea3c..cc268a69786c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
@@ -126,8 +126,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 9e51d3a5f4e6..98862c7c7258 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -67,6 +67,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -121,6 +132,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -153,6 +168,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -160,8 +185,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index 0f25c4a6f15d..b75ca4d7d001 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -62,6 +62,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -128,6 +139,10 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -160,6 +175,16 @@
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
@@ -167,8 +192,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -176,8 +199,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
new file mode 100644
index 000000000000..1238de25a969
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Zero Plus";
+ compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189ftv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ rtl8189ftv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A ports' VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
index af43533c7134..53c8c11620e0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
@@ -58,6 +58,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -73,9 +84,21 @@
};
};
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -83,8 +106,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
new file mode 100644
index 000000000000..d36de5eb81f3
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Pine H64";
+ compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
new file mode 100644
index 000000000000..56563150d61a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-accuracy = <300000000>;
+ clock-output-names = "iosc";
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h6-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-h6-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 26>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ uart0_ph_pins: uart0-ph {
+ pins = "PH0", "PH1";
+ function = "uart0";
+ };
+ };
+
+ uart0: serial@5000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 70>;
+ resets = <&ccu 21>;
+ status = "disabled";
+ };
+
+ uart1: serial@5000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 71>;
+ resets = <&ccu 22>;
+ status = "disabled";
+ };
+
+ uart2: serial@5000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 72>;
+ resets = <&ccu 23>;
+ status = "disabled";
+ };
+
+ uart3: serial@5000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu 73>;
+ resets = <&ccu 24>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 000756429b77..eaf13fe29287 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -88,7 +88,6 @@
&mmc {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
@@ -100,4 +99,9 @@
&usb0 {
status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 447b98d30921..57eedced5a51 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -14,6 +13,7 @@
aliases {
serial0 = &uart_AO;
+ serial1 = &uart_A;
};
};
@@ -24,8 +24,16 @@
pinctrl-names = "default";
};
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>;
+ pinctrl-names = "default";
+};
+
&uart_AO {
status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
};
&ir {
@@ -33,3 +41,9 @@
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_z_pins>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 70c776ef7aa7..b58808eb3cc8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/gpio/gpio.h>
@@ -163,18 +162,70 @@
status = "disabled";
};
+ i2c0: i2c@1f000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1f000 0x0 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ clock-names = "clk_i2c";
+ };
+
+ i2c1: i2c@1e000 {
+ compatible = "amlogic,meson-axg-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1e000 0x0 0x20>;
+ status = "disabled";
+ interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_I2C>;
+ clock-names = "clk_i2c";
+ };
+
+ i2c2: i2c@1d000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1d000 0x0 0x20>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ clock-names = "clk_i2c";
+ };
+
+ i2c3: i2c@1c000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1c000 0x0 0x20>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ clock-names = "clk_i2c";
+ };
+
uart_A: serial@24000 {
- compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
};
uart_B: serial@23000 {
- compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
+ compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
};
};
@@ -234,6 +285,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x18 0x0 0x4>;
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+ };
+
pinctrl_periphs: pinctrl@480 {
compatible = "amlogic,meson-axg-periphs-pinctrl";
#address-cells = <2>;
@@ -251,6 +309,36 @@
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
+ eth_rmii_x_pins: eth-x-rmii {
+ mux {
+ groups = "eth_mdio_x",
+ "eth_mdc_x",
+ "eth_rgmii_rx_clk_x",
+ "eth_rx_dv_x",
+ "eth_rxd0_x",
+ "eth_rxd1_x",
+ "eth_txen_x",
+ "eth_txd0_x",
+ "eth_txd1_x";
+ function = "eth";
+ };
+ };
+
+ eth_rmii_y_pins: eth-y-rmii {
+ mux {
+ groups = "eth_mdio_y",
+ "eth_mdc_y",
+ "eth_rgmii_rx_clk_y",
+ "eth_rx_dv_y",
+ "eth_rxd0_y",
+ "eth_rxd1_y",
+ "eth_txen_y",
+ "eth_txd0_y",
+ "eth_txd1_y";
+ function = "eth";
+ };
+ };
+
eth_rgmii_x_pins: eth-x-rgmii {
mux {
groups = "eth_mdio_x",
@@ -444,6 +532,134 @@
function = "spi1";
};
};
+
+ i2c0_pins: i2c0 {
+ mux {
+ groups = "i2c0_sck",
+ "i2c0_sda";
+ function = "i2c0";
+ };
+ };
+
+ i2c1_z_pins: i2c1_z {
+ mux {
+ groups = "i2c1_sck_z",
+ "i2c1_sda_z";
+ function = "i2c1";
+ };
+ };
+
+ i2c1_x_pins: i2c1_x {
+ mux {
+ groups = "i2c1_sck_x",
+ "i2c1_sda_x";
+ function = "i2c1";
+ };
+ };
+
+ i2c2_x_pins: i2c2_x {
+ mux {
+ groups = "i2c2_sck_x",
+ "i2c2_sda_x";
+ function = "i2c2";
+ };
+ };
+
+ i2c2_a_pins: i2c2_a {
+ mux {
+ groups = "i2c2_sck_a",
+ "i2c2_sda_a";
+ function = "i2c2";
+ };
+ };
+
+ i2c3_a6_pins: i2c3_a6 {
+ mux {
+ groups = "i2c3_sda_a6",
+ "i2c3_sck_a7";
+ function = "i2c3";
+ };
+ };
+
+ i2c3_a12_pins: i2c3_a12 {
+ mux {
+ groups = "i2c3_sda_a12",
+ "i2c3_sck_a13";
+ function = "i2c3";
+ };
+ };
+
+ i2c3_a19_pins: i2c3_a19 {
+ mux {
+ groups = "i2c3_sda_a19",
+ "i2c3_sck_a20";
+ function = "i2c3";
+ };
+ };
+
+ uart_a_pins: uart_a {
+ mux {
+ groups = "uart_tx_a",
+ "uart_rx_a";
+ function = "uart_a";
+ };
+ };
+
+ uart_a_cts_rts_pins: uart_a_cts_rts {
+ mux {
+ groups = "uart_cts_a",
+ "uart_rts_a";
+ function = "uart_a";
+ };
+ };
+
+ uart_b_x_pins: uart_b_x {
+ mux {
+ groups = "uart_tx_b_x",
+ "uart_rx_b_x";
+ function = "uart_b";
+ };
+ };
+
+ uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+ mux {
+ groups = "uart_cts_b_x",
+ "uart_rts_b_x";
+ function = "uart_b";
+ };
+ };
+
+ uart_b_z_pins: uart_b_z {
+ mux {
+ groups = "uart_tx_b_z",
+ "uart_rx_b_z";
+ function = "uart_b";
+ };
+ };
+
+ uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+ mux {
+ groups = "uart_cts_b_z",
+ "uart_rts_b_z";
+ function = "uart_b";
+ };
+ };
+
+ uart_ao_b_z_pins: uart_ao_b_z {
+ mux {
+ groups = "uart_ao_tx_b_z",
+ "uart_ao_rx_b_z";
+ function = "uart_ao_b_z";
+ };
+ };
+
+ uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+ mux {
+ groups = "uart_ao_cts_b_z",
+ "uart_ao_rts_b_z";
+ function = "uart_ao_b_z";
+ };
+ };
};
};
@@ -494,6 +710,44 @@
function = "remote_input_ao";
};
};
+
+ uart_ao_a_pins: uart_ao_a {
+ mux {
+ groups = "uart_ao_tx_a",
+ "uart_ao_rx_a";
+ function = "uart_ao_a";
+ };
+ };
+
+ uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+ mux {
+ groups = "uart_ao_cts_a",
+ "uart_ao_rts_a";
+ function = "uart_ao_a";
+ };
+ };
+
+ uart_ao_b_pins: uart_ao_b {
+ mux {
+ groups = "uart_ao_tx_b",
+ "uart_ao_rx_b";
+ function = "uart_ao_b";
+ };
+ };
+
+ uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+ mux {
+ groups = "uart_ao_cts_b",
+ "uart_ao_rts_b";
+ function = "uart_ao_b";
+ };
+ };
+ };
+
+ sec_AO: ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
};
pwm_AO_ab: pwm@7000 {
@@ -504,12 +758,23 @@
};
pwm_AO_cd: pwm@2000 {
- compatible = "amlogic,axg-ao-pwm";
+ compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x02000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
+ i2c_AO: i2c@5000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x05000 0x0 0x20>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ clock-names = "clk_i2c";
+ };
+
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index aeb6d21a3bec..4eef36b22538 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
@@ -48,6 +11,7 @@
/ {
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 4ee2e7951482..3c31e21cbed7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
*
@@ -6,44 +7,6 @@
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -169,6 +132,7 @@
compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
#address-cells = <1>;
#size-cells = <1>;
+ read-only;
sn: sn@14 {
reg = <0x14 0x10>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
index 011e8e08e429..7d5709c37e95 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
@@ -1,45 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -52,6 +13,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
index 818954b1d57f..4cf7f6e80c6a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -54,6 +17,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index ee4ada61c59c..54954b314a45 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -53,6 +16,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
@@ -310,7 +274,7 @@
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
- max-frequency = <200000000>;
+ max-frequency = <100000000>;
non-removable;
disable-wp;
cap-mmc-highspeed;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
index 09f34f7ef084..9d2406a7c4fa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
index ae3194663d64..56e0dd1ff55c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 932158a778ef..ce862266b9aa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxbb.dtsi"
@@ -47,6 +10,7 @@
/ {
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
index 62fb4968d680..c928adf85388 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
index 9a9663abdf5c..e81e1d68b5fa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
index 2fe167b2609d..a8fca0c6903f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 1fe8e24cf675..93a4acf2c46c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxbb.dtsi"
@@ -47,6 +10,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
index 1878ac2b2b83..2bfe69902552 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
@@ -1,92 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
-#include "meson-gxbb-p20x.dtsi"
+#include "meson-gxbb-wetek.dtsi"
/ {
compatible = "wetek,hub", "amlogic,meson-gxbb";
model = "WeTek Hub";
-
- leds {
- compatible = "gpio-leds";
-
- system {
- label = "wetek-play:system-status";
- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- panic-indicator;
- };
- };
-};
-
-&cvbs_connector {
- status = "disabled";
-};
-
-&ethmac {
- status = "okay";
- pinctrl-0 = <&eth_rgmii_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&eth_phy0>;
- phy-mode = "rgmii";
-
- amlogic,tx-delay-ns = <2>;
-
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- eth_phy0: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- };
- };
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
index f7144fd5e03f..0038522315de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
@@ -1,49 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
-#include "meson-gxbb-p20x.dtsi"
+#include "meson-gxbb-wetek.dtsi"
#include <dt-bindings/input/input.h>
/ {
@@ -51,15 +14,6 @@
model = "WeTek Play 2";
leds {
- compatible = "gpio-leds";
-
- system {
- label = "wetek-play:system-status";
- gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- panic-indicator;
- };
-
wifi {
label = "wetek-play:wifi-status";
gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
@@ -85,82 +39,18 @@
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
};
};
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
};
-&ethmac {
+&i2c_A {
status = "okay";
- pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
-
- phy-handle = <&eth_phy0>;
- phy-mode = "rgmii";
-
- amlogic,tx-delay-ns = <2>;
-
- snps,reset-gpio = <&gpio GPIOZ_14 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- eth_phy0: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- };
- };
};
-&hdmi_tx {
+&usb1_phy {
status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
};
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c_A {
+&usb1 {
status = "okay";
- pinctrl-0 = <&i2c_a_pins>;
- pinctrl-names = "default";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
new file mode 100644
index 000000000000..70325b273bd2
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+#include "meson-gxbb.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = &ethmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ system {
+ label = "wetek-play:system-status";
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+ };
+
+ usb_pwr: regulator-usb-pwrs {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB_PWR";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ethmac {
+ status = "okay";
+ pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&eth_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ eee-broken-1000t;
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vcc_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 3290a4dc3522..562c26a0ba33 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gx.dtsi"
@@ -284,14 +247,17 @@
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ assigned-clocks = <&clkc CLKID_GP0_PLL>,
+ <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ assigned-clock-parents = <0>, /* Do Nothing */
+ <&clkc CLKID_GP0_PLL>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
+ assigned-clock-rates = <744000000>,
+ <0>, /* Do Nothing */
+ <744000000>,
<0>; /* Do Nothing */
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
index f06cc234693b..eb327664a4d8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 BayLibre SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&apb {
@@ -30,14 +29,17 @@
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ assigned-clocks = <&clkc CLKID_GP0_PLL>,
+ <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ assigned-clock-parents = <0>, /* Do Nothing */
+ <&clkc CLKID_GP0_PLL>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
+ assigned-clock-rates = <744000000>,
+ <0>, /* Do Nothing */
+ <744000000>,
<0>; /* Do Nothing */
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 4f3f03fc31b0..a9f9bb90a877 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
index 95992cf1fe61..80a231476b80 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
index 5a90e30c1006..43321919547a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxl.dtsi"
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
index e82582574160..f1c410e2da2b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Carlo Caione
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@kernel.org>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -16,6 +15,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index 71a6e1ce7ad5..d32cf3846370 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -29,6 +28,7 @@
aliases {
serial2 = &uart_AO_B;
+ ethernet0 = &ethmac;
};
gpio-keys-polled {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index 9671f1e3c74a..22bf37404ff1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -18,6 +17,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index 271f14279180..69c721a70e44 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -52,6 +15,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
index 6e2bf858291c..5896e8a5d86b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index 7005068346a0..0a0953fbc7d4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
* Based on meson-gx-p23x-q20x.dtsi:
@@ -5,8 +6,6 @@
* Author: Carlo Caione <carlo@endlessm.com>
* - Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/* Common DTSI for devices which are based on the P212 reference board. */
@@ -17,6 +16,7 @@
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 3314a0b3dad9..40c19f69e9dc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxl.dtsi"
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index c8514110b9da..e1a39cbed8c9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gx.dtsi"
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index 1448c3dba08e..4fd46c1546a7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
* Copyright (c) 2017 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -59,8 +58,6 @@
1 1
2 2
3 3>;
- cooling-min-level = <0>;
- cooling-max-level = <3>;
#cooling-cells = <2>;
};
@@ -209,14 +206,10 @@
};
&cpu0 {
- cooling-min-level = <0>;
- cooling-max-level = <6>;
#cooling-cells = <2>;
};
&cpu4 {
- cooling-min-level = <0>;
- cooling-max-level = <4>;
#cooling-cells = <2>;
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index e7a228f6cc7e..f7a1cffab4a8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -54,6 +17,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index 388fac4f2d97..101417298a1d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
index 95e11d7faab8..8d132b17514a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
index a5e9b955d5ed..7212dc4531e4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016-2017 Andreas Färber
*
@@ -8,44 +9,6 @@
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -58,6 +21,7 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = &ethmac;
};
chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
index dc37eecb9514..e2ea6753263b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Copyright (c) 2017 Oleg <balbes-150@yandex.ru>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index 19a798d2ae2f..d076a7c425dd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxl.dtsi"
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index f165f04db0c9..eb749c50a736 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -68,10 +68,29 @@
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
ranges = <0 0 0 0x2c1c0000 0 0x40000>;
+
v2m_0: v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
- reg = <0 0 0 0x1000>;
+ reg = <0 0 0 0x10000>;
+ };
+
+ v2m@10000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0 0x10000 0 0x10000>;
+ };
+
+ v2m@20000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0 0x20000 0 0x10000>;
+ };
+
+ v2m@30000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0 0x30000 0 0x10000>;
};
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index a77462da4a36..a1e3194b7483 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/sound/samsung-i2s.h>
/ {
aliases {
@@ -112,8 +113,8 @@
sound {
compatible = "samsung,tm2-audio";
- audio-codec = <&wm5110>;
- i2s-controller = <&i2s0>;
+ audio-codec = <&wm5110>, <&hdmi>;
+ i2s-controller = <&i2s0 0>, <&i2s1 0>;
audio-amplifier = <&max98504>;
mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
model = "wm5110";
@@ -217,8 +218,40 @@
};
&cmu_aud {
- assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
- assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
+ assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
+ <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
+ <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
+ <&cmu_top CLK_MOUT_AUD_PLL>,
+ <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
+ <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
+ <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
+ <&cmu_top CLK_MOUT_SCLK_SPDIF>,
+
+ <&cmu_aud CLK_DIV_AUD_CA5>,
+ <&cmu_aud CLK_DIV_ACLK_AUD>,
+ <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
+ <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
+ <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
+ <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
+ <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
+ <&cmu_top CLK_DIV_SCLK_AUDIO0>,
+ <&cmu_top CLK_DIV_SCLK_AUDIO1>,
+ <&cmu_top CLK_DIV_SCLK_PCM1>,
+ <&cmu_top CLK_DIV_SCLK_I2S1>;
+
+ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
+ <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
+ <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
+ <&cmu_top CLK_FOUT_AUD_PLL>,
+ <&cmu_top CLK_MOUT_AUD_PLL>,
+ <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
+ <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
+ <&cmu_top CLK_SCLK_AUDIO0>;
+
+ assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+ <196608001>, <65536001>, <32768001>, <49152001>,
+ <2048001>, <24576001>, <196608001>,
+ <24576001>, <98304001>, <2048001>, <49152001>;
};
&cmu_fsys {
@@ -267,6 +300,11 @@
<&cmu_top CLK_MOUT_BUS_PLL_USER>;
};
+&cmu_top {
+ assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
+ assigned-clock-rates = <196608001>;
+};
+
&cpu0 {
cpu-supply = <&buck3_reg>;
};
@@ -779,9 +817,22 @@
clocks = <&pmu_system_controller 0>;
clock-names = "xtal";
- port {
- mhl_to_hdmi: endpoint {
- remote-endpoint = <&hdmi_to_mhl>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mhl_to_hdmi: endpoint {
+ remote-endpoint = <&hdmi_to_mhl>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mhl_to_musb_con: endpoint {
+ remote-endpoint = <&musb_con_to_mhl>;
+ };
};
};
};
@@ -798,6 +849,25 @@
muic: max77843-muic {
compatible = "maxim,max77843-muic";
+
+ musb_con: musb_connector {
+ compatible = "samsung,usb-connector-11pin",
+ "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ musb_con_to_mhl: endpoint {
+ remote-endpoint = <&mhl_to_musb_con>;
+ };
+ };
+ };
+ };
};
regulators {
@@ -838,6 +908,12 @@
status = "okay";
};
+&i2s1 {
+ assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
+ status = "okay";
+};
+
&mshc_0 {
status = "okay";
mmc-hs200-1_8v;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 62f276970174..c0231d077fa6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -969,6 +969,7 @@
ddc = <&hsi2c_11>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,sysreg-phandle = <&syscon_disp>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -1311,6 +1312,25 @@
status = "disabled";
};
+ i2s1: i2s@14d60000 {
+ compatible = "samsung,exynos7-i2s";
+ reg = <0x14d60000 0x100>;
+ dmas = <&pdma0 31 &pdma0 30>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_NONE>;
+ clocks = <&cmu_peric CLK_PCLK_I2S1>,
+ <&cmu_peric CLK_PCLK_I2S1>,
+ <&cmu_peric CLK_SCLK_I2S1>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ #clock-cells = <1>;
+ samsung,supports-6ch;
+ samsung,supports-rstclr;
+ samsung,supports-tdm;
+ samsung,supports-low-rfs;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
pwm: pwm@14dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x14dd0000 0x100>;
@@ -1639,7 +1659,7 @@
power-domains = <&pd_aud>;
};
- i2s0: i2s0@11440000 {
+ i2s0: i2s@11440000 {
compatible = "samsung,exynos7-i2s";
reg = <0x11440000 0x100>;
dmas = <&adma 0 &adma 2>;
@@ -1651,9 +1671,11 @@
<&cmu_aud CLK_SCLK_AUD_I2S>,
<&cmu_aud CLK_SCLK_I2S_BCLK>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ #clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
power-domains = <&pd_aud>;
+ #sound-dai-cells = <1>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 22723527e626..00dd89b92b42 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -23,7 +23,7 @@
};
chosen {
- linux,stdout-path = &serial_2;
+ stdout-path = &serial_2;
};
memory@40000000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 82b272fb41b9..bb788eddf9f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -70,6 +70,24 @@
reg = <0x0>;
clocks = <&clockgen 1 0>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_PH20>;
+ };
+ };
+
+ idle-states {
+ /*
+ * PSCI node is not added default, U-boot will add missing
+ * parts if it determines to use PSCI.
+ */
+ entry-method = "arm,psci";
+
+ CPU_PH20: cpu-ph20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PH20";
+ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <1000>;
+ min-residency-us = <3000>;
};
};
@@ -118,6 +136,37 @@
mask = <0x02>;
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -304,37 +353,6 @@
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 380e7c713395..1109f22bda5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -81,6 +81,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu1: cpu@1 {
@@ -89,6 +90,7 @@
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu2: cpu@2 {
@@ -97,6 +99,7 @@
reg = <0x2>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
};
cpu3: cpu@3 {
@@ -105,6 +108,7 @@
reg = <0x3>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
};
l2: l2-cache {
@@ -112,6 +116,23 @@
};
};
+ idle-states {
+ /*
+ * PSCI node is not added default, U-boot will add missing
+ * parts if it determines to use PSCI.
+ */
+ entry-method = "arm,psci";
+
+ CPU_PH20: cpu-ph20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PH20";
+ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <1000>;
+ min-residency-us = <3000>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
@@ -159,6 +180,37 @@
mask = <0x02>;
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>, /* Physical Secure PPI */
@@ -342,37 +394,6 @@
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&tmu 3>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
qman: qman@1880000 {
compatible = "fsl,qman";
reg = <0x0 0x1880000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 06b5e12d04d8..136ebfa9b333 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -122,7 +122,7 @@
CPU_PH20: cpu-ph20 {
compatible = "arm,idle-state";
idle-state-name = "PH20";
- arm,psci-suspend-param = <0x00010000>;
+ arm,psci-suspend-param = <0x0>;
entry-latency-us = <1000>;
exit-latency-us = <1000>;
min-residency-us = <3000>;
@@ -131,6 +131,8 @@
memory@80000000 {
device_type = "memory";
+ /* Real size will be filled by bootloader */
+ reg = <0x0 0x80000000 0x0 0x0>;
};
sysclk: sysclk {
@@ -147,6 +149,37 @@
mask = <0x02>;
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
@@ -362,37 +395,6 @@
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
- thermal-sensors = <&tmu 3>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
dspi: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 4fc150cd4ca5..1c6556bcfddf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -130,7 +130,7 @@
CPU_PH20: cpu-ph20 {
compatible = "arm,idle-state";
idle-state-name = "PH20";
- arm,psci-suspend-param = <0x00010000>;
+ arm,psci-suspend-param = <0x0>;
entry-latency-us = <1000>;
exit-latency-us = <1000>;
min-residency-us = <3000>;
@@ -158,6 +158,44 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu4 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
@@ -315,44 +353,6 @@
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
-
- map1 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu4 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
@@ -612,6 +612,62 @@
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ cluster1_core0_watchdog: wdt@c000000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core1_watchdog: wdt@c010000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core2_watchdog: wdt@c020000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc020000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core3_watchdog: wdt@c030000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc030000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core0_watchdog: wdt@c100000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc100000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core1_watchdog: wdt@c110000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc110000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core2_watchdog: wdt@c120000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc120000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core3_watchdog: wdt@c130000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc130000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
};
firmware {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index aeaef01d375f..0884e1a77901 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -143,7 +143,7 @@
CPU_PW20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
- arm,psci-suspend-param = <0x00010000>;
+ arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
index b2374469a830..1de618801c73 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
@@ -140,21 +140,21 @@
&dspi {
status = "okay";
- dflash0: n25q128a {
+ dflash0: n25q128a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
- dflash1: sst25wf040b {
+ dflash1: sst25wf040b@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <1>;
};
- dflash2: en25s64 {
+ dflash2: en25s64@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
@@ -177,7 +177,7 @@
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
- reg = <0>;
+ reg = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index f3a40af33af8..137ef4dfc3e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -111,6 +111,55 @@
mask = <0x2>;
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 4>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map2 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu4 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map3 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu6 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
@@ -194,55 +243,6 @@
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&tmu 4>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu2 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- map2 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu4 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- map3 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu6 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
serial0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
index c3c2be4f5072..ae15307f6e8b 100644
--- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
@@ -68,4 +68,10 @@
reg = <0x80000 0x4000>, <0x4080000 0x4000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ bman-portal@90000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x90000 0x4000>, <0x4090000 0x4000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
index 2a9aa060efda..6a93a4a9be0e 100644
--- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
@@ -77,4 +77,11 @@
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
cell-index = <8>;
};
+
+ qportal9: qman-portal@90000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x90000 0x4000>, <0x4090000 0x4000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ cell-index = <9>;
+ };
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 63d4f9dca77f..ec3eb8e33a3a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -100,11 +100,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
capacity-dmips-mhz = <1024>;
};
@@ -114,11 +110,7 @@
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
capacity-dmips-mhz = <1024>;
};
@@ -128,11 +120,7 @@
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
capacity-dmips-mhz = <1024>;
};
@@ -142,25 +130,13 @@
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
- cpu-idle-states = <
- &CPU_NAP
- &CPU_SLEEP
- &CLUSTER_SLEEP_1
- >;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
capacity-dmips-mhz = <1024>;
};
idle-states {
entry-method = "psci";
- CPU_NAP: cpu-nap {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0000001>;
- entry-latency-us = <7>;
- exit-latency-us = <2>;
- min-residency-us = <15>;
- };
-
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
@@ -922,7 +898,6 @@
#size-cells = <0>;
cd-inverted;
compatible = "hisilicon,hi3660-dw-mshc";
- num-slots = <1>;
bus-width = <0x4>;
disable-wp;
cap-sd-highspeed;
@@ -960,7 +935,6 @@
compatible = "hisilicon,hi3660-dw-mshc";
reg = <0x0 0xff3ff000 0x0 0x1000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- num-slots = <1>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
<&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
clock-names = "ciu", "biu";
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 047641fe294c..724a0d3b7683 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -299,7 +299,9 @@
/* GPIO blocks 16 thru 19 do not appear to be routed to pins */
dwmmc_0: dwmmc0@f723d000 {
+ max-frequency = <150000000>;
cap-mmc-highspeed;
+ mmc-hs200-1_8v;
non-removable;
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 6a180d1926e8..586b281cd531 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -88,8 +88,6 @@
next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
- cooling-min-level = <4>;
- cooling-max-level = <0>;
#cooling-cells = <2>; /* min followed by max */
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <311>;
@@ -817,6 +815,14 @@
pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
};
+ watchdog0: watchdog@f8005000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xf8005000 0x0 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
+ clock-names = "apb_pclk";
+ };
+
tsensor: tsensor@0,f7030700 {
compatible = "hisilicon,tsensor";
reg = <0x0 0xf7030700 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index a049b64f2101..35202ebe62a7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -291,6 +291,13 @@
#interrupt-cells = <2>;
num-pins = <128>;
};
+
+ mbigen_pcie0: intc_pcie0 {
+ msi-parent = <&its_dsa 0x40085>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <10>;
+ };
};
mbigen_dsa@c0080000 {
@@ -312,6 +319,31 @@
};
};
+ /**
+ * HiSilicon erratum 161010801: This describes the limitation
+ * of HiSilicon platforms hip06/hip07 to support the SMMUv3
+ * mappings for PCIe MSI transactions.
+ * PCIe controller on these platforms has to differentiate the
+ * MSI payload against other DMA payload and has to modify the
+ * MSI payload. This makes it difficult for these platforms to
+ * have a SMMU translation for MSI. In order to workaround this,
+ * ARM SMMUv3 driver requires a quirk to treat the MSI regions
+ * separately. Such a quirk is currently missing for DT based
+ * systems. Hence please make sure that the smmu pcie node on
+ * hip06 is disabled as this will break the PCIe functionality
+ * when iommu-map entry is used along with the PCIe node.
+ * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
+ */
+ smmu0: smmu_pcie {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xa0040000 0x0 0x20000>;
+ #iommu-cells = <1>;
+ dma-coherent;
+ smmu-cb-memtype = <0x0 0x1>;
+ hisilicon,broken-prefetch-cmd;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -676,6 +708,30 @@
<637 1>,<638 1>,<639 1>;
status = "disabled";
};
+
+ pcie0: pcie@a0090000 {
+ compatible = "hisilicon,hip06-pcie-ecam";
+ reg = <0 0xb0000000 0 0x2000000>,
+ <0 0xa0090000 0 0x10000>;
+ bus-range = <0 31>;
+ msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
+ msi-map-mask = <0xffff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
+ 0x5ff0000 0x01000000 0 0 0 0xb7ff0000
+ 0 0x10000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
+ 0x0 0 0 2 &mbigen_pcie0 650 4
+ 0x0 0 0 3 &mbigen_pcie0 650 4
+ 0x0 0 0 4 &mbigen_pcie0 650 4>;
+ status = "disabled";
+ };
+
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 2c01a21c3665..0600a6a84ab7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1083,6 +1083,31 @@
};
};
+ /**
+ * HiSilicon erratum 161010801: This describes the limitation
+ * of HiSilicon platforms hip06/hip07 to support the SMMUv3
+ * mappings for PCIe MSI transactions.
+ * PCIe controller on these platforms has to differentiate the
+ * MSI payload against other DMA payload and has to modify the
+ * MSI payload. This makes it difficult for these platforms to
+ * have a SMMU translation for MSI. In order to workaround this,
+ * ARM SMMUv3 driver requires a quirk to treat the MSI regions
+ * separately. Such a quirk is currently missing for DT based
+ * systems. Hence please make sure that the smmu pcie node on
+ * hip07 is disabled as this will break the PCIe functionality
+ * when iommu-map entry is used along with the PCIe node.
+ * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
+ */
+ smmu0: smmu_pcie {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xa0040000 0x0 0x20000>;
+ #iommu-cells = <1>;
+ dma-coherent;
+ smmu-cb-memtype = <0x0 0x1>;
+ hisilicon,broken-prefetch-cmd;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -1127,6 +1152,12 @@
reg = <0x0 0xc0000000 0x0 0x10000>;
};
+ dsa_cpld: dsa_cpld@78000010 {
+ compatible = "syscon";
+ reg = <0x0 0x78000010 0x0 0x100>;
+ reg-io-width = <2>;
+ };
+
pcie_subctl: pcie_subctl@a0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0x0 0xa0000000 0x0 0x10000>;
@@ -1258,6 +1289,7 @@
port@0 {
reg = <0>;
serdes-syscon = <&serdes_ctrl>;
+ cpld-syscon = <&dsa_cpld 0x0>;
port-rst-offset = <0>;
port-mode-offset = <0>;
mc-mac-mask = [ff f0 00 00 00 00];
@@ -1267,6 +1299,7 @@
port@1 {
reg = <1>;
serdes-syscon= <&serdes_ctrl>;
+ cpld-syscon = <&dsa_cpld 0x4>;
port-rst-offset = <1>;
port-mode-offset = <1>;
mc-mac-mask = [ff f0 00 00 00 00];
diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
index 11226f7b9ed9..dc1182ec9fa1 100644
--- a/arch/arm64/boot/dts/marvell/armada-371x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 371x family of SoCs
* (also named 88F3710)
@@ -6,43 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-37xx.dtsi"
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 0f3468e777f7..f2cc00594d64 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada 3720 development board
* (DB-88F3720-DDR3)
@@ -5,44 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* This file is compatible with the version 1.4 and the version 2.0 of
* the board, however the CON numbers are different between the 2
* version
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index bdfb5553ddb5..ef7fd2ca2515 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -1,46 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board
* Copyright (C) 2016 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
index 2554e0baea6b..97558a64e276 100644
--- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 372x family of SoCs
* (also named 88F3720)
@@ -6,43 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-37xx.dtsi"
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 375026867342..97207a61bc79 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 37xx family of SoCs.
*
@@ -5,43 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 4ab012991d9d..4e46326dd123 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
* one CP110.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 3ae05eee2c9a..d6bec058a30a 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada 7040 Development board platform
*/
@@ -162,36 +123,48 @@
};
};
-&cp0_nand {
+&cp0_nand_controller {
/*
* SPI on CPM and NAND have common pins on this board. We can
- * use only one at a time. To enable the NAND (whihch will
+ * use only one at a time. To enable the NAND (which will
* disable the SPI), the "status = "okay";" line have to be
* added here.
*/
- num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition@200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
+
+ nand@0 {
+ reg = <0>;
+ label = "pxa3xx_nand-0";
+ nand-rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+
+ };
};
};
-
&cp0_spi1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index cbe460b8fc00..47247215770d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
* one CP110.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index f63b4fbd642b..e5c6d7c25819 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for the Armada 70x0 SoC
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 3318d6b0214b..ba1307c0fadb 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
* two CP110.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index dba55baff20f..5689fb23bbab 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada 8040 Development board platform
*/
@@ -279,27 +240,35 @@
* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
* MDIO signal of CP1.
*/
-&cp1_nand {
- num-cs = <1>;
+&cp1_nand_controller {
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-enable-arbiter;
- marvell,system-controller = <&cp1_syscon0>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition@200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
+
+ nand@0 {
+ reg = <0>;
+ nand-rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 626e9d0462c3..81de03ef860d 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for MACCHIATOBin Armada 8040 community board platform
*/
@@ -49,7 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Marvell 8040 MACHIATOBin";
+ model = "Marvell 8040 MACCHIATOBin";
compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
@@ -163,6 +124,13 @@
};
};
+/* J25 UART header */
+&cp0_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart1_pins>;
+ status = "okay";
+};
+
&cp0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&cp0_ge_mdio_pins>;
@@ -195,6 +163,10 @@
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
+ cp0_uart1_pins: uart1-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "uart1";
+ };
cp0_xhci_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
@@ -290,6 +262,17 @@
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
+ cp1_uart0_pins: uart0-pins {
+ marvell,pins = "mpp6", "mpp7";
+ marvell,function = "uart0";
+ };
+};
+
+/* J27 UART header */
+&cp1_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_uart0_pins>;
+ status = "okay";
};
&cp1_sata0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 83d2b40e5981..7699b19224c2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
* two CP110.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-8080-db.dts b/arch/arm64/boot/dts/marvell/armada-8080-db.dts
index 85b58a19a9fb..4ba158f415ce 100644
--- a/arch/arm64/boot/dts/marvell/armada-8080-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8080-db.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada-8080 Development board platform
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi
index d5535b716735..299e814d1ded 100644
--- a/arch/arm64/boot/dts/marvell/armada-8080.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8080.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index e9c84a1d3c4d..8129b40f12a4 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for the Armada 80x0 SoC family
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index b98ea137371d..64b5e61a698e 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada AP806.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 116164ff260f..746e792767f5 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada AP806.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index f9b66b81f9fc..176e38d54872 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada AP806.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
index 7f0661e12f5e..7d00ae78fc79 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada AP810 OCTA cores.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
index 7e6f039f0f80..8107d120a8a7 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
* Device Tree file for Marvell Armada AP810.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi
index c6dd1d81c68d..d5e8aedec188 100644
--- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index a8af4136dbe7..48cad7919efa 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -1,9 +1,7 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
- */
-
-/*
+ *
* Device Tree file for Marvell Armada CP110.
*/
@@ -213,7 +211,9 @@
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 22>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 22>,
+ <&CP110_LABEL(clk) 1 16>;
status = "disabled";
};
@@ -223,7 +223,9 @@
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 23>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 23>,
+ <&CP110_LABEL(clk) 1 16>;
status = "disabled";
};
@@ -232,7 +234,8 @@
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 15>;
+ clocks = <&CP110_LABEL(clk) 1 15>,
+ <&CP110_LABEL(clk) 1 16>;
status = "disabled";
};
@@ -241,7 +244,9 @@
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
- clocks = <&CP110_LABEL(clk) 1 8>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 8>,
+ <&CP110_LABEL(clk) 1 14>;
};
CP110_LABEL(xor1): xor@6c0000 {
@@ -249,7 +254,9 @@
reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
- clocks = <&CP110_LABEL(clk) 1 7>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 7>,
+ <&CP110_LABEL(clk) 1 14>;
};
CP110_LABEL(spi0): spi@700600 {
@@ -257,7 +264,9 @@
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
- clocks = <&CP110_LABEL(clk) 1 21>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
@@ -266,7 +275,9 @@
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&CP110_LABEL(clk) 1 21>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
@@ -276,7 +287,9 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 21>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
@@ -286,23 +299,75 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 21>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart0): serial@702000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702000 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart1): serial@702100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702100 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart2): serial@702200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702200 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
- CP110_LABEL(nand): nand@720000 {
+ CP110_LABEL(uart3): serial@702300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702300 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(clk) 1 21>,
+ <&CP110_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand_controller): nand@720000 {
/*
* Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
- compatible = "marvell,armada-8k-nand",
- "marvell,armada370-nand";
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 2>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 2>,
+ <&CP110_LABEL(clk) 1 17>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
status = "disabled";
};
@@ -312,7 +377,9 @@
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 25>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 25>,
+ <&CP110_LABEL(clk) 1 17>;
status = "okay";
};
@@ -337,7 +404,9 @@
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
- clocks = <&CP110_LABEL(clk) 1 26>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 26>,
+ <&CP110_LABEL(clk) 1 17>;
dma-coherent;
};
};
@@ -364,7 +433,8 @@
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&CP110_LABEL(clk) 1 13>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
@@ -391,7 +461,8 @@
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&CP110_LABEL(clk) 1 11>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
@@ -418,7 +489,8 @@
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
- clocks = <&CP110_LABEL(clk) 1 12>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 10f9c76cd105..4ce9d6ca0bf7 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -41,6 +41,10 @@
};
+&auxadc {
+ status = "okay";
+};
+
&cpu0 {
proc-supply = <&cpus_fixed_vproc0>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index fdf66f4fe7c3..9d88f41aefa0 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -289,6 +289,15 @@
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt2712-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
new file mode 100644
index 000000000000..53b335d2de5f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for MediaTek MT6380 regulator
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Chenglin Xu <chenglin.xu@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ */
+
+&pwrap {
+ regulators {
+ compatible = "mediatek,mt6380-regulator";
+
+ mt6380_vcpu_reg: buck-vcore1 {
+ regulator-name = "vcore1";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1393750>;
+ regulator-ramp-delay = <6250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vcore_reg: buck-vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1393750>;
+ regulator-ramp-delay = <6250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vrf_reg: buck-vrf {
+ regulator-name = "vrf";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1575000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vm_reg: ldo-vm {
+ regulator-name = "vm";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_va_reg: ldo-va {
+ regulator-name = "va";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vphy_reg: ldo-vphy {
+ regulator-name = "vphy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vddr_reg: ldo-vddr {
+ regulator-name = "vddr";
+ regulator-min-microvolt = <1240000>;
+ regulator-max-microvolt = <1840000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vt_reg: ldo-vt {
+ regulator-name = "vt";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index c08309df2cc7..45d8655ee423 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -7,7 +7,11 @@
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
#include "mt7622.dtsi"
+#include "mt6380.dtsi"
/ {
model = "MediaTek MT7622 RFB1 board";
@@ -17,11 +21,476 @@
bootargs = "console=ttyS0,115200n1";
};
+ cpus {
+ cpu@0 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+
+ cpu@1 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ factory {
+ label = "factory";
+ linux,code = <BTN_0>;
+ gpios = <&pio 0 0>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 102 0>;
+ };
+ };
+
memory {
reg = <0 0x40000000 0 0x3F000000>;
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+
+ pcie@0,0 {
+ status = "okay";
+ };
+};
+
+&pio {
+ /* eMMC is shared pin with parallel NAND */
+ emmc_pins_default: emmc-pins-default {
+ mux {
+ function = "emmc", "emmc_rst";
+ groups = "emmc";
+ };
+
+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+ * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+ * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+ */
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+ };
+
+ emmc_pins_uhs: emmc-pins-uhs {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ drive-strength = <4>;
+ bias-pull-down;
+ };
+ };
+
+ eth_pins: eth-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio", "rgmii_via_gmac2";
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c2_0";
+ };
+ };
+
+ i2s1_pins: i2s1-pins {
+ mux {
+ function = "i2s";
+ groups = "i2s_out_bclk_ws_mclk",
+ "i2s1_in_data",
+ "i2s1_out_data";
+ };
+ };
+
+ irrx_pins: irrx-pins {
+ mux {
+ function = "ir";
+ groups = "ir_1_rx";
+ };
+ };
+
+ irtx_pins: irtx-pins {
+ mux {
+ function = "ir";
+ groups = "ir_1_tx";
+ };
+ };
+
+ /* Parallel nand is shared pin with eMMC */
+ parallel_nand_pins: parallel-nand-pins {
+ mux {
+ function = "flash";
+ groups = "par_nand";
+ };
+ };
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie0_pad_perst",
+ "pcie0_1_waken",
+ "pcie0_1_clkreq";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie1_pad_perst",
+ "pcie1_0_waken",
+ "pcie1_0_clkreq";
+ };
+ };
+
+ pmic_bus_pins: pmic-bus-pins {
+ mux {
+ function = "pmic";
+ groups = "pmic_bus";
+ };
+ };
+
+ pwm7_pins: pwm1-2-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm_ch7_2";
+ };
+ };
+
+ wled_pins: wled-pins {
+ mux {
+ function = "led";
+ groups = "wled";
+ };
+ };
+
+ sd0_pins_default: sd0-pins-default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+ * DAT2, DAT3, CMD, CLK for SD respectively.
+ */
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up;
+ };
+ };
+
+ sd0_pins_uhs: sd0-pins-uhs {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "I2S3_OUT";
+ bias-pull-down;
+ };
+ };
+
+ /* Serial NAND is shared pin with SPI-NOR */
+ serial_nand_pins: serial-nand-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ spic0_pins: spic0-pins {
+ mux {
+ function = "spi";
+ groups = "spic0_0";
+ };
+ };
+
+ spic1_pins: spic1-pins {
+ mux {
+ function = "spi";
+ groups = "spic1_0";
+ };
+ };
+
+ /* SPI-NOR is shared pin with serial NAND */
+ spi_nor_pins: spi-nor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ /* serial NAND is shared pin with SPI-NOR */
+ serial_nand_pins: serial-nand-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_1_tx_rx" ;
+ };
+ };
+
+ watchdog_pins: watchdog-pins {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+&bch {
+ status = "disabled";
+};
+
+&btif {
+ status = "okay";
+};
+
+&cir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&irrx_pins>;
+ status = "okay";
+};
+
+&eth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_pins>;
+ status = "okay";
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-handle = <&phy5>;
+ };
+
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ phy-mode = "sgmii";
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&emmc_pins_default>;
+ pinctrl-1 = <&emmc_pins_uhs>;
+ status = "okay";
+ bus-width = <8>;
+ max-frequency = <50000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+ non-removable;
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sd0_pins_default>;
+ pinctrl-1 = <&sd0_pins_uhs>;
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ r_smpl = <1>;
+ cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_3p3v>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&parallel_nand_pins>;
+ status = "disabled";
+};
+
+&nor_flash {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nor_pins>;
+ status = "disabled";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm7_pins>;
+ status = "okay";
+};
+
+&pwrap {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_bus_pins>;
+
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sata_phy {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic0_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic1_pins>;
+ status = "okay";
+};
+
+&ssusb {
+ vusb33-supply = <&reg_3p3v>;
+ vbus-supply = <&reg_5v>;
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index b111fec2ed9d..e9d5130df8d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -8,6 +8,11 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/mt7622-power.h>
+#include <dt-bindings/reset/mt7622-reset.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "mediatek,mt7622";
@@ -15,6 +20,50 @@
#address-cells = <2>;
#size-cells = <2>;
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-300000000 {
+ opp-hz = /bits/ 64 <30000000>;
+ opp-microvolt = <950000>;
+ };
+
+ opp-437500000 {
+ opp-hz = /bits/ 64 <437500000>;
+ opp-microvolt = <1000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-812500000 {
+ opp-hz = /bits/ 64 <812500000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-1025000000 {
+ opp-hz = /bits/ 64 <1025000000>;
+ opp-microvolt = <1150000>;
+ };
+
+ opp-1137500000 {
+ opp-hz = /bits/ 64 <1137500000>;
+ opp-microvolt = <1200000>;
+ };
+
+ opp-1262500000 {
+ opp-hz = /bits/ 64 <1262500000>;
+ opp-microvolt = <1250000>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-microvolt = <1310000>;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -23,6 +72,11 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
+ clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
@@ -31,21 +85,26 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
+ clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
};
- uart_clk: dummy25m {
+ pwrap_clk: dummy40m {
compatible = "fixed-clock";
+ clock-frequency = <40000000>;
#clock-cells = <0>;
- clock-frequency = <25000000>;
};
- bus_clk: dummy280m {
+ clk25m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <280000000>;
+ clock-frequency = <25000000>;
+ clock-output-names = "clkxtal";
};
psci {
@@ -65,6 +124,58 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ cpu_passive: cpu-passive {
+ temperature = <47000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_active: cpu-active {
+ temperature = <67000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu-hot {
+ temperature = <87000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu-crit {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_active>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map2 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -78,6 +189,58 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ infracfg: infracfg@10000000 {
+ compatible = "mediatek,mt7622-infracfg",
+ "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pwrap: pwrap@10001000 {
+ compatible = "mediatek,mt7622-pwrap";
+ reg = <0 0x10001000 0 0x250>;
+ reg-names = "pwrap";
+ clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
+ clock-names = "spi", "wrap";
+ resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pericfg: pericfg@10002000 {
+ compatible = "mediatek,mt7622-pericfg",
+ "syscon";
+ reg = <0 0x10002000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt7622-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ clock-names = "hif_sel";
+ };
+
+ cir: cir@10009000 {
+ compatible = "mediatek,mt7622-cir";
+ reg = <0 0x10009000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_IRRX_PD>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "clk", "bus";
+ status = "disabled";
+ };
+
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt7622-sysirq",
"mediatek,mt6577-sysirq";
@@ -87,6 +250,62 @@
reg = <0 0x10200620 0 0x20>;
};
+ efuse: efuse@10206000 {
+ compatible = "mediatek,mt7622-efuse",
+ "mediatek,efuse";
+ reg = <0 0x10206000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@198 {
+ reg = <0x198 0xc>;
+ };
+ };
+
+ apmixedsys: apmixedsys@10209000 {
+ compatible = "mediatek,mt7622-apmixedsys",
+ "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen@10210000 {
+ compatible = "mediatek,mt7622-topckgen",
+ "syscon";
+ reg = <0 0x10210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt7622-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_TRNG>;
+ clock-names = "rng";
+ };
+
+ pio: pinctrl@10211000 {
+ compatible = "mediatek,mt7622-pinctrl";
+ reg = <0 0x10211000 0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ watchdog: watchdog@10212000 {
+ compatible = "mediatek,mt7622-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10212000 0 0x800>;
+ };
+
+ rtc: rtc@10212800 {
+ compatible = "mediatek,mt7622-rtc",
+ "mediatek,soc-rtc";
+ reg = <0 0x10212800 0 0x200>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_RTC>;
+ clock-names = "rtc";
+ };
+
gic: interrupt-controller@10300000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -98,13 +317,459 @@
<0 0x10360000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt7622-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC_PD>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>, <&bus_clk>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART1_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART1_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART2_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11005000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART3_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt7622-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&pericfg CLK_PERI_PWM_PD>,
+ <&pericfg CLK_PERI_PWM1_PD>,
+ <&pericfg CLK_PERI_PWM2_PD>,
+ <&pericfg CLK_PERI_PWM3_PD>,
+ <&pericfg CLK_PERI_PWM4_PD>,
+ <&pericfg CLK_PERI_PWM5_PD>,
+ <&pericfg CLK_PERI_PWM6_PD>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
+ "pwm5", "pwm6";
+ status = "disabled";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt7622-i2c";
+ reg = <0 0x11007000 0 0x90>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt7622-i2c";
+ reg = <0 0x11008000 0 0x90>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt7622-i2c";
+ reg = <0 0x11009000 0 0x90>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI0_SEL>,
+ <&pericfg CLK_PERI_SPI0_PD>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ #thermal-sensor-cells = <1>;
+ compatible = "mediatek,mt7622-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM_PD>,
+ <&pericfg CLK_PERI_AUXADC_PD>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
+ reset-names = "therm";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
+ btif: serial@1100c000 {
+ compatible = "mediatek,mt7622-btif",
+ "mediatek,mtk-btif";
+ reg = <0 0x1100c000 0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_BTIF_PD>;
+ clock-names = "main";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7622-nfc";
+ reg = <0 0x1100D000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt7622-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
+ nor_flash: spi@11014000 {
+ compatible = "mediatek,mt7622-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x11014000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@11016000 {
+ compatible = "mediatek,mt7622-spi";
+ reg = <0 0x11016000 0 0x100>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI1_SEL>,
+ <&pericfg CLK_PERI_SPI1_PD>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart4: serial@11019000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11019000 0 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART4_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
+ <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ ssusbsys: ssusbsys@1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ssusb: usb@1a0c0000 {
+ compatible = "mediatek,mt7622-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x1a0c0000 0 0x01000>,
+ <0 0x1a0c4700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
+ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+ <&ssusbsys CLK_SSUSB_REF_EN>,
+ <&ssusbsys CLK_SSUSB_MCU_EN>,
+ <&ssusbsys CLK_SSUSB_DMA_EN>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+
+ status = "disabled";
+ };
+
+ u3phy: usb-phy@1a0c4000 {
+ compatible = "mediatek,mt7622-u3phy",
+ "mediatek,generic-tphy-v1";
+ reg = <0 0x1a0c4000 0 0x700>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ u2port0: usb-phy@1a0c4800 {
+ reg = <0 0x1a0c4800 0 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+ clock-names = "ref";
+ };
+
+ u3port0: usb-phy@1a0c4900 {
+ reg = <0 0x1a0c4900 0 0x0700>;
+ #phy-cells = <1>;
+ clocks = <&clk25m>;
+ clock-names = "ref";
+ };
+
+ u2port1: usb-phy@1a0c5000 {
+ reg = <0 0x1a0c5000 0 0x0100>;
+ #phy-cells = <1>;
+ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+ clock-names = "ref";
+ };
+ };
+
+ pciesys: pciesys@1a100800 {
+ compatible = "mediatek,mt7622-pciesys",
+ "syscon";
+ reg = <0 0x1a100800 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>,
+ <0 0x1a143000 0 0x1000>,
+ <0 0x1a145000 0 0x1000>;
+ reg-names = "subsys", "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+ <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P0_PIPE_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+ status = "disabled";
+
+ pcie0: pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci",
+ "mediatek,mtk-ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&sata_port PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ status = "disabled";
+ };
+
+ sata_phy: sata-phy@1a243000 {
+ compatible = "mediatek,generic-tphy-v1";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ sata_port: sata-phy@1a243000 {
+ reg = <0 0x1a243000 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_ETH_500M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt7622-ethsys",
+ "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ eth: ethernet@1b100000 {
+ compatible = "mediatek,mt7622-eth",
+ "mediatek,mt2701-eth",
+ "syscon";
+ reg = <0 0x1b100000 0 0x20000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&ethsys CLK_ETH_ESW_EN>,
+ <&ethsys CLK_ETH_GP0_EN>,
+ <&ethsys CLK_ETH_GP1_EN>,
+ <&ethsys CLK_ETH_GP2_EN>,
+ <&sgmiisys CLK_SGMII_TX250M_EN>,
+ <&sgmiisys CLK_SGMII_RX250M_EN>,
+ <&sgmiisys CLK_SGMII_CDR_REF>,
+ <&sgmiisys CLK_SGMII_CDR_FB>,
+ <&topckgen CLK_TOP_SGMIIPLL>,
+ <&apmixedsys CLK_APMIXED_ETH2PLL>;
+ clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
+ "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
+ "eth2pll";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
+ mediatek,ethsys = <&ethsys>;
+ mediatek,sgmiisys = <&sgmiisys>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sgmiisys: sgmiisys@1b128000 {
+ compatible = "mediatek,mt7622-sgmiisys",
+ "syscon";
+ reg = <0 0x1b128000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 676aa2f238d1..7c13d7df484e 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
new file mode 100644
index 000000000000..ecb034177fc2
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "tegra194.dtsi"
+
+#include <dt-bindings/mfd/max77620.h>
+
+/ {
+ model = "NVIDIA Tegra194 P2888 Processor Module";
+ compatible = "nvidia,p2888", "nvidia,tegra194";
+
+ aliases {
+ sdhci0 = "/cbb/sdhci@3460000";
+ sdhci1 = "/cbb/sdhci@3400000";
+ serial0 = &uartb;
+ i2c0 = "/bpmp/i2c";
+ i2c1 = "/cbb/i2c@3160000";
+ i2c2 = "/cbb/i2c@c240000";
+ i2c3 = "/cbb/i2c@3180000";
+ i2c4 = "/cbb/i2c@3190000";
+ i2c5 = "/cbb/i2c@31c0000";
+ i2c6 = "/cbb/i2c@c250000";
+ i2c7 = "/cbb/i2c@31e0000";
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ cbb {
+ serial@3110000 {
+ status = "okay";
+ };
+
+ /* SDMMC1 (SD/MMC) */
+ sdhci@3400000 {
+/*
+ cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
+*/
+ };
+
+ /* SDMMC4 (eMMC) */
+ sdhci@3460000 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vqmmc-supply = <&vdd_1v8ls>;
+ vmmc-supply = <&vdd_emmc_3v3>;
+ };
+
+ pmc@c360000 {
+ nvidia,invert-interrupt;
+ };
+ };
+
+ bpmp {
+ i2c {
+ status = "okay";
+
+ pmic: pmic@3c {
+ compatible = "maxim,max20024";
+ reg = <0x3c>;
+
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&max20024_default>;
+
+ max20024_default: pinmux {
+ gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ gpio1 {
+ pins = "gpio1";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+ };
+
+ gpio2 {
+ pins = "gpio2";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+ };
+
+ gpio3 {
+ pins = "gpio3";
+ function = "fps-out";
+ maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+ };
+
+ gpio4 {
+ pins = "gpio4";
+ function = "32k-out1";
+ drive-push-pull = <1>;
+ };
+
+ gpio6 {
+ pins = "gpio6";
+ function = "gpio";
+ drive-push-pull = <1>;
+ };
+
+ gpio7 {
+ pins = "gpio7";
+ function = "gpio";
+ drive-push-pull = <0>;
+ };
+ };
+
+ fps {
+ fps0 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ maxim,shutdown-fps-time-period-us = <640>;
+ };
+
+ fps1 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+ maxim,shutdown-fps-time-period-us = <640>;
+ maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
+ };
+
+ fps2 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ maxim,shutdown-fps-time-period-us = <640>;
+ };
+ };
+
+ regulators {
+ in-sd0-supply = <&vdd_5v0_sys>;
+ in-sd1-supply = <&vdd_5v0_sys>;
+ in-sd2-supply = <&vdd_5v0_sys>;
+ in-sd3-supply = <&vdd_5v0_sys>;
+ in-sd4-supply = <&vdd_5v0_sys>;
+
+ in-ldo0-1-supply = <&vdd_5v0_sys>;
+ in-ldo2-supply = <&vdd_5v0_sys>;
+ in-ldo3-5-supply = <&vdd_5v0_sys>;
+ in-ldo4-6-supply = <&vdd_5v0_sys>;
+ in-ldo7-8-supply = <&vdd_1v8ls>;
+
+ sd0 {
+ regulator-name = "VDD_1V0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd1 {
+ regulator-name = "VDD_1V8HS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8ls: sd2 {
+ regulator-name = "VDD_1V8LS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd3 {
+ regulator-name = "VDD_1V8AO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sd4 {
+ regulator-name = "VDD_DDR_1V1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo0 {
+ regulator-name = "VDD_RTC";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo2 {
+ regulator-name = "VDD_AO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_emmc_3v3: ldo3 {
+ regulator-name = "VDD_EMMC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo5 {
+ regulator-name = "VDD_USB_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6 {
+ regulator-name = "VDD_SDIO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7 {
+ regulator-name = "VDD_CSI_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_sys: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+
+ regulator-name = "VIN_SYS_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
new file mode 100644
index 000000000000..9ff3c18280c4
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p2888.dtsi"
+
+/ {
+ model = "NVIDIA Tegra194 P2972-0000 Development Board";
+ compatible = "nvidia,p2972-0000", "nvidia,tegra194";
+
+ cbb {
+ /* SDMMC1 (SD/MMC) */
+ sdhci@3400000 {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
new file mode 100644
index 000000000000..6322ef265c2f
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/tegra194-clock.h>
+#include <dt-bindings/gpio/tegra194-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/tegra194-reset.h>
+
+/ {
+ compatible = "nvidia,tegra194";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* control backbone */
+ cbb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x40000000>;
+
+ uarta: serial@3100000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x03100000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial@3110000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x03110000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial@3130000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x03130000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial@3140000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x03140000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial@3150000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x03150000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTF>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ gen1_i2c: i2c@3160000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x03160000 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C1>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ uarth: serial@3170000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x03170000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTH>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTH>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ cam_i2c: i2c@3180000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x03180000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C3>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux1 */
+ dp_aux_ch1_i2c: i2c@3190000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x03190000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C4>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C4>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux0 */
+ dp_aux_ch0_i2c: i2c@31b0000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x031b0000 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C6>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C6>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen7_i2c: i2c@31c0000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x031c0000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C7>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C7>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen9_i2c: i2c@31e0000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x031e0000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C9>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C9>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ sdmmc1: sdhci@3400000 {
+ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+ reg = <0x03400000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA194_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc3: sdhci@3440000 {
+ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+ reg = <0x03440000 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA194_RESET_SDMMC3>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc4: sdhci@3460000 {
+ compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+ reg = <0x03460000 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA194_RESET_SDMMC4>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@3881000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x03881000 0x1000>,
+ <0x03882000 0x2000>,
+ <0x03884000 0x2000>,
+ <0x03886000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ hsp_top0: hsp@3c00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x03c00000 0xa0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell";
+ #mbox-cells = <2>;
+ };
+
+ gen2_i2c: i2c@c240000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0c240000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C2>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen8_i2c: i2c@c250000 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0c250000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C8>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C8>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ uartc: serial@c280000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0c280000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTC>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTC>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartg: serial@c290000 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0c290000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_UARTG>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTG>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ pmc@c360000 {
+ compatible = "nvidia,tegra194-pmc";
+ reg = <0x0c360000 0x10000>,
+ <0x0c370000 0x10000>,
+ <0x0c380000 0x10000>,
+ <0x0c390000 0x10000>,
+ <0x0c3a0000 0x10000>;
+ reg-names = "pmc", "wake", "aotag", "scratch", "misc";
+ };
+ };
+
+ sysram@40000000 {
+ compatible = "nvidia,tegra194-sysram", "mmio-sram";
+ reg = <0x0 0x40000000 0x0 0x50000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x40000000 0x50000>;
+
+ cpu_bpmp_tx: shmem@4e000 {
+ compatible = "nvidia,tegra194-bpmp-shmem";
+ reg = <0x4e000 0x1000>;
+ label = "cpu-bpmp-tx";
+ pool;
+ };
+
+ cpu_bpmp_rx: shmem@4f000 {
+ compatible = "nvidia,tegra194-bpmp-shmem";
+ reg = <0x4f000 0x1000>;
+ label = "cpu-bpmp-rx";
+ pool;
+ };
+ };
+
+ bpmp: bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
+ TEGRA_HSP_DB_MASTER_BPMP>;
+ shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ bpmp_i2c: i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ nvidia,bpmp-bus-id = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ bpmp_thermal: thermal {
+ compatible = "nvidia,tegra186-bpmp-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index d67ef4319f3b..9d5a0e6b2ca4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1325,6 +1325,11 @@
status = "okay";
};
+ sata@70020000 {
+ status = "okay";
+ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+ };
+
padctl@7009f000 {
status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 9c2402108772..3be920efee82 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -798,6 +798,22 @@
#iommu-cells = <1>;
};
+ sata@70020000 {
+ compatible = "nvidia,tegra210-ahci";
+ reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
+ <0x0 0x70020000 0x0 0x7000>, /* SATA */
+ <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SATA>,
+ <&tegra_car TEGRA210_CLK_SATA_OOB>;
+ clock-names = "sata", "sata-oob";
+ resets = <&tegra_car 124>,
+ <&tegra_car 123>,
+ <&tegra_car 129>;
+ reset-names = "sata", "sata-oob", "sata-cold";
+ status = "disabled";
+ };
+
hda@70030000 {
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index e51b04900726..66b318e1de80 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8916";
@@ -113,6 +114,9 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -122,6 +126,9 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -131,6 +138,9 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -140,6 +150,9 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
@@ -188,6 +201,13 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal1 {
@@ -208,10 +228,35 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
+ cpu_opp_table: cpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ };
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ };
+ };
+
gpu_opp_table: opp_table {
compatible = "operating-points-v2";
@@ -326,9 +371,18 @@
status = "disabled";
};
- apcs: syscon@b011000 {
- compatible = "syscon";
- reg = <0x0b011000 0x1000>;
+ a53pll: clock@b016000 {
+ compatible = "qcom,msm8916-a53pll";
+ reg = <0xb016000 0x40>;
+ #clock-cells = <0>;
+ };
+
+ apcs: mailbox@b011000 {
+ compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
+ reg = <0xb011000 0x1000>;
+ #mbox-cells = <1>;
+ clocks = <&a53pll>;
+ #clock-cells = <0>;
};
blsp1_uart2: serial@78b0000 {
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0a6f7952bbb1..410ae787ebb4 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -75,6 +75,17 @@
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
+
+ rmtfs@86700000 {
+ compatible = "qcom,rmtfs-mem";
+
+ size = <0x0 0x200000>;
+ alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
};
cpus {
@@ -232,10 +243,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
clocks {
@@ -497,8 +508,8 @@
blsp2_spi5: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 2186d0193b73..5ede06000ea4 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -7,5 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 26769a11a190..f9acd125d687 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -23,6 +23,7 @@
/delete-node/ mmu@febe0000;
/delete-node/ mmu@fe980000;
+ /delete-node/ mmu@fd950000;
/delete-node/ mmu@fd960000;
/delete-node/ mmu@fd970000;
@@ -80,7 +81,7 @@
vspd3: vsp@fea38000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea38000 0 0x4000>;
+ reg = <0 0xfea38000 0 0x8000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index d12df6f2ff09..1d5e3ac0231c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -41,6 +41,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a57_1: cpu@1 {
@@ -50,6 +53,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a57_2: cpu@2 {
@@ -59,6 +65,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a57_3: cpu@3 {
@@ -68,6 +77,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a53_0: cpu@100 {
@@ -77,6 +89,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@101 {
@@ -86,6 +100,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu@102 {
@@ -95,6 +111,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu@103 {
@@ -104,6 +122,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@@ -165,11 +185,59 @@
clock-frequency = <0>;
};
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <960000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
};
/* External PCIe clock - can be overridden by the board */
@@ -208,6 +276,13 @@
method = "smc";
};
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -470,6 +545,15 @@
status = "disabled";
};
+ ipmmu_pv1: mmu@fd950000 {
+ compatible = "renesas,ipmmu-r8a7795";
+ reg = <0 0xfd950000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 7>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
ipmmu_pv2: mmu@fd960000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd960000 0 0x1000>;
@@ -798,7 +882,7 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -992,8 +1076,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled";
@@ -1009,8 +1094,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled";
@@ -1026,8 +1112,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
@@ -1138,8 +1225,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
@@ -1154,8 +1242,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
@@ -1170,8 +1259,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+ <&dmac2 0x13>, <&dmac2 0x12>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
@@ -1218,8 +1308,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
@@ -1251,8 +1342,9 @@
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@@ -1267,8 +1359,9 @@
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@@ -1283,8 +1376,9 @@
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>;
- dma-names = "tx", "rx";
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@@ -2143,7 +2237,7 @@
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x4000>;
+ reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2163,7 +2257,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x4000>;
+ reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2183,7 +2277,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x4000>;
+ reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2320,9 +2414,9 @@
tsc: thermal@e6198000 {
compatible = "renesas,r8a7795-thermal";
- reg = <0 0xe6198000 0 0x68>,
- <0 0xe61a0000 0 0x5c>,
- <0 0xe61a8000 0 0x5c>;
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>,
+ <0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -2357,12 +2451,24 @@
thermal-sensors = <&tsc 0>;
trips {
+ sensor1_passive: sensor1-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor1_passive>;
+ cooling-device = <&a57_0 4 4>;
+ };
+ };
};
sensor_thermal2: sensor-thermal2 {
@@ -2371,12 +2477,24 @@
thermal-sensors = <&tsc 1>;
trips {
+ sensor2_passive: sensor2-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor2_passive>;
+ cooling-device = <&a57_0 4 4>;
+ };
+ };
};
sensor_thermal3: sensor-thermal3 {
@@ -2385,12 +2503,24 @@
thermal-sensors = <&tsc 2>;
trips {
+ sensor3_passive: sensor3-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor3_passive>;
+ cooling-device = <&a57_0 4 4>;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c5192d513d7d..556eb8e45499 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -71,6 +71,9 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a57_1: cpu@1 {
@@ -80,6 +83,9 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a53_0: cpu@100 {
@@ -89,6 +95,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@101 {
@@ -98,6 +106,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu@102 {
@@ -107,6 +117,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu@103 {
@@ -116,6 +128,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@@ -147,6 +161,72 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <960000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
@@ -894,7 +974,7 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1561,9 +1641,9 @@
tsc: thermal@e6198000 {
compatible = "renesas,r8a7796-thermal";
- reg = <0 0xe6198000 0 0x68>,
- <0 0xe61a0000 0 0x5c>,
- <0 0xe61a8000 0 0x5c>;
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>,
+ <0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -1839,7 +1919,7 @@
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x4000>;
+ reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1859,7 +1939,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x4000>;
+ reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1879,7 +1959,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x4000>;
+ reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1998,12 +2078,24 @@
thermal-sensors = <&tsc 0>;
trips {
+ sensor1_passive: sensor1-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor1_passive>;
+ cooling-device = <&a57_0 5 5>;
+ };
+ };
};
sensor_thermal2: sensor-thermal2 {
@@ -2012,12 +2104,24 @@
thermal-sensors = <&tsc 1>;
trips {
+ sensor2_passive: sensor2-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor2_passive>;
+ cooling-device = <&a57_0 5 5>;
+ };
+ };
};
sensor_thermal3: sensor-thermal3 {
@@ -2026,12 +2130,24 @@
thermal-sensors = <&tsc 2>;
trips {
+ sensor3_passive: sensor3-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor3_passive>;
+ cooling-device = <&a57_0 5 5>;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
new file mode 100644
index 000000000000..75d890d91df9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Salvator-X board with R-Car M3-N
+ *
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ */
+
+/dts-v1/;
+#include "r8a77965.dtsi"
+#include "salvator-x.dtsi"
+
+/ {
+ model = "Renesas Salvator-X board based on r8a77965";
+ compatible = "renesas,salvator-x", "renesas,r8a77965";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
new file mode 100644
index 000000000000..a83a00deed9e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77965.dtsi"
+#include "salvator-xs.dtsi"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a77965";
+ compatible = "renesas,salvator-xs", "renesas,r8a77965";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
new file mode 100644
index 000000000000..f0871fcdd984
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -0,0 +1,878 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a77965 SoC
+ *
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ *
+ * Based on r8a7796.dtsi
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define CPG_AUDIO_CLK_I 10
+
+/ {
+ compatible = "renesas,r8a77965";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c7 = &i2c_dvfs;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a57_0: cpu@0 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = <&sysc 0>;
+ next-level-cache = <&L2_CA57>;
+ enable-method = "psci";
+ };
+
+ a57_1: cpu@1 {
+ compatible = "arm,cortex-a57","arm,armv8";
+ reg = <0x1>;
+ device_type = "cpu";
+ power-domains = <&sysc 1>;
+ next-level-cache = <&L2_CA57>;
+ enable-method = "psci";
+ };
+
+ L2_CA57: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc 12>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External USB clocks - can be overridden by the board */
+ usb3s0_clk: usb3s0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu_a57 {
+ compatible = "arm,cortex-a57-pmu";
+ interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a57_0>,
+ <&a57_1>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 408>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77965";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77965-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77965-rst";
+ reg = <0 0xe6160000 0 0x0200>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77965-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 16>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 29>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 15>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 16>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 18>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 906>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a77965",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 4>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 905>;
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 407>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a77965",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a77965",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a77965",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77965",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE 20>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77965",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE 20>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a77965",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE 20>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77965",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE 20>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77965",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE 20>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a77965",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 64>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE 20>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77965",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ csi20: csi2@fea80000 {
+ reg = <0 0xfea80000 0 0x10000>;
+ /* placeholder */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ csi40: csi2@feaa0000 {
+ reg = <0 0xfeaa0000 0 0x10000>;
+ /* placeholder */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ vin0: video@e6ef0000 {
+ reg = <0 0xe6ef0000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin1: video@e6ef1000 {
+ reg = <0 0xe6ef1000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin2: video@e6ef2000 {
+ reg = <0 0xe6ef2000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin3: video@e6ef3000 {
+ reg = <0 0xe6ef3000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin4: video@e6ef4000 {
+ reg = <0 0xe6ef4000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin5: video@e6ef5000 {
+ reg = <0 0xe6ef5000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin6: video@e6ef6000 {
+ reg = <0 0xe6ef6000 0 0x1000>;
+ /* placeholder */
+ };
+
+ vin7: video@e6ef7000 {
+ reg = <0 0xe6ef7000 0 0x1000>;
+ /* placeholder */
+ };
+
+ ohci0: usb@ee080000 {
+ reg = <0 0xee080000 0 0x100>;
+ /* placeholder */
+ };
+
+ ehci0: usb@ee080100 {
+ reg = <0 0xee080100 0 0x100>;
+ /* placeholder */
+ };
+
+ usb2_phy0: usb-phy@ee080200 {
+ reg = <0 0xee080200 0 0x700>;
+ /* placeholder */
+ };
+
+ usb2_phy1: usb-phy@ee0a0200 {
+ reg = <0 0xee0a0200 0 0x700>;
+ /* placeholder */
+ };
+
+ ohci1: usb@ee0a0000 {
+ reg = <0 0xee0a0000 0 0x100>;
+ /* placeholder */
+ };
+
+ ehci1: usb@ee0a0100 {
+ reg = <0 0xee0a0100 0 0x100>;
+ /* placeholder */
+ };
+
+ i2c0: i2c@e6500000 {
+ reg = <0 0xe6500000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c1: i2c@e6508000 {
+ reg = <0 0xe6508000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c2: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xe6510000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c3: i2c@e66d0000 {
+ reg = <0 0xe66d0000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c4: i2c@e66d8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xe66d8000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c5: i2c@e66e0000 {
+ reg = <0 0xe66e0000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c6: i2c@e66e8000 {
+ reg = <0 0xe66e8000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c_dvfs: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a77965",
+ "renesas,rcar-gen3-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 926>;
+ dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ reg = <0 0xe6e30000 0 8>;
+ /* placeholder */
+ };
+
+ pwm1: pwm@e6e31000 {
+ reg = <0 0xe6e31000 0 8>;
+ #pwm-cells = <2>;
+ /* placeholder */
+ };
+
+ pwm2: pwm@e6e32000 {
+ reg = <0 0xe6e32000 0 8>;
+ /* placeholder */
+ };
+
+ pwm3: pwm@e6e33000 {
+ reg = <0 0xe6e33000 0 8>;
+ /* placeholder */
+ };
+
+ pwm4: pwm@e6e34000 {
+ reg = <0 0xe6e34000 0 8>;
+ /* placeholder */
+ };
+
+ pwm5: pwm@e6e35000 {
+ reg = <0 0xe6e35000 0 8>;
+ /* placeholder */
+ };
+
+ pwm6: pwm@e6e36000 {
+ reg = <0 0xe6e36000 0 8>;
+ /* placeholder */
+ };
+
+ du: display@feb00000 {
+ reg = <0 0xfeb00000 0 0x80000>,
+ <0 0xfeb90000 0 0x14>;
+ /* placeholder */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_hdmi0: endpoint {
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ };
+ };
+
+ hsusb: usb@e6590000 {
+ reg = <0 0xe6590000 0 0x100>;
+ /* placeholder */
+ };
+
+ pciec0: pcie@fe000000 {
+ reg = <0 0xfe000000 0 0x80000>;
+ /* placeholder */
+ };
+
+ pciec1: pcie@ee800000 {
+ reg = <0 0xee800000 0 0x80000>;
+ /* placeholder */
+ };
+
+ rcar_sound: sound@ec500000 {
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ /* placeholder */
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ };
+ dvc1: dvc-1 {
+ };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ };
+ src1: src-1 {
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ };
+ ssi1: ssi-1 {
+ };
+ };
+ };
+
+ sdhi0: sd@ee100000 {
+ reg = <0 0xee100000 0 0x2000>;
+ /* placeholder */
+ };
+
+ sdhi1: sd@ee120000 {
+ reg = <0 0xee120000 0 0x2000>;
+ /* placeholder */
+ };
+
+ sdhi2: sd@ee140000 {
+ reg = <0 0xee140000 0 0x2000>;
+ /* placeholder */
+ };
+
+ sdhi3: sd@ee160000 {
+ reg = <0 0xee160000 0 0x2000>;
+ /* placeholder */
+ };
+
+ usb3_phy0: usb-phy@e65ee000 {
+ reg = <0 0xe65ee000 0 0x90>;
+ #phy-cells = <0>;
+ /* placeholder */
+ };
+
+ usb3_peri0: usb@ee020000 {
+ reg = <0 0xee020000 0 0x400>;
+ /* placeholder */
+ };
+
+ xhci0: usb@ee000000 {
+ reg = <0 0xee000000 0 0xc00>;
+ /* placeholder */
+ };
+
+ wdt0: watchdog@e6020000 {
+ reg = <0 0xe6020000 0 0x0c>;
+ /* placeholder */
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index 8fe5c193e049..3c5f598c9766 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -36,11 +36,14 @@
&avb {
renesas,no-ether-link;
phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -52,11 +55,41 @@
clock-frequency = <32768>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ io_expander: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&pfc {
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+};
+
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 8624ca87d6b2..a8ceeac77992 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -34,6 +34,7 @@
&avb {
renesas,no-ether-link;
phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@0 {
@@ -50,6 +51,16 @@
clock-frequency = <32768>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+};
+
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index c35a117fc447..c6db8ea43906 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -19,9 +19,12 @@
#address-cells = <2>;
#size-cells = <2>;
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
};
cpus {
@@ -60,6 +63,11 @@
clock-frequency = <0>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
@@ -92,18 +100,6 @@
resets = <&cpg 408>;
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
- IRQ_TYPE_LEVEL_LOW)>;
- };
-
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77970-wdt",
"renesas,rcar-gen3-wdt";
@@ -178,6 +174,101 @@
#iommu-cells = <1>;
};
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77970";
+ reg = <0 0xe6060000 0 0x504>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a77970",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a77970",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 28>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a77970",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a77970",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a77970",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 6>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a77970",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 15>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>;
@@ -255,6 +346,91 @@
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
+ i2c0: i2c@e6500000 {
+ compatible = "renesas,i2c-r8a77970",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a77970",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6510000 {
+ compatible = "renesas,i2c-r8a77970",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d0000 {
+ compatible = "renesas,i2c-r8a77970",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac1 0x97>, <&dmac1 0x96>,
+ <&dmac2 0x97>, <&dmac2 0x96>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e66d8000 {
+ compatible = "renesas,i2c-r8a77970",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ dmas = <&dmac1 0x99>, <&dmac1 0x98>,
+ <&dmac2 0x99>, <&dmac2 0x98>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a77970",
"renesas,rcar-gen3-hscif",
@@ -400,7 +576,7 @@
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77970",
"renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -436,10 +612,18 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii";
iommus = <&ipmmu_rt 3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
new file mode 100644
index 000000000000..06cf6845765a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Condor board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+ model = "Renesas Condor board based on r8a77980";
+ compatible = "renesas,condor", "renesas,r8a77980";
+
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0 0x48000000 0 0x78000000>;
+ };
+};
+
+&avb {
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&scif0 {
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
new file mode 100644
index 000000000000..03845fd74996
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a77980 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+ compatible = "renesas,r8a77980";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0>;
+ clocks = <&cpg CPG_CORE 0>;
+ power-domains = <&sysc 5>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller {
+ compatible = "cache";
+ power-domains = <&sysc 21>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77980-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77980-rst";
+ reg = <0 0xe6160000 0 0x200>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77980-sysc";
+ reg = <0 0xe6180000 0 0x440>;
+ #power-domain-cells = <1>;
+ };
+
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+ <&dmac2 0x37>, <&dmac2 0x36>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77980",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+ <&dmac2 0x57>, <&dmac2 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE 19>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+ <&dmac2 0x59>, <&dmac2 0x58>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a77980",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a77980",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 408>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 09de73b11db8..d03f19414028 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -27,11 +27,61 @@
stdout-path = "serial0:115200n8";
};
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&extal_clk {
@@ -46,6 +96,21 @@
};
};
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
@@ -61,12 +126,56 @@
function = "scif2";
};
+ sdhi2_pins: sd2 {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
&ehci0 {
status = "okay";
};
@@ -80,6 +189,7 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
+ phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@@ -97,6 +207,20 @@
status = "okay";
};
+&sdhi2 {
+ /* used for on-board eMMC */
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cff42cd1a6c8..82aed7ee984c 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -58,6 +58,11 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -88,18 +93,6 @@
resets = <&cpg 408>;
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt";
@@ -110,11 +103,6 @@
status = "disabled";
};
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- };
-
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfebd0000 0 0x1000>;
@@ -488,7 +476,7 @@
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77995",
"renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -524,7 +512,7 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -548,6 +536,73 @@
status = "disabled";
};
+ i2c0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77995",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77995",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77995",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77995",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
@@ -636,5 +691,105 @@
#phy-cells = <0>;
status = "disabled";
};
+
+ vspbs: vsp@fe960000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ renesas,fcp = <&fcpvb0>;
+ };
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 607>;
+ iommus = <&ipmmu_vp0 5>;
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x8000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ iommus = <&ipmmu_vi0 8>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x8000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ iommus = <&ipmmu_vi0 9>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a77995";
+ reg = <0 0xfeb00000 0 0x80000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ vsps = <&vspd0 0 &vspd1 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index c3fafb6025b3..2a7f36abd2dd 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -256,6 +256,7 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
+ phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@@ -338,6 +339,13 @@
&i2c4 {
status = "okay";
+ pca9654: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
csa_vdd: adc@7c {
compatible = "maxim,max9611";
reg = <0x7c>;
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 3e7a6b94e9f8..6f814845f8b6 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -146,6 +146,7 @@
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
+ phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index ce2701e37d00..48a83f882947 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,8 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
@@ -10,4 +12,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
new file mode 100644
index 000000000000..246c317f6a68
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Firefly roc-rk3328-cc";
+ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_host1_5v";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ status = "okay";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x25>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_io>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index cae341554486..be2bfbc6b483 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -318,7 +318,7 @@
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 2>, <&dmac 3>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
reg-io-width = <4>;
@@ -333,7 +333,7 @@
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "sclk_uart", "pclk_uart";
dmas = <&dmac 4>, <&dmac 5>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
reg-io-width = <4>;
@@ -348,7 +348,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 6>, <&dmac 7>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
reg-io-width = <4>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
new file mode 100644
index 000000000000..fca8e87d8f52
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include "rk3368-lion.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3368-uQ7 Baseboard";
+ compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ i2cmux2 {
+ i2c@0 {
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ reg = <0x50>;
+ };
+ };
+ };
+
+ leds {
+ pinctrl-0 = <&led_pins_module>, <&led_sd_haikou>;
+
+ sd-card-led {
+ label = "sd_card_led";
+ gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_baseboard: vcc3v3-baseboard {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <25000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ rockchip,default-sample-phase = <90>;
+ vmmc-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&spi2 {
+ cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
+
+&uart1 {
+ /* alternate function of GPIO5/6 */
+ status = "disabled";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&haikou_pin_hog>;
+
+ hog {
+ haikou_pin_hog: haikou-pin-hog {
+ rockchip,pins =
+ /* LID_BTN */
+ <RK_GPIO3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BATLOW# */
+ <RK_GPIO0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* SLP_BTN# */
+ <RK_GPIO3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BIOS_DISABLE# */
+ <RK_GPIO3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led_sd_haikou: led-sd-gpio {
+ rockchip,pins =
+ <RK_GPIO0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_cd_gpio: sdmmc-cd-gpio {
+ rockchip,pins =
+ <RK_GPIO2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_otg {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <RK_GPIO0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
new file mode 100644
index 000000000000..1315972412df
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ i2cmux1 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c1>;
+ mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+
+ /* Q7_GPO_I2C */
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* Q7_SMB */
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2cmux2 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c2>;
+ mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+
+ /* Q7_LVDS_BLC_I2C */
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ };
+
+ /* Q7_GP2_I2C */
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_module>;
+
+ module_led1 {
+ label = "module_led1";
+ gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ module_led2 {
+ label = "module_led2";
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&emmc {
+ bus-width = <8>;
+ clock-frequency = <150000000>;
+ disable-wp;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc33_io>;
+ vqmmc-supply = <&vcc18_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc33_io>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_sys>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc33_io: DCDC_REG4 {
+ regulator-name = "vcc33_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc33_video: LDO_REG2 {
+ regulator-name = "vcc33_video";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd10_pll: LDO_REG3 {
+ regulator-name = "vdd10_pll";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc18_io: LDO_REG4 {
+ regulator-name = "vcc18_io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ vdd10_video: LDO_REG6 {
+ regulator-name = "vdd10_video";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc18_video: LDO_REG8 {
+ regulator-name = "vcc18_video";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ led_pins_module: led-module-gpio {
+ rockchip,pins =
+ <RK_GPIO2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <RK_GPIO3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <RK_GPIO0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <RK_GPIO0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ norflash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 03f195025390..18f546f2dfd1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -406,8 +406,9 @@
wlan_pd_n: wlan-pd-n {
compatible = "regulator-fixed";
regulator-name = "wlan_pd_n";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_module_reset_l>;
- /* Note the wlan_module_reset_l pinctrl */
enable-active-high;
gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
@@ -515,10 +516,15 @@
compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <&i2s0 &i2s2>;
rockchip,codec = <&max98357a &headsetcodec
- &codec &wacky_spi_audio>;
+ &codec &wacky_spi_audio &cdn_dp>;
};
};
+&cdn_dp {
+ status = "okay";
+ extcon = <&usbc_extcon0>, <&usbc_extcon1>;
+};
+
/*
* Set some suspend operating points to avoid OVP in suspend
*
@@ -581,7 +587,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+ <&cru ACLK_VIO>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
@@ -589,7 +596,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <800000000>,
- <100000000>, <50000000>;
+ <100000000>, <50000000>,
+ <400000000>;
};
&emmc_phy {
@@ -983,12 +991,6 @@ ap_i2c_audio: &i2c8 {
pinctrl-0 = <
&ap_pwroff /* AP will auto-assert this when in S3 */
&clk_32k /* This pin is always 32k on gru boards */
-
- /*
- * We want this driven low ASAP; firmware should help us, but
- * we can help ourselves too.
- */
- &wlan_module_reset_l
>;
pcfg_output_low: pcfg-output-low {
@@ -1168,12 +1170,7 @@ ap_i2c_audio: &i2c8 {
};
wlan_module_reset_l: wlan-module-reset-l {
- /*
- * We want this driven low ASAP (As {Soon,Strongly} As
- * Possible), to avoid leakage through the powered-down
- * WiFi.
- */
- rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_output_low>;
+ rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index 9a7486058455..7d3e8bfd51dd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -61,6 +61,30 @@
};
};
+ i2s0-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Haikou,I2S-codec";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ clocks = <&sgtl5000_clk>;
+ sound-dai = <&sgtl5000>;
+ };
+
+ simple-audio-card,cpu {
+ bitclock-master;
+ frame-master;
+ sound-dai = <&i2s0>;
+ };
+ };
+
+ sgtl5000_clk: sgtl5000-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
@@ -80,6 +104,16 @@
vin-supply = <&dc_12v>;
};
+ vcc5v0_baseboard: vcc5v0-baseboard {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -89,6 +123,24 @@
regulator-name = "vcc5v0_otg";
regulator-always-on;
};
+
+ vdda_codec: vdda-codec {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda_codec";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_baseboard>;
+ };
+
+ vddd_codec: vddd-codec {
+ compatible = "regulator-fixed";
+ regulator-name = "vddd_codec";
+ regulator-boot-on;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1600000>;
+ vin-supply = <&vcc5v0_baseboard>;
+ };
};
&i2c1 {
@@ -110,6 +162,17 @@
&i2c4 {
status = "okay";
clock-frequency = <400000>;
+
+ sgtl5000: codec@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&sgtl5000_clk>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&vdda_codec>;
+ VDDIO-supply = <&vdda_codec>;
+ VDDD-supply = <&vddd_codec>;
+ status = "okay";
+ };
};
&i2c6 {
@@ -117,14 +180,6 @@
clock-frequency = <400000>;
};
-&i2s0 {
- status = "okay";
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- #sound-dai-cells = <0>;
- status = "okay";
-};
-
&pcie_phy {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index 1fc5060d7027..4a2d06abe9c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -435,6 +435,28 @@
};
};
+&i2s0 {
+ pinctrl-0 = <&i2s0_2ch_bus>;
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+/*
+ * As Q7 does not specify neither a global nor a RX clock for I2S these
+ * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
+ * Therefore we have to redefine the i2s0_2ch_bus definition to prevent
+ * conflicts.
+ */
+&i2s0_2ch_bus {
+ rockchip,pins =
+ <RK_GPIO3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
+};
+
&io_domains {
status = "okay";
bt656-supply = <&vcc_1v8>;
@@ -505,6 +527,12 @@
};
};
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
&u2phy1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
index b7bd88fb3ae3..56952d1a3fb8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
@@ -41,7 +41,6 @@
*/
/dts-v1/;
-#include <dt-bindings/input/input.h>
#include "rk3399-sapphire.dtsi"
/ {
@@ -95,22 +94,6 @@
};
};
- keys: gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Power";
- linux,code = <KEY_POWER>;
- linux,input-type = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_btn>;
- wakeup-source;
- };
- };
-
rt5651-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "realtek,rt5651-codec";
@@ -207,18 +190,7 @@
status = "okay";
};
-&i2s2 {
- #sound-dai-cells = <0>;
- status = "okay";
-};
-
&pinctrl {
- buttons {
- pwr_btn: pwr-btn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -232,6 +204,22 @@
};
};
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ clock-frequency = <50000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <50000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
&spdif {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts
new file mode 100644
index 000000000000..5a58060447cf
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-sapphire.dtsi"
+
+/ {
+ model = "Sapphire-RK3399 Board";
+ compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index ce592a4c0c4c..e5daed7d2026 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -41,6 +41,7 @@
*/
#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -102,6 +103,22 @@
regulator-max-microvolt = <12000000>;
};
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ linux,input-type = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_btn>;
+ wakeup-source;
+ };
+ };
+
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
@@ -143,6 +160,17 @@
regulator-always-on;
vin-supply = <&vcc_sys>;
};
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc_sys>;
+ };
};
&cpu_l0 {
@@ -421,17 +449,6 @@
regulator-off-in-suspend;
};
};
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc_sys>;
- };
};
&i2c3 {
@@ -440,6 +457,11 @@
status = "okay";
};
+&i2s2 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
&io_domains {
status = "okay";
@@ -470,6 +492,12 @@
};
&pinctrl {
+ buttons {
+ pwr_btn: pwr-btn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
@@ -513,29 +541,12 @@
&sdhci {
bus-width = <8>;
- keep-power-in-suspend;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- clock-frequency = <50000000>;
- disable-wp;
- keep-power-in-suspend;
- max-frequency = <50000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2605118d4b4c..4550c0f82be9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -411,8 +411,8 @@
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy0_otg>, <&tcphy0_usb3>;
- phy-names = "usb2-phy", "usb3-phy";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -444,8 +444,8 @@
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy1_otg>, <&tcphy1_usb3>;
- phy-names = "usb2-phy", "usb3-phy";
+ phys = <&u2phy1_otg>;
+ phy-names = "usb2-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -457,6 +457,42 @@
};
};
+ cdn_dp: dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+ <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+ reset-names = "spdif", "dptx", "apb", "core";
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+
+ ports {
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
@@ -1286,7 +1322,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+ <&cru ACLK_VIO>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@@ -1294,7 +1331,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
- <100000000>, <50000000>;
+ <100000000>, <50000000>,
+ <400000000>;
};
grf: syscon@ff770000 {
@@ -1547,6 +1585,11 @@
reg = <3>;
remote-endpoint = <&mipi1_in_vopl>;
};
+
+ vopl_out_dp: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&dp_in_vopl>;
+ };
};
};
@@ -1599,6 +1642,11 @@
reg = <3>;
remote-endpoint = <&mipi1_in_vopb>;
};
+
+ vopb_out_dp: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&dp_in_vopb>;
+ };
};
};
@@ -2043,6 +2091,16 @@
};
i2s0 {
+ i2s0_2ch_bus: i2s0-2ch-bus {
+ rockchip,pins =
+ <3 24 RK_FUNC_1 &pcfg_pull_none>,
+ <3 25 RK_FUNC_1 &pcfg_pull_none>,
+ <3 26 RK_FUNC_1 &pcfg_pull_none>,
+ <3 27 RK_FUNC_1 &pcfg_pull_none>,
+ <3 31 RK_FUNC_1 &pcfg_pull_none>,
+ <4 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins =
<3 24 RK_FUNC_1 &pcfg_pull_none>,
@@ -2293,6 +2351,23 @@
};
};
+ testclk {
+ test_clkout0: test-clkout0 {
+ rockchip,pins =
+ <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ test_clkout1: test-clkout1 {
+ rockchip,pins =
+ <2 25 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ test_clkout2: test-clkout2 {
+ rockchip,pins =
+ <0 8 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
index 2452b2243f42..9b4dc41703e3 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
@@ -1,14 +1,13 @@
-/*
- * Device Tree Source for UniPhier LD11 Global Board
- *
- * Copyright (C) 2016-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 Global Board
+//
+// Copyright (C) 2016-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+// Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
#include "uniphier-ld11.dtsi"
/ {
@@ -37,6 +36,53 @@
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
+
+ dvdd_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "DVDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ amp_vcc_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "AMP_VCC";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier LD11";
+ widgets = "Headphone", "Headphone Jack";
+ dais = <&i2s_port2
+ &i2s_port3
+ &i2s_port4
+ &spdif_port0
+ &comp_spdif_port0>;
+ };
+
+ spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ spdif_tx: endpoint {
+ remote-endpoint = <&spdif_hiecout1>;
+ };
+ };
+ };
+
+ comp-spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ comp_spdif_tx: endpoint {
+ remote-endpoint = <&comp_spdif_hiecout1>;
+ };
+ };
+ };
};
&serial0 {
@@ -47,9 +93,43 @@
status = "okay";
};
+&i2s_hpcmout1 {
+ dai-format = "i2s";
+ remote-endpoint = <&tas_speaker>;
+};
+
+&spdif_hiecout1 {
+ remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+ remote-endpoint = <&comp_spdif_tx>;
+};
+
&i2c0 {
status = "okay";
+ tas5707a@1d {
+ compatible = "ti,tas5711";
+ reg = <0x1d>;
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>;
+ pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <&dvdd_reg>;
+ DVDD-supply = <&dvdd_reg>;
+ PVDD_A-supply = <&amp_vcc_reg>;
+ PVDD_B-supply = <&amp_vcc_reg>;
+ PVDD_C-supply = <&amp_vcc_reg>;
+ PVDD_D-supply = <&amp_vcc_reg>;
+
+ port@0 {
+ tas_speaker: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&i2s_hpcmout1>;
+ };
+ };
+ };
+
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
@@ -69,6 +149,17 @@
status = "okay";
};
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
+
&nand {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
index 54c53170699a..b8f627348448 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD11 Reference Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 Reference Board
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld11.dtsi"
@@ -70,3 +68,14 @@
&usb2 {
status = "okay";
};
+
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index cd7c2d0a1f64..e62bda1cf2d9 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD11 SoC
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 SoC
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -187,6 +185,92 @@
<21 217 3>;
};
+ audio@56000000 {
+ compatible = "socionext,uniphier-ld11-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_aout1>,
+ <&pinctrl_aoutiec1>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_pcmin2: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_line: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_line>;
+ };
+ };
+
+ i2s_port3: port@3 {
+ i2s_hpcmout1: endpoint {
+ };
+ };
+
+ i2s_port4: port@4 {
+ i2s_hp: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_hp>;
+ };
+ };
+
+ spdif_port0: port@5 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ src_port0: port@6 {
+ i2s_epcmout2: endpoint {
+ };
+ };
+
+ src_port1: port@7 {
+ i2s_epcmout3: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@8 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+ };
+
+ codec@57900000 {
+ compatible = "socionext,uniphier-evea";
+ reg = <0x57900000 0x1000>;
+ clock-names = "evea", "exiv";
+ clocks = <&sys_clk 41>, <&sys_clk 42>;
+ reset-names = "evea", "exiv", "adamv";
+ resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
+ #sound-dai-cells = <1>;
+
+ port@0 {
+ evea_line: endpoint {
+ remote-endpoint = <&i2s_line>;
+ };
+ };
+
+ port@1 {
+ evea_hp: endpoint {
+ remote-endpoint = <&i2s_hp>;
+ };
+ };
+ };
+
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
@@ -396,7 +480,7 @@
};
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -460,6 +544,22 @@
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-ld11-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
@@ -475,3 +575,12 @@
};
#include "uniphier-pinctrl.dtsi"
+
+&pinctrl_aoutiec1 {
+ drive-strength = <4>; /* default: 4mA */
+
+ ao1arc {
+ pins = "AO1ARC";
+ drive-strength = <8>; /* 8mA */
+ };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
index fc2bc9d75d35..fe6608ea3277 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
@@ -1,14 +1,13 @@
-/*
- * Device Tree Source for UniPhier LD20 Global Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Global Board
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+// Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
#include "uniphier-ld20.dtsi"
/ {
@@ -37,6 +36,53 @@
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
+
+ dvdd_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "DVDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ amp_vcc_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "AMP_VCC";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier LD20";
+ widgets = "Headphone", "Headphone Jack";
+ dais = <&i2s_port2
+ &i2s_port3
+ &i2s_port4
+ &spdif_port0
+ &comp_spdif_port0>;
+ };
+
+ spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ spdif_tx: endpoint {
+ remote-endpoint = <&spdif_hiecout1>;
+ };
+ };
+ };
+
+ comp-spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ comp_spdif_tx: endpoint {
+ remote-endpoint = <&comp_spdif_hiecout1>;
+ };
+ };
+ };
};
&serial0 {
@@ -47,8 +93,55 @@
status = "okay";
};
+&i2s_hpcmout1 {
+ dai-format = "i2s";
+ remote-endpoint = <&tas_speaker>;
+};
+
+&spdif_hiecout1 {
+ remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+ remote-endpoint = <&comp_spdif_tx>;
+};
+
&i2c0 {
status = "okay";
+
+ tas5707@1b {
+ compatible = "ti,tas5711";
+ reg = <0x1b>;
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>;
+ pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <&dvdd_reg>;
+ DVDD-supply = <&dvdd_reg>;
+ PVDD_A-supply = <&amp_vcc_reg>;
+ PVDD_B-supply = <&amp_vcc_reg>;
+ PVDD_C-supply = <&amp_vcc_reg>;
+ PVDD_D-supply = <&amp_vcc_reg>;
+
+ port@0 {
+ tas_speaker: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&i2s_hpcmout1>;
+ };
+ };
+ };
+};
+
+&eth {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-0 = <&pinctrl_ether_rmii>;
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
};
&nand {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
index 693371033c90..2c1a92fafbfb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD20 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld20.dtsi"
@@ -58,3 +56,14 @@
&i2c0 {
status = "okay";
};
+
+&eth {
+ status = "okay";
+ phy-handle = <&ethphy>;
+};
+
+&mdio {
+ ethphy: ethphy@0 {
+ reg = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 8a3276ba2da1..9efe20d07589 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD20 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -287,6 +285,92 @@
<21 217 3>;
};
+ audio@56000000 {
+ compatible = "socionext,uniphier-ld20-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_aout1>,
+ <&pinctrl_aoutiec1>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_pcmin2: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_line: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_line>;
+ };
+ };
+
+ i2s_port3: port@3 {
+ i2s_hpcmout1: endpoint {
+ };
+ };
+
+ i2s_port4: port@4 {
+ i2s_hp: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_hp>;
+ };
+ };
+
+ spdif_port0: port@5 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ src_port0: port@6 {
+ i2s_epcmout2: endpoint {
+ };
+ };
+
+ src_port1: port@7 {
+ i2s_epcmout3: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@8 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+ };
+
+ codec@57900000 {
+ compatible = "socionext,uniphier-evea";
+ reg = <0x57900000 0x1000>;
+ clock-names = "evea", "exiv";
+ clocks = <&sys_clk 41>, <&sys_clk 42>;
+ reset-names = "evea", "exiv", "adamv";
+ resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
+ #sound-dai-cells = <1>;
+
+ port@0 {
+ evea_line: endpoint {
+ remote-endpoint = <&i2s_line>;
+ };
+ };
+
+ port@1 {
+ evea_hp: endpoint {
+ remote-endpoint = <&i2s_hp>;
+ };
+ };
+ };
+
adamv@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
@@ -442,7 +526,7 @@
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -513,6 +597,24 @@
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-ld20-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
@@ -528,3 +630,21 @@
};
#include "uniphier-pinctrl.dtsi"
+
+&pinctrl_aout1 {
+ drive-strength = <4>; /* default: 3.5mA */
+
+ ao1dacck {
+ pins = "AO1DACCK";
+ drive-strength = <5>; /* 5mA */
+ };
+};
+
+&pinctrl_aoutiec1 {
+ drive-strength = <4>; /* default: 3.5mA */
+
+ ao1arc {
+ pins = "AO1ARC";
+ drive-strength = <11>; /* 11mA */
+ };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index 3c7108729827..c1bb607bd211 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs3 Reference Board
- *
- * Copyright (C) 2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs3 Reference Board
+//
+// Copyright (C) 2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs3.dtsi"
@@ -77,6 +75,28 @@
status = "okay";
};
+&eth0 {
+ status = "okay";
+ phy-handle = <&ethphy0>;
+};
+
+&mdio0 {
+ ethphy0: ethphy@0 {
+ reg = <0>;
+ };
+};
+
+&eth1 {
+ status = "okay";
+ phy-handle = <&ethphy1>;
+};
+
+&mdio1 {
+ ethphy1: ethphy@0 {
+ reg = <0>;
+ };
+};
+
&nand {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 234fc58cc599..7c8f710d9bfa 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs3 SoC
- *
- * Copyright (C) 2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs3 SoC
+//
+// Copyright (C) 2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -407,6 +405,42 @@
};
};
+ eth0: ethernet@65000000 {
+ compatible = "socionext,uniphier-pxs3-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ eth1: ethernet@65200000 {
+ compatible = "socionext,uniphier-pxs3-ave4";
+ status = "disabled";
+ reg = <0x65200000 0x8500>;
+ interrupts = <0 67 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether1_rgmii>;
+ clocks = <&sys_clk 7>;
+ resets = <&sys_rst 7>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio1: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi
new file mode 100644
index 000000000000..4331006185bf
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi
@@ -0,0 +1,169 @@
+/*
+ * Spreadtrum SC2731 PMIC dts file
+ *
+ * Copyright (C) 2018, Spreadtrum Communications Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+&adi_bus {
+ sc2731_pmic: pmic@0 {
+ compatible = "sprd,sc2731";
+ reg = <0>;
+ spi-max-frequency = <26000000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@280 {
+ compatible = "sprd,sc27xx-rtc", "sprd,sc2731-rtc";
+ reg = <0x280>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ regulators {
+ compatible = "sprd,sc27xx-regulator";
+
+ vddarm0: BUCK_CPU0 {
+ regulator-name = "vddarm0";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1996875>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ };
+
+ vddarm1: BUCK_CPU1 {
+ regulator-name = "vddarm1";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1996875>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ };
+
+ dcdcrf: BUCK_RF {
+ regulator-name = "dcdcrf";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2196875>;
+ regulator-ramp-delay = <25000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-always-on;
+ };
+
+ vddcama0: LDO_CAMA0 {
+ regulator-name = "vddcama0";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ };
+
+ vddcama1: LDO_CAMA1 {
+ regulator-name = "vddcama1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddcammot: LDO_CAMMOT {
+ regulator-name = "vddcammot";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddvldo: LDO_VLDO {
+ regulator-name = "vddvldo";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddemmccore: LDO_EMMCCORE {
+ regulator-name = "vddemmccore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ regulator-boot-on;
+ };
+
+ vddsdcore: LDO_SDCORE {
+ regulator-name = "vddsdcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddsdio: LDO_SDIO {
+ regulator-name = "vddsdio";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddwifipa: LDO_WIFIPA {
+ regulator-name = "vddwifipa";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddusb33: LDO_USB33 {
+ regulator-name = "vddusb33";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddcamd0: LDO_CAMD0 {
+ regulator-name = "vddcamd0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1793750>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddcamd1: LDO_CAMD1 {
+ regulator-name = "vddcamd1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1793750>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddcon: LDO_CON {
+ regulator-name = "vddcon";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1793750>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddcamio: LDO_CAMIO {
+ regulator-name = "vddcamio";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1793750>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ };
+
+ vddsram: LDO_SRAM {
+ regulator-name = "vddsram";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1793750>;
+ regulator-enable-ramp-delay = <100>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
index ae0b28ce6319..985ebb5d157e 100644
--- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
+++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
@@ -9,6 +9,7 @@
/dts-v1/;
#include "sc9860.dtsi"
+#include "sc2731.dtsi"
/ {
model = "Spreadtrum SP9860G 3GFHD Board";
@@ -20,6 +21,7 @@
serial1 = &uart1; /* UART console */
serial2 = &uart2; /* Reserved */
serial3 = &uart3; /* for GPS */
+ spi0 = &adi_bus;
};
memory{
diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
index 328009c4638c..66a881e6da92 100644
--- a/arch/arm64/boot/dts/sprd/whale2.dtsi
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -6,6 +6,8 @@
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/clock/sprd,sc9860-clk.h>
+
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
@@ -104,6 +106,85 @@
status = "disabled";
};
};
+
+ ap-ahb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ap_dma: dma-controller@20100000 {
+ compatible = "sprd,sc9860-dma";
+ reg = <0 0x20100000 0 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ clock-names = "enable";
+ clocks = <&apahb_gate CLK_DMA_EB>;
+ };
+ };
+
+ aon {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ adi_bus: spi@40030000 {
+ compatible = "sprd,sc9860-adi";
+ reg = <0 0x40030000 0 0x10000>;
+ hwlocks = <&hwlock 0>;
+ hwlock-names = "adi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer@40050000 {
+ compatible = "sprd,sc9860-timer";
+ reg = <0 0x40050000 0 0x20>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_32k>;
+ };
+
+ hwlock: hwspinlock@40500000 {
+ compatible = "sprd,hwspinlock-r3p0";
+ reg = <0 0x40500000 0 0x1000>;
+ #hwlock-cells = <1>;
+ clock-names = "enable";
+ clocks = <&aon_gate CLK_SPLK_EB>;
+ };
+
+ pin_controller: pinctrl@402a0000 {
+ compatible = "sprd,sc9860-pinctrl";
+ reg = <0 0x402a0000 0 0x10000>;
+ };
+
+ watchdog@40310000 {
+ compatible = "sprd,sp9860-wdt";
+ reg = <0 0x40310000 0 0x1000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-sec = <12>;
+ clock-names = "enable";
+ clocks = <&aon_gate CLK_APCPU_WDG_EB>;
+ };
+ };
+
+ agcp {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ agcp_dma: dma-controller@41580000 {
+ compatible = "sprd,sc9860-dma";
+ reg = <0 0x41580000 0 0x4000>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ clock-names = "enable", "ashb_eb";
+ clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
+ <&agcp_gate CLK_AGCP_AP_ASHB_EB>;
+ };
+ };
};
ext_32k: ext_32k {
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index a2d67084a514..c2a0c00272e2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
new file mode 100644
index 000000000000..9c09baca7dd7
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/ {
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk200: clk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ clk250: clk250 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ clk300: clk300 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300000000>;
+ };
+
+ clk600: clk600 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
+ dp_aclk: clock0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-accuracy = <100>;
+ };
+
+ dp_aud_clk: clock1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ clock-accuracy = <100>;
+ };
+
+ dpdma_clk: dpdma_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <533000000>;
+ };
+
+ drm_clock: drm_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <262750000>;
+ clock-accuracy = <0x64>;
+ };
+};
+
+&can0 {
+ clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+ clocks = <&clk100 &clk100>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&gem0 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem1 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem2 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem3 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gpio {
+ clocks = <&clk100>;
+};
+
+&i2c0 {
+ clocks = <&clk100>;
+};
+
+&i2c1 {
+ clocks = <&clk100>;
+};
+
+&sata {
+ clocks = <&clk250>;
+};
+
+&sdhci0 {
+ clocks = <&clk200 &clk200>;
+};
+
+&sdhci1 {
+ clocks = <&clk200 &clk200>;
+};
+
+&spi0 {
+ clocks = <&clk200 &clk200>;
+};
+
+&spi1 {
+ clocks = <&clk200 &clk200>;
+};
+
+&uart0 {
+ clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+ clocks = <&clk100 &clk100>;
+};
+
+&usb0 {
+ clocks = <&clk250>, <&clk250>;
+};
+
+&usb1 {
+ clocks = <&clk250>, <&clk250>;
+};
+
+&watchdog0 {
+ clocks = <&clk250>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
index b87b8316f4ac..9f5eedbc2139 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* clock specification for Xilinx ZynqMP ep108 development board
*
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index bf552674a834..4b0684911626 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ep108 development board
*
@@ -47,7 +48,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- phy0: phy@0{
+ phy0: phy@0 {
reg = <0>;
max-speed = <100>;
};
@@ -78,10 +79,20 @@
&sata {
status = "okay";
ceva,broken-gen2;
+ /* SATA Phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+ ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+ ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+ ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+ ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+ ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
};
&sdhci0 {
status = "okay";
+ bus-width = <8>;
};
&sdhci1 {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
new file mode 100644
index 000000000000..0f7b4cf6078e
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1232 RevA";
+ compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
new file mode 100644
index 000000000000..9092828f92ec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1254
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1254 RevA";
+ compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
new file mode 100644
index 000000000000..4f404c580eec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1275 RevA";
+ compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 000000000000..9a3e39d1294f
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm015-dc1 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom: eeprom@55 {
+ compatible = "atmel,24c64"; /* 24AA64 */
+ reg = <0x55>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
new file mode 100644
index 000000000000..11cc67184fa9
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm016-dc2 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem2;
+ i2c0 = &i2c0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem2 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@5 {
+ reg = <5>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi0_flash0: flash0@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25wf080", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "data";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi1_flash0: flash0@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "data";
+ reg = <0x0 0x84000>;
+ };
+ };
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index 000000000000..7a49deeae647
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm017-dc3 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 { /* VSC8211 */
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+ status = "okay";
+};
+
+/* main */
+&uart0 {
+ status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 000000000000..54c7b4f1d1e4
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm018-dc4";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ ethernet2 = &gem2;
+ ethernet3 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy0>;
+ ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy7>;
+};
+
+&gem2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy3>;
+};
+
+&gem3 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy8>;
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644
index 000000000000..b8b5ff13818d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm019-dc5 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem1 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&ttc0 {
+ status = "okay";
+};
+
+&ttc1 {
+ status = "okay";
+};
+
+&ttc2 {
+ status = "okay";
+};
+
+&ttc3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
new file mode 100644
index 000000000000..3e862a9faf26
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU100 revC
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Nathalie Chan King Choy
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU100 RevC";
+ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+
+ aliases {
+ i2c0 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &dcc;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw4 {
+ label = "sw4";
+ gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds2 {
+ label = "ds2";
+ gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds3 {
+ label = "ds3";
+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx"; /* WLAN tx */
+ default-state = "off";
+ };
+
+ ds4 {
+ label = "ds4";
+ gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0rx"; /* WLAN rx */
+ default-state = "off";
+ };
+
+ ds5 {
+ label = "ds5";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ };
+
+ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+ label = "vbus_det";
+ gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ bt_power {
+ label = "bt_power";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ wmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "wmmcsdio_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sdio_pwrseq: sdio_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
+ "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
+ "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
+ "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
+ "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
+ "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
+ "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
+ "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
+ "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
+ "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
+ "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
+ "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ i2c-mux@75 { /* u11 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2csw_0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ label = "LS-I2C0";
+ };
+ i2csw_1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ label = "LS-I2C1";
+ };
+ i2csw_2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ label = "HS-I2C2";
+ };
+ i2csw_3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ label = "HS-I2C3";
+ };
+ i2csw_4: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pmic: pmic@5e { /* Custom TI PMIC u33 */
+ compatible = "ti,tps65086";
+ reg = <0x5e>;
+ interrupt-parent = <&gpio>;
+ interrupts = <77 GPIO_ACTIVE_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+ i2csw_5: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* PS_PMBUS */
+ ina226@40 { /* u35 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ /* MIO31 is alert which should be routed to PMUFW */
+ };
+ };
+ i2csw_6: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /*
+ * Not Connected
+ */
+ };
+ i2csw_7: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /*
+ * usb5744 (DNP) - U5
+ * 100kHz - this is default freq for us
+ */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+ broken-cd; /* CD has to be enabled by default */
+ disable-wp;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <0x4>;
+ non-removable;
+ disable-wp;
+ cap-power-off-card;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vqmmc-supply = <&wmmcsdio_fixed>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wifi@2 {
+ compatible = "ti,wl1831";
+ reg = <2>;
+ interrupt-parent = <&gpio>;
+ interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
+ };
+};
+
+&spi0 { /* Low Speed connector */
+ status = "okay";
+ label = "LS-SPI0";
+};
+
+&spi1 { /* High Speed connector */
+ status = "okay";
+ label = "HS-SPI1";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
new file mode 100644
index 000000000000..6647e97edba3
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revB.dts"
+
+/ {
+ model = "ZynqMP ZCU102 Rev1.0";
+ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&eeprom {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ board_sn: board-sn@0 {
+ reg = <0x0 0x14>;
+ };
+
+ eth_mac: eth-mac@20 {
+ reg = <0x20 0x6>;
+ };
+
+ board_name: board-name@d0 {
+ reg = <0xd0 0x6>;
+ };
+
+ board_revision: board-revision@e0 {
+ reg = <0xe0 0x3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
new file mode 100644
index 000000000000..5b4ffe646a9b
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevA
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU102 RevA";
+ compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@21 {
+ reg = <21>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - PS_GTR_LAN_SEL0
+ * 1 - PS_GTR_LAN_SEL1
+ * 2 - PS_GTR_LAN_SEL2
+ * 3 - PS_GTR_LAN_SEL3
+ * 4 - PCI_CLK_DIR_SEL
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7, 10 - 17 - not connected
+ */
+
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ output-low; /* PCIE = 0, DP = 1 */
+ line-name = "sel0";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ output-high; /* PCIE = 0, DP = 1 */
+ line-name = "sel1";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ output-high; /* PCIE = 0, USB0 = 1 */
+ line-name = "sel2";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ output-high; /* PCIE = 0, SATA = 1 */
+ line-name = "sel3";
+ };
+ };
+
+ tca6416_u61: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2c-mux@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+ max15303@20 { /* u8 */
+ compatible = "maxim,max15303";
+ status = "disabled"; /* unreachable */
+ reg = <0x20>;
+ };
+
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
+ };
+ };
+ /* 5 - 7 unconnected */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
new file mode 100644
index 000000000000..af4d86882a5c
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevB
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revA.dts"
+
+/ {
+ model = "ZynqMP ZCU102 RevB";
+ compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&gem3 {
+ phy-handle = <&phyc>;
+ phyc: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+ /* Cleanup from RevA */
+ /delete-node/ phy@21;
+};
+
+/* Fix collision with u61 */
+&i2c0 {
+ i2c-mux@75 {
+ i2c@2 {
+ max15303@1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ /delete-node/ max15303@20;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
new file mode 100644
index 000000000000..d4ad19a38c93
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU104 RevA";
+ compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+ reg = <0x6c>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
+ reg = <0x43>;
+ };
+ irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
+ reg = <0x4d>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ tca6416_u97: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - IRPS5401_ALERT_B
+ * 1 - HDMI_8T49N241_INT_ALM
+ * 2 - MAX6643_OT_B
+ * 3 - MAX6643_FANFAIL_B
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7 - FMC_LPC_PRSNT_M2C_B
+ * 4, 10 - 17 - not connected
+ */
+ };
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ /* 3, 6 not connected */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
new file mode 100644
index 000000000000..668f7f26716a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU106 RevA";
+ compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - SFP_SI5328_INT_ALM
+ * 1 - HDMI_SI5328_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMC_HPC0_PRSNT_M2C_B
+ * 11 - FMC_HPC1_PRSNT_M2C_B
+ * 2-4, 7, 12-17 - not connected
+ */
+ };
+
+ tca6416_u61: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2c-mux@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ };
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>; /* FAN controller */
+ temp@4c {/* lm96163 - u128 */
+ compatible = "national,lm96163";
+ reg = <0x4c>;
+ };
+ };
+ /* 6 - 7 unconnected */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
new file mode 100644
index 000000000000..9a9dd6a0142b
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU111 RevA";
+ compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u22: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - MAX6643_OT_B
+ * 1 - MAX6643_FANFAIL_B
+ * 2 - MIO26_PMU_INPUT_LS
+ * 4 - SFP_SI5382_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMCP_HSPC_PRSNT_M2C_B
+ * 11 - CLK_SPI_MUX_SEL0
+ * 12 - CLK_SPI_MUX_SEL1
+ * 16 - IRPS5401_ALERT_B
+ * 17 - INA226_PMBUS_ALERT
+ * 3, 7, 13-15 - not connected
+ */
+ };
+
+ i2c-mux@75 { /* u23 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ ina226@40 { /* u67 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u59 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u61 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u60 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u64 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u69 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ ina226@47 { /* u66 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@48 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ ina226@49 { /* u63 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u3 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u71 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4c { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4d { /* u73 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4e { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
+ reg = <0x43>;
+ };
+ irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
+ reg = <0x44>;
+ };
+ irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
+ reg = <0x45>;
+ };
+ /* u68 IR38064 +0 */
+ /* u70 IR38060 +1 */
+ /* u74 IR38060 +2 */
+ /* u75 IR38060 +6 */
+ /* J19 header too */
+
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2c-mux@74 { /* u26 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u88 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u46 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator@69 { /* SI5328 - u48 */
+ reg = <0x69>;
+ };
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ sc18is603@2f { /* sc18is602 - u93 */
+ compatible = "nxp,sc18is603";
+ reg = <0x2f>;
+ /* 4 gpios for CS not handled by driver */
+ /*
+ * USB2ANY cable or
+ * LMK04208 - u90 or
+ * LMX2594 - u102 or
+ * LMX2594 - u103 or
+ * LMX2594 - u104
+ */
+ };
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* FMC connector */
+ };
+ /* 7 NC */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u27 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 7665fbddff28..a091e6f03014 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP
*
@@ -355,7 +356,7 @@
};
gem0: ethernet@ff0b0000 {
- compatible = "cdns,gem";
+ compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
@@ -366,7 +367,7 @@
};
gem1: ethernet@ff0c0000 {
- compatible = "cdns,gem";
+ compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
@@ -377,7 +378,7 @@
};
gem2: ethernet@ff0d0000 {
- compatible = "cdns,gem";
+ compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
@@ -388,7 +389,7 @@
};
gem3: ethernet@ff0e0000 {
- compatible = "cdns,gem";
+ compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
@@ -439,10 +440,10 @@
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = <0 118 4>,
- <0 117 4>,
- <0 116 4>,
- <0 115 4>, /* MSI_1 [63...32] */
- <0 114 4>; /* MSI_0 [31...0] */
+ <0 117 4>,
+ <0 116 4>,
+ <0 115 4>, /* MSI_1 [63...32] */
+ <0 114 4>; /* MSI_0 [31...0] */
interrupt-names = "misc", "dummy", "intx",
"msi1", "msi0";
msi-parent = <&pcie>;
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 634b373785c4..ecf613761e78 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,7 +31,6 @@ CONFIG_PROFILING=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
CONFIG_ARCH_BCM2835=y
@@ -51,11 +50,14 @@ CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_R8A7795=y
CONFIG_ARCH_R8A7796=y
+CONFIG_ARCH_R8A77965=y
CONFIG_ARCH_R8A77970=y
+CONFIG_ARCH_R8A77980=y
CONFIG_ARCH_R8A77995=y
CONFIG_ARCH_STRATIX10=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_SPRD=y
+CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_THUNDER2=y
CONFIG_ARCH_UNIPHIER=y
@@ -99,10 +101,19 @@ CONFIG_HIBERNATION=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_ARM_CPUIDLE=y
CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_TEGRA186_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_NET=y
CONFIG_PACKET=y
@@ -209,7 +220,14 @@ CONFIG_QCOM_EMAC=m
CONFIG_RAVB=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
+CONFIG_SNI_AVE=y
+CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
+CONFIG_DWMAC_IPQ806X=m
+CONFIG_DWMAC_MESON=m
+CONFIG_DWMAC_ROCKCHIP=m
+CONFIG_DWMAC_SUNXI=m
+CONFIG_DWMAC_SUN8I=m
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_AT803X_PHY=m
CONFIG_MARVELL_PHY=m
@@ -305,6 +323,7 @@ CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_QDF2XXX=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_MB86S7X=y
CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_UNIPHIER=y
@@ -327,7 +346,10 @@ CONFIG_THERMAL_EMULATION=y
CONFIG_BRCMSTB_THERMAL=m
CONFIG_EXYNOS_THERMAL=y
CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_QCOM_TSENS=y
CONFIG_ROCKCHIP_THERMAL=m
+CONFIG_TEGRA_BPMP_THERMAL=m
+CONFIG_UNIPHIER_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_MESON_GXBB_WATCHDOG=m
@@ -444,12 +466,14 @@ CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_RENESAS_USB3=m
CONFIG_USB_ULPI_BUS=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_F_SDH30=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
@@ -500,6 +524,7 @@ CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_RCAR_DMAC=y
+CONFIG_RENESAS_USB_DMAC=m
CONFIG_VFIO=y
CONFIG_VFIO_PCI=y
CONFIG_VIRTIO_PCI=y
@@ -525,7 +550,9 @@ CONFIG_ARM_MHU=y
CONFIG_PLATFORM_MHU=y
CONFIG_BCM2835_MBOX=y
CONFIG_HI6220_MBOX=y
+CONFIG_QCOM_APCS_IPC=y
CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y
CONFIG_QCOM_IOMMU=y
@@ -539,7 +566,10 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ARCH_TEGRA_132_SOC=y
CONFIG_ARCH_TEGRA_210_SOC=y
CONFIG_ARCH_TEGRA_186_SOC=y
+CONFIG_ARCH_TEGRA_194_SOC=y
CONFIG_EXTCON_USB_GPIO=y
+CONFIG_MEMORY=y
+CONFIG_TEGRA_MC=y
CONFIG_IIO=y
CONFIG_EXYNOS_ADC=y
CONFIG_ROCKCHIP_SARADC=m
@@ -547,10 +577,12 @@ CONFIG_PWM=y
CONFIG_PWM_BCM2835=m
CONFIG_PWM_CROS_EC=m
CONFIG_PWM_MESON=m
+CONFIG_PWM_RCAR=m
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_TEGRA=m
CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=m
CONFIG_PHY_HI6220_USB=y
CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_SUN4I_USB=y
@@ -562,6 +594,8 @@ CONFIG_PHY_XGENE=y
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
+CONFIG_MESON_EFUSE=m
+CONFIG_QCOM_QFPROM=y
CONFIG_UNIPHIER_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
@@ -629,3 +663,6 @@ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_AES_ARM64_BS=m
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig
index 285c36c7b408..cb5a243110c4 100644
--- a/arch/arm64/crypto/Kconfig
+++ b/arch/arm64/crypto/Kconfig
@@ -113,4 +113,10 @@ config CRYPTO_AES_ARM64_BS
select CRYPTO_AES_ARM64
select CRYPTO_SIMD
+config CRYPTO_SPECK_NEON
+ tristate "NEON accelerated Speck cipher algorithms"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_SPECK
+
endif
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index cee9b8d9830b..f35ac684b1c0 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -53,20 +53,21 @@ sha512-arm64-y := sha512-glue.o sha512-core.o
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha20-neon.o
chacha20-neon-y := chacha20-neon-core.o chacha20-neon-glue.o
+obj-$(CONFIG_CRYPTO_SPECK_NEON) += speck-neon.o
+speck-neon-y := speck-neon-core.o speck-neon-glue.o
+
obj-$(CONFIG_CRYPTO_AES_ARM64) += aes-arm64.o
aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
obj-$(CONFIG_CRYPTO_AES_ARM64_BS) += aes-neon-bs.o
aes-neon-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
-AFLAGS_aes-ce.o := -DINTERLEAVE=4
-AFLAGS_aes-neon.o := -DINTERLEAVE=4
-
CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
$(obj)/aes-glue-%.o: $(src)/aes-glue.c FORCE
$(call if_changed_rule,cc_o_c)
+ifdef REGENERATE_ARM64_CRYPTO
quiet_cmd_perlasm = PERLASM $@
cmd_perlasm = $(PERL) $(<) void $(@)
@@ -75,5 +76,6 @@ $(src)/sha256-core.S_shipped: $(src)/sha512-armv8.pl
$(src)/sha512-core.S_shipped: $(src)/sha512-armv8.pl
$(call cmd,perlasm)
+endif
-.PRECIOUS: $(obj)/sha256-core.S $(obj)/sha512-core.S
+targets += sha256-core.S sha512-core.S
diff --git a/arch/arm64/crypto/aes-ce-ccm-glue.c b/arch/arm64/crypto/aes-ce-ccm-glue.c
index a1254036f2b1..68b11aa690e4 100644
--- a/arch/arm64/crypto/aes-ce-ccm-glue.c
+++ b/arch/arm64/crypto/aes-ce-ccm-glue.c
@@ -107,11 +107,13 @@ static int ccm_init_mac(struct aead_request *req, u8 maciv[], u32 msglen)
}
static void ccm_update_mac(struct crypto_aes_ctx *key, u8 mac[], u8 const in[],
- u32 abytes, u32 *macp, bool use_neon)
+ u32 abytes, u32 *macp)
{
- if (likely(use_neon)) {
+ if (may_use_simd()) {
+ kernel_neon_begin();
ce_aes_ccm_auth_data(mac, in, abytes, macp, key->key_enc,
num_rounds(key));
+ kernel_neon_end();
} else {
if (*macp > 0 && *macp < AES_BLOCK_SIZE) {
int added = min(abytes, AES_BLOCK_SIZE - *macp);
@@ -143,8 +145,7 @@ static void ccm_update_mac(struct crypto_aes_ctx *key, u8 mac[], u8 const in[],
}
}
-static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[],
- bool use_neon)
+static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[])
{
struct crypto_aead *aead = crypto_aead_reqtfm(req);
struct crypto_aes_ctx *ctx = crypto_aead_ctx(aead);
@@ -163,7 +164,7 @@ static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[],
ltag.len = 6;
}
- ccm_update_mac(ctx, mac, (u8 *)&ltag, ltag.len, &macp, use_neon);
+ ccm_update_mac(ctx, mac, (u8 *)&ltag, ltag.len, &macp);
scatterwalk_start(&walk, req->src);
do {
@@ -175,7 +176,7 @@ static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[],
n = scatterwalk_clamp(&walk, len);
}
p = scatterwalk_map(&walk);
- ccm_update_mac(ctx, mac, p, n, &macp, use_neon);
+ ccm_update_mac(ctx, mac, p, n, &macp);
len -= n;
scatterwalk_unmap(p);
@@ -242,43 +243,42 @@ static int ccm_encrypt(struct aead_request *req)
u8 __aligned(8) mac[AES_BLOCK_SIZE];
u8 buf[AES_BLOCK_SIZE];
u32 len = req->cryptlen;
- bool use_neon = may_use_simd();
int err;
err = ccm_init_mac(req, mac, len);
if (err)
return err;
- if (likely(use_neon))
- kernel_neon_begin();
-
if (req->assoclen)
- ccm_calculate_auth_mac(req, mac, use_neon);
+ ccm_calculate_auth_mac(req, mac);
/* preserve the original iv for the final round */
memcpy(buf, req->iv, AES_BLOCK_SIZE);
err = skcipher_walk_aead_encrypt(&walk, req, true);
- if (likely(use_neon)) {
+ if (may_use_simd()) {
while (walk.nbytes) {
u32 tail = walk.nbytes % AES_BLOCK_SIZE;
if (walk.nbytes == walk.total)
tail = 0;
+ kernel_neon_begin();
ce_aes_ccm_encrypt(walk.dst.virt.addr,
walk.src.virt.addr,
walk.nbytes - tail, ctx->key_enc,
num_rounds(ctx), mac, walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, tail);
}
- if (!err)
+ if (!err) {
+ kernel_neon_begin();
ce_aes_ccm_final(mac, buf, ctx->key_enc,
num_rounds(ctx));
-
- kernel_neon_end();
+ kernel_neon_end();
+ }
} else {
err = ccm_crypt_fallback(&walk, mac, buf, ctx, true);
}
@@ -301,43 +301,42 @@ static int ccm_decrypt(struct aead_request *req)
u8 __aligned(8) mac[AES_BLOCK_SIZE];
u8 buf[AES_BLOCK_SIZE];
u32 len = req->cryptlen - authsize;
- bool use_neon = may_use_simd();
int err;
err = ccm_init_mac(req, mac, len);
if (err)
return err;
- if (likely(use_neon))
- kernel_neon_begin();
-
if (req->assoclen)
- ccm_calculate_auth_mac(req, mac, use_neon);
+ ccm_calculate_auth_mac(req, mac);
/* preserve the original iv for the final round */
memcpy(buf, req->iv, AES_BLOCK_SIZE);
err = skcipher_walk_aead_decrypt(&walk, req, true);
- if (likely(use_neon)) {
+ if (may_use_simd()) {
while (walk.nbytes) {
u32 tail = walk.nbytes % AES_BLOCK_SIZE;
if (walk.nbytes == walk.total)
tail = 0;
+ kernel_neon_begin();
ce_aes_ccm_decrypt(walk.dst.virt.addr,
walk.src.virt.addr,
walk.nbytes - tail, ctx->key_enc,
num_rounds(ctx), mac, walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, tail);
}
- if (!err)
+ if (!err) {
+ kernel_neon_begin();
ce_aes_ccm_final(mac, buf, ctx->key_enc,
num_rounds(ctx));
-
- kernel_neon_end();
+ kernel_neon_end();
+ }
} else {
err = ccm_crypt_fallback(&walk, mac, buf, ctx, false);
}
diff --git a/arch/arm64/crypto/aes-glue.c b/arch/arm64/crypto/aes-glue.c
index 2fa850e86aa8..253188fb8cb0 100644
--- a/arch/arm64/crypto/aes-glue.c
+++ b/arch/arm64/crypto/aes-glue.c
@@ -64,17 +64,17 @@ MODULE_LICENSE("GPL v2");
/* defined in aes-modes.S */
asmlinkage void aes_ecb_encrypt(u8 out[], u8 const in[], u8 const rk[],
- int rounds, int blocks, int first);
+ int rounds, int blocks);
asmlinkage void aes_ecb_decrypt(u8 out[], u8 const in[], u8 const rk[],
- int rounds, int blocks, int first);
+ int rounds, int blocks);
asmlinkage void aes_cbc_encrypt(u8 out[], u8 const in[], u8 const rk[],
- int rounds, int blocks, u8 iv[], int first);
+ int rounds, int blocks, u8 iv[]);
asmlinkage void aes_cbc_decrypt(u8 out[], u8 const in[], u8 const rk[],
- int rounds, int blocks, u8 iv[], int first);
+ int rounds, int blocks, u8 iv[]);
asmlinkage void aes_ctr_encrypt(u8 out[], u8 const in[], u8 const rk[],
- int rounds, int blocks, u8 ctr[], int first);
+ int rounds, int blocks, u8 ctr[]);
asmlinkage void aes_xts_encrypt(u8 out[], u8 const in[], u8 const rk1[],
int rounds, int blocks, u8 const rk2[], u8 iv[],
@@ -133,19 +133,19 @@ static int ecb_encrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
- int err, first, rounds = 6 + ctx->key_length / 4;
+ int err, rounds = 6 + ctx->key_length / 4;
struct skcipher_walk walk;
unsigned int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
- for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) {
+ while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) {
+ kernel_neon_begin();
aes_ecb_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
- (u8 *)ctx->key_enc, rounds, blocks, first);
+ (u8 *)ctx->key_enc, rounds, blocks);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -153,19 +153,19 @@ static int ecb_decrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
- int err, first, rounds = 6 + ctx->key_length / 4;
+ int err, rounds = 6 + ctx->key_length / 4;
struct skcipher_walk walk;
unsigned int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
- for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) {
+ while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) {
+ kernel_neon_begin();
aes_ecb_decrypt(walk.dst.virt.addr, walk.src.virt.addr,
- (u8 *)ctx->key_dec, rounds, blocks, first);
+ (u8 *)ctx->key_dec, rounds, blocks);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -173,20 +173,19 @@ static int cbc_encrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
- int err, first, rounds = 6 + ctx->key_length / 4;
+ int err, rounds = 6 + ctx->key_length / 4;
struct skcipher_walk walk;
unsigned int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
- for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) {
+ while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) {
+ kernel_neon_begin();
aes_cbc_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
- (u8 *)ctx->key_enc, rounds, blocks, walk.iv,
- first);
+ (u8 *)ctx->key_enc, rounds, blocks, walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -194,20 +193,19 @@ static int cbc_decrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
- int err, first, rounds = 6 + ctx->key_length / 4;
+ int err, rounds = 6 + ctx->key_length / 4;
struct skcipher_walk walk;
unsigned int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
- for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) {
+ while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) {
+ kernel_neon_begin();
aes_cbc_decrypt(walk.dst.virt.addr, walk.src.virt.addr,
- (u8 *)ctx->key_dec, rounds, blocks, walk.iv,
- first);
+ (u8 *)ctx->key_dec, rounds, blocks, walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -215,20 +213,18 @@ static int ctr_encrypt(struct skcipher_request *req)
{
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
- int err, first, rounds = 6 + ctx->key_length / 4;
+ int err, rounds = 6 + ctx->key_length / 4;
struct skcipher_walk walk;
int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- first = 1;
- kernel_neon_begin();
while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) {
+ kernel_neon_begin();
aes_ctr_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
- (u8 *)ctx->key_enc, rounds, blocks, walk.iv,
- first);
+ (u8 *)ctx->key_enc, rounds, blocks, walk.iv);
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
- first = 0;
+ kernel_neon_end();
}
if (walk.nbytes) {
u8 __aligned(8) tail[AES_BLOCK_SIZE];
@@ -241,12 +237,13 @@ static int ctr_encrypt(struct skcipher_request *req)
*/
blocks = -1;
+ kernel_neon_begin();
aes_ctr_encrypt(tail, NULL, (u8 *)ctx->key_enc, rounds,
- blocks, walk.iv, first);
+ blocks, walk.iv);
+ kernel_neon_end();
crypto_xor_cpy(tdst, tsrc, tail, nbytes);
err = skcipher_walk_done(&walk, 0);
}
- kernel_neon_end();
return err;
}
@@ -270,16 +267,16 @@ static int xts_encrypt(struct skcipher_request *req)
struct skcipher_walk walk;
unsigned int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) {
+ kernel_neon_begin();
aes_xts_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
(u8 *)ctx->key1.key_enc, rounds, blocks,
(u8 *)ctx->key2.key_enc, walk.iv, first);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -292,16 +289,16 @@ static int xts_decrypt(struct skcipher_request *req)
struct skcipher_walk walk;
unsigned int blocks;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) {
+ kernel_neon_begin();
aes_xts_decrypt(walk.dst.virt.addr, walk.src.virt.addr,
(u8 *)ctx->key1.key_dec, rounds, blocks,
(u8 *)ctx->key2.key_enc, walk.iv, first);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -425,7 +422,7 @@ static int cmac_setkey(struct crypto_shash *tfm, const u8 *in_key,
/* encrypt the zero vector */
kernel_neon_begin();
- aes_ecb_encrypt(ctx->consts, (u8[AES_BLOCK_SIZE]){}, rk, rounds, 1, 1);
+ aes_ecb_encrypt(ctx->consts, (u8[AES_BLOCK_SIZE]){}, rk, rounds, 1);
kernel_neon_end();
cmac_gf128_mul_by_x(consts, consts);
@@ -454,8 +451,8 @@ static int xcbc_setkey(struct crypto_shash *tfm, const u8 *in_key,
return err;
kernel_neon_begin();
- aes_ecb_encrypt(key, ks[0], rk, rounds, 1, 1);
- aes_ecb_encrypt(ctx->consts, ks[1], rk, rounds, 2, 0);
+ aes_ecb_encrypt(key, ks[0], rk, rounds, 1);
+ aes_ecb_encrypt(ctx->consts, ks[1], rk, rounds, 2);
kernel_neon_end();
return cbcmac_setkey(tfm, key, sizeof(key));
diff --git a/arch/arm64/crypto/aes-modes.S b/arch/arm64/crypto/aes-modes.S
index 2674d43d1384..a68412e1e3a4 100644
--- a/arch/arm64/crypto/aes-modes.S
+++ b/arch/arm64/crypto/aes-modes.S
@@ -13,127 +13,39 @@
.text
.align 4
-/*
- * There are several ways to instantiate this code:
- * - no interleave, all inline
- * - 2-way interleave, 2x calls out of line (-DINTERLEAVE=2)
- * - 2-way interleave, all inline (-DINTERLEAVE=2 -DINTERLEAVE_INLINE)
- * - 4-way interleave, 4x calls out of line (-DINTERLEAVE=4)
- * - 4-way interleave, all inline (-DINTERLEAVE=4 -DINTERLEAVE_INLINE)
- *
- * Macros imported by this code:
- * - enc_prepare - setup NEON registers for encryption
- * - dec_prepare - setup NEON registers for decryption
- * - enc_switch_key - change to new key after having prepared for encryption
- * - encrypt_block - encrypt a single block
- * - decrypt block - decrypt a single block
- * - encrypt_block2x - encrypt 2 blocks in parallel (if INTERLEAVE == 2)
- * - decrypt_block2x - decrypt 2 blocks in parallel (if INTERLEAVE == 2)
- * - encrypt_block4x - encrypt 4 blocks in parallel (if INTERLEAVE == 4)
- * - decrypt_block4x - decrypt 4 blocks in parallel (if INTERLEAVE == 4)
- */
-
-#if defined(INTERLEAVE) && !defined(INTERLEAVE_INLINE)
-#define FRAME_PUSH stp x29, x30, [sp,#-16]! ; mov x29, sp
-#define FRAME_POP ldp x29, x30, [sp],#16
-
-#if INTERLEAVE == 2
-
-aes_encrypt_block2x:
- encrypt_block2x v0, v1, w3, x2, x6, w7
- ret
-ENDPROC(aes_encrypt_block2x)
-
-aes_decrypt_block2x:
- decrypt_block2x v0, v1, w3, x2, x6, w7
- ret
-ENDPROC(aes_decrypt_block2x)
-
-#elif INTERLEAVE == 4
-
aes_encrypt_block4x:
- encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
+ encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
ret
ENDPROC(aes_encrypt_block4x)
aes_decrypt_block4x:
- decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
+ decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
ret
ENDPROC(aes_decrypt_block4x)
-#else
-#error INTERLEAVE should equal 2 or 4
-#endif
-
- .macro do_encrypt_block2x
- bl aes_encrypt_block2x
- .endm
-
- .macro do_decrypt_block2x
- bl aes_decrypt_block2x
- .endm
-
- .macro do_encrypt_block4x
- bl aes_encrypt_block4x
- .endm
-
- .macro do_decrypt_block4x
- bl aes_decrypt_block4x
- .endm
-
-#else
-#define FRAME_PUSH
-#define FRAME_POP
-
- .macro do_encrypt_block2x
- encrypt_block2x v0, v1, w3, x2, x6, w7
- .endm
-
- .macro do_decrypt_block2x
- decrypt_block2x v0, v1, w3, x2, x6, w7
- .endm
-
- .macro do_encrypt_block4x
- encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
- .endm
-
- .macro do_decrypt_block4x
- decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
- .endm
-
-#endif
-
/*
* aes_ecb_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
- * int blocks, int first)
+ * int blocks)
* aes_ecb_decrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
- * int blocks, int first)
+ * int blocks)
*/
AES_ENTRY(aes_ecb_encrypt)
- FRAME_PUSH
- cbz w5, .LecbencloopNx
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
enc_prepare w3, x2, x5
.LecbencloopNx:
-#if INTERLEAVE >= 2
- subs w4, w4, #INTERLEAVE
+ subs w4, w4, #4
bmi .Lecbenc1x
-#if INTERLEAVE == 2
- ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
- do_encrypt_block2x
- st1 {v0.16b-v1.16b}, [x0], #32
-#else
ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
- do_encrypt_block4x
+ bl aes_encrypt_block4x
st1 {v0.16b-v3.16b}, [x0], #64
-#endif
b .LecbencloopNx
.Lecbenc1x:
- adds w4, w4, #INTERLEAVE
+ adds w4, w4, #4
beq .Lecbencout
-#endif
.Lecbencloop:
ld1 {v0.16b}, [x1], #16 /* get next pt block */
encrypt_block v0, w3, x2, x5, w6
@@ -141,35 +53,27 @@ AES_ENTRY(aes_ecb_encrypt)
subs w4, w4, #1
bne .Lecbencloop
.Lecbencout:
- FRAME_POP
+ ldp x29, x30, [sp], #16
ret
AES_ENDPROC(aes_ecb_encrypt)
AES_ENTRY(aes_ecb_decrypt)
- FRAME_PUSH
- cbz w5, .LecbdecloopNx
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
dec_prepare w3, x2, x5
.LecbdecloopNx:
-#if INTERLEAVE >= 2
- subs w4, w4, #INTERLEAVE
+ subs w4, w4, #4
bmi .Lecbdec1x
-#if INTERLEAVE == 2
- ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 ct blocks */
- do_decrypt_block2x
- st1 {v0.16b-v1.16b}, [x0], #32
-#else
ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
- do_decrypt_block4x
+ bl aes_decrypt_block4x
st1 {v0.16b-v3.16b}, [x0], #64
-#endif
b .LecbdecloopNx
.Lecbdec1x:
- adds w4, w4, #INTERLEAVE
+ adds w4, w4, #4
beq .Lecbdecout
-#endif
.Lecbdecloop:
ld1 {v0.16b}, [x1], #16 /* get next ct block */
decrypt_block v0, w3, x2, x5, w6
@@ -177,62 +81,68 @@ AES_ENTRY(aes_ecb_decrypt)
subs w4, w4, #1
bne .Lecbdecloop
.Lecbdecout:
- FRAME_POP
+ ldp x29, x30, [sp], #16
ret
AES_ENDPROC(aes_ecb_decrypt)
/*
* aes_cbc_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
- * int blocks, u8 iv[], int first)
+ * int blocks, u8 iv[])
* aes_cbc_decrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
- * int blocks, u8 iv[], int first)
+ * int blocks, u8 iv[])
*/
AES_ENTRY(aes_cbc_encrypt)
- cbz w6, .Lcbcencloop
-
- ld1 {v0.16b}, [x5] /* get iv */
+ ld1 {v4.16b}, [x5] /* get iv */
enc_prepare w3, x2, x6
-.Lcbcencloop:
- ld1 {v1.16b}, [x1], #16 /* get next pt block */
- eor v0.16b, v0.16b, v1.16b /* ..and xor with iv */
+.Lcbcencloop4x:
+ subs w4, w4, #4
+ bmi .Lcbcenc1x
+ ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
+ eor v0.16b, v0.16b, v4.16b /* ..and xor with iv */
encrypt_block v0, w3, x2, x6, w7
- st1 {v0.16b}, [x0], #16
+ eor v1.16b, v1.16b, v0.16b
+ encrypt_block v1, w3, x2, x6, w7
+ eor v2.16b, v2.16b, v1.16b
+ encrypt_block v2, w3, x2, x6, w7
+ eor v3.16b, v3.16b, v2.16b
+ encrypt_block v3, w3, x2, x6, w7
+ st1 {v0.16b-v3.16b}, [x0], #64
+ mov v4.16b, v3.16b
+ b .Lcbcencloop4x
+.Lcbcenc1x:
+ adds w4, w4, #4
+ beq .Lcbcencout
+.Lcbcencloop:
+ ld1 {v0.16b}, [x1], #16 /* get next pt block */
+ eor v4.16b, v4.16b, v0.16b /* ..and xor with iv */
+ encrypt_block v4, w3, x2, x6, w7
+ st1 {v4.16b}, [x0], #16
subs w4, w4, #1
bne .Lcbcencloop
- st1 {v0.16b}, [x5] /* return iv */
+.Lcbcencout:
+ st1 {v4.16b}, [x5] /* return iv */
ret
AES_ENDPROC(aes_cbc_encrypt)
AES_ENTRY(aes_cbc_decrypt)
- FRAME_PUSH
- cbz w6, .LcbcdecloopNx
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
ld1 {v7.16b}, [x5] /* get iv */
dec_prepare w3, x2, x6
.LcbcdecloopNx:
-#if INTERLEAVE >= 2
- subs w4, w4, #INTERLEAVE
+ subs w4, w4, #4
bmi .Lcbcdec1x
-#if INTERLEAVE == 2
- ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 ct blocks */
- mov v2.16b, v0.16b
- mov v3.16b, v1.16b
- do_decrypt_block2x
- eor v0.16b, v0.16b, v7.16b
- eor v1.16b, v1.16b, v2.16b
- mov v7.16b, v3.16b
- st1 {v0.16b-v1.16b}, [x0], #32
-#else
ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
mov v4.16b, v0.16b
mov v5.16b, v1.16b
mov v6.16b, v2.16b
- do_decrypt_block4x
+ bl aes_decrypt_block4x
sub x1, x1, #16
eor v0.16b, v0.16b, v7.16b
eor v1.16b, v1.16b, v4.16b
@@ -240,12 +150,10 @@ AES_ENTRY(aes_cbc_decrypt)
eor v2.16b, v2.16b, v5.16b
eor v3.16b, v3.16b, v6.16b
st1 {v0.16b-v3.16b}, [x0], #64
-#endif
b .LcbcdecloopNx
.Lcbcdec1x:
- adds w4, w4, #INTERLEAVE
+ adds w4, w4, #4
beq .Lcbcdecout
-#endif
.Lcbcdecloop:
ld1 {v1.16b}, [x1], #16 /* get next ct block */
mov v0.16b, v1.16b /* ...and copy to v0 */
@@ -256,49 +164,33 @@ AES_ENTRY(aes_cbc_decrypt)
subs w4, w4, #1
bne .Lcbcdecloop
.Lcbcdecout:
- FRAME_POP
st1 {v7.16b}, [x5] /* return iv */
+ ldp x29, x30, [sp], #16
ret
AES_ENDPROC(aes_cbc_decrypt)
/*
* aes_ctr_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
- * int blocks, u8 ctr[], int first)
+ * int blocks, u8 ctr[])
*/
AES_ENTRY(aes_ctr_encrypt)
- FRAME_PUSH
- cbz w6, .Lctrnotfirst /* 1st time around? */
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
+
enc_prepare w3, x2, x6
ld1 {v4.16b}, [x5]
-.Lctrnotfirst:
- umov x8, v4.d[1] /* keep swabbed ctr in reg */
- rev x8, x8
-#if INTERLEAVE >= 2
- cmn w8, w4 /* 32 bit overflow? */
+ umov x6, v4.d[1] /* keep swabbed ctr in reg */
+ rev x6, x6
+ cmn w6, w4 /* 32 bit overflow? */
bcs .Lctrloop
.LctrloopNx:
- subs w4, w4, #INTERLEAVE
+ subs w4, w4, #4
bmi .Lctr1x
-#if INTERLEAVE == 2
- mov v0.8b, v4.8b
- mov v1.8b, v4.8b
- rev x7, x8
- add x8, x8, #1
- ins v0.d[1], x7
- rev x7, x8
- add x8, x8, #1
- ins v1.d[1], x7
- ld1 {v2.16b-v3.16b}, [x1], #32 /* get 2 input blocks */
- do_encrypt_block2x
- eor v0.16b, v0.16b, v2.16b
- eor v1.16b, v1.16b, v3.16b
- st1 {v0.16b-v1.16b}, [x0], #32
-#else
ldr q8, =0x30000000200000001 /* addends 1,2,3[,0] */
- dup v7.4s, w8
+ dup v7.4s, w6
mov v0.16b, v4.16b
add v7.4s, v7.4s, v8.4s
mov v1.16b, v4.16b
@@ -309,29 +201,27 @@ AES_ENTRY(aes_ctr_encrypt)
mov v2.s[3], v8.s[1]
mov v3.s[3], v8.s[2]
ld1 {v5.16b-v7.16b}, [x1], #48 /* get 3 input blocks */
- do_encrypt_block4x
+ bl aes_encrypt_block4x
eor v0.16b, v5.16b, v0.16b
ld1 {v5.16b}, [x1], #16 /* get 1 input block */
eor v1.16b, v6.16b, v1.16b
eor v2.16b, v7.16b, v2.16b
eor v3.16b, v5.16b, v3.16b
st1 {v0.16b-v3.16b}, [x0], #64
- add x8, x8, #INTERLEAVE
-#endif
- rev x7, x8
+ add x6, x6, #4
+ rev x7, x6
ins v4.d[1], x7
cbz w4, .Lctrout
b .LctrloopNx
.Lctr1x:
- adds w4, w4, #INTERLEAVE
+ adds w4, w4, #4
beq .Lctrout
-#endif
.Lctrloop:
mov v0.16b, v4.16b
- encrypt_block v0, w3, x2, x6, w7
+ encrypt_block v0, w3, x2, x8, w7
- adds x8, x8, #1 /* increment BE ctr */
- rev x7, x8
+ adds x6, x6, #1 /* increment BE ctr */
+ rev x7, x6
ins v4.d[1], x7
bcs .Lctrcarry /* overflow? */
@@ -345,12 +235,12 @@ AES_ENTRY(aes_ctr_encrypt)
.Lctrout:
st1 {v4.16b}, [x5] /* return next CTR value */
- FRAME_POP
+ ldp x29, x30, [sp], #16
ret
.Lctrtailblock:
st1 {v0.16b}, [x0]
- FRAME_POP
+ ldp x29, x30, [sp], #16
ret
.Lctrcarry:
@@ -384,39 +274,26 @@ CPU_LE( .quad 1, 0x87 )
CPU_BE( .quad 0x87, 1 )
AES_ENTRY(aes_xts_encrypt)
- FRAME_PUSH
- cbz w7, .LxtsencloopNx
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
ld1 {v4.16b}, [x6]
- enc_prepare w3, x5, x6
- encrypt_block v4, w3, x5, x6, w7 /* first tweak */
- enc_switch_key w3, x2, x6
+ cbz w7, .Lxtsencnotfirst
+
+ enc_prepare w3, x5, x8
+ encrypt_block v4, w3, x5, x8, w7 /* first tweak */
+ enc_switch_key w3, x2, x8
ldr q7, .Lxts_mul_x
b .LxtsencNx
+.Lxtsencnotfirst:
+ enc_prepare w3, x2, x8
.LxtsencloopNx:
ldr q7, .Lxts_mul_x
next_tweak v4, v4, v7, v8
.LxtsencNx:
-#if INTERLEAVE >= 2
- subs w4, w4, #INTERLEAVE
+ subs w4, w4, #4
bmi .Lxtsenc1x
-#if INTERLEAVE == 2
- ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
- next_tweak v5, v4, v7, v8
- eor v0.16b, v0.16b, v4.16b
- eor v1.16b, v1.16b, v5.16b
- do_encrypt_block2x
- eor v0.16b, v0.16b, v4.16b
- eor v1.16b, v1.16b, v5.16b
- st1 {v0.16b-v1.16b}, [x0], #32
- cbz w4, .LxtsencoutNx
- next_tweak v4, v5, v7, v8
- b .LxtsencNx
-.LxtsencoutNx:
- mov v4.16b, v5.16b
- b .Lxtsencout
-#else
ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
next_tweak v5, v4, v7, v8
eor v0.16b, v0.16b, v4.16b
@@ -425,7 +302,7 @@ AES_ENTRY(aes_xts_encrypt)
eor v2.16b, v2.16b, v6.16b
next_tweak v7, v6, v7, v8
eor v3.16b, v3.16b, v7.16b
- do_encrypt_block4x
+ bl aes_encrypt_block4x
eor v3.16b, v3.16b, v7.16b
eor v0.16b, v0.16b, v4.16b
eor v1.16b, v1.16b, v5.16b
@@ -434,15 +311,13 @@ AES_ENTRY(aes_xts_encrypt)
mov v4.16b, v7.16b
cbz w4, .Lxtsencout
b .LxtsencloopNx
-#endif
.Lxtsenc1x:
- adds w4, w4, #INTERLEAVE
+ adds w4, w4, #4
beq .Lxtsencout
-#endif
.Lxtsencloop:
ld1 {v1.16b}, [x1], #16
eor v0.16b, v1.16b, v4.16b
- encrypt_block v0, w3, x2, x6, w7
+ encrypt_block v0, w3, x2, x8, w7
eor v0.16b, v0.16b, v4.16b
st1 {v0.16b}, [x0], #16
subs w4, w4, #1
@@ -450,45 +325,33 @@ AES_ENTRY(aes_xts_encrypt)
next_tweak v4, v4, v7, v8
b .Lxtsencloop
.Lxtsencout:
- FRAME_POP
+ st1 {v4.16b}, [x6]
+ ldp x29, x30, [sp], #16
ret
AES_ENDPROC(aes_xts_encrypt)
AES_ENTRY(aes_xts_decrypt)
- FRAME_PUSH
- cbz w7, .LxtsdecloopNx
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
ld1 {v4.16b}, [x6]
- enc_prepare w3, x5, x6
- encrypt_block v4, w3, x5, x6, w7 /* first tweak */
- dec_prepare w3, x2, x6
+ cbz w7, .Lxtsdecnotfirst
+
+ enc_prepare w3, x5, x8
+ encrypt_block v4, w3, x5, x8, w7 /* first tweak */
+ dec_prepare w3, x2, x8
ldr q7, .Lxts_mul_x
b .LxtsdecNx
+.Lxtsdecnotfirst:
+ dec_prepare w3, x2, x8
.LxtsdecloopNx:
ldr q7, .Lxts_mul_x
next_tweak v4, v4, v7, v8
.LxtsdecNx:
-#if INTERLEAVE >= 2
- subs w4, w4, #INTERLEAVE
+ subs w4, w4, #4
bmi .Lxtsdec1x
-#if INTERLEAVE == 2
- ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 ct blocks */
- next_tweak v5, v4, v7, v8
- eor v0.16b, v0.16b, v4.16b
- eor v1.16b, v1.16b, v5.16b
- do_decrypt_block2x
- eor v0.16b, v0.16b, v4.16b
- eor v1.16b, v1.16b, v5.16b
- st1 {v0.16b-v1.16b}, [x0], #32
- cbz w4, .LxtsdecoutNx
- next_tweak v4, v5, v7, v8
- b .LxtsdecNx
-.LxtsdecoutNx:
- mov v4.16b, v5.16b
- b .Lxtsdecout
-#else
ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
next_tweak v5, v4, v7, v8
eor v0.16b, v0.16b, v4.16b
@@ -497,7 +360,7 @@ AES_ENTRY(aes_xts_decrypt)
eor v2.16b, v2.16b, v6.16b
next_tweak v7, v6, v7, v8
eor v3.16b, v3.16b, v7.16b
- do_decrypt_block4x
+ bl aes_decrypt_block4x
eor v3.16b, v3.16b, v7.16b
eor v0.16b, v0.16b, v4.16b
eor v1.16b, v1.16b, v5.16b
@@ -506,15 +369,13 @@ AES_ENTRY(aes_xts_decrypt)
mov v4.16b, v7.16b
cbz w4, .Lxtsdecout
b .LxtsdecloopNx
-#endif
.Lxtsdec1x:
- adds w4, w4, #INTERLEAVE
+ adds w4, w4, #4
beq .Lxtsdecout
-#endif
.Lxtsdecloop:
ld1 {v1.16b}, [x1], #16
eor v0.16b, v1.16b, v4.16b
- decrypt_block v0, w3, x2, x6, w7
+ decrypt_block v0, w3, x2, x8, w7
eor v0.16b, v0.16b, v4.16b
st1 {v0.16b}, [x0], #16
subs w4, w4, #1
@@ -522,7 +383,8 @@ AES_ENTRY(aes_xts_decrypt)
next_tweak v4, v4, v7, v8
b .Lxtsdecloop
.Lxtsdecout:
- FRAME_POP
+ st1 {v4.16b}, [x6]
+ ldp x29, x30, [sp], #16
ret
AES_ENDPROC(aes_xts_decrypt)
@@ -533,8 +395,28 @@ AES_ENDPROC(aes_xts_decrypt)
AES_ENTRY(aes_mac_update)
ld1 {v0.16b}, [x4] /* get dg */
enc_prepare w2, x1, x7
- cbnz w5, .Lmacenc
+ cbz w5, .Lmacloop4x
+
+ encrypt_block v0, w2, x1, x7, w8
+.Lmacloop4x:
+ subs w3, w3, #4
+ bmi .Lmac1x
+ ld1 {v1.16b-v4.16b}, [x0], #64 /* get next pt block */
+ eor v0.16b, v0.16b, v1.16b /* ..and xor with dg */
+ encrypt_block v0, w2, x1, x7, w8
+ eor v0.16b, v0.16b, v2.16b
+ encrypt_block v0, w2, x1, x7, w8
+ eor v0.16b, v0.16b, v3.16b
+ encrypt_block v0, w2, x1, x7, w8
+ eor v0.16b, v0.16b, v4.16b
+ cmp w3, wzr
+ csinv x5, x6, xzr, eq
+ cbz w5, .Lmacout
+ encrypt_block v0, w2, x1, x7, w8
+ b .Lmacloop4x
+.Lmac1x:
+ add w3, w3, #4
.Lmacloop:
cbz w3, .Lmacout
ld1 {v1.16b}, [x0], #16 /* get next pt block */
@@ -544,7 +426,6 @@ AES_ENTRY(aes_mac_update)
csinv x5, x6, xzr, eq
cbz w5, .Lmacout
-.Lmacenc:
encrypt_block v0, w2, x1, x7, w8
b .Lmacloop
diff --git a/arch/arm64/crypto/aes-neonbs-glue.c b/arch/arm64/crypto/aes-neonbs-glue.c
index c55d68ccb89f..e7a95a566462 100644
--- a/arch/arm64/crypto/aes-neonbs-glue.c
+++ b/arch/arm64/crypto/aes-neonbs-glue.c
@@ -46,10 +46,9 @@ asmlinkage void aesbs_xts_decrypt(u8 out[], u8 const in[], u8 const rk[],
/* borrowed from aes-neon-blk.ko */
asmlinkage void neon_aes_ecb_encrypt(u8 out[], u8 const in[], u32 const rk[],
- int rounds, int blocks, int first);
+ int rounds, int blocks);
asmlinkage void neon_aes_cbc_encrypt(u8 out[], u8 const in[], u32 const rk[],
- int rounds, int blocks, u8 iv[],
- int first);
+ int rounds, int blocks, u8 iv[]);
struct aesbs_ctx {
u8 rk[13 * (8 * AES_BLOCK_SIZE) + 32];
@@ -100,9 +99,8 @@ static int __ecb_crypt(struct skcipher_request *req,
struct skcipher_walk walk;
int err;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
while (walk.nbytes >= AES_BLOCK_SIZE) {
unsigned int blocks = walk.nbytes / AES_BLOCK_SIZE;
@@ -110,12 +108,13 @@ static int __ecb_crypt(struct skcipher_request *req,
blocks = round_down(blocks,
walk.stride / AES_BLOCK_SIZE);
+ kernel_neon_begin();
fn(walk.dst.virt.addr, walk.src.virt.addr, ctx->rk,
ctx->rounds, blocks);
+ kernel_neon_end();
err = skcipher_walk_done(&walk,
walk.nbytes - blocks * AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -157,22 +156,21 @@ static int cbc_encrypt(struct skcipher_request *req)
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
struct skcipher_walk walk;
- int err, first = 1;
+ int err;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
while (walk.nbytes >= AES_BLOCK_SIZE) {
unsigned int blocks = walk.nbytes / AES_BLOCK_SIZE;
/* fall back to the non-bitsliced NEON implementation */
+ kernel_neon_begin();
neon_aes_cbc_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
- ctx->enc, ctx->key.rounds, blocks, walk.iv,
- first);
+ ctx->enc, ctx->key.rounds, blocks,
+ walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE);
- first = 0;
}
- kernel_neon_end();
return err;
}
@@ -183,9 +181,8 @@ static int cbc_decrypt(struct skcipher_request *req)
struct skcipher_walk walk;
int err;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
while (walk.nbytes >= AES_BLOCK_SIZE) {
unsigned int blocks = walk.nbytes / AES_BLOCK_SIZE;
@@ -193,13 +190,14 @@ static int cbc_decrypt(struct skcipher_request *req)
blocks = round_down(blocks,
walk.stride / AES_BLOCK_SIZE);
+ kernel_neon_begin();
aesbs_cbc_decrypt(walk.dst.virt.addr, walk.src.virt.addr,
ctx->key.rk, ctx->key.rounds, blocks,
walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk,
walk.nbytes - blocks * AES_BLOCK_SIZE);
}
- kernel_neon_end();
return err;
}
@@ -231,9 +229,8 @@ static int ctr_encrypt(struct skcipher_request *req)
u8 buf[AES_BLOCK_SIZE];
int err;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
- kernel_neon_begin();
while (walk.nbytes > 0) {
unsigned int blocks = walk.nbytes / AES_BLOCK_SIZE;
u8 *final = (walk.total % AES_BLOCK_SIZE) ? buf : NULL;
@@ -244,8 +241,10 @@ static int ctr_encrypt(struct skcipher_request *req)
final = NULL;
}
+ kernel_neon_begin();
aesbs_ctr_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
ctx->rk, ctx->rounds, blocks, walk.iv, final);
+ kernel_neon_end();
if (final) {
u8 *dst = walk.dst.virt.addr + blocks * AES_BLOCK_SIZE;
@@ -260,8 +259,6 @@ static int ctr_encrypt(struct skcipher_request *req)
err = skcipher_walk_done(&walk,
walk.nbytes - blocks * AES_BLOCK_SIZE);
}
- kernel_neon_end();
-
return err;
}
@@ -306,12 +303,11 @@ static int __xts_crypt(struct skcipher_request *req,
struct skcipher_walk walk;
int err;
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
kernel_neon_begin();
-
- neon_aes_ecb_encrypt(walk.iv, walk.iv, ctx->twkey,
- ctx->key.rounds, 1, 1);
+ neon_aes_ecb_encrypt(walk.iv, walk.iv, ctx->twkey, ctx->key.rounds, 1);
+ kernel_neon_end();
while (walk.nbytes >= AES_BLOCK_SIZE) {
unsigned int blocks = walk.nbytes / AES_BLOCK_SIZE;
@@ -320,13 +316,13 @@ static int __xts_crypt(struct skcipher_request *req,
blocks = round_down(blocks,
walk.stride / AES_BLOCK_SIZE);
+ kernel_neon_begin();
fn(walk.dst.virt.addr, walk.src.virt.addr, ctx->key.rk,
ctx->key.rounds, blocks, walk.iv);
+ kernel_neon_end();
err = skcipher_walk_done(&walk,
walk.nbytes - blocks * AES_BLOCK_SIZE);
}
- kernel_neon_end();
-
return err;
}
diff --git a/arch/arm64/crypto/chacha20-neon-glue.c b/arch/arm64/crypto/chacha20-neon-glue.c
index cbdb75d15cd0..727579c93ded 100644
--- a/arch/arm64/crypto/chacha20-neon-glue.c
+++ b/arch/arm64/crypto/chacha20-neon-glue.c
@@ -37,12 +37,19 @@ static void chacha20_doneon(u32 *state, u8 *dst, const u8 *src,
u8 buf[CHACHA20_BLOCK_SIZE];
while (bytes >= CHACHA20_BLOCK_SIZE * 4) {
+ kernel_neon_begin();
chacha20_4block_xor_neon(state, dst, src);
+ kernel_neon_end();
bytes -= CHACHA20_BLOCK_SIZE * 4;
src += CHACHA20_BLOCK_SIZE * 4;
dst += CHACHA20_BLOCK_SIZE * 4;
state[12] += 4;
}
+
+ if (!bytes)
+ return;
+
+ kernel_neon_begin();
while (bytes >= CHACHA20_BLOCK_SIZE) {
chacha20_block_xor_neon(state, dst, src);
bytes -= CHACHA20_BLOCK_SIZE;
@@ -55,6 +62,7 @@ static void chacha20_doneon(u32 *state, u8 *dst, const u8 *src,
chacha20_block_xor_neon(state, buf, buf);
memcpy(dst, buf, bytes);
}
+ kernel_neon_end();
}
static int chacha20_neon(struct skcipher_request *req)
@@ -68,11 +76,10 @@ static int chacha20_neon(struct skcipher_request *req)
if (!may_use_simd() || req->cryptlen <= CHACHA20_BLOCK_SIZE)
return crypto_chacha20_crypt(req);
- err = skcipher_walk_virt(&walk, req, true);
+ err = skcipher_walk_virt(&walk, req, false);
crypto_chacha20_init(state, ctx, walk.iv);
- kernel_neon_begin();
while (walk.nbytes > 0) {
unsigned int nbytes = walk.nbytes;
@@ -83,7 +90,6 @@ static int chacha20_neon(struct skcipher_request *req)
nbytes);
err = skcipher_walk_done(&walk, walk.nbytes - nbytes);
}
- kernel_neon_end();
return err;
}
diff --git a/arch/arm64/crypto/sha256-glue.c b/arch/arm64/crypto/sha256-glue.c
index b064d925fe2a..e8880ccdc71f 100644
--- a/arch/arm64/crypto/sha256-glue.c
+++ b/arch/arm64/crypto/sha256-glue.c
@@ -89,21 +89,32 @@ static struct shash_alg algs[] = { {
static int sha256_update_neon(struct shash_desc *desc, const u8 *data,
unsigned int len)
{
- /*
- * Stacking and unstacking a substantial slice of the NEON register
- * file may significantly affect performance for small updates when
- * executing in interrupt context, so fall back to the scalar code
- * in that case.
- */
+ struct sha256_state *sctx = shash_desc_ctx(desc);
+
if (!may_use_simd())
return sha256_base_do_update(desc, data, len,
(sha256_block_fn *)sha256_block_data_order);
- kernel_neon_begin();
- sha256_base_do_update(desc, data, len,
- (sha256_block_fn *)sha256_block_neon);
- kernel_neon_end();
+ while (len > 0) {
+ unsigned int chunk = len;
+
+ /*
+ * Don't hog the CPU for the entire time it takes to process all
+ * input when running on a preemptible kernel, but process the
+ * data block by block instead.
+ */
+ if (IS_ENABLED(CONFIG_PREEMPT) &&
+ chunk + sctx->count % SHA256_BLOCK_SIZE > SHA256_BLOCK_SIZE)
+ chunk = SHA256_BLOCK_SIZE -
+ sctx->count % SHA256_BLOCK_SIZE;
+ kernel_neon_begin();
+ sha256_base_do_update(desc, data, chunk,
+ (sha256_block_fn *)sha256_block_neon);
+ kernel_neon_end();
+ data += chunk;
+ len -= chunk;
+ }
return 0;
}
@@ -117,10 +128,9 @@ static int sha256_finup_neon(struct shash_desc *desc, const u8 *data,
sha256_base_do_finalize(desc,
(sha256_block_fn *)sha256_block_data_order);
} else {
- kernel_neon_begin();
if (len)
- sha256_base_do_update(desc, data, len,
- (sha256_block_fn *)sha256_block_neon);
+ sha256_update_neon(desc, data, len);
+ kernel_neon_begin();
sha256_base_do_finalize(desc,
(sha256_block_fn *)sha256_block_neon);
kernel_neon_end();
diff --git a/arch/arm64/crypto/speck-neon-core.S b/arch/arm64/crypto/speck-neon-core.S
new file mode 100644
index 000000000000..b14463438b09
--- /dev/null
+++ b/arch/arm64/crypto/speck-neon-core.S
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM64 NEON-accelerated implementation of Speck128-XTS and Speck64-XTS
+ *
+ * Copyright (c) 2018 Google, Inc
+ *
+ * Author: Eric Biggers <ebiggers@google.com>
+ */
+
+#include <linux/linkage.h>
+
+ .text
+
+ // arguments
+ ROUND_KEYS .req x0 // const {u64,u32} *round_keys
+ NROUNDS .req w1 // int nrounds
+ NROUNDS_X .req x1
+ DST .req x2 // void *dst
+ SRC .req x3 // const void *src
+ NBYTES .req w4 // unsigned int nbytes
+ TWEAK .req x5 // void *tweak
+
+ // registers which hold the data being encrypted/decrypted
+ // (underscores avoid a naming collision with ARM64 registers x0-x3)
+ X_0 .req v0
+ Y_0 .req v1
+ X_1 .req v2
+ Y_1 .req v3
+ X_2 .req v4
+ Y_2 .req v5
+ X_3 .req v6
+ Y_3 .req v7
+
+ // the round key, duplicated in all lanes
+ ROUND_KEY .req v8
+
+ // index vector for tbl-based 8-bit rotates
+ ROTATE_TABLE .req v9
+ ROTATE_TABLE_Q .req q9
+
+ // temporary registers
+ TMP0 .req v10
+ TMP1 .req v11
+ TMP2 .req v12
+ TMP3 .req v13
+
+ // multiplication table for updating XTS tweaks
+ GFMUL_TABLE .req v14
+ GFMUL_TABLE_Q .req q14
+
+ // next XTS tweak value(s)
+ TWEAKV_NEXT .req v15
+
+ // XTS tweaks for the blocks currently being encrypted/decrypted
+ TWEAKV0 .req v16
+ TWEAKV1 .req v17
+ TWEAKV2 .req v18
+ TWEAKV3 .req v19
+ TWEAKV4 .req v20
+ TWEAKV5 .req v21
+ TWEAKV6 .req v22
+ TWEAKV7 .req v23
+
+ .align 4
+.Lror64_8_table:
+ .octa 0x080f0e0d0c0b0a090007060504030201
+.Lror32_8_table:
+ .octa 0x0c0f0e0d080b0a090407060500030201
+.Lrol64_8_table:
+ .octa 0x0e0d0c0b0a09080f0605040302010007
+.Lrol32_8_table:
+ .octa 0x0e0d0c0f0a09080b0605040702010003
+.Lgf128mul_table:
+ .octa 0x00000000000000870000000000000001
+.Lgf64mul_table:
+ .octa 0x0000000000000000000000002d361b00
+
+/*
+ * _speck_round_128bytes() - Speck encryption round on 128 bytes at a time
+ *
+ * Do one Speck encryption round on the 128 bytes (8 blocks for Speck128, 16 for
+ * Speck64) stored in X0-X3 and Y0-Y3, using the round key stored in all lanes
+ * of ROUND_KEY. 'n' is the lane size: 64 for Speck128, or 32 for Speck64.
+ * 'lanes' is the lane specifier: "2d" for Speck128 or "4s" for Speck64.
+ */
+.macro _speck_round_128bytes n, lanes
+
+ // x = ror(x, 8)
+ tbl X_0.16b, {X_0.16b}, ROTATE_TABLE.16b
+ tbl X_1.16b, {X_1.16b}, ROTATE_TABLE.16b
+ tbl X_2.16b, {X_2.16b}, ROTATE_TABLE.16b
+ tbl X_3.16b, {X_3.16b}, ROTATE_TABLE.16b
+
+ // x += y
+ add X_0.\lanes, X_0.\lanes, Y_0.\lanes
+ add X_1.\lanes, X_1.\lanes, Y_1.\lanes
+ add X_2.\lanes, X_2.\lanes, Y_2.\lanes
+ add X_3.\lanes, X_3.\lanes, Y_3.\lanes
+
+ // x ^= k
+ eor X_0.16b, X_0.16b, ROUND_KEY.16b
+ eor X_1.16b, X_1.16b, ROUND_KEY.16b
+ eor X_2.16b, X_2.16b, ROUND_KEY.16b
+ eor X_3.16b, X_3.16b, ROUND_KEY.16b
+
+ // y = rol(y, 3)
+ shl TMP0.\lanes, Y_0.\lanes, #3
+ shl TMP1.\lanes, Y_1.\lanes, #3
+ shl TMP2.\lanes, Y_2.\lanes, #3
+ shl TMP3.\lanes, Y_3.\lanes, #3
+ sri TMP0.\lanes, Y_0.\lanes, #(\n - 3)
+ sri TMP1.\lanes, Y_1.\lanes, #(\n - 3)
+ sri TMP2.\lanes, Y_2.\lanes, #(\n - 3)
+ sri TMP3.\lanes, Y_3.\lanes, #(\n - 3)
+
+ // y ^= x
+ eor Y_0.16b, TMP0.16b, X_0.16b
+ eor Y_1.16b, TMP1.16b, X_1.16b
+ eor Y_2.16b, TMP2.16b, X_2.16b
+ eor Y_3.16b, TMP3.16b, X_3.16b
+.endm
+
+/*
+ * _speck_unround_128bytes() - Speck decryption round on 128 bytes at a time
+ *
+ * This is the inverse of _speck_round_128bytes().
+ */
+.macro _speck_unround_128bytes n, lanes
+
+ // y ^= x
+ eor TMP0.16b, Y_0.16b, X_0.16b
+ eor TMP1.16b, Y_1.16b, X_1.16b
+ eor TMP2.16b, Y_2.16b, X_2.16b
+ eor TMP3.16b, Y_3.16b, X_3.16b
+
+ // y = ror(y, 3)
+ ushr Y_0.\lanes, TMP0.\lanes, #3
+ ushr Y_1.\lanes, TMP1.\lanes, #3
+ ushr Y_2.\lanes, TMP2.\lanes, #3
+ ushr Y_3.\lanes, TMP3.\lanes, #3
+ sli Y_0.\lanes, TMP0.\lanes, #(\n - 3)
+ sli Y_1.\lanes, TMP1.\lanes, #(\n - 3)
+ sli Y_2.\lanes, TMP2.\lanes, #(\n - 3)
+ sli Y_3.\lanes, TMP3.\lanes, #(\n - 3)
+
+ // x ^= k
+ eor X_0.16b, X_0.16b, ROUND_KEY.16b
+ eor X_1.16b, X_1.16b, ROUND_KEY.16b
+ eor X_2.16b, X_2.16b, ROUND_KEY.16b
+ eor X_3.16b, X_3.16b, ROUND_KEY.16b
+
+ // x -= y
+ sub X_0.\lanes, X_0.\lanes, Y_0.\lanes
+ sub X_1.\lanes, X_1.\lanes, Y_1.\lanes
+ sub X_2.\lanes, X_2.\lanes, Y_2.\lanes
+ sub X_3.\lanes, X_3.\lanes, Y_3.\lanes
+
+ // x = rol(x, 8)
+ tbl X_0.16b, {X_0.16b}, ROTATE_TABLE.16b
+ tbl X_1.16b, {X_1.16b}, ROTATE_TABLE.16b
+ tbl X_2.16b, {X_2.16b}, ROTATE_TABLE.16b
+ tbl X_3.16b, {X_3.16b}, ROTATE_TABLE.16b
+.endm
+
+.macro _next_xts_tweak next, cur, tmp, n
+.if \n == 64
+ /*
+ * Calculate the next tweak by multiplying the current one by x,
+ * modulo p(x) = x^128 + x^7 + x^2 + x + 1.
+ */
+ sshr \tmp\().2d, \cur\().2d, #63
+ and \tmp\().16b, \tmp\().16b, GFMUL_TABLE.16b
+ shl \next\().2d, \cur\().2d, #1
+ ext \tmp\().16b, \tmp\().16b, \tmp\().16b, #8
+ eor \next\().16b, \next\().16b, \tmp\().16b
+.else
+ /*
+ * Calculate the next two tweaks by multiplying the current ones by x^2,
+ * modulo p(x) = x^64 + x^4 + x^3 + x + 1.
+ */
+ ushr \tmp\().2d, \cur\().2d, #62
+ shl \next\().2d, \cur\().2d, #2
+ tbl \tmp\().16b, {GFMUL_TABLE.16b}, \tmp\().16b
+ eor \next\().16b, \next\().16b, \tmp\().16b
+.endif
+.endm
+
+/*
+ * _speck_xts_crypt() - Speck-XTS encryption/decryption
+ *
+ * Encrypt or decrypt NBYTES bytes of data from the SRC buffer to the DST buffer
+ * using Speck-XTS, specifically the variant with a block size of '2n' and round
+ * count given by NROUNDS. The expanded round keys are given in ROUND_KEYS, and
+ * the current XTS tweak value is given in TWEAK. It's assumed that NBYTES is a
+ * nonzero multiple of 128.
+ */
+.macro _speck_xts_crypt n, lanes, decrypting
+
+ /*
+ * If decrypting, modify the ROUND_KEYS parameter to point to the last
+ * round key rather than the first, since for decryption the round keys
+ * are used in reverse order.
+ */
+.if \decrypting
+ mov NROUNDS, NROUNDS /* zero the high 32 bits */
+.if \n == 64
+ add ROUND_KEYS, ROUND_KEYS, NROUNDS_X, lsl #3
+ sub ROUND_KEYS, ROUND_KEYS, #8
+.else
+ add ROUND_KEYS, ROUND_KEYS, NROUNDS_X, lsl #2
+ sub ROUND_KEYS, ROUND_KEYS, #4
+.endif
+.endif
+
+ // Load the index vector for tbl-based 8-bit rotates
+.if \decrypting
+ ldr ROTATE_TABLE_Q, .Lrol\n\()_8_table
+.else
+ ldr ROTATE_TABLE_Q, .Lror\n\()_8_table
+.endif
+
+ // One-time XTS preparation
+.if \n == 64
+ // Load first tweak
+ ld1 {TWEAKV0.16b}, [TWEAK]
+
+ // Load GF(2^128) multiplication table
+ ldr GFMUL_TABLE_Q, .Lgf128mul_table
+.else
+ // Load first tweak
+ ld1 {TWEAKV0.8b}, [TWEAK]
+
+ // Load GF(2^64) multiplication table
+ ldr GFMUL_TABLE_Q, .Lgf64mul_table
+
+ // Calculate second tweak, packing it together with the first
+ ushr TMP0.2d, TWEAKV0.2d, #63
+ shl TMP1.2d, TWEAKV0.2d, #1
+ tbl TMP0.8b, {GFMUL_TABLE.16b}, TMP0.8b
+ eor TMP0.8b, TMP0.8b, TMP1.8b
+ mov TWEAKV0.d[1], TMP0.d[0]
+.endif
+
+.Lnext_128bytes_\@:
+
+ // Calculate XTS tweaks for next 128 bytes
+ _next_xts_tweak TWEAKV1, TWEAKV0, TMP0, \n
+ _next_xts_tweak TWEAKV2, TWEAKV1, TMP0, \n
+ _next_xts_tweak TWEAKV3, TWEAKV2, TMP0, \n
+ _next_xts_tweak TWEAKV4, TWEAKV3, TMP0, \n
+ _next_xts_tweak TWEAKV5, TWEAKV4, TMP0, \n
+ _next_xts_tweak TWEAKV6, TWEAKV5, TMP0, \n
+ _next_xts_tweak TWEAKV7, TWEAKV6, TMP0, \n
+ _next_xts_tweak TWEAKV_NEXT, TWEAKV7, TMP0, \n
+
+ // Load the next source blocks into {X,Y}[0-3]
+ ld1 {X_0.16b-Y_1.16b}, [SRC], #64
+ ld1 {X_2.16b-Y_3.16b}, [SRC], #64
+
+ // XOR the source blocks with their XTS tweaks
+ eor TMP0.16b, X_0.16b, TWEAKV0.16b
+ eor Y_0.16b, Y_0.16b, TWEAKV1.16b
+ eor TMP1.16b, X_1.16b, TWEAKV2.16b
+ eor Y_1.16b, Y_1.16b, TWEAKV3.16b
+ eor TMP2.16b, X_2.16b, TWEAKV4.16b
+ eor Y_2.16b, Y_2.16b, TWEAKV5.16b
+ eor TMP3.16b, X_3.16b, TWEAKV6.16b
+ eor Y_3.16b, Y_3.16b, TWEAKV7.16b
+
+ /*
+ * De-interleave the 'x' and 'y' elements of each block, i.e. make it so
+ * that the X[0-3] registers contain only the second halves of blocks,
+ * and the Y[0-3] registers contain only the first halves of blocks.
+ * (Speck uses the order (y, x) rather than the more intuitive (x, y).)
+ */
+ uzp2 X_0.\lanes, TMP0.\lanes, Y_0.\lanes
+ uzp1 Y_0.\lanes, TMP0.\lanes, Y_0.\lanes
+ uzp2 X_1.\lanes, TMP1.\lanes, Y_1.\lanes
+ uzp1 Y_1.\lanes, TMP1.\lanes, Y_1.\lanes
+ uzp2 X_2.\lanes, TMP2.\lanes, Y_2.\lanes
+ uzp1 Y_2.\lanes, TMP2.\lanes, Y_2.\lanes
+ uzp2 X_3.\lanes, TMP3.\lanes, Y_3.\lanes
+ uzp1 Y_3.\lanes, TMP3.\lanes, Y_3.\lanes
+
+ // Do the cipher rounds
+ mov x6, ROUND_KEYS
+ mov w7, NROUNDS
+.Lnext_round_\@:
+.if \decrypting
+ ld1r {ROUND_KEY.\lanes}, [x6]
+ sub x6, x6, #( \n / 8 )
+ _speck_unround_128bytes \n, \lanes
+.else
+ ld1r {ROUND_KEY.\lanes}, [x6], #( \n / 8 )
+ _speck_round_128bytes \n, \lanes
+.endif
+ subs w7, w7, #1
+ bne .Lnext_round_\@
+
+ // Re-interleave the 'x' and 'y' elements of each block
+ zip1 TMP0.\lanes, Y_0.\lanes, X_0.\lanes
+ zip2 Y_0.\lanes, Y_0.\lanes, X_0.\lanes
+ zip1 TMP1.\lanes, Y_1.\lanes, X_1.\lanes
+ zip2 Y_1.\lanes, Y_1.\lanes, X_1.\lanes
+ zip1 TMP2.\lanes, Y_2.\lanes, X_2.\lanes
+ zip2 Y_2.\lanes, Y_2.\lanes, X_2.\lanes
+ zip1 TMP3.\lanes, Y_3.\lanes, X_3.\lanes
+ zip2 Y_3.\lanes, Y_3.\lanes, X_3.\lanes
+
+ // XOR the encrypted/decrypted blocks with the tweaks calculated earlier
+ eor X_0.16b, TMP0.16b, TWEAKV0.16b
+ eor Y_0.16b, Y_0.16b, TWEAKV1.16b
+ eor X_1.16b, TMP1.16b, TWEAKV2.16b
+ eor Y_1.16b, Y_1.16b, TWEAKV3.16b
+ eor X_2.16b, TMP2.16b, TWEAKV4.16b
+ eor Y_2.16b, Y_2.16b, TWEAKV5.16b
+ eor X_3.16b, TMP3.16b, TWEAKV6.16b
+ eor Y_3.16b, Y_3.16b, TWEAKV7.16b
+ mov TWEAKV0.16b, TWEAKV_NEXT.16b
+
+ // Store the ciphertext in the destination buffer
+ st1 {X_0.16b-Y_1.16b}, [DST], #64
+ st1 {X_2.16b-Y_3.16b}, [DST], #64
+
+ // Continue if there are more 128-byte chunks remaining
+ subs NBYTES, NBYTES, #128
+ bne .Lnext_128bytes_\@
+
+ // Store the next tweak and return
+.if \n == 64
+ st1 {TWEAKV_NEXT.16b}, [TWEAK]
+.else
+ st1 {TWEAKV_NEXT.8b}, [TWEAK]
+.endif
+ ret
+.endm
+
+ENTRY(speck128_xts_encrypt_neon)
+ _speck_xts_crypt n=64, lanes=2d, decrypting=0
+ENDPROC(speck128_xts_encrypt_neon)
+
+ENTRY(speck128_xts_decrypt_neon)
+ _speck_xts_crypt n=64, lanes=2d, decrypting=1
+ENDPROC(speck128_xts_decrypt_neon)
+
+ENTRY(speck64_xts_encrypt_neon)
+ _speck_xts_crypt n=32, lanes=4s, decrypting=0
+ENDPROC(speck64_xts_encrypt_neon)
+
+ENTRY(speck64_xts_decrypt_neon)
+ _speck_xts_crypt n=32, lanes=4s, decrypting=1
+ENDPROC(speck64_xts_decrypt_neon)
diff --git a/arch/arm64/crypto/speck-neon-glue.c b/arch/arm64/crypto/speck-neon-glue.c
new file mode 100644
index 000000000000..6e233aeb4ff4
--- /dev/null
+++ b/arch/arm64/crypto/speck-neon-glue.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NEON-accelerated implementation of Speck128-XTS and Speck64-XTS
+ * (64-bit version; based on the 32-bit version)
+ *
+ * Copyright (c) 2018 Google, Inc
+ */
+
+#include <asm/hwcap.h>
+#include <asm/neon.h>
+#include <asm/simd.h>
+#include <crypto/algapi.h>
+#include <crypto/gf128mul.h>
+#include <crypto/internal/skcipher.h>
+#include <crypto/speck.h>
+#include <crypto/xts.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+/* The assembly functions only handle multiples of 128 bytes */
+#define SPECK_NEON_CHUNK_SIZE 128
+
+/* Speck128 */
+
+struct speck128_xts_tfm_ctx {
+ struct speck128_tfm_ctx main_key;
+ struct speck128_tfm_ctx tweak_key;
+};
+
+asmlinkage void speck128_xts_encrypt_neon(const u64 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+asmlinkage void speck128_xts_decrypt_neon(const u64 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+typedef void (*speck128_crypt_one_t)(const struct speck128_tfm_ctx *,
+ u8 *, const u8 *);
+typedef void (*speck128_xts_crypt_many_t)(const u64 *, int, void *,
+ const void *, unsigned int, void *);
+
+static __always_inline int
+__speck128_xts_crypt(struct skcipher_request *req,
+ speck128_crypt_one_t crypt_one,
+ speck128_xts_crypt_many_t crypt_many)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ const struct speck128_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ struct skcipher_walk walk;
+ le128 tweak;
+ int err;
+
+ err = skcipher_walk_virt(&walk, req, true);
+
+ crypto_speck128_encrypt(&ctx->tweak_key, (u8 *)&tweak, walk.iv);
+
+ while (walk.nbytes > 0) {
+ unsigned int nbytes = walk.nbytes;
+ u8 *dst = walk.dst.virt.addr;
+ const u8 *src = walk.src.virt.addr;
+
+ if (nbytes >= SPECK_NEON_CHUNK_SIZE && may_use_simd()) {
+ unsigned int count;
+
+ count = round_down(nbytes, SPECK_NEON_CHUNK_SIZE);
+ kernel_neon_begin();
+ (*crypt_many)(ctx->main_key.round_keys,
+ ctx->main_key.nrounds,
+ dst, src, count, &tweak);
+ kernel_neon_end();
+ dst += count;
+ src += count;
+ nbytes -= count;
+ }
+
+ /* Handle any remainder with generic code */
+ while (nbytes >= sizeof(tweak)) {
+ le128_xor((le128 *)dst, (const le128 *)src, &tweak);
+ (*crypt_one)(&ctx->main_key, dst, dst);
+ le128_xor((le128 *)dst, (const le128 *)dst, &tweak);
+ gf128mul_x_ble(&tweak, &tweak);
+
+ dst += sizeof(tweak);
+ src += sizeof(tweak);
+ nbytes -= sizeof(tweak);
+ }
+ err = skcipher_walk_done(&walk, nbytes);
+ }
+
+ return err;
+}
+
+static int speck128_xts_encrypt(struct skcipher_request *req)
+{
+ return __speck128_xts_crypt(req, crypto_speck128_encrypt,
+ speck128_xts_encrypt_neon);
+}
+
+static int speck128_xts_decrypt(struct skcipher_request *req)
+{
+ return __speck128_xts_crypt(req, crypto_speck128_decrypt,
+ speck128_xts_decrypt_neon);
+}
+
+static int speck128_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct speck128_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ int err;
+
+ err = xts_verify_key(tfm, key, keylen);
+ if (err)
+ return err;
+
+ keylen /= 2;
+
+ err = crypto_speck128_setkey(&ctx->main_key, key, keylen);
+ if (err)
+ return err;
+
+ return crypto_speck128_setkey(&ctx->tweak_key, key + keylen, keylen);
+}
+
+/* Speck64 */
+
+struct speck64_xts_tfm_ctx {
+ struct speck64_tfm_ctx main_key;
+ struct speck64_tfm_ctx tweak_key;
+};
+
+asmlinkage void speck64_xts_encrypt_neon(const u32 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+asmlinkage void speck64_xts_decrypt_neon(const u32 *round_keys, int nrounds,
+ void *dst, const void *src,
+ unsigned int nbytes, void *tweak);
+
+typedef void (*speck64_crypt_one_t)(const struct speck64_tfm_ctx *,
+ u8 *, const u8 *);
+typedef void (*speck64_xts_crypt_many_t)(const u32 *, int, void *,
+ const void *, unsigned int, void *);
+
+static __always_inline int
+__speck64_xts_crypt(struct skcipher_request *req, speck64_crypt_one_t crypt_one,
+ speck64_xts_crypt_many_t crypt_many)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ const struct speck64_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ struct skcipher_walk walk;
+ __le64 tweak;
+ int err;
+
+ err = skcipher_walk_virt(&walk, req, true);
+
+ crypto_speck64_encrypt(&ctx->tweak_key, (u8 *)&tweak, walk.iv);
+
+ while (walk.nbytes > 0) {
+ unsigned int nbytes = walk.nbytes;
+ u8 *dst = walk.dst.virt.addr;
+ const u8 *src = walk.src.virt.addr;
+
+ if (nbytes >= SPECK_NEON_CHUNK_SIZE && may_use_simd()) {
+ unsigned int count;
+
+ count = round_down(nbytes, SPECK_NEON_CHUNK_SIZE);
+ kernel_neon_begin();
+ (*crypt_many)(ctx->main_key.round_keys,
+ ctx->main_key.nrounds,
+ dst, src, count, &tweak);
+ kernel_neon_end();
+ dst += count;
+ src += count;
+ nbytes -= count;
+ }
+
+ /* Handle any remainder with generic code */
+ while (nbytes >= sizeof(tweak)) {
+ *(__le64 *)dst = *(__le64 *)src ^ tweak;
+ (*crypt_one)(&ctx->main_key, dst, dst);
+ *(__le64 *)dst ^= tweak;
+ tweak = cpu_to_le64((le64_to_cpu(tweak) << 1) ^
+ ((tweak & cpu_to_le64(1ULL << 63)) ?
+ 0x1B : 0));
+ dst += sizeof(tweak);
+ src += sizeof(tweak);
+ nbytes -= sizeof(tweak);
+ }
+ err = skcipher_walk_done(&walk, nbytes);
+ }
+
+ return err;
+}
+
+static int speck64_xts_encrypt(struct skcipher_request *req)
+{
+ return __speck64_xts_crypt(req, crypto_speck64_encrypt,
+ speck64_xts_encrypt_neon);
+}
+
+static int speck64_xts_decrypt(struct skcipher_request *req)
+{
+ return __speck64_xts_crypt(req, crypto_speck64_decrypt,
+ speck64_xts_decrypt_neon);
+}
+
+static int speck64_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct speck64_xts_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
+ int err;
+
+ err = xts_verify_key(tfm, key, keylen);
+ if (err)
+ return err;
+
+ keylen /= 2;
+
+ err = crypto_speck64_setkey(&ctx->main_key, key, keylen);
+ if (err)
+ return err;
+
+ return crypto_speck64_setkey(&ctx->tweak_key, key + keylen, keylen);
+}
+
+static struct skcipher_alg speck_algs[] = {
+ {
+ .base.cra_name = "xts(speck128)",
+ .base.cra_driver_name = "xts-speck128-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = SPECK128_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct speck128_xts_tfm_ctx),
+ .base.cra_alignmask = 7,
+ .base.cra_module = THIS_MODULE,
+ .min_keysize = 2 * SPECK128_128_KEY_SIZE,
+ .max_keysize = 2 * SPECK128_256_KEY_SIZE,
+ .ivsize = SPECK128_BLOCK_SIZE,
+ .walksize = SPECK_NEON_CHUNK_SIZE,
+ .setkey = speck128_xts_setkey,
+ .encrypt = speck128_xts_encrypt,
+ .decrypt = speck128_xts_decrypt,
+ }, {
+ .base.cra_name = "xts(speck64)",
+ .base.cra_driver_name = "xts-speck64-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = SPECK64_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct speck64_xts_tfm_ctx),
+ .base.cra_alignmask = 7,
+ .base.cra_module = THIS_MODULE,
+ .min_keysize = 2 * SPECK64_96_KEY_SIZE,
+ .max_keysize = 2 * SPECK64_128_KEY_SIZE,
+ .ivsize = SPECK64_BLOCK_SIZE,
+ .walksize = SPECK_NEON_CHUNK_SIZE,
+ .setkey = speck64_xts_setkey,
+ .encrypt = speck64_xts_encrypt,
+ .decrypt = speck64_xts_decrypt,
+ }
+};
+
+static int __init speck_neon_module_init(void)
+{
+ if (!(elf_hwcap & HWCAP_ASIMD))
+ return -ENODEV;
+ return crypto_register_skciphers(speck_algs, ARRAY_SIZE(speck_algs));
+}
+
+static void __exit speck_neon_module_exit(void)
+{
+ crypto_unregister_skciphers(speck_algs, ARRAY_SIZE(speck_algs));
+}
+
+module_init(speck_neon_module_init);
+module_exit(speck_neon_module_exit);
+
+MODULE_DESCRIPTION("Speck block cipher (NEON-accelerated)");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Eric Biggers <ebiggers@google.com>");
+MODULE_ALIAS_CRYPTO("xts(speck128)");
+MODULE_ALIAS_CRYPTO("xts-speck128-neon");
+MODULE_ALIAS_CRYPTO("xts(speck64)");
+MODULE_ALIAS_CRYPTO("xts-speck64-neon");
diff --git a/arch/arm64/include/asm/alternative.h b/arch/arm64/include/asm/alternative.h
index 669028172fd6..a91933b1e2e6 100644
--- a/arch/arm64/include/asm/alternative.h
+++ b/arch/arm64/include/asm/alternative.h
@@ -5,6 +5,8 @@
#include <asm/cpucaps.h>
#include <asm/insn.h>
+#define ARM64_CB_PATCH ARM64_NCAPS
+
#ifndef __ASSEMBLY__
#include <linux/init.h>
@@ -22,12 +24,19 @@ struct alt_instr {
u8 alt_len; /* size of new instruction(s), <= orig_len */
};
+typedef void (*alternative_cb_t)(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr, int nr_inst);
+
void __init apply_alternatives_all(void);
void apply_alternatives(void *start, size_t length);
-#define ALTINSTR_ENTRY(feature) \
+#define ALTINSTR_ENTRY(feature,cb) \
" .word 661b - .\n" /* label */ \
+ " .if " __stringify(cb) " == 0\n" \
" .word 663f - .\n" /* new instruction */ \
+ " .else\n" \
+ " .word " __stringify(cb) "- .\n" /* callback */ \
+ " .endif\n" \
" .hword " __stringify(feature) "\n" /* feature bit */ \
" .byte 662b-661b\n" /* source len */ \
" .byte 664f-663f\n" /* replacement len */
@@ -45,15 +54,18 @@ void apply_alternatives(void *start, size_t length);
* but most assemblers die if insn1 or insn2 have a .inst. This should
* be fixed in a binutils release posterior to 2.25.51.0.2 (anything
* containing commit 4e4d08cf7399b606 or c1baaddf8861).
+ *
+ * Alternatives with callbacks do not generate replacement instructions.
*/
-#define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled) \
+#define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled, cb) \
".if "__stringify(cfg_enabled)" == 1\n" \
"661:\n\t" \
oldinstr "\n" \
"662:\n" \
".pushsection .altinstructions,\"a\"\n" \
- ALTINSTR_ENTRY(feature) \
+ ALTINSTR_ENTRY(feature,cb) \
".popsection\n" \
+ " .if " __stringify(cb) " == 0\n" \
".pushsection .altinstr_replacement, \"a\"\n" \
"663:\n\t" \
newinstr "\n" \
@@ -61,11 +73,17 @@ void apply_alternatives(void *start, size_t length);
".popsection\n\t" \
".org . - (664b-663b) + (662b-661b)\n\t" \
".org . - (662b-661b) + (664b-663b)\n" \
+ ".else\n\t" \
+ "663:\n\t" \
+ "664:\n\t" \
+ ".endif\n" \
".endif\n"
#define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...) \
- __ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg))
+ __ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg), 0)
+#define ALTERNATIVE_CB(oldinstr, cb) \
+ __ALTERNATIVE_CFG(oldinstr, "NOT_AN_INSTRUCTION", ARM64_CB_PATCH, 1, cb)
#else
#include <asm/assembler.h>
@@ -132,6 +150,14 @@ void apply_alternatives(void *start, size_t length);
661:
.endm
+.macro alternative_cb cb
+ .set .Lasm_alt_mode, 0
+ .pushsection .altinstructions, "a"
+ altinstruction_entry 661f, \cb, ARM64_CB_PATCH, 662f-661f, 0
+ .popsection
+661:
+.endm
+
/*
* Provide the other half of the alternative code sequence.
*/
@@ -158,6 +184,13 @@ void apply_alternatives(void *start, size_t length);
.endm
/*
+ * Callback-based alternative epilogue
+ */
+.macro alternative_cb_end
+662:
+.endm
+
+/*
* Provides a trivial alternative or default sequence consisting solely
* of NOPs. The number of NOPs is chosen automatically to match the
* previous case.
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 9becba9ab392..e278f94df0c9 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -76,11 +76,6 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
return irqstat;
}
-static inline void gic_write_pmr(u32 val)
-{
- write_sysreg_s(val, SYS_ICC_PMR_EL1);
-}
-
static inline void gic_write_ctlr(u32 val)
{
write_sysreg_s(val, SYS_ICC_CTLR_EL1);
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 3c78835bba94..0bcc98dbba56 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -202,25 +202,15 @@ lr .req x30 // link register
/*
* Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
- * <symbol> is within the range +/- 4 GB of the PC when running
- * in core kernel context. In module context, a movz/movk sequence
- * is used, since modules may be loaded far away from the kernel
- * when KASLR is in effect.
+ * <symbol> is within the range +/- 4 GB of the PC.
*/
/*
* @dst: destination register (64 bit wide)
* @sym: name of the symbol
*/
.macro adr_l, dst, sym
-#ifndef MODULE
adrp \dst, \sym
add \dst, \dst, :lo12:\sym
-#else
- movz \dst, #:abs_g3:\sym
- movk \dst, #:abs_g2_nc:\sym
- movk \dst, #:abs_g1_nc:\sym
- movk \dst, #:abs_g0_nc:\sym
-#endif
.endm
/*
@@ -231,7 +221,6 @@ lr .req x30 // link register
* the address
*/
.macro ldr_l, dst, sym, tmp=
-#ifndef MODULE
.ifb \tmp
adrp \dst, \sym
ldr \dst, [\dst, :lo12:\sym]
@@ -239,15 +228,6 @@ lr .req x30 // link register
adrp \tmp, \sym
ldr \dst, [\tmp, :lo12:\sym]
.endif
-#else
- .ifb \tmp
- adr_l \dst, \sym
- ldr \dst, [\dst]
- .else
- adr_l \tmp, \sym
- ldr \dst, [\tmp]
- .endif
-#endif
.endm
/*
@@ -257,28 +237,18 @@ lr .req x30 // link register
* while <src> needs to be preserved.
*/
.macro str_l, src, sym, tmp
-#ifndef MODULE
adrp \tmp, \sym
str \src, [\tmp, :lo12:\sym]
-#else
- adr_l \tmp, \sym
- str \src, [\tmp]
-#endif
.endm
/*
- * @dst: Result of per_cpu(sym, smp_processor_id()), can be SP for
- * non-module code
+ * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
* @sym: The name of the per-cpu variable
* @tmp: scratch register
*/
.macro adr_this_cpu, dst, sym, tmp
-#ifndef MODULE
adrp \tmp, \sym
add \dst, \tmp, #:lo12:\sym
-#else
- adr_l \dst, \sym
-#endif
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
mrs \tmp, tpidr_el1
alternative_else
@@ -595,4 +565,140 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU
#endif
.endm
+ /*
+ * frame_push - Push @regcount callee saved registers to the stack,
+ * starting at x19, as well as x29/x30, and set x29 to
+ * the new value of sp. Add @extra bytes of stack space
+ * for locals.
+ */
+ .macro frame_push, regcount:req, extra
+ __frame st, \regcount, \extra
+ .endm
+
+ /*
+ * frame_pop - Pop the callee saved registers from the stack that were
+ * pushed in the most recent call to frame_push, as well
+ * as x29/x30 and any extra stack space that may have been
+ * allocated.
+ */
+ .macro frame_pop
+ __frame ld
+ .endm
+
+ .macro __frame_regs, reg1, reg2, op, num
+ .if .Lframe_regcount == \num
+ \op\()r \reg1, [sp, #(\num + 1) * 8]
+ .elseif .Lframe_regcount > \num
+ \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
+ .endif
+ .endm
+
+ .macro __frame, op, regcount, extra=0
+ .ifc \op, st
+ .if (\regcount) < 0 || (\regcount) > 10
+ .error "regcount should be in the range [0 ... 10]"
+ .endif
+ .if ((\extra) % 16) != 0
+ .error "extra should be a multiple of 16 bytes"
+ .endif
+ .ifdef .Lframe_regcount
+ .if .Lframe_regcount != -1
+ .error "frame_push/frame_pop may not be nested"
+ .endif
+ .endif
+ .set .Lframe_regcount, \regcount
+ .set .Lframe_extra, \extra
+ .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
+ stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
+ mov x29, sp
+ .endif
+
+ __frame_regs x19, x20, \op, 1
+ __frame_regs x21, x22, \op, 3
+ __frame_regs x23, x24, \op, 5
+ __frame_regs x25, x26, \op, 7
+ __frame_regs x27, x28, \op, 9
+
+ .ifc \op, ld
+ .if .Lframe_regcount == -1
+ .error "frame_push/frame_pop may not be nested"
+ .endif
+ ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
+ .set .Lframe_regcount, -1
+ .endif
+ .endm
+
+/*
+ * Check whether to yield to another runnable task from kernel mode NEON code
+ * (which runs with preemption disabled).
+ *
+ * if_will_cond_yield_neon
+ * // pre-yield patchup code
+ * do_cond_yield_neon
+ * // post-yield patchup code
+ * endif_yield_neon <label>
+ *
+ * where <label> is optional, and marks the point where execution will resume
+ * after a yield has been performed. If omitted, execution resumes right after
+ * the endif_yield_neon invocation. Note that the entire sequence, including
+ * the provided patchup code, will be omitted from the image if CONFIG_PREEMPT
+ * is not defined.
+ *
+ * As a convenience, in the case where no patchup code is required, the above
+ * sequence may be abbreviated to
+ *
+ * cond_yield_neon <label>
+ *
+ * Note that the patchup code does not support assembler directives that change
+ * the output section, any use of such directives is undefined.
+ *
+ * The yield itself consists of the following:
+ * - Check whether the preempt count is exactly 1, in which case disabling
+ * preemption once will make the task preemptible. If this is not the case,
+ * yielding is pointless.
+ * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable
+ * kernel mode NEON (which will trigger a reschedule), and branch to the
+ * yield fixup code.
+ *
+ * This macro sequence may clobber all CPU state that is not guaranteed by the
+ * AAPCS to be preserved across an ordinary function call.
+ */
+
+ .macro cond_yield_neon, lbl
+ if_will_cond_yield_neon
+ do_cond_yield_neon
+ endif_yield_neon \lbl
+ .endm
+
+ .macro if_will_cond_yield_neon
+#ifdef CONFIG_PREEMPT
+ get_thread_info x0
+ ldr w1, [x0, #TSK_TI_PREEMPT]
+ ldr x0, [x0, #TSK_TI_FLAGS]
+ cmp w1, #PREEMPT_DISABLE_OFFSET
+ csel x0, x0, xzr, eq
+ tbnz x0, #TIF_NEED_RESCHED, .Lyield_\@ // needs rescheduling?
+ /* fall through to endif_yield_neon */
+ .subsection 1
+.Lyield_\@ :
+#else
+ .section ".discard.cond_yield_neon", "ax"
+#endif
+ .endm
+
+ .macro do_cond_yield_neon
+ bl kernel_neon_end
+ bl kernel_neon_begin
+ .endm
+
+ .macro endif_yield_neon, lbl
+ .ifnb \lbl
+ b \lbl
+ .else
+ b .Lyield_out_\@
+ .endif
+ .previous
+.Lyield_out_\@ :
+ .endm
+
#endif /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index ea9bb4e0e9bb..9bbffc7a301f 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -20,8 +20,12 @@
#define CTR_L1IP_SHIFT 14
#define CTR_L1IP_MASK 3
+#define CTR_DMINLINE_SHIFT 16
+#define CTR_ERG_SHIFT 20
#define CTR_CWG_SHIFT 24
#define CTR_CWG_MASK 15
+#define CTR_IDC_SHIFT 28
+#define CTR_DIC_SHIFT 29
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index bef9f418f089..0094c6653b06 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -133,14 +133,15 @@ extern void flush_dcache_page(struct page *);
static inline void __flush_icache_all(void)
{
+ if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
+ return;
+
asm("ic ialluis");
dsb(ish);
}
-#define flush_dcache_mmap_lock(mapping) \
- spin_lock_irq(&(mapping)->tree_lock)
-#define flush_dcache_mmap_unlock(mapping) \
- spin_unlock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
/*
* We don't appear to need to do anything here. In fact, if we did, we'd
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index ae852add053d..4f5fd2a36e6e 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -18,7 +18,8 @@
#ifndef __ASM_CMPXCHG_H
#define __ASM_CMPXCHG_H
-#include <linux/bug.h>
+#include <linux/build_bug.h>
+#include <linux/compiler.h>
#include <asm/atomic.h>
#include <asm/barrier.h>
@@ -196,32 +197,6 @@ __CMPXCHG_GEN(_mb)
__ret; \
})
-/* this_cpu_cmpxchg */
-#define _protect_cmpxchg_local(pcp, o, n) \
-({ \
- typeof(*raw_cpu_ptr(&(pcp))) __ret; \
- preempt_disable(); \
- __ret = cmpxchg_local(raw_cpu_ptr(&(pcp)), o, n); \
- preempt_enable(); \
- __ret; \
-})
-
-#define this_cpu_cmpxchg_1(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
-#define this_cpu_cmpxchg_2(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
-#define this_cpu_cmpxchg_4(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
-#define this_cpu_cmpxchg_8(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
-
-#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \
-({ \
- int __ret; \
- preempt_disable(); \
- __ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \
- raw_cpu_ptr(&(ptr2)), \
- o1, o2, n1, n2); \
- preempt_enable(); \
- __ret; \
-})
-
#define __CMPWAIT_CASE(w, sz, name) \
static inline void __cmpwait_case_##name(volatile void *ptr, \
unsigned long val) \
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index bb263820de13..bc51b72fafd4 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -32,7 +32,7 @@
#define ARM64_HAS_VIRT_HOST_EXTN 11
#define ARM64_WORKAROUND_CAVIUM_27456 12
#define ARM64_HAS_32BIT_EL0 13
-#define ARM64_HYP_OFFSET_LOW 14
+#define ARM64_HARDEN_EL2_VECTORS 14
#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
#define ARM64_HAS_NO_FPSIMD 16
#define ARM64_WORKAROUND_REPEAT_TLBI 17
@@ -43,9 +43,12 @@
#define ARM64_SVE 22
#define ARM64_UNMAP_KERNEL_AT_EL0 23
#define ARM64_HARDEN_BRANCH_PREDICTOR 24
-#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
-#define ARM64_HAS_RAS_EXTN 26
+#define ARM64_HAS_RAS_EXTN 25
+#define ARM64_WORKAROUND_843419 26
+#define ARM64_HAS_CACHE_IDC 27
+#define ARM64_HAS_CACHE_DIC 28
+#define ARM64_HW_DBM 29
-#define ARM64_NCAPS 27
+#define ARM64_NCAPS 30
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 060e3a4008ab..09b0f2a80c8f 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -10,6 +10,7 @@
#define __ASM_CPUFEATURE_H
#include <asm/cpucaps.h>
+#include <asm/cputype.h>
#include <asm/fpsimd.h>
#include <asm/hwcap.h>
#include <asm/sigcontext.h>
@@ -89,24 +90,231 @@ struct arm64_ftr_reg {
extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
-/* scope of capability check */
-enum {
- SCOPE_SYSTEM,
- SCOPE_LOCAL_CPU,
-};
+/*
+ * CPU capabilities:
+ *
+ * We use arm64_cpu_capabilities to represent system features, errata work
+ * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
+ * ELF HWCAPs (which are exposed to user).
+ *
+ * To support systems with heterogeneous CPUs, we need to make sure that we
+ * detect the capabilities correctly on the system and take appropriate
+ * measures to ensure there are no incompatibilities.
+ *
+ * This comment tries to explain how we treat the capabilities.
+ * Each capability has the following list of attributes :
+ *
+ * 1) Scope of Detection : The system detects a given capability by
+ * performing some checks at runtime. This could be, e.g, checking the
+ * value of a field in CPU ID feature register or checking the cpu
+ * model. The capability provides a call back ( @matches() ) to
+ * perform the check. Scope defines how the checks should be performed.
+ * There are three cases:
+ *
+ * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
+ * matches. This implies, we have to run the check on all the
+ * booting CPUs, until the system decides that state of the
+ * capability is finalised. (See section 2 below)
+ * Or
+ * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
+ * matches. This implies, we run the check only once, when the
+ * system decides to finalise the state of the capability. If the
+ * capability relies on a field in one of the CPU ID feature
+ * registers, we use the sanitised value of the register from the
+ * CPU feature infrastructure to make the decision.
+ * Or
+ * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
+ * feature. This category is for features that are "finalised"
+ * (or used) by the kernel very early even before the SMP cpus
+ * are brought up.
+ *
+ * The process of detection is usually denoted by "update" capability
+ * state in the code.
+ *
+ * 2) Finalise the state : The kernel should finalise the state of a
+ * capability at some point during its execution and take necessary
+ * actions if any. Usually, this is done, after all the boot-time
+ * enabled CPUs are brought up by the kernel, so that it can make
+ * better decision based on the available set of CPUs. However, there
+ * are some special cases, where the action is taken during the early
+ * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
+ * Virtualisation Host Extensions). The kernel usually disallows any
+ * changes to the state of a capability once it finalises the capability
+ * and takes any action, as it may be impossible to execute the actions
+ * safely. A CPU brought up after a capability is "finalised" is
+ * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
+ * CPUs are treated "late CPUs" for capabilities determined by the boot
+ * CPU.
+ *
+ * At the moment there are two passes of finalising the capabilities.
+ * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
+ * setup_boot_cpu_capabilities().
+ * b) Everything except (a) - Run via setup_system_capabilities().
+ *
+ * 3) Verification: When a CPU is brought online (e.g, by user or by the
+ * kernel), the kernel should make sure that it is safe to use the CPU,
+ * by verifying that the CPU is compliant with the state of the
+ * capabilities finalised already. This happens via :
+ *
+ * secondary_start_kernel()-> check_local_cpu_capabilities()
+ *
+ * As explained in (2) above, capabilities could be finalised at
+ * different points in the execution. Each newly booted CPU is verified
+ * against the capabilities that have been finalised by the time it
+ * boots.
+ *
+ * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
+ * except for the primary boot CPU.
+ *
+ * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
+ * user after the kernel boot are verified against the capability.
+ *
+ * If there is a conflict, the kernel takes an action, based on the
+ * severity (e.g, a CPU could be prevented from booting or cause a
+ * kernel panic). The CPU is allowed to "affect" the state of the
+ * capability, if it has not been finalised already. See section 5
+ * for more details on conflicts.
+ *
+ * 4) Action: As mentioned in (2), the kernel can take an action for each
+ * detected capability, on all CPUs on the system. Appropriate actions
+ * include, turning on an architectural feature, modifying the control
+ * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
+ * alternatives. The kernel patching is batched and performed at later
+ * point. The actions are always initiated only after the capability
+ * is finalised. This is usally denoted by "enabling" the capability.
+ * The actions are initiated as follows :
+ * a) Action is triggered on all online CPUs, after the capability is
+ * finalised, invoked within the stop_machine() context from
+ * enable_cpu_capabilitie().
+ *
+ * b) Any late CPU, brought up after (1), the action is triggered via:
+ *
+ * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
+ *
+ * 5) Conflicts: Based on the state of the capability on a late CPU vs.
+ * the system state, we could have the following combinations :
+ *
+ * x-----------------------------x
+ * | Type | System | Late CPU |
+ * |-----------------------------|
+ * | a | y | n |
+ * |-----------------------------|
+ * | b | n | y |
+ * x-----------------------------x
+ *
+ * Two separate flag bits are defined to indicate whether each kind of
+ * conflict can be allowed:
+ * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
+ * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
+ *
+ * Case (a) is not permitted for a capability that the system requires
+ * all CPUs to have in order for the capability to be enabled. This is
+ * typical for capabilities that represent enhanced functionality.
+ *
+ * Case (b) is not permitted for a capability that must be enabled
+ * during boot if any CPU in the system requires it in order to run
+ * safely. This is typical for erratum work arounds that cannot be
+ * enabled after the corresponding capability is finalised.
+ *
+ * In some non-typical cases either both (a) and (b), or neither,
+ * should be permitted. This can be described by including neither
+ * or both flags in the capability's type field.
+ */
+
+
+/*
+ * Decide how the capability is detected.
+ * On any local CPU vs System wide vs the primary boot CPU
+ */
+#define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
+#define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
+/*
+ * The capabilitiy is detected on the Boot CPU and is used by kernel
+ * during early boot. i.e, the capability should be "detected" and
+ * "enabled" as early as possibly on all booting CPUs.
+ */
+#define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
+#define ARM64_CPUCAP_SCOPE_MASK \
+ (ARM64_CPUCAP_SCOPE_SYSTEM | \
+ ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
+ ARM64_CPUCAP_SCOPE_BOOT_CPU)
+
+#define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
+#define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
+#define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
+#define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
+
+/*
+ * Is it permitted for a late CPU to have this capability when system
+ * hasn't already enabled it ?
+ */
+#define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
+/* Is it safe for a late CPU to miss this capability when system has it */
+#define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
+
+/*
+ * CPU errata workarounds that need to be enabled at boot time if one or
+ * more CPUs in the system requires it. When one of these capabilities
+ * has been enabled, it is safe to allow any CPU to boot that doesn't
+ * require the workaround. However, it is not safe if a "late" CPU
+ * requires a workaround and the system hasn't enabled it already.
+ */
+#define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
+ (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
+/*
+ * CPU feature detected at boot time based on system-wide value of a
+ * feature. It is safe for a late CPU to have this feature even though
+ * the system hasn't enabled it, although the featuer will not be used
+ * by Linux in this case. If the system has enabled this feature already,
+ * then every late CPU must have it.
+ */
+#define ARM64_CPUCAP_SYSTEM_FEATURE \
+ (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
+/*
+ * CPU feature detected at boot time based on feature of one or more CPUs.
+ * All possible conflicts for a late CPU are ignored.
+ */
+#define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
+ (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
+ ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
+ ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
+
+/*
+ * CPU feature detected at boot time, on one or more CPUs. A late CPU
+ * is not allowed to have the capability when the system doesn't have it.
+ * It is Ok for a late CPU to miss the feature.
+ */
+#define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
+ (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
+ ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
+
+/*
+ * CPU feature used early in the boot based on the boot CPU. All secondary
+ * CPUs must match the state of the capability as detected by the boot CPU.
+ */
+#define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE ARM64_CPUCAP_SCOPE_BOOT_CPU
struct arm64_cpu_capabilities {
const char *desc;
u16 capability;
- int def_scope; /* default scope */
+ u16 type;
bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
- int (*enable)(void *); /* Called on all active CPUs */
+ /*
+ * Take the appropriate actions to enable this capability for this CPU.
+ * For each successfully booted CPU, this method is called for each
+ * globally detected capability.
+ */
+ void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
union {
struct { /* To be used for erratum handling only */
- u32 midr_model;
- u32 midr_range_min, midr_range_max;
+ struct midr_range midr_range;
+ const struct arm64_midr_revidr {
+ u32 midr_rv; /* revision/variant */
+ u32 revidr_mask;
+ } * const fixed_revs;
};
+ const struct midr_range *midr_range_list;
struct { /* Feature register checking */
u32 sys_reg;
u8 field_pos;
@@ -115,9 +323,38 @@ struct arm64_cpu_capabilities {
bool sign;
unsigned long hwcap;
};
+ /*
+ * A list of "matches/cpu_enable" pair for the same
+ * "capability" of the same "type" as described by the parent.
+ * Only matches(), cpu_enable() and fields relevant to these
+ * methods are significant in the list. The cpu_enable is
+ * invoked only if the corresponding entry "matches()".
+ * However, if a cpu_enable() method is associated
+ * with multiple matches(), care should be taken that either
+ * the match criteria are mutually exclusive, or that the
+ * method is robust against being called multiple times.
+ */
+ const struct arm64_cpu_capabilities *match_list;
};
};
+static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
+{
+ return cap->type & ARM64_CPUCAP_SCOPE_MASK;
+}
+
+static inline bool
+cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
+{
+ return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
+}
+
+static inline bool
+cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
+{
+ return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
+}
+
extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
extern struct static_key_false arm64_const_caps_ready;
@@ -236,15 +473,8 @@ static inline bool id_aa64pfr0_sve(u64 pfr0)
}
void __init setup_cpu_features(void);
-
-void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
- const char *info);
-void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps);
void check_local_cpu_capabilities(void);
-void update_cpu_errata_workarounds(void);
-void __init enable_errata_workarounds(void);
-void verify_local_cpu_errata_workarounds(void);
u64 read_sanitised_ftr_reg(u32 id);
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 350c76a1d15b..30014a9f8f2b 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -83,6 +83,8 @@
#define ARM_CPU_PART_CORTEX_A53 0xD03
#define ARM_CPU_PART_CORTEX_A73 0xD09
#define ARM_CPU_PART_CORTEX_A75 0xD0A
+#define ARM_CPU_PART_CORTEX_A35 0xD04
+#define ARM_CPU_PART_CORTEX_A55 0xD05
#define APM_CPU_PART_POTENZA 0x000
@@ -102,6 +104,8 @@
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
+#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
+#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
@@ -118,6 +122,45 @@
#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
/*
+ * Represent a range of MIDR values for a given CPU model and a
+ * range of variant/revision values.
+ *
+ * @model - CPU model as defined by MIDR_CPU_MODEL
+ * @rv_min - Minimum value for the revision/variant as defined by
+ * MIDR_CPU_VAR_REV
+ * @rv_max - Maximum value for the variant/revision for the range.
+ */
+struct midr_range {
+ u32 model;
+ u32 rv_min;
+ u32 rv_max;
+};
+
+#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
+ { \
+ .model = m, \
+ .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
+ .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
+ }
+
+#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
+
+static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
+{
+ return MIDR_IS_CPU_MODEL_RANGE(midr, range->model,
+ range->rv_min, range->rv_max);
+}
+
+static inline bool
+is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
+{
+ while (ranges->model)
+ if (is_midr_in_range(midr, ranges++))
+ return true;
+ return false;
+}
+
+/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID
* rather than directly reading processor_id or read_cpuid() directly.
diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h
index 8389050328bb..192d791f1103 100644
--- a/arch/arm64/include/asm/efi.h
+++ b/arch/arm64/include/asm/efi.h
@@ -31,7 +31,7 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md);
({ \
efi_##f##_t *__f; \
__f = p->f; \
- __f(args); \
+ __efi_rt_asm_wrapper(__f, #f, args); \
})
#define arch_efi_call_virt_teardown() \
@@ -40,6 +40,8 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md);
efi_virtmap_unload(); \
})
+efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...);
+
#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
/* arch specific definitions used by the stub code */
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 803443d74926..ce70c3ffb993 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -240,6 +240,15 @@
(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
ESR_ELx_SYS64_ISS_OP2_SHIFT))
+/*
+ * ISS field definitions for floating-point exception traps
+ * (FP_EXC_32/FP_EXC_64).
+ *
+ * (The FPEXC_* constants are used instead for common bits.)
+ */
+
+#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
+
#ifndef __ASSEMBLY__
#include <asm/types.h>
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index 8857a0f0d0f7..aa7162ae93e3 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -22,33 +22,9 @@
#ifndef __ASSEMBLY__
#include <linux/cache.h>
+#include <linux/init.h>
#include <linux/stddef.h>
-/*
- * FP/SIMD storage area has:
- * - FPSR and FPCR
- * - 32 128-bit data registers
- *
- * Note that user_fpsimd forms a prefix of this structure, which is
- * relied upon in the ptrace FP/SIMD accessors.
- */
-struct fpsimd_state {
- union {
- struct user_fpsimd_state user_fpsimd;
- struct {
- __uint128_t vregs[32];
- u32 fpsr;
- u32 fpcr;
- /*
- * For ptrace compatibility, pad to next 128-bit
- * boundary here if extending this struct.
- */
- };
- };
- /* the id of the last cpu to have restored this state */
- unsigned int cpu;
-};
-
#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
/* Masks for extracting the FPSR and FPCR from the FPSCR */
#define VFP_FPSCR_STAT_MASK 0xf800009f
@@ -62,8 +38,8 @@ struct fpsimd_state {
struct task_struct;
-extern void fpsimd_save_state(struct fpsimd_state *state);
-extern void fpsimd_load_state(struct fpsimd_state *state);
+extern void fpsimd_save_state(struct user_fpsimd_state *state);
+extern void fpsimd_load_state(struct user_fpsimd_state *state);
extern void fpsimd_thread_switch(struct task_struct *next);
extern void fpsimd_flush_thread(void);
@@ -83,7 +59,9 @@ extern void sve_save_state(void *state, u32 *pfpsr);
extern void sve_load_state(void const *state, u32 const *pfpsr,
unsigned long vq_minus_1);
extern unsigned int sve_get_vl(void);
-extern int sve_kernel_enable(void *);
+
+struct arm64_cpu_capabilities;
+extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused);
extern int __ro_after_init sve_max_vl;
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 4214c38d016b..f62c56b1793f 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -70,6 +70,7 @@ enum aarch64_insn_imm_type {
AARCH64_INSN_IMM_6,
AARCH64_INSN_IMM_S,
AARCH64_INSN_IMM_R,
+ AARCH64_INSN_IMM_N,
AARCH64_INSN_IMM_MAX
};
@@ -314,6 +315,11 @@ __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
__AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
+__AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
+__AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
+__AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
+__AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
+__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
@@ -423,6 +429,16 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
int shift,
enum aarch64_insn_variant variant,
enum aarch64_insn_logic_type type);
+u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
+ enum aarch64_insn_variant variant,
+ enum aarch64_insn_register Rn,
+ enum aarch64_insn_register Rd,
+ u64 imm);
+u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
+ enum aarch64_insn_register Rm,
+ enum aarch64_insn_register Rn,
+ enum aarch64_insn_register Rd,
+ u8 lsb);
u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
enum aarch64_insn_prfm_type type,
enum aarch64_insn_prfm_target target,
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index b0c84171e6a3..6dd285e979c9 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -25,6 +25,7 @@
/* Hyp Configuration Register (HCR) bits */
#define HCR_TEA (UL(1) << 37)
#define HCR_TERR (UL(1) << 36)
+#define HCR_TLOR (UL(1) << 35)
#define HCR_E2H (UL(1) << 34)
#define HCR_ID (UL(1) << 33)
#define HCR_CD (UL(1) << 32)
@@ -64,6 +65,7 @@
/*
* The bits we set in HCR:
+ * TLOR: Trap LORegion register accesses
* RW: 64bit by default, can be overridden for 32bit VMs
* TAC: Trap ACTLR
* TSC: Trap SMC
@@ -81,9 +83,9 @@
*/
#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
- HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
+ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
+ HCR_FMO | HCR_IMO)
#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
-#define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO)
#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
/* TCR_EL2 Registers bits */
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 24961b732e65..f6648a3e4152 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -33,6 +33,7 @@
#define KVM_ARM64_DEBUG_DIRTY_SHIFT 0
#define KVM_ARM64_DEBUG_DIRTY (1 << KVM_ARM64_DEBUG_DIRTY_SHIFT)
+/* Translate a kernel address of @sym into its equivalent linear mapping */
#define kvm_ksym_ref(sym) \
({ \
void *val = &sym; \
@@ -57,7 +58,9 @@ extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);
extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
-extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+extern int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu);
+
+extern int __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu);
extern u64 __vgic_v3_get_ich_vtr_el2(void);
extern u64 __vgic_v3_read_vmcr(void);
@@ -68,7 +71,19 @@ extern u32 __kvm_get_mdcr_el2(void);
extern u32 __init_stage2_translation(void);
-extern void __qcom_hyp_sanitize_btac_predictors(void);
+#else /* __ASSEMBLY__ */
+
+.macro get_host_ctxt reg, tmp
+ adr_l \reg, kvm_host_cpu_state
+ mrs \tmp, tpidr_el2
+ add \reg, \reg, \tmp
+.endm
+
+.macro get_vcpu_ptr vcpu, ctxt
+ get_host_ctxt \ctxt, \vcpu
+ ldr \vcpu, [\ctxt, #HOST_CONTEXT_VCPU]
+ kern_hyp_va \vcpu
+.endm
#endif
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 413dc82b1e89..23b33e8ea03a 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -26,13 +26,15 @@
#include <asm/esr.h>
#include <asm/kvm_arm.h>
+#include <asm/kvm_hyp.h>
#include <asm/kvm_mmio.h>
#include <asm/ptrace.h>
#include <asm/cputype.h>
#include <asm/virt.h>
unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
-unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
+unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu);
+void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v);
bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
@@ -45,6 +47,11 @@ void kvm_inject_undef32(struct kvm_vcpu *vcpu);
void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
+static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
+{
+ return !(vcpu->arch.hcr_el2 & HCR_RW);
+}
+
static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
{
vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
@@ -59,16 +66,19 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
vcpu->arch.hcr_el2 &= ~HCR_RW;
-}
-static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.hcr_el2;
+ /*
+ * TID3: trap feature register accesses that we virtualise.
+ * For now this is conditional, since no AArch32 feature regs
+ * are currently virtualised.
+ */
+ if (!vcpu_el1_is_32bit(vcpu))
+ vcpu->arch.hcr_el2 |= HCR_TID3;
}
-static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
+static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
{
- vcpu->arch.hcr_el2 = hcr;
+ return (unsigned long *)&vcpu->arch.hcr_el2;
}
static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
@@ -81,11 +91,27 @@ static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
}
-static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
+static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
{
return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
}
+static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
+{
+ if (vcpu->arch.sysregs_loaded_on_cpu)
+ return read_sysreg_el1(elr);
+ else
+ return *__vcpu_elr_el1(vcpu);
+}
+
+static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
+{
+ if (vcpu->arch.sysregs_loaded_on_cpu)
+ write_sysreg_el1(v, elr);
+ else
+ *__vcpu_elr_el1(vcpu) = v;
+}
+
static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
{
return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
@@ -135,13 +161,28 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
}
-/* Get vcpu SPSR for current mode */
-static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
+static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
{
if (vcpu_mode_is_32bit(vcpu))
- return vcpu_spsr32(vcpu);
+ return vcpu_read_spsr32(vcpu);
- return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
+ if (vcpu->arch.sysregs_loaded_on_cpu)
+ return read_sysreg_el1(spsr);
+ else
+ return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
+}
+
+static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
+{
+ if (vcpu_mode_is_32bit(vcpu)) {
+ vcpu_write_spsr32(vcpu, v);
+ return;
+ }
+
+ if (vcpu->arch.sysregs_loaded_on_cpu)
+ write_sysreg_el1(v, spsr);
+ else
+ vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
}
static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
@@ -282,15 +323,18 @@ static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
{
- return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
+ return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
}
static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
{
- if (vcpu_mode_is_32bit(vcpu))
+ if (vcpu_mode_is_32bit(vcpu)) {
*vcpu_cpsr(vcpu) |= COMPAT_PSR_E_BIT;
- else
- vcpu_sys_reg(vcpu, SCTLR_EL1) |= (1 << 25);
+ } else {
+ u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
+ sctlr |= (1 << 25);
+ vcpu_write_sys_reg(vcpu, SCTLR_EL1, sctlr);
+ }
}
static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
@@ -298,7 +342,7 @@ static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
if (vcpu_mode_is_32bit(vcpu))
return !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_E_BIT);
- return !!(vcpu_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
+ return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
}
static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 596f8e414a4c..ab46bc70add6 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -272,9 +272,6 @@ struct kvm_vcpu_arch {
/* IO related fields */
struct kvm_decode mmio_decode;
- /* Interrupt related fields */
- u64 irq_lines; /* IRQ and FIQ levels */
-
/* Cache some mmu pages needed inside spinlock regions */
struct kvm_mmu_memory_cache mmu_page_cache;
@@ -287,10 +284,25 @@ struct kvm_vcpu_arch {
/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
u64 vsesr_el2;
+
+ /* True when deferrable sysregs are loaded on the physical CPU,
+ * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
+ bool sysregs_loaded_on_cpu;
};
#define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
-#define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
+
+/*
+ * Only use __vcpu_sys_reg if you know you want the memory backed version of a
+ * register, and not the one most recently accessed by a running VCPU. For
+ * example, for userspace access or for system registers that are never context
+ * switched, but only emulated.
+ */
+#define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
+
+u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg);
+void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
+
/*
* CP14 and CP15 live in the same array, as they are backed by the
* same system registers.
@@ -298,14 +310,6 @@ struct kvm_vcpu_arch {
#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
-#ifdef CONFIG_CPU_BIG_ENDIAN
-#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
-#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
-#else
-#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
-#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
-#endif
-
struct kvm_vm_stat {
ulong remote_tlb_flush;
};
@@ -358,10 +362,15 @@ int kvm_perf_teardown(void);
struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
+void __kvm_set_tpidr_el2(u64 tpidr_el2);
+DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
+
static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
unsigned long hyp_stack_ptr,
unsigned long vector_ptr)
{
+ u64 tpidr_el2;
+
/*
* Call initialization code, and switch to the full blown HYP code.
* If the cpucaps haven't been finalized yet, something has gone very
@@ -370,6 +379,16 @@ static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
*/
BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
+
+ /*
+ * Calculate the raw per-cpu offset without a translation from the
+ * kernel's mapping to the linear mapping, and store it in tpidr_el2
+ * so that we can use adr_l to access per-cpu variables in EL2.
+ */
+ tpidr_el2 = (u64)this_cpu_ptr(&kvm_host_cpu_state)
+ - (u64)kvm_ksym_ref(kvm_host_cpu_state);
+
+ kvm_call_hyp(__kvm_set_tpidr_el2, tpidr_el2);
}
static inline void kvm_arch_hardware_unsetup(void) {}
@@ -416,6 +435,13 @@ static inline void kvm_arm_vhe_guest_enter(void)
static inline void kvm_arm_vhe_guest_exit(void)
{
local_daif_restore(DAIF_PROCCTX_NOIRQ);
+
+ /*
+ * When we exit from the guest we change a number of CPU configuration
+ * parameters, such as traps. Make sure these changes take effect
+ * before running the host or additional guests.
+ */
+ isb();
}
static inline bool kvm_arm_harden_branch_predictor(void)
@@ -423,4 +449,7 @@ static inline bool kvm_arm_harden_branch_predictor(void)
return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
}
+void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
+void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
+
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
index f26f9cd70c72..384c34397619 100644
--- a/arch/arm64/include/asm/kvm_hyp.h
+++ b/arch/arm64/include/asm/kvm_hyp.h
@@ -120,37 +120,38 @@ typeof(orig) * __hyp_text fname(void) \
return val; \
}
-void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
-void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu);
void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
+void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu);
+void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu);
+void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu);
+void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu);
int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu);
void __timer_enable_traps(struct kvm_vcpu *vcpu);
void __timer_disable_traps(struct kvm_vcpu *vcpu);
-void __sysreg_save_host_state(struct kvm_cpu_context *ctxt);
-void __sysreg_restore_host_state(struct kvm_cpu_context *ctxt);
-void __sysreg_save_guest_state(struct kvm_cpu_context *ctxt);
-void __sysreg_restore_guest_state(struct kvm_cpu_context *ctxt);
+void __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt);
+void __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt);
+void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt);
+void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt);
+void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt);
+void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt);
void __sysreg32_save_state(struct kvm_vcpu *vcpu);
void __sysreg32_restore_state(struct kvm_vcpu *vcpu);
-void __debug_save_state(struct kvm_vcpu *vcpu,
- struct kvm_guest_debug_arch *dbg,
- struct kvm_cpu_context *ctxt);
-void __debug_restore_state(struct kvm_vcpu *vcpu,
- struct kvm_guest_debug_arch *dbg,
- struct kvm_cpu_context *ctxt);
-void __debug_cond_save_host_state(struct kvm_vcpu *vcpu);
-void __debug_cond_restore_host_state(struct kvm_vcpu *vcpu);
+void __debug_switch_to_guest(struct kvm_vcpu *vcpu);
+void __debug_switch_to_host(struct kvm_vcpu *vcpu);
void __fpsimd_save_state(struct user_fpsimd_state *fp_regs);
void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs);
bool __fpsimd_enabled(void);
+void activate_traps_vhe_load(struct kvm_vcpu *vcpu);
+void deactivate_traps_vhe_put(void);
+
u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt);
void __noreturn __hyp_do_panic(unsigned long, ...);
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 7faed6e48b46..082110993647 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -69,9 +69,6 @@
* mappings, and none of this applies in that case.
*/
-#define HYP_PAGE_OFFSET_HIGH_MASK ((UL(1) << VA_BITS) - 1)
-#define HYP_PAGE_OFFSET_LOW_MASK ((UL(1) << (VA_BITS - 1)) - 1)
-
#ifdef __ASSEMBLY__
#include <asm/alternative.h>
@@ -81,28 +78,19 @@
* Convert a kernel VA into a HYP VA.
* reg: VA to be converted.
*
- * This generates the following sequences:
- * - High mask:
- * and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
- * nop
- * - Low mask:
- * and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
- * and x0, x0, #HYP_PAGE_OFFSET_LOW_MASK
- * - VHE:
- * nop
- * nop
- *
- * The "low mask" version works because the mask is a strict subset of
- * the "high mask", hence performing the first mask for nothing.
- * Should be completely invisible on any viable CPU.
+ * The actual code generation takes place in kvm_update_va_mask, and
+ * the instructions below are only there to reserve the space and
+ * perform the register allocation (kvm_update_va_mask uses the
+ * specific registers encoded in the instructions).
*/
.macro kern_hyp_va reg
-alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
- and \reg, \reg, #HYP_PAGE_OFFSET_HIGH_MASK
-alternative_else_nop_endif
-alternative_if ARM64_HYP_OFFSET_LOW
- and \reg, \reg, #HYP_PAGE_OFFSET_LOW_MASK
-alternative_else_nop_endif
+alternative_cb kvm_update_va_mask
+ and \reg, \reg, #1 /* mask with va_mask */
+ ror \reg, \reg, #1 /* rotate to the first tag bit */
+ add \reg, \reg, #0 /* insert the low 12 bits of the tag */
+ add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */
+ ror \reg, \reg, #63 /* rotate back */
+alternative_cb_end
.endm
#else
@@ -113,24 +101,44 @@ alternative_else_nop_endif
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
+void kvm_update_va_mask(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr, int nr_inst);
+
static inline unsigned long __kern_hyp_va(unsigned long v)
{
- asm volatile(ALTERNATIVE("and %0, %0, %1",
- "nop",
- ARM64_HAS_VIRT_HOST_EXTN)
- : "+r" (v)
- : "i" (HYP_PAGE_OFFSET_HIGH_MASK));
- asm volatile(ALTERNATIVE("nop",
- "and %0, %0, %1",
- ARM64_HYP_OFFSET_LOW)
- : "+r" (v)
- : "i" (HYP_PAGE_OFFSET_LOW_MASK));
+ asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
+ "ror %0, %0, #1\n"
+ "add %0, %0, #0\n"
+ "add %0, %0, #0, lsl 12\n"
+ "ror %0, %0, #63\n",
+ kvm_update_va_mask)
+ : "+r" (v));
return v;
}
#define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v))))
/*
+ * Obtain the PC-relative address of a kernel symbol
+ * s: symbol
+ *
+ * The goal of this macro is to return a symbol's address based on a
+ * PC-relative computation, as opposed to a loading the VA from a
+ * constant pool or something similar. This works well for HYP, as an
+ * absolute VA is guaranteed to be wrong. Only use this if trying to
+ * obtain the address of a symbol (i.e. not something you obtained by
+ * following a pointer).
+ */
+#define hyp_symbol_addr(s) \
+ ({ \
+ typeof(s) *addr; \
+ asm("adrp %0, %1\n" \
+ "add %0, %0, :lo12:%1\n" \
+ : "=r" (addr) : "S" (&s)); \
+ addr; \
+ })
+
+/*
* We currently only support a 40bit IPA.
*/
#define KVM_PHYS_SHIFT (40)
@@ -140,7 +148,11 @@ static inline unsigned long __kern_hyp_va(unsigned long v)
#include <asm/stage2_pgtable.h>
int create_hyp_mappings(void *from, void *to, pgprot_t prot);
-int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
+ void __iomem **kaddr,
+ void __iomem **haddr);
+int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
+ void **haddr);
void free_hyp_pgds(void);
void stage2_unmap_vm(struct kvm *kvm);
@@ -249,7 +261,7 @@ struct kvm;
static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
{
- return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
+ return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
}
static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
@@ -348,36 +360,95 @@ static inline unsigned int kvm_get_vmid_bits(void)
return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;
}
-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
+#ifdef CONFIG_KVM_INDIRECT_VECTORS
+/*
+ * EL2 vectors can be mapped and rerouted in a number of ways,
+ * depending on the kernel configuration and CPU present:
+ *
+ * - If the CPU has the ARM64_HARDEN_BRANCH_PREDICTOR cap, the
+ * hardening sequence is placed in one of the vector slots, which is
+ * executed before jumping to the real vectors.
+ *
+ * - If the CPU has both the ARM64_HARDEN_EL2_VECTORS cap and the
+ * ARM64_HARDEN_BRANCH_PREDICTOR cap, the slot containing the
+ * hardening sequence is mapped next to the idmap page, and executed
+ * before jumping to the real vectors.
+ *
+ * - If the CPU only has the ARM64_HARDEN_EL2_VECTORS cap, then an
+ * empty slot is selected, mapped next to the idmap page, and
+ * executed before jumping to the real vectors.
+ *
+ * Note that ARM64_HARDEN_EL2_VECTORS is somewhat incompatible with
+ * VHE, as we don't have hypervisor-specific mappings. If the system
+ * is VHE and yet selects this capability, it will be ignored.
+ */
#include <asm/mmu.h>
+extern void *__kvm_bp_vect_base;
+extern int __kvm_harden_el2_vector_slot;
+
static inline void *kvm_get_hyp_vector(void)
{
struct bp_hardening_data *data = arm64_get_bp_hardening_data();
- void *vect = kvm_ksym_ref(__kvm_hyp_vector);
+ void *vect = kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector));
+ int slot = -1;
- if (data->fn) {
- vect = __bp_harden_hyp_vecs_start +
- data->hyp_vectors_slot * SZ_2K;
+ if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR) && data->fn) {
+ vect = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs_start));
+ slot = data->hyp_vectors_slot;
+ }
- if (!has_vhe())
- vect = lm_alias(vect);
+ if (this_cpu_has_cap(ARM64_HARDEN_EL2_VECTORS) && !has_vhe()) {
+ vect = __kvm_bp_vect_base;
+ if (slot == -1)
+ slot = __kvm_harden_el2_vector_slot;
}
+ if (slot != -1)
+ vect += slot * SZ_2K;
+
return vect;
}
+/* This is only called on a !VHE system */
static inline int kvm_map_vectors(void)
{
- return create_hyp_mappings(kvm_ksym_ref(__bp_harden_hyp_vecs_start),
- kvm_ksym_ref(__bp_harden_hyp_vecs_end),
- PAGE_HYP_EXEC);
-}
+ /*
+ * HBP = ARM64_HARDEN_BRANCH_PREDICTOR
+ * HEL2 = ARM64_HARDEN_EL2_VECTORS
+ *
+ * !HBP + !HEL2 -> use direct vectors
+ * HBP + !HEL2 -> use hardened vectors in place
+ * !HBP + HEL2 -> allocate one vector slot and use exec mapping
+ * HBP + HEL2 -> use hardened vertors and use exec mapping
+ */
+ if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) {
+ __kvm_bp_vect_base = kvm_ksym_ref(__bp_harden_hyp_vecs_start);
+ __kvm_bp_vect_base = kern_hyp_va(__kvm_bp_vect_base);
+ }
+
+ if (cpus_have_const_cap(ARM64_HARDEN_EL2_VECTORS)) {
+ phys_addr_t vect_pa = __pa_symbol(__bp_harden_hyp_vecs_start);
+ unsigned long size = (__bp_harden_hyp_vecs_end -
+ __bp_harden_hyp_vecs_start);
+
+ /*
+ * Always allocate a spare vector slot, as we don't
+ * know yet which CPUs have a BP hardening slot that
+ * we can reuse.
+ */
+ __kvm_harden_el2_vector_slot = atomic_inc_return(&arm64_el2_vector_last_slot);
+ BUG_ON(__kvm_harden_el2_vector_slot >= BP_HARDEN_EL2_SLOTS);
+ return create_hyp_exec_mappings(vect_pa, size,
+ &__kvm_bp_vect_base);
+ }
+ return 0;
+}
#else
static inline void *kvm_get_hyp_vector(void)
{
- return kvm_ksym_ref(__kvm_hyp_vector);
+ return kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector));
}
static inline int kvm_map_vectors(void)
diff --git a/arch/arm64/include/asm/lse.h b/arch/arm64/include/asm/lse.h
index eec95768eaad..8262325e2fc6 100644
--- a/arch/arm64/include/asm/lse.h
+++ b/arch/arm64/include/asm/lse.h
@@ -4,8 +4,11 @@
#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
+#include <linux/compiler_types.h>
+#include <linux/export.h>
#include <linux/stringify.h>
#include <asm/alternative.h>
+#include <asm/cpucaps.h>
#ifdef __ASSEMBLER__
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 50fa96a49792..49d99214f43c 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -29,12 +29,6 @@
#include <asm/sizes.h>
/*
- * Allow for constants defined here to be used from assembly code
- * by prepending the UL suffix only with actual C code compilation.
- */
-#define UL(x) _AC(x, UL)
-
-/*
* Size of the PCI I/O space. This must remain a power of two so that
* IO_SPACE_LIMIT acts as a mask for the low bits of I/O addresses.
*/
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index a050d4f3615d..dd320df0d026 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -21,6 +21,8 @@
#define USER_ASID_FLAG (UL(1) << USER_ASID_BIT)
#define TTBR_ASID_MASK (UL(0xffff) << 48)
+#define BP_HARDEN_EL2_SLOTS 4
+
#ifndef __ASSEMBLY__
typedef struct {
@@ -49,9 +51,13 @@ struct bp_hardening_data {
bp_hardening_cb_t fn;
};
-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
+#if (defined(CONFIG_HARDEN_BRANCH_PREDICTOR) || \
+ defined(CONFIG_HARDEN_EL2_VECTORS))
extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[];
+extern atomic_t arm64_el2_vector_last_slot;
+#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR || CONFIG_HARDEN_EL2_VECTORS */
+#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h
index 4f766178fa6f..b6dbbe3123a9 100644
--- a/arch/arm64/include/asm/module.h
+++ b/arch/arm64/include/asm/module.h
@@ -39,6 +39,8 @@ struct mod_arch_specific {
u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
Elf64_Sym *sym);
+u64 module_emit_adrp_veneer(struct module *mod, void *loc, u64 val);
+
#ifdef CONFIG_RANDOMIZE_BASE
extern u64 module_alloc_base;
#else
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 43393208229e..9234013e759e 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -16,7 +16,10 @@
#ifndef __ASM_PERCPU_H
#define __ASM_PERCPU_H
+#include <linux/preempt.h>
+
#include <asm/alternative.h>
+#include <asm/cmpxchg.h>
#include <asm/stack_pointer.h>
static inline void set_my_cpu_offset(unsigned long off)
@@ -197,6 +200,32 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
return ret;
}
+/* this_cpu_cmpxchg */
+#define _protect_cmpxchg_local(pcp, o, n) \
+({ \
+ typeof(*raw_cpu_ptr(&(pcp))) __ret; \
+ preempt_disable(); \
+ __ret = cmpxchg_local(raw_cpu_ptr(&(pcp)), o, n); \
+ preempt_enable(); \
+ __ret; \
+})
+
+#define this_cpu_cmpxchg_1(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
+#define this_cpu_cmpxchg_2(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
+#define this_cpu_cmpxchg_4(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
+#define this_cpu_cmpxchg_8(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
+
+#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \
+({ \
+ int __ret; \
+ preempt_disable(); \
+ __ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \
+ raw_cpu_ptr(&(ptr2)), \
+ o1, o2, n1, n2); \
+ preempt_enable(); \
+ __ret; \
+})
+
#define _percpu_read(pcp) \
({ \
typeof(pcp) __retval; \
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index cdfe3e657a9e..fd208eac9f2a 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -291,6 +291,7 @@
#define TCR_TBI0 (UL(1) << 37)
#define TCR_HA (UL(1) << 39)
#define TCR_HD (UL(1) << 40)
+#define TCR_NFD1 (UL(1) << 54)
/*
* TTBR.
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index fce604e3e599..767598932549 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -34,10 +34,12 @@
#ifdef __KERNEL__
+#include <linux/build_bug.h>
+#include <linux/stddef.h>
#include <linux/string.h>
#include <asm/alternative.h>
-#include <asm/fpsimd.h>
+#include <asm/cpufeature.h>
#include <asm/hw_breakpoint.h>
#include <asm/lse.h>
#include <asm/pgtable-hwdef.h>
@@ -103,11 +105,19 @@ struct cpu_context {
struct thread_struct {
struct cpu_context cpu_context; /* cpu context */
- unsigned long tp_value; /* TLS register */
-#ifdef CONFIG_COMPAT
- unsigned long tp2_value;
-#endif
- struct fpsimd_state fpsimd_state;
+
+ /*
+ * Whitelisted fields for hardened usercopy:
+ * Maintainers must ensure manually that this contains no
+ * implicit padding.
+ */
+ struct {
+ unsigned long tp_value; /* TLS register */
+ unsigned long tp2_value;
+ struct user_fpsimd_state fpsimd_state;
+ } uw;
+
+ unsigned int fpsimd_cpu;
void *sve_state; /* SVE registers, if any */
unsigned int sve_vl; /* SVE vector length */
unsigned int sve_vl_onexec; /* SVE vl after next exec */
@@ -116,14 +126,17 @@ struct thread_struct {
struct debug_info debug; /* debugging */
};
-/*
- * Everything usercopied to/from thread_struct is statically-sized, so
- * no hardened usercopy whitelist is needed.
- */
static inline void arch_thread_struct_whitelist(unsigned long *offset,
unsigned long *size)
{
- *offset = *size = 0;
+ /* Verify that there is no padding among the whitelisted fields: */
+ BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
+ sizeof_field(struct thread_struct, uw.tp_value) +
+ sizeof_field(struct thread_struct, uw.tp2_value) +
+ sizeof_field(struct thread_struct, uw.fpsimd_state));
+
+ *offset = offsetof(struct thread_struct, uw);
+ *size = sizeof_field(struct thread_struct, uw);
}
#ifdef CONFIG_COMPAT
@@ -131,13 +144,13 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
({ \
unsigned long *__tls; \
if (is_compat_thread(task_thread_info(t))) \
- __tls = &(t)->thread.tp2_value; \
+ __tls = &(t)->thread.uw.tp2_value; \
else \
- __tls = &(t)->thread.tp_value; \
+ __tls = &(t)->thread.uw.tp_value; \
__tls; \
})
#else
-#define task_user_tls(t) (&(t)->thread.tp_value)
+#define task_user_tls(t) (&(t)->thread.uw.tp_value)
#endif
/* Sync TPIDR_EL0 back to thread_struct for current */
@@ -227,9 +240,9 @@ static inline void spin_lock_prefetch(const void *ptr)
#endif
-int cpu_enable_pan(void *__unused);
-int cpu_enable_cache_maint_trap(void *__unused);
-int cpu_clear_disr(void *__unused);
+void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);
+void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);
+void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused);
/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
#define SVE_SET_VL(arg) sve_set_current_vl(arg)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0e1960c59197..6171178075dc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -288,6 +288,12 @@
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
+#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
+#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
+#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
+#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
+#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
+
#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
@@ -490,6 +496,7 @@
#define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0)
/* id_aa64isar0 */
+#define ID_AA64ISAR0_TS_SHIFT 52
#define ID_AA64ISAR0_FHM_SHIFT 48
#define ID_AA64ISAR0_DP_SHIFT 44
#define ID_AA64ISAR0_SM4_SHIFT 40
@@ -511,6 +518,7 @@
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV2_SHIFT 56
+#define ID_AA64PFR0_DIT_SHIFT 48
#define ID_AA64PFR0_SVE_SHIFT 32
#define ID_AA64PFR0_RAS_SHIFT 28
#define ID_AA64PFR0_GIC_SHIFT 24
@@ -568,6 +576,7 @@
#define ID_AA64MMFR1_VMIDBITS_16 2
/* id_aa64mmfr2 */
+#define ID_AA64MMFR2_AT_SHIFT 32
#define ID_AA64MMFR2_LVA_SHIFT 16
#define ID_AA64MMFR2_IESB_SHIFT 12
#define ID_AA64MMFR2_LSM_SHIFT 8
diff --git a/arch/arm64/include/asm/system_misc.h b/arch/arm64/include/asm/system_misc.h
index 07aa8e3c5630..28893a0b141d 100644
--- a/arch/arm64/include/asm/system_misc.h
+++ b/arch/arm64/include/asm/system_misc.h
@@ -45,17 +45,6 @@ extern void __show_regs(struct pt_regs *);
extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
-#define show_unhandled_signals_ratelimited() \
-({ \
- static DEFINE_RATELIMIT_STATE(_rs, \
- DEFAULT_RATELIMIT_INTERVAL, \
- DEFAULT_RATELIMIT_BURST); \
- bool __show_ratelimited = false; \
- if (show_unhandled_signals && __ratelimit(&_rs)) \
- __show_ratelimited = true; \
- __show_ratelimited; \
-})
-
int handle_guest_sea(phys_addr_t addr, unsigned int esr);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 9e82dd79c7db..dfc61d73f740 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -60,6 +60,15 @@
__tlbi(op, (arg) | USER_ASID_FLAG); \
} while (0)
+/* This macro creates a properly formatted VA operand for the TLBI */
+#define __TLBI_VADDR(addr, asid) \
+ ({ \
+ unsigned long __ta = (addr) >> 12; \
+ __ta &= GENMASK_ULL(43, 0); \
+ __ta |= (unsigned long)(asid) << 48; \
+ __ta; \
+ })
+
/*
* TLB Management
* ==============
@@ -117,7 +126,7 @@ static inline void flush_tlb_all(void)
static inline void flush_tlb_mm(struct mm_struct *mm)
{
- unsigned long asid = ASID(mm) << 48;
+ unsigned long asid = __TLBI_VADDR(0, ASID(mm));
dsb(ishst);
__tlbi(aside1is, asid);
@@ -128,7 +137,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long uaddr)
{
- unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48);
+ unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
dsb(ishst);
__tlbi(vale1is, addr);
@@ -146,7 +155,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end,
bool last_level)
{
- unsigned long asid = ASID(vma->vm_mm) << 48;
+ unsigned long asid = ASID(vma->vm_mm);
unsigned long addr;
if ((end - start) > MAX_TLB_RANGE) {
@@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
return;
}
- start = asid | (start >> 12);
- end = asid | (end >> 12);
+ start = __TLBI_VADDR(start, asid);
+ end = __TLBI_VADDR(end, asid);
dsb(ishst);
for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) {
@@ -185,8 +194,8 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
return;
}
- start >>= 12;
- end >>= 12;
+ start = __TLBI_VADDR(start, 0);
+ end = __TLBI_VADDR(end, 0);
dsb(ishst);
for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12))
@@ -202,7 +211,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
static inline void __flush_tlb_pgtable(struct mm_struct *mm,
unsigned long uaddr)
{
- unsigned long addr = uaddr >> 12 | (ASID(mm) << 48);
+ unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm));
__tlbi(vae1is, addr);
__tlbi_user(vae1is, addr);
diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h
index 178e338d2889..c320f3bf6c57 100644
--- a/arch/arm64/include/asm/traps.h
+++ b/arch/arm64/include/asm/traps.h
@@ -35,10 +35,10 @@ struct undef_hook {
void register_undef_hook(struct undef_hook *hook);
void unregister_undef_hook(struct undef_hook *hook);
-void force_signal_inject(int signal, int code, struct pt_regs *regs,
- unsigned long address);
-
-void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr);
+void force_signal_inject(int signal, int code, unsigned long address);
+void arm64_notify_segfault(unsigned long addr);
+void arm64_force_sig_info(struct siginfo *info, const char *str,
+ struct task_struct *tsk);
/*
* Move regs->pc to next instruction and do necessary setup before it
diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
index c5f89442785c..9d1e24e030b3 100644
--- a/arch/arm64/include/asm/virt.h
+++ b/arch/arm64/include/asm/virt.h
@@ -102,12 +102,6 @@ static inline bool has_vhe(void)
return false;
}
-#ifdef CONFIG_ARM64_VHE
-extern void verify_cpu_run_el(void);
-#else
-static inline void verify_cpu_run_el(void) {}
-#endif
-
#endif /* __ASSEMBLY__ */
#endif /* ! __ASM__VIRT_H */
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index f018c3deea3b..17c65c8f33cb 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -44,5 +44,9 @@
#define HWCAP_SHA512 (1 << 21)
#define HWCAP_SVE (1 << 22)
#define HWCAP_ASIMDFHM (1 << 23)
+#define HWCAP_DIT (1 << 24)
+#define HWCAP_USCAT (1 << 25)
+#define HWCAP_ILRCPC (1 << 26)
+#define HWCAP_FLAGM (1 << 27)
#endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/include/uapi/asm/siginfo.h b/arch/arm64/include/uapi/asm/siginfo.h
index 9b4d91277742..574d12f86039 100644
--- a/arch/arm64/include/uapi/asm/siginfo.h
+++ b/arch/arm64/include/uapi/asm/siginfo.h
@@ -21,25 +21,4 @@
#include <asm-generic/siginfo.h>
-/*
- * SIGFPE si_codes
- */
-#ifdef __KERNEL__
-#define FPE_FIXME 0 /* Broken dup of SI_USER */
-#endif /* __KERNEL__ */
-
-/*
- * SIGBUS si_codes
- */
-#ifdef __KERNEL__
-#define BUS_FIXME 0 /* Broken dup of SI_USER */
-#endif /* __KERNEL__ */
-
-/*
- * SIGTRAP si_codes
- */
-#ifdef __KERNEL__
-#define TRAP_FIXME 0 /* Broken dup of SI_USER */
-#endif /* __KERNEL__ */
-
#endif
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index b87541360f43..bf825f38d206 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -38,7 +38,8 @@ arm64-obj-$(CONFIG_CPU_PM) += sleep.o suspend.o
arm64-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
arm64-obj-$(CONFIG_KGDB) += kgdb.o
-arm64-obj-$(CONFIG_EFI) += efi.o efi-entry.stub.o
+arm64-obj-$(CONFIG_EFI) += efi.o efi-entry.stub.o \
+ efi-rt-wrapper.o
arm64-obj-$(CONFIG_PCI) += pci.o
arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o
arm64-obj-$(CONFIG_ACPI) += acpi.o
@@ -54,10 +55,6 @@ arm64-reloc-test-y := reloc_test_core.o reloc_test_syms.o
arm64-obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
arm64-obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o
-ifeq ($(CONFIG_KVM),y)
-arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o
-endif
-
obj-y += $(arm64-obj-y) vdso/ probes/
obj-m += $(arm64-obj-m)
head-y := head.o
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
index 414288a558c8..5c4bce4ac381 100644
--- a/arch/arm64/kernel/alternative.c
+++ b/arch/arm64/kernel/alternative.c
@@ -107,32 +107,53 @@ static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnp
return insn;
}
+static void patch_alternative(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr, int nr_inst)
+{
+ __le32 *replptr;
+ int i;
+
+ replptr = ALT_REPL_PTR(alt);
+ for (i = 0; i < nr_inst; i++) {
+ u32 insn;
+
+ insn = get_alt_insn(alt, origptr + i, replptr + i);
+ updptr[i] = cpu_to_le32(insn);
+ }
+}
+
static void __apply_alternatives(void *alt_region, bool use_linear_alias)
{
struct alt_instr *alt;
struct alt_region *region = alt_region;
- __le32 *origptr, *replptr, *updptr;
+ __le32 *origptr, *updptr;
+ alternative_cb_t alt_cb;
for (alt = region->begin; alt < region->end; alt++) {
- u32 insn;
- int i, nr_inst;
+ int nr_inst;
- if (!cpus_have_cap(alt->cpufeature))
+ /* Use ARM64_CB_PATCH as an unconditional patch */
+ if (alt->cpufeature < ARM64_CB_PATCH &&
+ !cpus_have_cap(alt->cpufeature))
continue;
- BUG_ON(alt->alt_len != alt->orig_len);
+ if (alt->cpufeature == ARM64_CB_PATCH)
+ BUG_ON(alt->alt_len != 0);
+ else
+ BUG_ON(alt->alt_len != alt->orig_len);
pr_info_once("patching kernel code\n");
origptr = ALT_ORIG_PTR(alt);
- replptr = ALT_REPL_PTR(alt);
updptr = use_linear_alias ? lm_alias(origptr) : origptr;
- nr_inst = alt->alt_len / sizeof(insn);
+ nr_inst = alt->orig_len / AARCH64_INSN_SIZE;
- for (i = 0; i < nr_inst; i++) {
- insn = get_alt_insn(alt, origptr + i, replptr + i);
- updptr[i] = cpu_to_le32(insn);
- }
+ if (alt->cpufeature < ARM64_CB_PATCH)
+ alt_cb = patch_alternative;
+ else
+ alt_cb = ALT_REPL_PTR(alt);
+
+ alt_cb(alt, origptr, updptr, nr_inst);
flush_icache_range((uintptr_t)origptr,
(uintptr_t)(origptr + nr_inst));
diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c
index 68450e954d47..6e47fc3ab549 100644
--- a/arch/arm64/kernel/armv8_deprecated.c
+++ b/arch/arm64/kernel/armv8_deprecated.c
@@ -429,7 +429,7 @@ ret:
fault:
pr_debug("SWP{B} emulation: access caused memory abort!\n");
- arm64_notify_segfault(regs, address);
+ arm64_notify_segfault(address);
return 0;
}
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index 1303e04110cd..5bdda651bd05 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -23,6 +23,7 @@
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/kvm_host.h>
+#include <linux/preempt.h>
#include <linux/suspend.h>
#include <asm/cpufeature.h>
#include <asm/fixmap.h>
@@ -93,6 +94,8 @@ int main(void)
DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
BLANK();
+ DEFINE(PREEMPT_DISABLE_OFFSET, PREEMPT_DISABLE_OFFSET);
+ BLANK();
DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW);
@@ -138,6 +141,7 @@ int main(void)
DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2]));
DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
+ DEFINE(HOST_CONTEXT_VCPU, offsetof(struct kvm_cpu_context, __hyp_running_vcpu));
#endif
#ifdef CONFIG_CPU_PM
DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx));
diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S
deleted file mode 100644
index e5de33513b5d..000000000000
--- a/arch/arm64/kernel/bpi.S
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Contains CPU specific branch predictor invalidation sequences
- *
- * Copyright (C) 2018 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/linkage.h>
-#include <linux/arm-smccc.h>
-
-.macro ventry target
- .rept 31
- nop
- .endr
- b \target
-.endm
-
-.macro vectors target
- ventry \target + 0x000
- ventry \target + 0x080
- ventry \target + 0x100
- ventry \target + 0x180
-
- ventry \target + 0x200
- ventry \target + 0x280
- ventry \target + 0x300
- ventry \target + 0x380
-
- ventry \target + 0x400
- ventry \target + 0x480
- ventry \target + 0x500
- ventry \target + 0x580
-
- ventry \target + 0x600
- ventry \target + 0x680
- ventry \target + 0x700
- ventry \target + 0x780
-.endm
-
- .align 11
-ENTRY(__bp_harden_hyp_vecs_start)
- .rept 4
- vectors __kvm_hyp_vector
- .endr
-ENTRY(__bp_harden_hyp_vecs_end)
-
-ENTRY(__qcom_hyp_sanitize_link_stack_start)
- stp x29, x30, [sp, #-16]!
- .rept 16
- bl . + 4
- .endr
- ldp x29, x30, [sp], #16
-ENTRY(__qcom_hyp_sanitize_link_stack_end)
-
-.macro smccc_workaround_1 inst
- sub sp, sp, #(8 * 4)
- stp x2, x3, [sp, #(8 * 0)]
- stp x0, x1, [sp, #(8 * 2)]
- mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1
- \inst #0
- ldp x2, x3, [sp, #(8 * 0)]
- ldp x0, x1, [sp, #(8 * 2)]
- add sp, sp, #(8 * 4)
-.endm
-
-ENTRY(__smccc_workaround_1_smc_start)
- smccc_workaround_1 smc
-ENTRY(__smccc_workaround_1_smc_end)
-
-ENTRY(__smccc_workaround_1_hvc_start)
- smccc_workaround_1 hvc
-ENTRY(__smccc_workaround_1_hvc_end)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index b5a28336c077..a900befadfe8 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -24,10 +24,28 @@
static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
{
+ const struct arm64_midr_revidr *fix;
+ u32 midr = read_cpuid_id(), revidr;
+
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
- return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
- entry->midr_range_min,
- entry->midr_range_max);
+ if (!is_midr_in_range(midr, &entry->midr_range))
+ return false;
+
+ midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
+ revidr = read_cpuid(REVIDR_EL1);
+ for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
+ if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
+ return false;
+
+ return true;
+}
+
+static bool __maybe_unused
+is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
+ int scope)
+{
+ WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
+ return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
}
static bool __maybe_unused
@@ -41,7 +59,7 @@ is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
MIDR_ARCHITECTURE_MASK;
- return model == entry->midr_model;
+ return model == entry->midr_range.model;
}
static bool
@@ -53,26 +71,24 @@ has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
}
-static int cpu_enable_trap_ctr_access(void *__unused)
+static void
+cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
{
/* Clear SCTLR_EL1.UCT */
config_sctlr_el1(SCTLR_EL1_UCT, 0);
- return 0;
}
+atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
+
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
-#ifdef CONFIG_KVM
-extern char __qcom_hyp_sanitize_link_stack_start[];
-extern char __qcom_hyp_sanitize_link_stack_end[];
+#ifdef CONFIG_KVM_INDIRECT_VECTORS
extern char __smccc_workaround_1_smc_start[];
extern char __smccc_workaround_1_smc_end[];
-extern char __smccc_workaround_1_hvc_start[];
-extern char __smccc_workaround_1_hvc_end[];
static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
const char *hyp_vecs_end)
@@ -90,7 +106,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
const char *hyp_vecs_start,
const char *hyp_vecs_end)
{
- static int last_slot = -1;
static DEFINE_SPINLOCK(bp_lock);
int cpu, slot = -1;
@@ -103,10 +118,8 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
}
if (slot == -1) {
- last_slot++;
- BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
- / SZ_2K) <= last_slot);
- slot = last_slot;
+ slot = atomic_inc_return(&arm64_el2_vector_last_slot);
+ BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
}
@@ -115,12 +128,8 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
spin_unlock(&bp_lock);
}
#else
-#define __qcom_hyp_sanitize_link_stack_start NULL
-#define __qcom_hyp_sanitize_link_stack_end NULL
#define __smccc_workaround_1_smc_start NULL
#define __smccc_workaround_1_smc_end NULL
-#define __smccc_workaround_1_hvc_start NULL
-#define __smccc_workaround_1_hvc_end NULL
static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
const char *hyp_vecs_start,
@@ -128,7 +137,7 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
{
__this_cpu_write(bp_hardening_data.fn, fn);
}
-#endif /* CONFIG_KVM */
+#endif /* CONFIG_KVM_INDIRECT_VECTORS */
static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
bp_hardening_cb_t fn,
@@ -161,86 +170,166 @@ static void call_hvc_arch_workaround_1(void)
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}
-static int enable_smccc_arch_workaround_1(void *data)
+static void qcom_link_stack_sanitization(void)
+{
+ u64 tmp;
+
+ asm volatile("mov %0, x30 \n"
+ ".rept 16 \n"
+ "bl . + 4 \n"
+ ".endr \n"
+ "mov x30, %0 \n"
+ : "=&r" (tmp));
+}
+
+static void
+enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
{
- const struct arm64_cpu_capabilities *entry = data;
bp_hardening_cb_t cb;
void *smccc_start, *smccc_end;
struct arm_smccc_res res;
+ u32 midr = read_cpuid_id();
if (!entry->matches(entry, SCOPE_LOCAL_CPU))
- return 0;
+ return;
if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
- return 0;
+ return;
switch (psci_ops.conduit) {
case PSCI_CONDUIT_HVC:
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
if ((int)res.a0 < 0)
- return 0;
+ return;
cb = call_hvc_arch_workaround_1;
- smccc_start = __smccc_workaround_1_hvc_start;
- smccc_end = __smccc_workaround_1_hvc_end;
+ /* This is a guest, no need to patch KVM vectors */
+ smccc_start = NULL;
+ smccc_end = NULL;
break;
case PSCI_CONDUIT_SMC:
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
if ((int)res.a0 < 0)
- return 0;
+ return;
cb = call_smc_arch_workaround_1;
smccc_start = __smccc_workaround_1_smc_start;
smccc_end = __smccc_workaround_1_smc_end;
break;
default:
- return 0;
+ return;
}
+ if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
+ ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
+ cb = qcom_link_stack_sanitization;
+
install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
- return 0;
+ return;
}
+#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
-static void qcom_link_stack_sanitization(void)
+#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
+ .matches = is_affected_midr_range, \
+ .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
+
+#define CAP_MIDR_ALL_VERSIONS(model) \
+ .matches = is_affected_midr_range, \
+ .midr_range = MIDR_ALL_VERSIONS(model)
+
+#define MIDR_FIXED(rev, revidr_mask) \
+ .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
+
+#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+ CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
+
+#define CAP_MIDR_RANGE_LIST(list) \
+ .matches = is_affected_midr_range_list, \
+ .midr_range_list = list
+
+/* Errata affecting a range of revisions of given model variant */
+#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
+ ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
+
+/* Errata affecting a single variant/revision of a model */
+#define ERRATA_MIDR_REV(model, var, rev) \
+ ERRATA_MIDR_RANGE(model, var, rev, var, rev)
+
+/* Errata affecting all variants/revisions of a given a model */
+#define ERRATA_MIDR_ALL_VERSIONS(model) \
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+ CAP_MIDR_ALL_VERSIONS(model)
+
+/* Errata affecting a list of midr ranges, with same work around */
+#define ERRATA_MIDR_RANGE_LIST(midr_list) \
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
+ CAP_MIDR_RANGE_LIST(midr_list)
+
+/*
+ * Generic helper for handling capabilties with multiple (match,enable) pairs
+ * of call backs, sharing the same capability bit.
+ * Iterate over each entry to see if at least one matches.
+ */
+static bool __maybe_unused
+multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
{
- u64 tmp;
+ const struct arm64_cpu_capabilities *caps;
- asm volatile("mov %0, x30 \n"
- ".rept 16 \n"
- "bl . + 4 \n"
- ".endr \n"
- "mov x30, %0 \n"
- : "=&r" (tmp));
+ for (caps = entry->match_list; caps->matches; caps++)
+ if (caps->matches(caps, scope))
+ return true;
+
+ return false;
}
-static int qcom_enable_link_stack_sanitization(void *data)
+/*
+ * Take appropriate action for all matching entries in the shared capability
+ * entry.
+ */
+static void __maybe_unused
+multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
{
- const struct arm64_cpu_capabilities *entry = data;
+ const struct arm64_cpu_capabilities *caps;
- install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
- __qcom_hyp_sanitize_link_stack_start,
- __qcom_hyp_sanitize_link_stack_end);
-
- return 0;
+ for (caps = entry->match_list; caps->matches; caps++)
+ if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
+ caps->cpu_enable)
+ caps->cpu_enable(caps);
}
-#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
-#define MIDR_RANGE(model, min, max) \
- .def_scope = SCOPE_LOCAL_CPU, \
- .matches = is_affected_midr_range, \
- .midr_model = model, \
- .midr_range_min = min, \
- .midr_range_max = max
+#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
-#define MIDR_ALL_VERSIONS(model) \
- .def_scope = SCOPE_LOCAL_CPU, \
- .matches = is_affected_midr_range, \
- .midr_model = model, \
- .midr_range_min = 0, \
- .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
+/*
+ * List of CPUs where we need to issue a psci call to
+ * harden the branch predictor.
+ */
+static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
+ MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
+ MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
+ MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
+ MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
+ {},
+};
+
+#endif
+
+#ifdef CONFIG_HARDEN_EL2_VECTORS
+
+static const struct midr_range arm64_harden_el2_vectors[] = {
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
+ {},
+};
+
+#endif
const struct arm64_cpu_capabilities arm64_errata[] = {
#if defined(CONFIG_ARM64_ERRATUM_826319) || \
@@ -250,8 +339,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[012] */
.desc = "ARM errata 826319, 827319, 824069",
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
- MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
- .enable = cpu_enable_cache_maint_trap,
+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
+ .cpu_enable = cpu_enable_cache_maint_trap,
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_819472
@@ -259,8 +348,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[01] */
.desc = "ARM errata 819472",
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
- MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
- .enable = cpu_enable_cache_maint_trap,
+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
+ .cpu_enable = cpu_enable_cache_maint_trap,
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
@@ -268,9 +357,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 832075",
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
- MIDR_RANGE(MIDR_CORTEX_A57,
- MIDR_CPU_VAR_REV(0, 0),
- MIDR_CPU_VAR_REV(1, 2)),
+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
+ 0, 0,
+ 1, 2),
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_834220
@@ -278,9 +367,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 834220",
.capability = ARM64_WORKAROUND_834220,
- MIDR_RANGE(MIDR_CORTEX_A57,
- MIDR_CPU_VAR_REV(0, 0),
- MIDR_CPU_VAR_REV(1, 2)),
+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
+ 0, 0,
+ 1, 2),
+ },
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_843419
+ {
+ /* Cortex-A53 r0p[01234] */
+ .desc = "ARM erratum 843419",
+ .capability = ARM64_WORKAROUND_843419,
+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
+ MIDR_FIXED(0x4, BIT(8)),
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
@@ -288,7 +386,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A53 r0p[01234] */
.desc = "ARM erratum 845719",
.capability = ARM64_WORKAROUND_845719,
- MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154
@@ -296,7 +394,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cavium ThunderX, pass 1.x */
.desc = "Cavium erratum 23154",
.capability = ARM64_WORKAROUND_CAVIUM_23154,
- MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
+ ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
@@ -304,15 +402,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cavium ThunderX, T88 pass 1.x - 2.1 */
.desc = "Cavium erratum 27456",
.capability = ARM64_WORKAROUND_CAVIUM_27456,
- MIDR_RANGE(MIDR_THUNDERX,
- MIDR_CPU_VAR_REV(0, 0),
- MIDR_CPU_VAR_REV(1, 1)),
+ ERRATA_MIDR_RANGE(MIDR_THUNDERX,
+ 0, 0,
+ 1, 1),
},
{
/* Cavium ThunderX, T81 pass 1.0 */
.desc = "Cavium erratum 27456",
.capability = ARM64_WORKAROUND_CAVIUM_27456,
- MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
+ ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_30115
@@ -320,42 +418,41 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cavium ThunderX, T88 pass 1.x - 2.2 */
.desc = "Cavium erratum 30115",
.capability = ARM64_WORKAROUND_CAVIUM_30115,
- MIDR_RANGE(MIDR_THUNDERX, 0x00,
- (1 << MIDR_VARIANT_SHIFT) | 2),
+ ERRATA_MIDR_RANGE(MIDR_THUNDERX,
+ 0, 0,
+ 1, 2),
},
{
/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
.desc = "Cavium erratum 30115",
.capability = ARM64_WORKAROUND_CAVIUM_30115,
- MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
+ ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
},
{
/* Cavium ThunderX, T83 pass 1.0 */
.desc = "Cavium erratum 30115",
.capability = ARM64_WORKAROUND_CAVIUM_30115,
- MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
+ ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
},
#endif
{
.desc = "Mismatched cache line size",
.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
.matches = has_mismatched_cache_line_size,
- .def_scope = SCOPE_LOCAL_CPU,
- .enable = cpu_enable_trap_ctr_access,
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+ .cpu_enable = cpu_enable_trap_ctr_access,
},
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
{
.desc = "Qualcomm Technologies Falkor erratum 1003",
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
- MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
- MIDR_CPU_VAR_REV(0, 0),
- MIDR_CPU_VAR_REV(0, 0)),
+ ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
},
{
.desc = "Qualcomm Technologies Kryo erratum 1003",
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
- .def_scope = SCOPE_LOCAL_CPU,
- .midr_model = MIDR_QCOM_KRYO,
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+ .midr_range.model = MIDR_QCOM_KRYO,
.matches = is_kryo_midr,
},
#endif
@@ -363,9 +460,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
{
.desc = "Qualcomm Technologies Falkor erratum 1009",
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
- MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
- MIDR_CPU_VAR_REV(0, 0),
- MIDR_CPU_VAR_REV(0, 0)),
+ ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
@@ -373,92 +468,25 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A73 all versions */
.desc = "ARM erratum 858921",
.capability = ARM64_WORKAROUND_858921,
- MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+ ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
},
#endif
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
{
.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
- .enable = enable_smccc_arch_workaround_1,
- },
- {
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
- .enable = enable_smccc_arch_workaround_1,
- },
- {
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
- .enable = enable_smccc_arch_workaround_1,
- },
- {
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
- .enable = enable_smccc_arch_workaround_1,
- },
- {
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
- .enable = qcom_enable_link_stack_sanitization,
- },
- {
- .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
- MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
- },
- {
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
- .enable = qcom_enable_link_stack_sanitization,
- },
- {
- .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
- MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
- },
- {
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
- .enable = enable_smccc_arch_workaround_1,
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+ .cpu_enable = enable_smccc_arch_workaround_1,
+ ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
},
+#endif
+#ifdef CONFIG_HARDEN_EL2_VECTORS
{
- .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
- MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
- .enable = enable_smccc_arch_workaround_1,
+ .desc = "EL2 vector hardening",
+ .capability = ARM64_HARDEN_EL2_VECTORS,
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+ ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
},
#endif
{
}
};
-
-/*
- * The CPU Errata work arounds are detected and applied at boot time
- * and the related information is freed soon after. If the new CPU requires
- * an errata not detected at boot, fail this CPU.
- */
-void verify_local_cpu_errata_workarounds(void)
-{
- const struct arm64_cpu_capabilities *caps = arm64_errata;
-
- for (; caps->matches; caps++) {
- if (cpus_have_cap(caps->capability)) {
- if (caps->enable)
- caps->enable((void *)caps);
- } else if (caps->matches(caps, SCOPE_LOCAL_CPU)) {
- pr_crit("CPU%d: Requires work around for %s, not detected"
- " at boot time\n",
- smp_processor_id(),
- caps->desc ? : "an erratum");
- cpu_die_early();
- }
- }
-}
-
-void update_cpu_errata_workarounds(void)
-{
- update_cpu_capabilities(arm64_errata, "enabling workaround for");
-}
-
-void __init enable_errata_workarounds(void)
-{
- enable_cpu_capabilities(arm64_errata);
-}
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2985a067fc13..536d572e5596 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -123,6 +123,7 @@ cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
* sync with the documentation of the CPU feature register ABI.
*/
static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
@@ -148,6 +149,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
@@ -190,6 +192,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
};
static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
@@ -199,12 +202,12 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
};
static const struct arm64_ftr_bits ftr_ctr[] = {
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
/*
* Linux can handle differing I-cache policies. Userspace JITs will
* make use of *minLine.
@@ -506,6 +509,9 @@ static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
reg->user_mask = user_mask;
}
+extern const struct arm64_cpu_capabilities arm64_errata[];
+static void __init setup_boot_cpu_capabilities(void);
+
void __init init_cpu_features(struct cpuinfo_arm64 *info)
{
/* Before we start using the tables, make sure it is sorted */
@@ -548,6 +554,12 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
sve_init_vq_map();
}
+
+ /*
+ * Detect and enable early CPU capabilities based on the boot CPU,
+ * after we have initialised the CPU feature infrastructure.
+ */
+ setup_boot_cpu_capabilities();
}
static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
@@ -826,40 +838,38 @@ static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int _
MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
}
-static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
+static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
{
- return is_kernel_in_hyp_mode();
+ u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
+
+ return cpuid_feature_extract_signed_field(pfr0,
+ ID_AA64PFR0_FP_SHIFT) < 0;
}
-static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
- int __unused)
+static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
+ int __unused)
{
- phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
-
- /*
- * Activate the lower HYP offset only if:
- * - the idmap doesn't clash with it,
- * - the kernel is not running at EL2.
- */
- return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
+ return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_IDC_SHIFT);
}
-static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
+static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
+ int __unused)
{
- u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
-
- return cpuid_feature_extract_signed_field(pfr0,
- ID_AA64PFR0_FP_SHIFT) < 0;
+ return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_DIC_SHIFT);
}
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
- int __unused)
+ int scope)
{
+ /* List of CPUs that are not vulnerable and don't need KPTI */
+ static const struct midr_range kpti_safe_list[] = {
+ MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
+ MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
+ };
char const *str = "command line option";
- u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
/*
* For reasons that aren't entirely clear, enabling KPTI on Cavium
@@ -883,18 +893,15 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
return true;
/* Don't force KPTI for CPUs that are not vulnerable */
- switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
- case MIDR_CAVIUM_THUNDERX2:
- case MIDR_BRCM_VULCAN:
+ if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
return false;
- }
/* Defer to CPU feature registers */
- return !cpuid_feature_extract_unsigned_field(pfr0,
- ID_AA64PFR0_CSV3_SHIFT);
+ return !has_cpuid_feature(entry, scope);
}
-static int kpti_install_ng_mappings(void *__unused)
+static void
+kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
{
typedef void (kpti_remap_fn)(int, int, phys_addr_t);
extern kpti_remap_fn idmap_kpti_install_ng_mappings;
@@ -904,7 +911,7 @@ static int kpti_install_ng_mappings(void *__unused)
int cpu = smp_processor_id();
if (kpti_applied)
- return 0;
+ return;
remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
@@ -915,7 +922,7 @@ static int kpti_install_ng_mappings(void *__unused)
if (!cpu)
kpti_applied = true;
- return 0;
+ return;
}
static int __init parse_kpti(char *str)
@@ -932,7 +939,78 @@ static int __init parse_kpti(char *str)
__setup("kpti=", parse_kpti);
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
-static int cpu_copy_el2regs(void *__unused)
+#ifdef CONFIG_ARM64_HW_AFDBM
+static inline void __cpu_enable_hw_dbm(void)
+{
+ u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
+
+ write_sysreg(tcr, tcr_el1);
+ isb();
+}
+
+static bool cpu_has_broken_dbm(void)
+{
+ /* List of CPUs which have broken DBM support. */
+ static const struct midr_range cpus[] = {
+#ifdef CONFIG_ARM64_ERRATUM_1024718
+ MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+#endif
+ {},
+ };
+
+ return is_midr_in_range_list(read_cpuid_id(), cpus);
+}
+
+static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
+{
+ return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
+ !cpu_has_broken_dbm();
+}
+
+static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
+{
+ if (cpu_can_use_dbm(cap))
+ __cpu_enable_hw_dbm();
+}
+
+static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
+ int __unused)
+{
+ static bool detected = false;
+ /*
+ * DBM is a non-conflicting feature. i.e, the kernel can safely
+ * run a mix of CPUs with and without the feature. So, we
+ * unconditionally enable the capability to allow any late CPU
+ * to use the feature. We only enable the control bits on the
+ * CPU, if it actually supports.
+ *
+ * We have to make sure we print the "feature" detection only
+ * when at least one CPU actually uses it. So check if this CPU
+ * can actually use it and print the message exactly once.
+ *
+ * This is safe as all CPUs (including secondary CPUs - due to the
+ * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
+ * goes through the "matches" check exactly once. Also if a CPU
+ * matches the criteria, it is guaranteed that the CPU will turn
+ * the DBM on, as the capability is unconditionally enabled.
+ */
+ if (!detected && cpu_can_use_dbm(cap)) {
+ detected = true;
+ pr_info("detected: Hardware dirty bit management\n");
+ }
+
+ return true;
+}
+
+#endif
+
+#ifdef CONFIG_ARM64_VHE
+static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
+{
+ return is_kernel_in_hyp_mode();
+}
+
+static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
{
/*
* Copy register values that aren't redirected by hardware.
@@ -944,15 +1022,14 @@ static int cpu_copy_el2regs(void *__unused)
*/
if (!alternatives_applied)
write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
-
- return 0;
}
+#endif
static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "GIC system register CPU interface",
.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_useable_gicv3_cpuif,
.sys_reg = SYS_ID_AA64PFR0_EL1,
.field_pos = ID_AA64PFR0_GIC_SHIFT,
@@ -963,20 +1040,20 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "Privileged Access Never",
.capability = ARM64_HAS_PAN,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64MMFR1_EL1,
.field_pos = ID_AA64MMFR1_PAN_SHIFT,
.sign = FTR_UNSIGNED,
.min_field_value = 1,
- .enable = cpu_enable_pan,
+ .cpu_enable = cpu_enable_pan,
},
#endif /* CONFIG_ARM64_PAN */
#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
{
.desc = "LSE atomic instructions",
.capability = ARM64_HAS_LSE_ATOMICS,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64ISAR0_EL1,
.field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
@@ -987,14 +1064,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "Software prefetching using PRFM",
.capability = ARM64_HAS_NO_HW_PREFETCH,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
.matches = has_no_hw_prefetch,
},
#ifdef CONFIG_ARM64_UAO
{
.desc = "User Access Override",
.capability = ARM64_HAS_UAO,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64MMFR2_EL1,
.field_pos = ID_AA64MMFR2_UAO_SHIFT,
@@ -1008,46 +1085,50 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
#ifdef CONFIG_ARM64_PAN
{
.capability = ARM64_ALT_PAN_NOT_UAO,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = cpufeature_pan_not_uao,
},
#endif /* CONFIG_ARM64_PAN */
+#ifdef CONFIG_ARM64_VHE
{
.desc = "Virtualization Host Extensions",
.capability = ARM64_HAS_VIRT_HOST_EXTN,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
.matches = runs_at_el2,
- .enable = cpu_copy_el2regs,
+ .cpu_enable = cpu_copy_el2regs,
},
+#endif /* CONFIG_ARM64_VHE */
{
.desc = "32-bit EL0 Support",
.capability = ARM64_HAS_32BIT_EL0,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64PFR0_EL1,
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64PFR0_EL0_SHIFT,
.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
},
- {
- .desc = "Reduced HYP mapping offset",
- .capability = ARM64_HYP_OFFSET_LOW,
- .def_scope = SCOPE_SYSTEM,
- .matches = hyp_offset_low,
- },
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
{
.desc = "Kernel page table isolation (KPTI)",
.capability = ARM64_UNMAP_KERNEL_AT_EL0,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
+ /*
+ * The ID feature fields below are used to indicate that
+ * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
+ * more details.
+ */
+ .sys_reg = SYS_ID_AA64PFR0_EL1,
+ .field_pos = ID_AA64PFR0_CSV3_SHIFT,
+ .min_field_value = 1,
.matches = unmap_kernel_at_el0,
- .enable = kpti_install_ng_mappings,
+ .cpu_enable = kpti_install_ng_mappings,
},
#endif
{
/* FP/SIMD is not implemented */
.capability = ARM64_HAS_NO_FPSIMD,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.min_field_value = 0,
.matches = has_no_fpsimd,
},
@@ -1055,7 +1136,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "Data cache clean to Point of Persistence",
.capability = ARM64_HAS_DCPOP,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.field_pos = ID_AA64ISAR1_DPB_SHIFT,
@@ -1065,42 +1146,74 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
#ifdef CONFIG_ARM64_SVE
{
.desc = "Scalable Vector Extension",
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.capability = ARM64_SVE,
- .def_scope = SCOPE_SYSTEM,
.sys_reg = SYS_ID_AA64PFR0_EL1,
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64PFR0_SVE_SHIFT,
.min_field_value = ID_AA64PFR0_SVE,
.matches = has_cpuid_feature,
- .enable = sve_kernel_enable,
+ .cpu_enable = sve_kernel_enable,
},
#endif /* CONFIG_ARM64_SVE */
#ifdef CONFIG_ARM64_RAS_EXTN
{
.desc = "RAS Extension Support",
.capability = ARM64_HAS_RAS_EXTN,
- .def_scope = SCOPE_SYSTEM,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64PFR0_EL1,
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64PFR0_RAS_SHIFT,
.min_field_value = ID_AA64PFR0_RAS_V1,
- .enable = cpu_clear_disr,
+ .cpu_enable = cpu_clear_disr,
},
#endif /* CONFIG_ARM64_RAS_EXTN */
+ {
+ .desc = "Data cache clean to the PoU not required for I/D coherence",
+ .capability = ARM64_HAS_CACHE_IDC,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cache_idc,
+ },
+ {
+ .desc = "Instruction cache invalidation not required for I/D coherence",
+ .capability = ARM64_HAS_CACHE_DIC,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cache_dic,
+ },
+#ifdef CONFIG_ARM64_HW_AFDBM
+ {
+ /*
+ * Since we turn this on always, we don't want the user to
+ * think that the feature is available when it may not be.
+ * So hide the description.
+ *
+ * .desc = "Hardware pagetable Dirty Bit Management",
+ *
+ */
+ .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
+ .capability = ARM64_HW_DBM,
+ .sys_reg = SYS_ID_AA64MMFR1_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
+ .min_field_value = 2,
+ .matches = has_hw_dbm,
+ .cpu_enable = cpu_enable_hw_dbm,
+ },
+#endif
{},
};
-#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
+#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
{ \
.desc = #cap, \
- .def_scope = SCOPE_SYSTEM, \
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
.matches = has_cpuid_feature, \
.sys_reg = reg, \
.field_pos = field, \
.sign = s, \
.min_field_value = min_value, \
- .hwcap_type = type, \
+ .hwcap_type = cap_type, \
.hwcap = cap, \
}
@@ -1118,14 +1231,18 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
+ HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
+ HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
+ HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
#ifdef CONFIG_ARM64_SVE
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
#endif
@@ -1193,7 +1310,7 @@ static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
/* We support emulation of accesses to CPU ID feature registers */
elf_hwcap |= HWCAP_CPUID;
for (; hwcaps->matches; hwcaps++)
- if (hwcaps->matches(hwcaps, hwcaps->def_scope))
+ if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
cap_set_elf_hwcap(hwcaps);
}
@@ -1210,17 +1327,19 @@ static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
return false;
for (caps = cap_array; caps->matches; caps++)
- if (caps->capability == cap &&
- caps->matches(caps, SCOPE_LOCAL_CPU))
- return true;
+ if (caps->capability == cap)
+ return caps->matches(caps, SCOPE_LOCAL_CPU);
+
return false;
}
-void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
- const char *info)
+static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
+ u16 scope_mask, const char *info)
{
+ scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
for (; caps->matches; caps++) {
- if (!caps->matches(caps, caps->def_scope))
+ if (!(caps->type & scope_mask) ||
+ !caps->matches(caps, cpucap_default_scope(caps)))
continue;
if (!cpus_have_cap(caps->capability) && caps->desc)
@@ -1229,41 +1348,145 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
}
}
+static void update_cpu_capabilities(u16 scope_mask)
+{
+ __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
+ __update_cpu_capabilities(arm64_errata, scope_mask,
+ "enabling workaround for");
+}
+
+static int __enable_cpu_capability(void *arg)
+{
+ const struct arm64_cpu_capabilities *cap = arg;
+
+ cap->cpu_enable(cap);
+ return 0;
+}
+
/*
* Run through the enabled capabilities and enable() it on all active
* CPUs
*/
-void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
+static void __init
+__enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
+ u16 scope_mask)
{
+ scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
for (; caps->matches; caps++) {
unsigned int num = caps->capability;
- if (!cpus_have_cap(num))
+ if (!(caps->type & scope_mask) || !cpus_have_cap(num))
continue;
/* Ensure cpus_have_const_cap(num) works */
static_branch_enable(&cpu_hwcap_keys[num]);
- if (caps->enable) {
+ if (caps->cpu_enable) {
/*
- * Use stop_machine() as it schedules the work allowing
- * us to modify PSTATE, instead of on_each_cpu() which
- * uses an IPI, giving us a PSTATE that disappears when
- * we return.
+ * Capabilities with SCOPE_BOOT_CPU scope are finalised
+ * before any secondary CPU boots. Thus, each secondary
+ * will enable the capability as appropriate via
+ * check_local_cpu_capabilities(). The only exception is
+ * the boot CPU, for which the capability must be
+ * enabled here. This approach avoids costly
+ * stop_machine() calls for this case.
+ *
+ * Otherwise, use stop_machine() as it schedules the
+ * work allowing us to modify PSTATE, instead of
+ * on_each_cpu() which uses an IPI, giving us a PSTATE
+ * that disappears when we return.
*/
- stop_machine(caps->enable, (void *)caps, cpu_online_mask);
+ if (scope_mask & SCOPE_BOOT_CPU)
+ caps->cpu_enable(caps);
+ else
+ stop_machine(__enable_cpu_capability,
+ (void *)caps, cpu_online_mask);
}
}
}
+static void __init enable_cpu_capabilities(u16 scope_mask)
+{
+ __enable_cpu_capabilities(arm64_features, scope_mask);
+ __enable_cpu_capabilities(arm64_errata, scope_mask);
+}
+
+/*
+ * Run through the list of capabilities to check for conflicts.
+ * If the system has already detected a capability, take necessary
+ * action on this CPU.
+ *
+ * Returns "false" on conflicts.
+ */
+static bool
+__verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
+ u16 scope_mask)
+{
+ bool cpu_has_cap, system_has_cap;
+
+ scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
+
+ for (; caps->matches; caps++) {
+ if (!(caps->type & scope_mask))
+ continue;
+
+ cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
+ system_has_cap = cpus_have_cap(caps->capability);
+
+ if (system_has_cap) {
+ /*
+ * Check if the new CPU misses an advertised feature,
+ * which is not safe to miss.
+ */
+ if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
+ break;
+ /*
+ * We have to issue cpu_enable() irrespective of
+ * whether the CPU has it or not, as it is enabeld
+ * system wide. It is upto the call back to take
+ * appropriate action on this CPU.
+ */
+ if (caps->cpu_enable)
+ caps->cpu_enable(caps);
+ } else {
+ /*
+ * Check if the CPU has this capability if it isn't
+ * safe to have when the system doesn't.
+ */
+ if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
+ break;
+ }
+ }
+
+ if (caps->matches) {
+ pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
+ smp_processor_id(), caps->capability,
+ caps->desc, system_has_cap, cpu_has_cap);
+ return false;
+ }
+
+ return true;
+}
+
+static bool verify_local_cpu_caps(u16 scope_mask)
+{
+ return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
+ __verify_local_cpu_caps(arm64_features, scope_mask);
+}
+
/*
* Check for CPU features that are used in early boot
* based on the Boot CPU value.
*/
static void check_early_cpu_features(void)
{
- verify_cpu_run_el();
verify_cpu_asid_bits();
+ /*
+ * Early features are used by the kernel already. If there
+ * is a conflict, we cannot proceed further.
+ */
+ if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
+ cpu_panic_kernel();
}
static void
@@ -1278,27 +1501,6 @@ verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
}
}
-static void
-verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list)
-{
- const struct arm64_cpu_capabilities *caps = caps_list;
- for (; caps->matches; caps++) {
- if (!cpus_have_cap(caps->capability))
- continue;
- /*
- * If the new CPU misses an advertised feature, we cannot proceed
- * further, park the cpu.
- */
- if (!__this_cpu_has_cap(caps_list, caps->capability)) {
- pr_crit("CPU%d: missing feature: %s\n",
- smp_processor_id(), caps->desc);
- cpu_die_early();
- }
- if (caps->enable)
- caps->enable((void *)caps);
- }
-}
-
static void verify_sve_features(void)
{
u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
@@ -1316,6 +1518,7 @@ static void verify_sve_features(void)
/* Add checks on other ZCR bits here if necessary */
}
+
/*
* Run through the enabled system capabilities and enable() it on this CPU.
* The capabilities were decided based on the available CPUs at the boot time.
@@ -1326,8 +1529,14 @@ static void verify_sve_features(void)
*/
static void verify_local_cpu_capabilities(void)
{
- verify_local_cpu_errata_workarounds();
- verify_local_cpu_features(arm64_features);
+ /*
+ * The capabilities with SCOPE_BOOT_CPU are checked from
+ * check_early_cpu_features(), as they need to be verified
+ * on all secondary CPUs.
+ */
+ if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
+ cpu_die_early();
+
verify_local_elf_hwcaps(arm64_elf_hwcaps);
if (system_supports_32bit_el0())
@@ -1335,9 +1544,6 @@ static void verify_local_cpu_capabilities(void)
if (system_supports_sve())
verify_sve_features();
-
- if (system_uses_ttbr0_pan())
- pr_info("Emulating Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
}
void check_local_cpu_capabilities(void)
@@ -1350,20 +1556,22 @@ void check_local_cpu_capabilities(void)
/*
* If we haven't finalised the system capabilities, this CPU gets
- * a chance to update the errata work arounds.
+ * a chance to update the errata work arounds and local features.
* Otherwise, this CPU should verify that it has all the system
* advertised capabilities.
*/
if (!sys_caps_initialised)
- update_cpu_errata_workarounds();
+ update_cpu_capabilities(SCOPE_LOCAL_CPU);
else
verify_local_cpu_capabilities();
}
-static void __init setup_feature_capabilities(void)
+static void __init setup_boot_cpu_capabilities(void)
{
- update_cpu_capabilities(arm64_features, "detected feature:");
- enable_cpu_capabilities(arm64_features);
+ /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
+ update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
+ /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
+ enable_cpu_capabilities(SCOPE_BOOT_CPU);
}
DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
@@ -1382,20 +1590,33 @@ bool this_cpu_has_cap(unsigned int cap)
__this_cpu_has_cap(arm64_errata, cap));
}
+static void __init setup_system_capabilities(void)
+{
+ /*
+ * We have finalised the system-wide safe feature
+ * registers, finalise the capabilities that depend
+ * on it. Also enable all the available capabilities,
+ * that are not enabled already.
+ */
+ update_cpu_capabilities(SCOPE_SYSTEM);
+ enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
+}
+
void __init setup_cpu_features(void)
{
u32 cwg;
int cls;
- /* Set the CPU feature capabilies */
- setup_feature_capabilities();
- enable_errata_workarounds();
+ setup_system_capabilities();
mark_const_caps_ready();
setup_elf_hwcaps(arm64_elf_hwcaps);
if (system_supports_32bit_el0())
setup_elf_hwcaps(compat_elf_hwcaps);
+ if (system_uses_ttbr0_pan())
+ pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
+
sve_setup();
/* Advertise that we have computed the system capabilities */
@@ -1518,10 +1739,8 @@ static int __init enable_mrs_emulation(void)
core_initcall(enable_mrs_emulation);
-int cpu_clear_disr(void *__unused)
+void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
{
/* Firmware may have left a deferred SError in this register. */
write_sysreg_s(0, SYS_DISR_EL1);
-
- return 0;
}
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 7f94623df8a5..e9ab7b3ed317 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -77,6 +77,10 @@ static const char *const hwcap_str[] = {
"sha512",
"sve",
"asimdfhm",
+ "dit",
+ "uscat",
+ "ilrcpc",
+ "flagm",
NULL
};
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 53781f5687c5..06ca574495af 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -33,6 +33,7 @@
#include <asm/daifflags.h>
#include <asm/debug-monitors.h>
#include <asm/system_misc.h>
+#include <asm/traps.h>
/* Determine debug architecture. */
u8 debug_monitors_arch(void)
@@ -223,7 +224,7 @@ static void send_user_sigtrap(int si_code)
if (interrupts_enabled(regs))
local_irq_enable();
- force_sig_info(SIGTRAP, &info, current);
+ arm64_force_sig_info(&info, "User debug trap", current);
}
static int single_step_handler(unsigned long addr, unsigned int esr,
diff --git a/arch/arm64/kernel/efi-rt-wrapper.S b/arch/arm64/kernel/efi-rt-wrapper.S
new file mode 100644
index 000000000000..05235ebb336d
--- /dev/null
+++ b/arch/arm64/kernel/efi-rt-wrapper.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(__efi_rt_asm_wrapper)
+ stp x29, x30, [sp, #-32]!
+ mov x29, sp
+
+ /*
+ * Register x18 is designated as the 'platform' register by the AAPCS,
+ * which means firmware running at the same exception level as the OS
+ * (such as UEFI) should never touch it.
+ */
+ stp x1, x18, [sp, #16]
+
+ /*
+ * We are lucky enough that no EFI runtime services take more than
+ * 5 arguments, so all are passed in registers rather than via the
+ * stack.
+ */
+ mov x8, x0
+ mov x0, x2
+ mov x1, x3
+ mov x2, x4
+ mov x3, x5
+ mov x4, x6
+ blr x8
+
+ ldp x1, x2, [sp, #16]
+ cmp x2, x18
+ ldp x29, x30, [sp], #32
+ b.ne 0f
+ ret
+0: b efi_handle_corrupted_x18 // tail call
+ENDPROC(__efi_rt_asm_wrapper)
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
index a8bf1c892b90..4f9acb5fbe97 100644
--- a/arch/arm64/kernel/efi.c
+++ b/arch/arm64/kernel/efi.c
@@ -126,3 +126,9 @@ bool efi_poweroff_required(void)
{
return efi_enabled(EFI_RUNTIME_SERVICES);
}
+
+asmlinkage efi_status_t efi_handle_corrupted_x18(efi_status_t s, const char *f)
+{
+ pr_err_ratelimited(FW_BUG "register x18 corrupted by EFI %s\n", f);
+ return s;
+}
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index e7226c4c7493..87a35364e750 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -39,7 +39,9 @@
#include <linux/slab.h>
#include <linux/sysctl.h>
+#include <asm/esr.h>
#include <asm/fpsimd.h>
+#include <asm/cpufeature.h>
#include <asm/cputype.h>
#include <asm/simd.h>
#include <asm/sigcontext.h>
@@ -64,7 +66,7 @@
* been loaded into its FPSIMD registers most recently, or whether it has
* been used to perform kernel mode NEON in the meantime.
*
- * For (a), we add a 'cpu' field to struct fpsimd_state, which gets updated to
+ * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to
* the id of the current CPU every time the state is loaded onto a CPU. For (b),
* we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
* address of the userland FPSIMD state of the task that was loaded onto the CPU
@@ -73,7 +75,7 @@
* With this in place, we no longer have to restore the next FPSIMD state right
* when switching between tasks. Instead, we can defer this check to userland
* resume, at which time we verify whether the CPU's fpsimd_last_state and the
- * task's fpsimd_state.cpu are still mutually in sync. If this is the case, we
+ * task's fpsimd_cpu are still mutually in sync. If this is the case, we
* can omit the FPSIMD restore.
*
* As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to
@@ -90,14 +92,14 @@
* flag with local_bh_disable() unless softirqs are already masked.
*
* For a certain task, the sequence may look something like this:
- * - the task gets scheduled in; if both the task's fpsimd_state.cpu field
+ * - the task gets scheduled in; if both the task's fpsimd_cpu field
* contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
* variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is
* cleared, otherwise it is set;
*
* - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
* userland FPSIMD state is copied from memory to the registers, the task's
- * fpsimd_state.cpu field is set to the id of the current CPU, the current
+ * fpsimd_cpu field is set to the id of the current CPU, the current
* CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the
* TIF_FOREIGN_FPSTATE flag is cleared;
*
@@ -115,7 +117,7 @@
* whatever is in the FPSIMD registers is not saved to memory, but discarded.
*/
struct fpsimd_last_state_struct {
- struct fpsimd_state *st;
+ struct user_fpsimd_state *st;
bool sve_in_use;
};
@@ -222,7 +224,7 @@ static void sve_user_enable(void)
* sets TIF_SVE.
*
* When stored, FPSIMD registers V0-V31 are encoded in
- * task->fpsimd_state; bits [max : 128] for each of Z0-Z31 are
+ * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are
* logically zero but not stored anywhere; P0-P15 and FFR are not
* stored and have unspecified values from userspace's point of
* view. For hygiene purposes, the kernel zeroes them on next use,
@@ -231,9 +233,9 @@ static void sve_user_enable(void)
* task->thread.sve_state does not need to be non-NULL, valid or any
* particular size: it must not be dereferenced.
*
- * * FPSR and FPCR are always stored in task->fpsimd_state irrespctive of
- * whether TIF_SVE is clear or set, since these are not vector length
- * dependent.
+ * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state
+ * irrespective of whether TIF_SVE is clear or set, since these are
+ * not vector length dependent.
*/
/*
@@ -251,10 +253,10 @@ static void task_fpsimd_load(void)
if (system_supports_sve() && test_thread_flag(TIF_SVE))
sve_load_state(sve_pffr(current),
- &current->thread.fpsimd_state.fpsr,
+ &current->thread.uw.fpsimd_state.fpsr,
sve_vq_from_vl(current->thread.sve_vl) - 1);
else
- fpsimd_load_state(&current->thread.fpsimd_state);
+ fpsimd_load_state(&current->thread.uw.fpsimd_state);
if (system_supports_sve()) {
/* Toggle SVE trapping for userspace if needed */
@@ -285,15 +287,14 @@ static void task_fpsimd_save(void)
* re-enter user with corrupt state.
* There's no way to recover, so kill it:
*/
- force_signal_inject(
- SIGKILL, 0, current_pt_regs(), 0);
+ force_signal_inject(SIGKILL, SI_KERNEL, 0);
return;
}
sve_save_state(sve_pffr(current),
- &current->thread.fpsimd_state.fpsr);
+ &current->thread.uw.fpsimd_state.fpsr);
} else
- fpsimd_save_state(&current->thread.fpsimd_state);
+ fpsimd_save_state(&current->thread.uw.fpsimd_state);
}
}
@@ -404,20 +405,21 @@ static int __init sve_sysctl_init(void) { return 0; }
(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
/*
- * Transfer the FPSIMD state in task->thread.fpsimd_state to
+ * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
* task->thread.sve_state.
*
* Task can be a non-runnable task, or current. In the latter case,
* softirqs (and preemption) must be disabled.
* task->thread.sve_state must point to at least sve_state_size(task)
* bytes of allocated kernel memory.
- * task->thread.fpsimd_state must be up to date before calling this function.
+ * task->thread.uw.fpsimd_state must be up to date before calling this
+ * function.
*/
static void fpsimd_to_sve(struct task_struct *task)
{
unsigned int vq;
void *sst = task->thread.sve_state;
- struct fpsimd_state const *fst = &task->thread.fpsimd_state;
+ struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
unsigned int i;
if (!system_supports_sve())
@@ -431,7 +433,7 @@ static void fpsimd_to_sve(struct task_struct *task)
/*
* Transfer the SVE state in task->thread.sve_state to
- * task->thread.fpsimd_state.
+ * task->thread.uw.fpsimd_state.
*
* Task can be a non-runnable task, or current. In the latter case,
* softirqs (and preemption) must be disabled.
@@ -443,7 +445,7 @@ static void sve_to_fpsimd(struct task_struct *task)
{
unsigned int vq;
void const *sst = task->thread.sve_state;
- struct fpsimd_state *fst = &task->thread.fpsimd_state;
+ struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
unsigned int i;
if (!system_supports_sve())
@@ -510,7 +512,7 @@ void fpsimd_sync_to_sve(struct task_struct *task)
}
/*
- * Ensure that task->thread.fpsimd_state is up to date with respect to
+ * Ensure that task->thread.uw.fpsimd_state is up to date with respect to
* the user task, irrespective of whether SVE is in use or not.
*
* This should only be called by ptrace. task must be non-runnable.
@@ -525,21 +527,21 @@ void sve_sync_to_fpsimd(struct task_struct *task)
/*
* Ensure that task->thread.sve_state is up to date with respect to
- * the task->thread.fpsimd_state.
+ * the task->thread.uw.fpsimd_state.
*
* This should only be called by ptrace to merge new FPSIMD register
* values into a task for which SVE is currently active.
* task must be non-runnable.
* task->thread.sve_state must point to at least sve_state_size(task)
* bytes of allocated kernel memory.
- * task->thread.fpsimd_state must already have been initialised with
+ * task->thread.uw.fpsimd_state must already have been initialised with
* the new FPSIMD register values to be merged in.
*/
void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
{
unsigned int vq;
void *sst = task->thread.sve_state;
- struct fpsimd_state const *fst = &task->thread.fpsimd_state;
+ struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
unsigned int i;
if (!test_tsk_thread_flag(task, TIF_SVE))
@@ -757,12 +759,10 @@ fail:
* Enable SVE for EL1.
* Intended for use by the cpufeatures code during CPU boot.
*/
-int sve_kernel_enable(void *__always_unused p)
+void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
{
write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
isb();
-
- return 0;
}
void __init sve_setup(void)
@@ -831,7 +831,7 @@ asmlinkage void do_sve_acc(unsigned int esr, struct pt_regs *regs)
{
/* Even if we chose not to use SVE, the hardware could still trap: */
if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) {
- force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
+ force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
return;
}
@@ -867,18 +867,20 @@ asmlinkage void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs)
asmlinkage void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs)
{
siginfo_t info;
- unsigned int si_code = FPE_FIXME;
-
- if (esr & FPEXC_IOF)
- si_code = FPE_FLTINV;
- else if (esr & FPEXC_DZF)
- si_code = FPE_FLTDIV;
- else if (esr & FPEXC_OFF)
- si_code = FPE_FLTOVF;
- else if (esr & FPEXC_UFF)
- si_code = FPE_FLTUND;
- else if (esr & FPEXC_IXF)
- si_code = FPE_FLTRES;
+ unsigned int si_code = FPE_FLTUNK;
+
+ if (esr & ESR_ELx_FP_EXC_TFV) {
+ if (esr & FPEXC_IOF)
+ si_code = FPE_FLTINV;
+ else if (esr & FPEXC_DZF)
+ si_code = FPE_FLTDIV;
+ else if (esr & FPEXC_OFF)
+ si_code = FPE_FLTOVF;
+ else if (esr & FPEXC_UFF)
+ si_code = FPE_FLTUND;
+ else if (esr & FPEXC_IXF)
+ si_code = FPE_FLTRES;
+ }
memset(&info, 0, sizeof(info));
info.si_signo = SIGFPE;
@@ -908,10 +910,9 @@ void fpsimd_thread_switch(struct task_struct *next)
* the TIF_FOREIGN_FPSTATE flag so the state will be loaded
* upon the next return to userland.
*/
- struct fpsimd_state *st = &next->thread.fpsimd_state;
-
- if (__this_cpu_read(fpsimd_last_state.st) == st
- && st->cpu == smp_processor_id())
+ if (__this_cpu_read(fpsimd_last_state.st) ==
+ &next->thread.uw.fpsimd_state
+ && next->thread.fpsimd_cpu == smp_processor_id())
clear_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE);
else
set_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE);
@@ -927,7 +928,8 @@ void fpsimd_flush_thread(void)
local_bh_disable();
- memset(&current->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
+ memset(&current->thread.uw.fpsimd_state, 0,
+ sizeof(current->thread.uw.fpsimd_state));
fpsimd_flush_task_state(current);
if (system_supports_sve()) {
@@ -986,7 +988,7 @@ void fpsimd_preserve_current_state(void)
/*
* Like fpsimd_preserve_current_state(), but ensure that
- * current->thread.fpsimd_state is updated so that it can be copied to
+ * current->thread.uw.fpsimd_state is updated so that it can be copied to
* the signal frame.
*/
void fpsimd_signal_preserve_current_state(void)
@@ -1004,11 +1006,10 @@ static void fpsimd_bind_to_cpu(void)
{
struct fpsimd_last_state_struct *last =
this_cpu_ptr(&fpsimd_last_state);
- struct fpsimd_state *st = &current->thread.fpsimd_state;
- last->st = st;
+ last->st = &current->thread.uw.fpsimd_state;
last->sve_in_use = test_thread_flag(TIF_SVE);
- st->cpu = smp_processor_id();
+ current->thread.fpsimd_cpu = smp_processor_id();
}
/*
@@ -1043,7 +1044,7 @@ void fpsimd_update_current_state(struct user_fpsimd_state const *state)
local_bh_disable();
- current->thread.fpsimd_state.user_fpsimd = *state;
+ current->thread.uw.fpsimd_state = *state;
if (system_supports_sve() && test_thread_flag(TIF_SVE))
fpsimd_to_sve(current);
@@ -1060,7 +1061,7 @@ void fpsimd_update_current_state(struct user_fpsimd_state const *state)
*/
void fpsimd_flush_task_state(struct task_struct *t)
{
- t->thread.fpsimd_state.cpu = NR_CPUS;
+ t->thread.fpsimd_cpu = NR_CPUS;
}
static inline void fpsimd_flush_cpu_state(void)
@@ -1159,7 +1160,7 @@ EXPORT_SYMBOL(kernel_neon_end);
#ifdef CONFIG_EFI
-static DEFINE_PER_CPU(struct fpsimd_state, efi_fpsimd_state);
+static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state);
static DEFINE_PER_CPU(bool, efi_fpsimd_state_used);
static DEFINE_PER_CPU(bool, efi_sve_state_used);
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 2b6b8b24e5ab..b0853069702f 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -577,6 +577,13 @@ set_hcr:
7:
msr mdcr_el2, x3 // Configure debug traps
+ /* LORegions */
+ mrs x1, id_aa64mmfr1_el1
+ ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
+ cbz x0, 1f
+ msr_s SYS_LORC_EL1, xzr
+1:
+
/* Stage-2 translation */
msr vttbr_el2, xzr
diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h
index c7fcb232fe47..a820ed07fb80 100644
--- a/arch/arm64/kernel/image.h
+++ b/arch/arm64/kernel/image.h
@@ -103,6 +103,7 @@ __efistub_strlen = KALLSYMS_HIDE(__pi_strlen);
__efistub_strnlen = KALLSYMS_HIDE(__pi_strnlen);
__efistub_strcmp = KALLSYMS_HIDE(__pi_strcmp);
__efistub_strncmp = KALLSYMS_HIDE(__pi_strncmp);
+__efistub_strrchr = KALLSYMS_HIDE(__pi_strrchr);
__efistub___flush_dcache_area = KALLSYMS_HIDE(__pi___flush_dcache_area);
#ifdef CONFIG_KASAN
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 2718a77da165..816d03c4c913 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -35,6 +35,7 @@
#define AARCH64_INSN_SF_BIT BIT(31)
#define AARCH64_INSN_N_BIT BIT(22)
+#define AARCH64_INSN_LSL_12 BIT(22)
static int aarch64_insn_encoding_class[] = {
AARCH64_INSN_CLS_UNKNOWN,
@@ -343,6 +344,10 @@ static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
mask = BIT(6) - 1;
shift = 16;
break;
+ case AARCH64_INSN_IMM_N:
+ mask = 1;
+ shift = 22;
+ break;
default:
return -EINVAL;
}
@@ -899,9 +904,18 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
return AARCH64_BREAK_FAULT;
}
+ /* We can't encode more than a 24bit value (12bit + 12bit shift) */
+ if (imm & ~(BIT(24) - 1))
+ goto out;
+
+ /* If we have something in the top 12 bits... */
if (imm & ~(SZ_4K - 1)) {
- pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
- return AARCH64_BREAK_FAULT;
+ /* ... and in the low 12 bits -> error */
+ if (imm & (SZ_4K - 1))
+ goto out;
+
+ imm >>= 12;
+ insn |= AARCH64_INSN_LSL_12;
}
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
@@ -909,6 +923,10 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
+
+out:
+ pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
+ return AARCH64_BREAK_FAULT;
}
u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
@@ -1481,3 +1499,171 @@ pstate_check_t * const aarch32_opcode_cond_checks[16] = {
__check_hi, __check_ls, __check_ge, __check_lt,
__check_gt, __check_le, __check_al, __check_al
};
+
+static bool range_of_ones(u64 val)
+{
+ /* Doesn't handle full ones or full zeroes */
+ u64 sval = val >> __ffs64(val);
+
+ /* One of Sean Eron Anderson's bithack tricks */
+ return ((sval + 1) & (sval)) == 0;
+}
+
+static u32 aarch64_encode_immediate(u64 imm,
+ enum aarch64_insn_variant variant,
+ u32 insn)
+{
+ unsigned int immr, imms, n, ones, ror, esz, tmp;
+ u64 mask = ~0UL;
+
+ /* Can't encode full zeroes or full ones */
+ if (!imm || !~imm)
+ return AARCH64_BREAK_FAULT;
+
+ switch (variant) {
+ case AARCH64_INSN_VARIANT_32BIT:
+ if (upper_32_bits(imm))
+ return AARCH64_BREAK_FAULT;
+ esz = 32;
+ break;
+ case AARCH64_INSN_VARIANT_64BIT:
+ insn |= AARCH64_INSN_SF_BIT;
+ esz = 64;
+ break;
+ default:
+ pr_err("%s: unknown variant encoding %d\n", __func__, variant);
+ return AARCH64_BREAK_FAULT;
+ }
+
+ /*
+ * Inverse of Replicate(). Try to spot a repeating pattern
+ * with a pow2 stride.
+ */
+ for (tmp = esz / 2; tmp >= 2; tmp /= 2) {
+ u64 emask = BIT(tmp) - 1;
+
+ if ((imm & emask) != ((imm >> tmp) & emask))
+ break;
+
+ esz = tmp;
+ mask = emask;
+ }
+
+ /* N is only set if we're encoding a 64bit value */
+ n = esz == 64;
+
+ /* Trim imm to the element size */
+ imm &= mask;
+
+ /* That's how many ones we need to encode */
+ ones = hweight64(imm);
+
+ /*
+ * imms is set to (ones - 1), prefixed with a string of ones
+ * and a zero if they fit. Cap it to 6 bits.
+ */
+ imms = ones - 1;
+ imms |= 0xf << ffs(esz);
+ imms &= BIT(6) - 1;
+
+ /* Compute the rotation */
+ if (range_of_ones(imm)) {
+ /*
+ * Pattern: 0..01..10..0
+ *
+ * Compute how many rotate we need to align it right
+ */
+ ror = __ffs64(imm);
+ } else {
+ /*
+ * Pattern: 0..01..10..01..1
+ *
+ * Fill the unused top bits with ones, and check if
+ * the result is a valid immediate (all ones with a
+ * contiguous ranges of zeroes).
+ */
+ imm |= ~mask;
+ if (!range_of_ones(~imm))
+ return AARCH64_BREAK_FAULT;
+
+ /*
+ * Compute the rotation to get a continuous set of
+ * ones, with the first bit set at position 0
+ */
+ ror = fls(~imm);
+ }
+
+ /*
+ * immr is the number of bits we need to rotate back to the
+ * original set of ones. Note that this is relative to the
+ * element size...
+ */
+ immr = (esz - ror) % esz;
+
+ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, n);
+ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
+ return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
+}
+
+u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
+ enum aarch64_insn_variant variant,
+ enum aarch64_insn_register Rn,
+ enum aarch64_insn_register Rd,
+ u64 imm)
+{
+ u32 insn;
+
+ switch (type) {
+ case AARCH64_INSN_LOGIC_AND:
+ insn = aarch64_insn_get_and_imm_value();
+ break;
+ case AARCH64_INSN_LOGIC_ORR:
+ insn = aarch64_insn_get_orr_imm_value();
+ break;
+ case AARCH64_INSN_LOGIC_EOR:
+ insn = aarch64_insn_get_eor_imm_value();
+ break;
+ case AARCH64_INSN_LOGIC_AND_SETFLAGS:
+ insn = aarch64_insn_get_ands_imm_value();
+ break;
+ default:
+ pr_err("%s: unknown logical encoding %d\n", __func__, type);
+ return AARCH64_BREAK_FAULT;
+ }
+
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
+ return aarch64_encode_immediate(imm, variant, insn);
+}
+
+u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
+ enum aarch64_insn_register Rm,
+ enum aarch64_insn_register Rn,
+ enum aarch64_insn_register Rd,
+ u8 lsb)
+{
+ u32 insn;
+
+ insn = aarch64_insn_get_extr_value();
+
+ switch (variant) {
+ case AARCH64_INSN_VARIANT_32BIT:
+ if (lsb > 31)
+ return AARCH64_BREAK_FAULT;
+ break;
+ case AARCH64_INSN_VARIANT_64BIT:
+ if (lsb > 63)
+ return AARCH64_BREAK_FAULT;
+ insn |= AARCH64_INSN_SF_BIT;
+ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1);
+ break;
+ default:
+ pr_err("%s: unknown variant encoding %d\n", __func__, variant);
+ return AARCH64_BREAK_FAULT;
+ }
+
+ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb);
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
+ return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
+}
diff --git a/arch/arm64/kernel/kaslr.c b/arch/arm64/kernel/kaslr.c
index 47080c49cc7e..f0e6ab8abe9c 100644
--- a/arch/arm64/kernel/kaslr.c
+++ b/arch/arm64/kernel/kaslr.c
@@ -117,53 +117,42 @@ u64 __init kaslr_early_init(u64 dt_phys)
/*
* OK, so we are proceeding with KASLR enabled. Calculate a suitable
* kernel image offset from the seed. Let's place the kernel in the
- * lower half of the VMALLOC area (VA_BITS - 2).
+ * middle half of the VMALLOC area (VA_BITS - 2), and stay clear of
+ * the lower and upper quarters to avoid colliding with other
+ * allocations.
* Even if we could randomize at page granularity for 16k and 64k pages,
* let's always round to 2 MB so we don't interfere with the ability to
* map using contiguous PTEs
*/
mask = ((1UL << (VA_BITS - 2)) - 1) & ~(SZ_2M - 1);
- offset = seed & mask;
+ offset = BIT(VA_BITS - 3) + (seed & mask);
/* use the top 16 bits to randomize the linear region */
memstart_offset_seed = seed >> 48;
- /*
- * The kernel Image should not extend across a 1GB/32MB/512MB alignment
- * boundary (for 4KB/16KB/64KB granule kernels, respectively). If this
- * happens, round down the KASLR offset by (1 << SWAPPER_TABLE_SHIFT).
- *
- * NOTE: The references to _text and _end below will already take the
- * modulo offset (the physical displacement modulo 2 MB) into
- * account, given that the physical placement is controlled by
- * the loader, and will not change as a result of the virtual
- * mapping we choose.
- */
- if ((((u64)_text + offset) >> SWAPPER_TABLE_SHIFT) !=
- (((u64)_end + offset) >> SWAPPER_TABLE_SHIFT))
- offset = round_down(offset, 1 << SWAPPER_TABLE_SHIFT);
-
if (IS_ENABLED(CONFIG_KASAN))
/*
* KASAN does not expect the module region to intersect the
* vmalloc region, since shadow memory is allocated for each
* module at load time, whereas the vmalloc region is shadowed
* by KASAN zero pages. So keep modules out of the vmalloc
- * region if KASAN is enabled.
+ * region if KASAN is enabled, and put the kernel well within
+ * 4 GB of the module region.
*/
- return offset;
+ return offset % SZ_2G;
if (IS_ENABLED(CONFIG_RANDOMIZE_MODULE_REGION_FULL)) {
/*
- * Randomize the module region independently from the core
- * kernel. This prevents modules from leaking any information
+ * Randomize the module region over a 4 GB window covering the
+ * kernel. This reduces the risk of modules leaking information
* about the address of the kernel itself, but results in
* branches between modules and the core kernel that are
* resolved via PLTs. (Branches between modules will be
* resolved normally.)
*/
- module_range = VMALLOC_END - VMALLOC_START - MODULES_VSIZE;
- module_alloc_base = VMALLOC_START;
+ module_range = SZ_4G - (u64)(_end - _stext);
+ module_alloc_base = max((u64)_end + offset - SZ_4G,
+ (u64)MODULES_VADDR);
} else {
/*
* Randomize the module region by setting module_alloc_base to
diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
index 2122cd187f19..a20de58061a8 100644
--- a/arch/arm64/kernel/kgdb.c
+++ b/arch/arm64/kernel/kgdb.c
@@ -138,14 +138,25 @@ int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
void
sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
{
- struct pt_regs *thread_regs;
+ struct cpu_context *cpu_context = &task->thread.cpu_context;
/* Initialize to zero */
memset((char *)gdb_regs, 0, NUMREGBYTES);
- thread_regs = task_pt_regs(task);
- memcpy((void *)gdb_regs, (void *)thread_regs->regs, GP_REG_BYTES);
- /* Special case for PSTATE (check comments in asm/kgdb.h for details) */
- dbg_get_reg(33, gdb_regs + GP_REG_BYTES, thread_regs);
+
+ gdb_regs[19] = cpu_context->x19;
+ gdb_regs[20] = cpu_context->x20;
+ gdb_regs[21] = cpu_context->x21;
+ gdb_regs[22] = cpu_context->x22;
+ gdb_regs[23] = cpu_context->x23;
+ gdb_regs[24] = cpu_context->x24;
+ gdb_regs[25] = cpu_context->x25;
+ gdb_regs[26] = cpu_context->x26;
+ gdb_regs[27] = cpu_context->x27;
+ gdb_regs[28] = cpu_context->x28;
+ gdb_regs[29] = cpu_context->fp;
+
+ gdb_regs[31] = cpu_context->sp;
+ gdb_regs[32] = cpu_context->pc;
}
void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
diff --git a/arch/arm64/kernel/module-plts.c b/arch/arm64/kernel/module-plts.c
index ea640f92fe5a..fa3637284a3d 100644
--- a/arch/arm64/kernel/module-plts.c
+++ b/arch/arm64/kernel/module-plts.c
@@ -36,11 +36,53 @@ u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
return (u64)&plt[i - 1];
pltsec->plt_num_entries++;
- BUG_ON(pltsec->plt_num_entries > pltsec->plt_max_entries);
+ if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
+ return 0;
return (u64)&plt[i];
}
+#ifdef CONFIG_ARM64_ERRATUM_843419
+u64 module_emit_adrp_veneer(struct module *mod, void *loc, u64 val)
+{
+ struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
+ &mod->arch.init;
+ struct plt_entry *plt = (struct plt_entry *)pltsec->plt->sh_addr;
+ int i = pltsec->plt_num_entries++;
+ u32 mov0, mov1, mov2, br;
+ int rd;
+
+ if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
+ return 0;
+
+ /* get the destination register of the ADRP instruction */
+ rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD,
+ le32_to_cpup((__le32 *)loc));
+
+ /* generate the veneer instructions */
+ mov0 = aarch64_insn_gen_movewide(rd, (u16)~val, 0,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_MOVEWIDE_INVERSE);
+ mov1 = aarch64_insn_gen_movewide(rd, (u16)(val >> 16), 16,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_MOVEWIDE_KEEP);
+ mov2 = aarch64_insn_gen_movewide(rd, (u16)(val >> 32), 32,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_MOVEWIDE_KEEP);
+ br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4,
+ AARCH64_INSN_BRANCH_NOLINK);
+
+ plt[i] = (struct plt_entry){
+ cpu_to_le32(mov0),
+ cpu_to_le32(mov1),
+ cpu_to_le32(mov2),
+ cpu_to_le32(br)
+ };
+
+ return (u64)&plt[i];
+}
+#endif
+
#define cmp_3way(a,b) ((a) < (b) ? -1 : (a) > (b))
static int cmp_rela(const void *a, const void *b)
@@ -68,16 +110,21 @@ static bool duplicate_rel(const Elf64_Rela *rela, int num)
}
static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
- Elf64_Word dstidx)
+ Elf64_Word dstidx, Elf_Shdr *dstsec)
{
unsigned int ret = 0;
Elf64_Sym *s;
int i;
for (i = 0; i < num; i++) {
+ u64 min_align;
+
switch (ELF64_R_TYPE(rela[i].r_info)) {
case R_AARCH64_JUMP26:
case R_AARCH64_CALL26:
+ if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
+ break;
+
/*
* We only have to consider branch targets that resolve
* to symbols that are defined in a different section.
@@ -109,6 +156,41 @@ static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
if (rela[i].r_addend != 0 || !duplicate_rel(rela, i))
ret++;
break;
+ case R_AARCH64_ADR_PREL_PG_HI21_NC:
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
+ !cpus_have_const_cap(ARM64_WORKAROUND_843419))
+ break;
+
+ /*
+ * Determine the minimal safe alignment for this ADRP
+ * instruction: the section alignment at which it is
+ * guaranteed not to appear at a vulnerable offset.
+ *
+ * This comes down to finding the least significant zero
+ * bit in bits [11:3] of the section offset, and
+ * increasing the section's alignment so that the
+ * resulting address of this instruction is guaranteed
+ * to equal the offset in that particular bit (as well
+ * as all less signficant bits). This ensures that the
+ * address modulo 4 KB != 0xfff8 or 0xfffc (which would
+ * have all ones in bits [11:3])
+ */
+ min_align = 2ULL << ffz(rela[i].r_offset | 0x7);
+
+ /*
+ * Allocate veneer space for each ADRP that may appear
+ * at a vulnerable offset nonetheless. At relocation
+ * time, some of these will remain unused since some
+ * ADRP instructions can be patched to ADR instructions
+ * instead.
+ */
+ if (min_align > SZ_4K)
+ ret++;
+ else
+ dstsec->sh_addralign = max(dstsec->sh_addralign,
+ min_align);
+ break;
}
}
return ret;
@@ -166,10 +248,10 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
if (strncmp(secstrings + dstsec->sh_name, ".init", 5) != 0)
core_plts += count_plts(syms, rels, numrels,
- sechdrs[i].sh_info);
+ sechdrs[i].sh_info, dstsec);
else
init_plts += count_plts(syms, rels, numrels,
- sechdrs[i].sh_info);
+ sechdrs[i].sh_info, dstsec);
}
mod->arch.core.plt->sh_type = SHT_NOBITS;
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index f469e0435903..719fde8dcc19 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -55,9 +55,10 @@ void *module_alloc(unsigned long size)
* less likely that the module region gets exhausted, so we
* can simply omit this fallback in that case.
*/
- p = __vmalloc_node_range(size, MODULE_ALIGN, VMALLOC_START,
- VMALLOC_END, GFP_KERNEL, PAGE_KERNEL_EXEC, 0,
- NUMA_NO_NODE, __builtin_return_address(0));
+ p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
+ module_alloc_base + SZ_4G, GFP_KERNEL,
+ PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
+ __builtin_return_address(0));
if (p && (kasan_module_alloc(p, size) < 0)) {
vfree(p);
@@ -197,6 +198,34 @@ static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
return 0;
}
+static int reloc_insn_adrp(struct module *mod, __le32 *place, u64 val)
+{
+ u32 insn;
+
+ if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
+ !cpus_have_const_cap(ARM64_WORKAROUND_843419) ||
+ ((u64)place & 0xfff) < 0xff8)
+ return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
+ AARCH64_INSN_IMM_ADR);
+
+ /* patch ADRP to ADR if it is in range */
+ if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
+ AARCH64_INSN_IMM_ADR)) {
+ insn = le32_to_cpu(*place);
+ insn &= ~BIT(31);
+ } else {
+ /* out of range for ADR -> emit a veneer */
+ val = module_emit_adrp_veneer(mod, place, val & ~0xfff);
+ if (!val)
+ return -ENOEXEC;
+ insn = aarch64_insn_gen_branch_imm((u64)place, val,
+ AARCH64_INSN_BRANCH_NOLINK);
+ }
+
+ *place = cpu_to_le32(insn);
+ return 0;
+}
+
int apply_relocate_add(Elf64_Shdr *sechdrs,
const char *strtab,
unsigned int symindex,
@@ -336,14 +365,13 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
AARCH64_INSN_IMM_ADR);
break;
-#ifndef CONFIG_ARM64_ERRATUM_843419
case R_AARCH64_ADR_PREL_PG_HI21_NC:
overflow_check = false;
case R_AARCH64_ADR_PREL_PG_HI21:
- ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
- AARCH64_INSN_IMM_ADR);
+ ovf = reloc_insn_adrp(me, loc, val);
+ if (ovf && ovf != -ERANGE)
+ return ovf;
break;
-#endif
case R_AARCH64_ADD_ABS_LO12_NC:
case R_AARCH64_LDST8_ABS_LO12_NC:
overflow_check = false;
@@ -386,6 +414,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
ovf == -ERANGE) {
val = module_emit_plt_entry(me, loc, &rel[i], sym);
+ if (!val)
+ return -ENOEXEC;
ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
26, AARCH64_INSN_IMM_26);
}
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index c0da6efe5465..f08a2ed9db0d 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -257,7 +257,7 @@ static void tls_thread_flush(void)
write_sysreg(0, tpidr_el0);
if (is_compat_task()) {
- current->thread.tp_value = 0;
+ current->thread.uw.tp_value = 0;
/*
* We need to ensure ordering between the shadow state and the
@@ -351,7 +351,7 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
* for the new thread.
*/
if (clone_flags & CLONE_SETTLS)
- p->thread.tp_value = childregs->regs[3];
+ p->thread.uw.tp_value = childregs->regs[3];
} else {
memset(childregs, 0, sizeof(struct pt_regs));
childregs->pstate = PSR_MODE_EL1h;
@@ -379,7 +379,7 @@ static void tls_thread_switch(struct task_struct *next)
tls_preserve_current_state();
if (is_compat_thread(task_thread_info(next)))
- write_sysreg(next->thread.tp_value, tpidrro_el0);
+ write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
else if (!arm64_kernel_unmapped_at_el0())
write_sysreg(0, tpidrro_el0);
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 9ae31f7e2243..71d99af24ef2 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -209,7 +209,7 @@ static void ptrace_hbptriggered(struct perf_event *bp,
force_sig_ptrace_errno_trap(si_errno, (void __user *)bkpt->trigger);
}
#endif
- force_sig_info(SIGTRAP, &info, current);
+ arm64_force_sig_info(&info, "Hardware breakpoint trap (ptrace)", current);
}
/*
@@ -629,7 +629,7 @@ static int __fpr_get(struct task_struct *target,
sve_sync_to_fpsimd(target);
- uregs = &target->thread.fpsimd_state.user_fpsimd;
+ uregs = &target->thread.uw.fpsimd_state;
return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs,
start_pos, start_pos + sizeof(*uregs));
@@ -655,19 +655,19 @@ static int __fpr_set(struct task_struct *target,
struct user_fpsimd_state newstate;
/*
- * Ensure target->thread.fpsimd_state is up to date, so that a
+ * Ensure target->thread.uw.fpsimd_state is up to date, so that a
* short copyin can't resurrect stale data.
*/
sve_sync_to_fpsimd(target);
- newstate = target->thread.fpsimd_state.user_fpsimd;
+ newstate = target->thread.uw.fpsimd_state;
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate,
start_pos, start_pos + sizeof(newstate));
if (ret)
return ret;
- target->thread.fpsimd_state.user_fpsimd = newstate;
+ target->thread.uw.fpsimd_state = newstate;
return ret;
}
@@ -692,7 +692,7 @@ static int tls_get(struct task_struct *target, const struct user_regset *regset,
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
- unsigned long *tls = &target->thread.tp_value;
+ unsigned long *tls = &target->thread.uw.tp_value;
if (target == current)
tls_preserve_current_state();
@@ -705,13 +705,13 @@ static int tls_set(struct task_struct *target, const struct user_regset *regset,
const void *kbuf, const void __user *ubuf)
{
int ret;
- unsigned long tls = target->thread.tp_value;
+ unsigned long tls = target->thread.uw.tp_value;
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
if (ret)
return ret;
- target->thread.tp_value = tls;
+ target->thread.uw.tp_value = tls;
return ret;
}
@@ -842,7 +842,7 @@ static int sve_get(struct task_struct *target,
start = end;
end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &target->thread.fpsimd_state.fpsr,
+ &target->thread.uw.fpsimd_state.fpsr,
start, end);
if (ret)
return ret;
@@ -941,7 +941,7 @@ static int sve_set(struct task_struct *target,
start = end;
end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &target->thread.fpsimd_state.fpsr,
+ &target->thread.uw.fpsimd_state.fpsr,
start, end);
out:
@@ -1169,7 +1169,7 @@ static int compat_vfp_get(struct task_struct *target,
compat_ulong_t fpscr;
int ret, vregs_end_pos;
- uregs = &target->thread.fpsimd_state.user_fpsimd;
+ uregs = &target->thread.uw.fpsimd_state;
if (target == current)
fpsimd_preserve_current_state();
@@ -1202,7 +1202,7 @@ static int compat_vfp_set(struct task_struct *target,
compat_ulong_t fpscr;
int ret, vregs_end_pos;
- uregs = &target->thread.fpsimd_state.user_fpsimd;
+ uregs = &target->thread.uw.fpsimd_state;
vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t);
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
@@ -1225,7 +1225,7 @@ static int compat_tls_get(struct task_struct *target,
const struct user_regset *regset, unsigned int pos,
unsigned int count, void *kbuf, void __user *ubuf)
{
- compat_ulong_t tls = (compat_ulong_t)target->thread.tp_value;
+ compat_ulong_t tls = (compat_ulong_t)target->thread.uw.tp_value;
return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
}
@@ -1235,13 +1235,13 @@ static int compat_tls_set(struct task_struct *target,
const void __user *ubuf)
{
int ret;
- compat_ulong_t tls = target->thread.tp_value;
+ compat_ulong_t tls = target->thread.uw.tp_value;
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
if (ret)
return ret;
- target->thread.tp_value = tls;
+ target->thread.uw.tp_value = tls;
return ret;
}
@@ -1538,7 +1538,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
break;
case COMPAT_PTRACE_GET_THREAD_AREA:
- ret = put_user((compat_ulong_t)child->thread.tp_value,
+ ret = put_user((compat_ulong_t)child->thread.uw.tp_value,
(compat_ulong_t __user *)datap);
break;
diff --git a/arch/arm64/kernel/reloc_test_core.c b/arch/arm64/kernel/reloc_test_core.c
index c124752a8bd3..5915ce5759cc 100644
--- a/arch/arm64/kernel/reloc_test_core.c
+++ b/arch/arm64/kernel/reloc_test_core.c
@@ -28,6 +28,7 @@ asmlinkage u64 absolute_data16(void);
asmlinkage u64 signed_movw(void);
asmlinkage u64 unsigned_movw(void);
asmlinkage u64 relative_adrp(void);
+asmlinkage u64 relative_adrp_far(void);
asmlinkage u64 relative_adr(void);
asmlinkage u64 relative_data64(void);
asmlinkage u64 relative_data32(void);
@@ -43,9 +44,8 @@ static struct {
{ "R_AARCH64_ABS16", absolute_data16, UL(SYM16_ABS_VAL) },
{ "R_AARCH64_MOVW_SABS_Gn", signed_movw, UL(SYM64_ABS_VAL) },
{ "R_AARCH64_MOVW_UABS_Gn", unsigned_movw, UL(SYM64_ABS_VAL) },
-#ifndef CONFIG_ARM64_ERRATUM_843419
{ "R_AARCH64_ADR_PREL_PG_HI21", relative_adrp, (u64)&sym64_rel },
-#endif
+ { "R_AARCH64_ADR_PREL_PG_HI21", relative_adrp_far, (u64)&memstart_addr },
{ "R_AARCH64_ADR_PREL_LO21", relative_adr, (u64)&sym64_rel },
{ "R_AARCH64_PREL64", relative_data64, (u64)&sym64_rel },
{ "R_AARCH64_PREL32", relative_data32, (u64)&sym64_rel },
diff --git a/arch/arm64/kernel/reloc_test_syms.S b/arch/arm64/kernel/reloc_test_syms.S
index e1edcefeb02d..2b8d9cb8b078 100644
--- a/arch/arm64/kernel/reloc_test_syms.S
+++ b/arch/arm64/kernel/reloc_test_syms.S
@@ -43,15 +43,21 @@ ENTRY(unsigned_movw)
ret
ENDPROC(unsigned_movw)
-#ifndef CONFIG_ARM64_ERRATUM_843419
-
+ .align 12
+ .space 0xff8
ENTRY(relative_adrp)
adrp x0, sym64_rel
add x0, x0, #:lo12:sym64_rel
ret
ENDPROC(relative_adrp)
-#endif
+ .align 12
+ .space 0xffc
+ENTRY(relative_adrp_far)
+ adrp x0, memstart_addr
+ add x0, x0, #:lo12:memstart_addr
+ ret
+ENDPROC(relative_adrp_far)
ENTRY(relative_adr)
adr x0, sym64_rel
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index f60c052e8d1c..154b7d30145d 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -40,6 +40,7 @@
#include <asm/fpsimd.h>
#include <asm/ptrace.h>
#include <asm/signal32.h>
+#include <asm/traps.h>
#include <asm/vdso.h>
/*
@@ -179,7 +180,7 @@ static void __user *apply_user_offset(
static int preserve_fpsimd_context(struct fpsimd_context __user *ctx)
{
struct user_fpsimd_state const *fpsimd =
- &current->thread.fpsimd_state.user_fpsimd;
+ &current->thread.uw.fpsimd_state;
int err;
/* copy the FP and status/control registers */
@@ -565,11 +566,7 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
return regs->regs[0];
badframe:
- if (show_unhandled_signals)
- pr_info_ratelimited("%s[%d]: bad frame in %s: pc=%08llx sp=%08llx\n",
- current->comm, task_pid_nr(current), __func__,
- regs->pc, regs->sp);
- force_sig(SIGSEGV, current);
+ arm64_notify_segfault(regs->sp);
return 0;
}
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index 79feb861929b..77b91f478995 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -26,6 +26,7 @@
#include <asm/esr.h>
#include <asm/fpsimd.h>
#include <asm/signal32.h>
+#include <asm/traps.h>
#include <linux/uaccess.h>
#include <asm/unistd.h>
@@ -149,7 +150,7 @@ union __fpsimd_vreg {
static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
{
struct user_fpsimd_state const *fpsimd =
- &current->thread.fpsimd_state.user_fpsimd;
+ &current->thread.uw.fpsimd_state;
compat_ulong_t magic = VFP_MAGIC;
compat_ulong_t size = VFP_STORAGE_SIZE;
compat_ulong_t fpscr, fpexc;
@@ -307,11 +308,7 @@ asmlinkage int compat_sys_sigreturn(struct pt_regs *regs)
return regs->regs[0];
badframe:
- if (show_unhandled_signals)
- pr_info_ratelimited("%s[%d]: bad frame in %s: pc=%08llx sp=%08llx\n",
- current->comm, task_pid_nr(current), __func__,
- regs->pc, regs->compat_sp);
- force_sig(SIGSEGV, current);
+ arm64_notify_segfault(regs->compat_sp);
return 0;
}
@@ -344,11 +341,7 @@ asmlinkage int compat_sys_rt_sigreturn(struct pt_regs *regs)
return regs->regs[0];
badframe:
- if (show_unhandled_signals)
- pr_info_ratelimited("%s[%d]: bad frame in %s: pc=%08llx sp=%08llx\n",
- current->comm, task_pid_nr(current), __func__,
- regs->pc, regs->compat_sp);
- force_sig(SIGSEGV, current);
+ arm64_notify_segfault(regs->compat_sp);
return 0;
}
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 3b8ad7be9c33..f3e2e3aec0b0 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -85,43 +85,6 @@ enum ipi_msg_type {
IPI_WAKEUP
};
-#ifdef CONFIG_ARM64_VHE
-
-/* Whether the boot CPU is running in HYP mode or not*/
-static bool boot_cpu_hyp_mode;
-
-static inline void save_boot_cpu_run_el(void)
-{
- boot_cpu_hyp_mode = is_kernel_in_hyp_mode();
-}
-
-static inline bool is_boot_cpu_in_hyp_mode(void)
-{
- return boot_cpu_hyp_mode;
-}
-
-/*
- * Verify that a secondary CPU is running the kernel at the same
- * EL as that of the boot CPU.
- */
-void verify_cpu_run_el(void)
-{
- bool in_el2 = is_kernel_in_hyp_mode();
- bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode();
-
- if (in_el2 ^ boot_cpu_el2) {
- pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n",
- smp_processor_id(),
- in_el2 ? 2 : 1,
- boot_cpu_el2 ? 2 : 1);
- cpu_panic_kernel();
- }
-}
-
-#else
-static inline void save_boot_cpu_run_el(void) {}
-#endif
-
#ifdef CONFIG_HOTPLUG_CPU
static int op_cpu_kill(unsigned int cpu);
#else
@@ -447,13 +410,6 @@ void __init smp_prepare_boot_cpu(void)
*/
jump_label_init();
cpuinfo_store_boot_cpu();
- save_boot_cpu_run_el();
- /*
- * Run the errata work around checks on the boot CPU, once we have
- * initialised the cpu feature infrastructure from
- * cpuinfo_store_boot_cpu() above.
- */
- update_cpu_errata_workarounds();
}
static u64 __init of_get_cpu_mpidr(struct device_node *dn)
diff --git a/arch/arm64/kernel/sys.c b/arch/arm64/kernel/sys.c
index 26fe8ea93ea2..72981bae10eb 100644
--- a/arch/arm64/kernel/sys.c
+++ b/arch/arm64/kernel/sys.c
@@ -34,7 +34,7 @@ asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
if (offset_in_page(off) != 0)
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
}
SYSCALL_DEFINE1(arm64_personality, unsigned int, personality)
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index a382b2a1b84e..93ab57dcfc14 100644
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -27,6 +27,7 @@
#include <linux/uaccess.h>
#include <asm/cacheflush.h>
+#include <asm/system_misc.h>
#include <asm/unistd.h>
static long
@@ -67,6 +68,7 @@ do_compat_cache_op(unsigned long start, unsigned long end, int flags)
*/
long compat_arm_syscall(struct pt_regs *regs)
{
+ siginfo_t info;
unsigned int no = regs->regs[7];
switch (no) {
@@ -88,7 +90,7 @@ long compat_arm_syscall(struct pt_regs *regs)
return do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
case __ARM_NR_compat_set_tls:
- current->thread.tp_value = regs->regs[0];
+ current->thread.uw.tp_value = regs->regs[0];
/*
* Protect against register corruption from context switch.
@@ -99,6 +101,23 @@ long compat_arm_syscall(struct pt_regs *regs)
return 0;
default:
- return -ENOSYS;
+ /*
+ * Calls 9f00xx..9f07ff are defined to return -ENOSYS
+ * if not implemented, rather than raising SIGILL. This
+ * way the calling program can gracefully determine whether
+ * a feature is supported.
+ */
+ if ((no & 0xffff) <= 0x7ff)
+ return -ENOSYS;
+ break;
}
+
+ info.si_signo = SIGILL;
+ info.si_errno = 0;
+ info.si_code = ILL_ILLTRP;
+ info.si_addr = (void __user *)instruction_pointer(regs) -
+ (compat_thumb_mode(regs) ? 2 : 4);
+
+ arm64_notify_die("Oops - bad compat syscall(2)", regs, &info, no);
+ return 0;
}
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index eb2d15147e8d..ba964da31a25 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -38,6 +38,7 @@
#include <asm/atomic.h>
#include <asm/bug.h>
+#include <asm/cpufeature.h>
#include <asm/daifflags.h>
#include <asm/debug-monitors.h>
#include <asm/esr.h>
@@ -223,13 +224,46 @@ void die(const char *str, struct pt_regs *regs, int err)
do_exit(SIGSEGV);
}
+static bool show_unhandled_signals_ratelimited(void)
+{
+ static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
+ DEFAULT_RATELIMIT_BURST);
+ return show_unhandled_signals && __ratelimit(&rs);
+}
+
+void arm64_force_sig_info(struct siginfo *info, const char *str,
+ struct task_struct *tsk)
+{
+ unsigned int esr = tsk->thread.fault_code;
+ struct pt_regs *regs = task_pt_regs(tsk);
+
+ if (!unhandled_signal(tsk, info->si_signo))
+ goto send_sig;
+
+ if (!show_unhandled_signals_ratelimited())
+ goto send_sig;
+
+ pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
+ if (esr)
+ pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
+
+ pr_cont("%s", str);
+ print_vma_addr(KERN_CONT " in ", regs->pc);
+ pr_cont("\n");
+ __show_regs(regs);
+
+send_sig:
+ force_sig_info(info->si_signo, info, tsk);
+}
+
void arm64_notify_die(const char *str, struct pt_regs *regs,
struct siginfo *info, int err)
{
if (user_mode(regs)) {
+ WARN_ON(regs != current_pt_regs());
current->thread.fault_address = 0;
current->thread.fault_code = err;
- force_sig_info(info->si_signo, info, current);
+ arm64_force_sig_info(info, str, current);
} else {
die(str, regs, err);
}
@@ -311,12 +345,13 @@ exit:
return fn ? fn(regs, instr) : 1;
}
-void force_signal_inject(int signal, int code, struct pt_regs *regs,
- unsigned long address)
+void force_signal_inject(int signal, int code, unsigned long address)
{
siginfo_t info;
- void __user *pc = (void __user *)instruction_pointer(regs);
const char *desc;
+ struct pt_regs *regs = current_pt_regs();
+
+ clear_siginfo(&info);
switch (signal) {
case SIGILL:
@@ -330,17 +365,16 @@ void force_signal_inject(int signal, int code, struct pt_regs *regs,
break;
}
- if (unhandled_signal(current, signal) &&
- show_unhandled_signals_ratelimited()) {
- pr_info("%s[%d]: %s: pc=%p\n",
- current->comm, task_pid_nr(current), desc, pc);
- dump_instr(KERN_INFO, regs);
+ /* Force signals we don't understand to SIGKILL */
+ if (WARN_ON(signal != SIGKILL ||
+ siginfo_layout(signal, code) != SIL_FAULT)) {
+ signal = SIGKILL;
}
info.si_signo = signal;
info.si_errno = 0;
info.si_code = code;
- info.si_addr = pc;
+ info.si_addr = (void __user *)address;
arm64_notify_die(desc, regs, &info, 0);
}
@@ -348,7 +382,7 @@ void force_signal_inject(int signal, int code, struct pt_regs *regs,
/*
* Set up process info to signal segmentation fault - called on access error.
*/
-void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr)
+void arm64_notify_segfault(unsigned long addr)
{
int code;
@@ -359,7 +393,7 @@ void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr)
code = SEGV_ACCERR;
up_read(&current->mm->mmap_sem);
- force_signal_inject(SIGSEGV, code, regs, addr);
+ force_signal_inject(SIGSEGV, code, addr);
}
asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
@@ -371,13 +405,12 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
if (call_undef_hook(regs) == 0)
return;
- force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
+ force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
}
-int cpu_enable_cache_maint_trap(void *__unused)
+void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
{
config_sctlr_el1(SCTLR_EL1_UCI, 0);
- return 0;
}
#define __user_cache_maint(insn, address, res) \
@@ -426,12 +459,12 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
__user_cache_maint("ic ivau", address, ret);
break;
default:
- force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
+ force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
return;
}
if (ret)
- arm64_notify_segfault(regs, address);
+ arm64_notify_segfault(address);
else
arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
}
@@ -600,11 +633,6 @@ asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
{
siginfo_t info;
void __user *pc = (void __user *)instruction_pointer(regs);
- console_verbose();
-
- pr_crit("Bad EL0 synchronous exception detected on CPU%d, code 0x%08x -- %s\n",
- smp_processor_id(), esr, esr_get_class_string(esr));
- __show_regs(regs);
info.si_signo = SIGILL;
info.si_errno = 0;
@@ -612,9 +640,9 @@ asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
info.si_addr = pc;
current->thread.fault_address = 0;
- current->thread.fault_code = 0;
+ current->thread.fault_code = esr;
- force_sig_info(info.si_signo, &info, current);
+ arm64_force_sig_info(&info, "Bad EL0 synchronous exception", current);
}
#ifdef CONFIG_VMAP_STACK
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index 2257dfcc44cc..a2e3a5af1113 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -57,6 +57,9 @@ config KVM_ARM_PMU
Adds support for a virtual Performance Monitoring Unit (PMU) in
virtual machines.
+config KVM_INDIRECT_VECTORS
+ def_bool KVM && (HARDEN_BRANCH_PREDICTOR || HARDEN_EL2_VECTORS)
+
source drivers/vhost/Kconfig
endif # VIRTUALIZATION
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 87c4f7ae24de..93afff91cb7c 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -16,7 +16,7 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/e
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arm.o $(KVM)/arm/mmu.o $(KVM)/arm/mmio.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/psci.o $(KVM)/arm/perf.o
-kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o
+kvm-$(CONFIG_KVM_ARM_HOST) += inject_fault.o regmap.o va_layout.o
kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o
kvm-$(CONFIG_KVM_ARM_HOST) += guest.o debug.o reset.o sys_regs.o sys_regs_generic_v8.o
kvm-$(CONFIG_KVM_ARM_HOST) += vgic-sys-reg-v3.o
diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c
index fa63b28c65e0..a1f4ebdfe6d3 100644
--- a/arch/arm64/kvm/debug.c
+++ b/arch/arm64/kvm/debug.c
@@ -46,7 +46,9 @@ static DEFINE_PER_CPU(u32, mdcr_el2);
*/
static void save_guest_debug_regs(struct kvm_vcpu *vcpu)
{
- vcpu->arch.guest_debug_preserved.mdscr_el1 = vcpu_sys_reg(vcpu, MDSCR_EL1);
+ u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
+
+ vcpu->arch.guest_debug_preserved.mdscr_el1 = val;
trace_kvm_arm_set_dreg32("Saved MDSCR_EL1",
vcpu->arch.guest_debug_preserved.mdscr_el1);
@@ -54,10 +56,12 @@ static void save_guest_debug_regs(struct kvm_vcpu *vcpu)
static void restore_guest_debug_regs(struct kvm_vcpu *vcpu)
{
- vcpu_sys_reg(vcpu, MDSCR_EL1) = vcpu->arch.guest_debug_preserved.mdscr_el1;
+ u64 val = vcpu->arch.guest_debug_preserved.mdscr_el1;
+
+ vcpu_write_sys_reg(vcpu, val, MDSCR_EL1);
trace_kvm_arm_set_dreg32("Restored MDSCR_EL1",
- vcpu_sys_reg(vcpu, MDSCR_EL1));
+ vcpu_read_sys_reg(vcpu, MDSCR_EL1));
}
/**
@@ -108,6 +112,7 @@ void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu)
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
{
bool trap_debug = !(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY);
+ unsigned long mdscr;
trace_kvm_arm_setup_debug(vcpu, vcpu->guest_debug);
@@ -152,9 +157,13 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
*/
if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
*vcpu_cpsr(vcpu) |= DBG_SPSR_SS;
- vcpu_sys_reg(vcpu, MDSCR_EL1) |= DBG_MDSCR_SS;
+ mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
+ mdscr |= DBG_MDSCR_SS;
+ vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
} else {
- vcpu_sys_reg(vcpu, MDSCR_EL1) &= ~DBG_MDSCR_SS;
+ mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
+ mdscr &= ~DBG_MDSCR_SS;
+ vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
}
trace_kvm_arm_set_dreg32("SPSR_EL2", *vcpu_cpsr(vcpu));
@@ -170,7 +179,9 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
*/
if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
/* Enable breakpoints/watchpoints */
- vcpu_sys_reg(vcpu, MDSCR_EL1) |= DBG_MDSCR_MDE;
+ mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
+ mdscr |= DBG_MDSCR_MDE;
+ vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
vcpu->arch.debug_ptr = &vcpu->arch.external_debug_state;
vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
@@ -193,8 +204,12 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
if (trap_debug)
vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA;
+ /* If KDE or MDE are set, perform a full save/restore cycle. */
+ if (vcpu_read_sys_reg(vcpu, MDSCR_EL1) & (DBG_MDSCR_KDE | DBG_MDSCR_MDE))
+ vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
+
trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2);
- trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_sys_reg(vcpu, MDSCR_EL1));
+ trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_read_sys_reg(vcpu, MDSCR_EL1));
}
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu)
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index 5aa9ccf6db99..6fd91b31a131 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -117,7 +117,6 @@ CPU_BE( orr x4, x4, #SCTLR_ELx_EE)
/* Set the stack and new vectors */
kern_hyp_va x1
mov sp, x1
- kern_hyp_va x2
msr vbar_el2, x2
/* copy tpidr_el1 into tpidr_el2 for use by HYP */
diff --git a/arch/arm64/kvm/hyp/Makefile b/arch/arm64/kvm/hyp/Makefile
index f04400d494b7..4313f7475333 100644
--- a/arch/arm64/kvm/hyp/Makefile
+++ b/arch/arm64/kvm/hyp/Makefile
@@ -7,10 +7,10 @@ ccflags-y += -fno-stack-protector -DDISABLE_BRANCH_PROFILING
KVM=../../../../virt/kvm
-obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
+obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-cpuif-proxy.o
obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += debug-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += entry.o
diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c
index dabb5cc7b087..3e717f66f011 100644
--- a/arch/arm64/kvm/hyp/debug-sr.c
+++ b/arch/arm64/kvm/hyp/debug-sr.c
@@ -66,11 +66,6 @@
default: write_debug(ptr[0], reg, 0); \
}
-static void __hyp_text __debug_save_spe_vhe(u64 *pmscr_el1)
-{
- /* The vcpu can run. but it can't hide. */
-}
-
static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1)
{
u64 reg;
@@ -103,11 +98,7 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1)
dsb(nsh);
}
-static hyp_alternate_select(__debug_save_spe,
- __debug_save_spe_nvhe, __debug_save_spe_vhe,
- ARM64_HAS_VIRT_HOST_EXTN);
-
-static void __hyp_text __debug_restore_spe(u64 pmscr_el1)
+static void __hyp_text __debug_restore_spe_nvhe(u64 pmscr_el1)
{
if (!pmscr_el1)
return;
@@ -119,16 +110,13 @@ static void __hyp_text __debug_restore_spe(u64 pmscr_el1)
write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1);
}
-void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu,
- struct kvm_guest_debug_arch *dbg,
- struct kvm_cpu_context *ctxt)
+static void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu,
+ struct kvm_guest_debug_arch *dbg,
+ struct kvm_cpu_context *ctxt)
{
u64 aa64dfr0;
int brps, wrps;
- if (!(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY))
- return;
-
aa64dfr0 = read_sysreg(id_aa64dfr0_el1);
brps = (aa64dfr0 >> 12) & 0xf;
wrps = (aa64dfr0 >> 20) & 0xf;
@@ -141,16 +129,13 @@ void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu,
ctxt->sys_regs[MDCCINT_EL1] = read_sysreg(mdccint_el1);
}
-void __hyp_text __debug_restore_state(struct kvm_vcpu *vcpu,
- struct kvm_guest_debug_arch *dbg,
- struct kvm_cpu_context *ctxt)
+static void __hyp_text __debug_restore_state(struct kvm_vcpu *vcpu,
+ struct kvm_guest_debug_arch *dbg,
+ struct kvm_cpu_context *ctxt)
{
u64 aa64dfr0;
int brps, wrps;
- if (!(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY))
- return;
-
aa64dfr0 = read_sysreg(id_aa64dfr0_el1);
brps = (aa64dfr0 >> 12) & 0xf;
@@ -164,27 +149,54 @@ void __hyp_text __debug_restore_state(struct kvm_vcpu *vcpu,
write_sysreg(ctxt->sys_regs[MDCCINT_EL1], mdccint_el1);
}
-void __hyp_text __debug_cond_save_host_state(struct kvm_vcpu *vcpu)
+void __hyp_text __debug_switch_to_guest(struct kvm_vcpu *vcpu)
{
- /* If any of KDE, MDE or KVM_ARM64_DEBUG_DIRTY is set, perform
- * a full save/restore cycle. */
- if ((vcpu->arch.ctxt.sys_regs[MDSCR_EL1] & DBG_MDSCR_KDE) ||
- (vcpu->arch.ctxt.sys_regs[MDSCR_EL1] & DBG_MDSCR_MDE))
- vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
-
- __debug_save_state(vcpu, &vcpu->arch.host_debug_state.regs,
- kern_hyp_va(vcpu->arch.host_cpu_context));
- __debug_save_spe()(&vcpu->arch.host_debug_state.pmscr_el1);
+ struct kvm_cpu_context *host_ctxt;
+ struct kvm_cpu_context *guest_ctxt;
+ struct kvm_guest_debug_arch *host_dbg;
+ struct kvm_guest_debug_arch *guest_dbg;
+
+ /*
+ * Non-VHE: Disable and flush SPE data generation
+ * VHE: The vcpu can run, but it can't hide.
+ */
+ if (!has_vhe())
+ __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1);
+
+ if (!(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY))
+ return;
+
+ host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
+ guest_ctxt = &vcpu->arch.ctxt;
+ host_dbg = &vcpu->arch.host_debug_state.regs;
+ guest_dbg = kern_hyp_va(vcpu->arch.debug_ptr);
+
+ __debug_save_state(vcpu, host_dbg, host_ctxt);
+ __debug_restore_state(vcpu, guest_dbg, guest_ctxt);
}
-void __hyp_text __debug_cond_restore_host_state(struct kvm_vcpu *vcpu)
+void __hyp_text __debug_switch_to_host(struct kvm_vcpu *vcpu)
{
- __debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1);
- __debug_restore_state(vcpu, &vcpu->arch.host_debug_state.regs,
- kern_hyp_va(vcpu->arch.host_cpu_context));
+ struct kvm_cpu_context *host_ctxt;
+ struct kvm_cpu_context *guest_ctxt;
+ struct kvm_guest_debug_arch *host_dbg;
+ struct kvm_guest_debug_arch *guest_dbg;
+
+ if (!has_vhe())
+ __debug_restore_spe_nvhe(vcpu->arch.host_debug_state.pmscr_el1);
+
+ if (!(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY))
+ return;
+
+ host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
+ guest_ctxt = &vcpu->arch.ctxt;
+ host_dbg = &vcpu->arch.host_debug_state.regs;
+ guest_dbg = kern_hyp_va(vcpu->arch.debug_ptr);
+
+ __debug_save_state(vcpu, guest_dbg, guest_ctxt);
+ __debug_restore_state(vcpu, host_dbg, host_ctxt);
- if (vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
- vcpu->arch.debug_flags &= ~KVM_ARM64_DEBUG_DIRTY;
+ vcpu->arch.debug_flags &= ~KVM_ARM64_DEBUG_DIRTY;
}
u32 __hyp_text __kvm_get_mdcr_el2(void)
diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S
index fdd1068ee3a5..e41a161d313a 100644
--- a/arch/arm64/kvm/hyp/entry.S
+++ b/arch/arm64/kvm/hyp/entry.S
@@ -62,9 +62,6 @@ ENTRY(__guest_enter)
// Store the host regs
save_callee_saved_regs x1
- // Store host_ctxt and vcpu for use at exit time
- stp x1, x0, [sp, #-16]!
-
add x18, x0, #VCPU_CONTEXT
// Restore guest regs x0-x17
@@ -118,8 +115,7 @@ ENTRY(__guest_exit)
// Store the guest regs x19-x29, lr
save_callee_saved_regs x1
- // Restore the host_ctxt from the stack
- ldr x2, [sp], #16
+ get_host_ctxt x2, x3
// Now restore the host regs
restore_callee_saved_regs x2
@@ -213,15 +209,3 @@ alternative_endif
eret
ENDPROC(__fpsimd_guest_restore)
-
-ENTRY(__qcom_hyp_sanitize_btac_predictors)
- /**
- * Call SMC64 with Silicon provider serviceID 23<<8 (0xc2001700)
- * 0xC2000000-0xC200FFFF: assigned to SiP Service Calls
- * b15-b0: contains SiP functionID
- */
- movz x0, #0x1700
- movk x0, #0xc200, lsl #16
- smc #0
- ret
-ENDPROC(__qcom_hyp_sanitize_btac_predictors)
diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S
index f36464bd57c5..bffece27b5c1 100644
--- a/arch/arm64/kvm/hyp/hyp-entry.S
+++ b/arch/arm64/kvm/hyp/hyp-entry.S
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2015 - ARM Ltd
+ * Copyright (C) 2015-2018 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -24,6 +24,7 @@
#include <asm/kvm_arm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_mmu.h>
+#include <asm/mmu.h>
.text
.pushsection .hyp.text, "ax"
@@ -55,15 +56,9 @@ ENTRY(__vhe_hyp_call)
ENDPROC(__vhe_hyp_call)
el1_sync: // Guest trapped into EL2
- stp x0, x1, [sp, #-16]!
-
-alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
- mrs x1, esr_el2
-alternative_else
- mrs x1, esr_el1
-alternative_endif
- lsr x0, x1, #ESR_ELx_EC_SHIFT
+ mrs x0, esr_el2
+ lsr x0, x0, #ESR_ELx_EC_SHIFT
cmp x0, #ESR_ELx_EC_HVC64
ccmp x0, #ESR_ELx_EC_HVC32, #4, ne
b.ne el1_trap
@@ -117,10 +112,14 @@ el1_hvc_guest:
eret
el1_trap:
+ get_vcpu_ptr x1, x0
+
+ mrs x0, esr_el2
+ lsr x0, x0, #ESR_ELx_EC_SHIFT
/*
* x0: ESR_EC
+ * x1: vcpu pointer
*/
- ldr x1, [sp, #16 + 8] // vcpu stored by __guest_enter
/*
* We trap the first access to the FP/SIMD to save the host context
@@ -137,18 +136,18 @@ alternative_else_nop_endif
b __guest_exit
el1_irq:
- stp x0, x1, [sp, #-16]!
- ldr x1, [sp, #16 + 8]
+ get_vcpu_ptr x1, x0
mov x0, #ARM_EXCEPTION_IRQ
b __guest_exit
el1_error:
- stp x0, x1, [sp, #-16]!
- ldr x1, [sp, #16 + 8]
+ get_vcpu_ptr x1, x0
mov x0, #ARM_EXCEPTION_EL1_SERROR
b __guest_exit
el2_error:
+ ldp x0, x1, [sp], #16
+
/*
* Only two possibilities:
* 1) Either we come from the exit path, having just unmasked
@@ -180,14 +179,7 @@ ENTRY(__hyp_do_panic)
ENDPROC(__hyp_do_panic)
ENTRY(__hyp_panic)
- /*
- * '=kvm_host_cpu_state' is a host VA from the constant pool, it may
- * not be accessible by this address from EL2, hyp_panic() converts
- * it with kern_hyp_va() before use.
- */
- ldr x0, =kvm_host_cpu_state
- mrs x1, tpidr_el2
- add x0, x0, x1
+ get_host_ctxt x0, x1
b hyp_panic
ENDPROC(__hyp_panic)
@@ -206,32 +198,104 @@ ENDPROC(\label)
invalid_vector el2h_sync_invalid
invalid_vector el2h_irq_invalid
invalid_vector el2h_fiq_invalid
- invalid_vector el1_sync_invalid
- invalid_vector el1_irq_invalid
invalid_vector el1_fiq_invalid
.ltorg
.align 11
+.macro valid_vect target
+ .align 7
+ stp x0, x1, [sp, #-16]!
+ b \target
+.endm
+
+.macro invalid_vect target
+ .align 7
+ b \target
+ ldp x0, x1, [sp], #16
+ b \target
+.endm
+
ENTRY(__kvm_hyp_vector)
- ventry el2t_sync_invalid // Synchronous EL2t
- ventry el2t_irq_invalid // IRQ EL2t
- ventry el2t_fiq_invalid // FIQ EL2t
- ventry el2t_error_invalid // Error EL2t
-
- ventry el2h_sync_invalid // Synchronous EL2h
- ventry el2h_irq_invalid // IRQ EL2h
- ventry el2h_fiq_invalid // FIQ EL2h
- ventry el2_error // Error EL2h
-
- ventry el1_sync // Synchronous 64-bit EL1
- ventry el1_irq // IRQ 64-bit EL1
- ventry el1_fiq_invalid // FIQ 64-bit EL1
- ventry el1_error // Error 64-bit EL1
-
- ventry el1_sync // Synchronous 32-bit EL1
- ventry el1_irq // IRQ 32-bit EL1
- ventry el1_fiq_invalid // FIQ 32-bit EL1
- ventry el1_error // Error 32-bit EL1
+ invalid_vect el2t_sync_invalid // Synchronous EL2t
+ invalid_vect el2t_irq_invalid // IRQ EL2t
+ invalid_vect el2t_fiq_invalid // FIQ EL2t
+ invalid_vect el2t_error_invalid // Error EL2t
+
+ invalid_vect el2h_sync_invalid // Synchronous EL2h
+ invalid_vect el2h_irq_invalid // IRQ EL2h
+ invalid_vect el2h_fiq_invalid // FIQ EL2h
+ valid_vect el2_error // Error EL2h
+
+ valid_vect el1_sync // Synchronous 64-bit EL1
+ valid_vect el1_irq // IRQ 64-bit EL1
+ invalid_vect el1_fiq_invalid // FIQ 64-bit EL1
+ valid_vect el1_error // Error 64-bit EL1
+
+ valid_vect el1_sync // Synchronous 32-bit EL1
+ valid_vect el1_irq // IRQ 32-bit EL1
+ invalid_vect el1_fiq_invalid // FIQ 32-bit EL1
+ valid_vect el1_error // Error 32-bit EL1
ENDPROC(__kvm_hyp_vector)
+
+#ifdef CONFIG_KVM_INDIRECT_VECTORS
+.macro hyp_ventry
+ .align 7
+1: .rept 27
+ nop
+ .endr
+/*
+ * The default sequence is to directly branch to the KVM vectors,
+ * using the computed offset. This applies for VHE as well as
+ * !ARM64_HARDEN_EL2_VECTORS.
+ *
+ * For ARM64_HARDEN_EL2_VECTORS configurations, this gets replaced
+ * with:
+ *
+ * stp x0, x1, [sp, #-16]!
+ * movz x0, #(addr & 0xffff)
+ * movk x0, #((addr >> 16) & 0xffff), lsl #16
+ * movk x0, #((addr >> 32) & 0xffff), lsl #32
+ * br x0
+ *
+ * Where addr = kern_hyp_va(__kvm_hyp_vector) + vector-offset + 4.
+ * See kvm_patch_vector_branch for details.
+ */
+alternative_cb kvm_patch_vector_branch
+ b __kvm_hyp_vector + (1b - 0b)
+ nop
+ nop
+ nop
+ nop
+alternative_cb_end
+.endm
+
+.macro generate_vectors
+0:
+ .rept 16
+ hyp_ventry
+ .endr
+ .org 0b + SZ_2K // Safety measure
+.endm
+
+ .align 11
+ENTRY(__bp_harden_hyp_vecs_start)
+ .rept BP_HARDEN_EL2_SLOTS
+ generate_vectors
+ .endr
+ENTRY(__bp_harden_hyp_vecs_end)
+
+ .popsection
+
+ENTRY(__smccc_workaround_1_smc_start)
+ sub sp, sp, #(8 * 4)
+ stp x2, x3, [sp, #(8 * 0)]
+ stp x0, x1, [sp, #(8 * 2)]
+ mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1
+ smc #0
+ ldp x2, x3, [sp, #(8 * 0)]
+ ldp x0, x1, [sp, #(8 * 2)]
+ add sp, sp, #(8 * 4)
+ENTRY(__smccc_workaround_1_smc_end)
+#endif
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 870f4b1587f9..d9645236e474 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -33,49 +33,22 @@ static bool __hyp_text __fpsimd_enabled_nvhe(void)
return !(read_sysreg(cptr_el2) & CPTR_EL2_TFP);
}
-static bool __hyp_text __fpsimd_enabled_vhe(void)
+static bool fpsimd_enabled_vhe(void)
{
return !!(read_sysreg(cpacr_el1) & CPACR_EL1_FPEN);
}
-static hyp_alternate_select(__fpsimd_is_enabled,
- __fpsimd_enabled_nvhe, __fpsimd_enabled_vhe,
- ARM64_HAS_VIRT_HOST_EXTN);
-
-bool __hyp_text __fpsimd_enabled(void)
-{
- return __fpsimd_is_enabled()();
-}
-
-static void __hyp_text __activate_traps_vhe(void)
-{
- u64 val;
-
- val = read_sysreg(cpacr_el1);
- val |= CPACR_EL1_TTA;
- val &= ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN);
- write_sysreg(val, cpacr_el1);
-
- write_sysreg(kvm_get_hyp_vector(), vbar_el1);
-}
-
-static void __hyp_text __activate_traps_nvhe(void)
+/* Save the 32-bit only FPSIMD system register state */
+static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
{
- u64 val;
+ if (!vcpu_el1_is_32bit(vcpu))
+ return;
- val = CPTR_EL2_DEFAULT;
- val |= CPTR_EL2_TTA | CPTR_EL2_TFP | CPTR_EL2_TZ;
- write_sysreg(val, cptr_el2);
+ vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
}
-static hyp_alternate_select(__activate_traps_arch,
- __activate_traps_nvhe, __activate_traps_vhe,
- ARM64_HAS_VIRT_HOST_EXTN);
-
-static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
+static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
{
- u64 val;
-
/*
* We are about to set CPTR_EL2.TFP to trap all floating point
* register accesses to EL2, however, the ARM ARM clearly states that
@@ -85,23 +58,17 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
* If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
* it will cause an exception.
*/
- val = vcpu->arch.hcr_el2;
-
- if (!(val & HCR_RW) && system_supports_fpsimd()) {
+ if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
write_sysreg(1 << 30, fpexc32_el2);
isb();
}
+}
- if (val & HCR_RW) /* for AArch64 only: */
- val |= HCR_TID3; /* TID3: trap feature register accesses */
-
- write_sysreg(val, hcr_el2);
-
- if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (val & HCR_VSE))
- write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
-
- /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
+static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
+{
+ /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
write_sysreg(1 << 15, hstr_el2);
+
/*
* Make sure we trap PMU access from EL0 to EL2. Also sanitize
* PMSELR_EL0 to make sure it never contains the cycle
@@ -111,19 +78,56 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
write_sysreg(0, pmselr_el0);
write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
- __activate_traps_arch()();
}
-static void __hyp_text __deactivate_traps_vhe(void)
+static void __hyp_text __deactivate_traps_common(void)
{
- extern char vectors[]; /* kernel exception vectors */
- u64 mdcr_el2 = read_sysreg(mdcr_el2);
+ write_sysreg(0, hstr_el2);
+ write_sysreg(0, pmuserenr_el0);
+}
- mdcr_el2 &= MDCR_EL2_HPMN_MASK |
- MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
- MDCR_EL2_TPMS;
+static void activate_traps_vhe(struct kvm_vcpu *vcpu)
+{
+ u64 val;
- write_sysreg(mdcr_el2, mdcr_el2);
+ val = read_sysreg(cpacr_el1);
+ val |= CPACR_EL1_TTA;
+ val &= ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN);
+ write_sysreg(val, cpacr_el1);
+
+ write_sysreg(kvm_get_hyp_vector(), vbar_el1);
+}
+
+static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
+{
+ u64 val;
+
+ __activate_traps_common(vcpu);
+
+ val = CPTR_EL2_DEFAULT;
+ val |= CPTR_EL2_TTA | CPTR_EL2_TFP | CPTR_EL2_TZ;
+ write_sysreg(val, cptr_el2);
+}
+
+static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
+{
+ u64 hcr = vcpu->arch.hcr_el2;
+
+ write_sysreg(hcr, hcr_el2);
+
+ if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
+ write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
+
+ __activate_traps_fpsimd32(vcpu);
+ if (has_vhe())
+ activate_traps_vhe(vcpu);
+ else
+ __activate_traps_nvhe(vcpu);
+}
+
+static void deactivate_traps_vhe(void)
+{
+ extern char vectors[]; /* kernel exception vectors */
write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
write_sysreg(vectors, vbar_el1);
@@ -133,6 +137,8 @@ static void __hyp_text __deactivate_traps_nvhe(void)
{
u64 mdcr_el2 = read_sysreg(mdcr_el2);
+ __deactivate_traps_common();
+
mdcr_el2 &= MDCR_EL2_HPMN_MASK;
mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
@@ -141,10 +147,6 @@ static void __hyp_text __deactivate_traps_nvhe(void)
write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
}
-static hyp_alternate_select(__deactivate_traps_arch,
- __deactivate_traps_nvhe, __deactivate_traps_vhe,
- ARM64_HAS_VIRT_HOST_EXTN);
-
static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
{
/*
@@ -156,14 +158,32 @@ static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
if (vcpu->arch.hcr_el2 & HCR_VSE)
vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
- __deactivate_traps_arch()();
- write_sysreg(0, hstr_el2);
- write_sysreg(0, pmuserenr_el0);
+ if (has_vhe())
+ deactivate_traps_vhe();
+ else
+ __deactivate_traps_nvhe();
+}
+
+void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
+{
+ __activate_traps_common(vcpu);
+}
+
+void deactivate_traps_vhe_put(void)
+{
+ u64 mdcr_el2 = read_sysreg(mdcr_el2);
+
+ mdcr_el2 &= MDCR_EL2_HPMN_MASK |
+ MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
+ MDCR_EL2_TPMS;
+
+ write_sysreg(mdcr_el2, mdcr_el2);
+
+ __deactivate_traps_common();
}
-static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
+static void __hyp_text __activate_vm(struct kvm *kvm)
{
- struct kvm *kvm = kern_hyp_va(vcpu->kvm);
write_sysreg(kvm->arch.vttbr, vttbr_el2);
}
@@ -172,29 +192,22 @@ static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
write_sysreg(0, vttbr_el2);
}
-static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
+/* Save VGICv3 state on non-VHE systems */
+static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
{
- if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
__vgic_v3_save_state(vcpu);
- else
- __vgic_v2_save_state(vcpu);
-
- write_sysreg(read_sysreg(hcr_el2) & ~HCR_INT_OVERRIDE, hcr_el2);
+ __vgic_v3_deactivate_traps(vcpu);
+ }
}
-static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
+/* Restore VGICv3 state on non_VEH systems */
+static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
{
- u64 val;
-
- val = read_sysreg(hcr_el2);
- val |= HCR_INT_OVERRIDE;
- val |= vcpu->arch.irq_lines;
- write_sysreg(val, hcr_el2);
-
- if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
+ if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
+ __vgic_v3_activate_traps(vcpu);
__vgic_v3_restore_state(vcpu);
- else
- __vgic_v2_restore_state(vcpu);
+ }
}
static bool __hyp_text __true_value(void)
@@ -305,54 +318,27 @@ static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
}
}
-int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
+/*
+ * Return true when we were able to fixup the guest exit and should return to
+ * the guest, false when we should restore the host state and return to the
+ * main run loop.
+ */
+static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
{
- struct kvm_cpu_context *host_ctxt;
- struct kvm_cpu_context *guest_ctxt;
- bool fp_enabled;
- u64 exit_code;
-
- vcpu = kern_hyp_va(vcpu);
-
- host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
- host_ctxt->__hyp_running_vcpu = vcpu;
- guest_ctxt = &vcpu->arch.ctxt;
-
- __sysreg_save_host_state(host_ctxt);
- __debug_cond_save_host_state(vcpu);
-
- __activate_traps(vcpu);
- __activate_vm(vcpu);
-
- __vgic_restore_state(vcpu);
- __timer_enable_traps(vcpu);
-
- /*
- * We must restore the 32-bit state before the sysregs, thanks
- * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
- */
- __sysreg32_restore_state(vcpu);
- __sysreg_restore_guest_state(guest_ctxt);
- __debug_restore_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
-
- /* Jump in the fire! */
-again:
- exit_code = __guest_enter(vcpu, host_ctxt);
- /* And we're baaack! */
-
- if (ARM_EXCEPTION_CODE(exit_code) != ARM_EXCEPTION_IRQ)
+ if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
vcpu->arch.fault.esr_el2 = read_sysreg_el2(esr);
+
/*
* We're using the raw exception code in order to only process
* the trap if no SError is pending. We will come back to the
* same PC once the SError has been injected, and replay the
* trapping instruction.
*/
- if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu))
- goto again;
+ if (*exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu))
+ return true;
if (static_branch_unlikely(&vgic_v2_cpuif_trap) &&
- exit_code == ARM_EXCEPTION_TRAP) {
+ *exit_code == ARM_EXCEPTION_TRAP) {
bool valid;
valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
@@ -366,9 +352,9 @@ again:
if (ret == 1) {
if (__skip_instr(vcpu))
- goto again;
+ return true;
else
- exit_code = ARM_EXCEPTION_TRAP;
+ *exit_code = ARM_EXCEPTION_TRAP;
}
if (ret == -1) {
@@ -380,62 +366,135 @@ again:
*/
if (!__skip_instr(vcpu))
*vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
- exit_code = ARM_EXCEPTION_EL1_SERROR;
+ *exit_code = ARM_EXCEPTION_EL1_SERROR;
}
-
- /* 0 falls through to be handler out of EL2 */
}
}
if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
- exit_code == ARM_EXCEPTION_TRAP &&
+ *exit_code == ARM_EXCEPTION_TRAP &&
(kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
int ret = __vgic_v3_perform_cpuif_access(vcpu);
if (ret == 1) {
if (__skip_instr(vcpu))
- goto again;
+ return true;
else
- exit_code = ARM_EXCEPTION_TRAP;
+ *exit_code = ARM_EXCEPTION_TRAP;
}
-
- /* 0 falls through to be handled out of EL2 */
}
- if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) {
- u32 midr = read_cpuid_id();
+ /* Return to the host kernel and handle the exit */
+ return false;
+}
- /* Apply BTAC predictors mitigation to all Falkor chips */
- if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
- ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
- __qcom_hyp_sanitize_btac_predictors();
- }
+/* Switch to the guest for VHE systems running in EL2 */
+int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
+{
+ struct kvm_cpu_context *host_ctxt;
+ struct kvm_cpu_context *guest_ctxt;
+ bool fp_enabled;
+ u64 exit_code;
+
+ host_ctxt = vcpu->arch.host_cpu_context;
+ host_ctxt->__hyp_running_vcpu = vcpu;
+ guest_ctxt = &vcpu->arch.ctxt;
+
+ sysreg_save_host_state_vhe(host_ctxt);
+
+ __activate_traps(vcpu);
+ __activate_vm(vcpu->kvm);
+
+ sysreg_restore_guest_state_vhe(guest_ctxt);
+ __debug_switch_to_guest(vcpu);
+
+ do {
+ /* Jump in the fire! */
+ exit_code = __guest_enter(vcpu, host_ctxt);
+
+ /* And we're baaack! */
+ } while (fixup_guest_exit(vcpu, &exit_code));
+
+ fp_enabled = fpsimd_enabled_vhe();
+
+ sysreg_save_guest_state_vhe(guest_ctxt);
+
+ __deactivate_traps(vcpu);
+
+ sysreg_restore_host_state_vhe(host_ctxt);
+
+ if (fp_enabled) {
+ __fpsimd_save_state(&guest_ctxt->gp_regs.fp_regs);
+ __fpsimd_restore_state(&host_ctxt->gp_regs.fp_regs);
+ __fpsimd_save_fpexc32(vcpu);
}
- fp_enabled = __fpsimd_enabled();
+ __debug_switch_to_host(vcpu);
+
+ return exit_code;
+}
+
+/* Switch to the guest for legacy non-VHE systems */
+int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
+{
+ struct kvm_cpu_context *host_ctxt;
+ struct kvm_cpu_context *guest_ctxt;
+ bool fp_enabled;
+ u64 exit_code;
+
+ vcpu = kern_hyp_va(vcpu);
+
+ host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
+ host_ctxt->__hyp_running_vcpu = vcpu;
+ guest_ctxt = &vcpu->arch.ctxt;
+
+ __sysreg_save_state_nvhe(host_ctxt);
+
+ __activate_traps(vcpu);
+ __activate_vm(kern_hyp_va(vcpu->kvm));
+
+ __hyp_vgic_restore_state(vcpu);
+ __timer_enable_traps(vcpu);
+
+ /*
+ * We must restore the 32-bit state before the sysregs, thanks
+ * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
+ */
+ __sysreg32_restore_state(vcpu);
+ __sysreg_restore_state_nvhe(guest_ctxt);
+ __debug_switch_to_guest(vcpu);
+
+ do {
+ /* Jump in the fire! */
+ exit_code = __guest_enter(vcpu, host_ctxt);
+
+ /* And we're baaack! */
+ } while (fixup_guest_exit(vcpu, &exit_code));
- __sysreg_save_guest_state(guest_ctxt);
+ fp_enabled = __fpsimd_enabled_nvhe();
+
+ __sysreg_save_state_nvhe(guest_ctxt);
__sysreg32_save_state(vcpu);
__timer_disable_traps(vcpu);
- __vgic_save_state(vcpu);
+ __hyp_vgic_save_state(vcpu);
__deactivate_traps(vcpu);
__deactivate_vm(vcpu);
- __sysreg_restore_host_state(host_ctxt);
+ __sysreg_restore_state_nvhe(host_ctxt);
if (fp_enabled) {
__fpsimd_save_state(&guest_ctxt->gp_regs.fp_regs);
__fpsimd_restore_state(&host_ctxt->gp_regs.fp_regs);
+ __fpsimd_save_fpexc32(vcpu);
}
- __debug_save_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
/*
* This must come after restoring the host sysregs, since a non-VHE
* system may enable SPE here and make use of the TTBRs.
*/
- __debug_cond_restore_host_state(vcpu);
+ __debug_switch_to_host(vcpu);
return exit_code;
}
@@ -443,10 +502,20 @@ again:
static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
- struct kvm_vcpu *vcpu)
+ struct kvm_cpu_context *__host_ctxt)
{
+ struct kvm_vcpu *vcpu;
unsigned long str_va;
+ vcpu = __host_ctxt->__hyp_running_vcpu;
+
+ if (read_sysreg(vttbr_el2)) {
+ __timer_disable_traps(vcpu);
+ __deactivate_traps(vcpu);
+ __deactivate_vm(vcpu);
+ __sysreg_restore_state_nvhe(__host_ctxt);
+ }
+
/*
* Force the panic string to be loaded from the literal pool,
* making sure it is a kernel address and not a PC-relative
@@ -460,40 +529,31 @@ static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
read_sysreg(hpfar_el2), par, vcpu);
}
-static void __hyp_text __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
- struct kvm_vcpu *vcpu)
+static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
+ struct kvm_cpu_context *host_ctxt)
{
+ struct kvm_vcpu *vcpu;
+ vcpu = host_ctxt->__hyp_running_vcpu;
+
+ __deactivate_traps(vcpu);
+ sysreg_restore_host_state_vhe(host_ctxt);
+
panic(__hyp_panic_string,
spsr, elr,
read_sysreg_el2(esr), read_sysreg_el2(far),
read_sysreg(hpfar_el2), par, vcpu);
}
-static hyp_alternate_select(__hyp_call_panic,
- __hyp_call_panic_nvhe, __hyp_call_panic_vhe,
- ARM64_HAS_VIRT_HOST_EXTN);
-
-void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *__host_ctxt)
+void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
{
- struct kvm_vcpu *vcpu = NULL;
-
u64 spsr = read_sysreg_el2(spsr);
u64 elr = read_sysreg_el2(elr);
u64 par = read_sysreg(par_el1);
- if (read_sysreg(vttbr_el2)) {
- struct kvm_cpu_context *host_ctxt;
-
- host_ctxt = kern_hyp_va(__host_ctxt);
- vcpu = host_ctxt->__hyp_running_vcpu;
- __timer_disable_traps(vcpu);
- __deactivate_traps(vcpu);
- __deactivate_vm(vcpu);
- __sysreg_restore_host_state(host_ctxt);
- }
-
- /* Call panic for real */
- __hyp_call_panic()(spsr, elr, par, vcpu);
+ if (!has_vhe())
+ __hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
+ else
+ __hyp_call_panic_vhe(spsr, elr, par, host_ctxt);
unreachable();
}
diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
index 2c17afd2be96..b3894df6bf1a 100644
--- a/arch/arm64/kvm/hyp/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/sysreg-sr.c
@@ -19,32 +19,43 @@
#include <linux/kvm_host.h>
#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
#include <asm/kvm_hyp.h>
-/* Yes, this does nothing, on purpose */
-static void __hyp_text __sysreg_do_nothing(struct kvm_cpu_context *ctxt) { }
-
/*
* Non-VHE: Both host and guest must save everything.
*
- * VHE: Host must save tpidr*_el0, actlr_el1, mdscr_el1, sp_el0,
- * and guest must save everything.
+ * VHE: Host and guest must save mdscr_el1 and sp_el0 (and the PC and pstate,
+ * which are handled as part of the el2 return state) on every switch.
+ * tpidr_el0 and tpidrro_el0 only need to be switched when going
+ * to host userspace or a different VCPU. EL1 registers only need to be
+ * switched when potentially going to run a different VCPU. The latter two
+ * classes are handled as part of kvm_arch_vcpu_load and kvm_arch_vcpu_put.
*/
static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
{
- ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
- ctxt->sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0);
- ctxt->sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0);
ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1);
+
+ /*
+ * The host arm64 Linux uses sp_el0 to point to 'current' and it must
+ * therefore be saved/restored on every entry/exit to/from the guest.
+ */
ctxt->gp_regs.regs.sp = read_sysreg(sp_el0);
}
-static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
+static void __hyp_text __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
+{
+ ctxt->sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0);
+ ctxt->sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0);
+}
+
+static void __hyp_text __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
{
ctxt->sys_regs[MPIDR_EL1] = read_sysreg(vmpidr_el2);
ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1);
ctxt->sys_regs[SCTLR_EL1] = read_sysreg_el1(sctlr);
+ ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
ctxt->sys_regs[CPACR_EL1] = read_sysreg_el1(cpacr);
ctxt->sys_regs[TTBR0_EL1] = read_sysreg_el1(ttbr0);
ctxt->sys_regs[TTBR1_EL1] = read_sysreg_el1(ttbr1);
@@ -64,6 +75,10 @@ static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
ctxt->gp_regs.sp_el1 = read_sysreg(sp_el1);
ctxt->gp_regs.elr_el1 = read_sysreg_el1(elr);
ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(spsr);
+}
+
+static void __hyp_text __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
+{
ctxt->gp_regs.regs.pc = read_sysreg_el2(elr);
ctxt->gp_regs.regs.pstate = read_sysreg_el2(spsr);
@@ -71,36 +86,48 @@ static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
ctxt->sys_regs[DISR_EL1] = read_sysreg_s(SYS_VDISR_EL2);
}
-static hyp_alternate_select(__sysreg_call_save_host_state,
- __sysreg_save_state, __sysreg_do_nothing,
- ARM64_HAS_VIRT_HOST_EXTN);
+void __hyp_text __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt)
+{
+ __sysreg_save_el1_state(ctxt);
+ __sysreg_save_common_state(ctxt);
+ __sysreg_save_user_state(ctxt);
+ __sysreg_save_el2_return_state(ctxt);
+}
-void __hyp_text __sysreg_save_host_state(struct kvm_cpu_context *ctxt)
+void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt)
{
- __sysreg_call_save_host_state()(ctxt);
__sysreg_save_common_state(ctxt);
}
-void __hyp_text __sysreg_save_guest_state(struct kvm_cpu_context *ctxt)
+void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt)
{
- __sysreg_save_state(ctxt);
__sysreg_save_common_state(ctxt);
+ __sysreg_save_el2_return_state(ctxt);
}
static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
{
- write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
- write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0);
- write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0);
write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1);
+
+ /*
+ * The host arm64 Linux uses sp_el0 to point to 'current' and it must
+ * therefore be saved/restored on every entry/exit to/from the guest.
+ */
write_sysreg(ctxt->gp_regs.regs.sp, sp_el0);
}
-static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
+static void __hyp_text __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
+{
+ write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0);
+ write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0);
+}
+
+static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
{
write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], sctlr);
+ write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], cpacr);
write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], ttbr0);
write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], ttbr1);
@@ -120,6 +147,11 @@ static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
write_sysreg(ctxt->gp_regs.sp_el1, sp_el1);
write_sysreg_el1(ctxt->gp_regs.elr_el1, elr);
write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr);
+}
+
+static void __hyp_text
+__sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
+{
write_sysreg_el2(ctxt->gp_regs.regs.pc, elr);
write_sysreg_el2(ctxt->gp_regs.regs.pstate, spsr);
@@ -127,27 +159,30 @@ static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2);
}
-static hyp_alternate_select(__sysreg_call_restore_host_state,
- __sysreg_restore_state, __sysreg_do_nothing,
- ARM64_HAS_VIRT_HOST_EXTN);
+void __hyp_text __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt)
+{
+ __sysreg_restore_el1_state(ctxt);
+ __sysreg_restore_common_state(ctxt);
+ __sysreg_restore_user_state(ctxt);
+ __sysreg_restore_el2_return_state(ctxt);
+}
-void __hyp_text __sysreg_restore_host_state(struct kvm_cpu_context *ctxt)
+void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt)
{
- __sysreg_call_restore_host_state()(ctxt);
__sysreg_restore_common_state(ctxt);
}
-void __hyp_text __sysreg_restore_guest_state(struct kvm_cpu_context *ctxt)
+void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
{
- __sysreg_restore_state(ctxt);
__sysreg_restore_common_state(ctxt);
+ __sysreg_restore_el2_return_state(ctxt);
}
void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
{
u64 *spsr, *sysreg;
- if (read_sysreg(hcr_el2) & HCR_RW)
+ if (!vcpu_el1_is_32bit(vcpu))
return;
spsr = vcpu->arch.ctxt.gp_regs.spsr;
@@ -161,10 +196,7 @@ void __hyp_text __sysreg32_save_state(struct kvm_vcpu *vcpu)
sysreg[DACR32_EL2] = read_sysreg(dacr32_el2);
sysreg[IFSR32_EL2] = read_sysreg(ifsr32_el2);
- if (__fpsimd_enabled())
- sysreg[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
-
- if (vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
+ if (has_vhe() || vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
sysreg[DBGVCR32_EL2] = read_sysreg(dbgvcr32_el2);
}
@@ -172,7 +204,7 @@ void __hyp_text __sysreg32_restore_state(struct kvm_vcpu *vcpu)
{
u64 *spsr, *sysreg;
- if (read_sysreg(hcr_el2) & HCR_RW)
+ if (!vcpu_el1_is_32bit(vcpu))
return;
spsr = vcpu->arch.ctxt.gp_regs.spsr;
@@ -186,6 +218,78 @@ void __hyp_text __sysreg32_restore_state(struct kvm_vcpu *vcpu)
write_sysreg(sysreg[DACR32_EL2], dacr32_el2);
write_sysreg(sysreg[IFSR32_EL2], ifsr32_el2);
- if (vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
+ if (has_vhe() || vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY)
write_sysreg(sysreg[DBGVCR32_EL2], dbgvcr32_el2);
}
+
+/**
+ * kvm_vcpu_load_sysregs - Load guest system registers to the physical CPU
+ *
+ * @vcpu: The VCPU pointer
+ *
+ * Load system registers that do not affect the host's execution, for
+ * example EL1 system registers on a VHE system where the host kernel
+ * runs at EL2. This function is called from KVM's vcpu_load() function
+ * and loading system register state early avoids having to load them on
+ * every entry to the VM.
+ */
+void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu)
+{
+ struct kvm_cpu_context *host_ctxt = vcpu->arch.host_cpu_context;
+ struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt;
+
+ if (!has_vhe())
+ return;
+
+ __sysreg_save_user_state(host_ctxt);
+
+ /*
+ * Load guest EL1 and user state
+ *
+ * We must restore the 32-bit state before the sysregs, thanks
+ * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
+ */
+ __sysreg32_restore_state(vcpu);
+ __sysreg_restore_user_state(guest_ctxt);
+ __sysreg_restore_el1_state(guest_ctxt);
+
+ vcpu->arch.sysregs_loaded_on_cpu = true;
+
+ activate_traps_vhe_load(vcpu);
+}
+
+/**
+ * kvm_vcpu_put_sysregs - Restore host system registers to the physical CPU
+ *
+ * @vcpu: The VCPU pointer
+ *
+ * Save guest system registers that do not affect the host's execution, for
+ * example EL1 system registers on a VHE system where the host kernel
+ * runs at EL2. This function is called from KVM's vcpu_put() function
+ * and deferring saving system register state until we're no longer running the
+ * VCPU avoids having to save them on every exit from the VM.
+ */
+void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu)
+{
+ struct kvm_cpu_context *host_ctxt = vcpu->arch.host_cpu_context;
+ struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt;
+
+ if (!has_vhe())
+ return;
+
+ deactivate_traps_vhe_put();
+
+ __sysreg_save_el1_state(guest_ctxt);
+ __sysreg_save_user_state(guest_ctxt);
+ __sysreg32_save_state(vcpu);
+
+ /* Restore host user state */
+ __sysreg_restore_user_state(host_ctxt);
+
+ vcpu->arch.sysregs_loaded_on_cpu = false;
+}
+
+void __hyp_text __kvm_set_tpidr_el2(u64 tpidr_el2)
+{
+ asm("msr tpidr_el2, %0": : "r" (tpidr_el2));
+}
diff --git a/arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c b/arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c
new file mode 100644
index 000000000000..86801b6055d6
--- /dev/null
+++ b/arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2012-2015 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/compiler.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/kvm_host.h>
+
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_hyp.h>
+#include <asm/kvm_mmu.h>
+
+/*
+ * __vgic_v2_perform_cpuif_access -- perform a GICV access on behalf of the
+ * guest.
+ *
+ * @vcpu: the offending vcpu
+ *
+ * Returns:
+ * 1: GICV access successfully performed
+ * 0: Not a GICV access
+ * -1: Illegal GICV access
+ */
+int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu)
+{
+ struct kvm *kvm = kern_hyp_va(vcpu->kvm);
+ struct vgic_dist *vgic = &kvm->arch.vgic;
+ phys_addr_t fault_ipa;
+ void __iomem *addr;
+ int rd;
+
+ /* Build the full address */
+ fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
+ fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
+
+ /* If not for GICV, move on */
+ if (fault_ipa < vgic->vgic_cpu_base ||
+ fault_ipa >= (vgic->vgic_cpu_base + KVM_VGIC_V2_CPU_SIZE))
+ return 0;
+
+ /* Reject anything but a 32bit access */
+ if (kvm_vcpu_dabt_get_as(vcpu) != sizeof(u32))
+ return -1;
+
+ /* Not aligned? Don't bother */
+ if (fault_ipa & 3)
+ return -1;
+
+ rd = kvm_vcpu_dabt_get_rd(vcpu);
+ addr = hyp_symbol_addr(kvm_vgic_global_state)->vcpu_hyp_va;
+ addr += fault_ipa - vgic->vgic_cpu_base;
+
+ if (kvm_vcpu_dabt_iswrite(vcpu)) {
+ u32 data = vcpu_data_guest_to_host(vcpu,
+ vcpu_get_reg(vcpu, rd),
+ sizeof(u32));
+ writel_relaxed(data, addr);
+ } else {
+ u32 data = readl_relaxed(addr);
+ vcpu_set_reg(vcpu, rd, vcpu_data_host_to_guest(vcpu, data,
+ sizeof(u32)));
+ }
+
+ return 1;
+}
diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
index 60666a056944..d8e71659ba7e 100644
--- a/arch/arm64/kvm/inject_fault.c
+++ b/arch/arm64/kvm/inject_fault.c
@@ -58,7 +58,7 @@ static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type)
exc_offset = LOWER_EL_AArch32_VECTOR;
}
- return vcpu_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
+ return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
}
static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
@@ -67,13 +67,13 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr
bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
u32 esr = 0;
- *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+ vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
- *vcpu_spsr(vcpu) = cpsr;
+ vcpu_write_spsr(vcpu, cpsr);
- vcpu_sys_reg(vcpu, FAR_EL1) = addr;
+ vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
/*
* Build an {i,d}abort, depending on the level and the
@@ -94,7 +94,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr
if (!is_iabt)
esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
- vcpu_sys_reg(vcpu, ESR_EL1) = esr | ESR_ELx_FSC_EXTABT;
+ vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
}
static void inject_undef64(struct kvm_vcpu *vcpu)
@@ -102,11 +102,11 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
unsigned long cpsr = *vcpu_cpsr(vcpu);
u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
- *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+ vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
- *vcpu_spsr(vcpu) = cpsr;
+ vcpu_write_spsr(vcpu, cpsr);
/*
* Build an unknown exception, depending on the instruction
@@ -115,7 +115,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
if (kvm_vcpu_trap_il_is32bit(vcpu))
esr |= ESR_ELx_IL;
- vcpu_sys_reg(vcpu, ESR_EL1) = esr;
+ vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
}
/**
@@ -128,7 +128,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
*/
void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
{
- if (!(vcpu->arch.hcr_el2 & HCR_RW))
+ if (vcpu_el1_is_32bit(vcpu))
kvm_inject_dabt32(vcpu, addr);
else
inject_abt64(vcpu, false, addr);
@@ -144,7 +144,7 @@ void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
*/
void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
{
- if (!(vcpu->arch.hcr_el2 & HCR_RW))
+ if (vcpu_el1_is_32bit(vcpu))
kvm_inject_pabt32(vcpu, addr);
else
inject_abt64(vcpu, true, addr);
@@ -158,7 +158,7 @@ void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
*/
void kvm_inject_undefined(struct kvm_vcpu *vcpu)
{
- if (!(vcpu->arch.hcr_el2 & HCR_RW))
+ if (vcpu_el1_is_32bit(vcpu))
kvm_inject_undef32(vcpu);
else
inject_undef64(vcpu);
@@ -167,7 +167,7 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu)
static void pend_guest_serror(struct kvm_vcpu *vcpu, u64 esr)
{
vcpu_set_vsesr(vcpu, esr);
- vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) | HCR_VSE);
+ *vcpu_hcr(vcpu) |= HCR_VSE;
}
/**
diff --git a/arch/arm64/kvm/regmap.c b/arch/arm64/kvm/regmap.c
index bbc6ae32e4af..eefe403a2e63 100644
--- a/arch/arm64/kvm/regmap.c
+++ b/arch/arm64/kvm/regmap.c
@@ -141,28 +141,61 @@ unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num)
/*
* Return the SPSR for the current mode of the virtual CPU.
*/
-unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu)
+static int vcpu_spsr32_mode(const struct kvm_vcpu *vcpu)
{
unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
switch (mode) {
- case COMPAT_PSR_MODE_SVC:
- mode = KVM_SPSR_SVC;
- break;
- case COMPAT_PSR_MODE_ABT:
- mode = KVM_SPSR_ABT;
- break;
- case COMPAT_PSR_MODE_UND:
- mode = KVM_SPSR_UND;
- break;
- case COMPAT_PSR_MODE_IRQ:
- mode = KVM_SPSR_IRQ;
- break;
- case COMPAT_PSR_MODE_FIQ:
- mode = KVM_SPSR_FIQ;
- break;
+ case COMPAT_PSR_MODE_SVC: return KVM_SPSR_SVC;
+ case COMPAT_PSR_MODE_ABT: return KVM_SPSR_ABT;
+ case COMPAT_PSR_MODE_UND: return KVM_SPSR_UND;
+ case COMPAT_PSR_MODE_IRQ: return KVM_SPSR_IRQ;
+ case COMPAT_PSR_MODE_FIQ: return KVM_SPSR_FIQ;
+ default: BUG();
+ }
+}
+
+unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu)
+{
+ int spsr_idx = vcpu_spsr32_mode(vcpu);
+
+ if (!vcpu->arch.sysregs_loaded_on_cpu)
+ return vcpu_gp_regs(vcpu)->spsr[spsr_idx];
+
+ switch (spsr_idx) {
+ case KVM_SPSR_SVC:
+ return read_sysreg_el1(spsr);
+ case KVM_SPSR_ABT:
+ return read_sysreg(spsr_abt);
+ case KVM_SPSR_UND:
+ return read_sysreg(spsr_und);
+ case KVM_SPSR_IRQ:
+ return read_sysreg(spsr_irq);
+ case KVM_SPSR_FIQ:
+ return read_sysreg(spsr_fiq);
default:
BUG();
}
+}
+
+void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v)
+{
+ int spsr_idx = vcpu_spsr32_mode(vcpu);
+
+ if (!vcpu->arch.sysregs_loaded_on_cpu) {
+ vcpu_gp_regs(vcpu)->spsr[spsr_idx] = v;
+ return;
+ }
- return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[mode];
+ switch (spsr_idx) {
+ case KVM_SPSR_SVC:
+ write_sysreg_el1(v, spsr);
+ case KVM_SPSR_ABT:
+ write_sysreg(v, spsr_abt);
+ case KVM_SPSR_UND:
+ write_sysreg(v, spsr_und);
+ case KVM_SPSR_IRQ:
+ write_sysreg(v, spsr_irq);
+ case KVM_SPSR_FIQ:
+ write_sysreg(v, spsr_fiq);
+ }
}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 50a43c7b97ca..806b0b126a64 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -35,6 +35,7 @@
#include <asm/kvm_coproc.h>
#include <asm/kvm_emulate.h>
#include <asm/kvm_host.h>
+#include <asm/kvm_hyp.h>
#include <asm/kvm_mmu.h>
#include <asm/perf_event.h>
#include <asm/sysreg.h>
@@ -76,6 +77,93 @@ static bool write_to_read_only(struct kvm_vcpu *vcpu,
return false;
}
+u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg)
+{
+ if (!vcpu->arch.sysregs_loaded_on_cpu)
+ goto immediate_read;
+
+ /*
+ * System registers listed in the switch are not saved on every
+ * exit from the guest but are only saved on vcpu_put.
+ *
+ * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
+ * should never be listed below, because the guest cannot modify its
+ * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
+ * thread when emulating cross-VCPU communication.
+ */
+ switch (reg) {
+ case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1);
+ case SCTLR_EL1: return read_sysreg_s(sctlr_EL12);
+ case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1);
+ case CPACR_EL1: return read_sysreg_s(cpacr_EL12);
+ case TTBR0_EL1: return read_sysreg_s(ttbr0_EL12);
+ case TTBR1_EL1: return read_sysreg_s(ttbr1_EL12);
+ case TCR_EL1: return read_sysreg_s(tcr_EL12);
+ case ESR_EL1: return read_sysreg_s(esr_EL12);
+ case AFSR0_EL1: return read_sysreg_s(afsr0_EL12);
+ case AFSR1_EL1: return read_sysreg_s(afsr1_EL12);
+ case FAR_EL1: return read_sysreg_s(far_EL12);
+ case MAIR_EL1: return read_sysreg_s(mair_EL12);
+ case VBAR_EL1: return read_sysreg_s(vbar_EL12);
+ case CONTEXTIDR_EL1: return read_sysreg_s(contextidr_EL12);
+ case TPIDR_EL0: return read_sysreg_s(SYS_TPIDR_EL0);
+ case TPIDRRO_EL0: return read_sysreg_s(SYS_TPIDRRO_EL0);
+ case TPIDR_EL1: return read_sysreg_s(SYS_TPIDR_EL1);
+ case AMAIR_EL1: return read_sysreg_s(amair_EL12);
+ case CNTKCTL_EL1: return read_sysreg_s(cntkctl_EL12);
+ case PAR_EL1: return read_sysreg_s(SYS_PAR_EL1);
+ case DACR32_EL2: return read_sysreg_s(SYS_DACR32_EL2);
+ case IFSR32_EL2: return read_sysreg_s(SYS_IFSR32_EL2);
+ case DBGVCR32_EL2: return read_sysreg_s(SYS_DBGVCR32_EL2);
+ }
+
+immediate_read:
+ return __vcpu_sys_reg(vcpu, reg);
+}
+
+void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
+{
+ if (!vcpu->arch.sysregs_loaded_on_cpu)
+ goto immediate_write;
+
+ /*
+ * System registers listed in the switch are not restored on every
+ * entry to the guest but are only restored on vcpu_load.
+ *
+ * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
+ * should never be listed below, because the the MPIDR should only be
+ * set once, before running the VCPU, and never changed later.
+ */
+ switch (reg) {
+ case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return;
+ case SCTLR_EL1: write_sysreg_s(val, sctlr_EL12); return;
+ case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return;
+ case CPACR_EL1: write_sysreg_s(val, cpacr_EL12); return;
+ case TTBR0_EL1: write_sysreg_s(val, ttbr0_EL12); return;
+ case TTBR1_EL1: write_sysreg_s(val, ttbr1_EL12); return;
+ case TCR_EL1: write_sysreg_s(val, tcr_EL12); return;
+ case ESR_EL1: write_sysreg_s(val, esr_EL12); return;
+ case AFSR0_EL1: write_sysreg_s(val, afsr0_EL12); return;
+ case AFSR1_EL1: write_sysreg_s(val, afsr1_EL12); return;
+ case FAR_EL1: write_sysreg_s(val, far_EL12); return;
+ case MAIR_EL1: write_sysreg_s(val, mair_EL12); return;
+ case VBAR_EL1: write_sysreg_s(val, vbar_EL12); return;
+ case CONTEXTIDR_EL1: write_sysreg_s(val, contextidr_EL12); return;
+ case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); return;
+ case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); return;
+ case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); return;
+ case AMAIR_EL1: write_sysreg_s(val, amair_EL12); return;
+ case CNTKCTL_EL1: write_sysreg_s(val, cntkctl_EL12); return;
+ case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); return;
+ case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); return;
+ case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); return;
+ case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); return;
+ }
+
+immediate_write:
+ __vcpu_sys_reg(vcpu, reg) = val;
+}
+
/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
static u32 cache_levels;
@@ -121,16 +209,26 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
bool was_enabled = vcpu_has_cache_enabled(vcpu);
+ u64 val;
+ int reg = r->reg;
BUG_ON(!p->is_write);
- if (!p->is_aarch32) {
- vcpu_sys_reg(vcpu, r->reg) = p->regval;
+ /* See the 32bit mapping in kvm_host.h */
+ if (p->is_aarch32)
+ reg = r->reg / 2;
+
+ if (!p->is_aarch32 || !p->is_32bit) {
+ val = p->regval;
} else {
- if (!p->is_32bit)
- vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
- vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
+ val = vcpu_read_sys_reg(vcpu, reg);
+ if (r->reg % 2)
+ val = (p->regval << 32) | (u64)lower_32_bits(val);
+ else
+ val = ((u64)upper_32_bits(val) << 32) |
+ lower_32_bits(p->regval);
}
+ vcpu_write_sys_reg(vcpu, val, reg);
kvm_toggle_cache(vcpu, was_enabled);
return true;
@@ -175,6 +273,14 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
return read_zero(vcpu, p);
}
+static bool trap_undef(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ kvm_inject_undefined(vcpu);
+ return false;
+}
+
static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
@@ -231,10 +337,10 @@ static bool trap_debug_regs(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
if (p->is_write) {
- vcpu_sys_reg(vcpu, r->reg) = p->regval;
+ vcpu_write_sys_reg(vcpu, p->regval, r->reg);
vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
} else {
- p->regval = vcpu_sys_reg(vcpu, r->reg);
+ p->regval = vcpu_read_sys_reg(vcpu, r->reg);
}
trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
@@ -447,7 +553,8 @@ static void reset_wcr(struct kvm_vcpu *vcpu,
static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
- vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
+ u64 amair = read_sysreg(amair_el1);
+ vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
}
static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
@@ -464,7 +571,7 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
- vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
+ vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
}
static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
@@ -478,12 +585,12 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
*/
val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
| (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
- vcpu_sys_reg(vcpu, PMCR_EL0) = val;
+ __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
}
static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
{
- u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+ u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
if (!enabled)
@@ -525,14 +632,14 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (p->is_write) {
/* Only update writeable bits of PMCR */
- val = vcpu_sys_reg(vcpu, PMCR_EL0);
+ val = __vcpu_sys_reg(vcpu, PMCR_EL0);
val &= ~ARMV8_PMU_PMCR_MASK;
val |= p->regval & ARMV8_PMU_PMCR_MASK;
- vcpu_sys_reg(vcpu, PMCR_EL0) = val;
+ __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
kvm_pmu_handle_pmcr(vcpu, val);
} else {
/* PMCR.P & PMCR.C are RAZ */
- val = vcpu_sys_reg(vcpu, PMCR_EL0)
+ val = __vcpu_sys_reg(vcpu, PMCR_EL0)
& ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
p->regval = val;
}
@@ -550,10 +657,10 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return false;
if (p->is_write)
- vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
+ __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
else
/* return PMSELR.SEL field */
- p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
+ p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
& ARMV8_PMU_COUNTER_MASK;
return true;
@@ -586,7 +693,7 @@ static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
{
u64 pmcr, val;
- pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+ pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
kvm_inject_undefined(vcpu);
@@ -611,7 +718,7 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
if (pmu_access_event_counter_el0_disabled(vcpu))
return false;
- idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
+ idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
& ARMV8_PMU_COUNTER_MASK;
} else if (r->Op2 == 0) {
/* PMCCNTR_EL0 */
@@ -666,7 +773,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
/* PMXEVTYPER_EL0 */
- idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
+ idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
reg = PMEVTYPER0_EL0 + idx;
} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
@@ -684,9 +791,9 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (p->is_write) {
kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
- vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
+ __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
} else {
- p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
+ p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
}
return true;
@@ -708,15 +815,15 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
val = p->regval & mask;
if (r->Op2 & 0x1) {
/* accessing PMCNTENSET_EL0 */
- vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
+ __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
kvm_pmu_enable_counter(vcpu, val);
} else {
/* accessing PMCNTENCLR_EL0 */
- vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
+ __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
kvm_pmu_disable_counter(vcpu, val);
}
} else {
- p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
+ p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
}
return true;
@@ -740,12 +847,12 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (r->Op2 & 0x1)
/* accessing PMINTENSET_EL1 */
- vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
+ __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
else
/* accessing PMINTENCLR_EL1 */
- vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
+ __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
} else {
- p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
+ p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
}
return true;
@@ -765,12 +872,12 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (p->is_write) {
if (r->CRm & 0x2)
/* accessing PMOVSSET_EL0 */
- vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
+ __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
else
/* accessing PMOVSCLR_EL0 */
- vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
+ __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
} else {
- p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
+ p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
}
return true;
@@ -807,10 +914,10 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return false;
}
- vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
- & ARMV8_PMU_USERENR_MASK;
+ __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
+ p->regval & ARMV8_PMU_USERENR_MASK;
} else {
- p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
+ p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
& ARMV8_PMU_USERENR_MASK;
}
@@ -893,6 +1000,12 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)
task_pid_nr(current));
val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
+ } else if (id == SYS_ID_AA64MMFR1_EL1) {
+ if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
+ pr_err_once("kvm [%i]: LORegions unsupported for guests, suppressing\n",
+ task_pid_nr(current));
+
+ val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
}
return val;
@@ -1178,6 +1291,12 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
+ { SYS_DESC(SYS_LORSA_EL1), trap_undef },
+ { SYS_DESC(SYS_LOREA_EL1), trap_undef },
+ { SYS_DESC(SYS_LORN_EL1), trap_undef },
+ { SYS_DESC(SYS_LORC_EL1), trap_undef },
+ { SYS_DESC(SYS_LORID_EL1), trap_undef },
+
{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
@@ -1545,6 +1664,11 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
+ /* CNTP_TVAL */
+ { Op1( 0), CRn(14), CRm( 2), Op2( 0), access_cntp_tval },
+ /* CNTP_CTL */
+ { Op1( 0), CRn(14), CRm( 2), Op2( 1), access_cntp_ctl },
+
/* PMEVCNTRn */
PMU_PMEVCNTR(0),
PMU_PMEVCNTR(1),
@@ -1618,6 +1742,7 @@ static const struct sys_reg_desc cp15_64_regs[] = {
{ Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
+ { Op1( 2), CRn( 0), CRm(14), Op2( 0), access_cntp_cval },
};
/* Target specific emulation tables */
@@ -2194,7 +2319,7 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg
if (r->get_user)
return (r->get_user)(vcpu, r, reg, uaddr);
- return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
+ return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
}
int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
@@ -2215,7 +2340,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg
if (r->set_user)
return (r->set_user)(vcpu, r, reg, uaddr);
- return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
+ return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
}
static unsigned int num_demux_regs(void)
@@ -2421,6 +2546,6 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
reset_sys_reg_descs(vcpu, table, num);
for (num = 1; num < NR_SYS_REGS; num++)
- if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
- panic("Didn't reset vcpu_sys_reg(%zi)", num);
+ if (__vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
+ panic("Didn't reset __vcpu_sys_reg(%zi)", num);
}
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index 060f5348ef25..cd710f8b63e0 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -89,14 +89,14 @@ static inline void reset_unknown(struct kvm_vcpu *vcpu,
{
BUG_ON(!r->reg);
BUG_ON(r->reg >= NR_SYS_REGS);
- vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
+ __vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
}
static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
BUG_ON(!r->reg);
BUG_ON(r->reg >= NR_SYS_REGS);
- vcpu_sys_reg(vcpu, r->reg) = r->val;
+ __vcpu_sys_reg(vcpu, r->reg) = r->val;
}
static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c b/arch/arm64/kvm/sys_regs_generic_v8.c
index 969ade1d333d..ddb8497d18d6 100644
--- a/arch/arm64/kvm/sys_regs_generic_v8.c
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -38,13 +38,13 @@ static bool access_actlr(struct kvm_vcpu *vcpu,
if (p->is_write)
return ignore_write(vcpu, p);
- p->regval = vcpu_sys_reg(vcpu, ACTLR_EL1);
+ p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);
return true;
}
static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
- vcpu_sys_reg(vcpu, ACTLR_EL1) = read_sysreg(actlr_el1);
+ __vcpu_sys_reg(vcpu, ACTLR_EL1) = read_sysreg(actlr_el1);
}
/*
diff --git a/arch/arm64/kvm/va_layout.c b/arch/arm64/kvm/va_layout.c
new file mode 100644
index 000000000000..c712a7376bc1
--- /dev/null
+++ b/arch/arm64/kvm/va_layout.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2017 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm_host.h>
+#include <linux/random.h>
+#include <linux/memblock.h>
+#include <asm/alternative.h>
+#include <asm/debug-monitors.h>
+#include <asm/insn.h>
+#include <asm/kvm_mmu.h>
+
+/*
+ * The LSB of the random hyp VA tag or 0 if no randomization is used.
+ */
+static u8 tag_lsb;
+/*
+ * The random hyp VA tag value with the region bit if hyp randomization is used
+ */
+static u64 tag_val;
+static u64 va_mask;
+
+static void compute_layout(void)
+{
+ phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
+ u64 hyp_va_msb;
+ int kva_msb;
+
+ /* Where is my RAM region? */
+ hyp_va_msb = idmap_addr & BIT(VA_BITS - 1);
+ hyp_va_msb ^= BIT(VA_BITS - 1);
+
+ kva_msb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
+ (u64)(high_memory - 1));
+
+ if (kva_msb == (VA_BITS - 1)) {
+ /*
+ * No space in the address, let's compute the mask so
+ * that it covers (VA_BITS - 1) bits, and the region
+ * bit. The tag stays set to zero.
+ */
+ va_mask = BIT(VA_BITS - 1) - 1;
+ va_mask |= hyp_va_msb;
+ } else {
+ /*
+ * We do have some free bits to insert a random tag.
+ * Hyp VAs are now created from kernel linear map VAs
+ * using the following formula (with V == VA_BITS):
+ *
+ * 63 ... V | V-1 | V-2 .. tag_lsb | tag_lsb - 1 .. 0
+ * ---------------------------------------------------------
+ * | 0000000 | hyp_va_msb | random tag | kern linear VA |
+ */
+ tag_lsb = kva_msb;
+ va_mask = GENMASK_ULL(tag_lsb - 1, 0);
+ tag_val = get_random_long() & GENMASK_ULL(VA_BITS - 2, tag_lsb);
+ tag_val |= hyp_va_msb;
+ tag_val >>= tag_lsb;
+ }
+}
+
+static u32 compute_instruction(int n, u32 rd, u32 rn)
+{
+ u32 insn = AARCH64_BREAK_FAULT;
+
+ switch (n) {
+ case 0:
+ insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
+ AARCH64_INSN_VARIANT_64BIT,
+ rn, rd, va_mask);
+ break;
+
+ case 1:
+ /* ROR is a variant of EXTR with Rm = Rn */
+ insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
+ rn, rn, rd,
+ tag_lsb);
+ break;
+
+ case 2:
+ insn = aarch64_insn_gen_add_sub_imm(rd, rn,
+ tag_val & GENMASK(11, 0),
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_ADSB_ADD);
+ break;
+
+ case 3:
+ insn = aarch64_insn_gen_add_sub_imm(rd, rn,
+ tag_val & GENMASK(23, 12),
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_ADSB_ADD);
+ break;
+
+ case 4:
+ /* ROR is a variant of EXTR with Rm = Rn */
+ insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
+ rn, rn, rd, 64 - tag_lsb);
+ break;
+ }
+
+ return insn;
+}
+
+void __init kvm_update_va_mask(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr, int nr_inst)
+{
+ int i;
+
+ BUG_ON(nr_inst != 5);
+
+ if (!has_vhe() && !va_mask)
+ compute_layout();
+
+ for (i = 0; i < nr_inst; i++) {
+ u32 rd, rn, insn, oinsn;
+
+ /*
+ * VHE doesn't need any address translation, let's NOP
+ * everything.
+ *
+ * Alternatively, if we don't have any spare bits in
+ * the address, NOP everything after masking that
+ * kernel VA.
+ */
+ if (has_vhe() || (!tag_lsb && i > 0)) {
+ updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
+ continue;
+ }
+
+ oinsn = le32_to_cpu(origptr[i]);
+ rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
+ rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
+
+ insn = compute_instruction(i, rd, rn);
+ BUG_ON(insn == AARCH64_BREAK_FAULT);
+
+ updptr[i] = cpu_to_le32(insn);
+ }
+}
+
+void *__kvm_bp_vect_base;
+int __kvm_harden_el2_vector_slot;
+
+void kvm_patch_vector_branch(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr, int nr_inst)
+{
+ u64 addr;
+ u32 insn;
+
+ BUG_ON(nr_inst != 5);
+
+ if (has_vhe() || !cpus_have_const_cap(ARM64_HARDEN_EL2_VECTORS)) {
+ WARN_ON_ONCE(cpus_have_const_cap(ARM64_HARDEN_EL2_VECTORS));
+ return;
+ }
+
+ if (!va_mask)
+ compute_layout();
+
+ /*
+ * Compute HYP VA by using the same computation as kern_hyp_va()
+ */
+ addr = (uintptr_t)kvm_ksym_ref(__kvm_hyp_vector);
+ addr &= va_mask;
+ addr |= tag_val << tag_lsb;
+
+ /* Use PC[10:7] to branch to the same vector in KVM */
+ addr |= ((u64)origptr & GENMASK_ULL(10, 7));
+
+ /*
+ * Branch to the second instruction in the vectors in order to
+ * avoid the initial store on the stack (which we already
+ * perform in the hardening vectors).
+ */
+ addr += AARCH64_INSN_SIZE;
+
+ /* stp x0, x1, [sp, #-16]! */
+ insn = aarch64_insn_gen_load_store_pair(AARCH64_INSN_REG_0,
+ AARCH64_INSN_REG_1,
+ AARCH64_INSN_REG_SP,
+ -16,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX);
+ *updptr++ = cpu_to_le32(insn);
+
+ /* movz x0, #(addr & 0xffff) */
+ insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
+ (u16)addr,
+ 0,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_MOVEWIDE_ZERO);
+ *updptr++ = cpu_to_le32(insn);
+
+ /* movk x0, #((addr >> 16) & 0xffff), lsl #16 */
+ insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
+ (u16)(addr >> 16),
+ 16,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_MOVEWIDE_KEEP);
+ *updptr++ = cpu_to_le32(insn);
+
+ /* movk x0, #((addr >> 32) & 0xffff), lsl #32 */
+ insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
+ (u16)(addr >> 32),
+ 32,
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_MOVEWIDE_KEEP);
+ *updptr++ = cpu_to_le32(insn);
+
+ /* br x0 */
+ insn = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_0,
+ AARCH64_INSN_BRANCH_NOLINK);
+ *updptr++ = cpu_to_le32(insn);
+}
diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile
index 4e696f96451f..0ead8a1d1679 100644
--- a/arch/arm64/lib/Makefile
+++ b/arch/arm64/lib/Makefile
@@ -17,6 +17,7 @@ CFLAGS_atomic_ll_sc.o := -fcall-used-x0 -ffixed-x1 -ffixed-x2 \
-ffixed-x7 -fcall-saved-x8 -fcall-saved-x9 \
-fcall-saved-x10 -fcall-saved-x11 -fcall-saved-x12 \
-fcall-saved-x13 -fcall-saved-x14 -fcall-saved-x15 \
- -fcall-saved-x18
+ -fcall-saved-x18 -fomit-frame-pointer
+CFLAGS_REMOVE_atomic_ll_sc.o := -pg
lib-$(CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE) += uaccess_flushcache.o
diff --git a/arch/arm64/lib/strrchr.S b/arch/arm64/lib/strrchr.S
index 61eabd9a289a..f8e2784d5752 100644
--- a/arch/arm64/lib/strrchr.S
+++ b/arch/arm64/lib/strrchr.S
@@ -40,4 +40,4 @@ ENTRY(strrchr)
b 1b
2: mov x0, x3
ret
-ENDPROC(strrchr)
+ENDPIPROC(strrchr)
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 758bde7e2fa6..30334d81b021 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -50,6 +50,10 @@ ENTRY(flush_icache_range)
*/
ENTRY(__flush_cache_user_range)
uaccess_ttbr0_enable x2, x3, x4
+alternative_if ARM64_HAS_CACHE_IDC
+ dsb ishst
+ b 7f
+alternative_else_nop_endif
dcache_line_size x2, x3
sub x3, x2, #1
bic x4, x0, x3
@@ -60,8 +64,13 @@ user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
b.lo 1b
dsb ish
+7:
+alternative_if ARM64_HAS_CACHE_DIC
+ isb
+ b 8f
+alternative_else_nop_endif
invalidate_icache_by_line x0, x1, x2, x3, 9f
- mov x0, #0
+8: mov x0, #0
1:
uaccess_ttbr0_disable x1, x2
ret
@@ -80,6 +89,12 @@ ENDPROC(__flush_cache_user_range)
* - end - virtual end address of region
*/
ENTRY(invalidate_icache_range)
+alternative_if ARM64_HAS_CACHE_DIC
+ mov x0, xzr
+ isb
+ ret
+alternative_else_nop_endif
+
uaccess_ttbr0_enable x2, x3, x4
invalidate_icache_by_line x0, x1, x2, x3, 2f
@@ -116,6 +131,10 @@ ENDPIPROC(__flush_dcache_area)
* - size - size in question
*/
ENTRY(__clean_dcache_area_pou)
+alternative_if ARM64_HAS_CACHE_IDC
+ dsb ishst
+ ret
+alternative_else_nop_endif
dcache_by_line_op cvau, ish, x0, x1, x2, x3
ret
ENDPROC(__clean_dcache_area_pou)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index bff11553eb05..4165485e8b6e 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -43,6 +43,7 @@
#include <asm/system_misc.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
+#include <asm/traps.h>
#include <acpi/ghes.h>
@@ -289,58 +290,31 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr,
do_exit(SIGKILL);
}
-static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
- unsigned int esr, unsigned int sig, int code,
- struct pt_regs *regs, int fault)
+static void __do_user_fault(struct siginfo *info, unsigned int esr)
{
- struct siginfo si;
- const struct fault_info *inf;
- unsigned int lsb = 0;
-
- if (unhandled_signal(tsk, sig) && show_unhandled_signals_ratelimited()) {
- inf = esr_to_fault_info(esr);
- pr_info("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x",
- tsk->comm, task_pid_nr(tsk), inf->name, sig,
- addr, esr);
- print_vma_addr(KERN_CONT ", in ", regs->pc);
- pr_cont("\n");
- __show_regs(regs);
- }
-
- tsk->thread.fault_address = addr;
- tsk->thread.fault_code = esr;
- si.si_signo = sig;
- si.si_errno = 0;
- si.si_code = code;
- si.si_addr = (void __user *)addr;
- /*
- * Either small page or large page may be poisoned.
- * In other words, VM_FAULT_HWPOISON_LARGE and
- * VM_FAULT_HWPOISON are mutually exclusive.
- */
- if (fault & VM_FAULT_HWPOISON_LARGE)
- lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
- else if (fault & VM_FAULT_HWPOISON)
- lsb = PAGE_SHIFT;
- si.si_addr_lsb = lsb;
-
- force_sig_info(sig, &si, tsk);
+ current->thread.fault_address = (unsigned long)info->si_addr;
+ current->thread.fault_code = esr;
+ arm64_force_sig_info(info, esr_to_fault_info(esr)->name, current);
}
static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
{
- struct task_struct *tsk = current;
- const struct fault_info *inf;
-
/*
* If we are in kernel mode at this point, we have no context to
* handle this fault with.
*/
if (user_mode(regs)) {
- inf = esr_to_fault_info(esr);
- __do_user_fault(tsk, addr, esr, inf->sig, inf->code, regs, 0);
- } else
+ const struct fault_info *inf = esr_to_fault_info(esr);
+ struct siginfo si = {
+ .si_signo = inf->sig,
+ .si_code = inf->code,
+ .si_addr = (void __user *)addr,
+ };
+
+ __do_user_fault(&si, esr);
+ } else {
__do_kernel_fault(addr, esr, regs);
+ }
}
#define VM_FAULT_BADMAP 0x010000
@@ -393,7 +367,8 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
{
struct task_struct *tsk;
struct mm_struct *mm;
- int fault, sig, code, major = 0;
+ struct siginfo si;
+ int fault, major = 0;
unsigned long vm_flags = VM_READ | VM_WRITE;
unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
@@ -525,27 +500,37 @@ retry:
return 0;
}
+ clear_siginfo(&si);
+ si.si_addr = (void __user *)addr;
+
if (fault & VM_FAULT_SIGBUS) {
/*
* We had some memory, but were unable to successfully fix up
* this page fault.
*/
- sig = SIGBUS;
- code = BUS_ADRERR;
- } else if (fault & (VM_FAULT_HWPOISON | VM_FAULT_HWPOISON_LARGE)) {
- sig = SIGBUS;
- code = BUS_MCEERR_AR;
+ si.si_signo = SIGBUS;
+ si.si_code = BUS_ADRERR;
+ } else if (fault & VM_FAULT_HWPOISON_LARGE) {
+ unsigned int hindex = VM_FAULT_GET_HINDEX(fault);
+
+ si.si_signo = SIGBUS;
+ si.si_code = BUS_MCEERR_AR;
+ si.si_addr_lsb = hstate_index_to_shift(hindex);
+ } else if (fault & VM_FAULT_HWPOISON) {
+ si.si_signo = SIGBUS;
+ si.si_code = BUS_MCEERR_AR;
+ si.si_addr_lsb = PAGE_SHIFT;
} else {
/*
* Something tried to access memory that isn't in our memory
* map.
*/
- sig = SIGSEGV;
- code = fault == VM_FAULT_BADACCESS ?
- SEGV_ACCERR : SEGV_MAPERR;
+ si.si_signo = SIGSEGV;
+ si.si_code = fault == VM_FAULT_BADACCESS ?
+ SEGV_ACCERR : SEGV_MAPERR;
}
- __do_user_fault(tsk, addr, esr, sig, code, regs, fault);
+ __do_user_fault(&si, esr);
return 0;
no_context:
@@ -582,8 +567,6 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
const struct fault_info *inf;
inf = esr_to_fault_info(esr);
- pr_err("Synchronous External Abort: %s (0x%08x) at 0x%016lx\n",
- inf->name, esr, addr);
/*
* Synchronous aborts may interrupt code which had interrupts masked.
@@ -600,83 +583,83 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
nmi_exit();
}
- info.si_signo = SIGBUS;
+ info.si_signo = inf->sig;
info.si_errno = 0;
- info.si_code = BUS_FIXME;
+ info.si_code = inf->code;
if (esr & ESR_ELx_FnV)
info.si_addr = NULL;
else
info.si_addr = (void __user *)addr;
- arm64_notify_die("", regs, &info, esr);
+ arm64_notify_die(inf->name, regs, &info, esr);
return 0;
}
static const struct fault_info fault_info[] = {
- { do_bad, SIGBUS, BUS_FIXME, "ttbr address size fault" },
- { do_bad, SIGBUS, BUS_FIXME, "level 1 address size fault" },
- { do_bad, SIGBUS, BUS_FIXME, "level 2 address size fault" },
- { do_bad, SIGBUS, BUS_FIXME, "level 3 address size fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 8" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 8" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 12" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 12" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
- { do_sea, SIGBUS, BUS_FIXME, "synchronous external abort" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 17" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 18" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 19" },
- { do_sea, SIGBUS, BUS_FIXME, "level 0 (translation table walk)" },
- { do_sea, SIGBUS, BUS_FIXME, "level 1 (translation table walk)" },
- { do_sea, SIGBUS, BUS_FIXME, "level 2 (translation table walk)" },
- { do_sea, SIGBUS, BUS_FIXME, "level 3 (translation table walk)" },
- { do_sea, SIGBUS, BUS_FIXME, "synchronous parity or ECC error" }, // Reserved when RAS is implemented
- { do_bad, SIGBUS, BUS_FIXME, "unknown 25" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 26" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 27" },
- { do_sea, SIGBUS, BUS_FIXME, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
- { do_sea, SIGBUS, BUS_FIXME, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
- { do_sea, SIGBUS, BUS_FIXME, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
- { do_sea, SIGBUS, BUS_FIXME, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
- { do_bad, SIGBUS, BUS_FIXME, "unknown 32" },
+ { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 17" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 18" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 19" },
+ { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" },
+ { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" },
+ { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" },
+ { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" },
+ { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 25" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 26" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 27" },
+ { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
+ { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
+ { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
+ { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 32" },
{ do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 34" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 35" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 36" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 37" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 38" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 39" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 40" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 41" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 42" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 43" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 44" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 45" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 46" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 47" },
- { do_bad, SIGBUS, BUS_FIXME, "TLB conflict abort" },
- { do_bad, SIGBUS, BUS_FIXME, "Unsupported atomic hardware update fault" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 50" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 51" },
- { do_bad, SIGBUS, BUS_FIXME, "implementation fault (lockdown abort)" },
- { do_bad, SIGBUS, BUS_FIXME, "implementation fault (unsupported exclusive)" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 54" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 55" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 56" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 57" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 58" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 59" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 60" },
- { do_bad, SIGBUS, BUS_FIXME, "section domain fault" },
- { do_bad, SIGBUS, BUS_FIXME, "page domain fault" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 63" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 34" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 35" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 36" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 37" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 38" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 39" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 40" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 41" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 42" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 43" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 44" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 45" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 46" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 47" },
+ { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" },
+ { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 50" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 51" },
+ { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" },
+ { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 54" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 55" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 56" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 57" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 58" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 59" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 60" },
+ { do_bad, SIGKILL, SI_KERNEL, "section domain fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "page domain fault" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 63" },
};
int handle_guest_sea(phys_addr_t addr, unsigned int esr)
@@ -698,19 +681,17 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr,
if (!inf->fn(addr, esr, regs))
return;
- pr_alert("Unhandled fault: %s at 0x%016lx\n",
- inf->name, addr);
-
- mem_abort_decode(esr);
-
- if (!user_mode(regs))
+ if (!user_mode(regs)) {
+ pr_alert("Unhandled fault at 0x%016lx\n", addr);
+ mem_abort_decode(esr);
show_pte(addr);
+ }
info.si_signo = inf->sig;
info.si_errno = 0;
info.si_code = inf->code;
info.si_addr = (void __user *)addr;
- arm64_notify_die("", regs, &info, esr);
+ arm64_notify_die(inf->name, regs, &info, esr);
}
asmlinkage void __exception do_el0_irq_bp_hardening(void)
@@ -741,7 +722,6 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr,
struct pt_regs *regs)
{
struct siginfo info;
- struct task_struct *tsk = current;
if (user_mode(regs)) {
if (instruction_pointer(regs) > TASK_SIZE)
@@ -749,17 +729,11 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr,
local_irq_enable();
}
- if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS))
- pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n",
- tsk->comm, task_pid_nr(tsk),
- esr_get_class_string(esr), (void *)regs->pc,
- (void *)regs->sp);
-
info.si_signo = SIGBUS;
info.si_errno = 0;
info.si_code = BUS_ADRALN;
info.si_addr = (void __user *)addr;
- arm64_notify_die("Oops - SP/PC alignment exception", regs, &info, esr);
+ arm64_notify_die("SP/PC alignment exception", regs, &info, esr);
}
int __init early_brk64(unsigned long addr, unsigned int esr,
@@ -774,11 +748,11 @@ static struct fault_info __refdata debug_fault_info[] = {
{ do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" },
{ do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" },
{ do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 3" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 3" },
{ do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" },
- { do_bad, SIGTRAP, TRAP_FIXME, "aarch32 vector catch" },
+ { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" },
{ early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" },
- { do_bad, SIGBUS, BUS_FIXME, "unknown 7" },
+ { do_bad, SIGKILL, SI_KERNEL, "unknown 7" },
};
void __init hook_debug_fault_code(int nr,
@@ -814,14 +788,11 @@ asmlinkage int __exception do_debug_exception(unsigned long addr,
if (!inf->fn(addr, esr, regs)) {
rv = 1;
} else {
- pr_alert("Unhandled debug exception: %s (0x%08x) at 0x%016lx\n",
- inf->name, esr, addr);
-
info.si_signo = inf->sig;
info.si_errno = 0;
info.si_code = inf->code;
info.si_addr = (void __user *)addr;
- arm64_notify_die("", regs, &info, 0);
+ arm64_notify_die(inf->name, regs, &info, esr);
rv = 0;
}
@@ -833,7 +804,7 @@ asmlinkage int __exception do_debug_exception(unsigned long addr,
NOKPROBE_SYMBOL(do_debug_exception);
#ifdef CONFIG_ARM64_PAN
-int cpu_enable_pan(void *__unused)
+void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
{
/*
* We modify PSTATE. This won't work from irq context as the PSTATE
@@ -843,6 +814,5 @@ int cpu_enable_pan(void *__unused)
config_sctlr_el1(SCTLR_EL1_SPAN, 0);
asm(SET_PSTATE_PAN(1));
- return 0;
}
#endif /* CONFIG_ARM64_PAN */
diff --git a/arch/arm64/mm/mmap.c b/arch/arm64/mm/mmap.c
index decccffb03ca..842c8a5fcd53 100644
--- a/arch/arm64/mm/mmap.c
+++ b/arch/arm64/mm/mmap.c
@@ -38,12 +38,12 @@
#define MIN_GAP (SZ_128M)
#define MAX_GAP (STACK_TOP/6*5)
-static int mmap_is_legacy(void)
+static int mmap_is_legacy(struct rlimit *rlim_stack)
{
if (current->personality & ADDR_COMPAT_LAYOUT)
return 1;
- if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
+ if (rlim_stack->rlim_cur == RLIM_INFINITY)
return 1;
return sysctl_legacy_va_layout;
@@ -62,9 +62,9 @@ unsigned long arch_mmap_rnd(void)
return rnd << PAGE_SHIFT;
}
-static unsigned long mmap_base(unsigned long rnd)
+static unsigned long mmap_base(unsigned long rnd, struct rlimit *rlim_stack)
{
- unsigned long gap = rlimit(RLIMIT_STACK);
+ unsigned long gap = rlim_stack->rlim_cur;
unsigned long pad = (STACK_RND_MASK << PAGE_SHIFT) + stack_guard_gap;
/* Values close to RLIM_INFINITY can overflow. */
@@ -83,7 +83,7 @@ static unsigned long mmap_base(unsigned long rnd)
* This function, called very early during the creation of a new process VM
* image, sets up which VM layout function to use:
*/
-void arch_pick_mmap_layout(struct mm_struct *mm)
+void arch_pick_mmap_layout(struct mm_struct *mm, struct rlimit *rlim_stack)
{
unsigned long random_factor = 0UL;
@@ -94,11 +94,11 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
* Fall back to the standard layout if the personality bit is set, or
* if the expected stack growth is unlimited:
*/
- if (mmap_is_legacy()) {
+ if (mmap_is_legacy(rlim_stack)) {
mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
mm->get_unmapped_area = arch_get_unmapped_area;
} else {
- mm->mmap_base = mmap_base(random_factor);
+ mm->mmap_base = mmap_base(random_factor, rlim_stack);
mm->get_unmapped_area = arch_get_unmapped_area_topdown;
}
}
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index c0af47617299..5f9a73a4452c 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -36,6 +36,12 @@
#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
#endif
+#ifdef CONFIG_RANDOMIZE_BASE
+#define TCR_KASLR_FLAGS TCR_NFD1
+#else
+#define TCR_KASLR_FLAGS 0
+#endif
+
#define TCR_SMP_FLAGS TCR_SHARED
/* PTWs cacheable, inner/outer WBWA */
@@ -432,7 +438,8 @@ ENTRY(__cpu_setup)
* both user and kernel.
*/
ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
- TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1
+ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
+ TCR_TBI0 | TCR_A1
tcr_set_idmap_t0sz x10, x9
/*
@@ -441,16 +448,15 @@ ENTRY(__cpu_setup)
tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
#ifdef CONFIG_ARM64_HW_AFDBM
/*
- * Hardware update of the Access and Dirty bits.
+ * Enable hardware update of the Access Flags bit.
+ * Hardware dirty bit management is enabled later,
+ * via capabilities.
*/
mrs x9, ID_AA64MMFR1_EL1
and x9, x9, #0xf
- cbz x9, 2f
- cmp x9, #2
- b.lt 1f
- orr x10, x10, #TCR_HD // hardware Dirty flag update
-1: orr x10, x10, #TCR_HA // hardware Access flag update
-2:
+ cbz x9, 1f
+ orr x10, x10, #TCR_HA // hardware Access flag update
+1:
#endif /* CONFIG_ARM64_HW_AFDBM */
msr tcr_el1, x10
ret // return to head.S
diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt
deleted file mode 100644
index bfa4b378a368..000000000000
--- a/arch/blackfin/Clear_BSD.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-The Clear BSD license:
-
-Copyright (c) 2012, Analog Devices, Inc. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted (subject to the limitations in the
-disclaimer below) provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the
- distribution.
-
-* Neither the name of Analog Devices, Inc. nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
-NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
deleted file mode 100644
index d9c2866ba618..000000000000
--- a/arch/blackfin/Kconfig
+++ /dev/null
@@ -1,1463 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config MMU
- def_bool n
-
-config FPU
- def_bool n
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config RWSEM_XCHGADD_ALGORITHM
- def_bool n
-
-config BLACKFIN
- def_bool y
- select HAVE_ARCH_KGDB
- select HAVE_ARCH_TRACEHOOK
- select HAVE_DYNAMIC_FTRACE
- select HAVE_FTRACE_MCOUNT_RECORD
- select HAVE_FUNCTION_GRAPH_TRACER
- select HAVE_FUNCTION_TRACER
- select HAVE_IDE
- select HAVE_KERNEL_GZIP if RAMKERNEL
- select HAVE_KERNEL_BZIP2 if RAMKERNEL
- select HAVE_KERNEL_LZMA if RAMKERNEL
- select HAVE_KERNEL_LZO if RAMKERNEL
- select HAVE_OPROFILE
- select HAVE_PERF_EVENTS
- select ARCH_HAVE_CUSTOM_GPIO_H
- select GPIOLIB
- select HAVE_UID16
- select HAVE_UNDERSCORE_SYMBOL_PREFIX
- select VIRT_TO_BUS
- select ARCH_WANT_IPC_PARSE_VERSION
- select GENERIC_ATOMIC64
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
- select GENERIC_SMP_IDLE_THREAD
- select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
- select HAVE_MOD_ARCH_SPECIFIC
- select MODULES_USE_ELF_RELA
- select HAVE_DEBUG_STACKOVERFLOW
- select HAVE_NMI
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config GENERIC_CSUM
- def_bool y
-
-config GENERIC_BUG
- def_bool y
- depends on BUG
-
-config ZONE_DMA
- def_bool y
-
-config FORCE_MAX_ZONEORDER
- int
- default "14"
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config TRACE_IRQFLAGS_SUPPORT
- def_bool y
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.preempt"
-
-source "kernel/Kconfig.freezer"
-
-menu "Blackfin Processor Options"
-
-comment "Processor and Board Settings"
-
-choice
- prompt "CPU"
- default BF533
-
-config BF512
- bool "BF512"
- help
- BF512 Processor Support.
-
-config BF514
- bool "BF514"
- help
- BF514 Processor Support.
-
-config BF516
- bool "BF516"
- help
- BF516 Processor Support.
-
-config BF518
- bool "BF518"
- help
- BF518 Processor Support.
-
-config BF522
- bool "BF522"
- help
- BF522 Processor Support.
-
-config BF523
- bool "BF523"
- help
- BF523 Processor Support.
-
-config BF524
- bool "BF524"
- help
- BF524 Processor Support.
-
-config BF525
- bool "BF525"
- help
- BF525 Processor Support.
-
-config BF526
- bool "BF526"
- help
- BF526 Processor Support.
-
-config BF527
- bool "BF527"
- help
- BF527 Processor Support.
-
-config BF531
- bool "BF531"
- help
- BF531 Processor Support.
-
-config BF532
- bool "BF532"
- help
- BF532 Processor Support.
-
-config BF533
- bool "BF533"
- help
- BF533 Processor Support.
-
-config BF534
- bool "BF534"
- help
- BF534 Processor Support.
-
-config BF536
- bool "BF536"
- help
- BF536 Processor Support.
-
-config BF537
- bool "BF537"
- help
- BF537 Processor Support.
-
-config BF538
- bool "BF538"
- help
- BF538 Processor Support.
-
-config BF539
- bool "BF539"
- help
- BF539 Processor Support.
-
-config BF542_std
- bool "BF542"
- help
- BF542 Processor Support.
-
-config BF542M
- bool "BF542m"
- help
- BF542 Processor Support.
-
-config BF544_std
- bool "BF544"
- help
- BF544 Processor Support.
-
-config BF544M
- bool "BF544m"
- help
- BF544 Processor Support.
-
-config BF547_std
- bool "BF547"
- help
- BF547 Processor Support.
-
-config BF547M
- bool "BF547m"
- help
- BF547 Processor Support.
-
-config BF548_std
- bool "BF548"
- help
- BF548 Processor Support.
-
-config BF548M
- bool "BF548m"
- help
- BF548 Processor Support.
-
-config BF549_std
- bool "BF549"
- help
- BF549 Processor Support.
-
-config BF549M
- bool "BF549m"
- help
- BF549 Processor Support.
-
-config BF561
- bool "BF561"
- help
- BF561 Processor Support.
-
-config BF609
- bool "BF609"
- select CLKDEV_LOOKUP
- help
- BF609 Processor Support.
-
-endchoice
-
-config SMP
- depends on BF561
- select TICKSOURCE_CORETMR
- bool "Symmetric multi-processing support"
- ---help---
- This enables support for systems with more than one CPU,
- like the dual core BF561. If you have a system with only one
- CPU, say N. If you have a system with more than one CPU, say Y.
-
- If you don't know what to do here, say N.
-
-config NR_CPUS
- int
- depends on SMP
- default 2 if BF561
-
-config HOTPLUG_CPU
- bool "Support for hot-pluggable CPUs"
- depends on SMP
- default y
-
-config BF_REV_MIN
- int
- default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 2 if (BF537 || BF536 || BF534)
- default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
- default 4 if (BF538 || BF539)
-
-config BF_REV_MAX
- int
- default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 3 if (BF537 || BF536 || BF534 || BF54xM)
- default 5 if (BF561 || BF538 || BF539)
- default 6 if (BF533 || BF532 || BF531)
-
-choice
- prompt "Silicon Rev"
- default BF_REV_0_0 if (BF51x || BF52x || BF60x)
- default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
- default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
-
-config BF_REV_0_0
- bool "0.0"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_1
- bool "0.1"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_2
- bool "0.2"
- depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
-
-config BF_REV_0_3
- bool "0.3"
- depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
-
-config BF_REV_0_4
- bool "0.4"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
-
-config BF_REV_0_5
- bool "0.5"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
-
-config BF_REV_0_6
- bool "0.6"
- depends on (BF533 || BF532 || BF531)
-
-config BF_REV_ANY
- bool "any"
-
-config BF_REV_NONE
- bool "none"
-
-endchoice
-
-config BF53x
- bool
- depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
- default y
-
-config GPIO_ADI
- def_bool y
- depends on !PINCTRL
- depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
-
-config PINCTRL_BLACKFIN_ADI2
- def_bool y
- depends on (BF54x || BF60x)
- select PINCTRL
- select PINCTRL_ADI2
-
-config MEM_MT48LC64M4A2FB_7E
- bool
- depends on (BFIN533_STAMP)
- default y
-
-config MEM_MT48LC16M16A2TG_75
- bool
- depends on (BFIN533_EZKIT || BFIN561_EZKIT \
- || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
- || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
- || BFIN527_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M8A2_75
- bool
- depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
- default y
-
-config MEM_MT48LC8M32B2B5_7
- bool
- depends on (BFIN561_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M16A2TG_75
- bool
- depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
- default y
-
-config MEM_MT48H32M16LFCJ_75
- bool
- depends on (BFIN526_EZBRD)
- default y
-
-config MEM_MT47H64M16
- bool
- depends on (BFIN609_EZKIT)
- default y
-
-source "arch/blackfin/mach-bf518/Kconfig"
-source "arch/blackfin/mach-bf527/Kconfig"
-source "arch/blackfin/mach-bf533/Kconfig"
-source "arch/blackfin/mach-bf561/Kconfig"
-source "arch/blackfin/mach-bf537/Kconfig"
-source "arch/blackfin/mach-bf538/Kconfig"
-source "arch/blackfin/mach-bf548/Kconfig"
-source "arch/blackfin/mach-bf609/Kconfig"
-
-menu "Board customizations"
-
-config CMDLINE_BOOL
- bool "Default bootloader kernel arguments"
-
-config CMDLINE
- string "Initial kernel command string"
- depends on CMDLINE_BOOL
- default "console=ttyBF0,57600"
- help
- If you don't have a boot loader capable of passing a command line string
- to the kernel, you may specify one here. As a minimum, you should specify
- the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
-
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
-
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
-
-config PHY_RAM_BASE_ADDRESS
- hex "Physical RAM Base"
- default 0x0
- help
- set BF609 FPGA physical SRAM base address
-
-config ROM_BASE
- hex "Kernel ROM Base"
- depends on ROMKERNEL
- default "0x20040040"
- range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
- range 0x20000000 0x30000000 if (BF54x || BF561)
- range 0xB0000000 0xC0000000 if (BF60x)
- help
- Make sure your ROM base does not include any file-header
- information that is prepended to the kernel.
-
- For example, the bootable U-Boot format (created with
- mkimage) has a 64 byte header (0x40). So while the image
- you write to flash might start at say 0x20080000, you have
- to add 0x40 to get the kernel's ROM base as it will come
- after the header.
-
-comment "Clock/PLL Setup"
-
-config CLKIN_HZ
- int "Frequency of the crystal on the board in Hz"
- default "10000000" if BFIN532_IP0X
- default "11059200" if BFIN533_STAMP
- default "24576000" if PNAV10
- default "25000000" # most people use this
- default "27000000" if BFIN533_EZKIT
- default "30000000" if BFIN561_EZKIT
- default "24000000" if BFIN527_AD7160EVAL
- help
- The frequency of CLKIN crystal oscillator on the board in Hz.
- Warning: This value should match the crystal on the board. Otherwise,
- peripherals won't work properly.
-
-config BFIN_KERNEL_CLOCK
- bool "Re-program Clocks while Kernel boots?"
- default n
- help
- This option decides if kernel clocks are re-programed from the
- bootloader settings. If the clocks are not set, the SDRAM settings
- are also not changed, and the Bootloader does 100% of the hardware
- configuration.
-
-config PLL_BYPASS
- bool "Bypass PLL"
- depends on BFIN_KERNEL_CLOCK && (!BF60x)
- default n
-
-config CLKIN_HALF
- bool "Half Clock In"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- default n
- help
- If this is set the clock will be divided by 2, before it goes to the PLL.
-
-config VCO_MULT
- int "VCO Multiplier"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- range 1 64
- default "22" if BFIN533_EZKIT
- default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
- default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
- default "20" if (BFIN561_EZKIT || BF609)
- default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
- default "25" if BFIN527_AD7160EVAL
- help
- This controls the frequency of the on-chip PLL. This can be between 1 and 64.
- PLL Frequency = (Crystal Frequency) * (this setting)
-
-choice
- prompt "Core Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- default CCLK_DIV_1
- help
- This sets the frequency of the core. It can be 1, 2, 4 or 8
- Core Frequency = (PLL frequency) / (this setting)
-
-config CCLK_DIV_1
- bool "1"
-
-config CCLK_DIV_2
- bool "2"
-
-config CCLK_DIV_4
- bool "4"
-
-config CCLK_DIV_8
- bool "8"
-endchoice
-
-config SCLK_DIV
- int "System Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- range 1 15
- default 4
- help
- This sets the frequency of the system clock (including SDRAM or DDR) on
- !BF60x else it set the clock for system buses and provides the
- source from which SCLK0 and SCLK1 are derived.
- This can be between 1 and 15
- System Clock = (PLL frequency) / (this setting)
-
-config SCLK0_DIV
- int "System Clock0 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock0 for PVP and all other
- peripherals not clocked by SCLK1.
- This can be between 1 and 15
- System Clock0 = (System Clock) / (this setting)
-
-config SCLK1_DIV
- int "System Clock1 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
- This can be between 1 and 15
- System Clock1 = (System Clock) / (this setting)
-
-config DCLK_DIV
- int "DDR Clock Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 2
- help
- This sets the frequency of the DDR memory.
- This can be between 1 and 15
- DDR Clock = (PLL frequency) / (this setting)
-
-choice
- prompt "DDR SDRAM Chip Type"
- depends on BFIN_KERNEL_CLOCK
- depends on BF54x
- default MEM_MT46V32M16_5B
-
-config MEM_MT46V32M16_6T
- bool "MT46V32M16_6T"
-
-config MEM_MT46V32M16_5B
- bool "MT46V32M16_5B"
-endchoice
-
-choice
- prompt "DDR/SDRAM Timing"
- depends on BFIN_KERNEL_CLOCK && !BF60x
- default BFIN_KERNEL_CLOCK_MEMINIT_CALC
- help
- This option allows you to specify Blackfin SDRAM/DDR Timing parameters
- The calculated SDRAM timing parameters may not be 100%
- accurate - This option is therefore marked experimental.
-
-config BFIN_KERNEL_CLOCK_MEMINIT_CALC
- bool "Calculate Timings"
-
-config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
- bool "Provide accurate Timings based on target SCLK"
- help
- Please consult the Blackfin Hardware Reference Manuals as well
- as the memory device datasheet.
- http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
-endchoice
-
-menu "Memory Init Control"
- depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
-
-config MEM_DDRCTL0
- depends on BF54x
- hex "DDRCTL0"
- default 0x0
-
-config MEM_DDRCTL1
- depends on BF54x
- hex "DDRCTL1"
- default 0x0
-
-config MEM_DDRCTL2
- depends on BF54x
- hex "DDRCTL2"
- default 0x0
-
-config MEM_EBIU_DDRQUE
- depends on BF54x
- hex "DDRQUE"
- default 0x0
-
-config MEM_SDRRC
- depends on !BF54x
- hex "SDRRC"
- default 0x0
-
-config MEM_SDGCTL
- depends on !BF54x
- hex "SDGCTL"
- default 0x0
-endmenu
-
-#
-# Max & Min Speeds for various Chips
-#
-config MAX_VCO_HZ
- int
- default 400000000 if BF512
- default 400000000 if BF514
- default 400000000 if BF516
- default 400000000 if BF518
- default 400000000 if BF522
- default 600000000 if BF523
- default 400000000 if BF524
- default 600000000 if BF525
- default 400000000 if BF526
- default 600000000 if BF527
- default 400000000 if BF531
- default 400000000 if BF532
- default 750000000 if BF533
- default 500000000 if BF534
- default 400000000 if BF536
- default 600000000 if BF537
- default 533333333 if BF538
- default 533333333 if BF539
- default 600000000 if BF542
- default 533333333 if BF544
- default 600000000 if BF547
- default 600000000 if BF548
- default 533333333 if BF549
- default 600000000 if BF561
- default 800000000 if BF609
-
-config MIN_VCO_HZ
- int
- default 50000000
-
-config MAX_SCLK_HZ
- int
- default 200000000 if BF609
- default 133333333
-
-config MIN_SCLK_HZ
- int
- default 27000000
-
-comment "Kernel Timer/Scheduler"
-
-source kernel/Kconfig.hz
-
-config SET_GENERIC_CLOCKEVENTS
- bool "Generic clock events"
- default y
- select GENERIC_CLOCKEVENTS
-
-menu "Clock event device"
- depends on GENERIC_CLOCKEVENTS
-config TICKSOURCE_GPTMR0
- bool "GPTimer0"
- depends on !SMP
- select BFIN_GPTIMERS
-
-config TICKSOURCE_CORETMR
- bool "Core timer"
- default y
-endmenu
-
-menu "Clock source"
- depends on GENERIC_CLOCKEVENTS
-config CYCLES_CLOCKSOURCE
- bool "CYCLES"
- default y
- depends on !BFIN_SCRATCH_REG_CYCLES
- depends on !SMP
- help
- If you say Y here, you will enable support for using the 'cycles'
- registers as a clock source. Doing so means you will be unable to
- safely write to the 'cycles' register during runtime. You will
- still be able to read it (such as for performance monitoring), but
- writing the registers will most likely crash the kernel.
-
-config GPTMR0_CLOCKSOURCE
- bool "GPTimer0"
- select BFIN_GPTIMERS
- depends on !TICKSOURCE_GPTMR0
-endmenu
-
-comment "Misc"
-
-choice
- prompt "Blackfin Exception Scratch Register"
- default BFIN_SCRATCH_REG_RETN
- help
- Select the resource to reserve for the Exception handler:
- - RETN: Non-Maskable Interrupt (NMI)
- - RETE: Exception Return (JTAG/ICE)
- - CYCLES: Performance counter
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETN
- bool "RETN"
- help
- Use the RETN register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use NMI on the Blackfin while running Linux, but
- you can debug the system with a JTAG ICE and use the
- CYCLES performance registers.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETE
- bool "RETE"
- help
- Use the RETE register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use a JTAG ICE while debugging a Blackfin board,
- but you can safely use the CYCLES performance registers
- and the NMI.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_CYCLES
- bool "CYCLES"
- help
- Use the CYCLES register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use the CYCLES performance registers on a Blackfin
- board at anytime, but you can debug the system with a JTAG
- ICE and use the NMI.
-
- If you are unsure, please select "RETN".
-
-endchoice
-
-endmenu
-
-
-menu "Blackfin Kernel Optimizations"
-
-comment "Memory Optimizations"
-
-config I_ENTRY_L1
- bool "Locate interrupt entry code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
- into L1 instruction memory. (less latency)
-
-config EXCPT_IRQ_SYSC_L1
- bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
- (less latency)
-
-config DO_IRQ_L1
- bool "Locate frequently called do_irq dispatcher function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called do_irq dispatcher function is linked
- into L1 instruction memory. (less latency)
-
-config CORE_TIMER_IRQ_L1
- bool "Locate frequently called timer_interrupt() function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called timer_interrupt() function is linked
- into L1 instruction memory. (less latency)
-
-config IDLE_L1
- bool "Locate frequently idle function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called idle function is linked
- into L1 instruction memory. (less latency)
-
-config SCHEDULE_L1
- bool "Locate kernel schedule function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called kernel schedule is linked
- into L1 instruction memory. (less latency)
-
-config ARITHMETIC_OPS_L1
- bool "Locate kernel owned arithmetic functions in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, arithmetic functions are linked
- into L1 instruction memory. (less latency)
-
-config ACCESS_OK_L1
- bool "Locate access_ok function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the access_ok function is linked
- into L1 instruction memory. (less latency)
-
-config MEMSET_L1
- bool "Locate memset function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memset function is linked
- into L1 instruction memory. (less latency)
-
-config MEMCPY_L1
- bool "Locate memcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memcpy function is linked
- into L1 instruction memory. (less latency)
-
-config STRCMP_L1
- bool "locate strcmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcmp function is linked
- into L1 instruction memory (less latency).
-
-config STRNCMP_L1
- bool "locate strncmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncmp function is linked
- into L1 instruction memory (less latency).
-
-config STRCPY_L1
- bool "locate strcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcpy function is linked
- into L1 instruction memory (less latency).
-
-config STRNCPY_L1
- bool "locate strncpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncpy function is linked
- into L1 instruction memory (less latency).
-
-config SYS_BFIN_SPINLOCK_L1
- bool "Locate sys_bfin_spinlock function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, sys_bfin_spinlock function is linked
- into L1 instruction memory. (less latency)
-
-config CACHELINE_ALIGNED_L1
- bool "Locate cacheline_aligned data to L1 Data Memory"
- default y if !BF54x
- default n if BF54x
- depends on !SMP && !BF531 && !CRC32
- help
- If enabled, cacheline_aligned data is linked
- into L1 data memory. (less latency)
-
-config SYSCALL_TAB_L1
- bool "Locate Syscall Table L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the Syscall LUT is linked
- into L1 data memory. (less latency)
-
-config CPLB_SWITCH_TAB_L1
- bool "Locate CPLB Switch Tables L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the CPLB Switch Tables are linked
- into L1 data memory. (less latency)
-
-config ICACHE_FLUSH_L1
- bool "Locate icache flush funcs in L1 Inst Memory"
- default y
- help
- If enabled, the Blackfin icache flushing functions are linked
- into L1 instruction memory.
-
- Note that this might be required to address anomalies, but
- these functions are pretty small, so it shouldn't be too bad.
- If you are using a processor affected by an anomaly, the build
- system will double check for you and prevent it.
-
-config DCACHE_FLUSH_L1
- bool "Locate dcache flush funcs in L1 Inst Memory"
- default y
- depends on !SMP
- help
- If enabled, the Blackfin dcache flushing functions are linked
- into L1 instruction memory.
-
-config APP_STACK_L1
- bool "Support locating application stack in L1 Scratch Memory"
- default y
- depends on !SMP
- help
- If enabled the application stack can be located in L1
- scratch memory (less latency).
-
- Currently only works with FLAT binaries.
-
-config EXCEPTION_L1_SCRATCH
- bool "Locate exception stack in L1 Scratch Memory"
- default n
- depends on !SMP && !APP_STACK_L1
- help
- Whenever an exception occurs, use the L1 Scratch memory for
- stack storage. You cannot place the stacks of FLAT binaries
- in L1 when using this option.
-
- If you don't use L1 Scratch, then you should say Y here.
-
-comment "Speed Optimizations"
-config BFIN_INS_LOWOVERHEAD
- bool "ins[bwl] low overhead, higher interrupt latency"
- default y
- depends on !SMP
- help
- Reads on the Blackfin are speculative. In Blackfin terms, this means
- they can be interrupted at any time (even after they have been issued
- on to the external bus), and re-issued after the interrupt occurs.
- For memory - this is not a big deal, since memory does not change if
- it sees a read.
-
- If a FIFO is sitting on the end of the read, it will see two reads,
- when the core only sees one since the FIFO receives both the read
- which is cancelled (and not delivered to the core) and the one which
- is re-issued (which is delivered to the core).
-
- To solve this, interrupts are turned off before reads occur to
- I/O space. This option controls which the overhead/latency of
- controlling interrupts during this time
- "n" turns interrupts off every read
- (higher overhead, but lower interrupt latency)
- "y" turns interrupts off every loop
- (low overhead, but longer interrupt latency)
-
- default behavior is to leave this set to on (type "Y"). If you are experiencing
- interrupt latency issues, it is safe and OK to turn this off.
-
-endmenu
-
-choice
- prompt "Kernel executes from"
- help
- Choose the memory type that the kernel will be running in.
-
-config RAMKERNEL
- bool "RAM"
- help
- The kernel will be resident in RAM when running.
-
-config ROMKERNEL
- bool "ROM"
- help
- The kernel will be resident in FLASH/ROM when running.
-
-endchoice
-
-# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
-config XIP_KERNEL
- bool
- default y
- depends on ROMKERNEL
-
-source "mm/Kconfig"
-
-config BFIN_GPTIMERS
- tristate "Enable Blackfin General Purpose Timers API"
- default n
- help
- Enable support for the General Purpose Timers API. If you
- are unsure, say N.
-
- To compile this driver as a module, choose M here: the module
- will be called gptimers.
-
-choice
- prompt "Uncached DMA region"
- default DMA_UNCACHED_1M
-config DMA_UNCACHED_32M
- bool "Enable 32M DMA region"
-config DMA_UNCACHED_16M
- bool "Enable 16M DMA region"
-config DMA_UNCACHED_8M
- bool "Enable 8M DMA region"
-config DMA_UNCACHED_4M
- bool "Enable 4M DMA region"
-config DMA_UNCACHED_2M
- bool "Enable 2M DMA region"
-config DMA_UNCACHED_1M
- bool "Enable 1M DMA region"
-config DMA_UNCACHED_512K
- bool "Enable 512K DMA region"
-config DMA_UNCACHED_256K
- bool "Enable 256K DMA region"
-config DMA_UNCACHED_128K
- bool "Enable 128K DMA region"
-config DMA_UNCACHED_NONE
- bool "Disable DMA region"
-endchoice
-
-
-comment "Cache Support"
-
-config BFIN_ICACHE
- bool "Enable ICACHE"
- default y
-config BFIN_EXTMEM_ICACHEABLE
- bool "Enable ICACHE for external memory"
- depends on BFIN_ICACHE
- default y
-config BFIN_L2_ICACHEABLE
- bool "Enable ICACHE for L2 SRAM"
- depends on BFIN_ICACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-
-config BFIN_DCACHE
- bool "Enable DCACHE"
- default y
-config BFIN_DCACHE_BANKA
- bool "Enable only 16k BankA DCACHE - BankB is SRAM"
- depends on BFIN_DCACHE && !BF531
- default n
-config BFIN_EXTMEM_DCACHEABLE
- bool "Enable DCACHE for external memory"
- depends on BFIN_DCACHE
- default y
-choice
- prompt "External memory DCACHE policy"
- depends on BFIN_EXTMEM_DCACHEABLE
- default BFIN_EXTMEM_WRITEBACK if !SMP
- default BFIN_EXTMEM_WRITETHROUGH if SMP
-config BFIN_EXTMEM_WRITEBACK
- bool "Write back"
- depends on !SMP
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-config BFIN_EXTMEM_WRITETHROUGH
- bool "Write through"
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-endchoice
-
-config BFIN_L2_DCACHEABLE
- bool "Enable DCACHE for L2 SRAM"
- depends on BFIN_DCACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-choice
- prompt "L2 SRAM DCACHE policy"
- depends on BFIN_L2_DCACHEABLE
- default BFIN_L2_WRITEBACK
-config BFIN_L2_WRITEBACK
- bool "Write back"
-
-config BFIN_L2_WRITETHROUGH
- bool "Write through"
-endchoice
-
-
-comment "Memory Protection Unit"
-config MPU
- bool "Enable the memory protection unit"
- default n
- help
- Use the processor's MPU to protect applications from accessing
- memory they do not own. This comes at a performance penalty
- and is recommended only for debugging.
-
-comment "Asynchronous Memory Configuration"
-
-menu "EBIU_AMGCTL Global Control"
- depends on !BF60x
-config C_AMCKEN
- bool "Enable CLKOUT"
- default y
-
-config C_CDPRIO
- bool "DMA has priority over core for ext. accesses"
- default n
-
-config C_B0PEN
- depends on BF561
- bool "Bank 0 16 bit packing enable"
- default y
-
-config C_B1PEN
- depends on BF561
- bool "Bank 1 16 bit packing enable"
- default y
-
-config C_B2PEN
- depends on BF561
- bool "Bank 2 16 bit packing enable"
- default y
-
-config C_B3PEN
- depends on BF561
- bool "Bank 3 16 bit packing enable"
- default n
-
-choice
- prompt "Enable Asynchronous Memory Banks"
- default C_AMBEN_ALL
-
-config C_AMBEN
- bool "Disable All Banks"
-
-config C_AMBEN_B0
- bool "Enable Bank 0"
-
-config C_AMBEN_B0_B1
- bool "Enable Bank 0 & 1"
-
-config C_AMBEN_B0_B1_B2
- bool "Enable Bank 0 & 1 & 2"
-
-config C_AMBEN_ALL
- bool "Enable All Banks"
-endchoice
-endmenu
-
-menu "EBIU_AMBCTL Control"
- depends on !BF60x
-config BANK_0
- hex "Bank 0 (AMBCTL0.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 0 settings.
-
-config BANK_1
- hex "Bank 1 (AMBCTL0.H)"
- default 0x7BB0
- default 0x5558 if BF54x
- help
- These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 1 settings.
-
-config BANK_2
- hex "Bank 2 (AMBCTL1.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 2 settings.
-
-config BANK_3
- hex "Bank 3 (AMBCTL1.H)"
- default 0x99B3
- help
- These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 3 settings.
-
-endmenu
-
-config EBIU_MBSCTLVAL
- hex "EBIU Bank Select Control Register"
- depends on BF54x
- default 0
-
-config EBIU_MODEVAL
- hex "Flash Memory Mode Control Register"
- depends on BF54x
- default 1
-
-config EBIU_FCTLVAL
- hex "Flash Memory Bank Control Register"
- depends on BF54x
- default 6
-endmenu
-
-#############################################################################
-menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
-
-config PCI
- bool "PCI support"
- depends on BROKEN
- help
- Support for PCI bus.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-endmenu
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-menu "Power management options"
-
-source "kernel/power/Kconfig"
-
-config ARCH_SUSPEND_POSSIBLE
- def_bool y
-
-choice
- prompt "Standby Power Saving Mode"
- depends on PM && !BF60x
- default PM_BFIN_SLEEP_DEEPER
-config PM_BFIN_SLEEP_DEEPER
- bool "Sleep Deeper"
- help
- Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
- power dissipation by disabling the clock to the processor core (CCLK).
- Furthermore, Standby sets the internal power supply voltage (VDDINT)
- to 0.85 V to provide the greatest power savings, while preserving the
- processor state.
- The PLL and system clock (SCLK) continue to operate at a very low
- frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
- the SDRAM is put into Self Refresh Mode. Typically an external event
- such as GPIO interrupt or RTC activity wakes up the processor.
- Various Peripherals such as UART, SPORT, PPI may not function as
- normal during Sleep Deeper, due to the reduced SCLK frequency.
- When in the sleep mode, system DMA access to L1 memory is not supported.
-
- If unsure, select "Sleep Deeper".
-
-config PM_BFIN_SLEEP
- bool "Sleep"
- help
- Sleep Mode (High Power Savings) - The sleep mode reduces power
- dissipation by disabling the clock to the processor core (CCLK).
- The PLL and system clock (SCLK), however, continue to operate in
- this mode. Typically an external event or RTC activity will wake
- up the processor. When in the sleep mode, system DMA access to L1
- memory is not supported.
-
- If unsure, select "Sleep Deeper".
-endchoice
-
-comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
- depends on PM
-
-config PM_BFIN_WAKE_PH6
- bool "Allow Wake-Up from on-chip PHY or PH6 GP"
- depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
- default n
- help
- Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_GP
- bool "Allow Wake-Up from GPIOs"
- depends on PM && BF54x
- default n
- help
- Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
- (all processors, except ADSP-BF549). This option sets
- the general-purpose wake-up enable (GPWE) control bit to enable
- wake-up upon detection of an active low signal on the /GPW (PH7) pin.
- On ADSP-BF549 this option enables the same functionality on the
- /MRXON pin also PH7.
-
-config PM_BFIN_WAKE_PA15
- bool "Allow Wake-Up from PA15"
- depends on PM && BF60x
- default n
- help
- Enable PA15 Wake-Up
-
-config PM_BFIN_WAKE_PA15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PA15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PB15
- bool "Allow Wake-Up from PB15"
- depends on PM && BF60x
- default n
- help
- Enable PB15 Wake-Up
-
-config PM_BFIN_WAKE_PB15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PB15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PC15
- bool "Allow Wake-Up from PC15"
- depends on PM && BF60x
- default n
- help
- Enable PC15 Wake-Up
-
-config PM_BFIN_WAKE_PC15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PC15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PD06
- bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
- depends on PM && BF60x
- default n
- help
- Enable PD06(ETH0_PHYINT) Wake-up
-
-config PM_BFIN_WAKE_PD06_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PD06
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PE12
- bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
- depends on PM && BF60x
- default n
- help
- Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
-
-config PM_BFIN_WAKE_PE12_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PE12
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG04
- bool "Allow Wake-Up from PG04(CAN0_RX)"
- depends on PM && BF60x
- default n
- help
- Enable PG04(CAN0_RX) Wake-up
-
-config PM_BFIN_WAKE_PG04_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG04
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG13
- bool "Allow Wake-Up from PG13"
- depends on PM && BF60x
- default n
- help
- Enable PG13 Wake-Up
-
-config PM_BFIN_WAKE_PG13_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG13
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_USB
- bool "Allow Wake-Up from (USB)"
- depends on PM && BF60x
- default n
- help
- Enable (USB) Wake-up
-
-config PM_BFIN_WAKE_USB_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_USB
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-endmenu
-
-menu "CPU Frequency scaling"
-
-source "drivers/cpufreq/Kconfig"
-
-config BFIN_CPU_FREQ
- bool
- depends on CPU_FREQ
- default y
-
-config CPU_VOLTAGE
- bool "CPU Voltage scaling"
- depends on CPU_FREQ
- default n
- help
- Say Y here if you want CPU voltage scaling according to the CPU frequency.
- This option violates the PLL BYPASS recommendation in the Blackfin Processor
- manuals. There is a theoretical risk that during VDDINT transitions
- the PLL may unlock.
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "drivers/firmware/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/blackfin/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
deleted file mode 100644
index c8d957274cc2..000000000000
--- a/arch/blackfin/Kconfig.debug
+++ /dev/null
@@ -1,258 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_VERBOSE
- bool "Verbose fault messages"
- default y
- select PRINTK
- help
- When a program crashes due to an exception, or the kernel detects
- an internal error, the kernel can print a not so brief message
- explaining what the problem was. This debugging information is
- useful to developers and kernel hackers when tracking down problems,
- but mostly meaningless to other people. This is always helpful for
- debugging but serves no purpose on a production system.
- Most people should say N here.
-
-config DEBUG_MMRS
- tristate "Generate Blackfin MMR tree"
- depends on !PINCTRL
- select DEBUG_FS
- help
- Create a tree of Blackfin MMRs via the debugfs tree. If
- you enable this, you will find all MMRs laid out in the
- /sys/kernel/debug/blackfin/ directory where you can read/write
- MMRs directly from userspace. This is obviously just a debug
- feature.
-
-config DEBUG_HWERR
- bool "Hardware error interrupt debugging"
- depends on DEBUG_KERNEL
- help
- When enabled, the hardware error interrupt is never disabled, and
- will happen immediately when an error condition occurs. This comes
- at a slight cost in code size, but is necessary if you are getting
- hardware error interrupts and need to know where they are coming
- from.
-
-config EXACT_HWERR
- bool "Try to make Hardware errors exact"
- depends on DEBUG_HWERR
- help
- By default, the Blackfin hardware errors are not exact - the error
- be reported multiple cycles after the error happens. This delay
- can cause the wrong application, or even the kernel to receive a
- signal to be killed. If you are getting HW errors in your system,
- try turning this on to ensure they are at least coming from the
- proper thread.
-
- On production systems, it is safe (and a small optimization) to say N.
-
-config DEBUG_DOUBLEFAULT
- bool "Debug Double Faults"
- default n
- help
- If an exception is caused while executing code within the exception
- handler, the NMI handler, the reset vector, or in emulator mode,
- a double fault occurs. On the Blackfin, this is a unrecoverable
- event. You have two options:
- - RESET exactly when double fault occurs. The excepting
- instruction address is stored in RETX, where the next kernel
- boot will print it out.
- - Print debug message. This is much more error prone, although
- easier to handle. It is error prone since:
- - The excepting instruction is not committed.
- - All writebacks from the instruction are prevented.
- - The generated exception is not taken.
- - The EXCAUSE field is updated with an unrecoverable event
- The only way to check this is to see if EXCAUSE contains the
- unrecoverable event value at every exception return. By selecting
- this option, you are skipping over the faulting instruction, and
- hoping things stay together enough to print out a debug message.
-
- This does add a little kernel code, but is the only method to debug
- double faults - if unsure say "Y"
-
-choice
- prompt "Double Fault Failure Method"
- default DEBUG_DOUBLEFAULT_PRINT
- depends on DEBUG_DOUBLEFAULT
-
-config DEBUG_DOUBLEFAULT_PRINT
- bool "Print"
-
-config DEBUG_DOUBLEFAULT_RESET
- bool "Reset"
-
-endchoice
-
-config DEBUG_HUNT_FOR_ZERO
- bool "Catch NULL pointer reads/writes"
- default y
- help
- Say Y here to catch reads/writes to anywhere in the memory range
- from 0x0000 - 0x0FFF (the first 4k) of memory. This is useful in
- catching common programming errors such as NULL pointer dereferences.
-
- Misbehaving applications will be killed (generate a SEGV) while the
- kernel will trigger a panic.
-
- Enabling this option will take up an extra entry in CPLB table.
- Otherwise, there is no extra overhead.
-
-config DEBUG_BFIN_HWTRACE_ON
- bool "Turn on Blackfin's Hardware Trace"
- default y
- help
- All Blackfins include a Trace Unit which stores a history of the last
- 16 changes in program flow taken by the program sequencer. The history
- allows the user to recreate the program sequencer’s recent path. This
- can be handy when an application dies - we print out the execution
- path of how it got to the offending instruction.
-
- By turning this off, you may save a tiny amount of power.
-
-choice
- prompt "Omit loop Tracing"
- default DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- depends on DEBUG_BFIN_HWTRACE_ON
- help
- The trace buffer can be configured to omit recording of changes in
- program flow that match either the last entry or one of the last
- two entries. Omitting one of these entries from the record prevents
- the trace buffer from overflowing because of any sort of loop (for, do
- while, etc) in the program.
-
- Because zero-overhead Hardware loops are not recorded in the trace buffer,
- this feature can be used to prevent trace overflow from loops that
- are nested four deep.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- bool "Trace all Loops"
- help
- The trace buffer records all changes of flow
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- bool "Compress single-level loops"
- help
- The trace buffer does not record single loops - helpful if trace
- is spinning on a while or do loop.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
- bool "Compress two-level loops"
- help
- The trace buffer does not record loops two levels deep. Helpful if
- the trace is spinning in a nested loop
-
-endchoice
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION
- int
- depends on DEBUG_BFIN_HWTRACE_ON
- default 0 if DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- default 1 if DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- default 2 if DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
-
-
-config DEBUG_BFIN_HWTRACE_EXPAND
- bool "Expand Trace Buffer greater than 16 entries"
- depends on DEBUG_BFIN_HWTRACE_ON
- default n
- help
- By selecting this option, every time the 16 hardware entries in
- the Blackfin's HW Trace buffer are full, the kernel will move them
- into a software buffer, for dumping when there is an issue. This
- has a great impact on performance, (an interrupt every 16 change of
- flows) and should normally be turned off, except in those nasty
- debugging sessions
-
-config DEBUG_BFIN_HWTRACE_EXPAND_LEN
- int "Size of Trace buffer (in power of 2k)"
- range 0 4
- depends on DEBUG_BFIN_HWTRACE_EXPAND
- default 1
- help
- This sets the size of the software buffer that the trace information
- is kept in.
- 0 for (2^0) 1k, or 256 entries,
- 1 for (2^1) 2k, or 512 entries,
- 2 for (2^2) 4k, or 1024 entries,
- 3 for (2^3) 8k, or 2048 entries,
- 4 for (2^4) 16k, or 4096 entries
-
-config DEBUG_BFIN_NO_KERN_HWTRACE
- bool "Turn off hwtrace in CPLB handlers"
- depends on DEBUG_BFIN_HWTRACE_ON
- default y
- help
- The CPLB error handler contains a lot of flow changes which can
- quickly fill up the hardware trace buffer. When debugging crashes,
- the hardware trace may indicate that the problem lies in kernel
- space when in reality an application is buggy.
-
- Say Y here to disable hardware tracing in some known "jumpy" pieces
- of code so that the trace buffer will extend further back.
-
-config EARLY_PRINTK
- bool "Early printk"
- default n
- select SERIAL_CORE_CONSOLE
- help
- This option enables special console drivers which allow the kernel
- to print messages very early in the bootup process.
-
- This is useful for kernel debugging when your machine crashes very
- early before the console code is initialized. After enabling this
- feature, you must add "earlyprintk=serial,uart0,57600" to the
- command line (bootargs). It is safe to say Y here in all cases, as
- all of this lives in the init section and is thrown away after the
- kernel boots completely.
-
-config NMI_WATCHDOG
- bool "Enable NMI watchdog to help debugging lockup on SMP"
- default n
- depends on SMP
- help
- If any CPU in the system does not execute the period local timer
- interrupt for more than 5 seconds, then the NMI handler dumps debug
- information. This information can be used to debug the lockup.
-
-config CPLB_INFO
- bool "Display the CPLB information"
- help
- Display the CPLB information via /proc/cplbinfo.
-
-config ACCESS_CHECK
- bool "Check the user pointer address"
- default y
- help
- Usually the pointer transfer from user space is checked to see if its
- address is in the kernel space.
-
- Say N here to disable that check to improve the performance.
-
-config BFIN_ISRAM_SELF_TEST
- bool "isram boot self tests"
- default n
- help
- Run some self tests of the isram driver code at boot.
-
-config BFIN_PSEUDODBG_INSNS
- bool "Support pseudo debug instructions"
- default n
- help
- This option allows the kernel to emulate some pseudo instructions which
- allow simulator test cases to be run under Linux with no changes.
-
- Most people should say N here.
-
-config BFIN_PM_WAKEUP_TIME_BENCH
- bool "Display the total time for kernel to resume from power saving mode"
- default n
- help
- Display the total time when kernel resumes normal from standby or
- suspend to mem mode.
-
-endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
deleted file mode 100644
index 1fce08632ad7..000000000000
--- a/arch/blackfin/Makefile
+++ /dev/null
@@ -1,168 +0,0 @@
-#
-# arch/blackfin/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-LDFLAGS_vmlinux := -X
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-GZFLAGS := -9
-
-KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
-ifeq ($(CONFIG_ROMKERNEL),y)
-KBUILD_CFLAGS += -mlong-calls
-endif
-KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
-KBUILD_CFLAGS_MODULE += -mlong-calls
-LDFLAGS += -m elf32bfin
-
-KBUILD_DEFCONFIG := BF537-STAMP_defconfig
-
-# setup the machine name and the machine dependent settings
-machine-$(CONFIG_BF512) := bf518
-machine-$(CONFIG_BF514) := bf518
-machine-$(CONFIG_BF516) := bf518
-machine-$(CONFIG_BF518) := bf518
-machine-$(CONFIG_BF522) := bf527
-machine-$(CONFIG_BF523) := bf527
-machine-$(CONFIG_BF524) := bf527
-machine-$(CONFIG_BF525) := bf527
-machine-$(CONFIG_BF526) := bf527
-machine-$(CONFIG_BF527) := bf527
-machine-$(CONFIG_BF531) := bf533
-machine-$(CONFIG_BF532) := bf533
-machine-$(CONFIG_BF533) := bf533
-machine-$(CONFIG_BF534) := bf537
-machine-$(CONFIG_BF536) := bf537
-machine-$(CONFIG_BF537) := bf537
-machine-$(CONFIG_BF538) := bf538
-machine-$(CONFIG_BF539) := bf538
-machine-$(CONFIG_BF542) := bf548
-machine-$(CONFIG_BF542M) := bf548
-machine-$(CONFIG_BF544) := bf548
-machine-$(CONFIG_BF544M) := bf548
-machine-$(CONFIG_BF547) := bf548
-machine-$(CONFIG_BF547M) := bf548
-machine-$(CONFIG_BF548) := bf548
-machine-$(CONFIG_BF548M) := bf548
-machine-$(CONFIG_BF549) := bf548
-machine-$(CONFIG_BF549M) := bf548
-machine-$(CONFIG_BF561) := bf561
-machine-$(CONFIG_BF609) := bf609
-MACHINE := $(machine-y)
-export MACHINE
-
-cpu-$(CONFIG_BF512) := bf512
-cpu-$(CONFIG_BF514) := bf514
-cpu-$(CONFIG_BF516) := bf516
-cpu-$(CONFIG_BF518) := bf518
-cpu-$(CONFIG_BF522) := bf522
-cpu-$(CONFIG_BF523) := bf523
-cpu-$(CONFIG_BF524) := bf524
-cpu-$(CONFIG_BF525) := bf525
-cpu-$(CONFIG_BF526) := bf526
-cpu-$(CONFIG_BF527) := bf527
-cpu-$(CONFIG_BF531) := bf531
-cpu-$(CONFIG_BF532) := bf532
-cpu-$(CONFIG_BF533) := bf533
-cpu-$(CONFIG_BF534) := bf534
-cpu-$(CONFIG_BF536) := bf536
-cpu-$(CONFIG_BF537) := bf537
-cpu-$(CONFIG_BF538) := bf538
-cpu-$(CONFIG_BF539) := bf539
-cpu-$(CONFIG_BF542) := bf542
-cpu-$(CONFIG_BF542M) := bf542m
-cpu-$(CONFIG_BF544) := bf544
-cpu-$(CONFIG_BF544M) := bf544m
-cpu-$(CONFIG_BF547) := bf547
-cpu-$(CONFIG_BF547M) := bf547m
-cpu-$(CONFIG_BF548) := bf548
-cpu-$(CONFIG_BF548M) := bf548m
-cpu-$(CONFIG_BF549) := bf549
-cpu-$(CONFIG_BF549M) := bf549m
-cpu-$(CONFIG_BF561) := bf561
-cpu-$(CONFIG_BF609) := bf609
-
-rev-$(CONFIG_BF_REV_0_0) := 0.0
-rev-$(CONFIG_BF_REV_0_1) := 0.1
-rev-$(CONFIG_BF_REV_0_2) := 0.2
-rev-$(CONFIG_BF_REV_0_3) := 0.3
-rev-$(CONFIG_BF_REV_0_4) := 0.4
-rev-$(CONFIG_BF_REV_0_5) := 0.5
-rev-$(CONFIG_BF_REV_0_6) := 0.6
-rev-$(CONFIG_BF_REV_NONE) := none
-rev-$(CONFIG_BF_REV_ANY) := any
-
-CPU_REV := $(cpu-y)-$(rev-y)
-export CPU_REV
-
-KBUILD_CFLAGS += -mcpu=$(CPU_REV)
-KBUILD_AFLAGS += -mcpu=$(CPU_REV)
-
-# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
-CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
-CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
-
-core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
-
-# If we have a machine-specific directory, then include it in the build.
-ifneq ($(machine-y),)
-core-y += arch/$(ARCH)/mach-$(MACHINE)/
-core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/
-endif
-
-ifeq ($(CONFIG_MPU),y)
-core-y += arch/$(ARCH)/kernel/cplb-mpu/
-else
-core-y += arch/$(ARCH)/kernel/cplb-nompu/
-endif
-
-drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
-
-libs-y += arch/$(ARCH)/lib/
-
-machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
-
-KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
-KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include
-
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
-
-CLEAN_FILES += \
- arch/$(ARCH)/kernel/asm-offsets.s \
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-INSTALL_PATH ?= /tftpboot
-boot := arch/$(ARCH)/boot
-BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-PHONY += $(BOOT_TARGETS) install
-KBUILD_IMAGE := $(boot)/uImage
-
-all: uImage
-
-$(BOOT_TARGETS): vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-install:
- $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
-
-define archhelp
- echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)'
- echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
- echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
- echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
- echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
- echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)'
- echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)'
- echo ' install - Install kernel using'
- echo ' (your) ~/bin/$(INSTALLKERNEL) or'
- echo ' (distribution) PATH: $(INSTALLKERNEL) or'
- echo ' install to $$(INSTALL_PATH)'
-endef
diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore
deleted file mode 100644
index 1287a5487e7d..000000000000
--- a/arch/blackfin/boot/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-vmImage*
-vmlinux*
-uImage*
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
deleted file mode 100644
index 3efaa094fb90..000000000000
--- a/arch/blackfin/boot/Makefile
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# arch/blackfin/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
-
-ifeq ($(CONFIG_RAMKERNEL),y)
-UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
-else # CONFIG_ROMKERNEL must be set
-UIMAGE_LOADADDR = $(CONFIG_ROM_BASE)
-endif
-UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
-UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
-UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzma)
-
-$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzo)
-
-# The mkimage tool wants 64bytes prepended to the image
-quiet_cmd_mk_bin_xip = BIN $@
- cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@
-$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
- $(call if_changed,mk_bin_xip)
-
-$(obj)/uImage.bin: $(obj)/vmlinux.bin
- $(call if_changed,uimage,none)
-
-$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
- $(call if_changed,uimage,bzip2)
-
-$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
- $(call if_changed,uimage,gzip)
-
-$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
- $(call if_changed,uimage,lzma)
-
-$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
- $(call if_changed,uimage,lzo)
-
-$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
- $(call if_changed,uimage,none)
-
-suffix-y := bin
-suffix-$(CONFIG_KERNEL_GZIP) := gz
-suffix-$(CONFIG_KERNEL_BZIP2) := bz2
-suffix-$(CONFIG_KERNEL_LZMA) := lzma
-suffix-$(CONFIG_KERNEL_LZO) := lzo
-suffix-$(CONFIG_ROMKERNEL) := xip
-
-$(obj)/uImage: $(obj)/uImage.$(suffix-y)
- @ln -sf $(notdir $<) $@
-
-install:
- sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
diff --git a/arch/blackfin/boot/install.sh b/arch/blackfin/boot/install.sh
deleted file mode 100644
index e2c6e40902b7..000000000000
--- a/arch/blackfin/boot/install.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/sh
-#
-# arch/blackfin/boot/install.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-# Adapted from code in arch/i386/boot/install.sh by Mike Frysinger
-#
-# "make install" script for Blackfin architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install path (blank if root directory)
-#
-
-verify () {
- if [ ! -f "$1" ]; then
- echo "" 1>&2
- echo " *** Missing file: $1" 1>&2
- echo ' *** You need to run "make" before "make install".' 1>&2
- echo "" 1>&2
- exit 1
- fi
-}
-
-# Make sure the files actually exist
-verify "$2"
-verify "$3"
-
-# User may have a custom install script
-
-if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
-if which ${INSTALLKERNEL} >/dev/null 2>&1; then
- exec ${INSTALLKERNEL} "$@"
-fi
-
-# Default install - same as make zlilo
-
-back_it_up() {
- local file=$1
- [ -f ${file} ] || return 0
- local stamp=$(stat -c %Y ${file} 2>/dev/null)
- mv ${file} ${file}.${stamp:-old}
-}
-
-back_it_up $4/uImage
-back_it_up $4/System.map
-
-cat $2 > $4/uImage
-cp $3 $4/System.map
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
deleted file mode 100644
index 99c00d835f47..000000000000
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
deleted file mode 100644
index e66ba31ef84d..000000000000
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF526=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN526_EZBRD=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
deleted file mode 100644
index d95658fc3127..000000000000
--- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_IRQ_TWI=7
-CONFIG_IRQ_PORTH_INTA=7
-CONFIG_IRQ_PORTH_INTB=7
-CONFIG_BFIN527_AD7160EVAL=y
-CONFIG_BF527_SPORT0_PORTF=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600"
-CONFIG_CLKIN_HZ=24000000
-CONFIG_HZ_300=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x5554
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7160=y
-CONFIG_TOUCHSCREEN_AD7160_FW=y
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_BFIN_OTP is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
deleted file mode 100644
index 0207c588c19f..000000000000
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ /dev/null
@@ -1,188 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_EZKIT_V2=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_ADP5520=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_I2C=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_PMIC_ADP5520=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_LQ035Q1=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_ADP5520=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
deleted file mode 100644
index 99c131ba7d90..000000000000
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ /dev/null
@@ -1,181 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_T350MCQB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_LTV350QV=m
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig
deleted file mode 100644
index cdeb51856f26..000000000000
--- a/arch/blackfin/configs/BF527-TLL6527M_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DEV_0-1_pre2010"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_TLL6527M=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_BOOT_LOAD=0x400000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xFFC2
-CONFIG_BANK_1=0xFFC2
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_AD714X=y
-CONFIG_INPUT_ADXL34X=y
-# CONFIG_SERIO is not set
-CONFIG_BFIN_PPI=m
-CONFIG_BFIN_SIMPLE_TIMER=m
-CONFIG_BFIN_SPORT=m
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_SMBUS=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_BLACKFIN_CAM=m
-CONFIG_OV9655=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC7=m
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
deleted file mode 100644
index ed7d2c096739..000000000000
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BFIN533_EZKIT=y
-CONFIG_TIMER0=11
-CONFIG_CLKIN_HZ=27000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
deleted file mode 100644
index 0c241f4d28d7..000000000000
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_TIMER0=11
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
deleted file mode 100644
index e5360b30e39a..000000000000
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ /dev/null
@@ -1,136 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR1=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
deleted file mode 100644
index 60f6fb86125c..000000000000
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ /dev/null
@@ -1,133 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF538=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_IRQ_TIMER1=12
-CONFIG_IRQ_TIMER2=12
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_SPI=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-CONFIG_SERIAL_BFIN_UART2=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FB_BFIN_LQ035Q1=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
deleted file mode 100644
index 38cb17d218d4..000000000000
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ /dev/null
@@ -1,207 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF548_std=y
-CONFIG_IRQ_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_3=0x99B2
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR3=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BF5XX=y
-# CONFIG_MTD_NAND_BF5XX_HWECC is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_BF54X=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_BFIN=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_BF54X_LQ043=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_AC97=y
-CONFIG_SND_BF5XX_SOC_AD1980=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=m
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
deleted file mode 100644
index 78f6bc79f910..000000000000
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ /dev/null
@@ -1,149 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_BF_REV_0_5=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_ACVILON=y
-# CONFIG_BF561_COREB is not set
-CONFIG_CLKIN_HZ=12000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_4M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0x99b2
-CONFIG_BANK_1=0x3350
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_PHRAM=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PCA_PLATFORM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SPORT_NUM=1
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="cp1251"
-CONFIG_NTFS_FS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-# CONFIG_JFFS2_ZLIB is not set
-CONFIG_JFFS2_LZO=y
-# CONFIG_JFFS2_RTIME is not set
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp1251"
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
deleted file mode 100644
index fac8bb578249..000000000000
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_SMP=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
deleted file mode 100644
index 2a2e4d0cebc1..000000000000
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BFIN_L2_DCACHEABLE=y
-CONFIG_BFIN_L2_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
deleted file mode 100644
index 3ce77f07208a..000000000000
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ /dev/null
@@ -1,154 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF609=y
-CONFIG_PINT1_ASSIGN=0x01010000
-CONFIG_PINT2_ASSIGN=0x07000101
-CONFIG_PINT3_ASSIGN=0x02020303
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-# CONFIG_APP_STACK_L1 is not set
-# CONFIG_BFIN_INS_LOWOVERHEAD is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM_BFIN_WAKE_PE12=y
-CONFIG_PM_BFIN_WAKE_PE12_POL=1
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_CAN=y
-CONFIG_CAN_BFIN=y
-CONFIG_IRDA=y
-CONFIG_IRTTY_SIR=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_IEEE1588=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_BFIN_ROTARY=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_SIMPLE_TIMER=m
-# CONFIG_BFIN_CRC is not set
-CONFIG_BFIN_LINKPORT=y
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_ADI_V3=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_PINCTRL_MCP23S08=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_USB=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_ZERO=y
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=m
-CONFIG_UBIFS_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_BFIN_CRC=m
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
deleted file mode 100644
index f4a9200e1ab1..000000000000
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BLACKSTAMP=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_ROMKERNEL=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=m
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_SMB_FS=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
deleted file mode 100644
index 1902bb05d086..000000000000
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ /dev/null
@@ -1,129 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN527_BLUETECHNIX_CM=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB=m
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
deleted file mode 100644
index 9a5716d57ebc..000000000000
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BFIN533_BLUETECHNIX_CM=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
deleted file mode 100644
index 684592884349..000000000000
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_E=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
deleted file mode 100644
index d9915e984787..000000000000
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_U=y
-CONFIG_CLKIN_HZ=30000000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
deleted file mode 100644
index 92d8130cdb51..000000000000
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF548_std=y
-CONFIG_BF_REV_ANY=y
-CONFIG_IRQ_TIMER0=11
-CONFIG_BFIN548_BLUETECHNIX_CM=y
-# CONFIG_DEB_DMA_URGENT is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_1=0x5554
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=m
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=m
-CONFIG_SDH_BFIN=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=m
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_CIFS=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
deleted file mode 100644
index fa8d91132a57..000000000000
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_BLUETECHNIX_CM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMSC911X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
deleted file mode 100644
index 88600593c731..000000000000
--- a/arch/blackfin/configs/DNP5370_defconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DNP5370"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLOB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BF537=y
-CONFIG_BF_REV_0_3=y
-CONFIG_DNP5370=y
-CONFIG_IRQ_ERROR=7
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_C_AMBEN_B0_B1_B2=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_LLC2=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_ABSENT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=y
-CONFIG_BFIN_JTAG_COMM_CONSOLE=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_LM75=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_DMADEVICES=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_OBJECTS=y
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_DEBUG_KOBJECT=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_LIST=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_PAGE_POISONING=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
deleted file mode 100644
index 0ff97d8d047a..000000000000
--- a/arch/blackfin/configs/H8606_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_H8606_HVSISTEMAS=y
-CONFIG_TIMER0=11
-# CONFIG_CACHELINE_ALIGNED_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS=m
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
deleted file mode 100644
index 9e3ae4b36d20..000000000000
--- a/arch/blackfin/configs/IP0X_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BFIN532_IP0X=y
-CONFIG_TIMER0=11
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-# CONFIG_BFIN_ICACHE is not set
-# CONFIG_BFIN_DCACHE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xffc2
-CONFIG_BANK_1=0xffc2
-CONFIG_BANK_2=0xffc2
-CONFIG_BANK_3=0xffc2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_MANGLE=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_USB_OTG_WHITELIST=y
-CONFIG_USB_MON=y
-CONFIG_USB_ISP1362_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
deleted file mode 100644
index c7926812971c..000000000000
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_PNAV10=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x33B0
-CONFIG_BANK_2=0x33B0
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_BFIN_MAC_USE_L1 is not set
-CONFIG_BFIN_TX_DESC_NUM=100
-CONFIG_BFIN_RX_DESC_NUM=100
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_SOUND=y
-CONFIG_SND=m
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SOUND_PRIME=y
-# CONFIG_HID is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_HUNT_FOR_ZERO is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_ACCESS_CHECK is not set
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
deleted file mode 100644
index 23fdc57d657a..000000000000
--- a/arch/blackfin/configs/SRV1_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BOOT_LOAD=0x400000
-CONFIG_CLKIN_HZ=22118400
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=m
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_HWMON=m
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig
deleted file mode 100644
index e28959479fe0..000000000000
--- a/arch/blackfin/configs/TCM-BF518_defconfig
+++ /dev/null
@@ -1,131 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_BF_REV_0_1=y
-CONFIG_BFIN518F_TCM=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
deleted file mode 100644
index 39e85cce95d7..000000000000
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_TCM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
deleted file mode 100644
index fe736973630f..000000000000
--- a/arch/blackfin/include/asm/Kbuild
+++ /dev/null
@@ -1,28 +0,0 @@
-generic-y += bugs.h
-generic-y += current.h
-generic-y += device.h
-generic-y += div64.h
-generic-y += emergency-restart.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += futex.h
-generic-y += hw_irq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += percpu.h
-generic-y += pgalloc.h
-generic-y += preempt.h
-generic-y += serial.h
-generic-y += topology.h
-generic-y += trace_clock.h
-generic-y += unaligned.h
-generic-y += user.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/blackfin/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
deleted file mode 100644
index 63c7deceeeb6..000000000000
--- a/arch/blackfin/include/asm/atomic.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_ATOMIC__
-#define __ARCH_BLACKFIN_ATOMIC__
-
-#include <asm/cmpxchg.h>
-
-#ifdef CONFIG_SMP
-
-#include <asm/barrier.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
-asmlinkage int __raw_atomic_add_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xadd_asm(volatile int *ptr, int value);
-
-asmlinkage int __raw_atomic_and_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_or_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
-
-#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
-
-#define atomic_add_return(i, v) __raw_atomic_add_asm(&(v)->counter, i)
-#define atomic_sub_return(i, v) __raw_atomic_add_asm(&(v)->counter, -(i))
-
-#define atomic_fetch_add(i, v) __raw_atomic_xadd_asm(&(v)->counter, i)
-#define atomic_fetch_sub(i, v) __raw_atomic_xadd_asm(&(v)->counter, -(i))
-
-#define atomic_or(i, v) (void)__raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_and(i, v) (void)__raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_xor(i, v) (void)__raw_atomic_xor_asm(&(v)->counter, i)
-
-#define atomic_fetch_or(i, v) __raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_fetch_and(i, v) __raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_fetch_xor(i, v) __raw_atomic_xor_asm(&(v)->counter, i)
-
-#endif
-
-#include <asm-generic/atomic.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h
deleted file mode 100644
index 7cca51cae5ff..000000000000
--- a/arch/blackfin/include/asm/barrier.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_BARRIER_H
-#define _BLACKFIN_BARRIER_H
-
-#include <asm/cache.h>
-
-#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
-
-/*
- * Force strict CPU ordering.
- */
-#ifdef CONFIG_SMP
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-/* Force Core data cache coherence */
-# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
-# define rmb() do { barrier(); smp_check_barrier(); } while (0)
-# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier. All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads. This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies. See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * b = 2;
- * memory_barrier();
- * p = &b; q = p;
- * read_barrier_depends();
- * d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends(). However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * a = 2;
- * memory_barrier();
- * b = 3; y = b;
- * read_barrier_depends();
- * x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b". Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
- * in cases like this where there are no data dependencies.
- */
-# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
-#endif
-
-#endif /* !CONFIG_SMP */
-
-#define __smp_mb__before_atomic() barrier()
-#define __smp_mb__after_atomic() barrier()
-
-#include <asm-generic/barrier.h>
-
-#endif /* _BLACKFIN_BARRIER_H */
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
deleted file mode 100644
index dc47d79287f9..000000000000
--- a/arch/blackfin/include/asm/bfin-global.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Global extern defines for blackfin
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_GLOBAL_H_
-#define _BFIN_GLOBAL_H_
-
-#ifndef __ASSEMBLY__
-
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_DMA_UNCACHED_32M)
-# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_16M)
-# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_8M)
-# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_4M)
-# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_2M)
-# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_1M)
-# define DMA_UNCACHED_REGION (1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_512K)
-# define DMA_UNCACHED_REGION (512 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_256K)
-# define DMA_UNCACHED_REGION (256 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_128K)
-# define DMA_UNCACHED_REGION (128 * 1024)
-#else
-# define DMA_UNCACHED_REGION (0)
-#endif
-
-extern void bfin_setup_caches(unsigned int cpu);
-extern void bfin_setup_cpudata(unsigned int cpu);
-
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
-#ifdef CONFIG_BF60x
-extern unsigned long get_sclk0(void);
-extern unsigned long get_sclk1(void);
-extern unsigned long get_dclk(void);
-#endif
-extern unsigned long sclk_to_usecs(unsigned long sclk);
-extern unsigned long usecs_to_sclk(unsigned long usecs);
-
-struct pt_regs;
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(struct pt_regs *regs);
-extern void dump_bfin_trace_buffer(void);
-#else
-#define dump_bfin_process(regs)
-#define dump_bfin_mem(regs)
-#define dump_bfin_trace_buffer()
-#endif
-
-extern void *l1_data_A_sram_alloc(size_t);
-extern void *l1_data_B_sram_alloc(size_t);
-extern void *l1_inst_sram_alloc(size_t);
-extern void *l1_data_sram_alloc(size_t);
-extern void *l1_data_sram_zalloc(size_t);
-extern void *l2_sram_alloc(size_t);
-extern void *l2_sram_zalloc(size_t);
-extern int l1_data_A_sram_free(const void*);
-extern int l1_data_B_sram_free(const void*);
-extern int l1_inst_sram_free(const void*);
-extern int l1_data_sram_free(const void*);
-extern int l2_sram_free(const void *);
-extern int sram_free(const void*);
-
-#define L1_INST_SRAM 0x00000001
-#define L1_DATA_A_SRAM 0x00000002
-#define L1_DATA_B_SRAM 0x00000004
-#define L1_DATA_SRAM 0x00000006
-#define L2_SRAM 0x00000008
-extern void *sram_alloc_with_lsl(size_t, unsigned long);
-extern int sram_free_with_lsl(const void*);
-
-extern void *isram_memcpy(void *dest, const void *src, size_t n);
-
-extern const char bfin_board_name[];
-
-extern unsigned long bfin_sic_iwr[];
-extern unsigned vr_wakeup;
-extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-
-#endif
-
-#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h
deleted file mode 100644
index 836895156b5b..000000000000
--- a/arch/blackfin/include/asm/bfin-lq035q1.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
- *
- * Copyright 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BFIN_LQ035Q1_H
-#define BFIN_LQ035Q1_H
-
-/*
- * LCD Modes
- */
-#define LQ035_RL (0 << 8) /* Right -> Left Scan */
-#define LQ035_LR (1 << 8) /* Left -> Right Scan */
-#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
-#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
-#define LQ035_BGR (1 << 11) /* Use BGR format */
-#define LQ035_RGB (0 << 11) /* Use RGB format */
-#define LQ035_NORM (1 << 13) /* Reversal */
-#define LQ035_REV (0 << 13) /* Reversal */
-
-/*
- * PPI Modes
- */
-
-#define USE_RGB565_16_BIT_PPI 1
-#define USE_RGB565_8_BIT_PPI 2
-#define USE_RGB888_8_BIT_PPI 3
-
-struct bfin_lq035q1fb_disp_info {
-
- unsigned mode;
- unsigned ppi_mode;
- /* GPIOs */
- int use_bl;
- unsigned gpio_bl;
-};
-
-#endif /* BFIN_LQ035Q1_H */
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
deleted file mode 100644
index fb95c853bb1e..000000000000
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Blackfin On-Chip SPI Driver
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#define MIN_SPI_BAUD_VAL 2
-
-#define BIT_CTL_ENABLE 0x4000
-#define BIT_CTL_OPENDRAIN 0x2000
-#define BIT_CTL_MASTER 0x1000
-#define BIT_CTL_CPOL 0x0800
-#define BIT_CTL_CPHA 0x0400
-#define BIT_CTL_LSBF 0x0200
-#define BIT_CTL_WORDSIZE 0x0100
-#define BIT_CTL_EMISO 0x0020
-#define BIT_CTL_PSSE 0x0010
-#define BIT_CTL_GM 0x0008
-#define BIT_CTL_SZ 0x0004
-#define BIT_CTL_RXMOD 0x0000
-#define BIT_CTL_TXMOD 0x0001
-#define BIT_CTL_TIMOD_DMA_TX 0x0003
-#define BIT_CTL_TIMOD_DMA_RX 0x0002
-#define BIT_CTL_SENDOPT 0x0004
-#define BIT_CTL_TIMOD 0x0003
-
-#define BIT_STAT_SPIF 0x0001
-#define BIT_STAT_MODF 0x0002
-#define BIT_STAT_TXE 0x0004
-#define BIT_STAT_TXS 0x0008
-#define BIT_STAT_RBSY 0x0010
-#define BIT_STAT_RXS 0x0020
-#define BIT_STAT_TXCOL 0x0040
-#define BIT_STAT_CLR 0xFFFF
-
-#define BIT_STU_SENDOVER 0x0001
-#define BIT_STU_RECVFULL 0x0020
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin spi registers layout
- */
-struct bfin_spi_regs {
- __BFP(ctl);
- __BFP(flg);
- __BFP(stat);
- __BFP(tdbr);
- __BFP(rdbr);
- __BFP(baud);
- __BFP(shadow);
-};
-
-#undef __BFP
-
-#define MAX_CTRL_CS 8 /* cs in spi controller */
-
-/* device.platform_data for SSP controller devices */
-struct bfin5xx_spi_master {
- u16 num_chipselect;
- u8 enable_dma;
- u16 pin_req[7];
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct bfin5xx_spi_chip {
- u16 ctl_reg;
- u8 enable_dma;
- u16 cs_chg_udelay; /* Some devices require 16-bit delays */
- /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
- u16 idle_tx_val;
- u8 pio_interrupt; /* Enable spi data irq */
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
deleted file mode 100644
index b1492e0bcabb..000000000000
--- a/arch/blackfin/include/asm/bfin_can.h
+++ /dev/null
@@ -1,728 +0,0 @@
-/*
- * bfin_can.h - interface to Blackfin CANs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_CAN_H__
-#define __ASM_BFIN_CAN_H__
-
-/*
- * transmit and receive channels
- */
-#define TRANSMIT_CHL 24
-#define RECEIVE_STD_CHL 0
-#define RECEIVE_EXT_CHL 4
-#define RECEIVE_RTR_CHL 8
-#define RECEIVE_EXT_RTR_CHL 12
-#define MAX_CHL_NUMBER 32
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin can registers layout
- */
-struct bfin_can_mask_regs {
- __BFP(aml);
- __BFP(amh);
-};
-
-struct bfin_can_channel_regs {
- /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
- u16 data[8];
- __BFP(dlc);
- __BFP(tsv);
- __BFP(id0);
- __BFP(id1);
-};
-
-struct bfin_can_regs {
- /*
- * global control and status registers
- */
- __BFP(mc1); /* offset 0x00 */
- __BFP(md1); /* offset 0x04 */
- __BFP(trs1); /* offset 0x08 */
- __BFP(trr1); /* offset 0x0c */
- __BFP(ta1); /* offset 0x10 */
- __BFP(aa1); /* offset 0x14 */
- __BFP(rmp1); /* offset 0x18 */
- __BFP(rml1); /* offset 0x1c */
- __BFP(mbtif1); /* offset 0x20 */
- __BFP(mbrif1); /* offset 0x24 */
- __BFP(mbim1); /* offset 0x28 */
- __BFP(rfh1); /* offset 0x2c */
- __BFP(opss1); /* offset 0x30 */
- u32 __pad1[3];
- __BFP(mc2); /* offset 0x40 */
- __BFP(md2); /* offset 0x44 */
- __BFP(trs2); /* offset 0x48 */
- __BFP(trr2); /* offset 0x4c */
- __BFP(ta2); /* offset 0x50 */
- __BFP(aa2); /* offset 0x54 */
- __BFP(rmp2); /* offset 0x58 */
- __BFP(rml2); /* offset 0x5c */
- __BFP(mbtif2); /* offset 0x60 */
- __BFP(mbrif2); /* offset 0x64 */
- __BFP(mbim2); /* offset 0x68 */
- __BFP(rfh2); /* offset 0x6c */
- __BFP(opss2); /* offset 0x70 */
- u32 __pad2[3];
- __BFP(clock); /* offset 0x80 */
- __BFP(timing); /* offset 0x84 */
- __BFP(debug); /* offset 0x88 */
- __BFP(status); /* offset 0x8c */
- __BFP(cec); /* offset 0x90 */
- __BFP(gis); /* offset 0x94 */
- __BFP(gim); /* offset 0x98 */
- __BFP(gif); /* offset 0x9c */
- __BFP(control); /* offset 0xa0 */
- __BFP(intr); /* offset 0xa4 */
- __BFP(version); /* offset 0xa8 */
- __BFP(mbtd); /* offset 0xac */
- __BFP(ewr); /* offset 0xb0 */
- __BFP(esr); /* offset 0xb4 */
- u32 __pad3[2];
- __BFP(ucreg); /* offset 0xc0 */
- __BFP(uccnt); /* offset 0xc4 */
- __BFP(ucrc); /* offset 0xc8 */
- __BFP(uccnf); /* offset 0xcc */
- u32 __pad4[1];
- __BFP(version2); /* offset 0xd4 */
- u32 __pad5[10];
-
- /*
- * channel(mailbox) mask and message registers
- */
- struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
- struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
-};
-
-#undef __BFP
-
-/* CAN_CONTROL Masks */
-#define SRS 0x0001 /* Software Reset */
-#define DNM 0x0002 /* Device Net Mode */
-#define ABO 0x0004 /* Auto-Bus On Enable */
-#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
-#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define CSR 0x0040 /* CAN Suspend Mode Request */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-
-/* CAN_STATUS Masks */
-#define WT 0x0001 /* TX Warning Flag */
-#define WR 0x0002 /* RX Warning Flag */
-#define EP 0x0004 /* Error Passive Mode */
-#define EBO 0x0008 /* Error Bus Off Mode */
-#define SMA 0x0020 /* Sleep Mode Acknowledge */
-#define CSA 0x0040 /* Suspend Mode Acknowledge */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define MBPTR 0x1F00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode */
-#define REC 0x8000 /* Receive Mode */
-
-/* CAN_CLOCK Masks */
-#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
-
-/* CAN_TIMING Masks */
-#define TSEG1 0x000F /* Time Segment 1 */
-#define TSEG2 0x0070 /* Time Segment 2 */
-#define SAM 0x0080 /* Sampling */
-#define SJW 0x0300 /* Synchronization Jump Width */
-
-/* CAN_DEBUG Masks */
-#define DEC 0x0001 /* Disable CAN Error Counters */
-#define DRI 0x0002 /* Disable CAN RX Input */
-#define DTO 0x0004 /* Disable CAN TX Output */
-#define DIL 0x0008 /* Disable CAN Internal Loop */
-#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
-#define MRB 0x0020 /* Mode Read Back Enable */
-#define CDE 0x8000 /* CAN Debug Enable */
-
-/* CAN_CEC Masks */
-#define RXECNT 0x00FF /* Receive Error Counter */
-#define TXECNT 0xFF00 /* Transmit Error Counter */
-
-/* CAN_INTR Masks */
-#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
-#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
-#define GIRQ 0x0004 /* Global Interrupt */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-#define CANTX 0x0040 /* CAN TX Bus Value */
-#define CANRX 0x0080 /* CAN RX Bus Value */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
-#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define IDE 0x2000 /* Identifier Extension */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define AME 0x8000 /* Acceptance Mask Enable */
-
-/* CAN_MBxx_TIMESTAMP Masks */
-#define TSV 0xFFFF /* Timestamp */
-
-/* CAN_MBxx_LENGTH Masks */
-#define DLC 0x000F /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks */
-#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
-#define FMD 0x4000 /* Full Mask Data Field Enable */
-#define FDF 0x8000 /* Filter On Data Field Enable */
-
-/* CAN_MC1 Masks */
-#define MC0 0x0001 /* Enable Mailbox 0 */
-#define MC1 0x0002 /* Enable Mailbox 1 */
-#define MC2 0x0004 /* Enable Mailbox 2 */
-#define MC3 0x0008 /* Enable Mailbox 3 */
-#define MC4 0x0010 /* Enable Mailbox 4 */
-#define MC5 0x0020 /* Enable Mailbox 5 */
-#define MC6 0x0040 /* Enable Mailbox 6 */
-#define MC7 0x0080 /* Enable Mailbox 7 */
-#define MC8 0x0100 /* Enable Mailbox 8 */
-#define MC9 0x0200 /* Enable Mailbox 9 */
-#define MC10 0x0400 /* Enable Mailbox 10 */
-#define MC11 0x0800 /* Enable Mailbox 11 */
-#define MC12 0x1000 /* Enable Mailbox 12 */
-#define MC13 0x2000 /* Enable Mailbox 13 */
-#define MC14 0x4000 /* Enable Mailbox 14 */
-#define MC15 0x8000 /* Enable Mailbox 15 */
-
-/* CAN_MC2 Masks */
-#define MC16 0x0001 /* Enable Mailbox 16 */
-#define MC17 0x0002 /* Enable Mailbox 17 */
-#define MC18 0x0004 /* Enable Mailbox 18 */
-#define MC19 0x0008 /* Enable Mailbox 19 */
-#define MC20 0x0010 /* Enable Mailbox 20 */
-#define MC21 0x0020 /* Enable Mailbox 21 */
-#define MC22 0x0040 /* Enable Mailbox 22 */
-#define MC23 0x0080 /* Enable Mailbox 23 */
-#define MC24 0x0100 /* Enable Mailbox 24 */
-#define MC25 0x0200 /* Enable Mailbox 25 */
-#define MC26 0x0400 /* Enable Mailbox 26 */
-#define MC27 0x0800 /* Enable Mailbox 27 */
-#define MC28 0x1000 /* Enable Mailbox 28 */
-#define MC29 0x2000 /* Enable Mailbox 29 */
-#define MC30 0x4000 /* Enable Mailbox 30 */
-#define MC31 0x8000 /* Enable Mailbox 31 */
-
-/* CAN_MD1 Masks */
-#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
-#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
-#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
-#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
-#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
-#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
-#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
-#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
-#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
-#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
-#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
-#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
-#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
-#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
-#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
-#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
-
-/* CAN_MD2 Masks */
-#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
-#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
-#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
-#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
-#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
-#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
-#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
-#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
-#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
-#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
-#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
-#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
-#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
-#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
-#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
-#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
-
-/* CAN_RMP1 Masks */
-#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
-#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
-#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
-#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
-#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
-#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
-#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
-#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
-#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
-#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
-#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
-#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
-#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
-#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
-#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
-#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks */
-#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
-#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
-#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
-#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
-#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
-#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
-#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
-#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
-#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
-#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
-#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
-#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
-#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
-#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
-#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
-#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks */
-#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
-#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
-#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
-#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
-#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
-#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
-#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
-#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
-#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
-#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
-#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
-#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
-#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
-#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
-#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
-#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
-
-/* CAN_RML2 Masks */
-#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
-#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
-#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
-#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
-#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
-#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
-#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
-#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
-#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
-#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
-#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
-#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
-#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
-#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
-#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
-#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
-
-/* CAN_OPSS1 Masks */
-#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
-#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
-#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
-#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
-#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
-#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
-#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
-#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
-#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
-#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
-#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
-#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
-#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
-#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
-#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
-#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
-
-/* CAN_OPSS2 Masks */
-#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
-#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
-#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
-#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
-#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
-#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
-#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
-#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
-#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
-#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
-#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
-#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
-#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
-#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
-#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
-#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
-
-/* CAN_TRR1 Masks */
-#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
-#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
-#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
-#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
-#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
-#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
-#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
-#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
-#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
-#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
-#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks */
-#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks */
-#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
-#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
-#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
-#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
-#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
-#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
-#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
-#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
-#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
-#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
-#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
-#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
-#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
-#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
-#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
-#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
-
-/* CAN_TRS2 Masks */
-#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
-#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
-#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
-#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
-#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
-#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
-#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
-#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
-#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
-#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
-#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
-#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
-#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
-#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
-#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
-#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
-
-/* CAN_AA1 Masks */
-#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
-#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
-#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
-#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
-#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
-#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
-#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
-#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
-#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
-#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
-#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
-#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
-#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
-#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
-#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
-#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
-
-/* CAN_AA2 Masks */
-#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
-#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
-#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
-#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
-#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
-#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
-#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
-#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
-#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
-#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
-#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
-#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
-#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
-#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
-#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
-#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
-
-/* CAN_TA1 Masks */
-#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
-#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
-#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
-#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
-#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
-#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
-#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
-#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
-#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
-#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
-#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
-#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
-#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
-#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
-#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
-#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
-
-/* CAN_TA2 Masks */
-#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
-#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
-#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
-#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
-#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
-#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
-#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
-#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
-#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
-#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
-#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
-#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
-#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
-#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
-#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
-#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
-
-/* CAN_MBTD Masks */
-#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
-#define TDA 0x0040 /* Temporary Disable Acknowledge */
-#define TDR 0x0080 /* Temporary Disable Request */
-
-/* CAN_RFH1 Masks */
-#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
-#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
-#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
-#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
-#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
-#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
-#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
-#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
-#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
-#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
-#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
-#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
-#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
-#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
-#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
-#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
-
-/* CAN_RFH2 Masks */
-#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
-#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
-#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
-#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
-#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
-#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
-#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
-#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
-#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
-#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
-#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
-#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
-#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
-#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
-#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
-#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
-
-/* CAN_MBTIF1 Masks */
-#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
-#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
-#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
-#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
-#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
-#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
-#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
-#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
-#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
-#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
-#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
-#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
-#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
-#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
-#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
-#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBTIF2 Masks */
-#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
-#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
-#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
-#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
-#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
-#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
-#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
-#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
-#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
-#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
-#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
-#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
-#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
-#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
-#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
-#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBRIF1 Masks */
-#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
-#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
-#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
-#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
-#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
-#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
-#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
-#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
-#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
-#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
-#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
-#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
-#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
-#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
-#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
-#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBRIF2 Masks */
-#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
-#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
-#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
-#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
-#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
-#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
-#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
-#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
-#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
-#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
-#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
-#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
-#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
-#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
-#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
-#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBIM1 Masks */
-#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
-#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
-#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
-#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
-#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
-#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
-#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
-#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
-#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
-#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
-#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
-#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
-#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
-#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
-#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
-#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
-
-/* CAN_MBIM2 Masks */
-#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
-#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
-#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
-#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
-#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
-#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
-#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
-#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
-#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
-#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
-#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
-#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
-#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
-#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
-#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
-#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
-
-/* CAN_GIM Masks */
-#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
-#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
-#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
-#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
-#define ADIM 0x0400 /* Enable Access Denied Interrupt */
-
-/* CAN_GIS Masks */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define WUIS 0x0010 /* Wake-Up IRQ Status */
-#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
-#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
-#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
-#define ADIS 0x0400 /* Access Denied IRQ Status */
-
-/* CAN_GIF Masks */
-#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
-#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
-#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
-#define BOIF 0x0008 /* Bus Off IRQ Flag */
-#define WUIF 0x0010 /* Wake-Up IRQ Flag */
-#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
-#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
-#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
-#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
-#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
-#define ADIF 0x0400 /* Access Denied IRQ Flag */
-
-/* CAN_UCCNF Masks */
-#define UCCNF 0x000F /* Universal Counter Mode */
-#define UC_STAMP 0x0001 /* Timestamp Mode */
-#define UC_WDOG 0x0002 /* Watchdog Mode */
-#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
-#define UC_ERROR 0x0006 /* CAN Error Frame Count */
-#define UC_OVER 0x0007 /* CAN Overload Frame Count */
-#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
-#define UC_AA 0x0009 /* TX Abort Count */
-#define UC_TA 0x000A /* TX Successful Count */
-#define UC_REJECT 0x000B /* RX Message Rejected Count */
-#define UC_RML 0x000C /* RX Message Lost Count */
-#define UC_RX 0x000D /* Total Successful RX Messages Count */
-#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
-#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
-#define UCRC 0x0020 /* Universal Counter Reload/Clear */
-#define UCCT 0x0040 /* Universal Counter CAN Trigger */
-#define UCE 0x0080 /* Universal Counter Enable */
-
-/* CAN_ESR Masks */
-#define ACKE 0x0004 /* Acknowledge Error */
-#define SER 0x0008 /* Stuff Error */
-#define CRCE 0x0010 /* CRC Error */
-#define SA0 0x0020 /* Stuck At Dominant Error */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-
-/* CAN_EWR Masks */
-#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
deleted file mode 100644
index 6319f4e49083..000000000000
--- a/arch/blackfin/include/asm/bfin_dma.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * bfin_dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_DMA_H__
-#define __ASM_BFIN_DMA_H__
-
-#include <linux/types.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN 0x0001 /* DMA Channel Enable */
-#define WNR 0x0002 /* Channel Direction (W/R*) */
-#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
-#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
-
-#ifdef CONFIG_BF60x
-
-#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
-#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
-#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
-#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
-#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
-#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
-#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
-#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
-#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
-#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
-#define DI_EN DI_EN_X /* Data Interrupt Enable */
-#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
-#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
-#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
-#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
-#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
-#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
-#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
-#define NDSIZE 0x00070000 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
-#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
-#define DMAFLOW_LARGE DMAFLOW_LIST
-#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
-#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
-#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
-#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
-#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
-#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
-#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
-
-#else
-
-#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
-#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
-#define RESTART 0x0020 /* DMA Buffer Clear */
-#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
-#define DI_EN 0x0080 /* Data Interrupt Enable */
-#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
-#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
-#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
-#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
-#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
-#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
-#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
-#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
-#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
-#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
-#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define NDSIZE 0x0f00 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
-#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
-#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
-#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
-
-#endif
-#define DMAFLOW 0x7000 /* Flow Control */
-#define DMAFLOW_STOP 0x0000 /* Stop Mode */
-#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
-#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
-#ifdef CONFIG_BF60x
-#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
-#else
-#define DMA_PIRQ 0
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin dma registers layout
- */
-struct bfin_dma_regs {
- u32 next_desc_ptr;
- u32 start_addr;
-#ifdef CONFIG_BF60x
- u32 cfg;
- u32 x_count;
- u32 x_modify;
- u32 y_count;
- u32 y_modify;
- u32 pad1;
- u32 pad2;
- u32 curr_desc_ptr;
- u32 prev_desc_ptr;
- u32 curr_addr;
- u32 irq_status;
- u32 curr_x_count;
- u32 curr_y_count;
- u32 pad3;
- u32 bw_limit_count;
- u32 curr_bw_limit_count;
- u32 bw_monitor_count;
- u32 curr_bw_monitor_count;
-#else
- __BFP(config);
- u32 __pad0;
- __BFP(x_count);
- __BFP(x_modify);
- __BFP(y_count);
- __BFP(y_modify);
- u32 curr_desc_ptr;
- u32 curr_addr;
- __BFP(irq_status);
- __BFP(peripheral_map);
- __BFP(curr_x_count);
- u32 __pad1;
- __BFP(curr_y_count);
- u32 __pad2;
-#endif
-};
-
-#ifndef CONFIG_BF60x
-/*
- * bfin handshake mdma registers layout
- */
-struct bfin_hmdma_regs {
- __BFP(control);
- __BFP(ecinit);
- __BFP(bcinit);
- __BFP(ecurgent);
- __BFP(ecoverflow);
- __BFP(ecount);
- __BFP(bcount);
-};
-#endif
-
-#undef __BFP
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
deleted file mode 100644
index bf52e1f32257..000000000000
--- a/arch/blackfin/include/asm/bfin_pfmon.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Blackfin Performance Monitor definitions
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef __ASM_BFIN_PFMON_H__
-#define __ASM_BFIN_PFMON_H__
-
-/* PFCTL Masks */
-#define PFMON_MASK 0xff
-#define PFCEN_MASK 0x3
-#define PFCEN_DISABLE 0x0
-#define PFCEN_ENABLE_USER 0x1
-#define PFCEN_ENABLE_SUPV 0x2
-#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
-
-#define PFPWR_P 0
-#define PEMUSW0_P 2
-#define PFCEN0_P 3
-#define PFMON0_P 5
-#define PEMUSW1_P 13
-#define PFCEN1_P 14
-#define PFMON1_P 16
-#define PFCNT0_P 24
-#define PFCNT1_P 25
-
-#define PFPWR (1 << PFPWR_P)
-#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
-#define PEMUSW0 PEMUSW(0, 1)
-#define PEMUSW1 PEMUSW(1, 1)
-#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
-#define PFCEN0 PFCEN(0, PFCEN_MASK)
-#define PFCEN1 PFCEN(1, PFCEN_MASK)
-#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
-#define PFCNT0 PFCNT(0, 1)
-#define PFCNT1 PFCNT(1, 1)
-#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
-#define PFMON0 PFMON(0, PFMON_MASK)
-#define PFMON1 PFMON(1, PFMON_MASK)
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
deleted file mode 100644
index a4e872e16e75..000000000000
--- a/arch/blackfin/include/asm/bfin_ppi.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * bfin_ppi.h - interface to Blackfin PPIs
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PPI_H__
-#define __ASM_BFIN_PPI_H__
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin ppi registers layout
- */
-struct bfin_ppi_regs {
- __BFP(control);
- __BFP(status);
- __BFP(count);
- __BFP(delay);
- __BFP(frame);
-};
-
-/*
- * bfin eppi registers layout
- */
-struct bfin_eppi_regs {
- __BFP(status);
- __BFP(hcount);
- __BFP(hdelay);
- __BFP(vcount);
- __BFP(vdelay);
- __BFP(frame);
- __BFP(line);
- __BFP(clkdiv);
- u32 control;
- u32 fs1w_hbl;
- u32 fs1p_avpl;
- u32 fs2w_lvb;
- u32 fs2p_lavf;
- u32 clip;
-};
-
-/*
- * bfin eppi3 registers layout
- */
-struct bfin_eppi3_regs {
- u32 stat;
- u32 hcnt;
- u32 hdly;
- u32 vcnt;
- u32 vdly;
- u32 frame;
- u32 line;
- u32 clkdiv;
- u32 ctl;
- u32 fs1_wlhb;
- u32 fs1_paspl;
- u32 fs2_wlvb;
- u32 fs2_palpf;
- u32 imsk;
- u32 oddclip;
- u32 evenclip;
- u32 fs1_dly;
- u32 fs2_dly;
- u32 ctl2;
-};
-
-#undef __BFP
-
-#ifdef EPPI0_CTL2
-#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
-#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
-#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
-#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
-#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
-#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
-#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
-#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
-#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
-#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
-
-#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
-
-#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
-
-#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
-
-#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
-
-#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
-
-#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
-
-#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
-
-#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
-#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
-#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
-#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
-#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
-#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
-#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
-#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
-#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
-#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
-#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
-#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
-#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
-#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
-#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
-#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
-#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
-#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
-#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
-#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
-#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
-#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
-#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
-#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
-#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
-#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
-#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
-#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
-#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
-#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
-#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
-#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
-#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
-#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
-#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
-#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
-#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
-#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
-#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
-#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
-#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
-#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
-#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
-#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
-#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
-#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
-#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
-#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
-
-#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
-#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
-#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
-#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
-
-#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
-#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
-
-#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
-#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
-#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
-#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
-#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
-#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
-
-#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
-#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
-
-#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
-#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
-
-#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
deleted file mode 100644
index a99957ea9e9b..000000000000
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Blackfin Secure Digital Host (SDH) definitions
- *
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SDH_H__
-#define __BFIN_SDH_H__
-
-/* Platform resources */
-struct bfin_sd_host {
- int dma_chan;
- int irq_int0;
- int irq_int1;
- u16 pin_req[7];
-};
-
-/* SDH_COMMAND bitmasks */
-#define CMD_IDX 0x3f /* Command Index */
-#define CMD_RSP (1 << 6) /* Response */
-#define CMD_L_RSP (1 << 7) /* Long Response */
-#define CMD_INT_E (1 << 8) /* Command Interrupt */
-#define CMD_PEND_E (1 << 9) /* Command Pending */
-#define CMD_E (1 << 10) /* Command Enable */
-#ifdef RSI_BLKSZ
-#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
-#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
-#endif
-
-/* SDH_PWR_CTL bitmasks */
-#ifndef RSI_BLKSZ
-#define PWR_ON 0x3 /* Power On */
-#define SD_CMD_OD (1 << 6) /* Open Drain Output */
-#define ROD_CTL (1 << 7) /* Rod Control */
-#endif
-
-/* SDH_CLK_CTL bitmasks */
-#define CLKDIV 0xff /* MC_CLK Divisor */
-#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
-#define PWR_SV_E (1 << 9) /* Power Save Enable */
-#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
-#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
-#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
-#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
-#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
-
-/* SDH_RESP_CMD bitmasks */
-#define RESP_CMD 0x3f /* Response Command */
-
-/* SDH_DATA_CTL bitmasks */
-#define DTX_E (1 << 0) /* Data Transfer Enable */
-#define DTX_DIR (1 << 1) /* Data Transfer Direction */
-#define DTX_MODE (1 << 2) /* Data Transfer Mode */
-#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
-#ifndef RSI_BLKSZ
-#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
-#else
-
-/* Bit masks for SDH_BLK_SIZE */
-#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
-#endif
-
-/* SDH_STATUS bitmasks */
-#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
-#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
-#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
-#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
-#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
-#define RX_OVERRUN (1 << 5) /* Receive Overrun */
-#define CMD_RESP_END (1 << 6) /* CMD Response End */
-#define CMD_SENT (1 << 7) /* CMD Sent */
-#define DAT_END (1 << 8) /* Data End */
-#define START_BIT_ERR (1 << 9) /* Start Bit Error */
-#define DAT_BLK_END (1 << 10) /* Data Block End */
-#define CMD_ACT (1 << 11) /* CMD Active */
-#define TX_ACT (1 << 12) /* Transmit Active */
-#define RX_ACT (1 << 13) /* Receive Active */
-#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
-#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
-#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
-#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
-#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
-#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
-#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
-#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
-
-/* SDH_STATUS_CLR bitmasks */
-#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
-#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
-#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
-#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
-#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
-#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
-#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
-#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
-#define DAT_END_STAT (1 << 8) /* Data End Status */
-#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
-#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
-
-/* SDH_MASK0 bitmasks */
-#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
-#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
-#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
-#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
-#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
-#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
-#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
-#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
-#define DAT_END_MASK (1 << 8) /* Data End Mask */
-#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
-#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
-#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
-#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
-#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
-#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
-#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
-#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
-#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
-#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
-#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
-#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
-#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
-
-/* SDH_FIFO_CNT bitmasks */
-#define FIFO_COUNT 0x7fff /* FIFO Count */
-
-/* SDH_E_STATUS bitmasks */
-#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
-#define SD_CARD_DET (1 << 4) /* SD Card Detect */
-#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
-#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
-#define SD_CARD_READY (1 << 17) /* Card Ready */
-
-/* SDH_E_MASK bitmasks */
-#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
-#define SCD_MSK (1 << 4) /* Mask Card Detect */
-#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
-
-/* SDH_CFG bitmasks */
-#define CLKS_EN (1 << 0) /* Clocks Enable */
-#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
-#define MWE (1 << 3) /* Moving Window Enable */
-#define SD_RST (1 << 4) /* SDMMC Reset */
-#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
-#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
-#ifndef RSI_BLKSZ
-#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
-#else
-#define PWR_ON 0x600 /* Power On */
-#define SD_CMD_OD (1 << 11) /* Open Drain Output */
-#define BOOT_EN (1 << 12) /* Boot Enable */
-#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
-#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
-#endif
-
-/* SDH_RD_WAIT_EN bitmasks */
-#define RWR (1 << 0) /* Read Wait Request */
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
deleted file mode 100644
index b550ada7321b..000000000000
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ASM_SERIAL_H__
-#define __BFIN_ASM_SERIAL_H__
-
-#include <linux/circ_buf.h>
-#include <linux/serial_core.h>
-#include <linux/spinlock.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include <mach/anomaly.h>
-#include <mach/bfin_serial.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
- defined(CONFIG_BFIN_UART1_CTSRTS) || \
- defined(CONFIG_BFIN_UART2_CTSRTS) || \
- defined(CONFIG_BFIN_UART3_CTSRTS)
-# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
-# define SERIAL_BFIN_HARD_CTSRTS
-# else
-# define SERIAL_BFIN_CTSRTS
-# endif
-#endif
-
-struct bfin_serial_port {
- struct uart_port port;
- unsigned int old_status;
- int tx_irq;
- int rx_irq;
- int status_irq;
-#ifndef BFIN_UART_BF54X_STYLE
- unsigned int lsr;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_DMA
- int tx_done;
- int tx_count;
- struct circ_buf rx_dma_buf;
- struct timer_list rx_dma_timer;
- int rx_dma_nrows;
- spinlock_t rx_lock;
- unsigned int tx_dma_channel;
- unsigned int rx_dma_channel;
- struct work_struct tx_dma_workqueue;
-#elif ANOMALY_05000363
- unsigned int anomaly_threshold;
-#endif
-#if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
- int cts_pin;
- int rts_pin;
-#endif
-};
-
-#ifdef BFIN_UART_BF60X_STYLE
-
-/* UART_CTL Masks */
-#define UCEN 0x1 /* Enable UARTx Clocks */
-#define LOOP_ENA 0x2 /* Loopback Mode Enable */
-#define UMOD_MDB 0x10 /* Enable MDB Mode */
-#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
-#define UMOD_MASK 0x30 /* Uart Mode Mask */
-#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
-#define WLS_MASK 0x300 /* Word length Select Mask */
-#define WLS_OFFSET 8 /* Word length Select Offset */
-#define STB 0x1000 /* Stop Bits */
-#define STBH 0x2000 /* Half Stop Bits */
-#define PEN 0x4000 /* Parity Enable */
-#define EPS 0x8000 /* Even Parity Select */
-#define STP 0x10000 /* Stick Parity */
-#define FPE 0x20000 /* Force Parity Error On Transmit */
-#define FFE 0x40000 /* Force Framing Error On Transmit */
-#define SB 0x80000 /* Set Break */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-#define FCPOL 0x400000 /* Flow Control Pin Polarity */
-#define RPOLC 0x800000 /* IrDA RX Polarity Change */
-#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
-#define MRTS 0x2000000 /* Manual Request To Send */
-#define XOFF 0x4000000 /* Transmitter Off */
-#define ARTS 0x8000000 /* Automatic Request To Send */
-#define ACTS 0x10000000 /* Automatic Clear To Send */
-#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
-
-/* UART_STAT Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x80 /* TSR and UART_THR Empty */
-#define TFI 0x100 /* Transmission Finished Indicator */
-
-#define ASTKY 0x200 /* Address Sticky */
-#define ADDR 0x400 /* Address bit status */
-#define RO 0x800 /* Reception Ongoing */
-#define SCTS 0x1000 /* Sticky CTS */
-#define CTS 0x10000 /* Clear To Send */
-#define RFCS 0x20000 /* Receive FIFO Count Status */
-
-/* UART_CLOCK Masks */
-#define EDBO 0x80000000 /* Enable Devide by One */
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-/* UART_LCR Masks */
-#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
-#define WLS_MASK 0x03 /* Word length Select Mask */
-#define WLS_OFFSET 0 /* Word length Select Offset */
-#define STB 0x04 /* Stop Bits */
-#define PEN 0x08 /* Parity Enable */
-#define EPS 0x10 /* Even Parity Select */
-#define STP 0x20 /* Stick Parity */
-#define SB 0x40 /* Set Break */
-#define DLAB 0x80 /* Divisor Latch Access */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-
-/* UART_LSR Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x40 /* TSR and UART_THR Empty */
-#define TFI 0x80 /* Transmission Finished Indicator */
-
-/* UART_MCR Masks */
-#define XOFF 0x01 /* Transmitter Off */
-#define MRTS 0x02 /* Manual Request To Send */
-#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x08 /* Receive FIFO RTS Threshold */
-#define LOOP_ENA 0x10 /* Loopback Mode Enable */
-#define FCPOL 0x20 /* Flow Control Pin Polarity */
-#define ARTS 0x40 /* Automatic Request To Send */
-#define ACTS 0x80 /* Automatic Clear To Send */
-
-/* UART_MSR Masks */
-#define SCTS 0x01 /* Sticky CTS */
-#define CTS 0x10 /* Clear To Send */
-#define RFCS 0x20 /* Receive FIFO Count Status */
-
-/* UART_GCTL Masks */
-#define UCEN 0x01 /* Enable UARTx Clocks */
-#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
-#define UMOD_MASK 0x02 /* Uart Mode Mask */
-#define TPOLC 0x04 /* IrDA TX Polarity Change */
-#define RPOLC 0x08 /* IrDA RX Polarity Change */
-#define FPE 0x10 /* Force Parity Error On Transmit */
-#define FFE 0x20 /* Force Framing Error On Transmit */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-/* UART_IER Masks */
-#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
-#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI 0x04 /* Enable RX Status Interrupt */
-#define EDSSI 0x08 /* Enable Modem Status Interrupt */
-#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
-#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
-#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
-
-#if defined(BFIN_UART_BF60X_STYLE)
-# define OFFSET_REDIV 0x00 /* Version ID Register */
-# define OFFSET_CTL 0x04 /* Control Register */
-# define OFFSET_STAT 0x08 /* Status Register */
-# define OFFSET_SCR 0x0C /* SCR Scratch Register */
-# define OFFSET_CLK 0x10 /* Clock Rate Register */
-# define OFFSET_IER 0x14 /* Interrupt Enable Register */
-# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
-# define OFFSET_RBR 0x20 /* Receive Buffer register */
-# define OFFSET_THR 0x24 /* Transmit Holding register */
-#elif defined(BFIN_UART_BF54X_STYLE)
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_GCTL 0x08 /* Global Control Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
-# define OFFSET_THR 0x28 /* Transmit Holding register */
-# define OFFSET_RBR 0x2C /* Receive Buffer register */
-#else /* BF533 style */
-# define OFFSET_THR 0x00 /* Transmit Holding register */
-# define OFFSET_RBR 0x00 /* Receive Buffer register */
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_IER 0x04 /* Interrupt Enable Register */
-# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_GCTL 0x24 /* Global Control Register */
-/* code should not need IIR, so force build error if they use it */
-# undef OFFSET_IIR
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct bfin_uart_regs {
-#if defined(BFIN_UART_BF60X_STYLE)
- u32 revid;
- u32 ctl;
- u32 stat;
- u32 scr;
- u32 clk;
- u32 ier;
- u32 ier_set;
- u32 ier_clear;
- u32 rbr;
- u32 thr;
- u32 taip;
- u32 tsr;
- u32 rsr;
- u32 txdiv;
- u32 rxdiv;
-#elif defined(BFIN_UART_BF54X_STYLE)
- __BFP(dll);
- __BFP(dlh);
- __BFP(gctl);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- __BFP(ier_set);
- __BFP(ier_clear);
- __BFP(thr);
- __BFP(rbr);
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __pad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __pad1;
- const __BFP(iir);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- const u32 __pad2;
- __BFP(gctl);
-#endif
-};
-#undef __BFP
-
-#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
-
-/*
-#ifndef port_membase
-# define port_membase(p) 0
-#endif
-*/
-#ifdef BFIN_UART_BF60X_STYLE
-
-#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
-#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
-#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
-#define UART_GET_GCTL(p) UART_GET_CTL(p)
-#define UART_GET_LCR(p) UART_GET_CTL(p)
-#define UART_GET_MCR(p) UART_GET_CTL(p)
-#if ANOMALY_16000030
-#define UART_GET_STAT(p) \
-({ \
- u32 __ret; \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
- hard_local_irq_restore(flags); \
- __ret; \
-})
-#else
-#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
-#endif
-#define UART_GET_MSR(p) UART_GET_STAT(p)
-
-#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
-#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
-#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
-
-#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
-#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
-
-#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
-#define UART_GET_LSR(p) UART_GET_STAT(p)
-#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
-#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
-#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
-#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
-#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
-#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
-#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
-#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
-
-#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
-#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
-#define UART_PUT_CLK(p, v) do \
-{\
-UART_PUT_DLL(p, v & 0xFF); \
-UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
-
-#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
-#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
-#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
-
-#ifdef BFIN_UART_BF54X_STYLE
-
-#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
-#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
-
-#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
-#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
-#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BF533 style */
-
-#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
-#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
-#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
-
-#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
-#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
-
-#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
-#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
-
-/*
-#ifndef put_lsr_cache
-# define put_lsr_cache(p, v)
-#endif
-#ifndef get_lsr_cache
-# define get_lsr_cache(p) 0
-#endif
-*/
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline void UART_CLEAR_LSR(void *p)
-{
- put_lsr_cache(p, 0);
- bfin_write16(port_membase(p) + OFFSET_LSR, -1);
-}
-static inline unsigned int UART_GET_LSR(void *p)
-{
- unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
- put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
- return lsr | get_lsr_cache(p);
-}
-static inline void UART_PUT_LSR(void *p, uint16_t val)
-{
- put_lsr_cache(p, get_lsr_cache(p) & ~val);
-}
-
-/* This handles soft CTS/RTS */
-#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#endif /* BFIN_UART_BF54X_STYLE */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-#ifndef BFIN_UART_TX_FIFO_SIZE
-# define BFIN_UART_TX_FIFO_SIZE 2
-#endif
-
-#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
deleted file mode 100644
index b2d5e733079e..000000000000
--- a/arch/blackfin/include/asm/bfin_simple_timer.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _bfin_simple_timer_h_
-#define _bfin_simple_timer_h_
-
-#include <linux/ioctl.h>
-
-#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
-
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
-#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3)
-#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4)
-#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
-#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
-#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
-#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
-
-#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1
-#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
deleted file mode 100644
index 50b9dfd4839f..000000000000
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_SPORT_H__
-#define __BFIN_SPORT_H__
-
-
-#include <linux/types.h>
-#include <uapi/asm/bfin_sport.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct sport_register {
- __BFP(tcr1);
- __BFP(tcr2);
- __BFP(tclkdiv);
- __BFP(tfsdiv);
- union {
- u32 tx32;
- u16 tx16;
- };
- u32 __pad_tx;
- union {
- u32 rx32; /* use the anomaly wrapper below */
- u16 rx16;
- };
- u32 __pad_rx;
- __BFP(rcr1);
- __BFP(rcr2);
- __BFP(rclkdiv);
- __BFP(rfsdiv);
- __BFP(stat);
- __BFP(chnl);
- __BFP(mcmc1);
- __BFP(mcmc2);
- u32 mtcs0;
- u32 mtcs1;
- u32 mtcs2;
- u32 mtcs3;
- u32 mrcs0;
- u32 mrcs1;
- u32 mrcs2;
- u32 mrcs3;
-};
-#undef __BFP
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#define bfin_read_sport_rx32(base) \
-({ \
- struct sport_register *__mmrs = (void *)base; \
- u32 __ret; \
- unsigned long flags; \
- if (ANOMALY_05000473) \
- local_irq_save(flags); \
- __ret = __mmrs->rx32; \
- if (ANOMALY_05000473) \
- local_irq_restore(flags); \
- __ret; \
-})
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
deleted file mode 100644
index d82f5fa0ad9f..000000000000
--- a/arch/blackfin/include/asm/bfin_sport3.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * bfin_sport - Analog Devices BF6XX SPORT registers
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _BFIN_SPORT3_H_
-#define _BFIN_SPORT3_H_
-
-#include <linux/types.h>
-
-#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
-#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
-#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
-#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
-#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
-#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
-#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
-#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
-#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
-#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
-#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
-#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
-#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
-#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
-#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
-#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
-#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
-#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
-#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
-#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */
-#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
-#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
-#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
-#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
-#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
-#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
-#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
-#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
-#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
-#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
-#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
-#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
-#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
-
-#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
-#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
-
-#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
-#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
-#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
-#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
-#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
-
-#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
-#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
-
-#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
-#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
-#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
-#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
-#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
-#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
-
-#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
-
-#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
-#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
-#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
-
-struct sport_register {
- u32 spctl;
- u32 div;
- u32 spmctl;
- u32 spcs0;
- u32 spcs1;
- u32 spcs2;
- u32 spcs3;
- u32 spcnt;
- u32 sperrctl;
- u32 spmstat;
- u32 spctl2;
- u32 txa;
- u32 rxa;
- u32 txb;
- u32 rxb;
- u32 revid;
-};
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
deleted file mode 100644
index 211e9c78f6fb..000000000000
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * bfin_twi.h - interface to Blackfin TWIs
- *
- * Copyright 2005-2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_TWI_H__
-#define __ASM_BFIN_TWI_H__
-
-#include <asm/blackfin.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-
-/*
- * ADI twi registers layout
- */
-struct bfin_twi_regs {
- u16 clkdiv;
- u16 dummy1;
- u16 control;
- u16 dummy2;
- u16 slave_ctl;
- u16 dummy3;
- u16 slave_stat;
- u16 dummy4;
- u16 slave_addr;
- u16 dummy5;
- u16 master_ctl;
- u16 dummy6;
- u16 master_stat;
- u16 dummy7;
- u16 master_addr;
- u16 dummy8;
- u16 int_stat;
- u16 dummy9;
- u16 int_mask;
- u16 dummy10;
- u16 fifo_ctl;
- u16 dummy11;
- u16 fifo_stat;
- u16 dummy12;
- u32 __pad[20];
- u16 xmt_data8;
- u16 dummy13;
- u16 xmt_data16;
- u16 dummy14;
- u16 rcv_data8;
- u16 dummy15;
- u16 rcv_data16;
- u16 dummy16;
-};
-
-struct bfin_twi_iface {
- int irq;
- spinlock_t lock;
- char read_write;
- u8 command;
- u8 *transPtr;
- int readNum;
- int writeNum;
- int cur_mode;
- int manual_stop;
- int result;
- struct i2c_adapter adap;
- struct completion complete;
- struct i2c_msg *pmsg;
- int msg_num;
- int cur_msg;
- u16 saved_clkdiv;
- u16 saved_control;
- struct bfin_twi_regs __iomem *regs_base;
-};
-
-/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
-#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
-#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA 0x0080 /* TWI Enable */
-#define SCCB 0x0200 /* SCCB Compatibility Enable */
-
-/* TWI_SLAVE_CTL Masks */
-#define SEN 0x0001 /* Slave Enable */
-#define SADD_LEN 0x0002 /* Slave Address Length */
-#define STDVAL 0x0004 /* Slave Transmit Data Valid */
-#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */
-#define GEN 0x0010 /* General Call Address Matching Enabled */
-
-/* TWI_SLAVE_STAT Masks */
-#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */
-#define GCALL 0x0002 /* General Call Indicator */
-
-/* TWI_MASTER_CTL Masks */
-#define MEN 0x0001 /* Master Mode Enable */
-#define MADD_LEN 0x0002 /* Master Address Length */
-#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
-#define FAST 0x0008 /* Use Fast Mode Timing Specs */
-#define STOP 0x0010 /* Issue Stop Condition */
-#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT 0x3FC0 /* Data Bytes To Transfer */
-#define SDAOVR 0x4000 /* Serial Data Override */
-#define SCLOVR 0x8000 /* Serial Clock Override */
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG 0x0001 /* Master Transfer In Progress */
-#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK 0x0004 /* Address Not Acknowledged */
-#define DNAK 0x0008 /* Data Not Acknowledged */
-#define BUFRDERR 0x0010 /* Buffer Read Error */
-#define BUFWRERR 0x0020 /* Buffer Write Error */
-#define SDASEN 0x0040 /* Serial Data Sense */
-#define SCLSEN 0x0080 /* Serial Clock Sense */
-#define BUSBUSY 0x0100 /* Bus Busy Indicator */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT 0x0001 /* Slave Transfer Initiated */
-#define SCOMP 0x0002 /* Slave Transfer Complete */
-#define SERR 0x0004 /* Slave Transfer Error */
-#define SOVF 0x0008 /* Slave Overflow */
-#define MCOMP 0x0010 /* Master Transfer Complete */
-#define MERR 0x0020 /* Master Transfer Error */
-#define XMTSERV 0x0040 /* Transmit FIFO Service */
-#define RCVSERV 0x0080 /* Receive FIFO Service */
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
-#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
-#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT 0x0003 /* Transmit FIFO Status */
-#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
-#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT 0x000C /* Receive FIFO Status */
-#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
-#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-
-#define DEFINE_TWI_REG(reg_name, reg) \
-static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
- { return bfin_read16(&iface->regs_base->reg); } \
-static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
- { bfin_write16(&iface->regs_base->reg, v); }
-
-DEFINE_TWI_REG(CLKDIV, clkdiv)
-DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
-DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
-DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
-DEFINE_TWI_REG(MASTER_CTL, master_ctl)
-DEFINE_TWI_REG(MASTER_STAT, master_stat)
-DEFINE_TWI_REG(MASTER_ADDR, master_addr)
-DEFINE_TWI_REG(INT_STAT, int_stat)
-DEFINE_TWI_REG(INT_MASK, int_mask)
-DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
-DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
-DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
-#if !ANOMALY_16000030
-DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
-DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
-#else
-static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data8);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-
-static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data16);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-#endif
-
-static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->fifo_ctl);
-}
-
-static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
-{
- bfin_write16(&iface->regs_base->fifo_ctl, v);
- SSYNC();
-}
-
-static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->control);
-}
-
-static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
-{
- SSYNC();
- bfin_write16(&iface->regs_base->control, v);
-}
-#endif
diff --git a/arch/blackfin/include/asm/bfin_watchdog.h b/arch/blackfin/include/asm/bfin_watchdog.h
deleted file mode 100644
index dce09829a095..000000000000
--- a/arch/blackfin/include/asm/bfin_watchdog.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * bfin_watchdog.h - Blackfin watchdog definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_WATCHDOG_H
-#define _BFIN_WATCHDOG_H
-
-/* Bit in SWRST that indicates boot caused by watchdog */
-#define SWRST_RESET_WDOG 0x4000
-
-/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
-#define WDOG_EXPIRED 0x8000
-
-/* Masks for WDEV field in WDOG_CTL register */
-#define ICTL_RESET 0x0
-#define ICTL_NMI 0x2
-#define ICTL_GPI 0x4
-#define ICTL_NONE 0x6
-#define ICTL_MASK 0x6
-
-/* Masks for WDEN field in WDOG_CTL register */
-#define WDEN_MASK 0x0FF0
-#define WDEN_ENABLE 0x0000
-#define WDEN_DISABLE 0x0AD0
-
-#endif
diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h
deleted file mode 100644
index 9e4be5e5e767..000000000000
--- a/arch/blackfin/include/asm/bfrom.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Blackfin on-chip ROM API
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFROM_H__
-#define __BFROM_H__
-
-#include <linux/types.h>
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ 0x00000000 /* read registers */
-#define SYSCTRL_WRITE 0x00000001 /* write registers */
-#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
-#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
-#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
-#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
-
-typedef struct ADI_SYSCTRL_VALUES {
- uint16_t uwVrCtl;
- uint16_t uwPllCtl;
- uint16_t uwPllDiv;
- uint16_t uwPllLockCnt;
- uint16_t uwPllStat;
-} ADI_SYSCTRL_VALUES;
-
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
-
-/* We need a dedicated function since we need to screw with the stack pointer
- * when resetting. The on-chip ROM will save/restore registers on the stack
- * when doing a system reset, so the stack cannot be outside of the chip.
- */
-__attribute__((__noreturn__))
-static inline void bfrom_SoftReset(void *new_stack)
-{
- while (1)
- /*
- * We don't declare the SP as clobbered on purpose, since
- * it confuses the heck out of the compiler, and this function
- * never returns
- */
- __asm__ __volatile__(
- "sp = %[stack];"
- "jump (%[bfrom_syscontrol]);"
- : : [bfrom_syscontrol] "p"(bfrom_SysControl),
- "q0"(SYSCTRL_SOFTRESET),
- "q1"(0),
- "q2"(NULL),
- [stack] "p"(new_stack)
- );
-}
-
-/* OTP Functions */
-static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
-static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
-static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
-
-/* otp command: defines for "command" */
-#define OTP_INIT 0x00000001
-#define OTP_CLOSE 0x00000002
-
-/* otp read/write: defines for "flags" */
-#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF 0x00000001
-#define OTP_NO_ECC 0x00000010 /* do not use ECC */
-#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
-#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
-
-/* Return values for all functions */
-#define OTP_SUCCESS 0x00000000
-#define OTP_MASTER_ERROR 0x001
-#define OTP_WRITE_ERROR 0x003
-#define OTP_READ_ERROR 0x005
-#define OTP_ACC_VIO_ERROR 0x009
-#define OTP_DATA_MULT_ERROR 0x011
-#define OTP_ECC_MULT_ERROR 0x021
-#define OTP_PREV_WR_ERROR 0x041
-#define OTP_DATA_SB_WARN 0x100
-#define OTP_ECC_SB_WARN 0x200
-
-#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
deleted file mode 100644
index b298b654a26f..000000000000
--- a/arch/blackfin/include/asm/bitops.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-#include <linux/compiler.h>
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/find.h>
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/const_hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#include <asm/barrier.h>
-
-#ifndef CONFIG_SMP
-#include <linux/irqflags.h>
-/*
- * clear_bit may not imply a memory barrier
- */
-#include <asm-generic/bitops/atomic.h>
-#include <asm-generic/bitops/non-atomic.h>
-#else
-
-#include <asm/byteorder.h> /* swab32 */
-#include <linux/linkage.h>
-
-asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
-
-static inline void set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_set_asm(a, nr & 0x1f);
-}
-
-static inline void clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_clear_asm(a, nr & 0x1f);
-}
-
-static inline void change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_toggle_asm(a, nr & 0x1f);
-}
-
-static inline int test_bit(int nr, const volatile unsigned long *addr)
-{
- volatile const unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_asm(a, nr & 0x1f) != 0;
-}
-
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_set_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_clear_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_toggle_asm(a, nr & 0x1f);
-}
-
-#define test_bit __skip_test_bit
-#include <asm-generic/bitops/non-atomic.h>
-#undef test_bit
-
-#endif /* CONFIG_SMP */
-
-/* Needs to be after test_bit and friends */
-#include <asm-generic/bitops/le.h>
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-static inline unsigned int __arch_hweight32(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("%0.l = ONES %1;"
- "%0 = %0.l (Z);"
- : "=d" (res) : "d" (w));
- return res;
-}
-
-static inline unsigned int __arch_hweight64(__u64 w)
-{
- return __arch_hweight32((unsigned int)(w >> 32)) +
- __arch_hweight32((unsigned int)w);
-}
-
-static inline unsigned int __arch_hweight16(unsigned int w)
-{
- return __arch_hweight32(w & 0xffff);
-}
-
-static inline unsigned int __arch_hweight8(unsigned int w)
-{
- return __arch_hweight32(w & 0xff);
-}
-
-#endif /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
deleted file mode 100644
index f111f366d758..000000000000
--- a/arch/blackfin/include/asm/blackfin.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Common header file for Blackfin family of processors.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "ssync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "csync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("csync;");
-}
-
-#else /* __ASSEMBLY__ */
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312 || ANOMALY_05000244
-#define SSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- SSYNC; \
- sti scratch;
-
-#define CSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- CSYNC; \
- sti scratch;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/mem_map.h>
-#include <mach/blackfin.h>
-#include <asm/bfin-global.h>
-
-#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
deleted file mode 100644
index 76b2e82ee730..000000000000
--- a/arch/blackfin/include/asm/bug.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BUG_H
-#define _BLACKFIN_BUG_H
-
-#ifdef CONFIG_BUG
-
-/*
- * This can be any undefined 16-bit opcode, meaning
- * ((opcode & 0xc000) != 0xc000)
- * Anything from 0x0001 to 0x000A (inclusive) will work
- */
-#define BFIN_BUG_OPCODE 0x0001
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\",@progbits\n" \
- "2: .long 1b\n" \
- " .long %1\n" \
- " .short %2\n" \
- " .short %3\n" \
- " .org 2b + %4\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \
- "i"(__LINE__), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#else
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\",@progbits\n" \
- "2: .long 1b\n" \
- " .short %1\n" \
- " .org 2b + %2\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#endif /* CONFIG_DEBUG_BUGVERBOSE */
-
-#define BUG() \
- do { \
- _BUG_OR_WARN(0); \
- unreachable(); \
- } while (0)
-
-#define WARN_ON(condition) \
- ({ \
- int __ret_warn_on = !!(condition); \
- if (unlikely(__ret_warn_on)) \
- _BUG_OR_WARN(BUGFLAG_WARNING); \
- unlikely(__ret_warn_on); \
- })
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_WARN_ON
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
deleted file mode 100644
index 568885a2c286..000000000000
--- a/arch/blackfin/include/asm/cache.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h> /* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned \
- __attribute__((__aligned__(L1_CACHE_BYTES), \
- __section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX 5
-
-#if defined(CONFIG_SMP) && \
- !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
- __raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
- __raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
deleted file mode 100644
index 9a5b2c572ebf..000000000000
--- a/arch/blackfin/include/asm/cacheflush.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Blackfin low-level cache routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_CACHEFLUSH_H
-#define _BLACKFIN_CACHEFLUSH_H
-
-#include <asm/blackfin.h> /* for SSYNC() */
-#include <asm/sections.h> /* for _ramend */
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#endif
-
-extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dflush_page(void *page);
-extern void blackfin_invalidate_entire_dcache(void);
-extern void blackfin_invalidate_entire_icache(void);
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#ifdef CONFIG_SMP
-#define flush_icache_range_others(start, end) \
- smp_icache_flush_range_others((start), (end))
-#else
-#define flush_icache_range_others(start, end) do { } while (0)
-#endif
-
-static inline void flush_icache_range(unsigned start, unsigned end)
-{
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- if (end <= physical_mem_end)
- blackfin_dcache_flush_range(start, end);
-#endif
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- if (start >= L2_START && end <= L2_START + L2_LENGTH)
- blackfin_dcache_flush_range(start, end);
-#endif
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- if (end <= physical_mem_end) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- if (start >= L2_START && end <= L2_START + L2_LENGTH) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-}
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
- flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
-} while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
-
-#if defined(CONFIG_BFIN_DCACHE)
-# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
-#else
-# define invalidate_dcache_range(start,end) do { } while (0)
-#endif
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
-#else
-# define flush_dcache_range(start,end) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-# define flush_dcache_page(page) do { } while (0)
-#endif
-
-extern unsigned long reserved_mem_dcache_on;
-extern unsigned long reserved_mem_icache_on;
-
-static inline int bfin_addr_dcacheable(unsigned long addr)
-{
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (addr < (_ramend - DMA_UNCACHED_REGION))
- return 1;
-#endif
-
- if (reserved_mem_dcache_on &&
- addr >= _ramend && addr < physical_mem_end)
- return 1;
-
-#ifdef CONFIG_BFIN_L2_DCACHEABLE
- if (addr >= L2_START && addr < L2_START + L2_LENGTH)
- return 1;
-#endif
-
- return 0;
-}
-
-#endif /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
deleted file mode 100644
index 59af63c0c2be..000000000000
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
-#include <asm/def_LPBlackfin.h>
-
-/*Cache & SRAM Memory*/
-#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
-#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
-/*
-#define MMR_TIMEOUT 0xFFE00010
-*/
-#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
-#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
-#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
-#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
-#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
-#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
-#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
-#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
-#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
-#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
-#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
-#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
-#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
-#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
-#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
-#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
-/*
-#define DTEST_INDEX 0xFFE00304
-*/
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
-/*
-#define DTEST_DATA2 0xFFE00408
-#define DTEST_DATA3 0xFFE0040C
-*/
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
-#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
-#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
-#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
-#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
-#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
-#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
-#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
-#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
-#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
-#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
-#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
-#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
-#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
-#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
-#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
-#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
-#if 0
-#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
-#endif
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
-
-#if !ANOMALY_05000481
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#endif
-
-/* Event/Interrupt Registers*/
-
-#define bfin_read_EVT0() bfin_read32(EVT0)
-#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
-#define bfin_read_EVT1() bfin_read32(EVT1)
-#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
-#define bfin_read_EVT2() bfin_read32(EVT2)
-#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
-#define bfin_read_EVT3() bfin_read32(EVT3)
-#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
-#define bfin_read_EVT4() bfin_read32(EVT4)
-#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
-#define bfin_read_EVT5() bfin_read32(EVT5)
-#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
-#define bfin_read_EVT6() bfin_read32(EVT6)
-#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
-#define bfin_read_EVT7() bfin_read32(EVT7)
-#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
-#define bfin_read_EVT8() bfin_read32(EVT8)
-#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
-#define bfin_read_EVT9() bfin_read32(EVT9)
-#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
-#define bfin_read_EVT10() bfin_read32(EVT10)
-#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
-#define bfin_read_EVT11() bfin_read32(EVT11)
-#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
-#define bfin_read_EVT12() bfin_read32(EVT12)
-#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
-#define bfin_read_EVT13() bfin_read32(EVT13)
-#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
-#define bfin_read_EVT14() bfin_read32(EVT14)
-#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
-#define bfin_read_EVT15() bfin_read32(EVT15)
-#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
-
-/*Core Timer Registers*/
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
-
-/*Debug/MP/Emulation Registers*/
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
-#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
-#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
-#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
-#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
-
-/*Trace Buffer Registers*/
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
-#define bfin_read_TBUF() bfin_read32(TBUF)
-#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
-
-/*Watch Point Control Registers*/
-#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
-#define bfin_read_WPIA0() bfin_read32(WPIA0)
-#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
-#define bfin_read_WPIA1() bfin_read32(WPIA1)
-#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
-#define bfin_read_WPIA2() bfin_read32(WPIA2)
-#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
-#define bfin_read_WPIA3() bfin_read32(WPIA3)
-#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
-#define bfin_read_WPIA4() bfin_read32(WPIA4)
-#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
-#define bfin_read_WPIA5() bfin_read32(WPIA5)
-#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
-#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
-#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
-#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
-#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
-#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
-#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
-#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
-#define bfin_read_WPDA0() bfin_read32(WPDA0)
-#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
-#define bfin_read_WPDA1() bfin_read32(WPDA1)
-#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
-#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
-#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
-#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
-
-/*Performance Monitor Registers*/
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
-
-#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
deleted file mode 100644
index e7134bf94e3c..000000000000
--- a/arch/blackfin/include/asm/checksum.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * akbar.hussain@lineo.com
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CHECKSUM_H
-#define _BFIN_CHECKSUM_H
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- unsigned int carry;
-
- __asm__ ("%0 = %0 + %2;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %3;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %4;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- : "=d" (sum), "=&d" (carry)
- : "d" (daddr), "d" (saddr), "d" ((len + proto) << 8), "0"(sum)
- : "CC");
-
- return (sum);
-}
-#define csum_tcpudp_nofold __csum_tcpudp_nofold
-
-#include <asm-generic/checksum.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
deleted file mode 100644
index 9b3c85b3c288..000000000000
--- a/arch/blackfin/include/asm/clocks.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Common Clock definitions for various kernel files
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CLOCKS_H
-#define _BFIN_CLOCKS_H
-
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_CCLK_DIV_1
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# define CONFIG_CCLK_DIV 1
-#endif
-
-#ifdef CONFIG_CCLK_DIV_2
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# define CONFIG_CCLK_DIV 2
-#endif
-
-#ifdef CONFIG_CCLK_DIV_4
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# define CONFIG_CCLK_DIV 4
-#endif
-
-#ifdef CONFIG_CCLK_DIV_8
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# define CONFIG_CCLK_DIV 8
-#endif
-
-#ifndef CONFIG_PLL_BYPASS
-# ifndef CONFIG_CLKIN_HALF
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-# endif
-
-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-
-#else
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_VCO_MULT 0
-#endif
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- struct clk *parent;
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-int clk_init(void);
-#endif
diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h
deleted file mode 100644
index 253928854299..000000000000
--- a/arch/blackfin/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CMPXCHG__
-#define __ARCH_BLACKFIN_CMPXCHG__
-
-#ifdef CONFIG_SMP
-
-#include <linux/linkage.h>
-
-asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_xchg_1_asm(ptr, x);
- break;
- case 2:
- tmp = __raw_xchg_2_asm(ptr, x);
- break;
- case 4:
- tmp = __raw_xchg_4_asm(ptr, x);
- break;
- }
-
- return tmp;
-}
-
-/*
- * Atomic compare and exchange. Compare OLD with MEM, if identical,
- * store NEW in MEM. Return the initial value in MEM. Success is
- * indicated by comparing RETURN with OLD.
- */
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
- unsigned long new, int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_cmpxchg_1_asm(ptr, new, old);
- break;
- case 2:
- tmp = __raw_cmpxchg_2_asm(ptr, new, old);
- break;
- case 4:
- tmp = __raw_cmpxchg_4_asm(ptr, new, old);
- break;
- }
-
- return tmp;
-}
-#define cmpxchg(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-
-#else /* !CONFIG_SMP */
-
-#include <mach/blackfin.h>
-#include <asm/irqflags.h>
-
-struct __xchg_dummy {
- unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp = 0;
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- switch (size) {
- case 1:
- __asm__ __volatile__
- ("%0 = b%2 (z);\n\t"
- "b%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 2:
- __asm__ __volatile__
- ("%0 = w%2 (z);\n\t"
- "w%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 4:
- __asm__ __volatile__
- ("%0 = %2;\n\t"
- "%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- }
- hard_local_irq_restore(flags);
- return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n))
-#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
-
-#endif /* !CONFIG_SMP */
-
-#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
-
-#endif /* __ARCH_BLACKFIN_CMPXCHG__ */
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
deleted file mode 100644
index 507e7aa6a561..000000000000
--- a/arch/blackfin/include/asm/context.S
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
-
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r0 = 0x3f;
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
-#endif
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_syscall
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_no_interrupts
- [--sp] = SYSCFG;
- [--sp] = P0; /* orig_p0 */
- [--sp] = R0; /* orig_r0 */
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
-#ifdef CONFIG_KGDB
- fp = 0(Z);
- r1 = sp;
- r1 += 60;
- r1 += 60;
- r1 += 60;
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip reserved */
-#endif
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
-#ifdef CONFIG_DEBUG_KERNEL
- p1.l = lo(IPEND);
- p1.h = hi(IPEND);
- r1 = [p1];
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip IPEND as well. */
-#endif
- [--sp] = r0; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro restore_context_no_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- r0 = [sp++];
- RETI = r0; /* Restore RETI indirectly when in exception */
- RETS = [sp++];
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- SYSCFG = [sp++];
-.endm
-
-.macro restore_context_with_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- RETI = [sp++];
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-
- RETS = [sp++];
-
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.h = _bfin_irq_flags;
- p0.l = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- csync;
- SYSCFG = [sp++];
- csync;
-.endm
-
-.macro save_context_cplb
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
-
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = RETS;
-.endm
-
-.macro restore_context_cplb
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
-
- fp = [sp++];
-
- (R7:0, P5:0) = [SP++];
-.endm
-
-.macro pseudo_long_call func:req, scratch:req
-#ifdef CONFIG_ROMKERNEL
- \scratch\().l = \func;
- \scratch\().h = \func;
- call (\scratch);
-#else
- call \func;
-#endif
-.endm
-
-#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
-# define EX_SCRATCH_REG RETN
-#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
-# define EX_SCRATCH_REG RETE
-#else
-# define EX_SCRATCH_REG CYCLES
-#endif
-
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
deleted file mode 100644
index 5c37f620c4b3..000000000000
--- a/arch/blackfin/include/asm/cplb.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <mach/anomaly.h>
-
-#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-#define ANOMALY_05000158_WORKAROUND 0x200
-#else
-#define ANOMALY_05000158_WORKAROUND 0x0
-#endif
-
-#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
-#else
-#define SDRAM_DGENERIC (CPLB_COMMON)
-#endif
-
-#define SDRAM_DNON_CHBL (CPLB_COMMON)
-#define SDRAM_EBIU (CPLB_COMMON)
-#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-
-#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
-
-#ifdef CONFIG_SMP
-#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
-#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
-
-#else
-#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
-# if defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# else
-# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# endif
-
-# if defined(CONFIG_BFIN_L2_WRITEBACK)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
-# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
-# else
-# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-# endif
-#endif /* CONFIG_SMP */
-
-#define SIZE_1K 0x00000400 /* 1K */
-#define SIZE_4K 0x00001000 /* 4K */
-#define SIZE_1M 0x00100000 /* 1M */
-#define SIZE_4M 0x00400000 /* 4M */
-#define SIZE_16K 0x00004000 /* 16K */
-#define SIZE_64K 0x00010000 /* 64K */
-#define SIZE_16M 0x01000000 /* 16M */
-#define SIZE_64M 0x04000000 /* 64M */
-
-#define MAX_CPLBS 16
-
-#define CPLB_ENABLE_ICACHE_P 0
-#define CPLB_ENABLE_DCACHE_P 1
-#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P 4
-#define CPLB_ENABLE_DCPLBS_P 5
-
-#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
- CPLB_ENABLE_ICPLBS | \
- CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED 0x0000
-#define CPLB_NO_UNLOCKED 0x0001
-#define CPLB_NO_ADDR_MATCH 0x0002
-#define CPLB_PROT_VIOL 0x0003
-#define CPLB_UNKNOWN_ERR 0x0004
-
-#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
-
-#define FAULT_RW (1 << 16)
-#define FAULT_USERSUPV (1 << 17)
-#define FAULT_CPLBBITS 0x0000ffff
-
-#ifndef __ASSEMBLY__
-
-static inline void _disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
-#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
-
-static inline void _enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
-#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
deleted file mode 100644
index f315c83a015d..000000000000
--- a/arch/blackfin/include/asm/cplbinit.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Common CPLB definitions for CPLB init
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_CPLBINIT_H__
-#define __ASM_CPLBINIT_H__
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <linux/threads.h>
-
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-# define PDT_ATTR __attribute__((l1_data))
-#else
-# define PDT_ATTR
-#endif
-
-struct cplb_entry {
- unsigned long data, addr;
-};
-
-struct cplb_boundary {
- unsigned long eaddr; /* End of this region. */
- unsigned long data; /* CPLB data value. */
-};
-
-extern struct cplb_boundary dcplb_bounds[];
-extern struct cplb_boundary icplb_bounds[];
-extern int dcplb_nr_bounds, icplb_nr_bounds;
-
-extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
-extern int nr_dcplb_prot[], nr_cplb_flush[];
-
-#ifdef CONFIG_MPU
-
-extern int first_mask_dcplb;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask[NR_CPUS];
-
-extern void flush_switched_cplbs(unsigned int);
-extern void set_mask_dcplbs(unsigned long *, unsigned int);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* CONFIG_MPU */
-
-extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
-extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-extern void generate_cplb_tables_all(void);
-extern void generate_cplb_tables_cpu(unsigned int cpu);
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
deleted file mode 100644
index e349631c8299..000000000000
--- a/arch/blackfin/include/asm/cpu.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPU_H
-#define __ASM_BLACKFIN_CPU_H
-
-#include <linux/percpu.h>
-
-struct blackfin_cpudata {
- struct cpu cpu;
- unsigned int imemctl;
- unsigned int dmemctl;
-#ifdef CONFIG_SMP
- struct task_struct *idle;
-#endif
-};
-
-DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-#endif
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
deleted file mode 100644
index c5c8d8a3a5fa..000000000000
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/*
- * Blackfin core register bit & address definitions
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#include <mach/anomaly.h>
-
-#define MK_BMSK_(x) (1<<x)
-#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
-#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
- u32 __v; \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "%0 = " #asm_size "[%1]" #asm_ext ";" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- #asm_size "[%0] = %1;" \
- : \
- : "a" (addr), "d" ((u##size)(val)) \
- : "memory" \
- )
-
-#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32, , )
-#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
-
-#define bfin_read(addr) \
-({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
- switch (sizeof(*(addr))) { \
- case 1: bfin_write8(addr, val); break; \
- case 2: bfin_write16(addr, val); break; \
- case 4: bfin_write32(addr, val); break; \
- default: BUG(); \
- } \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#endif /* __ASSEMBLY__ */
-
-/**************************************************
- * System Register Bits
- **************************************************/
-
-/**************************************************
- * ASTAT register
- **************************************************/
-
-/* definitions of ASTAT bit positions*/
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ_P 0x00000000
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN_P 0x00000001
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC_P 0x00000005
-/*Quotient Bit*/
-#define ASTAT_AQ_P 0x00000006
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD_P 0x00000008
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_P 0x0000000C
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY_P 0x00000002
-/*Result of last ALU1 operation generated a carry*/
-#define ASTAT_AC1_P 0x0000000D
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0_P 0x00000010
-/*Sticky version of ASTAT_AV0 */
-#define ASTAT_AV0S_P 0x00000011
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1_P 0x00000012
-/*Sticky version of ASTAT_AV1 */
-#define ASTAT_AV1S_P 0x00000013
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_P 0x00000018
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_COPY_P 0x00000003
-/*Sticky version of ASTAT_V*/
-#define ASTAT_VS_P 0x00000019
-
-/* Masks */
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
-/*Quotient Bit*/
-#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
-/*Overflow Bit*/
-#define ASTAT_V MK_BMSK_(ASTAT_V_P)
-/*Overflow Bit*/
-#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
-
-/**************************************************
- * SEQSTAT register
- **************************************************/
-
-/* Bit Positions */
-#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
- * set by IDLE instruction.
- */
-#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
- * reset was a software reset
- * (=1)
- */
-#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
-/* Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
- 0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
- 0)
-
-/* Translate bits to something useful */
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE_SHIFT (14)
-#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
-
-/**************************************************
- * SYSCFG register
- **************************************************/
-
-/* Bit Positions */
-#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
- * set it forces an exception
- * for each instruction executed
- */
-#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
-
-/* Masks */
-
-/* Supervisor single step, when set it forces an exception for each
- *instruction executed
- */
-#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
-/* Enable cycle counter (=1) */
-#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
-/* Self Nesting Interrupt Enable */
-#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
-#define SYSCFG_CCCEN SYSCFG_CCEN
-
-/****************************************************
- * Core MMR Register Map
- ****************************************************/
-
-/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
-
-#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
- * Buffer Status
- */
-#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
- * Buffer Fault Address
- */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
- * Buffer 0
- */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
- * Buffer 1
- */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
- * Buffer 2
- */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
- * Lookaside Buffer 3
- */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
- * Lookaside Buffer 4
- */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
- * Lookaside Buffer 5
- */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
- * Lookaside Buffer 6
- */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
- * Lookaside Buffer 7
- */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
- * Lookaside Buffer 8
- */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
- * Lookaside Buffer 9
- */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
- * Lookaside Buffer 10
- */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
- * Lookaside Buffer 11
- */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
- * Lookaside Buffer 12
- */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
- * Lookaside Buffer 13
- */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
- * Lookaside Buffer 14
- */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
- * Lookaside Buffer 15
- */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
-
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
- * Protection Lookaside Buffer 0
- */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
- * Protection Lookaside Buffer 1
- */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
- * Protection Lookaside Buffer 2
- */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
- * Protection Lookaside Buffer 3
- */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
- * Protection Lookaside Buffer 4
- */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
- * Protection Lookaside Buffer 5
- */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
- * Protection Lookaside Buffer 6
- */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
- * Protection Lookaside Buffer 7
- */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
- * Protection Lookaside Buffer 8
- */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
- * Protection Lookaside Buffer 9
- */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
- * Protection Lookaside Buffer 10
- */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
- * Protection Lookaside Buffer 11
- */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
- * Protection Lookaside Buffer 12
- */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
- * Protection Lookaside Buffer 13
- */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
- * Protection Lookaside Buffer 14
- */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
- * Protection Lookaside Buffer 15
- */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
-
-/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
-#define DSPID 0xFFE05000 /* DSP Processor ID Register for
- * MP implementations
- */
-
-#define DBGSTAT 0xFFE05008 /* Debug Status Register */
-
-/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-/* Watchpoint Instruction Address Control Register */
-#define WPIACTL 0xFFE07000
-/* Watchpoint Instruction Address Register 0 */
-#define WPIA0 0xFFE07040
-/* Watchpoint Instruction Address Register 1 */
-#define WPIA1 0xFFE07044
-/* Watchpoint Instruction Address Register 2 */
-#define WPIA2 0xFFE07048
-/* Watchpoint Instruction Address Register 3 */
-#define WPIA3 0xFFE0704C
-/* Watchpoint Instruction Address Register 4 */
-#define WPIA4 0xFFE07050
-/* Watchpoint Instruction Address Register 5 */
-#define WPIA5 0xFFE07054
-/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT0 0xFFE07080
-/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT1 0xFFE07084
-/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT2 0xFFE07088
-/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT3 0xFFE0708C
-/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT4 0xFFE07090
-/* Watchpoint Instruction Address Count Register 5 */
-#define WPIACNT5 0xFFE07094
-/* Watchpoint Data Address Control Register */
-#define WPDACTL 0xFFE07100
-/* Watchpoint Data Address Register 0 */
-#define WPDA0 0xFFE07140
-/* Watchpoint Data Address Register 1 */
-#define WPDA1 0xFFE07144
-/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT0 0xFFE07180
-/* Watchpoint Data Address Count Value Register 1 */
-#define WPDACNT1 0xFFE07184
-/* Watchpoint Status Register */
-#define WPSTAT 0xFFE07200
-
-/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
-
-/* Performance Monitor Control Register */
-#define PFCTL 0xFFE08000
-/* Performance Monitor Counter Register 0 */
-#define PFCNTR0 0xFFE08100
-/* Performance Monitor Counter Register 1 */
-#define PFCNTR1 0xFFE08104
-
-/****************************************************
- * Core MMR Register Bits
- ****************************************************/
-
-/**************************************************
- * EVT registers (ILAT, IMASK, and IPEND).
- **************************************************/
-
-/* Bit Positions */
-#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
-#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
-#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
-#define EVT_EVX_P 0x00000003 /* Exception bit position */
-#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
-#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
-#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
-#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
-#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
-#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
-#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
-#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
-#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
-#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
-#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
-
-/* Masks */
-#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
-#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
-#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
-#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
-#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
-#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
-#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
-#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/**************************************************
- * DMEM_CONTROL Register
- **************************************************/
-/* Bit Positions */
-#define ENDM_P 0x00 /* (doesn't really exist) Enable
- *Data Memory L1
- */
-#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
-
-#define ENDCPLB_P 0x01 /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
-#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
-#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
-#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
-#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
-#define RDCHK 0x9 /* Enable L1 Parity Check */
-
-/* Masks */
-#define ENDM 0x00000001 /* (doesn't really exist) Enable
- * Data Memory L1
- */
-#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
-#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
-#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
-#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
-#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* Bit Positions */
-#define ENIM_P 0x00 /* Enable L1 Code Memory */
-#define IMCTL_ENIM_P 0x00 /* "" (older define) */
-#define ENICPLB_P 0x01 /* Enable ICPLB */
-#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
-#define IMC_P 0x02 /* Enable */
-#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0_P 0x03 /* Lock Way 0 */
-#define ILOC1_P 0x04 /* Lock Way 1 */
-#define ILOC2_P 0x05 /* Lock Way 2 */
-#define ILOC3_P 0x06 /* Lock Way 3 */
-#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
- * Priority
- */
-/* Masks */
-#define ENIM 0x00000001 /* Enable L1 Code Memory */
-#define ENICPLB 0x00000002 /* Enable ICPLB */
-#define IMC 0x00000004 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0 0x00000008 /* Lock Way 0 */
-#define ILOC1 0x00000010 /* Lock Way 1 */
-#define ILOC2 0x00000020 /* Lock Way 2 */
-#define ILOC3 0x00000040 /* Lock Way 3 */
-#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
- * Priority
- */
-
-/* TCNTL Masks */
-#define TMPWR 0x00000001 /* Timer Low Power Control,
- * 0=low power mode, 1=active state
- */
-#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD 0x00000004 /* Timer auto reload */
-#define TINT 0x00000008 /* Timer generated interrupt 0=no
- * interrupt has been generated,
- * 1=interrupt has been generated
- * (sticky)
- */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-/* Masks */
-#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-
-#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
-#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
-#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
-#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#ifdef CONFIG_BF60x
-#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
-#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
-#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
-#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
-#endif
-#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
- * mapped to L1
- */
-#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
- * priority port
- */
-#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
- * in L1
- */
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
- * 1=priority for non-replacement
- */
-/* DCPLB_DATA only */
-#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
- * access allowed (user mode)
- */
-#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
- * access allowed (supervisor mode)
- */
-#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
- * write-through writes,
- * 1= allocate cache lines on
- * write-through writes.
- */
-#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-/* TBUFCTL Masks */
-#define TBUFPWR 0x0001
-#define TBUFEN 0x0002
-#define TBUFOVF 0x0004
-#define TBUFCMPLP_SINGLE 0x0008
-#define TBUFCMPLP_DOUBLE 0x0010
-#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
-
-/* TBUFSTAT Masks */
-#define TBUFCNT 0x001F
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* Masks */
-#define TEST_READ 0x00000000 /* Read Access */
-#define TEST_WRITE 0x00000002 /* Write Access */
-#define TEST_TAG 0x00000000 /* Access TAG */
-#define TEST_DATA 0x00000004 /* Access DATA */
-#define TEST_DW0 0x00000000 /* Select Double Word 0 */
-#define TEST_DW1 0x00000008 /* Select Double Word 1 */
-#define TEST_DW2 0x00000010 /* Select Double Word 2 */
-#define TEST_DW3 0x00000018 /* Select Double Word 3 */
-#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
-#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
-#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
-#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
-#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
-#define TEST_WAY0 0x00000000 /* Access Way0 */
-#define TEST_WAY1 0x04000000 /* Access Way1 */
-/* ITEST_COMMAND only */
-#define TEST_WAY2 0x08000000 /* Access Way2 */
-#define TEST_WAY3 0x0C000000 /* Access Way3 */
-/* DTEST_COMMAND only */
-#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
-#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
-
-#endif /* _DEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
deleted file mode 100644
index 171d8deb04a5..000000000000
--- a/arch/blackfin/include/asm/delay.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * delay.h - delay functions
- *
- * Copyright (c) 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_DELAY_H__
-#define __ASM_DELAY_H__
-
-#include <mach/anomaly.h>
-
-static inline void __delay(unsigned long loops)
-{
-__asm__ __volatile__ (
- "LSETUP(1f, 1f) LC0 = %0;"
- "1: NOP;"
- :
- : "a" (loops)
- : "LT0", "LB0", "LC0"
- );
-}
-
-#include <linux/param.h> /* needed for HZ */
-
-/*
- * close approximation borrowed from m68knommu to avoid 64-bit math
- */
-
-#define HZSCALE (268435456 / (1000000/HZ))
-
-static inline unsigned long __to_delay(unsigned long scale)
-{
- extern unsigned long loops_per_jiffy;
- return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6;
-}
-
-static inline void udelay(unsigned long usecs)
-{
- __delay(__to_delay(usecs));
-}
-
-static inline void ndelay(unsigned long nsecs)
-{
- __delay(__to_delay(1) * nsecs / 1000);
-}
-
-#define ndelay ndelay
-
-#endif
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
deleted file mode 100644
index 04254ac36bed..000000000000
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_MAPPING_H
-#define _BLACKFIN_DMA_MAPPING_H
-
-#include <asm/cacheflush.h>
-
-extern void
-__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
-static inline void
-__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- switch (dir) {
- case DMA_NONE:
- BUG();
- case DMA_TO_DEVICE: /* writeback only */
- flush_dcache_range(addr, addr + size);
- break;
- case DMA_FROM_DEVICE: /* invalidate only */
- case DMA_BIDIRECTIONAL: /* flush and invalidate */
- /* Blackfin has no dedicated invalidate (it includes a flush) */
- invalidate_dcache_range(addr, addr + size);
- break;
- }
-}
-static inline void
-_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- if (__builtin_constant_p(dir))
- __dma_sync_inline(addr, size, dir);
- else
- __dma_sync(addr, size, dir);
-}
-
-extern const struct dma_map_ops bfin_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &bfin_dma_ops;
-}
-
-#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
deleted file mode 100644
index 40e9c2bbc6e3..000000000000
--- a/arch/blackfin/include/asm/dma.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/interrupt.h>
-#include <mach/dma.h>
-#include <linux/atomic.h>
-#include <asm/blackfin.h>
-#include <asm/page.h>
-#include <asm-generic/dma.h>
-#include <asm/bfin_dma.h>
-
-/*-------------------------
- * config reg bits value
- *-------------------------*/
-#define DATA_SIZE_8 0
-#define DATA_SIZE_16 1
-#define DATA_SIZE_32 2
-#ifdef CONFIG_BF60x
-#define DATA_SIZE_64 3
-#endif
-
-#define DMA_FLOW_STOP 0
-#define DMA_FLOW_AUTO 1
-#ifdef CONFIG_BF60x
-#define DMA_FLOW_LIST 4
-#define DMA_FLOW_ARRAY 5
-#define DMA_FLOW_LIST_DEMAND 6
-#define DMA_FLOW_ARRAY_DEMAND 7
-#else
-#define DMA_FLOW_ARRAY 4
-#define DMA_FLOW_SMALL 6
-#define DMA_FLOW_LARGE 7
-#endif
-
-#define DIMENSION_LINEAR 0
-#define DIMENSION_2D 1
-
-#define DIR_READ 0
-#define DIR_WRITE 1
-
-#define INTR_DISABLE 0
-#ifdef CONFIG_BF60x
-#define INTR_ON_PERI 1
-#endif
-#define INTR_ON_BUF 2
-#define INTR_ON_ROW 3
-
-#define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART 1
-
-#ifdef DMA_MMR_SIZE_32
-#define DMA_MMR_SIZE_TYPE long
-#define DMA_MMR_READ bfin_read32
-#define DMA_MMR_WRITE bfin_write32
-#else
-#define DMA_MMR_SIZE_TYPE short
-#define DMA_MMR_READ bfin_read16
-#define DMA_MMR_WRITE bfin_write16
-#endif
-
-struct dma_desc_array {
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
-} __attribute__((packed));
-
-struct dmasg {
- void *next_desc_addr;
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
- unsigned DMA_MMR_SIZE_TYPE y_count;
- DMA_MMR_SIZE_TYPE y_modify;
-} __attribute__((packed));
-
-struct dma_register {
- void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- unsigned long start_addr; /* DMA Start address register */
-#ifdef CONFIG_BF60x
- unsigned long cfg; /* DMA Configuration register */
-
- unsigned long x_count; /* DMA x_count register */
-
- long x_modify; /* DMA x_modify register */
-
- unsigned long y_count; /* DMA y_count register */
-
- long y_modify; /* DMA y_modify register */
-
- unsigned long reserved;
- unsigned long reserved2;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned long irq_status; /* DMA irq status register */
-
- unsigned long curr_x_count; /* DMA Current x-count register */
-
- unsigned long curr_y_count; /* DMA Current y-count register */
-
- unsigned long reserved3;
-
- unsigned long bw_limit_count; /* DMA band width limit count register */
- unsigned long curr_bw_limit_count; /* DMA Current band width limit
- count register */
- unsigned long bw_monitor_count; /* DMA band width limit count register */
- unsigned long curr_bw_monitor_count; /* DMA Current band width limit
- count register */
-#else
- unsigned short cfg; /* DMA Configuration register */
- unsigned short dummy1; /* DMA Configuration register */
-
- unsigned long reserved;
-
- unsigned short x_count; /* DMA x_count register */
- unsigned short dummy2;
-
- short x_modify; /* DMA x_modify register */
- unsigned short dummy3;
-
- unsigned short y_count; /* DMA y_count register */
- unsigned short dummy4;
-
- short y_modify; /* DMA y_modify register */
- unsigned short dummy5;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned short irq_status; /* DMA irq status register */
- unsigned short dummy6;
-
- unsigned short peripheral_map; /* DMA peripheral map register */
- unsigned short dummy7;
-
- unsigned short curr_x_count; /* DMA Current x-count register */
- unsigned short dummy8;
-
- unsigned long reserved2;
-
- unsigned short curr_y_count; /* DMA Current y-count register */
- unsigned short dummy9;
-
- unsigned long reserved3;
-#endif
-
-};
-
-struct dma_channel {
- const char *device_id;
- atomic_t chan_status;
- volatile struct dma_register *regs;
- struct dmasg *sg; /* large mode descriptor */
- unsigned int irq;
- void *data;
-#ifdef CONFIG_PM
- unsigned short saved_peripheral_map;
-#endif
-};
-
-#ifdef CONFIG_PM
-int blackfin_dma_suspend(void);
-void blackfin_dma_resume(void);
-#endif
-
-/*******************************************************************************
-* DMA API's
-*******************************************************************************/
-extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
-extern int channel2irq(unsigned int channel);
-
-static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->start_addr = addr;
-}
-static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->next_desc_ptr = addr;
-}
-static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->curr_desc_ptr = addr;
-}
-static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
-{
- dma_ch[channel].regs->x_count = x_count;
-}
-static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
-{
- dma_ch[channel].regs->y_count = y_count;
-}
-static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
-{
- dma_ch[channel].regs->x_modify = x_modify;
-}
-static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
-{
- dma_ch[channel].regs->y_modify = y_modify;
-}
-static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
-{
- dma_ch[channel].regs->cfg = config;
-}
-static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->curr_addr_ptr = addr;
-}
-
-#ifdef CONFIG_BF60x
-static inline unsigned long
-set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
- char dma_mode, char mem_width, char syncmode, char peri_width)
-{
- unsigned long config = 0;
-
- switch (intr_mode) {
- case INTR_ON_BUF:
- if (dma_mode == DIMENSION_2D)
- config = DI_EN_Y;
- else
- config = DI_EN_X;
- break;
- case INTR_ON_ROW:
- config = DI_EN_X;
- break;
- case INTR_ON_PERI:
- config = DI_EN_P;
- break;
- };
-
- return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
- (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
-}
-#endif
-
-static inline unsigned DMA_MMR_SIZE_TYPE
-set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char mem_width, char syncmode)
-{
-#ifdef CONFIG_BF60x
- return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
- mem_width, syncmode, mem_width);
-#else
- return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
- (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
-#endif
-}
-
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
-{
- return dma_ch[channel].regs->irq_status;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_x_count;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_y_count;
-}
-static inline void *get_dma_next_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->next_desc_ptr;
-}
-static inline void *get_dma_curr_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_desc_ptr;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
-{
- return dma_ch[channel].regs->cfg;
-}
-static inline unsigned long get_dma_curr_addr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_addr_ptr;
-}
-
-static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
-{
- /* Make sure the internal data buffers in the core are drained
- * so that the DMA descriptors are completely written when the
- * DMA engine goes to fetch them below.
- */
- SSYNC();
-
- dma_ch[channel].regs->next_desc_ptr = sg;
- dma_ch[channel].regs->cfg =
- (dma_ch[channel].regs->cfg & ~NDSIZE) |
- ((ndsize << NDSIZE_OFFSET) & NDSIZE);
-}
-
-static inline int dma_channel_active(unsigned int channel)
-{
- return atomic_read(&dma_ch[channel].chan_status);
-}
-
-static inline void disable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->cfg &= ~DMAEN;
- SSYNC();
-}
-static inline void enable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->curr_x_count = 0;
- dma_ch[channel].regs->curr_y_count = 0;
- dma_ch[channel].regs->cfg |= DMAEN;
-}
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
-
-static inline void dma_disable_irq(unsigned int channel)
-{
- disable_irq(dma_ch[channel].irq);
-}
-static inline void dma_disable_irq_nosync(unsigned int channel)
-{
- disable_irq_nosync(dma_ch[channel].irq);
-}
-static inline void dma_enable_irq(unsigned int channel)
-{
- enable_irq(dma_ch[channel].irq);
-}
-static inline void clear_dma_irqstat(unsigned int channel)
-{
- dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
-}
-
-void *dma_memcpy(void *dest, const void *src, size_t count);
-void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
-void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-void blackfin_dma_early_init(void);
-void early_dma_memcpy(void *dest, const void *src, size_t count);
-void early_dma_memcpy_done(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
deleted file mode 100644
index 2673b11376f4..000000000000
--- a/arch/blackfin/include/asm/dpmc.h
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
- *
- * Copyright (C) 2004-2009 Analog Device Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BLACKFIN_DPMC_H_
-#define _BLACKFIN_DPMC_H_
-
-#ifdef __ASSEMBLY__
-#define PM_REG0 R7
-#define PM_REG1 R6
-#define PM_REG2 R5
-#define PM_REG3 R4
-#define PM_REG4 R3
-#define PM_REG5 R2
-#define PM_REG6 R1
-#define PM_REG7 R0
-#define PM_REG8 P5
-#define PM_REG9 P4
-#define PM_REG10 P3
-#define PM_REG11 P2
-#define PM_REG12 P1
-#define PM_REG13 P0
-
-#define PM_REGSET0 R7:7
-#define PM_REGSET1 R7:6
-#define PM_REGSET2 R7:5
-#define PM_REGSET3 R7:4
-#define PM_REGSET4 R7:3
-#define PM_REGSET5 R7:2
-#define PM_REGSET6 R7:1
-#define PM_REGSET7 R7:0
-#define PM_REGSET8 R7:0, P5:5
-#define PM_REGSET9 R7:0, P5:4
-#define PM_REGSET10 R7:0, P5:3
-#define PM_REGSET11 R7:0, P5:2
-#define PM_REGSET12 R7:0, P5:1
-#define PM_REGSET13 R7:0, P5:0
-
-#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
-#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
-#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
-#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
-#define PM_PUSH(n, x) PM_REG##n = [FP++];
-#define PM_POP(n, x) [FP--] = PM_REG##n;
-#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
-#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
-#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
-#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
-#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
-#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
-
- .macro bfin_init_pm_bench_cycles
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- R4 = 0;
- CYCLES = R4;
- CYCLES2 = R4;
- R4 = SYSCFG;
- BITSET(R4, 1);
- SYSCFG = R4;
-#endif
- .endm
-
- .macro bfin_cpu_reg_save
- /*
- * Save the core regs early so we can blow them away when
- * saving/restoring MMR states
- */
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- /* We can't push RETI directly as that'll change IPEND[4] */
- r7 = RETI;
- [--sp] = RETS;
- [--sp] = ASTAT;
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- [--sp] = CYCLES;
- [--sp] = CYCLES2;
-#endif
- [--sp] = SYSCFG;
- [--sp] = RETX;
- [--sp] = SEQSTAT;
- [--sp] = r7;
-
- /* Save first func arg in M3 */
- M3 = R0;
- .endm
-
- .macro bfin_cpu_reg_restore
- /* Restore Core Registers */
- RETI = [sp++];
- SEQSTAT = [sp++];
- RETX = [sp++];
- SYSCFG = [sp++];
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- CYCLES2 = [sp++];
- CYCLES = [sp++];
-#endif
- ASTAT = [sp++];
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- usp = [sp++];
- fp = [sp++];
- (R7:0, P5:0) = [sp++];
-
- .endm
-
- .macro bfin_sys_mmr_save
- /* Save system MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-#ifdef SIC_IMASK0
- PM_SYS_PUSH(0, SIC_IMASK0)
- PM_SYS_PUSH(1, SIC_IMASK1)
-# ifdef SIC_IMASK2
- PM_SYS_PUSH(2, SIC_IMASK2)
-# endif
-#else
-# ifdef SIC_IMASK
- PM_SYS_PUSH(0, SIC_IMASK)
-# endif
-#endif
-
-#ifdef SIC_IAR0
- PM_SYS_PUSH(3, SIC_IAR0)
- PM_SYS_PUSH(4, SIC_IAR1)
- PM_SYS_PUSH(5, SIC_IAR2)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_PUSH(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR4
- PM_SYS_PUSH(7, SIC_IAR4)
- PM_SYS_PUSH(8, SIC_IAR5)
- PM_SYS_PUSH(9, SIC_IAR6)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_PUSH(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR8
- PM_SYS_PUSH(11, SIC_IAR8)
- PM_SYS_PUSH(12, SIC_IAR9)
- PM_SYS_PUSH(13, SIC_IAR10)
-#endif
- PM_PUSH_SYNC(13)
-#ifdef SIC_IAR11
- PM_SYS_PUSH(0, SIC_IAR11)
-#endif
-
-#ifdef SIC_IWR
- PM_SYS_PUSH(1, SIC_IWR)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_PUSH(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_PUSH(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
- PM_SYS_PUSH(3, SIC_IWR2)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_PUSH(4, PINT0_MASK_SET)
- PM_SYS_PUSH(5, PINT1_MASK_SET)
- PM_SYS_PUSH(6, PINT2_MASK_SET)
- PM_SYS_PUSH(7, PINT3_MASK_SET)
- PM_SYS_PUSH(8, PINT0_ASSIGN)
- PM_SYS_PUSH(9, PINT1_ASSIGN)
- PM_SYS_PUSH(10, PINT2_ASSIGN)
- PM_SYS_PUSH(11, PINT3_ASSIGN)
- PM_SYS_PUSH(12, PINT0_INVERT_SET)
- PM_SYS_PUSH(13, PINT1_INVERT_SET)
- PM_PUSH_SYNC(13)
- PM_SYS_PUSH(0, PINT2_INVERT_SET)
- PM_SYS_PUSH(1, PINT3_INVERT_SET)
- PM_SYS_PUSH(2, PINT0_EDGE_SET)
- PM_SYS_PUSH(3, PINT1_EDGE_SET)
- PM_SYS_PUSH(4, PINT2_EDGE_SET)
- PM_SYS_PUSH(5, PINT3_EDGE_SET)
-#endif
-
-#ifdef SYSCR
- PM_SYS_PUSH16(6, SYSCR)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_PUSH16(7, EBIU_AMGCTL)
- PM_SYS_PUSH(8, EBIU_AMBCTL0)
- PM_SYS_PUSH(9, EBIU_AMBCTL1)
-#endif
-#ifdef EBIU_FCTL
- PM_SYS_PUSH(10, EBIU_MBSCTL)
- PM_SYS_PUSH(11, EBIU_MODE)
- PM_SYS_PUSH(12, EBIU_FCTL)
- PM_PUSH_SYNC(12)
-#else
- PM_PUSH_SYNC(9)
-#endif
- .endm
-
-
- .macro bfin_sys_mmr_restore
-/* Restore System MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-
-#ifdef EBIU_FCTL
- PM_POP_SYNC(12)
- PM_SYS_POP(12, EBIU_FCTL)
- PM_SYS_POP(11, EBIU_MODE)
- PM_SYS_POP(10, EBIU_MBSCTL)
-#else
- PM_POP_SYNC(9)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_POP(9, EBIU_AMBCTL1)
- PM_SYS_POP(8, EBIU_AMBCTL0)
- PM_SYS_POP16(7, EBIU_AMGCTL)
-#endif
-
-#ifdef SYSCR
- PM_SYS_POP16(6, SYSCR)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_POP(5, PINT3_EDGE_SET)
- PM_SYS_POP(4, PINT2_EDGE_SET)
- PM_SYS_POP(3, PINT1_EDGE_SET)
- PM_SYS_POP(2, PINT0_EDGE_SET)
- PM_SYS_POP(1, PINT3_INVERT_SET)
- PM_SYS_POP(0, PINT2_INVERT_SET)
- PM_POP_SYNC(13)
- PM_SYS_POP(13, PINT1_INVERT_SET)
- PM_SYS_POP(12, PINT0_INVERT_SET)
- PM_SYS_POP(11, PINT3_ASSIGN)
- PM_SYS_POP(10, PINT2_ASSIGN)
- PM_SYS_POP(9, PINT1_ASSIGN)
- PM_SYS_POP(8, PINT0_ASSIGN)
- PM_SYS_POP(7, PINT3_MASK_SET)
- PM_SYS_POP(6, PINT2_MASK_SET)
- PM_SYS_POP(5, PINT1_MASK_SET)
- PM_SYS_POP(4, PINT0_MASK_SET)
-#endif
-
-#ifdef SIC_IWR2
- PM_SYS_POP(3, SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_POP(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_POP(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR
- PM_SYS_POP(1, SIC_IWR)
-#endif
-
-#ifdef SIC_IAR11
- PM_SYS_POP(0, SIC_IAR11)
-#endif
- PM_POP_SYNC(13)
-#ifdef SIC_IAR8
- PM_SYS_POP(13, SIC_IAR10)
- PM_SYS_POP(12, SIC_IAR9)
- PM_SYS_POP(11, SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_POP(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
- PM_SYS_POP(9, SIC_IAR6)
- PM_SYS_POP(8, SIC_IAR5)
- PM_SYS_POP(7, SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_POP(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
- PM_SYS_POP(5, SIC_IAR2)
- PM_SYS_POP(4, SIC_IAR1)
- PM_SYS_POP(3, SIC_IAR0)
-#endif
-#ifdef SIC_IMASK0
-# ifdef SIC_IMASK2
- PM_SYS_POP(2, SIC_IMASK2)
-# endif
- PM_SYS_POP(1, SIC_IMASK1)
- PM_SYS_POP(0, SIC_IMASK0)
-#else
-# ifdef SIC_IMASK
- PM_SYS_POP(0, SIC_IMASK)
-# endif
-#endif
- .endm
-
- .macro bfin_core_mmr_save
- /* Save Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR0);
- I2.L = lo(DCPLB_DATA0);
- I3.L = lo(ICPLB_ADDR0);
- B0.L = lo(ICPLB_DATA0);
- B1.L = lo(EVT2);
- B2.L = lo(IMASK);
- B3.L = lo(TCNTL);
-
- /* Event Vectors */
- FP = B1;
- PM_PUSH(0, EVT2)
- PM_PUSH(1, EVT3)
- FP += 4; /* EVT4 */
- PM_PUSH(2, EVT5)
- PM_PUSH(3, EVT6)
- PM_PUSH(4, EVT7)
- PM_PUSH(5, EVT8)
- PM_PUSH_SYNC(5)
-
- PM_PUSH(0, EVT9)
- PM_PUSH(1, EVT10)
- PM_PUSH(2, EVT11)
- PM_PUSH(3, EVT12)
- PM_PUSH(4, EVT13)
- PM_PUSH(5, EVT14)
- PM_PUSH(6, EVT15)
-
- /* CEC */
- FP = B2;
- PM_PUSH(7, IMASK)
- FP += 4; /* IPEND */
- PM_PUSH(8, ILAT)
- PM_PUSH(9, IPRIO)
-
- /* Core Timer */
- FP = B3;
- PM_PUSH(10, TCNTL)
- PM_PUSH(11, TPERIOD)
- PM_PUSH(12, TSCALE)
- PM_PUSH(13, TCOUNT)
- PM_PUSH_SYNC(13)
-
- /* Misc non-contiguous registers */
- FP = I0;
- PM_CORE_PUSH(0, DMEM_CONTROL);
- PM_CORE_PUSH(1, IMEM_CONTROL);
- PM_CORE_PUSH(2, TBUFCTL);
- PM_PUSH_SYNC(2)
-
- /* DCPLB Addr */
- FP = I1;
- PM_PUSH(0, DCPLB_ADDR0)
- PM_PUSH(1, DCPLB_ADDR1)
- PM_PUSH(2, DCPLB_ADDR2)
- PM_PUSH(3, DCPLB_ADDR3)
- PM_PUSH(4, DCPLB_ADDR4)
- PM_PUSH(5, DCPLB_ADDR5)
- PM_PUSH(6, DCPLB_ADDR6)
- PM_PUSH(7, DCPLB_ADDR7)
- PM_PUSH(8, DCPLB_ADDR8)
- PM_PUSH(9, DCPLB_ADDR9)
- PM_PUSH(10, DCPLB_ADDR10)
- PM_PUSH(11, DCPLB_ADDR11)
- PM_PUSH(12, DCPLB_ADDR12)
- PM_PUSH(13, DCPLB_ADDR13)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_ADDR14)
- PM_PUSH(1, DCPLB_ADDR15)
-
- /* DCPLB Data */
- FP = I2;
- PM_PUSH(2, DCPLB_DATA0)
- PM_PUSH(3, DCPLB_DATA1)
- PM_PUSH(4, DCPLB_DATA2)
- PM_PUSH(5, DCPLB_DATA3)
- PM_PUSH(6, DCPLB_DATA4)
- PM_PUSH(7, DCPLB_DATA5)
- PM_PUSH(8, DCPLB_DATA6)
- PM_PUSH(9, DCPLB_DATA7)
- PM_PUSH(10, DCPLB_DATA8)
- PM_PUSH(11, DCPLB_DATA9)
- PM_PUSH(12, DCPLB_DATA10)
- PM_PUSH(13, DCPLB_DATA11)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_DATA12)
- PM_PUSH(1, DCPLB_DATA13)
- PM_PUSH(2, DCPLB_DATA14)
- PM_PUSH(3, DCPLB_DATA15)
-
- /* ICPLB Addr */
- FP = I3;
- PM_PUSH(4, ICPLB_ADDR0)
- PM_PUSH(5, ICPLB_ADDR1)
- PM_PUSH(6, ICPLB_ADDR2)
- PM_PUSH(7, ICPLB_ADDR3)
- PM_PUSH(8, ICPLB_ADDR4)
- PM_PUSH(9, ICPLB_ADDR5)
- PM_PUSH(10, ICPLB_ADDR6)
- PM_PUSH(11, ICPLB_ADDR7)
- PM_PUSH(12, ICPLB_ADDR8)
- PM_PUSH(13, ICPLB_ADDR9)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_ADDR10)
- PM_PUSH(1, ICPLB_ADDR11)
- PM_PUSH(2, ICPLB_ADDR12)
- PM_PUSH(3, ICPLB_ADDR13)
- PM_PUSH(4, ICPLB_ADDR14)
- PM_PUSH(5, ICPLB_ADDR15)
-
- /* ICPLB Data */
- FP = B0;
- PM_PUSH(6, ICPLB_DATA0)
- PM_PUSH(7, ICPLB_DATA1)
- PM_PUSH(8, ICPLB_DATA2)
- PM_PUSH(9, ICPLB_DATA3)
- PM_PUSH(10, ICPLB_DATA4)
- PM_PUSH(11, ICPLB_DATA5)
- PM_PUSH(12, ICPLB_DATA6)
- PM_PUSH(13, ICPLB_DATA7)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_DATA8)
- PM_PUSH(1, ICPLB_DATA9)
- PM_PUSH(2, ICPLB_DATA10)
- PM_PUSH(3, ICPLB_DATA11)
- PM_PUSH(4, ICPLB_DATA12)
- PM_PUSH(5, ICPLB_DATA13)
- PM_PUSH(6, ICPLB_DATA14)
- PM_PUSH(7, ICPLB_DATA15)
- PM_PUSH_SYNC(7)
- .endm
-
- .macro bfin_core_mmr_restore
- /* Restore Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR15);
- I2.L = lo(DCPLB_DATA15);
- I3.L = lo(ICPLB_ADDR15);
- B0.L = lo(ICPLB_DATA15);
- B1.L = lo(EVT15);
- B2.L = lo(IPRIO);
- B3.L = lo(TCOUNT);
-
- /* ICPLB Data */
- FP = B0;
- PM_POP_SYNC(7)
- PM_POP(7, ICPLB_DATA15)
- PM_POP(6, ICPLB_DATA14)
- PM_POP(5, ICPLB_DATA13)
- PM_POP(4, ICPLB_DATA12)
- PM_POP(3, ICPLB_DATA11)
- PM_POP(2, ICPLB_DATA10)
- PM_POP(1, ICPLB_DATA9)
- PM_POP(0, ICPLB_DATA8)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_DATA7)
- PM_POP(12, ICPLB_DATA6)
- PM_POP(11, ICPLB_DATA5)
- PM_POP(10, ICPLB_DATA4)
- PM_POP(9, ICPLB_DATA3)
- PM_POP(8, ICPLB_DATA2)
- PM_POP(7, ICPLB_DATA1)
- PM_POP(6, ICPLB_DATA0)
-
- /* ICPLB Addr */
- FP = I3;
- PM_POP(5, ICPLB_ADDR15)
- PM_POP(4, ICPLB_ADDR14)
- PM_POP(3, ICPLB_ADDR13)
- PM_POP(2, ICPLB_ADDR12)
- PM_POP(1, ICPLB_ADDR11)
- PM_POP(0, ICPLB_ADDR10)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_ADDR9)
- PM_POP(12, ICPLB_ADDR8)
- PM_POP(11, ICPLB_ADDR7)
- PM_POP(10, ICPLB_ADDR6)
- PM_POP(9, ICPLB_ADDR5)
- PM_POP(8, ICPLB_ADDR4)
- PM_POP(7, ICPLB_ADDR3)
- PM_POP(6, ICPLB_ADDR2)
- PM_POP(5, ICPLB_ADDR1)
- PM_POP(4, ICPLB_ADDR0)
-
- /* DCPLB Data */
- FP = I2;
- PM_POP(3, DCPLB_DATA15)
- PM_POP(2, DCPLB_DATA14)
- PM_POP(1, DCPLB_DATA13)
- PM_POP(0, DCPLB_DATA12)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_DATA11)
- PM_POP(12, DCPLB_DATA10)
- PM_POP(11, DCPLB_DATA9)
- PM_POP(10, DCPLB_DATA8)
- PM_POP(9, DCPLB_DATA7)
- PM_POP(8, DCPLB_DATA6)
- PM_POP(7, DCPLB_DATA5)
- PM_POP(6, DCPLB_DATA4)
- PM_POP(5, DCPLB_DATA3)
- PM_POP(4, DCPLB_DATA2)
- PM_POP(3, DCPLB_DATA1)
- PM_POP(2, DCPLB_DATA0)
-
- /* DCPLB Addr */
- FP = I1;
- PM_POP(1, DCPLB_ADDR15)
- PM_POP(0, DCPLB_ADDR14)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_ADDR13)
- PM_POP(12, DCPLB_ADDR12)
- PM_POP(11, DCPLB_ADDR11)
- PM_POP(10, DCPLB_ADDR10)
- PM_POP(9, DCPLB_ADDR9)
- PM_POP(8, DCPLB_ADDR8)
- PM_POP(7, DCPLB_ADDR7)
- PM_POP(6, DCPLB_ADDR6)
- PM_POP(5, DCPLB_ADDR5)
- PM_POP(4, DCPLB_ADDR4)
- PM_POP(3, DCPLB_ADDR3)
- PM_POP(2, DCPLB_ADDR2)
- PM_POP(1, DCPLB_ADDR1)
- PM_POP(0, DCPLB_ADDR0)
-
-
- /* Misc non-contiguous registers */
-
- /* icache & dcache will enable later
- drop IMEM_CONTROL, DMEM_CONTROL pop
- */
- FP = I0;
- PM_POP_SYNC(2)
- PM_CORE_POP(2, TBUFCTL)
- PM_CORE_POP(1, IMEM_CONTROL)
- PM_CORE_POP(0, DMEM_CONTROL)
-
- /* Core Timer */
- FP = B3;
- R0 = 0x1;
- [FP - 0xC] = R0;
-
- PM_POP_SYNC(13)
- FP = B3;
- PM_POP(13, TCOUNT)
- PM_POP(12, TSCALE)
- PM_POP(11, TPERIOD)
- PM_POP(10, TCNTL)
-
- /* CEC */
- FP = B2;
- PM_POP(9, IPRIO)
- PM_POP(8, ILAT)
- FP += -4; /* IPEND */
- PM_POP(7, IMASK)
-
- /* Event Vectors */
- FP = B1;
- PM_POP(6, EVT15)
- PM_POP(5, EVT14)
- PM_POP(4, EVT13)
- PM_POP(3, EVT12)
- PM_POP(2, EVT11)
- PM_POP(1, EVT10)
- PM_POP(0, EVT9)
- PM_POP_SYNC(5)
- PM_POP(5, EVT8)
- PM_POP(4, EVT7)
- PM_POP(3, EVT6)
- PM_POP(2, EVT5)
- FP += -4; /* EVT4 */
- PM_POP(1, EVT3)
- PM_POP(0, EVT2)
- .endm
-#endif
-
-#include <mach/pll.h>
-
-/* PLL_CTL Masks */
-#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF 0x0002 /* PLL Not Powered */
-#define STOPCK 0x0008 /* Core Clock Off */
-#define PDWN 0x0020 /* Enter Deep Sleep Mode */
-#ifdef __ADSPBF539__
-# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
-#else
-# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS 0x0100 /* Bypass the PLL */
-#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
-#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-
-/* PLL_DIV Masks */
-#define SSEL 0x000F /* System Select */
-#define CSEL 0x0030 /* Core Select */
-#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
-#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
-#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
-#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
-
-#define CCLK_DIV1 CSEL_DIV1
-#define CCLK_DIV2 CSEL_DIV2
-#define CCLK_DIV4 CSEL_DIV4
-#define CCLK_DIV8 CSEL_DIV8
-
-#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
-
-/* PLL_STAT Masks */
-#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
-#define FULL_ON 0x0002 /* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
-#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
-
-#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
-#define CANWS 0x0800 /* CAN Wake-Up Status */
-#define USBWS 0x2000 /* USB Wake-Up Status */
-#define KPADWS 0x4000 /* Keypad Wake-Up Status */
-#define ROTWS 0x8000 /* Rotary Wake-Up Status */
-#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
-
-/* VR_CTL Masks */
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
-#else
-#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
-#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
-#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
-#endif
-#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
-
-#define GAIN 0x000C /* Voltage Level Gain */
-#define GAIN_5 0x0000 /* GAIN = 5 */
-#define GAIN_10 0x0004 /* GAIN = 1 */
-#define GAIN_20 0x0008 /* GAIN = 2 */
-#define GAIN_50 0x000C /* GAIN = 5 */
-
-#define VLEV 0x00F0 /* Internal Voltage Level */
-#ifdef __ADSPBF52x__
-#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#else
-#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-#endif
-
-#ifdef CONFIG_BF60x
-#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
-#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
-#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
-#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
-#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
-#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
-#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
-#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
-#else
-#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
-#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
-#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
-#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
-#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
-#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
-#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
-#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
-
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
-#else
-#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-
-void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void do_hibernate(int wakeup);
-void set_dram_srfs(void);
-void unset_dram_srfs(void);
-
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
-
-#ifdef CONFIG_CPU_FREQ
-#define CPUFREQ_CPU 0
-#endif
-struct bfin_dpmc_platform_data {
- const unsigned int *tuple_tab;
- unsigned short tabsize;
- unsigned short vr_settling_time; /* in us */
-};
-
-#endif
-
-#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h
deleted file mode 100644
index 68a910db8864..000000000000
--- a/arch/blackfin/include/asm/early_printk.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * function prototpyes for early printk
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_EARLY_PRINTK_H__
-#define __ASM_EARLY_PRINTK_H__
-
-#ifdef CONFIG_EARLY_PRINTK
-/* For those that don't include it already */
-#include <linux/console.h>
-
-extern int setup_early_printk(char *);
-extern void enable_shadow_console(void);
-extern int shadow_console_enabled(void);
-extern void mark_shadow_error(void);
-extern void early_shadow_reg(unsigned long reg, unsigned int n);
-extern void early_shadow_write(struct console *con, const char *s,
- unsigned int n) __attribute__((nonnull(2)));
-#define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str))
-#define early_shadow_stamp() \
- do { \
- early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \
- early_shadow_puts(__func__); \
- early_shadow_puts("]\n"); \
- } while (0)
-#else
-#define setup_early_printk(fmt) do { } while (0)
-#define enable_shadow_console(fmt) do { } while (0)
-#define early_shadow_stamp() do { } while (0)
-#endif /* CONFIG_EARLY_PRINTK */
-
-#endif /* __ASM_EARLY_PRINTK_H__ */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
deleted file mode 100644
index d15cb9b5d52c..000000000000
--- a/arch/blackfin/include/asm/elf.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field. */
-#define EF_BFIN_PIC 0x00000001 /* -fpic */
-#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
-#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
-#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
-#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
-
-#if 1 /* core dumps not supported, but linux/elfcore.h needs these */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct { } elf_fpregset_t;
-#endif
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r) _r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
-do { \
- _regs->r7 = 0; \
- _regs->p0 = _exec_map_addr; \
- _regs->p1 = _interp_map_addr; \
- _regs->p2 = _dynamic_addr; \
-} while(0)
-
-#if 0
-#define CORE_DUMP_USE_REGSET
-#endif
-#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE 4096
-
-#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */
-#define R_BFIN_PCREL5M2 1 /* LSETUP part a */
-#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */
-#define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */
-#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */
-#define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */
-#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */
-#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */
-#define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */
-#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */
-#define R_BFIN_UNUSEDC 12 /* # 0xc not used */
-#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */
-#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */
-#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */
-#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */
-#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */
-#define R_BFIN_UNUSED14 20 /* 0x14, undefined */
-#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_BFIN_PUSH 0xE0
-#define R_BFIN_CONST 0xE1
-#define R_BFIN_ADD 0xE2
-#define R_BFIN_SUB 0xE3
-#define R_BFIN_MULT 0xE4
-#define R_BFIN_DIV 0xE5
-#define R_BFIN_MOD 0xE6
-#define R_BFIN_LSHIFT 0xE7
-#define R_BFIN_RSHIFT 0xE8
-#define R_BFIN_AND 0xE9
-#define R_BFIN_OR 0xEA
-#define R_BFIN_XOR 0xEB
-#define R_BFIN_LAND 0xEC
-#define R_BFIN_LOR 0xED
-#define R_BFIN_LEN 0xEE
-#define R_BFIN_NEG 0xEF
-#define R_BFIN_COMP 0xF0
-#define R_BFIN_PAGE 0xF1
-#define R_BFIN_HWPAGE 0xF2
-#define R_BFIN_ADDR 0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- memcpy((char *) &pr_reg, (char *)regs, \
- sizeof(struct pt_regs));
-#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
deleted file mode 100644
index 4104d5783e2c..000000000000
--- a/arch/blackfin/include/asm/entry.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ENTRY_H
-#define __BFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-
-#define LFLUSH_I_AND_D 0x00000808
-#define LSIGTRAP 5
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/* This one is used for exceptions, emulation, and NMI. It doesn't push
- RETI and doesn't do cli. */
-#define SAVE_ALL_SYS save_context_no_interrupts
-/* This is used for all normal interrupts. It saves a minimum of registers
- to the stack, loads the IRQ number, and jumps to common code. */
-#ifdef CONFIG_IPIPE
-# define LOAD_IPIPE_IPEND \
- P0.l = lo(IPEND); \
- P0.h = hi(IPEND); \
- R1 = [P0];
-#else
-# define LOAD_IPIPE_IPEND
-#endif
-
-/*
- * Workaround for anomalies 05000283 and 05000315
- */
-#if ANOMALY_05000283 || ANOMALY_05000315
-# define ANOMALY_283_315_WORKAROUND(preg, dreg) \
- cc = dreg == dreg; \
- preg.h = HI(CHIPID); \
- preg.l = LO(CHIPID); \
- if cc jump 1f; \
- dreg.l = W[preg]; \
-1:
-#else
-# define ANOMALY_283_315_WORKAROUND(preg, dreg)
-#endif /* ANOMALY_05000283 || ANOMALY_05000315 */
-
-#ifndef CONFIG_EXACT_HWERR
-/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on,
- * otherwise it is a waste of cycles.
- */
-# ifndef CONFIG_DEBUG_KERNEL
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# else /* CONFIG_DEBUG_KERNEL */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# endif /* CONFIG_DEBUG_KERNEL */
-
-/* For timer interrupts, we need to save IPEND, since the user_mode
- *macro accesses it to determine where to account time.
- */
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry;
-#else /* CONFIG_EXACT_HWERR is defined */
-
-/* if we want hardware error to be exact, we need to do a SSYNC (which forces
- * read/writes to complete to the memory controllers), and check to see that
- * caused a pending HW error condition. If so, we assume it was caused by user
- * space, by setting the same interrupt that we are in (so it goes off again)
- * and context restore, and a RTI (without servicing anything). This should
- * cause the pending HWERR to fire, and when that is done, this interrupt will
- * be re-serviced properly.
- * As you can see by the code - we actually need to do two SSYNCS - one to
- * make sure the read/writes complete, and another to make sure the hardware
- * error is recognized by the core.
- *
- * The extra nop before the SSYNC is to make sure we work around 05000244,
- * since the 283/315 workaround includes a branch to the end
- */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-#endif /* CONFIG_EXACT_HWERR */
-
-/* This one pushes RETI without using CLI. Interrupts are enabled. */
-#define SAVE_CONTEXT_SYSCALL save_context_syscall
-#define SAVE_CONTEXT save_context_with_interrupts
-#define SAVE_CONTEXT_CPLB save_context_cplb
-
-#define RESTORE_ALL_SYS restore_context_no_interrupts
-#define RESTORE_CONTEXT restore_context_with_interrupts
-#define RESTORE_CONTEXT_CPLB restore_context_cplb
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BFIN_ENTRY_H */
diff --git a/arch/blackfin/include/asm/exec.h b/arch/blackfin/include/asm/exec.h
deleted file mode 100644
index 54c2e1db274a..000000000000
--- a/arch/blackfin/include/asm/exec.h
+++ /dev/null
@@ -1 +0,0 @@
-/* define arch_align_stack() here */
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
deleted file mode 100644
index bc330f06207b..000000000000
--- a/arch/blackfin/include/asm/fixed_code.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_ASM_FIXED_CODE_H__
-#define __BFIN_ASM_FIXED_CODE_H__
-
-#include <uapi/asm/fixed_code.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/linkage.h>
-#include <linux/ptrace.h>
-extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
-extern char fixed_code_start;
-extern char fixed_code_end;
-extern int atomic_xchg32(void);
-extern int atomic_cas32(void);
-extern int atomic_add32(void);
-extern int atomic_sub32(void);
-extern int atomic_ior32(void);
-extern int atomic_and32(void);
-extern int atomic_xor32(void);
-extern void safe_user_instruction(void);
-extern void sigreturn_stub(void);
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h
deleted file mode 100644
index f1d6ba7afbf2..000000000000
--- a/arch/blackfin/include/asm/flat.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * uClinux flat-format executables
- *
- * Copyright 2003-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __BLACKFIN_FLAT_H__
-#define __BLACKFIN_FLAT_H__
-
-#include <asm/unaligned.h>
-
-#define flat_argvp_envp_on_stack() 0
-#define flat_old_ram_flag(flags) (flags)
-
-extern unsigned long bfin_get_addr_from_rp (u32 *ptr, u32 relval,
- u32 flags, u32 *persistent);
-
-extern void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval);
-
-/* The amount by which a relocation can exceed the program image limits
- without being regarded as an error. */
-
-#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
-
-static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags,
- u32 *addr, u32 *persistent)
-{
- *addr = bfin_get_addr_from_rp(rp, relval, flags, persistent);
- return 0;
-}
-
-static inline int flat_put_addr_at_rp(u32 __user *rp, u32 val, u32 relval)
-{
- bfin_put_addr_at_rp(rp, val, relval);
- return 0;
-}
-
-/* Convert a relocation entry into an address. */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
- return relval & 0x03ffffff; /* Mask out top 6 bits */
-}
-
-static inline int flat_set_persistent(u32 relval, u32 *persistent)
-{
- int type = (relval >> 26) & 7;
- if (type == 3) {
- *persistent = relval << 16;
- return 1;
- }
- return 0;
-}
-
-static inline int flat_addr_absolute(unsigned long relval)
-{
- return (relval & (1 << 29)) != 0;
-}
-
-#endif /* __BLACKFIN_FLAT_H__ */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
deleted file mode 100644
index 2f1c3c2657ad..000000000000
--- a/arch/blackfin/include/asm/ftrace.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Blackfin ftrace code
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_FTRACE_H__
-#define __ASM_BFIN_FTRACE_H__
-
-#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void _mcount(void);
-#define MCOUNT_ADDR ((unsigned long)_mcount)
-
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
- return addr;
-}
-
-struct dyn_arch_ftrace {
- /* No extra data needed for Blackfin */
-};
-
-#endif
-
-#ifdef CONFIG_FRAME_POINTER
-#include <linux/mm.h>
-
-extern inline void *return_address(unsigned int level)
-{
- unsigned long *endstack, *fp, *ret_addr;
- unsigned int current_level = 0;
-
- if (level == 0)
- return __builtin_return_address(0);
-
- fp = (unsigned long *)__builtin_frame_address(0);
- endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level);
-
- while (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack && current_level < level) {
- fp = (unsigned long *)*fp;
- current_level++;
- }
-
- if (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack)
- ret_addr = (unsigned long *)*(fp + 1);
- else
- ret_addr = NULL;
-
- return ret_addr;
-}
-
-#else
-
-extern inline void *return_address(unsigned int level)
-{
- return NULL;
-}
-
-#endif /* CONFIG_FRAME_POINTER */
-
-#define ftrace_return_address(n) return_address(n)
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
deleted file mode 100644
index a2579321c7f1..000000000000
--- a/arch/blackfin/include/asm/gpio.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x) (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#include <mach/gpio.h>
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-
-#ifndef BFIN_GPIO_PINT
-# define BFIN_GPIO_PINT 0
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_PINCTRL
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/irq_handler.h>
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
- unsigned short data;
- unsigned short dummy1;
- unsigned short data_clear;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short toggle;
- unsigned short dummy4;
- unsigned short maska;
- unsigned short dummy5;
- unsigned short maska_clear;
- unsigned short dummy6;
- unsigned short maska_set;
- unsigned short dummy7;
- unsigned short maska_toggle;
- unsigned short dummy8;
- unsigned short maskb;
- unsigned short dummy9;
- unsigned short maskb_clear;
- unsigned short dummy10;
- unsigned short maskb_set;
- unsigned short dummy11;
- unsigned short maskb_toggle;
- unsigned short dummy12;
- unsigned short dir;
- unsigned short dummy13;
- unsigned short polar;
- unsigned short dummy14;
- unsigned short edge;
- unsigned short dummy15;
- unsigned short both;
- unsigned short dummy16;
- unsigned short inen;
-};
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-void bfin_special_gpio_free(unsigned gpio);
-int bfin_special_gpio_request(unsigned gpio, const char *label);
-# ifdef CONFIG_PM
-void bfin_special_gpio_pm_hibernate_restore(void);
-void bfin_special_gpio_pm_hibernate_suspend(void);
-# endif
-#endif
-
-#ifdef CONFIG_PM
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
-
-static inline int bfin_pm_standby_setup(void)
-{
- return bfin_gpio_pm_standby_ctrl(1);
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
- bfin_gpio_pm_standby_ctrl(0);
-}
-
-
-struct gpio_port_s {
- unsigned short data;
- unsigned short maska;
- unsigned short maskb;
- unsigned short dir;
- unsigned short polar;
- unsigned short edge;
- unsigned short both;
- unsigned short inen;
-
- unsigned short fer;
- unsigned short reserved;
- unsigned short mux;
-};
-#endif /*CONFIG_PM*/
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_irq_request(unsigned gpio, const char *label);
-void bfin_gpio_irq_free(unsigned gpio);
-void bfin_gpio_irq_prepare(unsigned gpio);
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq - GPIO_IRQ_BASE;
-}
-
-#else /* CONFIG_PINCTRL */
-
-/*
- * CONFIG_PM is not working with pin control and should probably
- * avoid being selected when pin control is active, but so far,
- * these stubs are here to make allyesconfig and allmodconfig
- * compile properly. These functions are normally backed by the
- * CONFIG_ADI_GPIO custom GPIO implementation.
- */
-
-static inline int bfin_pm_standby_setup(void)
-{
- return 0;
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
-}
-
-#endif /* CONFIG_PINCTRL */
-
-#include <asm/irq.h>
-#include <asm/errno.h>
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-
-static inline int gpio_get_value(unsigned int gpio)
-{
- return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
- __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
- return __gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return __gpio_to_irq(gpio);
-}
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
deleted file mode 100644
index 381e3d621a4c..000000000000
--- a/arch/blackfin/include/asm/gptimers.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _BLACKFIN_TIMERS_H_
-#define _BLACKFIN_TIMERS_H_
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * BF51x/BF52x/BF537: 8 timers:
- */
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-/*
- * BF54x: 11 timers (BF542: 8 timers):
- */
-#if defined(CONFIG_BF54x)
-# ifdef CONFIG_BF542
-# define MAX_BLACKFIN_GPTIMERS 8
-# else
-# define MAX_BLACKFIN_GPTIMERS 11
-# define TIMER8_GROUP_REG TIMER_ENABLE1
-# define TIMER_GROUP2 1
-# endif
-# define TIMER0_GROUP_REG TIMER_ENABLE0
-#endif
-/*
- * BF561: 12 timers:
- */
-#if defined(CONFIG_BF561)
-# define MAX_BLACKFIN_GPTIMERS 12
-# define TIMER0_GROUP_REG TMRS8_ENABLE
-# define TIMER8_GROUP_REG TMRS4_ENABLE
-# define TIMER_GROUP2 1
-#endif
-/*
- * BF609: 8 timers:
- */
-#if defined(CONFIG_BF60x)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_RUN
-#endif
-/*
- * All others: 3 timers:
- */
-#define TIMER_GROUP1 0
-#if !defined(MAX_BLACKFIN_GPTIMERS)
-# define MAX_BLACKFIN_GPTIMERS 3
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-
-#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
-#define BFIN_TIMER_OCTET(x) ((x) >> 3)
-
-/* used in masks for timer_enable() and timer_disable() */
-#define TIMER0bit 0x0001 /* 0001b */
-#define TIMER1bit 0x0002 /* 0010b */
-#define TIMER2bit 0x0004 /* 0100b */
-#define TIMER3bit 0x0008
-#define TIMER4bit 0x0010
-#define TIMER5bit 0x0020
-#define TIMER6bit 0x0040
-#define TIMER7bit 0x0080
-#define TIMER8bit 0x0100
-#define TIMER9bit 0x0200
-#define TIMER10bit 0x0400
-#define TIMER11bit 0x0800
-
-#define TIMER0_id 0
-#define TIMER1_id 1
-#define TIMER2_id 2
-#define TIMER3_id 3
-#define TIMER4_id 4
-#define TIMER5_id 5
-#define TIMER6_id 6
-#define TIMER7_id 7
-#define TIMER8_id 8
-#define TIMER9_id 9
-#define TIMER10_id 10
-#define TIMER11_id 11
-
-/* associated timers for ppi framesync: */
-
-#if defined(CONFIG_BF561)
-# define FS0_1_TIMER_ID TIMER8_id
-# define FS0_2_TIMER_ID TIMER9_id
-# define FS1_1_TIMER_ID TIMER10_id
-# define FS1_2_TIMER_ID TIMER11_id
-# define FS0_1_TIMER_BIT TIMER8bit
-# define FS0_2_TIMER_BIT TIMER9bit
-# define FS1_1_TIMER_BIT TIMER10bit
-# define FS1_2_TIMER_BIT TIMER11bit
-# undef FS1_TIMER_ID
-# undef FS2_TIMER_ID
-# undef FS1_TIMER_BIT
-# undef FS2_TIMER_BIT
-#else
-# define FS1_TIMER_ID TIMER0_id
-# define FS2_TIMER_ID TIMER1_id
-# define FS1_TIMER_BIT TIMER0bit
-# define FS2_TIMER_BIT TIMER1bit
-#endif
-
-#ifdef CONFIG_BF60x
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_EMU_RUN 0x8000
-#define TIMER_BPER_EN 0x4000
-#define TIMER_BWID_EN 0x2000
-#define TIMER_BDLY_EN 0x1000
-#define TIMER_OUT_DIS 0x0800
-#define TIMER_TIN_SEL 0x0400
-#define TIMER_CLK_SEL 0x0300
-#define TIMER_CLK_SCLK 0x0000
-#define TIMER_CLK_ALT_CLK0 0x0100
-#define TIMER_CLK_ALT_CLK1 0x0300
-#define TIMER_PULSE_HI 0x0080
-#define TIMER_SLAVE_TRIG 0x0040
-#define TIMER_IRQ_MODE 0x0030
-#define TIMER_IRQ_ACT_EDGE 0x0000
-#define TIMER_IRQ_DLY 0x0010
-#define TIMER_IRQ_WID_DLY 0x0020
-#define TIMER_IRQ_PER 0x0030
-#define TIMER_MODE 0x000f
-#define TIMER_MODE_WDOG_P 0x0008
-#define TIMER_MODE_WDOG_W 0x0009
-#define TIMER_MODE_PWM_CONT 0x000c
-#define TIMER_MODE_PWM 0x000d
-#define TIMER_MODE_WDTH 0x000a
-#define TIMER_MODE_WDTH_D 0x000b
-#define TIMER_MODE_EXT_CLK 0x000e
-#define TIMER_MODE_PININT 0x000f
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x0008
-#define TIMER_STATUS_TIMIL4 0x0010
-#define TIMER_STATUS_TIMIL5 0x0020
-#define TIMER_STATUS_TIMIL6 0x0040
-#define TIMER_STATUS_TIMIL7 0x0080
-
-#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0002
-#define TIMER_STATUS_TOVF2 0x0004
-#define TIMER_STATUS_TOVF3 0x0008
-#define TIMER_STATUS_TOVF4 0x0010
-#define TIMER_STATUS_TOVF5 0x0020
-#define TIMER_STATUS_TOVF6 0x0040
-#define TIMER_STATUS_TOVF7 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x0001
-#define TIMER_STATUS_TRUN1 0x0002
-#define TIMER_STATUS_TRUN2 0x0004
-#define TIMER_STATUS_TRUN3 0x0008
-#define TIMER_STATUS_TRUN4 0x0010
-#define TIMER_STATUS_TRUN5 0x0020
-#define TIMER_STATUS_TRUN6 0x0040
-#define TIMER_STATUS_TRUN7 0x0080
-
-#else
-
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_ERR 0xC000
-#define TIMER_ERR_OVFL 0x4000
-#define TIMER_ERR_PROG_PER 0x8000
-#define TIMER_ERR_PROG_PW 0xC000
-#define TIMER_EMU_RUN 0x0200
-#define TIMER_TOGGLE_HI 0x0100
-#define TIMER_CLK_SEL 0x0080
-#define TIMER_OUT_DIS 0x0040
-#define TIMER_TIN_SEL 0x0020
-#define TIMER_IRQ_ENA 0x0010
-#define TIMER_PERIOD_CNT 0x0008
-#define TIMER_PULSE_HI 0x0004
-#define TIMER_MODE 0x0003
-#define TIMER_MODE_PWM 0x0001
-#define TIMER_MODE_WDTH 0x0002
-#define TIMER_MODE_EXT_CLK 0x0003
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x00000008
-#define TIMER_STATUS_TIMIL4 0x00010000
-#define TIMER_STATUS_TIMIL5 0x00020000
-#define TIMER_STATUS_TIMIL6 0x00040000
-#define TIMER_STATUS_TIMIL7 0x00080000
-#define TIMER_STATUS_TIMIL8 0x0001
-#define TIMER_STATUS_TIMIL9 0x0002
-#define TIMER_STATUS_TIMIL10 0x0004
-#define TIMER_STATUS_TIMIL11 0x0008
-
-#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0020
-#define TIMER_STATUS_TOVF2 0x0040
-#define TIMER_STATUS_TOVF3 0x00000080
-#define TIMER_STATUS_TOVF4 0x00100000
-#define TIMER_STATUS_TOVF5 0x00200000
-#define TIMER_STATUS_TOVF6 0x00400000
-#define TIMER_STATUS_TOVF7 0x00800000
-#define TIMER_STATUS_TOVF8 0x0010
-#define TIMER_STATUS_TOVF9 0x0020
-#define TIMER_STATUS_TOVF10 0x0040
-#define TIMER_STATUS_TOVF11 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x1000
-#define TIMER_STATUS_TRUN1 0x2000
-#define TIMER_STATUS_TRUN2 0x4000
-#define TIMER_STATUS_TRUN3 0x00008000
-#define TIMER_STATUS_TRUN4 0x10000000
-#define TIMER_STATUS_TRUN5 0x20000000
-#define TIMER_STATUS_TRUN6 0x40000000
-#define TIMER_STATUS_TRUN7 0x80000000
-#define TIMER_STATUS_TRUN 0xF000F000
-#define TIMER_STATUS_TRUN8 0x1000
-#define TIMER_STATUS_TRUN9 0x2000
-#define TIMER_STATUS_TRUN10 0x4000
-#define TIMER_STATUS_TRUN11 0x8000
-
-#endif
-
-/* The actual gptimer API */
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(unsigned int timer_id);
-void set_gptimer_period(unsigned int timer_id, uint32_t period);
-uint32_t get_gptimer_period(unsigned int timer_id);
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
-uint32_t get_gptimer_delay(unsigned int timer_id);
-#endif
-uint32_t get_gptimer_count(unsigned int timer_id);
-int get_gptimer_intr(unsigned int timer_id);
-void clear_gptimer_intr(unsigned int timer_id);
-int get_gptimer_over(unsigned int timer_id);
-void clear_gptimer_over(unsigned int timer_id);
-void set_gptimer_config(unsigned int timer_id, uint16_t config);
-uint16_t get_gptimer_config(unsigned int timer_id);
-int get_gptimer_run(unsigned int timer_id);
-void set_gptimer_pulse_hi(unsigned int timer_id);
-void clear_gptimer_pulse_hi(unsigned int timer_id);
-void enable_gptimers(uint16_t mask);
-void disable_gptimers(uint16_t mask);
-void disable_gptimers_sync(uint16_t mask);
-uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(unsigned int group);
-void set_gptimer_status(unsigned int group, uint32_t value);
-
-static inline void enable_gptimer(unsigned int timer_id)
-{
- enable_gptimers(1 << timer_id);
-}
-
-static inline void disable_gptimer(unsigned int timer_id)
-{
- disable_gptimers(1 << timer_id);
-}
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin timer registers layout
- */
-struct bfin_gptimer_regs {
- __BFP(config);
- u32 counter;
- u32 period;
- u32 width;
-#ifdef CONFIG_BF60x
- u32 delay;
-#endif
-};
-
-/*
- * bfin group timer registers layout
- */
-#ifndef CONFIG_BF60x
-struct bfin_gptimer_group_regs {
- __BFP(enable);
- __BFP(disable);
- u32 status;
-};
-#else
-struct bfin_gptimer_group_regs {
- __BFP(run);
- __BFP(enable);
- __BFP(disable);
- __BFP(stop_cfg);
- __BFP(stop_cfg_set);
- __BFP(stop_cfg_clr);
- __BFP(data_imsk);
- __BFP(stat_imsk);
- __BFP(tr_msk);
- __BFP(tr_ie);
- __BFP(data_ilat);
- __BFP(stat_ilat);
- __BFP(err_status);
- __BFP(bcast_per);
- __BFP(bcast_wid);
- __BFP(bcast_dly);
-
-};
-#endif
-
-#undef __BFP
-
-#endif
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h
deleted file mode 100644
index 58b54a6d5a16..000000000000
--- a/arch/blackfin/include/asm/hardirq.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_HARDIRQ_H
-#define __BFIN_HARDIRQ_H
-
-#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
-
-extern void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
-#include <asm-generic/hardirq.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
deleted file mode 100644
index 6abebe82d4e9..000000000000
--- a/arch/blackfin/include/asm/io.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_IO_H
-#define _BFIN_IO_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include <asm/def_LPBlackfin.h>
-
-#define __raw_readb bfin_read8
-#define __raw_readw bfin_read16
-#define __raw_readl bfin_read32
-#define __raw_writeb(val, addr) bfin_write8(addr, val)
-#define __raw_writew(val, addr) bfin_write16(addr, val)
-#define __raw_writel(val, addr) bfin_write32(addr, val)
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-#define outsb outsb
-#define outsw outsw
-#define outsl outsl
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-#define insb insb
-#define insw insw
-#define insl insl
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#include <asm-generic/io.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
deleted file mode 100644
index fe1160fbff91..000000000000
--- a/arch/blackfin/include/asm/ipipe.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe.h
- *
- * Copyright (C) 2002-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_H
-#define __ASM_BLACKFIN_IPIPE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <linux/cpumask.h>
-#include <linux/list.h>
-#include <linux/threads.h>
-#include <linux/irq.h>
-#include <linux/ipipe_percpu.h>
-#include <asm/ptrace.h>
-#include <asm/irq.h>
-#include <asm/bitops.h>
-#include <linux/atomic.h>
-#include <asm/traps.h>
-#include <asm/bitsperlong.h>
-
-#define IPIPE_ARCH_STRING "1.16-01"
-#define IPIPE_MAJOR_NUMBER 1
-#define IPIPE_MINOR_NUMBER 16
-#define IPIPE_PATCH_NUMBER 1
-
-#ifdef CONFIG_SMP
-#error "I-pipe/blackfin: SMP not implemented"
-#else /* !CONFIG_SMP */
-#define ipipe_processor_id() 0
-#endif /* CONFIG_SMP */
-
-#define prepare_arch_switch(next) \
-do { \
- ipipe_schedule_notify(current, next); \
- hard_local_irq_disable(); \
-} while (0)
-
-#define task_hijacked(p) \
- ({ \
- int __x__ = __ipipe_root_domain_p; \
- if (__x__) \
- hard_local_irq_enable(); \
- !__x__; \
- })
-
-struct ipipe_domain;
-
-struct ipipe_sysinfo {
- int sys_nr_cpus; /* Number of CPUs on board */
- int sys_hrtimer_irq; /* hrtimer device IRQ */
- u64 sys_hrtimer_freq; /* hrtimer device frequency */
- u64 sys_hrclock_freq; /* hrclock device frequency */
- u64 sys_cpu_freq; /* CPU frequency (Hz) */
-};
-
-#define ipipe_read_tsc(t) \
- ({ \
- unsigned long __cy2; \
- __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
- "%1 = CYCLES\n" \
- "%2 = CYCLES2\n" \
- "CC = %2 == %0\n" \
- "if ! CC jump 1b\n" \
- : "=d,a" (((unsigned long *)&t)[1]), \
- "=d,a" (((unsigned long *)&t)[0]), \
- "=d,a" (__cy2) \
- : /*no input*/ : "CC"); \
- t; \
- })
-
-#define ipipe_cpu_freq() __ipipe_core_clock
-#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
-#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
-
-/* Private interface -- Internal use only */
-
-#define __ipipe_check_platform() do { } while (0)
-
-#define __ipipe_init_platform() do { } while (0)
-
-extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-extern unsigned long __ipipe_irq_lvmask;
-
-extern struct ipipe_domain ipipe_root;
-
-/* enable/disable_irqdesc _must_ be used in pairs. */
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-#define __ipipe_enable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_unmask(&desc->irq_data); \
- } while (0)
-
-#define __ipipe_disable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_mask(&desc->irq_data); \
- } while (0)
-
-static inline int __ipipe_check_tickdev(const char *devname)
-{
- return 1;
-}
-
-void __ipipe_enable_pipeline(void);
-
-#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
-
-void ___ipipe_sync_pipeline(void);
-
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
-
-int __ipipe_get_irq_priority(unsigned int irq);
-
-void __ipipe_serial_debug(const char *fmt, ...);
-
-asmlinkage void __ipipe_call_irqtail(unsigned long addr);
-
-DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-extern unsigned long __ipipe_core_clock;
-
-extern unsigned long __ipipe_freq_scale;
-
-extern unsigned long __ipipe_irq_tail_hook;
-
-static inline unsigned long __ipipe_ffnz(unsigned long ul)
-{
- return ffs(ul) - 1;
-}
-
-#define __ipipe_do_root_xirq(ipd, irq) \
- ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs)))
-
-#define __ipipe_run_irqtail(irq) /* Must be a macro */ \
- do { \
- unsigned long __pending; \
- CSYNC(); \
- __pending = bfin_read_IPEND(); \
- if (__pending & 0x8000) { \
- __pending &= ~0x8010; \
- if (__pending && (__pending & (__pending - 1)) == 0) \
- __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
- } \
- } while (0)
-
-#define __ipipe_syscall_watched_p(p, sc) \
- (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls)
-
-#ifdef CONFIG_BF561
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
-#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
-#elif defined(CONFIG_BF54x)
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
-#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
-#endif
-
-#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
-
-#else /* !CONFIG_IPIPE */
-
-#define task_hijacked(p) 0
-#define ipipe_trap_notify(t, r) 0
-#define __ipipe_root_tick_p(regs) 1
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
-#define IRQ_SYSTMR IRQ_CORETMR
-#define IRQ_PRIOTMR IRQ_CORETMR
-#else
-#define IRQ_SYSTMR IRQ_TIMER0
-#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
-#endif
-
-#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
-
-#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
deleted file mode 100644
index 84a4ffd36747..000000000000
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe_base.h
- *
- * Copyright (C) 2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
-#define __ASM_BLACKFIN_IPIPE_BASE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <asm/bitsperlong.h>
-#include <mach/irq.h>
-
-#define IPIPE_NR_XIRQS NR_IRQS
-
-/* Blackfin-specific, per-cpu pipeline status */
-#define IPIPE_SYNCDEFER_FLAG 15
-#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
-
- /* Blackfin traps -- i.e. exception vector numbers */
-#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
-/* Pseudo-vectors used for kernel events */
-#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
-#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
-#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
-#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
-#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
-#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
-#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
-#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
-#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7)
-#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN
-#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
-
-#define IPIPE_TIMER_IRQ IRQ_CORETMR
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#ifndef __ASSEMBLY__
-
-extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
-
-void __ipipe_stall_root(void);
-
-unsigned long __ipipe_test_and_stall_root(void);
-
-unsigned long __ipipe_test_root(void);
-
-void __ipipe_lock_root(void);
-
-void __ipipe_unlock_root(void);
-
-#endif /* !__ASSEMBLY__ */
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#endif /* CONFIG_IPIPE */
-
-#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
deleted file mode 100644
index 89de539ed010..000000000000
--- a/arch/blackfin/include/asm/irq.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 HuTao
- * 2002 Arcturus Networks Inc. (www.arcturusnetworks.com
- * Ted Ma <mated@sympatico.ca>
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_IRQ_H_
-#define _BFIN_IRQ_H_
-
-#include <linux/irqflags.h>
-
-/* IRQs that may be used by external irq_chip controllers */
-#define NR_SPARE_IRQS 32
-
-#include <mach/anomaly.h>
-
-/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
-#include <mach/irq.h>
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000244 \
- ".align 8;" \
- "sti %0;" \
- "idle;" \
- : \
- : "d" (bfin_irq_flags) \
- )
-
-#include <asm-generic/irq.h>
-
-#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
deleted file mode 100644
index d2f90c72378e..000000000000
--- a/arch/blackfin/include/asm/irq_handler.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _IRQ_HANDLER_H
-#define _IRQ_HANDLER_H
-
-#include <linux/types.h>
-#include <linux/linkage.h>
-#include <mach/irq.h>
-
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-#ifdef init_mach_irq
-extern void init_mach_irq(void);
-#else
-# define init_mach_irq()
-#endif
-
-/* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_evt14(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-asmlinkage void init_exception_buff(void);
-asmlinkage void trap_c(struct pt_regs *fp);
-asmlinkage void ex_replaceable(void);
-asmlinkage void early_trap(void);
-
-extern void *ex_table[];
-extern void return_from_exception(void);
-
-extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
-extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-struct irq_data;
-extern void bfin_handle_irq(unsigned irq);
-extern void bfin_ack_noop(struct irq_data *);
-extern void bfin_internal_mask_irq(unsigned int irq);
-extern void bfin_internal_unmask_irq(unsigned int irq);
-
-struct irq_desc;
-extern void bfin_demux_mac_status_irq(struct irq_desc *);
-extern void bfin_demux_gpio_irq(struct irq_desc *);
-
-#endif
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
deleted file mode 100644
index 07aff230a812..000000000000
--- a/arch/blackfin/include/asm/irqflags.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * interface to Blackfin CEC
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_IRQFLAGS_H__
-#define __ASM_BFIN_IRQFLAGS_H__
-
-#include <mach/blackfin.h>
-
-#ifdef CONFIG_SMP
-# include <asm/pda.h>
-# include <asm/processor.h>
-# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
-#else
-extern unsigned long bfin_irq_flags;
-#endif
-
-static inline notrace void bfin_sti(unsigned long flags)
-{
- asm volatile("sti %0;" : : "d" (flags));
-}
-
-static inline notrace unsigned long bfin_cli(void)
-{
- unsigned long flags;
- asm volatile("cli %0;" : "=d" (flags));
- return flags;
-}
-
-#ifdef CONFIG_DEBUG_HWERR
-# define bfin_no_irqs 0x3f
-#else
-# define bfin_no_irqs 0x1f
-#endif
-
-/*****************************************************************************/
-/*
- * Hard, untraced CPU interrupt flag manipulation and access.
- */
-static inline notrace void __hard_local_irq_disable(void)
-{
- bfin_cli();
-}
-
-static inline notrace void __hard_local_irq_enable(void)
-{
- bfin_sti(bfin_irq_flags);
-}
-
-static inline notrace unsigned long hard_local_save_flags(void)
-{
- return bfin_read_IMASK();
-}
-
-static inline notrace unsigned long __hard_local_irq_save(void)
-{
- unsigned long flags;
- flags = bfin_cli();
-#ifdef CONFIG_DEBUG_HWERR
- bfin_sti(0x3f);
-#endif
- return flags;
-}
-
-static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
-{
-#ifdef CONFIG_BF60x
- return (flags & IMASK_IVG11) == 0;
-#else
- return (flags & ~0x3f) == 0;
-#endif
-}
-
-static inline notrace int hard_irqs_disabled(void)
-{
- unsigned long flags = hard_local_save_flags();
- return hard_irqs_disabled_flags(flags);
-}
-
-static inline notrace void __hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags))
- __hard_local_irq_enable();
-}
-
-/*****************************************************************************/
-/*
- * Interrupt pipe handling.
- */
-#ifdef CONFIG_IPIPE
-
-#include <linux/compiler.h>
-#include <linux/ipipe_trace.h>
-/*
- * Way too many inter-deps between low-level headers in this port, so
- * we redeclare the required bits we cannot pick from
- * <asm/ipipe_base.h> to prevent circular dependencies.
- */
-void __ipipe_stall_root(void);
-void __ipipe_unstall_root(void);
-unsigned long __ipipe_test_root(void);
-unsigned long __ipipe_test_and_stall_root(void);
-void __ipipe_restore_root(unsigned long flags);
-
-#ifdef CONFIG_IPIPE_DEBUG_CONTEXT
-struct ipipe_domain;
-extern struct ipipe_domain ipipe_root;
-void ipipe_check_context(struct ipipe_domain *ipd);
-#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root)
-#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-#define __check_irqop_context(ipd) do { } while (0)
-#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-
-/*
- * Interrupt pipe interface to linux/irqflags.h.
- */
-static inline notrace void arch_local_irq_disable(void)
-{
- __check_irqop_context();
- __ipipe_stall_root();
- barrier();
-}
-
-static inline notrace void arch_local_irq_enable(void)
-{
- barrier();
- __check_irqop_context();
- __ipipe_unstall_root();
-}
-
-static inline notrace unsigned long arch_local_save_flags(void)
-{
- return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
-}
-
-static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
-{
- return flags == bfin_no_irqs;
-}
-
-static inline notrace unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
- __check_irqop_context();
- flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
- barrier();
-
- return flags;
-}
-
-static inline notrace void arch_local_irq_restore(unsigned long flags)
-{
- __check_irqop_context();
- __ipipe_restore_root(flags == bfin_no_irqs);
-}
-
-static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
-{
- /*
- * Merge virtual and real interrupt mask bits into a single
- * 32bit word.
- */
- return (real & ~(1 << 31)) | ((virt != 0) << 31);
-}
-
-static inline notrace int arch_demangle_irq_bits(unsigned long *x)
-{
- int virt = (*x & (1 << 31)) != 0;
- *x &= ~(1L << 31);
- return virt;
-}
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-static inline notrace void hard_local_irq_disable(void)
-{
- if (!hard_irqs_disabled()) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000000);
- }
-}
-
-static inline notrace void hard_local_irq_enable(void)
-{
- if (hard_irqs_disabled()) {
- ipipe_trace_end(0x80000000);
- __hard_local_irq_enable();
- }
-}
-
-static inline notrace unsigned long hard_local_irq_save(void)
-{
- unsigned long flags = hard_local_save_flags();
- if (!hard_irqs_disabled_flags(flags)) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000001);
- }
- return flags;
-}
-
-static inline notrace void hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags)) {
- ipipe_trace_end(0x80000001);
- __hard_local_irq_enable();
- }
-}
-
-#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-# define hard_local_irq_disable() __hard_local_irq_disable()
-# define hard_local_irq_enable() __hard_local_irq_enable()
-# define hard_local_irq_save() __hard_local_irq_save()
-# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-
-#define hard_local_irq_save_cond() hard_local_irq_save()
-#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags)
-
-#else /* !CONFIG_IPIPE */
-
-/*
- * Direct interface to linux/irqflags.h.
- */
-#define arch_local_save_flags() hard_local_save_flags()
-#define arch_local_irq_save() __hard_local_irq_save()
-#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define arch_local_irq_enable() __hard_local_irq_enable()
-#define arch_local_irq_disable() __hard_local_irq_disable()
-#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
-#define arch_irqs_disabled() hard_irqs_disabled()
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#define hard_local_irq_save() __hard_local_irq_save()
-#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define hard_local_irq_enable() __hard_local_irq_enable()
-#define hard_local_irq_disable() __hard_local_irq_disable()
-#define hard_local_irq_save_cond() hard_local_save_flags()
-#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0)
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_SMP
-#define hard_local_irq_save_smp() hard_local_irq_save()
-#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags)
-#else
-#define hard_local_irq_save_smp() hard_local_save_flags()
-#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0)
-#endif
-
-/*
- * Remap the arch-neutral IRQ state manipulation macros to the
- * blackfin-specific hard_local_irq_* API.
- */
-#define local_irq_save_hw(flags) \
- do { \
- (flags) = hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw(flags) \
- do { \
- hard_local_irq_restore(flags); \
- } while (0)
-#define local_irq_disable_hw() \
- do { \
- hard_local_irq_disable(); \
- } while (0)
-#define local_irq_enable_hw() \
- do { \
- hard_local_irq_enable(); \
- } while (0)
-#define local_irq_save_hw_notrace(flags) \
- do { \
- (flags) = __hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw_notrace(flags) \
- do { \
- __hard_local_irq_restore(flags); \
- } while (0)
-
-#define irqs_disabled_hw() hard_irqs_disabled()
-
-#endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
deleted file mode 100644
index 2703ddeeb5db..000000000000
--- a/arch/blackfin/include/asm/kgdb.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Blackfin KGDB header
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-#include <linux/ptrace.h>
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
- * At least NUMREGBYTES*2 are needed for register packets.
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-/*
- * Note that this register image is different from
- * the register image that Linux produces at interrupt time.
- *
- * Linux's register image is defined by struct pt_regs in ptrace.h.
- */
-enum regnames {
- /* Core Registers */
- BFIN_R0 = 0,
- BFIN_R1,
- BFIN_R2,
- BFIN_R3,
- BFIN_R4,
- BFIN_R5,
- BFIN_R6,
- BFIN_R7,
- BFIN_P0,
- BFIN_P1,
- BFIN_P2,
- BFIN_P3,
- BFIN_P4,
- BFIN_P5,
- BFIN_SP,
- BFIN_FP,
- BFIN_I0,
- BFIN_I1,
- BFIN_I2,
- BFIN_I3,
- BFIN_M0,
- BFIN_M1,
- BFIN_M2,
- BFIN_M3,
- BFIN_B0,
- BFIN_B1,
- BFIN_B2,
- BFIN_B3,
- BFIN_L0,
- BFIN_L1,
- BFIN_L2,
- BFIN_L3,
- BFIN_A0_DOT_X,
- BFIN_A0_DOT_W,
- BFIN_A1_DOT_X,
- BFIN_A1_DOT_W,
- BFIN_ASTAT,
- BFIN_RETS,
- BFIN_LC0,
- BFIN_LT0,
- BFIN_LB0,
- BFIN_LC1,
- BFIN_LT1,
- BFIN_LB1,
- BFIN_CYCLES,
- BFIN_CYCLES2,
- BFIN_USP,
- BFIN_SEQSTAT,
- BFIN_SYSCFG,
- BFIN_RETI,
- BFIN_RETX,
- BFIN_RETN,
- BFIN_RETE,
-
- /* Pseudo Registers */
- BFIN_PC,
- BFIN_CC,
- BFIN_EXTRA1, /* Address of .text section. */
- BFIN_EXTRA2, /* Address of .data section. */
- BFIN_EXTRA3, /* Address of .bss section. */
- BFIN_FDPIC_EXEC,
- BFIN_FDPIC_INTERP,
-
- /* MMRs */
- BFIN_IPEND,
-
- /* LAST ENTRY SHOULD NOT BE CHANGED. */
- BFIN_NUM_REGS /* The number of all registers. */
-};
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES BFIN_NUM_REGS*4
-
-static inline void arch_kgdb_breakpoint(void)
-{
- asm("EXCPT 2;");
-}
-#define BREAK_INSTR_SIZE 2
-#ifdef CONFIG_SMP
-# define CACHE_FLUSH_IS_SAFE 0
-#else
-# define CACHE_FLUSH_IS_SAFE 1
-#endif
-#define GDB_ADJUSTS_BREAK_OFFSET
-#define GDB_SKIP_HW_WATCH_TEST
-#define HW_INST_WATCHPOINT_NUM 6
-#define HW_WATCHPOINT_NUM 8
-#define TYPE_INST_WATCHPOINT 0
-#define TYPE_DATA_WATCHPOINT 1
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR 0x1
-#define WPIREN01 0x2
-#define WPIRINV01 0x4
-#define WPIAEN0 0x8
-#define WPIAEN1 0x10
-#define WPICNTEN0 0x20
-#define WPICNTEN1 0x40
-#define EMUSW0 0x80
-#define EMUSW1 0x100
-#define WPIREN23 0x200
-#define WPIRINV23 0x400
-#define WPIAEN2 0x800
-#define WPIAEN3 0x1000
-#define WPICNTEN2 0x2000
-#define WPICNTEN3 0x4000
-#define EMUSW2 0x8000
-#define EMUSW3 0x10000
-#define WPIREN45 0x20000
-#define WPIRINV45 0x40000
-#define WPIAEN4 0x80000
-#define WPIAEN5 0x100000
-#define WPICNTEN4 0x200000
-#define WPICNTEN5 0x400000
-#define EMUSW4 0x800000
-#define EMUSW5 0x1000000
-#define WPAND 0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01 0x1
-#define WPDRINV01 0x2
-#define WPDAEN0 0x4
-#define WPDAEN1 0x8
-#define WPDCNTEN0 0x10
-#define WPDCNTEN1 0x20
-
-#define WPDSRC0 0xc0
-#define WPDACC0_OFFSET 8
-#define WPDSRC1 0xc00
-#define WPDACC1_OFFSET 12
-
-/* Watchpoint status register bits mask */
-#define STATIA0 0x1
-#define STATIA1 0x2
-#define STATIA2 0x4
-#define STATIA3 0x8
-#define STATIA4 0x10
-#define STATIA5 0x20
-#define STATDA0 0x40
-#define STATDA1 0x80
-
-#endif
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h
deleted file mode 100644
index c87e68647a2b..000000000000
--- a/arch/blackfin/include/asm/l1layout.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Defines a layout of L1 scratchpad memory that userspace can rely on.
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _L1LAYOUT_H_
-#define _L1LAYOUT_H_
-
-#include <asm/blackfin.h>
-
-#ifndef CONFIG_SMP
-#ifndef __ASSEMBLY__
-
-/* Data that is "mapped" into the process VM at the start of the L1 scratch
- memory, so that each process can access it at a fixed address. Used for
- stack checking. */
-struct l1_scratch_task_info
-{
- /* Points to the start of the stack. */
- void *stack_start;
- /* Not updated by the kernel; a user process can modify this to
- keep track of the lowest address of the stack pointer during its
- runtime. */
- void *lowest_sp;
-};
-
-/* A pointer to the structure in memory. */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\
- get_l1_scratch_start())
-
-#endif
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
deleted file mode 100644
index f7d6d47a048d..000000000000
--- a/arch/blackfin/include/asm/linkage.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
deleted file mode 100644
index c865b33eeb68..000000000000
--- a/arch/blackfin/include/asm/mem_init.h
+++ /dev/null
@@ -1,500 +0,0 @@
-/*
- * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MEM_INIT_H__
-#define __MEM_INIT_H__
-
-#if defined(EBIU_SDGCTL)
-#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_1
-#define SDRAM_tRAS_num 1
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-/*
- * The BF526-EZ-Board changed SDRAM chips between revisions,
- * so we use below timings to accommodate both.
- */
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_8
-#define SDRAM_tRAS_num 8
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_2
-#endif
-
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-#else
-#define mem_SDRRC CONFIG_MEM_SDRRC
-#define mem_SDGCTL CONFIG_MEM_SDGCTL
-#endif
-#endif
-
-
-#if defined(EBIU_DDRCTL0)
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x) (1000*1000*1000/x)
-
-#if defined(CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(1)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if defined(CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(2)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define DDR_CL CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
- | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2 DDR_CL
-#else
-#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
-#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
-#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
-#endif
-#endif
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF 1
-#else
-#define CLKIN_HALF 0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS 1
-#else
-#define PLL_BYPASS 0
-#endif
-
-#ifdef CONFIG_BF60x
-
-/* DMC status bits */
-#define IDLE 0x1
-#define MEMINITDONE 0x4
-#define SRACK 0x8
-#define PDACK 0x10
-#define DPDACK 0x20
-#define DLLCALDONE 0x2000
-#define PENDREF 0xF0000
-#define PHYRDPHASE 0xF00000
-#define PHYRDPHASE_OFFSET 20
-
-/* DMC control bits */
-#define LPDDR 0x2
-#define INIT 0x4
-#define SRREQ 0x8
-#define PDREQ 0x10
-#define DPDREQ 0x20
-#define PREC 0x40
-#define ADDRMODE 0x100
-#define RDTOWR 0xE00
-#define PPREF 0x1000
-#define DLLCAL 0x2000
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT 0xFF
-#define DATACYC 0xF00
-#define DATACYC_OFFSET 8
-
-/* CGU Divisor bits */
-#define CSEL_OFFSET 0
-#define S0SEL_OFFSET 5
-#define SYSSEL_OFFSET 8
-#define S1SEL_OFFSET 13
-#define DSEL_OFFSET 16
-#define OSEL_OFFSET 22
-#define ALGN 0x20000000
-#define UPDT 0x40000000
-#define LOCK 0x80000000
-
-/* CGU Status bits */
-#define PLLEN 0x1
-#define PLLBP 0x2
-#define PLOCK 0x4
-#define CLKSALGN 0x8
-
-/* CGU Control bits */
-#define MSEL_MASK 0x7F00
-#define DF_MASK 0x1
-
-struct ddr_config {
- u32 ddr_clk;
- u32 dmc_ddrctl;
- u32 dmc_effctl;
- u32 dmc_ddrcfg;
- u32 dmc_ddrtr0;
- u32 dmc_ddrtr1;
- u32 dmc_ddrtr2;
- u32 dmc_ddrmr;
- u32 dmc_ddrmr1;
-};
-
-#if defined(CONFIG_MEM_MT47H64M16)
-static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
- [0] = {
- .ddr_clk = 125,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20705212,
- .dmc_ddrtr1 = 0x201003CF,
- .dmc_ddrtr2 = 0x00320107,
- .dmc_ddrmr = 0x00000422,
- .dmc_ddrmr1 = 0x4,
- },
- [1] = {
- .ddr_clk = 133,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20806313,
- .dmc_ddrtr1 = 0x2013040D,
- .dmc_ddrtr2 = 0x00320108,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [2] = {
- .ddr_clk = 150,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x20160492,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [3] = {
- .ddr_clk = 166,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x2016050E,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [4] = {
- .ddr_clk = 200,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20a07323,
- .dmc_ddrtr1 = 0x2016050f,
- .dmc_ddrtr2 = 0x00320509,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [5] = {
- .ddr_clk = 225,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x302006DB,
- .dmc_ddrtr2 = 0x0032020D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
- [6] = {
- .ddr_clk = 250,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x3020079E,
- .dmc_ddrtr2 = 0x0032050D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
-};
-#endif
-
-static inline void dmc_enter_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
- while (!(bfin_read_DMC0_STAT() & SRACK))
- continue;
- }
-}
-
-static inline void dmc_exit_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
- while (bfin_read_DMC0_STAT() & SRACK)
- continue;
- }
-}
-
-static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
-{
- dmc_enter_self_refresh();
-
- /* Don't set the same value of MSEL and DF to CGU_CTL */
- if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
- != cgu_ctl) {
- bfin_write32(CGU0_DIV, cgu_div);
- bfin_write32(CGU0_CTL, cgu_ctl);
- while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
- !(bfin_read32(CGU0_STAT) & PLOCK))
- continue;
- }
-
- bfin_write32(CGU0_DIV, cgu_div | UPDT);
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-
- dmc_exit_self_refresh();
-}
-
-static inline void init_dmc(u32 dmc_clk)
-{
- int i, dlldatacycle, dll_ctl;
-
- for (i = 0; i < 7; i++) {
- if (ddr_config_table[i].ddr_clk == dmc_clk) {
- bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
- bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
- bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
- bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
- bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
- bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
- bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
- bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
- break;
- }
- }
-
- while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
- continue;
-
- dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
- dll_ctl = bfin_read_DMC0_DLLCTL();
- dll_ctl &= ~DATACYC;
- bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
- while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
- continue;
-}
-#endif
-
-#endif /*__MEM_INIT_H__*/
-
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
deleted file mode 100644
index 5e21627c9ba2..000000000000
--- a/arch/blackfin/include/asm/mem_map.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MEM_MAP_H__
-#define __BFIN_MEM_MAP_H__
-
-#include <mach/mem_map.h>
-
-/* Every Blackfin so far has MMRs like this */
-#ifndef COREMMR_BASE
-# define COREMMR_BASE 0xFFE00000
-#endif
-#ifndef SYSMMR_BASE
-# define SYSMMR_BASE 0xFFC00000
-#endif
-
-/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
-#ifndef L1_SCRATCH_START
-# define L1_SCRATCH_START 0xFFB00000
-# define L1_SCRATCH_LENGTH 0x1000
-#endif
-
-/* Most parts lack on-chip L2 SRAM */
-#ifndef L2_START
-# define L2_START 0
-# define L2_LENGTH 0
-#endif
-
-/* Most parts lack on-chip L1 ROM */
-#ifndef L1_ROM_START
-# define L1_ROM_START 0
-# define L1_ROM_LENGTH 0
-#endif
-
-/* Allow wonky SMP ports to override this */
-#ifndef GET_PDA_SAFE
-# define GET_PDA_SAFE(preg) \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda;
-# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
-
-# ifndef __ASSEMBLY__
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return L1_DATA_B_START;
-}
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(0);
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(0);
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(0);
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(0);
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* !GET_PDA_SAFE */
-
-#endif
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
deleted file mode 100644
index 26f6b70b11e2..000000000000
--- a/arch/blackfin/include/asm/mmu.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2002 David McCullough <davidm@snapgear.com>
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef __MMU_H
-#define __MMU_H
-
-struct sram_list_struct {
- struct sram_list_struct *next;
- void *addr;
- size_t length;
-};
-
-typedef struct {
- unsigned long end_brk;
- unsigned long stack_start;
-
- /* Points to the location in SDRAM where the L1 stack is normally
- saved, or NULL if the stack is always in SDRAM. */
- void *l1_stack_save;
-
- struct sram_list_struct *sram_list;
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
- unsigned long exec_fdpic_loadmap;
- unsigned long interp_fdpic_loadmap;
-#endif
-#ifdef CONFIG_MPU
- unsigned long *page_rwx_mask;
-#endif
-} mm_context_t;
-
-#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
deleted file mode 100644
index 0ce6de873b27..000000000000
--- a/arch/blackfin/include/asm/mmu_context.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_MMU_CONTEXT_H__
-#define __BLACKFIN_MMU_CONTEXT_H__
-
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/cplbinit.h>
-#include <asm/sections.h>
-
-/* Note: L1 stacks are CPU-private things, so we bluntly disable this
- feature in SMP mode, and use the per-CPU scratch SRAM bank only to
- store the PDA instead. */
-
-extern void *current_l1_stack_save;
-extern int nr_l1stack_tasks;
-extern void *l1_stack_base;
-extern unsigned long l1_stack_len;
-
-extern int l1sram_free(const void*);
-extern void *l1sram_alloc_max(void*);
-
-static inline void free_l1stack(void)
-{
- nr_l1stack_tasks--;
- if (nr_l1stack_tasks == 0) {
- l1sram_free(l1_stack_base);
- l1_stack_base = NULL;
- l1_stack_len = 0;
- }
-}
-
-static inline unsigned long
-alloc_l1stack(unsigned long length, unsigned long *stack_base)
-{
- if (nr_l1stack_tasks == 0) {
- l1_stack_base = l1sram_alloc_max(&l1_stack_len);
- if (!l1_stack_base)
- return 0;
- }
-
- if (l1_stack_len < length) {
- if (nr_l1stack_tasks == 0)
- l1sram_free(l1_stack_base);
- return 0;
- }
- *stack_base = (unsigned long)l1_stack_base;
- nr_l1stack_tasks++;
- return l1_stack_len;
-}
-
-static inline int
-activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
-{
- if (current_l1_stack_save)
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
- return 1;
-}
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-
-static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
- struct task_struct *tsk)
-{
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
- if (prev_mm == next_mm)
- return;
-#ifdef CONFIG_MPU
- if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
- }
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- /* L1 stack switching. */
- if (!next_mm->context.l1_stack_save)
- return;
- if (next_mm->context.l1_stack_save == current_l1_stack_save)
- return;
- if (current_l1_stack_save) {
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- }
- current_l1_stack_save = next_mm->context.l1_stack_save;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-#endif
-}
-
-#ifdef CONFIG_IPIPE
-#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
-#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
-#else
-#define lock_mm_switch(flags) do { (void)(flags); } while (0)
-#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
-#endif /* CONFIG_IPIPE */
-
-#ifdef CONFIG_MPU
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- unsigned long flags;
- lock_mm_switch(flags);
- __switch_mm(prev, next, tsk);
- unlock_mm_switch(flags);
-}
-
-static inline void protect_page(struct mm_struct *mm, unsigned long addr,
- unsigned long flags)
-{
- unsigned long *mask = mm->context.page_rwx_mask;
- unsigned long page;
- unsigned long idx;
- unsigned long bit;
-
- if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
- else
- page = addr >> 12;
- idx = page >> 5;
- bit = 1 << (page & 31);
-
- if (flags & VM_READ)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_WRITE)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_EXEC)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
-}
-
-static inline void update_protections(struct mm_struct *mm)
-{
- unsigned int cpu = smp_processor_id();
- if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
- }
-}
-#else /* !CONFIG_MPU */
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- __switch_mm(prev, next, tsk);
-}
-#endif
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* Called when creating a new context during fork() or execve(). */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-#ifdef CONFIG_MPU
- unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
- mm->context.page_rwx_mask = (unsigned long *)p;
- memset(mm->context.page_rwx_mask, 0,
- page_mask_nelts * 3 * sizeof(long));
-#endif
- return 0;
-}
-
-static inline void destroy_context(struct mm_struct *mm)
-{
- struct sram_list_struct *tmp;
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- if (current_l1_stack_save == mm->context.l1_stack_save)
- current_l1_stack_save = 0;
- if (mm->context.l1_stack_save)
- free_l1stack();
-#endif
-
- while ((tmp = mm->context.sram_list)) {
- mm->context.sram_list = tmp->next;
- sram_free(tmp->addr);
- kfree(tmp);
- }
-#ifdef CONFIG_MPU
- if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
- current_rwx_mask[cpu] = NULL;
- free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
-#endif
-}
-
-#define ipipe_mm_switch_protect(flags) \
- flags = hard_local_irq_save_cond()
-
-#define ipipe_mm_switch_unprotect(flags) \
- hard_local_irq_restore_cond(flags)
-
-#endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
deleted file mode 100644
index 231a149b3f77..000000000000
--- a/arch/blackfin/include/asm/module.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#include <asm-generic/module.h>
-
-struct mod_arch_specific {
- Elf_Shdr *text_l1;
- Elf_Shdr *data_a_l1;
- Elf_Shdr *bss_a_l1;
- Elf_Shdr *data_b_l1;
- Elf_Shdr *bss_b_l1;
- Elf_Shdr *text_l2;
- Elf_Shdr *data_l2;
- Elf_Shdr *bss_l2;
-};
-#endif /* _ASM_BFIN_MODULE_H */
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
deleted file mode 100644
index 256c50d8d465..000000000000
--- a/arch/blackfin/include/asm/nand.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * BF5XX - NAND flash controller platform_device info
- *
- * Copyright 2007-2008 Analog Devices, Inc.
- *
- * Licensed under the GPL-2
- */
-
-/* struct bf5xx_nand_platform
- *
- * define a interface between platform board specific code and
- * bf54x NFC driver.
- *
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * partitions = mtd partition list
- */
-
-#define NFC_PG_SIZE_OFFSET 9
-
-#define NFC_NWIDTH_8 0
-#define NFC_NWIDTH_16 1
-#define NFC_NWIDTH_OFFSET 8
-
-#define NFC_RDDLY_OFFSET 4
-#define NFC_WRDLY_OFFSET 0
-
-#define NFC_STAT_NBUSY 1
-
-struct bf5xx_nand_platform {
- /* NAND chip information */
- unsigned short data_width;
-
- /* RD/WR strobe delay timing information, all times in SCLK cycles */
- unsigned short rd_dly;
- unsigned short wr_dly;
-
- /* NAND MTD partition information */
- int nr_partitions;
- struct mtd_partition *partitions;
-};
diff --git a/arch/blackfin/include/asm/nmi.h b/arch/blackfin/include/asm/nmi.h
deleted file mode 100644
index 107d23705f46..000000000000
--- a/arch/blackfin/include/asm/nmi.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_NMI_H_
-#define _BFIN_NMI_H_
-
-#include <linux/nmi.h>
-
-extern void arch_touch_nmi_watchdog(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
deleted file mode 100644
index b93474d5be75..000000000000
--- a/arch/blackfin/include/asm/page.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
-#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/page.h>
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h
deleted file mode 100644
index d06a89b89d20..000000000000
--- a/arch/blackfin/include/asm/page_offset.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This handles the memory map
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW 0x00000000
-#endif
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
deleted file mode 100644
index e6458ddbaf7e..000000000000
--- a/arch/blackfin/include/asm/pci.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Changed from asm-m68k version, Lineo Inc. May 2001 */
-
-#ifndef _ASM_BFIN_PCI_H
-#define _ASM_BFIN_PCI_H
-
-#include <linux/scatterlist.h>
-#include <asm-generic/pci.h>
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#endif /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
deleted file mode 100644
index 68d6f6618f2a..000000000000
--- a/arch/blackfin/include/asm/pda.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_PDA_H
-#define _ASM_BLACKFIN_PDA_H
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-struct blackfin_pda { /* Per-processor Data Area */
-#ifdef CONFIG_SMP
- struct blackfin_pda *next;
-#endif
-
- unsigned long syscfg;
-#ifdef CONFIG_SMP
- unsigned long imask; /* Current IMASK value */
-#endif
-
- unsigned long *ipdt; /* Start of switchable I-CPLB table */
- unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */
- unsigned long *dpdt; /* Start of switchable D-CPLB table */
- unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */
-
- /*
- * Single instructions can have multiple faults, which
- * need to be handled by traps.c, in irq5. We store
- * the exception cause to ensure we don't miss a
- * double fault condition
- */
- unsigned long ex_iptr;
- unsigned long ex_optr;
- unsigned long ex_buf[4];
- unsigned long ex_imask; /* Saved imask from exception */
- unsigned long ex_ipend; /* Saved IPEND from exception */
- unsigned long *ex_stack; /* Exception stack space */
-
-#ifdef ANOMALY_05000261
- unsigned long last_cplb_fault_retx;
-#endif
- unsigned long dcplb_fault_addr;
- unsigned long icplb_fault_addr;
- unsigned long retx;
- unsigned long seqstat;
- unsigned int __nmi_count; /* number of times NMI asserted on this CPU */
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- unsigned long dcplb_doublefault_addr;
- unsigned long icplb_doublefault_addr;
- unsigned long retx_doublefault;
- unsigned long seqstat_doublefault;
-#endif
-};
-
-struct blackfin_initial_pda {
- void *retx;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- void *dcplb_doublefault_addr;
- void *icplb_doublefault_addr;
- void *retx_doublefault;
- unsigned seqstat_doublefault;
-#endif
-};
-
-extern struct blackfin_pda cpu_pda[];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_BLACKFIN_PDA_H */
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
deleted file mode 100644
index 3d2b1716322f..000000000000
--- a/arch/blackfin/include/asm/perf_event.h
+++ /dev/null
@@ -1 +0,0 @@
-#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
deleted file mode 100644
index c1ee3d6533fb..000000000000
--- a/arch/blackfin/include/asm/pgtable.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PGTABLE_H
-#define _BLACKFIN_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/page.h>
-#include <asm/def_LPBlackfin.h>
-
-typedef pte_t *pte_addr_t;
-/*
-* Trivial page table functions.
-*/
-#define pgd_present(pgd) (1)
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-
-#define pmd_offset(a, b) ((void *)0)
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x))
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
-
-#define kern_addr_valid(addr) (1)
-
-#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
-#define pgprot_noncached(prot) (prot)
-
-extern void paging_init(void);
-
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-/*
- * Page assess control based on Blackfin CPLB management
- */
-#define _PAGE_RD (CPLB_USER_RD)
-#define _PAGE_WR (CPLB_USER_WR)
-#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
-#define _PAGE_ACCESSED CPLB_ALL_ACCESS
-#define _PAGE_DIRTY (CPLB_DIRTY)
-
-#define PTE_BIT_FUNC(fn, op) \
- static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
-
-PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
-PTE_BIT_FUNC(mkread, |= _PAGE_RD);
-PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
-PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
-PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
-PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
-PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
-PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
-PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
-PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-extern char empty_zero_page[];
-
-#define swapper_pg_dir ((pgd_t *) 0)
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init() do { } while (0)
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START 0
-#define VMALLOC_END 0xffffffff
-
-/* provide a special get_unmapped_area for framebuffer mmaps of nommu */
-extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
- unsigned long, unsigned long,
- unsigned long);
-#define HAVE_ARCH_FB_UNMAPPED_AREA
-
-#define pgprot_writecombine pgprot_noncached
-
-#include <asm-generic/pgtable.h>
-
-#endif /* _BLACKFIN_PGTABLE_H */
diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h
deleted file mode 100644
index f72239bf3638..000000000000
--- a/arch/blackfin/include/asm/pm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __PM_H__
-#define __PM_H__
-
-#include <linux/suspend.h>
-
-struct bfin_cpu_pm_fns {
- void (*save)(unsigned long *);
- void (*restore)(unsigned long *);
- int (*valid)(suspend_state_t state);
- void (*enter)(suspend_state_t state);
- int (*prepare)(void);
- void (*finish)(void);
-};
-
-extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
-
-# ifdef CONFIG_BFIN_COREB
-void bfin_coreb_start(void);
-void bfin_coreb_stop(void);
-void bfin_coreb_reset(void);
-# endif
-
-#endif
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
deleted file mode 100644
index c8f0939419be..000000000000
--- a/arch/blackfin/include/asm/portmux.h
+++ /dev/null
@@ -1,1204 +0,0 @@
-/*
- * Common header file for Blackfin family of processors
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x) ((x) & 0x1FF)
-#define P_FUNCT(x) (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
-#define P_DEFINED 0x8000
-#define P_UNDEF 0x4000
-#define P_MAYSHARE 0x2000
-#define P_DONTCARE 0x1000
-
-#ifdef CONFIG_PINCTRL
-int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-#define gpio_pint_regs bfin_pint_regs
-#define adi_internal_set_wake bfin_internal_set_wake
-
-#define peripheral_request(per, label) (0)
-#define peripheral_free(per)
-#define peripheral_request_list(per, label) (0)
-#define peripheral_free_list(per)
-#else
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-#endif
-
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <mach/portmux.h>
-#include <mach/gpio.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
deleted file mode 100644
index dbdbb8a558df..000000000000
--- a/arch/blackfin/include/asm/processor.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PROCESSOR_H
-#define __ASM_BFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <asm/ptrace.h>
-#include <mach/blackfin.h>
-
-static inline unsigned long rdusp(void)
-{
- unsigned long usp;
-
- __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
- return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
- __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-static inline unsigned long __get_SP(void)
-{
- unsigned long sp;
-
- __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp));
- return sp;
-}
-
-/*
- * User space process size: 1st byte beyond user address space.
- * Fairly meaningless on nommu. Parts of user programs can be scattered
- * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
- */
-#define TASK_SIZE 0xFFFFFFFF
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#endif
-
-#define TASK_UNMAPPED_BASE 0
-
-struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned short seqstat; /* saved status register */
- unsigned long esp0; /* points to SR of stack frame pt_regs */
- unsigned long pc; /* instruction pointer */
- void * debuggerinfo;
-};
-
-#define INIT_THREAD { \
- sizeof(init_stack) + (unsigned long) init_stack, 0, \
- PS_S, 0, 0 \
-}
-
-extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
- unsigned long new_sp);
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) \
- ({ \
- unsigned long eip = 0; \
- if ((tsk)->thread.esp0 > PAGE_SIZE && \
- MAP_NR((tsk)->thread.esp0) < max_mapnr) \
- eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
- eip; })
-#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax() smp_mb()
-
-/* Get the Silicon Revision of the chip */
-static inline uint32_t __pure bfin_revid(void)
-{
- /* Always use CHIPID, to work around ANOMALY_05000234 */
- uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;
-
-#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI
- /*
- * ANOMALY_05000364
- * Incorrect Revision Number in DSPID Register
- */
- if (ANOMALY_05000364 &&
- bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796)
- revid = 1;
-#endif
-
- return revid;
-}
-
-static inline uint16_t __pure bfin_cpuid(void)
-{
- return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
-}
-
-static inline uint32_t __pure bfin_dspid(void)
-{
- return bfin_read_DSPID();
-}
-
-#define blackfin_core_id() (bfin_dspid() & 0xff)
-
-static inline uint32_t __pure bfin_compiled_revid(void)
-{
-#if defined(CONFIG_BF_REV_0_0)
- return 0;
-#elif defined(CONFIG_BF_REV_0_1)
- return 1;
-#elif defined(CONFIG_BF_REV_0_2)
- return 2;
-#elif defined(CONFIG_BF_REV_0_3)
- return 3;
-#elif defined(CONFIG_BF_REV_0_4)
- return 4;
-#elif defined(CONFIG_BF_REV_0_5)
- return 5;
-#elif defined(CONFIG_BF_REV_0_6)
- return 6;
-#elif defined(CONFIG_BF_REV_ANY)
- return 0xffff;
-#else
- return -1;
-#endif
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h
deleted file mode 100644
index b00adfa08169..000000000000
--- a/arch/blackfin/include/asm/pseudo_instructions.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * header file for pseudo instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PSEUDO_
-#define _BLACKFIN_PSEUDO_
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-
-extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
-extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
-
-#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
deleted file mode 100644
index c00491594b46..000000000000
--- a/arch/blackfin/include/asm/ptrace.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-#ifndef __ASSEMBLY__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
- master interrupt enable. */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-
-#define arch_has_single_step() (1)
-/* common code demands this function */
-#define ptrace_disable(child) user_disable_single_step(child)
-#define current_user_stack_pointer() rdusp()
-
-extern int is_user_addr_valid(struct task_struct *child,
- unsigned long start, unsigned long len);
-
-/*
- * Get the address of the live pt_regs for the specified task.
- * These are saved onto the top kernel stack when the process
- * is not running.
- *
- * Note: if a user thread is execve'd from kernel space, the
- * kernel stack will not be empty on entry to the kernel, so
- * ptracing these tasks will fail.
- */
-#define task_pt_regs(task) \
- (struct pt_regs *) \
- ((unsigned long)task_stack_page(task) + \
- (THREAD_SIZE - sizeof(struct pt_regs)))
-
-#include <asm-generic/ptrace.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h
deleted file mode 100644
index ae1e36329bec..000000000000
--- a/arch/blackfin/include/asm/reboot.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * reboot.h - shutdown/reboot header
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_REBOOT_H__
-#define __ASM_REBOOT_H__
-
-/* optional board specific hooks */
-extern void native_machine_restart(char *cmd);
-extern void native_machine_halt(void);
-extern void native_machine_power_off(void);
-
-/* common reboot workarounds */
-extern void bfin_reset_boot_spi_cs(unsigned short pin);
-
-#endif
diff --git a/arch/blackfin/include/asm/rwlock.h b/arch/blackfin/include/asm/rwlock.h
deleted file mode 100644
index 98ebc07cb283..000000000000
--- a/arch/blackfin/include/asm/rwlock.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_BLACKFIN_RWLOCK_H
-#define _ASM_BLACKFIN_RWLOCK_H
-
-#define RW_LOCK_BIAS 0x01000000
-
-#endif
diff --git a/arch/blackfin/include/asm/scb.h b/arch/blackfin/include/asm/scb.h
deleted file mode 100644
index a294cc0d1a4a..000000000000
--- a/arch/blackfin/include/asm/scb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define SCB_SLOT_OFFSET 24
-#define SCB_MI_MAX_SLOT 32
-
-struct scb_mi_prio {
- unsigned long scb_mi_arbr;
- unsigned long scb_mi_arbw;
- unsigned char scb_mi_slots;
- unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
-};
-
-extern struct scb_mi_prio scb_data[];
-
-extern void init_scb(void);
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
deleted file mode 100644
index fbd408475725..000000000000
--- a/arch/blackfin/include/asm/sections.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_SECTIONS_H
-#define _BLACKFIN_SECTIONS_H
-
-/* only used when MTD_UCLINUX */
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
-
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-
-/*
- * The weak markings on the lengths might seem weird, but this is required
- * in order to make gcc accept the fact that these may actually have a value
- * of 0 (since they aren't actually addresses, but sizes of sections).
- */
-extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
-extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
- _data_l1_lma[], __weak _data_l1_len[];
-#ifdef CONFIG_ROMKERNEL
-extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[];
-#endif
-extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
- _data_b_l1_lma[], __weak _data_b_l1_len[];
-extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
- _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
-
-#include <asm/mem_map.h>
-
-/* Blackfin systems have discontinuous memory map and no virtualized memory */
-static inline int arch_is_kernel_text(unsigned long addr)
-{
- return
- (L1_CODE_LENGTH &&
- addr >= (unsigned long)_stext_l1 &&
- addr < (unsigned long)_etext_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_stext_l2 &&
- addr < (unsigned long)_etext_l2);
-}
-#define arch_is_kernel_text(addr) arch_is_kernel_text(addr)
-
-static inline int arch_is_kernel_data(unsigned long addr)
-{
- return
- (L1_DATA_A_LENGTH &&
- addr >= (unsigned long)_sdata_l1 &&
- addr < (unsigned long)_ebss_l1)
- ||
- (L1_DATA_B_LENGTH &&
- addr >= (unsigned long)_sdata_b_l1 &&
- addr < (unsigned long)_ebss_b_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_sdata_l2 &&
- addr < (unsigned long)_ebss_l2);
-}
-#define arch_is_kernel_data(addr) arch_is_kernel_data(addr)
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h
deleted file mode 100644
index f8e1984ffc7e..000000000000
--- a/arch/blackfin/include/asm/segment.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_SEGMENT_H
-#define _BFIN_SEGMENT_H
-
-#define KERNEL_DS (0x5)
-#define USER_DS (0x1)
-
-#endif /* _BFIN_SEGMENT_H */
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
deleted file mode 100644
index 9631598dcc5d..000000000000
--- a/arch/blackfin/include/asm/smp.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SMP_H
-#define __ASM_BLACKFIN_SMP_H
-
-#include <linux/kernel.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/cache.h>
-#include <asm/blackfin.h>
-#include <mach/smp.h>
-
-#define raw_smp_processor_id() blackfin_core_id()
-
-extern void bfin_relocate_coreb_l1_mem(void);
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
-asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
-extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct corelock_slot {
- int lock;
-};
-extern struct corelock_slot corelock;
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-extern unsigned long icache_invld_count[NR_CPUS];
-#endif
-#ifdef __ARCH_SYNC_CORE_DCACHE
-extern unsigned long dcache_invld_count[NR_CPUS];
-#endif
-
-void smp_icache_flush_range_others(unsigned long start,
- unsigned long end);
-#ifdef CONFIG_HOTPLUG_CPU
-void coreb_die(void);
-void cpu_die(void);
-void platform_cpu_die(void);
-int __cpu_disable(void);
-int __cpu_die(unsigned int cpu);
-#endif
-
-void smp_timer_broadcast(const struct cpumask *mask);
-
-
-#endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
deleted file mode 100644
index 839d1441af3a..000000000000
--- a/arch/blackfin/include/asm/spinlock.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SPINLOCK_H
-#define __BFIN_SPINLOCK_H
-
-#ifndef CONFIG_SMP
-# include <asm-generic/spinlock.h>
-#else
-
-#include <linux/atomic.h>
-#include <asm/processor.h>
-#include <asm/barrier.h>
-
-asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
-asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
-asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_read_lock_asm(volatile int *ptr);
-asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_write_lock_asm(volatile int *ptr);
-asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- return __raw_spin_is_locked_asm(&lock->lock);
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- __raw_spin_lock_asm(&lock->lock);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- return __raw_spin_trylock_asm(&lock->lock);
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- __raw_spin_unlock_asm(&lock->lock);
-}
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- __raw_read_lock_asm(&rw->lock);
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- return __raw_read_trylock_asm(&rw->lock);
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- __raw_read_unlock_asm(&rw->lock);
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- __raw_write_lock_asm(&rw->lock);
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- return __raw_write_trylock_asm(&rw->lock);
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- __raw_write_unlock_asm(&rw->lock);
-}
-
-#endif
-
-#endif /* !__BFIN_SPINLOCK_H */
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h
deleted file mode 100644
index 1a33608c958b..000000000000
--- a/arch/blackfin/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-#include <asm/rwlock.h>
-
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
deleted file mode 100644
index 423c099aa988..000000000000
--- a/arch/blackfin/include/asm/string.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_STRING_H_
-#define _BLACKFIN_STRING_H_
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-extern char *strcpy(char *dest, const char *src);
-
-#define __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *dest, const char *src, size_t n);
-
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *cs, const char *ct);
-
-#define __HAVE_ARCH_STRNCMP
-extern int strncmp(const char *cs, const char *ct, size_t count);
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t count);
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *d, const void *s, size_t count);
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *s, int c, size_t n);
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#endif /*__KERNEL__*/
-#endif /* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/switch_to.h b/arch/blackfin/include/asm/switch_to.h
deleted file mode 100644
index aaf671be9242..000000000000
--- a/arch/blackfin/include/asm/switch_to.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_SWITCH_TO_H
-#define _BLACKFIN_SWITCH_TO_H
-
-#define prepare_to_switch() do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/l1layout.h>
-#include <asm/mem_map.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#ifndef CONFIG_SMP
-#define switch_to(prev,next,last) \
-do { \
- memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- (last) = resume (prev, next); \
-} while (0)
-#else
-#define switch_to(prev, next, last) \
-do { \
- (last) = resume(prev, next); \
-} while (0)
-#endif
-
-#endif /* _BLACKFIN_SWITCH_TO_H */
diff --git a/arch/blackfin/include/asm/syscall.h b/arch/blackfin/include/asm/syscall.h
deleted file mode 100644
index 4921a4815cce..000000000000
--- a/arch/blackfin/include/asm/syscall.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Magic syscall break down functions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SYSCALL_H__
-#define __ASM_BLACKFIN_SYSCALL_H__
-
-/*
- * Blackfin syscalls are simple:
- * enter:
- * p0: syscall number
- * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5
- * exit:
- * r0: return/error value
- */
-
-#include <linux/err.h>
-#include <linux/sched.h>
-#include <asm/ptrace.h>
-
-static inline long
-syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->p0;
-}
-
-static inline void
-syscall_rollback(struct task_struct *task, struct pt_regs *regs)
-{
- regs->p0 = regs->orig_p0;
-}
-
-static inline long
-syscall_get_error(struct task_struct *task, struct pt_regs *regs)
-{
- return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0;
-}
-
-static inline long
-syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->r0;
-}
-
-static inline void
-syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
- int error, long val)
-{
- regs->r0 = error ? -error : val;
-}
-
-/**
- * syscall_get_arguments()
- * @task: unused
- * @regs: the register layout to extract syscall arguments from
- * @i: first syscall argument to extract
- * @n: number of syscall arguments to extract
- * @args: array to return the syscall arguments in
- *
- * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument
- */
-static inline void
-syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, unsigned long *args)
-{
- /*
- * Assume the ptrace layout doesn't change -- r5 is first in memory,
- * then r4, ..., then r0. So we simply reverse the ptrace register
- * array in memory to store into the args array.
- */
- long *aregs = &regs->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *args++ = *aregs--;
-}
-
-/* See syscall_get_arguments() comments */
-static inline void
-syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, const unsigned long *args)
-{
- long *aregs = &regs->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *aregs-- = *args++;
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
deleted file mode 100644
index a5aeab4e5f2d..000000000000
--- a/arch/blackfin/include/asm/thread_info.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-#include <asm/entry.h>
-#include <asm/l1layout.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-
-/* Thread Align Mask to reach to the top of the stack
- * for any process
- */
-#define ALIGN_PAGE_MASK 0xffffe000
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER 1
-#define THREAD_SIZE 8192 /* 2 pages */
-#define STACK_WARN (THREAD_SIZE/8)
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long mm_segment_t;
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- int cpu; /* cpu we're on */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- mm_segment_t addr_limit; /* address limit */
-#ifndef CONFIG_SMP
- struct l1_scratch_task_info l1_task_info;
-#endif
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
-}
-
-/* Given a task stack pointer, you can find its corresponding
- * thread_info structure just by masking it to the THREAD_SIZE
- * boundary (currently 8K as you can see above).
- */
-__attribute_const__
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- __asm__("%0 = sp;" : "=da"(ti));
- return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
-}
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_MEMDIE 4 /* is terminating due to OOM killer */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
-#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
-#define TIF_SINGLESTEP 9
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
deleted file mode 100644
index 9ca7db844d10..000000000000
--- a/arch/blackfin/include/asm/time.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * asm-blackfin/time.h:
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIME_H
-#define _ASM_BLACKFIN_TIME_H
-
-/*
- * The way that the Blackfin core timer works is:
- * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
- * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
- *
- * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
- * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
- * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
- * to use TSCALE, and program it to zero (which is pass CCLK through).
- * If you feel like using it, try to keep HZ * TIMESCALE to some
- * value that divides easy (like power of 2).
- */
-
-#ifndef CONFIG_CPU_FREQ
-# define TIME_SCALE 1
-#else
-/*
- * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
- * Whenever we change the Core Clock frequency changes we immediately
- * adjust the Core Timer Presale Register. This way we don't lose time.
- */
-#define TIME_SCALE 4
-
-# ifdef CONFIG_CYCLES_CLOCKSOURCE
-extern unsigned long long __bfin_cycles_off;
-extern unsigned int __bfin_cycles_mod;
-# endif
-#endif
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-extern void bfin_coretmr_init(void);
-extern void bfin_coretmr_clockevent_init(void);
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/timex.h b/arch/blackfin/include/asm/timex.h
deleted file mode 100644
index 248aeb066805..000000000000
--- a/arch/blackfin/include/asm/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * asm-blackfin/timex.h: cpu cycles!
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIMEX_H
-#define _ASM_BLACKFIN_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- unsigned long tmp, tmp2;
- __asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
- return tmp | ((cycles_t)tmp2 << 32);
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/tlb.h b/arch/blackfin/include/asm/tlb.h
deleted file mode 100644
index a74ae08af1a7..000000000000
--- a/arch/blackfin/include/asm/tlb.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TLB_H
-#define _BLACKFIN_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _BLACKFIN_TLB_H */
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
deleted file mode 100644
index 7c368682c0a3..000000000000
--- a/arch/blackfin/include/asm/tlbflush.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-generic/tlbflush.h>
-#define flush_tlb_kernel_range(s, e) do { } while (0)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
deleted file mode 100644
index 33589a29b8d8..000000000000
--- a/arch/blackfin/include/asm/trace.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * header file for hardware trace functions
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TRACE_
-#define _BLACKFIN_TRACE_
-
-/* Normally, we use ON, but you can't turn on software expansion until
- * interrupts subsystem is ready
- */
-
-#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
-#else
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT)
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long trace_buff_offset;
-extern unsigned long software_trace_buff[];
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void decode_address(char *buf, unsigned long address);
-extern bool get_instruction(unsigned int *val, unsigned short *address);
-#else
-static inline void decode_address(char *buf, unsigned long address) { }
-static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
-#endif
-
-/* Trace Macros for C files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
-
-#define trace_buffer_save(x) \
- do { \
- (x) = bfin_read_TBUFCTL(); \
- bfin_write_TBUFCTL((x) & ~TBUFEN); \
- } while (0)
-
-#define trace_buffer_restore(x) \
- do { \
- bfin_write_TBUFCTL((x)); \
- } while (0)
-#else /* DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_save(x)
-#define trace_buffer_restore(x)
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#else
-/* Trace Macros for Assembly files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_stop(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_init(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = BFIN_TRACE_INIT; \
- [preg] = dreg;
-
-#define trace_buffer_save(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [preg]; \
- [--sp] = dreg; \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_restore(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [sp++]; \
- [preg] = dreg;
-
-#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_init(preg, dreg)
-#define trace_buffer_save(preg, dreg)
-#define trace_buffer_restore(preg, dreg)
-
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
-#else
-# define DEBUG_HWTRACE_SAVE(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _BLACKFIN_TRACE_ */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
deleted file mode 100644
index cec771b8100c..000000000000
--- a/arch/blackfin/include/asm/traps.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2001 Lineo, Inc
- * Tony Kou
- * 1993 Hamish Macdonald
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR (63)
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2(level) \
- "System MMR Error\n" \
- level " - An error occurred due to an invalid access to an System MMR location\n" \
- level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
- level " or a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3(level) \
- "External Memory Addressing Error\n"
-#define EXC_0x04(level) \
- "Unimplmented exception occurred\n" \
- level " - Maybe you forgot to install a custom exception handler?\n"
-#define HWC_x12(level) \
- "Performance Monitor Overflow\n"
-#define HWC_x18(level) \
- "RAISE 5 instruction\n" \
- level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default(level) \
- "Reserved\n"
-#define EXC_0x03(level) \
- "Application stack overflow\n" \
- level " - Please increase the stack size of the application using elf2flt -s option,\n" \
- level " and/or reduce the stack use of the application.\n"
-#define EXC_0x10(level) \
- "Single step\n" \
- level " - When the processor is in single step mode, every instruction\n" \
- level " generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11(level) \
- "Exception caused by a trace buffer full condition\n" \
- level " - The processor takes this exception when the trace\n" \
- level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21(level) \
- "Undefined instruction\n" \
- level " - May be used to emulate instructions that are not defined for\n" \
- level " a particular processor implementation.\n"
-#define EXC_0x22(level) \
- "Illegal instruction combination\n" \
- level " - See section for multi-issue rules in the Blackfin\n" \
- level " Processor Instruction Set Reference.\n"
-#define EXC_0x23(level) \
- "Data access CPLB protection violation\n" \
- level " - Attempted read or write to Supervisor resource,\n" \
- level " or illegal data memory access. \n"
-#define EXC_0x24(level) \
- "Data access misaligned address violation\n" \
- level " - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25(level) \
- "Unrecoverable event\n" \
- level " - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26(level) \
- "Data access CPLB miss\n" \
- level " - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27(level) \
- "Data access multiple CPLB hits\n" \
- level " - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28(level) \
- "Program Sequencer Exception caused by an emulation watchpoint match\n" \
- level " - There is a watchpoint match, and one of the EMUSW\n" \
- level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A(level) \
- "Instruction fetch misaligned address violation\n" \
- level " - Attempted misaligned instruction cache fetch.\n"
-#define EXC_0x2B(level) \
- "CPLB protection violation\n" \
- level " - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C(level) \
- "Instruction fetch CPLB miss\n" \
- level " - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D(level) \
- "Instruction fetch multiple CPLB hits\n" \
- level " - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E(level) \
- "Illegal use of supervisor resource\n" \
- level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
- level " Supervisor resources are registers and instructions that are reserved\n" \
- level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
- level " only instructions.\n"
-
-extern void double_fault_c(struct pt_regs *fp);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
deleted file mode 100644
index 45da4bcb050e..000000000000
--- a/arch/blackfin/include/asm/uaccess.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Based on: include/asm-m68knommu/uaccess.h
- */
-
-#ifndef __BLACKFIN_UACCESS_H
-#define __BLACKFIN_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-#include <asm/sections.h>
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-
-static inline void set_fs(mm_segment_t fs)
-{
- current_thread_info()->addr_limit = fs;
-}
-
-#define segment_eq(a, b) ((a) == (b))
-
-#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- */
-
-#ifndef CONFIG_ACCESS_CHECK
-static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
-#else
-extern int _access_ok(unsigned long addr, unsigned long size);
-#endif
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, p) \
- ({ \
- int _err = 0; \
- typeof(*(p)) _x = (x); \
- typeof(*(p)) __user *_p = (p); \
- if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
- _err = -EFAULT; \
- } \
- else { \
- switch (sizeof (*(_p))) { \
- case 1: \
- __put_user_asm(_x, _p, B); \
- break; \
- case 2: \
- __put_user_asm(_x, _p, W); \
- break; \
- case 4: \
- __put_user_asm(_x, _p, ); \
- break; \
- case 8: { \
- long _xl, _xh; \
- _xl = ((__force long *)&_x)[0]; \
- _xh = ((__force long *)&_x)[1]; \
- __put_user_asm(_xl, ((__force long __user *)_p)+0, );\
- __put_user_asm(_xh, ((__force long __user *)_p)+1, );\
- } break; \
- default: \
- _err = __put_user_bad(); \
- break; \
- } \
- } \
- _err; \
- })
-
-#define __put_user(x, p) put_user(x, p)
-static inline int bad_user_access_length(void)
-{
- panic("bad_user_access_length");
- return -1;
-}
-
-#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
- __FILE__, __LINE__, __func__),\
- bad_user_access_length(), (-EFAULT))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long __force *)(x))
-
-#define __put_user_asm(x, p, bhw) \
- __asm__ (#bhw"[%1] = %0;\n\t" \
- : /* no outputs */ \
- :"d" (x), "a" (__ptr(p)) : "memory")
-
-#define get_user(x, ptr) \
-({ \
- int _err = 0; \
- unsigned long _val = 0; \
- const typeof(*(ptr)) __user *_p = (ptr); \
- const size_t ptr_size = sizeof(*(_p)); \
- if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \
- BUILD_BUG_ON(ptr_size >= 8); \
- switch (ptr_size) { \
- case 1: \
- __get_user_asm(_val, _p, B, (Z)); \
- break; \
- case 2: \
- __get_user_asm(_val, _p, W, (Z)); \
- break; \
- case 4: \
- __get_user_asm(_val, _p, , ); \
- break; \
- } \
- } else \
- _err = -EFAULT; \
- x = (__force typeof(*(ptr)))_val; \
- _err; \
-})
-
-#define __get_user(x, p) get_user(x, p)
-
-#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
-
-#define __get_user_asm(x, ptr, bhw, option) \
-({ \
- __asm__ __volatile__ ( \
- "%0 =" #bhw "[%1]" #option ";" \
- : "=d" (x) \
- : "a" (__ptr(ptr))); \
-})
-
-static inline unsigned long __must_check
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- memcpy(to, (const void __force *)from, n);
- return 0;
-}
-
-static inline unsigned long __must_check
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- memcpy((void __force *)to, from, n);
- SSYNC();
- return 0;
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long __must_check
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- char *tmp;
- if (!access_ok(VERIFY_READ, src, 1))
- return -EFAULT;
- strncpy(dst, (const char __force *)src, count);
- for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
- return (tmp - dst);
-}
-
-/*
- * Get the size of a string in user space.
- * src: The string to measure
- * n: The maximum valid length
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- * If the string is too long, returns a value greater than n.
- */
-static inline long __must_check strnlen_user(const char __user *src, long n)
-{
- if (!access_ok(VERIFY_READ, src, 1))
- return 0;
- return strnlen((const char __force *)src, n) + 1;
-}
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long __must_check
-__clear_user(void __user *to, unsigned long n)
-{
- if (!access_ok(VERIFY_WRITE, to, n))
- return n;
- memset((void __force *)to, 0, n);
- return 0;
-}
-
-#define clear_user(to, n) __clear_user(to, n)
-
-/* How to interpret these return values:
- * CORE: can be accessed by core load or dma memcpy
- * CORE_ONLY: can only be accessed by core load
- * DMA: can only be accessed by dma memcpy
- * IDMA: can only be accessed by interprocessor dma memcpy (BF561)
- * ITEST: can be accessed by isram memcpy or dma memcpy
- */
-enum {
- BFIN_MEM_ACCESS_CORE = 0,
- BFIN_MEM_ACCESS_CORE_ONLY,
- BFIN_MEM_ACCESS_DMA,
- BFIN_MEM_ACCESS_IDMA,
- BFIN_MEM_ACCESS_ITEST,
-};
-/**
- * bfin_mem_access_type() - what kind of memory access is required
- * @addr: the address to check
- * @size: number of bytes needed
- * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
- */
-int bfin_mem_access_type(unsigned long addr, unsigned long size);
-
-#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
deleted file mode 100644
index c8c8ff9eff61..000000000000
--- a/arch/blackfin/include/asm/unistd.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __ASM_BFIN_UNISTD_H
-#define __ASM_BFIN_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_VFORK
-
-#endif /* __ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/include/asm/vga.h b/arch/blackfin/include/asm/vga.h
deleted file mode 100644
index 89d82fd8fcf1..000000000000
--- a/arch/blackfin/include/asm/vga.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/vga.h>
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
deleted file mode 100644
index af9fc8171ebc..000000000000
--- a/arch/blackfin/include/mach-common/irq.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Common Blackfin IRQ definitions (i.e. the CEC)
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_COMMON_IRQ_H_
-#define _MACH_COMMON_IRQ_H_
-
-/*
- * Core events interrupt source definitions
- *
- * Event Source Event Name
- * Emulation EMU 0 (highest priority)
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * Peripherals IVG7 7
- * Peripherals IVG8 8
- * Peripherals IVG9 9
- * Peripherals IVG10 10
- * Peripherals IVG11 11
- * Peripherals IVG12 12
- * Peripherals IVG13 13
- * Softirq IVG14 14
- * System Call IVG15 15 (lowest priority)
- */
-
-/* The ABSTRACT IRQ definitions */
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-#define BFIN_IRQ(x) ((x) + IVG7)
-#define BFIN_SYSIRQ(x) ((x) - IVG7)
-
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
deleted file mode 100644
index 382178b361af..000000000000
--- a/arch/blackfin/include/mach-common/pll.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_COMMON_PLL_H
-#define _MACH_COMMON_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-#ifndef bfin_iwr_restore
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
-#ifdef SIC_IWR
- bfin_write_SIC_IWR(iwr0);
-#else
- bfin_write_SIC_IWR0(iwr0);
-# ifdef SIC_IWR1
- bfin_write_SIC_IWR1(iwr1);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(iwr2);
-# endif
-#endif
-}
-#endif
-
-#ifndef bfin_iwr_save
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
-#ifdef SIC_IWR
- *iwr0 = bfin_read_SIC_IWR();
-#else
- *iwr0 = bfin_read_SIC_IWR0();
-# ifdef SIC_IWR1
- *iwr1 = bfin_read_SIC_IWR1();
-# endif
-# ifdef SIC_IWR2
- *iwr2 = bfin_read_SIC_IWR2();
-# endif
-#endif
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#endif
-
-static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
-{
- unsigned long flags, iwr0, iwr1, iwr2;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- flags = hard_local_irq_save();
- /* Enable the PLL Wakeup bit in SIC IWR */
- bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
-
- bfin_write16(addr, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_iwr_restore(iwr0, iwr1, iwr2);
- hard_local_irq_restore(flags);
-}
-
-/* Writing to PLL_CTL initiates a PLL relock sequence */
-static inline void bfin_write_PLL_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(PLL_CTL, val);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence */
-static inline void bfin_write_VR_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(VR_CTL, val);
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
deleted file mode 100644
index 71bcd74f83fd..000000000000
--- a/arch/blackfin/include/mach-common/ports-a.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port A Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_A__
-#define __BFIN_PERIPHERAL_PORT_A__
-
-#define PA0 (1 << 0)
-#define PA1 (1 << 1)
-#define PA2 (1 << 2)
-#define PA3 (1 << 3)
-#define PA4 (1 << 4)
-#define PA5 (1 << 5)
-#define PA6 (1 << 6)
-#define PA7 (1 << 7)
-#define PA8 (1 << 8)
-#define PA9 (1 << 9)
-#define PA10 (1 << 10)
-#define PA11 (1 << 11)
-#define PA12 (1 << 12)
-#define PA13 (1 << 13)
-#define PA14 (1 << 14)
-#define PA15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
deleted file mode 100644
index 8013cc8e839b..000000000000
--- a/arch/blackfin/include/mach-common/ports-b.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port B Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_B__
-#define __BFIN_PERIPHERAL_PORT_B__
-
-#define PB0 (1 << 0)
-#define PB1 (1 << 1)
-#define PB2 (1 << 2)
-#define PB3 (1 << 3)
-#define PB4 (1 << 4)
-#define PB5 (1 << 5)
-#define PB6 (1 << 6)
-#define PB7 (1 << 7)
-#define PB8 (1 << 8)
-#define PB9 (1 << 9)
-#define PB10 (1 << 10)
-#define PB11 (1 << 11)
-#define PB12 (1 << 12)
-#define PB13 (1 << 13)
-#define PB14 (1 << 14)
-#define PB15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
deleted file mode 100644
index 94e71010ffe9..000000000000
--- a/arch/blackfin/include/mach-common/ports-c.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port C Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_C__
-#define __BFIN_PERIPHERAL_PORT_C__
-
-#define PC0 (1 << 0)
-#define PC1 (1 << 1)
-#define PC2 (1 << 2)
-#define PC3 (1 << 3)
-#define PC4 (1 << 4)
-#define PC5 (1 << 5)
-#define PC6 (1 << 6)
-#define PC7 (1 << 7)
-#define PC8 (1 << 8)
-#define PC9 (1 << 9)
-#define PC10 (1 << 10)
-#define PC11 (1 << 11)
-#define PC12 (1 << 12)
-#define PC13 (1 << 13)
-#define PC14 (1 << 14)
-#define PC15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
deleted file mode 100644
index ba84a9fb3450..000000000000
--- a/arch/blackfin/include/mach-common/ports-d.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port D Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_D__
-#define __BFIN_PERIPHERAL_PORT_D__
-
-#define PD0 (1 << 0)
-#define PD1 (1 << 1)
-#define PD2 (1 << 2)
-#define PD3 (1 << 3)
-#define PD4 (1 << 4)
-#define PD5 (1 << 5)
-#define PD6 (1 << 6)
-#define PD7 (1 << 7)
-#define PD8 (1 << 8)
-#define PD9 (1 << 9)
-#define PD10 (1 << 10)
-#define PD11 (1 << 11)
-#define PD12 (1 << 12)
-#define PD13 (1 << 13)
-#define PD14 (1 << 14)
-#define PD15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
deleted file mode 100644
index 2264fb58bc2b..000000000000
--- a/arch/blackfin/include/mach-common/ports-e.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port E Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_E__
-#define __BFIN_PERIPHERAL_PORT_E__
-
-#define PE0 (1 << 0)
-#define PE1 (1 << 1)
-#define PE2 (1 << 2)
-#define PE3 (1 << 3)
-#define PE4 (1 << 4)
-#define PE5 (1 << 5)
-#define PE6 (1 << 6)
-#define PE7 (1 << 7)
-#define PE8 (1 << 8)
-#define PE9 (1 << 9)
-#define PE10 (1 << 10)
-#define PE11 (1 << 11)
-#define PE12 (1 << 12)
-#define PE13 (1 << 13)
-#define PE14 (1 << 14)
-#define PE15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
deleted file mode 100644
index 2b8ca3ae2a8e..000000000000
--- a/arch/blackfin/include/mach-common/ports-f.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port F Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_F__
-#define __BFIN_PERIPHERAL_PORT_F__
-
-#define PF0 (1 << 0)
-#define PF1 (1 << 1)
-#define PF2 (1 << 2)
-#define PF3 (1 << 3)
-#define PF4 (1 << 4)
-#define PF5 (1 << 5)
-#define PF6 (1 << 6)
-#define PF7 (1 << 7)
-#define PF8 (1 << 8)
-#define PF9 (1 << 9)
-#define PF10 (1 << 10)
-#define PF11 (1 << 11)
-#define PF12 (1 << 12)
-#define PF13 (1 << 13)
-#define PF14 (1 << 14)
-#define PF15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
deleted file mode 100644
index 11ad917fcf91..000000000000
--- a/arch/blackfin/include/mach-common/ports-g.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port G Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_G__
-#define __BFIN_PERIPHERAL_PORT_G__
-
-#define PG0 (1 << 0)
-#define PG1 (1 << 1)
-#define PG2 (1 << 2)
-#define PG3 (1 << 3)
-#define PG4 (1 << 4)
-#define PG5 (1 << 5)
-#define PG6 (1 << 6)
-#define PG7 (1 << 7)
-#define PG8 (1 << 8)
-#define PG9 (1 << 9)
-#define PG10 (1 << 10)
-#define PG11 (1 << 11)
-#define PG12 (1 << 12)
-#define PG13 (1 << 13)
-#define PG14 (1 << 14)
-#define PG15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
deleted file mode 100644
index 511d088b8094..000000000000
--- a/arch/blackfin/include/mach-common/ports-h.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port H Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_H__
-#define __BFIN_PERIPHERAL_PORT_H__
-
-#define PH0 (1 << 0)
-#define PH1 (1 << 1)
-#define PH2 (1 << 2)
-#define PH3 (1 << 3)
-#define PH4 (1 << 4)
-#define PH5 (1 << 5)
-#define PH6 (1 << 6)
-#define PH7 (1 << 7)
-#define PH8 (1 << 8)
-#define PH9 (1 << 9)
-#define PH10 (1 << 10)
-#define PH11 (1 << 11)
-#define PH12 (1 << 12)
-#define PH13 (1 << 13)
-#define PH14 (1 << 14)
-#define PH15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
deleted file mode 100644
index 21bbab166ae8..000000000000
--- a/arch/blackfin/include/mach-common/ports-i.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port I Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_I__
-#define __BFIN_PERIPHERAL_PORT_I__
-
-#define PI0 (1 << 0)
-#define PI1 (1 << 1)
-#define PI2 (1 << 2)
-#define PI3 (1 << 3)
-#define PI4 (1 << 4)
-#define PI5 (1 << 5)
-#define PI6 (1 << 6)
-#define PI7 (1 << 7)
-#define PI8 (1 << 8)
-#define PI9 (1 << 9)
-#define PI10 (1 << 10)
-#define PI11 (1 << 11)
-#define PI12 (1 << 12)
-#define PI13 (1 << 13)
-#define PI14 (1 << 14)
-#define PI15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
deleted file mode 100644
index 96a252b0b0bd..000000000000
--- a/arch/blackfin/include/mach-common/ports-j.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port J Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_J__
-#define __BFIN_PERIPHERAL_PORT_J__
-
-#define PJ0 (1 << 0)
-#define PJ1 (1 << 1)
-#define PJ2 (1 << 2)
-#define PJ3 (1 << 3)
-#define PJ4 (1 << 4)
-#define PJ5 (1 << 5)
-#define PJ6 (1 << 6)
-#define PJ7 (1 << 7)
-#define PJ8 (1 << 8)
-#define PJ9 (1 << 9)
-#define PJ10 (1 << 10)
-#define PJ11 (1 << 11)
-#define PJ12 (1 << 12)
-#define PJ13 (1 << 13)
-#define PJ14 (1 << 14)
-#define PJ15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild
deleted file mode 100644
index 2240b38c2915..000000000000
--- a/arch/blackfin/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,25 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += auxvec.h
-generic-y += bitsperlong.h
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += ioctl.h
-generic-y += ipcbuf.h
-generic-y += kvm_para.h
-generic-y += mman.h
-generic-y += msgbuf.h
-generic-y += param.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += setup.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += termbits.h
-generic-y += termios.h
-generic-y += types.h
-generic-y += ucontext.h
diff --git a/arch/blackfin/include/uapi/asm/bfin_sport.h b/arch/blackfin/include/uapi/asm/bfin_sport.h
deleted file mode 100644
index 86c36a208dc5..000000000000
--- a/arch/blackfin/include/uapi/asm/bfin_sport.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_SPORT_H__
-#define _UAPI__BFIN_SPORT_H__
-
-/* Sport mode: it can be set to TDM, i2s or others */
-#define NORM_MODE 0x0
-#define TDM_MODE 0x1
-#define I2S_MODE 0x2
-#define NDSO_MODE 0x3
-
-/* Data format, normal, a-law or u-law */
-#define NORM_FORMAT 0x0
-#define ALAW_FORMAT 0x2
-#define ULAW_FORMAT 0x3
-
-/* Function driver which use sport must initialize the structure */
-struct sport_config {
- /* TDM (multichannels), I2S or other mode */
- unsigned int mode:3;
- unsigned int polled; /* use poll instead of irq when set */
-
- /* if TDM mode is selected, channels must be set */
- int channels; /* Must be in 8 units */
- unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
-
- /* I2S mode */
- unsigned int right_first:1; /* Right stereo channel first */
-
- /* In mormal mode, the following item need to be set */
- unsigned int lsb_first:1; /* order of transmit or receive data */
- unsigned int fsync:1; /* Frame sync required */
- unsigned int data_indep:1; /* data independent frame sync generated */
- unsigned int act_low:1; /* Active low TFS */
- unsigned int late_fsync:1; /* Late frame sync */
- unsigned int tckfe:1;
- unsigned int sec_en:1; /* Secondary side enabled */
-
- /* Choose clock source */
- unsigned int int_clk:1; /* Internal or external clock */
-
- /* If external clock is used, the following fields are ignored */
- int serial_clk;
- int fsync_clk;
-
- unsigned int data_format:2; /* Normal, u-law or a-law */
-
- int word_len; /* How length of the word in bits, 3-32 bits */
- int dma_enabled;
-};
-
-/* Userspace interface */
-#define SPORT_IOC_MAGIC 'P'
-#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
-#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long)
-#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long)
-
-
-/* SPORT_TCR1 Masks */
-#define TSPEN 0x0001 /* TX enable */
-#define ITCLK 0x0002 /* Internal TX Clock Select */
-#define TDTYPE 0x000C /* TX Data Formatting Select */
-#define DTYPE_NORM 0x0000 /* Data Format Normal */
-#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
-#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
-#define TLSBIT 0x0010 /* TX Bit Order */
-#define ITFS 0x0200 /* Internal TX Frame Sync Select */
-#define TFSR 0x0400 /* TX Frame Sync Required Select */
-#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
-#define LTFS 0x1000 /* Low TX Frame Sync Select */
-#define LATFS 0x2000 /* Late TX Frame Sync Select */
-#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
-
-/* SPORT_TCR2 Masks */
-#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
-#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
-#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
-#define TXSE 0x0100 /* TX Secondary Enable */
-#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
-#define TRFST 0x0400 /* TX Right-First Data Order */
-
-/* SPORT_RCR1 Masks */
-#define RSPEN 0x0001 /* RX enable */
-#define IRCLK 0x0002 /* Internal RX Clock Select */
-#define RDTYPE 0x000C /* RX Data Formatting Select */
-/* DTYPE_* defined above */
-#define RLSBIT 0x0010 /* RX Bit Order */
-#define IRFS 0x0200 /* Internal RX Frame Sync Select */
-#define RFSR 0x0400 /* RX Frame Sync Required Select */
-#define LRFS 0x1000 /* Low RX Frame Sync Select */
-#define LARFS 0x2000 /* Late RX Frame Sync Select */
-#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
-
-/* SPORT_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE 0x0100 /* RX Secondary Enable */
-#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
-#define RRFST 0x0400 /* Right-First Data Order */
-
-/* SPORT_STAT Masks */
-#define RXNE 0x0001 /* RX FIFO Not Empty Status */
-#define RUVF 0x0002 /* RX Underflow Status */
-#define ROVF 0x0004 /* RX Overflow Status */
-#define TXF 0x0008 /* TX FIFO Full Status */
-#define TUVF 0x0010 /* TX Underflow Status */
-#define TOVF 0x0020 /* TX Overflow Status */
-#define TXHRE 0x0040 /* TX Hold Register Empty */
-
-/* SPORT_MCMC1 Masks */
-#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
-#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
-#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
-#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
-#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
-#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
-
-/* SPORT_MCMC2 Masks */
-#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
-#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
-#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
-#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
-#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
-#define MFD 0xF000 /* Multichannel Frame Delay */
-#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
-#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
-
-#endif /* _UAPI__BFIN_SPORT_H__ */
diff --git a/arch/blackfin/include/uapi/asm/byteorder.h b/arch/blackfin/include/uapi/asm/byteorder.h
deleted file mode 100644
index bcab6670c7fe..000000000000
--- a/arch/blackfin/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__BFIN_ASM_BYTEORDER_H
-#define _UAPI__BFIN_ASM_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */
diff --git a/arch/blackfin/include/uapi/asm/cachectl.h b/arch/blackfin/include/uapi/asm/cachectl.h
deleted file mode 100644
index b5c86fbbca94..000000000000
--- a/arch/blackfin/include/uapi/asm/cachectl.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * based on the mips/cachectl.h
- *
- * Copyright 2010 Analog Devices Inc.
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_CACHECTL
-#define _UAPI_ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-#endif /* _UAPI_ASM_CACHECTL */
diff --git a/arch/blackfin/include/uapi/asm/fcntl.h b/arch/blackfin/include/uapi/asm/fcntl.h
deleted file mode 100644
index 0b02954f06c3..000000000000
--- a/arch/blackfin/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_FCNTL_H
-#define _UAPI_BFIN_FCNTL_H
-
-#define O_DIRECTORY 040000 /* must be a directory */
-#define O_NOFOLLOW 0100000 /* don't follow links */
-#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE 0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _UAPI_BFIN_FCNTL_H */
diff --git a/arch/blackfin/include/uapi/asm/fixed_code.h b/arch/blackfin/include/uapi/asm/fixed_code.h
deleted file mode 100644
index 707b9214bb26..000000000000
--- a/arch/blackfin/include/uapi/asm/fixed_code.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_ASM_FIXED_CODE_H__
-#define _UAPI__BFIN_ASM_FIXED_CODE_H__
-
-
-#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
-#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
-#endif
-
-#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-
-#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
-#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
-#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
-#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
-#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
-#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
-
-#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
-
-#endif /* _UAPI__BFIN_ASM_FIXED_CODE_H__ */
diff --git a/arch/blackfin/include/uapi/asm/ioctls.h b/arch/blackfin/include/uapi/asm/ioctls.h
deleted file mode 100644
index 422fee3e4776..000000000000
--- a/arch/blackfin/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__
-#define _UAPI__ARCH_BFIN_IOCTLS_H__
-
-#define FIOQSIZE 0x545E
-#include <asm-generic/ioctls.h>
-
-#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */
diff --git a/arch/blackfin/include/uapi/asm/poll.h b/arch/blackfin/include/uapi/asm/poll.h
deleted file mode 100644
index cd2f1a78aba5..000000000000
--- a/arch/blackfin/include/uapi/asm/poll.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#ifndef _UAPI__BFIN_POLL_H
-#define _UAPI__BFIN_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-
-#include <asm-generic/poll.h>
-
-#endif /* _UAPI__BFIN_POLL_H */
diff --git a/arch/blackfin/include/uapi/asm/posix_types.h b/arch/blackfin/include/uapi/asm/posix_types.h
deleted file mode 100644
index 8947c75cf638..000000000000
--- a/arch/blackfin/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H
-#define _UAPI__ARCH_BFIN_POSIX_TYPES_H
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned int __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-#define __kernel_size_t __kernel_size_t
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-#define __kernel_old_uid_t __kernel_old_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */
diff --git a/arch/blackfin/include/uapi/asm/ptrace.h b/arch/blackfin/include/uapi/asm/ptrace.h
deleted file mode 100644
index e4423d5560da..000000000000
--- a/arch/blackfin/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_PTRACE_H
-#define _UAPI_BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- * 0 - 7 are data registers R0-R7
- * 8 - 15 are address registers P0-P7
- * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- * 32 - 33 A registers A0 & A1
- * 34 - status register
- * -----------------------------
- *
- * We follows above, except:
- * 32-33 --- Low 32-bit of A0&1
- * 34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct pt_regs {
- long orig_pc;
- long ipend;
- long seqstat;
- long rete;
- long retn;
- long retx;
- long pc; /* PC == RETI */
- long rets;
- long reserved; /* Used as scratch during system calls */
- long astat;
- long lb1;
- long lb0;
- long lt1;
- long lt0;
- long lc1;
- long lc0;
- long a1w;
- long a1x;
- long a0w;
- long a0x;
- long b3;
- long b2;
- long b1;
- long b0;
- long l3;
- long l2;
- long l1;
- long l0;
- long m3;
- long m2;
- long m1;
- long m0;
- long i3;
- long i2;
- long i1;
- long i0;
- long usp;
- long fp;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- long r4;
- long r3;
- long r2;
- long r1;
- long r0;
- long orig_r0;
- long orig_p0;
- long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
-
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#define PS_S (0x0002)
-
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_ORIG_R0 208
-#define PT_ORIG_P0 212
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#define PT_LAST_PSEUDO PT_FDPIC_INTERP
-
-#endif /* _UAPI_BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/uapi/asm/sigcontext.h b/arch/blackfin/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 66b4d32af89c..000000000000
--- a/arch/blackfin/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-
-/* Add new entries at the end of the structure only. */
-struct sigcontext {
- unsigned long sc_r0;
- unsigned long sc_r1;
- unsigned long sc_r2;
- unsigned long sc_r3;
- unsigned long sc_r4;
- unsigned long sc_r5;
- unsigned long sc_r6;
- unsigned long sc_r7;
- unsigned long sc_p0;
- unsigned long sc_p1;
- unsigned long sc_p2;
- unsigned long sc_p3;
- unsigned long sc_p4;
- unsigned long sc_p5;
- unsigned long sc_usp;
- unsigned long sc_a0w;
- unsigned long sc_a1w;
- unsigned long sc_a0x;
- unsigned long sc_a1x;
- unsigned long sc_astat;
- unsigned long sc_rets;
- unsigned long sc_pc;
- unsigned long sc_retx;
- unsigned long sc_fp;
- unsigned long sc_i0;
- unsigned long sc_i1;
- unsigned long sc_i2;
- unsigned long sc_i3;
- unsigned long sc_m0;
- unsigned long sc_m1;
- unsigned long sc_m2;
- unsigned long sc_m3;
- unsigned long sc_l0;
- unsigned long sc_l1;
- unsigned long sc_l2;
- unsigned long sc_l3;
- unsigned long sc_b0;
- unsigned long sc_b1;
- unsigned long sc_b2;
- unsigned long sc_b3;
- unsigned long sc_lc0;
- unsigned long sc_lc1;
- unsigned long sc_lt0;
- unsigned long sc_lt1;
- unsigned long sc_lb0;
- unsigned long sc_lb1;
- unsigned long sc_seqstat;
-};
-
-#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */
diff --git a/arch/blackfin/include/uapi/asm/siginfo.h b/arch/blackfin/include/uapi/asm/siginfo.h
deleted file mode 100644
index 2dd8c9c39248..000000000000
--- a/arch/blackfin/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_SIGINFO_H
-#define _UAPI_BFIN_SIGINFO_H
-
-#include <linux/types.h>
-#include <asm-generic/siginfo.h>
-
-#define si_uid16 _sifields._kill._uid
-
-#endif /* _UAPI_BFIN_SIGINFO_H */
diff --git a/arch/blackfin/include/uapi/asm/signal.h b/arch/blackfin/include/uapi/asm/signal.h
deleted file mode 100644
index f8e3b99ba0a2..000000000000
--- a/arch/blackfin/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_BLACKFIN_SIGNAL_H
-#define _UAPI_BLACKFIN_SIGNAL_H
-
-#define SA_RESTORER 0x04000000
-#include <asm-generic/signal.h>
-
-#endif /* _UAPI_BLACKFIN_SIGNAL_H */
diff --git a/arch/blackfin/include/uapi/asm/stat.h b/arch/blackfin/include/uapi/asm/stat.h
deleted file mode 100644
index 458959d1a5ec..000000000000
--- a/arch/blackfin/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _UAPI_BFIN_STAT_H
-#define _UAPI_BFIN_STAT_H
-
-struct stat {
- unsigned short st_dev;
- unsigned short __pad1;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned short __pad2;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long __unused1;
- unsigned long st_mtime;
- unsigned long __unused2;
- unsigned long st_ctime;
- unsigned long __unused3;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad1[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad2[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- long long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#endif /* _UAPI_BFIN_STAT_H */
diff --git a/arch/blackfin/include/uapi/asm/swab.h b/arch/blackfin/include/uapi/asm/swab.h
deleted file mode 100644
index d3437933b95f..000000000000
--- a/arch/blackfin/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BLACKFIN_SWAB_H
-#define _UAPI_BLACKFIN_SWAB_H
-
-#include <linux/types.h>
-#include <asm-generic/swab.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx)
-{
- __u32 tmp;
- __asm__("%1 = %0 >> 8 (V);\n\t"
- "%0 = %0 << 8 (V);\n\t"
- "%0 = %0 | %1;\n\t"
- : "+d"(xx), "=&d"(tmp));
- return xx;
-}
-#define __arch_swahb32 __arch_swahb32
-
-static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx)
-{
- __u32 rv;
- __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
- return rv;
-}
-#define __arch_swahw32 __arch_swahw32
-
-static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx)
-{
- return __arch_swahb32(__arch_swahw32(xx));
-}
-#define __arch_swab32 __arch_swab32
-
-static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx)
-{
- __u32 xw = xx;
- __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
- return (__u16)xw;
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* __GNUC__ */
-
-#endif /* _UAPI_BLACKFIN_SWAB_H */
diff --git a/arch/blackfin/include/uapi/asm/unistd.h b/arch/blackfin/include/uapi/asm/unistd.h
deleted file mode 100644
index 2d392c09323c..000000000000
--- a/arch/blackfin/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ASM_BFIN_UNISTD_H
-#define _UAPI__ASM_BFIN_UNISTD_H
-/*
- * This file contains the system call numbers.
- */
-#define __NR_restart_syscall 0
-#define __NR_exit 1
- /* 2 __NR_fork not supported on nommu */
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
- /* 7 __NR_waitpid obsolete */
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_chown 16
- /* 17 __NR_break obsolete */
- /* 18 __NR_oldstat obsolete */
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
- /* 22 __NR_umount obsolete */
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
- /* 28 __NR_oldfstat obsolete */
-#define __NR_pause 29
- /* 30 __NR_utime obsolete */
- /* 31 __NR_stty obsolete */
- /* 32 __NR_gtty obsolete */
-#define __NR_access 33
-#define __NR_nice 34
- /* 35 __NR_ftime obsolete */
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
- /* 44 __NR_prof obsolete */
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
- /* 48 __NR_signal obsolete */
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
- /* 53 __NR_lock obsolete */
-#define __NR_ioctl 54
-#define __NR_fcntl 55
- /* 56 __NR_mpx obsolete */
-#define __NR_setpgid 57
- /* 58 __NR_ulimit obsolete */
- /* 59 __NR_oldolduname obsolete */
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
- /* 67 __NR_sigaction obsolete */
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
- /* 72 __NR_sigsuspend obsolete */
- /* 73 __NR_sigpending obsolete */
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
- /* 76 __NR_old_getrlimit obsolete */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
- /* 82 __NR_select obsolete */
-#define __NR_symlink 83
- /* 84 __NR_oldlstat obsolete */
-#define __NR_readlink 85
- /* 86 __NR_uselib obsolete */
- /* 87 __NR_swapon obsolete */
-#define __NR_reboot 88
- /* 89 __NR_readdir obsolete */
- /* 90 __NR_mmap obsolete */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
- /* 98 __NR_profil obsolete */
-#define __NR_statfs 99
-#define __NR_fstatfs 100
- /* 101 __NR_ioperm */
- /* 102 __NR_socketcall obsolete */
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
- /* 109 __NR_olduname obsolete */
- /* 110 __NR_iopl obsolete */
-#define __NR_vhangup 111
- /* 112 __NR_idle obsolete */
- /* 113 __NR_vm86old */
-#define __NR_wait4 114
- /* 115 __NR_swapoff obsolete */
-#define __NR_sysinfo 116
- /* 117 __NR_ipc oboslete */
-#define __NR_fsync 118
- /* 119 __NR_sigreturn obsolete */
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
- /* 123 __NR_modify_ldt obsolete */
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
- /* 126 __NR_sigprocmask obsolete */
- /* 127 __NR_create_module obsolete */
-#define __NR_init_module 128
-#define __NR_delete_module 129
- /* 130 __NR_get_kernel_syms obsolete */
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
- /* 135 was sysfs */
-#define __NR_personality 136
- /* 137 __NR_afs_syscall */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
- /* 142 __NR__newselect obsolete */
-#define __NR_flock 143
- /* 144 __NR_msync obsolete */
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
- /* 150 __NR_mlock */
- /* 151 __NR_munlock */
- /* 152 __NR_mlockall */
- /* 153 __NR_munlockall */
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
- /* 166 __NR_vm86 */
- /* 167 __NR_query_module */
- /* 168 __NR_poll */
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread 180
-#define __NR_pwrite 181
-#define __NR_lchown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
- /* 188 __NR_getpmsg */
- /* 189 __NR_putpmsg */
-#define __NR_vfork 190
-#define __NR_getrlimit 191
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_chown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_lchown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
- /* 218 __NR_mincore */
- /* 219 __NR_madvise */
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
- /* 222 reserved for TUX */
- /* 223 reserved for TUX */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
- /* 243 __NR_set_thread_area */
- /* 244 __NR_get_thread_area */
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
- /* 250 __NR_alloc_hugepages */
- /* 251 __NR_free_hugepages */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_bfin_spinlock 254
-
-#define __NR_epoll_create 255
-#define __NR_epoll_ctl 256
-#define __NR_epoll_wait 257
- /* 258 __NR_remap_file_pages */
-#define __NR_set_tid_address 259
-#define __NR_timer_create 260
-#define __NR_timer_settime 261
-#define __NR_timer_gettime 262
-#define __NR_timer_getoverrun 263
-#define __NR_timer_delete 264
-#define __NR_clock_settime 265
-#define __NR_clock_gettime 266
-#define __NR_clock_getres 267
-#define __NR_clock_nanosleep 268
-#define __NR_statfs64 269
-#define __NR_fstatfs64 270
-#define __NR_tgkill 271
-#define __NR_utimes 272
-#define __NR_fadvise64_64 273
- /* 274 __NR_vserver */
- /* 275 __NR_mbind */
- /* 276 __NR_get_mempolicy */
- /* 277 __NR_set_mempolicy */
-#define __NR_mq_open 278
-#define __NR_mq_unlink 279
-#define __NR_mq_timedsend 280
-#define __NR_mq_timedreceive 281
-#define __NR_mq_notify 282
-#define __NR_mq_getsetattr 283
-#define __NR_kexec_load 284
-#define __NR_waitid 285
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
- /* 294 __NR_migrate_pages */
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-
-/* Blackfin private syscalls */
-#define __NR_sram_alloc 311
-#define __NR_sram_free 312
-#define __NR_dma_memcpy 313
-
-/* socket syscalls */
-#define __NR_accept 314
-#define __NR_bind 315
-#define __NR_connect 316
-#define __NR_getpeername 317
-#define __NR_getsockname 318
-#define __NR_getsockopt 319
-#define __NR_listen 320
-#define __NR_recv 321
-#define __NR_recvfrom 322
-#define __NR_recvmsg 323
-#define __NR_send 324
-#define __NR_sendmsg 325
-#define __NR_sendto 326
-#define __NR_setsockopt 327
-#define __NR_shutdown 328
-#define __NR_socket 329
-#define __NR_socketpair 330
-
-/* sysv ipc syscalls */
-#define __NR_semctl 331
-#define __NR_semget 332
-#define __NR_semop 333
-#define __NR_msgctl 334
-#define __NR_msgget 335
-#define __NR_msgrcv 336
-#define __NR_msgsnd 337
-#define __NR_shmat 338
-#define __NR_shmctl 339
-#define __NR_shmdt 340
-#define __NR_shmget 341
-
-#define __NR_splice 342
-#define __NR_sync_file_range 343
-#define __NR_tee 344
-#define __NR_vmsplice 345
-
-#define __NR_epoll_pwait 346
-#define __NR_utimensat 347
-#define __NR_signalfd 348
-#define __NR_timerfd_create 349
-#define __NR_eventfd 350
-#define __NR_pread64 351
-#define __NR_pwrite64 352
-#define __NR_fadvise64 353
-#define __NR_set_robust_list 354
-#define __NR_get_robust_list 355
-#define __NR_fallocate 356
-#define __NR_semtimedop 357
-#define __NR_timerfd_settime 358
-#define __NR_timerfd_gettime 359
-#define __NR_signalfd4 360
-#define __NR_eventfd2 361
-#define __NR_epoll_create1 362
-#define __NR_dup3 363
-#define __NR_pipe2 364
-#define __NR_inotify_init1 365
-#define __NR_preadv 366
-#define __NR_pwritev 367
-#define __NR_rt_tgsigqueueinfo 368
-#define __NR_perf_event_open 369
-#define __NR_recvmmsg 370
-#define __NR_fanotify_init 371
-#define __NR_fanotify_mark 372
-#define __NR_prlimit64 373
-#define __NR_cacheflush 374
-#define __NR_name_to_handle_at 375
-#define __NR_open_by_handle_at 376
-#define __NR_clock_adjtime 377
-#define __NR_syncfs 378
-#define __NR_setns 379
-#define __NR_sendmmsg 380
-#define __NR_process_vm_readv 381
-#define __NR_process_vm_writev 382
-#define __NR_kcmp 383
-#define __NR_finit_module 384
-#define __NR_sched_setattr 385
-#define __NR_sched_getattr 386
-#define __NR_renameat2 387
-#define __NR_seccomp 388
-#define __NR_getrandom 389
-#define __NR_memfd_create 390
-#define __NR_bpf 391
-#define __NR_execveat 392
-
-#define __NR_syscall 393 /* For internal using, not implemented */
-#define NR_syscalls __NR_syscall
-
-/* Old optional stuff no one actually uses */
-#define __IGNORE_sysfs
-#define __IGNORE_uselib
-
-/* Implement the newer interfaces */
-#define __IGNORE_mmap
-#define __IGNORE_poll
-#define __IGNORE_select
-#define __IGNORE_utime
-
-/* Not relevant on no-mmu */
-#define __IGNORE_swapon
-#define __IGNORE_swapoff
-#define __IGNORE_msync
-#define __IGNORE_mlock
-#define __IGNORE_munlock
-#define __IGNORE_mlockall
-#define __IGNORE_munlockall
-#define __IGNORE_mincore
-#define __IGNORE_madvise
-#define __IGNORE_remap_file_pages
-#define __IGNORE_mbind
-#define __IGNORE_get_mempolicy
-#define __IGNORE_set_mempolicy
-#define __IGNORE_migrate_pages
-#define __IGNORE_move_pages
-#define __IGNORE_getcpu
-
-
-#endif /* _UAPI__ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/kernel/.gitignore b/arch/blackfin/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/blackfin/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
deleted file mode 100644
index 1580791f0e3a..000000000000
--- a/arch/blackfin/kernel/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/Makefile
-#
-
-extra-y := vmlinux.lds
-
-obj-y := \
- entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
- sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o reboot.o bfin_dma.o \
- exception.o dumpstack.o
-
-ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
- obj-y += time-ts.o
-else
- obj-y += time.o
-endif
-
-obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
-obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
-obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
-obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
-CFLAGS_REMOVE_ftrace.o = -pg
-
-obj-$(CONFIG_IPIPE) += ipipe.o
-obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_KGDB) += kgdb.o
-obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
-obj-$(CONFIG_NMI_WATCHDOG) += nmi.o
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
-obj-$(CONFIG_STACKTRACE) += stacktrace.o
-obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
-obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
-obj-$(CONFIG_PERF_EVENTS) += perf_event.o
-
-# the kgdb test puts code into L2 and without linker
-# relaxation, we need to force long calls to/from it
-CFLAGS_kgdb_test.o := -mlong-calls
-
-obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
deleted file mode 100644
index 486560aea050..000000000000
--- a/arch/blackfin/kernel/asm-offsets.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * generate definitions needed by assembly language modules
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/irq.h>
-#include <linux/thread_info.h>
-#include <linux/kbuild.h>
-#include <asm/pda.h>
-
-int main(void)
-{
- /* offsets into the task struct */
- DEFINE(TASK_STATE, offsetof(struct task_struct, state));
- DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
- DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
- DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
- DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
- DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack));
- DEFINE(TASK_MM, offsetof(struct task_struct, mm));
- DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
- DEFINE(TASK_SIGPENDING, offsetof(struct task_struct, pending));
-
- /* offsets into the irq_cpustat_t struct */
- DEFINE(CPUSTAT_SOFTIRQ_PENDING,
- offsetof(irq_cpustat_t, __softirq_pending));
-
- /* offsets into the thread struct */
- DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
- DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
- DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(PT_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
- DEFINE(THREAD_PC, offsetof(struct thread_struct, pc));
- DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
-
- /* offsets in thread_info struct */
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PREEMPT, thread_info, preempt_count);
-
- /* offsets into the pt_regs */
- DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0));
- DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0));
- DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc));
- DEFINE(PT_R0, offsetof(struct pt_regs, r0));
- DEFINE(PT_R1, offsetof(struct pt_regs, r1));
- DEFINE(PT_R2, offsetof(struct pt_regs, r2));
- DEFINE(PT_R3, offsetof(struct pt_regs, r3));
- DEFINE(PT_R4, offsetof(struct pt_regs, r4));
- DEFINE(PT_R5, offsetof(struct pt_regs, r5));
- DEFINE(PT_R6, offsetof(struct pt_regs, r6));
- DEFINE(PT_R7, offsetof(struct pt_regs, r7));
-
- DEFINE(PT_P0, offsetof(struct pt_regs, p0));
- DEFINE(PT_P1, offsetof(struct pt_regs, p1));
- DEFINE(PT_P2, offsetof(struct pt_regs, p2));
- DEFINE(PT_P3, offsetof(struct pt_regs, p3));
- DEFINE(PT_P4, offsetof(struct pt_regs, p4));
- DEFINE(PT_P5, offsetof(struct pt_regs, p5));
-
- DEFINE(PT_FP, offsetof(struct pt_regs, fp));
- DEFINE(PT_USP, offsetof(struct pt_regs, usp));
- DEFINE(PT_I0, offsetof(struct pt_regs, i0));
- DEFINE(PT_I1, offsetof(struct pt_regs, i1));
- DEFINE(PT_I2, offsetof(struct pt_regs, i2));
- DEFINE(PT_I3, offsetof(struct pt_regs, i3));
- DEFINE(PT_M0, offsetof(struct pt_regs, m0));
- DEFINE(PT_M1, offsetof(struct pt_regs, m1));
- DEFINE(PT_M2, offsetof(struct pt_regs, m2));
- DEFINE(PT_M3, offsetof(struct pt_regs, m3));
- DEFINE(PT_L0, offsetof(struct pt_regs, l0));
- DEFINE(PT_L1, offsetof(struct pt_regs, l1));
- DEFINE(PT_L2, offsetof(struct pt_regs, l2));
- DEFINE(PT_L3, offsetof(struct pt_regs, l3));
- DEFINE(PT_B0, offsetof(struct pt_regs, b0));
- DEFINE(PT_B1, offsetof(struct pt_regs, b1));
- DEFINE(PT_B2, offsetof(struct pt_regs, b2));
- DEFINE(PT_B3, offsetof(struct pt_regs, b3));
- DEFINE(PT_A0X, offsetof(struct pt_regs, a0x));
- DEFINE(PT_A0W, offsetof(struct pt_regs, a0w));
- DEFINE(PT_A1X, offsetof(struct pt_regs, a1x));
- DEFINE(PT_A1W, offsetof(struct pt_regs, a1w));
- DEFINE(PT_LC0, offsetof(struct pt_regs, lc0));
- DEFINE(PT_LC1, offsetof(struct pt_regs, lc1));
- DEFINE(PT_LT0, offsetof(struct pt_regs, lt0));
- DEFINE(PT_LT1, offsetof(struct pt_regs, lt1));
- DEFINE(PT_LB0, offsetof(struct pt_regs, lb0));
- DEFINE(PT_LB1, offsetof(struct pt_regs, lb1));
- DEFINE(PT_ASTAT, offsetof(struct pt_regs, astat));
- DEFINE(PT_RESERVED, offsetof(struct pt_regs, reserved));
- DEFINE(PT_RETS, offsetof(struct pt_regs, rets));
- DEFINE(PT_PC, offsetof(struct pt_regs, pc));
- DEFINE(PT_RETX, offsetof(struct pt_regs, retx));
- DEFINE(PT_RETN, offsetof(struct pt_regs, retn));
- DEFINE(PT_RETE, offsetof(struct pt_regs, rete));
- DEFINE(PT_SEQSTAT, offsetof(struct pt_regs, seqstat));
- DEFINE(PT_SYSCFG, offsetof(struct pt_regs, syscfg));
- DEFINE(PT_IPEND, offsetof(struct pt_regs, ipend));
- DEFINE(SIZEOF_PTREGS, sizeof(struct pt_regs));
- DEFINE(PT_TEXT_ADDR, sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_TEXT_END_ADDR, 4 + sizeof(struct pt_regs));/* Needed by gdb */
- DEFINE(PT_DATA_ADDR, 8 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_EXEC, 12 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_INTERP, 16 + sizeof(struct pt_regs));/* Needed by gdb */
-
- /* signal defines */
- DEFINE(SIGSEGV, SIGSEGV);
- DEFINE(SIGTRAP, SIGTRAP);
-
- /* PDA management (in L1 scratchpad) */
- DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg));
-#ifdef CONFIG_SMP
- DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask));
-#endif
- DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt));
- DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount));
- DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt));
- DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount));
- DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr));
- DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr));
- DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf));
- DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask));
- DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack));
- DEFINE(PDA_EXIPEND, offsetof(struct blackfin_pda, ex_ipend));
-#ifdef ANOMALY_05000261
- DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx));
-#endif
- DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr));
- DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr));
- DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx));
- DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_DF_DCPLB, offsetof(struct blackfin_pda, dcplb_doublefault_addr));
- DEFINE(PDA_DF_ICPLB, offsetof(struct blackfin_pda, icplb_doublefault_addr));
- DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
- DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
-#endif
-
- /* PDA initial management */
- DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
- DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
-#endif
-
-#ifdef CONFIG_SMP
- /* Inter-core lock (in L2 SRAM) */
- DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
-#endif
-
- return 0;
-}
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
deleted file mode 100644
index 9d3eb0cf8ccc..000000000000
--- a/arch/blackfin/kernel/bfin_dma.c
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
- * bfin_dma.c - Blackfin DMA implementation
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/proc_fs.h>
-#include <linux/sched.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <linux/uaccess.h>
-#include <asm/early_printk.h>
-
-/*
- * To make sure we work around 05000119 - we always check DMA_DONE bit,
- * never the DMA_RUN bit
- */
-
-struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-EXPORT_SYMBOL(dma_ch);
-
-static int __init blackfin_dma_init(void)
-{
- int i;
-
- printk(KERN_INFO "Blackfin DMA Controller\n");
-
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- atomic_set(&dma_ch[i].chan_status, 0);
- dma_ch[i].regs = dma_io_base_addr[i];
- }
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
- /* Mark MEMDMA Channel 3 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
-#else
- /* Mark MEMDMA Channel 0 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
-#endif
-
-#if defined(CONFIG_DEB_DMA_URGENT)
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
- | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
-#endif
-
- return 0;
-}
-arch_initcall(blackfin_dma_init);
-
-#ifdef CONFIG_PROC_FS
-static int proc_dma_show(struct seq_file *m, void *v)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i)
- if (dma_channel_active(i))
- seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
-
- return 0;
-}
-
-static int proc_dma_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_dma_show, NULL);
-}
-
-static const struct file_operations proc_dma_operations = {
- .open = proc_dma_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init proc_dma_init(void)
-{
- proc_create("dma", 0, NULL, &proc_dma_operations);
- return 0;
-}
-late_initcall(proc_dma_init);
-#endif
-
-static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
-{
-#ifdef CONFIG_BF54x
- unsigned int per_map;
-
- switch (channel) {
- case CH_UART2_RX: per_map = 0xC << 12; break;
- case CH_UART2_TX: per_map = 0xD << 12; break;
- case CH_UART3_RX: per_map = 0xE << 12; break;
- case CH_UART3_TX: per_map = 0xF << 12; break;
- default: return;
- }
-
- if (strncmp(device_id, "BFIN_UART", 9) == 0)
- dma_ch[channel].regs->peripheral_map = per_map;
-#endif
-}
-
-/**
- * request_dma - request a DMA channel
- *
- * Request the specific DMA channel from the system if it's available.
- */
-int request_dma(unsigned int channel, const char *device_id)
-{
- pr_debug("request_dma() : BEGIN\n");
-
- if (device_id == NULL)
- printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
-
-#if defined(CONFIG_BF561) && ANOMALY_05000182
- if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
- if (get_cclk() > 500000000) {
- printk(KERN_WARNING
- "Request IMDMA failed due to ANOMALY 05000182\n");
- return -EFAULT;
- }
- }
-#endif
-
- if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
- pr_debug("DMA CHANNEL IN USE\n");
- return -EBUSY;
- }
-
- set_dma_peripheral_map(channel, device_id);
- dma_ch[channel].device_id = device_id;
- dma_ch[channel].irq = 0;
-
- /* This is to be enabled by putting a restriction -
- * you have to request DMA, before doing any operations on
- * descriptor/channel
- */
- pr_debug("request_dma() : END\n");
- return 0;
-}
-EXPORT_SYMBOL(request_dma);
-
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
-{
- int ret;
- unsigned int irq;
-
- BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- irq = channel2irq(channel);
- ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
- if (ret)
- return ret;
-
- dma_ch[channel].irq = irq;
- dma_ch[channel].data = data;
-
- return 0;
-}
-EXPORT_SYMBOL(set_dma_callback);
-
-/**
- * clear_dma_buffer - clear DMA fifos for specified channel
- *
- * Set the Buffer Clear bit in the Configuration register of specific DMA
- * channel. This will stop the descriptor based DMA operation.
- */
-static void clear_dma_buffer(unsigned int channel)
-{
- dma_ch[channel].regs->cfg |= RESTART;
- SSYNC();
- dma_ch[channel].regs->cfg &= ~RESTART;
-}
-
-void free_dma(unsigned int channel)
-{
- pr_debug("freedma() : BEGIN\n");
- BUG_ON(channel >= MAX_DMA_CHANNELS ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- /* Halt the DMA */
- disable_dma(channel);
- clear_dma_buffer(channel);
-
- if (dma_ch[channel].irq)
- free_irq(dma_ch[channel].irq, dma_ch[channel].data);
-
- /* Clear the DMA Variable in the Channel */
- atomic_set(&dma_ch[channel].chan_status, 0);
-
- pr_debug("freedma() : END\n");
-}
-EXPORT_SYMBOL(free_dma);
-
-#ifdef CONFIG_PM
-# ifndef MAX_DMA_SUSPEND_CHANNELS
-# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
-# endif
-# ifndef CONFIG_BF60x
-int blackfin_dma_suspend(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- if (dma_ch[i].regs->cfg & DMAEN) {
- printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
- return -EBUSY;
- }
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
- }
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0);
-#endif
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- dma_ch[i].regs->cfg = 0;
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
- }
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-}
-# else
-int blackfin_dma_suspend(void)
-{
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
-}
-#endif
-#endif
-
-/**
- * blackfin_dma_early_init - minimal DMA init
- *
- * Setup a few DMA registers so we can safely do DMA transfers early on in
- * the kernel booting process. Really this just means using dma_memcpy().
- */
-void __init blackfin_dma_early_init(void)
-{
- early_shadow_stamp();
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
-}
-
-void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
- struct dma_register *dst_ch, *src_ch;
-
- early_shadow_stamp();
-
- /* We assume that everything is 4 byte aligned, so include
- * a basic sanity check
- */
- BUG_ON(dst % 4);
- BUG_ON(src % 4);
- BUG_ON(size % 4);
-
- src_ch = 0;
- /* Find an avalible memDMA channel */
- while (1) {
- if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
- dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
- } else {
- dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
- }
-
- if (!DMA_MMR_READ(&src_ch->cfg))
- break;
- else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
- DMA_MMR_WRITE(&src_ch->cfg, 0);
- break;
- }
- }
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted.
- */
- __builtin_bfin_ssync();
-
- /* Destination */
- bfin_write32(&dst_ch->start_addr, dst);
- DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Source */
- bfin_write32(&src_ch->start_addr, src);
- DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Enable */
- DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
- DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
-
- /* Since we are atomic now, don't use the workaround ssync */
- __builtin_bfin_ssync();
-
-#ifdef CONFIG_BF60x
- /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
- * transfer DDR data to L1 SRAM may corrupt data.
- * Should be reverted after this issue is root caused.
- */
- while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
- continue;
-#endif
-}
-
-void __init early_dma_memcpy_done(void)
-{
- early_shadow_stamp();
-
- while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
- (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
- continue;
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
- /*
- * Now that DMA is done, we would normally flush cache, but
- * i/d cache isn't running this early, so we don't bother,
- * and just clear out the DMA channel for next time
- */
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
- bfin_write_MDMA_D0_CONFIG(0);
- bfin_write_MDMA_D1_CONFIG(0);
-
- __builtin_bfin_ssync();
-}
-
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
-#else
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
-#endif
-
-/**
- * __dma_memcpy - program the MDMA registers
- *
- * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
- * while programming registers so that everything is fully configured. Wait
- * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
- * check will make sure we don't clobber any existing transfer.
- */
-static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
-{
- static DEFINE_SPINLOCK(mdma_lock);
- unsigned long flags;
-
- spin_lock_irqsave(&mdma_lock, flags);
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted. Do it under irq lock and
- * without the anomaly version (because we are atomic already).
- */
- __builtin_bfin_ssync();
-
- if (bfin_read_MDMA_S_CONFIG())
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- continue;
-
- if (conf & DMA2D) {
- /* For larger bit sizes, we've already divided down cnt so it
- * is no longer a multiple of 64k. So we have to break down
- * the limit here so it is a multiple of the incoming size.
- * There is no limitation here in terms of total size other
- * than the hardware though as the bits lost in the shift are
- * made up by MODIFY (== we can hit the whole address space).
- * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
- */
- u32 shift = abs(dmod) >> 1;
- size_t ycnt = cnt >> (16 - shift);
- cnt = 1 << (16 - shift);
- bfin_write_MDMA_D_Y_COUNT(ycnt);
- bfin_write_MDMA_S_Y_COUNT(ycnt);
- bfin_write_MDMA_D_Y_MODIFY(dmod);
- bfin_write_MDMA_S_Y_MODIFY(smod);
- }
-
- bfin_write_MDMA_D_START_ADDR(daddr);
- bfin_write_MDMA_D_X_COUNT(cnt);
- bfin_write_MDMA_D_X_MODIFY(dmod);
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_START_ADDR(saddr);
- bfin_write_MDMA_S_X_COUNT(cnt);
- bfin_write_MDMA_S_X_MODIFY(smod);
- bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(DMAEN | conf);
- if (conf & DMA2D)
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
- else
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
-
- spin_unlock_irqrestore(&mdma_lock, flags);
-
- SSYNC();
-
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- if (bfin_read_MDMA_S_CONFIG())
- continue;
- else
- return;
-
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(0);
- bfin_write_MDMA_D_CONFIG(0);
-}
-
-/**
- * _dma_memcpy - translate C memcpy settings into MDMA settings
- *
- * Handle all the high level steps before we touch the MDMA registers. So
- * handle direction, tweaking of sizes, and formatting of addresses.
- */
-static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- u32 conf, shift;
- s16 mod;
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (size == 0)
- return NULL;
-
- if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
- conf = WDSIZE_32;
- shift = 2;
- } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
- conf = WDSIZE_16;
- shift = 1;
- } else {
- conf = WDSIZE_8;
- shift = 0;
- }
-
- /* If the two memory regions have a chance of overlapping, make
- * sure the memcpy still works as expected. Do this by having the
- * copy run backwards instead.
- */
- mod = 1 << shift;
- if (src < dst) {
- mod *= -1;
- dst += size + mod;
- src += size + mod;
- }
- size >>= shift;
-
-#ifndef DMA_MMR_SIZE_32
- if (size > 0x10000)
- conf |= DMA2D;
-#endif
-
- __dma_memcpy(dst, mod, src, mod, size, conf);
-
- return pdst;
-}
-
-/**
- * dma_memcpy - DMA memcpy under mutex lock
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (bfin_addr_dcacheable(src))
- blackfin_dcache_flush_range(src, src + size);
-
- if (bfin_addr_dcacheable(dst))
- blackfin_dcache_invalidate_range(dst, dst + size);
-
- return dma_memcpy_nocache(pdst, psrc, size);
-}
-EXPORT_SYMBOL(dma_memcpy);
-
-/**
- * dma_memcpy_nocache - DMA memcpy under mutex lock
- * - No cache flush/invalidate
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
-{
-#ifdef DMA_MMR_SIZE_32
- _dma_memcpy(pdst, psrc, size);
-#else
- size_t bulk, rest;
-
- bulk = size & ~0xffff;
- rest = size - bulk;
- if (bulk)
- _dma_memcpy(pdst, psrc, bulk);
- _dma_memcpy(pdst + bulk, psrc + bulk, rest);
-#endif
- return pdst;
-}
-EXPORT_SYMBOL(dma_memcpy_nocache);
-
-/**
- * safe_dma_memcpy - DMA memcpy w/argument checking
- *
- * Verify arguments are safe before heading to dma_memcpy().
- */
-void *safe_dma_memcpy(void *dst, const void *src, size_t size)
-{
- if (!access_ok(VERIFY_WRITE, dst, size))
- return NULL;
- if (!access_ok(VERIFY_READ, src, size))
- return NULL;
- return dma_memcpy(dst, src, size);
-}
-EXPORT_SYMBOL(safe_dma_memcpy);
-
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_flush_range(buf, buf + len * size);
- __dma_memcpy(addr, 0, buf, size, len, dma_size);
-}
-
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_invalidate_range(buf, buf + len * size);
- __dma_memcpy(buf, size, addr, 0, len, dma_size);
-}
-
-#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
-{ \
- _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
-} \
-EXPORT_SYMBOL(dma_##io##s##bwl)
-MAKE_DMA_IO(out, b, 1, 8, const);
-MAKE_DMA_IO(in, b, 1, 8, );
-MAKE_DMA_IO(out, w, 2, 16, const);
-MAKE_DMA_IO(in, w, 2, 16, );
-MAKE_DMA_IO(out, l, 4, 32, const);
-MAKE_DMA_IO(in, l, 4, 32, );
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
deleted file mode 100644
index 63da80bbadf6..000000000000
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ /dev/null
@@ -1,1208 +0,0 @@
-/*
- * GPIO Abstraction Layer
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/gpio/driver.h>
-/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <asm/gpio.h>
-#include <asm/irq_handler.h>
-#include <asm/portmux.h>
-
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
- AWA_data = SYSCR,
- AWA_data_clear = SYSCR,
- AWA_data_set = SYSCR,
- AWA_toggle = SYSCR,
- AWA_maska = BFIN_UART_SCR,
- AWA_maska_clear = BFIN_UART_SCR,
- AWA_maska_set = BFIN_UART_SCR,
- AWA_maska_toggle = BFIN_UART_SCR,
- AWA_maskb = BFIN_UART_GCTL,
- AWA_maskb_clear = BFIN_UART_GCTL,
- AWA_maskb_set = BFIN_UART_GCTL,
- AWA_maskb_toggle = BFIN_UART_GCTL,
- AWA_dir = SPORT1_STAT,
- AWA_polar = SPORT1_STAT,
- AWA_edge = SPORT1_STAT,
- AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
- AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
- AWA_inen = DMA1_1_CONFIG,
-#endif
-};
- /* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...) do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
- (struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- (struct gpio_port_t *) PORTFIO,
- (struct gpio_port_t *) PORTGIO,
- (struct gpio_port_t *) PORTHIO,
-#elif defined(BF561_FAMILY)
- (struct gpio_port_t *) FIO0_FLAG_D,
- (struct gpio_port_t *) FIO1_FLAG_D,
- (struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTF_FER,
- (unsigned short *) PORTG_FER,
- (unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
- (unsigned short *) PORTF_MUX,
- (unsigned short *) PORTG_MUX,
- (unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-# if defined(CONFIG_BF52x)
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
- { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-# elif defined(CONFIG_BF51x)
- { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
- { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
- { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-# endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTCIO_FER,
- (unsigned short *) PORTDIO_FER,
- (unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#define RESOURCE_LABEL_SIZE 16
-
-static struct str_ident {
- char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-#if defined(CONFIG_PM)
-static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
-# ifdef BF538_FAMILY
-static unsigned short port_fer_saved[3];
-# endif
-#endif
-
-static void gpio_error(unsigned gpio)
-{
- printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
- if (label) {
- strncpy(str_ident[ident].name, label,
- RESOURCE_LABEL_SIZE);
- str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
- }
-}
-
-static char *get_label(unsigned short ident)
-{
- return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
- if (label == NULL) {
- dump_stack();
- printk(KERN_ERR "Please provide none-null label\n");
- }
-
- if (label)
- return strcmp(str_ident[ident].name, label);
- else
- return -EINVAL;
-}
-
-#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE));
-DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
-
-inline int check_gpio(unsigned gpio)
-{
- if (gpio >= MAX_BLACKFIN_GPIOS)
- return -EINVAL;
- return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
- /*
- * BF538/9 Port C,D and E are special.
- * Inverted PORT_FER polarity on CDE and no PORF_FER on F
- * Regular PORT F GPIOs are handled here, CDE are exclusively
- * managed by GPIOLIB
- */
-
- if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
- return;
-
- gpio -= MAX_BLACKFIN_GPIOS;
-
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- SSYNC();
- return;
-#endif
-
- if (check_gpio(gpio))
- return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static const s8 port_mux[] = {
- [GPIO_PF0] = 3,
- [GPIO_PF1] = 3,
- [GPIO_PF2] = 4,
- [GPIO_PF3] = 4,
- [GPIO_PF4] = 5,
- [GPIO_PF5] = 6,
- [GPIO_PF6] = 7,
- [GPIO_PF7] = 8,
- [GPIO_PF8 ... GPIO_PF15] = -1,
- [GPIO_PG0 ... GPIO_PG7] = -1,
- [GPIO_PG8] = 9,
- [GPIO_PG9] = 9,
- [GPIO_PG10] = 10,
- [GPIO_PG11] = 10,
- [GPIO_PG12] = 10,
- [GPIO_PG13] = 11,
- [GPIO_PG14] = 11,
- [GPIO_PG15] = 11,
- [GPIO_PH0 ... GPIO_PH15] = -1,
- [PORT_PJ0 ... PORT_PJ3] = -1,
- [PORT_PJ4] = 1,
- [PORT_PJ5] = 1,
- [PORT_PJ6 ... PORT_PJ9] = -1,
- [PORT_PJ10] = 0,
- [PORT_PJ11] = 0,
-};
-
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 m, pmux, pfunc, mask;
-
- if (offset < 0)
- return 0;
-
- pmux = bfin_read_PORT_MUX();
- for (m = 0; m < ARRAY_SIZE(port_mux); ++m) {
- if (m == ident)
- continue;
- if (port_mux[m] != offset)
- continue;
- if (!is_reserved(peri, m, 1))
- continue;
-
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pfunc = (pmux >> offset) & mask;
- if (pfunc != (function & mask)) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, m, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 pmux, mask;
-
- if (offset == -1)
- return;
-
- pmux = bfin_read_PORT_MUX();
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pmux &= ~(mask << offset);
- pmux |= ((function & mask) << offset);
-
- bfin_write_PORT_MUX(pmux);
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pin, gpiopin, pfunc;
-
- for (pin = 0; pin < GPIO_BANKSIZE; ++pin) {
- if (offset != pmux_offset[gpio_bank(ident)][pin])
- continue;
-
- gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin;
- if (gpiopin == ident)
- continue;
- if (!is_reserved(peri, gpiopin, 1))
- continue;
-
- pfunc = *port_mux[gpio_bank(ident)];
- pfunc = (pfunc >> offset) & 3;
- if (pfunc != function) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, gpiopin, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-inline void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pmux;
-
- pmux = *port_mux[gpio_bank(ident)];
- if (((pmux >> offset) & 3) == function)
- return;
- pmux &= ~(3 << offset);
- pmux |= (function & 3) << offset;
- *port_mux[gpio_bank(ident)] = pmux;
- SSYNC();
-}
-#else
-# define portmux_setup(...) do { } while (0)
-static int portmux_group_check(unsigned short per)
-{
- return 0;
-}
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO(dir) /* set_gpio_dir() */
-SET_GPIO(inen) /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge) /* set_gpio_edge() */
-SET_GPIO(both) /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
- unsigned long flags;
- if (ANOMALY_05000311 || ANOMALY_05000323)
- flags = hard_local_irq_save();
- gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
- if (ANOMALY_05000311 || ANOMALY_05000323) {
- AWA_DUMMY_READ(toggle);
- hard_local_irq_restore(flags);
- }
-}
-EXPORT_SYMBOL(set_gpio_toggle);
-
-
-/*Set current PORT date (16-bit word)*/
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- gpio_array[gpio_bank(gpio)]->name = arg; \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpiop_ ## name);
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpio_ ## name);
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/*Get current PORT date (16-bit word)*/
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = (gpio_array[gpio_bank(gpio)]->name); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpiop_ ## name);
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-
-#ifdef CONFIG_PM
-DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
-
-static const unsigned int sic_iwr_irqs[] = {
-#if defined(BF533_FAMILY)
- IRQ_PROG_INTB
-#elif defined(BF537_FAMILY)
- IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
-#elif defined(BF538_FAMILY)
- IRQ_PORTF_INTB
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
-#elif defined(BF561_FAMILY)
- IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
-#else
-# error no SIC_IWR defined
-#endif
-};
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin PM Setup API
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-* type -
-* PM_WAKE_RISING
-* PM_WAKE_FALLING
-* PM_WAKE_HIGH
-* PM_WAKE_LOW
-* PM_WAKE_BOTH_EDGES
-*
-* DESCRIPTION: Blackfin PM Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
- if (ctrl)
- reserve(wakeup, gpio);
- else
- unreserve(wakeup, gpio);
-
- set_gpio_maskb(gpio, ctrl);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
-{
- u16 bank, mask, i;
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- mask = map_entry(wakeup, i);
- bank = gpio_bank(i);
-
- if (mask)
- bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
- }
- return 0;
-}
-
-void bfin_gpio_pm_hibernate_suspend(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- port_fer_saved[i] = *port_fer[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].fer = *port_fer[bank];
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].mux = *port_mux[bank];
-#else
- if (bank == 0)
- gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
-#endif
-#endif
- gpio_bank_saved[bank].data = gpio_array[bank]->data;
- gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
- gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
- gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
- gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
- gpio_bank_saved[bank].both = gpio_array[bank]->both;
- gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_suspend();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-void bfin_gpio_pm_hibernate_restore(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- *port_fer[i] = port_fer_saved[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- *port_mux[bank] = gpio_bank_saved[bank].mux;
-#else
- if (bank == 0)
- bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
-#endif
- *port_fer[bank] = gpio_bank_saved[bank].fer;
-#endif
- gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
- gpio_array[bank]->data_set = gpio_bank_saved[bank].data
- & gpio_bank_saved[bank].dir;
- gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
- gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
- gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
- gpio_array[bank]->both = gpio_bank_saved[bank].both;
- gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_restore();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin Peripheral Resource Allocation
-* and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per Peripheral Identifier
-* label String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- /*
- * Don't cares are pins with only one dedicated function
- */
-
- if (per & P_DONTCARE)
- return 0;
-
- if (!(per & P_DEFINED))
- return -ENODEV;
-
- BUG_ON(ident >= MAX_RESOURCES);
-
- flags = hard_local_irq_save();
-
- /* If a pin can be muxed as either GPIO or peripheral, make
- * sure it is not already a GPIO pin when we request it.
- */
- if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d is already reserved as GPIO by %s !\n",
- __func__, ident, get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
-
- if (unlikely(is_reserved(peri, ident, 1))) {
-
- /*
- * Pin functions like AMC address strobes my
- * be requested and used by several drivers
- */
-
- if (!(per & P_MAYSHARE)) {
- /*
- * Allow that the identical pin function can
- * be requested from the same driver twice
- */
-
- if (cmp_label(ident, label) == 0)
- goto anyway;
-
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d function %d is already reserved by %s !\n",
- __func__, ident, P_FUNCT2MUX(per), get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- }
-
- if (unlikely(portmux_group_check(per))) {
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- anyway:
- reserve(peri, ident);
-
- portmux_setup(per);
- port_setup(ident, PERIPHERAL_USAGE);
-
- hard_local_irq_restore(flags);
- set_label(ident, label);
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request);
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
- u16 cnt;
- int ret;
-
- for (cnt = 0; per[cnt] != 0; cnt++) {
-
- ret = peripheral_request(per[cnt], label);
-
- if (ret < 0) {
- for ( ; cnt > 0; cnt--)
- peripheral_free(per[cnt - 1]);
-
- return ret;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request_list);
-
-void peripheral_free(unsigned short per)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- if (per & P_DONTCARE)
- return;
-
- if (!(per & P_DEFINED))
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(peri, ident, 0))) {
- hard_local_irq_restore(flags);
- return;
- }
-
- if (!(per & P_MAYSHARE))
- port_setup(ident, GPIO_USAGE);
-
- unreserve(peri, ident);
-
- set_label(ident, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(peripheral_free);
-
-void peripheral_free_list(const unsigned short per[])
-{
- u16 cnt;
- for (cnt = 0; per[cnt] != 0; cnt++)
- peripheral_free(per[cnt]);
-}
-EXPORT_SYMBOL(peripheral_free_list);
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int bfin_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(gpio, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
- " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
- } else { /* Reset POLAR setting when acquiring a gpio for the first time */
- set_gpio_polar(gpio, 0);
- }
-
- reserve(gpio, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_request);
-
-void bfin_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_gpio_free);
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int bfin_special_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(special_gpio, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
-
- reserve(special_gpio, gpio);
- reserve(peri, gpio);
-
- set_label(gpio, label);
- hard_local_irq_restore(flags);
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_special_gpio_request);
-
-void bfin_special_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(special_gpio, gpio);
- unreserve(peri, gpio);
- set_label(gpio, "free");
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_special_gpio_free);
-#endif
-
-
-int bfin_gpio_irq_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio, gpio, 1)))
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
- "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
- gpio, get_label(gpio));
-
- reserve(gpio_irq, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-
-void bfin_gpio_irq_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio_irq, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-
-static inline void __bfin_gpio_direction_input(unsigned gpio)
-{
- gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
- gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int bfin_gpio_direction_input(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
- __bfin_gpio_direction_input(gpio);
- AWA_DUMMY_READ(inen);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_input);
-
-void bfin_gpio_irq_prepare(unsigned gpio)
-{
- port_setup(gpio, GPIO_USAGE);
-}
-
-void bfin_gpio_set_value(unsigned gpio, int arg)
-{
- if (arg)
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- else
- gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_set_value);
-
-int bfin_gpio_direction_output(unsigned gpio, int value)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
-
- gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
- gpio_set_value(gpio, value);
- gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
- AWA_DUMMY_READ(dir);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_output);
-
-int bfin_gpio_get_value(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(get_gpio_edge(gpio))) {
- int ret;
- flags = hard_local_irq_save();
- set_gpio_edge(gpio, 0);
- ret = get_gpio_data(gpio);
- set_gpio_edge(gpio, 1);
- hard_local_irq_restore(flags);
- return ret;
- } else
- return get_gpio_data(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_get_value);
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high. To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
- unsigned short gpio = P_IDENT(pin);
- port_setup(gpio, GPIO_USAGE);
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- AWA_DUMMY_READ(data_set);
- udelay(1);
-}
-
-#if defined(CONFIG_PROC_FS)
-static int gpio_proc_show(struct seq_file *m, void *v)
-{
- int c, irq, gpio;
-
- for (c = 0; c < MAX_RESOURCES; c++) {
- irq = is_reserved(gpio_irq, c, 1);
- gpio = is_reserved(gpio, c, 1);
- if (!check_gpio(c) && (gpio || irq))
- seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
- get_label(c), (gpio && irq) ? " *" : "",
- get_gpio_dir(c) ? "OUTPUT" : "INPUT");
- else if (is_reserved(peri, c, 1))
- seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
- else
- continue;
- }
-
- return 0;
-}
-
-static int gpio_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_proc_show, NULL);
-}
-
-static const struct file_operations gpio_proc_ops = {
- .open = gpio_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static __init int gpio_register_proc(void)
-{
- struct proc_dir_entry *proc_gpio;
-
- proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops);
- return proc_gpio == NULL;
-}
-__initcall(gpio_register_proc);
-#endif
-
-#ifdef CONFIG_GPIOLIB
-static int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_direction_input(gpio);
-}
-
-static int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
-{
- return bfin_gpio_direction_output(gpio, level);
-}
-
-static int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!bfin_gpio_get_value(gpio);
-}
-
-static void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- return bfin_gpio_set_value(gpio, value);
-}
-
-static int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_request(gpio, chip->label);
-}
-
-static void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_free(gpio);
-}
-
-static int bfin_gpiolib_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
- return gpio + GPIO_IRQ_BASE;
-}
-
-static struct gpio_chip bfin_chip = {
- .label = "BFIN-GPIO",
- .direction_input = bfin_gpiolib_direction_input,
- .get = bfin_gpiolib_get_value,
- .direction_output = bfin_gpiolib_direction_output,
- .set = bfin_gpiolib_set_value,
- .request = bfin_gpiolib_gpio_request,
- .free = bfin_gpiolib_gpio_free,
- .to_irq = bfin_gpiolib_gpio_to_irq,
- .base = 0,
- .ngpio = MAX_BLACKFIN_GPIOS,
-};
-
-static int __init bfin_gpiolib_setup(void)
-{
- return gpiochip_add_data(&bfin_chip, NULL);
-}
-arch_initcall(bfin_gpiolib_setup);
-#endif
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
deleted file mode 100644
index 68096e8f787f..000000000000
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <asm/irq_handler.h>
-
-/* Allow people to have their own Blackfin exception handler in a module */
-EXPORT_SYMBOL(bfin_return_from_exception);
-
-/* All the Blackfin cache functions: mach-common/cache.S */
-EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
-EXPORT_SYMBOL(blackfin_icache_flush_range);
-EXPORT_SYMBOL(blackfin_dcache_flush_range);
-EXPORT_SYMBOL(blackfin_dflush_page);
-
-/* The following are special because they're not called
- * explicitly (the C compiler generates them). Fortunately,
- * their interface isn't gonna change any time soon now, so
- * it's OK to leave it out of version control.
- */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(memcmp);
-EXPORT_SYMBOL(memmove);
-EXPORT_SYMBOL(memchr);
-
-/*
- * Because string functions are both inline and exported functions and
- * folder arch/blackfin/lib is configured as a library path in Makefile,
- * symbols exported in folder lib is not linked into built-in.o but
- * inlined only. In order to export string symbols to kernel module
- * properly, they should be exported here.
- */
-EXPORT_SYMBOL(strcpy);
-EXPORT_SYMBOL(strncpy);
-EXPORT_SYMBOL(strcmp);
-EXPORT_SYMBOL(strncmp);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __smulsi3_highpart(void);
-extern void __umulsi3_highpart(void);
-extern void __divsi3(void);
-extern void __lshrdi3(void);
-extern void __modsi3(void);
-extern void __muldi3(void);
-extern void __udivsi3(void);
-extern void __umodsi3(void);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__umulsi3_highpart);
-EXPORT_SYMBOL(__smulsi3_highpart);
-EXPORT_SYMBOL(__divsi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__modsi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__udivsi3);
-EXPORT_SYMBOL(__umodsi3);
-
-/* Input/output symbols: lib/{in,out}s.S */
-EXPORT_SYMBOL(outsb);
-EXPORT_SYMBOL(insb);
-EXPORT_SYMBOL(outsw);
-EXPORT_SYMBOL(outsw_8);
-EXPORT_SYMBOL(insw);
-EXPORT_SYMBOL(insw_8);
-EXPORT_SYMBOL(outsl);
-EXPORT_SYMBOL(insl);
-EXPORT_SYMBOL(insl_16);
-
-#ifdef CONFIG_SMP
-EXPORT_SYMBOL(__raw_atomic_add_asm);
-EXPORT_SYMBOL(__raw_atomic_xadd_asm);
-EXPORT_SYMBOL(__raw_atomic_and_asm);
-EXPORT_SYMBOL(__raw_atomic_or_asm);
-EXPORT_SYMBOL(__raw_atomic_xor_asm);
-EXPORT_SYMBOL(__raw_atomic_test_asm);
-
-EXPORT_SYMBOL(__raw_xchg_1_asm);
-EXPORT_SYMBOL(__raw_xchg_2_asm);
-EXPORT_SYMBOL(__raw_xchg_4_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_1_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_2_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_4_asm);
-EXPORT_SYMBOL(__raw_spin_is_locked_asm);
-EXPORT_SYMBOL(__raw_spin_lock_asm);
-EXPORT_SYMBOL(__raw_spin_trylock_asm);
-EXPORT_SYMBOL(__raw_spin_unlock_asm);
-EXPORT_SYMBOL(__raw_read_lock_asm);
-EXPORT_SYMBOL(__raw_read_trylock_asm);
-EXPORT_SYMBOL(__raw_read_unlock_asm);
-EXPORT_SYMBOL(__raw_write_lock_asm);
-EXPORT_SYMBOL(__raw_write_trylock_asm);
-EXPORT_SYMBOL(__raw_write_unlock_asm);
-EXPORT_SYMBOL(__raw_bit_set_asm);
-EXPORT_SYMBOL(__raw_bit_clear_asm);
-EXPORT_SYMBOL(__raw_bit_toggle_asm);
-EXPORT_SYMBOL(__raw_bit_test_asm);
-EXPORT_SYMBOL(__raw_bit_test_set_asm);
-EXPORT_SYMBOL(__raw_bit_test_clear_asm);
-EXPORT_SYMBOL(__raw_bit_test_toggle_asm);
-EXPORT_SYMBOL(__raw_uncached_fetch_asm);
-#ifdef __ARCH_SYNC_CORE_DCACHE
-EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
-EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
-#endif
-#endif
-
-#ifdef CONFIG_FUNCTION_TRACER
-extern void _mcount(void);
-EXPORT_SYMBOL(_mcount);
-#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
deleted file mode 100644
index 394d0b1b28fe..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
deleted file mode 100644
index c15fd05f0b09..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-
-int first_switched_icplb, first_switched_dcplb;
-int first_mask_dcplb;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long d_data, i_data;
- unsigned long d_cache = 0, i_cache = 0;
-
- printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_cache = CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_cache |= CPLB_L1_AOW | CPLB_WT;
-#endif
-#endif
-
- i_d = i_i = 0;
-
- /* Set up the zero page. */
- dcplb_tbl[cpu][i_d].addr = 0;
- dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-
- icplb_tbl[cpu][i_i].addr = 0;
- icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
- d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
- i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
-
- for (; addr < memory_start; addr += 4 * 1024 * 1024) {
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD;
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
-#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
- dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
-#endif
-#if L1_CODE_LENGTH > 0
- icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
- icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-#endif
-
- /* Cover L2 memory */
-#if L2_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = L2_START;
- dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
- icplb_tbl[cpu][i_i].addr = L2_START;
- icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
-#endif
-
- first_mask_dcplb = i_d;
- first_switched_dcplb = i_d + (1 << page_mask_order);
- first_switched_icplb = i_i;
-
- while (i_d < MAX_CPLBS)
- dcplb_tbl[cpu][i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- icplb_tbl[cpu][i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
-}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
deleted file mode 100644
index b56bd8514b7c..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Blackfin CPLB exception handling for when MPU in on
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/mm.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mmu_context.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int page_mask_nelts;
-int page_mask_order;
-unsigned long *current_rwx_mask[NR_CPUS];
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-int nr_cplb_flush[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-/*
- * Given the contents of the status register, return the index of the
- * CPLB that caused the fault.
- */
-static inline int faulting_cplb_index(int status)
-{
- int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
- return 30 - signbits;
-}
-
-/*
- * Given the contents of the status register and the DCPLB_DATA contents,
- * return true if a write access should be permitted.
- */
-static inline int write_permitted(int status, unsigned long data)
-{
- if (status & FAULT_USERSUPV)
- return !!(data & CPLB_SUPV_WR);
- else
- return !!(data & CPLB_USER_WR);
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-MGR_ATTR static int evict_one_icplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_icplb; i < MAX_CPLBS; i++)
- if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
- if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- unsigned long *mask;
- int idx;
- unsigned long d_data;
-
- nr_dcplb_miss[cpu]++;
-
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (bfin_addr_dcacheable(addr)) {
- d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
- }
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
- }
-#endif
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
- addr &= ~(1 * 1024 * 1024 - 1);
- d_data &= ~PAGE_SIZE_4KB;
- d_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- d_data |= CPLB_USER_RD | CPLB_USER_WR;
- if (reserved_mem_dcache_on)
- d_data |= CPLB_L1_CHBL;
- } else {
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
-
- mask += page_mask_nelts;
- if (mask[idx] & bit)
- d_data |= CPLB_USER_WR;
- }
- }
- idx = evict_one_dcplb(cpu);
-
- addr &= PAGE_MASK;
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = d_data;
-
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data;
-
- nr_icplb_miss[cpu]++;
-
- /* If inside the uncached DMA region, fault. */
- if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
- return CPLB_PROT_VIOL;
-
- if (status & FAULT_USERSUPV)
- nr_icplb_supv_miss[cpu]++;
-
- /*
- * First, try to find a CPLB that matches this address. If we
- * find one, then the fact that we're in the miss handler means
- * that the instruction crosses a page boundary.
- */
- for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
- if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
- unsigned long this_addr = icplb_tbl[cpu][idx].addr;
- if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
- addr += PAGE_SIZE;
- break;
- }
- }
- }
-
- i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- /*
- * Normal RAM, and possibly the reserved memory area, are
- * cacheable.
- */
- if (addr < _ramend ||
- (addr < physical_mem_end && reserved_mem_icache_on))
- i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- i_data = L2_IMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & FAULT_USERSUPV)) {
- addr &= ~(1 * 1024 * 1024 - 1);
- i_data &= ~PAGE_SIZE_4KB;
- i_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- i_data |= CPLB_USER_RD;
- if (reserved_mem_icache_on)
- i_data |= CPLB_L1_CHBL;
- } else {
- /*
- * Two cases to distinguish - a supervisor access must
- * necessarily be for a module page; we grant it
- * unconditionally (could do better here in the future).
- * Otherwise, check the x bitmap of the current process.
- */
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- }
- idx = evict_one_icplb(cpu);
- addr &= PAGE_MASK;
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = i_data;
-
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
-{
- int status = bfin_read_DCPLB_STATUS();
-
- nr_dcplb_prot[cpu]++;
-
- if (status & FAULT_RW) {
- int idx = faulting_cplb_index(status);
- unsigned long data = dcplb_tbl[cpu][idx].data;
- if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
- write_permitted(status, data)) {
- data |= CPLB_DIRTY;
- dcplb_tbl[cpu][idx].data = data;
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- return 0;
- }
- }
- return CPLB_PROT_VIOL;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case 0x23:
- return dcplb_protection_fault(cpu);
- case 0x2C:
- return icplb_miss(cpu);
- case 0x26:
- return dcplb_miss(cpu);
- default:
- return 1;
- }
-}
-
-void flush_switched_cplbs(unsigned int cpu)
-{
- int i;
- unsigned long flags;
-
- nr_cplb_flush[cpu]++;
-
- flags = hard_local_irq_save();
- _disable_icplb();
- for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
- icplb_tbl[cpu][i].data = 0;
- bfin_write32(ICPLB_DATA0 + i * 4, 0);
- }
- _enable_icplb();
-
- _disable_dcplb();
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
- dcplb_tbl[cpu][i].data = 0;
- bfin_write32(DCPLB_DATA0 + i * 4, 0);
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-
-}
-
-void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
-{
- int i;
- unsigned long addr = (unsigned long)masks;
- unsigned long d_data;
- unsigned long flags;
-
- if (!masks) {
- current_rwx_mask[cpu] = masks;
- return;
- }
-
- flags = hard_local_irq_save();
- current_rwx_mask[cpu] = masks;
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else {
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_data |= CPLB_L1_CHBL;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
-#endif
- }
-
- _disable_dcplb();
- for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
- dcplb_tbl[cpu][i].addr = addr;
- dcplb_tbl[cpu][i].data = d_data;
- bfin_write32(DCPLB_DATA0 + i * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + i * 4, addr);
- addr += PAGE_SIZE;
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
deleted file mode 100644
index 81baa27bc389..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
deleted file mode 100644
index b49a53b583d5..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-
-int first_switched_icplb PDT_ATTR;
-int first_switched_dcplb PDT_ATTR;
-
-struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
-struct cplb_boundary icplb_bounds[9] PDT_ATTR;
-
-int icplb_nr_bounds PDT_ATTR;
-int dcplb_nr_bounds PDT_ATTR;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long cplb_pageflags, cplb_pagesize;
-
- struct cplb_entry *d_tbl = dcplb_tbl[cpu];
- struct cplb_entry *i_tbl = icplb_tbl[cpu];
-
- printk(KERN_INFO "NOMPU: setting up cplb tables\n");
-
- i_d = i_i = 0;
-
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- /* Set up the zero page. */
- d_tbl[i_d].addr = 0;
- d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
- i_tbl[i_i].addr = 0;
- i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-#endif
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
-
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-
- for (; addr < memory_start; addr += cplb_pagesize) {
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
-#ifdef CONFIG_BF60x
- addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
-#else
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
-#endif
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
- if (cpu == 0) {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#ifdef CONFIG_SMP
- else {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = COREB_L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = COREB_L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#endif
- first_switched_dcplb = i_d;
- first_switched_icplb = i_i;
-
- BUG_ON(first_switched_dcplb > MAX_CPLBS);
- BUG_ON(first_switched_icplb > MAX_CPLBS);
-
- while (i_d < MAX_CPLBS)
- d_tbl[i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- i_tbl[i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
- unsigned long uncached_end;
- int i_d, i_i;
-
- i_d = 0;
- /* Normal RAM, including MTD FS. */
-#ifdef CONFIG_MTD_UCLINUX
- uncached_end = memory_mtd_start + mtd_size;
-#else
- uncached_end = memory_end;
-#endif
- /*
- * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
- * so that we don't have to use 4kB pages and cause CPLB thrashing
- */
- if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
- ((_ramend - uncached_end) >= 1 * 1024 * 1024))
- dcplb_bounds[i_d].eaddr = uncached_end;
- else
- dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- dcplb_bounds[i_d].eaddr = _ramend;
- dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
- }
- if (_ramend != physical_mem_end) {
- /* Reserved memory. */
- dcplb_bounds[i_d].eaddr = physical_mem_end;
- dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
- SDRAM_DGENERIC : SDRAM_DNON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
- dcplb_bounds[i_d++].data = 0;
- /* ASYNC banks. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- dcplb_bounds[i_d++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
- dcplb_bounds[i_d++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START;
- dcplb_bounds[i_d++].data = 0;
- /* L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
- dcplb_bounds[i_d++].data = L2_DMEMORY;
- }
- dcplb_nr_bounds = i_d;
- BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
-
- i_i = 0;
- /* Normal RAM, including MTD FS. */
- icplb_bounds[i_i].eaddr = uncached_end;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
- if (_ramend != physical_mem_end) {
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- /* Normally this hole is caught by the async below. */
- icplb_bounds[i_i].eaddr = _ramend;
- icplb_bounds[i_i++].data = 0;
- }
- /* Reserved memory. */
- icplb_bounds[i_i].eaddr = physical_mem_end;
- icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
- SDRAM_IGENERIC : SDRAM_INON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
- icplb_bounds[i_i++].data = 0;
- /* ASYNC banks. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- icplb_bounds[i_i++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START;
- icplb_bounds[i_i++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START;
- icplb_bounds[i_i++].data = 0;
- /* L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
- icplb_bounds[i_i++].data = L2_IMEMORY;
- }
- icplb_nr_bounds = i_i;
- BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
deleted file mode 100644
index 79cc0f6dcdd5..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
- * Author: Michael McTernan <mmcternan@airvana.com>
- *
- * Description: CPLB miss handler.
- *
- * Modified:
- * Copyright 2008 Airvana Inc.
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/cplb.h>
-#include <asm/mmu_context.h>
-#include <asm/traps.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
-int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
-#ifdef CONFIG_CPLB_INFO
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-static inline void write_icplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
-#ifdef CONFIG_CPLB_INFO
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS] PDT_ATTR;
-static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-static int evict_one_icplb(int cpu)
-{
- int i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-static int evict_one_dcplb(int cpu)
-{
- int i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int icplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data, base, addr1, eaddr;
-
- nr_icplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_icplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = icplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < icplb_nr_bounds);
-
- if (unlikely(idx == icplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- i_data = icplb_bounds[idx].data;
- if (unlikely(i_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr1 = addr & ~(SIZE_4M - 1);
- addr &= ~(SIZE_1M - 1);
- i_data |= PAGE_SIZE_1MB;
- if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- i_data |= PAGE_SIZE_4MB;
- addr = addr1;
- }
-
- /* Pick entry to evict */
- idx = evict_one_icplb(cpu);
-
- write_icplb_data(cpu, idx, i_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR static int dcplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- int idx;
- unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
-
- nr_dcplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_dcplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = dcplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < dcplb_nr_bounds);
-
- if (unlikely(idx == dcplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- d_data = dcplb_bounds[idx].data;
- if (unlikely(d_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr &= ~(SIZE_1M - 1);
- d_data |= PAGE_SIZE_1MB;
-
- /* BF60x support large than 4M CPLB page size */
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-find_pagesize:
- addr1 = addr & ~(cplb_pagesize - 1);
- if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- d_data |= cplb_pageflags;
- addr = addr1;
- goto found_pagesize;
- } else {
- if (cplb_pagesize > SIZE_4M) {
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
- goto find_pagesize;
- }
- }
-
-found_pagesize:
-#ifdef CONFIG_BF60x
- if ((addr >= ASYNC_BANK0_BASE)
- && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- d_data |= PAGE_SIZE_64MB;
-#endif
-
- /* Pick entry to evict */
- idx = evict_one_dcplb(cpu);
-
- write_dcplb_data(cpu, idx, d_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case VEC_CPLB_I_M:
- return icplb_miss(cpu);
- case VEC_CPLB_M:
- return dcplb_miss(cpu);
- default:
- return CPLB_UNKNOWN_ERR;
- }
-}
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c
deleted file mode 100644
index 5b80d59e66e5..000000000000
--- a/arch/blackfin/kernel/cplbinfo.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/blackfin/kernel/cplbinfo.c - display CPLB status
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ctype.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-
-#include <asm/cplbinit.h>
-#include <asm/blackfin.h>
-
-static char const page_strtbl[][4] = {
- "1K", "4K", "1M", "4M",
-#ifdef CONFIG_BF60x
- "16K", "64K", "16M", "64M",
-#endif
-};
-#define page(flags) (((flags) & 0x70000) >> 16)
-#define strpage(flags) page_strtbl[page(flags)]
-
-struct cplbinfo_data {
- loff_t pos;
- char cplb_type;
- u32 mem_control;
- struct cplb_entry *tbl;
- int switched;
-};
-
-static void cplbinfo_print_header(struct seq_file *m)
-{
- seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
-}
-
-static int cplbinfo_nomore(struct cplbinfo_data *cdata)
-{
- return cdata->pos >= MAX_CPLBS;
-}
-
-static int cplbinfo_show(struct seq_file *m, void *p)
-{
- struct cplbinfo_data *cdata;
- unsigned long data, addr;
- loff_t pos;
-
- cdata = p;
- pos = cdata->pos;
- addr = cdata->tbl[pos].addr;
- data = cdata->tbl[pos].data;
-
- seq_printf(m,
- "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n",
- (int)pos, addr, data, strpage(data),
- (data & CPLB_USER_RD) ? 'Y' : 'N',
- (data & CPLB_USER_WR) ? 'Y' : 'N',
- (data & CPLB_SUPV_WR) ? 'Y' : 'N',
- pos < cdata->switched ? 'N' : 'Y');
-
- return 0;
-}
-
-static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu)
-{
- if (cdata->cplb_type == 'I') {
- cdata->mem_control = bfin_read_IMEM_CONTROL();
- cdata->tbl = icplb_tbl[cpu];
- cdata->switched = first_switched_icplb;
- } else {
- cdata->mem_control = bfin_read_DMEM_CONTROL();
- cdata->tbl = dcplb_tbl[cpu];
- cdata->switched = first_switched_dcplb;
- }
-}
-
-static void *cplbinfo_start(struct seq_file *m, loff_t *pos)
-{
- struct cplbinfo_data *cdata = m->private;
-
- if (!*pos) {
- seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type,
- (cdata->mem_control & ENDCPLB ? "en" : "dis"),
- cdata->mem_control);
- cplbinfo_print_header(m);
- } else if (cplbinfo_nomore(cdata))
- return NULL;
-
- get_cpu();
- return cdata;
-}
-
-static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos)
-{
- struct cplbinfo_data *cdata = p;
- cdata->pos = ++(*pos);
- if (cplbinfo_nomore(cdata))
- return NULL;
- else
- return cdata;
-}
-
-static void cplbinfo_stop(struct seq_file *m, void *p)
-{
- put_cpu();
-}
-
-static const struct seq_operations cplbinfo_sops = {
- .start = cplbinfo_start,
- .next = cplbinfo_next,
- .stop = cplbinfo_stop,
- .show = cplbinfo_show,
-};
-
-#define CPLBINFO_DCPLB_FLAG 0x80000000
-
-static int cplbinfo_open(struct inode *inode, struct file *file)
-{
- char cplb_type;
- unsigned int cpu = (unsigned long)PDE_DATA(file_inode(file));
- int ret;
- struct seq_file *m;
- struct cplbinfo_data *cdata;
-
- cplb_type = cpu & CPLBINFO_DCPLB_FLAG ? 'D' : 'I';
- cpu &= ~CPLBINFO_DCPLB_FLAG;
-
- if (!cpu_online(cpu))
- return -ENODEV;
-
- ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata));
- if (ret)
- return ret;
- m = file->private_data;
- cdata = m->private;
-
- cdata->pos = 0;
- cdata->cplb_type = cplb_type;
- cplbinfo_seq_init(cdata, cpu);
-
- return 0;
-}
-
-static const struct file_operations cplbinfo_fops = {
- .open = cplbinfo_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release_private,
-};
-
-static int __init cplbinfo_init(void)
-{
- struct proc_dir_entry *cplb_dir, *cpu_dir;
- char buf[10];
- unsigned int cpu;
-
- cplb_dir = proc_mkdir("cplbinfo", NULL);
- if (!cplb_dir)
- return -ENOMEM;
-
- for_each_possible_cpu(cpu) {
- sprintf(buf, "cpu%i", cpu);
- cpu_dir = proc_mkdir(buf, cplb_dir);
- if (!cpu_dir)
- return -ENOMEM;
-
- proc_create_data("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)cpu);
- proc_create_data("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)(cpu | CPLBINFO_DCPLB_FLAG));
- }
-
- return 0;
-}
-late_initcall(cplbinfo_init);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
deleted file mode 100644
index 194773ce109e..000000000000
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ /dev/null
@@ -1,1891 +0,0 @@
-/*
- * debugfs interface to core/system MMRs
- *
- * Copyright 2007-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/debugfs.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/bfin_ppi.h>
-#include <asm/bfin_serial.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_twi.h>
-#include <asm/gpio.h>
-
-/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
-#ifdef BFIN_PORT_MUX
-#undef PORT_MUX
-#define PORT_MUX BFIN_PORT_MUX
-#endif
-
-#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
-#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
-#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
-#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
-
-#define D_RO(name, bits) d_RO(#name, bits, name)
-#define D_WO(name, bits) d_WO(#name, bits, name)
-#define D32(name) d(#name, 32, name)
-#define D16(name) d(#name, 16, name)
-
-#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
-#define __REGS(peri, sname, rname) \
- do { \
- struct bfin_##peri##_regs r; \
- void *addr = (void *)(base + REGS_OFF(peri, rname)); \
- strcpy(_buf, sname); \
- if (sizeof(r.rname) == 2) \
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
- else \
- debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
- } while (0)
-#define REGS_STR_PFX(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%i_", num) : \
- sprintf(buf, #pfx "_")); \
- })
-#define REGS_STR_PFX_C(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%c_", 'A' + num) : \
- sprintf(buf, #pfx "_")); \
- })
-
-/*
- * Core registers (not memory mapped)
- */
-extern u32 last_seqstat;
-
-static int debug_cclk_get(void *data, u64 *val)
-{
- *val = get_cclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
-
-static int debug_sclk_get(void *data, u64 *val)
-{
- *val = get_sclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
-
-#define DEFINE_SYSREG(sr, pre, post) \
-static int sysreg_##sr##_get(void *data, u64 *val) \
-{ \
- unsigned long tmp; \
- pre; \
- __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
- *val = tmp; \
- return 0; \
-} \
-static int sysreg_##sr##_set(void *data, u64 val) \
-{ \
- unsigned long tmp = val; \
- __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
- post; \
- return 0; \
-} \
-DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
-
-DEFINE_SYSREG(cycles, , );
-DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
-DEFINE_SYSREG(emudat, , );
-DEFINE_SYSREG(seqstat, , );
-DEFINE_SYSREG(syscfg, , CSYNC());
-#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
-
-#ifndef CONFIG_BF60x
-/*
- * CAN
- */
-#define CAN_OFF(mmr) REGS_OFF(can, mmr)
-#define __CAN(uname, lname) __REGS(can, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
-{
- static struct dentry *am, *mb;
- int i, j;
- char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
-
- if (!am) {
- am = debugfs_create_dir("am", parent);
- mb = debugfs_create_dir("mb", parent);
- }
-
- __CAN(MC1, mc1);
- __CAN(MD1, md1);
- __CAN(TRS1, trs1);
- __CAN(TRR1, trr1);
- __CAN(TA1, ta1);
- __CAN(AA1, aa1);
- __CAN(RMP1, rmp1);
- __CAN(RML1, rml1);
- __CAN(MBTIF1, mbtif1);
- __CAN(MBRIF1, mbrif1);
- __CAN(MBIM1, mbim1);
- __CAN(RFH1, rfh1);
- __CAN(OPSS1, opss1);
-
- __CAN(MC2, mc2);
- __CAN(MD2, md2);
- __CAN(TRS2, trs2);
- __CAN(TRR2, trr2);
- __CAN(TA2, ta2);
- __CAN(AA2, aa2);
- __CAN(RMP2, rmp2);
- __CAN(RML2, rml2);
- __CAN(MBTIF2, mbtif2);
- __CAN(MBRIF2, mbrif2);
- __CAN(MBIM2, mbim2);
- __CAN(RFH2, rfh2);
- __CAN(OPSS2, opss2);
-
- __CAN(CLOCK, clock);
- __CAN(TIMING, timing);
- __CAN(DEBUG, debug);
- __CAN(STATUS, status);
- __CAN(CEC, cec);
- __CAN(GIS, gis);
- __CAN(GIM, gim);
- __CAN(GIF, gif);
- __CAN(CONTROL, control);
- __CAN(INTR, intr);
- __CAN(VERSION, version);
- __CAN(MBTD, mbtd);
- __CAN(EWR, ewr);
- __CAN(ESR, esr);
- /*__CAN(UCREG, ucreg); no longer exists */
- __CAN(UCCNT, uccnt);
- __CAN(UCRC, ucrc);
- __CAN(UCCNF, uccnf);
- __CAN(VERSION2, version2);
-
- for (i = 0; i < 32; ++i) {
- sprintf(_buf, "AM%02iL", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].aml)));
- sprintf(_buf, "AM%02iH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].amh)));
-
- for (j = 0; j < 3; ++j) {
- sprintf(_buf, "MB%02i_DATA%i", i, j);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
- }
- sprintf(_buf, "MB%02i_LENGTH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].dlc)));
- sprintf(_buf, "MB%02i_TIMESTAMP", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].tsv)));
- sprintf(_buf, "MB%02i_ID0", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id0)));
- sprintf(_buf, "MB%02i_ID1", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id1)));
- }
-}
-#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
-
-/*
- * DMA
- */
-#define __DMA(uname, lname) __REGS(dma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
-{
- char buf[32], *_buf;
-
- if (mdma)
- _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
- else
- _buf = buf + sprintf(buf, "%s%i_", pfx, num);
-
- __DMA(NEXT_DESC_PTR, next_desc_ptr);
- __DMA(START_ADDR, start_addr);
- __DMA(CONFIG, config);
- __DMA(X_COUNT, x_count);
- __DMA(X_MODIFY, x_modify);
- __DMA(Y_COUNT, y_count);
- __DMA(Y_MODIFY, y_modify);
- __DMA(CURR_DESC_PTR, curr_desc_ptr);
- __DMA(CURR_ADDR, curr_addr);
- __DMA(IRQ_STATUS, irq_status);
-#ifndef CONFIG_BF60x
- if (strcmp(pfx, "IMDMA") != 0)
- __DMA(PERIPHERAL_MAP, peripheral_map);
-#endif
- __DMA(CURR_X_COUNT, curr_x_count);
- __DMA(CURR_Y_COUNT, curr_y_count);
-}
-#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
-#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
-#define _MDMA(num, x) \
- do { \
- _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
- _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
- } while (0)
-#define MDMA(num) _MDMA(num, M)
-#define IMDMA(num) _MDMA(num, IM)
-
-/*
- * EPPI
- */
-#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
- __EPPI(STATUS, status);
- __EPPI(HCOUNT, hcount);
- __EPPI(HDELAY, hdelay);
- __EPPI(VCOUNT, vcount);
- __EPPI(VDELAY, vdelay);
- __EPPI(FRAME, frame);
- __EPPI(LINE, line);
- __EPPI(CLKDIV, clkdiv);
- __EPPI(CONTROL, control);
- __EPPI(FS1W_HBL, fs1w_hbl);
- __EPPI(FS1P_AVPL, fs1p_avpl);
- __EPPI(FS2W_LVB, fs2w_lvb);
- __EPPI(FS2P_LAVF, fs2p_lavf);
- __EPPI(CLIP, clip);
-}
-#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
-
-/*
- * General Purpose Timers
- */
-#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
- __GPTIMER(CONFIG, config);
- __GPTIMER(COUNTER, counter);
- __GPTIMER(PERIOD, period);
- __GPTIMER(WIDTH, width);
-}
-#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
-
-#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
-#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-
- if (num == -1) {
- _buf = buf + sprintf(buf, "TIMER_");
- __GPTIMER_GROUP(ENABLE, enable);
- __GPTIMER_GROUP(DISABLE, disable);
- __GPTIMER_GROUP(STATUS, status);
- } else {
- /* These MMRs are a bit odd as the group # is a suffix */
- _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
-
- _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
-
- _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
- d(buf, 32, base + GPTIMER_GROUP_OFF(status));
- }
-}
-#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
-
-/*
- * Handshake MDMA
- */
-#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
- __HMDMA(CONTROL, control);
- __HMDMA(ECINIT, ecinit);
- __HMDMA(BCINIT, bcinit);
- __HMDMA(ECURGENT, ecurgent);
- __HMDMA(ECOVERFLOW, ecoverflow);
- __HMDMA(ECOUNT, ecount);
- __HMDMA(BCOUNT, bcount);
-}
-#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
-
-/*
- * Peripheral Interrupts (PINT/GPIO)
- */
-#ifdef PINT0_MASK_SET
-#define __PINT(uname, lname) __REGS(pint, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
- __PINT(MASK_SET, mask_set);
- __PINT(MASK_CLEAR, mask_clear);
- __PINT(REQUEST, request);
- __PINT(ASSIGN, assign);
- __PINT(EDGE_SET, edge_set);
- __PINT(EDGE_CLEAR, edge_clear);
- __PINT(INVERT_SET, invert_set);
- __PINT(INVERT_CLEAR, invert_clear);
- __PINT(PINSTATE, pinstate);
- __PINT(LATCH, latch);
-}
-#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
-#endif
-
-/*
- * Port/GPIO
- */
-#define bfin_gpio_regs gpio_port_t
-#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-#ifdef __ADSPBF54x__
- _buf = REGS_STR_PFX_C(buf, PORT, num);
- __PORT(FER, port_fer);
- __PORT(SET, data_set);
- __PORT(CLEAR, data_clear);
- __PORT(DIR_SET, dir_set);
- __PORT(DIR_CLEAR, dir_clear);
- __PORT(INEN, inen);
- __PORT(MUX, port_mux);
-#else
- _buf = buf + sprintf(buf, "PORT%cIO_", num);
- __PORT(CLEAR, data_clear);
- __PORT(SET, data_set);
- __PORT(TOGGLE, toggle);
- __PORT(MASKA, maska);
- __PORT(MASKA_CLEAR, maska_clear);
- __PORT(MASKA_SET, maska_set);
- __PORT(MASKA_TOGGLE, maska_toggle);
- __PORT(MASKB, maskb);
- __PORT(MASKB_CLEAR, maskb_clear);
- __PORT(MASKB_SET, maskb_set);
- __PORT(MASKB_TOGGLE, maskb_toggle);
- __PORT(DIR, dir);
- __PORT(POLAR, polar);
- __PORT(EDGE, edge);
- __PORT(BOTH, both);
- __PORT(INEN, inen);
-#endif
- _buf[-1] = '\0';
- d(buf, 16, base + REGS_OFF(gpio, data));
-}
-#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
-
-/*
- * PPI
- */
-#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
- __PPI(CONTROL, control);
- __PPI(STATUS, status);
- __PPI(COUNT, count);
- __PPI(DELAY, delay);
- __PPI(FRAME, frame);
-}
-#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
-
-/*
- * SPI
- */
-#define __SPI(uname, lname) __REGS(spi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
- __SPI(CTL, ctl);
- __SPI(FLG, flg);
- __SPI(STAT, stat);
- __SPI(TDBR, tdbr);
- __SPI(RDBR, rdbr);
- __SPI(BAUD, baud);
- __SPI(SHADOW, shadow);
-}
-#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
-
-/*
- * SPORT
- */
-static inline int sport_width(void *mmr)
-{
- unsigned long lmmr = (unsigned long)mmr;
- if ((lmmr & 0xff) == 0x10)
- /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
- lmmr -= 0xc;
- else
- /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
- lmmr += 0xc;
- /* extract SLEN field from control register 2 and add 1 */
- return (bfin_read16(lmmr) & 0x1f) + 1;
-}
-static int sport_set(void *mmr, u64 val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- bfin_write16(mmr, val);
- else
- bfin_write32(mmr, val);
- local_irq_restore(flags);
- return 0;
-}
-static int sport_get(void *mmr, u64 *val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- *val = bfin_read16(mmr);
- else
- *val = bfin_read32(mmr);
- local_irq_restore(flags);
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
-/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
-#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
-#define _D_SPORT(name, perms, fops) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
- } while (0)
-#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
-#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
-#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
-#define __SPORT(name, bits) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
- } while (0)
-static void __init __maybe_unused
-bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
- __SPORT(CHNL, 16);
- __SPORT(MCMC1, 16);
- __SPORT(MCMC2, 16);
- __SPORT(MRCS0, 32);
- __SPORT(MRCS1, 32);
- __SPORT(MRCS2, 32);
- __SPORT(MRCS3, 32);
- __SPORT(MTCS0, 32);
- __SPORT(MTCS1, 32);
- __SPORT(MTCS2, 32);
- __SPORT(MTCS3, 32);
- __SPORT(RCLKDIV, 16);
- __SPORT(RCR1, 16);
- __SPORT(RCR2, 16);
- __SPORT(RFSDIV, 16);
- __SPORT_RW(RX);
- __SPORT(STAT, 16);
- __SPORT(TCLKDIV, 16);
- __SPORT(TCR1, 16);
- __SPORT(TCR2, 16);
- __SPORT(TFSDIV, 16);
- __SPORT_WO(TX);
-}
-#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
-
-/*
- * TWI
- */
-#define __TWI(uname, lname) __REGS(twi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
- __TWI(CLKDIV, clkdiv);
- __TWI(CONTROL, control);
- __TWI(SLAVE_CTL, slave_ctl);
- __TWI(SLAVE_STAT, slave_stat);
- __TWI(SLAVE_ADDR, slave_addr);
- __TWI(MASTER_CTL, master_ctl);
- __TWI(MASTER_STAT, master_stat);
- __TWI(MASTER_ADDR, master_addr);
- __TWI(INT_STAT, int_stat);
- __TWI(INT_MASK, int_mask);
- __TWI(FIFO_CTL, fifo_ctl);
- __TWI(FIFO_STAT, fifo_stat);
- __TWI(XMT_DATA8, xmt_data8);
- __TWI(XMT_DATA16, xmt_data16);
- __TWI(RCV_DATA8, rcv_data8);
- __TWI(RCV_DATA16, rcv_data16);
-}
-#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
-
-/*
- * UART
- */
-#define __UART(uname, lname) __REGS(uart, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
-#ifdef BFIN_UART_BF54X_STYLE
- __UART(DLL, dll);
- __UART(DLH, dlh);
- __UART(GCTL, gctl);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(IER_SET, ier_set);
- __UART(IER_CLEAR, ier_clear);
- __UART(THR, thr);
- __UART(RBR, rbr);
-#else
- __UART(DLL, dll);
- __UART(THR, thr);
- __UART(RBR, rbr);
- __UART(DLH, dlh);
- __UART(IER, ier);
- __UART(IIR, iir);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(GCTL, gctl);
-#endif
-}
-#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
-#endif /* CONFIG_BF60x */
-/*
- * The actual debugfs generation
- */
-static struct dentry *debug_mmrs_dentry;
-
-static int __init bfin_debug_mmrs_init(void)
-{
- struct dentry *top, *parent;
-
- pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
-
- top = debugfs_create_dir("blackfin", NULL);
- if (top == NULL)
- return -1;
-
- parent = debugfs_create_dir("core_regs", top);
- debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
- debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
- debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
- D_SYSREG(cycles);
- D_SYSREG(cycles2);
- D_SYSREG(emudat);
- D_SYSREG(seqstat);
- D_SYSREG(syscfg);
-
- /* Core MMRs */
- parent = debugfs_create_dir("ctimer", top);
- D32(TCNTL);
- D32(TCOUNT);
- D32(TPERIOD);
- D32(TSCALE);
-
- parent = debugfs_create_dir("cec", top);
- D32(EVT0);
- D32(EVT1);
- D32(EVT2);
- D32(EVT3);
- D32(EVT4);
- D32(EVT5);
- D32(EVT6);
- D32(EVT7);
- D32(EVT8);
- D32(EVT9);
- D32(EVT10);
- D32(EVT11);
- D32(EVT12);
- D32(EVT13);
- D32(EVT14);
- D32(EVT15);
- D32(EVT_OVERRIDE);
- D32(IMASK);
- D32(IPEND);
- D32(ILAT);
- D32(IPRIO);
-
- parent = debugfs_create_dir("debug", top);
- D32(DBGSTAT);
- D32(DSPID);
-
- parent = debugfs_create_dir("mmu", top);
- D32(SRAM_BASE_ADDRESS);
- D32(DCPLB_ADDR0);
- D32(DCPLB_ADDR10);
- D32(DCPLB_ADDR11);
- D32(DCPLB_ADDR12);
- D32(DCPLB_ADDR13);
- D32(DCPLB_ADDR14);
- D32(DCPLB_ADDR15);
- D32(DCPLB_ADDR1);
- D32(DCPLB_ADDR2);
- D32(DCPLB_ADDR3);
- D32(DCPLB_ADDR4);
- D32(DCPLB_ADDR5);
- D32(DCPLB_ADDR6);
- D32(DCPLB_ADDR7);
- D32(DCPLB_ADDR8);
- D32(DCPLB_ADDR9);
- D32(DCPLB_DATA0);
- D32(DCPLB_DATA10);
- D32(DCPLB_DATA11);
- D32(DCPLB_DATA12);
- D32(DCPLB_DATA13);
- D32(DCPLB_DATA14);
- D32(DCPLB_DATA15);
- D32(DCPLB_DATA1);
- D32(DCPLB_DATA2);
- D32(DCPLB_DATA3);
- D32(DCPLB_DATA4);
- D32(DCPLB_DATA5);
- D32(DCPLB_DATA6);
- D32(DCPLB_DATA7);
- D32(DCPLB_DATA8);
- D32(DCPLB_DATA9);
- D32(DCPLB_FAULT_ADDR);
- D32(DCPLB_STATUS);
- D32(DMEM_CONTROL);
- D32(DTEST_COMMAND);
- D32(DTEST_DATA0);
- D32(DTEST_DATA1);
-
- D32(ICPLB_ADDR0);
- D32(ICPLB_ADDR1);
- D32(ICPLB_ADDR2);
- D32(ICPLB_ADDR3);
- D32(ICPLB_ADDR4);
- D32(ICPLB_ADDR5);
- D32(ICPLB_ADDR6);
- D32(ICPLB_ADDR7);
- D32(ICPLB_ADDR8);
- D32(ICPLB_ADDR9);
- D32(ICPLB_ADDR10);
- D32(ICPLB_ADDR11);
- D32(ICPLB_ADDR12);
- D32(ICPLB_ADDR13);
- D32(ICPLB_ADDR14);
- D32(ICPLB_ADDR15);
- D32(ICPLB_DATA0);
- D32(ICPLB_DATA1);
- D32(ICPLB_DATA2);
- D32(ICPLB_DATA3);
- D32(ICPLB_DATA4);
- D32(ICPLB_DATA5);
- D32(ICPLB_DATA6);
- D32(ICPLB_DATA7);
- D32(ICPLB_DATA8);
- D32(ICPLB_DATA9);
- D32(ICPLB_DATA10);
- D32(ICPLB_DATA11);
- D32(ICPLB_DATA12);
- D32(ICPLB_DATA13);
- D32(ICPLB_DATA14);
- D32(ICPLB_DATA15);
- D32(ICPLB_FAULT_ADDR);
- D32(ICPLB_STATUS);
- D32(IMEM_CONTROL);
- if (!ANOMALY_05000481) {
- D32(ITEST_COMMAND);
- D32(ITEST_DATA0);
- D32(ITEST_DATA1);
- }
-
- parent = debugfs_create_dir("perf", top);
- D32(PFCNTR0);
- D32(PFCNTR1);
- D32(PFCTL);
-
- parent = debugfs_create_dir("trace", top);
- D32(TBUF);
- D32(TBUFCTL);
- D32(TBUFSTAT);
-
- parent = debugfs_create_dir("watchpoint", top);
- D32(WPIACTL);
- D32(WPIA0);
- D32(WPIA1);
- D32(WPIA2);
- D32(WPIA3);
- D32(WPIA4);
- D32(WPIA5);
- D32(WPIACNT0);
- D32(WPIACNT1);
- D32(WPIACNT2);
- D32(WPIACNT3);
- D32(WPIACNT4);
- D32(WPIACNT5);
- D32(WPDACTL);
- D32(WPDA0);
- D32(WPDA1);
- D32(WPDACNT0);
- D32(WPDACNT1);
- D32(WPSTAT);
-#ifndef CONFIG_BF60x
- /* System MMRs */
-#ifdef ATAPI_CONTROL
- parent = debugfs_create_dir("atapi", top);
- D16(ATAPI_CONTROL);
- D16(ATAPI_DEV_ADDR);
- D16(ATAPI_DEV_RXBUF);
- D16(ATAPI_DEV_TXBUF);
- D16(ATAPI_DMA_TFRCNT);
- D16(ATAPI_INT_MASK);
- D16(ATAPI_INT_STATUS);
- D16(ATAPI_LINE_STATUS);
- D16(ATAPI_MULTI_TIM_0);
- D16(ATAPI_MULTI_TIM_1);
- D16(ATAPI_MULTI_TIM_2);
- D16(ATAPI_PIO_TFRCNT);
- D16(ATAPI_PIO_TIM_0);
- D16(ATAPI_PIO_TIM_1);
- D16(ATAPI_REG_TIM_0);
- D16(ATAPI_SM_STATE);
- D16(ATAPI_STATUS);
- D16(ATAPI_TERMINATE);
- D16(ATAPI_UDMAOUT_TFRCNT);
- D16(ATAPI_ULTRA_TIM_0);
- D16(ATAPI_ULTRA_TIM_1);
- D16(ATAPI_ULTRA_TIM_2);
- D16(ATAPI_ULTRA_TIM_3);
- D16(ATAPI_UMAIN_TFRCNT);
- D16(ATAPI_XFER_LEN);
-#endif
-
-#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
- parent = debugfs_create_dir("can", top);
-# ifdef CAN_MC1
- bfin_debug_mmrs_can(parent, CAN_MC1, -1);
-# endif
-# ifdef CAN0_MC1
- CAN(0);
-# endif
-# ifdef CAN1_MC1
- CAN(1);
-# endif
-#endif
-
-#ifdef CNT_COMMAND
- parent = debugfs_create_dir("counter", top);
- D16(CNT_COMMAND);
- D16(CNT_CONFIG);
- D32(CNT_COUNTER);
- D16(CNT_DEBOUNCE);
- D16(CNT_IMASK);
- D32(CNT_MAX);
- D32(CNT_MIN);
- D16(CNT_STATUS);
-#endif
-
- parent = debugfs_create_dir("dmac", top);
-#ifdef DMAC_TC_CNT
- D16(DMAC_TC_CNT);
- D16(DMAC_TC_PER);
-#endif
-#ifdef DMAC0_TC_CNT
- D16(DMAC0_TC_CNT);
- D16(DMAC0_TC_PER);
-#endif
-#ifdef DMAC1_TC_CNT
- D16(DMAC1_TC_CNT);
- D16(DMAC1_TC_PER);
-#endif
-#ifdef DMAC1_PERIMUX
- D16(DMAC1_PERIMUX);
-#endif
-
-#ifdef __ADSPBF561__
- /* XXX: should rewrite the MMR map */
-# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
-# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
-# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
-# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
-# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
-# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
-# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
-# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
-# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
-# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
-# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
-# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
-# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
-# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
-# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
-# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
-# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
-# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
-# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
-# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
-# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
-# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
-# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
-# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
-#endif
- parent = debugfs_create_dir("dma", top);
- DMA(0);
- DMA(1);
- DMA(1);
- DMA(2);
- DMA(3);
- DMA(4);
- DMA(5);
- DMA(6);
- DMA(7);
-#ifdef DMA8_NEXT_DESC_PTR
- DMA(8);
- DMA(9);
- DMA(10);
- DMA(11);
-#endif
-#ifdef DMA12_NEXT_DESC_PTR
- DMA(12);
- DMA(13);
- DMA(14);
- DMA(15);
- DMA(16);
- DMA(17);
- DMA(18);
- DMA(19);
-#endif
-#ifdef DMA20_NEXT_DESC_PTR
- DMA(20);
- DMA(21);
- DMA(22);
- DMA(23);
-#endif
-
- parent = debugfs_create_dir("ebiu_amc", top);
- D32(EBIU_AMBCTL0);
- D32(EBIU_AMBCTL1);
- D16(EBIU_AMGCTL);
-#ifdef EBIU_MBSCTL
- D16(EBIU_MBSCTL);
- D32(EBIU_ARBSTAT);
- D32(EBIU_MODE);
- D16(EBIU_FCTL);
-#endif
-
-#ifdef EBIU_SDGCTL
- parent = debugfs_create_dir("ebiu_sdram", top);
-# ifdef __ADSPBF561__
- D32(EBIU_SDBCTL);
-# else
- D16(EBIU_SDBCTL);
-# endif
- D32(EBIU_SDGCTL);
- D16(EBIU_SDRRC);
- D16(EBIU_SDSTAT);
-#endif
-
-#ifdef EBIU_DDRACCT
- parent = debugfs_create_dir("ebiu_ddr", top);
- D32(EBIU_DDRACCT);
- D32(EBIU_DDRARCT);
- D32(EBIU_DDRBRC0);
- D32(EBIU_DDRBRC1);
- D32(EBIU_DDRBRC2);
- D32(EBIU_DDRBRC3);
- D32(EBIU_DDRBRC4);
- D32(EBIU_DDRBRC5);
- D32(EBIU_DDRBRC6);
- D32(EBIU_DDRBRC7);
- D32(EBIU_DDRBWC0);
- D32(EBIU_DDRBWC1);
- D32(EBIU_DDRBWC2);
- D32(EBIU_DDRBWC3);
- D32(EBIU_DDRBWC4);
- D32(EBIU_DDRBWC5);
- D32(EBIU_DDRBWC6);
- D32(EBIU_DDRBWC7);
- D32(EBIU_DDRCTL0);
- D32(EBIU_DDRCTL1);
- D32(EBIU_DDRCTL2);
- D32(EBIU_DDRCTL3);
- D32(EBIU_DDRGC0);
- D32(EBIU_DDRGC1);
- D32(EBIU_DDRGC2);
- D32(EBIU_DDRGC3);
- D32(EBIU_DDRMCCL);
- D32(EBIU_DDRMCEN);
- D32(EBIU_DDRQUE);
- D32(EBIU_DDRTACT);
- D32(EBIU_ERRADD);
- D16(EBIU_ERRMST);
- D16(EBIU_RSTCTL);
-#endif
-
-#ifdef EMAC_ADDRHI
- parent = debugfs_create_dir("emac", top);
- D32(EMAC_ADDRHI);
- D32(EMAC_ADDRLO);
- D32(EMAC_FLC);
- D32(EMAC_HASHHI);
- D32(EMAC_HASHLO);
- D32(EMAC_MMC_CTL);
- D32(EMAC_MMC_RIRQE);
- D32(EMAC_MMC_RIRQS);
- D32(EMAC_MMC_TIRQE);
- D32(EMAC_MMC_TIRQS);
- D32(EMAC_OPMODE);
- D32(EMAC_RXC_ALIGN);
- D32(EMAC_RXC_ALLFRM);
- D32(EMAC_RXC_ALLOCT);
- D32(EMAC_RXC_BROAD);
- D32(EMAC_RXC_DMAOVF);
- D32(EMAC_RXC_EQ64);
- D32(EMAC_RXC_FCS);
- D32(EMAC_RXC_GE1024);
- D32(EMAC_RXC_LNERRI);
- D32(EMAC_RXC_LNERRO);
- D32(EMAC_RXC_LONG);
- D32(EMAC_RXC_LT1024);
- D32(EMAC_RXC_LT128);
- D32(EMAC_RXC_LT256);
- D32(EMAC_RXC_LT512);
- D32(EMAC_RXC_MACCTL);
- D32(EMAC_RXC_MULTI);
- D32(EMAC_RXC_OCTET);
- D32(EMAC_RXC_OK);
- D32(EMAC_RXC_OPCODE);
- D32(EMAC_RXC_PAUSE);
- D32(EMAC_RXC_SHORT);
- D32(EMAC_RXC_TYPED);
- D32(EMAC_RXC_UNICST);
- D32(EMAC_RX_IRQE);
- D32(EMAC_RX_STAT);
- D32(EMAC_RX_STKY);
- D32(EMAC_STAADD);
- D32(EMAC_STADAT);
- D32(EMAC_SYSCTL);
- D32(EMAC_SYSTAT);
- D32(EMAC_TXC_1COL);
- D32(EMAC_TXC_ABORT);
- D32(EMAC_TXC_ALLFRM);
- D32(EMAC_TXC_ALLOCT);
- D32(EMAC_TXC_BROAD);
- D32(EMAC_TXC_CRSERR);
- D32(EMAC_TXC_DEFER);
- D32(EMAC_TXC_DMAUND);
- D32(EMAC_TXC_EQ64);
- D32(EMAC_TXC_GE1024);
- D32(EMAC_TXC_GT1COL);
- D32(EMAC_TXC_LATECL);
- D32(EMAC_TXC_LT1024);
- D32(EMAC_TXC_LT128);
- D32(EMAC_TXC_LT256);
- D32(EMAC_TXC_LT512);
- D32(EMAC_TXC_MACCTL);
- D32(EMAC_TXC_MULTI);
- D32(EMAC_TXC_OCTET);
- D32(EMAC_TXC_OK);
- D32(EMAC_TXC_UNICST);
- D32(EMAC_TXC_XS_COL);
- D32(EMAC_TXC_XS_DFR);
- D32(EMAC_TX_IRQE);
- D32(EMAC_TX_STAT);
- D32(EMAC_TX_STKY);
- D32(EMAC_VLAN1);
- D32(EMAC_VLAN2);
- D32(EMAC_WKUP_CTL);
- D32(EMAC_WKUP_FFCMD);
- D32(EMAC_WKUP_FFCRC0);
- D32(EMAC_WKUP_FFCRC1);
- D32(EMAC_WKUP_FFMSK0);
- D32(EMAC_WKUP_FFMSK1);
- D32(EMAC_WKUP_FFMSK2);
- D32(EMAC_WKUP_FFMSK3);
- D32(EMAC_WKUP_FFOFF);
-# ifdef EMAC_PTP_ACCR
- D32(EMAC_PTP_ACCR);
- D32(EMAC_PTP_ADDEND);
- D32(EMAC_PTP_ALARMHI);
- D32(EMAC_PTP_ALARMLO);
- D16(EMAC_PTP_CTL);
- D32(EMAC_PTP_FOFF);
- D32(EMAC_PTP_FV1);
- D32(EMAC_PTP_FV2);
- D32(EMAC_PTP_FV3);
- D16(EMAC_PTP_ID_OFF);
- D32(EMAC_PTP_ID_SNAP);
- D16(EMAC_PTP_IE);
- D16(EMAC_PTP_ISTAT);
- D32(EMAC_PTP_OFFSET);
- D32(EMAC_PTP_PPS_PERIOD);
- D32(EMAC_PTP_PPS_STARTHI);
- D32(EMAC_PTP_PPS_STARTLO);
- D32(EMAC_PTP_RXSNAPHI);
- D32(EMAC_PTP_RXSNAPLO);
- D32(EMAC_PTP_TIMEHI);
- D32(EMAC_PTP_TIMELO);
- D32(EMAC_PTP_TXSNAPHI);
- D32(EMAC_PTP_TXSNAPLO);
-# endif
-#endif
-
-#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
- parent = debugfs_create_dir("eppi", top);
-# ifdef EPPI0_STATUS
- EPPI(0);
-# endif
-# ifdef EPPI1_STATUS
- EPPI(1);
-# endif
-# ifdef EPPI2_STATUS
- EPPI(2);
-# endif
-#endif
-
- parent = debugfs_create_dir("gptimer", top);
-#ifdef TIMER_ENABLE
- GPTIMER_GROUP(TIMER_ENABLE, -1);
-#endif
-#ifdef TIMER_ENABLE0
- GPTIMER_GROUP(TIMER_ENABLE0, 0);
-#endif
-#ifdef TIMER_ENABLE1
- GPTIMER_GROUP(TIMER_ENABLE1, 1);
-#endif
- /* XXX: Should convert BF561 MMR names */
-#ifdef TMRS4_DISABLE
- GPTIMER_GROUP(TMRS4_ENABLE, 0);
- GPTIMER_GROUP(TMRS8_ENABLE, 1);
-#endif
- GPTIMER(0);
- GPTIMER(1);
- GPTIMER(2);
-#ifdef TIMER3_CONFIG
- GPTIMER(3);
- GPTIMER(4);
- GPTIMER(5);
- GPTIMER(6);
- GPTIMER(7);
-#endif
-#ifdef TIMER8_CONFIG
- GPTIMER(8);
- GPTIMER(9);
- GPTIMER(10);
-#endif
-#ifdef TIMER11_CONFIG
- GPTIMER(11);
-#endif
-
-#ifdef HMDMA0_CONTROL
- parent = debugfs_create_dir("hmdma", top);
- HMDMA(0);
- HMDMA(1);
-#endif
-
-#ifdef HOST_CONTROL
- parent = debugfs_create_dir("hostdp", top);
- D16(HOST_CONTROL);
- D16(HOST_STATUS);
- D16(HOST_TIMEOUT);
-#endif
-
-#ifdef IMDMA_S0_CONFIG
- parent = debugfs_create_dir("imdma", top);
- IMDMA(0);
- IMDMA(1);
-#endif
-
-#ifdef KPAD_CTL
- parent = debugfs_create_dir("keypad", top);
- D16(KPAD_CTL);
- D16(KPAD_PRESCALE);
- D16(KPAD_MSEL);
- D16(KPAD_ROWCOL);
- D16(KPAD_STAT);
- D16(KPAD_SOFTEVAL);
-#endif
-
- parent = debugfs_create_dir("mdma", top);
- MDMA(0);
- MDMA(1);
-#ifdef MDMA_D2_CONFIG
- MDMA(2);
- MDMA(3);
-#endif
-
-#ifdef MXVR_CONFIG
- parent = debugfs_create_dir("mxvr", top);
- D16(MXVR_CONFIG);
-# ifdef MXVR_PLL_CTL_0
- D32(MXVR_PLL_CTL_0);
-# endif
- D32(MXVR_STATE_0);
- D32(MXVR_STATE_1);
- D32(MXVR_INT_STAT_0);
- D32(MXVR_INT_STAT_1);
- D32(MXVR_INT_EN_0);
- D32(MXVR_INT_EN_1);
- D16(MXVR_POSITION);
- D16(MXVR_MAX_POSITION);
- D16(MXVR_DELAY);
- D16(MXVR_MAX_DELAY);
- D32(MXVR_LADDR);
- D16(MXVR_GADDR);
- D32(MXVR_AADDR);
- D32(MXVR_ALLOC_0);
- D32(MXVR_ALLOC_1);
- D32(MXVR_ALLOC_2);
- D32(MXVR_ALLOC_3);
- D32(MXVR_ALLOC_4);
- D32(MXVR_ALLOC_5);
- D32(MXVR_ALLOC_6);
- D32(MXVR_ALLOC_7);
- D32(MXVR_ALLOC_8);
- D32(MXVR_ALLOC_9);
- D32(MXVR_ALLOC_10);
- D32(MXVR_ALLOC_11);
- D32(MXVR_ALLOC_12);
- D32(MXVR_ALLOC_13);
- D32(MXVR_ALLOC_14);
- D32(MXVR_SYNC_LCHAN_0);
- D32(MXVR_SYNC_LCHAN_1);
- D32(MXVR_SYNC_LCHAN_2);
- D32(MXVR_SYNC_LCHAN_3);
- D32(MXVR_SYNC_LCHAN_4);
- D32(MXVR_SYNC_LCHAN_5);
- D32(MXVR_SYNC_LCHAN_6);
- D32(MXVR_SYNC_LCHAN_7);
- D32(MXVR_DMA0_CONFIG);
- D32(MXVR_DMA0_START_ADDR);
- D16(MXVR_DMA0_COUNT);
- D32(MXVR_DMA0_CURR_ADDR);
- D16(MXVR_DMA0_CURR_COUNT);
- D32(MXVR_DMA1_CONFIG);
- D32(MXVR_DMA1_START_ADDR);
- D16(MXVR_DMA1_COUNT);
- D32(MXVR_DMA1_CURR_ADDR);
- D16(MXVR_DMA1_CURR_COUNT);
- D32(MXVR_DMA2_CONFIG);
- D32(MXVR_DMA2_START_ADDR);
- D16(MXVR_DMA2_COUNT);
- D32(MXVR_DMA2_CURR_ADDR);
- D16(MXVR_DMA2_CURR_COUNT);
- D32(MXVR_DMA3_CONFIG);
- D32(MXVR_DMA3_START_ADDR);
- D16(MXVR_DMA3_COUNT);
- D32(MXVR_DMA3_CURR_ADDR);
- D16(MXVR_DMA3_CURR_COUNT);
- D32(MXVR_DMA4_CONFIG);
- D32(MXVR_DMA4_START_ADDR);
- D16(MXVR_DMA4_COUNT);
- D32(MXVR_DMA4_CURR_ADDR);
- D16(MXVR_DMA4_CURR_COUNT);
- D32(MXVR_DMA5_CONFIG);
- D32(MXVR_DMA5_START_ADDR);
- D16(MXVR_DMA5_COUNT);
- D32(MXVR_DMA5_CURR_ADDR);
- D16(MXVR_DMA5_CURR_COUNT);
- D32(MXVR_DMA6_CONFIG);
- D32(MXVR_DMA6_START_ADDR);
- D16(MXVR_DMA6_COUNT);
- D32(MXVR_DMA6_CURR_ADDR);
- D16(MXVR_DMA6_CURR_COUNT);
- D32(MXVR_DMA7_CONFIG);
- D32(MXVR_DMA7_START_ADDR);
- D16(MXVR_DMA7_COUNT);
- D32(MXVR_DMA7_CURR_ADDR);
- D16(MXVR_DMA7_CURR_COUNT);
- D16(MXVR_AP_CTL);
- D32(MXVR_APRB_START_ADDR);
- D32(MXVR_APRB_CURR_ADDR);
- D32(MXVR_APTB_START_ADDR);
- D32(MXVR_APTB_CURR_ADDR);
- D32(MXVR_CM_CTL);
- D32(MXVR_CMRB_START_ADDR);
- D32(MXVR_CMRB_CURR_ADDR);
- D32(MXVR_CMTB_START_ADDR);
- D32(MXVR_CMTB_CURR_ADDR);
- D32(MXVR_RRDB_START_ADDR);
- D32(MXVR_RRDB_CURR_ADDR);
- D32(MXVR_PAT_DATA_0);
- D32(MXVR_PAT_EN_0);
- D32(MXVR_PAT_DATA_1);
- D32(MXVR_PAT_EN_1);
- D16(MXVR_FRAME_CNT_0);
- D16(MXVR_FRAME_CNT_1);
- D32(MXVR_ROUTING_0);
- D32(MXVR_ROUTING_1);
- D32(MXVR_ROUTING_2);
- D32(MXVR_ROUTING_3);
- D32(MXVR_ROUTING_4);
- D32(MXVR_ROUTING_5);
- D32(MXVR_ROUTING_6);
- D32(MXVR_ROUTING_7);
- D32(MXVR_ROUTING_8);
- D32(MXVR_ROUTING_9);
- D32(MXVR_ROUTING_10);
- D32(MXVR_ROUTING_11);
- D32(MXVR_ROUTING_12);
- D32(MXVR_ROUTING_13);
- D32(MXVR_ROUTING_14);
-# ifdef MXVR_PLL_CTL_1
- D32(MXVR_PLL_CTL_1);
-# endif
- D16(MXVR_BLOCK_CNT);
-# ifdef MXVR_CLK_CTL
- D32(MXVR_CLK_CTL);
-# endif
-# ifdef MXVR_CDRPLL_CTL
- D32(MXVR_CDRPLL_CTL);
-# endif
-# ifdef MXVR_FMPLL_CTL
- D32(MXVR_FMPLL_CTL);
-# endif
-# ifdef MXVR_PIN_CTL
- D16(MXVR_PIN_CTL);
-# endif
-# ifdef MXVR_SCLK_CNT
- D16(MXVR_SCLK_CNT);
-# endif
-#endif
-
-#ifdef NFC_ADDR
- parent = debugfs_create_dir("nfc", top);
- D_WO(NFC_ADDR, 16);
- D_WO(NFC_CMD, 16);
- D_RO(NFC_COUNT, 16);
- D16(NFC_CTL);
- D_WO(NFC_DATA_RD, 16);
- D_WO(NFC_DATA_WR, 16);
- D_RO(NFC_ECC0, 16);
- D_RO(NFC_ECC1, 16);
- D_RO(NFC_ECC2, 16);
- D_RO(NFC_ECC3, 16);
- D16(NFC_IRQMASK);
- D16(NFC_IRQSTAT);
- D_WO(NFC_PGCTL, 16);
- D_RO(NFC_READ, 16);
- D16(NFC_RST);
- D_RO(NFC_STAT, 16);
-#endif
-
-#ifdef OTP_CONTROL
- parent = debugfs_create_dir("otp", top);
- D16(OTP_CONTROL);
- D16(OTP_BEN);
- D16(OTP_STATUS);
- D32(OTP_TIMING);
- D32(OTP_DATA0);
- D32(OTP_DATA1);
- D32(OTP_DATA2);
- D32(OTP_DATA3);
-#endif
-
-#ifdef PINT0_MASK_SET
- parent = debugfs_create_dir("pint", top);
- PINT(0);
- PINT(1);
- PINT(2);
- PINT(3);
-#endif
-
-#ifdef PIXC_CTL
- parent = debugfs_create_dir("pixc", top);
- D16(PIXC_CTL);
- D16(PIXC_PPL);
- D16(PIXC_LPF);
- D16(PIXC_AHSTART);
- D16(PIXC_AHEND);
- D16(PIXC_AVSTART);
- D16(PIXC_AVEND);
- D16(PIXC_ATRANSP);
- D16(PIXC_BHSTART);
- D16(PIXC_BHEND);
- D16(PIXC_BVSTART);
- D16(PIXC_BVEND);
- D16(PIXC_BTRANSP);
- D16(PIXC_INTRSTAT);
- D32(PIXC_RYCON);
- D32(PIXC_GUCON);
- D32(PIXC_BVCON);
- D32(PIXC_CCBIAS);
- D32(PIXC_TC);
-#endif
-
- parent = debugfs_create_dir("pll", top);
- D16(PLL_CTL);
- D16(PLL_DIV);
- D16(PLL_LOCKCNT);
- D16(PLL_STAT);
- D16(VR_CTL);
- D32(CHIPID); /* it's part of this hardware block */
-
-#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
- parent = debugfs_create_dir("ppi", top);
-# ifdef PPI_CONTROL
- bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
-# endif
-# ifdef PPI0_CONTROL
- PPI(0);
-# endif
-# ifdef PPI1_CONTROL
- PPI(1);
-# endif
-#endif
-
-#ifdef PWM_CTRL
- parent = debugfs_create_dir("pwm", top);
- D16(PWM_CTRL);
- D16(PWM_STAT);
- D16(PWM_TM);
- D16(PWM_DT);
- D16(PWM_GATE);
- D16(PWM_CHA);
- D16(PWM_CHB);
- D16(PWM_CHC);
- D16(PWM_SEG);
- D16(PWM_SYNCWT);
- D16(PWM_CHAL);
- D16(PWM_CHBL);
- D16(PWM_CHCL);
- D16(PWM_LSI);
- D16(PWM_STAT2);
-#endif
-
-#ifdef RSI_CONFIG
- parent = debugfs_create_dir("rsi", top);
- D32(RSI_ARGUMENT);
- D16(RSI_CEATA_CONTROL);
- D16(RSI_CLK_CONTROL);
- D16(RSI_COMMAND);
- D16(RSI_CONFIG);
- D16(RSI_DATA_CNT);
- D16(RSI_DATA_CONTROL);
- D16(RSI_DATA_LGTH);
- D32(RSI_DATA_TIMER);
- D16(RSI_EMASK);
- D16(RSI_ESTAT);
- D32(RSI_FIFO);
- D16(RSI_FIFO_CNT);
- D32(RSI_MASK0);
- D32(RSI_MASK1);
- D16(RSI_PID0);
- D16(RSI_PID1);
- D16(RSI_PID2);
- D16(RSI_PID3);
- D16(RSI_PID4);
- D16(RSI_PID5);
- D16(RSI_PID6);
- D16(RSI_PID7);
- D16(RSI_PWR_CONTROL);
- D16(RSI_RD_WAIT_EN);
- D32(RSI_RESPONSE0);
- D32(RSI_RESPONSE1);
- D32(RSI_RESPONSE2);
- D32(RSI_RESPONSE3);
- D16(RSI_RESP_CMD);
- D32(RSI_STATUS);
- D_WO(RSI_STATUSCL, 16);
-#endif
-
-#ifdef RTC_ALARM
- parent = debugfs_create_dir("rtc", top);
- D32(RTC_ALARM);
- D16(RTC_ICTL);
- D16(RTC_ISTAT);
- D16(RTC_PREN);
- D32(RTC_STAT);
- D16(RTC_SWCNT);
-#endif
-
-#ifdef SDH_CFG
- parent = debugfs_create_dir("sdh", top);
- D32(SDH_ARGUMENT);
- D16(SDH_CFG);
- D16(SDH_CLK_CTL);
- D16(SDH_COMMAND);
- D_RO(SDH_DATA_CNT, 16);
- D16(SDH_DATA_CTL);
- D16(SDH_DATA_LGTH);
- D32(SDH_DATA_TIMER);
- D16(SDH_E_MASK);
- D16(SDH_E_STATUS);
- D32(SDH_FIFO);
- D_RO(SDH_FIFO_CNT, 16);
- D32(SDH_MASK0);
- D32(SDH_MASK1);
- D_RO(SDH_PID0, 16);
- D_RO(SDH_PID1, 16);
- D_RO(SDH_PID2, 16);
- D_RO(SDH_PID3, 16);
- D_RO(SDH_PID4, 16);
- D_RO(SDH_PID5, 16);
- D_RO(SDH_PID6, 16);
- D_RO(SDH_PID7, 16);
- D16(SDH_PWR_CTL);
- D16(SDH_RD_WAIT_EN);
- D_RO(SDH_RESPONSE0, 32);
- D_RO(SDH_RESPONSE1, 32);
- D_RO(SDH_RESPONSE2, 32);
- D_RO(SDH_RESPONSE3, 32);
- D_RO(SDH_RESP_CMD, 16);
- D_RO(SDH_STATUS, 32);
- D_WO(SDH_STATUS_CLR, 16);
-#endif
-
-#ifdef SECURE_CONTROL
- parent = debugfs_create_dir("security", top);
- D16(SECURE_CONTROL);
- D16(SECURE_STATUS);
- D32(SECURE_SYSSWT);
-#endif
-
- parent = debugfs_create_dir("sic", top);
- D16(SWRST);
- D16(SYSCR);
- D16(SIC_RVECT);
- D32(SIC_IAR0);
- D32(SIC_IAR1);
- D32(SIC_IAR2);
-#ifdef SIC_IAR3
- D32(SIC_IAR3);
-#endif
-#ifdef SIC_IAR4
- D32(SIC_IAR4);
- D32(SIC_IAR5);
- D32(SIC_IAR6);
-#endif
-#ifdef SIC_IAR7
- D32(SIC_IAR7);
-#endif
-#ifdef SIC_IAR8
- D32(SIC_IAR8);
- D32(SIC_IAR9);
- D32(SIC_IAR10);
- D32(SIC_IAR11);
-#endif
-#ifdef SIC_IMASK
- D32(SIC_IMASK);
- D32(SIC_ISR);
- D32(SIC_IWR);
-#endif
-#ifdef SIC_IMASK0
- D32(SIC_IMASK0);
- D32(SIC_IMASK1);
- D32(SIC_ISR0);
- D32(SIC_ISR1);
- D32(SIC_IWR0);
- D32(SIC_IWR1);
-#endif
-#ifdef SIC_IMASK2
- D32(SIC_IMASK2);
- D32(SIC_ISR2);
- D32(SIC_IWR2);
-#endif
-#ifdef SICB_RVECT
- D16(SICB_SWRST);
- D16(SICB_SYSCR);
- D16(SICB_RVECT);
- D32(SICB_IAR0);
- D32(SICB_IAR1);
- D32(SICB_IAR2);
- D32(SICB_IAR3);
- D32(SICB_IAR4);
- D32(SICB_IAR5);
- D32(SICB_IAR6);
- D32(SICB_IAR7);
- D32(SICB_IMASK0);
- D32(SICB_IMASK1);
- D32(SICB_ISR0);
- D32(SICB_ISR1);
- D32(SICB_IWR0);
- D32(SICB_IWR1);
-#endif
-
- parent = debugfs_create_dir("spi", top);
-#ifdef SPI0_REGBASE
- SPI(0);
-#endif
-#ifdef SPI1_REGBASE
- SPI(1);
-#endif
-#ifdef SPI2_REGBASE
- SPI(2);
-#endif
-
- parent = debugfs_create_dir("sport", top);
-#ifdef SPORT0_STAT
- SPORT(0);
-#endif
-#ifdef SPORT1_STAT
- SPORT(1);
-#endif
-#ifdef SPORT2_STAT
- SPORT(2);
-#endif
-#ifdef SPORT3_STAT
- SPORT(3);
-#endif
-
-#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
- parent = debugfs_create_dir("twi", top);
-# ifdef TWI_CLKDIV
- bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
-# endif
-# ifdef TWI0_CLKDIV
- TWI(0);
-# endif
-# ifdef TWI1_CLKDIV
- TWI(1);
-# endif
-#endif
-
- parent = debugfs_create_dir("uart", top);
-#ifdef BFIN_UART_DLL
- bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
-#endif
-#ifdef UART0_DLL
- UART(0);
-#endif
-#ifdef UART1_DLL
- UART(1);
-#endif
-#ifdef UART2_DLL
- UART(2);
-#endif
-#ifdef UART3_DLL
- UART(3);
-#endif
-
-#ifdef USB_FADDR
- parent = debugfs_create_dir("usb", top);
- D16(USB_FADDR);
- D16(USB_POWER);
- D16(USB_INTRTX);
- D16(USB_INTRRX);
- D16(USB_INTRTXE);
- D16(USB_INTRRXE);
- D16(USB_INTRUSB);
- D16(USB_INTRUSBE);
- D16(USB_FRAME);
- D16(USB_INDEX);
- D16(USB_TESTMODE);
- D16(USB_GLOBINTR);
- D16(USB_GLOBAL_CTL);
- D16(USB_TX_MAX_PACKET);
- D16(USB_CSR0);
- D16(USB_TXCSR);
- D16(USB_RX_MAX_PACKET);
- D16(USB_RXCSR);
- D16(USB_COUNT0);
- D16(USB_RXCOUNT);
- D16(USB_TXTYPE);
- D16(USB_NAKLIMIT0);
- D16(USB_TXINTERVAL);
- D16(USB_RXTYPE);
- D16(USB_RXINTERVAL);
- D16(USB_TXCOUNT);
- D16(USB_EP0_FIFO);
- D16(USB_EP1_FIFO);
- D16(USB_EP2_FIFO);
- D16(USB_EP3_FIFO);
- D16(USB_EP4_FIFO);
- D16(USB_EP5_FIFO);
- D16(USB_EP6_FIFO);
- D16(USB_EP7_FIFO);
- D16(USB_OTG_DEV_CTL);
- D16(USB_OTG_VBUS_IRQ);
- D16(USB_OTG_VBUS_MASK);
- D16(USB_LINKINFO);
- D16(USB_VPLEN);
- D16(USB_HS_EOF1);
- D16(USB_FS_EOF1);
- D16(USB_LS_EOF1);
- D16(USB_APHY_CNTRL);
- D16(USB_APHY_CALIB);
- D16(USB_APHY_CNTRL2);
- D16(USB_PLLOSC_CTRL);
- D16(USB_SRP_CLKDIV);
- D16(USB_EP_NI0_TXMAXP);
- D16(USB_EP_NI0_TXCSR);
- D16(USB_EP_NI0_RXMAXP);
- D16(USB_EP_NI0_RXCSR);
- D16(USB_EP_NI0_RXCOUNT);
- D16(USB_EP_NI0_TXTYPE);
- D16(USB_EP_NI0_TXINTERVAL);
- D16(USB_EP_NI0_RXTYPE);
- D16(USB_EP_NI0_RXINTERVAL);
- D16(USB_EP_NI0_TXCOUNT);
- D16(USB_EP_NI1_TXMAXP);
- D16(USB_EP_NI1_TXCSR);
- D16(USB_EP_NI1_RXMAXP);
- D16(USB_EP_NI1_RXCSR);
- D16(USB_EP_NI1_RXCOUNT);
- D16(USB_EP_NI1_TXTYPE);
- D16(USB_EP_NI1_TXINTERVAL);
- D16(USB_EP_NI1_RXTYPE);
- D16(USB_EP_NI1_RXINTERVAL);
- D16(USB_EP_NI1_TXCOUNT);
- D16(USB_EP_NI2_TXMAXP);
- D16(USB_EP_NI2_TXCSR);
- D16(USB_EP_NI2_RXMAXP);
- D16(USB_EP_NI2_RXCSR);
- D16(USB_EP_NI2_RXCOUNT);
- D16(USB_EP_NI2_TXTYPE);
- D16(USB_EP_NI2_TXINTERVAL);
- D16(USB_EP_NI2_RXTYPE);
- D16(USB_EP_NI2_RXINTERVAL);
- D16(USB_EP_NI2_TXCOUNT);
- D16(USB_EP_NI3_TXMAXP);
- D16(USB_EP_NI3_TXCSR);
- D16(USB_EP_NI3_RXMAXP);
- D16(USB_EP_NI3_RXCSR);
- D16(USB_EP_NI3_RXCOUNT);
- D16(USB_EP_NI3_TXTYPE);
- D16(USB_EP_NI3_TXINTERVAL);
- D16(USB_EP_NI3_RXTYPE);
- D16(USB_EP_NI3_RXINTERVAL);
- D16(USB_EP_NI3_TXCOUNT);
- D16(USB_EP_NI4_TXMAXP);
- D16(USB_EP_NI4_TXCSR);
- D16(USB_EP_NI4_RXMAXP);
- D16(USB_EP_NI4_RXCSR);
- D16(USB_EP_NI4_RXCOUNT);
- D16(USB_EP_NI4_TXTYPE);
- D16(USB_EP_NI4_TXINTERVAL);
- D16(USB_EP_NI4_RXTYPE);
- D16(USB_EP_NI4_RXINTERVAL);
- D16(USB_EP_NI4_TXCOUNT);
- D16(USB_EP_NI5_TXMAXP);
- D16(USB_EP_NI5_TXCSR);
- D16(USB_EP_NI5_RXMAXP);
- D16(USB_EP_NI5_RXCSR);
- D16(USB_EP_NI5_RXCOUNT);
- D16(USB_EP_NI5_TXTYPE);
- D16(USB_EP_NI5_TXINTERVAL);
- D16(USB_EP_NI5_RXTYPE);
- D16(USB_EP_NI5_RXINTERVAL);
- D16(USB_EP_NI5_TXCOUNT);
- D16(USB_EP_NI6_TXMAXP);
- D16(USB_EP_NI6_TXCSR);
- D16(USB_EP_NI6_RXMAXP);
- D16(USB_EP_NI6_RXCSR);
- D16(USB_EP_NI6_RXCOUNT);
- D16(USB_EP_NI6_TXTYPE);
- D16(USB_EP_NI6_TXINTERVAL);
- D16(USB_EP_NI6_RXTYPE);
- D16(USB_EP_NI6_RXINTERVAL);
- D16(USB_EP_NI6_TXCOUNT);
- D16(USB_EP_NI7_TXMAXP);
- D16(USB_EP_NI7_TXCSR);
- D16(USB_EP_NI7_RXMAXP);
- D16(USB_EP_NI7_RXCSR);
- D16(USB_EP_NI7_RXCOUNT);
- D16(USB_EP_NI7_TXTYPE);
- D16(USB_EP_NI7_TXINTERVAL);
- D16(USB_EP_NI7_RXTYPE);
- D16(USB_EP_NI7_RXINTERVAL);
- D16(USB_EP_NI7_TXCOUNT);
- D16(USB_DMA_INTERRUPT);
- D16(USB_DMA0CONTROL);
- D16(USB_DMA0ADDRLOW);
- D16(USB_DMA0ADDRHIGH);
- D16(USB_DMA0COUNTLOW);
- D16(USB_DMA0COUNTHIGH);
- D16(USB_DMA1CONTROL);
- D16(USB_DMA1ADDRLOW);
- D16(USB_DMA1ADDRHIGH);
- D16(USB_DMA1COUNTLOW);
- D16(USB_DMA1COUNTHIGH);
- D16(USB_DMA2CONTROL);
- D16(USB_DMA2ADDRLOW);
- D16(USB_DMA2ADDRHIGH);
- D16(USB_DMA2COUNTLOW);
- D16(USB_DMA2COUNTHIGH);
- D16(USB_DMA3CONTROL);
- D16(USB_DMA3ADDRLOW);
- D16(USB_DMA3ADDRHIGH);
- D16(USB_DMA3COUNTLOW);
- D16(USB_DMA3COUNTHIGH);
- D16(USB_DMA4CONTROL);
- D16(USB_DMA4ADDRLOW);
- D16(USB_DMA4ADDRHIGH);
- D16(USB_DMA4COUNTLOW);
- D16(USB_DMA4COUNTHIGH);
- D16(USB_DMA5CONTROL);
- D16(USB_DMA5ADDRLOW);
- D16(USB_DMA5ADDRHIGH);
- D16(USB_DMA5COUNTLOW);
- D16(USB_DMA5COUNTHIGH);
- D16(USB_DMA6CONTROL);
- D16(USB_DMA6ADDRLOW);
- D16(USB_DMA6ADDRHIGH);
- D16(USB_DMA6COUNTLOW);
- D16(USB_DMA6COUNTHIGH);
- D16(USB_DMA7CONTROL);
- D16(USB_DMA7ADDRLOW);
- D16(USB_DMA7ADDRHIGH);
- D16(USB_DMA7COUNTLOW);
- D16(USB_DMA7COUNTHIGH);
-#endif
-
-#ifdef WDOG_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOG_CNT);
- D16(WDOG_CTL);
- D32(WDOG_STAT);
-#endif
-#ifdef WDOGA_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOGA_CNT);
- D16(WDOGA_CTL);
- D32(WDOGA_STAT);
- D32(WDOGB_CNT);
- D16(WDOGB_CTL);
- D32(WDOGB_STAT);
-#endif
-
- /* BF533 glue */
-#ifdef FIO_FLAG_D
-#define PORTFIO FIO_FLAG_D
-#endif
- /* BF561 glue */
-#ifdef FIO0_FLAG_D
-#define PORTFIO FIO0_FLAG_D
-#endif
-#ifdef FIO1_FLAG_D
-#define PORTGIO FIO1_FLAG_D
-#endif
-#ifdef FIO2_FLAG_D
-#define PORTHIO FIO2_FLAG_D
-#endif
- parent = debugfs_create_dir("port", top);
-#ifdef PORTFIO
- PORT(PORTFIO, 'F');
-#endif
-#ifdef PORTGIO
- PORT(PORTGIO, 'G');
-#endif
-#ifdef PORTHIO
- PORT(PORTHIO, 'H');
-#endif
-
-#ifdef __ADSPBF51x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
-#endif /* BF51x */
-
-#ifdef __ADSPBF52x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
- D16(PORTF_SLEW);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
- D16(PORTG_SLEW);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
- D16(PORTH_SLEW);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
- D16(MISCPORT_SLEW);
-#endif /* BF52x */
-
-#ifdef BF537_FAMILY
- D16(PORTF_FER);
- D16(PORTG_FER);
- D16(PORTH_FER);
- D16(PORT_MUX);
-#endif /* BF534 BF536 BF537 */
-
-#ifdef BF538_FAMILY
- D16(PORTCIO_FER);
- D16(PORTCIO);
- D16(PORTCIO_CLEAR);
- D16(PORTCIO_SET);
- D16(PORTCIO_TOGGLE);
- D16(PORTCIO_DIR);
- D16(PORTCIO_INEN);
-
- D16(PORTDIO);
- D16(PORTDIO_CLEAR);
- D16(PORTDIO_DIR);
- D16(PORTDIO_FER);
- D16(PORTDIO_INEN);
- D16(PORTDIO_SET);
- D16(PORTDIO_TOGGLE);
-
- D16(PORTEIO);
- D16(PORTEIO_CLEAR);
- D16(PORTEIO_DIR);
- D16(PORTEIO_FER);
- D16(PORTEIO_INEN);
- D16(PORTEIO_SET);
- D16(PORTEIO_TOGGLE);
-#endif /* BF538 BF539 */
-
-#ifdef __ADSPBF54x__
- {
- int num;
- unsigned long base;
-
- base = PORTA_FER;
- for (num = 0; num < 10; ++num) {
- PORT(base, num);
- base += sizeof(struct bfin_gpio_regs);
- }
-
- }
-#endif /* BF54x */
-#endif /* CONFIG_BF60x */
- debug_mmrs_dentry = top;
-
- return 0;
-}
-module_init(bfin_debug_mmrs_init);
-
-static void __exit bfin_debug_mmrs_exit(void)
-{
- debugfs_remove_recursive(debug_mmrs_dentry);
-}
-module_exit(bfin_debug_mmrs_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
deleted file mode 100644
index 477bb29a7987..000000000000
--- a/arch/blackfin/kernel/dma-mapping.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Dynamic DMA mapping support
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/gfp.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/scatterlist.h>
-#include <linux/export.h>
-#include <linux/bitmap.h>
-
-static spinlock_t dma_page_lock;
-static unsigned long *dma_page;
-static unsigned int dma_pages;
-static unsigned long dma_base;
-static unsigned long dma_size;
-static unsigned int dma_initialized;
-
-static void dma_alloc_init(unsigned long start, unsigned long end)
-{
- spin_lock_init(&dma_page_lock);
- dma_initialized = 0;
-
- dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
- memset(dma_page, 0, PAGE_SIZE);
- dma_base = PAGE_ALIGN(start);
- dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
- dma_pages = dma_size >> PAGE_SHIFT;
- memset((void *)dma_base, 0, DMA_UNCACHED_REGION);
- dma_initialized = 1;
-
- printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __func__,
- dma_page, dma_pages, dma_base);
-}
-
-static inline unsigned int get_pages(size_t size)
-{
- return ((size - 1) >> PAGE_SHIFT) + 1;
-}
-
-static unsigned long __alloc_dma_pages(unsigned int pages)
-{
- unsigned long ret = 0, flags;
- unsigned long start;
-
- if (dma_initialized == 0)
- dma_alloc_init(_ramend - DMA_UNCACHED_REGION, _ramend);
-
- spin_lock_irqsave(&dma_page_lock, flags);
-
- start = bitmap_find_next_zero_area(dma_page, dma_pages, 0, pages, 0);
- if (start < dma_pages) {
- ret = dma_base + (start << PAGE_SHIFT);
- bitmap_set(dma_page, start, pages);
- }
- spin_unlock_irqrestore(&dma_page_lock, flags);
- return ret;
-}
-
-static void __free_dma_pages(unsigned long addr, unsigned int pages)
-{
- unsigned long page = (addr - dma_base) >> PAGE_SHIFT;
- unsigned long flags;
-
- if ((page + pages) > dma_pages) {
- printk(KERN_ERR "%s: freeing outside range.\n", __func__);
- BUG();
- }
-
- spin_lock_irqsave(&dma_page_lock, flags);
- bitmap_clear(dma_page, page, pages);
- spin_unlock_irqrestore(&dma_page_lock, flags);
-}
-
-static void *bfin_dma_alloc(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- void *ret;
-
- ret = (void *)__alloc_dma_pages(get_pages(size));
-
- if (ret) {
- memset(ret, 0, size);
- *dma_handle = virt_to_phys(ret);
- }
-
- return ret;
-}
-
-static void bfin_dma_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- __free_dma_pages((unsigned long)vaddr, get_pages(size));
-}
-
-/*
- * Streaming DMA mappings
- */
-void __dma_sync(dma_addr_t addr, size_t size,
- enum dma_data_direction dir)
-{
- __dma_sync_inline(addr, size, dir);
-}
-EXPORT_SYMBOL(__dma_sync);
-
-static int bfin_dma_map_sg(struct device *dev, struct scatterlist *sg_list,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nents, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
-
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-
- return nents;
-}
-
-static void bfin_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg_list, int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nelems, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-}
-
-static dma_addr_t bfin_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction dir,
- unsigned long attrs)
-{
- dma_addr_t handle = (dma_addr_t)(page_address(page) + offset);
-
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- _dma_sync(handle, size, dir);
-
- return handle;
-}
-
-static inline void bfin_dma_sync_single_for_device(struct device *dev,
- dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
- _dma_sync(handle, size, dir);
-}
-
-const struct dma_map_ops bfin_dma_ops = {
- .alloc = bfin_dma_alloc,
- .free = bfin_dma_free,
-
- .map_page = bfin_dma_map_page,
- .map_sg = bfin_dma_map_sg,
-
- .sync_single_for_device = bfin_dma_sync_single_for_device,
- .sync_sg_for_device = bfin_dma_sync_sg_for_device,
-};
-EXPORT_SYMBOL(bfin_dma_ops);
diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c
deleted file mode 100644
index 3c992c1f8ef2..000000000000
--- a/arch/blackfin/kernel/dumpstack.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Provide basic stack dumping functions
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/debug.h>
-
-#include <asm/trace.h>
-
-/*
- * Checks to see if the address pointed to is either a
- * 16-bit CALL instruction, or a 32-bit CALL instruction
- */
-static bool is_bfin_call(unsigned short *addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, addr))
- return false;
-
- if ((opcode >= 0x0060 && opcode <= 0x0067) ||
- (opcode >= 0x0070 && opcode <= 0x0077) ||
- (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
- return true;
-
- return false;
-
-}
-
-void show_stack(struct task_struct *task, unsigned long *stack)
-{
-#ifdef CONFIG_PRINTK
- unsigned int *addr, *endstack, *fp = 0, *frame;
- unsigned short *ins_addr;
- char buf[150];
- unsigned int i, j, ret_addr, frame_no = 0;
-
- /*
- * If we have been passed a specific stack, use that one otherwise
- * if we have been passed a task structure, use that, otherwise
- * use the stack of where the variable "stack" exists
- */
-
- if (stack == NULL) {
- if (task) {
- /* We know this is a kernel stack, so this is the start/end */
- stack = (unsigned long *)task->thread.ksp;
- endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
- } else {
- /* print out the existing stack info */
- stack = (unsigned long *)&stack;
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
- }
- } else
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
-
- printk(KERN_NOTICE "Stack info:\n");
- decode_address(buf, (unsigned int)stack);
- printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
-
- if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
- printk(KERN_NOTICE "Invalid stack pointer\n");
- return;
- }
-
- /* First thing is to look for a frame pointer */
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
- if (*addr & 0x1)
- continue;
- ins_addr = (unsigned short *)*addr;
- ins_addr--;
- if (is_bfin_call(ins_addr))
- fp = addr - 1;
-
- if (fp) {
- /* Let's check to see if it is a frame pointer */
- while (fp >= (addr - 1) && fp < endstack
- && fp && ((unsigned int) fp & 0x3) == 0)
- fp = (unsigned int *)*fp;
- if (fp == 0 || fp == endstack) {
- fp = addr - 1;
- break;
- }
- fp = 0;
- }
- }
- if (fp) {
- frame = fp;
- printk(KERN_NOTICE " FP: (0x%p)\n", fp);
- } else
- frame = 0;
-
- /*
- * Now that we think we know where things are, we
- * walk the stack again, this time printing things out
- * incase there is no frame pointer, we still look for
- * valid return addresses
- */
-
- /* First time print out data, next time, print out symbols */
- for (j = 0; j <= 1; j++) {
- if (j)
- printk(KERN_NOTICE "Return addresses in stack:\n");
- else
- printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
-
- fp = frame;
- frame_no = 0;
-
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
- addr < endstack; addr++, i++) {
-
- ret_addr = 0;
- if (!j && i % 8 == 0)
- printk(KERN_NOTICE "%p:", addr);
-
- /* if it is an odd address, or zero, just skip it */
- if (*addr & 0x1 || !*addr)
- goto print;
-
- ins_addr = (unsigned short *)*addr;
-
- /* Go back one instruction, and see if it is a CALL */
- ins_addr--;
- ret_addr = is_bfin_call(ins_addr);
- print:
- if (!j && stack == (unsigned long *)addr)
- printk("[%08x]", *addr);
- else if (ret_addr)
- if (j) {
- decode_address(buf, (unsigned int)*addr);
- if (frame == addr) {
- printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
- continue;
- }
- printk(KERN_NOTICE " address : %s\n", buf);
- } else
- printk("<%08x>", *addr);
- else if (fp == addr) {
- if (j)
- frame = addr+1;
- else
- printk("(%08x)", *addr);
-
- fp = (unsigned int *)*addr;
- frame_no++;
-
- } else if (!j)
- printk(" %08x ", *addr);
- }
- if (!j)
- printk("\n");
- }
-#endif
-}
-EXPORT_SYMBOL(show_stack);
-
-void dump_stack(void)
-{
- unsigned long stack;
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags;
-#endif
- trace_buffer_save(tflags);
- dump_bfin_trace_buffer();
- dump_stack_print_info(KERN_DEFAULT);
- show_stack(current, &stack);
- trace_buffer_restore(tflags);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
deleted file mode 100644
index 4b89af9243d3..000000000000
--- a/arch/blackfin/kernel/early_printk.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * allow a console to be used for early printk
- * derived from arch/x86/kernel/early_printk.c
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched/debug.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <linux/reboot.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#ifdef CONFIG_SERIAL_BFIN
-extern struct console *bfin_earlyserial_init(unsigned int port,
- unsigned int cflag);
-#endif
-#ifdef CONFIG_BFIN_JTAG_COMM
-extern struct console *bfin_jc_early_init(void);
-#endif
-
-/* Default console */
-#define DEFAULT_PORT 0
-#define DEFAULT_CFLAG CS8|B57600
-
-/* Default console for early crashes */
-#define DEFAULT_EARLY_PORT "serial,uart0,57600"
-
-#ifdef CONFIG_SERIAL_CORE
-/* What should get here is "0,57600" */
-static struct console * __init earlyserial_init(char *buf)
-{
- int baud, bit;
- char parity;
- unsigned int serial_port = DEFAULT_PORT;
- unsigned int cflag = DEFAULT_CFLAG;
-
- serial_port = simple_strtoul(buf, &buf, 10);
- buf++;
-
- cflag = 0;
- baud = simple_strtoul(buf, &buf, 10);
- switch (baud) {
- case 1200:
- cflag |= B1200;
- break;
- case 2400:
- cflag |= B2400;
- break;
- case 4800:
- cflag |= B4800;
- break;
- case 9600:
- cflag |= B9600;
- break;
- case 19200:
- cflag |= B19200;
- break;
- case 38400:
- cflag |= B38400;
- break;
- case 115200:
- cflag |= B115200;
- break;
- default:
- cflag |= B57600;
- }
-
- parity = buf[0];
- buf++;
- switch (parity) {
- case 'e':
- cflag |= PARENB;
- break;
- case 'o':
- cflag |= PARODD;
- break;
- }
-
- bit = simple_strtoul(buf, &buf, 10);
- switch (bit) {
- case 5:
- cflag |= CS5;
- break;
- case 6:
- cflag |= CS6;
- break;
- case 7:
- cflag |= CS7;
- break;
- default:
- cflag |= CS8;
- }
-
-#ifdef CONFIG_SERIAL_BFIN
- return bfin_earlyserial_init(serial_port, cflag);
-#else
- return NULL;
-#endif
-
-}
-#endif
-
-int __init setup_early_printk(char *buf)
-{
-
- /* Crashing in here would be really bad, so check both the var
- and the pointer before we start using it
- */
- if (!buf)
- return 0;
-
- if (!*buf)
- return 0;
-
- if (early_console != NULL)
- return 0;
-
-#ifdef CONFIG_SERIAL_BFIN
- /* Check for Blackfin Serial */
- if (!strncmp(buf, "serial,uart", 11)) {
- buf += 11;
- early_console = earlyserial_init(buf);
- }
-#endif
-
-#ifdef CONFIG_BFIN_JTAG_COMM
- /* Check for Blackfin JTAG */
- if (!strncmp(buf, "jtag", 4)) {
- buf += 4;
- early_console = bfin_jc_early_init();
- }
-#endif
-
-#ifdef CONFIG_FB
- /* TODO: add framebuffer console support */
-#endif
-
- if (likely(early_console)) {
- early_console->flags |= CON_BOOT;
-
- register_console(early_console);
- printk(KERN_INFO "early printk enabled on %s%d\n",
- early_console->name,
- early_console->index);
- }
-
- return 0;
-}
-
-/*
- * Set up a temporary Event Vector Table, so if something bad happens before
- * the kernel is fully started, it doesn't vector off into somewhere we don't
- * know
- */
-
-asmlinkage void __init init_early_exception_vectors(void)
-{
- u32 evt;
- SSYNC();
-
- /*
- * This starts up the shadow buffer, incase anything crashes before
- * setup arch
- */
- mark_shadow_error();
- early_shadow_puts(linux_banner);
- early_shadow_stamp();
-
- if (CPUID != bfin_cpuid()) {
- early_shadow_puts("Running on wrong machine type, expected");
- early_shadow_reg(CPUID, 16);
- early_shadow_puts(", but running on");
- early_shadow_reg(bfin_cpuid(), 16);
- early_shadow_puts("\n");
- }
-
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- for (evt = EVT2; evt <= EVT15; evt += 4)
- bfin_write32(evt, early_trap);
- CSYNC();
-
- /* Set all the return from interrupt, exception, NMI to a known place
- * so if we do a RETI, RETX or RETN by mistake - we go somewhere known
- * Note - don't change RETS - we are in a subroutine, or
- * RETE - since it might screw up if emulator is attached
- */
- asm("\tRETI = %0; RETX = %0; RETN = %0;\n"
- : : "p"(early_trap));
-
-}
-
-__attribute__((__noreturn__))
-asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
-{
- /* This can happen before the uart is initialized, so initialize
- * the UART now (but only if we are running on the processor we think
- * we are compiled for - otherwise we write to MMRs that don't exist,
- * and cause other problems. Nothing comes out the UART, but it does
- * end up in the __buf_log.
- */
- if (likely(early_console == NULL) && CPUID == bfin_cpuid())
- setup_early_printk(DEFAULT_EARLY_PORT);
-
- if (!shadow_console_enabled()) {
- /* crap - we crashed before setup_arch() */
- early_shadow_puts("panic before setup_arch\n");
- early_shadow_puts("IPEND:");
- early_shadow_reg(fp->ipend, 16);
- if (fp->seqstat & SEQSTAT_EXCAUSE) {
- early_shadow_puts("\nEXCAUSE:");
- early_shadow_reg(fp->seqstat & SEQSTAT_EXCAUSE, 8);
- }
- if (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- early_shadow_puts("\nHWERRCAUSE:");
- early_shadow_reg(
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14, 8);
- }
- early_shadow_puts("\nErr @");
- if (fp->ipend & EVT_EVX)
- early_shadow_reg(fp->retx, 32);
- else
- early_shadow_reg(fp->pc, 32);
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- early_shadow_puts("\nTrace:");
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- while (bfin_read_TBUFSTAT() & TBUFCNT) {
- early_shadow_puts("\nT :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- early_shadow_puts("\n S :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- }
- }
-#endif
- early_shadow_puts("\nUse bfin-elf-addr2line to determine "
- "function names\n");
- /*
- * We should panic(), but we can't - since panic calls printk,
- * and printk uses memcpy.
- * we want to reboot, but if the machine type is different,
- * can't due to machine specific reboot sequences
- */
- if (CPUID == bfin_cpuid()) {
- early_shadow_puts("Trying to restart\n");
- machine_restart("");
- }
-
- early_shadow_puts("Halting, since it is not safe to restart\n");
- while (1)
- asm volatile ("EMUEXCPT; IDLE;\n");
-
- } else {
- printk(KERN_EMERG "Early panic\n");
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-
- panic("Died early");
-}
-
-early_param("earlyprintk", setup_early_printk);
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
deleted file mode 100644
index 4071265fc4fe..000000000000
--- a/arch/blackfin/kernel/entry.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-
-#include <asm/context.S>
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-ENTRY(_ret_from_fork)
-#ifdef CONFIG_IPIPE
- /*
- * Hw IRQs are off on entry, and we don't want the scheduling tail
- * code to starve high priority domains from interrupts while it
- * runs. Therefore we first stall the root stage to have the
- * virtual interrupt state reflect IMASK.
- */
- p0.l = ___ipipe_root_status;
- p0.h = ___ipipe_root_status;
- r4 = [p0];
- bitset(r4, 0);
- [p0] = r4;
- /*
- * Then we may enable hw IRQs, allowing preemption from high
- * priority domains. schedule_tail() will do local_irq_enable()
- * since Blackfin does not define __ARCH_WANT_UNLOCKED_CTXSW, so
- * there is no need to unstall the root domain by ourselves
- * afterwards.
- */
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r4 = [p0];
- sti r4;
-#endif /* CONFIG_IPIPE */
- SP += -12;
- pseudo_long_call _schedule_tail, p5;
- SP += 12;
- p1 = [sp++];
- r0 = [sp++];
- cc = p1 == 0;
- if cc jump .Lfork;
- sp += -12;
- call (p1);
- sp += 12;
-.Lfork:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_ret_from_fork)
diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c
deleted file mode 100644
index 9208b5fd5186..000000000000
--- a/arch/blackfin/kernel/exception.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Basic functions for adding/removing custom exception handlers
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <asm/irq_handler.h>
-
-int bfin_request_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != ex_replaceable)
- return -EBUSY;
-
- ex_table[exception] = handler;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_request_exception);
-
-int bfin_free_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != handler)
- return -EBUSY;
-
- ex_table[exception] = ex_replaceable;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_free_exception);
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
deleted file mode 100644
index 0565917f23ba..000000000000
--- a/arch/blackfin/kernel/fixed_code.S
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file contains sequences of code that will be copied to a
- * fixed location, defined in <asm/fixed_code.h>. The interrupt
- * handlers ensure that these sequences appear to be atomic when
- * executed from userspace.
- * These are aligned to 16 bytes, so that we have some space to replace
- * these sequences with something else (e.g. kernel traps if we ever do
- * BF561 SMP).
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/unistd.h>
-#include <asm/entry.h>
-
-__INIT
-
-ENTRY(_fixed_code_start)
-
-.align 16
-ENTRY(_sigreturn_stub)
- P0 = __NR_rt_sigreturn;
- EXCPT 0;
- /* Speculative execution paranoia. */
-0: JUMP.S 0b;
-ENDPROC (_sigreturn_stub)
-
-.align 16
- /*
- * Atomic swap, 8 bit.
- * Inputs: P0: memory address to use
- * R1: value to store
- * Output: R0: old contents of the memory address, zero extended.
- */
-ENTRY(_atomic_xchg32)
- R0 = [P0];
- [P0] = R1;
- rts;
-ENDPROC (_atomic_xchg32)
-
-.align 16
- /*
- * Compare and swap, 32 bit.
- * Inputs: P0: memory address to use
- * R1: compare value
- * R2: new value to store
- * The new value is stored if the contents of the memory
- * address is equal to the compare value.
- * Output: R0: old contents of the memory address.
- */
-ENTRY(_atomic_cas32)
- R0 = [P0];
- CC = R0 == R1;
- IF !CC JUMP 1f;
- [P0] = R2;
-1:
- rts;
-ENDPROC (_atomic_cas32)
-
-.align 16
- /*
- * Atomic add, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to add
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_add32)
- R1 = [P0];
- R0 = R1 + R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_add32)
-
-.align 16
- /*
- * Atomic sub, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to subtract
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_sub32)
- R1 = [P0];
- R0 = R1 - R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_sub32)
-
-.align 16
- /*
- * Atomic ior, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to ior
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_ior32)
- R1 = [P0];
- R0 = R1 | R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_ior32)
-
-.align 16
- /*
- * Atomic and, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to and
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_and32)
- R1 = [P0];
- R0 = R1 & R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_and32)
-
-.align 16
- /*
- * Atomic xor, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to xor
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_xor32)
- R1 = [P0];
- R0 = R1 ^ R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_xor32)
-
-.align 16
- /*
- * safe_user_instruction
- * Four NOPS are enough to allow the pipeline to speculativily load
- * execute anything it wants. After that, things have gone bad, and
- * we are stuck - so panic. Since we might be in user space, we can't
- * call panic, so just cause a unhandled exception, this should cause
- * a dump of the trace buffer so we can tell were we are, and a reboot
- */
-ENTRY(_safe_user_instruction)
- NOP; NOP; NOP; NOP;
- EXCPT 0x4;
-ENDPROC(_safe_user_instruction)
-
-ENTRY(_fixed_code_end)
-
-__FINIT
diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c
deleted file mode 100644
index 8ebc54daaa8e..000000000000
--- a/arch/blackfin/kernel/flat.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-#include <linux/flat.h>
-
-#define FLAT_BFIN_RELOC_TYPE_16_BIT 0
-#define FLAT_BFIN_RELOC_TYPE_16H_BIT 1
-#define FLAT_BFIN_RELOC_TYPE_32_BIT 2
-
-unsigned long bfin_get_addr_from_rp(u32 *ptr,
- u32 relval,
- u32 flags,
- u32 *persistent)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
- u32 val;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- usptr = (unsigned short *)ptr;
- pr_debug("*usptr = %x", get_unaligned(usptr));
- val = get_unaligned(usptr);
- val += *persistent;
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- pr_debug("*ptr = %x", get_unaligned(ptr));
- val = get_unaligned(ptr);
- break;
-
- default:
- pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
- return 0;
- }
-
- /*
- * Stack-relative relocs contain the offset into the stack, we
- * have to add the stack's start address here and return 1 from
- * flat_addr_absolute to prevent the normal address calculations
- */
- if (relval & (1 << 29))
- return val + current->mm->context.end_brk;
-
- if ((flags & FLAT_FLAG_GOTPIC) == 0)
- val = htonl(val);
- return val;
-}
-EXPORT_SYMBOL(bfin_get_addr_from_rp);
-
-/*
- * Insert the address ADDR into the symbol reference at RP;
- * RELVAL is the raw relocation-table entry from which RP is derived
- */
-void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- put_unaligned(addr, usptr);
- pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
- break;
-
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- put_unaligned(addr >> 16, usptr);
- pr_debug("new value %x", get_unaligned(usptr));
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- put_unaligned(addr, ptr);
- pr_debug("new ptr =%x", get_unaligned(ptr));
- break;
- }
-}
-EXPORT_SYMBOL(bfin_put_addr_at_rp);
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S
deleted file mode 100644
index 3b8bdcbb7da3..000000000000
--- a/arch/blackfin/kernel/ftrace-entry.S
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * mcount and friends -- ftrace stuff
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/ftrace.h>
-
-.text
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-/* Simple stub so we can boot the kernel until runtime patching has
- * disabled all calls to this. Then it'll be unused.
- */
-ENTRY(__mcount)
-# if ANOMALY_05000371
- nop; nop; nop; nop;
-# endif
- rts;
-ENDPROC(__mcount)
-
-/* GCC will have called us before setting up the function prologue, so we
- * can clobber the normal scratch registers, but we need to make sure to
- * save/restore the registers used for argument passing (R0-R2) in case
- * the profiled function is using them. With data registers, R3 is the
- * only one we can blow away. With pointer registers, we have P0-P2.
- *
- * Upon entry, the RETS will point to the top of the current profiled
- * function. And since GCC pushed the previous RETS for us, the previous
- * function will be waiting there. mmmm pie.
- */
-ENTRY(_ftrace_caller)
- /* save first/second/third function arg and the return register */
- [--sp] = r2;
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
-.globl _ftrace_call
-_ftrace_call:
- call _ftrace_stub
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
-.globl _ftrace_graph_call
-_ftrace_graph_call:
- nop; /* jump _ftrace_graph_caller; */
-# endif
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(_ftrace_caller)
-
-#else
-
-/* See documentation for _ftrace_caller */
-ENTRY(__mcount)
- /* save third function arg early so we can do testing below */
- [--sp] = r2;
-
- /* load the function pointer to the tracer */
- p0.l = _ftrace_trace_function;
- p0.h = _ftrace_trace_function;
- r3 = [p0];
-
- /* optional micro optimization: don't call the stub tracer */
- r2.l = _ftrace_stub;
- r2.h = _ftrace_stub;
- cc = r2 == r3;
- if ! cc jump .Ldo_trace;
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
- /* if the ftrace_graph_return function pointer is not set to
- * the ftrace_stub entry, call prepare_ftrace_return().
- */
- p0.l = _ftrace_graph_return;
- p0.h = _ftrace_graph_return;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-
- /* similarly, if the ftrace_graph_entry function pointer is not
- * set to the ftrace_graph_entry_stub entry, ...
- */
- p0.l = _ftrace_graph_entry;
- p0.h = _ftrace_graph_entry;
- r2.l = _ftrace_graph_entry_stub;
- r2.h = _ftrace_graph_entry_stub;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-# endif
-
- r2 = [sp++];
- rts;
-
-.Ldo_trace:
-
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* setup the tracer function */
- p0 = r3;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
- /* call the tracer */
- call (p0);
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(__mcount)
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-/* The prepare_ftrace_return() function is similar to the trace function
- * except it takes a pointer to the location of the frompc. This is so
- * the prepare_ftrace_return() can hijack it temporarily for probing
- * purposes.
- */
-ENTRY(_ftrace_graph_caller)
-# ifndef CONFIG_DYNAMIC_FTRACE
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* prepare_ftrace_return(parent, self_addr, frame_pointer) */
- r0 = sp; /* unsigned long *parent */
- r1 = rets; /* unsigned long self_addr */
-# else
- r0 = sp; /* unsigned long *parent */
- r1 = [sp]; /* unsigned long self_addr */
-# endif
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r2 = fp; /* unsigned long frame_pointer */
-# endif
- r0 += 16; /* skip the 4 local regs on stack */
- r1 += -MCOUNT_INSN_SIZE;
- call _prepare_ftrace_return;
-
- jump .Lfinish_trace;
-ENDPROC(_ftrace_graph_caller)
-
-/* Undo the rewrite caused by ftrace_graph_caller(). The common function
- * ftrace_return_to_handler() will return the original rets so we can
- * restore it and be on our way.
- */
-ENTRY(_return_to_handler)
- /* make sure original return values are saved */
- [--sp] = p0;
- [--sp] = r0;
- [--sp] = r1;
-
- /* get original return address */
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r0 = fp; /* Blackfin is sane, so omit this */
-# endif
- call _ftrace_return_to_handler;
- rets = r0;
-
- /* anomaly 05000371 - make sure we have at least three instructions
- * between rets setting and the return
- */
- r1 = [sp++];
- r0 = [sp++];
- p0 = [sp++];
- rts;
-ENDPROC(_return_to_handler)
-#endif
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
deleted file mode 100644
index 8dad7589b843..000000000000
--- a/arch/blackfin/kernel/ftrace.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * ftrace graph code
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ftrace.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/uaccess.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-static const unsigned char mnop[] = {
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
-};
-
-static void bfin_make_pcrel24(unsigned char *insn, unsigned long src,
- unsigned long dst)
-{
- uint32_t pcrel = (dst - src) >> 1;
- insn[0] = pcrel >> 16;
- insn[1] = 0xe3;
- insn[2] = pcrel;
- insn[3] = pcrel >> 8;
-}
-#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst))
-
-static int ftrace_modify_code(unsigned long ip, const unsigned char *code,
- unsigned long len)
-{
- int ret = probe_kernel_write((void *)ip, (void *)code, len);
- flush_icache_range(ip, ip + len);
- return ret;
-}
-
-int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
- unsigned long addr)
-{
- /* Turn the mcount call site into two MNOPs as those are 32bit insns */
- return ftrace_modify_code(rec->ip, mnop, sizeof(mnop));
-}
-
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
-{
- /* Restore the mcount call site */
- unsigned char call[8];
- call[0] = 0x67; /* [--SP] = RETS; */
- call[1] = 0x01;
- bfin_make_pcrel24(&call[2], rec->ip + 2, addr);
- call[6] = 0x27; /* RETS = [SP++]; */
- call[7] = 0x01;
- return ftrace_modify_code(rec->ip, call, sizeof(call));
-}
-
-int ftrace_update_ftrace_func(ftrace_func_t func)
-{
- unsigned char call[4];
- unsigned long ip = (unsigned long)&ftrace_call;
- bfin_make_pcrel24(call, ip, func);
- return ftrace_modify_code(ip, call, sizeof(call));
-}
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-
-# ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void ftrace_graph_call(void);
-
-int ftrace_enable_ftrace_graph_caller(void)
-{
- unsigned long ip = (unsigned long)&ftrace_graph_call;
- uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1;
- jump_pcrel12 |= 0x2000;
- return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12));
-}
-
-int ftrace_disable_ftrace_graph_caller(void)
-{
- return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2);
-}
-
-# endif
-
-/*
- * Hook the return address and push it in the stack of return addrs
- * in current thread info.
- */
-void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
- unsigned long frame_pointer)
-{
- struct ftrace_graph_ent trace;
- unsigned long return_hooker = (unsigned long)&return_to_handler;
-
- if (unlikely(atomic_read(&current->tracing_graph_pause)))
- return;
-
- if (ftrace_push_return_trace(*parent, self_addr, &trace.depth,
- frame_pointer, NULL) == -EBUSY)
- return;
-
- trace.func = self_addr;
-
- /* Only trace if the calling function expects to */
- if (!ftrace_graph_entry(&trace)) {
- current->curr_ret_stack--;
- return;
- }
-
- /* all is well in the world ! hijack RETS ... */
- *parent = return_hooker;
-}
-
-#endif
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
deleted file mode 100644
index d776773d3869..000000000000
--- a/arch/blackfin/kernel/gptimers.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * gptimers.c - Blackfin General Purpose Timer core API
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPLv2.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-
-#ifdef DEBUG
-# define tassert(expr)
-#else
-# define tassert(expr) \
- if (!(expr)) \
- printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
-#endif
-
-#ifndef CONFIG_BF60x
-# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
-#else
-# define BFIN_TIMER_NUM_GROUP 1
-#endif
-
-static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
-{
- (void *)TIMER0_CONFIG,
- (void *)TIMER1_CONFIG,
- (void *)TIMER2_CONFIG,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- (void *)TIMER3_CONFIG,
- (void *)TIMER4_CONFIG,
- (void *)TIMER5_CONFIG,
- (void *)TIMER6_CONFIG,
- (void *)TIMER7_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_CONFIG,
- (void *)TIMER9_CONFIG,
- (void *)TIMER10_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- (void *)TIMER11_CONFIG,
-# endif
-# endif
-#endif
-};
-
-static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
-{
- (void *)TIMER0_GROUP_REG,
-#if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_GROUP_REG,
-#endif
-};
-
-static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TRUN0,
- TIMER_STATUS_TRUN1,
- TIMER_STATUS_TRUN2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TRUN3,
- TIMER_STATUS_TRUN4,
- TIMER_STATUS_TRUN5,
- TIMER_STATUS_TRUN6,
- TIMER_STATUS_TRUN7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TRUN8,
- TIMER_STATUS_TRUN9,
- TIMER_STATUS_TRUN10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TRUN11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TOVF0,
- TIMER_STATUS_TOVF1,
- TIMER_STATUS_TOVF2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TOVF3,
- TIMER_STATUS_TOVF4,
- TIMER_STATUS_TOVF5,
- TIMER_STATUS_TOVF6,
- TIMER_STATUS_TOVF7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TOVF8,
- TIMER_STATUS_TOVF9,
- TIMER_STATUS_TOVF10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TOVF11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TIMIL0,
- TIMER_STATUS_TIMIL1,
- TIMER_STATUS_TIMIL2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TIMIL3,
- TIMER_STATUS_TIMIL4,
- TIMER_STATUS_TIMIL5,
- TIMER_STATUS_TIMIL6,
- TIMER_STATUS_TIMIL7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TIMIL8,
- TIMER_STATUS_TIMIL9,
- TIMER_STATUS_TIMIL10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TIMIL11,
-# endif
-# endif
-#endif
-};
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->width, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pwidth);
-
-uint32_t get_gptimer_pwidth(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->width);
-}
-EXPORT_SYMBOL(get_gptimer_pwidth);
-
-void set_gptimer_period(unsigned int timer_id, uint32_t period)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->period, period);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_period);
-
-uint32_t get_gptimer_period(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->period);
-}
-EXPORT_SYMBOL(get_gptimer_period);
-
-uint32_t get_gptimer_count(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->counter);
-}
-EXPORT_SYMBOL(get_gptimer_count);
-
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->delay, delay);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_delay);
-
-uint32_t get_gptimer_delay(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->delay);
-}
-EXPORT_SYMBOL(get_gptimer_delay);
-#endif
-
-#ifdef CONFIG_BF60x
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->data_ilat);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->data_ilat, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-#else
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->status);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->status, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-
-static uint32_t read_gptimer_status(unsigned int timer_id)
-{
- return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
-}
-
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-#endif
-
-void set_gptimer_config(unsigned int timer_id, uint16_t config)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->config, config);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_config);
-
-uint16_t get_gptimer_config(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->config);
-}
-EXPORT_SYMBOL(get_gptimer_config);
-
-void enable_gptimers(uint16_t mask)
-{
- int i;
-#ifdef CONFIG_BF60x
- uint16_t imask;
- imask = bfin_read16(TIMER_DATA_IMSK);
- imask &= ~mask;
- bfin_write16(TIMER_DATA_IMSK, imask);
-#endif
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->enable, mask & 0xFF);
- mask >>= 8;
- }
- SSYNC();
-}
-EXPORT_SYMBOL(enable_gptimers);
-
-static void _disable_gptimers(uint16_t mask)
-{
- int i;
- uint16_t m = mask;
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->disable, m & 0xFF);
- m >>= 8;
- }
-}
-
-void disable_gptimers(uint16_t mask)
-{
-#ifndef CONFIG_BF60x
- int i;
- _disable_gptimers(mask);
- for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
- if (mask & (1 << i))
- bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
- SSYNC();
-#else
- _disable_gptimers(mask);
-#endif
-}
-EXPORT_SYMBOL(disable_gptimers);
-
-void disable_gptimers_sync(uint16_t mask)
-{
- _disable_gptimers(mask);
- SSYNC();
-}
-EXPORT_SYMBOL(disable_gptimers_sync);
-
-void set_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pulse_hi);
-
-void clear_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(clear_gptimer_pulse_hi);
-
-uint16_t get_enabled_gptimers(void)
-{
- int i;
- uint16_t result = 0;
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
- result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
- return result;
-}
-EXPORT_SYMBOL(get_enabled_gptimers);
-
-MODULE_AUTHOR("Axel Weiss (awe@aglaia-gmbh.de)");
-MODULE_DESCRIPTION("Blackfin General Purpose Timers API");
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
deleted file mode 100644
index f657b38163e3..000000000000
--- a/arch/blackfin/kernel/ipipe.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* -*- linux-c -*-
- * linux/arch/blackfin/kernel/ipipe.c
- *
- * Copyright (C) 2005-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Architecture-dependent I-pipe support for the Blackfin.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/kthread.h>
-#include <linux/unistd.h>
-#include <linux/io.h>
-#include <linux/atomic.h>
-#include <asm/irq_handler.h>
-
-DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-
-static void __ipipe_no_irqtail(void);
-
-unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail;
-EXPORT_SYMBOL(__ipipe_irq_tail_hook);
-
-unsigned long __ipipe_core_clock;
-EXPORT_SYMBOL(__ipipe_core_clock);
-
-unsigned long __ipipe_freq_scale;
-EXPORT_SYMBOL(__ipipe_freq_scale);
-
-atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-unsigned long __ipipe_irq_lvmask = bfin_no_irqs;
-EXPORT_SYMBOL(__ipipe_irq_lvmask);
-
-static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
-{
- desc->ipipe_ack(irq, desc);
-}
-
-/*
- * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
- * interrupts are off, and secondary CPUs are still lost in space.
- */
-void __ipipe_enable_pipeline(void)
-{
- unsigned irq;
-
- __ipipe_core_clock = get_cclk(); /* Fetch this once. */
- __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock;
-
- for (irq = 0; irq < NR_IRQS; ++irq)
- ipipe_virtualize_irq(ipipe_root_domain,
- irq,
- (ipipe_irq_handler_t)&asm_do_IRQ,
- NULL,
- &__ipipe_ack_irq,
- IPIPE_HANDLE_MASK | IPIPE_PASS_MASK);
-}
-
-/*
- * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
- * interrupt protection log is maintained here for each domain. Hw
- * interrupts are masked on entry.
- */
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain, *next_domain;
- struct list_head *head, *pos;
- struct ipipe_irqdesc *idesc;
- int m_ack, s = -1;
-
- /*
- * Software-triggered IRQs do not need any ack. The contents
- * of the register frame should only be used when processing
- * the timer interrupt, but not for handling any other
- * interrupt.
- */
- m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
- this_domain = __ipipe_current_domain;
- idesc = &this_domain->irqs[irq];
-
- if (unlikely(test_bit(IPIPE_STICKY_FLAG, &idesc->control)))
- head = &this_domain->p_link;
- else {
- head = __ipipe_pipeline.next;
- next_domain = list_entry(head, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (likely(test_bit(IPIPE_WIRED_FLAG, &idesc->control))) {
- if (!m_ack && idesc->acknowledge != NULL)
- idesc->acknowledge(irq, irq_to_desc(irq));
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG,
- &p->status);
- __ipipe_dispatch_wired(next_domain, irq);
- goto out;
- }
- }
-
- /* Ack the interrupt. */
-
- pos = head;
- while (pos != &__ipipe_pipeline) {
- next_domain = list_entry(pos, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (test_bit(IPIPE_HANDLE_FLAG, &idesc->control)) {
- __ipipe_set_irq_pending(next_domain, irq);
- if (!m_ack && idesc->acknowledge != NULL) {
- idesc->acknowledge(irq, irq_to_desc(irq));
- m_ack = 1;
- }
- }
- if (!test_bit(IPIPE_PASS_FLAG, &idesc->control))
- break;
- pos = next_domain->p_link.next;
- }
-
- /*
- * Now walk the pipeline, yielding control to the highest
- * priority domain that has pending interrupt(s) or
- * immediately to the current domain if the interrupt has been
- * marked as 'sticky'. This search does not go beyond the
- * current domain in the pipeline. We also enforce the
- * additional root stage lock (blackfin-specific).
- */
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
-
- /*
- * If the interrupt preempted the head domain, then do not
- * even try to walk the pipeline, unless an interrupt is
- * pending for it.
- */
- if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
- !__ipipe_ipending_p(ipipe_head_cpudom_ptr()))
- goto out;
-
- __ipipe_walk_pipeline(head);
-out:
- if (!s)
- __clear_bit(IPIPE_STALL_FLAG, &p->status);
-}
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- struct irq_desc *desc = irq_to_desc(irq);
- int prio = __ipipe_get_irq_priority(irq);
-
- desc->depth = 0;
- if (ipd != &ipipe_root &&
- atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1)
- __set_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_enable_irqdesc);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- int prio = __ipipe_get_irq_priority(irq);
-
- if (ipd != &ipipe_root &&
- atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
- __clear_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_disable_irqdesc);
-
-asmlinkage int __ipipe_syscall_root(struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p;
- void (*hook)(void);
- int ret;
-
- WARN_ON_ONCE(irqs_disabled_hw());
-
- /*
- * We need to run the IRQ tail hook each time we intercept a
- * syscall, because we know that important operations might be
- * pending there (e.g. Xenomai deferred rescheduling).
- */
- hook = (__typeof__(hook))__ipipe_irq_tail_hook;
- hook();
-
- /*
- * This routine either returns:
- * 0 -- if the syscall is to be passed to Linux;
- * >0 -- if the syscall should not be passed to Linux, and no
- * tail work should be performed;
- * <0 -- if the syscall should not be passed to Linux but the
- * tail work has to be performed (for handling signals etc).
- */
-
- if (!__ipipe_syscall_watched_p(current, regs->orig_p0) ||
- !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL))
- return 0;
-
- ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
-
- hard_local_irq_disable();
-
- /*
- * This is the end of the syscall path, so we may
- * safely assume a valid Linux task stack here.
- */
- if (current->ipipe_flags & PF_EVTRET) {
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (!__ipipe_root_domain_p)
- ret = -1;
- else {
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
- }
-
- hard_local_irq_enable();
-
- return -ret;
-}
-
-static void __ipipe_no_irqtail(void)
-{
-}
-
-int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
-{
- info->sys_nr_cpus = num_online_cpus();
- info->sys_cpu_freq = ipipe_cpu_freq();
- info->sys_hrtimer_irq = IPIPE_TIMER_IRQ;
- info->sys_hrtimer_freq = __ipipe_core_clock;
- info->sys_hrclock_freq = __ipipe_core_clock;
-
- return 0;
-}
-
-/*
- * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
- * just like if it has been actually received from a hw source. Also
- * works for virtual interrupts.
- */
-int ipipe_trigger_irq(unsigned irq)
-{
- unsigned long flags;
-
-#ifdef CONFIG_IPIPE_DEBUG
- if (irq >= IPIPE_NR_IRQS ||
- (ipipe_virtual_irq_p(irq)
- && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
- return -EINVAL;
-#endif
-
- flags = hard_local_irq_save();
- __ipipe_handle_irq(irq, NULL);
- hard_local_irq_restore(flags);
-
- return 1;
-}
-
-asmlinkage void __ipipe_sync_root(void)
-{
- void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
- struct ipipe_percpu_domain_data *p;
- unsigned long flags;
-
- BUG_ON(irqs_disabled());
-
- flags = hard_local_irq_save();
-
- if (irq_tail_hook)
- irq_tail_hook();
-
- clear_thread_flag(TIF_IRQ_SYNC);
-
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
-
- hard_local_irq_restore(flags);
-}
-
-void ___ipipe_sync_pipeline(void)
-{
- if (__ipipe_root_domain_p &&
- test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
- return;
-
- __ipipe_sync_stage();
-}
-
-void __ipipe_disable_root_irqs_hw(void)
-{
- /*
- * This code is called by the ins{bwl} routines (see
- * arch/blackfin/lib/ins.S), which are heavily used by the
- * network stack. It masks all interrupts but those handled by
- * non-root domains, so that we keep decent network transfer
- * rates for Linux without inducing pathological jitter for
- * the real-time domain.
- */
- bfin_sti(__ipipe_irq_lvmask);
- __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
-}
-
-void __ipipe_enable_root_irqs_hw(void)
-{
- __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
- bfin_sti(bfin_irq_flags);
-}
-
-/*
- * We could use standard atomic bitops in the following root status
- * manipulation routines, but let's prepare for SMP support in the
- * same move, preventing CPU migration as required.
- */
-void __ipipe_stall_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_stall_root);
-
-unsigned long __ipipe_test_and_stall_root(void)
-{
- unsigned long *p, flags;
- int x;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_and_stall_root);
-
-unsigned long __ipipe_test_root(void)
-{
- const unsigned long *p;
- unsigned long flags;
- int x;
-
- flags = hard_local_irq_save_smp();
- p = &__ipipe_root_status;
- x = test_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore_smp(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_root);
-
-void __ipipe_lock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_lock_root);
-
-void __ipipe_unlock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_unlock_root);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
deleted file mode 100644
index 052cde5ed2e4..000000000000
--- a/arch/blackfin/kernel/irqchip.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/random.h>
-#include <linux/seq_file.h>
-#include <linux/kallsyms.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/seq_file.h>
-#include <asm/irq_handler.h>
-#include <asm/trace.h>
-#include <asm/pda.h>
-
-static atomic_t irq_err_count;
-void ack_bad_irq(unsigned int irq)
-{
- atomic_inc(&irq_err_count);
- printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
-}
-
-static struct irq_desc bad_irq_desc = {
- .handle_irq = handle_bad_irq,
- .lock = __RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
-};
-
-#ifdef CONFIG_CPUMASK_OFFSTACK
-/* We are not allocating a variable-sized bad_irq_desc.affinity */
-#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK."
-#endif
-
-#ifdef CONFIG_PROC_FS
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
- int j;
-
- seq_printf(p, "%*s: ", prec, "NMI");
- for_each_online_cpu(j)
- seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);
- seq_printf(p, " CORE Non Maskable Interrupt\n");
- seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-static void check_stack_overflow(int irq)
-{
- /* Debugging check for stack overflow: is there less than STACK_WARN free? */
- long sp = __get_SP() & (THREAD_SIZE - 1);
-
- if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
- dump_stack();
- pr_emerg("irq%i: possible stack overflow only %ld bytes free\n",
- irq, sp - sizeof(struct thread_info));
- }
-}
-#else
-static inline void check_stack_overflow(int irq) { }
-#endif
-
-#ifndef CONFIG_IPIPE
-static void maybe_lower_to_irq14(void)
-{
- unsigned short pending, other_ints;
-
- /*
- * If we're the only interrupt running (ignoring IRQ15 which
- * is for syscalls), lower our priority to IRQ14 so that
- * softirqs run at that level. If there's another,
- * lower-level interrupt, irq_exit will defer softirqs to
- * that. If the interrupt pipeline is enabled, we are already
- * running at IRQ14 priority, so we don't need this code.
- */
- CSYNC();
- pending = bfin_read_IPEND() & ~0x8000;
- other_ints = pending & (pending - 1);
- if (other_ints == 0)
- lower_to_irq14();
-}
-#else
-static inline void maybe_lower_to_irq14(void) { }
-#endif
-
-/*
- * do_IRQ handles all hardware IRQs. Decoded IRQs should not
- * come via this function. Instead, they should provide their
- * own 'handler'
- */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- check_stack_overflow(irq);
-
- /*
- * Some hardware gives randomly wrong interrupts. Rather
- * than crashing, do something sensible.
- */
- if (irq >= NR_IRQS)
- handle_bad_irq(&bad_irq_desc);
- else
- generic_handle_irq(irq);
-
- maybe_lower_to_irq14();
-
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-void __init init_IRQ(void)
-{
- init_arch_irq();
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- /* Now that evt_ivhw is set up, turn this on */
- trace_buff_offset = 0;
- bfin_write_TBUFCTL(BFIN_TRACE_ON);
- printk(KERN_INFO "Hardware Trace expanded to %ik\n",
- 1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN);
-#endif
-}
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
deleted file mode 100644
index cf773f0f1f30..000000000000
--- a/arch/blackfin/kernel/kgdb.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ptrace.h> /* for linux pt_regs struct */
-#include <linux/kgdb.h>
-#include <linux/uaccess.h>
-#include <asm/irq_regs.h>
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- gdb_regs[BFIN_R0] = regs->r0;
- gdb_regs[BFIN_R1] = regs->r1;
- gdb_regs[BFIN_R2] = regs->r2;
- gdb_regs[BFIN_R3] = regs->r3;
- gdb_regs[BFIN_R4] = regs->r4;
- gdb_regs[BFIN_R5] = regs->r5;
- gdb_regs[BFIN_R6] = regs->r6;
- gdb_regs[BFIN_R7] = regs->r7;
- gdb_regs[BFIN_P0] = regs->p0;
- gdb_regs[BFIN_P1] = regs->p1;
- gdb_regs[BFIN_P2] = regs->p2;
- gdb_regs[BFIN_P3] = regs->p3;
- gdb_regs[BFIN_P4] = regs->p4;
- gdb_regs[BFIN_P5] = regs->p5;
- gdb_regs[BFIN_SP] = regs->reserved;
- gdb_regs[BFIN_FP] = regs->fp;
- gdb_regs[BFIN_I0] = regs->i0;
- gdb_regs[BFIN_I1] = regs->i1;
- gdb_regs[BFIN_I2] = regs->i2;
- gdb_regs[BFIN_I3] = regs->i3;
- gdb_regs[BFIN_M0] = regs->m0;
- gdb_regs[BFIN_M1] = regs->m1;
- gdb_regs[BFIN_M2] = regs->m2;
- gdb_regs[BFIN_M3] = regs->m3;
- gdb_regs[BFIN_B0] = regs->b0;
- gdb_regs[BFIN_B1] = regs->b1;
- gdb_regs[BFIN_B2] = regs->b2;
- gdb_regs[BFIN_B3] = regs->b3;
- gdb_regs[BFIN_L0] = regs->l0;
- gdb_regs[BFIN_L1] = regs->l1;
- gdb_regs[BFIN_L2] = regs->l2;
- gdb_regs[BFIN_L3] = regs->l3;
- gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
- gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
- gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
- gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
- gdb_regs[BFIN_ASTAT] = regs->astat;
- gdb_regs[BFIN_RETS] = regs->rets;
- gdb_regs[BFIN_LC0] = regs->lc0;
- gdb_regs[BFIN_LT0] = regs->lt0;
- gdb_regs[BFIN_LB0] = regs->lb0;
- gdb_regs[BFIN_LC1] = regs->lc1;
- gdb_regs[BFIN_LT1] = regs->lt1;
- gdb_regs[BFIN_LB1] = regs->lb1;
- gdb_regs[BFIN_CYCLES] = 0;
- gdb_regs[BFIN_CYCLES2] = 0;
- gdb_regs[BFIN_USP] = regs->usp;
- gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
- gdb_regs[BFIN_SYSCFG] = regs->syscfg;
- gdb_regs[BFIN_RETI] = regs->pc;
- gdb_regs[BFIN_RETX] = regs->retx;
- gdb_regs[BFIN_RETN] = regs->retn;
- gdb_regs[BFIN_RETE] = regs->rete;
- gdb_regs[BFIN_PC] = regs->pc;
- gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
- gdb_regs[BFIN_EXTRA1] = 0;
- gdb_regs[BFIN_EXTRA2] = 0;
- gdb_regs[BFIN_EXTRA3] = 0;
- gdb_regs[BFIN_IPEND] = regs->ipend;
-}
-
-/*
- * Extracts ebp, esp and eip values understandable by gdb from the values
- * saved by switch_to.
- * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
- * prior to entering switch_to is 8 greater than the value that is saved.
- * If switch_to changes, change following code appropriately.
- */
-void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
-{
- gdb_regs[BFIN_SP] = p->thread.ksp;
- gdb_regs[BFIN_PC] = p->thread.pc;
- gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
-}
-
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- regs->r0 = gdb_regs[BFIN_R0];
- regs->r1 = gdb_regs[BFIN_R1];
- regs->r2 = gdb_regs[BFIN_R2];
- regs->r3 = gdb_regs[BFIN_R3];
- regs->r4 = gdb_regs[BFIN_R4];
- regs->r5 = gdb_regs[BFIN_R5];
- regs->r6 = gdb_regs[BFIN_R6];
- regs->r7 = gdb_regs[BFIN_R7];
- regs->p0 = gdb_regs[BFIN_P0];
- regs->p1 = gdb_regs[BFIN_P1];
- regs->p2 = gdb_regs[BFIN_P2];
- regs->p3 = gdb_regs[BFIN_P3];
- regs->p4 = gdb_regs[BFIN_P4];
- regs->p5 = gdb_regs[BFIN_P5];
- regs->fp = gdb_regs[BFIN_FP];
- regs->i0 = gdb_regs[BFIN_I0];
- regs->i1 = gdb_regs[BFIN_I1];
- regs->i2 = gdb_regs[BFIN_I2];
- regs->i3 = gdb_regs[BFIN_I3];
- regs->m0 = gdb_regs[BFIN_M0];
- regs->m1 = gdb_regs[BFIN_M1];
- regs->m2 = gdb_regs[BFIN_M2];
- regs->m3 = gdb_regs[BFIN_M3];
- regs->b0 = gdb_regs[BFIN_B0];
- regs->b1 = gdb_regs[BFIN_B1];
- regs->b2 = gdb_regs[BFIN_B2];
- regs->b3 = gdb_regs[BFIN_B3];
- regs->l0 = gdb_regs[BFIN_L0];
- regs->l1 = gdb_regs[BFIN_L1];
- regs->l2 = gdb_regs[BFIN_L2];
- regs->l3 = gdb_regs[BFIN_L3];
- regs->a0x = gdb_regs[BFIN_A0_DOT_X];
- regs->a0w = gdb_regs[BFIN_A0_DOT_W];
- regs->a1x = gdb_regs[BFIN_A1_DOT_X];
- regs->a1w = gdb_regs[BFIN_A1_DOT_W];
- regs->rets = gdb_regs[BFIN_RETS];
- regs->lc0 = gdb_regs[BFIN_LC0];
- regs->lt0 = gdb_regs[BFIN_LT0];
- regs->lb0 = gdb_regs[BFIN_LB0];
- regs->lc1 = gdb_regs[BFIN_LC1];
- regs->lt1 = gdb_regs[BFIN_LT1];
- regs->lb1 = gdb_regs[BFIN_LB1];
- regs->usp = gdb_regs[BFIN_USP];
- regs->syscfg = gdb_regs[BFIN_SYSCFG];
- regs->retx = gdb_regs[BFIN_RETX];
- regs->retn = gdb_regs[BFIN_RETN];
- regs->rete = gdb_regs[BFIN_RETE];
- regs->pc = gdb_regs[BFIN_PC];
-
-#if 0 /* can't change these */
- regs->astat = gdb_regs[BFIN_ASTAT];
- regs->seqstat = gdb_regs[BFIN_SEQSTAT];
- regs->ipend = gdb_regs[BFIN_IPEND];
-#endif
-}
-
-static struct hw_breakpoint {
- unsigned int occupied:1;
- unsigned int skip:1;
- unsigned int enabled:1;
- unsigned int type:1;
- unsigned int dataacc:2;
- unsigned short count;
- unsigned int addr;
-} breakinfo[HW_WATCHPOINT_NUM];
-
-static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
- int dataacc = 0;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- dataacc = 1;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_READ_WATCHPOINT:
- dataacc = 2;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_ACCESS_WATCHPOINT:
- dataacc = 3;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return -ENOSPC;
- }
-
- /* Because hardware data watchpoint impelemented in current
- * Blackfin can not trigger an exception event as the hardware
- * instrction watchpoint does, we ignaore all data watch point here.
- * They can be turned on easily after future blackfin design
- * supports this feature.
- */
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && !breakinfo[breakno].occupied) {
- breakinfo[breakno].occupied = 1;
- breakinfo[breakno].skip = 0;
- breakinfo[breakno].enabled = 1;
- breakinfo[breakno].addr = addr;
- breakinfo[breakno].dataacc = dataacc;
- breakinfo[breakno].count = 0;
- return 0;
- }
-
- return -ENOSPC;
-}
-
-static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- case BP_READ_WATCHPOINT:
- case BP_ACCESS_WATCHPOINT:
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return 0;
- }
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && breakinfo[breakno].occupied
- && breakinfo[breakno].addr == addr) {
- breakinfo[breakno].occupied = 0;
- breakinfo[breakno].enabled = 0;
- }
-
- return 0;
-}
-
-static void bfin_remove_all_hw_break(void)
-{
- int breakno;
-
- memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
-
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
- for (; breakno < HW_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
-}
-
-static void bfin_correct_hw_break(void)
-{
- int breakno;
- unsigned int wpiactl = 0;
- unsigned int wpdactl = 0;
- int enable_wp = 0;
-
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (breakinfo[breakno].enabled) {
- enable_wp = 1;
-
- switch (breakno) {
- case 0:
- wpiactl |= WPIAEN0|WPICNTEN0;
- bfin_write_WPIA0(breakinfo[breakno].addr);
- bfin_write_WPIACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 1:
- wpiactl |= WPIAEN1|WPICNTEN1;
- bfin_write_WPIA1(breakinfo[breakno].addr);
- bfin_write_WPIACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 2:
- wpiactl |= WPIAEN2|WPICNTEN2;
- bfin_write_WPIA2(breakinfo[breakno].addr);
- bfin_write_WPIACNT2(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 3:
- wpiactl |= WPIAEN3|WPICNTEN3;
- bfin_write_WPIA3(breakinfo[breakno].addr);
- bfin_write_WPIACNT3(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 4:
- wpiactl |= WPIAEN4|WPICNTEN4;
- bfin_write_WPIA4(breakinfo[breakno].addr);
- bfin_write_WPIACNT4(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 5:
- wpiactl |= WPIAEN5|WPICNTEN5;
- bfin_write_WPIA5(breakinfo[breakno].addr);
- bfin_write_WPIACNT5(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 6:
- wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC0_OFFSET;
- bfin_write_WPDA0(breakinfo[breakno].addr);
- bfin_write_WPDACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 7:
- wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC1_OFFSET;
- bfin_write_WPDA1(breakinfo[breakno].addr);
- bfin_write_WPDACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- }
- }
-
- /* Should enable WPPWR bit first before set any other
- * WPIACTL and WPDACTL bits */
- if (enable_wp) {
- bfin_write_WPIACTL(WPPWR);
- CSYNC();
- bfin_write_WPIACTL(wpiactl|WPPWR);
- bfin_write_WPDACTL(wpdactl);
- CSYNC();
- }
-}
-
-static void bfin_disable_hw_debug(struct pt_regs *regs)
-{
- /* Disable hardware debugging while we are in kgdb */
- bfin_write_WPIACTL(0);
- bfin_write_WPDACTL(0);
- CSYNC();
-}
-
-#ifdef CONFIG_SMP
-void kgdb_passive_cpu_callback(void *info)
-{
- kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
-}
-
-void kgdb_roundup_cpus(unsigned long flags)
-{
- unsigned int cpu;
-
- for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
- cpu = cpumask_next(cpu, cpu_online_mask))
- smp_call_function_single(cpu, kgdb_passive_cpu_callback,
- NULL, 0);
-}
-
-void kgdb_roundup_cpu(int cpu, unsigned long flags)
-{
- smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
-}
-#endif
-
-#ifdef CONFIG_IPIPE
-static unsigned long kgdb_arch_imask;
-#endif
-
-int kgdb_arch_handle_exception(int vector, int signo,
- int err_code, char *remcom_in_buffer,
- char *remcom_out_buffer,
- struct pt_regs *regs)
-{
- long addr;
- char *ptr;
- int newPC;
- int i;
-
- switch (remcom_in_buffer[0]) {
- case 'c':
- case 's':
- if (kgdb_contthread && kgdb_contthread != current) {
- strcpy(remcom_out_buffer, "E00");
- break;
- }
-
- kgdb_contthread = NULL;
-
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &remcom_in_buffer[1];
- if (kgdb_hex2long(&ptr, &addr)) {
- regs->retx = addr;
- }
- newPC = regs->retx;
-
- /* clear the trace bit */
- regs->syscfg &= 0xfffffffe;
-
- /* set the trace bit if we're stepping */
- if (remcom_in_buffer[0] == 's') {
- regs->syscfg |= 0x1;
- kgdb_single_step = regs->ipend;
- kgdb_single_step >>= 6;
- for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
- if (kgdb_single_step & 1)
- break;
- /* i indicate event priority of current stopped instruction
- * user space instruction is 0, IVG15 is 1, IVTMR is 10.
- * kgdb_single_step > 0 means in single step mode
- */
- kgdb_single_step = i + 1;
-
- preempt_disable();
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
- cpu_pda[raw_smp_processor_id()].ex_imask = 0;
-#endif
- }
-
- bfin_correct_hw_break();
-
- return 0;
- } /* switch */
- return -1; /* this means that we do not want to exit from the handler */
-}
-
-struct kgdb_arch arch_kgdb_ops = {
- .gdb_bpt_instr = {0xa1},
- .flags = KGDB_HW_BREAKPOINT,
- .set_hw_breakpoint = bfin_set_hw_break,
- .remove_hw_breakpoint = bfin_remove_hw_break,
- .disable_hw_break = bfin_disable_hw_debug,
- .remove_all_hw_break = bfin_remove_all_hw_break,
- .correct_hw_break = bfin_correct_hw_break,
-};
-
-#define IN_MEM(addr, size, l1_addr, l1_size) \
-({ \
- unsigned long __addr = (unsigned long)(addr); \
- (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
-})
-#define ASYNC_BANK_SIZE \
- (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
- ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
-
-int kgdb_validate_break_address(unsigned long addr)
-{
- int cpu = raw_smp_processor_id();
-
- if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
- return 0;
- if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
- return 0;
- if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#ifdef CONFIG_SMP
- else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#endif
- if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
- return 0;
-
- return -EFAULT;
-}
-
-void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
-{
- regs->retx = ip;
-}
-
-int kgdb_arch_init(void)
-{
- kgdb_single_step = 0;
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = 0;
-#endif
-
- bfin_remove_all_hw_break();
- return 0;
-}
-
-void kgdb_arch_exit(void)
-{
-}
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
deleted file mode 100644
index b8b785dc4e3b..000000000000
--- a/arch/blackfin/kernel/kgdb_test.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-
-#include <asm/current.h>
-#include <linux/uaccess.h>
-
-#include <asm/blackfin.h>
-
-/* Symbols are here for kgdb test to poke directly */
-static char cmdline[256];
-static size_t len;
-
-#ifndef CONFIG_SMP
-static int num1 __attribute__((l1_data));
-
-void kgdb_l1_test(void) __attribute__((l1_text));
-
-void kgdb_l1_test(void)
-{
- pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
- pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
- num1 = num1 + 10;
- pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-}
-#endif
-
-#if L2_LENGTH
-
-static int num2 __attribute__((l2));
-void kgdb_l2_test(void) __attribute__((l2));
-
-void kgdb_l2_test(void)
-{
- pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
- pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
- num2 = num2 + 20;
- pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-}
-
-#endif
-
-noinline int kgdb_test(char *name, int len, int count, int z)
-{
- pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
- count = z;
- return count;
-}
-
-static ssize_t
-kgdb_test_proc_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- kgdb_test("hello world!", 12, 0x55, 0x10);
-#ifndef CONFIG_SMP
- kgdb_l1_test();
-#endif
-#if L2_LENGTH
- kgdb_l2_test();
-#endif
-
- return 0;
-}
-
-static ssize_t
-kgdb_test_proc_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *pos)
-{
- len = min_t(size_t, 255, count);
- memcpy(cmdline, buffer, count);
- cmdline[len] = 0;
-
- return len;
-}
-
-static const struct file_operations kgdb_test_proc_fops = {
- .owner = THIS_MODULE,
- .read = kgdb_test_proc_read,
- .write = kgdb_test_proc_write,
- .llseek = noop_llseek,
-};
-
-static int __init kgdbtest_init(void)
-{
- struct proc_dir_entry *entry;
-
-#if L2_LENGTH
- num2 = 0;
-#endif
-
- entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
- if (entry == NULL)
- return -ENOMEM;
-
- return 0;
-}
-
-static void __exit kgdbtest_exit(void)
-{
- remove_proc_entry("kgdbtest", NULL);
-}
-
-module_init(kgdbtest_init);
-module_exit(kgdbtest_exit);
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
deleted file mode 100644
index 15af5768c403..000000000000
--- a/arch/blackfin/kernel/module.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/dma.h>
-#include <asm/cacheflush.h>
-#include <linux/uaccess.h>
-
-#define mod_err(mod, fmt, ...) \
- pr_err("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-#define mod_debug(mod, fmt, ...) \
- pr_debug("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-
-/* Transfer the section to the L1 memory */
-int
-module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
- char *secstrings, struct module *mod)
-{
- /*
- * XXX: sechdrs are vmalloced in kernel/module.c
- * and would be vfreed just after module is loaded,
- * so we hack to keep the only information we needed
- * in mod->arch to correctly free L1 I/D sram later.
- * NOTE: this breaks the semantic of mod->arch structure.
- */
- Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
- void *dest;
-
- for (s = sechdrs; s < sechdrs_end; ++s) {
- const char *shname = secstrings + s->sh_name;
-
- if (s->sh_size == 0)
- continue;
-
- if (!strcmp(".l1.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L1))) {
-
- dest = l1_inst_sram_alloc(s->sh_size);
- mod->arch.text_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 inst memory allocation failed\n");
- return -1;
- }
- dma_memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_alloc(s->sh_size);
- mod->arch.data_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_zalloc(s->sh_size);
- mod->arch.bss_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
-
- } else if (!strcmp(".l1.data.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.data_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.bss_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memset(dest, 0, s->sh_size);
-
- } else if (!strcmp(".l2.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.text_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.data_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_zalloc(s->sh_size);
- mod->arch.bss_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
-
- } else
- continue;
-
- s->sh_flags &= ~SHF_ALLOC;
- s->sh_addr = (unsigned long)dest;
- }
-
- return 0;
-}
-
-/*************************************************************************/
-/* FUNCTION : apply_relocate_add */
-/* ABSTRACT : Blackfin specific relocation handling for the loadable */
-/* modules. Modules are expected to be .o files. */
-/* Arithmetic relocations are handled. */
-/* We do not expect LSETUP to be split and hence is not */
-/* handled. */
-/* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */
-/* gas does not generate it. */
-/*************************************************************************/
-int
-apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
- unsigned int symindex, unsigned int relsec,
- struct module *mod)
-{
- unsigned int i;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- unsigned long location, value, size;
-
- mod_debug(mod, "applying relocate section %u to %u\n",
- relsec, sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = sechdrs[sechdrs[relsec].sh_info].sh_addr +
- rel[i].r_offset;
-
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
- value = sym->st_value;
- value += rel[i].r_addend;
-
-#ifdef CONFIG_SMP
- if (location >= COREB_L1_DATA_A_START) {
- mod_err(mod, "cannot relocate in L1: %u (SMP kernel)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-#endif
-
- mod_debug(mod, "location is %lx, value is %lx type is %d\n",
- location, value, ELF32_R_TYPE(rel[i].r_info));
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
-
- case R_BFIN_HUIMM16:
- value >>= 16;
- case R_BFIN_LUIMM16:
- case R_BFIN_RIMM16:
- size = 2;
- break;
- case R_BFIN_BYTE4_DATA:
- size = 4;
- break;
-
- case R_BFIN_PCREL24:
- case R_BFIN_PCREL24_JUMP_L:
- case R_BFIN_PCREL12_JUMP:
- case R_BFIN_PCREL12_JUMP_S:
- case R_BFIN_PCREL10:
- mod_err(mod, "unsupported relocation: %u (no -mlong-calls?)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
-
- default:
- mod_err(mod, "unknown relocation: %u\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-
- switch (bfin_mem_access_type(location, size)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy((void *)location, &value, size);
- break;
- default:
- mod_err(mod, "invalid relocation for %#lx\n", location);
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-int
-module_finalize(const Elf_Ehdr * hdr,
- const Elf_Shdr * sechdrs, struct module *mod)
-{
- unsigned int i, strindex = 0, symindex = 0;
- char *secstrings;
- long err = 0;
-
- secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
-
- for (i = 1; i < hdr->e_shnum; i++) {
- /* Internal symbols and strings. */
- if (sechdrs[i].sh_type == SHT_SYMTAB) {
- symindex = i;
- strindex = sechdrs[i].sh_link;
- }
- }
-
- for (i = 1; i < hdr->e_shnum; i++) {
- const char *strtab = (char *)sechdrs[strindex].sh_addr;
- unsigned int info = sechdrs[i].sh_info;
- const char *shname = secstrings + sechdrs[i].sh_name;
-
- /* Not a valid relocation section? */
- if (info >= hdr->e_shnum)
- continue;
-
- /* Only support RELA relocation types */
- if (sechdrs[i].sh_type != SHT_RELA)
- continue;
-
- if (!strcmp(".rela.l2.text", shname) ||
- !strcmp(".rela.l1.text", shname) ||
- (!strcmp(".rela.text", shname) &&
- (hdr->e_flags & (EF_BFIN_CODE_IN_L1 | EF_BFIN_CODE_IN_L2)))) {
-
- err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
- symindex, i, mod);
- if (err < 0)
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-void module_arch_cleanup(struct module *mod)
-{
- l1_inst_sram_free(mod->arch.text_l1);
- l1_data_A_sram_free(mod->arch.data_a_l1);
- l1_data_A_sram_free(mod->arch.bss_a_l1);
- l1_data_B_sram_free(mod->arch.data_b_l1);
- l1_data_B_sram_free(mod->arch.bss_b_l1);
- l2_sram_free(mod->arch.text_l2);
- l2_sram_free(mod->arch.data_l2);
- l2_sram_free(mod->arch.bss_l2);
-}
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
deleted file mode 100644
index 8a211d95821f..000000000000
--- a/arch/blackfin/kernel/nmi.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Blackfin nmi_watchdog Driver
- *
- * Originally based on bfin_wdt.c
- * Copyright 2010-2010 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/bitops.h>
-#include <linux/hardirq.h>
-#include <linux/syscore_ops.h>
-#include <linux/pm.h>
-#include <linux/nmi.h>
-#include <linux/smp.h>
-#include <linux/timer.h>
-#include <linux/sched/debug.h>
-#include <asm/blackfin.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/bfin_watchdog.h>
-
-#define DRV_NAME "nmi-wdt"
-
-#define NMI_WDT_TIMEOUT 5 /* 5 seconds */
-#define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */
-static int nmi_wdt_cpu = 1;
-
-static unsigned int timeout = NMI_WDT_TIMEOUT;
-static int nmi_active;
-
-static unsigned short wdoga_ctl;
-static unsigned int wdoga_cnt;
-static struct corelock_slot saved_corelock;
-static atomic_t nmi_touched[NR_CPUS];
-static struct timer_list ntimer;
-
-enum {
- COREA_ENTER_NMI = 0,
- COREA_EXIT_NMI,
- COREB_EXIT_NMI,
-
- NMI_EVENT_NR,
-};
-static unsigned long nmi_event __attribute__ ((__section__(".l2.bss")));
-
-/* we are in nmi, non-atomic bit ops is safe */
-static inline void set_nmi_event(int event)
-{
- __set_bit(event, &nmi_event);
-}
-
-static inline void wait_nmi_event(int event)
-{
- while (!test_bit(event, &nmi_event))
- barrier();
- __clear_bit(event, &nmi_event);
-}
-
-static inline void send_corea_nmi(void)
-{
- wdoga_ctl = bfin_read_WDOGA_CTL();
- wdoga_cnt = bfin_read_WDOGA_CNT();
-
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CNT(0);
- bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline void restore_corea_nmi(void)
-{
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-
- bfin_write_WDOGA_CNT(wdoga_cnt);
- bfin_write_WDOGA_CTL(wdoga_ctl);
-}
-
-static inline void save_corelock(void)
-{
- saved_corelock = corelock;
- corelock.lock = 0;
-}
-
-static inline void restore_corelock(void)
-{
- corelock = saved_corelock;
-}
-
-
-static inline void nmi_wdt_keepalive(void)
-{
- bfin_write_WDOGB_STAT(0);
-}
-
-static inline void nmi_wdt_stop(void)
-{
- bfin_write_WDOGB_CTL(WDEN_DISABLE);
-}
-
-/* before calling this function, you must stop the WDT */
-static inline void nmi_wdt_clear(void)
-{
- /* clear TRO bit, disable event generation */
- bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-}
-
-static inline void nmi_wdt_start(void)
-{
- bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline int nmi_wdt_running(void)
-{
- return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE);
-}
-
-static inline int nmi_wdt_set_timeout(unsigned long t)
-{
- u32 cnt, max_t, sclk;
- int run;
-
- sclk = get_sclk();
- max_t = -1 / sclk;
- cnt = t * sclk;
- if (t > max_t) {
- pr_warning("NMI: timeout value is too large\n");
- return -EINVAL;
- }
-
- run = nmi_wdt_running();
- nmi_wdt_stop();
- bfin_write_WDOGB_CNT(cnt);
- if (run)
- nmi_wdt_start();
-
- timeout = t;
-
- return 0;
-}
-
-int check_nmi_wdt_touched(void)
-{
- unsigned int this_cpu = smp_processor_id();
- unsigned int cpu;
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- if (!atomic_read(&nmi_touched[this_cpu]))
- return 0;
-
- atomic_set(&nmi_touched[this_cpu], 0);
-
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask) {
- invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
- (unsigned long)(&nmi_touched[cpu]));
- if (!atomic_read(&nmi_touched[cpu]))
- return 0;
- atomic_set(&nmi_touched[cpu], 0);
- }
-
- return 1;
-}
-
-static void nmi_wdt_timer(struct timer_list *unused)
-{
- if (check_nmi_wdt_touched())
- nmi_wdt_keepalive();
-
- mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT);
-}
-
-static int __init init_nmi_wdt(void)
-{
- nmi_wdt_set_timeout(timeout);
- nmi_wdt_start();
- nmi_active = true;
-
- timer_setup(&ntimer, nmi_wdt_timer, 0);
- ntimer.expires = jiffies + NMI_CHECK_TIMEOUT;
- add_timer(&ntimer);
-
- pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout);
- return 0;
-}
-device_initcall(init_nmi_wdt);
-
-void arch_touch_nmi_watchdog(void)
-{
- atomic_set(&nmi_touched[smp_processor_id()], 1);
-}
-
-/* Suspend/resume support */
-#ifdef CONFIG_PM
-static int nmi_wdt_suspend(void)
-{
- nmi_wdt_stop();
- return 0;
-}
-
-static void nmi_wdt_resume(void)
-{
- if (nmi_active)
- nmi_wdt_start();
-}
-
-static struct syscore_ops nmi_syscore_ops = {
- .resume = nmi_wdt_resume,
- .suspend = nmi_wdt_suspend,
-};
-
-static int __init init_nmi_wdt_syscore(void)
-{
- if (nmi_active)
- register_syscore_ops(&nmi_syscore_ops);
-
- return 0;
-}
-late_initcall(init_nmi_wdt_syscore);
-
-#endif /* CONFIG_PM */
-
-
-asmlinkage notrace void do_nmi(struct pt_regs *fp)
-{
- unsigned int cpu = smp_processor_id();
- nmi_enter();
-
- cpu_pda[cpu].__nmi_count += 1;
-
- if (cpu == nmi_wdt_cpu) {
- /* CoreB goes here first */
-
- /* reload the WDOG_STAT */
- nmi_wdt_keepalive();
-
- /* clear nmi interrupt for CoreB */
- nmi_wdt_stop();
- nmi_wdt_clear();
-
- /* trigger NMI interrupt of CoreA */
- send_corea_nmi();
-
- /* waiting CoreB to enter NMI */
- wait_nmi_event(COREA_ENTER_NMI);
-
- /* recover WDOGA's settings */
- restore_corea_nmi();
-
- save_corelock();
-
- /* corelock is save/cleared, CoreA is dummping messages */
-
- wait_nmi_event(COREA_EXIT_NMI);
- } else {
- /* OK, CoreA entered NMI */
- set_nmi_event(COREA_ENTER_NMI);
- }
-
- pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu);
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- show_stack(current, (unsigned long *)fp);
-
- if (cpu == nmi_wdt_cpu) {
- pr_emerg("This fault is not recoverable, sorry!\n");
-
- /* CoreA dump finished, restore the corelock */
- restore_corelock();
-
- set_nmi_event(COREB_EXIT_NMI);
- } else {
- /* CoreB dump finished, notice the CoreA we are done */
- set_nmi_event(COREA_EXIT_NMI);
-
- /* synchronize with CoreA */
- wait_nmi_event(COREB_EXIT_NMI);
- }
-
- nmi_exit();
-}
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
deleted file mode 100644
index 6a9524ad04a5..000000000000
--- a/arch/blackfin/kernel/perf_event.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Blackfin performance counters
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Ripped from SuperH version:
- *
- * Copyright (C) 2009 Paul Mundt
- *
- * Heavily based on the x86 and PowerPC implementations.
- *
- * x86:
- * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
- * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
- * Copyright (C) 2009 Jaswinder Singh Rajput
- * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
- * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
- * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
- *
- * ppc:
- * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/perf_event.h>
-#include <asm/bfin_pfmon.h>
-
-/*
- * We have two counters, and each counter can support an event type.
- * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
- *
- * 0x04 o pc invariant branches
- * 0x06 o mispredicted branches
- * 0x09 o predicted branches taken
- * 0x0B o EXCPT insn
- * 0x0C o CSYNC/SSYNC insn
- * 0x0D o Insns committed
- * 0x0E o Interrupts taken
- * 0x0F o Misaligned address exceptions
- * 0x80 o Code memory fetches stalled due to DMA
- * 0x83 o 64bit insn fetches delivered
- * 0x9A o data cache fills (bank a)
- * 0x9B o data cache fills (bank b)
- * 0x9C o data cache lines evicted (bank a)
- * 0x9D o data cache lines evicted (bank b)
- * 0x9E o data cache high priority fills
- * 0x9F o data cache low priority fills
- * 0x00 s loop 0 iterations
- * 0x01 s loop 1 iterations
- * 0x0A s CSYNC/SSYNC stalls
- * 0x10 s DAG read/after write hazards
- * 0x13 s RAW data hazards
- * 0x81 s code TAG stalls
- * 0x82 s code fill stalls
- * 0x90 s processor to memory stalls
- * 0x91 s data memory stalls not hidden by 0x90
- * 0x92 s data store buffer full stalls
- * 0x93 s data memory write buffer full stalls due to high->low priority
- * 0x95 s data memory fill buffer stalls
- * 0x96 s data TAG collision stalls
- * 0x97 s data collision stalls
- * 0x98 s data stalls
- * 0x99 s data stalls sent to processor
- */
-
-static const int event_map[] = {
- /* use CYCLES cpu register */
- [PERF_COUNT_HW_CPU_CYCLES] = -1,
- [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
- [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
- [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
- [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
- [PERF_COUNT_HW_BUS_CYCLES] = -1,
-};
-
-#define C(x) PERF_COUNT_HW_CACHE_##x
-
-static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [C(L1D)] = { /* Data bank A */
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x9A,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x83,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-};
-
-const char *perf_pmu_name(void)
-{
- return "bfin";
-}
-EXPORT_SYMBOL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- return ARRAY_SIZE(event_map);
-}
-EXPORT_SYMBOL(perf_num_counters);
-
-static u64 bfin_pfmon_read(int idx)
-{
- return bfin_read32(PFCNTR0 + (idx * 4));
-}
-
-static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
-}
-
-static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
-{
- u32 val, mask;
-
- val = PFPWR;
- if (idx) {
- mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
- /* The packed config is for event0, so shift it to event1 slots */
- val |= (hwc->config << (PFMON1_P - PFMON0_P));
- val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
- bfin_write_PFCNTR1(0);
- } else {
- mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
- val |= hwc->config;
- bfin_write_PFCNTR0(0);
- }
-
- bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
-}
-
-static void bfin_pfmon_disable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
-}
-
-static void bfin_pfmon_enable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
-}
-
-struct cpu_hw_events {
- struct perf_event *events[MAX_HWEVENTS];
- unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-};
-DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-static int hw_perf_cache_event(int config, int *evp)
-{
- unsigned long type, op, result;
- int ev;
-
- /* unpack config */
- type = config & 0xff;
- op = (config >> 8) & 0xff;
- result = (config >> 16) & 0xff;
-
- if (type >= PERF_COUNT_HW_CACHE_MAX ||
- op >= PERF_COUNT_HW_CACHE_OP_MAX ||
- result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
- return -EINVAL;
-
- ev = cache_events[type][op][result];
- if (ev == 0)
- return -EOPNOTSUPP;
- if (ev == -1)
- return -EINVAL;
- *evp = ev;
- return 0;
-}
-
-static void bfin_perf_event_update(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- u64 prev_raw_count, new_raw_count;
- s64 delta;
- int shift = 0;
-
- /*
- * Depending on the counter configuration, they may or may not
- * be chained, in which case the previous counter value can be
- * updated underneath us if the lower-half overflows.
- *
- * Our tactic to handle this is to first atomically read and
- * exchange a new raw count - then add that new-prev delta
- * count to the generic counter atomically.
- *
- * As there is no interrupt associated with the overflow events,
- * this is the simplest approach for maintaining consistency.
- */
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = bfin_pfmon_read(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- /*
- * Now we have the new raw value and have updated the prev
- * timestamp already. We can now calculate the elapsed delta
- * (counter-)time and add that to the generic counter.
- *
- * Careful, not all hw sign-extends above the physical width
- * of the count.
- */
- delta = (new_raw_count << shift) - (prev_raw_count << shift);
- delta >>= shift;
-
- local64_add(delta, &event->count);
-}
-
-static void bfin_pmu_stop(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (!(event->hw.state & PERF_HES_STOPPED)) {
- bfin_pfmon_disable(hwc, idx);
- cpuc->events[idx] = NULL;
- event->hw.state |= PERF_HES_STOPPED;
- }
-
- if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
- bfin_perf_event_update(event, &event->hw, idx);
- event->hw.state |= PERF_HES_UPTODATE;
- }
-}
-
-static void bfin_pmu_start(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
-
- cpuc->events[idx] = event;
- event->hw.state = 0;
- bfin_pfmon_enable(hwc, idx);
-}
-
-static void bfin_pmu_del(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
-
- bfin_pmu_stop(event, PERF_EF_UPDATE);
- __clear_bit(event->hw.idx, cpuc->used_mask);
-
- perf_event_update_userpage(event);
-}
-
-static int bfin_pmu_add(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- int ret = -EAGAIN;
-
- perf_pmu_disable(event->pmu);
-
- if (__test_and_set_bit(idx, cpuc->used_mask)) {
- idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
- if (idx == MAX_HWEVENTS)
- goto out;
-
- __set_bit(idx, cpuc->used_mask);
- hwc->idx = idx;
- }
-
- bfin_pfmon_disable(hwc, idx);
-
- event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
- if (flags & PERF_EF_START)
- bfin_pmu_start(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
- ret = 0;
-out:
- perf_pmu_enable(event->pmu);
- return ret;
-}
-
-static void bfin_pmu_read(struct perf_event *event)
-{
- bfin_perf_event_update(event, &event->hw, event->hw.idx);
-}
-
-static int bfin_pmu_event_init(struct perf_event *event)
-{
- struct perf_event_attr *attr = &event->attr;
- struct hw_perf_event *hwc = &event->hw;
- int config = -1;
- int ret;
-
- if (attr->exclude_hv || attr->exclude_idle)
- return -EPERM;
-
- ret = 0;
- switch (attr->type) {
- case PERF_TYPE_RAW:
- config = PFMON(0, attr->config & PFMON_MASK) |
- PFCNT(0, !(attr->config & 0x100));
- break;
- case PERF_TYPE_HW_CACHE:
- ret = hw_perf_cache_event(attr->config, &config);
- break;
- case PERF_TYPE_HARDWARE:
- if (attr->config >= ARRAY_SIZE(event_map))
- return -EINVAL;
-
- config = event_map[attr->config];
- break;
- }
-
- if (config == -1)
- return -EINVAL;
-
- if (!attr->exclude_kernel)
- config |= PFCEN(0, PFCEN_ENABLE_SUPV);
- if (!attr->exclude_user)
- config |= PFCEN(0, PFCEN_ENABLE_USER);
-
- hwc->config |= config;
-
- return ret;
-}
-
-static void bfin_pmu_enable(struct pmu *pmu)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct perf_event *event;
- struct hw_perf_event *hwc;
- int i;
-
- for (i = 0; i < MAX_HWEVENTS; ++i) {
- event = cpuc->events[i];
- if (!event)
- continue;
- hwc = &event->hw;
- bfin_pfmon_enable(hwc, hwc->idx);
- }
-
- bfin_pfmon_enable_all();
-}
-
-static void bfin_pmu_disable(struct pmu *pmu)
-{
- bfin_pfmon_disable_all();
-}
-
-static struct pmu pmu = {
- .pmu_enable = bfin_pmu_enable,
- .pmu_disable = bfin_pmu_disable,
- .event_init = bfin_pmu_event_init,
- .add = bfin_pmu_add,
- .del = bfin_pmu_del,
- .start = bfin_pmu_start,
- .stop = bfin_pmu_stop,
- .read = bfin_pmu_read,
-};
-
-static int bfin_pmu_prepare_cpu(unsigned int cpu)
-{
- struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
-
- bfin_write_PFCTL(0);
- memset(cpuhw, 0, sizeof(struct cpu_hw_events));
- return 0;
-}
-
-static int __init bfin_pmu_init(void)
-{
- int ret;
-
- /*
- * All of the on-chip counters are "limited", in that they have
- * no interrupts, and are therefore unable to do sampling without
- * further work and timer assistance.
- */
- pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
-
- ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
- if (!ret)
- cpuhp_setup_state(CPUHP_PERF_BFIN,"perf/bfin:starting",
- bfin_pmu_prepare_cpu, NULL);
- return ret;
-}
-early_initcall(bfin_pmu_init);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
deleted file mode 100644
index 89814850b08b..000000000000
--- a/arch/blackfin/kernel/process.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * Blackfin architecture-dependent process handling
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <linux/unistd.h>
-#include <linux/user.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm_types.h>
-#include <linux/tick.h>
-#include <linux/fs.h>
-#include <linux/err.h>
-
-#include <asm/blackfin.h>
-#include <asm/fixed_code.h>
-#include <asm/mem_map.h>
-#include <asm/irq.h>
-
-asmlinkage void ret_from_fork(void);
-
-/* Points to the SDRAM backup memory for the stack that is currently in
- * L1 scratchpad memory.
- */
-void *current_l1_stack_save;
-
-/* The number of tasks currently using a L1 stack area. The SRAM is
- * allocated/deallocated whenever this changes from/to zero.
- */
-int nr_l1stack_tasks;
-
-/* Start and length of the area in L1 scratchpad memory which we've allocated
- * for process stacks.
- */
-void *l1_stack_base;
-unsigned long l1_stack_len;
-
-void (*pm_power_off)(void) = NULL;
-EXPORT_SYMBOL(pm_power_off);
-
-/*
- * The idle loop on BFIN
- */
-#ifdef CONFIG_IDLE_L1
-void arch_cpu_idle(void)__attribute__((l1_text));
-#endif
-
-/*
- * This is our default idle handler. We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
- */
-void arch_cpu_idle(void)
-{
-#ifdef CONFIG_IPIPE
- ipipe_suspend_domain();
-#endif
- hard_local_irq_disable();
- if (!need_resched())
- idle_with_irq_disabled();
-
- hard_local_irq_enable();
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-void arch_cpu_idle_dead(void)
-{
- cpu_die();
-}
-#endif
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
-{
- regs->pc = new_ip;
- if (current->mm)
- regs->p5 = current->mm->start_data;
-#ifndef CONFIG_SMP
- task_thread_info(current)->l1_task_info.stack_start =
- (void *)current->mm->context.stack_start;
- task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
- memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
- sizeof(*L1_SCRATCH_TASK_INFO));
-#endif
- wrusp(new_sp);
-}
-EXPORT_SYMBOL_GPL(start_thread);
-
-void flush_thread(void)
-{
-}
-
-asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
-{
-#ifdef __ARCH_SYNC_CORE_DCACHE
- if (current->nr_cpus_allowed == num_possible_cpus())
- set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
-#endif
- if (newsp)
- newsp -= 12;
- return do_fork(clone_flags, newsp, 0, NULL, NULL);
-}
-
-int
-copy_thread(unsigned long clone_flags,
- unsigned long usp, unsigned long topstk,
- struct task_struct *p)
-{
- struct pt_regs *childregs;
- unsigned long *v;
-
- childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
- v = ((unsigned long *)childregs) - 2;
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(childregs, 0, sizeof(struct pt_regs));
- v[0] = usp;
- v[1] = topstk;
- childregs->orig_p0 = -1;
- childregs->ipend = 0x8000;
- __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
- p->thread.usp = 0;
- } else {
- *childregs = *current_pt_regs();
- childregs->r0 = 0;
- p->thread.usp = usp ? : rdusp();
- v[0] = v[1] = 0;
- }
-
- p->thread.ksp = (unsigned long)v;
- p->thread.pc = (unsigned long)ret_from_fork;
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
- unsigned long fp, pc;
- unsigned long stack_page;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- stack_page = (unsigned long)p;
- fp = p->thread.usp;
- do {
- if (fp < stack_page + sizeof(struct thread_info) ||
- fp >= 8184 + stack_page)
- return 0;
- pc = ((unsigned long *)fp)[1];
- if (!in_sched_functions(pc))
- return pc;
- fp = *(unsigned long *)fp;
- }
- while (count++ < 16);
- return 0;
-}
-
-void finish_atomic_sections (struct pt_regs *regs)
-{
- int __user *up0 = (int __user *)regs->p0;
-
- switch (regs->pc) {
- default:
- /* not in middle of an atomic step, so resume like normal */
- return;
-
- case ATOMIC_XCHG32 + 2:
- put_user(regs->r1, up0);
- break;
-
- case ATOMIC_CAS32 + 2:
- case ATOMIC_CAS32 + 4:
- if (regs->r0 == regs->r1)
- case ATOMIC_CAS32 + 6:
- put_user(regs->r2, up0);
- break;
-
- case ATOMIC_ADD32 + 2:
- regs->r0 = regs->r1 + regs->r0;
- /* fall through */
- case ATOMIC_ADD32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_SUB32 + 2:
- regs->r0 = regs->r1 - regs->r0;
- /* fall through */
- case ATOMIC_SUB32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_IOR32 + 2:
- regs->r0 = regs->r1 | regs->r0;
- /* fall through */
- case ATOMIC_IOR32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_AND32 + 2:
- regs->r0 = regs->r1 & regs->r0;
- /* fall through */
- case ATOMIC_AND32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_XOR32 + 2:
- regs->r0 = regs->r1 ^ regs->r0;
- /* fall through */
- case ATOMIC_XOR32 + 4:
- put_user(regs->r0, up0);
- break;
- }
-
- /*
- * We've finished the atomic section, and the only thing left for
- * userspace is to do a RTS, so we might as well handle that too
- * since we need to update the PC anyways.
- */
- regs->pc = regs->rets;
-}
-
-static inline
-int in_mem(unsigned long addr, unsigned long size,
- unsigned long start, unsigned long end)
-{
- return addr >= start && addr + size <= end;
-}
-static inline
-int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
- unsigned long const_addr, unsigned long const_size)
-{
- return const_size &&
- in_mem(addr, size, const_addr + off, const_addr + const_size);
-}
-static inline
-int in_mem_const(unsigned long addr, unsigned long size,
- unsigned long const_addr, unsigned long const_size)
-{
- return in_mem_const_off(addr, size, 0, const_addr, const_size);
-}
-#ifdef CONFIG_BF60x
-#define ASYNC_ENABLED(bnum, bctlnum) 1
-#else
-#define ASYNC_ENABLED(bnum, bctlnum) \
-({ \
- (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
- bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
- 1; \
-})
-#endif
-/*
- * We can't read EBIU banks that aren't enabled or we end up hanging
- * on the access to the async space. Make sure we validate accesses
- * that cross async banks too.
- * 0 - found, but unusable
- * 1 - found & usable
- * 2 - not found
- */
-static
-int in_async(unsigned long addr, unsigned long size)
-{
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
- if (!ASYNC_ENABLED(0, 0))
- return 0;
- if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
- return 1;
- size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
- addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
- }
- if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
- if (!ASYNC_ENABLED(1, 0))
- return 0;
- if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
- return 1;
- size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
- addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
- }
- if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
- if (!ASYNC_ENABLED(2, 1))
- return 0;
- if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
- return 1;
- size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
- addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
- }
- if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (ASYNC_ENABLED(3, 1))
- return 0;
- if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
- return 1;
- return 0;
- }
-
- /* not within async bounds */
- return 2;
-}
-
-int bfin_mem_access_type(unsigned long addr, unsigned long size)
-{
- int cpu = raw_smp_processor_id();
-
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return -EFAULT;
-
- if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
- return BFIN_MEM_ACCESS_CORE;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#endif
- if (in_mem_const(addr, size, L2_START, L2_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
-
- if (addr >= SYSMMR_BASE)
- return BFIN_MEM_ACCESS_CORE_ONLY;
-
- switch (in_async(addr, size)) {
- case 0: return -EFAULT;
- case 1: return BFIN_MEM_ACCESS_CORE;
- case 2: /* fall through */;
- }
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return BFIN_MEM_ACCESS_DMA;
-
- return -EFAULT;
-}
-
-#if defined(CONFIG_ACCESS_CHECK)
-#ifdef CONFIG_ACCESS_OK_L1
-__attribute__((l1_text))
-#endif
-/* Return 1 if access to memory range is OK, 0 otherwise */
-int _access_ok(unsigned long addr, unsigned long size)
-{
- int aret;
-
- if (size == 0)
- return 1;
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return 0;
- if (uaccess_kernel())
- return 1;
-#ifdef CONFIG_MTD_UCLINUX
- if (1)
-#else
- if (0)
-#endif
- {
- if (in_mem(addr, size, memory_start, memory_end))
- return 1;
- if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
- return 1;
-# ifndef CONFIG_ROMFS_ON_MTD
- if (0)
-# endif
- /* For XIP, allow user space to use pointers within the ROMFS. */
- if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
- return 1;
- } else {
- if (in_mem(addr, size, memory_start, physical_mem_end))
- return 1;
- }
-
- if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
- return 1;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return 1;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return 1;
-#endif
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
- if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
- return 1;
-#endif
-
- aret = in_async(addr, size);
- if (aret < 2)
- return aret;
-
- if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
- return 1;
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return 1;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return 1;
-
- return 0;
-}
-EXPORT_SYMBOL(_access_ok);
-#endif /* CONFIG_ACCESS_CHECK */
diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c
deleted file mode 100644
index db85bc94334e..000000000000
--- a/arch/blackfin/kernel/pseudodbg.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* The fake debug assert instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-
-const char * const greg_names[] = {
- "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
- "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP",
- "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3",
- "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
- "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS",
- "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>",
- "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2",
- "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT",
-};
-
-static const char *get_allreg_name(int grp, int reg)
-{
- return greg_names[(grp << 3) | reg];
-}
-
-/*
- * Unfortunately, the pt_regs structure is not laid out the same way as the
- * hardware register file, so we need to do some fix ups.
- *
- * CYCLES is not stored in the pt_regs structure - so, we just read it from
- * the hardware.
- *
- * Don't support:
- * - All reserved registers
- * - All in group 7 are (supervisors only)
- */
-
-static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
-{
- long *val = &fp->r0;
- unsigned long tmp;
-
- /* Only do Dregs and Pregs for now */
- if (grp == 5 ||
- (grp == 4 && (reg == 4 || reg == 5)) ||
- (grp == 7))
- return false;
-
- if (grp == 0 || (grp == 1 && reg < 6))
- val -= (reg + 8 * grp);
- else if (grp == 1 && reg == 6)
- val = &fp->usp;
- else if (grp == 1 && reg == 7)
- val = &fp->fp;
- else if (grp == 2) {
- val = &fp->i0;
- val -= reg;
- } else if (grp == 3 && reg >= 4) {
- val = &fp->l0;
- val -= (reg - 4);
- } else if (grp == 3 && reg < 4) {
- val = &fp->b0;
- val -= reg;
- } else if (grp == 4 && reg < 4) {
- val = &fp->a0x;
- val -= reg;
- } else if (grp == 4 && reg == 6)
- val = &fp->astat;
- else if (grp == 4 && reg == 7)
- val = &fp->rets;
- else if (grp == 6 && reg < 6) {
- val = &fp->lc0;
- val -= reg;
- } else if (grp == 6 && reg == 6) {
- __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp));
- val = &tmp;
- } else if (grp == 6 && reg == 7) {
- __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp));
- val = &tmp;
- }
-
- *value = *val;
- return true;
-
-}
-
-#define PseudoDbg_Assert_opcode 0xf0000000
-#define PseudoDbg_Assert_expected_bits 0
-#define PseudoDbg_Assert_expected_mask 0xffff
-#define PseudoDbg_Assert_regtest_bits 16
-#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_grp_bits 19
-#define PseudoDbg_Assert_grp_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 22
-#define PseudoDbg_Assert_dbgop_mask 0x3
-#define PseudoDbg_Assert_dontcare_bits 24
-#define PseudoDbg_Assert_dontcare_mask 0x7
-#define PseudoDbg_Assert_code_bits 27
-#define PseudoDbg_Assert_code_mask 0x1f
-
-/*
- * DBGA - debug assert
- */
-bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
-{
- int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
- int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
- int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
- int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
- long value;
-
- if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
- return false;
-
- if (!fix_up_reg(fp, &value, grp, regtest))
- return false;
-
- if (dbgop == 0 || dbgop == 2) {
- /* DBGA ( regs_lo , uimm16 ) */
- /* DBGAL ( regs , uimm16 ) */
- if (expected != (value & 0xFFFF)) {
- pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)(value & 0xFFFF));
- return false;
- }
-
- } else if (dbgop == 1 || dbgop == 3) {
- /* DBGA ( regs_hi , uimm16 ) */
- /* DBGAH ( regs , uimm16 ) */
- if (expected != ((value >> 16) & 0xFFFF)) {
- pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)((value >> 16) & 0xFFFF));
- return false;
- }
- }
-
- fp->pc += 4;
- return true;
-}
-
-#define PseudoDbg_opcode 0xf8000000
-#define PseudoDbg_reg_bits 0
-#define PseudoDbg_reg_mask 0x7
-#define PseudoDbg_grp_bits 3
-#define PseudoDbg_grp_mask 0x7
-#define PseudoDbg_fn_bits 6
-#define PseudoDbg_fn_mask 0x3
-#define PseudoDbg_code_bits 8
-#define PseudoDbg_code_mask 0xff
-
-/*
- * DBG - debug (dump a register value out)
- */
-bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
-{
- int grp, fn, reg;
- long value, value1;
-
- if ((opcode & 0xFF000000) != PseudoDbg_opcode)
- return false;
-
- opcode >>= 16;
- grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
- fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
- reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
-
- if (fn == 3 && (reg == 0 || reg == 1)) {
- if (!fix_up_reg(fp, &value, 4, 2 * reg))
- return false;
- if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1))
- return false;
-
- pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1);
- fp->pc += 2;
- return true;
-
- } else if (fn == 0) {
- if (!fix_up_reg(fp, &value, grp, reg))
- return false;
-
- pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value);
- fp->pc += 2;
- return true;
- }
-
- return false;
-}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
deleted file mode 100644
index a6827095b99a..000000000000
--- a/arch/blackfin/kernel/ptrace.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- * these modifications are Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/elf.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/regset.h>
-#include <linux/signal.h>
-#include <linux/tracehook.h>
-#include <linux/uaccess.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <asm/dma.h>
-#include <asm/fixed_code.h>
-#include <asm/cacheflush.h>
-#include <asm/mem_map.h>
-#include <asm/mmu_context.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long
-get_reg(struct task_struct *task, unsigned long regno,
- unsigned long __user *datap)
-{
- long tmp;
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_TEXT_ADDR:
- tmp = task->mm->start_code;
- break;
- case PT_TEXT_END_ADDR:
- tmp = task->mm->end_code;
- break;
- case PT_DATA_ADDR:
- tmp = task->mm->start_data;
- break;
- case PT_USP:
- tmp = task->thread.usp;
- break;
- default:
- if (regno < sizeof(*regs)) {
- void *reg_ptr = regs;
- tmp = *(long *)(reg_ptr + regno);
- } else
- return -EIO;
- }
-
- return put_user(tmp, datap);
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int
-put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
-{
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_PC:
- /*********************************************************************/
- /* At this point the kernel is most likely in exception. */
- /* The RETX register will be used to populate the pc of the process. */
- /*********************************************************************/
- regs->retx = data;
- regs->pc = data;
- break;
- case PT_RETX:
- break; /* regs->retx = data; break; */
- case PT_USP:
- regs->usp = data;
- task->thread.usp = data;
- break;
- case PT_SYSCFG: /* don't let userspace screw with this */
- if ((data & ~1) != 0x6)
- pr_warning("ptrace: ignore syscfg write of %#lx\n", data);
- break; /* regs->syscfg = data; break; */
- default:
- if (regno < sizeof(*regs)) {
- void *reg_offset = regs;
- *(long *)(reg_offset + regno) = data;
- }
- /* Ignore writes to pseudo registers */
- }
-
- return 0;
-}
-
-/*
- * check that an address falls within the bounds of the target process's memory mappings
- */
-int
-is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len)
-{
- bool valid;
- struct vm_area_struct *vma;
- struct sram_list_struct *sraml;
-
- /* overflow */
- if (start + len < start)
- return -EIO;
-
- down_read(&child->mm->mmap_sem);
- vma = find_vma(child->mm, start);
- valid = vma && start >= vma->vm_start && start + len <= vma->vm_end;
- up_read(&child->mm->mmap_sem);
- if (valid)
- return 0;
-
- for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
- if (start >= (unsigned long)sraml->addr
- && start + len < (unsigned long)sraml->addr + sraml->length)
- return 0;
-
- if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
- return 0;
-
-#ifdef CONFIG_APP_STACK_L1
- if (child->mm->context.l1_stack_save)
- if (start >= (unsigned long)l1_stack_base &&
- start + len < (unsigned long)l1_stack_base + l1_stack_len)
- return 0;
-#endif
-
- return -EIO;
-}
-
-/*
- * retrieve the contents of Blackfin userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* This sucks ... */
- regs->usp = target->thread.usp;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs, 0, sizeof(*regs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*regs), -1);
-}
-
-/*
- * update the contents of the Blackfin userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* Don't let people set SYSCFG (it's at the end of pt_regs) */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs, 0, PT_SYSCFG);
- if (ret < 0)
- return ret;
-
- /* This sucks ... */
- target->thread.usp = regs->usp;
- /* regs->retx = regs->pc; */
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- PT_SYSCFG, -1);
-}
-
-/*
- * Define the register sets available on the Blackfin under Linux
- */
-enum bfin_regset {
- REGSET_GENERAL,
-};
-
-static const struct user_regset bfin_regsets[] = {
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = sizeof(struct pt_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
-};
-
-static const struct user_regset_view user_bfin_native_view = {
- .name = "Blackfin",
- .e_machine = EM_BLACKFIN,
- .regsets = bfin_regsets,
- .n = ARRAY_SIZE(bfin_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_bfin_native_view;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg |= SYSCFG_SSSTEP;
-
- set_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg &= ~SYSCFG_SSSTEP;
-
- clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned long __user *datap = (unsigned long __user *)data;
- void *paddr = (void *)addr;
-
- switch (request) {
- /* when I and D space are separate, these will need to be fixed. */
- case PTRACE_PEEKDATA:
- pr_debug("ptrace: PEEKDATA\n");
- /* fall through */
- case PTRACE_PEEKTEXT: /* read word at location addr. */
- {
- unsigned long tmp = 0;
- int copied = 0, to_copy = sizeof(tmp);
-
- ret = -EIO;
- pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %i\n", addr, to_copy);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &tmp,
- to_copy, FOLL_FORCE);
- if (copied)
- break;
-
- /* hrm, why didn't that work ... maybe no mapping */
- if (addr >= FIXED_CODE_START &&
- addr + to_copy <= FIXED_CODE_END) {
- copy_from_user_page(0, 0, 0, &tmp, paddr, to_copy);
- copied = to_copy;
- } else if (addr >= BOOT_ROM_START) {
- memcpy(&tmp, paddr, to_copy);
- copied = to_copy;
- }
-
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
- if (copied == to_copy)
- ret = put_user(tmp, datap);
- break;
- }
-
- /* when I and D space are separate, this will have to be fixed. */
- case PTRACE_POKEDATA:
- pr_debug("ptrace: PTRACE_PEEKDATA\n");
- /* fall through */
- case PTRACE_POKETEXT: /* write the word at location addr. */
- {
- int copied = 0, to_copy = sizeof(data);
-
- ret = -EIO;
- pr_debug("ptrace: POKETEXT at addr 0x%08lx + %i bytes %lx\n",
- addr, to_copy, data);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &data,
- to_copy,
- FOLL_FORCE | FOLL_WRITE);
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d\n", copied);
- if (copied == to_copy)
- ret = 0;
- break;
- }
-
- case PTRACE_PEEKUSR:
- switch (addr) {
-#ifdef CONFIG_BINFMT_ELF_FDPIC /* backwards compat */
- case PT_FDPIC_EXEC:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_EXEC;
- goto case_default;
- case PT_FDPIC_INTERP:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_INTERP;
- goto case_default;
-#endif
- default:
- ret = get_reg(child, addr, datap);
- }
- pr_debug("ptrace: PEEKUSR reg %li with %#lx = %i\n", addr, data, ret);
- break;
-
- case PTRACE_POKEUSR:
- ret = put_reg(child, addr, data);
- pr_debug("ptrace: POKEUSR reg %li with %li = %i\n", addr, data, ret);
- break;
-
- case PTRACE_GETREGS:
- pr_debug("ptrace: PTRACE_GETREGS\n");
- return copy_regset_to_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case PTRACE_SETREGS:
- pr_debug("ptrace: PTRACE_SETREGS\n");
- return copy_regset_from_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case_default:
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-asmlinkage int syscall_trace_enter(struct pt_regs *regs)
-{
- int ret = 0;
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- ret = tracehook_report_syscall_entry(regs);
-
- return ret;
-}
-
-asmlinkage void syscall_trace_leave(struct pt_regs *regs)
-{
- int step;
-
- step = test_thread_flag(TIF_SINGLESTEP);
- if (step || test_thread_flag(TIF_SYSCALL_TRACE))
- tracehook_report_syscall_exit(regs, step);
-}
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
deleted file mode 100644
index c4f50a328501..000000000000
--- a/arch/blackfin/kernel/reboot.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <asm/bfin-global.h>
-#include <asm/reboot.h>
-#include <asm/bfrom.h>
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1. We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1. We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifndef CONFIG_BF60x
- if (!ANOMALY_05000353 && !ANOMALY_05000386)
- bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
-
- /* Wait for completion of "system" events such as cache line
- * line fills so that we avoid infinite stalls later on as
- * much as possible. This code is in L1, so it won't trigger
- * any such event after this point in time.
- */
- __builtin_bfin_ssync();
-
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
-
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
-
- /* Clear System software reset */
- bfin_write_SWRST(0);
-
- /* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- /* Seems to be fixed with newer parts though ... */
- if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
- bfin_read_SWRST();
-#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
-
- while (1)
- /* Issue core reset */
- asm("raise 1");
-#else
- while (1)
- bfin_write_RCU0_CTL(0x1);
-#endif
-}
-
-__attribute__((weak))
-void native_machine_restart(char *cmd)
-{
-}
-
-void machine_restart(char *cmd)
-{
- native_machine_restart(cmd);
- if (smp_processor_id())
- smp_call_function((void *)bfin_reset, 0, 1);
- else
- bfin_reset();
-}
-
-__attribute__((weak))
-void native_machine_halt(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_halt(void)
-{
- native_machine_halt();
-}
-
-__attribute__((weak))
-void native_machine_power_off(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_power_off(void)
-{
- native_machine_power_off();
-}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
deleted file mode 100644
index ad82468bd94d..000000000000
--- a/arch/blackfin/kernel/setup.c
+++ /dev/null
@@ -1,1468 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/delay.h>
-#include <linux/console.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/cpu.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/pfn.h>
-
-#ifdef CONFIG_MTD_UCLINUX
-#include <linux/mtd/map.h>
-#include <linux/ext2_fs.h>
-#include <uapi/linux/cramfs_fs.h>
-#include <linux/romfs_fs.h>
-#endif
-
-#include <asm/cplb.h>
-#include <asm/cacheflush.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/clocks.h>
-#include <asm/div64.h>
-#include <asm/cpu.h>
-#include <asm/fixed_code.h>
-#include <asm/early_printk.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-#ifdef CONFIG_BF60x
-#include <mach/pm.h>
-#endif
-#ifdef CONFIG_SCB_PRIORITY
-#include <asm/scb.h>
-#endif
-
-u16 _bfin_swrst;
-EXPORT_SYMBOL(_bfin_swrst);
-
-unsigned long memory_start, memory_end, physical_mem_end;
-unsigned long _rambase, _ramstart, _ramend;
-unsigned long reserved_mem_dcache_on;
-unsigned long reserved_mem_icache_on;
-EXPORT_SYMBOL(memory_start);
-EXPORT_SYMBOL(memory_end);
-EXPORT_SYMBOL(physical_mem_end);
-EXPORT_SYMBOL(_ramend);
-EXPORT_SYMBOL(reserved_mem_dcache_on);
-
-#ifdef CONFIG_MTD_UCLINUX
-extern struct map_info uclinux_ram_map;
-unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
-EXPORT_SYMBOL(memory_mtd_end);
-EXPORT_SYMBOL(memory_mtd_start);
-EXPORT_SYMBOL(mtd_size);
-#endif
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-struct blackfin_initial_pda __initdata initial_pda;
-
-/* boot memmap, for parsing "memmap=" */
-#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
-#define BFIN_MEMMAP_RAM 1
-#define BFIN_MEMMAP_RESERVED 2
-static struct bfin_memmap {
- int nr_map;
- struct bfin_memmap_entry {
- unsigned long long addr; /* start of memory segment */
- unsigned long long size;
- unsigned long type;
- } map[BFIN_MEMMAP_MAX];
-} bfin_memmap __initdata;
-
-/* for memmap sanitization */
-struct change_member {
- struct bfin_memmap_entry *pentry; /* pointer to original entry */
- unsigned long long addr; /* address for this change point */
-};
-static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
-static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
-
-DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-static int early_init_clkin_hz(char *buf);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-void __init generate_cplb_tables(void)
-{
- unsigned int cpu;
-
- generate_cplb_tables_all();
- /* Generate per-CPU I&D CPLB tables */
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- generate_cplb_tables_cpu(cpu);
-}
-#endif
-
-void bfin_setup_caches(unsigned int cpu)
-{
-#ifdef CONFIG_BFIN_ICACHE
- bfin_icache_init(icplb_tbl[cpu]);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- bfin_dcache_init(dcplb_tbl[cpu]);
-#endif
-
- bfin_setup_cpudata(cpu);
-
- /*
- * In cache coherence emulation mode, we need to have the
- * D-cache enabled before running any atomic operation which
- * might involve cache invalidation (i.e. spinlock, rwlock).
- * So printk's are deferred until then.
- */
-#ifdef CONFIG_BFIN_ICACHE
- printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# ifdef CONFIG_BFIN_L2_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
-
-#else
- printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# if defined CONFIG_BFIN_L2_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_L2_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
-#else
- printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
-#endif
-}
-
-void bfin_setup_cpudata(unsigned int cpu)
-{
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
-
- cpudata->imemctl = bfin_read_IMEM_CONTROL();
- cpudata->dmemctl = bfin_read_DMEM_CONTROL();
-}
-
-void __init bfin_cache_init(void)
-{
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
- generate_cplb_tables();
-#endif
- bfin_setup_caches(0);
-}
-
-void __init bfin_relocate_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
- unsigned long l2_len = (unsigned long)_l2_len;
-
- early_shadow_stamp();
-
- /*
- * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
- * we know that everything about l1 text/data is nice and aligned,
- * so copy by 4 byte chunks, and don't worry about overlapping
- * src/dest.
- *
- * We can't use the dma_memcpy functions, since they can call
- * scheduler functions which might be in L1 :( and core writes
- * into L1 instruction cause bad access errors, so we are stuck,
- * we are required to use DMA, but can't use the common dma
- * functions. We can't use memcpy either - since that might be
- * going to be in the relocated L1
- */
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
- blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
-#endif
-
- /* if necessary, copy L2 text/data to L2 SRAM */
- if (L2_LENGTH && l2_len)
- memcpy(_stext_l2, _l2_lma, l2_len);
-}
-
-#ifdef CONFIG_SMP
-void __init bfin_relocate_coreb_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
- text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
- data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
- data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
- blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
- (unsigned long)_stext_l1 + COREB_L1_CODE_START;
-#endif
-}
-#endif
-
-#ifdef CONFIG_ROMKERNEL
-void __init bfin_relocate_xip_data(void)
-{
- early_shadow_stamp();
-
- memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
- memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
-}
-#endif
-
-/* add_memory_region to memmap */
-static void __init add_memory_region(unsigned long long start,
- unsigned long long size, int type)
-{
- int i;
-
- i = bfin_memmap.nr_map;
-
- if (i == BFIN_MEMMAP_MAX) {
- printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
- return;
- }
-
- bfin_memmap.map[i].addr = start;
- bfin_memmap.map[i].size = size;
- bfin_memmap.map[i].type = type;
- bfin_memmap.nr_map++;
-}
-
-/*
- * Sanitize the boot memmap, removing overlaps.
- */
-static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
-{
- struct change_member *change_tmp;
- unsigned long current_type, last_type;
- unsigned long long last_addr;
- int chgidx, still_changing;
- int overlap_entries;
- int new_entry;
- int old_nr, new_nr, chg_nr;
- int i;
-
- /*
- Visually we're performing the following (1,2,3,4 = memory types)
-
- Sample memory map (w/overlaps):
- ____22__________________
- ______________________4_
- ____1111________________
- _44_____________________
- 11111111________________
- ____________________33__
- ___________44___________
- __________33333_________
- ______________22________
- ___________________2222_
- _________111111111______
- _____________________11_
- _________________4______
-
- Sanitized equivalent (no overlap):
- 1_______________________
- _44_____________________
- ___1____________________
- ____22__________________
- ______11________________
- _________1______________
- __________3_____________
- ___________44___________
- _____________33_________
- _______________2________
- ________________1_______
- _________________4______
- ___________________2____
- ____________________33__
- ______________________4_
- */
- /* if there's only one memory region, don't bother */
- if (*pnr_map < 2)
- return -1;
-
- old_nr = *pnr_map;
-
- /* bail out if we find any unreasonable addresses in memmap */
- for (i = 0; i < old_nr; i++)
- if (map[i].addr + map[i].size < map[i].addr)
- return -1;
-
- /* create pointers for initial change-point information (for sorting) */
- for (i = 0; i < 2*old_nr; i++)
- change_point[i] = &change_point_list[i];
-
- /* record all known change-points (starting and ending addresses),
- omitting those that are for empty memory regions */
- chgidx = 0;
- for (i = 0; i < old_nr; i++) {
- if (map[i].size != 0) {
- change_point[chgidx]->addr = map[i].addr;
- change_point[chgidx++]->pentry = &map[i];
- change_point[chgidx]->addr = map[i].addr + map[i].size;
- change_point[chgidx++]->pentry = &map[i];
- }
- }
- chg_nr = chgidx; /* true number of change-points */
-
- /* sort change-point list by memory addresses (low -> high) */
- still_changing = 1;
- while (still_changing) {
- still_changing = 0;
- for (i = 1; i < chg_nr; i++) {
- /* if <current_addr> > <last_addr>, swap */
- /* or, if current=<start_addr> & last=<end_addr>, swap */
- if ((change_point[i]->addr < change_point[i-1]->addr) ||
- ((change_point[i]->addr == change_point[i-1]->addr) &&
- (change_point[i]->addr == change_point[i]->pentry->addr) &&
- (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
- ) {
- change_tmp = change_point[i];
- change_point[i] = change_point[i-1];
- change_point[i-1] = change_tmp;
- still_changing = 1;
- }
- }
- }
-
- /* create a new memmap, removing overlaps */
- overlap_entries = 0; /* number of entries in the overlap table */
- new_entry = 0; /* index for creating new memmap entries */
- last_type = 0; /* start with undefined memory type */
- last_addr = 0; /* start with 0 as last starting address */
- /* loop through change-points, determining affect on the new memmap */
- for (chgidx = 0; chgidx < chg_nr; chgidx++) {
- /* keep track of all overlapping memmap entries */
- if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
- /* add map entry to overlap list (> 1 entry implies an overlap) */
- overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
- } else {
- /* remove entry from list (order independent, so swap with last) */
- for (i = 0; i < overlap_entries; i++) {
- if (overlap_list[i] == change_point[chgidx]->pentry)
- overlap_list[i] = overlap_list[overlap_entries-1];
- }
- overlap_entries--;
- }
- /* if there are overlapping entries, decide which "type" to use */
- /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
- current_type = 0;
- for (i = 0; i < overlap_entries; i++)
- if (overlap_list[i]->type > current_type)
- current_type = overlap_list[i]->type;
- /* continue building up new memmap based on this information */
- if (current_type != last_type) {
- if (last_type != 0) {
- new_map[new_entry].size =
- change_point[chgidx]->addr - last_addr;
- /* move forward only if the new size was non-zero */
- if (new_map[new_entry].size != 0)
- if (++new_entry >= BFIN_MEMMAP_MAX)
- break; /* no more space left for new entries */
- }
- if (current_type != 0) {
- new_map[new_entry].addr = change_point[chgidx]->addr;
- new_map[new_entry].type = current_type;
- last_addr = change_point[chgidx]->addr;
- }
- last_type = current_type;
- }
- }
- new_nr = new_entry; /* retain count for new entries */
-
- /* copy new mapping into original location */
- memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
- *pnr_map = new_nr;
-
- return 0;
-}
-
-static void __init print_memory_map(char *who)
-{
- int i;
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
- bfin_memmap.map[i].addr,
- bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
- switch (bfin_memmap.map[i].type) {
- case BFIN_MEMMAP_RAM:
- printk(KERN_CONT "(usable)\n");
- break;
- case BFIN_MEMMAP_RESERVED:
- printk(KERN_CONT "(reserved)\n");
- break;
- default:
- printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
- break;
- }
- }
-}
-
-static __init int parse_memmap(char *arg)
-{
- unsigned long long start_at, mem_size;
-
- if (!arg)
- return -EINVAL;
-
- mem_size = memparse(arg, &arg);
- if (*arg == '@') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
- } else if (*arg == '$') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
- }
-
- return 0;
-}
-
-/*
- * Initial parsing of the command line. Currently, we support:
- * - Controlling the linux memory size: mem=xxx[KMG]
- * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
- * $ -> reserved memory is dcacheable
- * # -> reserved memory is icacheable
- * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
- * @ from <start> to <start>+<mem>, type RAM
- * $ from <start> to <start>+<mem>, type RESERVED
- */
-static __init void parse_cmdline_early(char *cmdline_p)
-{
- char c = ' ', *to = cmdline_p;
- unsigned int memsize;
- for (;;) {
- if (c == ' ') {
- if (!memcmp(to, "mem=", 4)) {
- to += 4;
- memsize = memparse(to, &to);
- if (memsize)
- _ramend = memsize;
-
- } else if (!memcmp(to, "max_mem=", 8)) {
- to += 8;
- memsize = memparse(to, &to);
- if (memsize) {
- physical_mem_end = memsize;
- if (*to != ' ') {
- if (*to == '$'
- || *(to + 1) == '$')
- reserved_mem_dcache_on = 1;
- if (*to == '#'
- || *(to + 1) == '#')
- reserved_mem_icache_on = 1;
- }
- }
- } else if (!memcmp(to, "clkin_hz=", 9)) {
- to += 9;
- early_init_clkin_hz(to);
-#ifdef CONFIG_EARLY_PRINTK
- } else if (!memcmp(to, "earlyprintk=", 12)) {
- to += 12;
- setup_early_printk(to);
-#endif
- } else if (!memcmp(to, "memmap=", 7)) {
- to += 7;
- parse_memmap(to);
- }
- }
- c = *(to++);
- if (!c)
- break;
- }
-}
-
-/*
- * Setup memory defaults from user config.
- * The physical memory layout looks like:
- *
- * [_rambase, _ramstart]: kernel image
- * [memory_start, memory_end]: dynamic memory managed by kernel
- * [memory_end, _ramend]: reserved memory
- * [memory_mtd_start(memory_end),
- * memory_mtd_start + mtd_size]: rootfs (if any)
- * [_ramend - DMA_UNCACHED_REGION,
- * _ramend]: uncached DMA region
- * [_ramend, physical_mem_end]: memory not managed by kernel
- */
-static __init void memory_setup(void)
-{
-#ifdef CONFIG_MTD_UCLINUX
- unsigned long mtd_phys = 0;
-#endif
- unsigned long max_mem;
-
- _rambase = CONFIG_BOOT_LOAD;
- _ramstart = (unsigned long)_end;
-
- if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
- console_init();
- panic("DMA region exceeds memory limit: %lu.",
- _ramend - _ramstart);
- }
- max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
-
-#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
- /* Due to a Hardware Anomaly we need to limit the size of usable
- * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
- * 05000263 - Hardware loop corrupted when taking an ICPLB exception
- */
-# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
- if (max_mem >= 56 * 1024 * 1024)
- max_mem = 56 * 1024 * 1024;
-# else
- if (max_mem >= 60 * 1024 * 1024)
- max_mem = 60 * 1024 * 1024;
-# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
-#endif /* ANOMALY_05000263 */
-
-
-#ifdef CONFIG_MPU
- /* Round up to multiple of 4MB */
- memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
-#else
- memory_start = PAGE_ALIGN(_ramstart);
-#endif
-
-#if defined(CONFIG_MTD_UCLINUX)
- /* generic memory mapped MTD driver */
- memory_mtd_end = memory_end;
-
- mtd_phys = _ramstart;
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
-
-# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
- if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
- mtd_size =
- PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
-# endif
-
-# if defined(CONFIG_CRAMFS)
- if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
-# endif
-
-# if defined(CONFIG_ROMFS_FS)
- if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
- && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
- mtd_size =
- PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
-
- /* ROM_FS is XIP, so if we found it, we need to limit memory */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
- }
-# endif /* CONFIG_ROMFS_FS */
-
- /* Since the default MTD_UCLINUX has no magic number, we just blindly
- * read 8 past the end of the kernel's image, and look at it.
- * When no image is attached, mtd_size is set to a random number
- * Do some basic sanity checks before operating on things
- */
- if (mtd_size == 0 || memory_end <= mtd_size) {
- pr_emerg("Could not find valid ram mtd attached.\n");
- } else {
- memory_end -= mtd_size;
-
- /* Relocate MTD image to the top of memory after the uncached memory area */
- uclinux_ram_map.phys = memory_mtd_start = memory_end;
- uclinux_ram_map.size = mtd_size;
- pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
- _end, mtd_size, (void *)memory_mtd_start);
- dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
- }
-#endif /* CONFIG_MTD_UCLINUX */
-
- /* We need lo limit memory, since everything could have a text section
- * of userspace in it, and expose anomaly 05000263. If the anomaly
- * doesn't exist, or we don't need to - then dont.
- */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
-
-#ifdef CONFIG_MPU
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
- ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
-#else
- page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
-#endif
- page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
-#endif
-
- init_mm.start_code = (unsigned long)_stext;
- init_mm.end_code = (unsigned long)_etext;
- init_mm.end_data = (unsigned long)_edata;
- init_mm.brk = (unsigned long)0;
-
- printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
-
- printk(KERN_INFO "Memory map:\n"
- " fixedcode = 0x%p-0x%p\n"
- " text = 0x%p-0x%p\n"
- " rodata = 0x%p-0x%p\n"
- " bss = 0x%p-0x%p\n"
- " data = 0x%p-0x%p\n"
- " stack = 0x%p-0x%p\n"
- " init = 0x%p-0x%p\n"
- " available = 0x%p-0x%p\n"
-#ifdef CONFIG_MTD_UCLINUX
- " rootfs = 0x%p-0x%p\n"
-#endif
-#if DMA_UNCACHED_REGION > 0
- " DMA Zone = 0x%p-0x%p\n"
-#endif
- , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
- _stext, _etext,
- __start_rodata, __end_rodata,
- __bss_start, __bss_stop,
- _sdata, _edata,
- (void *)&init_thread_union,
- (void *)((int)(&init_thread_union) + THREAD_SIZE),
- __init_begin, __init_end,
- (void *)_ramstart, (void *)memory_end
-#ifdef CONFIG_MTD_UCLINUX
- , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
-#endif
-#if DMA_UNCACHED_REGION > 0
- , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
-#endif
- );
-}
-
-/*
- * Find the lowest, highest page frame number we have available
- */
-void __init find_min_max_pfn(void)
-{
- int i;
-
- max_pfn = 0;
- min_low_pfn = PFN_DOWN(memory_end);
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- unsigned long start, end;
- /* RAM? */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- start = PFN_UP(bfin_memmap.map[i].addr);
- end = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
- if (start >= end)
- continue;
- if (end > max_pfn)
- max_pfn = end;
- if (start < min_low_pfn)
- min_low_pfn = start;
- }
-}
-
-static __init void setup_bootmem_allocator(void)
-{
- int bootmap_size;
- int i;
- unsigned long start_pfn, end_pfn;
- unsigned long curr_pfn, last_pfn, size;
-
- /* mark memory between memory_start and memory_end usable */
- add_memory_region(memory_start,
- memory_end - memory_start, BFIN_MEMMAP_RAM);
- /* sanity check for overlap */
- sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
- print_memory_map("boot memmap");
-
- /* initialize globals in linux/bootmem.h */
- find_min_max_pfn();
- /* pfn of the last usable page frame */
- if (max_pfn > memory_end >> PAGE_SHIFT)
- max_pfn = memory_end >> PAGE_SHIFT;
- /* pfn of last page frame directly mapped by kernel */
- max_low_pfn = max_pfn;
- /* pfn of the first usable page frame after kernel image*/
- if (min_low_pfn < memory_start >> PAGE_SHIFT)
- min_low_pfn = memory_start >> PAGE_SHIFT;
- start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
- end_pfn = memory_end >> PAGE_SHIFT;
-
- /*
- * give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map at the start of memory.
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- memory_start >> PAGE_SHIFT, /* map goes here */
- start_pfn, end_pfn);
-
- /* register the memmap regions with the bootmem allocator */
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- /*
- * Reserve usable memory
- */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- /*
- * We are rounding up the start address of usable memory:
- */
- curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
- if (curr_pfn >= end_pfn)
- continue;
- /*
- * ... and at the end of the usable range downwards:
- */
- last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
-
- if (last_pfn > end_pfn)
- last_pfn = end_pfn;
-
- /*
- * .. finally, did all the rounding and playing
- * around just make the area go away?
- */
- if (last_pfn <= curr_pfn)
- continue;
-
- size = last_pfn - curr_pfn;
- free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
- }
-
- /* reserve memory before memory_start, including bootmap */
- reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
- memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
- BOOTMEM_DEFAULT);
-}
-
-#define EBSZ_TO_MEG(ebsz) \
-({ \
- int meg = 0; \
- switch (ebsz & 0xf) { \
- case 0x1: meg = 16; break; \
- case 0x3: meg = 32; break; \
- case 0x5: meg = 64; break; \
- case 0x7: meg = 128; break; \
- case 0x9: meg = 256; break; \
- case 0xb: meg = 512; break; \
- } \
- meg; \
-})
-static inline int __init get_mem_size(void)
-{
-#if defined(EBIU_SDBCTL)
-# if defined(BF561_FAMILY)
- int ret = 0;
- u32 sdbctl = bfin_read_EBIU_SDBCTL();
- ret += EBSZ_TO_MEG(sdbctl >> 0);
- ret += EBSZ_TO_MEG(sdbctl >> 8);
- ret += EBSZ_TO_MEG(sdbctl >> 16);
- ret += EBSZ_TO_MEG(sdbctl >> 24);
- return ret;
-# else
- return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
-# endif
-#elif defined(EBIU_DDRCTL1)
- u32 ddrctl = bfin_read_EBIU_DDRCTL1();
- int ret = 0;
- switch (ddrctl & 0xc0000) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- }
- switch (ddrctl & 0x30000) {
- case DEVWD_4:
- ret *= 2;
- case DEVWD_8:
- ret *= 2;
- case DEVWD_16:
- break;
- }
- if ((ddrctl & 0xc000) == 0x4000)
- ret *= 2;
- return ret;
-#elif defined(CONFIG_BF60x)
- u32 ddrctl = bfin_read_DMC0_CFG();
- int ret;
- switch (ddrctl & 0xf00) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- case DEVSZ_1G:
- ret = 1024 / 8;
- break;
- case DEVSZ_2G:
- ret = 2048 / 8;
- break;
- }
- return ret;
-#endif
- BUG();
-}
-
-__attribute__((weak))
-void __init native_machine_early_platform_add_devices(void)
-{
-}
-
-#ifdef CONFIG_BF60x
-static inline u_long bfin_get_clk(char *name)
-{
- struct clk *clk;
- u_long clk_rate;
-
- clk = clk_get(NULL, name);
- if (IS_ERR(clk))
- return 0;
-
- clk_rate = clk_get_rate(clk);
- clk_put(clk);
- return clk_rate;
-}
-#endif
-
-void __init setup_arch(char **cmdline_p)
-{
- u32 mmr;
- unsigned long sclk, cclk;
-
- native_machine_early_platform_add_devices();
-
- enable_shadow_console();
-
- /* Check to make sure we are running on the right processor */
- mmr = bfin_cpuid();
- if (unlikely(CPUID != bfin_cpuid()))
- printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
- CPU, bfin_cpuid(), bfin_revid());
-
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
-#if defined(CONFIG_CMDLINE_BOOL)
- strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
- command_line[sizeof(command_line) - 1] = 0;
-#endif
-
- /* Keep a copy of command line */
- *cmdline_p = &command_line[0];
- memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- memset(&bfin_memmap, 0, sizeof(bfin_memmap));
-
-#ifdef CONFIG_BF60x
- /* Should init clock device before parse command early */
- clk_init();
-#endif
- /* If the user does not specify things on the command line, use
- * what the bootloader set things up as
- */
- physical_mem_end = 0;
- parse_cmdline_early(&command_line[0]);
-
- if (_ramend == 0)
- _ramend = get_mem_size() * 1024 * 1024;
-
- if (physical_mem_end == 0)
- physical_mem_end = _ramend;
-
- memory_setup();
-
-#ifndef CONFIG_BF60x
- /* Initialize Async memory banks */
- bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
- bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
- bfin_write_EBIU_AMGCTL(AMGCTLVAL);
-#ifdef CONFIG_EBIU_MBSCTLVAL
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
-#endif
-#endif
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
- bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
- bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
- bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
- bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
- ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
-#endif
-
- cclk = get_cclk();
- sclk = get_sclk();
-
- if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
- panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
-
-#ifdef BF561_FAMILY
- if (ANOMALY_05000266) {
- bfin_read_IMDMA_D0_IRQ_STATUS();
- bfin_read_IMDMA_D1_IRQ_STATUS();
- }
-#endif
-
- mmr = bfin_read_TBUFCTL();
- printk(KERN_INFO "Hardware Trace %s and %sabled\n",
- (mmr & 0x1) ? "active" : "off",
- (mmr & 0x2) ? "en" : "dis");
-#ifndef CONFIG_BF60x
- mmr = bfin_read_SYSCR();
- printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
-
- /* Newer parts mirror SWRST bits in SYSCR */
-#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- _bfin_swrst = bfin_read_SWRST();
-#else
- /* Clear boot mode field */
- _bfin_swrst = mmr & ~0xf;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
-#endif
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
- bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
-#endif
-
-#ifdef CONFIG_SMP
- if (_bfin_swrst & SWRST_DBL_FAULT_A) {
-#else
- if (_bfin_swrst & RESET_DOUBLE) {
-#endif
- printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* We assume the crashing kernel, and the current symbol table match */
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda.retx);
- } else if (_bfin_swrst & RESET_WDOG)
- printk(KERN_INFO "Recovering from Watchdog event\n");
- else if (_bfin_swrst & RESET_SOFTWARE)
- printk(KERN_NOTICE "Reset caused by Software reset\n");
-#endif
- printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
- if (bfin_compiled_revid() == 0xffff)
- printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
- else if (bfin_compiled_revid() == -1)
- printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
- else
- printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
-
- if (likely(CPUID == bfin_cpuid())) {
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
- bfin_revid());
- else if (bfin_compiled_revid() != 0xffff) {
- printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
- bfin_compiled_revid(), bfin_revid());
- if (bfin_compiled_revid() > bfin_revid())
- panic("Error: you are missing anomaly workarounds for this rev");
- }
- }
- if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
- printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
- CPU, bfin_revid());
- }
-
- printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
-
-#ifdef CONFIG_BF60x
- printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
- cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
-#else
- printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
- cclk / 1000000, sclk / 1000000);
-#endif
-
- setup_bootmem_allocator();
-
- paging_init();
-
- /* Copy atomic sequences to their fixed location, and sanity check that
- these locations are the ones that we advertise to userspace. */
- memcpy((void *)FIXED_CODE_START, &fixed_code_start,
- FIXED_CODE_END - FIXED_CODE_START);
- BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
- != SIGRETURN_STUB - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
- != ATOMIC_XCHG32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
- != ATOMIC_CAS32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
- != ATOMIC_ADD32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
- != ATOMIC_SUB32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
- != ATOMIC_IOR32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
- != ATOMIC_AND32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
- != ATOMIC_XOR32 - FIXED_CODE_START);
- BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
- != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
-
-#ifdef CONFIG_SMP
- platform_init_cpus();
-#endif
- init_exception_vectors();
- bfin_cache_init(); /* Initialize caches for the boot CPU */
-#ifdef CONFIG_SCB_PRIORITY
- init_scb();
-#endif
-}
-
-static int __init topology_init(void)
-{
- unsigned int cpu;
-
- for_each_possible_cpu(cpu) {
- register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
- }
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-/* Get the input clock frequency */
-static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
-#ifndef CONFIG_BF60x
-static u_long get_clkin_hz(void)
-{
- return cached_clkin_hz;
-}
-#endif
-static int __init early_init_clkin_hz(char *buf)
-{
- cached_clkin_hz = simple_strtoul(buf, NULL, 0);
-#ifdef BFIN_KERNEL_CLOCK
- if (cached_clkin_hz != CONFIG_CLKIN_HZ)
- panic("cannot change clkin_hz when reprogramming clocks");
-#endif
- return 1;
-}
-early_param("clkin_hz=", early_init_clkin_hz);
-
-#ifndef CONFIG_BF60x
-/* Get the voltage input multiplier */
-static u_long get_vco(void)
-{
- static u_long cached_vco;
- u_long msel, pll_ctl;
-
- /* The assumption here is that VCO never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_vco)
- return cached_vco;
-
- pll_ctl = bfin_read_PLL_CTL();
- msel = (pll_ctl >> 9) & 0x3F;
- if (0 == msel)
- msel = 64;
-
- cached_vco = get_clkin_hz();
- cached_vco >>= (1 & pll_ctl); /* DF bit */
- cached_vco *= msel;
- return cached_vco;
-}
-#endif
-
-/* Get the Core clock */
-u_long get_cclk(void)
-{
-#ifdef CONFIG_BF60x
- return bfin_get_clk("CCLK");
-#else
- static u_long cached_cclk_pll_div, cached_cclk;
- u_long csel, ssel;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV();
- if (ssel == cached_cclk_pll_div)
- return cached_cclk;
- else
- cached_cclk_pll_div = ssel;
-
- csel = ((ssel >> 4) & 0x03);
- ssel &= 0xf;
- if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
- cached_cclk = get_vco() / ssel;
- else
- cached_cclk = get_vco() >> csel;
- return cached_cclk;
-#endif
-}
-EXPORT_SYMBOL(get_cclk);
-
-#ifdef CONFIG_BF60x
-/* Get the bf60x clock of SCLK0 domain */
-u_long get_sclk0(void)
-{
- return bfin_get_clk("SCLK0");
-}
-EXPORT_SYMBOL(get_sclk0);
-
-/* Get the bf60x clock of SCLK1 domain */
-u_long get_sclk1(void)
-{
- return bfin_get_clk("SCLK1");
-}
-EXPORT_SYMBOL(get_sclk1);
-
-/* Get the bf60x DRAM clock */
-u_long get_dclk(void)
-{
- return bfin_get_clk("DCLK");
-}
-EXPORT_SYMBOL(get_dclk);
-#endif
-
-/* Get the default system clock */
-u_long get_sclk(void)
-{
-#ifdef CONFIG_BF60x
- return get_sclk0();
-#else
- static u_long cached_sclk;
- u_long ssel;
-
- /* The assumption here is that SCLK never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_sclk)
- return cached_sclk;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV() & 0xf;
- if (0 == ssel) {
- printk(KERN_WARNING "Invalid System Clock\n");
- ssel = 1;
- }
-
- cached_sclk = get_vco() / ssel;
- return cached_sclk;
-#endif
-}
-EXPORT_SYMBOL(get_sclk);
-
-unsigned long sclk_to_usecs(unsigned long sclk)
-{
- u64 tmp = USEC_PER_SEC * (u64)sclk;
- do_div(tmp, get_sclk());
- return tmp;
-}
-EXPORT_SYMBOL(sclk_to_usecs);
-
-unsigned long usecs_to_sclk(unsigned long usecs)
-{
- u64 tmp = get_sclk() * (u64)usecs;
- do_div(tmp, USEC_PER_SEC);
- return tmp;
-}
-EXPORT_SYMBOL(usecs_to_sclk);
-
-/*
- * Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- char *cpu, *mmu, *fpu, *vendor, *cache;
- uint32_t revid;
- int cpu_num = *(unsigned int *)v;
- u_long sclk, cclk;
- u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
-
- cpu = CPU;
- mmu = "none";
- fpu = "none";
- revid = bfin_revid();
-
- sclk = get_sclk();
- cclk = get_cclk();
-
- switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
- case 0xca:
- vendor = "Analog Devices";
- break;
- default:
- vendor = "unknown";
- break;
- }
-
- seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
-
- if (CPUID == bfin_cpuid())
- seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
- else
- seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
- CPUID, bfin_cpuid());
-
- seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
- "stepping\t: %d ",
- cpu, cclk/1000000, sclk/1000000,
-#ifdef CONFIG_MPU
- "mpu on",
-#else
- "mpu off",
-#endif
- revid);
-
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- seq_printf(m, "(Compiled for Rev none)");
- else if (bfin_compiled_revid() == 0xffff)
- seq_printf(m, "(Compiled for Rev any)");
- else
- seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
- }
-
- seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
- cclk/1000000, cclk%1000000,
- sclk/1000000, sclk%1000000);
- seq_printf(m, "bogomips\t: %lu.%02lu\n"
- "Calibration\t: %lu loops\n",
- (loops_per_jiffy * HZ) / 500000,
- ((loops_per_jiffy * HZ) / 5000) % 100,
- (loops_per_jiffy * HZ));
-
- /* Check Cache configutation */
- switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
- case ACACHE_BSRAM:
- cache = "dbank-A/B\t: cache/sram";
- dcache_size = 16;
- dsup_banks = 1;
- break;
- case ACACHE_BCACHE:
- cache = "dbank-A/B\t: cache/cache";
- dcache_size = 32;
- dsup_banks = 2;
- break;
- case ASRAM_BSRAM:
- cache = "dbank-A/B\t: sram/sram";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- default:
- cache = "unknown";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- }
-
- /* Is it turned on? */
- if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
- dcache_size = 0;
-
- if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
- icache_size = 0;
-
- seq_printf(m, "cache size\t: %d KB(L1 icache) "
- "%d KB(L1 dcache) %d KB(L2 cache)\n",
- icache_size, dcache_size, 0);
- seq_printf(m, "%s\n", cache);
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
-
- if (icache_size)
- seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
- BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
- else
- seq_printf(m, "icache setup\t: off\n");
-
- seq_printf(m,
- "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
- dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
- BFIN_DLINES);
-#ifdef __ARCH_SYNC_CORE_DCACHE
- seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
-#endif
-#ifdef __ARCH_SYNC_CORE_ICACHE
- seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
-#endif
-
- seq_printf(m, "\n");
-
- if (cpu_num != num_possible_cpus() - 1)
- return 0;
-
- if (L2_LENGTH) {
- seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
- }
- seq_printf(m, "board name\t: %s\n", bfin_board_name);
- seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
- physical_mem_end >> 10, 0ul, physical_mem_end);
- seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
- ((int)memory_end - (int)_rambase) >> 10,
- _rambase, memory_end);
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- if (*pos == 0)
- *pos = cpumask_first(cpu_online_mask);
- if (*pos >= num_online_cpus())
- return NULL;
-
- return pos;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- *pos = cpumask_next(*pos, cpu_online_mask);
-
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-void __init cmdline_init(const char *r0)
-{
- early_shadow_stamp();
- if (r0)
- strlcpy(command_line, r0, COMMAND_LINE_SIZE);
-}
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c
deleted file mode 100644
index aeb8343eeb03..000000000000
--- a/arch/blackfin/kernel/shadow_console.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * manage a small early shadow of the log buffer which we can pass between the
- * bootloader so early crash messages are communicated properly and easily
- *
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
-#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
-#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
-#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
-
-static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
-
-__init void early_shadow_write(struct console *con, const char *s,
- unsigned int n)
-{
- unsigned int i;
- /*
- * save 2 bytes for the double null at the end
- * once we fail on a long line, make sure we don't write a short line afterwards
- */
- if ((shadow_console_buffer + n) <= (char *)(SHADOW_CONSOLE_END - 2)) {
- /* can't use memcpy - it may not be relocated yet */
- for (i = 0; i <= n; i++)
- shadow_console_buffer[i] = s[i];
- shadow_console_buffer += n;
- shadow_console_buffer[0] = 0;
- shadow_console_buffer[1] = 0;
- } else
- shadow_console_buffer = (char *)SHADOW_CONSOLE_END;
-}
-
-static __initdata struct console early_shadow_console = {
- .name = "early_shadow",
- .write = early_shadow_write,
- .flags = CON_BOOT | CON_PRINTBUFFER,
- .index = -1,
- .device = 0,
-};
-
-__init int shadow_console_enabled(void)
-{
- return early_shadow_console.flags & CON_ENABLED;
-}
-
-__init void mark_shadow_error(void)
-{
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
- loc[0] = SHADOW_CONSOLE_MAGIC;
- loc[1] = SHADOW_CONSOLE_START;
-}
-
-__init void enable_shadow_console(void)
-{
- if (!shadow_console_enabled()) {
- register_console(&early_shadow_console);
- /* for now, assume things are going to fail */
- mark_shadow_error();
- }
-}
-
-static __init int disable_shadow_console(void)
-{
- /*
- * by the time pure_initcall runs, the standard console is enabled,
- * and the early_console is off, so unset the magic numbers
- * unregistering the console is taken care of in common code (See
- * ./kernel/printk:disable_boot_consoles() )
- */
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
-
- loc[0] = 0;
-
- return 0;
-}
-pure_initcall(disable_shadow_console);
-
-/*
- * since we can't use printk, dump numbers (as hex), n = # bits
- */
-__init void early_shadow_reg(unsigned long reg, unsigned int n)
-{
- /*
- * can't use any "normal" kernel features, since thay
- * may not be relocated to their execute address yet
- */
- int i;
- char ascii[11] = " 0x";
-
- n = n / 4;
- reg = reg << ((8 - n) * 4);
- n += 3;
-
- for (i = 3; i <= n ; i++) {
- ascii[i] = hex_asc_lo(reg >> 28);
- reg <<= 4;
- }
- early_shadow_write(NULL, ascii, n);
-
-}
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
deleted file mode 100644
index 5f5172779204..000000000000
--- a/arch/blackfin/kernel/signal.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/signal.h>
-#include <linux/syscalls.h>
-#include <linux/ptrace.h>
-#include <linux/tty.h>
-#include <linux/personality.h>
-#include <linux/binfmts.h>
-#include <linux/uaccess.h>
-#include <linux/tracehook.h>
-#include <linux/sched/task_stack.h>
-
-#include <asm/cacheflush.h>
-#include <asm/ucontext.h>
-#include <asm/fixed_code.h>
-#include <asm/syscall.h>
-
-/* Location of the trace bit in SYSCFG. */
-#define TRACE_BITS 0x0001
-
-struct fdpic_func_descriptor {
- unsigned long text;
- unsigned long GOT;
-};
-
-struct rt_sigframe {
- int sig;
- struct siginfo *pinfo;
- void *puc;
- /* This is no longer needed by the kernel, but unfortunately userspace
- * code expects it to be there. */
- char retcode[8];
- struct siginfo info;
- struct ucontext uc;
-};
-
-static inline int
-rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *pr0)
-{
- unsigned long usp = 0;
- int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
-#define RESTORE(x) err |= __get_user(regs->x, &sc->sc_##x)
-
- /* restore passed registers */
- RESTORE(r0); RESTORE(r1); RESTORE(r2); RESTORE(r3);
- RESTORE(r4); RESTORE(r5); RESTORE(r6); RESTORE(r7);
- RESTORE(p0); RESTORE(p1); RESTORE(p2); RESTORE(p3);
- RESTORE(p4); RESTORE(p5);
- err |= __get_user(usp, &sc->sc_usp);
- wrusp(usp);
- RESTORE(a0w); RESTORE(a1w);
- RESTORE(a0x); RESTORE(a1x);
- RESTORE(astat);
- RESTORE(rets);
- RESTORE(pc);
- RESTORE(retx);
- RESTORE(fp);
- RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3);
- RESTORE(m0); RESTORE(m1); RESTORE(m2); RESTORE(m3);
- RESTORE(l0); RESTORE(l1); RESTORE(l2); RESTORE(l3);
- RESTORE(b0); RESTORE(b1); RESTORE(b2); RESTORE(b3);
- RESTORE(lc0); RESTORE(lc1);
- RESTORE(lt0); RESTORE(lt1);
- RESTORE(lb0); RESTORE(lb1);
- RESTORE(seqstat);
-
- regs->orig_p0 = -1; /* disable syscall checks */
-
- *pr0 = regs->r0;
- return err;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- unsigned long usp = rdusp();
- struct rt_sigframe *frame = (struct rt_sigframe *)(usp);
- sigset_t set;
- int r0;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (rt_restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return r0;
-
- badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-static inline int rt_setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs)
-{
- int err = 0;
-
-#define SETUP(x) err |= __put_user(regs->x, &sc->sc_##x)
-
- SETUP(r0); SETUP(r1); SETUP(r2); SETUP(r3);
- SETUP(r4); SETUP(r5); SETUP(r6); SETUP(r7);
- SETUP(p0); SETUP(p1); SETUP(p2); SETUP(p3);
- SETUP(p4); SETUP(p5);
- err |= __put_user(rdusp(), &sc->sc_usp);
- SETUP(a0w); SETUP(a1w);
- SETUP(a0x); SETUP(a1x);
- SETUP(astat);
- SETUP(rets);
- SETUP(pc);
- SETUP(retx);
- SETUP(fp);
- SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3);
- SETUP(m0); SETUP(m1); SETUP(m2); SETUP(m3);
- SETUP(l0); SETUP(l1); SETUP(l2); SETUP(l3);
- SETUP(b0); SETUP(b1); SETUP(b2); SETUP(b3);
- SETUP(lc0); SETUP(lc1);
- SETUP(lt0); SETUP(lt1);
- SETUP(lb0); SETUP(lb1);
- SETUP(seqstat);
-
- return err;
-}
-
-static inline void *get_sigframe(struct ksignal *ksig,
- size_t frame_size)
-{
- unsigned long usp = sigsp(rdusp(), ksig);
-
- return (void *)((usp - frame_size) & -8UL);
-}
-
-static int
-setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- struct rt_sigframe *frame;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- err |= __put_user(ksig->sig, &frame->sig);
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
-
- /* Create the ucontext. */
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, &frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
- err |= rt_setup_sigcontext(&frame->uc.uc_mcontext, regs);
- err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor *) ksig->ka.sa.sa_handler;
- u32 pc, p3;
- err |= __get_user(pc, &funcptr->text);
- err |= __get_user(p3, &funcptr->GOT);
- if (err)
- return -EFAULT;
- regs->pc = pc;
- regs->p3 = p3;
- } else
- regs->pc = (unsigned long)ksig->ka.sa.sa_handler;
- wrusp((unsigned long)frame);
- regs->rets = SIGRETURN_STUB;
-
- regs->r0 = frame->sig;
- regs->r1 = (unsigned long)(&frame->info);
- regs->r2 = (unsigned long)(&frame->uc);
-
- return 0;
-}
-
-static inline void
-handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
-{
- switch (regs->r0) {
- case -ERESTARTNOHAND:
- if (!has_handler)
- goto do_restart;
- regs->r0 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
- regs->r0 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- do_restart:
- regs->p0 = regs->orig_p0;
- regs->r0 = regs->orig_r0;
- regs->pc -= 2;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- regs->p0 = __NR_restart_syscall;
- regs->pc -= 2;
- break;
- }
-}
-
-/*
- * OK, we're invoking a handler
- */
-static void
-handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- int ret;
-
- /* are we from a system call? to see pt_regs->orig_p0 */
- if (regs->orig_p0 >= 0)
- /* If so, check system call restarting.. */
- handle_restart(regs, &ksig->ka, 1);
-
- /* set up the stack frame */
- ret = setup_rt_frame(ksig, sigmask_to_save(), regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Note that we go through the signals twice: once to check the signals
- * that the kernel can handle, and then we build all the user-level signal
- * handling stack-frames in one go after that.
- */
-asmlinkage void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- current->thread.esp0 = (unsigned long)regs;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
- return;
- }
-
- /* Did we come from a system call? */
- if (regs->orig_p0 >= 0)
- /* Restart the system call - no handlers present */
- handle_restart(regs, NULL, 0);
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- */
-asmlinkage void do_notify_resume(struct pt_regs *regs)
-{
- if (test_thread_flag(TIF_SIGPENDING))
- do_signal(regs);
-
- if (test_thread_flag(TIF_NOTIFY_RESUME)) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
-
diff --git a/arch/blackfin/kernel/stacktrace.c b/arch/blackfin/kernel/stacktrace.c
deleted file mode 100644
index 17198f3650b6..000000000000
--- a/arch/blackfin/kernel/stacktrace.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Blackfin stacktrace code (mostly copied from avr32)
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/stacktrace.h>
-#include <linux/thread_info.h>
-#include <linux/module.h>
-
-register unsigned long current_frame_pointer asm("FP");
-
-struct stackframe {
- unsigned long fp;
- unsigned long rets;
-};
-
-/*
- * Save stack-backtrace addresses into a stack_trace buffer.
- */
-void save_stack_trace(struct stack_trace *trace)
-{
- unsigned long low, high;
- unsigned long fp;
- struct stackframe *frame;
- int skip = trace->skip;
-
- low = (unsigned long)task_stack_page(current);
- high = low + THREAD_SIZE;
- fp = current_frame_pointer;
-
- while (fp >= low && fp <= (high - sizeof(*frame))) {
- frame = (struct stackframe *)fp;
-
- if (skip) {
- skip--;
- } else {
- trace->entries[trace->nr_entries++] = frame->rets;
- if (trace->nr_entries >= trace->max_entries)
- break;
- }
-
- /*
- * The next frame must be at a higher address than the
- * current frame.
- */
- low = fp + sizeof(*frame);
- fp = frame->fp;
- }
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
deleted file mode 100644
index d998383cb956..000000000000
--- a/arch/blackfin/kernel/sys_bfin.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * contains various random system calls that have a non-standard
- * calling sequence on the Linux/Blackfin platform.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/spinlock.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/ipc.h>
-#include <linux/unistd.h>
-
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/cachectl.h>
-#include <asm/ptrace.h>
-
-asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
-{
- return sram_alloc_with_lsl(size, flags);
-}
-
-asmlinkage int sys_sram_free(const void *addr)
-{
- return sram_free_with_lsl(addr);
-}
-
-asmlinkage void *sys_dma_memcpy(void *dest, const void *src, size_t len)
-{
- return safe_dma_memcpy(dest, src, len);
-}
-
-#if defined(CONFIG_FB) || defined(CONFIG_FB_MODULE)
-#include <linux/fb.h>
-#include <linux/export.h>
-unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
- unsigned long len, unsigned long pgoff, unsigned long flags)
-{
- struct fb_info *info = filp->private_data;
- return (unsigned long)info->screen_base;
-}
-EXPORT_SYMBOL(get_fb_unmapped_area);
-#endif
-
-/* Needed for legacy userspace atomic emulation */
-static DEFINE_SPINLOCK(bfin_spinlock_lock);
-
-#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int sys_bfin_spinlock(int *p)
-{
- int ret, tmp = 0;
-
- spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
- ret = get_user(tmp, p);
- if (likely(ret == 0)) {
- if (unlikely(tmp))
- ret = 1;
- else
- put_user(1, p);
- }
- spin_unlock(&bfin_spinlock_lock);
-
- return ret;
-}
-
-SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op)
-{
- if (is_user_addr_valid(current, addr, len) != 0)
- return -EINVAL;
-
- if (op & DCACHE)
- blackfin_dcache_flush_range(addr, addr + len);
- if (op & ICACHE)
- blackfin_icache_flush_range(addr, addr + len);
-
- return 0;
-}
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
deleted file mode 100644
index 01350557fbd7..000000000000
--- a/arch/blackfin/kernel/time-ts.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * Based on arm clockevents implementation and old bfin time tick.
- *
- * Copyright 2008-2009 Analog Devics Inc.
- * 2008 GeoTechnologies
- * Vitja Makarov
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpufreq.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-#include <asm/nmi.h>
-
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-
-static notrace u64 bfin_read_cycles(struct clocksource *cs)
-{
-#ifdef CONFIG_CPU_FREQ
- return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
-#else
- return get_cycles();
-#endif
-}
-
-static struct clocksource bfin_cs_cycles = {
- .name = "bfin_cs_cycles",
- .rating = 400,
- .read = bfin_read_cycles,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_cycles_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
- bfin_cs_cycles.mult, bfin_cs_cycles.shift);
-}
-
-static int __init bfin_cs_cycles_init(void)
-{
- if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_cycles_init()
-#endif
-
-#ifdef CONFIG_GPTMR0_CLOCKSOURCE
-
-void __init setup_gptimer0(void)
-{
- disable_gptimers(TIMER0bit);
-
-#ifdef CONFIG_BF60x
- bfin_write16(TIMER_DATA_IMSK, 0);
- set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
- | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
-#else
- set_gptimer_config(TIMER0_id, \
- TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#endif
- set_gptimer_period(TIMER0_id, -1);
- set_gptimer_pwidth(TIMER0_id, -2);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-
-static u64 bfin_read_gptimer0(struct clocksource *cs)
-{
- return bfin_read_TIMER0_COUNTER();
-}
-
-static struct clocksource bfin_cs_gptimer0 = {
- .name = "bfin_cs_gptimer0",
- .rating = 350,
- .read = bfin_read_gptimer0,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
- bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
-}
-
-static int __init bfin_cs_gptimer0_init(void)
-{
- setup_gptimer0();
-
- if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_gptimer0_init()
-#endif
-
-#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
-/* prefer to use cycles since it has higher rating */
-notrace unsigned long long sched_clock(void)
-{
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
- return bfin_cs_cycles_sched_clock();
-#else
- return bfin_cs_gptimer0_sched_clock();
-#endif
-}
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
-static int bfin_gptmr0_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-
- /* it starts counting three SCLK cycles after the TIMENx bit is set */
- set_gptimer_pwidth(TIMER0_id, cycles - 3);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_periodic(struct clock_event_device *evt)
-{
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA |
- TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM_CONT |
- TIMER_PULSE_HI | TIMER_IRQ_PER);
-#endif
-
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI |
- TIMER_IRQ_WID_DLY);
-#endif
-
- set_gptimer_period(TIMER0_id, 0);
- return 0;
-}
-
-static int bfin_gptmr0_shutdown(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
- return 0;
-}
-
-static void bfin_gptmr0_ack(void)
-{
- clear_gptimer_intr(TIMER0_id);
-}
-
-static void __init bfin_gptmr0_init(void)
-{
- disable_gptimers(TIMER0bit);
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
- smp_mb();
- /*
- * We want to ACK before we handle so that we can handle smaller timer
- * intervals. This way if the timer expires again while we're handling
- * things, we're more likely to see that 2nd int rather than swallowing
- * it by ACKing the int at the end of this handler.
- */
- bfin_gptmr0_ack();
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction gptmr0_irq = {
- .name = "Blackfin GPTimer0",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_gptmr0_interrupt,
-};
-
-static struct clock_event_device clockevent_gptmr0 = {
- .name = "bfin_gptimer0",
- .rating = 300,
- .irq = IRQ_TIMER0,
- .shift = 32,
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = bfin_gptmr0_set_next_event,
- .set_state_shutdown = bfin_gptmr0_shutdown,
- .set_state_periodic = bfin_gptmr0_set_periodic,
- .set_state_oneshot = bfin_gptmr0_set_oneshot,
-};
-
-static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
-{
- unsigned long clock_tick;
-
- clock_tick = get_sclk();
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(0);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_GPTMR0 */
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-/* per-cpu local core timer */
-DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
-
-static int bfin_coretmr_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TCOUNT(cycles);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN);
- return 0;
-}
-
-static int bfin_coretmr_set_periodic(struct clock_event_device *evt)
-{
- unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
-
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
- return 0;
-}
-
-static int bfin_coretmr_set_oneshot(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
- return 0;
-}
-
-static int bfin_coretmr_shutdown(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(0);
- CSYNC();
- return 0;
-}
-
-void bfin_coretmr_init(void)
-{
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter. */
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
-
- CSYNC();
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-
-irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
- smp_mb();
- evt->event_handler(evt);
-
- touch_nmi_watchdog();
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction coretmr_irq = {
- .name = "Blackfin CoreTimer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_coretmr_interrupt,
-};
-
-void bfin_coretmr_clockevent_init(void)
-{
- unsigned long clock_tick;
- unsigned int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
-#ifdef CONFIG_SMP
- evt->broadcast = smp_timer_broadcast;
-#endif
-
- evt->name = "bfin_core_timer";
- evt->rating = 350;
- evt->irq = -1;
- evt->shift = 32;
- evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->set_next_event = bfin_coretmr_set_next_event;
- evt->set_state_shutdown = bfin_coretmr_shutdown;
- evt->set_state_periodic = bfin_coretmr_set_periodic;
- evt->set_state_oneshot = bfin_coretmr_set_oneshot;
-
- clock_tick = get_cclk() / TIME_SCALE;
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(cpu);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_CORETMR */
-
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- bfin_cs_cycles_init();
- bfin_cs_gptimer0_init();
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- bfin_coretmr_init();
- setup_irq(IRQ_CORETMR, &coretmr_irq);
- bfin_coretmr_clockevent_init();
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_gptmr0_init();
- setup_irq(IRQ_TIMER0, &gptmr0_irq);
- gptmr0_irq.dev_id = &clockevent_gptmr0;
- bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
-#endif
-
-#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
-# error at least one clock event device is required
-#endif
-}
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
deleted file mode 100644
index 3126b920a4a5..000000000000
--- a/arch/blackfin/kernel/time.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * arch/blackfin/kernel/time.c
- *
- * This file contains the Blackfin-specific time handling details.
- * Most of the stuff is located in the machine specific files.
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-
-/* This is an NTP setting */
-#define TICK_SIZE (tick_nsec / 1000)
-
-static struct irqaction bfin_timer_irq = {
- .name = "Blackfin Timer Tick",
-};
-
-#if defined(CONFIG_IPIPE)
-void __init setup_system_timer0(void)
-{
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-
- disable_gptimers(TIMER0bit);
- set_gptimer_status(0, TIMER_STATUS_TRUN0);
- while (get_gptimer_status(0) & TIMER_STATUS_TRUN0)
- udelay(10);
-
- set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, 1);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-#else
-void __init setup_core_timer(void)
-{
- u32 tcount;
-
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter */
- bfin_write_TSCALE(TIME_SCALE - 1);
-
- tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
-
- /* now enable the timer */
- CSYNC();
-
- bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
-}
-#endif
-
-static void __init
-time_sched_init(irqreturn_t(*timer_routine) (int, void *))
-{
-#if defined(CONFIG_IPIPE)
- setup_system_timer0();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_TIMER0, &bfin_timer_irq);
-#else
- setup_core_timer();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_CORETMR, &bfin_timer_irq);
-#endif
-}
-
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
-/*
- * Should return useconds since last timer tick
- */
-static u32 blackfin_gettimeoffset(void)
-{
- unsigned long offset;
- unsigned long clocks_per_jiffy;
-
-#if defined(CONFIG_IPIPE)
- clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
- offset = bfin_read_TIMER0_COUNTER() / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2))
- offset += (USEC_PER_SEC / HZ);
-#else
- clocks_per_jiffy = bfin_read_TPERIOD();
- offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- /* Check if we just wrapped the counters and maybe missed a tick */
- if ((bfin_read_ILAT() & (1 << IRQ_CORETMR))
- && (offset < (100000 / HZ / 2)))
- offset += (USEC_PER_SEC / HZ);
-#endif
- return offset;
-}
-#endif
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t timer_interrupt(int irq, void *dummy)
-{
- xtime_update(1);
-
-#ifdef CONFIG_IPIPE
- update_root_process_times(get_irq_regs());
-#else
- update_process_times(user_mode(get_irq_regs()));
-#endif
- profile_tick(CPU_PROFILING);
-
- return IRQ_HANDLED;
-}
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
- arch_gettimeoffset = blackfin_gettimeoffset;
-#endif
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- time_sched_init(timer_interrupt);
-}
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
deleted file mode 100644
index 151f22196ab6..000000000000
--- a/arch/blackfin/kernel/trace.c
+++ /dev/null
@@ -1,988 +0,0 @@
-/* provide some functions which dump the trace buffer, in a nice way for people
- * to read it, and understand what is going on
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/hardirq.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/oom.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/traps.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-
-void decode_address(char *buf, unsigned long address)
-{
- struct task_struct *p;
- struct mm_struct *mm;
- unsigned long offset;
- struct rb_node *n;
-
-#ifdef CONFIG_KALLSYMS
- unsigned long symsize;
- const char *symname;
- char *modname;
- char *delim = ":";
- char namebuf[128];
-#endif
-
- buf += sprintf(buf, "<0x%08lx> ", address);
-
-#ifdef CONFIG_KALLSYMS
- /* look up the address and see if we are in kernel space */
- symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
-
- if (symname) {
- /* yeah! kernel space! */
- if (!modname)
- modname = delim = "";
- sprintf(buf, "{ %s%s%s%s + 0x%lx }",
- delim, modname, delim, symname,
- (unsigned long)offset);
- return;
- }
-#endif
-
- if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
- /* Problem in fixed code section? */
- strcat(buf, "/* Maybe fixed code section */");
- return;
-
- } else if (address < CONFIG_BOOT_LOAD) {
- /* Problem somewhere before the kernel start address */
- strcat(buf, "/* Maybe null pointer? */");
- return;
-
- } else if (address >= COREMMR_BASE) {
- strcat(buf, "/* core mmrs */");
- return;
-
- } else if (address >= SYSMMR_BASE) {
- strcat(buf, "/* system mmrs */");
- return;
-
- } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
- strcat(buf, "/* on-chip L1 ROM */");
- return;
-
- } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
- strcat(buf, "/* on-chip scratchpad */");
- return;
-
- } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
- strcat(buf, "/* unconnected memory */");
- return;
-
- } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
- strcat(buf, "/* reserved memory */");
- return;
-
- } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
- strcat(buf, "/* on-chip Data Bank A */");
- return;
-
- } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
- strcat(buf, "/* on-chip Data Bank B */");
- return;
- }
-
- /*
- * Don't walk any of the vmas if we are oopsing, it has been known
- * to cause problems - corrupt vmas (kernel crashes) cause double faults
- */
- if (oops_in_progress) {
- strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
- return;
- }
-
- /* looks like we're off in user-land, so let's walk all the
- * mappings of all our processes and see if we can't be a whee
- * bit more specific
- */
- read_lock(&tasklist_lock);
- for_each_process(p) {
- struct task_struct *t;
-
- t = find_lock_task_mm(p);
- if (!t)
- continue;
-
- mm = t->mm;
- if (!down_read_trylock(&mm->mmap_sem))
- goto __continue;
-
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- struct vm_area_struct *vma;
-
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
-
- if (address >= vma->vm_start && address < vma->vm_end) {
- char _tmpbuf[256];
- char *name = t->comm;
- struct file *file = vma->vm_file;
-
- if (file) {
- char *d_name = file_path(file, _tmpbuf,
- sizeof(_tmpbuf));
- if (!IS_ERR(d_name))
- name = d_name;
- }
-
- /* FLAT does not have its text aligned to the start of
- * the map while FDPIC ELF does ...
- */
-
- /* before we can check flat/fdpic, we need to
- * make sure current is valid
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3)) {
- if (current->mm &&
- (address > current->mm->start_code) &&
- (address < current->mm->end_code))
- offset = address - current->mm->start_code;
- else
- offset = (address - vma->vm_start) +
- (vma->vm_pgoff << PAGE_SHIFT);
-
- sprintf(buf, "[ %s + 0x%lx ]", name, offset);
- } else
- sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
- name, vma->vm_start, vma->vm_end);
-
- up_read(&mm->mmap_sem);
- task_unlock(t);
-
- if (buf[0] == '\0')
- sprintf(buf, "[ %s ] dynamic memory", name);
-
- goto done;
- }
- }
-
- up_read(&mm->mmap_sem);
-__continue:
- task_unlock(t);
- }
-
- /*
- * we were unable to find this address anywhere,
- * or some MMs were skipped because they were in use.
- */
- sprintf(buf, "/* kernel dynamic memory */");
-
-done:
- read_unlock(&tasklist_lock);
-}
-
-#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
-
-/*
- * Similar to get_user, do some address checking, then dereference
- * Return true on success, false on bad address
- */
-bool get_mem16(unsigned short *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- switch (bfin_mem_access_type(addr, 2)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- *val = *address;
- return true;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy(val, address, 2);
- return true;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy(val, address, 2);
- return true;
- default: /* invalid access */
- return false;
- }
-}
-
-bool get_instruction(unsigned int *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
- unsigned short opcode0, opcode1;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- /* MMR region will never have instructions */
- if (addr >= SYSMMR_BASE)
- return false;
-
- /* Scratchpad will never have instructions */
- if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
- return false;
-
- /* Data banks will never have instructions */
- if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
- return false;
-
- if (!get_mem16(&opcode0, address))
- return false;
-
- /* was this a 32-bit instruction? If so, get the next 16 bits */
- if ((opcode0 & 0xc000) == 0xc000) {
- if (!get_mem16(&opcode1, address + 1))
- return false;
- *val = (opcode0 << 16) + opcode1;
- } else
- *val = opcode0;
-
- return true;
-}
-
-#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
-/*
- * decode the instruction if we are printing out the trace, as it
- * makes things easier to follow, without running it through objdump
- * Decode the change of flow, and the common load/store instructions
- * which are the main cause for faults, and discontinuities in the trace
- * buffer.
- */
-
-#define ProgCtrl_opcode 0x0000
-#define ProgCtrl_poprnd_bits 0
-#define ProgCtrl_poprnd_mask 0xf
-#define ProgCtrl_prgfunc_bits 4
-#define ProgCtrl_prgfunc_mask 0xf
-#define ProgCtrl_code_bits 8
-#define ProgCtrl_code_mask 0xff
-
-static void decode_ProgCtrl_0(unsigned int opcode)
-{
- int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
- int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
-
- if (prgfunc == 0 && poprnd == 0)
- pr_cont("NOP");
- else if (prgfunc == 1 && poprnd == 0)
- pr_cont("RTS");
- else if (prgfunc == 1 && poprnd == 1)
- pr_cont("RTI");
- else if (prgfunc == 1 && poprnd == 2)
- pr_cont("RTX");
- else if (prgfunc == 1 && poprnd == 3)
- pr_cont("RTN");
- else if (prgfunc == 1 && poprnd == 4)
- pr_cont("RTE");
- else if (prgfunc == 2 && poprnd == 0)
- pr_cont("IDLE");
- else if (prgfunc == 2 && poprnd == 3)
- pr_cont("CSYNC");
- else if (prgfunc == 2 && poprnd == 4)
- pr_cont("SSYNC");
- else if (prgfunc == 2 && poprnd == 5)
- pr_cont("EMUEXCPT");
- else if (prgfunc == 3)
- pr_cont("CLI R%i", poprnd);
- else if (prgfunc == 4)
- pr_cont("STI R%i", poprnd);
- else if (prgfunc == 5)
- pr_cont("JUMP (P%i)", poprnd);
- else if (prgfunc == 6)
- pr_cont("CALL (P%i)", poprnd);
- else if (prgfunc == 7)
- pr_cont("CALL (PC + P%i)", poprnd);
- else if (prgfunc == 8)
- pr_cont("JUMP (PC + P%i", poprnd);
- else if (prgfunc == 9)
- pr_cont("RAISE %i", poprnd);
- else if (prgfunc == 10)
- pr_cont("EXCPT %i", poprnd);
- else
- pr_cont("0x%04x", opcode);
-
-}
-
-#define BRCC_opcode 0x1000
-#define BRCC_offset_bits 0
-#define BRCC_offset_mask 0x3ff
-#define BRCC_B_bits 10
-#define BRCC_B_mask 0x1
-#define BRCC_T_bits 11
-#define BRCC_T_mask 0x1
-#define BRCC_code_bits 12
-#define BRCC_code_mask 0xf
-
-static void decode_BRCC_0(unsigned int opcode)
-{
- int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
- int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
-
- pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
-}
-
-#define CALLa_opcode 0xe2000000
-#define CALLa_addr_bits 0
-#define CALLa_addr_mask 0xffffff
-#define CALLa_S_bits 24
-#define CALLa_S_mask 0x1
-#define CALLa_code_bits 25
-#define CALLa_code_mask 0x7f
-
-static void decode_CALLa_0(unsigned int opcode)
-{
- int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
-
- if (S)
- pr_cont("CALL pcrel");
- else
- pr_cont("JUMP.L");
-}
-
-#define LoopSetup_opcode 0xe0800000
-#define LoopSetup_eoffset_bits 0
-#define LoopSetup_eoffset_mask 0x3ff
-#define LoopSetup_dontcare_bits 10
-#define LoopSetup_dontcare_mask 0x3
-#define LoopSetup_reg_bits 12
-#define LoopSetup_reg_mask 0xf
-#define LoopSetup_soffset_bits 16
-#define LoopSetup_soffset_mask 0xf
-#define LoopSetup_c_bits 20
-#define LoopSetup_c_mask 0x1
-#define LoopSetup_rop_bits 21
-#define LoopSetup_rop_mask 0x3
-#define LoopSetup_code_bits 23
-#define LoopSetup_code_mask 0x1ff
-
-static void decode_LoopSetup_0(unsigned int opcode)
-{
- int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
- int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
- int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
-
- pr_cont("LSETUP <> LC%i", c);
- if ((rop & 1) == 1)
- pr_cont("= P%i", reg);
- if ((rop & 2) == 2)
- pr_cont(" >> 0x1");
-}
-
-#define DspLDST_opcode 0x9c00
-#define DspLDST_reg_bits 0
-#define DspLDST_reg_mask 0x7
-#define DspLDST_i_bits 3
-#define DspLDST_i_mask 0x3
-#define DspLDST_m_bits 5
-#define DspLDST_m_mask 0x3
-#define DspLDST_aop_bits 7
-#define DspLDST_aop_mask 0x3
-#define DspLDST_W_bits 9
-#define DspLDST_W_mask 0x1
-#define DspLDST_code_bits 10
-#define DspLDST_code_mask 0x3f
-
-static void decode_dspLDST_0(unsigned int opcode)
-{
- int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
- int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
- int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
- int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
- int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
-
- if (W == 0) {
- pr_cont("R%i", reg);
- switch (m) {
- case 0:
- pr_cont(" = ");
- break;
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-
- pr_cont("[ I%i", i);
-
- switch (aop) {
- case 0:
- pr_cont("++ ]");
- break;
- case 1:
- pr_cont("-- ]");
- break;
- }
-
- if (W == 1) {
- pr_cont(" = R%i", reg);
- switch (m) {
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-}
-
-#define LDST_opcode 0x9000
-#define LDST_reg_bits 0
-#define LDST_reg_mask 0x7
-#define LDST_ptr_bits 3
-#define LDST_ptr_mask 0x7
-#define LDST_Z_bits 6
-#define LDST_Z_mask 0x1
-#define LDST_aop_bits 7
-#define LDST_aop_mask 0x3
-#define LDST_W_bits 9
-#define LDST_W_mask 0x1
-#define LDST_sz_bits 10
-#define LDST_sz_mask 0x3
-#define LDST_code_bits 12
-#define LDST_code_mask 0xf
-
-static void decode_LDST_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
- int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
- int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
- int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
- int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
- int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- switch (sz) {
- case 1:
- pr_cont("W");
- break;
- case 2:
- pr_cont("B");
- break;
- }
-
- pr_cont("[P%i", ptr);
-
- switch (aop) {
- case 0:
- pr_cont("++");
- break;
- case 1:
- pr_cont("--");
- break;
- }
- pr_cont("]");
-
- if (W == 1)
- pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- if (sz) {
- if (Z)
- pr_cont(" (X)");
- else
- pr_cont(" (Z)");
- }
-}
-
-#define LDSTii_opcode 0xa000
-#define LDSTii_reg_bit 0
-#define LDSTii_reg_mask 0x7
-#define LDSTii_ptr_bit 3
-#define LDSTii_ptr_mask 0x7
-#define LDSTii_offset_bit 6
-#define LDSTii_offset_mask 0xf
-#define LDSTii_op_bit 10
-#define LDSTii_op_mask 0x3
-#define LDSTii_W_bit 12
-#define LDSTii_W_mask 0x1
-#define LDSTii_code_bit 13
-#define LDSTii_code_mask 0x7
-
-static void decode_LDSTii_0(unsigned int opcode)
-{
- int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
- int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
- int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
- int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
- int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
-
- if (W == 0) {
- pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
- op == 1 || op == 2 ? "" : "W", ptr, offset);
- if (op == 2)
- pr_cont("(Z)");
- if (op == 3)
- pr_cont("(X)");
- } else {
- pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
- offset, op == 3 ? "P" : "R", reg);
- }
-}
-
-#define LDSTidxI_opcode 0xe4000000
-#define LDSTidxI_offset_bits 0
-#define LDSTidxI_offset_mask 0xffff
-#define LDSTidxI_reg_bits 16
-#define LDSTidxI_reg_mask 0x7
-#define LDSTidxI_ptr_bits 19
-#define LDSTidxI_ptr_mask 0x7
-#define LDSTidxI_sz_bits 22
-#define LDSTidxI_sz_mask 0x3
-#define LDSTidxI_Z_bits 24
-#define LDSTidxI_Z_mask 0x1
-#define LDSTidxI_W_bits 25
-#define LDSTidxI_W_mask 0x1
-#define LDSTidxI_code_bits 26
-#define LDSTidxI_code_mask 0x3f
-
-static void decode_LDSTidxI_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
- int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
- int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
- int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
- int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
- int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
-
- if (sz == 1)
- pr_cont("W");
- if (sz == 2)
- pr_cont("B");
-
- pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
- (offset & 0x1f) << 2);
-
- if (W == 0 && sz != 0) {
- if (Z)
- pr_cont("(X)");
- else
- pr_cont("(Z)");
- }
-
- if (W == 1)
- pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
-}
-
-static void decode_opcode(unsigned int opcode)
-{
-#ifdef CONFIG_BUG
- if (opcode == BFIN_BUG_OPCODE)
- pr_cont("BUG");
- else
-#endif
- if ((opcode & 0xffffff00) == ProgCtrl_opcode)
- decode_ProgCtrl_0(opcode);
- else if ((opcode & 0xfffff000) == BRCC_opcode)
- decode_BRCC_0(opcode);
- else if ((opcode & 0xfffff000) == 0x2000)
- pr_cont("JUMP.S");
- else if ((opcode & 0xfe000000) == CALLa_opcode)
- decode_CALLa_0(opcode);
- else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
- decode_LoopSetup_0(opcode);
- else if ((opcode & 0xfffffc00) == DspLDST_opcode)
- decode_dspLDST_0(opcode);
- else if ((opcode & 0xfffff000) == LDST_opcode)
- decode_LDST_0(opcode);
- else if ((opcode & 0xffffe000) == LDSTii_opcode)
- decode_LDSTii_0(opcode);
- else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
- decode_LDSTidxI_0(opcode);
- else if (opcode & 0xffff0000)
- pr_cont("0x%08x", opcode);
- else
- pr_cont("0x%04x", opcode);
-}
-
-#define BIT_MULTI_INS 0x08000000
-static void decode_instruction(unsigned short *address)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, address))
- return;
-
- decode_opcode(opcode);
-
- /* If things are a 32-bit instruction, it has the possibility of being
- * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
- * This test collidates with the unlink instruction, so disallow that
- */
- if ((opcode & 0xc0000000) == 0xc0000000 &&
- (opcode & BIT_MULTI_INS) &&
- (opcode & 0xe8000000) != 0xe8000000) {
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 2))
- return;
- decode_opcode(opcode);
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 3))
- return;
- decode_opcode(opcode);
- }
-}
-#endif
-
-void dump_bfin_trace_buffer(void)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags, i = 0, fault = 0;
- char buf[150];
- unsigned short *addr;
- unsigned int cpu = raw_smp_processor_id();
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- int j, index;
-#endif
-
- trace_buffer_save(tflags);
-
- pr_notice("Hardware Trace:\n");
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
-#endif
-
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice("%4i Target : %s\n", i, buf);
- /* Normally, the faulting instruction doesn't go into
- * the trace buffer, (since it doesn't commit), so
- * we print out the fault address here
- */
- if (!fault && addr == ((unsigned short *)evt_ivhw)) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- fault = 1;
- continue;
- }
- if (!fault && addr == (unsigned short *)trap &&
- (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
- pr_cont("\n");
- fault = 1;
- }
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" Source : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- }
- }
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- if (trace_buff_offset)
- index = trace_buff_offset / 4;
- else
- index = EXPAND_LEN;
-
- j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
- while (j) {
- decode_address(buf, software_trace_buff[index]);
- pr_notice("%4i Target : %s\n", i, buf);
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- decode_address(buf, software_trace_buff[index]);
- pr_notice(" Source : %s ", buf);
- decode_instruction((unsigned short *)software_trace_buff[index]);
- pr_cont("\n");
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- j--;
- i++;
- }
-#endif
-
- trace_buffer_restore(tflags);
-#endif
-}
-EXPORT_SYMBOL(dump_bfin_trace_buffer);
-
-void dump_bfin_process(struct pt_regs *fp)
-{
- /* We should be able to look at fp->ipend, but we don't push it on the
- * stack all the time, so do this until we fix that */
- unsigned int context = bfin_read_IPEND();
-
- if (oops_in_progress)
- pr_emerg("Kernel OOPS in progress\n");
-
- if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
- pr_notice("HW Error context\n");
- else if (context & 0x0020)
- pr_notice("Deferred Exception context\n");
- else if (context & 0x3FC0)
- pr_notice("Interrupt context\n");
- else if (context & 0x4000)
- pr_notice("Deferred Interrupt context\n");
- else if (context & 0x8000)
- pr_notice("Kernel process context\n");
-
- /* Because we are crashing, and pointers could be bad, we check things
- * pretty closely before we use them
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3) && current->pid) {
- pr_notice("CURRENT PROCESS:\n");
- if (current->comm >= (char *)FIXED_CODE_START)
- pr_notice("COMM=%s PID=%d",
- current->comm, current->pid);
- else
- pr_notice("COMM= invalid");
-
- pr_cont(" CPU=%d\n", current_thread_info()->cpu);
- if (!((unsigned long)current->mm & 0x3) &&
- (unsigned long)current->mm >= FIXED_CODE_START) {
- pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
- (void *)current->mm->start_code,
- (void *)current->mm->end_code,
- (void *)current->mm->start_data,
- (void *)current->mm->end_data);
- pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
- (void *)current->mm->end_data,
- (void *)current->mm->brk,
- (void *)current->mm->start_stack);
- } else
- pr_notice("invalid mm\n");
- } else
- pr_notice("No Valid process in current context\n");
-}
-
-void dump_bfin_mem(struct pt_regs *fp)
-{
- unsigned short *addr, *erraddr, val = 0, err = 0;
- char sti = 0, buf[6];
-
- erraddr = (void *)fp->pc;
-
- pr_notice("return address: [0x%p]; contents of:", erraddr);
-
- for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
- addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
- addr++) {
- if (!((unsigned long)addr & 0xF))
- pr_notice("0x%p: ", addr);
-
- if (!get_mem16(&val, addr)) {
- val = 0;
- sprintf(buf, "????");
- } else
- sprintf(buf, "%04x", val);
-
- if (addr == erraddr) {
- pr_cont("[%s]", buf);
- err = val;
- } else
- pr_cont(" %s ", buf);
-
- /* Do any previous instructions turn on interrupts? */
- if (addr <= erraddr && /* in the past */
- ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
- val == 0x017b)) /* [SP++] = RETI */
- sti = 1;
- }
-
- pr_cont("\n");
-
- /* Hardware error interrupts can be deferred */
- if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
- oops_in_progress)){
- pr_notice("Looks like this was a deferred error - sorry\n");
-#ifndef CONFIG_DEBUG_HWERR
- pr_notice("The remaining message may be meaningless\n");
- pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
-#else
- /* If we are handling only one peripheral interrupt
- * and current mm and pid are valid, and the last error
- * was in that user space process's text area
- * print it out - because that is where the problem exists
- */
- if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
- (current->pid && current->mm)) {
- /* And the last RETI points to the current userspace context */
- if ((fp + 1)->pc >= current->mm->start_code &&
- (fp + 1)->pc <= current->mm->end_code) {
- pr_notice("It might be better to look around here :\n");
- pr_notice("-------------------------------------------\n");
- show_regs(fp + 1);
- pr_notice("-------------------------------------------\n");
- }
- }
-#endif
- }
-}
-
-void show_regs(struct pt_regs *fp)
-{
- char buf[150];
- struct irqaction *action;
- unsigned int i;
- unsigned long flags = 0;
- unsigned int cpu = raw_smp_processor_id();
- unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
-
- pr_notice("\n");
- show_regs_print_info(KERN_NOTICE);
-
- if (CPUID != bfin_cpuid())
- pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
- "but running on:0x%04x (Rev %d)\n",
- CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
-
- pr_notice("ADSP-%s-0.%d",
- CPU, bfin_compiled_revid());
-
- if (bfin_compiled_revid() != bfin_revid())
- pr_cont("(Detected 0.%d)", bfin_revid());
-
- pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
- get_cclk()/1000000, get_sclk()/1000000,
-#ifdef CONFIG_MPU
- "mpu on"
-#else
- "mpu off"
-#endif
- );
-
- pr_notice("%s", linux_banner);
-
- pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
- pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
- (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
- if (fp->ipend & EVT_IRPTEN)
- pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
- EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
- pr_notice(" Peripheral interrupts masked off\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
- pr_notice(" Kernel interrupts masked off\n");
- if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
- pr_notice(" HWERRCAUSE: 0x%lx\n",
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
-#ifdef EBIU_ERRMST
- /* If the error was from the EBIU, print it out */
- if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
- pr_notice(" EBIU Error Reason : 0x%04x\n",
- bfin_read_EBIU_ERRMST());
- pr_notice(" EBIU Error Address : 0x%08x\n",
- bfin_read_EBIU_ERRADD());
- }
-#endif
- }
- pr_notice(" EXCAUSE : 0x%lx\n",
- fp->seqstat & SEQSTAT_EXCAUSE);
- for (i = 2; i <= 15 ; i++) {
- if (fp->ipend & (1 << i)) {
- if (i != 4) {
- decode_address(buf, bfin_read32(EVT0 + 4*i));
- pr_notice(" physical IVG%i asserted : %s\n", i, buf);
- } else
- pr_notice(" interrupts disabled\n");
- }
- }
-
- /* if no interrupts are going off, don't print this out */
- if (fp->ipend & ~0x3F) {
- for (i = 0; i < (NR_IRQS - 1); i++) {
- struct irq_desc *desc = irq_to_desc(i);
- if (!in_atomic)
- raw_spin_lock_irqsave(&desc->lock, flags);
-
- action = desc->action;
- if (!action)
- goto unlock;
-
- decode_address(buf, (unsigned int)action->handler);
- pr_notice(" logical irq %3d mapped : %s", i, buf);
- for (action = action->next; action; action = action->next) {
- decode_address(buf, (unsigned int)action->handler);
- pr_cont(", %s", buf);
- }
- pr_cont("\n");
-unlock:
- if (!in_atomic)
- raw_spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-
- decode_address(buf, fp->rete);
- pr_notice(" RETE: %s\n", buf);
- decode_address(buf, fp->retn);
- pr_notice(" RETN: %s\n", buf);
- decode_address(buf, fp->retx);
- pr_notice(" RETX: %s\n", buf);
- decode_address(buf, fp->rets);
- pr_notice(" RETS: %s\n", buf);
- decode_address(buf, fp->pc);
- pr_notice(" PC : %s\n", buf);
-
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
- (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
- decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
- pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
- }
-
- pr_notice("PROCESSOR STATE:\n");
- pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
- fp->p4, fp->p5, fp->fp, (long)fp);
- pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
- pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- pr_notice("USP : %08lx ASTAT: %08lx\n",
- rdusp(), fp->astat);
-
- pr_notice("\n");
-}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
deleted file mode 100644
index a323a40a46e9..000000000000
--- a/arch/blackfin/kernel/traps.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Main exception handling logic.
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/bug.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <linux/irq.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/pseudo_instructions.h>
-#include <asm/pda.h>
-#include <asm/asm-offsets.h>
-
-#ifdef CONFIG_KGDB
-# include <linux/kgdb.h>
-
-# define CHK_DEBUGGER_TRAP() \
- do { \
- kgdb_handle_exception(trapnr, sig, info.si_code, fp); \
- } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() \
- do { \
- if (kgdb_connected) \
- CHK_DEBUGGER_TRAP(); \
- } while (0)
-#else
-# define CHK_DEBUGGER_TRAP() do { } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
-#endif
-
-
-#ifdef CONFIG_DEBUG_VERBOSE
-#define verbose_printk(fmt, arg...) \
- printk(fmt, ##arg)
-#else
-#define verbose_printk(fmt, arg...) \
- ({ if (0) printk(fmt, ##arg); 0; })
-#endif
-
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
-u32 last_seqstat;
-#ifdef CONFIG_DEBUG_MMRS_MODULE
-EXPORT_SYMBOL(last_seqstat);
-#endif
-#endif
-
-/* Initiate the event table handler */
-void __init trap_init(void)
-{
- CSYNC();
- bfin_write_EVT3(trap);
- CSYNC();
-}
-
-static int kernel_mode_regs(struct pt_regs *regs)
-{
- return regs->ipend & 0xffc0;
-}
-
-asmlinkage notrace void trap_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- int opcode;
-#endif
- unsigned int cpu = raw_smp_processor_id();
- const char *strerror = NULL;
- int sig = 0;
- siginfo_t info;
- unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
-
- trace_buffer_save(j);
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
- last_seqstat = (u32)fp->seqstat;
-#endif
-
- /* Important - be very careful dereferncing pointers - will lead to
- * double faults if the stack has become corrupt
- */
-
- /* trap_c() will be called for exceptions. During exceptions
- * processing, the pc value should be set with retx value.
- * With this change we can cleanup some code in signal.c- TODO
- */
- fp->orig_pc = fp->retx;
- /* printk("exception: 0x%x, ipend=%x, reti=%x, retx=%x\n",
- trapnr, fp->ipend, fp->pc, fp->retx); */
-
- /* send the appropriate signal to the user program */
- switch (trapnr) {
-
- /* This table works in conjunction with the one in ./mach-common/entry.S
- * Some exceptions are handled there (in assembly, in exception space)
- * Some are handled here, (in C, in interrupt space)
- * Some, like CPLB, are handled in both, where the normal path is
- * handled in assembly/exception space, and the error path is handled
- * here
- */
-
- /* 0x00 - Linux Syscall, getting here is an error */
- /* 0x01 - userspace gdb breakpoint, handled here */
- case VEC_EXCPT01:
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a breakpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x03 - User Defined, userspace stack overflow */
- case VEC_EXCPT03:
- info.si_code = SEGV_STACKFLOW;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x02 - KGDB initial connection and break signal trap */
- case VEC_EXCPT02:
-#ifdef CONFIG_KGDB
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP();
- goto traps_done;
-#endif
- /* 0x04 - User Defined */
- /* 0x05 - User Defined */
- /* 0x06 - User Defined */
- /* 0x07 - User Defined */
- /* 0x08 - User Defined */
- /* 0x09 - User Defined */
- /* 0x0A - User Defined */
- /* 0x0B - User Defined */
- /* 0x0C - User Defined */
- /* 0x0D - User Defined */
- /* 0x0E - User Defined */
- /* 0x0F - User Defined */
- /* If we got here, it is most likely that someone was trying to use a
- * custom exception handler, and it is not actually installed properly
- */
- case VEC_EXCPT04 ... VEC_EXCPT15:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x10 HW Single step, handled here */
- case VEC_STEP:
- info.si_code = TRAP_STEP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a single step in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x11 - Trace Buffer Full, handled here */
- case VEC_OVFLOW:
- info.si_code = TRAP_TRACEFLOW;
- sig = SIGTRAP;
- strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x12 - Reserved, Caught by default */
- /* 0x13 - Reserved, Caught by default */
- /* 0x14 - Reserved, Caught by default */
- /* 0x15 - Reserved, Caught by default */
- /* 0x16 - Reserved, Caught by default */
- /* 0x17 - Reserved, Caught by default */
- /* 0x18 - Reserved, Caught by default */
- /* 0x19 - Reserved, Caught by default */
- /* 0x1A - Reserved, Caught by default */
- /* 0x1B - Reserved, Caught by default */
- /* 0x1C - Reserved, Caught by default */
- /* 0x1D - Reserved, Caught by default */
- /* 0x1E - Reserved, Caught by default */
- /* 0x1F - Reserved, Caught by default */
- /* 0x20 - Reserved, Caught by default */
- /* 0x21 - Undefined Instruction, handled here */
- case VEC_UNDEF_I:
-#ifdef CONFIG_BUG
- if (kernel_mode_regs(fp)) {
- switch (report_bug(fp->pc, fp)) {
- case BUG_TRAP_TYPE_NONE:
- break;
- case BUG_TRAP_TYPE_WARN:
- dump_bfin_trace_buffer();
- fp->pc += 2;
- goto traps_done;
- case BUG_TRAP_TYPE_BUG:
- /* call to panic() will dump trace, and it is
- * off at this point, so it won't be clobbered
- */
- panic("BUG()");
- }
- }
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- /*
- * Support for the fake instructions, if the instruction fails,
- * then just execute a illegal opcode failure (like normal).
- * Don't support these instructions inside the kernel
- */
- if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) {
- if (execute_pseudodbg_assert(fp, opcode))
- goto traps_done;
- if (execute_pseudodbg(fp, opcode))
- goto traps_done;
- }
-#endif
- info.si_code = ILL_ILLOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x22 - Illegal Instruction Combination, handled here */
- case VEC_ILGAL_I:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x23 - Data CPLB protection violation, handled here */
- case VEC_CPLB_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x24 - Data access misaligned, handled here */
- case VEC_MISALI_D:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x25 - Unrecoverable Event, handled here */
- case VEC_UNCOV:
- info.si_code = ILL_ILLEXCPT;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
- error case is handled here */
- case VEC_CPLB_M:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE);
- break;
- /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
- case VEC_CPLB_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "NULL pointer access\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x28 - Emulation Watchpoint, handled here */
- case VEC_WATCH:
- info.si_code = TRAP_WATCHPT;
- sig = SIGTRAP;
- pr_debug(EXC_0x28(KERN_DEBUG));
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a watchpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
-#ifdef CONFIG_BF535
- /* 0x29 - Instruction fetch access error (535 only) */
- case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */
- info.si_code = BUS_OPFETCH;
- sig = SIGBUS;
- strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n";
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
-#else
- /* 0x29 - Reserved, Caught by default */
-#endif
- /* 0x2A - Instruction fetch misaligned, handled here */
- case VEC_MISALI_I:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2B - Instruction CPLB protection violation, handled here */
- case VEC_CPLB_I_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
- case VEC_CPLB_I_M:
- info.si_code = ILL_CPLB_MISS;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE);
- break;
- /* 0x2D - Instruction CPLB Multiple Hits, handled here */
- case VEC_CPLB_I_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "Jump to NULL address\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2E - Illegal use of Supervisor Resource, handled here */
- case VEC_ILL_RES:
- info.si_code = ILL_PRVOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2F - Reserved, Caught by default */
- /* 0x30 - Reserved, Caught by default */
- /* 0x31 - Reserved, Caught by default */
- /* 0x32 - Reserved, Caught by default */
- /* 0x33 - Reserved, Caught by default */
- /* 0x34 - Reserved, Caught by default */
- /* 0x35 - Reserved, Caught by default */
- /* 0x36 - Reserved, Caught by default */
- /* 0x37 - Reserved, Caught by default */
- /* 0x38 - Reserved, Caught by default */
- /* 0x39 - Reserved, Caught by default */
- /* 0x3A - Reserved, Caught by default */
- /* 0x3B - Reserved, Caught by default */
- /* 0x3C - Reserved, Caught by default */
- /* 0x3D - Reserved, Caught by default */
- /* 0x3E - Reserved, Caught by default */
- /* 0x3F - Reserved, Caught by default */
- case VEC_HWERR:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- switch (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- /* System MMR Error */
- case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x2(KERN_NOTICE);
- break;
- /* External Memory Addressing Error */
- case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
- if (ANOMALY_05000310) {
- static unsigned long anomaly_rets;
-
- if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * A false hardware error will happen while fetching at
- * the L1 instruction SRAM boundary. Ignore it.
- */
- anomaly_rets = fp->rets;
- goto traps_done;
- } else if (fp->rets == anomaly_rets) {
- /*
- * While boundary code returns to a function, at the ret
- * point, a new false hardware error might occur too based
- * on tests. Ignore it too.
- */
- goto traps_done;
- } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * If boundary code calls a function, at the entry point,
- * a new false hardware error maybe happen based on tests.
- * Ignore it too.
- */
- goto traps_done;
- } else
- anomaly_rets = 0;
- }
-
- info.si_code = BUS_ADRERR;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
- break;
- /* Performance Monitor Overflow */
- case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
- strerror = KERN_NOTICE HWC_x12(KERN_NOTICE);
- break;
- /* RAISE 5 instruction */
- case (SEQSTAT_HWERRCAUSE_RAISE_5):
- printk(KERN_NOTICE HWC_x18(KERN_NOTICE));
- break;
- default: /* Reserved */
- printk(KERN_NOTICE HWC_default(KERN_NOTICE));
- break;
- }
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /*
- * We should be handling all known exception types above,
- * if we get here we hit a reserved one, so panic
- */
- default:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
- (fp->seqstat & SEQSTAT_EXCAUSE));
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- }
-
- BUG_ON(sig == 0);
-
- /* If the fault was caused by a kernel thread, or interrupt handler
- * we will kernel panic, so the system reboots.
- */
- if (kernel_mode_regs(fp) || (current && !current->mm)) {
- console_verbose();
- oops_in_progress = 1;
- }
-
- if (sig != SIGTRAP) {
- if (strerror)
- verbose_printk(strerror);
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
-
- /* Print out the trace buffer if it makes sense */
-#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
- if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M)
- verbose_printk(KERN_NOTICE "No trace since you do not have "
- "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n\n");
- else
-#endif
- dump_bfin_trace_buffer();
-
- if (oops_in_progress) {
- /* Dump the current kernel stack */
- verbose_printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
-#ifndef CONFIG_ACCESS_CHECK
- verbose_printk(KERN_EMERG "Please turn on "
- "CONFIG_ACCESS_CHECK\n");
-#endif
- panic("Kernel exception");
- } else {
-#ifdef CONFIG_DEBUG_VERBOSE
- unsigned long *stack;
- /* Dump the user space stack */
- stack = (unsigned long *)rdusp();
- verbose_printk(KERN_NOTICE "Userspace Stack\n");
- show_stack(NULL, stack);
-#endif
- }
- }
-
-#ifdef CONFIG_IPIPE
- if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp))
-#endif
- {
- info.si_signo = sig;
- info.si_errno = 0;
- switch (trapnr) {
- case VEC_CPLB_VL:
- case VEC_MISALI_D:
- case VEC_CPLB_M:
- case VEC_CPLB_MHIT:
- info.si_addr = (void __user *)cpu_pda[cpu].dcplb_fault_addr;
- break;
- default:
- info.si_addr = (void __user *)fp->pc;
- break;
- }
- force_sig_info(sig, &info, current);
- }
-
- if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) ||
- (ANOMALY_05000281 && trapnr == VEC_HWERR) ||
- (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL)))
- fp->pc = SAFE_USER_INSTRUCTION;
-
- traps_done:
- trace_buffer_restore(j);
-}
-
-asmlinkage void double_fault_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
- trace_buffer_save(j);
-#endif
-
- console_verbose();
- oops_in_progress = 1;
-#ifdef CONFIG_DEBUG_VERBOSE
- printk(KERN_EMERG "Double Fault\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
- unsigned int cpu = raw_smp_processor_id();
- char buf[150];
- decode_address(buf, cpu_pda[cpu].retx_doublefault);
- printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
- (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
- decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
-
- decode_address(buf, fp->retx);
- printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
- } else
-#endif
- {
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-#endif
- panic("Double Fault - unrecoverable event");
-
-}
-
-
-void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
-{
- switch (cplb_panic) {
- case CPLB_NO_UNLOCKED:
- printk(KERN_EMERG "All CPLBs are locked\n");
- break;
- case CPLB_PROT_VIOL:
- return;
- case CPLB_NO_ADDR_MATCH:
- return;
- case CPLB_UNKNOWN_ERR:
- printk(KERN_EMERG "Unknown CPLB Exception\n");
- break;
- }
-
- oops_in_progress = 1;
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_stack();
- panic("Unrecoverable event");
-}
-
-#ifdef CONFIG_BUG
-int is_valid_bugaddr(unsigned long addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, (unsigned short *)addr))
- return 0;
-
- return opcode == BFIN_BUG_OPCODE;
-}
-#endif
-
-/* stub this out */
-#ifndef CONFIG_DEBUG_VERBOSE
-void show_regs(struct pt_regs *fp)
-{
-
-}
-#endif
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
deleted file mode 100644
index 334ef8139b35..000000000000
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/mem_map.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-OUTPUT_FORMAT("elf32-bfin")
-ENTRY(__start)
-_jiffies = _jiffies_64;
-
-SECTIONS
-{
-#ifdef CONFIG_RAMKERNEL
- . = CONFIG_BOOT_LOAD;
-#else
- . = CONFIG_ROM_BASE;
-#endif
-
- /* Neither the text, ro_data or bss section need to be aligned
- * So pack them back to back
- */
- .text :
- {
- __text = .;
- _text = .;
- __stext = .;
- TEXT_TEXT
-#ifndef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- CPUIDLE_TEXT
- LOCK_TEXT
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- KPROBES_TEXT
-#ifdef CONFIG_ROMKERNEL
- __sinittext = .;
- INIT_TEXT
- __einittext = .;
- EXIT_TEXT
-#endif
- *(.text.*)
- *(.fixup)
-
-#if !L1_CODE_LENGTH
- *(.l1.text)
-#endif
- __etext = .;
- }
-
- EXCEPTION_TABLE(4)
- NOTES
-
- /* Just in case the first read only is a 32-bit access */
- RO_DATA(4)
- __rodata_end = .;
-
-#ifdef CONFIG_ROMKERNEL
- . = CONFIG_BOOT_LOAD;
- .bss : AT(__rodata_end)
-#else
- .bss :
-#endif
- {
- . = ALIGN(4);
- ___bss_start = .;
- *(.bss .bss.*)
- *(COMMON)
-#if !L1_DATA_A_LENGTH
- *(.l1.bss)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.bss.B)
-#endif
- . = ALIGN(4);
- ___bss_stop = .;
- }
-
-#if defined(CONFIG_ROMKERNEL)
- .data : AT(LOADADDR(.bss) + SIZEOF(.bss))
-#else
- .data :
-#endif
- {
- __sdata = .;
- /* This gets done first, so the glob doesn't suck it in */
- CACHELINE_ALIGNED_DATA(32)
-
-#if !L1_DATA_A_LENGTH
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
- *(.l1.data)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.data.B)
-#endif
-#if !L2_LENGTH
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
- *(.l2.data)
-#endif
-
- DATA_DATA
- CONSTRUCTORS
-
- INIT_TASK_DATA(THREAD_SIZE)
-
- __edata = .;
- }
- __data_lma = LOADADDR(.data);
- __data_len = SIZEOF(.data);
-
- BUG_TABLE
-
- /* The init section should be last, so when we free it, it goes into
- * the general memory pool, and (hopefully) will decrease fragmentation
- * a tiny bit. The init section has a _requirement_ that it be
- * PAGE_SIZE aligned
- */
- . = ALIGN(PAGE_SIZE);
- ___init_begin = .;
-
-#ifdef CONFIG_RAMKERNEL
- INIT_TEXT_SECTION(PAGE_SIZE)
-
- /* We have to discard exit text and such at runtime, not link time, to
- * handle embedded cross-section references (alt instructions, bug
- * table, eh_frame, etc...). We need all of our .text up front and
- * .data after it for PCREL call issues.
- */
- .exit.text :
- {
- EXIT_TEXT
- }
-
- . = ALIGN(16);
- INIT_DATA_SECTION(16)
- PERCPU_SECTION(32)
-
- .exit.data :
- {
- EXIT_DATA
- }
-
- .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
-#else
- .init.data : AT(__data_lma + __data_len + 32)
- {
- __sinitdata = .;
- INIT_DATA
- INIT_SETUP(16)
- INIT_CALLS
- CON_INITCALL
- SECURITY_INITCALL
- INIT_RAM_FS
-
- . = ALIGN(PAGE_SIZE);
- ___per_cpu_load = .;
- PERCPU_INPUT(32)
-
- EXIT_DATA
- __einitdata = .;
- }
- __init_data_lma = LOADADDR(.init.data);
- __init_data_len = SIZEOF(.init.data);
- __init_data_end = .;
-
- .text_l1 L1_CODE_START : AT(__init_data_lma + __init_data_len)
-#endif
- {
- . = ALIGN(4);
- __stext_l1 = .;
- *(.l1.text.head)
- *(.l1.text)
-#ifdef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- . = ALIGN(4);
- __etext_l1 = .;
- }
- __text_l1_lma = LOADADDR(.text_l1);
- __text_l1_len = SIZEOF(.text_l1);
- ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
-
- .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
- {
- . = ALIGN(4);
- __sdata_l1 = .;
- *(.l1.data)
- __edata_l1 = .;
-
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l1 = .;
- *(.l1.bss)
- . = ALIGN(4);
- __ebss_l1 = .;
- }
- __data_l1_lma = LOADADDR(.data_l1);
- __data_l1_len = SIZEOF(.data_l1);
- ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
-
- .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
- {
- . = ALIGN(4);
- __sdata_b_l1 = .;
- *(.l1.data.B)
- __edata_b_l1 = .;
-
- . = ALIGN(4);
- __sbss_b_l1 = .;
- *(.l1.bss.B)
- . = ALIGN(4);
- __ebss_b_l1 = .;
- }
- __data_b_l1_lma = LOADADDR(.data_b_l1);
- __data_b_l1_len = SIZEOF(.data_b_l1);
- ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
-
- .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
- {
- . = ALIGN(4);
- __stext_l2 = .;
- *(.l2.text)
- . = ALIGN(4);
- __etext_l2 = .;
-
- . = ALIGN(4);
- __sdata_l2 = .;
- *(.l2.data)
- __edata_l2 = .;
-
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l2 = .;
- *(.l2.bss)
- . = ALIGN(4);
- __ebss_l2 = .;
- }
- __l2_lma = LOADADDR(.text_data_l2);
- __l2_len = SIZEOF(.text_data_l2);
- ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
-
- /* Force trailing alignment of our init section so that when we
- * free our init memory, we don't leave behind a partial page.
- */
-#ifdef CONFIG_RAMKERNEL
- . = __l2_lma + __l2_len;
-#else
- . = __init_data_end;
-#endif
- . = ALIGN(PAGE_SIZE);
- ___init_end = .;
-
- __end =.;
-
- STABS_DEBUG
-
- DWARF_DEBUG
-
- DISCARDS
-}
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
deleted file mode 100644
index 74ddde0eb2e7..000000000000
--- a/arch/blackfin/lib/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/lib/Makefile
-#
-
-lib-y := \
- ashldi3.o ashrdi3.o lshrdi3.o \
- muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
- memcpy.o memset.o memcmp.o memchr.o memmove.o \
- strcmp.o strcpy.o strncmp.o strncpy.o \
- umulsi3_highpart.o smulsi3_highpart.o \
- ins.o outs.o
diff --git a/arch/blackfin/lib/ashldi3.c b/arch/blackfin/lib/ashldi3.c
deleted file mode 100644
index ab69d8768afc..000000000000
--- a/arch/blackfin/lib/ashldi3.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashldi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.low = 0;
- w.s.high = (USItype) uu.s.low << -bm;
- } else {
- USItype carries = (USItype) uu.s.low >> bm;
- w.s.low = (USItype) uu.s.low << b;
- w.s.high = ((USItype) uu.s.high << b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c
deleted file mode 100644
index b5b351e82e10..000000000000
--- a/arch/blackfin/lib/ashrdi3.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- /* w.s.high = 1..1 or 0..0 */
- w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
- w.s.low = uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
deleted file mode 100644
index ef2cd99efb89..000000000000
--- a/arch/blackfin/lib/divsi3.S
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- *
- * 16 / 32 bit signed division.
- * Special cases :
- * 1) If(numerator == 0)
- * return 0
- * 2) If(denominator ==0)
- * return positive max = 0x7fffffff
- * 3) If(numerator == denominator)
- * return 1
- * 4) If(denominator ==1)
- * return numerator
- * 5) If(denominator == -1)
- * return -numerator
- *
- * Operand : R0 - Numerator (i)
- * R1 - Denominator (i)
- * R0 - Quotient (o)
- * Registers Used : R2-R7,P0-P2
- *
- */
-
-.global ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2;
-___divsi3 :
-
-
- R3 = R0 ^ R1;
- R0 = ABS R0;
-
- CC = V;
-
- r3 = rot r3 by -1;
- r1 = abs r1; /* now both positive, r3.30 means "negate result",
- ** r3.31 means overflow, add one to result
- */
- cc = r0 < r1;
- if cc jump .Lret_zero;
- r2 = r1 >> 15;
- cc = r2;
- if cc jump .Lidents;
- r2 = r1 << 16;
- cc = r2 <= r0;
- if cc jump .Lidents;
-
- DIVS(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
-
- R0 = R0.L (Z);
- r1 = r3 >> 31; /* add overflow issue back in */
- r0 = r0 + r1;
- r1 = -r0;
- cc = bittst(r3, 30);
- if cc r0 = r1;
- RTS;
-
-/* Can't use the primitives. Test common identities.
-** If the identity is true, return the value in R2.
-*/
-
-.Lidents:
- CC = R1 == 0; /* check for divide by zero */
- IF CC JUMP .Lident_return;
-
- CC = R0 == 0; /* check for division of zero */
- IF CC JUMP .Lzero_return;
-
- CC = R0 == R1; /* check for identical operands */
- IF CC JUMP .Lident_return;
-
- CC = R1 == 1; /* check for divide by 1 */
- IF CC JUMP .Lident_return;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- /* Identities haven't helped either.
- ** Perform the full division process.
- */
-
- P1 = 31; /* Set loop counter */
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
- R2 = -R1;
- [--SP] = R2;
- R2 = R0 << 1; /* R2 lsw of dividend */
- R6 = R0 ^ R1; /* Get sign */
- R5 = R6 >> 31; /* Shift sign to LSB */
-
- R0 = 0 ; /* Clear msw partial remainder */
- R2 = R2 | R5; /* Shift quotient bit */
- R6 = R0 ^ R1; /* Get new quotient bit */
-
- LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */
-.Llst: R7 = R2 >> 31; /* record copy of carry from R2 */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R0 = R0 << 1 || R5 = [SP];
- R0 = R0 | R7; /* and add carry */
- CC = R6 < 0; /* Check quotient(AQ) */
- /* we might be subtracting divisor (AQ==0) */
- IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
- R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
- R6 = R0 ^ R1; /* Generate next quotient bit */
- R5 = R6 >> 31;
- /* Assume AQ==1, shift in zero */
- BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
-.Llend: R2 = R2 + R5; /* and then set shifted-in value to
- ** tweaked AQ.
- */
- r1 = r3 >> 31;
- r2 = r2 + r1;
- cc = bittst(r3,30);
- r0 = -r2;
- if !cc r0 = r2;
- SP += 4;
- (R7:5)= [SP++]; /* Pop registers R6-R7 */
- RTS;
-
-.Lident_return:
- CC = R1 == 0; /* check for divide by zero => 0x7fffffff */
- R2 = -1 (X);
- R2 >>= 1;
- IF CC JUMP .Ltrue_ident_return;
-
- CC = R0 == R1; /* check for identical operands => 1 */
- R2 = 1 (Z);
- IF CC JUMP .Ltrue_ident_return;
-
- R2 = R0; /* assume divide by 1 => numerator */
- /*FALLTHRU*/
-
-.Ltrue_ident_return:
- R0 = R2; /* Return an identity value */
- R2 = -R2;
- CC = bittst(R3,30);
- IF CC R0 = R2;
-.Lzero_return:
- RTS; /* ...including zero */
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_ident_return;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- r1 = r3 >> 31;
- r0 = r0 + r1;
- R2 = -R0; // negate result if necessary
- CC = bittst(R3,30);
- IF CC R0 = R2;
- RTS;
-
-.Lret_zero:
- R0 = 0;
- RTS;
-
-.size ___divsi3, .-___divsi3
diff --git a/arch/blackfin/lib/gcclib.h b/arch/blackfin/lib/gcclib.h
deleted file mode 100644
index 724f07f14f8d..000000000000
--- a/arch/blackfin/lib/gcclib.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BITS_PER_UNIT 8
-#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
-
-typedef unsigned int UQItype __attribute__ ((mode(QI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-typedef unsigned int UDItype __attribute__ ((mode(DI)));
-
-struct DIstruct {
- SItype low, high;
-};
-
-typedef union {
- struct DIstruct s;
- DItype ll;
-} DIunion;
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
deleted file mode 100644
index d59608deccc1..000000000000
--- a/arch/blackfin/lib/ins.S
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.align 2
-
-#ifdef CONFIG_IPIPE
-# define DO_CLI \
- [--sp] = rets; \
- [--sp] = (P5:0); \
- sp += -12; \
- call ___ipipe_disable_root_irqs_hw; \
- sp += 12; \
- (P5:0) = [sp++];
-# define CLI_INNER_NOP
-#else
-# define DO_CLI cli R3;
-# define CLI_INNER_NOP nop; nop; nop;
-#endif
-
-#ifdef CONFIG_IPIPE
-# define DO_STI \
- sp += -12; \
- call ___ipipe_enable_root_irqs_hw; \
- sp += 12; \
-2: rets = [sp++];
-#else
-# define DO_STI 2: sti R3;
-#endif
-
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-# define CLI_OUTER DO_CLI;
-# define STI_OUTER DO_STI;
-# define CLI_INNER 1:
-# if ANOMALY_05000416
-# define STI_INNER nop; 2: nop;
-# else
-# define STI_INNER 2:
-# endif
-#else
-# define CLI_OUTER
-# define STI_OUTER
-# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
-# define STI_INNER DO_STI;
-#endif
-
-/*
- * Reads on the Blackfin are speculative. In Blackfin terms, this means they
- * can be interrupted at any time (even after they have been issued on to the
- * external bus), and re-issued after the interrupt occurs.
- *
- * If a FIFO is sitting on the end of the read, it will see two reads,
- * when the core only sees one. The FIFO receives the read which is cancelled,
- * and not delivered to the core.
- *
- * To solve this, interrupts are turned off before reads occur to I/O space.
- * There are 3 versions of all these functions
- * - turns interrupts off every read (higher overhead, but lower latency)
- * - turns interrupts off every loop (low overhead, but longer latency)
- * - DMA version, which do not suffer from this issue. DMA versions have
- * different name (prefixed by dma_ ), and are located in
- * ../kernel/bfin_dma.c
- * Using the dma related functions are recommended for transferring large
- * buffers in/out of FIFOs.
- */
-
-#define COMMON_INS(func, ops) \
-ENTRY(_ins##func) \
- P0 = R0; /* P0 = port */ \
- CLI_OUTER; /* 3 instructions before first read access */ \
- P1 = R1; /* P1 = address */ \
- P2 = R2; /* P2 = count */ \
- SSYNC; \
- \
- LSETUP(1f, 2f) LC0 = P2; \
- CLI_INNER; \
- ops; \
- STI_INNER; \
- \
- STI_OUTER; \
- RTS; \
-ENDPROC(_ins##func)
-
-COMMON_INS(l, \
- R0 = [P0]; \
- [P1++] = R0; \
-)
-
-COMMON_INS(w, \
- R0 = W[P0]; \
- W[P1++] = R0; \
-)
-
-COMMON_INS(w_8, \
- R0 = W[P0]; \
- B[P1++] = R0; \
- R0 = R0 >> 8; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(b, \
- R0 = B[P0]; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(l_16, \
- R0 = [P0]; \
- W[P1++] = R0; \
- R0 = R0 >> 16; \
- W[P1++] = R0; \
-)
diff --git a/arch/blackfin/lib/lshrdi3.c b/arch/blackfin/lib/lshrdi3.c
deleted file mode 100644
index 53f1741047e5..000000000000
--- a/arch/blackfin/lib/lshrdi3.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __lshrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.high = 0;
- w.s.low = (USItype) uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = (USItype) uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S
deleted file mode 100644
index bcfc8a14c3f2..000000000000
--- a/arch/blackfin/lib/memchr.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memchr(const void *s, int c, size_t n);
- * R0 = address (s)
- * R1 = sought byte (c)
- * R2 = count (n)
- *
- * Returns pointer to located character.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memchr)
- P0 = R0; /* P0 = address */
- P2 = R2; /* P2 = count */
- R1 = R1.B(Z);
- CC = R2 == 0;
- IF CC JUMP .Lfailed;
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-
-.Lbyte_loop_s:
- R3 = B[P0++](Z);
- CC = R3 == R1;
- IF CC JUMP .Lfound;
-.Lbyte_loop_e:
- NOP;
-
-.Lfailed:
- R0=0;
- RTS;
-
-.Lfound:
- R0 = P0;
- R0 += -1;
- RTS;
-
-ENDPROC(_memchr)
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
deleted file mode 100644
index 2e1c9477f2f7..000000000000
--- a/arch/blackfin/lib/memcmp.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* int memcmp(const void *s1, const void *s2, size_t n);
- * R0 = First Address (s1)
- * R1 = Second Address (s2)
- * R2 = count (n)
- *
- * Favours word aligned data.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memcmp)
- I1 = P3;
- P0 = R0; /* P0 = s1 address */
- P3 = R1; /* P3 = s2 Address */
- P2 = R2 ; /* P2 = count */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- I0 = R1; /* s2 */
- R1 = R1 | R0; /* OR addresses together */
- R1 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero. */
- IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
-
- P1 = P2 >> 2; /* count = n/4 */
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
-
- LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
-.Lquad_loop_s:
-#if ANOMALY_05000202
- R0 = [P0++];
- R1 = [I0++];
-#else
- MNOP || R0 = [P0++] || R1 = [I0++];
-#endif
- CC = R0 == R1;
- IF !CC JUMP .Lquad_different;
-.Lquad_loop_e:
- NOP;
-
- P3 = I0; /* s2 */
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely*/
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-.Lbyte_loop_s:
- R1 = B[P3++](Z); /* *s2 */
- R0 = B[P0++](Z); /* *s1 */
- CC = R0 == R1;
- IF !CC JUMP .Ldifferent;
-.Lbyte_loop_e:
- NOP;
-
-.Ldifferent:
- R0 = R0 - R1;
- P3 = I1;
- RTS;
-
-.Lquad_different:
- /* We've read two quads which don't match.
- * Can't just compare them, because we're
- * a little-endian machine, so the MSBs of
- * the regs occur at later addresses in the
- * string.
- * Arrange to re-read those two quads again,
- * byte-by-byte.
- */
- P0 += -4; /* back up to the start of the */
- P3 = I0; /* quads, and increase the*/
- P2 += 4; /* remainder count*/
- P3 += -4;
- JUMP .Lbytes;
-
-.Lfinished:
- R0 = 0;
- P3 = I1;
- RTS;
-
-ENDPROC(_memcmp)
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
deleted file mode 100644
index 53cb3698ab33..000000000000
--- a/arch/blackfin/lib/memcpy.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * internal version of memcpy(), issued by the compiler to copy blocks of
- * data around. This is really memmove() - it has to be able to deal with
- * possible overlaps, because that ambiguity is when the compiler gives up
- * and calls a function. We have our own, internal version so that we get
- * something we trust, even if the user has redefined the normal symbol.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memcpy(void *dest, const void *src, size_t n);
- * R0 = To Address (dest) (leave unchanged to form result)
- * R1 = From Address (src)
- * R2 = count
- *
- * Note: Favours word alignment
- */
-
-#ifdef CONFIG_MEMCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_memcpy)
- CC = R2 <= 0; /* length not positive? */
- IF CC JUMP .L_P1L2147483647; /* Nothing to do */
-
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
- P2 = R2 ; /* length */
-
- /* check for overlapping data */
- CC = R1 < R0; /* src < dst */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 < R3; /* and dst < src+len */
- IF CC JUMP .Lhas_overlap;
-
-.Lno_overlap:
- /* Check for aligned data.*/
-
- R3 = R1 | R0;
- R1 = 0x3;
- R3 = R3 & R1;
- CC = R3; /* low bits set on either address? */
- IF CC JUMP .Lnot_aligned;
-
- /* Both addresses are word-aligned, so we can copy
- at least part of the data using word copies.*/
- P2 = P2 >> 2;
- CC = P2 <= 2;
- IF !CC JUMP .Lmore_than_seven;
- /* less than eight bytes... */
- P2 = R2;
- LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
-.Lthree_start:
- R3 = B[P1++] (X);
-.Lthree_end:
- B[P0++] = R3;
-
- RTS;
-
-.Lmore_than_seven:
- /* There's at least eight bytes to copy. */
- P2 += -1; /* because we unroll one iteration */
- LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
- I1 = P1;
- R3 = [I1++];
-#if ANOMALY_05000202
-.Lword_loops:
- [P0++] = R3;
-.Lword_loope:
- R3 = [I1++];
-#else
-.Lword_loops:
-.Lword_loope:
- MNOP || [P0++] = R3 || R3 = [I1++];
-#endif
- [P0++] = R3;
- /* Any remaining bytes to copy? */
- R3 = 0x3;
- R3 = R2 & R3;
- CC = R3 == 0;
- P1 = I1; /* in case there's something left, */
- IF !CC JUMP .Lbytes_left;
- RTS;
-.Lbytes_left: P2 = R3;
-.Lnot_aligned:
- /* From here, we're copying byte-by-byte. */
- LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
-.Lbyte_start:
- R1 = B[P1++] (X);
-.Lbyte_end:
- B[P0++] = R1;
-
-.L_P1L2147483647:
- RTS;
-
-.Lhas_overlap:
- /* Need to reverse the copying, because the
- * dst would clobber the src.
- * Don't bother to work out alignment for
- * the reverse case.
- */
- P0 = P0 + P2;
- P0 += -1;
- P1 = P1 + P2;
- P1 += -1;
- LSETUP(.Lover_start, .Lover_end) LC0=P2;
-.Lover_start:
- R1 = B[P1--] (X);
-.Lover_end:
- B[P0--] = R1;
-
- RTS;
-
-ENDPROC(_memcpy)
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
deleted file mode 100644
index e0b78208f1d6..000000000000
--- a/arch/blackfin/lib/memmove.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-/*
- * C Library function MEMMOVE
- * R0 = To Address (leave unchanged to form result)
- * R1 = From Address
- * R2 = count
- * Data may overlap
- */
-
-ENTRY(_memmove)
- I1 = P3;
- P0 = R0; /* P0 = To address */
- P3 = R1; /* P3 = From Address */
- P2 = R2; /* P2 = count */
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely */
-
- CC = R1 < R0 (IU); /* From < To */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 <= R3 (IU); /* (From+len) >= To */
- IF CC JUMP .Loverlap;
-.Lno_overlap:
- R3 = 11;
- CC = R2 <= R3;
- IF CC JUMP .Lbytes;
- R3 = R1 | R0; /* OR addresses together */
- R3 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero.*/
- IF !CC JUMP .Lbytes; /* Jump if addrs not aligned.*/
-
- I0 = P3;
- P1 = P2 >> 2; /* count = n/4 */
- P1 += -1;
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
- R1 = [I0++];
-
- LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
-#if ANOMALY_05000202
-.Lquad_loops:
- [P0++] = R1;
-.Lquad_loope:
- R1 = [I0++];
-#else
-.Lquad_loops:
-.Lquad_loope:
- MNOP || [P0++] = R1 || R1 = [I0++];
-#endif
- [P0++] = R1;
-
- CC = P2 == 0; /* any remaining bytes? */
- P3 = I0; /* Amend P3 to updated ptr. */
- IF !CC JUMP .Lbytes;
- P3 = I1;
- RTS;
-
-.Lbytes: LSETUP (.Lbyte2_s, .Lbyte2_e) LC0=P2;
-.Lbyte2_s: R1 = B[P3++](Z);
-.Lbyte2_e: B[P0++] = R1;
-
-.Lfinished: P3 = I1;
- RTS;
-
-.Loverlap:
- P2 += -1;
- P0 = P0 + P2;
- P3 = P3 + P2;
- R1 = B[P3--] (Z);
- CC = P2 == 0;
- IF CC JUMP .Lno_loop;
-#if ANOMALY_05000245
- NOP;
- NOP;
-#endif
- LSETUP (.Lol_s, .Lol_e) LC0 = P2;
-.Lol_s: B[P0--] = R1;
-.Lol_e: R1 = B[P3--] (Z);
-.Lno_loop: B[P0] = R1;
- P3 = I1;
- RTS;
-
-ENDPROC(_memmove)
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
deleted file mode 100644
index cdcf9148ea20..000000000000
--- a/arch/blackfin/lib/memset.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-#ifdef CONFIG_MEMSET_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- * C Library function MEMSET
- * R0 = address (leave unchanged to form result)
- * R1 = filler byte
- * R2 = count
- * Favours word aligned data.
- * The strncpy assumes that I0 and I1 are not used in this function
- */
-
-ENTRY(_memset)
- P0 = R0 ; /* P0 = address */
- P2 = R2 ; /* P2 = count */
- R3 = R0 + R2; /* end */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- R1 = R1.B (Z); /* R1 = fill char */
- R2 = 3;
- R2 = R0 & R2; /* addr bottom two bits */
- CC = R2 == 0; /* AZ set if zero. */
- IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
-
-.Laligned:
- P1 = P2 >> 2; /* count = n/4 */
- R2 = R1 << 8; /* create quad filler */
- R2.L = R2.L + R1.L(NS);
- R2.H = R2.L + R1.H(NS);
- P2 = R3;
-
- LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop:
- [P0++] = R2;
-
- CC = P0 == P2;
- IF !CC JUMP .Lbytes_left;
- RTS;
-
-.Lbytes_left:
- R2 = R3; /* end point */
- R3 = P0; /* current position */
- R2 = R2 - R3; /* bytes left */
- P2 = R2;
-
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count */
- IF CC JUMP .Lfinished; /* Unusual */
-
-.Lbytes:
- LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
-.Lbyte_loop:
- B[P0++] = R1;
-
-.Lfinished:
- RTS;
-
-.Lforce_align:
- CC = BITTST (R0, 0); /* odd byte */
- R0 = 4;
- R0 = R0 - R2;
- P1 = R0;
- R0 = P0; /* Recover return address */
- IF !CC JUMP .Lskip1;
- B[P0++] = R1;
-.Lskip1:
- CC = R2 <= 2; /* 2 bytes */
- P2 -= P1; /* reduce count */
- IF !CC JUMP .Laligned;
- B[P0++] = R1;
- B[P0++] = R1;
- JUMP .Laligned;
-
-ENDPROC(_memset)
diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S
deleted file mode 100644
index f7026ce1fa0e..000000000000
--- a/arch/blackfin/lib/modsi3.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This program computes 32 bit signed remainder. It calls div32 function
- * for quotient estimation.
- * Registers in: R0, R1 = Numerator/ Denominator
- * Registers out: R0 = Remainder
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.global ___modsi3;
-.type ___modsi3, STT_FUNC;
-.extern ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___modsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if numerator == 0 */
- CC=R1==0;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if numerator == denominator */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 1 */
- CC = R1 == -1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == -1 */
-
- /* Valid input. Use __divsi3() to compute the quotient, and then
- * derive the remainder from that. */
-
- [--SP] = (R7:6); /* Push R7 and R6 */
- [--SP] = RETS; /* and return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1; /* Save for later */
- SP += -12; /* Should always provide this space */
- CALL ___divsi3; /* Compute signed quotient using ___divsi3()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Get back return address */
- (R7:6) = [SP++]; /* Pop registers R7 and R4 */
- RTS; /* Store remainder */
-
-.LRETURN_ZERO:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___modsi3, .-___modsi3
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S
deleted file mode 100644
index abf9b2a515b2..000000000000
--- a/arch/blackfin/lib/muldi3.S
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___muldi3;
-.type ___muldi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- R1:R0 * R3:R2
- = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
-[X] = (R1.h * R3.h) * 2^96
-[X] + (R1.h * R3.l + R1.l * R3.h) * 2^80
-[X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
-[T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
-[T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
-[T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
-[T4] + (R0.l * R2.l)
-
- We can discard the first three lines marked "X" since we produce
- only a 64 bit result. So, we need ten 16-bit multiplies.
-
- Individual mul-acc results:
-[E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
-[E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
-[E3] = R0.l * R2.h + R2.l * R0.h
-[E4] = R0.l * R2.l
-
- We also need to add high parts from lower-level results to higher ones:
- E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4
-
- One interesting property is that all parts of the result that depend
- on the sign of the multiplication are discarded. Those would be the
- multiplications involving R1.h and R3.h, but only the top 16 bit of
- the 32 bit result depend on the sign, and since R1.h and R3.h only
- occur in E1, the top half of these results is cut off.
- So, we can just use FU mode for all of the 16-bit multiplies, and
- ignore questions of when to use mixed mode. */
-
-___muldi3:
- /* [SP] technically is part of the caller's frame, but we can
- use it as scratch space. */
- A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
- A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
- A0 += A1; /* E1 */
- R4 = A0.w;
- A0 = R0.l * R3.l (FU); /* E2 */
- A0 += R2.l * R1.l (FU); /* E2 */
-
- A1 = R2.L * R0.L (FU); /* E4 */
- R3 = A1.w;
- A1 = A1 >> 16; /* E3c */
- A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
- A1 += R0.L * R2.H (FU); /* E3c */
- R0 = A1.w;
- A1 = A1 >> 16; /* E2c */
- A0 += A1; /* E2c */
- R1 = A0.w;
-
- /* low(result) = low(E3c):low(E4) */
- R0 = PACK (R0.l, R3.l);
- /* high(result) = E2c + (E1 << 16) */
- R1.h = R1.h + R4.l (NS) || R4 = [SP];
- RTS;
-
-.size ___muldi3, .-___muldi3
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
deleted file mode 100644
index 06a5e674401f..000000000000
--- a/arch/blackfin/lib/outs.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * 2005 BuyWays BV
- * Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-ENTRY(_outsl)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
-1: RTS;
-ENDPROC(_outsl)
-
-ENTRY(_outsw)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw)
-
-ENTRY(_outsb)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
-1: RTS;
-ENDPROC(_outsb)
-
-ENTRY(_outsw_8)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
- R0 = B[P1++];
- R0 = R0 << 8;
- R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw_8)
diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S
deleted file mode 100644
index e50d6c4ac2a5..000000000000
--- a/arch/blackfin/lib/smulsi3_highpart.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___smulsi3_highpart;
-.type ___smulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___smulsi3_highpart:
- R2 = R1.L * R0.L (FU);
- R3 = R1.H * R0.L (IS,M);
- R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
-
- R1.L = R2.H + R1.L;
- cc = ac0;
- R2 = cc;
-
- R1.L = R1.L + R3.L;
- cc = ac0;
- R1 >>>= 16;
- R3 >>>= 16;
- R1 = R1 + R3;
- R1 = R1 + R2;
- R2 = cc;
- R1 = R1 + R2;
-
- R0 = R0 + R1;
- RTS;
-
-.size ___smulsi3_highpart, .-___smulsi3_highpart
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
deleted file mode 100644
index 9c8b9863713e..000000000000
--- a/arch/blackfin/lib/strcmp.S
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcmp(char *s1, const char *s2);
- * R0 = address (s1)
- * R1 = address (s2)
- *
- * Returns an integer less than, equal to, or greater than zero if s1
- * (or the first n bytes thereof) is found, respectively, to be less
- * than, to match, or be greater than s2.
- */
-
-#ifdef CONFIG_STRCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcmp)
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 2f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if cc jump 1b (bp); /* no, keep going */
- jump.s 3f; /* strings are equal */
-2:
- R0 = R0 - R1; /* *s1 - *s2 */
-3:
- RTS;
-
-ENDPROC(_strcmp)
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
deleted file mode 100644
index 9495aa77cc40..000000000000
--- a/arch/blackfin/lib/strcpy.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcpy(char *dest, const char *src);
- * R0 = address (dest)
- * R1 = address (src)
- *
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcpy)
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1;
- if cc jump 1b (bp);
- RTS;
-
-ENDPROC(_strcpy)
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
deleted file mode 100644
index 3bfaedce893e..000000000000
--- a/arch/blackfin/lib/strncmp.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strncpy(char *s1, const char *s2, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size (n)
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRNCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncmp)
- CC = R2 == 0;
- if CC JUMP 5f;
-
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 3f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if ! cc jump 4f; /* yes, all done */
- R2 += -1; /* no, adjust count */
- CC = R2 == 0;
- if ! cc jump 1b (bp); /* more to do, keep going */
-2:
- R0 = 0; /* strings are equal */
- jump.s 4f;
-3:
- R0 = R0 - R1; /* *s1 - *s2 */
-4:
- RTS;
-
-5:
- R0 = 0;
- RTS;
-
-ENDPROC(_strncmp)
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
deleted file mode 100644
index 92fd1823bbee..000000000000
--- a/arch/blackfin/lib/strncpy.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-#include <asm/context.S>
-
-/* void *strncpy(char *dest, const char *src, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size
- * Returns a pointer (R0) to the destination string dest
- * we do this by not changing R0
- */
-
-#ifdef CONFIG_STRNCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncpy)
- CC = R2 == 0;
- if CC JUMP 6f;
-
- P2 = R2 ; /* size */
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
- LSETUP (1f, 2f) LC0 = P2;
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1 == 0;
-2:
- if CC jump 3f;
-
- RTS;
-
- /* if src is shorter than n, we need to null pad bytes in dest
- * but, we can get here when the last byte is zero, and we don't
- * want to copy an extra byte at the end, so we need to check
- */
-3:
- R2 = LC0;
- CC = R2
- if ! CC jump 6f;
-
- /* if the required null padded portion is small, do it here, rather than
- * handling the overhead of memset (which is OK when things are big).
- */
- R3 = 0x20;
- CC = R2 < R3;
- IF CC jump 4f;
-
- R2 += -1;
-
- /* Set things up for memset
- * R0 = address
- * R1 = filler byte (this case it's zero, set above)
- * R2 = count (set above)
- */
-
- I1 = R0;
- R0 = RETS;
- I0 = R0;
- R0 = P0;
- pseudo_long_call _memset, p0;
- R0 = I0;
- RETS = R0;
- R0 = I1;
- RTS;
-
-4:
- LSETUP(5f, 5f) LC0;
-5:
- B [P0++] = R1;
-6:
- RTS;
-
-ENDPROC(_strncpy)
diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S
deleted file mode 100644
index 90bfa809b392..000000000000
--- a/arch/blackfin/lib/udivsi3.S
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-#define CARRY AC0
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-
-ENTRY(___udivsi3)
-
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- IF CC JUMP .Lreturn_ident;
-
- R2 = R1 << 16;
- CC = R2 <= R0 (IU);
- IF CC JUMP .Lidents;
-
- R2 = R0 >> 31; /* if X is a 31-bit number */
- R3 = R1 >> 15; /* and Y is a 15-bit number */
- R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
- CC = R2;
- IF CC JUMP .Ly_16bit;
-
-/* METHOD 1: FAST DIVQ
- We know we have a 31-bit dividend, and 15-bit divisor so we can use the
- simple divq approach (first setting AQ to 0 - implying unsigned division,
- then 16 DIVQ's).
-*/
-
- AQ = CC; /* Clear AQ (CC==0) */
-
-/* ISR States: When dividing two integers (32.0/16.0) using divide primitives,
- we need to shift the dividend one bit to the left.
- We have already checked that we have a 31-bit number so we are safe to do
- that.
-*/
- R0 <<= 1;
- DIVQ(R0, R1); // 1
- DIVQ(R0, R1); // 2
- DIVQ(R0, R1); // 3
- DIVQ(R0, R1); // 4
- DIVQ(R0, R1); // 5
- DIVQ(R0, R1); // 6
- DIVQ(R0, R1); // 7
- DIVQ(R0, R1); // 8
- DIVQ(R0, R1); // 9
- DIVQ(R0, R1); // 10
- DIVQ(R0, R1); // 11
- DIVQ(R0, R1); // 12
- DIVQ(R0, R1); // 13
- DIVQ(R0, R1); // 14
- DIVQ(R0, R1); // 15
- DIVQ(R0, R1); // 16
- R0 = R0.L (Z);
- RTS;
-
-.Ly_16bit:
- /* We know that the upper 17 bits of Y might have bits set,
- ** or that the sign bit of X might have a bit. If Y is a
- ** 16-bit number, but not bigger, then we can use the builtins
- ** with a post-divide correction.
- ** R3 currently holds Y>>15, which means R3's LSB is the
- ** bit we're interested in.
- */
-
- /* According to the ISR, to use the Divide primitives for
- ** unsigned integer divide, the useable range is 31 bits
- */
- CC = ! BITTST(R0, 31);
-
- /* IF condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 += -1; /* if so, Y is 0x00008nnn */
- CC &= AZ;
-
- /* If condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */
- R2 = R0 >> 16;
-
- R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */
- CC &= CARRY;
- IF CC JUMP .Lshift_and_correct;
-
- /* Fall through to the identities */
-
-/* METHOD 2: identities and manual calculation
- We are not able to use the divide primites, but may still catch some special
- cases.
-*/
-.Lidents:
- /* Test for common identities. Value to be returned is placed in R2. */
- CC = R0 == 0; /* 0/Y => 0 */
- IF CC JUMP .Lreturn_r0;
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Lreturn_ident;
- CC = R1 == 1; /* X/1 => X */
- IF CC JUMP .Lreturn_ident;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
-
- /* Idents don't match. Go for the full operation. */
-
-
- R6 = 2; /* assume we'll shift two */
- R3 = 1;
-
- P2 = R1;
- /* If either R0 or R1 have sign set, */
- /* divide them by two, and note it's */
- /* been done. */
- CC = R1 < 0;
- R2 = R1 >> 1;
- IF CC R1 = R2; /* Possibly-shifted R1 */
- IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
-
- P0 = 0;
- R3 = -R1;
- [--SP] = R3;
- R2 = R0 >> 1;
- R2 = R0 >> 1;
- CC = R0 < 0;
- IF CC P0 = R6; /* Number of values divided */
- IF !CC R2 = R0; /* Shifted R0 */
-
- /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
-
- /* r2 holds Copy dividend */
- R3 = 0; /* Clear partial remainder */
- R7 = 0; /* Initialise quotient bit */
-
- P1 = 32; /* Set loop counter */
- LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */
-.Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R3 = R3 << 1 || R5 = [SP];
- R3 = R3 | R6; /* Include any carry */
- CC = R7 < 0; /* Check quotient(AQ) */
- /* If AQ==0, we'll sub divisor */
- IF CC R5 = R1; /* and if AQ==1, we'll add it. */
- R3 = R3 + R5; /* Add/sub divisor to partial remainder */
- R7 = R3 ^ R1; /* Generate next quotient bit */
-
- R5 = R7 >> 31; /* Get AQ */
- BITTGL(R5, 0); /* Invert it, to get what we'll shift */
-.Lulend: R2 = R2 + R5; /* and "shift" it in. */
-
- CC = P0 == 0; /* Check how many inputs we shifted */
- IF CC JUMP .Lno_mult; /* if none... */
- R6 = R2 << 1;
- CC = P0 == 1;
- IF CC R2 = R6; /* if 1, Q = Q*2 */
- IF !CC R1 = P2; /* if 2, restore stored divisor */
-
- R3 = R2; /* Copy of R2 */
- R3 *= R1; /* Q * divisor */
- R5 = R0 - R3; /* Z = (dividend - Q * divisor) */
- CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
- R6 = CC; /* if yes, R6 = 1 */
- R2 = R2 + R6; /* if yes, add one to quotient(Q) */
-.Lno_mult:
- SP += 4;
- (R7:5) = [SP++]; /* Pop registers R5-R7 */
- R0 = R2; /* Store quotient */
- RTS;
-
-.Lreturn_ident:
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- R2 = 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -1 (X); /* X/0 => 0xFFFFFFFF */
- CC = R1 == 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -R2; /* R2 now 1 */
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Ltrue_return_ident;
- R2 = R0; /* X/1 => X */
- /*FALLTHRU*/
-
-.Ltrue_return_ident:
- R0 = R2;
-.Lreturn_r0:
- RTS;
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_return_ident;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- RTS;
-
-/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION
- Two scaling operations are required to use the divide primitives with a
- divisor > 0x7FFFF.
- Firstly (as in method 1) we need to shift the dividend 1 to the left for
- integer division.
- Secondly we need to shift both the divisor and dividend 1 to the right so
- both are in range for the primitives.
- The left/right shift of the dividend does nothing so we can skip it.
-*/
-.Lshift_and_correct:
- R2 = R0;
- // R3 is already R1 >> 1
- CC=!CC;
- AQ = CC; /* Clear AQ, got here with CC = 0 */
- DIVQ(R2, R3); // 1
- DIVQ(R2, R3); // 2
- DIVQ(R2, R3); // 3
- DIVQ(R2, R3); // 4
- DIVQ(R2, R3); // 5
- DIVQ(R2, R3); // 6
- DIVQ(R2, R3); // 7
- DIVQ(R2, R3); // 8
- DIVQ(R2, R3); // 9
- DIVQ(R2, R3); // 10
- DIVQ(R2, R3); // 11
- DIVQ(R2, R3); // 12
- DIVQ(R2, R3); // 13
- DIVQ(R2, R3); // 14
- DIVQ(R2, R3); // 15
- DIVQ(R2, R3); // 16
-
- /* According to the Instruction Set Reference:
- To divide by a divisor > 0x7FFF,
- 1. prescale and perform divide to obtain quotient (Q) (done above),
- 2. multiply quotient by unscaled divisor (result M)
- 3. subtract the product from the divident to get an error (E = X - M)
- 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q)
- */
- R3 = R2.L (Z); /* Q = X' / Y' */
- R2 = R3; /* Preserve Q */
- R2 *= R1; /* M = Q * Y */
- R2 = R0 - R2; /* E = X - M */
- R0 = R3; /* Copy Q into result reg */
-
-/* Correction: If result of the multiply is negative, we overflowed
- and need to correct the result by subtracting 1 from the result.*/
- R3 = 0xFFFF (Z);
- R2 = R2 >> 16; /* E >> 16 */
- CC = R2 == R3;
- R3 = 1 ;
- R1 = R0 - R3;
- IF CC R0 = R1;
- RTS;
-
-ENDPROC(___udivsi3)
diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S
deleted file mode 100644
index 3794c00d859d..000000000000
--- a/arch/blackfin/lib/umodsi3.S
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * libgcc1 routines for Blackfin 5xx
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.extern ___udivsi3;
-.type ___udivsi3, STT_FUNC;
-.globl ___umodsi3
-.type ___umodsi3, STT_FUNC;
-___umodsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if NR == 0 */
- CC= R1==0;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if NR == DR */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 1 */
- CC = R0<R1 (IU);
- IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */
-
- [--SP] = (R7:6); /* Push registers and */
- [--SP] = RETS; /* Return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1;
- SP += -12; /* Should always provide this space */
- CALL ___udivsi3; /* Compute unsigned quotient using ___udiv32()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Pop return address */
- ( R7:6) = [SP++]; /* And registers */
- RTS; /* Return remainder */
-.LRETURN_ZERO_VAL:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___umodsi3, .-___umodsi3
diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S
deleted file mode 100644
index 0dcace96e4e7..000000000000
--- a/arch/blackfin/lib/umulsi3_highpart.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___umulsi3_highpart;
-.type ___umulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___umulsi3_highpart:
- R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
- R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
- R0 >>= 16;
- /* Unsigned multiplication has the nice property that we can
- ignore carry on this first addition. */
- R0 = R0 + R3;
- R0 = R0 + R1;
- cc = ac0;
- R1 = cc;
- R1 = PACK(R1.l,R0.h);
- R0 = R1 + R2;
- RTS;
-
-.size ___umulsi3_highpart, .-___umulsi3_highpart
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
deleted file mode 100644
index 4731f6b27e47..000000000000
--- a/arch/blackfin/mach-bf518/Kconfig
+++ /dev/null
@@ -1,320 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF51x
- def_bool y
- depends on (BF512 || BF514 || BF516 || BF518)
-
-if (BF51x)
-
-source "arch/blackfin/mach-bf518/boards/Kconfig"
-
-menu "BF518 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "PWM Channel Pins"
- default BF518_PWM_ALL_PORTF
- help
- Select pins used for the PWM channels:
- PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_ALL_PORTF
- bool "PF1 - PF6"
- help
- PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
-
-config BF518_PWM_PORTF_PORTG
- bool "PF11 - PF14 / PG1 - PG2"
- help
- PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
- PG{1,2} <-> PWM_{CH,CL}
-
-endchoice
-
-choice
- prompt "PWM Sync Pin"
- default BF518_PWM_SYNC_PF7
- help
- Select the pin used for PWM_SYNC.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_SYNC_PF7
- bool "PF7"
-config BF518_PWM_SYNC_PF15
- bool "PF15"
-endchoice
-
-choice
- prompt "PWM Trip B Pin"
- default BF518_PWM_TRIPB_PG10
- help
- Select the pin used for PWM_TRIPB.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_TRIPB_PG10
- bool "PG10"
-config BF518_PWM_TRIPB_PG14
- bool "PG14"
-endchoice
-
-choice
- prompt "PPI / Timer Pins"
- default BF518_PPI_TMR_PG5
- help
- Select pins used for PPI/Timer:
- PPICLK PPIFS1 PPIFS2
- TMRCLK TMR0 TMR1
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PPI_TMR_PG5
- bool "PG5 - PG7"
- help
- PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-config BF518_PPI_TMR_PG12
- bool "PG12 - PG14"
- help
- PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF51x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_PTP_ERROR
- int "IRQ_PTP_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI0
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_RSI_INT0
- int "IRQ_RSI_INT0"
- default 7
-config IRQ_RSI_INT1
- int "IRQ_RSI_INT1"
- default 7
-config IRQ_PWM_TRIP
- int "IRQ_PWM_TRIP"
- default 10
-config IRQ_PWM_SYNC
- int "IRQ_PWM_SYNC"
- default 10
-config IRQ_PTP_STAT
- int "IRQ_PTP_STAT"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile
deleted file mode 100644
index 168a193f9f9a..000000000000
--- a/arch/blackfin/mach-bf518/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf518/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig
deleted file mode 100644
index f7b93b950ef4..000000000000
--- a/arch/blackfin/mach-bf518/boards/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN518F_EZBRD
- help
- Select your board!
-
-config BFIN518F_EZBRD
- bool "BF518F-EZBRD"
- help
- BF518-EZBRD board support.
-
-config BFIN518F_TCM
- bool "Bluetechnix TCM-BF518"
- help
- Bluetechnix TCM-BF518 board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile
deleted file mode 100644
index a9ef25c6b302..000000000000
--- a/arch/blackfin/mach-bf518/boards/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf518/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN518F_TCM) += tcm-bf518.o
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
deleted file mode 100644
index c51d1b810ac3..000000000000
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF518F-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = {
- P_MII0_ETxD0,
- P_MII0_ETxD1,
- P_MII0_ETxEN,
- P_MII0_ERxD0,
- P_MII0_ERxD1,
- P_MII0_TxCLK,
- P_MII0_PHYINT,
- P_MII0_CRS,
- P_MII0_MDC,
- P_MII0_MDIO,
- 0
-};
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
- .vlan1_mask = 1,
- .vlan2_mask = 2,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
- peripheral_request(P_AMS2, "ParaFlash");
-#if !IS_ENABLED(CONFIG_SPI_BFIN5XX)
- peripheral_request(P_AMS3, "ParaFlash");
-#endif
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
deleted file mode 100644
index 37d868085f6a..000000000000
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ /dev/null
@@ -1,739 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM-BF518";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition tcm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- },
- {
- .name = "linux(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tcm_flash_data = {
- .width = 2,
- .parts = tcm_partitions,
- .nr_parts = ARRAY_SIZE(tcm_partitions),
-};
-
-static struct resource tcm_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device tcm_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &tcm_flash_data,
- },
- .num_resources = 1,
- .resource = &tcm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tcm_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &tcm_flash_device,
-#endif
-};
-
-static int __init tcm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tcm_devices, ARRAY_SIZE(tcm_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tcm_init);
-
-static struct platform_device *tcm_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tcm_early_devices,
- ARRAY_SIZE(tcm_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
deleted file mode 100644
index bcd1fbc8c543..000000000000
--- a/arch/blackfin/mach-bf518/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
deleted file mode 100644
index 46cb88231d66..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
deleted file mode 100644
index 6906dee4f4cc..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/bf518.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF518_H__
-#define __MACH_BF518_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
-
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3C)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF518
-#define CPU "BF518"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF516
-#define CPU "BF516"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF514
-#define CPU "BF514"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF512
-#define CPU "BF512"
-#define CPUID 0x27e8
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF518_H__ */
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
deleted file mode 100644
index a8828863226e..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf518.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF512
-# include "defBF512.h"
-#endif
-#ifdef CONFIG_BF514
-# include "defBF514.h"
-#endif
-#ifdef CONFIG_BF516
-# include "defBF516.h"
-#endif
-#ifdef CONFIG_BF518
-# include "defBF518.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF512
-# include "cdefBF512.h"
-# endif
-# ifdef CONFIG_BF514
-# include "cdefBF514.h"
-# endif
-# ifdef CONFIG_BF516
-# include "cdefBF516.h"
-# endif
-# ifdef CONFIG_BF518
-# include "cdefBF518.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
deleted file mode 100644
index 1c03ad4bcb72..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF512_H
-#define _CDEF_BF512_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-#endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
deleted file mode 100644
index 861221d1dcc9..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF514_H
-#define _CDEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "cdefBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
-#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
-#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
-#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
-#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
-#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
-#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
-#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
-
-#endif /* _CDEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
deleted file mode 100644
index cc9bf0d378c3..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF516_H
-#define _CDEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "cdefBF514.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
deleted file mode 100644
index 96a82fd62ef1..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF518_H
-#define _CDEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "cdefBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
deleted file mode 100644
index e6a017faad01..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF512_H
-#define _DEF_BF512_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
-/* ************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
-#define SPI1_REGBASE 0xFFC03400
-#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
-#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
-#define SPI1_STAT 0xFFC03408 /* SPI Status register */
-#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
-#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Motor Control PWM Registers */
-
-#define PWM_CTRL 0xffc03700 /* PWM Control Register */
-#define PWM_STAT 0xffc03704 /* PWM Status Register */
-#define PWM_TM 0xffc03708 /* PWM Period Register */
-#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
-#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
-#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
-#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
-#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
-#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
-#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
-#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
deleted file mode 100644
index 97feaa629ed7..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF514_H
-#define _DEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "defBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
-
-#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
deleted file mode 100644
index 7c79cb6a03b1..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF516_H
-#define _DEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "defBF514.h"
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
deleted file mode 100644
index 12042ff13601..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF518_H
-#define _DEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "defBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
-
-/* Bit masks for EMAC_PTP_CTL */
-
-#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
-#define TL 0x2 /* Timestamp lock control */
-#define ASEN 0x10 /* Auxiliary snapshot control */
-#define PPSEN 0x80 /* Pulse-per-second (PPS) control */
-#define CKOEN 0x2000 /* Clock output control */
-
-/* Bit masks for EMAC_PTP_IE */
-
-#define ALIE 0x1 /* Alarm interrupt enable */
-#define RXEIE 0x2 /* Receive event interrupt enable */
-#define RXGIE 0x4 /* Receive general interrupt enable */
-#define TXIE 0x8 /* Transmit interrupt enable */
-#define RXOVE 0x10 /* Receive overrun error interrupt enable */
-#define TXOVE 0x20 /* Transmit overrun error interrupt enable */
-#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
-
-/* Bit masks for EMAC_PTP_ISTAT */
-
-#define ALS 0x1 /* Alarm status */
-#define RXEL 0x2 /* Receive event interrupt status */
-#define RXGL 0x4 /* Receive general interrupt status */
-#define TXTL 0x8 /* Transmit snapshot status */
-#define RXOV 0x10 /* Receive snapshot overrun status */
-#define TXOV 0x20 /* Transmit snapshot overrun status */
-#define ASL 0x40 /* Auxiliary snapshot interrupt status */
-
-#endif /* _DEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h
deleted file mode 100644
index bbd33c1706e2..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/dma.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_RSI 4 /* RSI */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPI1 5 /* SPI1 transmit/receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI0 7 /* SPI0 transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_SRC 12 /* RX */
-#define CH_MEM_STREAM0_DEST 13 /* TX */
-#define CH_MEM_STREAM1_SRC 14 /* RX */
-#define CH_MEM_STREAM1_DEST 15 /* TX */
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
deleted file mode 100644
index b480705bfc2e..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
deleted file mode 100644
index edf8efd457dc..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF518_IRQ_H_
-#define _BF518_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
-#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
-#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
-#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
-#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
-#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_PTP_ERROR_POS 8
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_RSI_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPI1_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI0_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS 0
-#define IRQ_RSI_INT0_POS 12
-#define IRQ_RSI_INT1_POS 16
-#define IRQ_PWM_TRIP_POS 20
-#define IRQ_PWM_SYNC_POS 24
-#define IRQ_PTP_STAT_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h
deleted file mode 100644
index 073b5d73d391..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF51x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF518/6/4/2 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16 * 1024)
-#else
-#define BFIN_ICACHESIZE (0)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0x8000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16 * 1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32 * 1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE 0
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
deleted file mode 100644
index b3b806f468da..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#else
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#endif
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#else
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-
-/* PWM */
-#ifndef CONFIG_BF518_PWM_PORTF_PORTG
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#else
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_SYNC_PF15
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_TRIPB_PG14
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#else
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c
deleted file mode 100644
index bb05bef34ec0..000000000000
--- a/arch/blackfin/mach-bf518/ints-priority.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
- ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
- ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
- ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
- ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
deleted file mode 100644
index 6df20f9c7bd4..000000000000
--- a/arch/blackfin/mach-bf527/Kconfig
+++ /dev/null
@@ -1,325 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF52x
- def_bool y
- depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
-
-if (BF52x)
-
-source "arch/blackfin/mach-bf527/boards/Kconfig"
-
-menu "BF527 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "SPORT0"
- default BF527_SPORT0_PORTG
- help
- Select PORT used for SPORT0. See Hardware Reference Manual
-
-config BF527_SPORT0_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_SPORT0_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "SPORT0 TSCLK Location"
- depends on BF527_SPORT0_PORTG
- default BF527_SPORT0_TSCLK_PG10
- help
- Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
-
-config BF527_SPORT0_TSCLK_PG10
- bool "PORT PG10"
- help
- PORT PG10
-
-config BF527_SPORT0_TSCLK_PG14
- bool "PORT PG14"
- help
- PORT PG14
-endchoice
-
-choice
- prompt "UART1"
- default BF527_UART1_PORTF
- help
- Select PORT used for UART1. See Hardware Reference Manual
-
-config BF527_UART1_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_UART1_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "NAND (NFC) Data"
- default BF527_NAND_D_PORTH
- help
- Select PORT used for NAND Data Bus. See Hardware Reference Manual
-
-config BF527_NAND_D_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_NAND_D_PORTH
- bool "PORT H"
- help
- PORT H
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF52x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-config GPIO_HYST_PORTH_8
- bool "Enable Hysteresis on PORTH 8"
-config GPIO_HYST_PORTH_9_15
- bool "Enable Hysteresis on PORTH {9...15}"
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_TMR0_FS1_PPICLK
- bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI_ERROR
- int "IRQ_SPI_ERROR"
- default 7
-config IRQ_NFC_ERROR
- int "IRQ_NFC_ERROR"
- default 7
-config IRQ_HDMA_ERROR
- int "IRQ_HDMA_ERROR"
- default 7
-config IRQ_HDMA
- int "IRQ_HDMA"
- default 7
-config IRQ_USB_EINT
- int "IRQ_USB_EINT"
- default 10
-config IRQ_USB_INT0
- int "IRQ_USB_INT0"
- default 10
-config IRQ_USB_INT1
- int "IRQ_USB_INT1"
- default 10
-config IRQ_USB_INT2
- int "IRQ_USB_INT2"
- default 10
-config IRQ_USB_DMA
- int "IRQ_USB_DMA"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
deleted file mode 100644
index 4a6cdafab8ce..000000000000
--- a/arch/blackfin/mach-bf527/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf527/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
deleted file mode 100644
index a76f02fae11c..000000000000
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN527_EZKIT
- help
- Select your board!
-
-config BFIN527_EZKIT
- bool "BF527-EZKIT"
- help
- BF527-EZKIT-LITE board support.
-
-config BFIN527_EZKIT_V2
- bool "BF527-EZKIT-V2"
- help
- BF527-EZKIT-LITE V2.1+ board support.
-
-config BFIN527_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF527"
- help
- CM-BF527 support for EVAL- and DEV-Board.
-
-config BFIN526_EZBRD
- bool "BF526-EZBRD"
- help
- BF526-EZBRD/EZKIT Lite board support.
-
-config BFIN527_AD7160EVAL
- bool "BF527-AD7160-EVAL"
- help
- BF527-AD7160-EVAL board support.
-
-config BFIN527_TLL6527M
- bool "The Learning Labs TLL6527M"
- help
- TLL6527M V1.0 platform support
-
-endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
deleted file mode 100644
index 6ada1537e20a..000000000000
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf527/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
-obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
-obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
-obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
deleted file mode 100644
index 68f2a8a806ea..000000000000
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/*
- * Copyright 2004-20010 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
-static struct resource bf52x_ra158z_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_ra158z_device = {
- .name = "bfin-ra158z",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
- .resource = bf52x_ra158z_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ad7160eval_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ad7160eval_flash_data = {
- .width = 2,
- .parts = ad7160eval_partitions,
- .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
-};
-
-static struct resource ad7160eval_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ad7160eval_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ad7160eval_flash_data,
- },
- .num_resources = 1,
- .resource = &ad7160eval_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PH3 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
-#include <linux/input/ad7160.h>
-static const struct ad7160_platform_data bfin_ad7160_ts_info = {
- .sensor_x_res = 854,
- .sensor_y_res = 480,
- .pressure = 100,
- .filter_coef = 3,
- .coord_pref = AD7160_ORIG_TOP_LEFT,
- .first_touch_window = 5,
- .move_window = 3,
- .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
- AD7160_EMIT_ABS_MT_PRESSURE |
- AD7160_TRACKING_ID_ASCENDING,
- .finger_act_ctrl = 0x64,
- .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(60) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW,
-
- .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(80) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW |
- AD7160_HAPTIC_SLOT_C(120) |
- AD7160_HAPTIC_SLOT_C_LVL_HIGH |
- AD7160_HAPTIC_SLOT_D(30) |
- AD7160_HAPTIC_SLOT_D_LVL_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
- {
- I2C_BOARD_INFO("ad7160", 0x33),
- .irq = IRQ_PH1,
- .platform_data = (void *)&bfin_ad7160_ts_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
- &bf52x_ra158z_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ad7160eval_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-};
-
-static int __init ad7160eval_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ad7160eval_init);
-
-static struct platform_device *ad7160eval_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ad7160eval_early_devices,
- ARRAY_SIZE(ad7160eval_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
deleted file mode 100644
index b1004b35db36..000000000000
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ /dev/null
@@ -1,992 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/etherdevice.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF527";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PF11,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cmbf527_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init cm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(cm_init);
-
-static struct platform_device *cmbf527_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cmbf527_early_devices,
- ARRAY_SIZE(cmbf527_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
deleted file mode 100644
index 80bcfd1d023e..000000000000
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ /dev/null
@@ -1,891 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF526-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "sst25wf040",
-};
-
-/* SPI flash chip (sst25wf040) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PG0,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG0,
- .end = GPIO_PG0,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = GPIO_PG12,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
deleted file mode 100644
index 571edfd2ecf3..000000000000
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ /dev/null
@@ -1,1335 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-#ifdef CONFIG_BFIN527_EZKIT_V2
-const char bfin_board_name[] = "ADI BF527-EZKIT V2";
-#else
-const char bfin_board_name[] = "ADI BF527-EZKIT";
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
-
-static struct resource bf52x_t350mcqb_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_t350mcqb_device = {
- .name = "bfin-t350mcqb",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
- .resource = bf52x_t350mcqb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_8_BIT_PPI,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB800 + 4,
- .end = 0x203FB800 + 5,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 0, /* Export GPIO to gpiolib */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-
-static const u16 bfin_snd_pin[][7] = {
- {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
- {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836",
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(3, 3)] = KEY_1,
- [ADP5520_KEY(2, 3)] = KEY_2,
- [ADP5520_KEY(1, 3)] = KEY_3,
- [ADP5520_KEY(0, 3)] = KEY_UP,
- [ADP5520_KEY(3, 2)] = KEY_4,
- [ADP5520_KEY(2, 2)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(0, 2)] = KEY_DOWN,
- [ADP5520_KEY(3, 1)] = KEY_7,
- [ADP5520_KEY(2, 1)] = KEY_8,
- [ADP5520_KEY(1, 1)] = KEY_9,
- [ADP5520_KEY(0, 1)] = KEY_DOT,
- [ADP5520_KEY(3, 0)] = KEY_BACKSPACE,
- [ADP5520_KEY(2, 0)] = KEY_0,
- [ADP5520_KEY(1, 0)] = KEY_HELP,
- [ADP5520_KEY(0, 0)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .leds = &adp5520_leds_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PF8,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PF9,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
- &bf52x_t350mcqb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
deleted file mode 100644
index ce5488e8226b..000000000000
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
- * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
- * Author: Ashish Gupta
- *
- * Copyright: 2010 - The Learning Labs Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-#define LCD_BACKLIGHT_GPIO 0x40
-/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
- * LCD Backlight Enable
- */
-#endif
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "TLL6527M";
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- /*.gpio_vrsel = GPIO_PG13,*/
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = LCD_BACKLIGHT_GPIO,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition tll6527m_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0xA0000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0xD00000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tll6527m_flash_data = {
- .width = 2,
- .parts = tll6527m_partitions,
- .nr_parts = ARRAY_SIZE(tll6527m_partitions),
-};
-
-static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
-
-static struct resource tll6527m_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)tll6527m_flash_gpios,
- .end = ARRAY_SIZE(tll6527m_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device tll6527m_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &tll6527m_flash_data,
- },
- .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
- .resource = tll6527m_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
-/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
- * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
- * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
- * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
- */
-#include <linux/gpio-decoder.h>
-#define EXP_GPIO_SPISEL_BASE 0x64
-static unsigned gpio_addr_inputs[] = {
- GPIO_PG1, GPIO_PH9, GPIO_PH10
-};
-
-static struct gpio_decoder_platform_data spi_decoded_cs = {
- .base = EXP_GPIO_SPISEL_BASE,
- .input_addrs = gpio_addr_inputs,
- .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
- .default_output = 0,
-/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
-};
-
-static struct platform_device spi_decoded_gpio = {
- .name = "gpio-decoder",
- .id = 0,
- .dev = {
- .platform_data = &spi_decoded_cs,
- },
-};
-
-#else
-#define EXP_GPIO_SPISEL_BASE 0x0
-
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl345_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 2,
- .inactivity_time = 2,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
- .ev_code_act_inactivity = KEY_A, /* EV_KEY */
- .use_int2 = 1,
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3,
- /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1,
- /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* configure AUX as GPIO output*/
- .gpio_base = LCD_BACKLIGHT_GPIO,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
- .spi_present_mask = BIT(0),
- .base = 0x30,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
- .spi_present_mask = BIT(2),
- .base = 0x38,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
- /* Can be connected to TLL6527M GPIO connector */
- /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
-/*
- * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
- * SPI buffer limitations
- */
- .max_speed_hz = 10000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PH14,
- .max_speed_hz = 5000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 10000000,
- /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_sys_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_usr_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
- /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PH14,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
- {
- I2C_BOARD_INFO("adm1192", 0x2e),
- },
-
- {
- I2C_BOARD_INFO("ltc3576", 0x09),
- },
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PH13,
- .platform_data = (void *)&adxl345_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tll6527m_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &tll6527m_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
- &spi_decoded_gpio,
-#endif
-};
-
-static int __init tll6527m_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tll6527m_init);
-
-static struct platform_device *tll6527m_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tll6527m_early_devices,
- ARRAY_SIZE(tll6527m_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags,
- u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
deleted file mode 100644
index 1fabdefea73a..000000000000
--- a/arch/blackfin/mach-bf527/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file contains the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
deleted file mode 100644
index 2f9cc33deec4..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
deleted file mode 100644
index 8ff155b34f64..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_8
-#define HYST_PORTH_8 (1 << 2)
-#else
-#define HYST_PORTH_8 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_9_15
-#define HYST_PORTH_9_15 (1 << 4)
-#else
-#define HYST_PORTH_9_15 (0 << 4)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
-
-#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
-#define HYST_TMR0_FS1_PPICLK (1 << 0)
-#else
-#define HYST_TMR0_FS1_PPICLK (0 << 0)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3F)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF526
-#define CPU "BF526"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF524
-#define CPU "BF524"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF523
-#define CPU "BF523"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#define CPUID 0x27e4
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
deleted file mode 100644
index e1d279274487..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf527.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "defBF522.h"
-#endif
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "defBF525.h"
-#endif
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "defBF527.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "cdefBF522.h"
-# endif
-# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "cdefBF525.h"
-# endif
-# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "cdefBF527.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
deleted file mode 100644
index 2c12e879aa4e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ /dev/null
@@ -1,1095 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
deleted file mode 100644
index bd045318a250..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "cdefBF522.h"
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
deleted file mode 100644
index eb22f5866105..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "cdefBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
deleted file mode 100644
index e007017cf958..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ /dev/null
@@ -1,1309 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03700 /* NAND Control Register */
-#define NFC_STAT 0xffc03704 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
-#define NFC_READ 0xffc0372c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03740 /* NAND Address Register */
-#define NFC_CMD 0xffc03744 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
deleted file mode 100644
index 591e00ff620a..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "defBF522.h"
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03800 /* Function address register */
-#define USB_POWER 0xffc03804 /* Power management register */
-#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03820 /* USB frame number */
-#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
-
-#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
-#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
-#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
-#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
-#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
-#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
-#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
-#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
-#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
-#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
-#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
-#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
-#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
deleted file mode 100644
index aeb84795b35e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "defBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h
deleted file mode 100644
index eb287da101a2..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/dma.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI 7 /* SPI transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
deleted file mode 100644
index fba606b699c3..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
deleted file mode 100644
index ed7310ff819b..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
-#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
-#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
-#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
-#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
deleted file mode 100644
index d96e894afd2c..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF52x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
deleted file mode 100644
index 08bae421f5c9..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT (P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
deleted file mode 100644
index 44ca215bf164..000000000000
--- a/arch/blackfin/mach-bf527/ints-priority.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
- ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
- ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
- ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
deleted file mode 100644
index 4e1a05be7137..000000000000
--- a/arch/blackfin/mach-bf533/Kconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF533 || BF532 || BF531)
-
-source "arch/blackfin/mach-bf533/boards/Kconfig"
-
-menu "BF533/2/1 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config UART_ERROR
- int "UART ERROR"
- default 7
-config SPORT0_ERROR
- int "SPORT0 ERROR"
- default 7
-config SPI_ERROR
- int "SPI ERROR"
- default 7
-config SPORT1_ERROR
- int "SPORT1 ERROR"
- default 7
-config PPI_ERROR
- int "PPI ERROR"
- default 7
-config DMA_ERROR
- int "DMA ERROR"
- default 7
-config PLLWAKE_ERROR
- int "PLL WAKEUP ERROR"
- default 7
-
-config RTC_ERROR
- int "RTC ERROR"
- default 8
-config DMA0_PPI
- int "DMA0 PPI"
- default 8
-
-config DMA1_SPORT0RX
- int "DMA1 (SPORT0 RX)"
- default 9
-config DMA2_SPORT0TX
- int "DMA2 (SPORT0 TX)"
- default 9
-config DMA3_SPORT1RX
- int "DMA3 (SPORT1 RX)"
- default 9
-config DMA4_SPORT1TX
- int "DMA4 (SPORT1 TX)"
- default 9
-config DMA5_SPI
- int "DMA5 (SPI)"
- default 10
-config DMA6_UARTRX
- int "DMA6 (UART0 RX)"
- default 10
-config DMA7_UARTTX
- int "DMA7 (UART0 TX)"
- default 10
-config TIMER0
- int "TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config TIMER1
- int "TIMER1"
- default 11
-config TIMER2
- int "TIMER2"
- default 11
-config PFA
- int "PF Interrupt A"
- default 12
-config PFB
- int "PF Interrupt B"
- default 12
-config MEMDMA0
- int "MEMORY DMA0"
- default 13
-config MEMDMA1
- int "MEMORY DMA1"
- default 13
-config WDTIMER
- int "WATCH DOG TIMER"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
deleted file mode 100644
index 874840f76028..000000000000
--- a/arch/blackfin/mach-bf533/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf533/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
deleted file mode 100644
index 01300f40db15..000000000000
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007-2008 HV Sistemas S.L.
- * Javier Herrero <jherrero@hvsistemas.es>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "HV Sistemas H8606";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
-* Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x20300000,
- .end = 0x20300002,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x20300004,
- .end = 0x20300006,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_SHAREABLE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .id = 0,
- .name = "dm9000",
- .resource = dm9000_resources,
- .num_resources = ARRAY_SIZE(dm9000_resources),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader (spi)",
- .size = 0x40000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "fpga (spi)",
- .size = 0x30000,
- .offset = 0x40000
- }, {
- .name = "linux kernel (spi)",
- .size = 0x150000,
- .offset = 0x70000
- }, {
- .name = "jffs2 root file system (spi)",
- .size = 0x640000,
- .offset = 0x1c0000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- /* this value is the baudrate divisor */
- .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 16,
- .bus_num = 1,
- .chip_select = 4,
- },
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
-
-#include <linux/serial_8250.h>
-#include <linux/serial.h>
-
-/*
- * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
- * running at half system clock, both with interrupt output or-ed to PF8. Change to
- * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
- */
-
-static struct plat_serial8250_port serial8250_platform_data [] = {
- {
- .membase = (void *)0x20200000,
- .mapbase = 0x20200000,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- .membase = (void *)0x20200010,
- .mapbase = 0x20200010,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- }
-};
-
-static struct platform_device serial8250_device = {
- .id = PLAT8250_DEV_PLATFORM,
- .name = "serial8250",
- .dev = {
- .platform_data = serial8250_platform_data,
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
-
-/*
- * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
- * interrupt output wired to PF9. Change to suit different FPGA configuration
- */
-
-static struct resource opencores_kbd_resources[] = {
- [0] = {
- .start = 0x20200030,
- .end = 0x20300030 + 2,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device opencores_kbd_device = {
- .id = -1,
- .name = "opencores-kbd",
- .resource = opencores_kbd_resources,
- .num_resources = ARRAY_SIZE(opencores_kbd_resources),
-};
-#endif
-
-static struct platform_device *h8606_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
- &serial8250_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
- &opencores_kbd_device,
-#endif
-};
-
-static int __init H8606_init(void)
-{
- printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(H8606_init);
-
-static struct platform_device *H8606_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(H8606_early_devices,
- ARRAY_SIZE(H8606_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig
deleted file mode 100644
index 3fde0df1b5f2..000000000000
--- a/arch/blackfin/mach-bf533/boards/Kconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN533_STAMP
- help
- Select your board!
-
-config BFIN533_EZKIT
- bool "BF533-EZKIT"
- help
- BF533-EZKIT-LITE board support.
-
-config BFIN533_STAMP
- bool "BF533-STAMP"
- help
- BF533-STAMP board support.
-
-config BLACKSTAMP
- bool "BlackStamp"
- help
- Support for the BlackStamp board. Hardware info available at
- http://blackfin.uclinux.org/gf/project/blackstamp/
-
-config BFIN533_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF533"
- depends on (BF533)
- help
- CM-BF533 support for EVAL- and DEV-Board.
-
-config H8606_HVSISTEMAS
- bool "HV Sistemas H8606"
- depends on (BF532)
- help
- HV Sistemas H8606 board support.
-
-config BFIN532_IP0X
- bool "IP04/IP08 IP-PBX"
- depends on (BF532)
- help
- Core support for IP04/IP04 open hardware IP-PBX.
-
-endchoice
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile
deleted file mode 100644
index 35256d2fc040..000000000000
--- a/arch/blackfin/mach-bf533/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf533/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN533_STAMP) += stamp.o
-obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
-obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
-obj-$(CONFIG_BLACKSTAMP) += blackstamp.o
-obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
deleted file mode 100644
index fab69c736515..000000000000
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
- * Board Info File for the BlackStamp
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * 2008 Benjamin Matthews <bmat@lle.rochester.edu>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * More info about the BlackStamp at:
- * http://blackfin.uclinux.org/gf/project/blackstamp/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "BlackStamp";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF4, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF5, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF6, 0, "gpio-keys: BTN2"},
-}; /* Mapped to the first three PF Test Points */
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-}; /* This hasn't actually been used these pins
- * are (currently) free pins on the expansion connector */
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-};
-
-static int __init blackstamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(blackstamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
deleted file mode 100644
index 4ef2fb0e48d5..000000000000
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF533";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x20308000,
- .end = 0x20308000 + 0xFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF6,
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux+rootfs(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &para_flash_data,
- },
- .num_resources = 1,
- .resource = &para_flash_resource,
-};
-#endif
-
-
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf533_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &para_flash_device,
-#endif
-};
-
-static int __init cm_bf533_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(cm_bf533_init);
-
-static struct platform_device *cm_bf533_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf533_early_devices,
- ARRAY_SIZE(cm_bf533_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
deleted file mode 100644
index d64d270e9e62..000000000000
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-EZKIT";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions_a[] = {
- {
- .name = "bootloader(nor a)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor a)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_a = {
- .width = 2,
- .parts = ezkit_partitions_a,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_a),
-};
-
-static struct resource ezkit_flash_resource_a = {
- .start = 0x20000000,
- .end = 0x200fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_a = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data_a,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_a,
-};
-
-static struct mtd_partition ezkit_partitions_b[] = {
- {
- .name = "file system(nor b)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_b = {
- .width = 2,
- .parts = ezkit_partitions_b,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_b),
-};
-
-static struct resource ezkit_flash_resource_b = {
- .start = 0x20100000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_b = {
- .name = "physmap-flash",
- .id = 4,
- .dev = {
- .platform_data = &ezkit_flash_data_b,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram sram_data_a = {
- .mapname = "Flash A SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_a = {
- .start = 0x20240000,
- .end = 0x2024ffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_a = {
- .name = "mtd-ram",
- .id = 8,
- .dev = {
- .platform_data = &sram_data_a,
- },
- .num_resources = 1,
- .resource = &sram_resource_a,
-};
-
-static struct platdata_mtd_ram sram_data_b = {
- .mapname = "Flash B SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_b = {
- .start = 0x202c0000,
- .end = 0x202cffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_b = {
- .name = "mtd-ram",
- .id = 9,
- .dev = {
- .platform_data = &sram_data_b,
- },
- .num_resources = 1,
- .resource = &sram_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device_a,
- &ezkit_flash_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &sram_device_a,
- &sram_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
deleted file mode 100644
index 39c8e8547b82..000000000000
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007 David Rowe
- * 2006 Intratrade Ltd.
- * Ivan Danov <idanov@gmail.com>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "IP04/IP08";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
-
-#include <linux/dm9000.h>
-
-static struct resource dm9000_resource1[] = {
- {
- .start = 0x20100000,
- .end = 0x20100000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20100000 + 2,
- .end = 0x20100000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-static struct resource dm9000_resource2[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20200000 + 2,
- .end = 0x20200000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-/*
-* for the moment we limit ourselves to 16bit IO until some
-* better IO routines can be written and tested
-*/
-static struct dm9000_plat_data dm9000_platdata1 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device1 = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000_resource1),
- .resource = dm9000_resource1,
- .dev = {
- .platform_data = &dm9000_platdata1,
- }
-};
-
-static struct dm9000_plat_data dm9000_platdata2 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device2 = {
- .name = "dm9000",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm9000_resource2),
- .resource = dm9000_resource2,
- .dev = {
- .platform_data = &dm9000_platdata2,
- }
-};
-
-#endif
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* if 1 - block!!! */
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 2,
- .bus_num = 1,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi-master",
- .id = 1, /* Bus number */
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 1,
- .flags = IORESOURCE_MEM,
- },{
- .start = 0x20300000 + 2,
- .end = 0x20300000 + 3,
- .flags = IORESOURCE_MEM,
- },{
- .start = IRQ_PF11,
- .end = IRQ_PF11,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0, /* external OC */
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-static struct platform_device *ip0x_devices[] __initdata = {
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device1,
- &dm9000_device2,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-};
-
-static int __init ip0x_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ip0x_init);
-
-static struct platform_device *ip0x_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ip0x_early_devices,
- ARRAY_SIZE(ip0x_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
deleted file mode 100644
index 27cbf2fa2c62..000000000000
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ /dev/null
@@ -1,919 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-STAMP";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-};
-
-static struct resource stamp_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x7BB07BB0, /* AMBCTL0 setting when accessing flash */
- .end = 0x7BB07BB0, /* AMBCTL1 setting when accessing flash */
- .flags = IORESOURCE_MEM,
- }, {
- .start = GPIO_PF0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "bfin-async-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = ARRAY_SIZE(stamp_flash_resource),
- .resource = stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_JOYSTICK_AD7142)
- {
- I2C_BOARD_INFO("ad7142_joystick", 0x2C),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#include <asm/bfin_sport.h>
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
-static struct platform_device bfin_ad74111_codec_device = {
- .name = "ad74111",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
- &bfin_ad74111_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
- ret = gpio_request(GPIO_PF0, "net2272");
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PF1, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- return ret;
- }
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- gpio_free(GPIO_PF1);
- return ret;
- }
-
- gpio_direction_output(GPIO_PF0, 0);
- gpio_direction_output(GPIO_PF1, 1);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround pull up on cpld / flash pin not being strong enough */
- gpio_request(GPIO_PF0, "flash_cpld");
- gpio_direction_output(GPIO_PF0, 0);
-}
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
deleted file mode 100644
index 1f5988d43139..000000000000
--- a/arch/blackfin/mach-bf533/dma.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
deleted file mode 100644
index 0e754efc3cf6..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set at Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
deleted file mode 100644
index e3e05f8f7af9..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bf533.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF533_H__
-#define __MACH_BF533_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_BIT 0x0FFFFFFF
-#define UART_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0xFF0FFFFF
-#define SPI_ERROR_BIT 0xFFF0FFFF
-#define SPORT0_ERROR_BIT 0xFFFF0FFF
-#define PPI_ERROR_BIT 0xFFFFF0FF
-#define DMA_ERROR_BIT 0xFFFFFF0F
-#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_BIT 0x0FFFFFFF
-#define DMA6_UARTRX_BIT 0xF0FFFFFF
-#define DMA5_SPI_BIT 0xFF0FFFFF
-#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
-#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
-#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
-#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
-#define DMA0_PPI_BIT 0xFFFFFFFF
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_BIT 0x0FFFFFFF
-#define MEMDMA1_BIT 0xF0FFFFFF
-#define MEMDMA0_BIT 0xFF0FFFFF
-#define PFB_BIT 0xFFF0FFFF
-#define PFA_BIT 0xFFFF0FFF
-#define TIMER2_BIT 0xFFFFF0FF
-#define TIMER1_BIT 0xFFFFFF0F
-#define TIMER0_BIT 0xFFFFFFFF
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF533
-#define CPU "BF533"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF532
-#define CPU "BF532"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF531
-#define CPU "BF531"
-#define CPUID 0x27a5
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
deleted file mode 100644
index 08072c86d5dc..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
deleted file mode 100644
index e366207fbf12..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF533_FAMILY
-
-#include "bf533.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF532.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF532.h"
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
deleted file mode 100644
index fd0cbe4df21a..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ /dev/null
@@ -1,682 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* DMA Traffic controls */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
-#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
-#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
-#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
-#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
-#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
-#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
-#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
-#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
-#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
-#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
-
-#if ANOMALY_05000311
-/* Keep at the CPP expansion to avoid circular header dependency loops */
-#define BFIN_WRITE_FIO_FLAG(name, val) \
- do { \
- unsigned long __flags; \
- __flags = hard_local_irq_save(); \
- bfin_write16(FIO_FLAG_##name, val); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- } while (0)
-#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
-#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
-#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
-#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
-
-#define BFIN_READ_FIO_FLAG(name) \
- ({ \
- unsigned long __flags; \
- u16 __ret; \
- __flags = hard_local_irq_save(); \
- __ret = bfin_read16(FIO_FLAG_##name); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- __ret; \
- })
-#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
-#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
-#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
-#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#endif
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-
-/* UART Controller */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-/*
-#define UART_MSR
-*/
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER 0, 1, 2 Registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
-
-/* SPORT0 Controller */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* Parallel Peripheral Interface (PPI) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
deleted file mode 100644
index d438150b1025..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/*
- * System & MMR bit and Address definitions for ADSP-BF532
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#if 0
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
-#endif
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic controls */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
- /* SIC_IAR0 Masks */
-
-#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Masks */
-
-#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
-#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001
-#define TIMIL1 0x0002
-#define TIMIL2 0x0004
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000
-#define TRUN1 0x2000
-#define TRUN2 0x4000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x00000001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
-#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-
-#endif /* _DEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
deleted file mode 100644
index fb34934c5ba8..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 12
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_MEM_STREAM0_DEST 8 /* TX */
-#define CH_MEM_STREAM0_SRC 9 /* RX */
-#define CH_MEM_STREAM1_DEST 10 /* TX */
-#define CH_MEM_STREAM1_SRC 11 /* RX */
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
deleted file mode 100644
index cce4f8fb3785..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-
-#define PORT_F GPIO_PF0
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
deleted file mode 100644
index 709733754142..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF533_IRQ_H_
-#define _BF533_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 24
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
-#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
-#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
-
-#define SYS_IRQS 31
-
-#define IRQ_PF0 33
-#define IRQ_PF1 34
-#define IRQ_PF2 35
-#define IRQ_PF3 36
-#define IRQ_PF4 37
-#define IRQ_PF5 38
-#define IRQ_PF6 39
-#define IRQ_PF7 40
-#define IRQ_PF8 41
-#define IRQ_PF9 42
-#define IRQ_PF10 43
-#define IRQ_PF11 44
-#define IRQ_PF12 45
-#define IRQ_PF13 46
-#define IRQ_PF14 47
-#define IRQ_PF15 48
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define RTC_ERROR_POS 28
-#define UART_ERROR_POS 24
-#define SPORT1_ERROR_POS 20
-#define SPI_ERROR_POS 16
-#define SPORT0_ERROR_POS 12
-#define PPI_ERROR_POS 8
-#define DMA_ERROR_POS 4
-#define PLLWAKE_ERROR_POS 0
-
-/* IAR1 BIT FIELDS */
-#define DMA7_UARTTX_POS 28
-#define DMA6_UARTRX_POS 24
-#define DMA5_SPI_POS 20
-#define DMA4_SPORT1TX_POS 16
-#define DMA3_SPORT1RX_POS 12
-#define DMA2_SPORT0TX_POS 8
-#define DMA1_SPORT0RX_POS 4
-#define DMA0_PPI_POS 0
-
-/* IAR2 BIT FIELDS */
-#define WDTIMER_POS 28
-#define MEMDMA1_POS 24
-#define MEMDMA0_POS 20
-#define PFB_POS 16
-#define PFA_POS 12
-#define TIMER2_POS 8
-#define TIMER1_POS 4
-#define TIMER0_POS 0
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
deleted file mode 100644
index 197af1a398ac..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/mem_map.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * BF533 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF533 processors */
-
-#ifdef CONFIG_BF533
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF532 processors */
-
-#ifdef CONFIG_BF532
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0xC000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0xC000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF531 processors */
-
-#ifdef CONFIG_BF531
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-#define L1_CODE_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x0000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h
deleted file mode 100644
index 96f5d9129f20..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/portmux.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c
deleted file mode 100644
index 8f714cf8135b..000000000000
--- a/arch/blackfin/mach-bf533/ints-priority.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) |
- ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) |
- ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) |
- ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) |
- ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) |
- ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) |
- ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) |
- ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) |
- ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) |
- ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) |
- ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) |
- ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) |
- ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) |
- ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) |
- ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) |
- ((CONFIG_TIMER1 - 7) << TIMER1_POS) |
- ((CONFIG_TIMER2 - 7) << TIMER2_POS) |
- ((CONFIG_PFA - 7) << PFA_POS) |
- ((CONFIG_PFB - 7) << PFB_POS) |
- ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) |
- ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) |
- ((CONFIG_WDTIMER - 7) << WDTIMER_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
deleted file mode 100644
index 1d69b043afd4..000000000000
--- a/arch/blackfin/mach-bf537/Kconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF537 || BF534 || BF536)
-
-source "arch/blackfin/mach-bf537/boards/Kconfig"
-
-menu "BF537 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA_ERROR
- int "IRQ_DMA_ERROR Generic"
- default 7
-config IRQ_ERROR
- int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
- default 11
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PROG_INTA
- int "IRQ_PROG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
deleted file mode 100644
index 56994b675f9c..000000000000
--- a/arch/blackfin/mach-bf537/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
deleted file mode 100644
index 60b7b29e512e..000000000000
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN537_STAMP
- help
- Select your board!
-
-config BFIN537_STAMP
- bool "BF537-STAMP"
- help
- BF537-STAMP board support.
-
-config BFIN537_BLUETECHNIX_CM_E
- bool "Bluetechnix CM-BF537E"
- depends on (BF537)
- help
- CM-BF537E support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_CM_U
- bool "Bluetechnix CM-BF537U"
- depends on (BF537)
- help
- CM-BF537U support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_TCM
- bool "Bluetechnix TCM-BF537"
- depends on (BF537)
- help
- TCM-BF537 support for EVAL- and DEV-Board.
-
-config PNAV10
- bool "PNAV board"
- depends on (BF537)
- help
- PNAV board support.
-
-config CAMSIG_MINOTAUR
- bool "Cambridge Signal Processing LTD Minotaur"
- depends on (BF537)
- help
- Board supply package for CSP Minotaur
-
-config DNP5370
- bool "SSV Dil/NetPC DNP/5370"
- depends on (BF537)
- help
- Board supply package for DNP/5370 DIL64 module
-
-endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
deleted file mode 100644
index 47a1acc5f389..000000000000
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf537/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN537_STAMP) += stamp.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
-obj-$(CONFIG_PNAV10) += pnav10.o
-obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
-obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
deleted file mode 100644
index 1e1014df5e9e..000000000000
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537E";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537e_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537e_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537e_init);
-
-static struct platform_device *cm_bf537e_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537e_early_devices,
- ARRAY_SIZE(cm_bf537e_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
deleted file mode 100644
index d056db9e5592..000000000000
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ /dev/null
@@ -1,802 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537U";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PH14,
- .end = IRQ_PH14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH0 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537u_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PH15, driver_name);
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PH13, "net2272");
- if (ret) {
- gpio_free(GPIO_PH15);
- return ret;
- }
-
- /* Set PH15 Low make /AMS2 work properly */
- gpio_direction_output(GPIO_PH15, 0);
-
- /* enable CLKBUF output */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PH13, 0);
- mdelay(2);
- gpio_set_value(GPIO_PH13, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537u_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537u_init);
-
-static struct platform_device *cm_bf537u_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537u_early_devices,
- ARRAY_SIZE(cm_bf537u_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
deleted file mode 100644
index c4a8ffb15417..000000000000
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This is the configuration for SSV Dil/NetPC DNP/5370 board.
- *
- * DIL module: http://www.dilnetpc.com/dnp0086.htm
- * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
- *
- * Copyright 2010 3ality Digital Systems
- * Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/phy.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "DNP/5370";
-#define FLASH_MAC 0x202f0000
-#define CONFIG_MTD_PHYSMAP_LEN 0x300000
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition asmb_flash_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x30000,
- .offset = 0,
- }, {
- .name = "linux kernel and rootfs(nor)",
- .size = 0x300000 - 0x30000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC address(nor)",
- .size = 0x10000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data asmb_flash_data = {
- .width = 1,
- .parts = asmb_flash_partitions,
- .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
-};
-
-static struct resource asmb_flash_resource = {
- .start = 0x20000000,
- .end = 0x202fffff,
- .flags = IORESOURCE_MEM,
-};
-
-/* 4 MB NOR flash attached to async memory banks 0-2,
- * therefore only 3 MB visible.
- */
-static struct platform_device asmb_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &asmb_flash_data,
- },
- .num_resources = 1,
- .resource = &asmb_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-/* This mapping is for at45db642 it has 1056 page size,
- * partition size and offset should be page aligned
- */
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "JFFS2 dataflash(nor)",
-#ifdef CONFIG_MTD_PAGESIZE_1024
- .offset = 0x40000,
- .size = 0x7C0000,
-#else
- .offset = 0x0,
- .size = 0x840000,
-#endif
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "mtd_dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
- .type = "mtd_dataflash",
-};
-
-static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-/* SD/MMC card reader at SPI bus */
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-/* 8 Megabyte Atmel NOR flash chip at SPI bus */
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- {
- .modalias = "mtd_dataflash",
- .max_speed_hz = 16700000,
- .bus_num = 0,
- .chip_select = 2,
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &spi_dataflash_chip_info,
- .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
- },
-#endif
-};
-
-/* SPI controller data */
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct platform_device *dnp5370_devices[] __initdata = {
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &asmb_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-};
-
-static int __init dnp5370_init(void)
-{
- printk(KERN_INFO "DNP/5370: registering device resources\n");
- platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
- printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
- ARRAY_SIZE(bfin_spi_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
- return 0;
-}
-arch_initcall(dnp5370_init);
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
deleted file mode 100644
index dd7bda07bf90..000000000000
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Cambridge Signal Processing
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "CamSig Minotaur BF537";
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = IRQ_PF6, /* Card Detect PF6 */
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-
-/* Partition sizes */
-#define FLASH_SIZE 0x00400000
-#define PSIZE_UBOOT 0x00030000
-#define PSIZE_INITRAMFS 0x00240000
-
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = PSIZE_UBOOT,
- .offset = 0x000000,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "initramfs(spi)",
- .size = PSIZE_INITRAMFS,
- .offset = PSIZE_UBOOT
- }, {
- .name = "opt(spi)",
- .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
- .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static struct platform_device *minotaur_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-};
-
-static int __init minotaur_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(minotaur_init);
-
-static struct platform_device *minotaur_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(minotaur_early_devices,
- ARRAY_SIZE(minotaur_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
deleted file mode 100644
index 06a50ddb54c0..000000000000
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI PNAV-1.0";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF2,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
-},
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537-lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-};
-
-static int __init pnav_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(pnav_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
deleted file mode 100644
index 400e6693643e..000000000000
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ /dev/null
@@ -1,3019 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/i2c.h>
-#include <linux/platform_data/adp5588.h>
-#include <linux/etherdevice.h>
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
-#include <linux/regulator/fixed.h>
-#endif
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/regulator/userspace-consumer.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF537-STAMP";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
-static struct resource sl811_hcd_resources[] = {
- {
- .start = 0x20340000,
- .end = 0x20340000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20340004,
- .end = 0x20340004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
-void sl811_port_power(struct device *dev, int is_on)
-{
- gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
-}
-#endif
-
-static struct sl811_platform_data sl811_priv = {
- .potpg = 10,
- .power = 250, /* == 500mA */
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
- .port_power = &sl811_port_power,
-#endif
-};
-
-static struct platform_device sl811_hcd_device = {
- .name = "sl811-hcd",
- .id = 0,
- .dev = {
- .platform_data = &sl811_priv,
- },
- .num_resources = ARRAY_SIZE(sl811_hcd_resources),
- .resource = sl811_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20360000,
- .end = 0x20360000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20360004,
- .end = 0x20360004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "linux kernel(nand)",
- .size = 0x400000,
- .offset = 0,
- }, {
- .name = "file system(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 1
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF3
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .part_probe_types = part_probes,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x20212000,
- .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
- gpio_direction_input(BFIN_NAND_PLAT_READY);
-}
-#else
-static void bfin_plat_nand_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC Address(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x3F0000,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource stamp_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = 1,
- .resource = &stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- /* .type = "m25p64", */
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
-#include <linux/input/ad714x.h>
-
-static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
- {
- .start_stage = 0,
- .end_stage = 7,
- .max_coord = 128,
- },
-};
-
-static struct ad714x_button_plat ad7147_spi_button_plat[] = {
- {
- .keycode = BTN_FORWARD,
- .l_mask = 0,
- .h_mask = 0x600,
- },
- {
- .keycode = BTN_LEFT,
- .l_mask = 0,
- .h_mask = 0x500,
- },
- {
- .keycode = BTN_MIDDLE,
- .l_mask = 0,
- .h_mask = 0x800,
- },
- {
- .keycode = BTN_RIGHT,
- .l_mask = 0x100,
- .h_mask = 0x400,
- },
- {
- .keycode = BTN_BACK,
- .l_mask = 0x200,
- .h_mask = 0x400,
- },
-};
-static struct ad714x_platform_data ad7147_spi_platform_data = {
- .slider_num = 1,
- .button_num = 5,
- .slider = ad7147_spi_slider_plat,
- .button = ad7147_spi_button_plat,
- .stage_cfg_reg = {
- {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
- {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
- {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
- {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
- },
- .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
-#include <linux/input/ad714x.h>
-static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
- {
- .keycode = BTN_1,
- .l_mask = 0,
- .h_mask = 0x1,
- },
- {
- .keycode = BTN_2,
- .l_mask = 0,
- .h_mask = 0x2,
- },
- {
- .keycode = BTN_3,
- .l_mask = 0,
- .h_mask = 0x4,
- },
- {
- .keycode = BTN_4,
- .l_mask = 0x0,
- .h_mask = 0x8,
- },
-};
-static struct ad714x_platform_data ad7142_i2c_platform_data = {
- .button_num = 4,
- .button = ad7142_i2c_button_plat,
- .stage_cfg_reg = {
- /* fixme: figure out right setting for all comoponent according
- * to hardware feature of EVAL-AD7142EB board */
- {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- },
- .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
-static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
-static unsigned short ad2s1200_platform_data[] = {
- /* used as SAMPLE and RDVEL */
- GPIO_PF5, GPIO_PF6, 0
-};
-
-static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
-static unsigned short ad2s1210_platform_data[] = {
- /* use as SAMPLE, A0, A1 */
- GPIO_PF7, GPIO_PF8, GPIO_PF9,
-# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
- /* the RES0 and RES1 pins */
- GPIO_PF4, GPIO_PF5,
-# endif
- 0,
-};
-
-static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
-static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
-static unsigned short ad7816_platform_data[] = {
- GPIO_PF4, /* rdwr_pin */
- GPIO_PF5, /* convert_pin */
- GPIO_PF7, /* busy_pin */
- 0,
-};
-
-static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
-static unsigned long adt7310_platform_data[3] = {
-/* INT bound temperature alarm event. line 1 */
- IRQ_PG4, IRQF_TRIGGER_LOW,
-/* CT bound temperature alarm event irq_flags. line 0 */
- IRQF_TRIGGER_LOW,
-};
-
-static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
-static unsigned short ad7298_platform_data[] = {
- GPIO_PF7, /* busy_pin */
- 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
-static unsigned long adt7316_spi_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-
-static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-#include <linux/spi/ad7877.h>
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ENC28J60)
-static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
- .enable_dma = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADF702X)
-#include <linux/spi/adf702x.h>
-#define TXREG 0x0160A470
-static const u32 adf7021_regs[] = {
- 0x09608FA0,
- 0x00575011,
- 0x00A7F092,
- 0x2B141563,
- 0x81F29E94,
- 0x00003155,
- 0x050A4F66,
- 0x00000007,
- 0x00000008,
- 0x000231E9,
- 0x3296354A,
- 0x891A2B3B,
- 0x00000D9C,
- 0x0000000D,
- 0x0000000E,
- 0x0000000F,
-};
-
-static struct adf702x_platform_data adf7021_platform_data = {
- .regs_base = (void *)SPORT1_TCR1,
- .dma_ch_rx = CH_SPORT1_RX,
- .dma_ch_tx = CH_SPORT1_TX,
- .irq_sport_err = IRQ_SPORT1_ERROR,
- .gpio_int_rfs = GPIO_PF8,
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
- .adf702x_model = MODEL_ADF7021,
- .adf702x_regs = adf7021_regs,
- .tx_reg = TXREG,
-};
-static inline void adf702x_mac_init(void)
-{
- eth_random_addr(adf7021_platform_data.mac_addr);
-}
-#else
-static inline void adf702x_mac_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
-#include <linux/spi/ads7846.h>
-static int ads7873_get_pendown_state(void)
-{
- return gpio_get_value(GPIO_PF6);
-}
-
-static struct ads7846_platform_data __initdata ad7873_pdata = {
- .model = 7873, /* AD7873 */
- .x_max = 0xfff,
- .y_max = 0xfff,
- .x_plate_ohms = 620,
- .debounce_max = 1,
- .debounce_rep = 0,
- .debounce_tol = (~0),
- .get_pendown_state = ads7873_get_pendown_state,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7476)
-static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#ifdef CONFIG_SND_SOC_AD193X_SPI
- {
- .modalias = "ad193x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- .modalias = "adav801",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
- {
- .modalias = "ad714x_captouch",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF4,
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- .platform_data = &ad7147_spi_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
- {
- .modalias = "ad2s90",
- .bus_num = 0,
- .chip_select = 3, /* change it for your board */
- .mode = SPI_MODE_3,
- .platform_data = NULL,
- .controller_data = &ad2s90_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
- {
- .modalias = "ad2s1200",
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1200_platform_data,
- .controller_data = &ad2s1200_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
- {
- .modalias = "ad2s1210",
- .max_speed_hz = 8192000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1210_platform_data,
- .controller_data = &ad2s1210_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
- {
- .modalias = "ad7314",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .controller_data = &ad7314_spi_chip_info,
- .mode = SPI_MODE_1,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
- {
- .modalias = "ad7818",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7816_platform_data,
- .controller_data = &ad7816_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
- {
- .modalias = "adt7310",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* CT alarm event. Line 0 */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7310_platform_data,
- .controller_data = &adt7310_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
- {
- .modalias = "ad7298",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7298_platform_data,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
- {
- .modalias = "adt7316",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* interrupt line */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7316_spi_data,
- .controller_data = &adt7316_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF7,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_ENC28J60)
- {
- .modalias = "enc28j60",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF6,
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .controller_data = &enc28j60_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADF702X)
- {
- .modalias = "adf702x",
- .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &adf7021_platform_data,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
- {
- .modalias = "ads7846",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .irq = IRQ_PF6,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &ad7873_pdata,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_AD7476)
- {
- .modalias = "ad7476", /* Name of spi_driver for this device */
- .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. */
- .platform_data = NULL, /* No spi_driver specific config */
- .controller_data = &spi_ad7476_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7753)
- {
- .modalias = "ade7753",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7754)
- {
- .modalias = "ade7754",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7758)
- {
- .modalias = "ade7758",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7759)
- {
- .modalias = "ade7759",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7854_SPI)
- {
- .modalias = "ade7854",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16060)
- {
- .modalias = "adis16060_r",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_0,
- },
- {
- .modalias = "adis16060_w",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2, /* CS for write, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16130)
- {
- .modalias = "adis16130",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16201)
- {
- .modalias = "adis16201",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16203)
- {
- .modalias = "adis16203",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16204)
- {
- .modalias = "adis16204",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16209)
- {
- .modalias = "adis16209",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16220)
- {
- .modalias = "adis16220",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16240)
- {
- .modalias = "adis16240",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16260)
- {
- .modalias = "adis16260",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16261)
- {
- .modalias = "adis16261",
- .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16300)
- {
- .modalias = "adis16300",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16350)
- {
- .modalias = "adis16364",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16400)
- {
- .modalias = "adis16400",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537_lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI,
- .irq_err = IRQ_PPI_ERROR,
- .base = (void __iomem *)PPI_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PF10;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF537",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
-static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
- [0] = KEY_GRAVE,
- [1] = KEY_1,
- [2] = KEY_2,
- [3] = KEY_3,
- [4] = KEY_4,
- [5] = KEY_5,
- [6] = KEY_6,
- [7] = KEY_7,
- [8] = KEY_8,
- [9] = KEY_9,
- [10] = KEY_0,
- [11] = KEY_MINUS,
- [12] = KEY_EQUAL,
- [13] = KEY_BACKSLASH,
- [15] = KEY_KP0,
- [16] = KEY_Q,
- [17] = KEY_W,
- [18] = KEY_E,
- [19] = KEY_R,
- [20] = KEY_T,
- [21] = KEY_Y,
- [22] = KEY_U,
- [23] = KEY_I,
- [24] = KEY_O,
- [25] = KEY_P,
- [26] = KEY_LEFTBRACE,
- [27] = KEY_RIGHTBRACE,
- [29] = KEY_KP1,
- [30] = KEY_KP2,
- [31] = KEY_KP3,
- [32] = KEY_A,
- [33] = KEY_S,
- [34] = KEY_D,
- [35] = KEY_F,
- [36] = KEY_G,
- [37] = KEY_H,
- [38] = KEY_J,
- [39] = KEY_K,
- [40] = KEY_L,
- [41] = KEY_SEMICOLON,
- [42] = KEY_APOSTROPHE,
- [43] = KEY_BACKSLASH,
- [45] = KEY_KP4,
- [46] = KEY_KP5,
- [47] = KEY_KP6,
- [48] = KEY_102ND,
- [49] = KEY_Z,
- [50] = KEY_X,
- [51] = KEY_C,
- [52] = KEY_V,
- [53] = KEY_B,
- [54] = KEY_N,
- [55] = KEY_M,
- [56] = KEY_COMMA,
- [57] = KEY_DOT,
- [58] = KEY_SLASH,
- [60] = KEY_KPDOT,
- [61] = KEY_KP7,
- [62] = KEY_KP8,
- [63] = KEY_KP9,
- [64] = KEY_SPACE,
- [65] = KEY_BACKSPACE,
- [66] = KEY_TAB,
- [67] = KEY_KPENTER,
- [68] = KEY_ENTER,
- [69] = KEY_ESC,
- [70] = KEY_DELETE,
- [74] = KEY_KPMINUS,
- [76] = KEY_UP,
- [77] = KEY_DOWN,
- [78] = KEY_RIGHT,
- [79] = KEY_LEFT,
-};
-
-static struct adp5588_kpad_platform_data adp5588_kpad_data = {
- .rows = 8,
- .cols = 10,
- .keymap = adp5588_keymap,
- .keymapsize = ARRAY_SIZE(adp5588_keymap),
- .repeat = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 Backlight Data
- */
-
-static struct adp5520_backlight_platform_data adp5520_backlight_data = {
- .fade_in = ADP5520_FADE_T_1200ms,
- .fade_out = ADP5520_FADE_T_1200ms,
- .fade_led_law = ADP5520_BL_LAW_LINEAR,
- .en_ambl_sens = 1,
- .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
- .l1_daylight_max = ADP5520_BL_CUR_mA(15),
- .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
- .l2_office_max = ADP5520_BL_CUR_mA(7),
- .l2_office_dim = ADP5520_BL_CUR_mA(0),
- .l3_dark_max = ADP5520_BL_CUR_mA(3),
- .l3_dark_dim = ADP5520_BL_CUR_mA(0),
- .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
- .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
- .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
- .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
-};
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-#ifdef ADP5520_EN_ALL_LEDS
- {
- .name = "adp5520-led2",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
- },
- {
- .name = "adp5520-led3",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
- },
-#endif
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 GPIO Data
- */
-
-static struct adp5520_gpio_platform_data adp5520_gpio_data = {
- .gpio_start = 50,
- .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
- .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(0, 0)] = KEY_GRAVE,
- [ADP5520_KEY(0, 1)] = KEY_1,
- [ADP5520_KEY(0, 2)] = KEY_2,
- [ADP5520_KEY(0, 3)] = KEY_3,
- [ADP5520_KEY(1, 0)] = KEY_4,
- [ADP5520_KEY(1, 1)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(1, 3)] = KEY_7,
- [ADP5520_KEY(2, 0)] = KEY_8,
- [ADP5520_KEY(2, 1)] = KEY_9,
- [ADP5520_KEY(2, 2)] = KEY_0,
- [ADP5520_KEY(2, 3)] = KEY_MINUS,
- [ADP5520_KEY(3, 0)] = KEY_EQUAL,
- [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
- [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
- [ADP5520_KEY(3, 3)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .backlight = &adp5520_backlight_data,
- .leds = &adp5520_leds_data,
- .gpio = &adp5520_gpio_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
-static struct adp5588_gpio_platform_data adp5588_gpio_data = {
- .gpio_start = 50,
- .pullup_dis_mask = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
-#include <linux/platform_data/adp8870.h>
-static struct led_info adp8870_leds[] = {
- {
- .name = "adp8870-led7",
- .default_trigger = "none",
- .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
- },
-};
-
-
-static struct adp8870_backlight_platform_data adp8870_pdata = {
- .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
- ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
- .pwm_assign = 0, /* 1 = Enables PWM mode */
-
- .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8870_leds,
- .num_leds = ARRAY_SIZE(adp8870_leds),
- .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8870_FADE_T_600ms,
- .led_fade_out = ADP8870_FADE_T_600ms,
- .led_on_time = ADP8870_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
-#include <linux/platform_data/adp8860.h>
-static struct led_info adp8860_leds[] = {
- {
- .name = "adp8860-led7",
- .default_trigger = "none",
- .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms,
- },
-};
-
-static struct adp8860_backlight_platform_data adp8860_pdata = {
- .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 |
- ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */
-
- .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8860_leds,
- .num_leds = ARRAY_SIZE(adp8860_leds),
- .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8860_FADE_T_600ms,
- .led_fade_out = ADP8860_FADE_T_600ms,
- .led_on_time = ADP8860_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-static struct regulator_consumer_supply ad5398_consumer = {
- .supply = "current",
-};
-
-static struct regulator_init_data ad5398_regulator_data = {
- .constraints = {
- .name = "current range",
- .max_uA = 120000,
- .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &ad5398_consumer,
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
-static struct platform_device ad5398_virt_consumer_device = {
- .name = "reg-virt-consumer",
- .id = 0,
- .dev = {
- .platform_data = "current", /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data ad5398_bulk_data = {
- .supply = "current",
-};
-
-static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = {
- .name = "ad5398",
- .num_supplies = 1,
- .supplies = &ad5398_bulk_data,
-};
-
-static struct platform_device ad5398_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &ad5398_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7410_platform_data[2] = {
- IRQ_PG4, IRQF_TRIGGER_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7316_i2c_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#ifdef CONFIG_SND_SOC_AD193X_I2C
- {
- I2C_BOARD_INFO("ad1937", 0x04),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- I2C_BOARD_INFO("adav803", 0x10),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
- {
- I2C_BOARD_INFO("ad7142_captouch", 0x2C),
- .irq = IRQ_PG5,
- .platform_data = (void *)&ad7142_i2c_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7150)
- {
- I2C_BOARD_INFO("ad7150", 0x48),
- .irq = IRQ_PG5, /* fixme: use real interrupt number */
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7152)
- {
- I2C_BOARD_INFO("ad7152", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD774X)
- {
- I2C_BOARD_INFO("ad774x", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADE7854_I2C)
- {
- I2C_BOARD_INFO("ade7854", 0x38),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_LM75)
- {
- I2C_BOARD_INFO("adt75", 0x9),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
- {
- I2C_BOARD_INFO("adt7410", 0x48),
- /* CT critical temperature event. line 0 */
- .irq = IRQ_PG5,
- .platform_data = (void *)&adt7410_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7291)
- {
- I2C_BOARD_INFO("ad7291", 0x20),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
- {
- I2C_BOARD_INFO("adt7316", 0x48),
- .irq = IRQ_PG6,
- .platform_data = (void *)&adt7316_i2c_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PG6,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2F),
- .irq = IRQ_PG5,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-keys", 0x34),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5588_kpad_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PG3,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-gpio", 0x34),
- .platform_data = (void *)&adp5588_gpio_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- {
- I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
- {
- I2C_BOARD_INFO("adp8870", 0x2B),
- .platform_data = (void *)&adp8870_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371)
- {
- I2C_BOARD_INFO("adau1371", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361)
- {
- I2C_BOARD_INFO("adau1361", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701)
- {
- I2C_BOARD_INFO("adau1701", 0x34),
- },
-#endif
-#if IS_ENABLED(CONFIG_AD525X_DPOT)
- {
- I2C_BOARD_INFO("ad5258", 0x18),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
- {
- I2C_BOARD_INFO("ad5398", 0xC),
- .platform_data = (void *)&ad5398_regulator_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
- {
- I2C_BOARD_INFO("adp8860", 0x2A),
- .platform_data = (void *)&adp8860_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2e),
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
-
-#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-#define PATA_INT IRQ_PF5
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 1,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20314020,
- .end = 0x2031403F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2031401C,
- .end = 0x2031401F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 0,
-};
-/* CompactFlash Storage Card Memory Mapped Addressing
- * /REG = A11 = 1
- */
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20211800,
- .end = 0x20211807,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2021180E, /* Device Ctl */
- .end = 0x2021180E,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
-static struct platform_device bfin_eval_adav801_device = {
- .name = "bfin-eval-adav801",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
-#define REGULATOR_ADP122 "adp122"
-#define REGULATOR_ADP122_UV 2500000
-
-static struct regulator_consumer_supply adp122_consumers = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_init_data adp_switch_regulator_data = {
- .constraints = {
- .name = REGULATOR_ADP122,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .min_uV = REGULATOR_ADP122_UV,
- .max_uV = REGULATOR_ADP122_UV,
- .min_uA = 0,
- .max_uA = 300000,
- },
- .num_consumer_supplies = 1, /* only 1 */
- .consumer_supplies = &adp122_consumers,
-};
-
-static struct fixed_voltage_config adp_switch_pdata = {
- .supply_name = REGULATOR_ADP122,
- .microvolts = REGULATOR_ADP122_UV,
- .gpio = GPIO_PF2,
- .enable_high = 1,
- .enabled_at_boot = 0,
- .init_data = &adp_switch_regulator_data,
-};
-
-static struct platform_device adp_switch_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &adp_switch_pdata,
- },
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data adp122_bulk_data = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = {
- .name = REGULATOR_ADP122,
- .num_supplies = 1,
- .supplies = &adp122_bulk_data,
-};
-
-static struct platform_device adp122_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &adp122_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
-
-static struct resource iio_gpio_trigger_resources[] = {
- [0] = {
- .start = IRQ_PF5,
- .end = IRQ_PF5,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device iio_gpio_trigger = {
- .name = "iio_gpio_trigger",
- .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
- .resource = iio_gpio_trigger_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
-static struct platform_device bf5xx_adau1373_device = {
- .name = "bfin-eval-adau1373",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
-static struct platform_device bf5xx_adau1701_device = {
- .name = "bfin-eval-adau1701",
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
- &sl811_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
- &ad5398_virt_consumer_device,
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &ad5398_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
- &adp_switch_device,
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &adp122_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
- &iio_gpio_trigger,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
- &bf5xx_adau1373_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
- &bf5xx_adau1701_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
- &bfin_eval_adav801_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF6, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF6, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF6, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- bfin_plat_nand_init();
- adf702x_mac_init();
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-#define FLASH_MAC 0x203f0000
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
deleted file mode 100644
index ed309c9a62b6..000000000000
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ /dev/null
@@ -1,792 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM BF537";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4, GPIO_PF5 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init tcm_bf537_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(tcm_bf537_init);
-
-static struct platform_device *cm_bf537_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537_early_devices,
- ARRAY_SIZE(cm_bf537_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
deleted file mode 100644
index 5c62e99c9fac..000000000000
--- a/arch/blackfin/mach-bf537/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * This file contains the simple DMA Implementation for Blackfin
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
deleted file mode 100644
index 2bc70c5b9415..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC TX DMA Error After an Early Frame Abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO Input Latched on Wrong MDC Edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* UART Gets Disabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
-#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
deleted file mode 100644
index 8b291418ca32..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * System MMR Register and memory map for ADSP-BF537
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF537_H__
-#define __MACH_BF537_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF537
-#define CPU "BF537"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF536
-#define CPU "BF536"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF534
-#define CPU "BF534"
-#define CPUID 0x27c6
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF537_H__ */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
deleted file mode 100644
index baa096fc724a..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF537_FAMILY
-
-#include "bf537.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF534
-# include "defBF534.h"
-#endif
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "defBF537.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF534
-# include "cdefBF534.h"
-# endif
-# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "cdefBF537.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
deleted file mode 100644
index 563ede907336..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ /dev/null
@@ -1,1736 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
-
-/* For Mailboxes 16-31 */
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
-
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
-#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
-#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
-
-/* Mailbox Acceptance Masks */
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
-
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
-
-/* CAN Acceptance Mask Area Macros */
-#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
-#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
-#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
-#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
-
-/* Mailbox Registers */
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
-
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
-
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
-
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
-
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
-
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
-
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
-
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
-
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
-
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
-
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
-
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
-
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
-
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
-
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
-
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
-
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
-
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
-
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
-
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
-
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
-
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
-
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
-
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
-
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
-
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
-
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
-
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
-
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
-
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
-
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
-
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
-
-/* CAN Mailbox Area Macros */
-#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
-#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
-#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
-#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
-#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
-#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
-#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
-#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
-#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
-#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
-#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
-#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
-#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
-#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
-#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
-#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
-#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
-
-#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
deleted file mode 100644
index 19ec21ea150a..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534 */
-#include "cdefBF534.h"
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
-
-#endif /* _CDEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
deleted file mode 100644
index ef6a98cdfd44..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ /dev/null
@@ -1,1470 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
-
-/* CAN Configuration, Control, and Status Registers */
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-#endif /* _DEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
deleted file mode 100644
index e10332c9f660..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all MMR and bit defines common to BF534 */
-#include "defBF534.h"
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-/* EMAC_OPMODE Masks */
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h
deleted file mode 100644
index 5ae83b1183a1..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/dma.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0
-#define CH_EMAC_RX 1
-#define CH_EMAC_TX 2
-#define CH_SPORT0_RX 3
-#define CH_SPORT0_TX 4
-#define CH_SPORT1_RX 5
-#define CH_SPORT1_TX 6
-#define CH_SPI 7
-#define CH_UART0_RX 8
-#define CH_UART0_TX 9
-#define CH_UART1_RX 10
-#define CH_UART1_TX 11
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
deleted file mode 100644
index fba606b699c3..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
deleted file mode 100644
index b6ed8235bda4..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF537_IRQ_H_
-#define _BF537_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 32
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
-#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
-#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
-#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
-#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
-#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
-
-#define SYS_IRQS 39
-
-#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
-#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
-#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
-
-#define IRQ_PF0 50
-#define IRQ_PF1 51
-#define IRQ_PF2 52
-#define IRQ_PF3 53
-#define IRQ_PF4 54
-#define IRQ_PF5 55
-#define IRQ_PF6 56
-#define IRQ_PF7 57
-#define IRQ_PF8 58
-#define IRQ_PF9 59
-#define IRQ_PF10 60
-#define IRQ_PF11 61
-#define IRQ_PF12 62
-#define IRQ_PF13 63
-#define IRQ_PF14 64
-#define IRQ_PF15 65
-
-#define IRQ_PG0 66
-#define IRQ_PG1 67
-#define IRQ_PG2 68
-#define IRQ_PG3 69
-#define IRQ_PG4 70
-#define IRQ_PG5 71
-#define IRQ_PG6 72
-#define IRQ_PG7 73
-#define IRQ_PG8 74
-#define IRQ_PG9 75
-#define IRQ_PG10 76
-#define IRQ_PG11 77
-#define IRQ_PG12 78
-#define IRQ_PG13 79
-#define IRQ_PG14 80
-#define IRQ_PG15 81
-
-#define IRQ_PH0 82
-#define IRQ_PH1 83
-#define IRQ_PH2 84
-#define IRQ_PH3 85
-#define IRQ_PH4 86
-#define IRQ_PH5 87
-#define IRQ_PH6 88
-#define IRQ_PH7 89
-#define IRQ_PH8 90
-#define IRQ_PH9 91
-#define IRQ_PH10 92
-#define IRQ_PH11 93
-#define IRQ_PH12 94
-#define IRQ_PH13 95
-#define IRQ_PH14 96
-#define IRQ_PH15 97
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-
-#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
-#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
-#else
-#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
-#endif
-
-#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
-#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_WATCH 112 /* Watchdog Timer */
-#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
-#else
-#define IRQ_WATCH IRQ_PF_INTB_WATCH
-#endif
-
-#define NR_MACH_IRQS (113 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-#define init_mach_irq init_mach_irq
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
deleted file mode 100644
index 942f08de306b..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/mem_map.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * BF537 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF537 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-
-#ifdef CONFIG_BF537
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif /*CONFIG_BF537*/
-
-/* Memory Map for ADSP-BF536 processors */
-
-#ifdef CONFIG_BF536
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#define L1_CODE_LENGTH 0xC000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Memory Map for ADSP-BF534 processors */
-
-#ifdef CONFIG_BF534
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
deleted file mode 100644
index 71d9eaeb579e..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/portmux.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
-
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0 (GPIO_PH15 + 1)
-#define PORT_PJ1 (GPIO_PH15 + 2)
-#define PORT_PJ2 (GPIO_PH15 + 3)
-#define PORT_PJ3 (GPIO_PH15 + 4)
-#define PORT_PJ4 (GPIO_PH15 + 5)
-#define PORT_PJ5 (GPIO_PH15 + 6)
-#define PORT_PJ6 (GPIO_PH15 + 7)
-#define PORT_PJ7 (GPIO_PH15 + 8)
-#define PORT_PJ8 (GPIO_PH15 + 9)
-#define PORT_PJ9 (GPIO_PH15 + 10)
-#define PORT_PJ10 (GPIO_PH15 + 11)
-#define PORT_PJ11 (GPIO_PH15 + 12)
-
-#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
deleted file mode 100644
index a48baae4384d..000000000000
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-#include <asm/irq_handler.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/dpmc.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
- ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- SSYNC();
-}
-
-#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-#define UART_ERR_MASK (0x6) /* UART_IIR */
-#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
-
-static int error_int_mask;
-
-static void bf537_generic_error_mask_irq(struct irq_data *d)
-{
- error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
- if (!error_int_mask)
- bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bf537_generic_error_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
- error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bf537_generic_error_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_generic_error_mask_irq,
- .irq_mask = bf537_generic_error_mask_irq,
- .irq_unmask = bf537_generic_error_unmask_irq,
-};
-
-static void bf537_demux_error_irq(struct irq_desc *inta_desc)
-{
- int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
- irq = IRQ_MAC_ERROR;
- else
-#endif
- if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT0_ERROR;
- else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT1_ERROR;
- else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
- irq = IRQ_PPI_ERROR;
- else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
- irq = IRQ_CAN_ERROR;
- else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
- irq = IRQ_SPI_ERROR;
- else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART0_ERROR;
- else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART1_ERROR;
-
- if (irq) {
- if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
- bfin_handle_irq(irq);
- else {
-
- switch (irq) {
- case IRQ_PPI_ERROR:
- bfin_write_PPI_STATUS(PPI_ERR_MASK);
- break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- case IRQ_MAC_ERROR:
- bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
- break;
-#endif
- case IRQ_SPORT0_ERROR:
- bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_SPORT1_ERROR:
- bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_CAN_ERROR:
- bfin_write_CAN_GIS(CAN_ERR_MASK);
- break;
-
- case IRQ_SPI_ERROR:
- bfin_write_SPI_STAT(SPI_ERR_MASK);
- break;
-
- default:
- break;
- }
-
- pr_debug("IRQ %d:"
- " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
- __func__);
-
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_rx_int_mask;
-
-static void bf537_mac_rx_mask_irq(struct irq_data *d)
-{
- mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
- if (!mac_rx_int_mask)
- bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
-}
-
-static void bf537_mac_rx_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
- mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
-}
-
-static struct irq_chip bf537_mac_rx_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_mac_rx_mask_irq,
- .irq_mask = bf537_mac_rx_mask_irq,
- .irq_unmask = bf537_mac_rx_unmask_irq,
-};
-
-static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
-{
- if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
- bfin_handle_irq(IRQ_MAC_RX);
- else
- bfin_demux_gpio_irq(desc);
-}
-#endif
-
-void __init init_mach_irq(void)
-{
- int irq;
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
- /* Clear EMAC Interrupt Status bits so we can demux it later */
- bfin_write_EMAC_SYSTAT(-1);
-#endif
-
- irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
- for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
- irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
- handle_level_irq);
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
- irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
- irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
-
- irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-}
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig
deleted file mode 100644
index 4aea85e4e5cf..000000000000
--- a/arch/blackfin/mach-bf538/Kconfig
+++ /dev/null
@@ -1,166 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF538 || BF539)
-
-source "arch/blackfin/mach-bf538/boards/Kconfig"
-
-menu "BF538 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 12
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 12
-config IRQ_MEM0_DMA0
- int "IRQ_MEM0_DMA0"
- default 13
-config IRQ_MEM0_DMA1
- int "IRQ_MEM0_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_DMA1_ERROR
- int "IRQ_DMA1_ERROR"
- default 7
-config IRQ_SPORT2_ERROR
- int "IRQ_SPORT2_ERROR"
- default 7
-config IRQ_SPORT3_ERROR
- int "IRQ_SPORT3_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_SPI2_ERROR
- int "IRQ_SPI2_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_UART2_ERROR
- int "IRQ_UART2_ERROR"
- default 7
-config IRQ_CAN_ERROR
- int "IRQ_CAN_ERROR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_UART2_RX
- int "IRQ_UART2_RX"
- default 10
-config IRQ_UART2_TX
- int "IRQ_UART2_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MEM1_DMA0
- int "IRQ_MEM1_DMA0"
- default 13
-config IRQ_MEM1_DMA1
- int "IRQ_MEM1_DMA1"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
deleted file mode 100644
index c0be54f2cd2b..000000000000
--- a/arch/blackfin/mach-bf538/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf538/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-obj-$(CONFIG_GPIOLIB) += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/boards/Kconfig b/arch/blackfin/mach-bf538/boards/Kconfig
deleted file mode 100644
index 114cff440d43..000000000000
--- a/arch/blackfin/mach-bf538/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN538_EZKIT
- help
- Select your board!
-
-config BFIN538_EZKIT
- bool "BF538-EZKIT"
- help
- BF538-EZKIT-LITE board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf538/boards/Makefile b/arch/blackfin/mach-bf538/boards/Makefile
deleted file mode 100644
index 6143b320d585..000000000000
--- a/arch/blackfin/mach-bf538/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf538/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
deleted file mode 100644
index 1b6a52ad8a0e..000000000000
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF538-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif /* CONFIG_RTC_DRV_BFIN */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART0 */
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART1 */
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_THR,
- .end = UART2_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART2 */
-#endif /* CONFIG_SERIAL_BFIN */
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif /* CONFIG_BFIN_SIR0 */
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif /* CONFIG_BFIN_SIR1 */
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif /* CONFIG_BFIN_SIR2 */
-#endif /* CONFIG_BFIN_SIR */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
-#endif /* CONFIG_SERIAL_BFIN_SPORT */
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_CAN_BFIN */
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif /* CONFIG_SMC91X */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif /* CONFIG_MTD_M25P80 */
-#endif /* CONFIG_SPI_BFIN5XX */
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif /* CONFIG_TOUCHSCREEN_AD7879 */
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-
-static struct spi_board_info bf538_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif /* CONFIG_MTD_M25P80 */
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF3,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif /* CONFIG_SPI_SPIDEV */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (2) */
-static struct resource bfin_spi2_resource[] = {
- [0] = {
- .start = SPI2_REGBASE,
- .end = SPI2_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI2,
- .end = CH_SPI2,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI2,
- .end = IRQ_SPI2,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf538_spi_master_info0 = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info1 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info1, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info2 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master2 = {
- .name = "bfin-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi2_resource),
- .resource = bfin_spi2_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info2, /* Passed to driver */
- },
-};
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
-};
-#endif /* CONFIG_I2C_BLACKFIN_TWI */
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF538SBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_100, 150000000),
- VRPAIR(VLEV_100, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SMC91X)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-static struct platform_device *cm_bf538_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf538_spi_master0,
- &bf538_spi_master1,
- &bf538_spi_master2,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
- &i2c_bfin_twi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf538_spi_board_info,
- ARRAY_SIZE(bf538_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
deleted file mode 100644
index cce8ef5a5cec..000000000000
--- a/arch/blackfin/mach-bf538/dma.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_UART2_RX:
- ret_irq = IRQ_UART2_RX;
- break;
-
- case CH_UART2_TX:
- ret_irq = IRQ_UART2_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
-
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
-
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
-
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
-
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM0_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM0_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM1_DMA0;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM1_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
deleted file mode 100644
index 48c100228f2d..000000000000
--- a/arch/blackfin/mach-bf538/ext-gpio.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
- *
- * Copyright 2009-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#define DEFINE_REG(reg, off) \
-static inline u16 read_##reg(void __iomem *port) \
- { return bfin_read16(port + off); } \
-static inline void write_##reg(void __iomem *port, u16 v) \
- { bfin_write16(port + off, v); }
-
-DEFINE_REG(PORTIO, 0x00)
-DEFINE_REG(PORTIO_CLEAR, 0x10)
-DEFINE_REG(PORTIO_SET, 0x20)
-DEFINE_REG(PORTIO_DIR, 0x40)
-DEFINE_REG(PORTIO_INEN, 0x50)
-
-static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
-{
- switch (chip->base) {
- default: /* not really needed, but keeps gcc happy */
- case GPIO_PC0: return (void __iomem *)PORTCIO;
- case GPIO_PD0: return (void __iomem *)PORTDIO;
- case GPIO_PE0: return (void __iomem *)PORTEIO;
- }
-}
-
-static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- return !!(read_PORTIO(port) & (1u << gpio));
-}
-
-static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- if (value)
- write_PORTIO_SET(port, (1u << gpio));
- else
- write_PORTIO_CLEAR(port, (1u << gpio));
-}
-
-static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
- bf538_gpio_set_value(port, gpio, value);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_request(chip->base + gpio, chip->label);
-}
-
-static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_free(chip->base + gpio);
-}
-
-/* We don't set the irq fields as these banks cannot generate interrupts */
-
-static struct gpio_chip bf538_portc_chip = {
- .label = "GPIO-PC",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PC0,
- .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
-};
-
-static struct gpio_chip bf538_portd_chip = {
- .label = "GPIO-PD",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PD0,
- .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
-};
-
-static struct gpio_chip bf538_porte_chip = {
- .label = "GPIO-PE",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PE0,
- .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
-};
-
-static int __init bf538_extgpio_setup(void)
-{
- return gpiochip_add_data(&bf538_portc_chip, NULL) |
- gpiochip_add_data(&bf538_portd_chip, NULL) |
- gpiochip_add_data(&bf538_porte_chip, NULL);
-}
-arch_initcall(bf538_extgpio_setup);
-
-#ifdef CONFIG_PM
-static struct {
- u16 data, dir, inen;
-} gpio_bank_saved[3];
-
-static void __iomem * const port_bases[3] = {
- (void *)PORTCIO,
- (void *)PORTDIO,
- (void *)PORTEIO,
-};
-
-void bfin_special_gpio_pm_hibernate_suspend(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
- gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
- gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
- }
-}
-
-void bfin_special_gpio_pm_hibernate_restore(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
- write_PORTIO_SET(port_bases[i],
- gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
- write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
- }
-}
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
deleted file mode 100644
index eaac26973f6a..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 4
-# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
-#endif
-
-#if defined(__ADSPBF538__)
-# define ANOMALY_BF538 1
-#else
-# define ANOMALY_BF538 0
-#endif
-#if defined(__ADSPBF539__)
-# define ANOMALY_BF539 1
-#else
-# define ANOMALY_BF539 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (1)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (ANOMALY_BF538)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
-/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
-#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
-/* Hibernate Leakage Current Is Higher Than Specified */
-#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000294 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
-/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
-#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
-/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
-/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
-#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
-/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
-#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Specific GPIO Pins May Change State when Entering Hibernate */
-#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bf538.h b/arch/blackfin/mach-bf538/include/mach/bf538.h
deleted file mode 100644
index 0cf5bf8dab84..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/bf538.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF538_H__
-#define __MACH_BF538_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF538
-#define CPU "BF538"
-#define CPUID 0x27C4
-#endif
-#ifdef CONFIG_BF539
-#define CPU "BF539"
-#define CPUID 0x27C4 /* FXIME:? */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF538_H__ */
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
deleted file mode 100644
index c66e2760aad3..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 3
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
deleted file mode 100644
index 791d08400cf0..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF538_FAMILY
-
-#include "bf538.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF538
-# include "defBF538.h"
-#endif
-#ifdef CONFIG_BF539
-# include "defBF539.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF538
-# include "cdefBF538.h"
-# endif
-# ifdef CONFIG_BF539
-# include "cdefBF539.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
deleted file mode 100644
index f6a56792180b..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ /dev/null
@@ -1,1960 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF538_H
-#define _CDEF_BF538_H
-
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
-#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_IER() bfin_read16(UART2_IER)
-#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
-#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR)
-#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER)
-#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
-#define bfin_read_PORTCIO() bfin_read16(PORTCIO)
-#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
-#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR)
-#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
-#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET)
-#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
-#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE)
-#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
-#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR)
-#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
-#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN)
-#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
-#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER)
-#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
-#define bfin_read_PORTDIO() bfin_read16(PORTDIO)
-#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
-#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR)
-#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
-#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET)
-#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
-#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE)
-#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
-#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR)
-#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
-#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN)
-#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
-#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER)
-#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
-#define bfin_read_PORTEIO() bfin_read16(PORTEIO)
-#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
-#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR)
-#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
-#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET)
-#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
-#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE)
-#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
-#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR)
-#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
-#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN)
-#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
deleted file mode 100644
index acc15f3aba38..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF539_H
-#define _CDEF_BF539_H
-
-/* Include MMRs Common to BF538 */
-#include "cdefBF538.h"
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)
-#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1)
-#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-
-#endif /* _CDEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
deleted file mode 100644
index 876a77028001..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ /dev/null
@@ -1,1749 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF538_H
-#define _DEF_BF538_H
-
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
-#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
-#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
-#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI0_REGBASE SPI0_CTL
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
-
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-#define TWI0_REGBASE TWI0_CLKDIV
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE TWI0_CONTROL
-#define TWI0_INT_SRC TWI0_INT_STAT
-#define TWI0_INT_ENABLE TWI0_INT_MASK
-
-
-/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
-
-/* GPIO Port C Register Names */
-#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
-#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
-#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
-#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
-#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
-#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
-#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
-
-/* GPIO Port D Register Names */
-#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
-#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
-#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
-#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
-#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
-#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
-#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
-
-/* GPIO Port E Register Names */
-#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
-#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
-#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
-#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
-#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
-#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
-#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
-#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
-
-#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
-
-#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
-
-#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
-
-#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
-
-#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
-
-#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
-
-#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
-
-#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
-#define UART2_THR 0xFFC02100 /* Transmit Holding register */
-#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
-#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
-#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
-#define UART2_GCTL 0xFFC02124 /* Global Control Register */
-
-
-/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
-#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
-#define TWI1_REGBASE TWI1_CLKDIV
-
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE TWI1_CONTROL
-#define TWI1_INT_SRC TWI1_INT_STAT
-#define TWI1_INT_ENABLE TWI1_INT_MASK
-
-
-/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
-#define SPI1_REGBASE SPI1_CTL
-
-/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
-#define SPI2_REGBASE SPI2_CTL
-
-/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
-
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-/* the following is for backwards compatibility */
-#define CAN_CNF CAN_DEBUG
-
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
-#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
-#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
-#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
-#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
-#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
-#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
-#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
-#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ MDMA1_0_IRQ
-#define MDMA1_IRQ MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#ifdef _MISRA_RULES
-#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL 0xC000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ********** DMA CONTROLLER MASKS ***********************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x0040 /* DMA Channel Type Indicator */
-#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
-#define PMAP 0xF000 /* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
-#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
-#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
-#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
-#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
-#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
-
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001 /* Disable Timer 0 */
-#define TIMDIS1 0x0002 /* Disable Timer 1 */
-#define TIMDIS2 0x0004 /* Disable Timer 2 */
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001 /* Timer 0 Interrupt */
-#define TIMIL1 0x0002 /* Timer 1 Interrupt */
-#define TIMIL2 0x0004 /* Timer 2 Interrupt */
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x) (((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x) (((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P 0x0000 /* Enable CLKOUT */
-#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
deleted file mode 100644
index 199e871634b4..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF539_H
-#define _DEF_BF539_H
-
-#include "defBF538.h"
-
-/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
-
-#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
-#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
-
-#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
-
-#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
-
-#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
-
-#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
-
-#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
-
-#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
-
-#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
-
-#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
-#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
-#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
-
-#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
-#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
-#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
-
-#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
-#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
-#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
-
-#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
-#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
-#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
-
-#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
-#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
-#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
-
-#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
-#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
-#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
-
-#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
-#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
-#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
-
-#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
-#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
-#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
-
-#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
-
-#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
-
-#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
-
-#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
-
-#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
-#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
-#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
-
-#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h
deleted file mode 100644
index eb05cacbf4d3..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/dma.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI0 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_SPORT2_RX 8
-#define CH_SPORT2_TX 9
-#define CH_SPORT3_RX 10
-#define CH_SPORT3_TX 11
-#define CH_SPI1 14
-#define CH_SPI2 15
-#define CH_UART1_RX 16
-#define CH_UART1_TX 17
-#define CH_UART2_RX 18
-#define CH_UART2_TX 19
-
-#define CH_MEM_STREAM0_DEST 20
-#define CH_MEM_STREAM0_SRC 21
-#define CH_MEM_STREAM1_DEST 22
-#define CH_MEM_STREAM1_SRC 23
-#define CH_MEM_STREAM2_DEST 24
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM3_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-
-#define MAX_DMA_CHANNELS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
deleted file mode 100644
index 3561c7d8935b..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-#ifdef CONFIG_GPIOLIB
-/* We only use the special logic with GPIOLIB devices */
-#define BFIN_SPECIAL_GPIO_BANKS 3
-#endif
-
-#define GPIO_PF0 0 /* PF */
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PC0 16 /* PC */
-#define GPIO_PC1 17
-#define GPIO_PC4 20
-#define GPIO_PC5 21
-#define GPIO_PC6 22
-#define GPIO_PC7 23
-#define GPIO_PC8 24
-#define GPIO_PC9 25
-#define GPIO_PD0 32 /* PD */
-#define GPIO_PD1 33
-#define GPIO_PD2 34
-#define GPIO_PD3 35
-#define GPIO_PD4 36
-#define GPIO_PD5 37
-#define GPIO_PD6 38
-#define GPIO_PD7 39
-#define GPIO_PD8 40
-#define GPIO_PD9 41
-#define GPIO_PD10 42
-#define GPIO_PD11 43
-#define GPIO_PD12 44
-#define GPIO_PD13 45
-#define GPIO_PE0 48 /* PE */
-#define GPIO_PE1 49
-#define GPIO_PE2 50
-#define GPIO_PE3 51
-#define GPIO_PE4 52
-#define GPIO_PE5 53
-#define GPIO_PE6 54
-#define GPIO_PE7 55
-#define GPIO_PE8 56
-#define GPIO_PE9 57
-#define GPIO_PE10 58
-#define GPIO_PE11 59
-#define GPIO_PE12 60
-#define GPIO_PE13 61
-#define GPIO_PE14 62
-#define GPIO_PE15 63
-
-#define PORT_F GPIO_PF0
-#define PORT_C GPIO_PC0
-#define PORT_D GPIO_PD0
-#define PORT_E GPIO_PE0
-
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
deleted file mode 100644
index 07ca069d37cd..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF538_IRQ_H_
-#define _BF538_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
-#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
-#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
-#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
-#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
-#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
-#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
-#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
-#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
-#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
-#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
-#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_PPI_ERROR_POS 8
-#define IRQ_SPORT0_ERROR_POS 12
-#define IRQ_SPORT1_ERROR_POS 16
-#define IRQ_SPI0_ERROR_POS 20
-#define IRQ_UART0_ERROR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_PPI_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_PORTF_INTA_POS 12
-#define IRQ_PORTF_INTB_POS 16
-#define IRQ_MEM0_DMA0_POS 20
-#define IRQ_MEM0_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA1_ERROR_POS 0
-#define IRQ_SPORT2_ERROR_POS 4
-#define IRQ_SPORT3_ERROR_POS 8
-#define IRQ_SPI1_ERROR_POS 16
-#define IRQ_SPI2_ERROR_POS 20
-#define IRQ_UART1_ERROR_POS 24
-#define IRQ_UART2_ERROR_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_CAN_ERROR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_UART2_RX_POS 12
-#define IRQ_UART2_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MEM1_DMA0_POS 4
-#define IRQ_MEM1_DMA1_POS 8
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h
deleted file mode 100644
index aff00f453e9e..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/mem_map.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * BF538 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF538/9 processors */
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
deleted file mode 100644
index b773c5fdbc72..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES 64
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
-
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
-
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c
deleted file mode 100644
index 1fa793ced347..000000000000
--- a/arch/blackfin/mach-bf538/ints-priority.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
-
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
- ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
- ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
- ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
- ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
- ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
deleted file mode 100644
index 71c2a765af1d..000000000000
--- a/arch/blackfin/mach-bf548/Kconfig
+++ /dev/null
@@ -1,383 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF542
- def_bool y
- depends on BF542_std || BF542M
-config BF544
- def_bool y
- depends on BF544_std || BF544M
-config BF547
- def_bool y
- depends on BF547_std || BF547M
-config BF548
- def_bool y
- depends on BF548_std || BF548M
-config BF549
- def_bool y
- depends on BF549_std || BF549M
-
-config BF54xM
- def_bool y
- depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
-
-config BF54x
- def_bool y
- depends on (BF542 || BF544 || BF547 || BF548 || BF549)
-
-if (BF54x)
-
-source "arch/blackfin/mach-bf548/boards/Kconfig"
-
-menu "BF548 Specific Configuration"
-
-config DEB_DMA_URGENT
- bool "DMA has priority over core for ext. accesses"
- depends on BF54x
- default y
- help
- Treat any DEB1, DEB2 and DEB3 request as Urgent
-
-config BF548_ATAPI_ALTERNATIVE_PORT
- bool "BF548 ATAPI alternative port via GPIO"
- help
- BF548 ATAPI data and address PINs can be routed through
- async address or GPIO port F and G. Select y to route it
- to GPIO.
-
-choice
- prompt "UART2 DMA channel selection"
- depends on SERIAL_BFIN_UART2
- default UART2_DMA_RX_ON_DMA18
- help
- UART2 DMA channel selection
- RX -> DMA18
- TX -> DMA19
- or
- RX -> DMA13
- TX -> DMA14
-
-config UART2_DMA_RX_ON_DMA18
- bool "UART2 DMA RX -> DMA18 TX -> DMA19"
- help
- UART2 DMA channel assignment
- RX -> DMA18
- TX -> DMA19
- use SPORT2 default DMA channel
-
-config UART2_DMA_RX_ON_DMA13
- bool "UART2 DMA RX -> DMA13 TX -> DMA14"
- help
- UART2 DMA channel assignment
- RX -> DMA13
- TX -> DMA14
- use EPPI1 EPPI2 default DMA channel
-endchoice
-
-choice
- prompt "UART3 DMA channel selection"
- depends on SERIAL_BFIN_UART3
- default UART3_DMA_RX_ON_DMA20
- help
- UART3 DMA channel selection
- RX -> DMA20
- TX -> DMA21
- or
- RX -> DMA15
- TX -> DMA16
-
-config UART3_DMA_RX_ON_DMA20
- bool "UART3 DMA RX -> DMA20 TX -> DMA21"
- help
- UART3 DMA channel assignment
- RX -> DMA20
- TX -> DMA21
- use SPORT3 default DMA channel
-
-config UART3_DMA_RX_ON_DMA15
- bool "UART3 DMA RX -> DMA15 TX -> DMA16"
- help
- UART3 DMA channel assignment
- RX -> DMA15
- TX -> DMA16
- use PIXC default DMA channel
-
-endchoice
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMAC0_ERR
- int "IRQ_DMAC0_ERR"
- default 7
-config IRQ_EPPI0_ERR
- int "IRQ_EPPI0_ERR"
- default 7
-config IRQ_SPORT0_ERR
- int "IRQ_SPORT0_ERR"
- default 7
-config IRQ_SPORT1_ERR
- int "IRQ_SPORT1_ERR"
- default 7
-config IRQ_SPI0_ERR
- int "IRQ_SPI0_ERR"
- default 7
-config IRQ_UART0_ERR
- int "IRQ_UART0_ERR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_EPPI0
- int "IRQ_EPPI0"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER8
- int "IRQ_TIMER8"
- default 11
-config IRQ_TIMER9
- int "IRQ_TIMER9"
- default 11
-config IRQ_TIMER10
- int "IRQ_TIMER10"
- default 11
-config IRQ_PINT0
- int "IRQ_PINT0"
- default 12
-config IRQ_PINT1
- int "IRQ_PINT0"
- default 12
-config IRQ_MDMAS0
- int "IRQ_MDMAS0"
- default 13
-config IRQ_MDMAS1
- int "IRQ_DMDMAS1"
- default 13
-config IRQ_WATCHDOG
- int "IRQ_WATCHDOG"
- default 13
-config IRQ_DMAC1_ERR
- int "IRQ_DMAC1_ERR"
- default 7
-config IRQ_SPORT2_ERR
- int "IRQ_SPORT2_ERR"
- default 7
-config IRQ_SPORT3_ERR
- int "IRQ_SPORT3_ERR"
- default 7
-config IRQ_MXVR_DATA
- int "IRQ MXVR Data"
- default 7
-config IRQ_SPI1_ERR
- int "IRQ_SPI1_ERR"
- default 7
-config IRQ_SPI2_ERR
- int "IRQ_SPI2_ERR"
- default 7
-config IRQ_UART1_ERR
- int "IRQ_UART1_ERR"
- default 7
-config IRQ_UART2_ERR
- int "IRQ_UART2_ERR"
- default 7
-config IRQ_CAN0_ERR
- int "IRQ_CAN0_ERR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_EPPI1
- int "IRQ_EPPI1"
- default 9
-config IRQ_EPPI2
- int "IRQ_EPPI2"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_ATAPI_RX
- int "IRQ_ATAPI_RX"
- default 10
-config IRQ_ATAPI_TX
- int "IRQ_ATAPI_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN0_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN0_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MDMAS2
- int "IRQ_MDMAS2"
- default 13
-config IRQ_MDMAS3
- int "IRQ_DMMAS3"
- default 13
-config IRQ_MXVR_ERR
- int "IRQ_MXVR_ERR"
- default 11
-config IRQ_MXVR_MSG
- int "IRQ_MXVR_MSG"
- default 11
-config IRQ_MXVR_PKT
- int "IRQ_MXVR_PKT"
- default 11
-config IRQ_EPPI1_ERR
- int "IRQ_EPPI1_ERR"
- default 7
-config IRQ_EPPI2_ERR
- int "IRQ_EPPI2_ERR"
- default 7
-config IRQ_UART3_ERR
- int "IRQ_UART3_ERR"
- default 7
-config IRQ_HOST_ERR
- int "IRQ_HOST_ERR"
- default 7
-config IRQ_PIXC_ERR
- int "IRQ_PIXC_ERR"
- default 7
-config IRQ_NFC_ERR
- int "IRQ_NFC_ERR"
- default 7
-config IRQ_ATAPI_ERR
- int "IRQ_ATAPI_ERR"
- default 7
-config IRQ_CAN1_ERR
- int "IRQ_CAN1_ERR"
- default 7
-config IRQ_HS_DMA_ERR
- int "IRQ Handshake DMA Status"
- default 7
-config IRQ_PIXC_IN0
- int "IRQ PIXC IN0"
- default 8
-config IRQ_PIXC_IN1
- int "IRQ PIXC IN1"
- default 8
-config IRQ_PIXC_OUT
- int "IRQ PIXC OUT"
- default 8
-config IRQ_SDH
- int "IRQ SDH"
- default 8
-config IRQ_CNT
- int "IRQ CNT"
- default 8
-config IRQ_KEY
- int "IRQ KEY"
- default 8
-config IRQ_CAN1_RX
- int "IRQ CAN1 RX"
- default 11
-config IRQ_CAN1_TX
- int "IRQ_CAN1_TX"
- default 11
-config IRQ_SDH_MASK0
- int "IRQ_SDH_MASK0"
- default 11
-config IRQ_SDH_MASK1
- int "IRQ_SDH_MASK1"
- default 11
-config IRQ_USB_INT0
- int "IRQ USB INT0"
- default 11
-config IRQ_USB_INT1
- int "IRQ USB INT1"
- default 11
-config IRQ_USB_INT2
- int "IRQ USB INT2"
- default 11
-config IRQ_USB_DMA
- int "IRQ USB DMA"
- default 11
-config IRQ_OTPSEC
- int "IRQ OPTSEC"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 11
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 11
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 11
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 11
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 11
-config IRQ_PINT2
- int "IRQ_PIN2"
- default 11
-config IRQ_PINT3
- int "IRQ_PIN3"
- default 11
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
deleted file mode 100644
index 56994b675f9c..000000000000
--- a/arch/blackfin/mach-bf548/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf548/boards/Kconfig b/arch/blackfin/mach-bf548/boards/Kconfig
deleted file mode 100644
index e8ce579ae8f0..000000000000
--- a/arch/blackfin/mach-bf548/boards/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN548_EZKIT
- help
- Select your board!
-
-config BFIN548_EZKIT
- bool "BF548-EZKIT"
- help
- BFIN548-EZKIT board support.
-
-config BFIN548_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF548"
- depends on (BF548)
- help
- CM-BF548 support for DEV-Board.
-
-endchoice
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
deleted file mode 100644
index 319ef54c4221..000000000000
--- a/arch/blackfin/mach-bf548/boards/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf548/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN548_BLUETECHNIX_CM) += cm_bf548.o
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
deleted file mode 100644
index 120c9941c242..000000000000
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ /dev/null
@@ -1,1268 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF548";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 480,
- .height = 272,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE6,
- .end = IRQ_PE6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PH6,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = 4 * 1024 * 1024,
- .size = (256 - 4) * 1024 * 1024,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &para_flash_data,
- },
- .num_resources = 1,
- .resource = &para_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bf54x_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PJ11,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
-},
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf548_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &para_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-};
-
-static int __init cm_bf548_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf54x_spi_board_info,
- ARRAY_SIZE(bf54x_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(cm_bf548_init);
-
-static struct platform_device *cm_bf548_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf548_early_devices,
- ARRAY_SIZE(cm_bf548_early_devices));
-}
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
deleted file mode 100644
index 3cdd4835a9f7..000000000000
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ /dev/null
@@ -1,2199 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF548-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 95,
- .height = 54,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static const unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTE_FER,
- .end = PORTE_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTH_FER,
- .end = PORTH_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE8,
- .end = IRQ_PE8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PE7,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-static unsigned short bfin_can1_peripherals[] = {
- P_CAN1_RX, P_CAN1_TX, 0
-};
-
-static struct resource bfin_can1_resources[] = {
- {
- .start = 0xFFC03200,
- .end = 0xFFC037FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN1_RX,
- .end = IRQ_CAN1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_TX,
- .end = IRQ_CAN1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_ERROR,
- .end = IRQ_CAN1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can1_device = {
- .name = "bfin_can",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_can1_resources),
- .resource = bfin_can1_resources,
- .dev = {
- .platform_data = &bfin_can1_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x8000 * 3,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x8000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x21ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_gpio_base = GPIO_PA0, /* Optional */
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_gpio_base = GPIO_PB0,
- .port_pin_base = GPIO_PB0,
- .port_width = 15,
- .pint_id = 0,
- .pint_assign = true,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_gpio_base = GPIO_PC0,
- .port_pin_base = GPIO_PC0,
- .port_width = 14,
- .pint_id = 2,
- .pint_assign = true,
- .pint_map = 0,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_gpio_base = GPIO_PD0,
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_gpio_base = GPIO_PE0,
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = true,
- .pint_map = 2,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_gpio_base = GPIO_PF0,
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 3,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_gpio_base = GPIO_PG0,
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gph_resources[] = {
- {
- .start = PORTH_FER,
- .end = PORTH_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PH0,
- .end = IRQ_PH0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
- .port_gpio_base = GPIO_PH0,
- .port_pin_base = GPIO_PH0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gph_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 7,
- .num_resources = ARRAY_SIZE(bfin_gph_resources),
- .resource = bfin_gph_resources,
- .dev = {
- .platform_data = &bfin_gph_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpi_resources[] = {
- {
- .start = PORTI_FER,
- .end = PORTI_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PI0,
- .end = IRQ_PI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
- .port_gpio_base = GPIO_PI0,
- .port_pin_base = GPIO_PI0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpi_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 8,
- .num_resources = ARRAY_SIZE(bfin_gpi_resources),
- .resource = bfin_gpi_resources,
- .dev = {
- .platform_data = &bfin_gpi_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpj_resources[] = {
- {
- .start = PORTJ_FER,
- .end = PORTJ_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PJ0,
- .end = IRQ_PJ0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
- .port_gpio_base = GPIO_PJ0,
- .port_pin_base = GPIO_PJ0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpj_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 9,
- .num_resources = ARRAY_SIZE(bfin_gpj_resources),
- .resource = bfin_gpj_resources,
- .dev = {
- .platform_data = &bfin_gpj_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI,
- .dma_ch = CH_EPPI1,
- .irq_err = IRQ_EPPI1_ERROR,
- .base = (void __iomem *)EPPI1_STATUS,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PG6;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF548",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
- .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */
- .blank_clocks = 8, /* 8 clocks as SAV and EAV */
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 212,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
- SPORT_REQ(2),
- SPORT_REQ(3),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
- {
- .pin_req = &bfin_snd_pin[2][0],
- },
- {
- .pin_req = &bfin_snd_pin[3][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
- BFIN_SND_RES(2),
- BFIN_SND_RES(3),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
-static struct platform_device bfin_ad1980_codec_device = {
- .name = "ad1980",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
- &bfin_gph_device,
- &bfin_gpi_device,
- &bfin_gpj_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
- &bfin_can1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
- &bfin_ad1980_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "4bit", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "8bit", "pinctrl-adi2.0", "keys_8x8grp", "keys"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-#endif
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
deleted file mode 100644
index 69ead33cbf91..000000000000
--- a/arch/blackfin/mach-bf548/dma.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) DMA21_NEXT_DESC_PTR,
- (struct dma_register *) DMA22_NEXT_DESC_PTR,
- (struct dma_register *) DMA23_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0:
- ret_irq = IRQ_EPPI0;
- break;
- case CH_EPPI1:
- ret_irq = IRQ_EPPI1;
- break;
- case CH_EPPI2:
- ret_irq = IRQ_EPPI2;
- break;
- case CH_PIXC_IMAGE:
- ret_irq = IRQ_PIXC_IN0;
- break;
- case CH_PIXC_OVERLAY:
- ret_irq = IRQ_PIXC_IN1;
- break;
- case CH_PIXC_OUTPUT:
- ret_irq = IRQ_PIXC_OUT;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
- case CH_SDH:
- ret_irq = IRQ_SDH;
- break;
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
deleted file mode 100644
index 098fad63e03b..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.0 or 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF548 silicon version 0.0, or 0.1
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* FIFO Boot Mode Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-/*
- * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
- * shows that the fix itself does not cover all cases.
- */
-#define ANOMALY_05000353 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
-/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
-#define ANOMALY_05000379 (1)
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
-/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
-#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
-#define ANOMALY_05000446 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
-#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
-/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
-#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
-/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
-/* USB TX DMA Hang */
-#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
-#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
-#define ANOMALY_05000500 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
-#define ANOMALY_05000502 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
deleted file mode 100644
index 751e5e11ecf8..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF548_H__
-#define __MACH_BF548_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF542)
-# define CPU "BF542"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF544)
-# define CPU "BF544"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF547)
-# define CPU "BF547"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF548)
-# define CPU "BF548"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF549)
-# define CPU "BF549"
-# define CPUID 0x27de
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
deleted file mode 100644
index 8821efe57fbc..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BF54X_LQ043_H
-#define BF54X_LQ043_H
-
-struct bfin_bf54xfb_val {
- unsigned int defval;
- unsigned int min;
- unsigned int max;
-};
-
-struct bfin_bf54xfb_mach_info {
- unsigned char fixed_syncs; /* do not update sync/border */
-
- /* LCD types */
- int type;
-
- /* Screen size */
- int width;
- int height;
-
- /* Screen info */
- struct bfin_bf54xfb_val xres;
- struct bfin_bf54xfb_val yres;
- struct bfin_bf54xfb_val bpp;
-
- /* GPIOs */
- unsigned short disp;
-
-};
-
-#endif /* BF54X_LQ043_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
deleted file mode 100644
index 49338ae299ab..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_KPAD_H
-#define _BFIN_KPAD_H
-
-struct bfin_kpad_platform_data {
- int rows;
- int cols;
- const unsigned int *keymap;
- unsigned short keymapsize;
- unsigned short repeat;
- u32 debounce_time; /* in ns */
- u32 coldrive_time; /* in ns */
- u32 keyup_test_interval; /* in ms */
-};
-
-#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
deleted file mode 100644
index a77109f99720..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 4
-
-#define BFIN_UART_BF54X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
deleted file mode 100644
index 72da721a77f5..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf548.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF542
-# include "defBF542.h"
-#endif
-#ifdef CONFIG_BF544
-# include "defBF544.h"
-#endif
-#ifdef CONFIG_BF547
-# include "defBF547.h"
-#endif
-#ifdef CONFIG_BF548
-# include "defBF548.h"
-#endif
-#ifdef CONFIG_BF549
-# include "defBF549.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF542
-# include "cdefBF542.h"
-# endif
-# ifdef CONFIG_BF544
-# include "cdefBF544.h"
-# endif
-# ifdef CONFIG_BF547
-# include "cdefBF547.h"
-# endif
-# ifdef CONFIG_BF548
-# include "cdefBF548.h"
-# endif
-# ifdef CONFIG_BF549
-# include "cdefBF549.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
deleted file mode 100644
index 916347901d5a..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-#endif /* _CDEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
deleted file mode 100644
index 33ec8102ceda..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ /dev/null
@@ -1,913 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
deleted file mode 100644
index be83f645bba8..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ /dev/null
@@ -1,796 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF547_H
-#define _CDEF_BF547_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
deleted file mode 100644
index bae67a65633e..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "cdefBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
deleted file mode 100644
index 002136ad5a44..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "cdefBF547.h"
-
-/* MXVR Registers */
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-
-/* MXVR Allocation Table Registers */
-
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-
-/* MXVR Channel Assign Registers */
-
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-
-/* MXVR DMA0 Registers */
-
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-
-/* MXVR DMA1 Registers */
-
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-
-/* MXVR DMA2 Registers */
-
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-
-/* MXVR DMA3 Registers */
-
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-
-/* MXVR DMA4 Registers */
-
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-
-/* MXVR DMA5 Registers */
-
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-
-/* MXVR DMA6 Registers */
-
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-
-/* MXVR DMA7 Registers */
-
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-
-/* MXVR Asynch Packet Registers */
-
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-
-/* MXVR Frame Counter Registers */
-
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-
-/* MXVR Routing Table Registers */
-
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
-
-#endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
deleted file mode 100644
index 50c89c8052f3..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ /dev/null
@@ -1,2633 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-/* SIC Registers */
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-
-/* Watchdog Timer Registers */
-
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-
-/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPORT1 Registers */
-
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-/* Asynchronous Memory Control Registers */
-
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-
-/* DDR Memory Control Registers */
-
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-
-/* DMAC0 Registers */
-
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-
-/* MDMA Stream 0 Registers */
-
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers */
-
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-
-/* EPPI1 Registers */
-
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-
-/* Port B Registers */
-
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-
-/* Port C Registers */
-
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-
-/* Port D Registers */
-
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-
-/* Port E Registers */
-
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-
-/* Port F Registers */
-
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-
-/* Port G Registers */
-
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-
-/* Port H Registers */
-
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-
-/* Port I Registers */
-
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-
-/* Port J Registers */
-
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-
-/* PWM Timer Registers */
-
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-/* Timer Groubfin_read_() of 8 */
-
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-
-/* DMAC1 Registers */
-
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-
-/* DMA Channel 21 Registers */
-
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-
-/* DMA Channel 22 Registers */
-
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-
-/* DMA Channel 23 Registers */
-
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-
-/* MDMA Stream 2 Registers */
-
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers */
-
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-
-/* SPORT2 Registers */
-
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-
-/* SPORT3 Registers */
-
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-
-/* EPPI2 Registers */
-
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* UART3 Registers */
-
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* DMA Peribfin_read_()heral Mux Register */
-
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
-
-#endif /* _CDEF_BF54X_H */
-
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
deleted file mode 100644
index ae4b889e3606..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
deleted file mode 100644
index 018ebfc27f5a..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-#endif /* _DEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
deleted file mode 100644
index 7cc7928a3c73..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ /dev/null
@@ -1,1034 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF547_H
-#define _DEF_BF547_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
-#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xffc02108 /* Global Control Register */
-#define UART2_LCR 0xffc0210c /* Line Control Register */
-#define UART2_MCR 0xffc02110 /* Modem Control Register */
-#define UART2_LSR 0xffc02114 /* Line Status Register */
-#define UART2_MSR 0xffc02118 /* Modem Status Register */
-#define UART2_SCR 0xffc0211c /* Scratch Register */
-#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
-#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2 Registers */
-
-#define SPI2_REGBASE 0xffc02400
-#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
deleted file mode 100644
index 27f29481e283..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "defBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
deleted file mode 100644
index ac569fc12972..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "defBF547.h"
-
-/* MXVR Registers */
-
-#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
-#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
-#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
-#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
-#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
-#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
-#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
-#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
-#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
-#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
-#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
-#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
-#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
-#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
-#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
-#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
-#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
-#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
-#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
-#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
-#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
-#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
-#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
-#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
-#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
-#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
-#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
-#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
-
-#endif /* _DEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
deleted file mode 100644
index 8f6e1925779d..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ /dev/null
@@ -1,2294 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define PLL_CTL 0xffc00000 /* PLL Control Register */
-#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
-#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xffc0000c /* PLL Status Register */
-#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define SWRST 0xffc00100 /* Software Reset Register */
-#define SYSCR 0xffc00104 /* System Configuration register */
-
-/* SIC Registers */
-
-#define SIC_RVECT 0xffc00108
-#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define RTC_STAT 0xffc00300 /* RTC Status Register */
-#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
-#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xffc00408 /* Global Control Register */
-#define UART0_LCR 0xffc0040c /* Line Control Register */
-#define UART0_MCR 0xffc00410 /* Modem Control Register */
-#define UART0_LSR 0xffc00414 /* Line Status Register */
-#define UART0_MSR 0xffc00418 /* Modem Status Register */
-#define UART0_SCR 0xffc0041c /* Scratch Register */
-#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xffc00428 /* Transmit Hold Register */
-#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define SPI0_REGBASE 0xffc00500
-#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define TWI0_REGBASE 0xffc00700
-#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
-#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define PORTA_FER 0xffc014c0 /* Function Enable Register */
-#define PORTA 0xffc014c4 /* GPIO Data Register */
-#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define PORTB_FER 0xffc014e0 /* Function Enable Register */
-#define PORTB 0xffc014e4 /* GPIO Data Register */
-#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define PORTC_FER 0xffc01500 /* Function Enable Register */
-#define PORTC 0xffc01504 /* GPIO Data Register */
-#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define PORTD_FER 0xffc01520 /* Function Enable Register */
-#define PORTD 0xffc01524 /* GPIO Data Register */
-#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define PORTE_FER 0xffc01540 /* Function Enable Register */
-#define PORTE 0xffc01544 /* GPIO Data Register */
-#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define PORTF_FER 0xffc01560 /* Function Enable Register */
-#define PORTF 0xffc01564 /* GPIO Data Register */
-#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define PORTG_FER 0xffc01580 /* Function Enable Register */
-#define PORTG 0xffc01584 /* GPIO Data Register */
-#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define PORTH_FER 0xffc015a0 /* Function Enable Register */
-#define PORTH 0xffc015a4 /* GPIO Data Register */
-#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define PORTI_FER 0xffc015c0 /* Function Enable Register */
-#define PORTI 0xffc015c4 /* GPIO Data Register */
-#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
-#define PORTJ 0xffc015e4 /* GPIO Data Register */
-#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xffc02008 /* Global Control Register */
-#define UART1_LCR 0xffc0200c /* Line Control Register */
-#define UART1_MCR 0xffc02010 /* Modem Control Register */
-#define UART1_LSR 0xffc02014 /* Line Status Register */
-#define UART1_MSR 0xffc02018 /* Modem Status Register */
-#define UART1_SCR 0xffc0201c /* Scratch Register */
-#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xffc02028 /* Transmit Hold Register */
-#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define SPI1_REGBASE 0xffc02300
-#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
-#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
-#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03b00 /* NAND Control Register */
-#define NFC_STAT 0xffc03b04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
-#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
-#define NFC_CMD 0xffc03b44 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc04200 /* Configuration Register */
-#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc04208 /* Status Register */
-#define CNT_COMMAND 0xffc0420c /* Command Register */
-#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
-#define CNT_COUNTER 0xffc04214 /* Counter Register */
-#define CNT_MAX 0xffc04218 /* Maximal Count Register */
-#define CNT_MIN 0xffc0421c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc04324 /* Secure Control */
-#define SECURE_STATUS 0xffc04328 /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* Bit masks for SIC_IAR0 */
-
-#define PLL_WAKEUP 0x1 /* PLL Wakeup */
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
-#define EPPI0_ERR 0x4 /* EPPI0 Error */
-#define SPORT0_ERR 0x8 /* SPORT0 Error */
-#define SPORT1_ERR 0x10 /* SPORT1 Error */
-#define SPI0_ERR 0x20 /* SPI0 Error */
-#define UART0_ERR 0x40 /* UART0 Error */
-#define RTC 0x80 /* Real-Time Clock */
-#define DMA12 0x100 /* DMA Channel 12 */
-#define DMA0 0x200 /* DMA Channel 0 */
-#define DMA1 0x400 /* DMA Channel 1 */
-#define DMA2 0x800 /* DMA Channel 2 */
-#define DMA3 0x1000 /* DMA Channel 3 */
-#define DMA4 0x2000 /* DMA Channel 4 */
-#define DMA6 0x4000 /* DMA Channel 6 */
-#define DMA7 0x8000 /* DMA Channel 7 */
-#define PINT0 0x80000 /* Pin Interrupt 0 */
-#define PINT1 0x100000 /* Pin Interrupt 1 */
-#define MDMA0 0x200000 /* Memory DMA Stream 0 */
-#define MDMA1 0x400000 /* Memory DMA Stream 1 */
-#define WDOG 0x800000 /* Watchdog Timer */
-#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
-#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
-#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
-#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
-#define SPI1_ERR 0x10000000 /* SPI1 Error */
-#define SPI2_ERR 0x20000000 /* SPI2 Error */
-#define UART1_ERR 0x40000000 /* UART1 Error */
-#define UART2_ERR 0x80000000 /* UART2 Error */
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define CAN0_ERR 0x1 /* CAN0 Error */
-#define DMA18 0x2 /* DMA Channel 18 */
-#define DMA19 0x4 /* DMA Channel 19 */
-#define DMA20 0x8 /* DMA Channel 20 */
-#define DMA21 0x10 /* DMA Channel 21 */
-#define DMA13 0x20 /* DMA Channel 13 */
-#define DMA14 0x40 /* DMA Channel 14 */
-#define DMA5 0x80 /* DMA Channel 5 */
-#define DMA23 0x100 /* DMA Channel 23 */
-#define DMA8 0x200 /* DMA Channel 8 */
-#define DMA9 0x400 /* DMA Channel 9 */
-#define DMA10 0x800 /* DMA Channel 10 */
-#define DMA11 0x1000 /* DMA Channel 11 */
-#define TWI0 0x2000 /* TWI0 */
-#define TWI1 0x4000 /* TWI1 */
-#define CAN0_RX 0x8000 /* CAN0 Receive */
-#define CAN0_TX 0x10000 /* CAN0 Transmit */
-#define MDMA2 0x20000 /* Memory DMA Stream 0 */
-#define MDMA3 0x40000 /* Memory DMA Stream 1 */
-#define MXVR_STAT 0x80000 /* MXVR Status */
-#define MXVR_CM 0x100000 /* MXVR Control Message */
-#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
-#define EPPI1_ERR 0x400000 /* EPPI1 Error */
-#define EPPI2_ERR 0x800000 /* EPPI2 Error */
-#define UART3_ERR 0x1000000 /* UART3 Error */
-#define HOST_ERR 0x2000000 /* Host DMA Port Error */
-#define USB_ERR 0x4000000 /* USB Error */
-#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
-#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
-#define ATAPI_ERR 0x20000000 /* ATAPI Error */
-#define CAN1_ERR 0x40000000 /* CAN1 Error */
-#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
-#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
-#define DMAR0 0x80000000 /* DMAR0 Block */
-#define DMAR1 0x80000000 /* DMAR1 Block */
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define DMA15 0x1 /* DMA Channel 15 */
-#define DMA16 0x2 /* DMA Channel 16 */
-#define DMA17 0x4 /* DMA Channel 17 */
-#define DMA22 0x8 /* DMA Channel 22 */
-#define CNT 0x10 /* Counter */
-#define KEY 0x20 /* Keypad */
-#define CAN1_RX 0x40 /* CAN1 Receive */
-#define CAN1_TX 0x80 /* CAN1 Transmit */
-#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
-#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
-#define USB_EINT 0x400 /* USB Exception */
-#define USB_INT0 0x800 /* USB Interrupt 0 */
-#define USB_INT1 0x1000 /* USB Interrupt 1 */
-#define USB_INT2 0x2000 /* USB Interrupt 2 */
-#define USB_DMAINT 0x4000 /* USB DMA */
-#define OTPSEC 0x8000 /* OTP Access Complete */
-#define TIMER0 0x400000 /* Timer 0 */
-#define TIMER1 0x800000 /* Timer 1 */
-#define TIMER2 0x1000000 /* Timer 2 */
-#define TIMER3 0x2000000 /* Timer 3 */
-#define TIMER4 0x4000000 /* Timer 4 */
-#define TIMER5 0x8000000 /* Timer 5 */
-#define TIMER6 0x10000000 /* Timer 6 */
-#define TIMER7 0x20000000 /* Timer 7 */
-#define PINT2 0x40000000 /* Pin Interrupt 2 */
-#define PINT3 0x80000000 /* Pin Interrupt 3 */
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define CTYPE 0x40 /* DMA Channel Type */
-#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TC_PER */
-
-#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
-#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
-#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
-#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TC_CNT */
-
-#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
-#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
-#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
-#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
-#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
-#define B0TT 0xc /* Bank 0 transition time */
-#define B0ST 0x30 /* Bank 0 Setup time */
-#define B0HT 0xc0 /* Bank 0 Hold time */
-#define B0RAT 0xf00 /* Bank 0 Read access time */
-#define B0WAT 0xf000 /* Bank 0 write access time */
-#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
-#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
-#define B1TT 0xc0000 /* Bank 1 transition time */
-#define B1ST 0x300000 /* Bank 1 Setup time */
-#define B1HT 0xc00000 /* Bank 1 Hold time */
-#define B1RAT 0xf000000 /* Bank 1 Read access time */
-#define B1WAT 0xf0000000 /* Bank 1 write access time */
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
-#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
-#define B2TT 0xc /* Bank 2 transition time */
-#define B2ST 0x30 /* Bank 2 Setup time */
-#define B2HT 0xc0 /* Bank 2 Hold time */
-#define B2RAT 0xf00 /* Bank 2 Read access time */
-#define B2WAT 0xf000 /* Bank 2 write access time */
-#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
-#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
-#define B3TT 0xc0000 /* Bank 3 transition time */
-#define B3ST 0x300000 /* Bank 3 Setup time */
-#define B3HT 0xc00000 /* Bank 3 Hold time */
-#define B3RAT 0xf000000 /* Bank 3 Read access time */
-#define B3WAT 0xf0000000 /* Bank 3 write access time */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
-#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
-#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
-#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
-#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
-#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
-#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define TESTSETLOCK 0x1 /* Test set lock */
-#define BCLK 0x6 /* Burst clock frequency */
-#define PGWS 0x38 /* Page wait states */
-#define PGSZ 0x40 /* Page size */
-#define RDDL 0x380 /* Read data delay */
-
-/* Bit masks for EBIU_ARBSTAT */
-
-#define ARBSTAT 0x1 /* Arbitration status */
-#define BGSTAT 0x2 /* Bus grant status */
-
-/* Bit masks for EBIU_DDRCTL0 */
-
-#define TREFI 0x3fff /* Refresh Interval */
-#define TRFC 0x3c000 /* Auto-refresh command period */
-#define TRP 0x3c0000 /* Pre charge-to-active command period */
-#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
-#define TRC 0x3c000000 /* Active-to-active time */
-#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
-#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
-#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
-#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
-#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define TRCD 0xf /* Active-to-Read/write delay */
-#define TMRD 0xf0 /* Mode register set to active */
-#define TWR 0x300 /* Write Recovery time */
-#define DDRDATWIDTH 0x3000 /* DDR data width */
-#define EXTBANKS 0xc000 /* External banks */
-#define DDRDEVWIDTH 0x30000 /* DDR device width */
-#define DDRDEVSIZE 0xc0000 /* DDR device size */
-#define TWTR 0xf0000000 /* Write-to-read delay */
-#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
-#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
-#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
-#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
-#define DDR_DATWIDTH 0x2000 /* DDR data width */
-#define EXTBANK_1 0 /* 1 external bank */
-#define EXTBANK_2 0x4000 /* 2 external banks */
-#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
-#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
-#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
-#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
-#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
-#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
-#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
-
-/* Bit masks for EBIU_DDRCTL2 */
-
-#define BURSTLENGTH 0x7 /* Burst length */
-#define CASLATENCY 0x70 /* CAS latency */
-#define DLLRESET 0x100 /* DLL Reset */
-#define REGE 0x1000 /* Register mode enable */
-#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
-#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
-#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
-#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
-
-/* Bit masks for EBIU_DDRCTL3 */
-
-#define PASR 0x7 /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-
-#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
-#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
-#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
-#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
-#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define DEB1_ERROR 0x1 /* DEB1 Error */
-#define DEB2_ERROR 0x2 /* DEB2 Error */
-#define DEB3_ERROR 0x4 /* DEB3 Error */
-#define CORE_ERROR 0x8 /* Core error */
-#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
-#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
-#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
-#define CORE_MERROR 0x80 /* Core Error (2nd) */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define DDRSRESET 0x1 /* DDR soft reset */
-#define PFTCHSRESET 0x4 /* DDR prefetch reset */
-#define SRREQ 0x8 /* Self-refresh request */
-#define SRACK 0x10 /* Self-refresh acknowledge */
-#define MDDRENABLE 0x20 /* Mobile DDR enable */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define B0WCENABLE 0x1 /* Bank 0 write count enable */
-#define B1WCENABLE 0x2 /* Bank 1 write count enable */
-#define B2WCENABLE 0x4 /* Bank 2 write count enable */
-#define B3WCENABLE 0x8 /* Bank 3 write count enable */
-#define B4WCENABLE 0x10 /* Bank 4 write count enable */
-#define B5WCENABLE 0x20 /* Bank 5 write count enable */
-#define B6WCENABLE 0x40 /* Bank 6 write count enable */
-#define B7WCENABLE 0x80 /* Bank 7 write count enable */
-#define B0RCENABLE 0x100 /* Bank 0 read count enable */
-#define B1RCENABLE 0x200 /* Bank 1 read count enable */
-#define B2RCENABLE 0x400 /* Bank 2 read count enable */
-#define B3RCENABLE 0x800 /* Bank 3 read count enable */
-#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
-#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
-#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
-#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
-#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
-#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
-#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
-#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
-#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
-#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
-#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
-#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define CB0WCOUNT 0x1 /* Clear write count 0 */
-#define CB1WCOUNT 0x2 /* Clear write count 1 */
-#define CB2WCOUNT 0x4 /* Clear write count 2 */
-#define CB3WCOUNT 0x8 /* Clear write count 3 */
-#define CB4WCOUNT 0x10 /* Clear write count 4 */
-#define CB5WCOUNT 0x20 /* Clear write count 5 */
-#define CB6WCOUNT 0x40 /* Clear write count 6 */
-#define CB7WCOUNT 0x80 /* Clear write count 7 */
-#define CBRCOUNT 0x100 /* Clear read count 0 */
-#define CB1RCOUNT 0x200 /* Clear read count 1 */
-#define CB2RCOUNT 0x400 /* Clear read count 2 */
-#define CB3RCOUNT 0x800 /* Clear read count 3 */
-#define CB4RCOUNT 0x1000 /* Clear read count 4 */
-#define CB5RCOUNT 0x2000 /* Clear read count 5 */
-#define CB6RCOUNT 0x4000 /* Clear read count 6 */
-#define CB7RCOUNT 0x8000 /* Clear read count 7 */
-#define CRACOUNT 0x10000 /* Clear row activation count */
-#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
-#define CARCOUNT 0x40000 /* Clear auto-refresh count */
-#define CG0COUNT 0x100000 /* Clear grant count 0 */
-#define CG1COUNT 0x200000 /* Clear grant count 1 */
-#define CG2COUNT 0x400000 /* Clear grant count 2 */
-#define CG3COUNT 0x800000 /* Clear grant count 3 */
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define Px0 0x1 /* GPIO 0 */
-#define Px1 0x2 /* GPIO 1 */
-#define Px2 0x4 /* GPIO 2 */
-#define Px3 0x8 /* GPIO 3 */
-#define Px4 0x10 /* GPIO 4 */
-#define Px5 0x20 /* GPIO 5 */
-#define Px6 0x40 /* GPIO 6 */
-#define Px7 0x80 /* GPIO 7 */
-#define Px8 0x100 /* GPIO 8 */
-#define Px9 0x200 /* GPIO 9 */
-#define Px10 0x400 /* GPIO 10 */
-#define Px11 0x800 /* GPIO 11 */
-#define Px12 0x1000 /* GPIO 12 */
-#define Px13 0x2000 /* GPIO 13 */
-#define Px14 0x4000 /* GPIO 14 */
-#define Px15 0x8000 /* GPIO 15 */
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define PxM0 0x3 /* GPIO Mux 0 */
-#define PxM1 0xc /* GPIO Mux 1 */
-#define PxM2 0x30 /* GPIO Mux 2 */
-#define PxM3 0xc0 /* GPIO Mux 3 */
-#define PxM4 0x300 /* GPIO Mux 4 */
-#define PxM5 0xc00 /* GPIO Mux 5 */
-#define PxM6 0x3000 /* GPIO Mux 6 */
-#define PxM7 0xc000 /* GPIO Mux 7 */
-#define PxM8 0x30000 /* GPIO Mux 8 */
-#define PxM9 0xc0000 /* GPIO Mux 9 */
-#define PxM10 0x300000 /* GPIO Mux 10 */
-#define PxM11 0xc00000 /* GPIO Mux 11 */
-#define PxM12 0x3000000 /* GPIO Mux 12 */
-#define PxM13 0xc000000 /* GPIO Mux 13 */
-#define PxM14 0x30000000 /* GPIO Mux 14 */
-#define PxM15 0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define IB0 0x1 /* Interrupt Bit 0 */
-#define IB1 0x2 /* Interrupt Bit 1 */
-#define IB2 0x4 /* Interrupt Bit 2 */
-#define IB3 0x8 /* Interrupt Bit 3 */
-#define IB4 0x10 /* Interrupt Bit 4 */
-#define IB5 0x20 /* Interrupt Bit 5 */
-#define IB6 0x40 /* Interrupt Bit 6 */
-#define IB7 0x80 /* Interrupt Bit 7 */
-#define IB8 0x100 /* Interrupt Bit 8 */
-#define IB9 0x200 /* Interrupt Bit 9 */
-#define IB10 0x400 /* Interrupt Bit 10 */
-#define IB11 0x800 /* Interrupt Bit 11 */
-#define IB12 0x1000 /* Interrupt Bit 12 */
-#define IB13 0x2000 /* Interrupt Bit 13 */
-#define IB14 0x4000 /* Interrupt Bit 14 */
-#define IB15 0x8000 /* Interrupt Bit 15 */
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define TMODE 0x3 /* Timer Mode */
-#define PULSE_HI 0x4 /* Pulse Polarity */
-#define PERIOD_CNT 0x8 /* Period Count */
-#define IRQ_ENA 0x10 /* Interrupt Request Enable */
-#define TIN_SEL 0x20 /* Timer Input Select */
-#define OUT_DIS 0x40 /* Output Pad Disable */
-#define CLK_SEL 0x80 /* Timer Clock Select */
-#define TOGGLE_HI 0x100 /* Toggle Mode */
-#define EMU_RUN 0x200 /* Emulation Behavior Select */
-#define ERR_TYP 0xc000 /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define TIMEN0 0x1 /* Timer 0 Enable */
-#define TIMEN1 0x2 /* Timer 1 Enable */
-#define TIMEN2 0x4 /* Timer 2 Enable */
-#define TIMEN3 0x8 /* Timer 3 Enable */
-#define TIMEN4 0x10 /* Timer 4 Enable */
-#define TIMEN5 0x20 /* Timer 5 Enable */
-#define TIMEN6 0x40 /* Timer 6 Enable */
-#define TIMEN7 0x80 /* Timer 7 Enable */
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define TIMDIS0 0x1 /* Timer 0 Disable */
-#define TIMDIS1 0x2 /* Timer 1 Disable */
-#define TIMDIS2 0x4 /* Timer 2 Disable */
-#define TIMDIS3 0x8 /* Timer 3 Disable */
-#define TIMDIS4 0x10 /* Timer 4 Disable */
-#define TIMDIS5 0x20 /* Timer 5 Disable */
-#define TIMDIS6 0x40 /* Timer 6 Disable */
-#define TIMDIS7 0x80 /* Timer 7 Disable */
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define TIMIL0 0x1 /* Timer 0 Interrupt */
-#define TIMIL1 0x2 /* Timer 1 Interrupt */
-#define TIMIL2 0x4 /* Timer 2 Interrupt */
-#define TIMIL3 0x8 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x10000 /* Timer 4 Interrupt */
-#define TIMIL5 0x20000 /* Timer 5 Interrupt */
-#define TIMIL6 0x40000 /* Timer 6 Interrupt */
-#define TIMIL7 0x80000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define RSTDABL 0x2 /* Reset Disable */
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x4000 /* Emulation Override */
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define SECURE1 0x2 /* SECURE 1 */
-#define SECURE2 0x4 /* SECURE 2 */
-#define SECURE3 0x8 /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define SECSTAT 0xe0 /* Secure Status */
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* Bit masks for EPPIx_STATUS */
-
-#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
-#define YFIFO_ERR 0x2 /* Luma FIFO Error */
-#define LTERR_OVR 0x4 /* Line Track Overflow */
-#define LTERR_UNDR 0x8 /* Line Track Underflow */
-#define FTERR_OVR 0x10 /* Frame Track Overflow */
-#define FTERR_UNDR 0x20 /* Frame Track Underflow */
-#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
-#define DMA1URQ 0x80 /* DMA1 Urgent Request */
-#define DMA0URQ 0x100 /* DMA0 Urgent Request */
-#define ERR_DET 0x4000 /* Preamble Error Detected */
-#define FLD 0x8000 /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define EPPI_EN 0x1 /* Enable */
-#define EPPI_DIR 0x2 /* Direction */
-#define XFR_TYPE 0xc /* Operating Mode */
-#define FS_CFG 0x30 /* Frame Sync Configuration */
-#define FLD_SEL 0x40 /* Field Select/Trigger */
-#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
-#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
-#define ICLKGEN 0x200 /* Internal Clock Generation */
-#define IFSGEN 0x400 /* Internal Frame Sync Generation */
-#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
-#define POLS 0x6000 /* Frame Sync Polarity */
-#define DLENGTH 0x38000 /* Data Length */
-#define SKIP_EN 0x40000 /* Skip Enable */
-#define SKIP_EO 0x80000 /* Skip Even or Odd */
-#define PACKEN 0x100000 /* Packing/Unpacking Enable */
-#define SWAPEN 0x200000 /* Swap Enable */
-#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
-#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
-#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
-#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
-#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
-#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
-#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8 (0 << 15) /* 000 - 8 bits */
-#define DLEN_10 (1 << 15) /* 001 - 10 bits */
-#define DLEN_12 (2 << 15) /* 010 - 12 bits */
-#define DLEN_14 (3 << 15) /* 011 - 14 bits */
-#define DLEN_16 (4 << 15) /* 100 - 16 bits */
-#define DLEN_18 (5 << 15) /* 101 - 18 bits */
-#define DLEN_24 (6 << 15) /* 110 - 24 bits */
-
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
-#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
-#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
-#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
-#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
-#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
-#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
-#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-/* BCODE bit field options (SYSCFG register) */
-
-#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
-#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
-#define BCODE_NOBOOT 0x0030 /* always perform full boot */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
- ((((b15)&3) << 30) | \
- (((b14)&3) << 28) | \
- (((b13)&3) << 26) | \
- (((b12)&3) << 24) | \
- (((b11)&3) << 22) | \
- (((b10)&3) << 20) | \
- (((b9) &3) << 18) | \
- (((b8) &3) << 16) | \
- (((b7) &3) << 14) | \
- (((b6) &3) << 12) | \
- (((b5) &3) << 10) | \
- (((b4) &3) << 8) | \
- (((b3) &3) << 6) | \
- (((b2) &3) << 4) | \
- (((b1) &3) << 2) | \
- (((b0) &3)))
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-#endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
deleted file mode 100644
index 1a1091b071fd..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_RX 0
-#define CH_SPORT0_TX 1
-#define CH_SPORT1_RX 2
-#define CH_SPORT1_TX 3
-#define CH_SPI0 4
-#define CH_SPI1 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_UART1_RX 8
-#define CH_UART1_TX 9
-#define CH_ATAPI_RX 10
-#define CH_ATAPI_TX 11
-#define CH_EPPI0 12
-#define CH_EPPI1 13
-#define CH_EPPI2 14
-#define CH_PIXC_IMAGE 15
-#define CH_PIXC_OVERLAY 16
-#define CH_PIXC_OUTPUT 17
-#define CH_SPORT2_RX 18
-#define CH_SPORT2_TX 19
-#define CH_SPORT3_RX 20
-#define CH_SPORT3_TX 21
-#define CH_SDH 22
-#define CH_NFC 22
-#define CH_SPI2 23
-
-#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
-#define CH_UART2_RX 13
-#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
-#define CH_UART2_TX 14
-#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
-#else /* Default USE SPORT2's DMA Channel */
-#define CH_UART2_RX 18
-#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
-#define CH_UART2_TX 19
-#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
-#endif
-
-#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
-#define CH_UART3_RX 15
-#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
-#define CH_UART3_TX 16
-#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
-#else /* Default USE SPORT3's DMA Channel */
-#define CH_UART3_RX 20
-#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
-#define CH_UART3_TX 21
-#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
-#endif
-
-#define CH_MEM_STREAM0_DEST 24
-#define CH_MEM_STREAM0_SRC 25
-#define CH_MEM_STREAM1_DEST 26
-#define CH_MEM_STREAM1_SRC 27
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-
-#define MAX_DMA_CHANNELS 32
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
deleted file mode 100644
index 006da1edcf84..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31 /* N/A */
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46 /* N/A */
-#define GPIO_PC15 47 /* N/A */
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-#define GPIO_PH0 112
-#define GPIO_PH1 113
-#define GPIO_PH2 114
-#define GPIO_PH3 115
-#define GPIO_PH4 116
-#define GPIO_PH5 117
-#define GPIO_PH6 118
-#define GPIO_PH7 119
-#define GPIO_PH8 120
-#define GPIO_PH9 121
-#define GPIO_PH10 122
-#define GPIO_PH11 123
-#define GPIO_PH12 124
-#define GPIO_PH13 125
-#define GPIO_PH14 126 /* N/A */
-#define GPIO_PH15 127 /* N/A */
-#define GPIO_PI0 128
-#define GPIO_PI1 129
-#define GPIO_PI2 130
-#define GPIO_PI3 131
-#define GPIO_PI4 132
-#define GPIO_PI5 133
-#define GPIO_PI6 134
-#define GPIO_PI7 135
-#define GPIO_PI8 136
-#define GPIO_PI9 137
-#define GPIO_PI10 138
-#define GPIO_PI11 139
-#define GPIO_PI12 140
-#define GPIO_PI13 141
-#define GPIO_PI14 142
-#define GPIO_PI15 143
-#define GPIO_PJ0 144
-#define GPIO_PJ1 145
-#define GPIO_PJ2 146
-#define GPIO_PJ3 147
-#define GPIO_PJ4 148
-#define GPIO_PJ5 149
-#define GPIO_PJ6 150
-#define GPIO_PJ7 151
-#define GPIO_PJ8 152
-#define GPIO_PJ9 153
-#define GPIO_PJ10 154
-#define GPIO_PJ11 155
-#define GPIO_PJ12 156
-#define GPIO_PJ13 157
-#define GPIO_PJ14 158 /* N/A */
-#define GPIO_PJ15 159 /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 4
-#define NR_PINTS 160
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned short port_fer;
- unsigned short dummy1;
- unsigned short data;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short data_clear;
- unsigned short dummy4;
- unsigned short dir_set;
- unsigned short dummy5;
- unsigned short dir_clear;
- unsigned short dummy6;
- unsigned short inen;
- unsigned short dummy7;
- unsigned int port_mux;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-#include <mach-common/ports-i.h>
-#include <mach-common/ports-j.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
deleted file mode 100644
index cf7cb725cfa2..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF548_IRQ_H_
-#define _BF548_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (3 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
-#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
-#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
-#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
-#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
-#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
-#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
-#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
-#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
-#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
-#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
-#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
-#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
-#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
-#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
-#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
-#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
-#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
-#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
-#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
-#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
-#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
-
-#define SYS_IRQS IRQ_PINT3
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
-#define IRQ_PH0 BFIN_PH_IRQ(0)
-#define IRQ_PH1 BFIN_PH_IRQ(1)
-#define IRQ_PH2 BFIN_PH_IRQ(2)
-#define IRQ_PH3 BFIN_PH_IRQ(3)
-#define IRQ_PH4 BFIN_PH_IRQ(4)
-#define IRQ_PH5 BFIN_PH_IRQ(5)
-#define IRQ_PH6 BFIN_PH_IRQ(6)
-#define IRQ_PH7 BFIN_PH_IRQ(7)
-#define IRQ_PH8 BFIN_PH_IRQ(8)
-#define IRQ_PH9 BFIN_PH_IRQ(9)
-#define IRQ_PH10 BFIN_PH_IRQ(10)
-#define IRQ_PH11 BFIN_PH_IRQ(11)
-#define IRQ_PH12 BFIN_PH_IRQ(12)
-#define IRQ_PH13 BFIN_PH_IRQ(13)
-#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
-#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
-
-#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
-#define IRQ_PI0 BFIN_PI_IRQ(0)
-#define IRQ_PI1 BFIN_PI_IRQ(1)
-#define IRQ_PI2 BFIN_PI_IRQ(2)
-#define IRQ_PI3 BFIN_PI_IRQ(3)
-#define IRQ_PI4 BFIN_PI_IRQ(4)
-#define IRQ_PI5 BFIN_PI_IRQ(5)
-#define IRQ_PI6 BFIN_PI_IRQ(6)
-#define IRQ_PI7 BFIN_PI_IRQ(7)
-#define IRQ_PI8 BFIN_PI_IRQ(8)
-#define IRQ_PI9 BFIN_PI_IRQ(9)
-#define IRQ_PI10 BFIN_PI_IRQ(10)
-#define IRQ_PI11 BFIN_PI_IRQ(11)
-#define IRQ_PI12 BFIN_PI_IRQ(12)
-#define IRQ_PI13 BFIN_PI_IRQ(13)
-#define IRQ_PI14 BFIN_PI_IRQ(14)
-#define IRQ_PI15 BFIN_PI_IRQ(15)
-
-#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
-#define IRQ_PJ0 BFIN_PJ_IRQ(0)
-#define IRQ_PJ1 BFIN_PJ_IRQ(1)
-#define IRQ_PJ2 BFIN_PJ_IRQ(2)
-#define IRQ_PJ3 BFIN_PJ_IRQ(3)
-#define IRQ_PJ4 BFIN_PJ_IRQ(4)
-#define IRQ_PJ5 BFIN_PJ_IRQ(5)
-#define IRQ_PJ6 BFIN_PJ_IRQ(6)
-#define IRQ_PJ7 BFIN_PJ_IRQ(7)
-#define IRQ_PJ8 BFIN_PJ_IRQ(8)
-#define IRQ_PJ9 BFIN_PJ_IRQ(9)
-#define IRQ_PJ10 BFIN_PJ_IRQ(10)
-#define IRQ_PJ11 BFIN_PJ_IRQ(11)
-#define IRQ_PJ12 BFIN_PJ_IRQ(12)
-#define IRQ_PJ13 BFIN_PJ_IRQ(13)
-#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
-#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-
-/* For compatibility reasons with existing code */
-
-#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
-#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
-#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
-#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
-#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR IRQ_UART1_ERROR
-#define IRQ_UART2_ERR IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR IRQ_UART3_ERROR
-#define IRQ_HOST_ERR IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
-#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMAC0_ERR_POS 4
-#define IRQ_EPPI0_ERR_POS 8
-#define IRQ_SPORT0_ERR_POS 12
-#define IRQ_SPORT1_ERR_POS 16
-#define IRQ_SPI0_ERR_POS 20
-#define IRQ_UART0_ERR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_EPPI0_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER8_POS 0
-#define IRQ_TIMER9_POS 4
-#define IRQ_TIMER10_POS 8
-#define IRQ_PINT0_POS 12
-#define IRQ_PINT1_POS 16
-#define IRQ_MDMAS0_POS 20
-#define IRQ_MDMAS1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMAC1_ERR_POS 0
-#define IRQ_SPORT2_ERR_POS 4
-#define IRQ_SPORT3_ERR_POS 8
-#define IRQ_MXVR_DATA_POS 12
-#define IRQ_SPI1_ERR_POS 16
-#define IRQ_SPI2_ERR_POS 20
-#define IRQ_UART1_ERR_POS 24
-#define IRQ_UART2_ERR_POS 28
-
-/* IAR4 BIT FILEDS */
-#define IRQ_CAN0_ERR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_UART2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_UART2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_UART3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_UART3_TX_POS 16
-#define IRQ_EPPI1_POS 20
-#define IRQ_EPPI2_POS 24
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_ATAPI_RX_POS 12
-#define IRQ_ATAPI_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN0_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN0_TX_POS 0
-#define IRQ_MDMAS2_POS 4
-#define IRQ_MDMAS3_POS 8
-#define IRQ_MXVR_ERR_POS 12
-#define IRQ_MXVR_MSG_POS 16
-#define IRQ_MXVR_PKT_POS 20
-#define IRQ_EPPI1_ERR_POS 24
-#define IRQ_EPPI2_ERR_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_UART3_ERR_POS 0
-#define IRQ_HOST_ERR_POS 4
-#define IRQ_PIXC_ERR_POS 12
-#define IRQ_NFC_ERR_POS 16
-#define IRQ_ATAPI_ERR_POS 20
-#define IRQ_CAN1_ERR_POS 24
-#define IRQ_HS_DMA_ERR_POS 28
-
-/* IAR8 BIT FIELDS */
-#define IRQ_PIXC_IN0_POS 0
-#define IRQ_PIXC_IN1_POS 4
-#define IRQ_PIXC_OUT_POS 8
-#define IRQ_SDH_POS 12
-#define IRQ_CNT_POS 16
-#define IRQ_KEY_POS 20
-#define IRQ_CAN1_RX_POS 24
-#define IRQ_CAN1_TX_POS 28
-
-/* IAR9 BIT FIELDS */
-#define IRQ_SDH_MASK0_POS 0
-#define IRQ_SDH_MASK1_POS 4
-#define IRQ_USB_INT0_POS 12
-#define IRQ_USB_INT1_POS 16
-#define IRQ_USB_INT2_POS 20
-#define IRQ_USB_DMA_POS 24
-#define IRQ_OTPSEC_POS 28
-
-/* IAR10 BIT FIELDS */
-#define IRQ_TIMER0_POS 24
-#define IRQ_TIMER1_POS 28
-
-/* IAR11 BIT FIELDS */
-#define IRQ_TIMER2_POS 0
-#define IRQ_TIMER3_POS 4
-#define IRQ_TIMER4_POS 8
-#define IRQ_TIMER5_POS 12
-#define IRQ_TIMER6_POS 16
-#define IRQ_TIMER7_POS 20
-#define IRQ_PINT2_POS 24
-#define IRQ_PINT3_POS 28
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
deleted file mode 100644
index caac2dfb41eb..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * BF548 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x1000
-
-/* L1 Instruction ROM */
-
-#define L1_ROM_START 0xFFA14000
-#define L1_ROM_LENGTH 0x10000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#if defined(CONFIG_BF542)
-# define L2_LENGTH 0
-#elif defined(CONFIG_BF544)
-# define L2_LENGTH 0x10000
-#else
-# define L2_LENGTH 0x20000
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
deleted file mode 100644
index d9f8632d7d09..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#else
-# define P_ATAPI_D0A (P_DONTCARE)
-# define P_ATAPI_D1A (P_DONTCARE)
-# define P_ATAPI_D2A (P_DONTCARE)
-# define P_ATAPI_D3A (P_DONTCARE)
-# define P_ATAPI_D4A (P_DONTCARE)
-# define P_ATAPI_D5A (P_DONTCARE)
-# define P_ATAPI_D6A (P_DONTCARE)
-# define P_ATAPI_D7A (P_DONTCARE)
-# define P_ATAPI_D8A (P_DONTCARE)
-# define P_ATAPI_D9A (P_DONTCARE)
-# define P_ATAPI_D10A (P_DONTCARE)
-# define P_ATAPI_D11A (P_DONTCARE)
-# define P_ATAPI_D12A (P_DONTCARE)
-# define P_ATAPI_D13A (P_DONTCARE)
-# define P_ATAPI_D14A (P_DONTCARE)
-# define P_ATAPI_D15A (P_DONTCARE)
-#endif
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#else
-# define P_ATAPI_A0A (P_DONTCARE)
-# define P_ATAPI_A1A (P_DONTCARE)
-# define P_ATAPI_A2A (P_DONTCARE)
-#endif
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0 (P_DONTCARE)
-#define P_NAND_D1 (P_DONTCARE)
-#define P_NAND_D2 (P_DONTCARE)
-#define P_NAND_D3 (P_DONTCARE)
-#define P_NAND_D4 (P_DONTCARE)
-#define P_NAND_D5 (P_DONTCARE)
-#define P_NAND_D6 (P_DONTCARE)
-#define P_NAND_D7 (P_DONTCARE)
-#define P_NAND_WE (P_DONTCARE)
-#define P_NAND_RE (P_DONTCARE)
-#define P_NAND_CLE (P_DONTCARE)
-#define P_NAND_ALE (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
deleted file mode 100644
index 48dd3a4bc4a5..000000000000
--- a/arch/blackfin/mach-bf548/ints-priority.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
- ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
- ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
- ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
- ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
- ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
- ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
- ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
- ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
- ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
- ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
- ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
- ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
- ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
- ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
- ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
- ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
- ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
- ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
- ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
- ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
- ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
- ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
- ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
- ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
- ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
- ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
- ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
- ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
- ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
- ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
-
- bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
- ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
- ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
- ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
-
- bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
- ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
- ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
-
- bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
-
- bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
- ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
deleted file mode 100644
index 059c3cbdb5ec..000000000000
--- a/arch/blackfin/mach-bf561/Kconfig
+++ /dev/null
@@ -1,213 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF561)
-
-source "arch/blackfin/mach-bf561/boards/Kconfig"
-
-menu "BF561 Specific Configuration"
-
-if (!SMP)
-
-comment "Core B Support"
-
-config BF561_COREB
- bool "Enable Core B loader"
- default y
-
-endif
-
-comment "Interrupt Priority Assignment"
-
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "PLL Wakeup Interrupt"
- default 7
-config IRQ_DMA1_ERROR
- int "DMA1 Error (generic)"
- default 7
-config IRQ_DMA2_ERROR
- int "DMA2 Error (generic)"
- default 7
-config IRQ_IMDMA_ERROR
- int "IMDMA Error (generic)"
- default 7
-config IRQ_PPI0_ERROR
- int "PPI0 Error Interrupt"
- default 7
-config IRQ_PPI1_ERROR
- int "PPI1 Error Interrupt"
- default 7
-config IRQ_SPORT0_ERROR
- int "SPORT0 Error Interrupt"
- default 7
-config IRQ_SPORT1_ERROR
- int "SPORT1 Error Interrupt"
- default 7
-config IRQ_SPI_ERROR
- int "SPI Error Interrupt"
- default 7
-config IRQ_UART_ERROR
- int "UART Error Interrupt"
- default 7
-config IRQ_RESERVED_ERROR
- int "Reserved Interrupt"
- default 7
-config IRQ_DMA1_0
- int "DMA1 0 Interrupt(PPI1)"
- default 8
-config IRQ_DMA1_1
- int "DMA1 1 Interrupt(PPI2)"
- default 8
-config IRQ_DMA1_2
- int "DMA1 2 Interrupt"
- default 8
-config IRQ_DMA1_3
- int "DMA1 3 Interrupt"
- default 8
-config IRQ_DMA1_4
- int "DMA1 4 Interrupt"
- default 8
-config IRQ_DMA1_5
- int "DMA1 5 Interrupt"
- default 8
-config IRQ_DMA1_6
- int "DMA1 6 Interrupt"
- default 8
-config IRQ_DMA1_7
- int "DMA1 7 Interrupt"
- default 8
-config IRQ_DMA1_8
- int "DMA1 8 Interrupt"
- default 8
-config IRQ_DMA1_9
- int "DMA1 9 Interrupt"
- default 8
-config IRQ_DMA1_10
- int "DMA1 10 Interrupt"
- default 8
-config IRQ_DMA1_11
- int "DMA1 11 Interrupt"
- default 8
-config IRQ_DMA2_0
- int "DMA2 0 (SPORT0 RX)"
- default 9
-config IRQ_DMA2_1
- int "DMA2 1 (SPORT0 TX)"
- default 9
-config IRQ_DMA2_2
- int "DMA2 2 (SPORT1 RX)"
- default 9
-config IRQ_DMA2_3
- int "DMA2 3 (SPORT2 TX)"
- default 9
-config IRQ_DMA2_4
- int "DMA2 4 (SPI)"
- default 9
-config IRQ_DMA2_5
- int "DMA2 5 (UART RX)"
- default 9
-config IRQ_DMA2_6
- int "DMA2 6 (UART TX)"
- default 9
-config IRQ_DMA2_7
- int "DMA2 7 Interrupt"
- default 9
-config IRQ_DMA2_8
- int "DMA2 8 Interrupt"
- default 9
-config IRQ_DMA2_9
- int "DMA2 9 Interrupt"
- default 9
-config IRQ_DMA2_10
- int "DMA2 10 Interrupt"
- default 9
-config IRQ_DMA2_11
- int "DMA2 11 Interrupt"
- default 9
-config IRQ_TIMER0
- int "TIMER 0 Interrupt"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "TIMER 1 Interrupt"
- default 10
-config IRQ_TIMER2
- int "TIMER 2 Interrupt"
- default 10
-config IRQ_TIMER3
- int "TIMER 3 Interrupt"
- default 10
-config IRQ_TIMER4
- int "TIMER 4 Interrupt"
- default 10
-config IRQ_TIMER5
- int "TIMER 5 Interrupt"
- default 10
-config IRQ_TIMER6
- int "TIMER 6 Interrupt"
- default 10
-config IRQ_TIMER7
- int "TIMER 7 Interrupt"
- default 10
-config IRQ_TIMER8
- int "TIMER 8 Interrupt"
- default 10
-config IRQ_TIMER9
- int "TIMER 9 Interrupt"
- default 10
-config IRQ_TIMER10
- int "TIMER 10 Interrupt"
- default 10
-config IRQ_TIMER11
- int "TIMER 11 Interrupt"
- default 10
-config IRQ_PROG0_INTA
- int "Programmable Flags0 A (8)"
- default 11
-config IRQ_PROG0_INTB
- int "Programmable Flags0 B (8)"
- default 11
-config IRQ_PROG1_INTA
- int "Programmable Flags1 A (8)"
- default 11
-config IRQ_PROG1_INTB
- int "Programmable Flags1 B (8)"
- default 11
-config IRQ_PROG2_INTA
- int "Programmable Flags2 A (8)"
- default 11
-config IRQ_PROG2_INTB
- int "Programmable Flags2 B (8)"
- default 11
-config IRQ_DMA1_WRRD0
- int "MDMA1 0 write/read INT"
- default 8
-config IRQ_DMA1_WRRD1
- int "MDMA1 1 write/read INT"
- default 8
-config IRQ_DMA2_WRRD0
- int "MDMA2 0 write/read INT"
- default 9
-config IRQ_DMA2_WRRD1
- int "MDMA2 1 write/read INT"
- default 9
-config IRQ_IMDMA_WRRD0
- int "IMDMA 0 write/read INT"
- default 12
-config IRQ_IMDMA_WRRD1
- int "IMDMA 1 write/read INT"
- default 12
-config IRQ_WDTIMER
- int "Watch Dog Timer"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
deleted file mode 100644
index b34029718318..000000000000
--- a/arch/blackfin/mach-bf561/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# arch/blackfin/mach-bf561/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-
-obj-$(CONFIG_BF561_COREB) += coreb.o
-obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
deleted file mode 100644
index 1e2989c5d6b2..000000000000
--- a/arch/blackfin/mach-bf561/atomic.S
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/asm-offsets.h>
-#include <asm/rwlock.h>
-#include <asm/cplb.h>
-
-.text
-
-.macro coreslot_loadaddr reg:req
- \reg\().l = _corelock;
- \reg\().h = _corelock;
-.endm
-
-.macro safe_testset addr:req, scratch:req
-#if ANOMALY_05000477
- cli \scratch;
- testset (\addr);
- sti \scratch;
-#else
- testset (\addr);
-#endif
-.endm
-
-/*
- * r0 = address of atomic data to flush and invalidate (32bit).
- *
- * Clear interrupts and return the old mask.
- * We assume that no atomic data can span cachelines.
- *
- * Clobbers: r2:0, p0
- */
-ENTRY(_get_core_lock)
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock;
- SSYNC(r2);
- jump .Lretry_corelock
-.Ldone_corelock:
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- rts;
-ENDPROC(_get_core_lock)
-
-/*
- * r0 = address of atomic data in uncacheable memory region (32bit).
- *
- * Clear interrupts and return the old mask.
- *
- * Clobbers: r0, p0
- */
-ENTRY(_get_core_lock_noflush)
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock_noflush:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock_noflush;
- SSYNC(r2);
- jump .Lretry_corelock_noflush
-.Ldone_corelock_noflush:
- /*
- * SMP kgdb runs into dead loop without NOP here, when one core
- * single steps over get_core_lock_noflush and the other executes
- * get_core_lock as a slave node.
- */
- nop;
- CSYNC(r2);
- rts;
-ENDPROC(_get_core_lock_noflush)
-
-/*
- * r0 = interrupt mask to restore.
- * r1 = address of atomic data to flush and invalidate (32bit).
- *
- * Interrupts are masked on entry (see _get_core_lock).
- * Clobbers: r2:0, p0
- */
-ENTRY(_put_core_lock)
- /* Write-through cache assumed, so no flush needed here. */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
- SSYNC(r2);
- sti r0;
- rts;
-ENDPROC(_put_core_lock)
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-
-ENTRY(___raw_smp_mark_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Set bit of other cores in barrier mask. Don't change current core bit.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- r7 = ~r6;
- cc = r5 == 0;
- if cc jump 1f;
- r7 = r7 | r6;
-1:
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_mark_barrier_asm)
-
-ENTRY(___raw_smp_check_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Clear current core bit in barrier mask if it is set.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- cc = r5 == 0;
- if cc jump 1f;
- r6 = ~r6;
- r7 = r7 & r6;
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
-
- /*
- * Invalidate the entire D-cache of current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
- jump 2f;
-1:
- call _put_core_lock;
-2:
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_check_barrier_asm)
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_start_lock_coherent:
-
- [--sp] = rets;
- [--sp] = ( r7:6 );
- r7 = r0;
- p1 = r1;
-
- /*
- * Determine whether the atomic data was previously
- * owned by another CPU (=r6).
- */
- GET_CPUID(p0, r2);
- r1 = 1;
- r1 <<= r2;
- r2 = ~r1;
-
- r1 = [p1];
- r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
- r6 = r1 & r2;
- r1 = [p1];
- r1 <<= 4;
- r1 >>= 4;
- [p1] = r1;
-
- /*
- * Release the core lock now, but keep IRQs disabled while we are
- * performing the remaining housekeeping chores for the current CPU.
- */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
-
- /*
- * If another CPU has owned the same atomic section before us,
- * then our D-cached copy of the shared data protected by the
- * current spin/write_lock may be obsolete.
- */
- cc = r6 == 0;
- if cc jump .Lcache_synced
-
- /*
- * Invalidate the entire D-cache of the current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
-
-.Lcache_synced:
- SSYNC(r2);
- sti r7;
- ( r7:6 ) = [sp++];
- rets = [sp++];
- rts
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_end_lock_coherent:
-
- p1 = r1;
- GET_CPUID(p0, r2);
- r2 += 28;
- r1 = 1;
- r1 <<= r2;
- r2 = [p1];
- r2 = r1 | r2;
- [p1] = r2;
- r1 = p1;
- jump _put_core_lock;
-
-#endif /* __ARCH_SYNC_CORE_DCACHE */
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_is_locked_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- cc = bittst( r3, 0 );
- r3 = cc;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = r3;
- rts;
-ENDPROC(___raw_spin_is_locked_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_lock_asm)
- p1 = r0;
- [--sp] = rets;
-.Lretry_spinlock:
- call _get_core_lock;
- r1 = p1;
- r2 = [p1];
- cc = bittst( r2, 0 );
- if cc jump .Lbusy_spinlock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r3 = p1;
- bitset ( r2, 0 ); /* Raise the lock bit. */
- [p1] = r2;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lbusy_spinlock:
- /* We don't touch the atomic area if busy, so that flush
- will behave like nop in _put_core_lock. */
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- jump .Lretry_spinlock
-ENDPROC(___raw_spin_lock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = p1;
- r3 = [p1];
- cc = bittst( r3, 0 );
- if cc jump .Lfailed_trylock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- bitset ( r3, 0 ); /* Raise the lock bit. */
- [p1] = r3;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- r0 = 1;
- rets = [sp++];
- rts;
-.Lfailed_trylock:
- call _put_core_lock;
- r0 = 0;
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_trylock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_spin_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- bitclr ( r2, 0 );
- [p1] = r2;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_read_lock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
-.Lrdlock_try:
- r1 = [p1];
- r1 += -1;
- [p1] = r1;
- cc = r1 < 0;
- if cc jump .Lrdlock_failed
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lrdlock_failed:
- r1 += 1;
- [p1] = r1;
-.Lrdlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 < 2;
- if cc jump .Lrdlock_wait;
- jump .Lrdlock_try
-ENDPROC(___raw_read_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 <= 0;
- if cc jump .Lfailed_tryrdlock;
- r1 += -1;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-.Lfailed_tryrdlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_read_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Note: Processing controlled by a reader lock should not have
- * any side-effect on cache issues with the other core, so we
- * just release the core lock and exit (no _end_lock_coherent).
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 += 1;
- [p1] = r1;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- rts;
-ENDPROC(___raw_read_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_lock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
-.Lwrlock_try:
- r1 = [p1];
- r1 = r1 - r3;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r2 = r1;
- r2 <<= 4;
- r2 >>= 4;
- cc = r2 == 0;
-#else
- cc = r1 == 0;
-#endif
- if !cc jump .Lwrlock_wait
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lwrlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 <<= 4;
- r1 >>= 4;
-#endif
- cc = r1 == r3;
- if !cc jump .Lwrlock_wait;
- jump .Lwrlock_try
-ENDPROC(___raw_write_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r2.l = lo(RW_LOCK_BIAS);
- r2.h = hi(RW_LOCK_BIAS);
- cc = r1 == r2;
- if !cc jump .Lfailed_trywrlock;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 >>= 28;
- r1 <<= 28;
-#else
- r1 = 0;
-#endif
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-
-.Lfailed_trywrlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_write_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_unlock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 = r1 + r3;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_write_unlock_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the new value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_add_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- r3 = r3 + r2;
- [p1] = r3;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the old value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xadd_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r3 + r2;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * AND the mask bits from a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_and_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 & r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_and_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * OR the mask bits into a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_or_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 | r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_or_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * XOR the mask bits with a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xor_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 ^ r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_xor_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * Perform a logical AND between the mask bits and a 32bit word, and
- * return the masked value. We need this on this architecture in
- * order to invalidate the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_test_asm)
- p1 = r0;
- r3 = r1;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- r0 = r0 & r3;
- rts;
-ENDPROC(___raw_atomic_test_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * Swap *ptr with value and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-#define __do_xchg(src, dst) \
- p1 = r0; \
- r3 = r1; \
- [--sp] = rets; \
- call _get_core_lock; \
- r2 = src; \
- dst = r3; \
- r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_xchg_1_asm)
- __do_xchg(b[p1] (z), b[p1])
-ENDPROC(___raw_xchg_1_asm)
-
-ENTRY(___raw_xchg_2_asm)
- __do_xchg(w[p1] (z), w[p1])
-ENDPROC(___raw_xchg_2_asm)
-
-ENTRY(___raw_xchg_4_asm)
- __do_xchg([p1], [p1])
-ENDPROC(___raw_xchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = new
- * r2 = old
- *
- * Swap *ptr with new if *ptr == old and return the previous *ptr
- * value atomically.
- *
- * Clobbers: r3:0, p1:0
- */
-#define __do_cmpxchg(src, dst) \
- [--sp] = rets; \
- [--sp] = r4; \
- p1 = r0; \
- r3 = r1; \
- r4 = r2; \
- call _get_core_lock; \
- r2 = src; \
- cc = r2 == r4; \
- if !cc jump 1f; \
- dst = r3; \
- 1: r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- r4 = [sp++]; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_cmpxchg_1_asm)
- __do_cmpxchg(b[p1] (z), b[p1])
-ENDPROC(___raw_cmpxchg_1_asm)
-
-ENTRY(___raw_cmpxchg_2_asm)
- __do_cmpxchg(w[p1] (z), w[p1])
-ENDPROC(___raw_cmpxchg_2_asm)
-
-ENTRY(___raw_cmpxchg_4_asm)
- __do_cmpxchg([p1], [p1])
-ENDPROC(___raw_cmpxchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Set a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_set_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_or_asm
-ENDPROC(___raw_bit_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Clear a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_clear_asm)
- r2 = 1;
- r2 <<= r1;
- r1 = ~r2;
- jump ___raw_atomic_and_asm
-ENDPROC(___raw_bit_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Toggle a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_toggle_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_xor_asm
-ENDPROC(___raw_bit_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-set a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_set_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_set_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-clear a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_clear_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_clear_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-toggle a bit in a 32bit word,
- * and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_toggle_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_toggle_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test a bit in a 32bit word and return its value.
- * We need this on this architecture in order to invalidate
- * the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_test_asm
-ENDPROC(___raw_bit_test_asm)
-
-/*
- * r0 = ptr
- *
- * Fetch and return an uncached 32bit value.
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_uncached_fetch_asm)
- p1 = r0;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- rts;
-ENDPROC(___raw_uncached_fetch_asm)
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
deleted file mode 100644
index 10e977b56710..000000000000
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN561_EZKIT
- help
- Select your board!
-
-config BFIN561_EZKIT
- bool "BF561-EZKIT"
- help
- BF561-EZKIT-LITE board support.
-
-config BFIN561_TEPLA
- bool "BF561-TEPLA"
- help
- BF561-TEPLA board support.
-
-config BFIN561_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF561"
- help
- CM-BF561 support for EVAL- and DEV-Board.
-
-config BFIN561_ACVILON
- bool "BF561-ACVILON"
- help
- BF561-ACVILON System On Module support (SO-DIMM 144).
- For more information about Acvilon BF561 SoM
- please go to http://www.niistt.ru/
-
-endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
deleted file mode 100644
index a5879f7857ad..000000000000
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# arch/blackfin/mach-bf561/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
-obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
-obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
deleted file mode 100644
index 696cc9d7820a..000000000000
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * File: arch/blackfin/mach-bf561/acvilon.c
- * Based on: arch/blackfin/mach-bf561/ezkit.c
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- * Copyright 2004-2006 Analog Devices Inc.
- * Copyright 2009 CJSC "NII STT"
- *
- * Bugs:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- *
- * For more information about Acvilon BF561 SoM please
- * go to http://www.niistt.ru/
- *
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/jiffies.h>
-#include <linux/i2c-pca-platform.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/cacheflush.h>
-#include <linux/i2c.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Acvilon board";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x20000000,
- .end = 0x20000000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .port1_disable = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-static struct resource bfin_i2c_pca_resources[] = {
- {
- .name = "pca9564-regs",
- .start = 0x2C000000,
- .end = 0x2C000000 + 16,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
- }, {
-
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
- .gpio = -1,
- .i2c_clock_speed = 330000,
- .timeout = HZ,
-};
-
-/* PCA9564 I2C Bus driver */
-static struct platform_device bfin_i2c_pca_device = {
- .name = "i2c-pca-platform",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
- .resource = bfin_i2c_pca_resources,
- .dev = {
- .platform_data = &pca9564_platform_data,
- }
-};
-
-/* I2C devices fitted. */
-static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("ds1339", 0x68),
- },
- {
- I2C_BOARD_INFO("tcn75", 0x49),
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram mtd_ram_data = {
- .mapname = "rootfs(RAM)",
- .bankwidth = 4,
-};
-
-static struct resource mtd_ram_resource = {
- .start = 0x4000000,
- .end = 0x5ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mtd_ram_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &mtd_ram_data,
- },
- .num_resources = 1,
- .resource = &mtd_ram_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x28000000,
- .end = 0x28000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- /* Passed to driver */
- .platform_data = &bfin_uart0_peripherals,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "params(nand)",
- .size = 32 * 1024 * 1024,
- .offset = 0,
- }, {
- .name = "userfs(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 3
-
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF10
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x24000000,
- .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
-}
-#else
-static void bfin_plat_nand_init(void)
-{
-}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader",
- .size = 0x4200,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM},
- {
- .name = "u-boot",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "u-boot(params)",
- .size = 0x4200,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "kernel",
- .size = 0x294000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "params",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select */
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-static struct resource bfin_gpios_resources = {
- .start = 31,
-/* .end = MAX_BLACKFIN_GPIOS - 1, */
- .end = 32,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device bfin_gpios_device = {
- .name = "simple-gpio",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_gpios_resources,
-};
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */ ,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *acvilon_devices[] __initdata = {
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
- &bfin_gpios_device,
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
- &bfin_i2c_pca_device,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &mtd_ram_device,
-#endif
-
-};
-
-static int __init acvilon_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- bfin_plat_nand_init();
- ret =
- platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
- if (ret < 0)
- return ret;
-
- i2c_register_board_info(0, acvilon_i2c_devs,
- ARRAY_SIZE(acvilon_i2c_devs));
-
- bfin_write_FIO0_FLAG_C(1 << 14);
- msleep(5);
- bfin_write_FIO0_FLAG_S(1 << 14);
-
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(acvilon_init);
-
-static struct platform_device *acvilon_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(acvilon_early_devices,
- ARRAY_SIZE(acvilon_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
deleted file mode 100644
index 10c57771822d..000000000000
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/mtd/physmap.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF561";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x28000300,
- .end = 0x28000300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24008000,
- .end = 0x24008000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF43,
- .end = IRQ_PF43,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x24000000,
- .end = 0x24000000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF45,
- .end = IRQ_PF45,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x24008000,
- .end = 0x24008000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x24008004,
- .end = 0x24008004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF47,
- .end = IRQ_PF47,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF46
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2400C000,
- .end = 0x2400C001F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2400D018,
- .end = 0x2400D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &para_flash_data,
- },
- .num_resources = 1,
- .resource = &para_flash_resource,
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf561_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &para_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF46, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PF46 */
- gpio_direction_output(GPIO_PF46, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF46, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf561_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf561_init);
-
-static struct platform_device *cm_bf561_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf561_early_devices,
- ARRAY_SIZE(cm_bf561_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
deleted file mode 100644
index acc5363f60c6..000000000000
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF561-EZKIT";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0F0000,
- .end = 0x203C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x2c060000,
- .end = 0x2c060000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x2c060004,
- .end = 0x2c060004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x2C000000,
- .end = 0x2C000000 + 0x7F,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x2C010300,
- .end = 0x2C010300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x2000 * 7,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x2000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI0,
- .irq_err = IRQ_PPI1_ERROR,
- .base = (void __iomem *)PPI0_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7183)
-#include <media/i2c/adv7183.h>
-static struct v4l2_input adv7183_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
-};
-
-static struct bcap_route adv7183_routes[] = {
- {
- .input = ADV7183_COMPOSITE4,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_SVIDEO0,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_COMPONENT0,
- .output = ADV7183_8BIT_OUT,
- },
-};
-
-
-static const unsigned adv7183_gpio[] = {
- GPIO_PF13, /* reset pin */
- GPIO_PF2, /* output enable pin */
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF561",
- .inputs = adv7183_inputs,
- .num_inputs = ARRAY_SIZE(adv7183_inputs),
- .routes = adv7183_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7183",
- .addr = 0x20,
- .platform_data = (void *)adv7183_gpio,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init ezkit_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
- SSYNC();
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
- bfin_write_FIO0_FLAG_S(1 << 15);
- SSYNC();
- /*
- * This initialization lasts for approximately 4500 MCLKs.
- * MCLK = 12.288MHz
- */
- udelay(400);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
deleted file mode 100644
index f87b8cc0cd4c..000000000000
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2004-2007 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Thanks to Jamey Hicks.
- *
- * Only SMSC91C1111 was registered, may do more later.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-
-const char bfin_board_name[] = "Tepla-BF561";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-static struct resource smc91x_resources[] = {
- {
- .start = 0x2C000300,
- .end = 0x2C000320,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-static struct platform_device *tepla_devices[] __initdata = {
- &smc91x_device,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-};
-
-static int __init tepla_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices));
-}
-
-arch_initcall(tepla_init);
-
-static struct platform_device *tepla_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tepla_early_devices,
- ARRAY_SIZE(tepla_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
deleted file mode 100644
index cf27554e76bf..000000000000
--- a/arch/blackfin/mach-bf561/coreb.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Load firmware into Core B on a BF561
- *
- * Author: Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* The Core B reset func requires code in the application that is loaded into
- * Core B. In order to reset, the application needs to install an interrupt
- * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
- * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
- * B to stall when Supplemental Interrupt 0 is set, and will reset PC to
- * 0xff600000 when COREB_SRAM_INIT is cleared.
- */
-
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/miscdevice.h>
-
-#define CMD_COREB_START _IO('b', 0)
-#define CMD_COREB_STOP _IO('b', 1)
-#define CMD_COREB_RESET _IO('b', 2)
-
-static long
-coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int ret = 0;
-
- switch (cmd) {
- case CMD_COREB_START:
- bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
- break;
- case CMD_COREB_STOP:
- bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- case CMD_COREB_RESET:
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- CSYNC();
-
- return ret;
-}
-
-static const struct file_operations coreb_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = coreb_ioctl,
- .llseek = noop_llseek,
-};
-
-static struct miscdevice coreb_dev = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "coreb",
- .fops = &coreb_fops,
-};
-builtin_misc_device(coreb_dev);
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
deleted file mode 100644
index 8ffdd6b4a242..000000000000
--- a/arch/blackfin/mach-bf561/dma.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI0:
- ret_irq = IRQ_PPI0;
- break;
- case CH_PPI1:
- ret_irq = IRQ_PPI1;
- break;
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
- case CH_UART_RX:
- ret_irq = IRQ_UART_RX;
- break;
- case CH_UART_TX:
- ret_irq = IRQ_UART_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM_DMA2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM_DMA3;
- break;
-
- case CH_IMEM_STREAM0_SRC:
- case CH_IMEM_STREAM0_DEST:
- ret_irq = IRQ_IMEM_DMA0;
- break;
- case CH_IMEM_STREAM1_SRC:
- case CH_IMEM_STREAM1_DEST:
- ret_irq = IRQ_IMEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
deleted file mode 100644
index 0123117b8ff2..000000000000
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/smp.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <mach/pll.h>
-
-int hotplug_coreb;
-
-void platform_cpu_die(void)
-{
- unsigned long iwr;
-
- hotplug_coreb = 1;
-
- /*
- * When CoreB wakes up, the code in _coreb_trampoline_start cannot
- * turn off the data cache. This causes the CoreB failed to boot.
- * As a workaround, we invalidate all the data cache before sleep.
- */
- blackfin_invalidate_entire_dcache();
-
- /* disable core timer */
- bfin_write_TCNTL(0);
-
- /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
- SSYNC();
-
- /* set CoreB wakeup by ipi0, iwr will be discarded */
- bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
- SSYNC();
-
- coreb_die();
-}
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
deleted file mode 100644
index 038249c1d0d4..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* SIGNBITS Instruction Not Functional under Certain Conditions */
-#define ANOMALY_05000127 (1)
-/* IMDMA S1/D1 Channel May Stall */
-#define ANOMALY_05000149 (1)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* Internal Memory DMA Does Not Operate at Full Speed */
-#define ANOMALY_05000182 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI Not Functional at Core Voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET Operation Forces Stall on the Other Core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
- * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
- * after the behavior and the root cause are confirmed with hardware team.
- */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA May Corrupt Data under Certain Conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data Cache Write Back to External Synchronous Memory May Be Lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error when ISR Context Is Not Restored */
-/* Temporarily walk around for bug 5423 till this issue is confirmed by
- * official anomaly document. It looks 05000281 still exists on bf561
- * v0.5.
- */
-#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* Reads Will Receive Incorrect Data under Certain Conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted after SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* 24-Bit SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* Slave SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
-#define ANOMALY_05000412 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
-#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* SCKELOW Feature Is Not Functional */
-#define ANOMALY_05000458 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000119 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
deleted file mode 100644
index 9f9a367e6a24..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF561_H__
-#define __MACH_BF561_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************
- * Blackfin Cache setup
- */
-
-
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS */
-#define PLL_WAKEUP_BIT 0xFFFFFFFF
-#define DMA1_ERROR_BIT 0xFFFFFF0F
-#define DMA2_ERROR_BIT 0xFFFFF0FF
-#define IMDMA_ERROR_BIT 0xFFFF0FFF
-#define PPI1_ERROR_BIT 0xFFF0FFFF
-#define PPI2_ERROR_BIT 0xFF0FFFFF
-#define SPORT0_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0x0FFFFFFF
-/* IAR1 BIT FIELDS */
-#define SPI_ERROR_BIT 0xFFFFFFFF
-#define UART_ERROR_BIT 0xFFFFFF0F
-#define RESERVED_ERROR_BIT 0xFFFFF0FF
-#define DMA1_0_BIT 0xFFFF0FFF
-#define DMA1_1_BIT 0xFFF0FFFF
-#define DMA1_2_BIT 0xFF0FFFFF
-#define DMA1_3_BIT 0xF0FFFFFF
-#define DMA1_4_BIT 0x0FFFFFFF
-/* IAR2 BIT FIELDS */
-#define DMA1_5_BIT 0xFFFFFFFF
-#define DMA1_6_BIT 0xFFFFFF0F
-#define DMA1_7_BIT 0xFFFFF0FF
-#define DMA1_8_BIT 0xFFFF0FFF
-#define DMA1_9_BIT 0xFFF0FFFF
-#define DMA1_10_BIT 0xFF0FFFFF
-#define DMA1_11_BIT 0xF0FFFFFF
-#define DMA2_0_BIT 0x0FFFFFFF
-/* IAR3 BIT FIELDS */
-#define DMA2_1_BIT 0xFFFFFFFF
-#define DMA2_2_BIT 0xFFFFFF0F
-#define DMA2_3_BIT 0xFFFFF0FF
-#define DMA2_4_BIT 0xFFFF0FFF
-#define DMA2_5_BIT 0xFFF0FFFF
-#define DMA2_6_BIT 0xFF0FFFFF
-#define DMA2_7_BIT 0xF0FFFFFF
-#define DMA2_8_BIT 0x0FFFFFFF
-/* IAR4 BIT FIELDS */
-#define DMA2_9_BIT 0xFFFFFFFF
-#define DMA2_10_BIT 0xFFFFFF0F
-#define DMA2_11_BIT 0xFFFFF0FF
-#define TIMER0_BIT 0xFFFF0FFF
-#define TIMER1_BIT 0xFFF0FFFF
-#define TIMER2_BIT 0xFF0FFFFF
-#define TIMER3_BIT 0xF0FFFFFF
-#define TIMER4_BIT 0x0FFFFFFF
-/* IAR5 BIT FIELDS */
-#define TIMER5_BIT 0xFFFFFFFF
-#define TIMER6_BIT 0xFFFFFF0F
-#define TIMER7_BIT 0xFFFFF0FF
-#define TIMER8_BIT 0xFFFF0FFF
-#define TIMER9_BIT 0xFFF0FFFF
-#define TIMER10_BIT 0xFF0FFFFF
-#define TIMER11_BIT 0xF0FFFFFF
-#define PROG0_INTA_BIT 0x0FFFFFFF
-/* IAR6 BIT FIELDS */
-#define PROG0_INTB_BIT 0xFFFFFFFF
-#define PROG1_INTA_BIT 0xFFFFFF0F
-#define PROG1_INTB_BIT 0xFFFFF0FF
-#define PROG2_INTA_BIT 0xFFFF0FFF
-#define PROG2_INTB_BIT 0xFFF0FFFF
-#define DMA1_WRRD0_BIT 0xFF0FFFFF
-#define DMA1_WRRD1_BIT 0xF0FFFFFF
-#define DMA2_WRRD0_BIT 0x0FFFFFFF
-/* IAR7 BIT FIELDS */
-#define DMA2_WRRD1_BIT 0xFFFFFFFF
-#define IMDMA_WRRD0_BIT 0xFFFFFF0F
-#define IMDMA_WRRD1_BIT 0xFFFFF0FF
-#define WATCH_BIT 0xFFFF0FFF
-#define RESERVED_1_BIT 0xFFF0FFFF
-#define RESERVED_2_BIT 0xFF0FFFFF
-#define SUPPLE_0_BIT 0xF0FFFFFF
-#define SUPPLE_1_BIT 0x0FFFFFFF
-
-/* Miscellaneous Values */
-
-/****************************** EBIU Settings ********************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#if defined(CONFIG_C_AMBEN_ALL)
-#define V_AMBEN AMBEN_ALL
-#elif defined(CONFIG_C_AMBEN)
-#define V_AMBEN 0x0
-#elif defined(CONFIG_C_AMBEN_B0)
-#define V_AMBEN AMBEN_B0
-#elif defined(CONFIG_C_AMBEN_B0_B1)
-#define V_AMBEN AMBEN_B0_B1
-#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#ifdef CONFIG_C_B0PEN
-#define V_B0PEN 0x10
-#else
-#define V_B0PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B1PEN
-#define V_B1PEN 0x20
-#else
-#define V_B1PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B2PEN
-#define V_B2PEN 0x40
-#else
-#define V_B2PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B3PEN
-#define V_B3PEN 0x80
-#else
-#define V_B3PEN 0x00
-#endif
-
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-
-#ifdef CONFIG_BF561
-#define CPU "BF561"
-#define CPUID 0x27bb
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
deleted file mode 100644
index 08072c86d5dc..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
deleted file mode 100644
index dc470534c085..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF561_FAMILY
-
-#include "bf561.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF561.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF561.h"
-#endif
-
-#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
-#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
-#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
-
-/* Weird muxer funcs which pick SIC regs from IMASK base */
-#define __SIC_MUX(base, x) ((base) + ((x) << 2))
-#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
-#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
-#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
-#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
-#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
-#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
-
-#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
deleted file mode 100644
index 753331597207..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ /dev/null
@@ -1,1460 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
-#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
-#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
-#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
-#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
-#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
-#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
-#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
-#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
-#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
-#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
-#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
-#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
-#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
-#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
-#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
-#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
-#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
-#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
-#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
-#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
-#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
-#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
-#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
-#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
-#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
-#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
-#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
-#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
-#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
-#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
-#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
-#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
-#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
-#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
-#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
-#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
-#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
-#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
-#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
-#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
-#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
-#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
-#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
-#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
-#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
-#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
-#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
-#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
-#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
-#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
-#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
-#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
-#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
-#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
-#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
-#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
-#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
-#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
-#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
-#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
-#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
-#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
-#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
-#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
-#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
-#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
-#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
-#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
-#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
-#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
-#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
-#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
-#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
-#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
-#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
-#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
-#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
-#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
-#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
-#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
-#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
-#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
-#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
-#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
-#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
-#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
-#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
-/*DMA traffic control registers */
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
-#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
-#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
-#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
-#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
-#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
-#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
-#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
-#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
-#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
-#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
-#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
-#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
-#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
-#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
-#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
-#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
-#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
-#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
-#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
-#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
-#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
-#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
-#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
-#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
-#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
-#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
-#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
-#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
-#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
-#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
-#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
-#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
-#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
-#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
-#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
-#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
-#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
-#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
-#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
-#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
-#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
-#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
-#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
-#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
-#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
-#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
-#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
-#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
-#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
-#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
-#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
-#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
-#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
-#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
-#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
-#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
-#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
-#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
-#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
-#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
-#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
-#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
-#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
-#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
-#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
-#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
-#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
-#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
-#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
-#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
-#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
-#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
-#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
-#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
-#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
-#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
-#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
-#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
-#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
-#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
-#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
-#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
-#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
-#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
-#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
-#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
-#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
-#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
-#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
-#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
-#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
-#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
-#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
-#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
-#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
-#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
-#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
-#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
-#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
-#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
-#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
-#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
-#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
-#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
-#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
-#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
-#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
-#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
-
-#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
deleted file mode 100644
index 9f21f768c63a..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ /dev/null
@@ -1,1402 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
-#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
-#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
-#define RESET_SOFTWARE (SWRST_OCCURRED)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SWRST 0xFFC00100 /* Software Reset register */
-#define SYSCR 0xFFC00104 /* System Reset Configuration register */
-#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
-#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
-#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
-#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
-#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
-#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST 0xFFC01100 /* reserved */
-#define SICB_SYSCR 0xFFC01104 /* reserved */
-#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
-#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
-#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
-#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
-#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
-#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
-#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
-#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
-
-#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
-#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
-#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
-#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
-#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
-
-#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
-#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
-#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
-#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
-
-#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
-#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
-#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
-#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
-
-#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
-#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
-#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
-#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
-
-#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
-#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
-#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
-#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
-#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
-#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
-#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
-#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
-#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
-#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
-#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
-#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
-#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
-#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
-#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
-#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
-#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
-#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
-#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
-#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
-#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
-#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
-#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
-#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
-#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
-#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
-#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
-#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
-
-/*DMA traffic control registers */
-#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */
-#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */
-#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */
-#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SICA_SYSCR Masks */
-#define COREB_SRAM_INIT 0x0020
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
-#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
-#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
-#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
-#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
-#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
-#define SWRST_OCCURRED 0x8000 /* SWRST Status */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15 */
-#define Peripheral_IVG(Per_number, IVG_number) \
- ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
- /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
- /* r0.h = hi(Peripheral_IVG(62, 10)); */
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define DLEN_10 0x00000800 /* Data Length = 10 Bits */
-#define DLEN_11 0x00001000 /* Data Length = 11 Bits */
-#define DLEN_12 0x00001800 /* Data Length = 12 Bits */
-#define DLEN_13 0x00002000 /* Data Length = 13 Bits */
-#define DLEN_14 0x00002800 /* Data Length = 14 Bits */
-#define DLEN_15 0x00003000 /* Data Length = 15 Bits */
-#define DLEN_16 0x00003800 /* Data Length = 16 Bits */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-#define TIMEN3 0x0008
-#define TIMEN4 0x0010
-#define TIMEN5 0x0020
-#define TIMEN6 0x0040
-#define TIMEN7 0x0080
-#define TIMEN8 0x0001
-#define TIMEN9 0x0002
-#define TIMEN10 0x0004
-#define TIMEN11 0x0008
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-#define TIMEN3_P 0x03
-#define TIMEN4_P 0x04
-#define TIMEN5_P 0x05
-#define TIMEN6_P 0x06
-#define TIMEN7_P 0x07
-#define TIMEN8_P 0x00
-#define TIMEN9_P 0x01
-#define TIMEN10_P 0x02
-#define TIMEN11_P 0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-#define TIMDIS3 0x0008
-#define TIMDIS4 0x0010
-#define TIMDIS5 0x0020
-#define TIMDIS6 0x0040
-#define TIMDIS7 0x0080
-#define TIMDIS8 0x0001
-#define TIMDIS9 0x0002
-#define TIMDIS10 0x0004
-#define TIMDIS11 0x0008
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-#define TIMDIS3_P 0x03
-#define TIMDIS4_P 0x04
-#define TIMDIS5_P 0x05
-#define TIMDIS6_P 0x06
-#define TIMDIS7_P 0x07
-#define TIMDIS8_P 0x00
-#define TIMDIS9_P 0x01
-#define TIMDIS10_P 0x02
-#define TIMDIS11_P 0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x00000001
-#define TIMIL1 0x00000002
-#define TIMIL2 0x00000004
-#define TIMIL3 0x00000008
-#define TIMIL4 0x00010000
-#define TIMIL5 0x00020000
-#define TIMIL6 0x00040000
-#define TIMIL7 0x00080000
-#define TIMIL8 0x0001
-#define TIMIL9 0x0002
-#define TIMIL10 0x0004
-#define TIMIL11 0x0008
-#define TOVF_ERR0 0x00000010
-#define TOVF_ERR1 0x00000020
-#define TOVF_ERR2 0x00000040
-#define TOVF_ERR3 0x00000080
-#define TOVF_ERR4 0x00100000
-#define TOVF_ERR5 0x00200000
-#define TOVF_ERR6 0x00400000
-#define TOVF_ERR7 0x00800000
-#define TOVF_ERR8 0x0010
-#define TOVF_ERR9 0x0020
-#define TOVF_ERR10 0x0040
-#define TOVF_ERR11 0x0080
-#define TRUN0 0x00001000
-#define TRUN1 0x00002000
-#define TRUN2 0x00004000
-#define TRUN3 0x00008000
-#define TRUN4 0x10000000
-#define TRUN5 0x20000000
-#define TRUN6 0x40000000
-#define TRUN7 0x80000000
-#define TRUN8 0x1000
-#define TRUN9 0x2000
-#define TRUN10 0x4000
-#define TRUN11 0x8000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TIMIL3_P 0x03
-#define TIMIL4_P 0x10
-#define TIMIL5_P 0x11
-#define TIMIL6_P 0x12
-#define TIMIL7_P 0x13
-#define TIMIL8_P 0x00
-#define TIMIL9_P 0x01
-#define TIMIL10_P 0x02
-#define TIMIL11_P 0x03
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TOVF_ERR3_P 0x07
-#define TOVF_ERR4_P 0x14
-#define TOVF_ERR5_P 0x15
-#define TOVF_ERR6_P 0x16
-#define TOVF_ERR7_P 0x17
-#define TOVF_ERR8_P 0x04
-#define TOVF_ERR9_P 0x05
-#define TOVF_ERR10_P 0x06
-#define TOVF_ERR11_P 0x07
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-#define TRUN3_P 0x0F
-#define TRUN4_P 0x1C
-#define TRUN5_P 0x1D
-#define TRUN6_P 0x1E
-#define TRUN7_P 0x1F
-#define TRUN8_P 0x0C
-#define TRUN9_P 0x0D
-#define TRUN10_P 0x0E
-#define TRUN11_P 0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif /* _DEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
deleted file mode 100644
index 13647c71f1c7..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/dma.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 36
-
-/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
-#define MAX_DMA_SUSPEND_CHANNELS 32
-
-#define CH_PPI0 0
-#define CH_PPI (CH_PPI0)
-#define CH_PPI1 1
-#define CH_SPORT0_RX 12
-#define CH_SPORT0_TX 13
-#define CH_SPORT1_RX 14
-#define CH_SPORT1_TX 15
-#define CH_SPI 16
-#define CH_UART_RX 17
-#define CH_UART_TX 18
-#define CH_MEM_STREAM0_DEST 24 /* TX */
-#define CH_MEM_STREAM0_SRC 25 /* RX */
-#define CH_MEM_STREAM1_DEST 26 /* TX */
-#define CH_MEM_STREAM1_SRC 27 /* RX */
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-#define CH_IMEM_STREAM0_DEST 32
-#define CH_IMEM_STREAM0_SRC 33
-#define CH_IMEM_STREAM1_DEST 34
-#define CH_IMEM_STREAM1_SRC 35
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
deleted file mode 100644
index f9f8b2adf4ba..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PF16 16
-#define GPIO_PF17 17
-#define GPIO_PF18 18
-#define GPIO_PF19 19
-#define GPIO_PF20 20
-#define GPIO_PF21 21
-#define GPIO_PF22 22
-#define GPIO_PF23 23
-#define GPIO_PF24 24
-#define GPIO_PF25 25
-#define GPIO_PF26 26
-#define GPIO_PF27 27
-#define GPIO_PF28 28
-#define GPIO_PF29 29
-#define GPIO_PF30 30
-#define GPIO_PF31 31
-#define GPIO_PF32 32
-#define GPIO_PF33 33
-#define GPIO_PF34 34
-#define GPIO_PF35 35
-#define GPIO_PF36 36
-#define GPIO_PF37 37
-#define GPIO_PF38 38
-#define GPIO_PF39 39
-#define GPIO_PF40 40
-#define GPIO_PF41 41
-#define GPIO_PF42 42
-#define GPIO_PF43 43
-#define GPIO_PF44 44
-#define GPIO_PF45 45
-#define GPIO_PF46 46
-#define GPIO_PF47 47
-
-#define PORT_FIO0 GPIO_PF0
-#define PORT_FIO1 GPIO_PF16
-#define PORT_FIO2 GPIO_PF32
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
deleted file mode 100644
index d6998520f70f..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF561_IRQ_H_
-#define _BF561_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
-#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
-#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
-#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
-#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
-#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
-#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
-#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
-#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
-#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
-#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
-#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
-#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
-#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
-#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
-#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
-#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
-#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
-#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
-#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
-#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
-#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
-#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
-#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
-#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
-#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
-#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
-#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
-#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
-#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
-#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
-#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
-#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
-#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
-#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
-#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
-#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
-#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
-#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
-#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
-#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
-#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
-#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
-#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
-#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
-#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
-#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
-#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
-#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
-#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
-#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
-#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
-#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
-#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
-#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
-#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
-
-#define SYS_IRQS 71
-
-#define IRQ_PF0 73
-#define IRQ_PF1 74
-#define IRQ_PF2 75
-#define IRQ_PF3 76
-#define IRQ_PF4 77
-#define IRQ_PF5 78
-#define IRQ_PF6 79
-#define IRQ_PF7 80
-#define IRQ_PF8 81
-#define IRQ_PF9 82
-#define IRQ_PF10 83
-#define IRQ_PF11 84
-#define IRQ_PF12 85
-#define IRQ_PF13 86
-#define IRQ_PF14 87
-#define IRQ_PF15 88
-#define IRQ_PF16 89
-#define IRQ_PF17 90
-#define IRQ_PF18 91
-#define IRQ_PF19 92
-#define IRQ_PF20 93
-#define IRQ_PF21 94
-#define IRQ_PF22 95
-#define IRQ_PF23 96
-#define IRQ_PF24 97
-#define IRQ_PF25 98
-#define IRQ_PF26 99
-#define IRQ_PF27 100
-#define IRQ_PF28 101
-#define IRQ_PF29 102
-#define IRQ_PF30 103
-#define IRQ_PF31 104
-#define IRQ_PF32 105
-#define IRQ_PF33 106
-#define IRQ_PF34 107
-#define IRQ_PF35 108
-#define IRQ_PF36 109
-#define IRQ_PF37 110
-#define IRQ_PF38 111
-#define IRQ_PF39 112
-#define IRQ_PF40 113
-#define IRQ_PF41 114
-#define IRQ_PF42 115
-#define IRQ_PF43 116
-#define IRQ_PF44 117
-#define IRQ_PF45 118
-#define IRQ_PF46 119
-#define IRQ_PF47 120
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF47 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA1_ERROR_POS 4
-#define IRQ_DMA2_ERROR_POS 8
-#define IRQ_IMDMA_ERROR_POS 12
-#define IRQ_PPI0_ERROR_POS 16
-#define IRQ_PPI1_ERROR_POS 20
-#define IRQ_SPORT0_ERROR_POS 24
-#define IRQ_SPORT1_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS 0
-#define IRQ_UART_ERROR_POS 4
-#define IRQ_RESERVED_ERROR_POS 8
-#define IRQ_DMA1_0_POS 12
-#define IRQ_DMA1_1_POS 16
-#define IRQ_DMA1_2_POS 20
-#define IRQ_DMA1_3_POS 24
-#define IRQ_DMA1_4_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS 0
-#define IRQ_DMA1_6_POS 4
-#define IRQ_DMA1_7_POS 8
-#define IRQ_DMA1_8_POS 12
-#define IRQ_DMA1_9_POS 16
-#define IRQ_DMA1_10_POS 20
-#define IRQ_DMA1_11_POS 24
-#define IRQ_DMA2_0_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS 0
-#define IRQ_DMA2_2_POS 4
-#define IRQ_DMA2_3_POS 8
-#define IRQ_DMA2_4_POS 12
-#define IRQ_DMA2_5_POS 16
-#define IRQ_DMA2_6_POS 20
-#define IRQ_DMA2_7_POS 24
-#define IRQ_DMA2_8_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS 0
-#define IRQ_DMA2_10_POS 4
-#define IRQ_DMA2_11_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_TIMER8_POS 12
-#define IRQ_TIMER9_POS 16
-#define IRQ_TIMER10_POS 20
-#define IRQ_TIMER11_POS 24
-#define IRQ_PROG0_INTA_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS 0
-#define IRQ_PROG1_INTA_POS 4
-#define IRQ_PROG1_INTB_POS 8
-#define IRQ_PROG2_INTA_POS 12
-#define IRQ_PROG2_INTB_POS 16
-#define IRQ_DMA1_WRRD0_POS 20
-#define IRQ_DMA1_WRRD1_POS 24
-#define IRQ_DMA2_WRRD0_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS 0
-#define IRQ_IMDMA_WRRD0_POS 4
-#define IRQ_IMDMA_WRRD1_POS 8
-#define IRQ_WDTIMER_POS 12
-#define IRQ_RESERVED_1_POS 16
-#define IRQ_RESERVED_2_POS 20
-#define IRQ_SUPPLE_0_POS 24
-#define IRQ_SUPPLE_1_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
deleted file mode 100644
index 4cc91995f781..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * BF561 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF561 processors */
-
-#define COREA_L1_CODE_START 0xFFA00000
-#define COREA_L1_DATA_A_START 0xFF800000
-#define COREA_L1_DATA_B_START 0xFF900000
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define L1_CODE_START COREA_L1_CODE_START
-#define L1_DATA_A_START COREA_L1_DATA_A_START
-#define L1_DATA_B_START COREA_L1_DATA_B_START
-
-#define L1_CODE_LENGTH 0x4000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/*
- * If we are in SMP mode, then the cache settings of Core B will match
- * the settings of Core A. If we aren't, then we assume Core B is not
- * using any cache. This allows the rest of the kernel to work with
- * the core in either mode as we are only loading user code into it and
- * it is the user's problem to make sure they aren't doing something
- * stupid there.
- *
- * Note that we treat the L1 code region as a contiguous blob to make
- * the rest of the kernel simpler. Easier to check one region than a
- * bunch of small ones. Again, possible misbehavior here is the fault
- * of the user -- don't try to use memory that doesn't exist.
- */
-#ifdef CONFIG_SMP
-# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
-# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
-# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
-#else
-# define COREB_L1_CODE_LENGTH 0x14000
-# define COREB_L1_DATA_A_LENGTH 0x8000
-# define COREB_L1_DATA_B_LENGTH 0x8000
-#endif
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#define L2_LENGTH 0x20000
-
-/* Scratch Pad Memory */
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#ifdef CONFIG_SMP
-
-/*
- * The following macros both return the address of the PDA for the
- * current core.
- *
- * In its first safe (and hairy) form, the macro neither clobbers any
- * register aside of the output Preg, nor uses the stack, since it
- * could be called with an invalid stack pointer, or the current stack
- * space being uncovered by any CPLB (e.g. early exception handling).
- *
- * The constraints on the second form are a bit relaxed, and the code
- * is allowed to use the specified Dreg for determining the PDA
- * address to be returned into Preg.
- */
-# define GET_PDA_SAFE(preg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- preg = [preg]; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- if cc jump 2f; \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if !cc jump 3f; \
-1: \
- /* preg = 0x0; */ \
- cc = !cc; /* restore cc to 0 */ \
- jump 4f; \
-2: \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if cc jump 4f; \
- /* preg = 0x1000000; */ \
- cc = !cc; /* restore cc to 1 */ \
-3: \
- preg = [preg]; \
-4:
-
-# define GET_PDA(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- cc = bittst(dreg, 0); \
- if !cc jump 1f; \
- preg = [preg]; \
-1: \
-
-# define GET_CPUID(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- dreg = ROT dreg BY -1; \
- dreg = CC;
-
-# ifndef __ASSEMBLY__
-
-# include <asm/processor.h>
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
-}
-
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(blackfin_core_id());
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SMP */
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
deleted file mode 100644
index 00bdacee9cc2..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SMP
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-#include <mach/irq.h>
-
-#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
-#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
-
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
- bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
-}
-#define bfin_iwr_restore bfin_iwr_restore
-
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
- *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#define bfin_iwr_save bfin_iwr_save
-
-static inline void
-bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
- IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
-}
-
-#endif
-
-#endif
-
-#include <mach-common/pll.h>
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h
deleted file mode 100644
index 2339ffd0dde8..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/portmux.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DONTCARE)
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DONTCARE)
-#define P_PPI0_D5 (P_DONTCARE)
-#define P_PPI0_D6 (P_DONTCARE)
-#define P_PPI0_D7 (P_DONTCARE)
-#define P_PPI1_CLK (P_DONTCARE)
-#define P_PPI1_FS1 (P_DONTCARE)
-#define P_PPI1_FS2 (P_DONTCARE)
-#define P_PPI1_FS3 (P_DONTCARE)
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0 (P_DONTCARE)
-#define P_PPI1_D1 (P_DONTCARE)
-#define P_PPI1_D2 (P_DONTCARE)
-#define P_PPI1_D3 (P_DONTCARE)
-#define P_PPI1_D4 (P_DONTCARE)
-#define P_PPI1_D5 (P_DONTCARE)
-#define P_PPI1_D6 (P_DONTCARE)
-#define P_PPI1_D7 (P_DONTCARE)
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11 (P_DONTCARE)
-#define P_TMR10 (P_DONTCARE)
-#define P_TMR9 (P_DONTCARE)
-#define P_TMR8 (P_DONTCARE)
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
deleted file mode 100644
index 346c60589be6..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BF561_SMP
-#define _MACH_BF561_SMP
-
-/* This header has to stand alone to avoid circular deps */
-
-struct task_struct;
-
-void platform_init_cpus(void);
-
-void platform_prepare_cpus(unsigned int max_cpus);
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
-
-void platform_secondary_init(unsigned int cpu);
-
-void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
-
-void platform_send_ipi(cpumask_t callmap, int irq);
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq);
-
-void platform_clear_ipi(unsigned int cpu, int irq);
-
-void bfin_local_timer_setup(void);
-
-#endif /* !_MACH_BF561_SMP */
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
deleted file mode 100644
index 7ee9262fe132..000000000000
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
- ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
- ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
- ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
- ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
- ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
- ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
- ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
- ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
- ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
- ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
- ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
- ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
- ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
- ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
- ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
- ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
- ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
- ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
- ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
- ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
- ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
- ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
- ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
- ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
- ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
- ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
- ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
- ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
- ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
- ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
- ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
- ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
- ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
- ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
- ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
- ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
- (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
- (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
deleted file mode 100644
index 01e5408620ac..000000000000
--- a/arch/blackfin/mach-bf561/secondary.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * BF561 coreB bootstrap file
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-
-/*
- * This code must come first as CoreB is hardcoded (in hardware)
- * to start at the beginning of its L1 instruction memory.
- */
-.section .l1.text.head
-
-/* Lay the initial stack into the L1 scratch area of Core B */
-#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-ENTRY(_coreb_trampoline_start)
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda_coreb;
- p1.h = _initial_pda_coreb;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- /* This section keeps the processor in supervisor mode
- * during core B startup. Branches to the idle task.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _coreb_start;
- p1.h = _coreb_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
- r0 = EVT_IVG15 (z);
- sti r0;
-
- raise 15;
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
- reti = p0;
-#if defined(ANOMALY_05000281)
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(_coreb_trampoline_start)
-
-#ifdef CONFIG_HOTPLUG_CPU
-.section ".text"
-ENTRY(_coreb_die)
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- R0 = IWR_DISABLE_ALL;
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
- SSYNC;
-
- p0.h = hi(COREB_L1_CODE_START);
- p0.l = lo(COREB_L1_CODE_START);
- jump (p0);
-ENDPROC(_coreb_die)
-#endif
-
-__INIT
-ENTRY(_coreb_start)
- [--sp] = reti;
-
- p0.l = lo(WDOGB_CTL);
- p0.h = hi(WDOGB_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0; /* Clear the watchdog. */
- ssync;
-
- /*
- * switch to IDLE stack.
- */
- p0.l = _secondary_stack;
- p0.h = _secondary_stack;
- sp = [p0];
- usp = sp;
- fp = sp;
-#ifdef CONFIG_HOTPLUG_CPU
- p0.l = _hotplug_coreb;
- p0.h = _hotplug_coreb;
- r0 = [p0];
- cc = BITTST(r0, 0);
- if cc jump 3f;
-#endif
- sp += -12;
- call _init_pda
- sp += 12;
-#ifdef CONFIG_HOTPLUG_CPU
-3:
-#endif
- call _secondary_start_kernel;
-.L_exit:
- jump.s .L_exit;
-ENDPROC(_coreb_start)
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
deleted file mode 100644
index 8c0c80fd1a45..000000000000
--- a/arch/blackfin/mach-bf561/smp.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <asm/smp.h>
-#include <asm/dma.h>
-#include <asm/time.h>
-
-static DEFINE_SPINLOCK(boot_lock);
-
-/*
- * platform_init_cpus() - Tell the world about how many cores we
- * have. This is called while setting up the architecture support
- * (setup_arch()), so don't be too demanding here with respect to
- * available kernel services.
- */
-
-void __init platform_init_cpus(void)
-{
- struct cpumask mask;
-
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_possible(&mask);
-}
-
-void __init platform_prepare_cpus(unsigned int max_cpus)
-{
- struct cpumask mask;
-
- bfin_relocate_coreb_l1_mem();
-
- /* Both cores ought to be present on a bf561! */
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_present(&mask);
-}
-
-int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
-{
- return -EINVAL;
-}
-
-void platform_secondary_init(unsigned int cpu)
-{
- /* Clone setup for peripheral interrupt sources from CoreA. */
- bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
- bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
- SSYNC();
-
- /* Clone setup for IARs from CoreA. */
- bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
- bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
- bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
- bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
- bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
- bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
- bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
- bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
- bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
- bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
- SSYNC();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
-}
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- unsigned long timeout;
-
- printk(KERN_INFO "Booting Core B.\n");
-
- spin_lock(&boot_lock);
-
- if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
- /* CoreB already running, sending ipi to wakeup it */
- smp_send_reschedule(cpu);
- } else {
- /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
- bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
- SSYNC();
- }
-
- timeout = jiffies + HZ;
- /* release the lock and let coreb run */
- spin_unlock(&boot_lock);
- while (time_before(jiffies, timeout)) {
- if (cpu_online(cpu))
- break;
- udelay(100);
- barrier();
- }
-
- if (cpu_online(cpu)) {
- return 0;
- } else
- panic("CPU%u: processor failed to boot\n", cpu);
-}
-
-static const char supple0[] = "IRQ_SUPPLE_0";
-static const char supple1[] = "IRQ_SUPPLE_1";
-void __init platform_request_ipi(int irq, void *handler)
-{
- int ret;
- const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
-
- ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, name, handler);
- if (ret)
- panic("Cannot request %s for IPI service", name);
-}
-
-void platform_send_ipi(cpumask_t callmap, int irq)
-{
- unsigned int cpu;
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
-
- for_each_cpu(cpu, &callmap) {
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
- }
-}
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-void platform_clear_ipi(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-/*
- * Setup core B's local core timer.
- * In SMP, core timer is used for clock event device.
- */
-void bfin_local_timer_setup(void)
-{
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
- struct irq_chip *chip = irq_data_get_irq_chip(data);
-
- bfin_coretmr_init();
- bfin_coretmr_clockevent_init();
-
- chip->irq_unmask(data);
-#else
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-#endif
-
-}
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
deleted file mode 100644
index 7d6a8b8926ba..000000000000
--- a/arch/blackfin/mach-bf609/Kconfig
+++ /dev/null
@@ -1,1684 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF60x
- def_bool y
- depends on (BF609)
- select IRQ_PREFLOW_FASTEOI
-
-if (BF60x)
-
-source "arch/blackfin/mach-bf609/boards/Kconfig"
-
-menu "BF609 Specific Configuration"
-
-config SEC_IRQ_PRIORITY_LEVELS
- int "SEC interrupt priority levels"
- default 7
- range 0 7
- help
- Divide the total number of interrupt priority levels into sub-levels.
- There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
-
-config L1_PARITY_CHECK
- bool "Enable L1 parity check"
- default n
- help
- Enable the L1 parity check in L1 sram. A fault event is raised
- when L1 parity error is found.
-
-comment "System Cross Bar Priority Assignment"
-
-config SCB_PRIORITY
- bool "Init System Cross Bar Priority"
- default n
-
-menuconfig SCB0_MI0
- bool "SCB0 Master Interface 0 (DDR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI0
-
-config SCB0_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI0
-
-menuconfig SCB0_MI1
- bool "SCB0 Master Interface 1 (SMC)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI1
-
-config SCB0_MI1_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI1
-
-menuconfig SCB0_MI2
- bool "SCB0 Master Interface 2 (Data L2)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI2
-
-config SCB0_MI2_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI2
-
-menuconfig SCB0_MI3
- bool "SCB0 Master Interface 3 (L1A)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI3
-
-config SCB0_MI3_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI3
-
-menuconfig SCB0_MI4
- bool "SCB0 Master Interface 4 (L1B)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI4
-
-config SCB0_MI4_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI4
-
-menuconfig SCB0_MI5
- bool "SCB0 Master Interface 5 (SMMR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MMR0 -- 1
- MMR1 -- 3
- SCB2 -- 10
- SCB4 -- 12
-
-if SCB0_MI5
-
-config SCB0_MI5_SLOT0
- int "Slot 0 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT1
- int "Slot 1 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT2
- int "Slot 2 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT3
- int "Slot 3 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT5
- int "Slot 5 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT7
- int "Slot 7 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT8
- int "Slot 8 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT9
- int "Slot 9 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT10
- int "Slot 10 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT12
- int "Slot 12 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT14
- int "Slot 14 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT15
- int "Slot 15 slave interface id"
- default 12
- range 0 13
-
-endif # SCB0_MI5
-
-menuconfig SCB1_MI0
- bool "SCB1 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- SPORT0A -- 0
- SPORT0B -- 1
- SPORT1A -- 2
- SPORT1B -- 3
- SPORT2A -- 4
- SPORT2B -- 5
- SPI0TX -- 6
- SPI0RX -- 7
- SPI1TX -- 8
- SPI1RX -- 9
-
-if SCB1_MI0
-
-config SCB1_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 9
-
-config SCB1_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 9
-
-config SCB1_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 8
- range 0 9
-
-config SCB1_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 9
- range 0 9
-
-config SCB1_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB1_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB1_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB1_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-endif # SCB1_MI0
-
-menuconfig SCB2_MI0
- bool "SCB2 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- RSI -- 0
- SDU DMA -- 1
- SDU -- 2
- EMAC0 -- 3
- EMAC1 -- 4
-
-if SCB2_MI0
-
-config SCB2_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB2_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB2_MI0
-
-menuconfig SCB3_MI0
- bool "SCB3 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- LP0 -- 0
- LP1 -- 1
- LP2 -- 2
- LP3 -- 3
- UART0TX -- 4
- UART0RX -- 5
- UART1TX -- 4
- UART1RX -- 5
-
-if SCB3_MI0
-
-config SCB3_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB3_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB3_MI0
-
-menuconfig SCB4_MI0
- bool "SCB4 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MDA21 -- 0
- MDA22 -- 1
- MDA23 -- 2
- MDA24 -- 3
- MDA25 -- 4
- MDA26 -- 5
- MDA27 -- 6
- MDA28 -- 7
-
-if SCB4_MI0
-
-config SCB4_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB4_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB4_MI0
-
-menuconfig SCB5_MI0
- bool "SCB5 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI0 MDA29 -- 0
- PPI0 MDA30 -- 1
- PPI2 MDA31 -- 2
- PPI2 MDA32 -- 3
-
-if SCB5_MI0
-
-config SCB5_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB5_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB5_MI0
-
-menuconfig SCB6_MI0
- bool "SCB6 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI1 MDA33 -- 0
- PPI1 MDA34 -- 1
-
-if SCB6_MI0
-
-config SCB6_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 1
-
-config SCB6_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 1
- range 0 1
-
-endif # SCB6_MI0
-
-menuconfig SCB7_MI0
- bool "SCB7 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PIXC0 -- 0
- PIXC1 -- 1
- PIXC2 -- 2
-
-if SCB7_MI0
-
-config SCB7_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 2
-
-config SCB7_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 2
- range 0 2
-
-endif # SCB7_MI0
-
-menuconfig SCB8_MI0
- bool "SCB8 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP CPDOB -- 0
- PVP CPDOC -- 1
- PVP CPCO -- 2
- PVP CPCI -- 3
-
-if SCB8_MI0
-
-config SCB8_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB8_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB8_MI0
-
-menuconfig SCB9_MI0
- bool "SCB9 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP MPDO -- 0
- PVP MPDI -- 1
- PVP MPCO -- 2
- PVP MPCI -- 3
- PVP CPDOA -- 4
-
-if SCB9_MI0
-
-config SCB9_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB9_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB9_MI0
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
deleted file mode 100644
index 60ffaf85d303..000000000000
--- a/arch/blackfin/mach-bf609/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# arch/blackfin/mach-bf609/Makefile
-#
-
-obj-y := dma.o clock.o ints-priority.o
-obj-$(CONFIG_PM) += pm.o dpm.o
-obj-$(CONFIG_SCB_PRIORITY) += scb.o
diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig
deleted file mode 100644
index 350154b2a3ee..000000000000
--- a/arch/blackfin/mach-bf609/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN609_EZKIT
- help
- Select your board!
-
-config BFIN609_EZKIT
- bool "BF609-EZKIT"
- help
- BFIN609-EZKIT board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile
deleted file mode 100644
index 11f98b0882ea..000000000000
--- a/arch/blackfin/mach-bf609/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf609/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
deleted file mode 100644
index 51157a255824..000000000000
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ /dev/null
@@ -1,2191 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/spi/adi_spi3.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF609-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
-#include <linux/stmmac.h>
-#include <linux/phy.h>
-
-static struct stmmac_mdio_bus_data phy_private_data = {
- .phy_mask = 1,
-};
-
-static struct stmmac_dma_cfg eth_dma_cfg = {
- .pbl = 2,
-};
-
-int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
-{
- bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
- return 0;
-}
-
-static struct plat_stmmacenet_data eth_private_data = {
- .has_gmac = 1,
- .bus_id = 0,
- .enh_desc = 1,
- .phy_addr = 1,
- .mdio_bus_data = &phy_private_data,
- .dma_cfg = &eth_dma_cfg,
- .force_thresh_dma_mode = 1,
- .interface = PHY_INTERFACE_MODE_RMII,
- .init = stmmac_ptp_clk_init,
-};
-
-static struct platform_device bfin_eth_device = {
- .name = "stmmaceth",
- .id = 0,
- .num_resources = 2,
- .resource = (struct resource[]) {
- {
- .start = EMAC0_MACCFG,
- .end = EMAC0_MACCFG + 0x1274,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "macirq",
- .start = IRQ_EMAC0_STAT,
- .end = IRQ_EMAC0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- },
- .dev = {
- .power.can_wakeup = 1,
- .platform_data = &eth_private_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_REVID,
- .end = UART0_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTD_FER,
- .end = PORTD_FER+2,
- .flags = IORESOURCE_REG,
- },
- {
- .start = PORTD_MUX,
- .end = PORTD_MUX+3,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_STAT,
- .end = IRQ_UART0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PD10,
- .end = GPIO_PD10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PD9,
- .end = GPIO_PD9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX,
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- P_UART0_RTS, P_UART0_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_REVID,
- .end = UART1_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTG_FER_SET,
- .end = PORTG_FER_SET+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_STAT,
- .end = IRQ_UART1_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PG13,
- .end = GPIO_PG13,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PG10,
- .end = GPIO_PG10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFCC1000,
- .end = 0xFFCC1398,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_STAT,
- .end = IRQ_USB_STAT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 0,
- .dma = 1,
- .num_eps = 16,
- .dma_channels = 8,
- .clkin = 48, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC00A00,
- .end = 0xFFC00FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_STAT,
- .end = IRQ_CAN0_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bfin_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bfin_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_nand_device = {
- .name = "bfin-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_nand_resources),
- .resource = bfin_nand_resources,
- .dev = {
- .platform_data = &bfin_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bfin_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-int bf609_nor_flash_init(struct platform_device *pdev)
-{
-#define CONFIG_SMC_GCTL_VAL 0x00000010
-
- bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
- bfin_write32(SMC_B0CTL, 0x01002011);
- bfin_write32(SMC_B0TIM, 0x08170977);
- bfin_write32(SMC_B0ETIM, 0x00092231);
- return 0;
-}
-
-void bf609_nor_flash_exit(struct platform_device *pdev)
-{
- bfin_write32(SMC_GCTL, 0);
-}
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .init = bf609_nor_flash_init,
- .exit = bf609_nor_flash_exit,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0xb0000000,
- .end = 0xb0ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (w25q32) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x00180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "w25q32",
-};
-
-static struct adi_spi3_chip spi_flash_chip_info = {
- .enable_dma = true, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
-static struct adi_spi3_chip spidev_chip_info = {
- .enable_dma = true,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
-static struct platform_device bfin_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-#include <asm/bfin_sport3.h>
-static struct resource bfin_snd_resources[] = {
- {
- .start = SPORT0_CTL_A,
- .end = SPORT0_CTL_A,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = SPORT0_CTL_B,
- .end = SPORT0_CTL_B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_SPORT0_TX_STAT,
- .end = IRQ_SPORT0_TX_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX_STAT,
- .end = IRQ_SPORT0_RX_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const unsigned short bfin_snd_pin[] = {
- P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
- P_SPORT0_BFS, P_SPORT0_BD0, 0,
-};
-
-static struct bfin_snd_platform_data bfin_snd_data = {
- .pin_req = bfin_snd_pin,
-};
-
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .num_resources = ARRAY_SIZE(bfin_snd_resources),
- .resource = bfin_snd_resources,
- .dev = {
- .platform_data = &bfin_snd_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.76",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-static struct platform_device adau1761_device = {
- .name = "bfin-eval-adau1x61",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
-#include <sound/adau17x1.h>
-static struct adau1761_platform_data adau1761_info = {
- .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
- .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
- P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
- P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
-#endif
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PE4;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
- | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- .blank_pixels = 4,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-#include <media/i2c/adv7842.h>
-
-static struct v4l2_input adv7842_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 3,
- .name = "VGA",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 4,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
-};
-
-static struct bcap_route adv7842_routes[] = {
- {
- .input = 3,
- .output = 0,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
- },
- {
- .input = 4,
- .output = 0,
- },
- {
- .input = 2,
- .output = 0,
- },
- {
- .input = 1,
- .output = 0,
- },
- {
- .input = 0,
- .output = 1,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
- | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- },
-};
-
-static struct adv7842_output_format adv7842_opf[] = {
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
- .blank_data = 1,
- .insert_av_codes = 1,
- },
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
- .blank_data = 1,
- },
-};
-
-static struct adv7842_platform_data adv7842_data = {
- .opf = adv7842_opf,
- .num_opf = ARRAY_SIZE(adv7842_opf),
- .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
- .prim_mode = ADV7842_PRIM_MODE_SDP,
- .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
- .hdmi_free_run_enable = 1,
- .sdp_free_run_auto = 1,
- .llc_dll_phase = 0x10,
- .i2c_sdp_io = 0x40,
- .i2c_sdp = 0x41,
- .i2c_cp = 0x42,
- .i2c_vdp = 0x43,
- .i2c_afe = 0x44,
- .i2c_hdmi = 0x45,
- .i2c_repeater = 0x46,
- .i2c_edid = 0x47,
- .i2c_infoframe = 0x48,
- .i2c_cec = 0x49,
- .i2c_avlink = 0x4a,
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = adv7842_inputs,
- .num_inputs = ARRAY_SIZE(adv7842_inputs),
- .routes = adv7842_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7842",
- .addr = 0x20,
- .platform_data = (void *)&adv7842_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_display.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req_disp[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req_disp,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
-#include <media/i2c/adv7511.h>
-
-static struct v4l2_output adv7511_outputs[] = {
- {
- .index = 0,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
-};
-
-static struct disp_route adv7511_routes[] = {
- {
- .output = 0,
- },
-};
-
-static struct adv7511_platform_data adv7511_data = {
- .edid_addr = 0x7e,
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7511_outputs,
- .num_outputs = ARRAY_SIZE(adv7511_outputs),
- .routes = adv7511_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7511",
- .addr = 0x39,
- .platform_data = (void *)&adv7511_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
- | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
-#include <media/i2c/adv7343.h>
-
-static struct v4l2_output adv7343_outputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
-
-};
-
-static struct disp_route adv7343_routes[] = {
- {
- .output = ADV7343_COMPOSITE_ID,
- },
- {
- .output = ADV7343_SVIDEO_ID,
- },
- {
- .output = ADV7343_COMPONENT_ID,
- },
-};
-
-static struct adv7343_platform_data adv7343_data = {
- .mode_config = {
- .sleep_mode = false,
- .pll_control = false,
- .dac_1 = true,
- .dac_2 = true,
- .dac_3 = true,
- .dac_4 = true,
- .dac_5 = true,
- .dac_6 = true,
- },
- .sd_config = {
- .sd_dac_out1 = false,
- .sd_dac_out2 = false,
- },
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7343_outputs,
- .num_outputs = ARRAY_SIZE(adv7343_outputs),
- .routes = adv7343_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7343",
- .addr = 0x2b,
- .platform_data = (void *)&adv7343_data,
- },
- .ppi_info = &ppi_info_disp,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
- | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-static struct platform_device bfin_display_device = {
- .name = "bfin_display",
- .dev = {
- .platform_data = &bfin_display_data,
- },
-};
-#endif
-
-#if defined(CONFIG_FB_BF609_NL8048) \
- || defined(CONFIG_FB_BF609_NL8048_MODULE)
-static struct resource nl8048_resources[] = {
- {
- .start = EPPI2_STAT,
- .end = EPPI2_STAT,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_EPPI2_CH0,
- .end = CH_EPPI2_CH0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_EPPI2_STAT,
- .end = IRQ_EPPI2_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-static struct platform_device bfin_fb_device = {
- .name = "bf609_nl8048",
- .num_resources = ARRAY_SIZE(nl8048_resources),
- .resource = nl8048_resources,
- .dev = {
- .platform_data = (void *)GPIO_PC15,
- },
-};
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
-#define BFIN_CRC_NAME "bfin-crc"
-
-static struct resource bfin_crc0_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM0_DEST_CRC0,
- .end = CH_MEM_STREAM0_DEST_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc0_device = {
- .name = BFIN_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crc0_resources),
- .resource = bfin_crc0_resources,
-};
-
-static struct resource bfin_crc1_resources[] = {
- {
- .start = REG_CRC1_CTL,
- .end = REG_CRC1_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC1_DCNTEXP,
- .end = IRQ_CRC1_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM1_SRC_CRC1,
- .end = CH_MEM_STREAM1_SRC_CRC1,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM1_DEST_CRC1,
- .end = CH_MEM_STREAM1_DEST_CRC1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc1_device = {
- .name = BFIN_CRC_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_crc1_resources),
- .resource = bfin_crc1_resources,
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
-#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
-#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
-
-static struct resource bfin_crypto_crc_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crypto_crc_device = {
- .name = BFIN_CRYPTO_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
- .resource = bfin_crypto_crc_resources,
- .dev = {
- .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_pint4_resources[] = {
- {
- .start = PINT4_MASK_SET,
- .end = PINT4_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT4,
- .end = IRQ_PINT4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint4_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_pint4_resources),
- .resource = bfin_pint4_resources,
-};
-
-static struct resource bfin_pint5_resources[] = {
- {
- .start = PINT5_MASK_SET,
- .end = PINT5_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT5,
- .end = IRQ_PINT5,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint5_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_pint5_resources),
- .resource = bfin_pint5_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_pin_base = GPIO_PB0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_pin_base = GPIO_PC0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 1,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 4,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 5,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PD9,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .controller_data = &spidev_chip_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI0_TX,
- .end = CH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI0_RX,
- .end = CH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI1_TX,
- .end = CH_SPI1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI1_RX,
- .end = CH_SPI1_RX,
- .flags = IORESOURCE_DMA,
- },
-
-};
-
-/* SPI controller data */
-static struct adi_spi3_master bf60x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master0 = {
- .name = "adi-spi3",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct adi_spi3_master bf60x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master1 = {
- .name = "adi-spi3",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_CLKDIV,
- .end = TWI0_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_CLKDIV,
- .end = TWI1_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
- .base = 120,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
- .base = 130,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
- .base = 140,
-};
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
- .base = 150,
-};
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
-static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
- .base = 160,
-};
-# endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- .platform_data = (void *)&adau1761_info
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- I2C_BOARD_INFO("mcp23017", 0x21),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch0
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x22),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch1
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x23),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch2
- },
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
- {
- I2C_BOARD_INFO("mcp23017", 0x26),
- .platform_data = (void *)&bfin_adv7842_soft_switch
- },
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
- {
- I2C_BOARD_INFO("mcp23017", 0x25),
- .platform_data = (void *)&bfin_adv7511_soft_switch
- },
-# endif
-#endif
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_pint4_device,
- &bfin_pint5_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
- &bfin_eth_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bfin_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bfin_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
- &bf60x_spi_master0,
- &bf60x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
- &bfin_crc0_device,
- &bfin_crc1_device,
-#endif
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
- &bfin_crypto_crc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
- &bfin_pcm,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
- &bfin_i2s,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
- &adau1761_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
- &bfin_display_device,
-#endif
-
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "8bit", "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "16bit", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit", "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
deleted file mode 100644
index 16e0b09e2197..000000000000
--- a/arch/blackfin/mach-bf609/clock.c
+++ /dev/null
@@ -1,409 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/clkdev.h>
-
-#include <asm/clocks.h>
-
-#define CGU0_CTL_DF (1 << 0)
-
-#define CGU0_CTL_MSEL_SHIFT 8
-#define CGU0_CTL_MSEL_MASK (0x7f << 8)
-
-#define CGU0_STAT_PLLEN (1 << 0)
-#define CGU0_STAT_PLLBP (1 << 1)
-#define CGU0_STAT_PLLLK (1 << 2)
-#define CGU0_STAT_CLKSALGN (1 << 3)
-#define CGU0_STAT_CCBF0 (1 << 4)
-#define CGU0_STAT_CCBF1 (1 << 5)
-#define CGU0_STAT_SCBF0 (1 << 6)
-#define CGU0_STAT_SCBF1 (1 << 7)
-#define CGU0_STAT_DCBF (1 << 8)
-#define CGU0_STAT_OCBF (1 << 9)
-#define CGU0_STAT_ADDRERR (1 << 16)
-#define CGU0_STAT_LWERR (1 << 17)
-#define CGU0_STAT_DIVERR (1 << 18)
-#define CGU0_STAT_WDFMSERR (1 << 19)
-#define CGU0_STAT_WDIVERR (1 << 20)
-#define CGU0_STAT_PLOCKERR (1 << 21)
-
-#define CGU0_DIV_CSEL_SHIFT 0
-#define CGU0_DIV_CSEL_MASK 0x0000001F
-#define CGU0_DIV_S0SEL_SHIFT 5
-#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
-#define CGU0_DIV_SYSSEL_SHIFT 8
-#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
-#define CGU0_DIV_S1SEL_SHIFT 13
-#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
-#define CGU0_DIV_DSEL_SHIFT 16
-#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
-#define CGU0_DIV_OSEL_SHIFT 22
-#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
-
-#define CLK(_clk, _devname, _conname) \
- { \
- .clk = &_clk, \
- .dev_id = _devname, \
- .con_id = _conname, \
- }
-
-#define NEEDS_INITIALIZATION 0x11
-
-static LIST_HEAD(clk_list);
-
-static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
-{
- u32 val2;
-
- val2 = bfin_read32(reg);
- val2 &= ~mask;
- val2 |= val;
- bfin_write32(reg, val2);
-}
-
-int wait_for_pll_align(void)
-{
- int i = 10000;
- while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
-
- if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
- printk(KERN_CRIT "fail to align clk\n");
- return -1;
- }
-
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->enable)
- ret = clk->ops->enable(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- if (!clk)
- return;
-
- if (clk->ops && clk->ops->disable)
- clk->ops->disable(clk);
-}
-EXPORT_SYMBOL(clk_disable);
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long ret = 0;
- if (clk->ops && clk->ops->get_rate)
- ret = clk->ops->get_rate(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- long ret = 0;
- if (clk->ops && clk->ops->round_rate)
- ret = clk->ops->round_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->set_rate)
- ret = clk->ops->set_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long vco_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
-unsigned long pll_get_rate(struct clk *clk)
-{
- u32 df;
- u32 msel;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 stat = bfin_read32(CGU0_STAT);
- if (stat & CGU0_STAT_PLLBP)
- return 0;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / (df + 1) * msel * 2;
-}
-
-unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- div = rate / clk->parent->rate;
- return clk->parent->rate * div;
-}
-
-int pll_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 msel;
- u32 stat = bfin_read32(CGU0_STAT);
- if (!(stat & CGU0_STAT_PLLEN))
- return -EBUSY;
- if (!(stat & CGU0_STAT_PLLLK))
- return -EBUSY;
- if (wait_for_pll_align())
- return -EBUSY;
- msel = rate / clk->parent->rate / 2;
- clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
- CGU0_CTL_MSEL_MASK);
- clk->rate = rate;
- return 0;
-}
-
-unsigned long cclk_get_rate(struct clk *clk)
-{
- if (clk->parent)
- return clk->parent->rate;
- else
- return 0;
-}
-
-unsigned long sys_clk_get_rate(struct clk *clk)
-{
- unsigned long drate;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
-
- if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
- drate = clk->parent->rate / (df + 1);
- drate *= msel;
- drate /= div;
- return drate;
- } else {
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / div;
- }
-}
-
-unsigned long dummy_get_rate(struct clk *clk)
-{
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate;
-}
-
-unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate;
- unsigned long drate;
- int i;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
-
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- max_rate = clk->parent->rate / (df + 1) * msel;
-
- if (rate > max_rate)
- return 0;
-
- for (i = 1; i < clk->mask; i++) {
- drate = max_rate / i;
- if (rate >= drate)
- return drate;
- }
- return 0;
-}
-
-int sys_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
-
- rate = clk_round_rate(clk, rate);
-
- if (!rate)
- return -EINVAL;
-
- div = (clk_get_rate(clk) * div) / rate;
-
- if (wait_for_pll_align())
- return -EBUSY;
- clk_reg_write_mask(CGU0_DIV, div << clk->shift,
- clk->mask);
- clk->rate = rate;
- return 0;
-}
-
-static struct clk_ops vco_ops = {
- .get_rate = vco_get_rate,
-};
-
-static struct clk_ops pll_ops = {
- .get_rate = pll_get_rate,
- .set_rate = pll_set_rate,
-};
-
-static struct clk_ops cclk_ops = {
- .get_rate = cclk_get_rate,
-};
-
-static struct clk_ops sys_clk_ops = {
- .get_rate = sys_clk_get_rate,
- .set_rate = sys_clk_set_rate,
- .round_rate = sys_clk_round_rate,
-};
-
-static struct clk_ops dummy_clk_ops = {
- .get_rate = dummy_get_rate,
-};
-
-static struct clk sys_clkin = {
- .name = "SYS_CLKIN",
- .rate = CONFIG_CLKIN_HZ,
- .ops = &vco_ops,
-};
-
-static struct clk pll_clk = {
- .name = "PLLCLK",
- .rate = 500000000,
- .parent = &sys_clkin,
- .ops = &pll_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk = {
- .name = "CCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_CSEL_MASK,
- .shift = CGU0_DIV_CSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk0 = {
- .name = "CCLK0",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk cclk1 = {
- .name = "CCLK1",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk sysclk = {
- .name = "SYSCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_SYSSEL_MASK,
- .shift = CGU0_DIV_SYSSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk sclk0 = {
- .name = "SCLK0",
- .rate = 500000000,
- .mask = CGU0_DIV_S0SEL_MASK,
- .shift = CGU0_DIV_S0SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk sclk1 = {
- .name = "SCLK1",
- .rate = 500000000,
- .mask = CGU0_DIV_S1SEL_MASK,
- .shift = CGU0_DIV_S1SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk dclk = {
- .name = "DCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_DSEL_MASK,
- .shift = CGU0_DIV_DSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
-};
-
-static struct clk oclk = {
- .name = "OCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_OSEL_MASK,
- .shift = CGU0_DIV_OSEL_SHIFT,
- .parent = &pll_clk,
-};
-
-static struct clk ethclk = {
- .name = "stmmaceth",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk ethpclk = {
- .name = "pclk",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk spiclk = {
- .name = "spi",
- .parent = &sclk1,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk_lookup bf609_clks[] = {
- CLK(sys_clkin, NULL, "SYS_CLKIN"),
- CLK(pll_clk, NULL, "PLLCLK"),
- CLK(cclk, NULL, "CCLK"),
- CLK(cclk0, NULL, "CCLK0"),
- CLK(cclk1, NULL, "CCLK1"),
- CLK(sysclk, NULL, "SYSCLK"),
- CLK(sclk0, NULL, "SCLK0"),
- CLK(sclk1, NULL, "SCLK1"),
- CLK(dclk, NULL, "DCLK"),
- CLK(oclk, NULL, "OCLK"),
- CLK(ethclk, NULL, "stmmaceth"),
- CLK(ethpclk, NULL, "pclk"),
- CLK(spiclk, NULL, "spi"),
-};
-
-int __init clk_init(void)
-{
- int i;
- struct clk *clkp;
- for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
- clkp = bf609_clks[i].clk;
- if (clkp->flags & NEEDS_INITIALIZATION)
- clk_get_rate(clkp);
- }
- clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
- return 0;
-}
diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c
deleted file mode 100644
index 1da4b38ac22c..000000000000
--- a/arch/blackfin/mach-bf609/dma.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
- (struct dma_register *) DMA29_NEXT_DESC_PTR,
- (struct dma_register *) DMA30_NEXT_DESC_PTR,
- (struct dma_register *) DMA31_NEXT_DESC_PTR,
- (struct dma_register *) DMA32_NEXT_DESC_PTR,
- (struct dma_register *) DMA33_NEXT_DESC_PTR,
- (struct dma_register *) DMA34_NEXT_DESC_PTR,
- (struct dma_register *) DMA35_NEXT_DESC_PTR,
- (struct dma_register *) DMA36_NEXT_DESC_PTR,
- (struct dma_register *) DMA37_NEXT_DESC_PTR,
- (struct dma_register *) DMA38_NEXT_DESC_PTR,
- (struct dma_register *) DMA39_NEXT_DESC_PTR,
- (struct dma_register *) DMA40_NEXT_DESC_PTR,
- (struct dma_register *) DMA41_NEXT_DESC_PTR,
- (struct dma_register *) DMA42_NEXT_DESC_PTR,
- (struct dma_register *) DMA43_NEXT_DESC_PTR,
- (struct dma_register *) DMA44_NEXT_DESC_PTR,
- (struct dma_register *) DMA45_NEXT_DESC_PTR,
- (struct dma_register *) DMA46_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPI0_TX:
- ret_irq = IRQ_SPI0_TX;
- break;
- case CH_SPI0_RX:
- ret_irq = IRQ_SPI0_RX;
- break;
- case CH_SPI1_TX:
- ret_irq = IRQ_SPI1_TX;
- break;
- case CH_SPI1_RX:
- ret_irq = IRQ_SPI1_RX;
- break;
- case CH_RSI:
- ret_irq = IRQ_RSI;
- break;
- case CH_SDU:
- ret_irq = IRQ_SDU;
- break;
- case CH_LP0:
- ret_irq = IRQ_LP0;
- break;
- case CH_LP1:
- ret_irq = IRQ_LP1;
- break;
- case CH_LP2:
- ret_irq = IRQ_LP2;
- break;
- case CH_LP3:
- ret_irq = IRQ_LP3;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0_CH0:
- ret_irq = IRQ_EPPI0_CH0;
- break;
- case CH_EPPI0_CH1:
- ret_irq = IRQ_EPPI0_CH1;
- break;
- case CH_EPPI1_CH0:
- ret_irq = IRQ_EPPI1_CH0;
- break;
- case CH_EPPI1_CH1:
- ret_irq = IRQ_EPPI1_CH1;
- break;
- case CH_EPPI2_CH0:
- ret_irq = IRQ_EPPI2_CH0;
- break;
- case CH_EPPI2_CH1:
- ret_irq = IRQ_EPPI2_CH1;
- break;
- case CH_PIXC_CH0:
- ret_irq = IRQ_PIXC_CH0;
- break;
- case CH_PIXC_CH1:
- ret_irq = IRQ_PIXC_CH1;
- break;
- case CH_PIXC_CH2:
- ret_irq = IRQ_PIXC_CH2;
- break;
- case CH_PVP_CPDOB:
- ret_irq = IRQ_PVP_CPDOB;
- break;
- case CH_PVP_CPDOC:
- ret_irq = IRQ_PVP_CPDOC;
- break;
- case CH_PVP_CPSTAT:
- ret_irq = IRQ_PVP_CPSTAT;
- break;
- case CH_PVP_CPCI:
- ret_irq = IRQ_PVP_CPCI;
- break;
- case CH_PVP_MPDO:
- ret_irq = IRQ_PVP_MPDO;
- break;
- case CH_PVP_MPDI:
- ret_irq = IRQ_PVP_MPDI;
- break;
- case CH_PVP_MPSTAT:
- ret_irq = IRQ_PVP_MPSTAT;
- break;
- case CH_PVP_MPCI:
- ret_irq = IRQ_PVP_MPCI;
- break;
- case CH_PVP_CPDOA:
- ret_irq = IRQ_PVP_CPDOA;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
deleted file mode 100644
index fcb8f688a8b2..000000000000
--- a/arch/blackfin/mach-bf609/dpm.S
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#include <asm/context.S>
-
-#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
- /* switch stack to L1 scratch, prepare for ddr srfr */
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
- SP = P0;
-
- call _bf609_ddr_sr;
- call _bfin_hibernate_syscontrol;
-
- P0.H = HI(DPM0_RESTORE4);
- P0.L = LO(DPM0_RESTORE4);
- P1.H = _bf609_pm_data;
- P1.L = _bf609_pm_data;
- [P0] = P1;
-
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000010);
- R3.L = LO(0x00000010);
-
- bfin_init_pm_bench_cycles;
-
- [P0] = R3;
-
- SSYNC;
-ENDPROC(_enter_hibernate)
-
-/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
- * is disabled. This behavior differ from bf5xx serial processor.
- */
-ENTRY(_dummy_deepsleep)
- [--sp] = SYSCFG;
- [--sp] = (R7:0,P5:0);
- cli r0;
-
- /* get wake up interrupt ID */
- P0.l = LO(SEC_SCI_BASE + SEC_CSID);
- P0.h = HI(SEC_SCI_BASE + SEC_CSID);
- R0 = [P0];
-
- /* ACK wake up interrupt in SEC */
- P1.l = LO(SEC_END);
- P1.h = HI(SEC_END);
-
- [P1] = R0;
- SSYNC;
-
- /* restore EVT 11 entry */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _evt_evt11;
- p1.l = _evt_evt11;
-
- [p0] = p1;
- SSYNC;
-
- (R7:0,P5:0) = [sp++];
- SYSCFG = [sp++];
- RTI;
-ENDPROC(_dummy_deepsleep)
-
-ENTRY(_enter_deepsleep)
- LINK 0xC;
- [--sp] = (R7:0,P5:0);
-
- /* Change EVT 11 entry to dummy handler for wake up event */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _dummy_deepsleep;
- p1.l = _dummy_deepsleep;
-
- [p0] = p1;
-
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
-
- EX_SCRATCH_REG = SP;
- SP = P0;
-
- SSYNC;
-
- /* should put ddr to self refresh mode before sleep */
- call _bf609_ddr_sr;
-
- /* Set DPM controller to deep sleep mode */
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000008);
- R3.L = LO(0x00000008);
- [P0] = R3;
- CSYNC;
-
- /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
- r0.l = 0x800;
- r0.h = 0;
- sti r0;
- SSYNC;
-
- bfin_init_pm_bench_cycles;
-
- /* Fall into deep sleep in idle*/
- idle;
- SSYNC;
-
- /* Restore PLL after wake up from deep sleep */
- call _bf609_resume_ccbuf;
-
- /* turn ddr out of self refresh mode */
- call _bf609_ddr_sr_exit;
-
- SP = EX_SCRATCH_REG;
-
- (R7:0,P5:0) = [SP++];
- UNLINK;
- RTS;
-ENDPROC(_enter_deepsleep)
-
-.section .text
-ENTRY(_bf609_hibernate)
- bfin_cpu_reg_save;
- bfin_core_mmr_save;
-
- P0.H = _bf609_pm_data;
- P0.L = _bf609_pm_data;
- R1.H = 0xDEAD;
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1;
- [P0++] = R2;
- [P0++] = SP;
-
- P1.H = _enter_hibernate;
- P1.L = _enter_hibernate;
-
- call (P1);
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
deleted file mode 100644
index 696786e9a531..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
-#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
-/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
-#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
-/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
-#define ANOMALY_16000024 (1)
-/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
-#define ANOMALY_16000025 (1)
-/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Default SPI Master Boot Mode Setting is Incorrect */
-#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
-/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
-/* Incorrect Default USB_PLL_OSC.PLLM Value */
-#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
-/* Core Reads of System MMRs May Cause the Core to Hang */
-#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
-/* PPI Data Underflow on First Word Not Reported in Certain Modes */
-#define ANOMALY_16000033 (1)
-/* CNV1 Red Pixel Substitution feature not functional in the PVP */
-#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
-/* IPF0 Output Port Color Separation feature not functional */
-#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
-/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
-#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
-/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
-#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
-/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
-#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
-/* CGU_STAT.PLOCKERR Bit May be Unreliable */
-#define ANOMALY_16000039 (1)
-/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
-#define ANOMALY_16000040 (1)
-/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
-#define ANOMALY_16000041 (1)
-/* Instruction Cache Failure When Parity Is Enabled */
-#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
deleted file mode 100644
index c897c2a2fbfa..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/bf609.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF609_H__
-#define __MACH_BF609_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF609)
-# define CPU "BF609"
-# define CPUID 0x27fe /* temperary fake value */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF609_H__ */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
deleted file mode 100644
index 1fd398147fd9..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-#define BFIN_UART_TX_FIFO_SIZE 8
-
-#define BFIN_UART_BF60X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
deleted file mode 100644
index b1a48c410711..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/blackfin.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf609.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF609
-# include "defBF609.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF609
-# include "cdefBF609.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
deleted file mode 100644
index c4f3fe19acda..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF609_H
-#define _CDEF_BF609_H
-
-/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
-#include "cdefBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-
-#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
deleted file mode 100644
index 102ee4025ac9..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
+++ /dev/null
@@ -1,3254 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF60X_H
-#define _CDEF_BF60X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-/* SEC0 Registers */
-#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)
-#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
-#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)
-#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
-#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)
-#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
-
-#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)
-#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
-
-#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
-
-#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))
-#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
-
-/* RCU0 Registers */
-#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
-
-/* Watchdog Timer Registers */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID)
-#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
-#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
-#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT)
-#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
-#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
-#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK)
-#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
-#define bfin_read_UART0_IER() bfin_read32(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
-#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
-#define bfin_read_UART0_THR() bfin_read32(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
-#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP)
-#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
-#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR)
-#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
-#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR)
-#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
-#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT)
-#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
-#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT)
-#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID)
-#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
-#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
-#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT)
-#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
-#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
-#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK)
-#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
-#define bfin_read_UART1_IER() bfin_read32(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
-#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
-#define bfin_read_UART1_THR() bfin_read32(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
-#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP)
-#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
-#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR)
-#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
-#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR)
-#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
-#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT)
-#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
-#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT)
-#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
-
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
-#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL)
-#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
-#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL)
-#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
-#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)
-#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
-#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY)
-#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
-#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL)
-#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
-#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC)
-#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
-#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR)
-#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
-#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC)
-#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
-#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR)
-#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
-#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK)
-#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
-#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR)
-#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
-#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET)
-#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
-#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
-#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT)
-#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
-#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR)
-#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
-#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO)
-#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
-#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO)
-#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
-#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL)
-#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
-#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL)
-#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
-#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)
-#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
-#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY)
-#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
-#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL)
-#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
-#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC)
-#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
-#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR)
-#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
-#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC)
-#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
-#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR)
-#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
-#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK)
-#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
-#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)
-#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
-#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET)
-#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
-#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
-#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT)
-#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
-#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR)
-#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
-#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO)
-#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
-#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO)
-#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
-
-/* Timer 0-7 registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-
-
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT1 Registers */
-
-
-/* SMC Registers */
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-/* DDR2 Memory Control Registers */
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
-#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR)
-#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT)
-#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
-#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT)
-#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
-#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT)
-#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
-#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT)
-#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR)
-#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT)
-#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
-#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT)
-#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
-#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT)
-#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
-#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT)
-#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR)
-#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT)
-#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
-#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT)
-#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
-#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT)
-#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
-#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT)
-#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR)
-#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT)
-#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
-#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT)
-#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
-#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT)
-#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
-#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT)
-#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR)
-#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT)
-#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
-#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT)
-#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
-#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT)
-#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
-#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT)
-#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR)
-#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT)
-#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
-#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT)
-#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
-#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT)
-#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
-#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT)
-#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR)
-#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT)
-#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
-#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT)
-#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
-#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT)
-#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
-#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT)
-#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR)
-#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT)
-#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
-#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT)
-#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
-#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT)
-#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
-#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT)
-#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR)
-#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT)
-#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
-#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT)
-#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
-#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT)
-#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
-#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT)
-#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR)
-#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT)
-#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
-#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT)
-#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
-#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT)
-#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
-#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT)
-#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR)
-#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT)
-#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
-#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT)
-#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
-#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT)
-#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
-#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT)
-#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR)
-#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT)
-#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
-#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT)
-#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
-#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT)
-#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
-#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT)
-#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR)
-#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT)
-#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
-#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT)
-#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
-#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT)
-#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
-#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT)
-#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR)
-#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT)
-#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
-#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT)
-#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
-#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT)
-#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
-#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT)
-#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR)
-#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT)
-#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
-#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT)
-#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
-#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT)
-#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
-#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT)
-#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR)
-#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT)
-#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
-#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT)
-#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
-#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT)
-#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
-#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT)
-#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR)
-#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT)
-#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
-#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT)
-#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
-#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT)
-#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
-#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT)
-#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
-#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
-#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
-#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
-#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
-#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
-#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
-#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
-#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
-#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
-#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
-#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
-#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
-#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
-#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
-#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
-#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
-#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
-#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
-#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
-#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
-#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
-#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
-#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
-#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
-#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
-#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
-#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
-#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
-#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
-#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
-#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
-#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
-
-
-/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
-
-#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
-#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG)
-#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
-
-#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG)
-#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG)
-#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
-
-
-/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
-
-#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR)
-#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
-#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG)
-#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
-#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT)
-#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY)
-#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
-#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT)
-#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
-#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY)
-#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR)
-#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS)
-#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR)
-#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
-#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG)
-#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
-#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT)
-#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY)
-#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
-#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT)
-#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY)
-#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR)
-#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS)
-#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
-
-#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR)
-#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
-#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG)
-#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
-#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT)
-#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY)
-#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
-#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT)
-#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
-#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY)
-#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR)
-#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS)
-#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR)
-#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
-#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG)
-#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
-#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT)
-#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY)
-#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
-#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT)
-#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY)
-#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR)
-#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS)
-#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
-
-
-/* DMA Channel 29 Registers */
-
-#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR)
-#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
-#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR)
-#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
-#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG)
-#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
-#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT)
-#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
-#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY)
-#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
-#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT)
-#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
-#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY)
-#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
-#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR)
-#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
-#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR)
-#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
-#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR)
-#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
-#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS)
-#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
-#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT)
-#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
-#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT)
-#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
-#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT)
-#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
-#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT)
-#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
-#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT)
-#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
-#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
-#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
-
-/* DMA Channel 30 Registers */
-
-#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
-#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
-#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
-#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
-#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
-#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
-#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
-#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
-#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
-#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
-#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
-#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
-#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
-#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
-#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
-#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
-#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
-#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
-#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
-#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
-#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
-#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
-#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
-#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
-#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
-#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
-#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
-#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
-#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
-#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
-#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
-#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
-#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
-#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
-
-/* DMA Channel 31 Registers */
-
-#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
-#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
-#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
-#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
-#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
-#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
-#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
-#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
-#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
-#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
-#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
-#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
-#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
-#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
-#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
-#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
-#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
-#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
-#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
-#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
-#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
-#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
-#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
-#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
-#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
-#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
-#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
-#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
-#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
-#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
-#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
-#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
-#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
-#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
-
-/* DMA Channel 32 Registers */
-
-#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
-#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
-#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
-#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
-#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
-#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
-#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
-#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
-#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
-#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
-#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
-#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
-#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
-#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
-#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
-#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
-#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
-#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
-#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
-#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
-#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
-#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
-#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
-#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
-#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
-#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
-#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
-#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
-#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
-#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
-#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
-#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
-#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
-#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
-
-/* DMA Channel 33 Registers */
-
-#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
-#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
-#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
-#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
-#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
-#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
-#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
-#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
-#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
-#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
-#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
-#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
-#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
-#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
-#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
-#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
-#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
-#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
-#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
-#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
-#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
-#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
-#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
-#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
-#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
-#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
-#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
-#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
-#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
-#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
-#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
-#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
-#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
-#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
-
-/* DMA Channel 34 Registers */
-
-#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
-#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
-#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
-#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
-#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
-#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
-#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
-#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
-#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
-#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
-#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
-#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
-#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
-#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
-#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
-#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
-#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
-#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
-#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
-#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
-#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
-#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
-#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
-#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
-#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
-#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
-#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
-#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
-#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
-#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
-#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
-#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
-#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
-#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
-
-/* DMA Channel 35 Registers */
-
-#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
-#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
-#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
-#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
-#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
-#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
-#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
-#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
-#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
-#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
-#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
-#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
-#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
-#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
-#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
-#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
-#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
-#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
-#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
-#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
-#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
-#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
-#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
-#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
-#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
-#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
-#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
-#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
-#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
-#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
-#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
-#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
-#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
-#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
-
-/* DMA Channel 36 Registers */
-
-#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
-#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
-#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
-#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
-#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
-#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
-#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
-#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
-#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
-#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
-#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
-#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
-#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
-#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
-#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
-#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
-#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
-#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
-#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
-#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
-#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
-#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
-#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
-#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
-#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
-#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
-#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
-#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
-#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
-#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
-#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
-#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
-#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
-#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
-
-/* DMA Channel 37 Registers */
-
-#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
-#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
-#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
-#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
-#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
-#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
-#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
-#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
-#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
-#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
-#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
-#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
-#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
-#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
-#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
-#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
-#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
-#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
-#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
-#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
-#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
-#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
-#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
-#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
-#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
-#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
-#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
-#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
-#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
-#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
-#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
-#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
-#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
-#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
-
-/* DMA Channel 38 Registers */
-
-#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
-#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
-#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
-#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
-#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
-#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
-#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
-#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
-#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
-#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
-#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
-#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
-#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
-#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
-#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
-#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
-#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
-#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
-#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
-#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
-#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
-#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
-#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
-#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
-#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
-#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
-#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
-#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
-#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
-#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
-#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
-#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
-#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
-#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
-
-/* DMA Channel 39 Registers */
-
-#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
-#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
-#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
-#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
-#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
-#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
-#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
-#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
-#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
-#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
-#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
-#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
-#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
-#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
-#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
-#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
-#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
-#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
-#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
-#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
-#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
-#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
-#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
-#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
-#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
-#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
-#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT)
-#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
-#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT)
-#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
-#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT)
-#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
-#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT)
-#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
-
-/* DMA Channel 40 Registers */
-
-#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR)
-#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
-#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR)
-#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
-#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG)
-#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
-#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT)
-#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
-#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY)
-#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
-#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT)
-#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
-#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY)
-#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
-#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR)
-#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
-#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR)
-#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
-#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR)
-#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
-#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS)
-#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
-#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT)
-#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
-#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT)
-#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
-#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT)
-#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
-#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT)
-#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
-#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT)
-#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
-#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT)
-#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
-
-/* DMA Channel 41 Registers */
-
-#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR)
-#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
-#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR)
-#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
-#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG)
-#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
-#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT)
-#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
-#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY)
-#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
-#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT)
-#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
-#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY)
-#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
-#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR)
-#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
-#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR)
-#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
-#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR)
-#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
-#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS)
-#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
-#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT)
-#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
-#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT)
-#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
-#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT)
-#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
-#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT)
-#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
-#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT)
-#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
-#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT)
-#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
-
-/* DMA Channel 42 Registers */
-
-#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR)
-#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
-#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR)
-#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
-#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG)
-#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
-#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT)
-#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
-#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY)
-#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
-#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT)
-#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
-#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY)
-#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
-#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR)
-#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
-#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR)
-#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
-#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR)
-#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
-#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS)
-#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
-#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT)
-#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
-#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT)
-#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
-#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT)
-#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
-#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT)
-#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
-#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT)
-#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
-#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT)
-#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
-
-/* DMA Channel 43 Registers */
-
-#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR)
-#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
-#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR)
-#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
-#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG)
-#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
-#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT)
-#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
-#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY)
-#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
-#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT)
-#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
-#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY)
-#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
-#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR)
-#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
-#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR)
-#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
-#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR)
-#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
-#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS)
-#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
-#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT)
-#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
-#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT)
-#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
-#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT)
-#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
-#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT)
-#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
-#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT)
-#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
-#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT)
-#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
-
-/* DMA Channel 44 Registers */
-
-#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR)
-#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
-#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR)
-#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
-#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG)
-#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
-#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT)
-#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
-#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY)
-#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
-#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT)
-#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
-#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY)
-#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
-#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR)
-#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
-#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR)
-#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
-#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR)
-#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
-#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS)
-#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
-#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
-#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
-#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
-#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
-#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
-#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
-#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
-#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
-#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
-#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
-#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
-#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
-
-/* DMA Channel 45 Registers */
-
-#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
-#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
-#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
-#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
-#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
-#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
-#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
-#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
-#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
-#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
-#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
-#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
-#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
-#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
-#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
-#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
-#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
-#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
-#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
-#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
-#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
-#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
-#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
-#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
-#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
-#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
-#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
-#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
-#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
-#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
-#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
-#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
-#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
-#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
-
-/* DMA Channel 46 Registers */
-
-#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
-#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
-#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
-#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
-#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
-#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
-#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
-#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
-#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
-#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
-#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
-#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
-#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
-#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
-#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
-#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
-#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
-#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
-#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
-#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
-#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
-#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
-#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
-#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
-#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
-#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
-#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
-#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
-#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
-#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
-#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
-#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
-#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
-#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
-
-
-/* EPPI1 Registers */
-
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port Interrubfin_read_()t 4 Registers (32-bit) */
-
-#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET)
-#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
-#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR)
-#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
-#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST)
-#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
-#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN)
-#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
-#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET)
-#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
-#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR)
-#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
-#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET)
-#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
-#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR)
-#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
-#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE)
-#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
-#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH)
-#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
-
-/* Port Interrubfin_read_()t 5 Registers (32-bit) */
-
-#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET)
-#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
-#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR)
-#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
-#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST)
-#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
-#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN)
-#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
-#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET)
-#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
-#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR)
-#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
-#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET)
-#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
-#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR)
-#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
-#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE)
-#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
-#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH)
-#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
-#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET)
-#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
-#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR)
-#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
-#define bfin_read_PORTA() bfin_read32(PORTA)
-#define bfin_write_PORTA(val) bfin_write32(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR)
-#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
-#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET)
-#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
-#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR)
-#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL)
-#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
-#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL)
-#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
-#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET)
-#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
-#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR)
-#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
-#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK)
-#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
-#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID)
-#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
-
-
-
-/* Port B Registers */
-#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
-#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET)
-#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
-#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR)
-#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
-#define bfin_read_PORTB() bfin_read32(PORTB)
-#define bfin_write_PORTB(val) bfin_write32(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR)
-#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
-#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET)
-#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
-#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR)
-#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL)
-#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
-#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL)
-#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
-#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET)
-#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
-#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR)
-#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
-#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK)
-#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
-#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID)
-#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
-
-
-/* Port C Registers */
-#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
-#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET)
-#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
-#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR)
-#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
-#define bfin_read_PORTC() bfin_read32(PORTC)
-#define bfin_write_PORTC(val) bfin_write32(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR)
-#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
-#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET)
-#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
-#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR)
-#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL)
-#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
-#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL)
-#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
-#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET)
-#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
-#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR)
-#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
-#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK)
-#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
-#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID)
-#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
-
-
-/* Port D Registers */
-#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
-#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET)
-#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
-#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR)
-#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
-#define bfin_read_PORTD() bfin_read32(PORTD)
-#define bfin_write_PORTD(val) bfin_write32(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR)
-#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
-#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET)
-#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
-#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR)
-#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL)
-#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
-#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL)
-#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
-#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET)
-#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
-#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR)
-#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
-#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK)
-#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
-#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID)
-#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
-
-
-/* Port E Registers */
-#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
-#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET)
-#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
-#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR)
-#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
-#define bfin_read_PORTE() bfin_read32(PORTE)
-#define bfin_write_PORTE(val) bfin_write32(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR)
-#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
-#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET)
-#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
-#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR)
-#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL)
-#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
-#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL)
-#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
-#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET)
-#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
-#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR)
-#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
-#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK)
-#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
-#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID)
-#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
-
-
-/* Port F Registers */
-#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
-#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET)
-#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
-#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR)
-#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
-#define bfin_read_PORTF() bfin_read32(PORTF)
-#define bfin_write_PORTF(val) bfin_write32(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR)
-#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
-#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET)
-#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
-#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR)
-#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL)
-#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
-#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL)
-#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
-#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET)
-#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
-#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR)
-#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
-#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK)
-#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
-#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID)
-#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
-
-
-/* Port G Registers */
-#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
-#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET)
-#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
-#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR)
-#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
-#define bfin_read_PORTG() bfin_read32(PORTG)
-#define bfin_write_PORTG(val) bfin_write32(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR)
-#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
-#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET)
-#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
-#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR)
-#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL)
-#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
-#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL)
-#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
-#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET)
-#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
-#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR)
-#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
-#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK)
-#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
-#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID)
-#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
-
-
-
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* RSI Register */
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-
-/* usb register */
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#endif /* _CDEF_BF60X_H */
-
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
deleted file mode 100644
index 8045ade34370..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF609.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF609_H
-#define _DEF_BF609_H
-
-/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
-#include "defBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-/* =========================
- PIXC Registers
- ========================= */
-
-/* =========================
- PIXC0
- ========================= */
-#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
-#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
-#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
-#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
-#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
-#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
-#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
-#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
-#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
-#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
-#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
-#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
-#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
-#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
-#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
-#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
-#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
-#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
-#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
-#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
-
-/* =========================
- PVP Registers
- ========================= */
-
-/* =========================
- PVP0
- ========================= */
-#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
-#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
-#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
-#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
-#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
-#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
-#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
-#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
-#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
-#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
-#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
-#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
-#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
-#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
-#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
-#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
-#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
-#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
-#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
-#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
-#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
-#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
-#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
-#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
-#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
-#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
-#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
-#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
-#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
-#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
-#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
-#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
-#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
-#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
-#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
-#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
-#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
-#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
-#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
-#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
-#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
-#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
-#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
-#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
-#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
-#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
-#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
-#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
-#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
-#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
-#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
-#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
-#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
-#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
-#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
-#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
-#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
-#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
-#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
-#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
-#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
-#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
-#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
-#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
-#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
-#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
-#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
-#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */
-#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */
-#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */
-#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */
-#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */
-#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */
-#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */
-#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */
-#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */
-#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */
-#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */
-#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */
-#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */
-#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */
-#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */
-#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */
-#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */
-#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */
-#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */
-#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
-#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
-#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */
-#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */
-#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */
-
-#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
deleted file mode 100644
index 3933e912cacd..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ /dev/null
@@ -1,3596 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF60X_H
-#define _DEF_BF60X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-
-/* =========================
- CNT Registers
- ========================= */
-
-/* =========================
- CNT0
- ========================= */
-#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */
-#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */
-#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */
-#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */
-#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */
-#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */
-#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
-#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
-
-
-/* =========================
- RSI Registers
- ========================= */
-
-#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
-#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
-#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
-#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
-#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
-#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
-#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
-#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
-#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
-#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
-#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
-#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
-#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
-#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
-#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
-#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
-#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
-
-/* =========================
- CAN Registers
- ========================= */
-
-/* =========================
- CAN0
- ========================= */
-#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */
-#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */
-#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */
-#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
-#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */
-#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */
-#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */
-#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
-#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */
-#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
-#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */
-#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */
-#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
-#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */
-#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */
-#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */
-#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
-#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
-#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
-#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
-#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
-#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
-#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */
-
-/* =========================
- LINK PORT Registers
- ========================= */
-#define LP0_CTL 0xFFC01000 /* LP0 Control Register */
-#define LP0_STAT 0xFFC01004 /* LP0 Status Register */
-#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
-#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */
-#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
-#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
-#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
-#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
-#define LP1_CTL 0xFFC01100 /* LP1 Control Register */
-#define LP1_STAT 0xFFC01104 /* LP1 Status Register */
-#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
-#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */
-#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
-#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
-#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
-#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
-#define LP2_CTL 0xFFC01200 /* LP2 Control Register */
-#define LP2_STAT 0xFFC01204 /* LP2 Status Register */
-#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
-#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */
-#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
-#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
-#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
-#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
-#define LP3_CTL 0xFFC01300 /* LP3 Control Register */
-#define LP3_STAT 0xFFC01304 /* LP3 Status Register */
-#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
-#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */
-#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
-#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
-#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
-#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
- TIMER Registers
- ========================= */
-#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */
-#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */
-#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */
-#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */
-#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */
-#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */
-#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */
-#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */
-#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */
-#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */
-#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */
-#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */
-#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */
-#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */
-#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */
-#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */
-#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */
-
-/* =========================
- TIMER0~7
- ========================= */
-#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */
-#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */
-#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */
-#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */
-#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */
-
-#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
-#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
-#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
-#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
-#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
-
-#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */
-#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */
-#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */
-#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */
-#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */
-
-#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */
-#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */
-#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */
-#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */
-#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */
-
-#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */
-#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */
-#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */
-#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */
-#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */
-
-#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */
-#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */
-#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */
-#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */
-#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */
-
-#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */
-#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */
-#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */
-#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */
-#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */
-
-#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */
-#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */
-#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */
-#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */
-#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */
-
-/* =========================
- CRC Registers
- ========================= */
-
-/* =========================
- CRC0
- ========================= */
-#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
-#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */
-#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */
-#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */
-#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */
-#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */
-#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
-
-/* =========================
- CRC1
- ========================= */
-#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
-#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */
-#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */
-#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */
-#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */
-#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */
-#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
-
-/* =========================
- TWI Registers
- ========================= */
-
-/* =========================
- TWI0
- ========================= */
-#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
-#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
-#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */
-
-/* =========================
- TWI1
- ========================= */
-#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
-#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
-#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
-#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
-#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
-
-
-/* =========================
- UART Registers
- ========================= */
-
-/* =========================
- UART0
- ========================= */
-#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
-#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
-#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
-#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
-#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
-#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */
-#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
-#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
-#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
-#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
-#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
-#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
-#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */
-#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */
-
-/* =========================
- UART1
- ========================= */
-#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
-#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
-#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
-#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
-#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
-#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */
-#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
-#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
-#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
-#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
-#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
-#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
-#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */
-#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */
-
-
-/* =========================
- PORT Registers
- ========================= */
-
-/* =========================
- PORTA
- ========================= */
-#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
-#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
-#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
-#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
-#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
-#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
-#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
-#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
-#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
-#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
-#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
-#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
-#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */
-#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */
-#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */
-#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
-#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
-
-/* =========================
- PORTB
- ========================= */
-#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
-#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
-#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
-#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
-#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
-#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
-#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
-#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
-#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
-#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
-#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
-#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
-#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */
-#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */
-#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */
-#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
-#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
-
-/* =========================
- PORTC
- ========================= */
-#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
-#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
-#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
-#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
-#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
-#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
-#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
-#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
-#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
-#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
-#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
-#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
-#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */
-#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */
-#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */
-#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
-#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
-
-/* =========================
- PORTD
- ========================= */
-#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
-#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
-#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
-#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
-#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
-#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
-#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
-#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
-#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
-#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
-#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
-#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
-#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */
-#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */
-#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */
-#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
-#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
-
-/* =========================
- PORTE
- ========================= */
-#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
-#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
-#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
-#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
-#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
-#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
-#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
-#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
-#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
-#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
-#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
-#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
-#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */
-#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */
-#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */
-#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
-#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
-
-/* =========================
- PORTF
- ========================= */
-#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
-#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
-#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
-#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
-#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
-#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
-#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
-#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
-#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
-#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
-#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
-#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
-#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */
-#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */
-#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */
-#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
-#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
-
-/* =========================
- PORTG
- ========================= */
-#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
-#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
-#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
-#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
-#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
-#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
-#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
-#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
-#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
-#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
-#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
-#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
-#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */
-#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */
-#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */
-#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
-#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
-
-/* ==================================================
- Pads Controller Registers
- ================================================== */
-
-/* =========================
- PADS0
- ========================= */
-#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
-#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
-#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
-
-/* =========================
- PINT Registers
- ========================= */
-
-/* =========================
- PINT0
- ========================= */
-#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
-#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */
-#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
-#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
-#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
-#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
-#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
-
-/* =========================
- PINT1
- ========================= */
-#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
-#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
-#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
-#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
-#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
-#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
-#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
-
-/* =========================
- PINT2
- ========================= */
-#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
-#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */
-#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
-#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
-#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
-#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
-#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
-
-/* =========================
- PINT3
- ========================= */
-#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
-#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */
-#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
-#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
-#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
-#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
-#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
-
-/* =========================
- PINT4
- ========================= */
-#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
-#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
-#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */
-#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
-#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
-#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
-#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
-#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
-#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
-#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
-
-/* =========================
- PINT5
- ========================= */
-#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
-#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
-#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */
-#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
-#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
-#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
-#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
-#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
-#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
-#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
-
-
-/* =========================
- SMC Registers
- ========================= */
-
-/* =========================
- SMC0
- ========================= */
-#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */
-#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */
-#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */
-#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */
-#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */
-#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */
-#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */
-#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */
-#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */
-#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */
-#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */
-
-
-/* =========================
- WDOG Registers
- ========================= */
-
-/* =========================
- WDOG0
- ========================= */
-#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
-#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
-#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
-#define WDOG_CTL WDOG0_CTL
-#define WDOG_CNT WDOG0_CNT
-#define WDOG_STAT WDOG0_STAT
-
-/* =========================
- WDOG1
- ========================= */
-#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
-#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
-#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================
- SDU Registers
- ========================= */
-
-/* =========================
- SDU0
- ========================= */
-#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
-#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
-#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
-#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
-#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
-#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
-#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
-#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
-#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
-#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
-#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
-#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
-
-
-/* =========================
- EMAC Registers
- ========================= */
-/* =========================
- EMAC0
- ========================= */
-#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
-#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */
-#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */
-#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */
-#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */
-#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */
-#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */
-#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
-#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */
-#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */
-#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */
-#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */
-#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */
-#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */
-#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */
-#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */
-#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
-#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */
-#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */
-#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */
-#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
-#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */
-#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */
-#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */
-#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */
-#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */
-#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */
-#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */
-#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */
-#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */
-#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */
-#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */
-#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */
-#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */
-#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */
-#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */
-#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */
-#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */
-#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */
-#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */
-#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */
-#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */
-#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */
-#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */
-#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */
-#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */
-#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */
-#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */
-#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */
-#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */
-#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */
-#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */
-#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */
-#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */
-#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */
-#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */
-#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */
-#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */
-#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */
-#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */
-#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */
-#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */
-#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */
-#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */
-#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */
-#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */
-#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */
-#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */
-#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */
-#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */
-#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */
-#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */
-#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */
-#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */
-#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */
-#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */
-#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */
-#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */
-#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */
-#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */
-#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */
-#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */
-#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */
-#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */
-#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */
-#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */
-#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */
-#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */
-#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */
-#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */
-#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */
-#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */
-#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */
-#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */
-#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */
-#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */
-#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */
-#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
-#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
-#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
-#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */
-#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */
-#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */
-#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */
-#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */
-#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */
-#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */
-#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */
-#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */
-
-/* =========================
- EMAC1
- ========================= */
-#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
-#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */
-#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */
-#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */
-#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */
-#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */
-#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */
-#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
-#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */
-#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */
-#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */
-#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */
-#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */
-#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */
-#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */
-#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */
-#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
-#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */
-#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */
-#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */
-#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
-#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */
-#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */
-#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */
-#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */
-#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */
-#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */
-#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */
-#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */
-#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */
-#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */
-#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */
-#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */
-#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */
-#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */
-#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */
-#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */
-#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */
-#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */
-#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */
-#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */
-#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */
-#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */
-#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */
-#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */
-#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */
-#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */
-#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */
-#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */
-#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */
-#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */
-#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */
-#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */
-#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */
-#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */
-#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */
-#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */
-#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */
-#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */
-#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */
-#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */
-#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */
-#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */
-#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */
-#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */
-#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */
-#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */
-#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */
-#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */
-#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */
-#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */
-#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */
-#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */
-#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */
-#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */
-#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */
-#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */
-#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */
-#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */
-#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */
-#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */
-#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */
-#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */
-#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */
-#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */
-#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */
-#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */
-#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */
-#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */
-#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */
-#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */
-#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */
-#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */
-#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */
-#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */
-#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */
-#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */
-#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
-#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
-#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
-#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */
-#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */
-#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */
-#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */
-#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */
-#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */
-#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */
-#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */
-#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */
-
-
-/* =========================
- SPI Registers
- ========================= */
-
-/* =========================
- SPI0
- ========================= */
-#define SPI0_REGBASE 0xFFC40400
-#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
-#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */
-#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */
-#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
-#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
-#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
-#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */
-#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */
-#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */
-#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */
-#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
-#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
-#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
-#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
-#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
-#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
-#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
-#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
- SPI1
- ========================= */
-#define SPI1_REGBASE 0xFFC40500
-#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
-#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */
-#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */
-#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
-#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
-#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
-#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */
-#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */
-#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */
-#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */
-#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
-#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
-#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
-#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
-#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
-#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
-#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
-#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
- SPORT Registers
- ========================= */
-
-/* =========================
- SPORT0
- ========================= */
-#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */
-#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */
-#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */
-#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */
-#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */
-#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */
-#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */
-#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */
-#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */
-#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */
-#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */
-#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */
-#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */
-#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT1
- ========================= */
-#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */
-#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */
-#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */
-#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */
-#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */
-#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */
-#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */
-#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */
-#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */
-#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */
-#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */
-#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */
-#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */
-#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT2
- ========================= */
-#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */
-#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */
-#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */
-#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */
-#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */
-#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */
-#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */
-#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */
-#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */
-#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */
-#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */
-#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */
-#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */
-#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- EPPI Registers
- ========================= */
-
-/* =========================
- EPPI0
- ========================= */
-#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
-#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
-#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
-#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
-#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
-#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
-#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
-#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
-#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
-
-/* =========================
- EPPI1
- ========================= */
-#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
-#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
-#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
-#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
-#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
-#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
-#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
-#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
-#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
-
-/* =========================
- EPPI2
- ========================= */
-#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
-#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
-#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
-#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
-#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
-#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
-#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
-#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
-#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
-
-
-
-/* =========================
- DDE Registers
- ========================= */
-
-/* =========================
- DMA0
- ========================= */
-#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
-#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
-#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
-#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */
-#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
-#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
-#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
-#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
-#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */
-#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */
-#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */
-#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
-#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
-#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
-#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA1
- ========================= */
-#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
-#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
-#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
-#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */
-#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
-#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
-#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
-#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
-#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */
-#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */
-#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
-#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
-#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
-#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
-#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA2
- ========================= */
-#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
-#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
-#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
-#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */
-#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
-#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
-#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
-#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
-#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */
-#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */
-#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */
-#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
-#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
-#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
-#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA3
- ========================= */
-#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
-#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
-#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
-#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */
-#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
-#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
-#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
-#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
-#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */
-#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */
-#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
-#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
-#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
-#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
-#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA4
- ========================= */
-#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
-#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
-#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
-#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */
-#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
-#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
-#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
-#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
-#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */
-#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */
-#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */
-#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
-#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
-#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
-#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA5
- ========================= */
-#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
-#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
-#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
-#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */
-#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
-#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
-#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
-#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
-#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */
-#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */
-#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
-#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
-#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
-#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
-#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA6
- ========================= */
-#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
-#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
-#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
-#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
-#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
-#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
-#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
-#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
-#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
-#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
-#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
-#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
-#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
-#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
-#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA7
- ========================= */
-#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
-#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
-#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
-#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */
-#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
-#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
-#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
-#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
-#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */
-#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */
-#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
-#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
-#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
-#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
-#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA8
- ========================= */
-#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
-#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
-#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
-#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */
-#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
-#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
-#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
-#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
-#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */
-#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */
-#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */
-#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
-#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
-#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
-#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA9
- ========================= */
-#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
-#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
-#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
-#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */
-#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
-#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
-#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
-#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
-#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */
-#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */
-#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
-#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
-#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
-#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
-#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA10
- ========================= */
-#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
-#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
-#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
-#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
-#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
-#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
-#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
-#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
-#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
-#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
-#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
-#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
-#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
-#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA11
- ========================= */
-#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
-#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
-#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
-#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */
-#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
-#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
-#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
-#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
-#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */
-#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */
-#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
-#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
-#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
-#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
-#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA12
- ========================= */
-#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
-#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
-#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
-#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */
-#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
-#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
-#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
-#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
-#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */
-#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */
-#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */
-#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
-#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
-#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
-#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA13
- ========================= */
-#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
-#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
-#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
-#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */
-#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
-#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
-#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
-#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
-#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */
-#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */
-#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */
-#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
-#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
-#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
-#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA14
- ========================= */
-#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
-#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
-#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
-#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */
-#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
-#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
-#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
-#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
-#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */
-#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */
-#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
-#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
-#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
-#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
-#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA15
- ========================= */
-#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
-#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
-#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
-#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */
-#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
-#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
-#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
-#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
-#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */
-#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */
-#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */
-#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
-#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
-#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
-#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA16
- ========================= */
-#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
-#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
-#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
-#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */
-#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
-#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
-#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
-#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
-#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */
-#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */
-#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
-#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
-#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
-#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
-#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA17
- ========================= */
-#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
-#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
-#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
-#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */
-#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
-#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
-#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
-#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
-#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */
-#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */
-#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */
-#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
-#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
-#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
-#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA18
- ========================= */
-#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
-#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
-#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
-#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */
-#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
-#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
-#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
-#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
-#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */
-#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */
-#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
-#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
-#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
-#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
-#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA19
- ========================= */
-#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
-#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
-#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
-#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */
-#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
-#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
-#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
-#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
-#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */
-#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */
-#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */
-#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
-#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
-#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
-#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA20
- ========================= */
-#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
-#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
-#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
-#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
-#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
-#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
-#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
-#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
-#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
-#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
-#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
-#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
-#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
-#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
-#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA21
- ========================= */
-#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
-#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
-#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
-#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
-#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
-#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
-#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
-#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
-#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
-#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
-#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
-#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
-#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
-#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
-#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA22
- ========================= */
-#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
-#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
-#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
-#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */
-#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
-#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
-#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
-#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
-#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */
-#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */
-#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
-#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
-#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
-#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
-#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA23
- ========================= */
-#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
-#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
-#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
-#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
-#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
-#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
-#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
-#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
-#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
-#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
-#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
-#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
-#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
-#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
-#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA24
- ========================= */
-#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
-#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
-#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */
-#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
-#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */
-#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
-#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
-#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
-#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
-#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */
-#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */
-#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
-#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
-#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
-#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
-#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA25
- ========================= */
-#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
-#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
-#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */
-#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
-#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */
-#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
-#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
-#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
-#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
-#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */
-#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */
-#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */
-#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
-#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
-#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
-#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA26
- ========================= */
-#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
-#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
-#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */
-#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
-#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */
-#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
-#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
-#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
-#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
-#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */
-#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */
-#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
-#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
-#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
-#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
-#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA27
- ========================= */
-#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
-#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
-#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */
-#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
-#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */
-#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
-#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
-#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
-#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
-#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */
-#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */
-#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */
-#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
-#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
-#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
-#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA28
- ========================= */
-#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
-#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
-#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */
-#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
-#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */
-#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
-#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
-#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
-#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
-#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */
-#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */
-#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
-#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
-#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
-#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
-#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA29
- ========================= */
-#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
-#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
-#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */
-#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
-#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
-#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
-#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
-#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
-#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
-#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */
-#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */
-#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
-#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
-#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
-#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
-#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA30
- ========================= */
-#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
-#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
-#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */
-#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
-#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
-#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
-#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
-#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
-#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
-#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */
-#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */
-#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
-#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
-#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
-#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
-#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA31
- ========================= */
-#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
-#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
-#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */
-#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
-#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
-#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
-#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
-#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
-#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
-#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */
-#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */
-#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
-#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
-#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
-#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
-#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA32
- ========================= */
-#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
-#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
-#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */
-#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
-#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
-#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
-#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
-#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
-#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
-#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */
-#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */
-#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
-#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
-#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
-#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
-#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA33
- ========================= */
-#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
-#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
-#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */
-#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
-#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
-#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
-#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
-#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
-#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
-#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */
-#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */
-#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
-#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
-#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
-#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
-#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA34
- ========================= */
-#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
-#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
-#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */
-#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
-#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
-#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
-#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
-#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
-#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
-#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */
-#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */
-#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
-#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
-#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
-#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
-#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA35
- ========================= */
-#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
-#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
-#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */
-#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
-#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */
-#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
-#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
-#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
-#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
-#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */
-#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */
-#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */
-#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
-#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
-#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
-#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA36
- ========================= */
-#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
-#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
-#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */
-#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
-#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */
-#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
-#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
-#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
-#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
-#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */
-#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */
-#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
-#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
-#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
-#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
-#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA37
- ========================= */
-#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
-#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
-#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */
-#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
-#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */
-#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
-#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
-#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
-#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
-#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */
-#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */
-#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */
-#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
-#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
-#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
-#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA38
- ========================= */
-#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
-#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
-#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */
-#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
-#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */
-#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
-#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
-#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
-#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
-#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */
-#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */
-#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */
-#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
-#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
-#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
-#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA39
- ========================= */
-#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
-#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
-#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */
-#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
-#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */
-#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
-#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
-#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
-#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
-#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */
-#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */
-#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
-#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
-#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
-#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
-#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA40
- ========================= */
-#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
-#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
-#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */
-#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
-#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */
-#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
-#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
-#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
-#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
-#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */
-#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */
-#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */
-#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
-#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
-#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
-#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA41
- ========================= */
-#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
-#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
-#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */
-#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
-#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */
-#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
-#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
-#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
-#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
-#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */
-#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */
-#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
-#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
-#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
-#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
-#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA42
- ========================= */
-#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
-#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
-#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */
-#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
-#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */
-#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
-#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
-#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
-#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
-#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */
-#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */
-#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */
-#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
-#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
-#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
-#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA43
- ========================= */
-#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
-#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
-#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */
-#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
-#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */
-#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
-#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
-#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
-#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
-#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */
-#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */
-#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
-#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
-#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
-#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
-#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA44
- ========================= */
-#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
-#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
-#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */
-#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
-#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */
-#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
-#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
-#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
-#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
-#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */
-#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */
-#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */
-#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
-#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
-#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
-#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA45
- ========================= */
-#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
-#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
-#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */
-#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
-#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */
-#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
-#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
-#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
-#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
-#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */
-#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */
-#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
-#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
-#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
-#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
-#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA46
- ========================= */
-#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
-#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
-#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */
-#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
-#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */
-#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
-#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
-#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
-#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
-#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */
-#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */
-#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */
-#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
-#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
-#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
-#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
-
-
-/********************************************************************************
- DMA Alias Definitions
- ********************************************************************************/
-#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR)
-#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR)
-#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG)
-#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT)
-#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY)
-#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT)
-#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY)
-#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR)
-#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR)
-#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR)
-#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS)
-#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT)
-#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT)
-#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT)
-#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT)
-#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR)
-#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR)
-#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG)
-#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT)
-#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY)
-#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT)
-#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY)
-#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR)
-#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR)
-#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR)
-#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS)
-#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT)
-#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT)
-#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT)
-#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT)
-#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR)
-#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR)
-#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG)
-#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT)
-#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY)
-#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT)
-#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY)
-#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR)
-#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR)
-#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR)
-#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS)
-#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT)
-#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT)
-#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT)
-#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT)
-#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR)
-#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR)
-#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG)
-#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT)
-#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY)
-#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT)
-#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY)
-#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR)
-#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR)
-#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR)
-#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS)
-#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT)
-#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT)
-#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT)
-#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT)
-#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR)
-#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR)
-#define MDMA2_DEST_CONFIG (DMA26_CONFIG)
-#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT)
-#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY)
-#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT)
-#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY)
-#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR)
-#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR)
-#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR)
-#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS)
-#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT)
-#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT)
-#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT)
-#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT)
-#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT)
-#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT)
-#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR)
-#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR)
-#define MDMA2_SRC_CONFIG (DMA25_CONFIG)
-#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT)
-#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY)
-#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT)
-#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY)
-#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR)
-#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR)
-#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR)
-#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS)
-#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT)
-#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT)
-#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT)
-#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT)
-#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT)
-#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT)
-#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR)
-#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR)
-#define MDMA3_DEST_CONFIG (DMA28_CONFIG)
-#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT)
-#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY)
-#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT)
-#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY)
-#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR)
-#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR)
-#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR)
-#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS)
-#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT)
-#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT)
-#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT)
-#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT)
-#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT)
-#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT)
-#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR)
-#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR)
-#define MDMA3_SRC_CONFIG (DMA27_CONFIG)
-#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT)
-#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY)
-#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT)
-#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY)
-#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR)
-#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR)
-#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR)
-#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS)
-#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT)
-#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT)
-#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT)
-#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT)
-#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT)
-#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT)
-
-
-/* =========================
- DMC Registers
- ========================= */
-
-/* =========================
- DMC0
- ========================= */
-#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
-#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
-#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
-#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
-#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
-#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
-#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
-#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
-#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
-#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
-#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
-#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
-#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
-
-#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */
-#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */
-#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */
-#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */
-#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
-#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
-
-/* =========================
- L2CTL Registers
- ========================= */
-
-/* =========================
- L2CTL0
- ========================= */
-#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */
-#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */
-#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */
-#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */
-#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */
-#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */
-#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */
-#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Register */
-#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */
-#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */
-#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */
-#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */
-#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */
-#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */
-#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */
-#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */
-#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */
-#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */
-#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */
-#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */
-
-
-/* =========================
- SEC Registers
- ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Core Interface (SCI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-
-#define SEC_SCI_BASE 0xFFCA4400
-#define SEC_SCI_OFF 0x40
-#define SEC_CCTL 0x0 /* SEC Core Control Register n */
-#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
-#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
-#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
-#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
-#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
-#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
-#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
-
-#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
-#define bfin_write_SEC_SCI(n, reg, val) \
- bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Fault Management Interface (SFI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
-#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
-#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
-#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
-#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
-#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
-#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
-#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
-#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
-#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Global Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
-#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
-#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
-#define SEC_END 0xFFCA400C /* SEC Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Source Interface (SSI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */
-#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */
-#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */
-#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_CCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */
-#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */
-#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */
-#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */
-#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */
-#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */
-#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */
-#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CACT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */
-#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CGMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */
-#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPLVL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSID_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */
-#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */
-#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */
-#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */
-#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */
-#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */
-#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_FCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */
-#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */
-#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */
-#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FSID_SID 0x000000FF /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FEND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FEND_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL_LOCK 0x80000000 /* Lock */
-#define SEC_GCTL_RESET 0x00000002 /* Reset */
-#define SEC_GCTL_EN 0x00000001 /* Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */
-#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */
-#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */
-#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */
-#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */
-#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */
-#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_RAISE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_END Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL_LOCK 0x80000000 /* Lock */
-#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */
-#define SEC_SCTL_GRP 0x000F0000 /* Group Select */
-#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */
-#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */
-#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */
-#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */
-#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */
-#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */
-#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */
-#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */
-#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_SSTAT_ERR 0x00000002 /* Error */
-
-
-/* =========================
- RCU Registers
- ========================= */
-
-/* =========================
- RCU0
- ========================= */
-#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
-#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
-#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
-#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
-#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
-#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
-
-
-/* =========================
- CGU0
- ========================= */
-#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
-#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
-#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
-#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
-
-
-/* =========================
- DPM Registers
- ========================= */
-
-/* =========================
- DPM0
- ========================= */
-#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
-#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
-#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
-#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
-#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
-#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
-#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
-#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
-#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
-#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
-#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
-#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
-#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
-#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
-#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
-#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
-#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
-#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
-#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
-#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
-#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
-#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
-#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
-
-
-/* =========================
- DBG Registers
- ========================= */
-
-/* USB register */
-#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */
-#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */
-#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */
-#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */
-#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */
-#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */
-#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */
-#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */
-#define USB_FRAME 0xFFCC100C /* USB Frame Number */
-#define USB_INDEX 0xFFCC100E /* USB Index */
-#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */
-#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */
-#define USB_EP_NI0_TXMAXP 0xFFCC1010
-#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */
-#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */
-#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */
-#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */
-#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */
-#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */
-#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */
-#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */
-#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */
-#define USB_EP0_FIFO 0xFFCC1020
-#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */
-#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */
-#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */
-#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */
-#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */
-#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */
-#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */
-#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */
-#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */
-#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */
-#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */
-#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */
-#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */
-#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */
-#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */
-#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */
-#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */
-#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */
-#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */
-#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */
-#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */
-#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */
-#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */
-#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */
-#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */
-#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */
-#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */
-#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */
-#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */
-#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */
-#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */
-#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */
-#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */
-#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */
-#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */
-#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */
-#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */
-#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */
-#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */
-#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */
-#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */
-#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */
-#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */
-#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */
-#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */
-#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */
-#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */
-#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */
-#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */
-#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */
-#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */
-#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */
-#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */
-#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */
-#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */
-#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */
-#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */
-#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */
-#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */
-#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */
-#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */
-#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */
-#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */
-#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */
-#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */
-#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */
-#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */
-#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */
-#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */
-#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */
-#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */
-#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */
-#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */
-#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */
-#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */
-#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */
-#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */
-#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */
-#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */
-#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */
-#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
-#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */
-#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */
-#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */
-#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */
-#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */
-#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */
-#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */
-#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */
-#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */
-#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */
-#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */
-#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */
-#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */
-#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */
-#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */
-#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */
-#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */
-#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */
-#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */
-#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */
-#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */
-#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */
-#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */
-#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */
-#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */
-#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */
-#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */
-#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */
-#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */
-#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */
-#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */
-#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */
-#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */
-#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */
-#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */
-#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */
-#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */
-#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */
-#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */
-#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */
-#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */
-#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */
-#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */
-#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
-#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */
-#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
-#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */
-#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
-
-
-
-/* =========================
- CHIPID
- ========================= */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-
-#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
deleted file mode 100644
index 872d141ca119..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/dma.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_TX 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT1_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT2_TX 4
-#define CH_SPORT2_RX 5
-#define CH_SPI0_TX 6
-#define CH_SPI0_RX 7
-#define CH_SPI1_TX 8
-#define CH_SPI1_RX 9
-#define CH_RSI 10
-#define CH_SDU 11
-#define CH_LP0 13
-#define CH_LP1 14
-#define CH_LP2 15
-#define CH_LP3 16
-#define CH_UART0_TX 17
-#define CH_UART0_RX 18
-#define CH_UART1_TX 19
-#define CH_UART1_RX 20
-#define CH_MEM_STREAM0_SRC_CRC0 21
-#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
-#define CH_MEM_STREAM0_DEST_CRC0 22
-#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
-#define CH_MEM_STREAM1_SRC_CRC1 23
-#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
-#define CH_MEM_STREAM1_DEST_CRC1 24
-#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM2_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-#define CH_MEM_STREAM3_DEST 28
-#define CH_EPPI0_CH0 29
-#define CH_EPPI0_CH1 30
-#define CH_EPPI1_CH0 31
-#define CH_EPPI1_CH1 32
-#define CH_EPPI2_CH0 33
-#define CH_EPPI2_CH1 34
-#define CH_PIXC_CH0 35
-#define CH_PIXC_CH1 36
-#define CH_PIXC_CH2 37
-#define CH_PVP_CPDOB 38
-#define CH_PVP_CPDOC 39
-#define CH_PVP_CPSTAT 40
-#define CH_PVP_CPCI 41
-#define CH_PVP_MPDO 42
-#define CH_PVP_MPDI 43
-#define CH_PVP_MPSTAT 44
-#define CH_PVP_MPCI 45
-#define CH_PVP_CPDOA 46
-
-#define MAX_DMA_CHANNELS 47
-#define MAX_DMA_SUSPEND_CHANNELS 0
-#define DMA_MMR_SIZE_32
-
-#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
-#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
-#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
-#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
-#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
-#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
-#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
-#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
-#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
-#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
-#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
-#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
-#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
-#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
-
-#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
-#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
-#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
-#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
-#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
-#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
-
-#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
-#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
-#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
-#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
-#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
-#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
-#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
-#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
-#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
-#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
-#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
-#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
-#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
-#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
deleted file mode 100644
index 07182513e794..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46
-#define GPIO_PC15 47
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 6
-#define NR_PINTS 112
-
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned long port_fer;
- unsigned long port_fer_set;
- unsigned long port_fer_clear;
- unsigned long data;
- unsigned long data_set;
- unsigned long data_clear;
- unsigned long dir;
- unsigned long dir_set;
- unsigned long dir_clear;
- unsigned long inen;
- unsigned long inen_set;
- unsigned long inen_clear;
- unsigned long port_mux;
- unsigned long toggle;
- unsigned long polar;
- unsigned long polar_set;
- unsigned long polar_clear;
- unsigned long lock;
- unsigned long spare;
- unsigned long revid;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
deleted file mode 100644
index d1cb6a86f80a..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF60x_IRQ_H_
-#define _BF60x_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (5 * 32)
-
-#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
-#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
-#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
-#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
-#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
-#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
-#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
-#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
-#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
-#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
-#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
-
-#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
-#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
-#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
-#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
-#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
-#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
-#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
-#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
-#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
-#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
-#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
-#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
-#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
-#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
-#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
-#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
-#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
-#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
-#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
-#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
-#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
-#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
-#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
-#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
-#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
-#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
-#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
-#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
-#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
-#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
-#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
-#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
-#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
-#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
-/* -- RESERVED -- 65 DMA12 Data (Reserved) */
-/* -- RESERVED -- 66 Reserved */
-/* -- RESERVED -- 67 Reserved */
-#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
-/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
-#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
-/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
-#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
-#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
-#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
-#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
-#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
-#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
-#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
-#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
-#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
-#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
-#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
-#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
-#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
-#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
-#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
-#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
-#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
-#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
-#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
-#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
-#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
-#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
-#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
-#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
-#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
-#define IRQ_MDMAS2 IRQ_MDMA2_DEST
-#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
-#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
-#define IRQ_MDMAS3 IRQ_MDMA3_DEST
-#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
-#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
-#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
-#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
-#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
-#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
-#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
-#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
-#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
-#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
-#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
-#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
-#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
-#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
-#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
-#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
-#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
-#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
-#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
-#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
-#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
-#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
-#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
-#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
-#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
-#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
-#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
-#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
-#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
-#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
-/* -- RESERVED -- 130 Reserved */
-#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
-/* -- RESERVED -- 132 Reserved */
-#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
-#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
-#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
-#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
-#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
-#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
-#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
-
-#define SYS_IRQS IRQ_SWU6
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PG15 + 1)
-
-#define SEC_SCTL_PRIO_OFFSET 8
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-extern u8 sec_int_priority[];
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
deleted file mode 100644
index 20b65bfc5311..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/mem_map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * BF60x memory map
- *
- * Copyright 2011 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xC8000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF60x processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#define L1_CODE_LENGTH 0x10000
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define COREB_L1_CODE_LENGTH 0x14000
-#define COREB_L1_DATA_A_LENGTH 0x8000
-#define COREB_L1_DATA_B_LENGTH 0x8000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xC8080000
-#define L2_LENGTH 0x40000
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
deleted file mode 100644
index 1857a4a0f262..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
deleted file mode 100644
index a1efd936dd30..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __MACH_BF609_PM_H__
-#define __MACH_BF609_PM_H__
-
-#include <linux/suspend.h>
-#include <linux/platform_device.h>
-
-extern int bfin609_pm_enter(suspend_state_t state);
-extern int bf609_pm_prepare(void);
-extern void bf609_pm_finish(void);
-
-void bf609_hibernate(void);
-void bfin_sec_raise_irq(unsigned int sid);
-void coreb_enable(void);
-
-int bf609_nor_flash_init(struct platform_device *pdev);
-void bf609_nor_flash_exit(struct platform_device *pdev);
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
deleted file mode 100644
index c48bb71a55ce..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_PTPPPS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-
-#define P_RMII1 {\
- P_MII1_ETxD0, \
- P_MII1_ETxD1, \
- P_MII1_ETxEN, \
- P_MII1_ERxD0, \
- P_MII1_ERxD1, \
- P_MII1_ERxER, \
- P_MII1_TxCLK, \
- P_MII1_PHYINT, \
- P_MII1_CRS, \
- P_MII1_PTPPPS, \
- P_MII1_MDC, \
- P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* CORE IDLE */
-#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-/* CAN */
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-/* SPORT */
-#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
-#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
-#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
-#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
-#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
-#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
-#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
-#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
-#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
-#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
-
-#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
-#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
-#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
-#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
-#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
-#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
-#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-
-#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
-#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-
-/* LINK PORT */
-#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
-#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
-#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
-#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
-#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
-#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
-#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
-#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
-#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
-#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
-
-#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
-#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
-#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
-#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
-#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
-#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
-#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
-#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
-#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
-#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
-
-#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
-#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
-#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
-#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
-#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-/* Rotary Encoder */
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
deleted file mode 100644
index f68abb9aa79e..000000000000
--- a/arch/blackfin/mach-bf609/ints-priority.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-u8 sec_int_priority[] = {
- 255, /* IRQ_SEC_ERR */
- 255, /* IRQ_CGU_EVT */
- 254, /* IRQ_WATCH0 */
- 254, /* IRQ_WATCH1 */
- 253, /* IRQ_L2CTL0_ECC_ERR */
- 253, /* IRQ_L2CTL0_ECC_WARN */
- 253, /* IRQ_C0_DBL_FAULT */
- 253, /* IRQ_C1_DBL_FAULT */
- 252, /* IRQ_C0_HW_ERR */
- 252, /* IRQ_C1_HW_ERR */
- 255, /* IRQ_C0_NMI_L1_PARITY_ERR */
- 255, /* IRQ_C1_NMI_L1_PARITY_ERR */
-
- 50, /* IRQ_TIMER0 */
- 50, /* IRQ_TIMER1 */
- 50, /* IRQ_TIMER2 */
- 50, /* IRQ_TIMER3 */
- 50, /* IRQ_TIMER4 */
- 50, /* IRQ_TIMER5 */
- 50, /* IRQ_TIMER6 */
- 50, /* IRQ_TIMER7 */
- 50, /* IRQ_TIMER_STAT */
- 0, /* IRQ_PINT0 */
- 0, /* IRQ_PINT1 */
- 0, /* IRQ_PINT2 */
- 0, /* IRQ_PINT3 */
- 0, /* IRQ_PINT4 */
- 0, /* IRQ_PINT5 */
- 0, /* IRQ_CNT */
- 50, /* RQ_PWM0_TRIP */
- 50, /* IRQ_PWM0_SYNC */
- 50, /* IRQ_PWM1_TRIP */
- 50, /* IRQ_PWM1_SYNC */
- 0, /* IRQ_TWI0 */
- 0, /* IRQ_TWI1 */
- 10, /* IRQ_SOFT0 */
- 10, /* IRQ_SOFT1 */
- 10, /* IRQ_SOFT2 */
- 10, /* IRQ_SOFT3 */
- 0, /* IRQ_ACM_EVT_MISS */
- 0, /* IRQ_ACM_EVT_COMPLETE */
- 0, /* IRQ_CAN0_RX */
- 0, /* IRQ_CAN0_TX */
- 0, /* IRQ_CAN0_STAT */
- 100, /* IRQ_SPORT0_TX */
- 100, /* IRQ_SPORT0_TX_STAT */
- 100, /* IRQ_SPORT0_RX */
- 100, /* IRQ_SPORT0_RX_STAT */
- 100, /* IRQ_SPORT1_TX */
- 100, /* IRQ_SPORT1_TX_STAT */
- 100, /* IRQ_SPORT1_RX */
- 100, /* IRQ_SPORT1_RX_STAT */
- 100, /* IRQ_SPORT2_TX */
- 100, /* IRQ_SPORT2_TX_STAT */
- 100, /* IRQ_SPORT2_RX */
- 100, /* IRQ_SPORT2_RX_STAT */
- 0, /* IRQ_SPI0_TX */
- 0, /* IRQ_SPI0_RX */
- 0, /* IRQ_SPI0_STAT */
- 0, /* IRQ_SPI1_TX */
- 0, /* IRQ_SPI1_RX */
- 0, /* IRQ_SPI1_STAT */
- 0, /* IRQ_RSI */
- 0, /* IRQ_RSI_INT0 */
- 0, /* IRQ_RSI_INT1 */
- 0, /* DMA11 Data (SDU) */
- 0, /* DMA12 Data (Reserved) */
- 0, /* Reserved */
- 0, /* Reserved */
- 30, /* IRQ_EMAC0_STAT */
- 0, /* EMAC0 Power (Reserved) */
- 30, /* IRQ_EMAC1_STAT */
- 0, /* EMAC1 Power (Reserved) */
- 0, /* IRQ_LP0 */
- 0, /* IRQ_LP0_STAT */
- 0, /* IRQ_LP1 */
- 0, /* IRQ_LP1_STAT */
- 0, /* IRQ_LP2 */
- 0, /* IRQ_LP2_STAT */
- 0, /* IRQ_LP3 */
- 0, /* IRQ_LP3_STAT */
- 0, /* IRQ_UART0_TX */
- 0, /* IRQ_UART0_RX */
- 0, /* IRQ_UART0_STAT */
- 0, /* IRQ_UART1_TX */
- 0, /* IRQ_UART1_RX */
- 0, /* IRQ_UART1_STAT */
- 0, /* IRQ_MDMA0_SRC_CRC0 */
- 0, /* IRQ_MDMA0_DEST_CRC0 */
- 0, /* IRQ_CRC0_DCNTEXP */
- 0, /* IRQ_CRC0_ERR */
- 0, /* IRQ_MDMA1_SRC_CRC1 */
- 0, /* IRQ_MDMA1_DEST_CRC1 */
- 0, /* IRQ_CRC1_DCNTEXP */
- 0, /* IRQ_CRC1_ERR */
- 0, /* IRQ_MDMA2_SRC */
- 0, /* IRQ_MDMA2_DEST */
- 0, /* IRQ_MDMA3_SRC */
- 0, /* IRQ_MDMA3_DEST */
- 120, /* IRQ_EPPI0_CH0 */
- 120, /* IRQ_EPPI0_CH1 */
- 120, /* IRQ_EPPI0_STAT */
- 120, /* IRQ_EPPI2_CH0 */
- 120, /* IRQ_EPPI2_CH1 */
- 120, /* IRQ_EPPI2_STAT */
- 120, /* IRQ_EPPI1_CH0 */
- 120, /* IRQ_EPPI1_CH1 */
- 120, /* IRQ_EPPI1_STAT */
- 120, /* IRQ_PIXC_CH0 */
- 120, /* IRQ_PIXC_CH1 */
- 120, /* IRQ_PIXC_CH2 */
- 120, /* IRQ_PIXC_STAT */
- 120, /* IRQ_PVP_CPDOB */
- 120, /* IRQ_PVP_CPDOC */
- 120, /* IRQ_PVP_CPSTAT */
- 120, /* IRQ_PVP_CPCI */
- 120, /* IRQ_PVP_STAT0 */
- 120, /* IRQ_PVP_MPDO */
- 120, /* IRQ_PVP_MPDI */
- 120, /* IRQ_PVP_MPSTAT */
- 120, /* IRQ_PVP_MPCI */
- 120, /* IRQ_PVP_CPDOA */
- 120, /* IRQ_PVP_STAT1 */
- 0, /* IRQ_USB_STAT */
- 0, /* IRQ_USB_DMA */
- 0, /* IRQ_TRU_INT0 */
- 0, /* IRQ_TRU_INT1 */
- 0, /* IRQ_TRU_INT2 */
- 0, /* IRQ_TRU_INT3 */
- 0, /* IRQ_DMAC0_ERROR */
- 0, /* IRQ_CGU0_ERROR */
- 0, /* Reserved */
- 0, /* IRQ_DPM */
- 0, /* Reserved */
- 0, /* IRQ_SWU0 */
- 0, /* IRQ_SWU1 */
- 0, /* IRQ_SWU2 */
- 0, /* IRQ_SWU3 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU6 */
-};
-
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
deleted file mode 100644
index b1bfcf434d16..000000000000
--- a/arch/blackfin/mach-bf609/pm.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <mach/pm.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-
-/***********************************************************/
-/* */
-/* Wakeup Actions for DPM_RESTORE */
-/* */
-/***********************************************************/
-#define BITP_ROM_WUA_CHKHDR 24
-#define BITP_ROM_WUA_DDRLOCK 7
-#define BITP_ROM_WUA_DDRDLLEN 6
-#define BITP_ROM_WUA_DDR 5
-#define BITP_ROM_WUA_CGU 4
-#define BITP_ROM_WUA_MEMBOOT 2
-#define BITP_ROM_WUA_EN 1
-
-#define BITM_ROM_WUA_CHKHDR (0xFF000000)
-#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
-
-#define BITM_ROM_WUA_DDRLOCK (0x00000080)
-#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
-#define BITM_ROM_WUA_DDR (0x00000020)
-#define BITM_ROM_WUA_CGU (0x00000010)
-#define BITM_ROM_WUA_MEMBOOT (0x00000002)
-#define BITM_ROM_WUA_EN (0x00000001)
-
-/***********************************************************/
-/* */
-/* Syscontrol */
-/* */
-/***********************************************************/
-#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
-#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
-#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
-#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
-#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
-#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
-#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
-#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
-#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
-#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
-#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
-#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
-#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
-
-#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
-#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
-#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
-#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
-#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
-#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
-#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
-#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
-#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
-#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
-#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
-#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
-#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
-#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
-#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
-
-
-/* Structures for the syscontrol() function */
-struct STRUCT_ROM_SYSCTRL {
- uint32_t ulCGU_CTL;
- uint32_t ulCGU_STAT;
- uint32_t ulCGU_DIV;
- uint32_t ulCGU_CLKOUTSEL;
- uint32_t ulWUA_Flags;
- uint32_t ulWUA_BootAddr;
- uint32_t ulWUA_User;
- uint32_t ulDDR_CTL;
- uint32_t ulDDR_CFG;
- uint32_t ulDDR_TR0;
- uint32_t ulDDR_TR1;
- uint32_t ulDDR_TR2;
- uint32_t ulDDR_MR;
- uint32_t ulDDR_EMR1;
- uint32_t ulDDR_EMR2;
- uint32_t ulDDR_PADCTL;
- uint32_t ulDDR_DLLCTL;
- uint32_t ulReserved;
-};
-
-struct bfin_pm_data {
- uint32_t magic;
- uint32_t resume_addr;
- uint32_t sp;
-};
-
-struct bfin_pm_data bf609_pm_data;
-
-struct STRUCT_ROM_SYSCTRL configvalues;
-uint32_t dactionflags;
-
-#define FUNC_ROM_SYSCONTROL 0xC8000080
-__attribute__((l1_data))
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
-
-__attribute__((l1_text))
-void bfin_cpu_suspend(void)
-{
- __asm__ __volatile__( \
- ".align 8;" \
- "idle;" \
- : : \
- );
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr(void)
-{
- dmc_enter_self_refresh();
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
-{
- dmc_exit_self_refresh();
-
- /* After wake up from deep sleep and exit DDR from self refress mode,
- * should wait till CGU PLL is locked.
- */
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-}
-
-__attribute__((l1_text))
-void bf609_resume_ccbuf(void)
-{
- bfin_write32(DPM0_CCBF_EN, 3);
- bfin_write32(DPM0_CTL, 2);
-
- while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
-}
-
-__attribute__((l1_text))
-void bfin_hibernate_syscontrol(void)
-{
- configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
- | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
-
- dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
- | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
- | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
-
- bfrom_SysControl(dactionflags, &configvalues, NULL);
-
- bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
-}
-
-asmlinkage void enter_deepsleep(void);
-
-__attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- SSYNC();
- enter_deepsleep();
-}
-
-void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
- bfin_write32(DPM0_HIB_DIS, 0xFFFF);
-
- bf609_hibernate();
-}
-
-void bf609_cpu_pm_enter(suspend_state_t state)
-{
- int error;
- unsigned long wakeup = 0;
- unsigned long wakeup_pol = 0;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PA15
- wakeup |= PA15WE;
-# if CONFIG_PM_BFIN_WAKE_PA15_POL
- wakeup_pol |= PA15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PB15
- wakeup |= PB15WE;
-# if CONFIG_PM_BFIN_WAKE_PB15_POL
- wakeup_pol |= PB15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PC15
- wakeup |= PC15WE;
-# if CONFIG_PM_BFIN_WAKE_PC15_POL
- wakeup_pol |= PC15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PD06
- wakeup |= PD06WE;
-# if CONFIG_PM_BFIN_WAKE_PD06_POL
- wakeup_pol |= PD06WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- wakeup |= PE12WE;
-# if CONFIG_PM_BFIN_WAKE_PE12_POL
- wakeup_pol |= PE12WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG04
- wakeup |= PG04WE;
-# if CONFIG_PM_BFIN_WAKE_PG04_POL
- wakeup_pol |= PG04WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG13
- wakeup |= PG13WE;
-# if CONFIG_PM_BFIN_WAKE_PG13_POL
- wakeup_pol |= PG13WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_USB
- wakeup |= USBWE;
-# if CONFIG_PM_BFIN_WAKE_USB_POL
- wakeup_pol |= USBWE;
-# endif
-#endif
-
- error = irq_set_irq_wake(255, 1);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
- error = irq_set_irq_wake(231, 1);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
-
- if (state == PM_SUSPEND_STANDBY)
- bfin_deepsleep(wakeup, wakeup_pol);
- else {
- bfin_hibernate(wakeup, wakeup_pol);
- }
-
-}
-
-int bf609_cpu_pm_prepare(void)
-{
- return 0;
-}
-
-void bf609_cpu_pm_finish(void)
-{
-
-}
-
-static struct bfin_cpu_pm_fns bf609_cpu_pm = {
- .enter = bf609_cpu_pm_enter,
- .prepare = bf609_cpu_pm_prepare,
- .finish = bf609_cpu_pm_finish,
-};
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static int smc_pm_syscore_suspend(void)
-{
- bf609_nor_flash_exit(NULL);
- return 0;
-}
-
-static void smc_pm_syscore_resume(void)
-{
- bf609_nor_flash_init(NULL);
-}
-
-static struct syscore_ops smc_pm_syscore_ops = {
- .suspend = smc_pm_syscore_suspend,
- .resume = smc_pm_syscore_resume,
-};
-#endif
-
-static irqreturn_t test_isr(int irq, void *dev_id)
-{
- printk(KERN_DEBUG "gpio irq %d\n", irq);
- if (irq == 231)
- bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1));
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dpm0_isr(int irq, void *dev_id)
-{
- bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
- bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
- return IRQ_HANDLED;
-}
-
-static int __init bf609_init_pm(void)
-{
- int irq;
- int error;
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
- register_syscore_ops(&smc_pm_syscore_ops);
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- irq = gpio_to_irq(GPIO_PE12);
- if (irq < 0) {
- error = irq;
- printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
- GPIO_PE12, error);
- }
-
- error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
- | IRQF_FORCE_RESUME, "gpiope12", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-#endif
-
- error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "cgu0 event", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "dpm0 event", NULL);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- bfin_cpu_pm = &bf609_cpu_pm;
- return 0;
-}
-
-late_initcall(bf609_init_pm);
diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c
deleted file mode 100644
index ac1f07c33594..000000000000
--- a/arch/blackfin/mach-bf609/scb.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/scb.h>
-
-struct scb_mi_prio scb_data[] = {
-#ifdef CONFIG_SCB0_MI0
- { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
- CONFIG_SCB0_MI0_SLOT0,
- CONFIG_SCB0_MI0_SLOT1,
- CONFIG_SCB0_MI0_SLOT2,
- CONFIG_SCB0_MI0_SLOT3,
- CONFIG_SCB0_MI0_SLOT4,
- CONFIG_SCB0_MI0_SLOT5,
- CONFIG_SCB0_MI0_SLOT6,
- CONFIG_SCB0_MI0_SLOT7,
- CONFIG_SCB0_MI0_SLOT8,
- CONFIG_SCB0_MI0_SLOT9,
- CONFIG_SCB0_MI0_SLOT10,
- CONFIG_SCB0_MI0_SLOT11,
- CONFIG_SCB0_MI0_SLOT12,
- CONFIG_SCB0_MI0_SLOT13,
- CONFIG_SCB0_MI0_SLOT14,
- CONFIG_SCB0_MI0_SLOT15,
- CONFIG_SCB0_MI0_SLOT16,
- CONFIG_SCB0_MI0_SLOT17,
- CONFIG_SCB0_MI0_SLOT18,
- CONFIG_SCB0_MI0_SLOT19,
- CONFIG_SCB0_MI0_SLOT20,
- CONFIG_SCB0_MI0_SLOT21,
- CONFIG_SCB0_MI0_SLOT22,
- CONFIG_SCB0_MI0_SLOT23,
- CONFIG_SCB0_MI0_SLOT24,
- CONFIG_SCB0_MI0_SLOT25,
- CONFIG_SCB0_MI0_SLOT26,
- CONFIG_SCB0_MI0_SLOT27,
- CONFIG_SCB0_MI0_SLOT28,
- CONFIG_SCB0_MI0_SLOT29,
- CONFIG_SCB0_MI0_SLOT30,
- CONFIG_SCB0_MI0_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI1
- { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
- CONFIG_SCB0_MI1_SLOT0,
- CONFIG_SCB0_MI1_SLOT1,
- CONFIG_SCB0_MI1_SLOT2,
- CONFIG_SCB0_MI1_SLOT3,
- CONFIG_SCB0_MI1_SLOT4,
- CONFIG_SCB0_MI1_SLOT5,
- CONFIG_SCB0_MI1_SLOT6,
- CONFIG_SCB0_MI1_SLOT7,
- CONFIG_SCB0_MI1_SLOT8,
- CONFIG_SCB0_MI1_SLOT9,
- CONFIG_SCB0_MI1_SLOT10,
- CONFIG_SCB0_MI1_SLOT11,
- CONFIG_SCB0_MI1_SLOT12,
- CONFIG_SCB0_MI1_SLOT13,
- CONFIG_SCB0_MI1_SLOT14,
- CONFIG_SCB0_MI1_SLOT15,
- CONFIG_SCB0_MI1_SLOT16,
- CONFIG_SCB0_MI1_SLOT17,
- CONFIG_SCB0_MI1_SLOT18,
- CONFIG_SCB0_MI1_SLOT19,
- CONFIG_SCB0_MI1_SLOT20,
- CONFIG_SCB0_MI1_SLOT21,
- CONFIG_SCB0_MI1_SLOT22,
- CONFIG_SCB0_MI1_SLOT23,
- CONFIG_SCB0_MI1_SLOT24,
- CONFIG_SCB0_MI1_SLOT25,
- CONFIG_SCB0_MI1_SLOT26,
- CONFIG_SCB0_MI1_SLOT27,
- CONFIG_SCB0_MI1_SLOT28,
- CONFIG_SCB0_MI1_SLOT29,
- CONFIG_SCB0_MI1_SLOT30,
- CONFIG_SCB0_MI1_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI2
- { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
- CONFIG_SCB0_MI2_SLOT0,
- CONFIG_SCB0_MI2_SLOT1,
- CONFIG_SCB0_MI2_SLOT2,
- CONFIG_SCB0_MI2_SLOT3,
- CONFIG_SCB0_MI2_SLOT4,
- CONFIG_SCB0_MI2_SLOT5,
- CONFIG_SCB0_MI2_SLOT6,
- CONFIG_SCB0_MI2_SLOT7,
- CONFIG_SCB0_MI2_SLOT8,
- CONFIG_SCB0_MI2_SLOT9,
- CONFIG_SCB0_MI2_SLOT10,
- CONFIG_SCB0_MI2_SLOT11,
- CONFIG_SCB0_MI2_SLOT12,
- CONFIG_SCB0_MI2_SLOT13,
- CONFIG_SCB0_MI2_SLOT14,
- CONFIG_SCB0_MI2_SLOT15,
- CONFIG_SCB0_MI2_SLOT16,
- CONFIG_SCB0_MI2_SLOT17,
- CONFIG_SCB0_MI2_SLOT18,
- CONFIG_SCB0_MI2_SLOT19,
- CONFIG_SCB0_MI2_SLOT20,
- CONFIG_SCB0_MI2_SLOT21,
- CONFIG_SCB0_MI2_SLOT22,
- CONFIG_SCB0_MI2_SLOT23,
- CONFIG_SCB0_MI2_SLOT24,
- CONFIG_SCB0_MI2_SLOT25,
- CONFIG_SCB0_MI2_SLOT26,
- CONFIG_SCB0_MI2_SLOT27,
- CONFIG_SCB0_MI2_SLOT28,
- CONFIG_SCB0_MI2_SLOT29,
- CONFIG_SCB0_MI2_SLOT30,
- CONFIG_SCB0_MI2_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI3
- { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
- CONFIG_SCB0_MI3_SLOT0,
- CONFIG_SCB0_MI3_SLOT1,
- CONFIG_SCB0_MI3_SLOT2,
- CONFIG_SCB0_MI3_SLOT3,
- CONFIG_SCB0_MI3_SLOT4,
- CONFIG_SCB0_MI3_SLOT5,
- CONFIG_SCB0_MI3_SLOT6,
- CONFIG_SCB0_MI3_SLOT7,
- CONFIG_SCB0_MI3_SLOT8,
- CONFIG_SCB0_MI3_SLOT9,
- CONFIG_SCB0_MI3_SLOT10,
- CONFIG_SCB0_MI3_SLOT11,
- CONFIG_SCB0_MI3_SLOT12,
- CONFIG_SCB0_MI3_SLOT13,
- CONFIG_SCB0_MI3_SLOT14,
- CONFIG_SCB0_MI3_SLOT15,
- CONFIG_SCB0_MI3_SLOT16,
- CONFIG_SCB0_MI3_SLOT17,
- CONFIG_SCB0_MI3_SLOT18,
- CONFIG_SCB0_MI3_SLOT19,
- CONFIG_SCB0_MI3_SLOT20,
- CONFIG_SCB0_MI3_SLOT21,
- CONFIG_SCB0_MI3_SLOT22,
- CONFIG_SCB0_MI3_SLOT23,
- CONFIG_SCB0_MI3_SLOT24,
- CONFIG_SCB0_MI3_SLOT25,
- CONFIG_SCB0_MI3_SLOT26,
- CONFIG_SCB0_MI3_SLOT27,
- CONFIG_SCB0_MI3_SLOT28,
- CONFIG_SCB0_MI3_SLOT29,
- CONFIG_SCB0_MI3_SLOT30,
- CONFIG_SCB0_MI3_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI4
- { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
- CONFIG_SCB0_MI4_SLOT0,
- CONFIG_SCB0_MI4_SLOT1,
- CONFIG_SCB0_MI4_SLOT2,
- CONFIG_SCB0_MI4_SLOT3,
- CONFIG_SCB0_MI4_SLOT4,
- CONFIG_SCB0_MI4_SLOT5,
- CONFIG_SCB0_MI4_SLOT6,
- CONFIG_SCB0_MI4_SLOT7,
- CONFIG_SCB0_MI4_SLOT8,
- CONFIG_SCB0_MI4_SLOT9,
- CONFIG_SCB0_MI4_SLOT10,
- CONFIG_SCB0_MI4_SLOT11,
- CONFIG_SCB0_MI4_SLOT12,
- CONFIG_SCB0_MI4_SLOT13,
- CONFIG_SCB0_MI4_SLOT14,
- CONFIG_SCB0_MI4_SLOT15,
- CONFIG_SCB0_MI4_SLOT16,
- CONFIG_SCB0_MI4_SLOT17,
- CONFIG_SCB0_MI4_SLOT18,
- CONFIG_SCB0_MI4_SLOT19,
- CONFIG_SCB0_MI4_SLOT20,
- CONFIG_SCB0_MI4_SLOT21,
- CONFIG_SCB0_MI4_SLOT22,
- CONFIG_SCB0_MI4_SLOT23,
- CONFIG_SCB0_MI4_SLOT24,
- CONFIG_SCB0_MI4_SLOT25,
- CONFIG_SCB0_MI4_SLOT26,
- CONFIG_SCB0_MI4_SLOT27,
- CONFIG_SCB0_MI4_SLOT28,
- CONFIG_SCB0_MI4_SLOT29,
- CONFIG_SCB0_MI4_SLOT30,
- CONFIG_SCB0_MI4_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI5
- { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
- CONFIG_SCB0_MI5_SLOT0,
- CONFIG_SCB0_MI5_SLOT1,
- CONFIG_SCB0_MI5_SLOT2,
- CONFIG_SCB0_MI5_SLOT3,
- CONFIG_SCB0_MI5_SLOT4,
- CONFIG_SCB0_MI5_SLOT5,
- CONFIG_SCB0_MI5_SLOT6,
- CONFIG_SCB0_MI5_SLOT7,
- CONFIG_SCB0_MI5_SLOT8,
- CONFIG_SCB0_MI5_SLOT9,
- CONFIG_SCB0_MI5_SLOT10,
- CONFIG_SCB0_MI5_SLOT11,
- CONFIG_SCB0_MI5_SLOT12,
- CONFIG_SCB0_MI5_SLOT13,
- CONFIG_SCB0_MI5_SLOT14,
- CONFIG_SCB0_MI5_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB1_MI0
- { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
- CONFIG_SCB1_MI0_SLOT0,
- CONFIG_SCB1_MI0_SLOT1,
- CONFIG_SCB1_MI0_SLOT2,
- CONFIG_SCB1_MI0_SLOT3,
- CONFIG_SCB1_MI0_SLOT4,
- CONFIG_SCB1_MI0_SLOT5,
- CONFIG_SCB1_MI0_SLOT6,
- CONFIG_SCB1_MI0_SLOT7,
- CONFIG_SCB1_MI0_SLOT8,
- CONFIG_SCB1_MI0_SLOT9,
- CONFIG_SCB1_MI0_SLOT10,
- CONFIG_SCB1_MI0_SLOT11,
- CONFIG_SCB1_MI0_SLOT12,
- CONFIG_SCB1_MI0_SLOT13,
- CONFIG_SCB1_MI0_SLOT14,
- CONFIG_SCB1_MI0_SLOT15,
- CONFIG_SCB1_MI0_SLOT16,
- CONFIG_SCB1_MI0_SLOT17,
- CONFIG_SCB1_MI0_SLOT18,
- CONFIG_SCB1_MI0_SLOT19
- },
- },
-#endif
-#ifdef CONFIG_SCB2_MI0
- { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
- CONFIG_SCB2_MI0_SLOT0,
- CONFIG_SCB2_MI0_SLOT1,
- CONFIG_SCB2_MI0_SLOT2,
- CONFIG_SCB2_MI0_SLOT3,
- CONFIG_SCB2_MI0_SLOT4,
- CONFIG_SCB2_MI0_SLOT5,
- CONFIG_SCB2_MI0_SLOT6,
- CONFIG_SCB2_MI0_SLOT7,
- CONFIG_SCB2_MI0_SLOT8,
- CONFIG_SCB2_MI0_SLOT9
- },
- },
-#endif
-#ifdef CONFIG_SCB3_MI0
- { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
- CONFIG_SCB3_MI0_SLOT0,
- CONFIG_SCB3_MI0_SLOT1,
- CONFIG_SCB3_MI0_SLOT2,
- CONFIG_SCB3_MI0_SLOT3,
- CONFIG_SCB3_MI0_SLOT4,
- CONFIG_SCB3_MI0_SLOT5,
- CONFIG_SCB3_MI0_SLOT6,
- CONFIG_SCB3_MI0_SLOT7,
- CONFIG_SCB3_MI0_SLOT8,
- CONFIG_SCB3_MI0_SLOT9,
- CONFIG_SCB3_MI0_SLOT10,
- CONFIG_SCB3_MI0_SLOT11,
- CONFIG_SCB3_MI0_SLOT12,
- CONFIG_SCB3_MI0_SLOT13,
- CONFIG_SCB3_MI0_SLOT14,
- CONFIG_SCB3_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB4_MI0
- { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
- CONFIG_SCB4_MI0_SLOT0,
- CONFIG_SCB4_MI0_SLOT1,
- CONFIG_SCB4_MI0_SLOT2,
- CONFIG_SCB4_MI0_SLOT3,
- CONFIG_SCB4_MI0_SLOT4,
- CONFIG_SCB4_MI0_SLOT5,
- CONFIG_SCB4_MI0_SLOT6,
- CONFIG_SCB4_MI0_SLOT7,
- CONFIG_SCB4_MI0_SLOT8,
- CONFIG_SCB4_MI0_SLOT9,
- CONFIG_SCB4_MI0_SLOT10,
- CONFIG_SCB4_MI0_SLOT11,
- CONFIG_SCB4_MI0_SLOT12,
- CONFIG_SCB4_MI0_SLOT13,
- CONFIG_SCB4_MI0_SLOT14,
- CONFIG_SCB4_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB5_MI0
- { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
- CONFIG_SCB5_MI0_SLOT0,
- CONFIG_SCB5_MI0_SLOT1,
- CONFIG_SCB5_MI0_SLOT2,
- CONFIG_SCB5_MI0_SLOT3,
- CONFIG_SCB5_MI0_SLOT4,
- CONFIG_SCB5_MI0_SLOT5,
- CONFIG_SCB5_MI0_SLOT6,
- CONFIG_SCB5_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB6_MI0
- { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
- CONFIG_SCB6_MI0_SLOT0,
- CONFIG_SCB6_MI0_SLOT1,
- CONFIG_SCB6_MI0_SLOT2,
- CONFIG_SCB6_MI0_SLOT3
- },
- },
-#endif
-#ifdef CONFIG_SCB7_MI0
- { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
- CONFIG_SCB7_MI0_SLOT0,
- CONFIG_SCB7_MI0_SLOT1,
- CONFIG_SCB7_MI0_SLOT2,
- CONFIG_SCB7_MI0_SLOT3,
- CONFIG_SCB7_MI0_SLOT4,
- CONFIG_SCB7_MI0_SLOT5
- },
- },
-#endif
-#ifdef CONFIG_SCB8_MI0
- { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
- CONFIG_SCB8_MI0_SLOT0,
- CONFIG_SCB8_MI0_SLOT1,
- CONFIG_SCB8_MI0_SLOT2,
- CONFIG_SCB8_MI0_SLOT3,
- CONFIG_SCB8_MI0_SLOT4,
- CONFIG_SCB8_MI0_SLOT5,
- CONFIG_SCB8_MI0_SLOT6,
- CONFIG_SCB8_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB9_MI0
- { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
- CONFIG_SCB9_MI0_SLOT0,
- CONFIG_SCB9_MI0_SLOT1,
- CONFIG_SCB9_MI0_SLOT2,
- CONFIG_SCB9_MI0_SLOT3,
- CONFIG_SCB9_MI0_SLOT4,
- CONFIG_SCB9_MI0_SLOT5,
- CONFIG_SCB9_MI0_SLOT6,
- CONFIG_SCB9_MI0_SLOT7,
- CONFIG_SCB9_MI0_SLOT8,
- CONFIG_SCB9_MI0_SLOT9
- },
- },
-#endif
- { 0, }
-};
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
deleted file mode 100644
index fcef1c8e117f..000000000000
--- a/arch/blackfin/mach-common/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-common/Makefile
-#
-
-obj-y := \
- cache.o cache-c.o entry.o head.o \
- interrupt.o arch_checks.o ints-priority.o
-
-obj-$(CONFIG_PM) += pm.o
-ifneq ($(CONFIG_BF60x),y)
-obj-$(CONFIG_PM) += dpmc_modes.o
-endif
-obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
-obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
deleted file mode 100644
index d8643fdd0fcf..000000000000
--- a/arch/blackfin/mach-common/arch_checks.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Do some checking to make sure things are OK
- *
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/fixed_code.h>
-#include <mach/anomaly.h>
-#include <asm/clocks.h>
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-
-# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
-# error "VCO selected is more than maximum value. Please change the VCO multipler"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
-# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
-# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
-# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-# error "Please select sclk less than cclk"
-# endif
-
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-#if CONFIG_BOOT_LOAD < FIXED_CODE_END
-# error "The kernel load address must be after the fixed code section"
-#endif
-
-#if (CONFIG_BOOT_LOAD & 0x3)
-# error "The kernel load address must be 4 byte aligned"
-#endif
-
-/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
-#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
-# error "The kernel load address is too high; keep it below 10meg for safety"
-#endif
-
-#if ANOMALY_05000263 && defined(CONFIG_MPU)
-# error the MPU will not function safely while Anomaly 05000263 applies
-#endif
-
-#if ANOMALY_05000448
-# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
-#endif
-
-/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
-#if ANOMALY_05000220 && \
- (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
-# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
-#endif
-
-#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
-# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
-#endif
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
deleted file mode 100644
index f4adedc92895..000000000000
--- a/arch/blackfin/mach-common/cache-c.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Blackfin cache control code (simpler control-style functions)
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-
-/* Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-void blackfin_invalidate_entire_dcache(void)
-{
- u32 dmem = bfin_read_DMEM_CONTROL();
- bfin_write_DMEM_CONTROL(dmem & ~0xc);
- SSYNC();
- bfin_write_DMEM_CONTROL(dmem);
- SSYNC();
-}
-
-/* Invalidate the Entire Instruction cache by
- * clearing IMC bit
- */
-void blackfin_invalidate_entire_icache(void)
-{
- u32 imem = bfin_read_IMEM_CONTROL();
- bfin_write_IMEM_CONTROL(imem & ~0x4);
- SSYNC();
- bfin_write_IMEM_CONTROL(imem);
- SSYNC();
-}
-
-#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
-
-static void
-bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
- unsigned long cplb_data, unsigned long mem_control,
- unsigned long mem_mask)
-{
- int i;
-#ifdef CONFIG_L1_PARITY_CHECK
- u32 ctrl;
-
- if (cplb_addr == DCPLB_ADDR0) {
- ctrl = bfin_read32(mem_control) | (1 << RDCHK);
- CSYNC();
- bfin_write32(mem_control, ctrl);
- SSYNC();
- }
-#endif
-
- for (i = 0; i < MAX_CPLBS; i++) {
- bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
- bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
- }
-
- _enable_cplb(mem_control, mem_mask);
-}
-
-#ifdef CONFIG_BFIN_ICACHE
-void bfin_icache_init(struct cplb_entry *icplb_tbl)
-{
- bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
- (IMC | ENICPLB));
-}
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
-{
- /*
- * Anomaly notes:
- * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
- * register, so that the port preferences for DAG0 and DAG1 are set
- * to port B
- */
- bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
- (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
-}
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
deleted file mode 100644
index 9f4dd35bfd74..000000000000
--- a/arch/blackfin/mach-common/cache.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Blackfin cache control code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/page.h>
-
-/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
-#if ANOMALY_05000443
-# define BROK_FLUSH_INST "IFLUSH"
-#else
-# define BROK_FLUSH_INST "no anomaly! yeah!"
-#endif
-
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them. Only the actual flush instruction differs. We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req label
-
- R2 = -L1_CACHE_BYTES;
-
- /* start = (start & -L1_CACHE_BYTES) */
- R0 = R0 & R2;
-
- /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
- R1 += -1;
- R1 = R1 & R2;
- R1 += L1_CACHE_BYTES;
-
- /* count = (end - start) >> L1_CACHE_SHIFT */
- R2 = R1 - R0;
- R2 >>= L1_CACHE_SHIFT;
- P1 = R2;
-
-.ifnb \label
-\label :
-.endif
- P0 = R0;
-
- LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifeqs "\flushins", BROK_FLUSH_INST
- \flushins [P0++];
- nop;
- nop;
-2: nop;
-.else
-2: \flushins [P0++];
-.endif
-
- RTS;
-.endm
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-#ifdef CONFIG_SMP
-# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1
-#endif
-ENTRY(_blackfin_icache_flush_range)
- do_flush IFLUSH
-ENDPROC(_blackfin_icache_flush_range)
-
-#ifdef CONFIG_SMP
-.text
-# undef _blackfin_icache_flush_range
-ENTRY(_blackfin_icache_flush_range)
- p0.L = LO(DSPID);
- p0.H = HI(DSPID);
- r3 = [p0];
- r3 = r3.b (z);
- p2 = r3;
- p0.L = _blackfin_iflush_l1_entry;
- p0.H = _blackfin_iflush_l1_entry;
- p0 = p0 + (p2 << 2);
- p1 = [p0];
- jump (p1);
-ENDPROC(_blackfin_icache_flush_range)
-#endif
-
-#ifdef CONFIG_DCACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back. Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate. Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_invalidate_range)
- do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
- do_flush FLUSH, .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)
-
-/* Our headers convert the page structure to an address, so just need to flush
- * its contents like normal. We know the start address is page aligned (which
- * greater than our cache alignment), as is the end address. So just jump into
- * the middle of the dcache flush function.
- */
-ENTRY(_blackfin_dflush_page)
- P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
- jump .Ldfr;
-ENDPROC(_blackfin_dflush_page)
diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h
deleted file mode 100644
index fed851a51aaf..000000000000
--- a/arch/blackfin/mach-common/clock.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_COMMON_CLKDEV_H
-#define __MACH_COMMON_CLKDEV_H
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- const struct params *params;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-#endif
-
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
deleted file mode 100644
index d436bd907fc8..000000000000
--- a/arch/blackfin/mach-common/clocks-init.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-#include <asm/dma.h>
-#include <asm/clocks.h>
-#include <asm/mem_init.h>
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_BF60x
-
-#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
-#define CGU_DIV_VAL \
- ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
- (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
- (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
- (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
- (CONFIG_DCLK_DIV << DSEL_OFFSET))
-
-#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
-#if ((CONFIG_BFIN_DCLK != 125) && \
- (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
- (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
- (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
-#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-
-#else
-#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
-#define PLL_CTL_VAL \
- (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
- (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
-#endif
-
-__attribute__((l1_text))
-static void do_sync(void)
-{
- __builtin_bfin_ssync();
-}
-
-__attribute__((l1_text))
-void init_clocks(void)
-{
- /* Kill any active DMAs as they may trigger external memory accesses
- * in the middle of reprogramming things, and that'll screw us up.
- * For example, any automatic DMAs left by U-Boot for splash screens.
- */
-#ifdef CONFIG_BF60x
- init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
- init_dmc(CONFIG_BFIN_DCLK);
-#else
- size_t i;
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- struct dma_register *dma = dma_io_base_addr[i];
- dma->cfg = 0;
- }
-
- do_sync();
-
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_ENABLE(0));
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_ENABLE(0));
-#endif
- do_sync();
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
- do_sync();
-#endif
-
-#ifdef CLKBUFOE
- bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
- do_sync();
- __asm__ __volatile__("IDLE;");
-#endif
- bfin_write_PLL_LOCKCNT(0x300);
- do_sync();
- /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
- bfin_write16(PLL_CTL, PLL_CTL_VAL);
- __asm__ __volatile__("IDLE;");
- bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDRRC(mem_SDRRC);
- bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
-#else
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
- do_sync();
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
- bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
- bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
- bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
-#ifdef CONFIG_MEM_EBIU_DDRQUE
- bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
-#endif
-#endif
-#endif
- do_sync();
- bfin_read16(0);
-
-}
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
deleted file mode 100644
index 724a8c5f5578..000000000000
--- a/arch/blackfin/mach-common/dpmc.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/cpufreq.h>
-
-#include <asm/delay.h>
-#include <asm/dpmc.h>
-
-#define DRIVER_NAME "bfin dpmc"
-
-struct bfin_dpmc_platform_data *pdata;
-
-/**
- * bfin_set_vlev - Update VLEV field in VR_CTL Reg.
- * Avoid BYPASS sequence
- */
-static void bfin_set_vlev(unsigned int vlev)
-{
- unsigned pll_lcnt;
-
- pll_lcnt = bfin_read_PLL_LOCKCNT();
-
- bfin_write_PLL_LOCKCNT(1);
- bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev);
- bfin_write_PLL_LOCKCNT(pll_lcnt);
-}
-
-/**
- * bfin_get_vlev - Get CPU specific VLEV from platform device data
- */
-static unsigned int bfin_get_vlev(unsigned int freq)
-{
- int i;
-
- if (!pdata)
- goto err_out;
-
- freq >>= 16;
-
- for (i = 0; i < pdata->tabsize; i++)
- if (freq <= (pdata->tuple_tab[i] & 0xFFFF))
- return pdata->tuple_tab[i] >> 16;
-
-err_out:
- printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n");
- return VLEV_120;
-}
-
-#ifdef CONFIG_CPU_FREQ
-# ifdef CONFIG_SMP
-static void bfin_idle_this_cpu(void *info)
-{
- unsigned long flags = 0;
- unsigned long iwr0, iwr1, iwr2;
- unsigned int cpu = smp_processor_id();
-
- local_irq_save_hw(flags);
- bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2);
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- SSYNC();
- asm("IDLE;");
- bfin_iwr_restore(iwr0, iwr1, iwr2);
-
- local_irq_restore_hw(flags);
-}
-
-static void bfin_idle_cpu(void)
-{
- smp_call_function(bfin_idle_this_cpu, NULL, 0);
-}
-
-static void bfin_wakeup_cpu(void)
-{
- unsigned int cpu;
- unsigned int this_cpu = smp_processor_id();
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
-}
-
-# else
-static void bfin_idle_cpu(void) {}
-static void bfin_wakeup_cpu(void) {}
-# endif
-
-static int
-vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
-{
- struct cpufreq_freqs *freq = data;
-
- if (freq->cpu != CPUFREQ_CPU)
- return 0;
-
- if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- udelay(pdata->vr_settling_time); /* Wait until Volatge settled */
- bfin_wakeup_cpu();
- } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- bfin_wakeup_cpu();
- }
-
- return 0;
-}
-
-static struct notifier_block vreg_cpufreq_notifier_block = {
- .notifier_call = vreg_cpufreq_notifier
-};
-#endif /* CONFIG_CPU_FREQ */
-
-/**
- * bfin_dpmc_probe -
- *
- */
-static int bfin_dpmc_probe(struct platform_device *pdev)
-{
- if (pdev->dev.platform_data)
- pdata = pdev->dev.platform_data;
- else
- return -EINVAL;
-
- return cpufreq_register_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-/**
- * bfin_dpmc_remove -
- */
-static int bfin_dpmc_remove(struct platform_device *pdev)
-{
- pdata = NULL;
- return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-struct platform_driver bfin_dpmc_device_driver = {
- .probe = bfin_dpmc_probe,
- .remove = bfin_dpmc_remove,
- .driver = {
- .name = DRIVER_NAME,
- }
-};
-module_platform_driver(bfin_dpmc_device_driver);
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("cpu power management driver for Blackfin");
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
deleted file mode 100644
index de99f3aac2c5..000000000000
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <asm/dpmc.h>
-
-.section .l1.text
-ENTRY(_sleep_mode)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R1 = W[P0](z);
- BITSET (R1, 3);
- W[P0] = R1.L;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R7 = w[p0](z);
- BITCLR (R7, 3);
- BITCLR (R7, 5);
- w[p0] = R7.L;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_mode)
-
-/*
- * This func never returns as it puts the part into hibernate, and
- * is only called from do_hibernate, so we don't bother saving or
- * restoring any of the normal C runtime state. When we wake up,
- * the entry point will be in do_hibernate and not here.
- *
- * We accept just one argument -- the value to write to VR_CTL.
- */
-
-ENTRY(_hibernate_mode)
- /* Save/setup the regs we need early for minor pipeline optimization */
- R4 = R0;
-
- P3.H = hi(VR_CTL);
- P3.L = lo(VR_CTL);
- /* Disable all wakeup sources */
- R0 = IWR_DISABLE_ALL;
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
- call _set_sic_iwr;
- call _set_dram_srfs;
- SSYNC;
-
- /* Finally, we climb into our cave to hibernate */
- W[P3] = R4.L;
-
- bfin_init_pm_bench_cycles;
-
- CLI R2;
- IDLE;
-.Lforever:
- jump .Lforever;
-ENDPROC(_hibernate_mode)
-
-ENTRY(_sleep_deeper)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- CLI R4;
-
- P3 = R0;
- P4 = R1;
- P5 = R2;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
- call _set_dram_srfs; /* Set SDRAM Self Refresh */
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- R6 = W[P0](z);
- R0.L = 0xF;
- W[P0] = R0.l; /* Set Max VCO to SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R5 = W[P0](z);
- R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
- W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- R7 = W[P0](z);
- R1 = 0x6;
- R1 <<= 16;
- R2 = 0x0404(Z);
- R1 = R1|R2;
-
- R2 = DEPOSIT(R7, R1);
- W[P0] = R2; /* Set Min Core Voltage */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = P3;
- R1 = P4;
- R3 = P5;
- call _set_sic_iwr; /* Set Awake from IDLE */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R0 = W[P0](z);
- BITSET (R0, 3);
- W[P0] = R0.L; /* Turn CCLK OFF */
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr; /* Set Awake from IDLE PLL */
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- W[P0]= R7;
-
- SSYNC;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- W[P0]= R6; /* Restore CCLK and SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- w[p0] = R5; /* Restore VCO multiplier */
- IDLE;
- call _test_pll_locked;
-
- call _unset_dram_srfs; /* SDRAM Self Refresh Off */
-
- STI R4;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_deeper)
-
-ENTRY(_set_dram_srfs)
- /* set the dram to self refresh mode */
- SSYNC;
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITSET(R2, 3); /* SRREQ enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-1:
- R2 = [P0];
- CC = BITTST(R2, 4);
- if !CC JUMP 1b;
-#else /* SDRAM */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
- P1.L = lo(EBIU_SDSTAT);
- P1.H = hi(EBIU_SDSTAT);
-
- R2 = [P0];
- BITSET(R2, 24); /* SRFS enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-
-1:
- R2 = w[P1];
- SSYNC;
- cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
- if !cc jump 1b;
-
- R2 = [P0];
- BITCLR(R2, 0); /* SCTLE disable CLKOUT */
- [P0] = R2;
-#endif
- RTS;
-ENDPROC(_set_dram_srfs)
-
-ENTRY(_unset_dram_srfs)
- /* set the dram out of self refresh mode */
-
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITCLR(R2, 3); /* clear SRREQ bit */
- [P0] = R2;
-#elif defined(EBIU_SDGCTL) /* SDRAM */
- /* release CLKOUT from self-refresh */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
-
- R2 = [P0];
- BITSET(R2, 0); /* SCTLE enable CLKOUT */
- [P0] = R2
- SSYNC;
-
- /* release SDRAM from self-refresh */
- R2 = [P0];
- BITCLR(R2, 24); /* clear SRFS bit */
- [P0] = R2
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_unset_dram_srfs)
-
-ENTRY(_set_sic_iwr)
-#ifdef SIC_IWR0
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
-# ifdef SIC_IWR2
- [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
-# endif
-#else
- P0.H = hi(SIC_IWR);
- P0.L = lo(SIC_IWR);
- [P0] = R0;
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_set_sic_iwr)
-
-ENTRY(_test_pll_locked)
- P0.H = hi(PLL_STAT);
- P0.L = lo(PLL_STAT);
-1:
- R0 = W[P0] (Z);
- CC = BITTST(R0,5);
- IF !CC JUMP 1b;
- RTS;
-ENDPROC(_test_pll_locked)
-
-.section .text
-ENTRY(_do_hibernate)
- bfin_cpu_reg_save;
- bfin_sys_mmr_save;
- bfin_core_mmr_save;
-
- /* Setup args to hibernate mode early for pipeline optimization */
- R0 = M3;
- P1.H = _hibernate_mode;
- P1.L = _hibernate_mode;
-
- /* Save Magic, return address and Stack Pointer */
- P0 = 0;
- R1.H = 0xDEAD; /* Hibernate Magic */
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1; /* Store Hibernate Magic */
- [P0++] = R2; /* Save Return Address */
- [P0++] = SP; /* Save Stack Pointer */
-
- /* Must use an indirect call as we need to jump to L1 */
- call (P1); /* Goodbye */
-
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_sys_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
deleted file mode 100644
index 8d9431e22e8c..000000000000
--- a/arch/blackfin/mach-common/entry.S
+++ /dev/null
@@ -1,1711 +0,0 @@
-/*
- * Contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all
- * interrupts and faults that can result in a task-switch.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/unistd.h>
-#include <asm/blackfin.h>
-#include <asm/errno.h>
-#include <asm/fixed_code.h>
-#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-
-#include <asm/context.S>
-
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Slightly simplified and streamlined entry point for CPLB misses.
- * This one does not lower the level to IRQ5, and thus can be used to
- * patch up CPLB misses on the kernel stack.
- */
-#if ANOMALY_05000261
-#define _ex_dviol _ex_workaround_261
-#define _ex_dmiss _ex_workaround_261
-#define _ex_dmult _ex_workaround_261
-
-ENTRY(_ex_workaround_261)
- /*
- * Work around an anomaly: if we see a new DCPLB fault, return
- * without doing anything. Then, if we get the same fault again,
- * handle it.
- */
- P4 = R7; /* Store EXCAUSE */
-
- GET_PDA(p5, r7);
- r7 = [p5 + PDA_LFRETX];
- r6 = retx;
- [p5 + PDA_LFRETX] = r6;
- cc = r6 == r7;
- if !cc jump _bfin_return_from_exception;
- /* fall through */
- R7 = P4;
- R6 = VEC_CPLB_M; /* Data CPLB Miss */
- cc = R6 == R7;
- if cc jump _ex_dcplb_miss (BP);
-#ifdef CONFIG_MPU
- R6 = VEC_CPLB_VL; /* Data CPLB Violation */
- cc = R6 == R7;
- if cc jump _ex_dcplb_viol (BP);
-#endif
- /* Handle Data CPLB Protection Violation
- * and Data CPLB Multiple Hits - Linux Trap Zero
- */
- jump _ex_trap_c;
-ENDPROC(_ex_workaround_261)
-
-#else
-#ifdef CONFIG_MPU
-#define _ex_dviol _ex_dcplb_viol
-#else
-#define _ex_dviol _ex_trap_c
-#endif
-#define _ex_dmiss _ex_dcplb_miss
-#define _ex_dmult _ex_trap_c
-#endif
-
-
-ENTRY(_ex_dcplb_viol)
-ENTRY(_ex_dcplb_miss)
-ENTRY(_ex_icplb_miss)
- (R7:6,P5:4) = [sp++];
- /* We leave the previously pushed ASTAT on the stack. */
- SAVE_CONTEXT_CPLB
-
- /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that
- * will change the stack pointer. */
- R0 = SEQSTAT;
- R1 = SP;
-
- DEBUG_HWTRACE_SAVE(p5, r7)
-
- sp += -12;
- call _cplb_hdr;
- sp += 12;
- CC = R0 == 0;
- IF !CC JUMP _handle_bad_cplb;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing this, did we double fault? */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = 0x25;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- DEBUG_HWTRACE_RESTORE(p5, r7)
- RESTORE_CONTEXT_CPLB
- ASTAT = [SP++];
- SP = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_ex_icplb_miss)
-
-ENTRY(_ex_syscall)
- raise 15; /* invoked by TRAP #0, for sys call */
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_syscall)
-
-ENTRY(_ex_single_step)
- /* If we just returned from an interrupt, the single step event is
- for the RTI instruction. */
- r7 = retx;
- r6 = reti;
- cc = r7 == r6;
- if cc jump _bfin_return_from_exception;
-
-#ifdef CONFIG_KGDB
- /* Don't do single step in hardware exception handler */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- cc = bittst(r6, 4);
- if cc jump _bfin_return_from_exception;
- cc = bittst(r6, 5);
- if cc jump _bfin_return_from_exception;
-
- /* skip single step if current interrupt priority is higher than
- * that of the first instruction, from which gdb starts single step */
- r6 >>= 6;
- r7 = 10;
-.Lfind_priority_start:
- cc = bittst(r6, 0);
- if cc jump .Lfind_priority_done;
- r6 >>= 1;
- r7 += -1;
- cc = r7 == 0;
- if cc jump .Lfind_priority_done;
- jump.s .Lfind_priority_start;
-.Lfind_priority_done:
- p4.l = _kgdb_single_step;
- p4.h = _kgdb_single_step;
- r6 = [p4];
- cc = r6 == 0;
- if cc jump .Ldo_single_step;
- r6 += -1;
- cc = r6 < r7;
- if cc jump 1f;
-.Ldo_single_step:
-#else
- /* If we were in user mode, do the single step normally. */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- r7 = 0xffe0 (z);
- r7 = r7 & r6;
- cc = r7 == 0;
- if !cc jump 1f;
-#endif
-#ifdef CONFIG_EXACT_HWERR
- /* Read the ILAT, and to check to see if the process we are
- * single stepping caused a previous hardware error
- * If so, do not single step, (which lowers to IRQ5, and makes
- * us miss the error).
- */
- p5.l = lo(ILAT);
- p5.h = hi(ILAT);
- r7 = [p5];
- cc = bittst(r7, EVT_IVHW_P);
- if cc jump 1f;
-#endif
- /* Single stepping only a single instruction, so clear the trace
- * bit here. */
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P);
- syscfg = R7;
- jump _ex_trap_c;
-
-1:
- /*
- * We were in an interrupt handler. By convention, all of them save
- * SYSCFG with their first instruction, so by checking whether our
- * RETX points at the entry point, we can determine whether to allow
- * a single step, or whether to clear SYSCFG.
- *
- * First, find out the interrupt level and the event vector for it.
- */
- p5.l = lo(EVT0);
- p5.h = hi(EVT0);
- p5 += -4;
-2:
- r7 = rot r7 by -1;
- p5 += 4;
- if !cc jump 2b;
-
- /* What we actually do is test for the _second_ instruction in the
- * IRQ handler. That way, if there are insns following the restore
- * of SYSCFG after leaving the handler, we will not turn off SYSCFG
- * for them. */
-
- r7 = [p5];
- r7 += 2;
- r6 = RETX;
- cc = R7 == R6;
- if !cc jump _bfin_return_from_exception;
-
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = R7;
-
- /* Fall through to _bfin_return_from_exception. */
-ENDPROC(_ex_single_step)
-
-ENTRY(_bfin_return_from_exception)
-#if ANOMALY_05000257
- R7=LC0;
- LC0=R7;
- R7=LC1;
- LC1=R7;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing the current exception,
- * did we cause another, and double fault?
- */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = VEC_UNCOV;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- sp = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_bfin_return_from_exception)
-
-ENTRY(_handle_bad_cplb)
- DEBUG_HWTRACE_RESTORE(p5, r7)
- /* To get here, we just tried and failed to change a CPLB
- * so, handle things in trap_c (C code), by lowering to
- * IRQ5, just like we normally do. Since this is not a
- * "normal" return path, we have a do a lot of stuff to
- * the stack to get ready so, we can fall through - we
- * need to make a CPLB exception look like a normal exception
- */
- RESTORE_CONTEXT_CPLB
- /* ASTAT is still on the stack, where it is needed. */
- [--sp] = (R7:6,P5:4);
-
-ENTRY(_ex_replaceable)
- nop;
-
-ENTRY(_ex_trap_c)
- /* The only thing that has been saved in this context is
- * (R7:6,P5:4), ASTAT & SP - don't use anything else
- */
-
- GET_PDA(p5, r6);
-
- /* Make sure we are not in a double fault */
- p4.l = lo(IPEND);
- p4.h = hi(IPEND);
- r7 = [p4];
- CC = BITTST (r7, 5);
- if CC jump _double_fault;
- [p5 + PDA_EXIPEND] = r7;
-
- /* Call C code (trap_c) to handle the exception, which most
- * likely involves sending a signal to the current process.
- * To avoid double faults, lower our priority to IRQ5 first.
- */
- r7.h = _exception_to_level5;
- r7.l = _exception_to_level5;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r6 = [p4];
- [p5 + PDA_ICPLB] = r6;
-
- r6 = retx;
- [p5 + PDA_RETX] = r6;
-
- r6 = SEQSTAT;
- [p5 + PDA_SEQSTAT] = r6;
-
- /* Save the state of single stepping */
- r6 = SYSCFG;
- [p5 + PDA_SYSCFG] = r6;
- /* Clear it while we handle the exception in IRQ5 mode */
- BITCLR(r6, SYSCFG_SSSTEP_P);
- SYSCFG = r6;
-
- /* Save the current IMASK, since we change in order to jump to level 5 */
- cli r6;
- [p5 + PDA_EXIMASK] = r6;
-
- p4.l = lo(SAFE_USER_INSTRUCTION);
- p4.h = hi(SAFE_USER_INSTRUCTION);
- retx = p4;
-
- /* Disable all interrupts, but make sure level 5 is enabled so
- * we can switch to that level.
- */
- r6 = 0x3f;
- sti r6;
-
- /* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
- * clear it (re-enabling interrupts again) by the special sequence of pushing
- * RETI onto the stack. This way we can lower ourselves to IVG5 even if the
- * exception was taken after the interrupt handler was called but before it
- * got a chance to enable global interrupts itself.
- */
- [--sp] = reti;
- sp += 4;
-
- raise 5;
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_trap_c)
-
-/* We just realized we got an exception, while we were processing a different
- * exception. This is a unrecoverable event, so crash.
- * Note: this cannot be ENTRY() as we jump here with "if cc jump" ...
- */
-ENTRY(_double_fault)
- /* Turn caches & protection off, to ensure we don't get any more
- * double exceptions
- */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- /* Fix up the stack */
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- SP = EX_SCRATCH_REG;
-
- /* We should be out of the exception stack, and back down into
- * kernel or user space stack
- */
- SAVE_ALL_SYS
-
- /* The dumping functions expect the return address in the RETI
- * slot. */
- r6 = retx;
- [sp + PT_PC] = r6;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _double_fault_c, p5;
- SP += 12;
-.L_double_fault_panic:
- JUMP .L_double_fault_panic
-
-ENDPROC(_double_fault)
-
-ENTRY(_exception_to_level5)
- SAVE_ALL_SYS
-
- GET_PDA(p5, r7); /* Fetch current PDA */
- r6 = [p5 + PDA_RETX];
- [sp + PT_PC] = r6;
-
- r6 = [p5 + PDA_SYSCFG];
- [sp + PT_SYSCFG] = r6;
-
- r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */
- [sp + PT_SEQSTAT] = r6;
-
- /* Restore the hardware error vector. */
- r7.h = _evt_ivhw;
- r7.l = _evt_ivhw;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Now that we have the hardware error vector programmed properly
- * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes
- * another hardware error, we can catch it (self-nesting).
- */
- [--sp] = reti;
- sp += 4;
-#endif
-
- r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */
- [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p4;
- SP += 12;
-
- /* If interrupts were off during the exception (IPEND[4] = 1), turn them off
- * before we return.
- */
- CC = BITTST(r7, EVT_IRPTEN_P)
- if !CC jump 1f;
- /* this will load a random value into the reti register - but that is OK,
- * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro
- */
- sp += -4;
- reti = [sp++];
-1:
- /* restore the interrupt mask (IMASK) */
- r6 = [p5 + PDA_EXIMASK];
- sti r6;
-
- call _ret_from_exception;
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_exception_to_level5)
-
-ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
- /* Since the kernel stack can be anywhere, it's not guaranteed to be
- * covered by a CPLB. Switch to an exception stack; use RETN as a
- * scratch register (for want of a better option).
- */
- EX_SCRATCH_REG = sp;
- GET_PDA_SAFE(sp);
- sp = [sp + PDA_EXSTACK];
- /* Try to deal with syscalls quickly. */
- [--sp] = ASTAT;
- [--sp] = (R7:6,P5:4);
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
-#ifdef CONFIG_EXACT_HWERR
- /* Make sure all pending read/writes complete. This will ensure any
- * accesses which could cause hardware errors completes, and signal
- * the the hardware before we do something silly, like crash the
- * kernel. We don't need to work around anomaly 05000312, since
- * we are already atomic
- */
- ssync;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- GET_PDA(p5, r7);
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_ICPLB] = r7;
-
- r7 = retx;
- [p5 + PDA_DF_RETX] = r7;
-
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- [p5 + PDA_DF_SEQSTAT] = r7;
-#else
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
-#endif
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- p5.h = _ex_table;
- p5.l = _ex_table;
- p4 = r7;
- p5 = p5 + (p4 << 2);
- p4 = [p5];
- jump (p4);
-
-.Lbadsys:
- r7 = -ENOSYS; /* signextending enough */
- [sp + PT_R0] = r7; /* return value from system call */
- jump .Lsyscall_really_exit;
-ENDPROC(_trap)
-
-ENTRY(_system_call)
- /* Store IPEND */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* Store RETS for now */
- r0 = rets;
- [sp + PT_RESERVED] = r0;
- /* Set the stack for the current process */
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6; /* thread_info */
- p2 = r7;
- p2 = [p2];
-
- [p2+(TASK_THREAD+THREAD_KSP)] = sp;
-#ifdef CONFIG_IPIPE
- r0 = sp;
- SP += -12;
- pseudo_long_call ___ipipe_syscall_root, p0;
- SP += 12;
- cc = r0 == 1;
- if cc jump .Lsyscall_really_exit;
- cc = r0 == -1;
- if cc jump .Lresume_userspace;
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- p0 = [sp + PT_ORIG_P0];
-#endif /* CONFIG_IPIPE */
-
- /* are we tracing syscalls?*/
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6;
- p2 = r7;
- r7 = [p2+TI_FLAGS];
- CC = BITTST(r7,TIF_SYSCALL_TRACE);
- if CC JUMP _sys_trace;
- CC = BITTST(r7,TIF_SINGLESTEP);
- if CC JUMP _sys_trace;
-
- /* Make sure the system call # is valid */
- p4 = __NR_syscall;
- /* System call number is passed in P0 */
- cc = p4 <= p0;
- if cc jump .Lbadsys;
-
- /* Execute the appropriate system call */
-
- p4 = p0;
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
- [sp + PT_R0] = r0;
-
-.Lresume_userspace:
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
-.Lresume_userspace_1:
- /* Disable interrupts. */
- [--sp] = reti;
- reti = [sp++];
-
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
-
-.Lsyscall_resched:
-#ifdef CONFIG_IPIPE
- cc = BITTST(r7, TIF_IRQ_SYNC);
- if !cc jump .Lsyscall_no_irqsync;
- /*
- * Clear IPEND[4] manually to undo what resume_userspace_1 just did;
- * we need this so that high priority domain interrupts may still
- * preempt the current domain while the pipeline log is being played
- * back.
- */
- [--sp] = reti;
- SP += 4; /* don't merge with next insn to keep the pattern obvious */
- SP += -12;
- pseudo_long_call ___ipipe_sync_root, p4;
- SP += 12;
- jump .Lresume_userspace_1;
-.Lsyscall_no_irqsync:
-#endif
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lsyscall_sigpending;
-
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- SP += -12;
- pseudo_long_call _schedule, p4;
- SP += 12;
-
- jump .Lresume_userspace_1;
-
-.Lsyscall_sigpending:
- cc = BITTST(r7, TIF_SIGPENDING);
- if cc jump .Lsyscall_do_signals;
- cc = BITTST(r7, TIF_NOTIFY_RESUME);
- if !cc jump .Lsyscall_really_exit;
-.Lsyscall_do_signals:
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- r0 = sp;
- SP += -12;
- pseudo_long_call _do_notify_resume, p5;
- SP += 12;
-
-.Lsyscall_really_exit:
- r5 = [sp + PT_RESERVED];
- rets = r5;
- rts;
-ENDPROC(_system_call)
-
-/* Do not mark as ENTRY() to avoid error in assembler ...
- * this symbol need not be global anyways, so ...
- */
-_sys_trace:
- r0 = sp;
- pseudo_long_call _syscall_trace_enter, p5;
-
- /* Make sure the system call # is valid */
- p4 = [SP + PT_P0];
- p3 = __NR_syscall;
- cc = p3 <= p4;
- r0 = -ENOSYS;
- if cc jump .Lsys_trace_badsys;
-
- /* Execute the appropriate system call */
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- r5 = [sp + PT_R5];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
-.Lsys_trace_badsys:
- [sp + PT_R0] = r0;
-
- r0 = sp;
- pseudo_long_call _syscall_trace_leave, p5;
- jump .Lresume_userspace;
-ENDPROC(_sys_trace)
-
-ENTRY(_resume)
- /*
- * Beware - when entering resume, prev (the current task) is
- * in r0, next (the new task) is in r1.
- */
- p0 = r0;
- p1 = r1;
- [--sp] = rets;
- [--sp] = fp;
- [--sp] = (r7:4, p5:3);
-
- /* save usp */
- p2 = usp;
- [p0+(TASK_THREAD+THREAD_USP)] = p2;
-
- /* save current kernel stack pointer */
- [p0+(TASK_THREAD+THREAD_KSP)] = sp;
-
- /* save program counter */
- r1.l = _new_old_task;
- r1.h = _new_old_task;
- [p0+(TASK_THREAD+THREAD_PC)] = r1;
-
- /* restore the kernel stack pointer */
- sp = [p1+(TASK_THREAD+THREAD_KSP)];
-
- /* restore user stack pointer */
- p0 = [p1+(TASK_THREAD+THREAD_USP)];
- usp = p0;
-
- /* restore pc */
- p0 = [p1+(TASK_THREAD+THREAD_PC)];
- jump (p0);
-
- /*
- * Following code actually lands up in a new (old) task.
- */
-
-_new_old_task:
- (r7:4, p5:3) = [sp++];
- fp = [sp++];
- rets = [sp++];
-
- /*
- * When we come out of resume, r0 carries "old" task, because we are
- * in "new" task.
- */
- rts;
-ENDPROC(_resume)
-
-ENTRY(_ret_from_exception)
-#ifdef CONFIG_IPIPE
- p2.l = _ipipe_percpu_domain;
- p2.h = _ipipe_percpu_domain;
- r0.l = _ipipe_root;
- r0.h = _ipipe_root;
- r2 = [p2];
- cc = r0 == r2;
- if !cc jump 4f; /* not on behalf of the root domain, get out */
-#endif /* CONFIG_IPIPE */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
-
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
-1:
- r2 = LO(~0x37) (Z);
- r0 = r2 & r0;
- cc = r0 == 0;
- if !cc jump 4f; /* if not return to user mode, get out */
-
- /* Make sure any pending system call or deferred exception
- * return in ILAT for this process to get executed, otherwise
- * in case context switch happens, system call of
- * first process (i.e in ILAT) will be carried
- * forward to the switched process
- */
-
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- r1 = (EVT_IVG14 | EVT_IVG15) (z);
- r0 = r0 & r1;
- cc = r0 == 0;
- if !cc jump 5f;
-
- /* Set the stack for the current process */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = r7 == 0;
- if cc jump 4f;
-
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal;
- p1.h = _schedule_and_signal;
- [p0] = p1;
- csync;
- raise 15; /* raise evt15 to do signal or reschedule */
-4:
- r0 = syscfg;
- bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = r0;
-5:
- rts;
-ENDPROC(_ret_from_exception)
-
-#if defined(CONFIG_PREEMPT)
-
-ENTRY(_up_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
-
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_up_evt14;
- p1.h = _evt_up_evt14;
- [p0] = p1;
- csync;
-
- raise 14;
-1:
- jump 1b;
-ENDPROC(_up_to_irq14)
-
-ENTRY(_evt_up_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
-
- /* restore normal evt14 */
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_evt14;
- p1.h = _evt_evt14;
- [p0] = p1;
- csync;
-
- rts;
-ENDPROC(_evt_up_evt14)
-
-#endif
-
-#ifdef CONFIG_IPIPE
-
-_resume_kernel_from_int:
- r1 = LO(~0x8000) (Z);
- r1 = r0 & r1;
- r0 = 1;
- r0 = r1 - r0;
- r2 = r1 & r0;
- cc = r2 == 0;
- /* Sync the root stage only from the outer interrupt level. */
- if !cc jump .Lnosync;
- r0.l = ___ipipe_sync_root;
- r0.h = ___ipipe_sync_root;
- [--sp] = reti;
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- SP += -12;
- call ___ipipe_call_irqtail
- SP += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
- reti = [sp++];
-.Lnosync:
- rts
-#elif defined(CONFIG_PREEMPT)
-
-_resume_kernel_from_int:
- /* check preempt_count */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT];
- cc = r7 == 0x0;
- if !cc jump .Lreturn_to_kernel;
-.Lneed_schedule:
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lreturn_to_kernel;
- /*
- * let schedule done at level 15, otherwise sheduled process will run
- * at high level and block low level interrupt
- */
- r6 = reti; /* save reti */
- r5.l = .Lkernel_schedule;
- r5.h = .Lkernel_schedule;
- reti = r5;
- rti;
-.Lkernel_schedule:
- [--sp] = rets;
- sp += -12;
- pseudo_long_call _preempt_schedule_irq, p4;
- sp += 12;
- rets = [sp++];
-
- [--sp] = rets;
- sp += -12;
- /* up to irq14 so that reti after restore_all can return to irq15(kernel) */
- pseudo_long_call _up_to_irq14, p4;
- sp += 12;
- rets = [sp++];
-
- reti = r6; /* restore reti so that origin process can return to interrupted point */
-
- jump .Lneed_schedule;
-#else
-
-#define _resume_kernel_from_int .Lreturn_to_kernel
-#endif
-
-ENTRY(_return_from_int)
- /* If someone else already raised IRQ 15, do nothing. */
- csync;
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- cc = bittst (r0, EVT_IVG15_P);
- if cc jump .Lreturn_to_kernel;
-
- /* if not return to user mode, get out */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- r1 = 0x17(Z);
- r2 = ~r1;
- r2.h = 0;
- r0 = r2 & r0;
- r1 = 1;
- r1 = r0 - r1;
- r2 = r0 & r1;
- cc = r2 == 0;
- if !cc jump _resume_kernel_from_int;
-
- /* Lower the interrupt level to 15. */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal_from_int;
- p1.h = _schedule_and_signal_from_int;
- [p0] = p1;
- csync;
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
- r0 = 0x801f (z);
- STI r0;
- raise 15; /* raise evt15 to do signal or reschedule */
- rti;
-.Lreturn_to_kernel:
- rts;
-ENDPROC(_return_from_int)
-
-ENTRY(_lower_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14;
- rti;
-ENDPROC(_lower_to_irq14)
-
-ENTRY(_evt_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
- rts;
-ENDPROC(_evt_evt14)
-
-ENTRY(_schedule_and_signal_from_int)
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
-
- /* Set orig_p0 to -1 to indicate this isn't the end of a syscall. */
- r0 = -1 (x);
- [sp + PT_ORIG_P0] = r0;
-
- p1 = rets;
- [sp + PT_RESERVED] = p1;
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- /* trace_hardirqs_on() checks if all irqs are disabled. But here IRQ 15
- * is turned on, so disable all irqs. */
- cli r0;
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- /* finish the userspace "atomic" functions for it */
- r1.l = lo(FIXED_CODE_END);
- r1.h = hi(FIXED_CODE_END);
- r2 = [sp + PT_PC];
- cc = r1 <= r2;
- if cc jump .Lresume_userspace (bp);
-
- r0 = sp;
- sp += -12;
-
- pseudo_long_call _finish_atomic_sections, p5;
- sp += 12;
- jump.s .Lresume_userspace;
-ENDPROC(_schedule_and_signal_from_int)
-
-ENTRY(_schedule_and_signal)
- SAVE_CONTEXT_SYSCALL
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
- p0.l = 1f;
- p0.h = 1f;
- [sp + PT_RESERVED] = P0;
- call .Lresume_userspace;
-1:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_schedule_and_signal)
-
-/* We handle this 100% in exception space - to reduce overhead
- * Only potiential problem is if the software buffer gets swapped out of the
- * CPLB table - then double fault. - so we don't let this happen in other places
- */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-ENTRY(_ex_trace_buff_full)
- [--sp] = P3;
- [--sp] = P2;
- [--sp] = LC0;
- [--sp] = LT0;
- [--sp] = LB0;
- P5.L = _trace_buff_offset;
- P5.H = _trace_buff_offset;
- P3 = [P5]; /* trace_buff_offset */
- P5.L = lo(TBUFSTAT);
- P5.H = hi(TBUFSTAT);
- R7 = [P5];
- R7 <<= 1; /* double, since we need to read twice */
- LC0 = R7;
- R7 <<= 2; /* need to shift over again,
- * to get the number of bytes */
- P5.L = lo(TBUF);
- P5.H = hi(TBUF);
- R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1;
-
- P2 = R7;
- P3 = P3 + P2;
- R7 = P3;
- R7 = R7 & R6;
- P3 = R7;
- P2.L = _trace_buff_offset;
- P2.H = _trace_buff_offset;
- [P2] = P3;
-
- P2.L = _software_trace_buff;
- P2.H = _software_trace_buff;
-
- LSETUP (.Lstart, .Lend) LC0;
-.Lstart:
- R7 = [P5]; /* read TBUF */
- P4 = P3 + P2;
- [P4] = R7;
- P3 += -4;
- R7 = P3;
- R7 = R7 & R6;
-.Lend:
- P3 = R7;
-
- LB0 = [sp++];
- LT0 = [sp++];
- LC0 = [sp++];
- P2 = [sp++];
- P3 = [sp++];
- jump _bfin_return_from_exception;
-ENDPROC(_ex_trace_buff_full)
-
-#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4
-.data
-#else
-.section .l1.data.B
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */
-ENTRY(_trace_buff_offset)
- .long 0;
-ALIGN
-ENTRY(_software_trace_buff)
- .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256);
- .long 0
- .endr
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
-
-#ifdef CONFIG_EARLY_PRINTK
-__INIT
-ENTRY(_early_trap)
- SAVE_ALL_SYS
- trace_buffer_stop(p0,r0);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- /* Turn caches off, to ensure we don't get double exceptions */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- r1 = RETX;
-
- SP += -12;
- call _early_trap_c;
- SP += 12;
-ENDPROC(_early_trap)
-__FINIT
-#endif /* CONFIG_EARLY_PRINTK */
-
-/*
- * Put these in the kernel data section - that should always be covered by
- * a CPLB. This is needed to ensure we don't get double fault conditions
- */
-
-#ifdef CONFIG_SYSCALL_TAB_L1
-.section .l1.data
-#else
-.data
-#endif
-
-ENTRY(_ex_table)
- /* entry for each EXCAUSE[5:0]
- * This table must be in sync with the table in ./kernel/traps.c
- * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
- */
- .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
- .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */
-#ifdef CONFIG_KGDB
- .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection
- and break signal trap */
-#else
- .long _ex_replaceable /* 0x02 - User Defined */
-#endif
- .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
- .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
- .long _ex_replaceable /* 0x05 - User Defined */
- .long _ex_replaceable /* 0x06 - User Defined */
- .long _ex_replaceable /* 0x07 - User Defined */
- .long _ex_replaceable /* 0x08 - User Defined */
- .long _ex_replaceable /* 0x09 - User Defined */
- .long _ex_replaceable /* 0x0A - User Defined */
- .long _ex_replaceable /* 0x0B - User Defined */
- .long _ex_replaceable /* 0x0C - User Defined */
- .long _ex_replaceable /* 0x0D - User Defined */
- .long _ex_replaceable /* 0x0E - User Defined */
- .long _ex_replaceable /* 0x0F - User Defined */
- .long _ex_single_step /* 0x10 - HW Single step */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */
-#else
- .long _ex_trap_c /* 0x11 - Trace Buffer Full */
-#endif
- .long _ex_trap_c /* 0x12 - Reserved */
- .long _ex_trap_c /* 0x13 - Reserved */
- .long _ex_trap_c /* 0x14 - Reserved */
- .long _ex_trap_c /* 0x15 - Reserved */
- .long _ex_trap_c /* 0x16 - Reserved */
- .long _ex_trap_c /* 0x17 - Reserved */
- .long _ex_trap_c /* 0x18 - Reserved */
- .long _ex_trap_c /* 0x19 - Reserved */
- .long _ex_trap_c /* 0x1A - Reserved */
- .long _ex_trap_c /* 0x1B - Reserved */
- .long _ex_trap_c /* 0x1C - Reserved */
- .long _ex_trap_c /* 0x1D - Reserved */
- .long _ex_trap_c /* 0x1E - Reserved */
- .long _ex_trap_c /* 0x1F - Reserved */
- .long _ex_trap_c /* 0x20 - Reserved */
- .long _ex_trap_c /* 0x21 - Undefined Instruction */
- .long _ex_trap_c /* 0x22 - Illegal Instruction Combination */
- .long _ex_dviol /* 0x23 - Data CPLB Protection Violation */
- .long _ex_trap_c /* 0x24 - Data access misaligned */
- .long _ex_trap_c /* 0x25 - Unrecoverable Event */
- .long _ex_dmiss /* 0x26 - Data CPLB Miss */
- .long _ex_dmult /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero */
- .long _ex_trap_c /* 0x28 - Emulation Watchpoint */
- .long _ex_trap_c /* 0x29 - Instruction fetch access error (535 only) */
- .long _ex_trap_c /* 0x2A - Instruction fetch misaligned */
- .long _ex_trap_c /* 0x2B - Instruction CPLB protection Violation */
- .long _ex_icplb_miss /* 0x2C - Instruction CPLB miss */
- .long _ex_trap_c /* 0x2D - Instruction CPLB Multiple Hits */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2F - Reserved */
- .long _ex_trap_c /* 0x30 - Reserved */
- .long _ex_trap_c /* 0x31 - Reserved */
- .long _ex_trap_c /* 0x32 - Reserved */
- .long _ex_trap_c /* 0x33 - Reserved */
- .long _ex_trap_c /* 0x34 - Reserved */
- .long _ex_trap_c /* 0x35 - Reserved */
- .long _ex_trap_c /* 0x36 - Reserved */
- .long _ex_trap_c /* 0x37 - Reserved */
- .long _ex_trap_c /* 0x38 - Reserved */
- .long _ex_trap_c /* 0x39 - Reserved */
- .long _ex_trap_c /* 0x3A - Reserved */
- .long _ex_trap_c /* 0x3B - Reserved */
- .long _ex_trap_c /* 0x3C - Reserved */
- .long _ex_trap_c /* 0x3D - Reserved */
- .long _ex_trap_c /* 0x3E - Reserved */
- .long _ex_trap_c /* 0x3F - Reserved */
-END(_ex_table)
-
-ENTRY(_sys_call_table)
- .long _sys_restart_syscall /* 0 */
- .long _sys_exit
- .long _sys_ni_syscall /* fork */
- .long _sys_read
- .long _sys_write
- .long _sys_open /* 5 */
- .long _sys_close
- .long _sys_ni_syscall /* old waitpid */
- .long _sys_creat
- .long _sys_link
- .long _sys_unlink /* 10 */
- .long _sys_execve
- .long _sys_chdir
- .long _sys_time
- .long _sys_mknod
- .long _sys_chmod /* 15 */
- .long _sys_chown /* chown16 */
- .long _sys_ni_syscall /* old break syscall holder */
- .long _sys_ni_syscall /* old stat */
- .long _sys_lseek
- .long _sys_getpid /* 20 */
- .long _sys_mount
- .long _sys_ni_syscall /* old umount */
- .long _sys_setuid
- .long _sys_getuid
- .long _sys_stime /* 25 */
- .long _sys_ptrace
- .long _sys_alarm
- .long _sys_ni_syscall /* old fstat */
- .long _sys_pause
- .long _sys_ni_syscall /* old utime */ /* 30 */
- .long _sys_ni_syscall /* old stty syscall holder */
- .long _sys_ni_syscall /* old gtty syscall holder */
- .long _sys_access
- .long _sys_nice
- .long _sys_ni_syscall /* 35 */ /* old ftime syscall holder */
- .long _sys_sync
- .long _sys_kill
- .long _sys_rename
- .long _sys_mkdir
- .long _sys_rmdir /* 40 */
- .long _sys_dup
- .long _sys_pipe
- .long _sys_times
- .long _sys_ni_syscall /* old prof syscall holder */
- .long _sys_brk /* 45 */
- .long _sys_setgid
- .long _sys_getgid
- .long _sys_ni_syscall /* old sys_signal */
- .long _sys_geteuid /* geteuid16 */
- .long _sys_getegid /* getegid16 */ /* 50 */
- .long _sys_acct
- .long _sys_umount /* recycled never used phys() */
- .long _sys_ni_syscall /* old lock syscall holder */
- .long _sys_ioctl
- .long _sys_fcntl /* 55 */
- .long _sys_ni_syscall /* old mpx syscall holder */
- .long _sys_setpgid
- .long _sys_ni_syscall /* old ulimit syscall holder */
- .long _sys_ni_syscall /* old old uname */
- .long _sys_umask /* 60 */
- .long _sys_chroot
- .long _sys_ustat
- .long _sys_dup2
- .long _sys_getppid
- .long _sys_getpgrp /* 65 */
- .long _sys_setsid
- .long _sys_ni_syscall /* old sys_sigaction */
- .long _sys_sgetmask
- .long _sys_ssetmask
- .long _sys_setreuid /* setreuid16 */ /* 70 */
- .long _sys_setregid /* setregid16 */
- .long _sys_ni_syscall /* old sys_sigsuspend */
- .long _sys_ni_syscall /* old sys_sigpending */
- .long _sys_sethostname
- .long _sys_setrlimit /* 75 */
- .long _sys_ni_syscall /* old getrlimit */
- .long _sys_getrusage
- .long _sys_gettimeofday
- .long _sys_settimeofday
- .long _sys_getgroups /* getgroups16 */ /* 80 */
- .long _sys_setgroups /* setgroups16 */
- .long _sys_ni_syscall /* old_select */
- .long _sys_symlink
- .long _sys_ni_syscall /* old lstat */
- .long _sys_readlink /* 85 */
- .long _sys_uselib
- .long _sys_ni_syscall /* sys_swapon */
- .long _sys_reboot
- .long _sys_ni_syscall /* old_readdir */
- .long _sys_ni_syscall /* sys_mmap */ /* 90 */
- .long _sys_munmap
- .long _sys_truncate
- .long _sys_ftruncate
- .long _sys_fchmod
- .long _sys_fchown /* fchown16 */ /* 95 */
- .long _sys_getpriority
- .long _sys_setpriority
- .long _sys_ni_syscall /* old profil syscall holder */
- .long _sys_statfs
- .long _sys_fstatfs /* 100 */
- .long _sys_ni_syscall
- .long _sys_ni_syscall /* old sys_socketcall */
- .long _sys_syslog
- .long _sys_setitimer
- .long _sys_getitimer /* 105 */
- .long _sys_newstat
- .long _sys_newlstat
- .long _sys_newfstat
- .long _sys_ni_syscall /* old uname */
- .long _sys_ni_syscall /* iopl for i386 */ /* 110 */
- .long _sys_vhangup
- .long _sys_ni_syscall /* obsolete idle() syscall */
- .long _sys_ni_syscall /* vm86old for i386 */
- .long _sys_wait4
- .long _sys_ni_syscall /* 115 */ /* sys_swapoff */
- .long _sys_sysinfo
- .long _sys_ni_syscall /* old sys_ipc */
- .long _sys_fsync
- .long _sys_ni_syscall /* old sys_sigreturn */
- .long _bfin_clone /* 120 */
- .long _sys_setdomainname
- .long _sys_newuname
- .long _sys_ni_syscall /* old sys_modify_ldt */
- .long _sys_adjtimex
- .long _sys_mprotect /* 125 */
- .long _sys_ni_syscall /* old sys_sigprocmask */
- .long _sys_ni_syscall /* old "creat_module" */
- .long _sys_init_module
- .long _sys_delete_module
- .long _sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long _sys_quotactl
- .long _sys_getpgid
- .long _sys_fchdir
- .long _sys_bdflush
- .long _sys_ni_syscall /* 135 */ /* sys_sysfs */
- .long _sys_personality
- .long _sys_ni_syscall /* for afs_syscall */
- .long _sys_setfsuid /* setfsuid16 */
- .long _sys_setfsgid /* setfsgid16 */
- .long _sys_llseek /* 140 */
- .long _sys_getdents
- .long _sys_ni_syscall /* sys_select */
- .long _sys_flock
- .long _sys_msync
- .long _sys_readv /* 145 */
- .long _sys_writev
- .long _sys_getsid
- .long _sys_fdatasync
- .long _sys_sysctl
- .long _sys_mlock /* 150 */
- .long _sys_munlock
- .long _sys_mlockall
- .long _sys_munlockall
- .long _sys_sched_setparam
- .long _sys_sched_getparam /* 155 */
- .long _sys_sched_setscheduler
- .long _sys_sched_getscheduler
- .long _sys_sched_yield
- .long _sys_sched_get_priority_max
- .long _sys_sched_get_priority_min /* 160 */
- .long _sys_sched_rr_get_interval
- .long _sys_nanosleep
- .long _sys_mremap
- .long _sys_setresuid /* setresuid16 */
- .long _sys_getresuid /* getresuid16 */ /* 165 */
- .long _sys_ni_syscall /* for vm86 */
- .long _sys_ni_syscall /* old "query_module" */
- .long _sys_ni_syscall /* sys_poll */
- .long _sys_ni_syscall /* old nfsservctl */
- .long _sys_setresgid /* setresgid16 */ /* 170 */
- .long _sys_getresgid /* getresgid16 */
- .long _sys_prctl
- .long _sys_rt_sigreturn
- .long _sys_rt_sigaction
- .long _sys_rt_sigprocmask /* 175 */
- .long _sys_rt_sigpending
- .long _sys_rt_sigtimedwait
- .long _sys_rt_sigqueueinfo
- .long _sys_rt_sigsuspend
- .long _sys_pread64 /* 180 */
- .long _sys_pwrite64
- .long _sys_lchown /* lchown16 */
- .long _sys_getcwd
- .long _sys_capget
- .long _sys_capset /* 185 */
- .long _sys_sigaltstack
- .long _sys_sendfile
- .long _sys_ni_syscall /* streams1 */
- .long _sys_ni_syscall /* streams2 */
- .long _sys_vfork /* 190 */
- .long _sys_getrlimit
- .long _sys_mmap_pgoff
- .long _sys_truncate64
- .long _sys_ftruncate64
- .long _sys_stat64 /* 195 */
- .long _sys_lstat64
- .long _sys_fstat64
- .long _sys_chown
- .long _sys_getuid
- .long _sys_getgid /* 200 */
- .long _sys_geteuid
- .long _sys_getegid
- .long _sys_setreuid
- .long _sys_setregid
- .long _sys_getgroups /* 205 */
- .long _sys_setgroups
- .long _sys_fchown
- .long _sys_setresuid
- .long _sys_getresuid
- .long _sys_setresgid /* 210 */
- .long _sys_getresgid
- .long _sys_lchown
- .long _sys_setuid
- .long _sys_setgid
- .long _sys_setfsuid /* 215 */
- .long _sys_setfsgid
- .long _sys_pivot_root
- .long _sys_mincore
- .long _sys_madvise
- .long _sys_getdents64 /* 220 */
- .long _sys_fcntl64
- .long _sys_ni_syscall /* reserved for TUX */
- .long _sys_ni_syscall
- .long _sys_gettid
- .long _sys_readahead /* 225 */
- .long _sys_setxattr
- .long _sys_lsetxattr
- .long _sys_fsetxattr
- .long _sys_getxattr
- .long _sys_lgetxattr /* 230 */
- .long _sys_fgetxattr
- .long _sys_listxattr
- .long _sys_llistxattr
- .long _sys_flistxattr
- .long _sys_removexattr /* 235 */
- .long _sys_lremovexattr
- .long _sys_fremovexattr
- .long _sys_tkill
- .long _sys_sendfile64
- .long _sys_futex /* 240 */
- .long _sys_sched_setaffinity
- .long _sys_sched_getaffinity
- .long _sys_ni_syscall /* sys_set_thread_area */
- .long _sys_ni_syscall /* sys_get_thread_area */
- .long _sys_io_setup /* 245 */
- .long _sys_io_destroy
- .long _sys_io_getevents
- .long _sys_io_submit
- .long _sys_io_cancel
- .long _sys_ni_syscall /* 250 */ /* sys_alloc_hugepages */
- .long _sys_ni_syscall /* sys_freec_hugepages */
- .long _sys_exit_group
- .long _sys_lookup_dcookie
- .long _sys_bfin_spinlock
- .long _sys_epoll_create /* 255 */
- .long _sys_epoll_ctl
- .long _sys_epoll_wait
- .long _sys_ni_syscall /* remap_file_pages */
- .long _sys_set_tid_address
- .long _sys_timer_create /* 260 */
- .long _sys_timer_settime
- .long _sys_timer_gettime
- .long _sys_timer_getoverrun
- .long _sys_timer_delete
- .long _sys_clock_settime /* 265 */
- .long _sys_clock_gettime
- .long _sys_clock_getres
- .long _sys_clock_nanosleep
- .long _sys_statfs64
- .long _sys_fstatfs64 /* 270 */
- .long _sys_tgkill
- .long _sys_utimes
- .long _sys_fadvise64_64
- .long _sys_ni_syscall /* vserver */
- .long _sys_mbind /* 275 */
- .long _sys_ni_syscall /* get_mempolicy */
- .long _sys_ni_syscall /* set_mempolicy */
- .long _sys_mq_open
- .long _sys_mq_unlink
- .long _sys_mq_timedsend /* 280 */
- .long _sys_mq_timedreceive
- .long _sys_mq_notify
- .long _sys_mq_getsetattr
- .long _sys_ni_syscall /* kexec_load */
- .long _sys_waitid /* 285 */
- .long _sys_add_key
- .long _sys_request_key
- .long _sys_keyctl
- .long _sys_ioprio_set
- .long _sys_ioprio_get /* 290 */
- .long _sys_inotify_init
- .long _sys_inotify_add_watch
- .long _sys_inotify_rm_watch
- .long _sys_ni_syscall /* migrate_pages */
- .long _sys_openat /* 295 */
- .long _sys_mkdirat
- .long _sys_mknodat
- .long _sys_fchownat
- .long _sys_futimesat
- .long _sys_fstatat64 /* 300 */
- .long _sys_unlinkat
- .long _sys_renameat
- .long _sys_linkat
- .long _sys_symlinkat
- .long _sys_readlinkat /* 305 */
- .long _sys_fchmodat
- .long _sys_faccessat
- .long _sys_pselect6
- .long _sys_ppoll
- .long _sys_unshare /* 310 */
- .long _sys_sram_alloc
- .long _sys_sram_free
- .long _sys_dma_memcpy
- .long _sys_accept
- .long _sys_bind /* 315 */
- .long _sys_connect
- .long _sys_getpeername
- .long _sys_getsockname
- .long _sys_getsockopt
- .long _sys_listen /* 320 */
- .long _sys_recv
- .long _sys_recvfrom
- .long _sys_recvmsg
- .long _sys_send
- .long _sys_sendmsg /* 325 */
- .long _sys_sendto
- .long _sys_setsockopt
- .long _sys_shutdown
- .long _sys_socket
- .long _sys_socketpair /* 330 */
- .long _sys_semctl
- .long _sys_semget
- .long _sys_semop
- .long _sys_msgctl
- .long _sys_msgget /* 335 */
- .long _sys_msgrcv
- .long _sys_msgsnd
- .long _sys_shmat
- .long _sys_shmctl
- .long _sys_shmdt /* 340 */
- .long _sys_shmget
- .long _sys_splice
- .long _sys_sync_file_range
- .long _sys_tee
- .long _sys_vmsplice /* 345 */
- .long _sys_epoll_pwait
- .long _sys_utimensat
- .long _sys_signalfd
- .long _sys_timerfd_create
- .long _sys_eventfd /* 350 */
- .long _sys_pread64
- .long _sys_pwrite64
- .long _sys_fadvise64
- .long _sys_set_robust_list
- .long _sys_get_robust_list /* 355 */
- .long _sys_fallocate
- .long _sys_semtimedop
- .long _sys_timerfd_settime
- .long _sys_timerfd_gettime
- .long _sys_signalfd4 /* 360 */
- .long _sys_eventfd2
- .long _sys_epoll_create1
- .long _sys_dup3
- .long _sys_pipe2
- .long _sys_inotify_init1 /* 365 */
- .long _sys_preadv
- .long _sys_pwritev
- .long _sys_rt_tgsigqueueinfo
- .long _sys_perf_event_open
- .long _sys_recvmmsg /* 370 */
- .long _sys_fanotify_init
- .long _sys_fanotify_mark
- .long _sys_prlimit64
- .long _sys_cacheflush
- .long _sys_name_to_handle_at /* 375 */
- .long _sys_open_by_handle_at
- .long _sys_clock_adjtime
- .long _sys_syncfs
- .long _sys_setns
- .long _sys_sendmmsg /* 380 */
- .long _sys_process_vm_readv
- .long _sys_process_vm_writev
- .long _sys_kcmp
- .long _sys_finit_module
- .long _sys_sched_setattr /* 385 */
- .long _sys_sched_getattr
- .long _sys_renameat2
- .long _sys_seccomp
- .long _sys_getrandom
- .long _sys_memfd_create /* 390 */
- .long _sys_bpf
- .long _sys_execveat
-
- .rept NR_syscalls-(.-_sys_call_table)/4
- .long _sys_ni_syscall
- .endr
-END(_sys_call_table)
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
deleted file mode 100644
index 31515f0146f9..000000000000
--- a/arch/blackfin/mach-common/head.S
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Common Blackfin startup code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/thread_info.h>
-#include <asm/trace.h>
-#include <asm/asm-offsets.h>
-
-__INIT
-
-ENTRY(__init_clear_bss)
- r2 = r2 - r1;
- cc = r2 == 0;
- if cc jump .L_bss_done;
- r2 >>= 2;
- p1 = r1;
- p2 = r2;
- lsetup (1f, 1f) lc0 = p2;
-1: [p1++] = r0;
-.L_bss_done:
- rts;
-ENDPROC(__init_clear_bss)
-
-ENTRY(__start)
- /* R0: argument of command line string, passed from uboot, save it */
- R7 = R0;
-
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda;
- p1.h = _initial_pda;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = _init_thread_union + THREAD_SIZE;
- sp.h = _init_thread_union + THREAD_SIZE;
- fp = sp;
- usp = sp;
-
-#ifdef CONFIG_EARLY_PRINTK
- call _init_early_exception_vectors;
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#endif
-
- r0 = r6;
- /* Zero out all of the fun bss regions */
-#if L1_DATA_A_LENGTH > 0
- r1.l = __sbss_l1;
- r1.h = __sbss_l1;
- r2.l = __ebss_l1;
- r2.h = __ebss_l1;
- call __init_clear_bss
-#endif
-#if L1_DATA_B_LENGTH > 0
- r1.l = __sbss_b_l1;
- r1.h = __sbss_b_l1;
- r2.l = __ebss_b_l1;
- r2.h = __ebss_b_l1;
- call __init_clear_bss
-#endif
-#if L2_LENGTH > 0
- r1.l = __sbss_l2;
- r1.h = __sbss_l2;
- r2.l = __ebss_l2;
- r2.h = __ebss_l2;
- call __init_clear_bss
-#endif
- r1.l = ___bss_start;
- r1.h = ___bss_start;
- r2.l = ___bss_stop;
- r2.h = ___bss_stop;
- call __init_clear_bss
-
- /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
- call _bfin_relocate_l1_mem;
-
-#ifdef CONFIG_ROMKERNEL
- call _bfin_relocate_xip_data;
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
- /* Only use on-chip scratch space for stack when absolutely required
- * to avoid Anomaly 05000227 ... we know the init_clocks() func only
- * uses L1 text and stack space and no other memory region.
- */
-# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
- sp.l = lo(KERNEL_CLOCK_STACK);
- sp.h = hi(KERNEL_CLOCK_STACK);
- call _init_clocks;
- sp = usp; /* usp hasn't been touched, so restore from there */
-#endif
-
- /* This section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
-#ifdef CONFIG_EARLY_PRINTK
- r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z);
-#else
- r0 = EVT_IVG15 (z);
-#endif
- sti r0;
-
- raise 15;
-#ifdef CONFIG_EARLY_PRINTK
- p0.l = _early_trap;
- p0.h = _early_trap;
-#else
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
-#endif
- reti = p0;
-#if ANOMALY_05000281
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(__start)
-
-/* A little BF561 glue ... */
-#ifndef WDOG_CTL
-# define WDOG_CTL WDOGA_CTL
-#endif
-
-ENTRY(_real_start)
- /* Enable nested interrupts */
- [--sp] = reti;
- /* watchdog off for now */
- p0.l = lo(WDOG_CTL);
- p0.h = hi(WDOG_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0;
- ssync;
- /* Pass the u-boot arguments to the global value command line */
- R0 = R7;
- call _cmdline_init;
-
- sp += -12 + 4; /* +4 is for reti loading above */
- call _init_pda
- sp += 12;
- jump.l _start_kernel;
-ENDPROC(_real_start)
-
-__FINIT
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
deleted file mode 100644
index 469ce7282dc8..000000000000
--- a/arch/blackfin/mach-common/interrupt.S
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * Interrupt Entries
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>
- * Kenneth Albanowski <kjahds@kjahds.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <linux/linkage.h>
-#include <asm/entry.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-#include <asm/thread_info.h>
-
-#include <asm/context.S>
-
-.extern _ret_from_exception
-
-#ifdef CONFIG_I_ENTRY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 4 /* just in case */
-
-/* Common interrupt entry code. First we do CLI, then push
- * RETI, to keep interrupts disabled, but to allow this state to be changed
- * by local_bh_enable.
- * R0 contains the interrupt number, while R1 may contain the value of IPEND,
- * or garbage if IPEND won't be needed by the ISR. */
-__common_int_entry:
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r2 = RETI;
- [--sp] = r2;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
-
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r1 = 0x3f;
- sti r1;
-#else
- cli r1;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = r0;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- r0 = [sp++];
-#endif
- [--sp] = RETI; /* orig_pc */
- /* Clear all L registers. */
- r1 = 0 (x);
- l0 = r1;
- l1 = r1;
- l2 = r1;
- l3 = r1;
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- r1 = sp;
- SP += -12;
-#ifdef CONFIG_IPIPE
- call ___ipipe_grab_irq
- SP += 12;
- cc = r0 == 0;
- if cc jump .Lcommon_restore_context;
-#else /* CONFIG_IPIPE */
-
-#ifdef CONFIG_PREEMPT
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT]; /* get preempt count */
- r7 += 1; /* increment it */
- [p5 + TI_PREEMPT] = r7;
-#endif
- pseudo_long_call _do_irq, p2;
-
-#ifdef CONFIG_PREEMPT
- r7 += -1;
- [p5 + TI_PREEMPT] = r7; /* restore preempt count */
-#endif
-
- SP += 12;
-#endif /* CONFIG_IPIPE */
- pseudo_long_call _return_from_int, p2;
-.Lcommon_restore_context:
- RESTORE_CONTEXT
- rti;
-
-/* interrupt routine for ivhw - 5 */
-ENTRY(_evt_ivhw)
- /* In case a single action kicks off multiple memory transactions, (like
- * a cache line fetch, - this can cause multiple hardware errors, let's
- * catch them all. First - make sure all the actions are complete, and
- * the core sees the hardware errors.
- */
- SSYNC;
- SSYNC;
-
- SAVE_ALL_SYS
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- /* Handle all stacked hardware errors
- * To make sure we don't hang forever, only do it 10 times
- */
- R0 = 0;
- R2 = 10;
-1:
- P0.L = LO(ILAT);
- P0.H = HI(ILAT);
- R1 = [P0];
- CC = BITTST(R1, EVT_IVHW_P);
- IF ! CC JUMP 2f;
- /* OK a hardware error is pending - clear it */
- R1 = EVT_IVHW_P;
- [P0] = R1;
- R0 += 1;
- CC = R1 == R2;
- if CC JUMP 2f;
- JUMP 1b;
-2:
- # We are going to dump something out, so make sure we print IPEND properly
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* set the EXCAUSE to HWERR for trap_c */
- r0 = [sp + PT_SEQSTAT];
- R1.L = LO(VEC_HWERR);
- R1.H = HI(VEC_HWERR);
- R0 = R0 | R1;
- [sp + PT_SEQSTAT] = R0;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p5;
- SP += 12;
-
-#ifdef EBIU_ERRMST
- /* make sure EBIU_ERRMST is clear */
- p0.l = LO(EBIU_ERRMST);
- p0.h = HI(EBIU_ERRMST);
- r0.l = (CORE_ERROR | CORE_MERROR);
- w[p0] = r0.l;
-#endif
-
- pseudo_long_call _ret_from_exception, p2;
-
-.Lcommon_restore_all_sys:
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_evt_ivhw)
-
-/* Interrupt routine for evt2 (NMI).
- * For inner circle type details, please see:
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi
- */
-ENTRY(_evt_nmi)
-#ifndef CONFIG_NMI_WATCHDOG
-.weak _evt_nmi
-#else
- /* Not take account of CPLBs, this handler will not return */
- SAVE_ALL_SYS
- r0 = sp;
- r1 = retn;
- [sp + PT_PC] = r1;
- trace_buffer_save(p4,r5);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- SP += -12;
- call _do_nmi;
- SP += 12;
-1:
- jump 1b;
-#endif
- rtn;
-ENDPROC(_evt_nmi)
-
-/* interrupt routine for core timer - 6 */
-ENTRY(_evt_timer)
- TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P)
-
-/* interrupt routine for evt7 - 7 */
-ENTRY(_evt_evt7)
- INTERRUPT_ENTRY(EVT_IVG7_P)
-ENTRY(_evt_evt8)
- INTERRUPT_ENTRY(EVT_IVG8_P)
-ENTRY(_evt_evt9)
- INTERRUPT_ENTRY(EVT_IVG9_P)
-ENTRY(_evt_evt10)
- INTERRUPT_ENTRY(EVT_IVG10_P)
-ENTRY(_evt_evt11)
- INTERRUPT_ENTRY(EVT_IVG11_P)
-ENTRY(_evt_evt12)
- INTERRUPT_ENTRY(EVT_IVG12_P)
-ENTRY(_evt_evt13)
- INTERRUPT_ENTRY(EVT_IVG13_P)
-
-
- /* interrupt routine for system_call - 15 */
-ENTRY(_evt_system_call)
- SAVE_CONTEXT_SYSCALL
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
- pseudo_long_call _system_call, p2;
- jump .Lcommon_restore_context;
-ENDPROC(_evt_system_call)
-
-#ifdef CONFIG_IPIPE
-/*
- * __ipipe_call_irqtail: lowers the current priority level to EVT15
- * before running a user-defined routine, then raises the priority
- * level to EVT14 to prepare the caller for a normal interrupt
- * return through RTI.
- *
- * We currently use this feature in two occasions:
- *
- * - before branching to __ipipe_irq_tail_hook as requested by a high
- * priority domain after the pipeline delivered an interrupt,
- * e.g. such as Xenomai, in order to start its rescheduling
- * procedure, since we may not switch tasks when IRQ levels are
- * nested on the Blackfin, so we have to fake an interrupt return
- * so that we may reschedule immediately.
- *
- * - before branching to __ipipe_sync_root(), in order to play any interrupt
- * pending for the root domain (i.e. the Linux kernel). This lowers
- * the core priority level enough so that Linux IRQ handlers may
- * never delay interrupts handled by high priority domains; we defer
- * those handlers until this point instead. This is a substitute
- * to using a threaded interrupt model for the Linux kernel.
- *
- * r0: address of user-defined routine
- * context: caller must have preempted EVT15, hw interrupts must be off.
- */
-ENTRY(___ipipe_call_irqtail)
- p0 = r0;
- r0.l = 1f;
- r0.h = 1f;
- reti = r0;
- rti;
-1:
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- sp += -12;
- call (p0);
- sp += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14; /* Branches to _evt_evt14 */
-2:
- jump 2b; /* Likely paranoid. */
-ENDPROC(___ipipe_call_irqtail)
-
-#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
deleted file mode 100644
index e81a5b7dabdc..000000000000
--- a/arch/blackfin/mach-common/ints-priority.c
+++ /dev/null
@@ -1,1366 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 Bas Vermeulen <bas@buyways.nl>
- * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * 1999 D. Jeff Dionne <jeff@uclinux.org>
- * 1996 Roman Zippel
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/syscore_ops.h>
-#include <asm/delay.h>
-#ifdef CONFIG_IPIPE
-#include <linux/ipipe.h>
-#endif
-#include <asm/traps.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/dpmc.h>
-#include <asm/traps.h>
-#include <asm/gpio.h>
-
-/*
- * NOTES:
- * - we have separated the physical Hardware interrupt from the
- * levels that the LINUX kernel sees (see the description in irq.h)
- * -
- */
-
-#ifndef CONFIG_SMP
-/* Initialize this to an actual value to force it into the .data
- * section so that we know it is properly initialized at entry into
- * the kernel but before bss is initialized to zero (which is where
- * it would live otherwise). The 0x1f magic represents the IRQs we
- * cannot actually mask out in hardware.
- */
-unsigned long bfin_irq_flags = 0x1f;
-EXPORT_SYMBOL(bfin_irq_flags);
-#endif
-
-#ifdef CONFIG_PM
-unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
-unsigned vr_wakeup;
-#endif
-
-#ifndef SEC_GCTL
-static struct ivgx {
- /* irq number for request_irq, available in mach-bf5xx/irq.h */
- unsigned int irqno;
- /* corresponding bit in the SIC_ISR register */
- unsigned int isrflag;
-} ivg_table[NR_PERI_INTS];
-
-static struct ivg_slice {
- /* position of first irq in ivg_table for given ivg */
- struct ivgx *ifirst;
- struct ivgx *istop;
-} ivg7_13[IVG13 - IVG7 + 1];
-
-
-/*
- * Search SIC_IAR and fill tables with the irqvalues
- * and their positions in the SIC_ISR register.
- */
-static void __init search_IAR(void)
-{
- unsigned ivg, irq_pos = 0;
- for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
- int irqN;
-
- ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
-
- for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
- int irqn;
- u32 iar =
- bfin_read32((unsigned long *)SIC_IAR0 +
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
-#else
- (irqN >> 3)
-#endif
- );
- for (irqn = irqN; irqn < irqN + 4; ++irqn) {
- int iar_shift = (irqn & 7) * 4;
- if (ivg == (0xf & (iar >> iar_shift))) {
- ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
- ivg7_13[ivg].istop++;
- irq_pos++;
- }
- }
- }
- }
-}
-#endif
-
-/*
- * This is for core internal IRQs
- */
-void bfin_ack_noop(struct irq_data *d)
-{
- /* Dummy function. */
-}
-
-static void bfin_core_mask_irq(struct irq_data *d)
-{
- bfin_irq_flags &= ~(1 << d->irq);
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
-}
-
-static void bfin_core_unmask_irq(struct irq_data *d)
-{
- bfin_irq_flags |= 1 << d->irq;
- /*
- * If interrupts are enabled, IMASK must contain the same value
- * as bfin_irq_flags. Make sure that invariant holds. If interrupts
- * are currently disabled we need not do anything; one of the
- * callers will take care of setting IMASK to the proper value
- * when reenabling interrupts.
- * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
- * what we need.
- */
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
- return;
-}
-
-#ifndef SEC_GCTL
-void bfin_internal_mask_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
- bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 << BFIN_SYSIRQ(irq)));
-#endif /* end of SIC_IMASK0 */
- hard_local_irq_restore(flags);
-}
-
-static void bfin_internal_mask_irq_chip(struct irq_data *d)
-{
- bfin_internal_mask_irq(d->irq);
-}
-
-#ifdef CONFIG_SMP
-void bfin_internal_unmask_irq_affinity(unsigned int irq,
- const struct cpumask *affinity)
-#else
-void bfin_internal_unmask_irq(unsigned int irq)
-#endif
-{
- unsigned long flags = hard_local_irq_save();
-
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(0, affinity))
-# endif
- bfin_write_SIC_IMASK(mask_bank,
- bfin_read_SIC_IMASK(mask_bank) |
- (1 << mask_bit));
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(1, affinity))
- bfin_write_SICB_IMASK(mask_bank,
- bfin_read_SICB_IMASK(mask_bank) |
- (1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
- (1 << BFIN_SYSIRQ(irq)));
-#endif
- hard_local_irq_restore(flags);
-}
-
-#ifdef CONFIG_SMP
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq_affinity(d->irq,
- irq_data_get_affinity_mask(d));
-}
-
-static int bfin_internal_set_affinity(struct irq_data *d,
- const struct cpumask *mask, bool force)
-{
- bfin_internal_mask_irq(d->irq);
- bfin_internal_unmask_irq_affinity(d->irq, mask);
-
- return 0;
-}
-#else
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq(d->irq);
-}
-#endif
-
-#if defined(CONFIG_PM)
-int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- u32 bank, bit, wakeup = 0;
- unsigned long flags;
- bank = BFIN_SYSIRQ(irq) / 32;
- bit = BFIN_SYSIRQ(irq) % 32;
-
- switch (irq) {
-#ifdef IRQ_RTC
- case IRQ_RTC:
- wakeup |= WAKE;
- break;
-#endif
-#ifdef IRQ_CAN0_RX
- case IRQ_CAN0_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_CAN1_RX
- case IRQ_CAN1_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_USB_INT0
- case IRQ_USB_INT0:
- wakeup |= USBWE;
- break;
-#endif
-#ifdef CONFIG_BF54x
- case IRQ_CNT:
- wakeup |= ROTWE;
- break;
-#endif
- default:
- break;
- }
-
- flags = hard_local_irq_save();
-
- if (state) {
- bfin_sic_iwr[bank] |= (1 << bit);
- vr_wakeup |= wakeup;
-
- } else {
- bfin_sic_iwr[bank] &= ~(1 << bit);
- vr_wakeup &= ~wakeup;
- }
-
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
-{
- return bfin_internal_set_wake(d->irq, state);
-}
-#else
-inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- return 0;
-}
-# define bfin_internal_set_wake_chip NULL
-#endif
-
-#else /* SEC_GCTL */
-static void bfin_sec_preflow_handler(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_mask_ack_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_unmask_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write32(SEC_END, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl |= SEC_SCTL_SRC_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
- bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
- reg_sctl |= SEC_SCTL_FAULT_EN;
- else
- reg_sctl |= SEC_SCTL_INT_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_enable_sci(sid);
- bfin_sec_enable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_disable_sci(sid);
- bfin_sec_disable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl;
- int i;
-
- bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
-
- for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
- reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
- reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
- bfin_write_SEC_SCTL(i, reg_sctl);
- }
-
- hard_local_irq_restore(flags);
-}
-
-void bfin_sec_raise_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(irq);
-
- bfin_write32(SEC_RAISE, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void init_software_driven_irq(void)
-{
- bfin_sec_set_ssi_coreid(34, 0);
- bfin_sec_set_ssi_coreid(35, 1);
-
- bfin_sec_enable_sci(35);
- bfin_sec_enable_ssi(35);
- bfin_sec_set_ssi_coreid(36, 0);
- bfin_sec_set_ssi_coreid(37, 1);
- bfin_sec_enable_sci(37);
- bfin_sec_enable_ssi(37);
-}
-
-void handle_sec_sfi_fault(uint32_t gstat)
-{
-
-}
-
-void handle_sec_sci_fault(uint32_t gstat)
-{
- uint32_t core_id;
- uint32_t cstat;
-
- core_id = gstat & SEC_GSTAT_SCI;
- cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
- if (cstat & SEC_CSTAT_ERR) {
- switch (cstat & SEC_CSTAT_ERRC) {
- case SEC_CSTAT_ACKERR:
- printk(KERN_DEBUG "sec ack err\n");
- break;
- default:
- printk(KERN_DEBUG "sec sci unknown err\n");
- }
- }
-
-}
-
-void handle_sec_ssi_fault(uint32_t gstat)
-{
- uint32_t sid;
- uint32_t sstat;
-
- sid = gstat & SEC_GSTAT_SID;
- sstat = bfin_read_SEC_SSTAT(sid);
-
-}
-
-void handle_sec_fault(uint32_t sec_gstat)
-{
- if (sec_gstat & SEC_GSTAT_ERR) {
-
- switch (sec_gstat & SEC_GSTAT_ERRC) {
- case 0:
- handle_sec_sfi_fault(sec_gstat);
- break;
- case SEC_GSTAT_SCIERR:
- handle_sec_sci_fault(sec_gstat);
- break;
- case SEC_GSTAT_SSIERR:
- handle_sec_ssi_fault(sec_gstat);
- break;
- }
-
-
- }
-}
-
-static struct irqaction bfin_fault_irq = {
- .name = "Blackfin fault",
-};
-
-static irqreturn_t bfin_fault_routine(int irq, void *data)
-{
- struct pt_regs *fp = get_irq_regs();
-
- switch (irq) {
- case IRQ_C0_DBL_FAULT:
- double_fault_c(fp);
- break;
- case IRQ_C0_HW_ERR:
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
- panic("Core 0 hardware error");
- break;
- case IRQ_C0_NMI_L1_PARITY_ERR:
- panic("Core 0 NMI L1 parity error");
- break;
- case IRQ_SEC_ERR:
- pr_err("SEC error\n");
- handle_sec_fault(bfin_read32(SEC_GSTAT));
- break;
- default:
- panic("Unknown fault %d", irq);
- }
-
- return IRQ_HANDLED;
-}
-#endif /* SEC_GCTL */
-
-static struct irq_chip bfin_core_irqchip = {
- .name = "CORE",
- .irq_mask = bfin_core_mask_irq,
- .irq_unmask = bfin_core_unmask_irq,
-};
-
-#ifndef SEC_GCTL
-static struct irq_chip bfin_internal_irqchip = {
- .name = "INTN",
- .irq_mask = bfin_internal_mask_irq_chip,
- .irq_unmask = bfin_internal_unmask_irq_chip,
- .irq_disable = bfin_internal_mask_irq_chip,
- .irq_enable = bfin_internal_unmask_irq_chip,
-#ifdef CONFIG_SMP
- .irq_set_affinity = bfin_internal_set_affinity,
-#endif
- .irq_set_wake = bfin_internal_set_wake_chip,
-};
-#else
-static struct irq_chip bfin_sec_irqchip = {
- .name = "SEC",
- .irq_mask_ack = bfin_sec_mask_ack_irq,
- .irq_mask = bfin_sec_mask_ack_irq,
- .irq_unmask = bfin_sec_unmask_irq,
- .irq_eoi = bfin_sec_unmask_irq,
- .irq_disable = bfin_sec_disable,
- .irq_enable = bfin_sec_enable,
-};
-#endif
-
-void bfin_handle_irq(unsigned irq)
-{
-#ifdef CONFIG_IPIPE
- struct pt_regs regs; /* Contents not used. */
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, &regs);
- ipipe_trace_irq_exit(irq);
-#else /* !CONFIG_IPIPE */
- generic_handle_irq(irq);
-#endif /* !CONFIG_IPIPE */
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_stat_int_mask;
-
-static void bfin_mac_status_ack_irq(unsigned int irq)
-{
- switch (irq) {
- case IRQ_MAC_MMCINT:
- bfin_write_EMAC_MMC_TIRQS(
- bfin_read_EMAC_MMC_TIRQE() &
- bfin_read_EMAC_MMC_TIRQS());
- bfin_write_EMAC_MMC_RIRQS(
- bfin_read_EMAC_MMC_RIRQE() &
- bfin_read_EMAC_MMC_RIRQS());
- break;
- case IRQ_MAC_RXFSINT:
- bfin_write_EMAC_RX_STKY(
- bfin_read_EMAC_RX_IRQE() &
- bfin_read_EMAC_RX_STKY());
- break;
- case IRQ_MAC_TXFSINT:
- bfin_write_EMAC_TX_STKY(
- bfin_read_EMAC_TX_IRQE() &
- bfin_read_EMAC_TX_STKY());
- break;
- case IRQ_MAC_WAKEDET:
- bfin_write_EMAC_WKUP_CTL(
- bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
- break;
- default:
- /* These bits are W1C */
- bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
- break;
- }
-}
-
-static void bfin_mac_status_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_mask_irq(IRQ_MAC_ERROR);
-#endif
- bfin_mac_status_ack_irq(irq);
-}
-
-static void bfin_mac_status_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_unmask_irq(IRQ_MAC_ERROR);
-#endif
- mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
-}
-
-#ifdef CONFIG_PM
-int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
-{
-#ifdef BF537_FAMILY
- return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
-#else
- return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
-#endif
-}
-#else
-# define bfin_mac_status_set_wake NULL
-#endif
-
-static struct irq_chip bfin_mac_status_irqchip = {
- .name = "MACST",
- .irq_mask = bfin_mac_status_mask_irq,
- .irq_unmask = bfin_mac_status_unmask_irq,
- .irq_set_wake = bfin_mac_status_set_wake,
-};
-
-void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
-{
- int i, irq = 0;
- u32 status = bfin_read_EMAC_SYSTAT();
-
- for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
- if (status & (1L << i)) {
- irq = IRQ_MAC_PHYINT + i;
- break;
- }
-
- if (irq) {
- if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
- bfin_handle_irq(irq);
- } else {
- bfin_mac_status_ack_irq(irq);
- pr_debug("IRQ %d:"
- " MASKED MAC ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- printk(KERN_ERR
- "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
- " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
- "(EMAC_SYSTAT=0x%X)\n",
- __func__, __FILE__, __LINE__, status);
-}
-#endif
-
-static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
-{
-#ifdef CONFIG_IPIPE
- handle = handle_level_irq;
-#endif
- irq_set_handler_locked(d, handle);
-}
-
-#ifdef CONFIG_GPIO_ADI
-
-static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
-
-static void bfin_gpio_ack_irq(struct irq_data *d)
-{
- /* AFAIK ack_irq in case mask_ack is provided
- * get's only called for edge sense irqs
- */
- set_gpio_data(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_mask_ack_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- u32 gpionr = irq_to_gpio(irq);
-
- if (!irqd_is_level_type(d))
- set_gpio_data(gpionr, 0);
-
- set_gpio_maska(gpionr, 0);
-}
-
-static void bfin_gpio_mask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_unmask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 1);
-}
-
-static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- bfin_gpio_unmask_irq(d);
-
- return 0;
-}
-
-static void bfin_gpio_irq_shutdown(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- bfin_gpio_mask_irq(d);
- __clear_bit(gpionr, gpio_enabled);
- bfin_gpio_irq_free(gpionr);
-}
-
-static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
- unsigned int irq = d->irq;
- int ret;
- char buf[16];
- u32 gpionr = irq_to_gpio(irq);
-
- if (type == IRQ_TYPE_PROBE) {
- /* only probe unenabled GPIO interrupt lines */
- if (test_bit(gpionr, gpio_enabled))
- return 0;
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
- IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-
- snprintf(buf, 16, "gpio-irq%d", irq);
- ret = bfin_gpio_irq_request(gpionr, buf);
- if (ret)
- return ret;
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- } else {
- __clear_bit(gpionr, gpio_enabled);
- return 0;
- }
-
- set_gpio_inen(gpionr, 0);
- set_gpio_dir(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_gpio_both(gpionr, 1);
- else
- set_gpio_both(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
- set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
- else
- set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- set_gpio_edge(gpionr, 1);
- set_gpio_inen(gpionr, 1);
- set_gpio_data(gpionr, 0);
-
- } else {
- set_gpio_edge(gpionr, 0);
- set_gpio_inen(gpionr, 1);
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- bfin_set_irq_handler(d, handle_edge_irq);
- else
- bfin_set_irq_handler(d, handle_level_irq);
-
- return 0;
-}
-
-static void bfin_demux_gpio_block(unsigned int irq)
-{
- unsigned int gpio, mask;
-
- gpio = irq_to_gpio(irq);
- mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
- while (mask) {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- }
-}
-
-void bfin_demux_gpio_irq(struct irq_desc *desc)
-{
- unsigned int inta_irq = irq_desc_get_irq(desc);
- unsigned int irq;
-
- switch (inta_irq) {
-#if defined(BF537_FAMILY)
- case IRQ_PF_INTA_PG_INTA:
- bfin_demux_gpio_block(IRQ_PF0);
- irq = IRQ_PG0;
- break;
- case IRQ_PH_INTA_MAC_RX:
- irq = IRQ_PH0;
- break;
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PORTG_INTA:
- irq = IRQ_PG0;
- break;
- case IRQ_PORTH_INTA:
- irq = IRQ_PH0;
- break;
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PROG1_INTA:
- irq = IRQ_PF16;
- break;
- case IRQ_PROG2_INTA:
- irq = IRQ_PF32;
- break;
-#endif
- default:
- BUG();
- return;
- }
-
- bfin_demux_gpio_block(irq);
-}
-
-#ifdef CONFIG_PM
-
-static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
-{
- return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
-}
-
-#else
-
-# define bfin_gpio_set_wake NULL
-
-#endif
-
-static struct irq_chip bfin_gpio_irqchip = {
- .name = "GPIO",
- .irq_ack = bfin_gpio_ack_irq,
- .irq_mask = bfin_gpio_mask_irq,
- .irq_mask_ack = bfin_gpio_mask_ack_irq,
- .irq_unmask = bfin_gpio_unmask_irq,
- .irq_disable = bfin_gpio_mask_irq,
- .irq_enable = bfin_gpio_unmask_irq,
- .irq_set_type = bfin_gpio_irq_type,
- .irq_startup = bfin_gpio_irq_startup,
- .irq_shutdown = bfin_gpio_irq_shutdown,
- .irq_set_wake = bfin_gpio_set_wake,
-};
-
-#endif
-
-#ifdef CONFIG_PM
-
-#ifdef SEC_GCTL
-static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
-
-static int sec_suspend(void)
-{
- u32 bank;
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
- return 0;
-}
-
-static void sec_resume(void)
-{
- u32 bank;
-
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
-}
-
-static struct syscore_ops sec_pm_syscore_ops = {
- .suspend = sec_suspend,
- .resume = sec_resume,
-};
-#endif
-
-#endif
-
-void init_exception_vectors(void)
-{
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- bfin_write_EVT2(evt_nmi);
- bfin_write_EVT3(trap);
- bfin_write_EVT5(evt_ivhw);
- bfin_write_EVT6(evt_timer);
- bfin_write_EVT7(evt_evt7);
- bfin_write_EVT8(evt_evt8);
- bfin_write_EVT9(evt_evt9);
- bfin_write_EVT10(evt_evt10);
- bfin_write_EVT11(evt_evt11);
- bfin_write_EVT12(evt_evt12);
- bfin_write_EVT13(evt_evt13);
- bfin_write_EVT14(evt_evt14);
- bfin_write_EVT15(evt_system_call);
- CSYNC();
-}
-
-#ifndef SEC_GCTL
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#ifdef SIC_IMASK0
- bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef SIC_IMASK2
- bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
-# endif
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
-# endif
-#else
- bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
-#endif
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR)
- irq_set_chip(irq, &bfin_core_irqchip);
- else
- irq_set_chip(irq, &bfin_internal_irqchip);
-
- switch (irq) {
-#if !BFIN_GPIO_PINT
-#if defined(BF537_FAMILY)
- case IRQ_PH_INTA_MAC_RX:
- case IRQ_PF_INTA_PG_INTA:
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- case IRQ_PORTG_INTA:
- case IRQ_PORTH_INTA:
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- case IRQ_PROG1_INTA:
- case IRQ_PROG2_INTA:
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
-#endif
- irq_set_chained_handler(irq, bfin_demux_gpio_irq);
- break;
-#endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- case IRQ_MAC_ERROR:
- irq_set_chained_handler(irq,
- bfin_demux_mac_status_irq);
- break;
-#endif
-#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- case IRQ_SUPPLE_0:
- case IRQ_SUPPLE_1:
- irq_set_handler(irq, handle_percpu_irq);
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
- case IRQ_CORETMR:
-# ifdef CONFIG_SMP
- irq_set_handler(irq, handle_percpu_irq);
-# else
- irq_set_handler(irq, handle_simple_irq);
-# endif
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_GPTMR0
- case IRQ_TIMER0:
- irq_set_handler(irq, handle_simple_irq);
- break;
-#endif
-
- default:
-#ifdef CONFIG_IPIPE
- irq_set_handler(irq, handle_level_irq);
-#else
- irq_set_handler(irq, handle_simple_irq);
-#endif
- break;
- }
- }
-
- init_mach_irq();
-
-#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
- irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
- handle_level_irq);
-#endif
- /* if configured as edge, then will be changed to do_edge_IRQ */
-#ifdef CONFIG_GPIO_ADI
- for (irq = GPIO_IRQ_BASE;
- irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
- irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
- handle_level_irq);
-#endif
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
- /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
- * local_irq_enable()
- */
- program_IAR();
- /* Therefore it's better to setup IARs before interrupts enabled */
- search_IAR();
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- /* This implicitly covers ANOMALY_05000171
- * Boot-ROM code modifies SICA_IWRx wakeup registers
- */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
- unsigned long sic_status[3];
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-#ifdef SIC_ISR
- sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-#else
- if (smp_processor_id()) {
-# ifdef SICB_ISR0
- /* This will be optimized out in UP mode. */
- sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
- sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
- } else {
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
- }
-#endif
-#ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-#endif
-
- for (;; ivg++) {
- if (ivg >= ivg_stop)
- return -1;
-#ifdef SIC_ISR
- if (sic_status[0] & ivg->isrflag)
-#else
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
-#endif
- return ivg->irqno;
- }
-}
-
-#else /* SEC_GCTL */
-
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- bfin_write_SEC_GCTL(SEC_GCTL_RESET);
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR) {
- irq_set_chip_and_handler(irq, &bfin_core_irqchip,
- handle_simple_irq);
-#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
- if (irq == IRQ_CORETMR)
- irq_set_handler(irq, handle_percpu_irq);
-#endif
- } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
- irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
- handle_percpu_irq);
- } else {
- irq_set_chip(irq, &bfin_sec_irqchip);
- irq_set_handler(irq, handle_fasteoi_irq);
- __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
- }
- }
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
-
- bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
- bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
- bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- init_software_driven_irq();
-
-#ifdef CONFIG_PM
- register_syscore_ops(&sec_pm_syscore_ops);
-#endif
-
- bfin_fault_irq.handler = bfin_fault_routine;
-#ifdef CONFIG_L1_PARITY_CHECK
- setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
-#endif
- setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
- setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
-
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-
- return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
-}
-#endif /* SEC_GCTL */
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-void do_irq(int vec, struct pt_regs *fp)
-{
- int irq = vec_to_irq(vec);
- if (irq == -1)
- return;
- asm_do_IRQ(irq, fp);
-}
-
-#ifdef CONFIG_IPIPE
-
-int __ipipe_get_irq_priority(unsigned irq)
-{
- int ient, prio;
-
- if (irq <= IRQ_CORETMR)
- return irq;
-
-#ifdef SEC_GCTL
- if (irq >= BFIN_IRQ(0))
- return IVG11;
-#else
- for (ient = 0; ient < NR_PERI_INTS; ient++) {
- struct ivgx *ivg = ivg_table + ient;
- if (ivg->irqno == irq) {
- for (prio = 0; prio <= IVG13-IVG7; prio++) {
- if (ivg7_13[prio].ifirst <= ivg &&
- ivg7_13[prio].istop > ivg)
- return IVG7 + prio;
- }
- }
- }
-#endif
-
- return IVG15;
-}
-
-/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain = __ipipe_current_domain;
- int irq, s = 0;
-
- irq = vec_to_irq(vec);
- if (irq == -1)
- return 0;
-
- if (irq == IRQ_SYSTMR) {
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
-#endif
- /* This is basically what we need from the register frame. */
- __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
- __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
- if (this_domain != ipipe_root_domain)
- __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
- else
- __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
- }
-
- /*
- * We don't want Linux interrupt handlers to run at the
- * current core priority level (i.e. < EVT15), since this
- * might delay other interrupts handled by a high priority
- * domain. Here is what we do instead:
- *
- * - we raise the SYNCDEFER bit to prevent
- * __ipipe_handle_irq() to sync the pipeline for the root
- * stage for the incoming interrupt. Upon return, that IRQ is
- * pending in the interrupt log.
- *
- * - we raise the TIF_IRQ_SYNC bit for the current thread, so
- * that _schedule_and_signal_from_int will eventually sync the
- * pipeline from EVT15.
- */
- if (this_domain == ipipe_root_domain) {
- s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- barrier();
- }
-
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, regs);
- ipipe_trace_irq_exit(irq);
-
- if (user_mode(regs) &&
- !ipipe_test_foreign_stack() &&
- (current->ipipe_flags & PF_EVTRET) != 0) {
- /*
- * Testing for user_regs() does NOT fully eliminate
- * foreign stack contexts, because of the forged
- * interrupt returns we do through
- * __ipipe_call_irqtail. In that case, we might have
- * preempted a foreign stack context in a high
- * priority domain, with a single interrupt level now
- * pending after the irqtail unwinding is done. In
- * which case user_mode() is now true, and the event
- * gets dispatched spuriously.
- */
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (this_domain == ipipe_root_domain) {
- set_thread_flag(TIF_IRQ_SYNC);
- if (!s) {
- __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- return !test_bit(IPIPE_STALL_FLAG, &p->status);
- }
- }
-
- return 0;
-}
-
-#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
deleted file mode 100644
index f57b5fe5355e..000000000000
--- a/arch/blackfin/mach-common/pm.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Blackfin power management
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- * based on arm/mach-omap/pm.c
- * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
- */
-
-#include <linux/suspend.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-
-#include <asm/cplb.h>
-#include <asm/dma.h>
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <asm/gpio.h>
-
-#ifdef CONFIG_BF60x
-struct bfin_cpu_pm_fns *bfin_cpu_pm;
-#endif
-
-void bfin_pm_suspend_standby_enter(void)
-{
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_setup();
-#endif
-
-#ifdef CONFIG_BF60x
- bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
-#else
-# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
- sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# else
- sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# endif
-#endif
-
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_restore();
-#endif
-
-#ifndef CONFIG_BF60x
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
-
-#endif
-}
-
-int bf53x_suspend_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
- L1_CODE_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
- (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
- (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
- memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
- L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
- L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-int bf53x_resume_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
- L1_DATA_A_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
- memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# ifdef CONFIG_BF60x
-__attribute__((l1_text))
-# endif
-static void flushinv_all_dcache(void)
-{
- register u32 way, bank, subbank, set;
- register u32 status, addr;
- u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
- for (bank = 0; bank < 2; ++bank) {
- if (!(dmem_ctl & (1 << (DMC1_P - bank))))
- continue;
-
- for (way = 0; way < 2; ++way)
- for (subbank = 0; subbank < 4; ++subbank)
- for (set = 0; set < 64; ++set) {
-
- bfin_write_DTEST_COMMAND(
- way << 26 |
- bank << 23 |
- subbank << 16 |
- set << 5
- );
- CSYNC();
- status = bfin_read_DTEST_DATA0();
-
- /* only worry about valid/dirty entries */
- if ((status & 0x3) != 0x3)
- continue;
-
-
- /* construct the address using the tag */
- addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
- /* flush it */
- __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
- }
- }
-}
-#endif
-
-int bfin_pm_suspend_mem_enter(void)
-{
- int ret;
-#ifndef CONFIG_BF60x
- int wakeup;
-#endif
-
- unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
- + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
- GFP_ATOMIC);
-
- if (memptr == NULL) {
- panic("bf53x_suspend_l1_mem malloc failed");
- return -ENOMEM;
- }
-
-#ifndef CONFIG_BF60x
- wakeup = bfin_read_VR_CTL() & ~FREQ;
- wakeup |= SCKELOW;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PH6
- wakeup |= PHYWE;
-#endif
-#ifdef CONFIG_PM_BFIN_WAKE_GP
- wakeup |= GPWE;
-#endif
-#endif
-
- ret = blackfin_dma_suspend();
-
- if (ret) {
- kfree(memptr);
- return ret;
- }
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_suspend();
-#endif
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
- flushinv_all_dcache();
- udelay(1);
-#endif
- _disable_dcplb();
- _disable_icplb();
- bf53x_suspend_l1_mem(memptr);
-
-#ifndef CONFIG_BF60x
- do_hibernate(wakeup | vr_wakeup); /* See you later! */
-#else
- bfin_cpu_pm->enter(PM_SUSPEND_MEM);
-#endif
-
- bf53x_resume_l1_mem(memptr);
-
- _enable_icplb();
- _enable_dcplb();
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_restore();
-#endif
- blackfin_dma_resume();
-
- kfree(memptr);
-
- return 0;
-}
-
-/*
- * bfin_pm_valid - Tell the PM core that we only support the standby sleep
- * state
- * @state: suspend state we're checking.
- *
- */
-static int bfin_pm_valid(suspend_state_t state)
-{
- return (state == PM_SUSPEND_STANDBY
-#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
- /*
- * On BF533/2/1:
- * If we enter Hibernate the SCKE Pin is driven Low,
- * so that the SDRAM enters Self Refresh Mode.
- * However when the reset sequence that follows hibernate
- * state is executed, SCKE is driven High, taking the
- * SDRAM out of Self Refresh.
- *
- * If you reconfigure and access the SDRAM "very quickly",
- * you are likely to avoid errors, otherwise the SDRAM
- * start losing its contents.
- * An external HW workaround is possible using logic gates.
- */
- || state == PM_SUSPEND_MEM
-#endif
- );
-}
-
-/*
- * bfin_pm_enter - Actually enter a sleep state.
- * @state: State we're entering.
- *
- */
-static int bfin_pm_enter(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_STANDBY:
- bfin_pm_suspend_standby_enter();
- break;
- case PM_SUSPEND_MEM:
- bfin_pm_suspend_mem_enter();
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
-void bfin_pm_end(void)
-{
- u32 cycle, cycle2;
- u64 usec64;
- u32 usec;
-
- __asm__ __volatile__ (
- "1: %0 = CYCLES2\n"
- "%1 = CYCLES\n"
- "%2 = CYCLES2\n"
- "CC = %2 == %0\n"
- "if ! CC jump 1b\n"
- : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
- );
-
- usec64 = ((u64)cycle2 << 32) + cycle;
- do_div(usec64, get_cclk() / USEC_PER_SEC);
- usec = usec64;
- if (usec == 0)
- usec = 1;
-
- pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
- usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
-}
-#endif
-
-static const struct platform_suspend_ops bfin_pm_ops = {
- .enter = bfin_pm_enter,
- .valid = bfin_pm_valid,
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- .end = bfin_pm_end,
-#endif
-};
-
-static int __init bfin_pm_init(void)
-{
- suspend_set_ops(&bfin_pm_ops);
- return 0;
-}
-
-__initcall(bfin_pm_init);
diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c
deleted file mode 100644
index 8923398db66f..000000000000
--- a/arch/blackfin/mach-common/scb-init.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <asm/scb.h>
-
-__attribute__((l1_text))
-inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i)
- bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
-}
-
-__attribute__((l1_text))
-inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i) {
- bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
- scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
- }
-}
-
-__attribute__((l1_text))
-void init_scb(void)
-{
- unsigned int i, j;
- unsigned char scb_tmp_prio[32];
-
- pr_info("Init System Crossbar\n");
- for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
-
- scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
-
- pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
- scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
- for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
- pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
- }
-
-}
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
deleted file mode 100644
index b32ddab7966c..000000000000
--- a/arch/blackfin/mach-common/smp.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task_stack.h>
-#include <linux/interrupt.h>
-#include <linux/cache.h>
-#include <linux/clockchips.h>
-#include <linux/profile.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/irq_handler.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/cpu.h>
-#include <asm/time.h>
-#include <linux/err.h>
-
-/*
- * Anomaly notes:
- * 05000120 - we always define corelock as 32-bit integer in L2
- */
-struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct blackfin_initial_pda initial_pda_coreb;
-
-enum ipi_message_type {
- BFIN_IPI_NONE,
- BFIN_IPI_TIMER,
- BFIN_IPI_RESCHEDULE,
- BFIN_IPI_CALL_FUNC,
- BFIN_IPI_CPU_STOP,
-};
-
-struct blackfin_flush_data {
- unsigned long start;
- unsigned long end;
-};
-
-void *secondary_stack;
-
-static struct blackfin_flush_data smp_flush_data;
-
-static DEFINE_SPINLOCK(stop_lock);
-
-/* A magic number - stress test shows this is safe for common cases */
-#define BFIN_IPI_MSGQ_LEN 5
-
-/* Simple FIFO buffer, overflow leads to panic */
-struct ipi_data {
- atomic_t count;
- atomic_t bits;
-};
-
-static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
-
-static void ipi_cpu_stop(unsigned int cpu)
-{
- spin_lock(&stop_lock);
- printk(KERN_CRIT "CPU%u: stopping\n", cpu);
- dump_stack();
- spin_unlock(&stop_lock);
-
- set_cpu_online(cpu, false);
-
- local_irq_disable();
-
- while (1)
- SSYNC();
-}
-
-static void ipi_flush_icache(void *info)
-{
- struct blackfin_flush_data *fdata = info;
-
- /* Invalidate the memory holding the bounds of the flushed region. */
- blackfin_dcache_invalidate_range((unsigned long)fdata,
- (unsigned long)fdata + sizeof(*fdata));
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-
- /* ipi_flaush_icache is invoked by generic flush_icache_range,
- * so call blackfin arch icache flush directly here.
- */
- blackfin_icache_flush_range(fdata->start, fdata->end);
-}
-
-/* Use IRQ_SUPPLE_0 to request reschedule.
- * When returning from interrupt to user space,
- * there is chance to reschedule */
-static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
-{
- unsigned int cpu = smp_processor_id();
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- return IRQ_HANDLED;
-}
-
-DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
-void ipi_timer(void)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
- evt->event_handler(evt);
-}
-
-static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
-{
- struct ipi_data *bfin_ipi_data;
- unsigned int cpu = smp_processor_id();
- unsigned long pending;
- unsigned long msg;
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_1);
-
- smp_rmb();
- bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
- while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
- msg = 0;
- do {
- msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
- switch (msg) {
- case BFIN_IPI_TIMER:
- ipi_timer();
- break;
- case BFIN_IPI_RESCHEDULE:
- scheduler_ipi();
- break;
- case BFIN_IPI_CALL_FUNC:
- generic_smp_call_function_interrupt();
- break;
- case BFIN_IPI_CPU_STOP:
- ipi_cpu_stop(cpu);
- break;
- default:
- goto out;
- }
- atomic_dec(&bfin_ipi_data->count);
- } while (msg < BITS_PER_LONG);
-
- }
-out:
- return IRQ_HANDLED;
-}
-
-static void bfin_ipi_init(void)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- for_each_possible_cpu(cpu) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_set(&bfin_ipi_data->bits, 0);
- atomic_set(&bfin_ipi_data->count, 0);
- }
-}
-
-void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- unsigned long flags;
-
- local_irq_save(flags);
- for_each_cpu(cpu, cpumask) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_or((1 << msg), &bfin_ipi_data->bits);
- atomic_inc(&bfin_ipi_data->count);
- }
- local_irq_restore(flags);
- smp_wmb();
- for_each_cpu(cpu, cpumask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- send_ipi(mask, BFIN_IPI_CALL_FUNC);
-}
-
-void smp_send_reschedule(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
-
- return;
-}
-
-void smp_send_msg(const struct cpumask *mask, unsigned long type)
-{
- send_ipi(mask, type);
-}
-
-void smp_timer_broadcast(const struct cpumask *mask)
-{
- smp_send_msg(mask, BFIN_IPI_TIMER);
-}
-
-void smp_send_stop(void)
-{
- cpumask_t callmap;
-
- preempt_disable();
- cpumask_copy(&callmap, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &callmap);
- if (!cpumask_empty(&callmap))
- send_ipi(&callmap, BFIN_IPI_CPU_STOP);
-
- preempt_enable();
-
- return;
-}
-
-int __cpu_up(unsigned int cpu, struct task_struct *idle)
-{
- int ret;
-
- secondary_stack = task_stack_page(idle) + THREAD_SIZE;
-
- ret = platform_boot_secondary(cpu, idle);
-
- secondary_stack = NULL;
-
- return ret;
-}
-
-static void setup_secondary(unsigned int cpu)
-{
- unsigned long ilat;
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- /* Enable interrupt levels IVG7-15. IARs have been already
- * programmed by the boot CPU. */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-}
-
-void secondary_start_kernel(void)
-{
- unsigned int cpu = smp_processor_id();
- struct mm_struct *mm = &init_mm;
-
- if (_bfin_swrst & SWRST_DBL_FAULT_B) {
- printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda_coreb.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda_coreb.retx);
- }
-
- /*
- * We want the D-cache to be enabled early, in case the atomic
- * support code emulates cache coherence (see
- * __ARCH_SYNC_CORE_DCACHE).
- */
- init_exception_vectors();
-
- local_irq_disable();
-
- /* Attach the new idle task to the global mm. */
- mmget(mm);
- mmgrab(mm);
- current->active_mm = mm;
-
- preempt_disable();
-
- setup_secondary(cpu);
-
- platform_secondary_init(cpu);
- /* setup local core timer */
- bfin_local_timer_setup();
-
- local_irq_enable();
-
- bfin_setup_caches(cpu);
-
- notify_cpu_starting(cpu);
- /*
- * Calibrate loops per jiffy value.
- * IRQs need to be enabled here - D-cache can be invalidated
- * in timer irq handler, so core B can read correct jiffies.
- */
- calibrate_delay();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- set_cpu_online(cpu, true);
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
-}
-
-void __init smp_prepare_boot_cpu(void)
-{
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- platform_prepare_cpus(max_cpus);
- bfin_ipi_init();
- platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
- platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- unsigned long bogosum = 0;
- unsigned int cpu;
-
- for_each_online_cpu(cpu)
- bogosum += loops_per_jiffy;
-
- printk(KERN_INFO "SMP: Total of %d processors activated "
- "(%lu.%02lu BogoMIPS).\n",
- num_online_cpus(),
- bogosum / (500000/HZ),
- (bogosum / (5000/HZ)) % 100);
-}
-
-void smp_icache_flush_range_others(unsigned long start, unsigned long end)
-{
- smp_flush_data.start = start;
- smp_flush_data.end = end;
-
- preempt_disable();
- if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
- printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
- preempt_enable();
-}
-EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-unsigned long icache_invld_count[NR_CPUS];
-void resync_core_icache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_icache();
- icache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_icache);
-#endif
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-unsigned long dcache_invld_count[NR_CPUS];
-unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
-
-void resync_core_dcache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_dcache();
- dcache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_dcache);
-#endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-int __cpu_disable(void)
-{
- unsigned int cpu = smp_processor_id();
-
- if (cpu == 0)
- return -EPERM;
-
- set_cpu_online(cpu, false);
- return 0;
-}
-
-int __cpu_die(unsigned int cpu)
-{
- return cpu_wait_death(cpu, 5);
-}
-
-void cpu_die(void)
-{
- (void)cpu_report_death();
-
- atomic_dec(&init_mm.mm_users);
- atomic_dec(&init_mm.mm_count);
-
- local_irq_disable();
- platform_cpu_die();
-}
-#endif
diff --git a/arch/blackfin/mm/Makefile b/arch/blackfin/mm/Makefile
deleted file mode 100644
index 4c011b1f661f..000000000000
--- a/arch/blackfin/mm/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mm/Makefile
-#
-
-obj-y := sram-alloc.o isram-driver.o init.o maccess.o
diff --git a/arch/blackfin/mm/blackfin_sram.h b/arch/blackfin/mm/blackfin_sram.h
deleted file mode 100644
index fb0b1599cfb7..000000000000
--- a/arch/blackfin/mm/blackfin_sram.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Local prototypes meant for internal use only
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_SRAM_H__
-#define __BLACKFIN_SRAM_H__
-
-extern void *l1sram_alloc(size_t);
-
-#endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
deleted file mode 100644
index b59cd7c3261a..000000000000
--- a/arch/blackfin/mm/init.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/gfp.h>
-#include <linux/swap.h>
-#include <linux/bootmem.h>
-#include <linux/uaccess.h>
-#include <linux/export.h>
-#include <asm/bfin-global.h>
-#include <asm/pda.h>
-#include <asm/cplbinit.h>
-#include <asm/early_printk.h>
-#include "blackfin_sram.h"
-
-/*
- * ZERO_PAGE is a special page that is used for zero-initialized data and COW.
- * Let the bss do its zero-init magic so we don't have to do it ourselves.
- */
-char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-EXPORT_SYMBOL(empty_zero_page);
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
-#if defined CONFIG_SYSCALL_TAB_L1
-__attribute__((l1_data))
-#endif
-static unsigned long exception_stack[NR_CPUS][1024];
-#endif
-
-struct blackfin_pda cpu_pda[NR_CPUS];
-EXPORT_SYMBOL(cpu_pda);
-
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/head.S.
- * The parameters are pointers to where to stick the starting and ending
- * addresses of available kernel virtual memory.
- */
-void __init paging_init(void)
-{
- /*
- * make sure start_mem is page aligned, otherwise bootmem and
- * page_alloc get different views of the world
- */
- unsigned long end_mem = memory_end & PAGE_MASK;
-
- unsigned long zones_size[MAX_NR_ZONES] = {
- [0] = 0,
- [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
- [ZONE_NORMAL] = 0,
-#ifdef CONFIG_HIGHMEM
- [ZONE_HIGHMEM] = 0,
-#endif
- };
-
- /* Set up SFC/DFC registers (user data space) */
- set_fs(KERNEL_DS);
-
- pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
- PAGE_ALIGN(memory_start), end_mem);
- free_area_init_node(0, zones_size,
- CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
-}
-
-asmlinkage void __init init_pda(void)
-{
- unsigned int cpu = raw_smp_processor_id();
-
- early_shadow_stamp();
-
- /* Initialize the PDA fields holding references to other parts
- of the memory. The content of such memory is still
- undefined at the time of the call, we are only setting up
- valid pointers to it. */
- memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
-
-#ifdef CONFIG_EXCEPTION_L1_SCRATCH
- cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
- L1_SCRATCH_LENGTH);
-#else
- cpu_pda[cpu].ex_stack = exception_stack[cpu + 1];
-#endif
-
-#ifdef CONFIG_SMP
- cpu_pda[cpu].imask = 0x1f;
-#endif
-}
-
-void __init mem_init(void)
-{
- char buf[64];
-
- high_memory = (void *)(memory_end & PAGE_MASK);
- max_mapnr = MAP_NR(high_memory);
- printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr);
-
- /* This will put all low memory onto the freelists. */
- free_all_bootmem();
-
- snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10);
- mem_init_print_info(buf);
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_MPU
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-#endif
-}
-#endif
-
-void __ref free_initmem(void)
-{
-#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
- free_initmem_default(-1);
- if (memory_start == (unsigned long)(&__init_end))
- memory_start = (unsigned long)(&__init_begin);
-#endif
-}
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c
deleted file mode 100644
index aaa1e64b753b..000000000000
--- a/arch/blackfin/mm/isram-driver.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Instruction SRAM accessor functions for the Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#define pr_fmt(fmt) "isram: " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-/*
- * IMPORTANT WARNING ABOUT THESE FUNCTIONS
- *
- * The emulator will not function correctly if a write command is left in
- * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
- * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
- * and DTEST_COMMAND are zero when exiting these functions.
- */
-
-
-/*
- * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
- * be accessed by a normal core load, so we need to go through a few hoops to
- * read/write it.
- * To try to make it easier - we export a memcpy interface, where either src or
- * dest can be in this special L1 memory area.
- * The low level read/write functions should not be exposed to the rest of the
- * kernel, since they operate on 64-bit data, and need specific address alignment
- */
-
-static DEFINE_SPINLOCK(dtest_lock);
-
-/* Takes a void pointer */
-#define IADDR2DTEST(x) \
- ({ unsigned long __addr = (unsigned long)(x); \
- ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
- (1 << 24) | /* instruction access = 1 */ \
- ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
- ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
- (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
- (1 << 2); /* data array = 1 */ \
- })
-
-/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
-#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
-
-/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
-#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
-
-static void isram_write(const void *addr, uint64_t data)
-{
- uint32_t cmd;
- unsigned long flags;
-
- if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return;
-
- cmd = IADDR2DTEST(addr) | 2; /* write */
-
- /*
- * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
-
- bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
- bfin_write_DTEST_DATA1(data >> 32);
-
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
-
- spin_unlock_irqrestore(&dtest_lock, flags);
-}
-
-static uint64_t isram_read(const void *addr)
-{
- uint32_t cmd;
- unsigned long flags;
- uint64_t ret;
-
- if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return 0;
-
- cmd = IADDR2DTEST(addr) | 0; /* read */
-
- /*
- * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
- ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
- spin_unlock_irqrestore(&dtest_lock, flags);
-
- return ret;
-}
-
-static bool isram_check_addr(const void *addr, size_t n)
-{
- if ((addr >= (void *)L1_CODE_START) &&
- (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- show_stack(NULL, NULL);
- pr_err("copy involving %p length (%zu) too long\n", addr, n);
- }
- return true;
- }
- return false;
-}
-
-/*
- * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
- * The isram_memcpy() function returns a pointer to dest.
- * Either dest or src can be in L1 instruction sram.
- */
-void *isram_memcpy(void *dest, const void *src, size_t n)
-{
- uint64_t data_in = 0, data_out = 0;
- size_t count;
- bool dest_in_l1, src_in_l1, need_data, put_data;
- unsigned char byte, *src_byte, *dest_byte;
-
- src_byte = (unsigned char *)src;
- dest_byte = (unsigned char *)dest;
-
- dest_in_l1 = isram_check_addr(dest, n);
- src_in_l1 = isram_check_addr(src, n);
-
- need_data = true;
- put_data = true;
- for (count = 0; count < n; count++) {
- if (src_in_l1) {
- if (need_data) {
- data_in = isram_read(src + count);
- need_data = false;
- }
-
- if (ADDR2LAST(src + count))
- need_data = true;
-
- byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
-
- } else {
- /* src is in L2 or L3 - so just dereference*/
- byte = src_byte[count];
- }
-
- if (dest_in_l1) {
- if (put_data) {
- data_out = isram_read(dest + count);
- put_data = false;
- }
-
- data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
- data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
-
- if (ADDR2LAST(dest + count)) {
- put_data = true;
- isram_write(dest + count, data_out);
- }
- } else {
- /* dest in L2 or L3 - so just dereference */
- dest_byte[count] = byte;
- }
- }
-
- /* make sure we dump the last byte if necessary */
- if (dest_in_l1 && !put_data)
- isram_write(dest + count, data_out);
-
- return dest;
-}
-EXPORT_SYMBOL(isram_memcpy);
-
-#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
-
-static int test_len = 0x20000;
-
-static __init void hex_dump(unsigned char *buf, int len)
-{
- while (len--)
- pr_cont("%02x", *buf++);
-}
-
-static __init int isram_read_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_read tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- /* make sure we can read the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- data1 = isram_read(l1inst + i);
- memcpy(&data2, sdram + i, sizeof(data2));
- if (data1 != data2) {
- pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- return ret;
-}
-
-static __init int isram_write_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_write tests\n");
-
- /* setup some different data to play with */
- memset(sdram, 0, test_len * 2);
- dma_memcpy(l1inst, sdram, test_len);
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
-
- /* make sure we can write the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- memcpy(&data1, sdram + i, sizeof(data1));
- isram_write(l1inst + i, data1);
- data2 = isram_read(l1inst + i);
- if (data1 != data2) {
- pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- dma_memcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: isram_write() did not work properly\n");
- ++ret;
- }
-
- return ret;
-}
-
-static __init int
-_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
- void *(*fmemcpy)(void *, const void *, size_t))
-{
- memset(sdram, pattern, test_len);
- fmemcpy(l1inst, sdram, test_len);
- fmemcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
- smemcpy, l1inst, sdram, test_len, pattern);
- return 1;
- }
- return 0;
-}
-#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
-
-static __init int isram_memcpy_test(char *sdram, void *l1inst)
-{
- int i, j, thisret, ret = 0;
-
- /* check broad isram_memcpy() */
- pr_info("INFO: running broad isram_memcpy tests\n");
- for (i = 0xf; i >= 0; --i)
- ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
-
- /* check read of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (read) tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- memset(cmp, 0, sizeof(cmp));
- isram_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + 1);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- /* check write of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (write) tests\n");
-
- memset(sdram + test_len, 0, test_len);
- dma_memcpy(l1inst, sdram + test_len, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- isram_memcpy(l1inst + i, sdram + i, j);
- dma_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + i);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- return ret;
-}
-
-static __init int isram_test_init(void)
-{
- int ret;
- char *sdram;
- void *l1inst;
-
- /* Try to test as much of L1SRAM as possible */
- while (test_len) {
- test_len >>= 1;
- l1inst = l1_inst_sram_alloc(test_len);
- if (l1inst)
- break;
- }
- if (!l1inst) {
- pr_warning("SKIP: could not allocate L1 inst\n");
- return 0;
- }
- pr_info("INFO: testing %#x bytes (%p - %p)\n",
- test_len, l1inst, l1inst + test_len);
-
- sdram = kmalloc(test_len * 2, GFP_KERNEL);
- if (!sdram) {
- sram_free(l1inst);
- pr_warning("SKIP: could not allocate sdram\n");
- return 0;
- }
-
- /* sanity check initial L1 inst state */
- ret = 1;
- pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
- if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
- goto abort;
- if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
- goto abort;
-
- ret = 0;
- ret += isram_read_test(sdram, l1inst);
- ret += isram_write_test(sdram, l1inst);
- ret += isram_memcpy_test(sdram, l1inst);
-
- abort:
- sram_free(l1inst);
- kfree(sdram);
-
- if (ret)
- return -EIO;
-
- pr_info("PASS: all tests worked !\n");
- return 0;
-}
-late_initcall(isram_test_init);
-
-static __exit void isram_test_exit(void)
-{
- /* stub to allow unloading */
-}
-module_exit(isram_test_exit);
-
-#endif
diff --git a/arch/blackfin/mm/maccess.c b/arch/blackfin/mm/maccess.c
deleted file mode 100644
index e2532114c5fd..000000000000
--- a/arch/blackfin/mm/maccess.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * safe read and write memory routines callable while atomic
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/uaccess.h>
-#include <asm/dma.h>
-
-static int validate_memory_access_address(unsigned long addr, int size)
-{
- if (size < 0 || addr == 0)
- return -EFAULT;
- return bfin_mem_access_type(addr, size);
-}
-
-long probe_kernel_read(void *dst, const void *src, size_t size)
-{
- unsigned long lsrc = (unsigned long)src;
- int mem_type;
-
- mem_type = validate_memory_access_address(lsrc, size);
- if (mem_type < 0)
- return mem_type;
-
- if (lsrc >= SYSMMR_BASE) {
- if (size == 2 && lsrc % 2 == 0) {
- u16 mmr = bfin_read16(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- } else if (size == 4 && lsrc % 4 == 0) {
- u32 mmr = bfin_read32(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_read(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
-
-long probe_kernel_write(void *dst, const void *src, size_t size)
-{
- unsigned long ldst = (unsigned long)dst;
- int mem_type;
-
- mem_type = validate_memory_access_address(ldst, size);
- if (mem_type < 0)
- return mem_type;
-
- if (ldst >= SYSMMR_BASE) {
- if (size == 2 && ldst % 2 == 0) {
- u16 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write16(dst, mmr);
- return 0;
- } else if (size == 4 && ldst % 4 == 0) {
- u32 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write32(dst, mmr);
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_write(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
deleted file mode 100644
index d2a96c2c02a3..000000000000
--- a/arch/blackfin/mm/sram-alloc.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * SRAM allocator for Blackfin on-chip memory
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/miscdevice.h>
-#include <linux/ioport.h>
-#include <linux/fcntl.h>
-#include <linux/init.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-#include <linux/rtc.h>
-#include <linux/slab.h>
-#include <linux/mm_types.h>
-
-#include <asm/blackfin.h>
-#include <asm/mem_map.h>
-#include "blackfin_sram.h"
-
-/* the data structure for L1 scratchpad and DATA SRAM */
-struct sram_piece {
- void *paddr;
- int size;
- pid_t pid;
- struct sram_piece *next;
-};
-
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head);
-
-#if L1_DATA_A_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head);
-#endif
-
-#if L1_DATA_B_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head);
-#endif
-
-#if L1_DATA_A_LENGTH || L1_DATA_B_LENGTH
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock);
-#endif
-
-#if L1_CODE_LENGTH != 0
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head);
-#endif
-
-#if L2_LENGTH != 0
-static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp;
-static struct sram_piece free_l2_sram_head, used_l2_sram_head;
-#endif
-
-static struct kmem_cache *sram_piece_cache;
-
-/* L1 Scratchpad SRAM initialization function */
-static void __init l1sram_init(void)
-{
- unsigned int cpu;
- unsigned long reserve;
-
-#ifdef CONFIG_SMP
- reserve = 0;
-#else
- reserve = sizeof(struct l1_scratch_task_info);
-#endif
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_ssram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_ssram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu) + reserve;
- per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH - reserve;
- per_cpu(free_l1_ssram_head, cpu).next->pid = 0;
- per_cpu(free_l1_ssram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_ssram_head, cpu).next = NULL;
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1sram_lock, cpu));
- printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n",
- L1_SCRATCH_LENGTH >> 10);
- }
-}
-
-static void __init l1_data_sram_init(void)
-{
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- unsigned int cpu;
-#endif
-#if L1_DATA_A_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_A_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_A_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_A_sram_head, cpu).next->paddr =
- (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->size =
- L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_A_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n",
- L1_DATA_A_LENGTH >> 10,
- per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10);
- }
-#endif
-#if L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_B_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_B_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_B_sram_head, cpu).next->paddr =
- (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->size =
- L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_B_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n",
- L1_DATA_B_LENGTH >> 10,
- per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10);
- /* mutex initialize */
- }
-#endif
-
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- spin_lock_init(&per_cpu(l1_data_sram_lock, cpu));
-#endif
-}
-
-static void __init l1_inst_sram_init(void)
-{
-#if L1_CODE_LENGTH != 0
- unsigned int cpu;
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_inst_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_inst_sram_head, cpu).next) {
- printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
- return;
- }
-
- per_cpu(free_l1_inst_sram_head, cpu).next->paddr =
- (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->size =
- L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_inst_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n",
- L1_CODE_LENGTH >> 10,
- per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu));
- }
-#endif
-}
-
-#ifdef __ADSPBF60x__
-static irqreturn_t l2_ecc_err(int irq, void *dev_id)
-{
- int status;
-
- printk(KERN_ERR "L2 ecc error happened\n");
- status = bfin_read32(L2CTL0_STAT);
- if (status & 0x1)
- printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0));
- if (status & 0x2)
- printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1));
-
- status = status >> 8;
- if (status)
- printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n",
- status, bfin_read32(L2CTL0_ERRADDR0 + status));
-
- panic("L2 Ecc error");
- return IRQ_HANDLED;
-}
-#endif
-
-static void __init l2_sram_init(void)
-{
-#if L2_LENGTH != 0
-
-#ifdef __ADSPBF60x__
- int ret;
-
- ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err",
- NULL);
- if (unlikely(ret < 0)) {
- printk(KERN_INFO "Fail to request l2 ecc error interrupt");
- return;
- }
-#endif
-
- free_l2_sram_head.next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!free_l2_sram_head.next) {
- printk(KERN_INFO "Fail to initialize L2 SRAM.\n");
- return;
- }
-
- free_l2_sram_head.next->paddr =
- (void *)L2_START + (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->size =
- L2_LENGTH - (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->pid = 0;
- free_l2_sram_head.next->next = NULL;
-
- used_l2_sram_head.next = NULL;
-
- printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n",
- L2_LENGTH >> 10,
- free_l2_sram_head.next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&l2_sram_lock);
-#endif
-}
-
-static int __init bfin_sram_init(void)
-{
- sram_piece_cache = kmem_cache_create("sram_piece_cache",
- sizeof(struct sram_piece),
- 0, SLAB_PANIC, NULL);
-
- l1sram_init();
- l1_data_sram_init();
- l1_inst_sram_init();
- l2_sram_init();
-
- return 0;
-}
-pure_initcall(bfin_sram_init);
-
-/* SRAM allocate function */
-static void *_sram_alloc(size_t size, struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (size <= 0 || !pfree_head || !pused_head)
- return NULL;
-
- /* Align the size */
- size = (size + 3) & ~3;
-
- pslot = pfree_head->next;
- plast = pfree_head;
-
- /* search an available piece slot */
- while (pslot != NULL && size > pslot->size) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return NULL;
-
- if (pslot->size == size) {
- plast->next = pslot->next;
- pavail = pslot;
- } else {
- /* use atomic so our L1 allocator can be used atomically */
- pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC);
-
- if (!pavail)
- return NULL;
-
- pavail->paddr = pslot->paddr;
- pavail->size = size;
- pslot->paddr += size;
- pslot->size -= size;
- }
-
- pavail->pid = current->pid;
-
- pslot = pused_head->next;
- plast = pused_head;
-
- /* insert new piece into used piece list !!! */
- while (pslot != NULL && pavail->paddr < pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- pavail->next = pslot;
- plast->next = pavail;
-
- return pavail->paddr;
-}
-
-/* Allocate the largest available block. */
-static void *_sram_alloc_max(struct sram_piece *pfree_head,
- struct sram_piece *pused_head,
- unsigned long *psize)
-{
- struct sram_piece *pslot, *pmax;
-
- if (!pfree_head || !pused_head)
- return NULL;
-
- pmax = pslot = pfree_head->next;
-
- /* search an available piece slot */
- while (pslot != NULL) {
- if (pslot->size > pmax->size)
- pmax = pslot;
- pslot = pslot->next;
- }
-
- if (!pmax)
- return NULL;
-
- *psize = pmax->size;
-
- return _sram_alloc(*psize, pfree_head, pused_head);
-}
-
-/* SRAM free function */
-static int _sram_free(const void *addr,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
- plast = pused_head;
-
- /* search an available piece slot */
- while (pslot != NULL && pslot->paddr != addr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return -1;
-
- plast->next = pslot->next;
- pavail = pslot;
- pavail->pid = 0;
-
- /* insert free pieces back to the free list */
- pslot = pfree_head->next;
- plast = pfree_head;
-
- while (pslot != NULL && addr > pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (plast != pfree_head && plast->paddr + plast->size == pavail->paddr) {
- plast->size += pavail->size;
- kmem_cache_free(sram_piece_cache, pavail);
- } else {
- pavail->next = plast->next;
- plast->next = pavail;
- plast = pavail;
- }
-
- if (pslot && plast->paddr + plast->size == pslot->paddr) {
- plast->size += pslot->size;
- plast->next = pslot->next;
- kmem_cache_free(sram_piece_cache, pslot);
- }
-
- return 0;
-}
-
-int sram_free(const void *addr)
-{
-
-#if L1_CODE_LENGTH != 0
- if (addr >= (void *)get_l1_code_start()
- && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH))
- return l1_inst_sram_free(addr);
- else
-#endif
-#if L1_DATA_A_LENGTH != 0
- if (addr >= (void *)get_l1_data_a_start()
- && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH))
- return l1_data_A_sram_free(addr);
- else
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (addr >= (void *)get_l1_data_b_start()
- && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH))
- return l1_data_B_sram_free(addr);
- else
-#endif
-#if L2_LENGTH != 0
- if (addr >= (void *)L2_START
- && addr < (void *)(L2_START + L2_LENGTH))
- return l2_sram_free(addr);
- else
-#endif
- return -1;
-}
-EXPORT_SYMBOL(sram_free);
-
-void *l1_data_A_sram_alloc(size_t size)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_alloc);
-
-int l1_data_A_sram_free(const void *addr)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_free);
-
-void *l1_data_B_sram_alloc(size_t size)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_alloc);
-
-int l1_data_B_sram_free(const void *addr)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_free);
-
-void *l1_data_sram_alloc(size_t size)
-{
- void *addr = l1_data_A_sram_alloc(size);
-
- if (!addr)
- addr = l1_data_B_sram_alloc(size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_alloc);
-
-void *l1_data_sram_zalloc(size_t size)
-{
- void *addr = l1_data_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_zalloc);
-
-int l1_data_sram_free(const void *addr)
-{
- int ret;
- ret = l1_data_A_sram_free(addr);
- if (ret == -1)
- ret = l1_data_B_sram_free(addr);
- return ret;
-}
-EXPORT_SYMBOL(l1_data_sram_free);
-
-void *l1_inst_sram_alloc(size_t size)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_alloc);
-
-int l1_inst_sram_free(const void *addr)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_free);
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc(size_t size)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc_max(size_t *psize)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu), psize);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory free function */
-int l1sram_free(const void *addr)
-{
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return ret;
-}
-
-void *l2_sram_alloc(size_t size)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- void *addr;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- addr = _sram_alloc(size, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- pr_debug("Allocated address in l2_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_alloc);
-
-void *l2_sram_zalloc(size_t size)
-{
- void *addr = l2_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l2_sram_zalloc);
-
-int l2_sram_free(const void *addr)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- int ret;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- ret = _sram_free(addr, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_free);
-
-int sram_free_with_lsl(const void *addr)
-{
- struct sram_list_struct *lsl, **tmp;
- struct mm_struct *mm = current->mm;
- int ret = -1;
-
- for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
- if ((*tmp)->addr == addr) {
- lsl = *tmp;
- ret = sram_free(addr);
- *tmp = lsl->next;
- kfree(lsl);
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(sram_free_with_lsl);
-
-/* Allocate memory and keep in L1 SRAM List (lsl) so that the resources are
- * tracked. These are designed for userspace so that when a process exits,
- * we can safely reap their resources.
- */
-void *sram_alloc_with_lsl(size_t size, unsigned long flags)
-{
- void *addr = NULL;
- struct sram_list_struct *lsl = NULL;
- struct mm_struct *mm = current->mm;
-
- lsl = kzalloc(sizeof(struct sram_list_struct), GFP_KERNEL);
- if (!lsl)
- return NULL;
-
- if (flags & L1_INST_SRAM)
- addr = l1_inst_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_A_SRAM))
- addr = l1_data_A_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_B_SRAM))
- addr = l1_data_B_sram_alloc(size);
-
- if (addr == NULL && (flags & L2_SRAM))
- addr = l2_sram_alloc(size);
-
- if (addr == NULL) {
- kfree(lsl);
- return NULL;
- }
- lsl->addr = addr;
- lsl->length = size;
- lsl->next = mm->context.sram_list;
- mm->context.sram_list = lsl;
- return addr;
-}
-EXPORT_SYMBOL(sram_alloc_with_lsl);
-
-#ifdef CONFIG_PROC_FS
-/* Once we get a real allocator, we'll throw all of this away.
- * Until then, we need some sort of visibility into the L1 alloc.
- */
-/* Need to keep line of output the same. Currently, that is 44 bytes
- * (including newline).
- */
-static int _sram_proc_show(struct seq_file *m, const char *desc,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "ALLOCATED");
-
- pslot = pslot->next;
- }
-
- pslot = pfree_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "FREE");
-
- pslot = pslot->next;
- }
-
- return 0;
-}
-static int sram_proc_show(struct seq_file *m, void *v)
-{
- unsigned int cpu;
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- if (_sram_proc_show(m, "Scratchpad",
- &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
- goto not_done;
-#if L1_DATA_A_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data A",
- &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data B",
- &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_CODE_LENGTH != 0
- if (_sram_proc_show(m, "L1 Instruction",
- &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu)))
- goto not_done;
-#endif
- }
-#if L2_LENGTH != 0
- if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
- goto not_done;
-#endif
- not_done:
- return 0;
-}
-
-static int sram_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, sram_proc_show, NULL);
-}
-
-static const struct file_operations sram_proc_ops = {
- .open = sram_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init sram_proc_init(void)
-{
- struct proc_dir_entry *ptr;
-
- ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
- if (!ptr) {
- printk(KERN_WARNING "unable to create /proc/sram\n");
- return -1;
- }
- return 0;
-}
-late_initcall(sram_proc_init);
-#endif
diff --git a/arch/blackfin/oprofile/Makefile b/arch/blackfin/oprofile/Makefile
deleted file mode 100644
index e89e1c9f3496..000000000000
--- a/arch/blackfin/oprofile/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/oprofile/Makefile
-#
-
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
- oprof.o cpu_buffer.o buffer_sync.o \
- event_buffer.o oprofile_files.o \
- oprofilefs.o oprofile_stats.o \
- timer_int.o )
-
-oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o
diff --git a/arch/blackfin/oprofile/bfin_oprofile.c b/arch/blackfin/oprofile/bfin_oprofile.c
deleted file mode 100644
index c3b9713b23f8..000000000000
--- a/arch/blackfin/oprofile/bfin_oprofile.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * bfin_oprofile.c - Blackfin oprofile code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/oprofile.h>
-#include <linux/init.h>
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- return -1;
-}
-
-void oprofile_arch_exit(void)
-{
-}
diff --git a/arch/c6x/Makefile b/arch/c6x/Makefile
index 6f6096ff05a4..6ab942e6c534 100644
--- a/arch/c6x/Makefile
+++ b/arch/c6x/Makefile
@@ -25,6 +25,7 @@ KBUILD_AFLAGS += -mbig-endian
LINKFLAGS += -mbig-endian
KBUILD_LDFLAGS += -mbig-endian
LDFLAGS += -EB
+CHECKFLAGS += -D_BIG_ENDIAN
endif
head-y := arch/c6x/kernel/head.o
diff --git a/arch/c6x/kernel/asm-offsets.c b/arch/c6x/kernel/asm-offsets.c
index cff57764fcad..0f8fde494875 100644
--- a/arch/c6x/kernel/asm-offsets.c
+++ b/arch/c6x/kernel/asm-offsets.c
@@ -107,7 +107,6 @@ void foo(void)
/* These would be unneccessary if we ran asm files
* through the preprocessor.
*/
- DEFINE(KTHREAD_SIZE, THREAD_SIZE);
DEFINE(KTHREAD_SHIFT, THREAD_SHIFT);
DEFINE(KTHREAD_START_SP, THREAD_START_SP);
DEFINE(ENOSYS_, ENOSYS);
diff --git a/arch/c6x/platforms/plldata.c b/arch/c6x/platforms/plldata.c
index e8b6cc6a7b5a..1ef04b5ab93f 100644
--- a/arch/c6x/platforms/plldata.c
+++ b/arch/c6x/platforms/plldata.c
@@ -19,6 +19,7 @@
#include <asm/clock.h>
#include <asm/setup.h>
+#include <asm/special_insns.h>
#include <asm/irq.h>
/*
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
deleted file mode 100644
index cd5a0865c97f..000000000000
--- a/arch/cris/Kconfig
+++ /dev/null
@@ -1,595 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config MMU
- bool
- default y
-
-config ZONE_DMA
- bool
- default y
-
-config RWSEM_GENERIC_SPINLOCK
- bool
- default y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
-
-config ARCH_HAS_ILOG2_U32
- bool
- default n
-
-config ARCH_HAS_ILOG2_U64
- bool
- default n
-
-config GENERIC_HWEIGHT
- bool
- default y
-
-config GENERIC_CALIBRATE_DELAY
- bool
- default y
-
-config NO_IOPORT_MAP
- def_bool y if !PCI
-
-config NO_DMA
- def_bool y if !PCI
-
-config FORCE_MAX_ZONEORDER
- int
- default 6
-
-config TRACE_IRQFLAGS_SUPPORT
- depends on ETRAX_ARCH_V32
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config LOCKDEP_SUPPORT
- depends on ETRAX_ARCH_V32
- def_bool y
-
-config CRIS
- bool
- default y
- select HAVE_IDE
- select GENERIC_ATOMIC64
- select HAVE_UID16
- select VIRT_TO_BUS
- select ARCH_WANT_IPC_PARSE_VERSION
- select GENERIC_IRQ_SHOW
- select GENERIC_IOMAP
- select MODULES_USE_ELF_RELA
- select CLONE_BACKWARDS2
- select HAVE_EXIT_THREAD if ETRAX_ARCH_V32
- select OLD_SIGSUSPEND
- select OLD_SIGACTION
- select GPIOLIB
- select IRQ_DOMAIN if ETRAX_ARCH_V32
- select OF if ETRAX_ARCH_V32
- select OF_EARLY_FLATTREE if ETRAX_ARCH_V32
- select CLKSRC_MMIO if ETRAX_ARCH_V32
- select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32
- select GENERIC_SCHED_CLOCK if ETRAX_ARCH_V32
- select HAVE_DEBUG_BUGVERBOSE if ETRAX_ARCH_V32
- select HAVE_NMI
- select DMA_DIRECT_OPS if PCI
-
-config HZ
- int
- default 100
-
-config NR_CPUS
- int
- default "1"
-
-config BUILTIN_DTB
- string "DTB to build into the kernel image"
- depends on OF
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-menu "General setup"
-
-source "fs/Kconfig.binfmt"
-
-config ETRAX_CMDLINE
- string "Kernel command line"
- default "root=/dev/mtdblock3"
- help
- Pass additional commands to the kernel.
-
-config ETRAX_WATCHDOG
- bool "Enable ETRAX watchdog"
- help
- Enable the built-in watchdog timer support on ETRAX based embedded
- network computers.
-
-config ETRAX_WATCHDOG_NICE_DOGGY
- bool "Disable watchdog during Oops printouts"
- depends on ETRAX_WATCHDOG
- help
- By enabling this you make sure that the watchdog does not bite while
- printing oopses. Recommended for development systems but not for
- production releases.
-
-config ETRAX_FAST_TIMER
- bool "Enable ETRAX fast timer API"
- help
- This options enables the API to a fast timer implementation using
- timer1 to get sub jiffie resolution timers (primarily one-shot
- timers).
- This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled.
-
-config ETRAX_KMALLOCED_MODULES
- bool "Enable module allocation with kmalloc"
- help
- Enable module allocation with kmalloc instead of vmalloc.
-
-source "kernel/Kconfig.preempt"
-
-source mm/Kconfig
-
-endmenu
-
-menu "Hardware setup"
-
-choice
- prompt "Processor type"
- default ETRAX100LX
-
-config ETRAX100LX
- bool "ETRAX-100LX-v1"
- select ARCH_USES_GETTIMEOFFSET
- help
- Support version 1 of the ETRAX 100LX.
-
-config ETRAX100LX_V2
- bool "ETRAX-100LX-v2"
- select ARCH_USES_GETTIMEOFFSET
- help
- Support version 2 of the ETRAX 100LX.
-
-config ETRAXFS
- bool "ETRAX-FS-V32"
- help
- Support CRIS V32.
-
-config CRIS_MACH_ARTPEC3
- bool "ARTPEC-3"
- help
- Support Axis ARTPEC-3.
-
-endchoice
-
-config ETRAX_ARCH_V10
- bool
- default y if ETRAX100LX || ETRAX100LX_V2
- default n if !(ETRAX100LX || ETRAX100LX_V2)
- select TTY
-
-config ETRAX_ARCH_V32
- bool
- default y if (ETRAXFS || CRIS_MACH_ARTPEC3)
- default n if !(ETRAXFS || CRIS_MACH_ARTPEC3)
-
-config ETRAX_DRAM_SIZE
- int "DRAM size (dec, in MB)"
- default "8"
- help
- Size of DRAM (decimal in MB) typically 2, 8 or 16.
-
-config ETRAX_VMEM_SIZE
- int "Video memory size (dec, in MB)"
- depends on ETRAX_ARCH_V32 && !ETRAXFS
- default 8 if !ETRAXFS
- help
- Size of Video accessible memory (decimal, in MB).
-
-config ETRAX_FLASH_BUSWIDTH
- int "Buswidth of NOR flash in bytes"
- default "2"
- help
- Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2.
-
-config ETRAX_FLASH1_SIZE
- int "FLASH1 size (dec, in MB. 0 = Unknown)"
- default "0"
-
-choice
- prompt "Product debug-port"
- default ETRAX_DEBUG_PORT0
-
-config ETRAX_DEBUG_PORT0
- bool "Serial-0"
- help
- Choose a serial port for the ETRAX debug console. Default to
- port 0.
-
-config ETRAX_DEBUG_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for the console.
-
-config ETRAX_DEBUG_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for the console.
-
-config ETRAX_DEBUG_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for the console.
-
-config ETRAX_DEBUG_PORT_NULL
- bool "disabled"
- help
- Disable serial-port debugging.
-
-endchoice
-
-choice
- prompt "Kernel GDB port"
- depends on ETRAX_KGDB
- default ETRAX_KGDB_PORT0
- help
- Choose a serial port for kernel debugging. NOTE: This port should
- not be enabled under Drivers for built-in interfaces (as it has its
- own initialization code) and should not be the same as the debug port.
-
-config ETRAX_KGDB_PORT0
- bool "Serial-0"
- help
- Use serial port 0 for kernel debugging.
-
-config ETRAX_KGDB_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for kernel debugging.
-
-config ETRAX_KGDB_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for kernel debugging.
-
-config ETRAX_KGDB_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for kernel debugging.
-
-endchoice
-
-source arch/cris/arch-v10/Kconfig
-source arch/cris/arch-v32/Kconfig
-
-endmenu
-
-source "net/Kconfig"
-
-# bring in ETRAX built-in drivers
-menu "Drivers for built-in interfaces"
-source arch/cris/arch-v10/drivers/Kconfig
-source arch/cris/arch-v32/drivers/Kconfig
-
-config ETRAX_AXISFLASHMAP
- bool "Axis flash-map support"
- select MTD
- select MTD_CFI
- select MTD_CFI_AMDSTD
- select MTD_JEDECPROBE if ETRAX_ARCH_V32
- select MTD_BLOCK
- select MTD_COMPLEX_MAPPINGS
- help
- This option enables MTD mapping of flash devices. Needed to use
- flash memories. If unsure, say Y.
-
-config ETRAX_SYNCHRONOUS_SERIAL
- bool "Synchronous serial-port support"
- help
- Select this to enable the synchronous serial port driver.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT0
- bool "Synchronous serial port 0 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL
- help
- Enabled synchronous serial port 0.
-
-config ETRAX_SYNCHRONOUS_SERIAL0_DMA
- bool "Enable DMA on synchronous serial port 0."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT1
- bool "Synchronous serial port 1 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL && (ETRAXFS || ETRAX_ARCH_V10)
- help
- Enabled synchronous serial port 1.
-
-config ETRAX_SYNCHRONOUS_SERIAL1_DMA
- bool "Enable DMA on synchronous serial port 1."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-choice
- prompt "Network LED behavior"
- depends on ETRAX_ETHERNET
- default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
-
-config ETRAX_NETWORK_LED_ON_WHEN_LINK
- bool "LED_on_when_link"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
- bool "LED_on_when_activity"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-endchoice
-
-choice
- prompt "Ser0 DMA out channel"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10
-
-config ETRAX_SERIAL_PORT0_NO_DMA_OUT
- bool "Ser0 uses no DMA for output"
- help
- Do not use DMA for ser0 output.
-
-config ETRAX_SERIAL_PORT0_DMA6_OUT
- bool "Ser0 uses DMA6 for output"
- depends on ETRAXFS
- help
- Enables the DMA6 output channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT0_DMA0_OUT
- bool "Ser0 uses DMA0 for output"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA0 output channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser0 DMA in channel "
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser0.
-
-config ETRAX_SERIAL_PORT0_NO_DMA_IN
- bool "Ser0 uses no DMA for input"
- help
- Do not use DMA for ser0 input.
-
-config ETRAX_SERIAL_PORT0_DMA7_IN
- bool "Ser0 uses DMA7 for input"
- depends on ETRAXFS
- help
- Enables the DMA7 input channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT0_DMA1_IN
- bool "Ser0 uses DMA1 for input"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA1 input channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser1 DMA in channel "
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser1.
-
-config ETRAX_SERIAL_PORT1_NO_DMA_IN
- bool "Ser1 uses no DMA for input"
- help
- Do not use DMA for ser1 input.
-
-config ETRAX_SERIAL_PORT1_DMA5_IN
- bool "Ser1 uses DMA5 for input"
- depends on ETRAX_ARCH_V32
- help
- Enables the DMA5 input channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT1_DMA9_IN
- depends on ETRAX_ARCH_V10
- bool "Ser1 uses DMA9 for input"
-
-endchoice
-
-
-choice
- prompt "Ser1 DMA out channel"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser1.
-
-config ETRAX_SERIAL_PORT1_NO_DMA_OUT
- bool "Ser1 uses no DMA for output"
- help
- Do not use DMA for ser1 output.
-
-config ETRAX_SERIAL_PORT1_DMA8_OUT
- depends on ETRAX_ARCH_V10
- bool "Ser1 uses DMA8 for output"
-
-config ETRAX_SERIAL_PORT1_DMA4_OUT
- depends on ETRAX_ARCH_V32
- bool "Ser1 uses DMA4 for output"
- help
- Enables the DMA4 output channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser2 DMA out channel"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10
-
-config ETRAX_SERIAL_PORT2_NO_DMA_OUT
- bool "Ser2 uses no DMA for output"
- help
- Do not use DMA for ser2 output.
-
-config ETRAX_SERIAL_PORT2_DMA2_OUT
- bool "Ser2 uses DMA2 for output"
- depends on ETRAXFS || ETRAX_ARCH_V10
- help
- Enables the DMA2 output channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT2_DMA6_OUT
- bool "Ser2 uses DMA6 for output"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA6 output channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser2 DMA in channel"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser2.
-
-config ETRAX_SERIAL_PORT2_NO_DMA_IN
- bool "Ser2 uses no DMA for input"
- help
- Do not use DMA for ser2 input.
-
-config ETRAX_SERIAL_PORT2_DMA3_IN
- bool "Ser2 uses DMA3 for input"
- depends on ETRAXFS || ETRAX_ARCH_V10
- help
- Enables the DMA3 input channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT2_DMA7_IN
- bool "Ser2 uses DMA7 for input"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA7 input channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser3 DMA in channel"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser3.
-
-config ETRAX_SERIAL_PORT3_NO_DMA_IN
- bool "Ser3 uses no DMA for input"
- help
- Do not use DMA for ser3 input.
-
-config ETRAX_SERIAL_PORT3_DMA5_IN
- depends on ETRAX_ARCH_V10
- bool "DMA 5"
-
-endchoice
-
-choice
- prompt "Ser3 DMA out channel"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10
-
-config ETRAX_SERIAL_PORT3_NO_DMA_OUT
- bool "Ser3 uses no DMA for output"
- help
- Do not use DMA for ser3 output.
-
-config ETRAX_SERIAL_PORT3_DMA4_OUT
- depends on ETRAX_ARCH_V10
- bool "DMA 4"
-
-endchoice
-
-endmenu
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/cris/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/cris/Kconfig.debug b/arch/cris/Kconfig.debug
deleted file mode 100644
index 6084d5e0c512..000000000000
--- a/arch/cris/Kconfig.debug
+++ /dev/null
@@ -1,41 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-config PROFILING
- bool "Kernel profiling support"
-
-config SYSTEM_PROFILER
- bool "System profiling support"
-
-source "lib/Kconfig.debug"
-
-config ETRAX_KGDB
- bool "Use kernel GDB debugger"
- depends on DEBUG_KERNEL
- ---help---
- The CRIS version of gdb can be used to remotely debug a running
- Linux kernel via the serial debug port. Provided you have gdb-cris
- installed, run gdb-cris vmlinux, then type
-
- (gdb) set remotebaud 115200 <- kgdb uses 115200 as default
- (gdb) target remote /dev/ttyS0 <- maybe you use another port
-
- This should connect you to your booted kernel (or boot it now if you
- didn't before). The kernel halts when it boots, waiting for gdb if
- this option is turned on!
-
-
-config DEBUG_NMI_OOPS
- bool "NMI causes oops printout"
- depends on DEBUG_KERNEL
- help
- If the system locks up without any debug information you can say Y
- here to make it possible to dump an OOPS with an external NMI.
-
-config NO_SEGFAULT_TERMINATION
- bool "Keep segfaulting processes"
- help
- Place segfaulting user mode processes on a wait queue instead of
- delivering a terminating SIGSEGV to allow debugging with gdb.
-
-endmenu
diff --git a/arch/cris/Makefile b/arch/cris/Makefile
deleted file mode 100644
index 4a5404b3d0e4..000000000000
--- a/arch/cris/Makefile
+++ /dev/null
@@ -1,104 +0,0 @@
-#
-# cris/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies. Remember to do have actions
-# for "archclean" and "archdep" for cleaning up and making dependencies for
-# this architecture
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-
-KBUILD_DEFCONFIG := etrax-100lx_v2_defconfig
-
-arch-y := v10
-arch-$(CONFIG_ETRAX_ARCH_V10) := v10
-arch-$(CONFIG_ETRAX_ARCH_V32) := v32
-
-# No config available for make clean etc
-mach-y := fs
-mach-$(CONFIG_CRIS_MACH_ARTPEC3) := a3
-mach-$(CONFIG_ETRAXFS) := fs
-
-ifneq ($(arch-y),)
-SARCH := arch-$(arch-y)
-inc := -Iarch/cris/include/uapi/$(SARCH)
-inc += -Iarch/cris/include/$(SARCH)
-inc += -Iarch/cris/include/uapi/$(SARCH)/arch
-inc += -Iarch/cris/include/$(SARCH)/arch
-else
-SARCH :=
-inc :=
-endif
-
-ifneq ($(mach-y),)
-MACH := mach-$(mach-y)
-inc += -Iarch/cris/include/$(SARCH)/$(MACH)/
-inc += -Iarch/cris/include/$(SARCH)/$(MACH)/mach
-else
-MACH :=
-endif
-
-ifneq ($(CONFIG_BUILTIN_DTB),"")
-core-$(CONFIG_OF) += arch/cris/boot/dts/
-endif
-
-LD = $(CROSS_COMPILE)ld -mcrislinux
-
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-
-KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc)
-KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc)
-KBUILD_CPPFLAGS += $(inc)
-
-ifdef CONFIG_FRAME_POINTER
-KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g
-KBUILD_CFLAGS += -fno-omit-frame-pointer
-endif
-
-head-y := arch/cris/$(SARCH)/kernel/head.o
-
-LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libgcc.a)
-
-core-y += arch/cris/kernel/ arch/cris/mm/
-core-y += arch/cris/$(SARCH)/kernel/ arch/cris/$(SARCH)/mm/
-ifdef CONFIG_ETRAX_ARCH_V32
-core-y += arch/cris/$(SARCH)/$(MACH)/
-endif
-drivers-y += arch/cris/$(SARCH)/drivers/
-libs-y += arch/cris/$(SARCH)/lib/ $(LIBGCC)
-
-# cris source path
-SRC_ARCH = $(srctree)/arch/cris
-# cris object files path
-OBJ_ARCH = $(objtree)/arch/cris
-
-boot := arch/cris/boot
-MACHINE := arch/cris/$(SARCH)
-
-all: zImage
-
-zImage Image: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
-
-archprepare:
-
-archclean:
- $(Q)if [ -e arch/cris/boot ]; then \
- $(MAKE) $(clean)=arch/cris/boot; \
- fi
-
-CLEAN_FILES += \
- $(boot)/zImage \
- $(boot)/compressed/decompress.bin \
- $(boot)/compressed/piggy.gz \
- $(boot)/rescue/rescue.bin
-
-
-# MRPROPER_FILES +=
-
-define archhelp
- echo '* zImage - Compressed kernel image (arch/cris/boot/zImage)'
- echo '* Image - Uncompressed kernel image (arch/cris/boot/Image)'
-endef
diff --git a/arch/cris/arch-v10/Kconfig b/arch/cris/arch-v10/Kconfig
deleted file mode 100644
index d4015a931374..000000000000
--- a/arch/cris/arch-v10/Kconfig
+++ /dev/null
@@ -1,399 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V10
-
-menu "CRIS v10 options"
-
-# ETRAX 100LX v1 has a MMU "feature" requiring a low mapping
-config CRIS_LOW_MAP
- bool
- depends on ETRAX_ARCH_V10 && ETRAX100LX
- default y
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- depends on ETRAX_ARCH_V10
- default "c0000000" if !ETRAX100LX
- default "60000000" if ETRAX100LX
-
-choice
- prompt "Product LED port"
- depends on ETRAX_ARCH_V10
- default ETRAX_PA_LEDS
-
-config ETRAX_PA_LEDS
- bool "Port-PA-LEDs"
- help
- The ETRAX network driver is responsible for flashing LED's when
- packets arrive and are sent. It uses macros defined in
- <file:arch/cris/include/asm/io.h>, and those macros are defined after
- what YOU choose in this option. The actual bits used are configured
- separately. Select this if the LEDs are on port PA. Some products
- put the leds on PB or a memory-mapped latch (CSP0) instead.
-
-config ETRAX_PB_LEDS
- bool "Port-PB-LEDs"
- help
- The ETRAX network driver is responsible for flashing LED's when
- packets arrive and are sent. It uses macros defined in
- <file:arch/cris/include/asm/io.h>, and those macros are defined after
- what YOU choose in this option. The actual bits used are configured
- separately. Select this if the LEDs are on port PB. Some products
- put the leds on PA or a memory-mapped latch (CSP0) instead.
-
-config ETRAX_CSP0_LEDS
- bool "Port-CSP0-LEDs"
- help
- The ETRAX network driver is responsible for flashing LED's when
- packets arrive and are sent. It uses macros defined in
- <file:arch/cris/include/asm/io.h>, and those macros are defined after
- what YOU choose in this option. The actual bits used are configured
- separately. Select this if the LEDs are on a memory-mapped latch
- using chip select CSP0, this is mapped at 0x90000000.
- Some products put the leds on PA or PB instead.
-
-config ETRAX_NO_LEDS
- bool "None"
- help
- Select this option if you don't have any LED at all.
-
-endchoice
-
-config ETRAX_LED1G
- int "First green LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "2"
- help
- Bit to use for the first green LED.
- Most Axis products use bit 2 here.
-
-config ETRAX_LED1R
- int "First red LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "3"
- help
- Bit to use for the first red LED.
- Most Axis products use bit 3 here.
- For products with only one controllable LED,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED2G
- int "Second green LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "4"
- help
- Bit to use for the second green LED. The "Active" LED.
- Most Axis products use bit 4 here.
- For products with only one controllable LED,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED2R
- int "Second red LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "5"
- help
- Bit to use for the second red LED.
- Most Axis products use bit 5 here.
- For products with only one controllable LED,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED3G
- int "Third green LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "2"
- help
- Bit to use for the third green LED. The "Drive" LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED3R
- int "Third red LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "2"
- help
- Bit to use for the third red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED4R
- int "Fourth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fourth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED4G
- int "Fourth green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fourth green LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED5R
- int "Fifth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fifth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED5G
- int "Fifth green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fifth green LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED6R
- int "Sixth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the sixth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED6G
- int "Sixth green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the sixth green LED. The "Drive" LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED7R
- int "Seventh red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the seventh red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED7G
- int "Seventh green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the seventh green LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED8Y
- int "Eighth yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the eighth yellow LED. The "Drive" LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED9Y
- int "Ninth yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the ninth yellow LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED10Y
- int "Tenth yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the tenth yellow LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED11Y
- int "Eleventh yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the eleventh yellow LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED12R
- int "Twelfth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the twelfth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-
-choice
- prompt "Product rescue-port"
- depends on ETRAX_ARCH_V10
- default ETRAX_RESCUE_SER0
-
-config ETRAX_RESCUE_SER0
- bool "Serial-0"
- help
- Select one of the four serial ports as a rescue port. The default
- is port 0.
-
-config ETRAX_RESCUE_SER1
- bool "Serial-1"
- help
- Use serial port 1 as the rescue port.
-
-config ETRAX_RESCUE_SER2
- bool "Serial-2"
- help
- Use serial port 2 as the rescue port.
-
-config ETRAX_RESCUE_SER3
- bool "Serial-3"
- help
- Use serial port 3 as the rescue port.
-
-endchoice
-
-config ETRAX_DEF_R_WAITSTATES
- hex "R_WAITSTATES"
- depends on ETRAX_ARCH_V10
- default "95a6"
- help
- Waitstates for SRAM, Flash and peripherals (not DRAM). 95f8 is a
- good choice for most Axis products...
-
-config ETRAX_DEF_R_BUS_CONFIG
- hex "R_BUS_CONFIG"
- depends on ETRAX_ARCH_V10
- default "104"
- help
- Assorted bits controlling write mode, DMA burst length etc. 104 is
- a good choice for most Axis products...
-
-config ETRAX_SDRAM
- bool "SDRAM support"
- depends on ETRAX_ARCH_V10
- help
- Enable this if you use SDRAM chips and configure
- R_SDRAM_CONFIG and R_SDRAM_TIMING as well.
-
-config ETRAX_DEF_R_DRAM_CONFIG
- hex "R_DRAM_CONFIG"
- depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM
- default "1a200040"
- help
- The R_DRAM_CONFIG register specifies everything on how the DRAM
- chips in the system are connected to the ETRAX CPU. This is
- different depending on the manufacturer, chip type and number of
- chips. So this value often needs to be different for each Axis
- product.
-
-config ETRAX_DEF_R_DRAM_TIMING
- hex "R_DRAM_TIMING"
- depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM
- default "5611"
- help
- Different DRAM chips have different speeds. Current Axis products
- use 50ns DRAM chips which can use the timing: 5611.
-
-config ETRAX_DEF_R_SDRAM_CONFIG
- hex "R_SDRAM_CONFIG"
- depends on ETRAX_ARCH_V10 && ETRAX_SDRAM
- default "d2fa7878"
- help
- The R_SDRAM_CONFIG register specifies everything on how the SDRAM
- chips in the system are connected to the ETRAX CPU. This is
- different depending on the manufacturer, chip type and number of
- chips. So this value often needs to be different for each Axis
- product.
-
-config ETRAX_DEF_R_SDRAM_TIMING
- hex "R_SDRAM_TIMING"
- depends on ETRAX_ARCH_V10 && ETRAX_SDRAM
- default "80004801"
- help
- Different SDRAM chips have different timing.
-
-config ETRAX_DEF_R_PORT_PA_DIR
- hex "R_PORT_PA_DIR"
- depends on ETRAX_ARCH_V10
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_R_PORT_PA_DATA
- hex "R_PORT_PA_DATA"
- depends on ETRAX_ARCH_V10
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_R_PORT_PB_CONFIG
- hex "R_PORT_PB_CONFIG"
- depends on ETRAX_ARCH_V10
- default "00"
- help
- Configures the type of the general port B bits. 1 is chip select,
- 0 is port. Most products should use 00 here.
-
-config ETRAX_DEF_R_PORT_PB_DIR
- hex "R_PORT_PB_DIR"
- depends on ETRAX_ARCH_V10
- default "00"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used. Bits
- 0 and 1 on port PB are usually used for I2C communication, but the
- kernel I2C driver sets the appropriate directions itself so you
- don't need to take that into consideration when setting this option.
- If you don't know what to use, it is always safe to put all as
- inputs.
-
-config ETRAX_DEF_R_PORT_PB_DATA
- hex "R_PORT_PB_DATA"
- depends on ETRAX_ARCH_V10
- default "ff"
- help
- Configures the initial data for the general port A bits. Most
- products should use FF here.
-
-config ETRAX_SOFT_SHUTDOWN
- bool "Software Shutdown Support"
- depends on ETRAX_ARCH_V10
- help
- Enable this if ETRAX is used with a power-supply that can be turned
- off and on with PS_ON signal. Gives the possibility to detect
- powerbutton and then do a power off after unmounting disks.
-
-config ETRAX_SHUTDOWN_BIT
- int "Shutdown bit on port CSP0"
- depends on ETRAX_SOFT_SHUTDOWN
- default "12"
- help
- Configure what pin on CSPO-port that is used for controlling power
- supply.
-
-config ETRAX_POWERBUTTON_BIT
- int "Power button bit on port G"
- depends on ETRAX_SOFT_SHUTDOWN
- default "25"
- help
- Configure where power button is connected.
-
-endmenu
-
-endif
diff --git a/arch/cris/arch-v10/README.mm b/arch/cris/arch-v10/README.mm
deleted file mode 100644
index 67731d75cb51..000000000000
--- a/arch/cris/arch-v10/README.mm
+++ /dev/null
@@ -1,244 +0,0 @@
-Memory management for CRIS/MMU
-------------------------------
-HISTORY:
-
-$Log: README.mm,v $
-Revision 1.1 2001/12/17 13:59:27 bjornw
-Initial revision
-
-Revision 1.1 2000/07/10 16:25:21 bjornw
-Initial revision
-
-Revision 1.4 2000/01/17 02:31:59 bjornw
-Added discussion of paging and VM.
-
-Revision 1.3 1999/12/03 16:43:23 hp
-Blurb about that the 3.5G-limitation is not a MMU limitation
-
-Revision 1.2 1999/12/03 16:04:21 hp
-Picky comment about not mapping the first page
-
-Revision 1.1 1999/12/03 15:41:30 bjornw
-First version of CRIS/MMU memory layout specification.
-
-
-
-
-
-------------------------------
-
-See the ETRAX-NG HSDD for reference.
-
-We use the page-size of 8 kbytes, as opposed to the i386 page-size of 4 kbytes.
-
-The MMU can, apart from the normal mapping of pages, also do a top-level
-segmentation of the kernel memory space. We use this feature to avoid having
-to use page-tables to map the physical memory into the kernel's address
-space. We also use it to keep the user-mode virtual mapping in the same
-map during kernel-mode, so that the kernel easily can access the corresponding
-user-mode process' data.
-
-As a comparison, the Linux/i386 2.0 puts the kernel and physical RAM at
-address 0, overlapping with the user-mode virtual space, so that descriptor
-registers are needed for each memory access to specify which MMU space to
-map through. That changed in 2.2, putting the kernel/physical RAM at
-0xc0000000, to co-exist with the user-mode mapping. We will do something
-quite similar, but with the additional complexity of having to map the
-internal chip I/O registers and the flash memory area (including SRAM
-and peripherial chip-selets).
-
-The kernel-mode segmentation map:
-
- ------------------------ ------------------------
-FFFFFFFF| | => cached | |
- | kernel seg_f | flash | |
-F0000000|______________________| | |
-EFFFFFFF| | => uncached | |
- | kernel seg_e | flash | |
-E0000000|______________________| | DRAM |
-DFFFFFFF| | paged to any | Un-cached |
- | kernel seg_d | =======> | |
-D0000000|______________________| | |
-CFFFFFFF| | | |
- | kernel seg_c |==\ | |
-C0000000|______________________| \ |______________________|
-BFFFFFFF| | uncached | |
- | kernel seg_b |=====\=========>| Registers |
-B0000000|______________________| \c |______________________|
-AFFFFFFF| | \a | |
- | | \c | FLASH/SRAM/Peripheral|
- | | \h |______________________|
- | | \e | |
- | | \d | |
- | kernel seg_0 - seg_a | \==>| DRAM |
- | | | Cached |
- | | paged to any | |
- | | =======> |______________________|
- | | | |
- | | | Illegal |
- | | |______________________|
- | | | |
- | | | FLASH/SRAM/Peripheral|
-00000000|______________________| |______________________|
-
-In user-mode it looks the same except that only the space 0-AFFFFFFF is
-available. Therefore, in this model, the virtual address space per process
-is limited to 0xb0000000 bytes (minus 8192 bytes, since the first page,
-0..8191, is never mapped, in order to trap NULL references).
-
-It also means that the total physical RAM that can be mapped is 256 MB
-(kseg_c above). More RAM can be mapped by choosing a different segmentation
-and shrinking the user-mode memory space.
-
-The MMU can map all 4 GB in user mode, but doing that would mean that a
-few extra instructions would be needed for each access to user mode
-memory.
-
-The kernel needs access to both cached and uncached flash. Uncached is
-necessary because of the special write/erase sequences. Also, the
-peripherial chip-selects are decoded from that region.
-
-The kernel also needs its own virtual memory space. That is kseg_d. It
-is used by the vmalloc() kernel function to allocate virtual contiguous
-chunks of memory not possible using the normal kmalloc physical RAM
-allocator.
-
-The setting of the actual MMU control registers to use this layout would
-be something like this:
-
-R_MMU_KSEG = ( ( seg_f, seg ) | // Flash cached
- ( seg_e, seg ) | // Flash uncached
- ( seg_d, page ) | // kernel vmalloc area
- ( seg_c, seg ) | // kernel linear segment
- ( seg_b, seg ) | // kernel linear segment
- ( seg_a, page ) |
- ( seg_9, page ) |
- ( seg_8, page ) |
- ( seg_7, page ) |
- ( seg_6, page ) |
- ( seg_5, page ) |
- ( seg_4, page ) |
- ( seg_3, page ) |
- ( seg_2, page ) |
- ( seg_1, page ) |
- ( seg_0, page ) );
-
-R_MMU_KBASE_HI = ( ( base_f, 0x0 ) | // flash/sram/periph cached
- ( base_e, 0x8 ) | // flash/sram/periph uncached
- ( base_d, 0x0 ) | // don't care
- ( base_c, 0x4 ) | // physical RAM cached area
- ( base_b, 0xb ) | // uncached on-chip registers
- ( base_a, 0x0 ) | // don't care
- ( base_9, 0x0 ) | // don't care
- ( base_8, 0x0 ) ); // don't care
-
-R_MMU_KBASE_LO = ( ( base_7, 0x0 ) | // don't care
- ( base_6, 0x0 ) | // don't care
- ( base_5, 0x0 ) | // don't care
- ( base_4, 0x0 ) | // don't care
- ( base_3, 0x0 ) | // don't care
- ( base_2, 0x0 ) | // don't care
- ( base_1, 0x0 ) | // don't care
- ( base_0, 0x0 ) ); // don't care
-
-NOTE: while setting up the MMU, we run in a non-mapped mode in the DRAM (0x40
-segment) and need to setup the seg_4 to a unity mapping, so that we don't get
-a fault before we have had time to jump into the real kernel segment (0xc0). This
-is done in head.S temporarily, but fixed by the kernel later in paging_init.
-
-
-Paging - PTE's, PMD's and PGD's
--------------------------------
-
-[ References: asm/pgtable.h, asm/page.h, asm/mmu.h ]
-
-The paging mechanism uses virtual addresses to split a process memory-space into
-pages, a page being the smallest unit that can be freely remapped in memory. On
-Linux/CRIS, a page is 8192 bytes (for technical reasons not equal to 4096 as in
-most other 32-bit architectures). It would be inefficient to let a virtual memory
-mapping be controlled by a long table of page mappings, so it is broken down into
-a 2-level structure with a Page Directory containing pointers to Page Tables which
-each have maps of up to 2048 pages (8192 / sizeof(void *)). Linux can actually
-handle 3-level structures as well, with a Page Middle Directory in between, but
-in many cases, this is folded into a two-level structure by excluding the Middle
-Directory.
-
-We'll take a look at how an address is translated while we discuss how it's handled
-in the Linux kernel.
-
-The example address is 0xd004000c; in binary this is:
-
-31 23 15 7 0
-11010000 00000100 00000000 00001100
-
-|______| |__________||____________|
- PGD PTE page offset
-
-Given the top-level Page Directory, the offset in that directory is calculated
-using the upper 8 bits:
-
-static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
-{
- return mm->pgd + (address >> PGDIR_SHIFT);
-}
-
-PGDIR_SHIFT is the log2 of the amount of memory an entry in the PGD can map; in our
-case it is 24, corresponding to 16 MB. This means that each entry in the PGD
-corresponds to 16 MB of virtual memory.
-
-The pgd_t from our example will therefore be the 208'th (0xd0) entry in mm->pgd.
-
-Since the Middle Directory does not exist, it is a unity mapping:
-
-static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
- return (pmd_t *) dir;
-}
-
-The Page Table provides the final lookup by using bits 13 to 23 as index:
-
-static inline pte_t * pte_offset(pmd_t * dir, unsigned long address)
-{
- return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) &
- (PTRS_PER_PTE - 1));
-}
-
-PAGE_SHIFT is the log2 of the size of a page; 13 in our case. PTRS_PER_PTE is
-the number of pointers that fit in a Page Table and is used to mask off the
-PGD-part of the address.
-
-The so-far unused bits 0 to 12 are used to index inside a page linearily.
-
-The VM system
--------------
-
-The kernels own page-directory is the swapper_pg_dir, cleared in paging_init,
-and contains the kernels virtual mappings (the kernel itself is not paged - it
-is mapped linearily using kseg_c as described above). Architectures without
-kernel segments like the i386, need to setup swapper_pg_dir directly in head.S
-to map the kernel itself. swapper_pg_dir is pointed to by init_mm.pgd as the
-init-task's PGD.
-
-To see what support functions are used to setup a page-table, let's look at the
-kernel's internal paged memory system, vmalloc/vfree.
-
-void * vmalloc(unsigned long size)
-
-The vmalloc-system keeps a paged segment in kernel-space at 0xd0000000. What
-happens first is that a virtual address chunk is allocated to the request using
-get_vm_area(size). After that, physical RAM pages are allocated and put into
-the kernel's page-table using alloc_area_pages(addr, size).
-
-static int alloc_area_pages(unsigned long address, unsigned long size)
-
-First the PGD entry is found using init_mm.pgd. This is passed to
-alloc_area_pmd (remember the 3->2 folding). It uses pte_alloc_kernel to
-check if the PGD entry points anywhere - if not, a page table page is
-allocated and the PGD entry updated. Then the alloc_area_pte function is
-used just like alloc_area_pmd to check which page table entry is desired,
-and a physical page is allocated and the table entry updated. All of this
-is repeated at the top-level until the entire address range specified has
-been mapped.
-
-
-
diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig
deleted file mode 100644
index 8792af63c049..000000000000
--- a/arch/cris/arch-v10/drivers/Kconfig
+++ /dev/null
@@ -1,561 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V10
-
-config ETRAX_ETHERNET
- bool "Ethernet support"
- depends on ETRAX_ARCH_V10 && NETDEVICES
- select MII
- help
- This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
- controller.
-
-config ETRAX_SERIAL
- bool "Serial-port support"
- depends on ETRAX_ARCH_V10
- help
- Enables the ETRAX 100 serial driver for ser0 (ttyS0)
- You probably want this enabled.
-
-config ETRAX_SERIAL_FAST_TIMER
- bool "Use fast timers for serial DMA flush (experimental)"
- depends on ETRAX_SERIAL
- help
- Select this to have the serial DMAs flushed at a higher rate than
- normally, possible by using the fast timer API, the timeout is
- approx. 4 character times.
- If unsure, say N.
-
-config ETRAX_SERIAL_FLUSH_DMA_FAST
- bool "Fast serial port DMA flush"
- depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER
- help
- Select this to have the serial DMAs flushed at a higher rate than
- normally possible through a fast timer interrupt (currently at
- 15360 Hz).
- If unsure, say N.
-
-config ETRAX_SERIAL_RX_TIMEOUT_TICKS
- int "Receive flush timeout (ticks) "
- depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER && !ETRAX_SERIAL_FLUSH_DMA_FAST
- default "5"
- help
- Number of timer ticks between flush of receive fifo (1 tick = 10ms).
- Try 0-3 for low latency applications. Approx 5 for high load
- applications (e.g. PPP). Maybe this should be more adaptive some
- day...
-
-config ETRAX_SERIAL_PORT0
- bool "Serial port 0 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser0 (ttyS0)
- Normally you want this on, unless you use external DMA 1 that uses
- the same DMA channels.
-
-choice
- prompt "Ser0 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER0_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
-
-config ETRAX_SER0_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
- help
- Enables the status and control signals DTR, RI, DSR and CD on PB for
- ser0.
-
-config ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER0_DTR_ON_PA_BIT
- int "Ser0 DTR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_RI_ON_PA_BIT
- int "Ser0 RI on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_DSR_ON_PA_BIT
- int "Ser0 DSR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_CD_ON_PA_BIT
- int "Ser0 CD on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_DTR_ON_PB_BIT
- int "Ser0 DTR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DTR signal for serial
- port 0.
-
-config ETRAX_SER0_RI_ON_PB_BIT
- int "Ser0 RI on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the RI signal for serial
- port 0.
-
-config ETRAX_SER0_DSR_ON_PB_BIT
- int "Ser0 DSR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DSR signal for serial
- port 0.
-
-config ETRAX_SER0_CD_ON_PB_BIT
- int "Ser0 CD on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the CD signal for serial
- port 0.
-
-config ETRAX_SERIAL_PORT1
- bool "Serial port 1 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser1 (ttyS1).
-
-choice
- prompt "Ser1 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER1_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
-
-config ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
- help
- Enables the status and control signals DTR, RI, DSR and CD on PB for
- ser1.
-
-config ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER1_DTR_ON_PA_BIT
- int "Ser1 DTR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_RI_ON_PA_BIT
- int "Ser1 RI on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_DSR_ON_PA_BIT
- int "Ser1 DSR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_CD_ON_PA_BIT
- int "Ser1 CD on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_DTR_ON_PB_BIT
- int "Ser1 DTR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DTR signal for serial
- port 1.
-
-config ETRAX_SER1_RI_ON_PB_BIT
- int "Ser1 RI on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the RI signal for serial
- port 1.
-
-config ETRAX_SER1_DSR_ON_PB_BIT
- int "Ser1 DSR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DSR signal for serial
- port 1.
-
-config ETRAX_SER1_CD_ON_PB_BIT
- int "Ser1 CD on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the CD signal for serial
- port 1.
-
-comment "Make sure you do not have the same PB bits more than once!"
- depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
-
-config ETRAX_SERIAL_PORT2
- bool "Serial port 2 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser2 (ttyS2).
-
-choice
- prompt "Ser2 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER2_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
- help
- Enables the status and control signals DTR, RI, DSR and CD on PA for
- ser2.
-
-config ETRAX_SER2_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
-
-config ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER2_DTR_ON_PA_BIT
- int "Ser2 DTR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the DTR signal for serial
- port 2.
-
-config ETRAX_SER2_RI_ON_PA_BIT
- int "Ser2 RI on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the RI signal for serial
- port 2.
-
-config ETRAX_SER2_DSR_ON_PA_BIT
- int "Ser2 DSR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the DTR signal for serial
- port 2.
-
-config ETRAX_SER2_CD_ON_PA_BIT
- int "Ser2 CD on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the CD signal for serial
- port 2.
-
-config ETRAX_SER2_DTR_ON_PB_BIT
- int "Ser2 DTR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER2_RI_ON_PB_BIT
- int "Ser2 RI on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER2_DSR_ON_PB_BIT
- int "Ser2 DSR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER2_CD_ON_PB_BIT
- int "Ser2 CD on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SERIAL_PORT3
- bool "Serial port 3 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser3 (ttyS3).
-
-choice
- prompt "Ser3 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER3_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
-
-config ETRAX_SER3_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
-
-config ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER3_DTR_ON_PA_BIT
- int "Ser3 DTR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_RI_ON_PA_BIT
- int "Ser3 RI on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_DSR_ON_PA_BIT
- int "Ser3 DSR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_CD_ON_PA_BIT
- int "Ser3 CD on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_DTR_ON_PB_BIT
- int "Ser3 DTR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_RI_ON_PB_BIT
- int "Ser3 RI on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_DSR_ON_PB_BIT
- int "Ser3 DSR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_CD_ON_PB_BIT
- int "Ser3 CD on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_RS485
- bool "RS-485 support"
- depends on ETRAX_SERIAL
- help
- Enables support for RS-485 serial communication. For a primer on
- RS-485, see <http://en.wikipedia.org/wiki/Rs485>
-
-config ETRAX_RS485_ON_PA
- bool "RS-485 mode on PA"
- depends on ETRAX_RS485
- help
- Control Driver Output Enable on RS485 transceiver using a pin on PA
- port:
- Axis 2400/2401 uses PA 3.
-
-config ETRAX_RS485_ON_PA_BIT
- int "RS-485 mode on PA bit"
- depends on ETRAX_RS485_ON_PA
- default "3"
- help
- Control Driver Output Enable on RS485 transceiver using a this bit
- on PA port.
-
-config ETRAX_RS485_DISABLE_RECEIVER
- bool "Disable serial receiver"
- depends on ETRAX_RS485
- help
- It's necessary to disable the serial receiver to avoid serial
- loopback. Not all products are able to do this in software only.
- Axis 2400/2401 must disable receiver.
-
-config ETRAX_USB_HOST
- bool "USB host"
- select USB
- help
- This option enables the host functionality of the ETRAX 100LX
- built-in USB controller. In host mode the controller is designed
- for CTRL and BULK traffic only, INTR traffic may work as well
- however (depending on the requirements of timeliness).
-
-config ETRAX_PTABLE_SECTOR
- int "Byte-offset of partition table sector"
- depends on ETRAX_AXISFLASHMAP
- default "65536"
- help
- Byte-offset of the partition table in the first flash chip.
- The default value is 64kB and should not be changed unless
- you know exactly what you are doing. The only valid reason
- for changing this is when the flash block size is bigger
- than 64kB (e.g. when using two parallel 16 bit flashes).
-
-config ETRAX_I2C
- bool "I2C support"
- depends on ETRAX_ARCH_V10
- help
- Enables an I2C driver on ETRAX100.
- EXAMPLE usage:
- i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
- ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
- i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
- val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
-
-# this is true for most products since PB-I2C seems to be somewhat
-# flawed..
-config ETRAX_I2C_USES_PB_NOT_PB_I2C
- bool "I2C uses PB not PB-I2C"
- depends on ETRAX_I2C
- help
- Select whether to use the special I2C mode in the PB I/O register or
- not. This option needs to be selected in order to use some drivers
- that access the I2C I/O pins directly instead of going through the
- I2C driver, like the DS1302 realtime-clock driver. If you are
- uncertain, choose Y here.
-
-config ETRAX_I2C_DATA_PORT
- int "I2C SDA bit number"
- depends on ETRAX_I2C_USES_PB_NOT_PB_I2C
- default "0"
- help
- Selects the pin on Port B where the data pin is connected
-
-config ETRAX_I2C_CLK_PORT
- int "I2C SCL bit number"
- depends on ETRAX_I2C_USES_PB_NOT_PB_I2C
- default "1"
- help
- Select the pin on Port B where the clock pin is connected
-
-config ETRAX_I2C_EEPROM
- bool "I2C EEPROM (non-volatile RAM) support"
- depends on ETRAX_I2C
- help
- Enables I2C EEPROM (non-volatile RAM) on PB0 and PB1 using the I2C
- driver. Select size option: Probed, 2k, 8k, 16k.
- (Probing works for 2k and 8k but not that well for 16k)
-
-choice
- prompt "EEPROM size"
- depends on ETRAX_I2C_EEPROM
- default ETRAX_I2C_EEPROM_PROBE
-
-config ETRAX_I2C_EEPROM_PROBE
- bool "Probed"
- help
- Specifies size or auto probe of the EEPROM size.
- Options: Probed, 2k, 8k, 16k.
- (Probing works for 2k and 8k but not that well for 16k)
-
-config ETRAX_I2C_EEPROM_2KB
- bool "2kB"
- help
- Use a 2kB EEPROM.
-
-config ETRAX_I2C_EEPROM_8KB
- bool "8kB"
- help
- Use a 8kB EEPROM.
-
-config ETRAX_I2C_EEPROM_16KB
- bool "16kB"
- help
- Use a 16kB EEPROM.
-
-endchoice
-
-config ETRAX_GPIO
- bool "GPIO support"
- depends on ETRAX_ARCH_V10
- ---help---
- Enables the ETRAX general port device (major 120, minors 0 and 1).
- You can use this driver to access the general port bits. It supports
- these ioctl's:
- #include <linux/etraxgpio.h>
- fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
- ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
- ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
- val = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READBITS), NULL);
- Remember that you need to setup the port directions appropriately in
- the General configuration.
-
-config ETRAX_PA_CHANGEABLE_DIR
- hex "PA user changeable dir mask"
- depends on ETRAX_GPIO
- default "00"
- help
- This is a bitmask with information of what bits in PA that a user
- can change direction on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-config ETRAX_PA_CHANGEABLE_BITS
- hex "PA user changeable bits mask"
- depends on ETRAX_GPIO
- default "FF"
- help
- This is a bitmask with information of what bits in PA that a user
- can change the value on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-config ETRAX_PB_CHANGEABLE_DIR
- hex "PB user changeable dir mask"
- depends on ETRAX_GPIO
- default "00"
- help
- This is a bitmask with information of what bits in PB that a user
- can change direction on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-config ETRAX_PB_CHANGEABLE_BITS
- hex "PB user changeable bits mask"
- depends on ETRAX_GPIO
- default "FF"
- help
- This is a bitmask with information of what bits in PB that a user
- can change the value on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-endif
diff --git a/arch/cris/arch-v10/drivers/Makefile b/arch/cris/arch-v10/drivers/Makefile
deleted file mode 100644
index d5549dca81bf..000000000000
--- a/arch/cris/arch-v10/drivers/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
-obj-$(CONFIG_ETRAX_I2C) += i2c.o
-obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o
-obj-$(CONFIG_ETRAX_GPIO) += gpio.o
-obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
-
diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c
deleted file mode 100644
index 28292da49664..000000000000
--- a/arch/cris/arch-v10/drivers/axisflashmap.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * Physical mapping layer for MTD using the Axis partitiontable format
- *
- * Copyright (c) 2001, 2002 Axis Communications AB
- *
- * This file is under the GPL.
- *
- * First partition is always sector 0 regardless of if we find a partitiontable
- * or not. In the start of the next sector, there can be a partitiontable that
- * tells us what other partitions to define. If there isn't, we use a default
- * partition split defined below.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-
-#include <linux/mtd/concat.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/mtdram.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/axisflashmap.h>
-#include <asm/mmu.h>
-#include <arch/sv_addr_ag.h>
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define FLASH_UNCACHED_ADDR KSEG_8
-#define FLASH_CACHED_ADDR KSEG_5
-#else
-#define FLASH_UNCACHED_ADDR KSEG_E
-#define FLASH_CACHED_ADDR KSEG_F
-#endif
-
-#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
-#define flash_data __u8
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
-#define flash_data __u16
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
-#define flash_data __u32
-#endif
-
-/* From head.S */
-extern unsigned long romfs_start, romfs_length, romfs_in_flash;
-
-/* The master mtd for the entire flash. */
-struct mtd_info* axisflash_mtd = NULL;
-
-/* Map driver functions. */
-
-static map_word flash_read(struct map_info *map, unsigned long ofs)
-{
- map_word tmp;
- tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs);
- return tmp;
-}
-
-static void flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- memcpy(to, (void *)(map->map_priv_1 + from), len);
-}
-
-static void flash_write(struct map_info *map, map_word d, unsigned long adr)
-{
- *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0];
-}
-
-/*
- * The map for chip select e0.
- *
- * We run into tricky coherence situations if we mix cached with uncached
- * accesses to we only use the uncached version here.
- *
- * The size field is the total size where the flash chips may be mapped on the
- * chip select. MTD probes should find all devices there and it does not matter
- * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD
- * probes will ignore them.
- *
- * The start address in map_priv_1 is in virtual memory so we cannot use
- * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start
- * address of cse0.
- */
-static struct map_info map_cse0 = {
- .name = "cse0",
- .size = MEM_CSE0_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR
-};
-
-/*
- * The map for chip select e1.
- *
- * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong
- * address, but there isn't.
- */
-static struct map_info map_cse1 = {
- .name = "cse1",
- .size = MEM_CSE1_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
-};
-
-/* If no partition-table was found, we use this default-set. */
-#define MAX_PARTITIONS 7
-#define NUM_DEFAULT_PARTITIONS 3
-
-/*
- * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the
- * size of one flash block and "filesystem"-partition needs 5 blocks to be able
- * to use JFFS.
- */
-static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
- {
- .name = "boot firmware",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "kernel",
- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR),
- .offset = CONFIG_ETRAX_PTABLE_SECTOR
- },
- {
- .name = "filesystem",
- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR)
- }
-};
-
-/* Initialize the ones normally used. */
-static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
- {
- .name = "part0",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "part1",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part2",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part3",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part4",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part5",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part6",
- .size = 0,
- .offset = 0
- },
-};
-
-/*
- * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
- * chips in that order (because the amd_flash-driver is faster).
- */
-static struct mtd_info *probe_cs(struct map_info *map_cs)
-{
- struct mtd_info *mtd_cs = NULL;
-
- printk(KERN_INFO
- "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n",
- map_cs->name, map_cs->size, map_cs->map_priv_1);
-
-#ifdef CONFIG_MTD_CFI
- mtd_cs = do_map_probe("cfi_probe", map_cs);
-#endif
-#ifdef CONFIG_MTD_JEDECPROBE
- if (!mtd_cs)
- mtd_cs = do_map_probe("jedec_probe", map_cs);
-#endif
-
- return mtd_cs;
-}
-
-/*
- * Probe each chip select individually for flash chips. If there are chips on
- * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
- * so that MTD partitions can cross chip boundaries.
- *
- * The only known restriction to how you can mount your chips is that each
- * chip select must hold similar flash chips. But you need external hardware
- * to do that anyway and you can put totally different chips on cse0 and cse1
- * so it isn't really much of a restriction.
- */
-static struct mtd_info *flash_probe(void)
-{
- struct mtd_info *mtd_cse0;
- struct mtd_info *mtd_cse1;
- struct mtd_info *mtd_cse;
-
- mtd_cse0 = probe_cs(&map_cse0);
- mtd_cse1 = probe_cs(&map_cse1);
-
- if (!mtd_cse0 && !mtd_cse1) {
- /* No chip found. */
- return NULL;
- }
-
- if (mtd_cse0 && mtd_cse1) {
- struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 };
-
- /* Since the concatenation layer adds a small overhead we
- * could try to figure out if the chips in cse0 and cse1 are
- * identical and reprobe the whole cse0+cse1 window. But since
- * flash chips are slow, the overhead is relatively small.
- * So we use the MTD concatenation layer instead of further
- * complicating the probing procedure.
- */
- mtd_cse = mtd_concat_create(mtds, ARRAY_SIZE(mtds),
- "cse0+cse1");
- if (!mtd_cse) {
- printk(KERN_ERR "%s and %s: Concatenation failed!\n",
- map_cse0.name, map_cse1.name);
-
- /* The best we can do now is to only use what we found
- * at cse0.
- */
- mtd_cse = mtd_cse0;
- map_destroy(mtd_cse1);
- }
- } else {
- mtd_cse = mtd_cse0? mtd_cse0 : mtd_cse1;
- }
-
- return mtd_cse;
-}
-
-/*
- * Probe the flash chip(s) and, if it succeeds, read the partition-table
- * and register the partitions with MTD.
- */
-static int __init init_axis_flash(void)
-{
- struct mtd_info *mymtd;
- int err = 0;
- int pidx = 0;
- struct partitiontable_head *ptable_head = NULL;
- struct partitiontable_entry *ptable;
- int use_default_ptable = 1; /* Until proven otherwise. */
- const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n";
-
- if (!(mymtd = flash_probe())) {
- /* There's no reason to use this module if no flash chip can
- * be identified. Make sure that's understood.
- */
- printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
- } else {
- printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n",
- mymtd->name, mymtd->size);
- axisflash_mtd = mymtd;
- }
-
- if (mymtd) {
- mymtd->owner = THIS_MODULE;
- ptable_head = (struct partitiontable_head *)(FLASH_CACHED_ADDR +
- CONFIG_ETRAX_PTABLE_SECTOR +
- PARTITION_TABLE_OFFSET);
- }
- pidx++; /* First partition is always set to the default. */
-
- if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
- && (ptable_head->size <
- (MAX_PARTITIONS * sizeof(struct partitiontable_entry) +
- PARTITIONTABLE_END_MARKER_SIZE))
- && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) +
- ptable_head->size -
- PARTITIONTABLE_END_MARKER_SIZE)
- == PARTITIONTABLE_END_MARKER)) {
- /* Looks like a start, sane length and end of a
- * partition table, lets check csum etc.
- */
- int ptable_ok = 0;
- struct partitiontable_entry *max_addr =
- (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head) +
- ptable_head->size);
- unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
- unsigned char *p;
- unsigned long csum = 0;
-
- ptable = (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head));
-
- /* Lets be PARANOID, and check the checksum. */
- p = (unsigned char*) ptable;
-
- while (p <= (unsigned char*)max_addr) {
- csum += *p++;
- csum += *p++;
- csum += *p++;
- csum += *p++;
- }
- ptable_ok = (csum == ptable_head->checksum);
-
- /* Read the entries and use/show the info. */
- printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n",
- (ptable_ok ? " valid" : "n invalid"), ptable_head,
- max_addr);
-
- /* We have found a working bootblock. Now read the
- * partition table. Scan the table. It ends when
- * there is 0xffffffff, that is, empty flash.
- */
- while (ptable_ok
- && ptable->offset != 0xffffffff
- && ptable < max_addr
- && pidx < MAX_PARTITIONS) {
-
- axis_partitions[pidx].offset = offset + ptable->offset;
- axis_partitions[pidx].size = ptable->size;
-
- printk(pmsg, pidx, axis_partitions[pidx].offset,
- axis_partitions[pidx].size);
- pidx++;
- ptable++;
- }
- use_default_ptable = !ptable_ok;
- }
-
- if (romfs_in_flash) {
- /* Add an overlapping device for the root partition (romfs). */
-
- axis_partitions[pidx].name = "romfs";
- axis_partitions[pidx].size = romfs_length;
- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
-
- printk(KERN_INFO
- " Adding readonly flash partition for romfs image:\n");
- printk(pmsg, pidx, axis_partitions[pidx].offset,
- axis_partitions[pidx].size);
- pidx++;
- }
-
- if (mymtd) {
- if (use_default_ptable) {
- printk(KERN_INFO " Using default partition table.\n");
- err = mtd_device_register(mymtd,
- axis_default_partitions,
- NUM_DEFAULT_PARTITIONS);
- } else {
- err = mtd_device_register(mymtd, axis_partitions,
- pidx);
- }
-
- if (err)
- panic("axisflashmap could not add MTD partitions!\n");
- }
-
- if (!romfs_in_flash) {
- /* Create an RAM device for the root partition (romfs). */
-
-#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0)
- /* No use trying to boot this kernel from RAM. Panic! */
- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
- "device due to kernel (mis)configuration!\n");
- panic("This kernel cannot boot from RAM!\n");
-#else
- struct mtd_info *mtd_ram;
-
- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
- if (!mtd_ram)
- panic("axisflashmap couldn't allocate memory for "
- "mtd_info!\n");
-
- printk(KERN_INFO " Adding RAM partition for romfs image:\n");
- printk(pmsg, pidx, (unsigned)romfs_start,
- (unsigned)romfs_length);
-
- err = mtdram_init_device(mtd_ram,
- (void *)romfs_start,
- romfs_length,
- "romfs");
- if (err)
- panic("axisflashmap could not initialize MTD RAM "
- "device!\n");
-#endif
- }
- return err;
-}
-
-/* This adds the above to the kernels init-call chain. */
-module_init(init_axis_flash);
-
-EXPORT_SYMBOL(axisflash_mtd);
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
deleted file mode 100644
index 2d312c8a4dd5..000000000000
--- a/arch/cris/arch-v10/drivers/eeprom.c
+++ /dev/null
@@ -1,852 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*!*****************************************************************************
-*!
-*! Implements an interface for i2c compatible eeproms to run under Linux.
-*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by
-*! Johan.Adolfsson@axis.com
-*!
-*! Probing results:
-*! 8k or not is detected (the assumes 2k or 16k)
-*! 2k or 16k detected using test reads and writes.
-*!
-*!------------------------------------------------------------------------
-*! HISTORY
-*!
-*! DATE NAME CHANGES
-*! ---- ---- -------
-*! Aug 28 1999 Edgar Iglesias Initial Version
-*! Aug 31 1999 Edgar Iglesias Allow simultaneous users.
-*! Sep 03 1999 Edgar Iglesias Updated probe.
-*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted
-*! in the spin-lock.
-*!
-*! (c) 1999 Axis Communications AB, Lund, Sweden
-*!*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/wait.h>
-#include <linux/uaccess.h>
-#include "i2c.h"
-
-#define D(x)
-
-/* If we should use adaptive timing or not: */
-/* #define EEPROM_ADAPTIVE_TIMING */
-
-#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */
-#define EEPROM_MINOR_NR 0
-
-/* Empirical sane initial value of the delay, the value will be adapted to
- * what the chip needs when using EEPROM_ADAPTIVE_TIMING.
- */
-#define INITIAL_WRITEDELAY_US 4000
-#define MAX_WRITEDELAY_US 10000 /* 10 ms according to spec for 2KB EEPROM */
-
-/* This one defines how many times to try when eeprom fails. */
-#define EEPROM_RETRIES 10
-
-#define EEPROM_2KB (2 * 1024)
-/*#define EEPROM_4KB (4 * 1024)*/ /* Exists but not used in Axis products */
-#define EEPROM_8KB (8 * 1024 - 1 ) /* Last byte has write protection bit */
-#define EEPROM_16KB (16 * 1024)
-
-#define i2c_delay(x) udelay(x)
-
-/*
- * This structure describes the attached eeprom chip.
- * The values are probed for.
- */
-
-struct eeprom_type
-{
- unsigned long size;
- unsigned long sequential_write_pagesize;
- unsigned char select_cmd;
- unsigned long usec_delay_writecycles; /* Min time between write cycles
- (up to 10ms for some models) */
- unsigned long usec_delay_step; /* For adaptive algorithm */
- int adapt_state; /* 1 = To high , 0 = Even, -1 = To low */
-
- /* this one is to keep the read/write operations atomic */
- struct mutex lock;
- int retry_cnt_addr; /* Used to keep track of number of retries for
- adaptive timing adjustments */
- int retry_cnt_read;
-};
-
-static int eeprom_open(struct inode * inode, struct file * file);
-static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig);
-static ssize_t eeprom_read(struct file * file, char * buf, size_t count,
- loff_t *off);
-static ssize_t eeprom_write(struct file * file, const char * buf, size_t count,
- loff_t *off);
-static int eeprom_close(struct inode * inode, struct file * file);
-
-static int eeprom_address(unsigned long addr);
-static int read_from_eeprom(char * buf, int count);
-static int eeprom_write_buf(loff_t addr, const char * buf, int count);
-static int eeprom_read_buf(loff_t addr, char * buf, int count);
-
-static void eeprom_disable_write_protect(void);
-
-
-static const char eeprom_name[] = "eeprom";
-
-/* chip description */
-static struct eeprom_type eeprom;
-
-/* This is the exported file-operations structure for this device. */
-const struct file_operations eeprom_fops =
-{
- .llseek = eeprom_lseek,
- .read = eeprom_read,
- .write = eeprom_write,
- .open = eeprom_open,
- .release = eeprom_close
-};
-
-/* eeprom init call. Probes for different eeprom models. */
-
-int __init eeprom_init(void)
-{
- mutex_init(&eeprom.lock);
-
-#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE
-#define EETEXT "Found"
-#else
-#define EETEXT "Assuming"
-#endif
- if (register_chrdev(EEPROM_MAJOR_NR, eeprom_name, &eeprom_fops))
- {
- printk(KERN_INFO "%s: unable to get major %d for eeprom device\n",
- eeprom_name, EEPROM_MAJOR_NR);
- return -1;
- }
-
- printk("EEPROM char device v0.3, (c) 2000 Axis Communications AB\n");
-
- /*
- * Note: Most of this probing method was taken from the printserver (5470e)
- * codebase. It did not contain a way of finding the 16kB chips
- * (M24128 or variants). The method used here might not work
- * for all models. If you encounter problems the easiest way
- * is probably to define your model within #ifdef's, and hard-
- * code it.
- */
-
- eeprom.size = 0;
- eeprom.usec_delay_writecycles = INITIAL_WRITEDELAY_US;
- eeprom.usec_delay_step = 128;
- eeprom.adapt_state = 0;
-
-#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE
- i2c_start();
- i2c_outbyte(0x80);
- if(!i2c_getack())
- {
- /* It's not 8k.. */
- int success = 0;
- unsigned char buf_2k_start[16];
-
- /* Im not sure this will work... :) */
- /* assume 2kB, if failure go for 16kB */
- /* Test with 16kB settings.. */
- /* If it's a 2kB EEPROM and we address it outside it's range
- * it will mirror the address space:
- * 1. We read two locations (that are mirrored),
- * if the content differs * it's a 16kB EEPROM.
- * 2. if it doesn't differ - write different value to one of the locations,
- * check the other - if content still is the same it's a 2k EEPROM,
- * restore original data.
- */
-#define LOC1 8
-#define LOC2 (0x1fb) /*1fb, 3ed, 5df, 7d1 */
-
- /* 2k settings */
- i2c_stop();
- eeprom.size = EEPROM_2KB;
- eeprom.select_cmd = 0xA0;
- eeprom.sequential_write_pagesize = 16;
- if( eeprom_read_buf( 0, buf_2k_start, 16 ) == 16 )
- {
- D(printk("2k start: '%16.16s'\n", buf_2k_start));
- }
- else
- {
- printk(KERN_INFO "%s: Failed to read in 2k mode!\n", eeprom_name);
- }
-
- /* 16k settings */
- eeprom.size = EEPROM_16KB;
- eeprom.select_cmd = 0xA0;
- eeprom.sequential_write_pagesize = 64;
-
- {
- unsigned char loc1[4], loc2[4], tmp[4];
- if( eeprom_read_buf(LOC2, loc2, 4) == 4)
- {
- if( eeprom_read_buf(LOC1, loc1, 4) == 4)
- {
- D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n",
- LOC1, loc1, LOC2, loc2));
-#if 0
- if (memcmp(loc1, loc2, 4) != 0 )
- {
- /* It's 16k */
- printk(KERN_INFO "%s: 16k detected in step 1\n", eeprom_name);
- eeprom.size = EEPROM_16KB;
- success = 1;
- }
- else
-#endif
- {
- /* Do step 2 check */
- /* Invert value */
- loc1[0] = ~loc1[0];
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- /* If 2k EEPROM this write will actually write 10 bytes
- * from pos 0
- */
- D(printk("1 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n",
- LOC1, loc1, LOC2, loc2));
- if( eeprom_read_buf(LOC1, tmp, 4) == 4)
- {
- D(printk("2 loc1: (%i) '%4.4s' tmp '%4.4s'\n",
- LOC1, loc1, tmp));
- if (memcmp(loc1, tmp, 4) != 0 )
- {
- printk(KERN_INFO "%s: read and write differs! Not 16kB\n",
- eeprom_name);
- loc1[0] = ~loc1[0];
-
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- success = 1;
- }
- else
- {
- printk(KERN_INFO "%s: Restore 2k failed during probe,"
- " EEPROM might be corrupt!\n", eeprom_name);
-
- }
- i2c_stop();
- /* Go to 2k mode and write original data */
- eeprom.size = EEPROM_2KB;
- eeprom.select_cmd = 0xA0;
- eeprom.sequential_write_pagesize = 16;
- if( eeprom_write_buf(0, buf_2k_start, 16) == 16)
- {
- }
- else
- {
- printk(KERN_INFO "%s: Failed to write back 2k start!\n",
- eeprom_name);
- }
-
- eeprom.size = EEPROM_2KB;
- }
- }
-
- if(!success)
- {
- if( eeprom_read_buf(LOC2, loc2, 1) == 1)
- {
- D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n",
- LOC1, loc1, LOC2, loc2));
- if (memcmp(loc1, loc2, 4) == 0 )
- {
- /* Data the same, must be mirrored -> 2k */
- /* Restore data */
- printk(KERN_INFO "%s: 2k detected in step 2\n", eeprom_name);
- loc1[0] = ~loc1[0];
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- success = 1;
- }
- else
- {
- printk(KERN_INFO "%s: Restore 2k failed during probe,"
- " EEPROM might be corrupt!\n", eeprom_name);
-
- }
-
- eeprom.size = EEPROM_2KB;
- }
- else
- {
- printk(KERN_INFO "%s: 16k detected in step 2\n",
- eeprom_name);
- loc1[0] = ~loc1[0];
- /* Data differs, assume 16k */
- /* Restore data */
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- success = 1;
- }
- else
- {
- printk(KERN_INFO "%s: Restore 16k failed during probe,"
- " EEPROM might be corrupt!\n", eeprom_name);
- }
-
- eeprom.size = EEPROM_16KB;
- }
- }
- }
- }
- } /* read LOC1 */
- } /* address LOC1 */
- if (!success)
- {
- printk(KERN_INFO "%s: Probing failed!, using 2KB!\n", eeprom_name);
- eeprom.size = EEPROM_2KB;
- }
- } /* read */
- }
- }
- else
- {
- i2c_outbyte(0x00);
- if(!i2c_getack())
- {
- /* No 8k */
- eeprom.size = EEPROM_2KB;
- }
- else
- {
- i2c_start();
- i2c_outbyte(0x81);
- if (!i2c_getack())
- {
- eeprom.size = EEPROM_2KB;
- }
- else
- {
- /* It's a 8kB */
- i2c_inbyte();
- eeprom.size = EEPROM_8KB;
- }
- }
- }
- i2c_stop();
-#elif defined(CONFIG_ETRAX_I2C_EEPROM_16KB)
- eeprom.size = EEPROM_16KB;
-#elif defined(CONFIG_ETRAX_I2C_EEPROM_8KB)
- eeprom.size = EEPROM_8KB;
-#elif defined(CONFIG_ETRAX_I2C_EEPROM_2KB)
- eeprom.size = EEPROM_2KB;
-#endif
-
- switch(eeprom.size)
- {
- case (EEPROM_2KB):
- printk("%s: " EETEXT " i2c compatible 2kB eeprom.\n", eeprom_name);
- eeprom.sequential_write_pagesize = 16;
- eeprom.select_cmd = 0xA0;
- break;
- case (EEPROM_8KB):
- printk("%s: " EETEXT " i2c compatible 8kB eeprom.\n", eeprom_name);
- eeprom.sequential_write_pagesize = 16;
- eeprom.select_cmd = 0x80;
- break;
- case (EEPROM_16KB):
- printk("%s: " EETEXT " i2c compatible 16kB eeprom.\n", eeprom_name);
- eeprom.sequential_write_pagesize = 64;
- eeprom.select_cmd = 0xA0;
- break;
- default:
- eeprom.size = 0;
- printk("%s: Did not find a supported eeprom\n", eeprom_name);
- break;
- }
-
-
-
- eeprom_disable_write_protect();
-
- return 0;
-}
-
-/* Opens the device. */
-static int eeprom_open(struct inode * inode, struct file * file)
-{
- if(iminor(inode) != EEPROM_MINOR_NR)
- return -ENXIO;
- if(imajor(inode) != EEPROM_MAJOR_NR)
- return -ENXIO;
-
- if( eeprom.size > 0 )
- {
- /* OK */
- return 0;
- }
-
- /* No EEprom found */
- return -EFAULT;
-}
-
-/* Changes the current file position. */
-
-static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig)
-{
-/*
- * orig 0: position from beginning of eeprom
- * orig 1: relative from current position
- * orig 2: position from last eeprom address
- */
-
- switch (orig)
- {
- case 0:
- file->f_pos = offset;
- break;
- case 1:
- file->f_pos += offset;
- break;
- case 2:
- file->f_pos = eeprom.size - offset;
- break;
- default:
- return -EINVAL;
- }
-
- /* truncate position */
- if (file->f_pos < 0)
- {
- file->f_pos = 0;
- return(-EOVERFLOW);
- }
-
- if (file->f_pos >= eeprom.size)
- {
- file->f_pos = eeprom.size - 1;
- return(-EOVERFLOW);
- }
-
- return ( file->f_pos );
-}
-
-/* Reads data from eeprom. */
-
-static int eeprom_read_buf(loff_t addr, char * buf, int count)
-{
- return eeprom_read(NULL, buf, count, &addr);
-}
-
-
-
-/* Reads data from eeprom. */
-
-static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t *off)
-{
- int read=0;
- unsigned long p = *off;
-
- unsigned char page;
-
- if(p >= eeprom.size) /* Address i 0 - (size-1) */
- {
- return -EFAULT;
- }
-
- if (mutex_lock_interruptible(&eeprom.lock))
- return -EINTR;
-
- page = (unsigned char) (p >> 8);
-
- if(!eeprom_address(p))
- {
- printk(KERN_INFO "%s: Read failed to address the eeprom: "
- "0x%08X (%i) page: %i\n", eeprom_name, (int)p, (int)p, page);
- i2c_stop();
-
- /* don't forget to wake them up */
- mutex_unlock(&eeprom.lock);
- return -EFAULT;
- }
-
- if( (p + count) > eeprom.size)
- {
- /* truncate count */
- count = eeprom.size - p;
- }
-
- /* stop dummy write op and initiate the read op */
- i2c_start();
-
- /* special case for small eeproms */
- if(eeprom.size < EEPROM_16KB)
- {
- i2c_outbyte( eeprom.select_cmd | 1 | (page << 1) );
- }
-
- /* go on with the actual read */
- read = read_from_eeprom( buf, count);
-
- if(read > 0)
- {
- *off += read;
- }
-
- mutex_unlock(&eeprom.lock);
- return read;
-}
-
-/* Writes data to eeprom. */
-
-static int eeprom_write_buf(loff_t addr, const char * buf, int count)
-{
- return eeprom_write(NULL, buf, count, &addr);
-}
-
-
-/* Writes data to eeprom. */
-
-static ssize_t eeprom_write(struct file * file, const char * buf, size_t count,
- loff_t *off)
-{
- int i, written, restart=1;
- unsigned long p;
-
- if (!access_ok(VERIFY_READ, buf, count))
- {
- return -EFAULT;
- }
-
- /* bail out if we get interrupted */
- if (mutex_lock_interruptible(&eeprom.lock))
- return -EINTR;
- for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++)
- {
- restart = 0;
- written = 0;
- p = *off;
-
-
- while( (written < count) && (p < eeprom.size))
- {
- /* address the eeprom */
- if(!eeprom_address(p))
- {
- printk(KERN_INFO "%s: Write failed to address the eeprom: "
- "0x%08X (%i) \n", eeprom_name, (int)p, (int)p);
- i2c_stop();
-
- /* don't forget to wake them up */
- mutex_unlock(&eeprom.lock);
- return -EFAULT;
- }
-#ifdef EEPROM_ADAPTIVE_TIMING
- /* Adaptive algorithm to adjust timing */
- if (eeprom.retry_cnt_addr > 0)
- {
- /* To Low now */
- D(printk(">D=%i d=%i\n",
- eeprom.usec_delay_writecycles, eeprom.usec_delay_step));
-
- if (eeprom.usec_delay_step < 4)
- {
- eeprom.usec_delay_step++;
- eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
- }
- else
- {
-
- if (eeprom.adapt_state > 0)
- {
- /* To Low before */
- eeprom.usec_delay_step *= 2;
- if (eeprom.usec_delay_step > 2)
- {
- eeprom.usec_delay_step--;
- }
- eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
- }
- else if (eeprom.adapt_state < 0)
- {
- /* To High before (toggle dir) */
- eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
- if (eeprom.usec_delay_step > 1)
- {
- eeprom.usec_delay_step /= 2;
- eeprom.usec_delay_step--;
- }
- }
- }
-
- eeprom.adapt_state = 1;
- }
- else
- {
- /* To High (or good) now */
- D(printk("<D=%i d=%i\n",
- eeprom.usec_delay_writecycles, eeprom.usec_delay_step));
-
- if (eeprom.adapt_state < 0)
- {
- /* To High before */
- if (eeprom.usec_delay_step > 1)
- {
- eeprom.usec_delay_step *= 2;
- eeprom.usec_delay_step--;
-
- if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step)
- {
- eeprom.usec_delay_writecycles -= eeprom.usec_delay_step;
- }
- }
- }
- else if (eeprom.adapt_state > 0)
- {
- /* To Low before (toggle dir) */
- if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step)
- {
- eeprom.usec_delay_writecycles -= eeprom.usec_delay_step;
- }
- if (eeprom.usec_delay_step > 1)
- {
- eeprom.usec_delay_step /= 2;
- eeprom.usec_delay_step--;
- }
-
- eeprom.adapt_state = -1;
- }
-
- if (eeprom.adapt_state > -100)
- {
- eeprom.adapt_state--;
- }
- else
- {
- /* Restart adaption */
- D(printk("#Restart\n"));
- eeprom.usec_delay_step++;
- }
- }
-#endif /* EEPROM_ADAPTIVE_TIMING */
- /* write until we hit a page boundary or count */
- do
- {
- i2c_outbyte(buf[written]);
- if(!i2c_getack())
- {
- restart=1;
- printk(KERN_INFO "%s: write error, retrying. %d\n", eeprom_name, i);
- i2c_stop();
- break;
- }
- written++;
- p++;
- } while( written < count && ( p % eeprom.sequential_write_pagesize ));
-
- /* end write cycle */
- i2c_stop();
- i2c_delay(eeprom.usec_delay_writecycles);
- } /* while */
- } /* for */
-
- mutex_unlock(&eeprom.lock);
- if (written == 0 && p >= eeprom.size){
- return -ENOSPC;
- }
- *off = p;
- return written;
-}
-
-/* Closes the device. */
-
-static int eeprom_close(struct inode * inode, struct file * file)
-{
- /* do nothing for now */
- return 0;
-}
-
-/* Sets the current address of the eeprom. */
-
-static int eeprom_address(unsigned long addr)
-{
- int i;
- unsigned char page, offset;
-
- page = (unsigned char) (addr >> 8);
- offset = (unsigned char) addr;
-
- for(i = 0; i < EEPROM_RETRIES; i++)
- {
- /* start a dummy write for addressing */
- i2c_start();
-
- if(eeprom.size == EEPROM_16KB)
- {
- i2c_outbyte( eeprom.select_cmd );
- i2c_getack();
- i2c_outbyte(page);
- }
- else
- {
- i2c_outbyte( eeprom.select_cmd | (page << 1) );
- }
- if(!i2c_getack())
- {
- /* retry */
- i2c_stop();
- /* Must have a delay here.. 500 works, >50, 100->works 5th time*/
- i2c_delay(MAX_WRITEDELAY_US / EEPROM_RETRIES * i);
- /* The chip needs up to 10 ms from write stop to next start */
-
- }
- else
- {
- i2c_outbyte(offset);
-
- if(!i2c_getack())
- {
- /* retry */
- i2c_stop();
- }
- else
- break;
- }
- }
-
-
- eeprom.retry_cnt_addr = i;
- D(printk("%i\n", eeprom.retry_cnt_addr));
- if(eeprom.retry_cnt_addr == EEPROM_RETRIES)
- {
- /* failed */
- return 0;
- }
- return 1;
-}
-
-/* Reads from current address. */
-
-static int read_from_eeprom(char * buf, int count)
-{
- int i, read=0;
-
- for(i = 0; i < EEPROM_RETRIES; i++)
- {
- if(eeprom.size == EEPROM_16KB)
- {
- i2c_outbyte( eeprom.select_cmd | 1 );
- }
-
- if(i2c_getack())
- {
- break;
- }
- }
-
- if(i == EEPROM_RETRIES)
- {
- printk(KERN_INFO "%s: failed to read from eeprom\n", eeprom_name);
- i2c_stop();
-
- return -EFAULT;
- }
-
- while( (read < count))
- {
- if (put_user(i2c_inbyte(), &buf[read++]))
- {
- i2c_stop();
-
- return -EFAULT;
- }
-
- /*
- * make sure we don't ack last byte or you will get very strange
- * results!
- */
- if(read < count)
- {
- i2c_sendack();
- }
- }
-
- /* stop the operation */
- i2c_stop();
-
- return read;
-}
-
-/* Disables write protection if applicable. */
-
-#define DBP_SAVE(x)
-#define ax_printf printk
-static void eeprom_disable_write_protect(void)
-{
- /* Disable write protect */
- if (eeprom.size == EEPROM_8KB)
- {
- /* Step 1 Set WEL = 1 (write 00000010 to address 1FFFh */
- i2c_start();
- i2c_outbyte(0xbe);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false\n"));
- }
- i2c_outbyte(0xFF);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 2\n"));
- }
- i2c_outbyte(0x02);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 3\n"));
- }
- i2c_stop();
-
- i2c_delay(1000);
-
- /* Step 2 Set RWEL = 1 (write 00000110 to address 1FFFh */
- i2c_start();
- i2c_outbyte(0xbe);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 55\n"));
- }
- i2c_outbyte(0xFF);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 52\n"));
- }
- i2c_outbyte(0x06);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 53\n"));
- }
- i2c_stop();
-
- /* Step 3 Set BP1, BP0, and/or WPEN bits (write 00000110 to address 1FFFh */
- i2c_start();
- i2c_outbyte(0xbe);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 56\n"));
- }
- i2c_outbyte(0xFF);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 57\n"));
- }
- i2c_outbyte(0x06);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 58\n"));
- }
- i2c_stop();
-
- /* Write protect disabled */
- }
-}
-device_initcall(eeprom_init);
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
deleted file mode 100644
index cd0e05d89d42..000000000000
--- a/arch/cris/arch-v10/drivers/gpio.c
+++ /dev/null
@@ -1,857 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Etrax general port I/O device
- *
- * Copyright (c) 1999-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (initial version)
- * Ola Knutsson (LED handling)
- * Johan Adolfsson (read/set directions, write, port G)
- */
-
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/ioport.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/poll.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-
-#include <asm/etraxgpio.h>
-#include <arch/svinto.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <arch/io_interface_mux.h>
-
-#define GPIO_MAJOR 120 /* experimental MAJOR number */
-
-#define D(x)
-
-#if 0
-static int dp_cnt;
-#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
-#else
-#define DP(x)
-#endif
-
-static char gpio_name[] = "etrax gpio";
-
-#if 0
-static wait_queue_head_t *gpio_wq;
-#endif
-
-static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
-static ssize_t gpio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *off);
-static int gpio_open(struct inode *inode, struct file *filp);
-static int gpio_release(struct inode *inode, struct file *filp);
-static __poll_t gpio_poll(struct file *filp, struct poll_table_struct *wait);
-
-/* private data per open() of this driver */
-
-struct gpio_private {
- struct gpio_private *next;
- /* These fields are for PA and PB only */
- volatile unsigned char *port, *shadow;
- volatile unsigned char *dir, *dir_shadow;
- unsigned char changeable_dir;
- unsigned char changeable_bits;
- unsigned char clk_mask;
- unsigned char data_mask;
- unsigned char write_msb;
- unsigned char pad1, pad2, pad3;
- /* These fields are generic */
- unsigned long highalarm, lowalarm;
- wait_queue_head_t alarm_wq;
- int minor;
-};
-
-/* linked list of alarms to check for */
-
-static struct gpio_private *alarmlist;
-
-static int gpio_some_alarms; /* Set if someone uses alarm */
-static unsigned long gpio_pa_irq_enabled_mask;
-
-static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
-
-/* Port A and B use 8 bit access, but Port G is 32 bit */
-#define NUM_PORTS (GPIO_MINOR_B+1)
-
-static volatile unsigned char *ports[NUM_PORTS] = {
- R_PORT_PA_DATA,
- R_PORT_PB_DATA,
-};
-static volatile unsigned char *shads[NUM_PORTS] = {
- &port_pa_data_shadow,
- &port_pb_data_shadow
-};
-
-/* What direction bits that are user changeable 1=changeable*/
-#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
-#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00
-#endif
-#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR
-#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00
-#endif
-
-#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS
-#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF
-#endif
-#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS
-#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF
-#endif
-
-
-static unsigned char changeable_dir[NUM_PORTS] = {
- CONFIG_ETRAX_PA_CHANGEABLE_DIR,
- CONFIG_ETRAX_PB_CHANGEABLE_DIR
-};
-static unsigned char changeable_bits[NUM_PORTS] = {
- CONFIG_ETRAX_PA_CHANGEABLE_BITS,
- CONFIG_ETRAX_PB_CHANGEABLE_BITS
-};
-
-static volatile unsigned char *dir[NUM_PORTS] = {
- R_PORT_PA_DIR,
- R_PORT_PB_DIR
-};
-
-static volatile unsigned char *dir_shadow[NUM_PORTS] = {
- &port_pa_dir_shadow,
- &port_pb_dir_shadow
-};
-
-/* All bits in port g that can change dir. */
-static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
-
-/* Port G is 32 bit, handle it special, some bits are both inputs
- and outputs at the same time, only some of the bits can change direction
- and some of them in groups of 8 bit. */
-static unsigned long changeable_dir_g;
-static unsigned long dir_g_in_bits;
-static unsigned long dir_g_out_bits;
-static unsigned long dir_g_shadow; /* 1=output */
-
-#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
-
-
-static __poll_t gpio_poll(struct file *file, poll_table *wait)
-{
- __poll_t mask = 0;
- struct gpio_private *priv = file->private_data;
- unsigned long data;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- poll_wait(file, &priv->alarm_wq, wait);
- if (priv->minor == GPIO_MINOR_A) {
- unsigned long tmp;
- data = *R_PORT_PA_DATA;
- /* PA has support for high level interrupt -
- * lets activate for those low and with highalarm set
- */
- tmp = ~data & priv->highalarm & 0xFF;
- tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
-
- gpio_pa_irq_enabled_mask |= tmp;
- *R_IRQ_MASK1_SET = tmp;
- } else if (priv->minor == GPIO_MINOR_B)
- data = *R_PORT_PB_DATA;
- else if (priv->minor == GPIO_MINOR_G)
- data = *R_PORT_G_DATA;
- else {
- mask = 0;
- goto out;
- }
-
- if ((data & priv->highalarm) ||
- (~data & priv->lowalarm)) {
- mask = EPOLLIN|EPOLLRDNORM;
- }
-
-out:
- spin_unlock_irqrestore(&gpio_lock, flags);
- DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
-
- return mask;
-}
-
-int etrax_gpio_wake_up_check(void)
-{
- struct gpio_private *priv;
- unsigned long data = 0;
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
- priv = alarmlist;
- while (priv) {
- if (USE_PORTS(priv))
- data = *priv->port;
- else if (priv->minor == GPIO_MINOR_G)
- data = *R_PORT_G_DATA;
-
- if ((data & priv->highalarm) ||
- (~data & priv->lowalarm)) {
- DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
- wake_up_interruptible(&priv->alarm_wq);
- ret = 1;
- }
- priv = priv->next;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- return ret;
-}
-
-static irqreturn_t
-gpio_poll_timer_interrupt(int irq, void *dev_id)
-{
- if (gpio_some_alarms) {
- etrax_gpio_wake_up_check();
- return IRQ_HANDLED;
- }
- return IRQ_NONE;
-}
-
-static irqreturn_t
-gpio_interrupt(int irq, void *dev_id)
-{
- unsigned long tmp;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- /* Find what PA interrupts are active */
- tmp = (*R_IRQ_READ1);
-
- /* Find those that we have enabled */
- tmp &= gpio_pa_irq_enabled_mask;
-
- /* Clear them.. */
- *R_IRQ_MASK1_CLR = tmp;
- gpio_pa_irq_enabled_mask &= ~tmp;
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- if (gpio_some_alarms)
- return IRQ_RETVAL(etrax_gpio_wake_up_check());
-
- return IRQ_NONE;
-}
-
-static void gpio_write_bit(struct gpio_private *priv,
- unsigned char data, int bit)
-{
- *priv->port = *priv->shadow &= ~(priv->clk_mask);
- if (data & 1 << bit)
- *priv->port = *priv->shadow |= priv->data_mask;
- else
- *priv->port = *priv->shadow &= ~(priv->data_mask);
-
- /* For FPGA: min 5.0ns (DCC) before CCLK high */
- *priv->port = *priv->shadow |= priv->clk_mask;
-}
-
-static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
-{
- int i;
-
- if (priv->write_msb)
- for (i = 7; i >= 0; i--)
- gpio_write_bit(priv, data, i);
- else
- for (i = 0; i <= 7; i++)
- gpio_write_bit(priv, data, i);
-}
-
-static ssize_t gpio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *off)
-{
- struct gpio_private *priv = file->private_data;
- unsigned long flags;
- ssize_t retval = count;
-
- if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
- return -EFAULT;
-
- if (!access_ok(VERIFY_READ, buf, count))
- return -EFAULT;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- /* It must have been configured using the IO_CFG_WRITE_MODE */
- /* Perhaps a better error code? */
- if (priv->clk_mask == 0 || priv->data_mask == 0) {
- retval = -EPERM;
- goto out;
- }
-
- D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
- "clk 0x%02X msb: %i\n",
- count, priv->data_mask, priv->clk_mask, priv->write_msb));
-
- while (count--)
- gpio_write_byte(priv, *buf++);
-
-out:
- spin_unlock_irqrestore(&gpio_lock, flags);
- return retval;
-}
-
-
-
-static int
-gpio_open(struct inode *inode, struct file *filp)
-{
- struct gpio_private *priv;
- int p = iminor(inode);
- unsigned long flags;
-
- if (p > GPIO_MINOR_LAST)
- return -EINVAL;
-
- priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
-
- if (!priv)
- return -ENOMEM;
-
- priv->minor = p;
-
- /* initialize the io/alarm struct */
-
- if (USE_PORTS(priv)) { /* A and B */
- priv->port = ports[p];
- priv->shadow = shads[p];
- priv->dir = dir[p];
- priv->dir_shadow = dir_shadow[p];
- priv->changeable_dir = changeable_dir[p];
- priv->changeable_bits = changeable_bits[p];
- } else {
- priv->port = NULL;
- priv->shadow = NULL;
- priv->dir = NULL;
- priv->dir_shadow = NULL;
- priv->changeable_dir = 0;
- priv->changeable_bits = 0;
- }
-
- priv->highalarm = 0;
- priv->lowalarm = 0;
- priv->clk_mask = 0;
- priv->data_mask = 0;
- init_waitqueue_head(&priv->alarm_wq);
-
- filp->private_data = priv;
-
- /* link it into our alarmlist */
- spin_lock_irqsave(&gpio_lock, flags);
- priv->next = alarmlist;
- alarmlist = priv;
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- return 0;
-}
-
-static int
-gpio_release(struct inode *inode, struct file *filp)
-{
- struct gpio_private *p;
- struct gpio_private *todel;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- p = alarmlist;
- todel = filp->private_data;
-
- /* unlink from alarmlist and free the private structure */
-
- if (p == todel) {
- alarmlist = todel->next;
- } else {
- while (p->next != todel)
- p = p->next;
- p->next = todel->next;
- }
-
- kfree(todel);
- /* Check if there are still any alarms set */
- p = alarmlist;
- while (p) {
- if (p->highalarm | p->lowalarm) {
- gpio_some_alarms = 1;
- goto out;
- }
- p = p->next;
- }
- gpio_some_alarms = 0;
-out:
- spin_unlock_irqrestore(&gpio_lock, flags);
- return 0;
-}
-
-/* Main device API. ioctl's to read/set/clear bits, as well as to
- * set alarms to wait for using a subsequent select().
- */
-inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
-{
- /* Set direction 0=unchanged 1=input,
- * return mask with 1=input */
- if (USE_PORTS(priv)) {
- *priv->dir = *priv->dir_shadow &=
- ~((unsigned char)arg & priv->changeable_dir);
- return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
- }
-
- if (priv->minor != GPIO_MINOR_G)
- return 0;
-
- /* We must fiddle with R_GEN_CONFIG to change dir */
- if (((arg & dir_g_in_bits) != arg) &&
- (arg & changeable_dir_g)) {
- arg &= changeable_dir_g;
- /* Clear bits in genconfig to set to input */
- if (arg & (1<<0)) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
- dir_g_in_bits |= (1<<0);
- dir_g_out_bits &= ~(1<<0);
- }
- if ((arg & 0x0000FF00) == 0x0000FF00) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
- dir_g_in_bits |= 0x0000FF00;
- dir_g_out_bits &= ~0x0000FF00;
- }
- if ((arg & 0x00FF0000) == 0x00FF0000) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
- dir_g_in_bits |= 0x00FF0000;
- dir_g_out_bits &= ~0x00FF0000;
- }
- if (arg & (1<<24)) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
- dir_g_in_bits |= (1<<24);
- dir_g_out_bits &= ~(1<<24);
- }
- D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
- "genconfig to 0x%08lX "
- "in_bits: 0x%08lX "
- "out_bits: 0x%08lX\n",
- (unsigned long)genconfig_shadow,
- dir_g_in_bits, dir_g_out_bits));
- *R_GEN_CONFIG = genconfig_shadow;
- /* Must be a >120 ns delay before writing this again */
-
- }
- return dir_g_in_bits;
-} /* setget_input */
-
-inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
-{
- if (USE_PORTS(priv)) {
- *priv->dir = *priv->dir_shadow |=
- ((unsigned char)arg & priv->changeable_dir);
- return *priv->dir_shadow;
- }
- if (priv->minor != GPIO_MINOR_G)
- return 0;
-
- /* We must fiddle with R_GEN_CONFIG to change dir */
- if (((arg & dir_g_out_bits) != arg) &&
- (arg & changeable_dir_g)) {
- /* Set bits in genconfig to set to output */
- if (arg & (1<<0)) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
- dir_g_out_bits |= (1<<0);
- dir_g_in_bits &= ~(1<<0);
- }
- if ((arg & 0x0000FF00) == 0x0000FF00) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
- dir_g_out_bits |= 0x0000FF00;
- dir_g_in_bits &= ~0x0000FF00;
- }
- if ((arg & 0x00FF0000) == 0x00FF0000) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
- dir_g_out_bits |= 0x00FF0000;
- dir_g_in_bits &= ~0x00FF0000;
- }
- if (arg & (1<<24)) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
- dir_g_out_bits |= (1<<24);
- dir_g_in_bits &= ~(1<<24);
- }
- D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
- "genconfig to 0x%08lX "
- "in_bits: 0x%08lX "
- "out_bits: 0x%08lX\n",
- (unsigned long)genconfig_shadow,
- dir_g_in_bits, dir_g_out_bits));
- *R_GEN_CONFIG = genconfig_shadow;
- /* Must be a >120 ns delay before writing this again */
- }
- return dir_g_out_bits & 0x7FFFFFFF;
-} /* setget_output */
-
-static int
-gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
-
-static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- unsigned long flags;
- unsigned long val;
- int ret = 0;
-
- struct gpio_private *priv = file->private_data;
- if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
- return -EINVAL;
-
- switch (_IOC_NR(cmd)) {
- case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
- // read the port
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- ret = *priv->port;
- } else if (priv->minor == GPIO_MINOR_G) {
- ret = (*R_PORT_G_DATA) & 0x7FFFFFFF;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- break;
- case IO_SETBITS:
- // set changeable bits with a 1 in arg
- spin_lock_irqsave(&gpio_lock, flags);
-
- if (USE_PORTS(priv)) {
- *priv->port = *priv->shadow |=
- ((unsigned char)arg & priv->changeable_bits);
- } else if (priv->minor == GPIO_MINOR_G) {
- *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- break;
- case IO_CLRBITS:
- // clear changeable bits with a 1 in arg
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- *priv->port = *priv->shadow &=
- ~((unsigned char)arg & priv->changeable_bits);
- } else if (priv->minor == GPIO_MINOR_G) {
- *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_HIGHALARM:
- // set alarm when bits with 1 in arg go high
- spin_lock_irqsave(&gpio_lock, flags);
- priv->highalarm |= arg;
- gpio_some_alarms = 1;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_LOWALARM:
- // set alarm when bits with 1 in arg go low
- spin_lock_irqsave(&gpio_lock, flags);
- priv->lowalarm |= arg;
- gpio_some_alarms = 1;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_CLRALARM:
- /* clear alarm for bits with 1 in arg */
- spin_lock_irqsave(&gpio_lock, flags);
- priv->highalarm &= ~arg;
- priv->lowalarm &= ~arg;
- {
- /* Must update gpio_some_alarms */
- struct gpio_private *p = alarmlist;
- int some_alarms;
- p = alarmlist;
- some_alarms = 0;
- while (p) {
- if (p->highalarm | p->lowalarm) {
- some_alarms = 1;
- break;
- }
- p = p->next;
- }
- gpio_some_alarms = some_alarms;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
- /* Read direction 0=input 1=output */
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- ret = *priv->dir_shadow;
- } else if (priv->minor == GPIO_MINOR_G) {
- /* Note: Some bits are both in and out,
- * Those that are dual is set here as well.
- */
- ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
- /* Set direction 0=unchanged 1=input,
- * return mask with 1=input
- */
- spin_lock_irqsave(&gpio_lock, flags);
- ret = setget_input(priv, arg) & 0x7FFFFFFF;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
- /* Set direction 0=unchanged 1=output,
- * return mask with 1=output
- */
- spin_lock_irqsave(&gpio_lock, flags);
- ret = setget_output(priv, arg) & 0x7FFFFFFF;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_SHUTDOWN:
- spin_lock_irqsave(&gpio_lock, flags);
- SOFT_SHUTDOWN();
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_GET_PWR_BT:
- spin_lock_irqsave(&gpio_lock, flags);
-#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
- ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
-#else
- ret = 0;
-#endif
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_CFG_WRITE_MODE:
- spin_lock_irqsave(&gpio_lock, flags);
- priv->clk_mask = arg & 0xFF;
- priv->data_mask = (arg >> 8) & 0xFF;
- priv->write_msb = (arg >> 16) & 0x01;
- /* Check if we're allowed to change the bits and
- * the direction is correct
- */
- if (!((priv->clk_mask & priv->changeable_bits) &&
- (priv->data_mask & priv->changeable_bits) &&
- (priv->clk_mask & *priv->dir_shadow) &&
- (priv->data_mask & *priv->dir_shadow)))
- {
- priv->clk_mask = 0;
- priv->data_mask = 0;
- ret = -EPERM;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_READ_INBITS:
- /* *arg is result of reading the input pins */
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- val = *priv->port;
- } else if (priv->minor == GPIO_MINOR_G) {
- val = *R_PORT_G_DATA;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- case IO_READ_OUTBITS:
- /* *arg is result of reading the output shadow */
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- val = *priv->shadow;
- } else if (priv->minor == GPIO_MINOR_G) {
- val = port_g_data_shadow;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- case IO_SETGET_INPUT:
- /* bits set in *arg is set to input,
- * *arg updated with current input pins.
- */
- if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
- {
- ret = -EFAULT;
- break;
- }
- spin_lock_irqsave(&gpio_lock, flags);
- val = setget_input(priv, val);
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- case IO_SETGET_OUTPUT:
- /* bits set in *arg is set to output,
- * *arg updated with current output pins.
- */
- if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
- ret = -EFAULT;
- break;
- }
- spin_lock_irqsave(&gpio_lock, flags);
- val = setget_output(priv, val);
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- default:
- spin_lock_irqsave(&gpio_lock, flags);
- if (priv->minor == GPIO_MINOR_LEDS)
- ret = gpio_leds_ioctl(cmd, arg);
- else
- ret = -EINVAL;
- spin_unlock_irqrestore(&gpio_lock, flags);
- } /* switch */
-
- return ret;
-}
-
-static int
-gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
-{
- unsigned char green;
- unsigned char red;
-
- switch (_IOC_NR(cmd)) {
- case IO_LEDACTIVE_SET:
- green = ((unsigned char)arg) & 1;
- red = (((unsigned char)arg) >> 1) & 1;
- CRIS_LED_ACTIVE_SET_G(green);
- CRIS_LED_ACTIVE_SET_R(red);
- break;
-
- case IO_LED_SETBIT:
- CRIS_LED_BIT_SET(arg);
- break;
-
- case IO_LED_CLRBIT:
- CRIS_LED_BIT_CLR(arg);
- break;
-
- default:
- return -EINVAL;
- } /* switch */
-
- return 0;
-}
-
-static const struct file_operations gpio_fops = {
- .owner = THIS_MODULE,
- .poll = gpio_poll,
- .unlocked_ioctl = gpio_ioctl,
- .write = gpio_write,
- .open = gpio_open,
- .release = gpio_release,
- .llseek = noop_llseek,
-};
-
-static void ioif_watcher(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available)
-{
- unsigned long int flags;
-
- D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
- D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
- "PA: 0x%02x PB: 0x%02x\n",
- gpio_in_available, gpio_out_available,
- pa_available, pb_available));
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- dir_g_in_bits = gpio_in_available;
- dir_g_out_bits = gpio_out_available;
-
- /* Initialise the dir_g_shadow etc. depending on genconfig */
- /* 0=input 1=output */
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
- dir_g_shadow |= (1 << 0);
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
- dir_g_shadow |= 0x0000FF00;
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
- dir_g_shadow |= 0x00FF0000;
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
- dir_g_shadow |= (1 << 24);
-
- changeable_dir_g = changeable_dir_g_mask;
- changeable_dir_g &= dir_g_out_bits;
- changeable_dir_g &= dir_g_in_bits;
-
- /* Correct the bits that can change direction */
- dir_g_out_bits &= ~changeable_dir_g;
- dir_g_out_bits |= dir_g_shadow;
- dir_g_in_bits &= ~changeable_dir_g;
- dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
- "val: %08lX\n",
- dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
- printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
- dir_g_shadow, changeable_dir_g);
-}
-
-/* main driver initialization routine, called from mem.c */
-
-static int __init gpio_init(void)
-{
- int res;
-#if defined (CONFIG_ETRAX_CSP0_LEDS)
- int i;
-#endif
-
- res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
- if (res < 0) {
- printk(KERN_ERR "gpio: couldn't get a major number.\n");
- return res;
- }
-
- /* Clear all leds */
-#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
- CRIS_LED_NETWORK_SET(0);
- CRIS_LED_ACTIVE_SET(0);
- CRIS_LED_DISK_READ(0);
- CRIS_LED_DISK_WRITE(0);
-
-#if defined (CONFIG_ETRAX_CSP0_LEDS)
- for (i = 0; i < 32; i++)
- CRIS_LED_BIT_SET(i);
-#endif
-
-#endif
- /* The I/O interface allocation watcher will be called when
- * registering it. */
- if (cris_io_interface_register_watcher(ioif_watcher)){
- printk(KERN_WARNING "gpio_init: Failed to install IO "
- "if allocator watcher\n");
- }
-
- printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
- "Axis Communications AB\n");
- /* We call etrax_gpio_wake_up_check() from timer interrupt and
- * from default_idle() in kernel/process.c
- * The check in default_idle() reduces latency from ~15 ms to ~6 ms
- * in some tests.
- */
- res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
- IRQF_SHARED, "gpio poll", gpio_name);
- if (res) {
- printk(KERN_CRIT "err: timer0 irq for gpio\n");
- return res;
- }
- res = request_irq(PA_IRQ_NBR, gpio_interrupt,
- IRQF_SHARED, "gpio PA", gpio_name);
- if (res)
- printk(KERN_CRIT "err: PA irq for gpio\n");
-
- return res;
-}
-
-/* this makes sure that gpio_init is called during kernel boot */
-module_init(gpio_init);
-
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
deleted file mode 100644
index ec35d62e8e63..000000000000
--- a/arch/cris/arch-v10/drivers/i2c.c
+++ /dev/null
@@ -1,699 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*!***************************************************************************
-*!
-*! FILE NAME : i2c.c
-*!
-*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other
-*! kernel modules (i2c_writereg/readreg) and from userspace using
-*! ioctl()'s
-*!
-*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN
-*!
-*!***************************************************************************/
-
-/****************** INCLUDE FILES SECTION ***********************************/
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/init.h>
-
-#include <asm/etraxi2c.h>
-
-#include <arch/svinto.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <arch/io_interface_mux.h>
-
-#include "i2c.h"
-
-/****************** I2C DEFINITION SECTION *************************/
-
-#define D(x)
-
-#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */
-static const char i2c_name[] = "i2c";
-
-#define CLOCK_LOW_TIME 8
-#define CLOCK_HIGH_TIME 8
-#define START_CONDITION_HOLD_TIME 8
-#define STOP_CONDITION_HOLD_TIME 8
-#define ENABLE_OUTPUT 0x01
-#define ENABLE_INPUT 0x00
-#define I2C_CLOCK_HIGH 1
-#define I2C_CLOCK_LOW 0
-#define I2C_DATA_HIGH 1
-#define I2C_DATA_LOW 0
-
-#ifdef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
-/* Use PB and not PB_I2C */
-#ifndef CONFIG_ETRAX_I2C_DATA_PORT
-#define CONFIG_ETRAX_I2C_DATA_PORT 0
-#endif
-#ifndef CONFIG_ETRAX_I2C_CLK_PORT
-#define CONFIG_ETRAX_I2C_CLK_PORT 1
-#endif
-
-#define SDABIT CONFIG_ETRAX_I2C_DATA_PORT
-#define SCLBIT CONFIG_ETRAX_I2C_CLK_PORT
-#define i2c_enable()
-#define i2c_disable()
-
-/* enable or disable output-enable, to select output or input on the i2c bus */
-
-#define i2c_dir_out() \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 1)
-#define i2c_dir_in() \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 0)
-
-/* control the i2c clock and data signals */
-
-#define i2c_clk(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SCLBIT, x)
-#define i2c_data(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SDABIT, x)
-
-/* read a bit from the i2c interface */
-
-#define i2c_getbit() (((*R_PORT_PB_READ & (1 << SDABIT))) >> SDABIT)
-
-#else
-/* enable or disable the i2c interface */
-
-#define i2c_enable() *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_en))
-#define i2c_disable() *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_en))
-
-/* enable or disable output-enable, to select output or input on the i2c bus */
-
-#define i2c_dir_out() \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 1);
-#define i2c_dir_in() \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 0);
-
-/* control the i2c clock and data signals */
-
-#define i2c_clk(x) \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \
- ~IO_MASK(R_PORT_PB_I2C, i2c_clk)) | IO_FIELD(R_PORT_PB_I2C, i2c_clk, (x))); \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 1, x);
-
-#define i2c_data(x) \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \
- ~IO_MASK(R_PORT_PB_I2C, i2c_d)) | IO_FIELD(R_PORT_PB_I2C, i2c_d, (x))); \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 0, x);
-
-/* read a bit from the i2c interface */
-
-#define i2c_getbit() (*R_PORT_PB_READ & 0x1)
-#endif
-
-/* use the kernels delay routine */
-
-#define i2c_delay(usecs) udelay(usecs)
-
-static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */
-
-/****************** FUNCTION DEFINITION SECTION *************************/
-
-
-/* generate i2c start condition */
-
-void
-i2c_start(void)
-{
- /*
- * SCL=1 SDA=1
- */
- i2c_dir_out();
- i2c_delay(CLOCK_HIGH_TIME/6);
- i2c_data(I2C_DATA_HIGH);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- /*
- * SCL=1 SDA=0
- */
- i2c_data(I2C_DATA_LOW);
- i2c_delay(START_CONDITION_HOLD_TIME);
- /*
- * SCL=0 SDA=0
- */
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME);
-}
-
-/* generate i2c stop condition */
-
-void
-i2c_stop(void)
-{
- i2c_dir_out();
-
- /*
- * SCL=0 SDA=0
- */
- i2c_clk(I2C_CLOCK_LOW);
- i2c_data(I2C_DATA_LOW);
- i2c_delay(CLOCK_LOW_TIME*2);
- /*
- * SCL=1 SDA=0
- */
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME*2);
- /*
- * SCL=1 SDA=1
- */
- i2c_data(I2C_DATA_HIGH);
- i2c_delay(STOP_CONDITION_HOLD_TIME);
-
- i2c_dir_in();
-}
-
-/* write a byte to the i2c interface */
-
-void
-i2c_outbyte(unsigned char x)
-{
- int i;
-
- i2c_dir_out();
-
- for (i = 0; i < 8; i++) {
- if (x & 0x80) {
- i2c_data(I2C_DATA_HIGH);
- } else {
- i2c_data(I2C_DATA_LOW);
- }
-
- i2c_delay(CLOCK_LOW_TIME/2);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME/2);
- x <<= 1;
- }
- i2c_data(I2C_DATA_LOW);
- i2c_delay(CLOCK_LOW_TIME/2);
-
- /*
- * enable input
- */
- i2c_dir_in();
-}
-
-/* read a byte from the i2c interface */
-
-unsigned char
-i2c_inbyte(void)
-{
- unsigned char aBitByte = 0;
- int i;
-
- /* Switch off I2C to get bit */
- i2c_disable();
- i2c_dir_in();
- i2c_delay(CLOCK_HIGH_TIME/2);
-
- /* Get bit */
- aBitByte |= i2c_getbit();
-
- /* Enable I2C */
- i2c_enable();
- i2c_delay(CLOCK_LOW_TIME/2);
-
- for (i = 1; i < 8; i++) {
- aBitByte <<= 1;
- /* Clock pulse */
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME);
-
- /* Switch off I2C to get bit */
- i2c_disable();
- i2c_dir_in();
- i2c_delay(CLOCK_HIGH_TIME/2);
-
- /* Get bit */
- aBitByte |= i2c_getbit();
-
- /* Enable I2C */
- i2c_enable();
- i2c_delay(CLOCK_LOW_TIME/2);
- }
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
-
- /*
- * we leave the clock low, getbyte is usually followed
- * by sendack/nack, they assume the clock to be low
- */
- i2c_clk(I2C_CLOCK_LOW);
- return aBitByte;
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_getack
-*#
-*# DESCRIPTION : checks if ack was received from ic2
-*#
-*#--------------------------------------------------------------------------*/
-
-int
-i2c_getack(void)
-{
- int ack = 1;
- /*
- * enable output
- */
- i2c_dir_out();
- /*
- * Release data bus by setting
- * data high
- */
- i2c_data(I2C_DATA_HIGH);
- /*
- * enable input
- */
- i2c_dir_in();
- i2c_delay(CLOCK_HIGH_TIME/4);
- /*
- * generate ACK clock pulse
- */
- i2c_clk(I2C_CLOCK_HIGH);
- /*
- * Use PORT PB instead of I2C
- * for input. (I2C not working)
- */
- i2c_clk(1);
- i2c_data(1);
- /*
- * switch off I2C
- */
- i2c_data(1);
- i2c_disable();
- i2c_dir_in();
- /*
- * now wait for ack
- */
- i2c_delay(CLOCK_HIGH_TIME/2);
- /*
- * check for ack
- */
- if(i2c_getbit())
- ack = 0;
- i2c_delay(CLOCK_HIGH_TIME/2);
- if(!ack){
- if(!i2c_getbit()) /* receiver pulld SDA low */
- ack = 1;
- i2c_delay(CLOCK_HIGH_TIME/2);
- }
-
- /*
- * our clock is high now, make sure data is low
- * before we enable our output. If we keep data high
- * and enable output, we would generate a stop condition.
- */
- i2c_data(I2C_DATA_LOW);
-
- /*
- * end clock pulse
- */
- i2c_enable();
- i2c_dir_out();
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_HIGH_TIME/4);
- /*
- * enable output
- */
- i2c_dir_out();
- /*
- * remove ACK clock pulse
- */
- i2c_data(I2C_DATA_HIGH);
- i2c_delay(CLOCK_LOW_TIME/2);
- return ack;
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: I2C::sendAck
-*#
-*# DESCRIPTION : Send ACK on received data
-*#
-*#--------------------------------------------------------------------------*/
-void
-i2c_sendack(void)
-{
- /*
- * enable output
- */
- i2c_delay(CLOCK_LOW_TIME);
- i2c_dir_out();
- /*
- * set ack pulse high
- */
- i2c_data(I2C_DATA_LOW);
- /*
- * generate clock pulse
- */
- i2c_delay(CLOCK_HIGH_TIME/6);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME/6);
- /*
- * reset data out
- */
- i2c_data(I2C_DATA_HIGH);
- i2c_delay(CLOCK_LOW_TIME);
-
- i2c_dir_in();
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_sendnack
-*#
-*# DESCRIPTION : Sends NACK on received data
-*#
-*#--------------------------------------------------------------------------*/
-void
-i2c_sendnack(void)
-{
- /*
- * enable output
- */
- i2c_delay(CLOCK_LOW_TIME);
- i2c_dir_out();
- /*
- * set data high
- */
- i2c_data(I2C_DATA_HIGH);
- /*
- * generate clock pulse
- */
- i2c_delay(CLOCK_HIGH_TIME/6);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME);
-
- i2c_dir_in();
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_writereg
-*#
-*# DESCRIPTION : Writes a value to an I2C device
-*#
-*#--------------------------------------------------------------------------*/
-int
-i2c_writereg(unsigned char theSlave, unsigned char theReg,
- unsigned char theValue)
-{
- int error, cntr = 3;
- unsigned long flags;
-
- spin_lock(&i2c_lock);
-
- do {
- error = 0;
- /*
- * we don't like to be interrupted
- */
- local_irq_save(flags);
-
- i2c_start();
- /*
- * send slave address
- */
- i2c_outbyte((theSlave & 0xfe));
- /*
- * wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * now select register
- */
- i2c_dir_out();
- i2c_outbyte(theReg);
- /*
- * now it's time to wait for ack
- */
- if(!i2c_getack())
- error |= 2;
- /*
- * send register register data
- */
- i2c_outbyte(theValue);
- /*
- * now it's time to wait for ack
- */
- if(!i2c_getack())
- error |= 4;
- /*
- * end byte stream
- */
- i2c_stop();
- /*
- * enable interrupt again
- */
- local_irq_restore(flags);
-
- } while(error && cntr--);
-
- i2c_delay(CLOCK_LOW_TIME);
-
- spin_unlock(&i2c_lock);
-
- return -error;
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_readreg
-*#
-*# DESCRIPTION : Reads a value from the decoder registers.
-*#
-*#--------------------------------------------------------------------------*/
-unsigned char
-i2c_readreg(unsigned char theSlave, unsigned char theReg)
-{
- unsigned char b = 0;
- int error, cntr = 3;
- unsigned long flags;
-
- spin_lock(&i2c_lock);
-
- do {
- error = 0;
- /*
- * we don't like to be interrupted
- */
- local_irq_save(flags);
- /*
- * generate start condition
- */
- i2c_start();
-
- /*
- * send slave address
- */
- i2c_outbyte((theSlave & 0xfe));
- /*
- * wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * now select register
- */
- i2c_dir_out();
- i2c_outbyte(theReg);
- /*
- * now it's time to wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * repeat start condition
- */
- i2c_delay(CLOCK_LOW_TIME);
- i2c_start();
- /*
- * send slave address
- */
- i2c_outbyte(theSlave | 0x01);
- /*
- * wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * fetch register
- */
- b = i2c_inbyte();
- /*
- * last received byte needs to be nacked
- * instead of acked
- */
- i2c_sendnack();
- /*
- * end sequence
- */
- i2c_stop();
- /*
- * enable interrupt again
- */
- local_irq_restore(flags);
-
- } while(error && cntr--);
-
- spin_unlock(&i2c_lock);
-
- return b;
-}
-
-static int
-i2c_open(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-static int
-i2c_release(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-/* Main device API. ioctl's to write or read to/from i2c registers.
- */
-
-static long i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
- return -EINVAL;
- }
-
- switch (_IOC_NR(cmd)) {
- case I2C_WRITEREG:
- /* write to an i2c slave */
- D(printk(KERN_DEBUG "i2cw %d %d %d\n",
- I2C_ARGSLAVE(arg),
- I2C_ARGREG(arg),
- I2C_ARGVALUE(arg)));
-
- return i2c_writereg(I2C_ARGSLAVE(arg),
- I2C_ARGREG(arg),
- I2C_ARGVALUE(arg));
- case I2C_READREG:
- {
- unsigned char val;
- /* read from an i2c slave */
- D(printk(KERN_DEBUG "i2cr %d %d ",
- I2C_ARGSLAVE(arg),
- I2C_ARGREG(arg)));
- val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
- D(printk(KERN_DEBUG "= %d\n", val));
- return val;
- }
- default:
- return -EINVAL;
-
- }
- return 0;
-}
-
-static const struct file_operations i2c_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = i2c_ioctl,
- .open = i2c_open,
- .release = i2c_release,
- .llseek = noop_llseek,
-};
-
-int __init
-i2c_init(void)
-{
- static int res = 0;
- static int first = 1;
-
- if (!first) {
- return res;
- }
- first = 0;
-
- /* Setup and enable the Port B I2C interface */
-
-#ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
- if ((res = cris_request_io_interface(if_i2c, "I2C"))) {
- printk(KERN_CRIT "i2c_init: Failed to get IO interface\n");
- return res;
- }
-
- *R_PORT_PB_I2C = port_pb_i2c_shadow |=
- IO_STATE(R_PORT_PB_I2C, i2c_en, on) |
- IO_FIELD(R_PORT_PB_I2C, i2c_d, 1) |
- IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1) |
- IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable);
-
- port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0);
- port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1);
-
- *R_PORT_PB_DIR = (port_pb_dir_shadow |=
- IO_STATE(R_PORT_PB_DIR, dir0, input) |
- IO_STATE(R_PORT_PB_DIR, dir1, output));
-#else
- if ((res = cris_io_interface_allocate_pins(if_i2c,
- 'b',
- CONFIG_ETRAX_I2C_DATA_PORT,
- CONFIG_ETRAX_I2C_DATA_PORT))) {
- printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C data port\n");
- return res;
- } else if ((res = cris_io_interface_allocate_pins(if_i2c,
- 'b',
- CONFIG_ETRAX_I2C_CLK_PORT,
- CONFIG_ETRAX_I2C_CLK_PORT))) {
- cris_io_interface_free_pins(if_i2c,
- 'b',
- CONFIG_ETRAX_I2C_DATA_PORT,
- CONFIG_ETRAX_I2C_DATA_PORT);
- printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C clk port\n");
- }
-#endif
-
- return res;
-}
-
-static int __init
-i2c_register(void)
-{
- int res;
-
- res = i2c_init();
- if (res < 0)
- return res;
- res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
- if(res < 0) {
- printk(KERN_ERR "i2c: couldn't get a major number.\n");
- return res;
- }
-
- printk(KERN_INFO "I2C driver v2.2, (c) 1999-2004 Axis Communications AB\n");
-
- return 0;
-}
-
-/* this makes sure that i2c_register is called during boot */
-
-module_init(i2c_register);
-
-/****************** END OF FILE i2c.c ********************************/
diff --git a/arch/cris/arch-v10/drivers/i2c.h b/arch/cris/arch-v10/drivers/i2c.h
deleted file mode 100644
index de45c1ffbd7b..000000000000
--- a/arch/cris/arch-v10/drivers/i2c.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* i2c.h */
-int i2c_init(void);
-
-/* High level I2C actions */
-int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
-unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
-
-/* Low level I2C */
-void i2c_start(void);
-void i2c_stop(void);
-void i2c_outbyte(unsigned char x);
-unsigned char i2c_inbyte(void);
-int i2c_getack(void);
-void i2c_sendack(void);
-
-
-
diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c
deleted file mode 100644
index ed1a568a7217..000000000000
--- a/arch/cris/arch-v10/drivers/sync_serial.c
+++ /dev/null
@@ -1,1463 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simple synchronous serial port driver for ETRAX 100LX.
- *
- * Synchronous serial ports are used for continuous streamed data like audio.
- * The default setting for this driver is compatible with the STA 013 MP3
- * decoder. The driver can easily be tuned to fit other audio encoder/decoders
- * and SPI
- *
- * Copyright (c) 2001-2008 Axis Communications AB
- *
- * Author: Mikael Starvik, Johan Adolfsson
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/major.h>
-#include <linux/sched/signal.h>
-#include <linux/interrupt.h>
-#include <linux/poll.h>
-#include <linux/init.h>
-#include <linux/mutex.h>
-#include <linux/timer.h>
-#include <linux/wait.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <arch/svinto.h>
-#include <linux/uaccess.h>
-#include <asm/sync_serial.h>
-#include <arch/io_interface_mux.h>
-
-/* The receiver is a bit tricky because of the continuous stream of data.*/
-/* */
-/* Three DMA descriptors are linked together. Each DMA descriptor is */
-/* responsible for port->bufchunk of a common buffer. */
-/* */
-/* +---------------------------------------------+ */
-/* | +----------+ +----------+ +----------+ | */
-/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
-/* +----------+ +----------+ +----------+ */
-/* | | | */
-/* v v v */
-/* +-------------------------------------+ */
-/* | BUFFER | */
-/* +-------------------------------------+ */
-/* |<- data_avail ->| */
-/* readp writep */
-/* */
-/* If the application keeps up the pace readp will be right after writep.*/
-/* If the application can't keep the pace we have to throw away data. */
-/* The idea is that readp should be ready with the data pointed out by */
-/* Descr[i] when the DMA has filled in Descr[i+1]. */
-/* Otherwise we will discard */
-/* the rest of the data pointed out by Descr1 and set readp to the start */
-/* of Descr2 */
-
-#define SYNC_SERIAL_MAJOR 125
-
-/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
-/* words can be handled */
-#define IN_BUFFER_SIZE 12288
-#define IN_DESCR_SIZE 256
-#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
-#define OUT_BUFFER_SIZE 4096
-
-#define DEFAULT_FRAME_RATE 0
-#define DEFAULT_WORD_RATE 7
-
-/* NOTE: Enabling some debug will likely cause overrun or underrun,
- * especially if manual mode is use.
- */
-#define DEBUG(x)
-#define DEBUGREAD(x)
-#define DEBUGWRITE(x)
-#define DEBUGPOLL(x)
-#define DEBUGRXINT(x)
-#define DEBUGTXINT(x)
-
-/* Define some macros to access ETRAX 100 registers */
-#define SETF(var, reg, field, val) \
- do { \
- var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_FIELD_(reg##_, field##_, val); \
- } while (0)
-
-#define SETS(var, reg, field, val) \
- do { \
- var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_STATE_(reg##_, field##_, _##val); \
- } while (0)
-
-struct sync_port {
- /* Etrax registers and bits*/
- const volatile unsigned *const status;
- volatile unsigned *const ctrl_data;
- volatile unsigned *const output_dma_first;
- volatile unsigned char *const output_dma_cmd;
- volatile unsigned char *const output_dma_clr_irq;
- volatile unsigned *const input_dma_first;
- volatile unsigned char *const input_dma_cmd;
- volatile unsigned *const input_dma_descr;
- /* 8*4 */
- volatile unsigned char *const input_dma_clr_irq;
- volatile unsigned *const data_out;
- const volatile unsigned *const data_in;
- char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
- char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
- char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
-
- char output_dma_bit; /* In R_IRQ_MASK2_RD */
- /* End of fields initialised in array */
- char started; /* 1 if port has been started */
- char port_nbr; /* Port 0 or 1 */
- char busy; /* 1 if port is busy */
-
- char enabled; /* 1 if port is enabled */
- char use_dma; /* 1 if port uses dma */
- char tr_running;
-
- char init_irqs;
-
- /* Register shadow */
- unsigned int ctrl_data_shadow;
- /* Remaining bytes for current transfer */
- volatile unsigned int out_count;
- /* Current position in out_buffer */
- unsigned char *outp;
- /* 16*4 */
- /* Next byte to be read by application */
- volatile unsigned char *volatile readp;
- /* Next byte to be written by etrax */
- volatile unsigned char *volatile writep;
-
- unsigned int in_buffer_size;
- unsigned int inbufchunk;
- struct etrax_dma_descr out_descr __attribute__ ((aligned(32)));
- struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32)));
- unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
- unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
- unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
- struct etrax_dma_descr *next_rx_desc;
- struct etrax_dma_descr *prev_rx_desc;
- int full;
-
- wait_queue_head_t out_wait_q;
- wait_queue_head_t in_wait_q;
-};
-
-
-static DEFINE_MUTEX(sync_serial_mutex);
-static int etrax_sync_serial_init(void);
-static void initialize_port(int portnbr);
-static inline int sync_data_avail(struct sync_port *port);
-
-static int sync_serial_open(struct inode *inode, struct file *file);
-static int sync_serial_release(struct inode *inode, struct file *file);
-static __poll_t sync_serial_poll(struct file *filp, poll_table *wait);
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg);
-static ssize_t sync_serial_write(struct file *file, const char *buf,
- size_t count, loff_t *ppos);
-static ssize_t sync_serial_read(struct file *file, char *buf,
- size_t count, loff_t *ppos);
-
-#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
- (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
-#define SYNC_SER_DMA
-#endif
-
-static void send_word(struct sync_port *port);
-static void start_dma(struct sync_port *port, const char *data, int count);
-static void start_dma_in(struct sync_port *port);
-#ifdef SYNC_SER_DMA
-static irqreturn_t tr_interrupt(int irq, void *dev_id);
-static irqreturn_t rx_interrupt(int irq, void *dev_id);
-#endif
-#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
- !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
- (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
- !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
-#define SYNC_SER_MANUAL
-#endif
-#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id);
-#endif
-
-/* The ports */
-static struct sync_port ports[] = {
- {
- .status = R_SYNC_SERIAL1_STATUS,
- .ctrl_data = R_SYNC_SERIAL1_CTRL,
- .output_dma_first = R_DMA_CH8_FIRST,
- .output_dma_cmd = R_DMA_CH8_CMD,
- .output_dma_clr_irq = R_DMA_CH8_CLR_INTR,
- .input_dma_first = R_DMA_CH9_FIRST,
- .input_dma_cmd = R_DMA_CH9_CMD,
- .input_dma_descr = R_DMA_CH9_DESCR,
- .input_dma_clr_irq = R_DMA_CH9_CLR_INTR,
- .data_out = R_SYNC_SERIAL1_TR_DATA,
- .data_in = R_SYNC_SERIAL1_REC_DATA,
- .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
- .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
- .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
- .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
- .init_irqs = 1,
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- },
- {
- .status = R_SYNC_SERIAL3_STATUS,
- .ctrl_data = R_SYNC_SERIAL3_CTRL,
- .output_dma_first = R_DMA_CH4_FIRST,
- .output_dma_cmd = R_DMA_CH4_CMD,
- .output_dma_clr_irq = R_DMA_CH4_CLR_INTR,
- .input_dma_first = R_DMA_CH5_FIRST,
- .input_dma_cmd = R_DMA_CH5_CMD,
- .input_dma_descr = R_DMA_CH5_DESCR,
- .input_dma_clr_irq = R_DMA_CH5_CLR_INTR,
- .data_out = R_SYNC_SERIAL3_TR_DATA,
- .data_in = R_SYNC_SERIAL3_REC_DATA,
- .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
- .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
- .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
- .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
- .init_irqs = 1,
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- }
-};
-
-/* Register shadows */
-static unsigned sync_serial_prescale_shadow;
-
-#define NUMBER_OF_PORTS 2
-
-static const struct file_operations sync_serial_fops = {
- .owner = THIS_MODULE,
- .write = sync_serial_write,
- .read = sync_serial_read,
- .poll = sync_serial_poll,
- .unlocked_ioctl = sync_serial_ioctl,
- .open = sync_serial_open,
- .release = sync_serial_release,
- .llseek = noop_llseek,
-};
-
-static int __init etrax_sync_serial_init(void)
-{
- ports[0].enabled = 0;
- ports[1].enabled = 0;
-
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) {
- printk(KERN_CRIT "ETRAX100LX sync_serial: "
- "Could not allocate IO group for port %d\n", 0);
- return -EBUSY;
- }
-#endif
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) {
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- cris_free_io_interface(if_sync_serial_1);
-#endif
- printk(KERN_CRIT "ETRAX100LX sync_serial: "
- "Could not allocate IO group for port %d\n", 1);
- return -EBUSY;
- }
-#endif
-
- if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
- &sync_serial_fops) < 0) {
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- cris_free_io_interface(if_sync_serial_3);
-#endif
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- cris_free_io_interface(if_sync_serial_1);
-#endif
- printk("unable to get major for synchronous serial port\n");
- return -EBUSY;
- }
-
- /* Deselect synchronous serial ports while configuring. */
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
-
- /* Initialize Ports */
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- ports[0].enabled = 1;
- SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
- ports[0].use_dma = 1;
-#else
- ports[0].use_dma = 0;
-#endif
- initialize_port(0);
-#endif
-
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- ports[1].enabled = 1;
- SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
- ports[1].use_dma = 1;
-#else
- ports[1].use_dma = 0;
-#endif
- initialize_port(1);
-#endif
-
- *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
-
- /* Set up timing */
- *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
- IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
- IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate,
- DEFAULT_FRAME_RATE) |
- IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
-
- /* Select synchronous ports */
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
-
- printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n");
- return 0;
-}
-
-static void __init initialize_port(int portnbr)
-{
- struct sync_port *port = &ports[portnbr];
-
- DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
-
- port->started = 0;
- port->port_nbr = portnbr;
- port->busy = 0;
- port->tr_running = 0;
-
- port->out_count = 0;
- port->outp = port->out_buffer;
-
- port->readp = port->flip;
- port->writep = port->flip;
- port->in_buffer_size = IN_BUFFER_SIZE;
- port->inbufchunk = IN_DESCR_SIZE;
- port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
- port->prev_rx_desc->ctrl = d_eol;
-
- init_waitqueue_head(&port->out_wait_q);
- init_waitqueue_head(&port->in_wait_q);
-
- port->ctrl_data_shadow =
- IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
- IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
- IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
-
- if (port->use_dma)
- port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
- dma_enable, on);
- else
- port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
- dma_enable, off);
-
- *port->ctrl_data = port->ctrl_data_shadow;
-}
-
-static inline int sync_data_avail(struct sync_port *port)
-{
- int avail;
- unsigned char *start;
- unsigned char *end;
-
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- /* 0123456789 0123456789
- * ----- - -----
- * ^rp ^wp ^wp ^rp
- */
- if (end >= start)
- avail = end - start;
- else
- avail = port->in_buffer_size - (start - end);
- return avail;
-}
-
-static inline int sync_data_avail_to_end(struct sync_port *port)
-{
- int avail;
- unsigned char *start;
- unsigned char *end;
-
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- /* 0123456789 0123456789
- * ----- -----
- * ^rp ^wp ^wp ^rp
- */
-
- if (end >= start)
- avail = end - start;
- else
- avail = port->flip + port->in_buffer_size - start;
- return avail;
-}
-
-
-static int sync_serial_open(struct inode *inode, struct file *file)
-{
- int dev = MINOR(inode->i_rdev);
- struct sync_port *port;
- int mode;
- int err = -EBUSY;
-
- mutex_lock(&sync_serial_mutex);
- DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- err = -ENODEV;
- goto out;
- }
- port = &ports[dev];
- /* Allow open this device twice (assuming one reader and one writer) */
- if (port->busy == 2) {
- DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
- goto out;
- }
- if (port->init_irqs) {
- if (port->use_dma) {
- if (port == &ports[0]) {
-#ifdef SYNC_SER_DMA
- if (request_irq(24, tr_interrupt, 0,
- "synchronous serial 1 dma tr",
- &ports[0])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 IRQ");
- goto out;
- } else if (request_irq(25, rx_interrupt, 0,
- "synchronous serial 1 dma rx",
- &ports[0])) {
- free_irq(24, &port[0]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 IRQ");
- goto out;
- } else if (cris_request_dma(8,
- "synchronous serial 1 dma tr",
- DMA_VERBOSE_ON_ERROR,
- dma_ser1)) {
- free_irq(24, &port[0]);
- free_irq(25, &port[0]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 "
- "TX DMA channel");
- goto out;
- } else if (cris_request_dma(9,
- "synchronous serial 1 dma rec",
- DMA_VERBOSE_ON_ERROR,
- dma_ser1)) {
- cris_free_dma(8, NULL);
- free_irq(24, &port[0]);
- free_irq(25, &port[0]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 "
- "RX DMA channel");
- goto out;
- }
-#endif
- RESET_DMA(8); WAIT_DMA(8);
- RESET_DMA(9); WAIT_DMA(9);
- *R_DMA_CH8_CLR_INTR =
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
- do);
- *R_DMA_CH9_CLR_INTR =
- IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
- do);
- *R_IRQ_MASK2_SET =
- IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
- set) |
- IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
- set);
- } else if (port == &ports[1]) {
-#ifdef SYNC_SER_DMA
- if (request_irq(20, tr_interrupt, 0,
- "synchronous serial 3 dma tr",
- &ports[1])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 IRQ");
- goto out;
- } else if (request_irq(21, rx_interrupt, 0,
- "synchronous serial 3 dma rx",
- &ports[1])) {
- free_irq(20, &ports[1]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 IRQ");
- goto out;
- } else if (cris_request_dma(4,
- "synchronous serial 3 dma tr",
- DMA_VERBOSE_ON_ERROR,
- dma_ser3)) {
- free_irq(21, &ports[1]);
- free_irq(20, &ports[1]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 "
- "TX DMA channel");
- goto out;
- } else if (cris_request_dma(5,
- "synchronous serial 3 dma rec",
- DMA_VERBOSE_ON_ERROR,
- dma_ser3)) {
- cris_free_dma(4, NULL);
- free_irq(21, &ports[1]);
- free_irq(20, &ports[1]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 "
- "RX DMA channel");
- goto out;
- }
-#endif
- RESET_DMA(4); WAIT_DMA(4);
- RESET_DMA(5); WAIT_DMA(5);
- *R_DMA_CH4_CLR_INTR =
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
- do);
- *R_DMA_CH5_CLR_INTR =
- IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
- do);
- *R_IRQ_MASK2_SET =
- IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
- set) |
- IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
- set);
- }
- start_dma_in(port);
- port->init_irqs = 0;
- } else { /* !port->use_dma */
-#ifdef SYNC_SER_MANUAL
- if (port == &ports[0]) {
- if (request_irq(8,
- manual_interrupt,
- IRQF_SHARED,
- "synchronous serial manual irq",
- &ports[0])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial manual irq");
- goto out;
- }
- } else if (port == &ports[1]) {
- if (request_irq(8,
- manual_interrupt,
- IRQF_SHARED,
- "synchronous serial manual irq",
- &ports[1])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial manual irq");
- goto out;
- }
- }
- port->init_irqs = 0;
-#else
- panic("sync_serial: Manual mode not supported.\n");
-#endif /* SYNC_SER_MANUAL */
- }
- } /* port->init_irqs */
-
- port->busy++;
- /* Start port if we use it as input */
- mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
- if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
- mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
- mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
- mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
- running);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
- enable);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
- enable);
- port->started = 1;
- *port->ctrl_data = port->ctrl_data_shadow;
- if (!port->use_dma)
- *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
- DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
- }
- err = 0;
-
-out:
- mutex_unlock(&sync_serial_mutex);
- return err;
-}
-
-static int sync_serial_release(struct inode *inode, struct file *file)
-{
- int dev = MINOR(inode->i_rdev);
- struct sync_port *port;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
- if (port->busy)
- port->busy--;
- if (!port->busy)
- *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
- (1 << port->transmitter_ready_bit));
-
- return 0;
-}
-
-
-
-static __poll_t sync_serial_poll(struct file *file, poll_table *wait)
-{
- int dev = MINOR(file_inode(file)->i_rdev);
- __poll_t mask = 0;
- struct sync_port *port;
- DEBUGPOLL(static __poll_t prev_mask = 0);
-
- port = &ports[dev];
- poll_wait(file, &port->out_wait_q, wait);
- poll_wait(file, &port->in_wait_q, wait);
- /* Some room to write */
- if (port->out_count < OUT_BUFFER_SIZE)
- mask |= EPOLLOUT | EPOLLWRNORM;
- /* At least an inbufchunk of data */
- if (sync_data_avail(port) >= port->inbufchunk)
- mask |= EPOLLIN | EPOLLRDNORM;
-
- DEBUGPOLL(if (mask != prev_mask)
- printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n",
- mask,
- mask & EPOLLOUT ? "POLLOUT" : "",
- mask & EPOLLIN ? "POLLIN" : "");
- prev_mask = mask;
- );
- return mask;
-}
-
-static int sync_serial_ioctl_unlocked(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int return_val = 0;
- unsigned long flags;
-
- int dev = MINOR(file_inode(file)->i_rdev);
- struct sync_port *port;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -1;
- }
- port = &ports[dev];
-
- local_irq_save(flags);
- /* Disable port while changing config */
- if (dev) {
- if (port->use_dma) {
- RESET_DMA(4); WAIT_DMA(4);
- port->tr_running = 0;
- port->out_count = 0;
- port->outp = port->out_buffer;
- *R_DMA_CH4_CLR_INTR =
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
- }
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
- } else {
- if (port->use_dma) {
- RESET_DMA(8); WAIT_DMA(8);
- port->tr_running = 0;
- port->out_count = 0;
- port->outp = port->out_buffer;
- *R_DMA_CH8_CLR_INTR =
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
- }
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
- }
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
- local_irq_restore(flags);
-
- switch (cmd) {
- case SSP_SPEED:
- if (GET_SPEED(arg) == CODEC) {
- if (dev)
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
- codec);
- else
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
- codec);
-
- SETF(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, prescaler,
- GET_FREQ(arg));
- SETF(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, frame_rate,
- GET_FRAME_RATE(arg));
- SETF(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, word_rate,
- GET_WORD_RATE(arg));
- } else {
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- tr_baud, GET_SPEED(arg));
- if (dev)
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
- baudrate);
- else
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
- baudrate);
- }
- break;
- case SSP_MODE:
- if (arg > 5)
- return -EINVAL;
- if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
- *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
- else if (!port->use_dma)
- *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
- break;
- case SSP_FRAME_SYNC:
- if (arg & NORMAL_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_synctype, normal);
- else if (arg & EARLY_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_synctype, early);
-
- if (arg & BIT_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_syncsize, bit);
- else if (arg & WORD_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_syncsize, word);
- else if (arg & EXTENDED_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_syncsize, extended);
-
- if (arg & SYNC_ON)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_sync, on);
- else if (arg & SYNC_OFF)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_sync, off);
-
- if (arg & WORD_SIZE_8)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size8bit);
- else if (arg & WORD_SIZE_12)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size12bit);
- else if (arg & WORD_SIZE_16)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size16bit);
- else if (arg & WORD_SIZE_24)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size24bit);
- else if (arg & WORD_SIZE_32)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size32bit);
-
- if (arg & BIT_ORDER_MSB)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- bitorder, msb);
- else if (arg & BIT_ORDER_LSB)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- bitorder, lsb);
-
- if (arg & FLOW_CONTROL_ENABLE)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- flow_ctrl, enabled);
- else if (arg & FLOW_CONTROL_DISABLE)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- flow_ctrl, disabled);
-
- if (arg & CLOCK_NOT_GATED)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_mode, normal);
- else if (arg & CLOCK_GATED)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_mode, gated);
-
- break;
- case SSP_IPOLARITY:
- /* NOTE!! negedge is considered NORMAL */
- if (arg & CLOCK_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_polarity, neg);
- else if (arg & CLOCK_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_polarity, pos);
-
- if (arg & FRAME_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_polarity, normal);
- else if (arg & FRAME_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_polarity, inverted);
-
- if (arg & STATUS_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_polarity, normal);
- else if (arg & STATUS_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_polarity, inverted);
- break;
- case SSP_OPOLARITY:
- if (arg & CLOCK_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_driver, normal);
- else if (arg & CLOCK_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_driver, inverted);
-
- if (arg & FRAME_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_driver, normal);
- else if (arg & FRAME_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_driver, inverted);
-
- if (arg & STATUS_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_driver, normal);
- else if (arg & STATUS_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_driver, inverted);
- break;
- case SSP_SPI:
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl,
- disabled);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder,
- msb);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize,
- size8bit);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize,
- word);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype,
- normal);
- if (arg & SPI_SLAVE) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_polarity, inverted);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_polarity, neg);
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- mode, SLAVE_INPUT);
- } else {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_driver, inverted);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_driver, inverted);
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- mode, MASTER_OUTPUT);
- }
- break;
- case SSP_INBUFCHUNK:
-#if 0
- if (arg > port->in_buffer_size/NUM_IN_DESCR)
- return -EINVAL;
- port->inbufchunk = arg;
- /* Make sure in_buffer_size is a multiple of inbufchunk */
- port->in_buffer_size =
- (port->in_buffer_size/port->inbufchunk) *
- port->inbufchunk;
- DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n",
- port->inbufchunk, port->in_buffer_size));
- if (port->use_dma) {
- if (port->port_nbr == 0) {
- RESET_DMA(9);
- WAIT_DMA(9);
- } else {
- RESET_DMA(5);
- WAIT_DMA(5);
- }
- start_dma_in(port);
- }
-#endif
- break;
- default:
- return_val = -1;
- }
- /* Make sure we write the config without interruption */
- local_irq_save(flags);
- /* Set config and enable port */
- *port->ctrl_data = port->ctrl_data_shadow;
- nop(); nop(); nop(); nop();
- *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
- nop(); nop(); nop(); nop();
- if (dev)
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
- else
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
-
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
- /* Reset DMA. At readout from serial port the data could be shifted
- * one byte if not resetting DMA.
- */
- if (port->use_dma) {
- if (port->port_nbr == 0) {
- RESET_DMA(9);
- WAIT_DMA(9);
- } else {
- RESET_DMA(5);
- WAIT_DMA(5);
- }
- start_dma_in(port);
- }
- local_irq_restore(flags);
- return return_val;
-}
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- long ret;
-
- mutex_lock(&sync_serial_mutex);
- ret = sync_serial_ioctl_unlocked(file, cmd, arg);
- mutex_unlock(&sync_serial_mutex);
-
- return ret;
-}
-
-
-static ssize_t sync_serial_write(struct file *file, const char *buf,
- size_t count, loff_t *ppos)
-{
- int dev = MINOR(file_inode(file)->i_rdev);
- DECLARE_WAITQUEUE(wait, current);
- struct sync_port *port;
- unsigned long flags;
- unsigned long c, c1;
- unsigned long free_outp;
- unsigned long outp;
- unsigned long out_buffer;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n",
- port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
- /* Space to end of buffer */
- /*
- * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE
- * outp^ +out_count
- * ^free_outp
- * out_buffer 45<- c ->0123OUT_BUFFER_SIZE
- * +out_count outp^
- * free_outp
- *
- */
-
- /* Read variables that may be updated by interrupts */
- local_irq_save(flags);
- if (count > OUT_BUFFER_SIZE - port->out_count)
- count = OUT_BUFFER_SIZE - port->out_count;
-
- outp = (unsigned long)port->outp;
- free_outp = outp + port->out_count;
- local_irq_restore(flags);
- out_buffer = (unsigned long)port->out_buffer;
-
- /* Find out where and how much to write */
- if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
- free_outp -= OUT_BUFFER_SIZE;
- if (free_outp >= outp)
- c = out_buffer + OUT_BUFFER_SIZE - free_outp;
- else
- c = outp - free_outp;
- if (c > count)
- c = count;
-
- DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n",
- outp, free_outp, c));
- if (copy_from_user((void *)free_outp, buf, c))
- return -EFAULT;
-
- if (c != count) {
- buf += c;
- c1 = count - c;
- DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n",
- free_outp-out_buffer, c, c1));
- if (copy_from_user((void *)out_buffer, buf, c1))
- return -EFAULT;
- }
- local_irq_save(flags);
- port->out_count += count;
- local_irq_restore(flags);
-
- /* Make sure transmitter/receiver is running */
- if (!port->started) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
- running);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
- enable);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
- enable);
- port->started = 1;
- }
-
- *port->ctrl_data = port->ctrl_data_shadow;
-
- if (file->f_flags & O_NONBLOCK) {
- local_irq_save(flags);
- if (!port->tr_running) {
- if (!port->use_dma) {
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- *R_IRQ_MASK1_SET = 1 <<
- port->transmitter_ready_bit;
- } else
- start_dma(port,
- (unsigned char *volatile)port->outp, c);
- }
- local_irq_restore(flags);
- DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n",
- port->port_nbr, count));
- return count;
- }
-
- /* Sleep until all sent */
- add_wait_queue(&port->out_wait_q, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
- local_irq_save(flags);
- if (!port->tr_running) {
- if (!port->use_dma) {
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
- } else
- start_dma(port, port->outp, c);
- }
- local_irq_restore(flags);
- schedule();
- remove_wait_queue(&port->out_wait_q, &wait);
- if (signal_pending(current))
- return -EINTR;
-
- DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count));
- return count;
-}
-
-static ssize_t sync_serial_read(struct file *file, char *buf,
- size_t count, loff_t *ppos)
-{
- int dev = MINOR(file_inode(file)->i_rdev);
- int avail;
- struct sync_port *port;
- unsigned char *start;
- unsigned char *end;
- unsigned long flags;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n",
- dev, count, port->readp - port->flip,
- port->writep - port->flip, port->in_buffer_size));
-
- if (!port->started) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
- running);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
- enable);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
- enable);
- port->started = 1;
- }
- *port->ctrl_data = port->ctrl_data_shadow;
-
- /* Calculate number of available bytes */
- /* Save pointers to avoid that they are modified by interrupt */
- local_irq_save(flags);
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- local_irq_restore(flags);
- while (start == end && !port->full) {
- /* No data */
- if (file->f_flags & O_NONBLOCK)
- return -EAGAIN;
-
- wait_event_interruptible(port->in_wait_q,
- !(start == end && !port->full));
- if (signal_pending(current))
- return -EINTR;
-
- local_irq_save(flags);
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- local_irq_restore(flags);
- }
-
- /* Lazy read, never return wrapped data. */
- if (port->full)
- avail = port->in_buffer_size;
- else if (end > start)
- avail = end - start;
- else
- avail = port->flip + port->in_buffer_size - start;
-
- count = count > avail ? avail : count;
- if (copy_to_user(buf, start, count))
- return -EFAULT;
- /* Disable interrupts while updating readp */
- local_irq_save(flags);
- port->readp += count;
- if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
- port->readp = port->flip;
- port->full = 0;
- local_irq_restore(flags);
- DEBUGREAD(printk(KERN_DEBUG "r %d\n", count));
- return count;
-}
-
-static void send_word(struct sync_port *port)
-{
- switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize,
- port->ctrl_data_shadow)) {
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
- port->out_count--;
- *port->data_out = *port->outp++;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
- {
- int data = (*port->outp++) << 8;
- data |= *port->outp++;
- port->out_count -= 2;
- *port->data_out = data;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- }
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
- port->out_count -= 2;
- *port->data_out = *(unsigned short *)port->outp;
- port->outp += 2;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
- port->out_count -= 3;
- *port->data_out = *(unsigned int *)port->outp;
- port->outp += 3;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
- port->out_count -= 4;
- *port->data_out = *(unsigned int *)port->outp;
- port->outp += 4;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- }
-}
-
-
-static void start_dma(struct sync_port *port, const char *data, int count)
-{
- port->tr_running = 1;
- port->out_descr.hw_len = 0;
- port->out_descr.next = 0;
- port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
- port->out_descr.sw_len = count;
- port->out_descr.buf = virt_to_phys(data);
- port->out_descr.status = 0;
-
- *port->output_dma_first = virt_to_phys(&port->out_descr);
- *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
- DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n",
- (unsigned long)data, count));
-}
-
-static void start_dma_in(struct sync_port *port)
-{
- int i;
- unsigned long buf;
- port->writep = port->flip;
-
- if (port->writep > port->flip + port->in_buffer_size) {
- panic("Offset too large in sync serial driver\n");
- return;
- }
- buf = virt_to_phys(port->in_buffer);
- for (i = 0; i < NUM_IN_DESCR; i++) {
- port->in_descr[i].sw_len = port->inbufchunk;
- port->in_descr[i].ctrl = d_int;
- port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
- port->in_descr[i].buf = buf;
- port->in_descr[i].hw_len = 0;
- port->in_descr[i].status = 0;
- port->in_descr[i].fifo_len = 0;
- buf += port->inbufchunk;
- prepare_rx_descriptor(&port->in_descr[i]);
- }
- /* Link the last descriptor to the first */
- port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
- port->in_descr[i-1].ctrl |= d_eol;
- port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
- *port->input_dma_first = virt_to_phys(port->next_rx_desc);
- *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
-}
-
-#ifdef SYNC_SER_DMA
-static irqreturn_t tr_interrupt(int irq, void *dev_id)
-{
- unsigned long ireg = *R_IRQ_MASK2_RD;
- struct etrax_dma_descr *descr;
- unsigned int sentl;
- int handled = 0;
- int i;
-
- for (i = 0; i < NUMBER_OF_PORTS; i++) {
- struct sync_port *port = &ports[i];
- if (!port->enabled || !port->use_dma)
- continue;
-
- /* IRQ active for the port? */
- if (!(ireg & (1 << port->output_dma_bit)))
- continue;
-
- handled = 1;
-
- /* Clear IRQ */
- *port->output_dma_clr_irq =
- IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
- IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
-
- descr = &port->out_descr;
- if (!(descr->status & d_stop))
- sentl = descr->sw_len;
- else
- /* Otherwise find amount of data sent here */
- sentl = descr->hw_len;
-
- port->out_count -= sentl;
- port->outp += sentl;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- if (port->out_count) {
- int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
- if (c > port->out_count)
- c = port->out_count;
- DEBUGTXINT(printk(KERN_DEBUG
- "tx_int DMAWRITE %i %i\n", sentl, c));
- start_dma(port, port->outp, c);
- } else {
- DEBUGTXINT(printk(KERN_DEBUG
- "tx_int DMA stop %i\n", sentl));
- port->tr_running = 0;
- }
- /* wake up the waiting process */
- wake_up_interruptible(&port->out_wait_q);
- }
- return IRQ_RETVAL(handled);
-} /* tr_interrupt */
-
-static irqreturn_t rx_interrupt(int irq, void *dev_id)
-{
- unsigned long ireg = *R_IRQ_MASK2_RD;
- int i;
- int handled = 0;
-
- for (i = 0; i < NUMBER_OF_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || !port->use_dma)
- continue;
-
- if (!(ireg & (1 << port->input_dma_descr_bit)))
- continue;
-
- /* Descriptor interrupt */
- handled = 1;
- while (*port->input_dma_descr !=
- virt_to_phys(port->next_rx_desc)) {
- if (port->writep + port->inbufchunk > port->flip +
- port->in_buffer_size) {
- int first_size = port->flip +
- port->in_buffer_size - port->writep;
- memcpy(port->writep,
- phys_to_virt(port->next_rx_desc->buf),
- first_size);
- memcpy(port->flip,
- phys_to_virt(port->next_rx_desc->buf +
- first_size),
- port->inbufchunk - first_size);
- port->writep = port->flip +
- port->inbufchunk - first_size;
- } else {
- memcpy(port->writep,
- phys_to_virt(port->next_rx_desc->buf),
- port->inbufchunk);
- port->writep += port->inbufchunk;
- if (port->writep >= port->flip
- + port->in_buffer_size)
- port->writep = port->flip;
- }
- if (port->writep == port->readp)
- port->full = 1;
- prepare_rx_descriptor(port->next_rx_desc);
- port->next_rx_desc->ctrl |= d_eol;
- port->prev_rx_desc->ctrl &= ~d_eol;
- port->prev_rx_desc = phys_to_virt((unsigned)
- port->next_rx_desc);
- port->next_rx_desc = phys_to_virt((unsigned)
- port->next_rx_desc->next);
- /* Wake up the waiting process */
- wake_up_interruptible(&port->in_wait_q);
- *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
- cmd, restart);
- /* DMA has reached end of descriptor */
- *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
- clr_descr, do);
- }
- }
- return IRQ_RETVAL(handled);
-} /* rx_interrupt */
-#endif /* SYNC_SER_DMA */
-
-#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id)
-{
- int i;
- int handled = 0;
-
- for (i = 0; i < NUMBER_OF_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || port->use_dma)
- continue;
-
- /* Data received? */
- if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) {
- handled = 1;
- /* Read data */
- switch (port->ctrl_data_shadow &
- IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) {
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
- *port->writep++ =
- *(volatile char *)port->data_in;
- break;
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
- {
- int data = *(unsigned short *)port->data_in;
- *port->writep = (data & 0x0ff0) >> 4;
- *(port->writep + 1) = data & 0x0f;
- port->writep += 2;
- break;
- }
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
- *(unsigned short *)port->writep =
- *(volatile unsigned short *)port->data_in;
- port->writep += 2;
- break;
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
- *(unsigned int *)port->writep = *port->data_in;
- port->writep += 3;
- break;
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
- *(unsigned int *)port->writep = *port->data_in;
- port->writep += 4;
- break;
- }
-
- /* Wrap? */
- if (port->writep >= port->flip + port->in_buffer_size)
- port->writep = port->flip;
- if (port->writep == port->readp) {
- /* Receive buffer overrun, discard oldest */
- port->readp++;
- /* Wrap? */
- if (port->readp >= port->flip +
- port->in_buffer_size)
- port->readp = port->flip;
- }
- if (sync_data_avail(port) >= port->inbufchunk) {
- /* Wake up application */
- wake_up_interruptible(&port->in_wait_q);
- }
- }
-
- /* Transmitter ready? */
- if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) {
- if (port->out_count > 0) {
- /* More data to send */
- send_word(port);
- } else {
- /* Transmission finished */
- /* Turn off IRQ */
- *R_IRQ_MASK1_CLR = 1 <<
- port->transmitter_ready_bit;
- /* Wake up application */
- wake_up_interruptible(&port->out_wait_q);
- }
- }
- }
- return IRQ_RETVAL(handled);
-}
-#endif
-
-module_init(etrax_sync_serial_init);
diff --git a/arch/cris/arch-v10/kernel/Makefile b/arch/cris/arch-v10/kernel/Makefile
deleted file mode 100644
index 7ec04b4a285e..000000000000
--- a/arch/cris/arch-v10/kernel/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-extra-y := head.o
-
-
-obj-y := entry.o traps.o shadows.o debugport.o irq.o \
- process.o setup.o signal.o traps.o time.o ptrace.o \
- dma.o io_interface_mux.o
-
-obj-$(CONFIG_ETRAX_KGDB) += kgdb.o
-obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
-obj-$(CONFIG_MODULES) += crisksyms.o
-
-clean:
-
diff --git a/arch/cris/arch-v10/kernel/crisksyms.c b/arch/cris/arch-v10/kernel/crisksyms.c
deleted file mode 100644
index e1d897ed5b37..000000000000
--- a/arch/cris/arch-v10/kernel/crisksyms.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <asm/io.h>
-#include <arch/svinto.h>
-
-/* Export shadow registers for the CPU I/O pins */
-EXPORT_SYMBOL(genconfig_shadow);
-EXPORT_SYMBOL(port_pa_data_shadow);
-EXPORT_SYMBOL(port_pa_dir_shadow);
-EXPORT_SYMBOL(port_pb_data_shadow);
-EXPORT_SYMBOL(port_pb_dir_shadow);
-EXPORT_SYMBOL(port_pb_config_shadow);
-EXPORT_SYMBOL(port_g_data_shadow);
-
-/* Cache flush functions */
-EXPORT_SYMBOL(flush_etrax_cache);
-EXPORT_SYMBOL(prepare_rx_descriptor);
diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c
deleted file mode 100644
index d30834d4dd7e..000000000000
--- a/arch/cris/arch-v10/kernel/debugport.c
+++ /dev/null
@@ -1,560 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Serialport functions for debugging
- *
- * Copyright (c) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * Exports:
- * console_print_etrax(char *buf)
- * int getDebugChar()
- * putDebugChar(int)
- * enableDebugIRQ()
- * init_etrax_debug()
- *
- */
-
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/delay.h>
-#include <linux/tty.h>
-#include <arch/svinto.h>
-
-extern void reset_watchdog(void);
-
-struct dbg_port
-{
- unsigned int index;
- const volatile unsigned* read;
- volatile char* write;
- volatile unsigned* xoff;
- volatile char* baud;
- volatile char* tr_ctrl;
- volatile char* rec_ctrl;
- unsigned long irq;
- unsigned int started;
- unsigned long baudrate;
- unsigned char parity;
- unsigned int bits;
-};
-
-struct dbg_port ports[]=
-{
- {
- 0,
- R_SERIAL0_READ,
- R_SERIAL0_TR_DATA,
- R_SERIAL0_XOFF,
- R_SERIAL0_BAUD,
- R_SERIAL0_TR_CTRL,
- R_SERIAL0_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser0_data, set),
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 1,
- R_SERIAL1_READ,
- R_SERIAL1_TR_DATA,
- R_SERIAL1_XOFF,
- R_SERIAL1_BAUD,
- R_SERIAL1_TR_CTRL,
- R_SERIAL1_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser1_data, set),
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 2,
- R_SERIAL2_READ,
- R_SERIAL2_TR_DATA,
- R_SERIAL2_XOFF,
- R_SERIAL2_BAUD,
- R_SERIAL2_TR_CTRL,
- R_SERIAL2_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser2_data, set),
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 3,
- R_SERIAL3_READ,
- R_SERIAL3_TR_DATA,
- R_SERIAL3_XOFF,
- R_SERIAL3_BAUD,
- R_SERIAL3_TR_CTRL,
- R_SERIAL3_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser3_data, set),
- 0,
- 115200,
- 'N',
- 8
- }
-};
-
-#ifdef CONFIG_ETRAX_SERIAL
-extern struct tty_driver *serial_driver;
-#endif
-
-struct dbg_port* port =
-#if defined(CONFIG_ETRAX_DEBUG_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- &ports[3];
-#else
- NULL;
-#endif
-
-static struct dbg_port* kgdb_port =
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- &ports[3];
-#else
- NULL;
-#endif
-
-static void
-start_port(struct dbg_port* p)
-{
- unsigned long rec_ctrl = 0;
- unsigned long tr_ctrl = 0;
-
- if (!p)
- return;
-
- if (p->started)
- return;
- p->started = 1;
-
- if (p->index == 0)
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
- }
- else if (p->index == 1)
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
- }
- else if (p->index == 2)
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select);
- }
- else
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select);
- }
-
- *R_GEN_CONFIG = genconfig_shadow;
-
- *p->xoff =
- IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) |
- IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) |
- IO_FIELD(R_SERIAL0_XOFF, xoff_char, 0);
-
- switch (p->baudrate)
- {
- case 0:
- case 115200:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz);
- break;
- case 1200:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz);
- break;
- case 2400:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz);
- break;
- case 4800:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz);
- break;
- case 9600:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz);
- break;
- case 19200:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz);
- break;
- case 38400:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz);
- break;
- case 57600:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz);
- break;
- default:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz);
- break;
- }
-
- if (p->parity == 'E') {
- rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
- tr_ctrl =
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
- } else if (p->parity == 'O') {
- rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
- tr_ctrl =
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
- } else {
- rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, disable);
- tr_ctrl =
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable);
- }
- if (p->bits == 7)
- {
- rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
- tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
- }
- else
- {
- rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit);
- tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit);
- }
-
- *p->rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) |
- IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) |
- IO_STATE(R_SERIAL0_REC_CTRL, sampling, middle) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) |
- rec_ctrl;
-
- *p->tr_ctrl =
- IO_FIELD(R_SERIAL0_TR_CTRL, txd, 0) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) |
- IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) |
- IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, one_bit) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, normal) |
- tr_ctrl;
-}
-
-static void
-console_write_direct(struct console *co, const char *buf, unsigned int len)
-{
- int i;
- unsigned long flags;
-
- if (!port)
- return;
-
- local_irq_save(flags);
-
- /* Send data */
- for (i = 0; i < len; i++) {
- /* LF -> CRLF */
- if (buf[i] == '\n') {
- while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
- ;
- *port->write = '\r';
- }
- /* Wait until transmitter is ready and send.*/
- while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
- ;
- *port->write = buf[i];
- }
-
- /*
- * Feed the watchdog, otherwise it will reset the chip during boot.
- * The time to send an ordinary boot message line (10-90 chars)
- * varies between 1-8ms at 115200. What makes up for the additional
- * 90ms that allows the watchdog to bite?
- */
- reset_watchdog();
-
- local_irq_restore(flags);
-}
-
-static void
-console_write(struct console *co, const char *buf, unsigned int len)
-{
- if (!port)
- return;
-
- console_write_direct(co, buf, len);
-}
-
-/* legacy function */
-
-void
-console_print_etrax(const char *buf)
-{
- console_write(NULL, buf, strlen(buf));
-}
-
-/* Use polling to get a single character FROM the debug port */
-
-int
-getDebugChar(void)
-{
- unsigned long readval;
-
- if (!kgdb_port)
- return 0;
-
- do {
- readval = *kgdb_port->read;
- } while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail)));
-
- return (readval & IO_MASK(R_SERIAL0_READ, data_in));
-}
-
-/* Use polling to put a single character to the debug port */
-
-void
-putDebugChar(int val)
-{
- if (!kgdb_port)
- return;
-
- while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
- ;
- *kgdb_port->write = val;
-}
-
-/* Enable irq for receiving chars on the debug port, used by kgdb */
-
-void
-enableDebugIRQ(void)
-{
- if (!kgdb_port)
- return;
-
- *R_IRQ_MASK1_SET = kgdb_port->irq;
- /* use R_VECT_MASK directly, since we really bypass Linux normal
- * IRQ handling in kgdb anyway, we don't need to use enable_irq
- */
- *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
-
- *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
-}
-
-static int __init
-console_setup(struct console *co, char *options)
-{
- char* s;
-
- if (options) {
- port = &ports[co->index];
- port->baudrate = 115200;
- port->parity = 'N';
- port->bits = 8;
- port->baudrate = simple_strtoul(options, NULL, 10);
- s = options;
- while(*s >= '0' && *s <= '9')
- s++;
- if (*s) port->parity = *s++;
- if (*s) port->bits = *s++ - '0';
- port->started = 0;
- start_port(0);
- }
- return 0;
-}
-
-
-/* This is a dummy serial device that throws away anything written to it.
- * This is used when no debug output is wanted.
- */
-static struct tty_driver dummy_driver;
-
-static int dummy_open(struct tty_struct *tty, struct file * filp)
-{
- return 0;
-}
-
-static void dummy_close(struct tty_struct *tty, struct file * filp)
-{
-}
-
-static int dummy_write(struct tty_struct * tty,
- const unsigned char *buf, int count)
-{
- return count;
-}
-
-static int dummy_write_room(struct tty_struct *tty)
-{
- return 8192;
-}
-
-static const struct tty_operations dummy_ops = {
- .open = dummy_open,
- .close = dummy_close,
- .write = dummy_write,
- .write_room = dummy_write_room,
-};
-
-void __init
-init_dummy_console(void)
-{
- memset(&dummy_driver, 0, sizeof(struct tty_driver));
- dummy_driver.driver_name = "serial";
- dummy_driver.name = "ttyS";
- dummy_driver.major = TTY_MAJOR;
- dummy_driver.minor_start = 68;
- dummy_driver.num = 1; /* etrax100 has 4 serial ports */
- dummy_driver.type = TTY_DRIVER_TYPE_SERIAL;
- dummy_driver.subtype = SERIAL_TYPE_NORMAL;
- dummy_driver.init_termios = tty_std_termios;
- /* Normally B9600 default... */
- dummy_driver.init_termios.c_cflag =
- B115200 | CS8 | CREAD | HUPCL | CLOCAL;
- dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
- dummy_driver.init_termios.c_ispeed = 115200;
- dummy_driver.init_termios.c_ospeed = 115200;
-
- dummy_driver.ops = &dummy_ops;
- if (tty_register_driver(&dummy_driver))
- panic("Couldn't register dummy serial driver\n");
-}
-
-static struct tty_driver*
-etrax_console_device(struct console* co, int *index)
-{
- if (port)
- *index = port->index;
- else
- *index = 0;
-#ifdef CONFIG_ETRAX_SERIAL
- return port ? serial_driver : &dummy_driver;
-#else
- return &dummy_driver;
-#endif
-}
-
-static struct console ser_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : -1,
- cflag : 0,
- next : NULL
-};
-static struct console ser0_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 0,
- cflag : 0,
- next : NULL
-};
-
-static struct console ser1_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 1,
- cflag : 0,
- next : NULL
-};
-static struct console ser2_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 2,
- cflag : 0,
- next : NULL
-};
-static struct console ser3_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 3,
- cflag : 0,
- next : NULL
-};
-/*
- * Register console (for printk's etc)
- */
-
-int __init
-init_etrax_debug(void)
-{
- static int first = 1;
-
- if (!first) {
- unregister_console(&ser_console);
- register_console(&ser0_console);
- register_console(&ser1_console);
- register_console(&ser2_console);
- register_console(&ser3_console);
- init_dummy_console();
- return 0;
- }
-
- first = 0;
- register_console(&ser_console);
- start_port(port);
-#ifdef CONFIG_ETRAX_KGDB
- start_port(kgdb_port);
-#endif
- return 0;
-}
-__initcall(init_etrax_debug);
diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c
deleted file mode 100644
index c68e978def05..000000000000
--- a/arch/cris/arch-v10/kernel/dma.c
+++ /dev/null
@@ -1,288 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Wrapper for DMA channel allocator that updates DMA client muxing.
- * Copyright 2004-2007, Axis Communications AB
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-
-#include <asm/dma.h>
-#include <arch/svinto.h>
-#include <arch/system.h>
-
-/* Macro to access ETRAX 100 registers */
-#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_STATE_(reg##_, field##_, _##val)
-
-
-static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
-
-int cris_request_dma(unsigned int dmanr, const char * device_id,
- unsigned options, enum dma_owner owner)
-{
- unsigned long flags;
- unsigned long int gens;
- int fail = -EINVAL;
-
- if (dmanr >= MAX_DMA_CHANNELS) {
- printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr);
- return -EINVAL;
- }
-
- local_irq_save(flags);
- if (used_dma_channels[dmanr]) {
- local_irq_restore(flags);
- if (options & DMA_VERBOSE_ON_ERROR) {
- printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
- }
- if (options & DMA_PANIC_ON_ERROR) {
- panic("request_dma error!");
- }
- return -EBUSY;
- }
-
- gens = genconfig_shadow;
-
- switch(owner)
- {
- case dma_eth:
- if ((dmanr != NETWORK_TX_DMA_NBR) &&
- (dmanr != NETWORK_RX_DMA_NBR)) {
- printk(KERN_CRIT "Invalid DMA channel for eth\n");
- goto bail;
- }
- break;
- case dma_ser0:
- if (dmanr == SER0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma6, serial0);
- } else if (dmanr == SER0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma7, serial0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser0\n");
- goto bail;
- }
- break;
- case dma_ser1:
- if (dmanr == SER1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma8, serial1);
- } else if (dmanr == SER1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma9, serial1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser1\n");
- goto bail;
- }
- break;
- case dma_ser2:
- if (dmanr == SER2_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, serial2);
- } else if (dmanr == SER2_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, serial2);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser2\n");
- goto bail;
- }
- break;
- case dma_ser3:
- if (dmanr == SER3_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, serial3);
- } else if (dmanr == SER3_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, serial3);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser3\n");
- goto bail;
- }
- break;
- case dma_ata:
- if (dmanr == ATA_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, ata);
- } else if (dmanr == ATA_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, ata);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ata\n");
- goto bail;
- }
- break;
- case dma_ext0:
- if (dmanr == EXTDMA0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, extdma0);
- } else if (dmanr == EXTDMA0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, extdma0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ext0\n");
- goto bail;
- }
- break;
- case dma_ext1:
- if (dmanr == EXTDMA1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma6, extdma1);
- } else if (dmanr == EXTDMA1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma7, extdma1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ext1\n");
- goto bail;
- }
- break;
- case dma_int6:
- if (dmanr == MEM2MEM_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma7, intdma6);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for int6\n");
- goto bail;
- }
- break;
- case dma_int7:
- if (dmanr == MEM2MEM_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma6, intdma7);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for int7\n");
- goto bail;
- }
- break;
- case dma_usb:
- if (dmanr == USB_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma8, usb);
- } else if (dmanr == USB_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma9, usb);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for usb\n");
- goto bail;
- }
- break;
- case dma_scsi0:
- if (dmanr == SCSI0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, scsi0);
- } else if (dmanr == SCSI0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, scsi0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for scsi0\n");
- goto bail;
- }
- break;
- case dma_scsi1:
- if (dmanr == SCSI1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, scsi1);
- } else if (dmanr == SCSI1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, scsi1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for scsi1\n");
- goto bail;
- }
- break;
- case dma_par0:
- if (dmanr == PAR0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, par0);
- } else if (dmanr == PAR0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, par0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for par0\n");
- goto bail;
- }
- break;
- case dma_par1:
- if (dmanr == PAR1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, par1);
- } else if (dmanr == PAR1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, par1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for par1\n");
- goto bail;
- }
- break;
- default:
- printk(KERN_CRIT "Invalid DMA owner.\n");
- goto bail;
- }
-
- used_dma_channels[dmanr] = 1;
- used_dma_channels_users[dmanr] = device_id;
-
- {
- volatile int i;
- genconfig_shadow = gens;
- *R_GEN_CONFIG = genconfig_shadow;
- /* Wait 12 cycles before doing any DMA command */
- for(i = 6; i > 0; i--)
- nop();
- }
- fail = 0;
- bail:
- local_irq_restore(flags);
- return fail;
-}
-
-void cris_free_dma(unsigned int dmanr, const char * device_id)
-{
- unsigned long flags;
- if (dmanr >= MAX_DMA_CHANNELS) {
- printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr);
- return;
- }
-
- local_irq_save(flags);
- if (!used_dma_channels[dmanr]) {
- printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr);
- } else if (device_id != used_dma_channels_users[dmanr]) {
- printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr);
- } else {
- switch(dmanr)
- {
- case 0:
- *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) ==
- IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset));
- break;
- case 1:
- *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) ==
- IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset));
- break;
- case 2:
- *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) ==
- IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset));
- break;
- case 3:
- *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) ==
- IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset));
- break;
- case 4:
- *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) ==
- IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset));
- break;
- case 5:
- *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) ==
- IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset));
- break;
- case 6:
- *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) ==
- IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
- break;
- case 7:
- *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) ==
- IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset));
- break;
- case 8:
- *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) ==
- IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset));
- break;
- case 9:
- *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) ==
- IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset));
- break;
- }
- used_dma_channels[dmanr] = 0;
- }
- local_irq_restore(flags);
-}
-
-EXPORT_SYMBOL(cris_request_dma);
-EXPORT_SYMBOL(cris_free_dma);
diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S
deleted file mode 100644
index 1f066eebbd2b..000000000000
--- a/arch/cris/arch-v10/kernel/entry.S
+++ /dev/null
@@ -1,978 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/cris/entry.S
- *
- * Copyright (C) 2000, 2001, 2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- */
-
-/*
- * entry.S contains the system-call and fault low-level handling routines.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- * Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
- * if the order here is changed, it needs to be
- * updated in fork.c:copy_process, signal.c:do_signal,
- * ptrace.c and ptrace.h
- *
- */
-
-#include <linux/linkage.h>
-#include <linux/sys.h>
-#include <asm/unistd.h>
-#include <arch/sv_addr_ag.h>
-#include <asm/errno.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
- ;; functions exported from this file
-
- .globl system_call
- .globl ret_from_intr
- .globl ret_from_fork
- .globl ret_from_kernel_thread
- .globl resume
- .globl multiple_interrupt
- .globl hwbreakpoint
- .globl IRQ1_interrupt
- .globl spurious_interrupt
- .globl hw_bp_trigs
- .globl mmu_bus_fault
- .globl do_sigtrap
- .globl gdb_handle_breakpoint
- .globl sys_call_table
-
- ;; below are various parts of system_call which are not in the fast-path
-
-#ifdef CONFIG_PREEMPT
- ; Check if preemptive kernel scheduling should be done
-_resume_kernel:
- di
- ; Load current task struct
- movs.w -8192, $r0 ; THREAD_SIZE = 8192
- and.d $sp, $r0
- move.d [$r0+TI_preempt_count], $r10 ; Preemption disabled?
- bne _Rexit
- nop
-_need_resched:
- move.d [$r0+TI_flags], $r10
- btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set
- bpl _Rexit
- nop
- ; Ok, lets's do some preemptive kernel scheduling
- jsr preempt_schedule_irq
- ; Load new task struct
- movs.w -8192, $r0 ; THREAD_SIZE = 8192
- and.d $sp, $r0
- ; One more time (with new task)
- ba _need_resched
- nop
-#else
-#define _resume_kernel _Rexit
-#endif
-
- ; Called at exit from fork. schedule_tail must be called to drop
- ; spinlock if CONFIG_PREEMPT
-ret_from_fork:
- jsr schedule_tail
- ba ret_from_sys_call
- nop
-
-ret_from_kernel_thread:
- jsr schedule_tail
- move.d $r2, $r10 ; argument is here
- jsr $r1 ; call the payload
- moveq 0, $r9 ; no syscall restarts, TYVM...
- ba ret_from_sys_call
-
-ret_from_intr:
- ;; check for resched if preemptive kernel or if we're going back to user-mode
- ;; this test matches the user_regs(regs) macro
- ;; we cannot simply test $dccr, because that does not necessarily
- ;; reflect what mode we'll return into.
-
- move.d [$sp + PT_dccr], $r0; regs->dccr
- btstq 8, $r0 ; U-flag
- bpl _resume_kernel
- ; Note that di below is in delay slot
-
-_resume_userspace:
- di ; so need_resched and sigpending don't change
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- move.d [$r0+TI_flags], $r10 ; current->work
- and.d _TIF_WORK_MASK, $r10 ; is there any work to be done on return
- bne _work_pending
- nop
- ba _Rexit
- nop
-
- ;; The system_call is called by a BREAK instruction, which works like
- ;; an interrupt call but it stores the return PC in BRP instead of IRP.
- ;; Since we dont really want to have two epilogues (one for system calls
- ;; and one for interrupts) we push the contents of BRP instead of IRP in the
- ;; system call prologue, to make it look like an ordinary interrupt on the
- ;; stackframe.
- ;;
- ;; Since we can't have system calls inside interrupts, it should not matter
- ;; that we don't stack IRP.
- ;;
- ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,r13,mof,srp
- ;;
- ;; This function looks on the _surface_ like spaghetti programming, but it's
- ;; really designed so that the fast-path does not force cache-loading of non-used
- ;; instructions. Only the non-common cases cause the outlined code to run..
-
-system_call:
- ;; stack-frame similar to the irq heads, which is reversed in ret_from_sys_call
- move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
- push $srp
- push $dccr
- push $mof
- subq 14*4, $sp ; make room for r0-r13
- movem $r13, [$sp] ; push r0-r13
- push $r10 ; push orig_r10
- clear.d [$sp=$sp-4] ; frametype == 0, normal stackframe
-
- movs.w -ENOSYS, $r0
- move.d $r0, [$sp+PT_r10] ; put the default return value in r10 in the frame
-
- ;; check if this process is syscall-traced
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- move.d [$r0+TI_flags], $r0
- btstq TIF_SYSCALL_TRACE, $r0
- bmi _syscall_trace_entry
- nop
-
-_syscall_traced:
-
- ;; check for sanity in the requested syscall number
-
- cmpu.w NR_syscalls, $r9
- bcc ret_from_sys_call
- lslq 2, $r9 ; multiply by 4, in the delay slot
-
- ;; as a bonus 7th parameter, we give the location on the stack
- ;; of the register structure itself. some syscalls need this.
-
- push $sp
-
- ;; the parameter carrying registers r10, r11, r12 and 13 are intact.
- ;; the fifth and sixth parameters (if any) was in mof and srp
- ;; respectively, and we need to put them on the stack.
-
- push $srp
- push $mof
-
- jsr [$r9+sys_call_table] ; actually do the system call
- addq 3*4, $sp ; pop the mof, srp and regs parameters
- move.d $r10, [$sp+PT_r10] ; save the return value
-
- moveq 1, $r9 ; "parameter" to ret_from_sys_call to show it was a sys call
-
- ;; fall through into ret_from_sys_call to return
-
-ret_from_sys_call:
- ;; r9 is a parameter - if >=1 we came from a syscall, if 0, from an irq
-
- ;; get the current task-struct pointer (see top for defs)
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- di ; make sure need_resched and sigpending don't change
- move.d [$r0+TI_flags],$r1
- and.d _TIF_ALLWORK_MASK, $r1
- bne _syscall_exit_work
- nop
-
-_Rexit:
- ;; this epilogue MUST match the prologues in multiple_interrupt, irq.h and ptregs.h
- pop $r10 ; frametype
- bne _RBFexit ; was not CRIS_FRAME_NORMAL, handle otherwise
- addq 4, $sp ; skip orig_r10, in delayslot
- movem [$sp+], $r13 ; registers r0-r13
- pop $mof ; multiply overflow register
- pop $dccr ; condition codes
- pop $srp ; subroutine return pointer
- ;; now we have a 4-word SBFS frame which we do not want to restore
- ;; using RBF since it was not stacked with SBFS. instead we would like to
- ;; just get the PC value to restart it with, and skip the rest of
- ;; the frame.
- ;; Also notice that it's important to use instructions here that
- ;; keep the interrupts disabled (since we've already popped DCCR)
- move [$sp=$sp+16], $p8; pop the SBFS frame from the sp
- jmpu [$sp-16] ; return through the irp field in the sbfs frame
-
-_RBFexit:
- movem [$sp+], $r13 ; registers r0-r13, in delay slot
- pop $mof ; multiply overflow register
- pop $dccr ; condition codes
- pop $srp ; subroutine return pointer
- rbf [$sp+] ; return by popping the CPU status
-
- ;; We get here after doing a syscall if extra work might need to be done
- ;; perform syscall exit tracing if needed
-
-_syscall_exit_work:
- ;; $r0 contains current at this point and irq's are disabled
-
- move.d [$r0+TI_flags], $r1
- btstq TIF_SYSCALL_TRACE, $r1
- bpl _work_pending
- nop
-
- ei
-
- move.d $r9, $r1 ; preserve r9
- jsr do_syscall_trace
- move.d $r1, $r9
-
- ba _resume_userspace
- nop
-
-_work_pending:
- move.d [$r0+TI_flags], $r1
- btstq TIF_NEED_RESCHED, $r1
- bpl _work_notifysig ; was neither trace nor sched, must be signal/notify
- nop
-
-_work_resched:
- move.d $r9, $r1 ; preserve r9
- jsr schedule
- move.d $r1, $r9
- di
-
- move.d [$r0+TI_flags], $r1
- and.d _TIF_WORK_MASK, $r1; ignore the syscall trace counter
- beq _Rexit
- nop
- btstq TIF_NEED_RESCHED, $r1
- bmi _work_resched ; current->work.need_resched
- nop
-
-_work_notifysig:
- ;; deal with pending signals and notify-resume requests
-
- move.d $r9, $r10 ; do_notify_resume syscall/irq param
- move.d $sp, $r11 ; the regs param
- move.d $r1, $r12 ; the thread_info_flags parameter
- jsr do_notify_resume
-
- ba _Rexit
- nop
-
- ;; We get here as a sidetrack when we've entered a syscall with the
- ;; trace-bit set. We need to call do_syscall_trace and then continue
- ;; with the call.
-
-_syscall_trace_entry:
- ;; PT_r10 in the frame contains -ENOSYS as required, at this point
-
- jsr do_syscall_trace
-
- ;; now re-enter the syscall code to do the syscall itself
- ;; we need to restore $r9 here to contain the wanted syscall, and
- ;; the other parameter-bearing registers
-
- move.d [$sp+PT_r9], $r9
- move.d [$sp+PT_orig_r10], $r10 ; PT_r10 is already filled with -ENOSYS.
- move.d [$sp+PT_r11], $r11
- move.d [$sp+PT_r12], $r12
- move.d [$sp+PT_r13], $r13
- move [$sp+PT_mof], $mof
- move [$sp+PT_srp], $srp
-
- ba _syscall_traced
- nop
-
- ;; resume performs the actual task-switching, by switching stack pointers
- ;; input arguments: r10 = prev, r11 = next, r12 = thread offset in task struct
- ;; returns old current in r10
- ;;
- ;; TODO: see the i386 version. The switch_to which calls resume in our version
- ;; could really be an inline asm of this.
-
-resume:
- push $srp ; we keep the old/new PC on the stack
- add.d $r12, $r10 ; r10 = current tasks tss
- move $dccr, [$r10+THREAD_dccr]; save irq enable state
- di
-
- move $usp, [$r10+ THREAD_usp] ; save user-mode stackpointer
-
- ;; See copy_thread for the reason why register R9 is saved.
- subq 10*4, $sp
- movem $r9, [$sp] ; save non-scratch registers and R9.
-
- move.d $sp, [$r10+THREAD_ksp] ; save the kernel stack pointer for the old task
- move.d $sp, $r10 ; return last running task in r10
- and.d -8192, $r10 ; get thread_info from stackpointer
- move.d [$r10+TI_task], $r10 ; get task
- add.d $r12, $r11 ; find the new tasks tss
- move.d [$r11+THREAD_ksp], $sp ; switch into the new stackframe by restoring kernel sp
-
- movem [$sp+], $r9 ; restore non-scratch registers and R9.
-
- move [$r11+THREAD_usp], $usp ; restore user-mode stackpointer
-
- move [$r11+THREAD_dccr], $dccr ; restore irq enable status
- jump [$sp+] ; restore PC
-
- ;; This is the MMU bus fault handler.
- ;; It needs to stack the CPU status and overall is different
- ;; from the other interrupt handlers.
-
-mmu_bus_fault:
- ;; For refills we try to do a quick page table lookup. If it is
- ;; a real fault we let the mm subsystem handle it.
-
- ;; the first longword in the sbfs frame was the interrupted PC
- ;; which fits nicely with the "IRP" slot in pt_regs normally used to
- ;; contain the return address. used by Oops to print kernel errors.
- sbfs [$sp=$sp-16] ; push the internal CPU status
- push $dccr
- di
- subq 2*4, $sp
- movem $r1, [$sp]
- move.d [R_MMU_CAUSE], $r1
- ;; ETRAX 100LX TR89 bugfix: if the second half of an unaligned
- ;; write causes a MMU-fault, it will not be restarted correctly.
- ;; This could happen if a write crosses a page-boundary and the
- ;; second page is not yet COW'ed or even loaded. The workaround
- ;; is to clear the unaligned bit in the CPU status record, so
- ;; that the CPU will rerun both the first and second halves of
- ;; the instruction. This will not have any sideeffects unless
- ;; the first half goes to any device or memory that can't be
- ;; written twice, and which is mapped through the MMU.
- ;;
- ;; We only need to do this for writes.
- btstq 8, $r1 ; Write access?
- bpl 1f
- nop
- move.d [$sp+16], $r0 ; Clear unaligned bit in csrinstr
- and.d ~(1<<5), $r0
- move.d $r0, [$sp+16]
-1: btstq 12, $r1 ; Refill?
- bpl 2f
- lsrq 24, $r1 ; Get PGD index (bit 24-31)
- move.d [current_pgd], $r0 ; PGD for the current process
- move.d [$r0+$r1.d], $r0 ; Get PMD
- beq 2f
- nop
- and.w PAGE_MASK, $r0 ; Remove PMD flags
- move.d [R_MMU_CAUSE], $r1
- lsrq PAGE_SHIFT, $r1
- and.d 0x7ff, $r1 ; Get PTE index into PGD (bit 13-23)
- move.d [$r0+$r1.d], $r1 ; Get PTE
- beq 2f
- nop
- ;; Store in TLB
- move.d $r1, [R_TLB_LO]
- ;; Return
- movem [$sp+], $r1
- pop $dccr
- rbf [$sp+] ; return by popping the CPU status
-
-2: ; PMD or PTE missing, let the mm subsystem fix it up.
- movem [$sp+], $r1
- pop $dccr
-
- ; Ok, not that easy, pass it on to the mm subsystem
- ; The MMU status record is now on the stack
- push $srp ; make a stackframe similar to pt_regs
- push $dccr
- push $mof
- di
- subq 14*4, $sp
- movem $r13, [$sp]
- push $r10 ; dummy orig_r10
- moveq 1, $r10
- push $r10 ; frametype == 1, BUSFAULT frame type
-
- move.d $sp, $r10 ; pt_regs argument to handle_mmu_bus_fault
-
- jsr handle_mmu_bus_fault ; in arch/cris/arch-v10/mm/fault.c
-
- ;; now we need to return through the normal path, we cannot just
- ;; do the RBFexit since we might have killed off the running
- ;; process due to a SEGV, scheduled due to a page blocking or
- ;; whatever.
-
- moveq 0, $r9 ; busfault is equivalent to an irq
-
- ba ret_from_intr
- nop
-
- ;; special handlers for breakpoint and NMI
-hwbreakpoint:
- push $dccr
- di
- push $r10
- push $r11
- move.d [hw_bp_trig_ptr],$r10
- move $brp,$r11
- move.d $r11,[$r10+]
- move.d $r10,[hw_bp_trig_ptr]
-1: pop $r11
- pop $r10
- pop $dccr
- retb
- nop
-
-IRQ1_interrupt:
- ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
- move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
- push $srp
- push $dccr
- push $mof
- di
- subq 14*4, $sp
- movem $r13, [$sp]
- push $r10 ; push orig_r10
- clear.d [$sp=$sp-4] ; frametype == 0, normal frame
-
- ;; If there is a glitch on the NMI pin shorter than ~100ns
- ;; (i.e. non-active by the time we get here) then the nmi_pin bit
- ;; in R_IRQ_MASK0_RD will already be cleared. The watchdog_nmi bit
- ;; is cleared by us however (when feeding the watchdog), which is why
- ;; we use that bit to determine what brought us here.
-
- move.d [R_IRQ_MASK0_RD], $r1 ; External NMI or watchdog?
- and.d (1<<30), $r1
- bne wdog
- move.d $sp, $r10
- jsr handle_nmi
- setf m ; Enable NMI again
- ba _Rexit ; Return the standard way
- nop
-wdog:
-#if defined(CONFIG_ETRAX_WATCHDOG)
-;; Check if we're waiting for reset to happen, as signalled by
-;; hard_reset_now setting cause_of_death to a magic value. If so, just
-;; get stuck until reset happens.
- .comm cause_of_death, 4 ;; Don't declare this anywhere.
- move.d [cause_of_death], $r10
- cmp.d 0xbedead, $r10
-_killed_by_death:
- beq _killed_by_death
- nop
-
-;; We'll see this in ksymoops dumps.
-Watchdog_bite:
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- ;; We just restart the watchdog here to be sure we dont get
- ;; hit while printing the watchdogmsg below
- ;; This restart is compatible with the rest of the C-code, so
- ;; the C-code can keep restarting the watchdog after this point.
- ;; The non-NICE_DOGGY code below though, disables the possibility
- ;; to restart since it changes the watchdog key, to avoid any
- ;; buggy loops etc. keeping the watchdog alive after this.
- jsr reset_watchdog
-#else
-
-;; We need to extend the 3.3ms after the NMI at watchdog bite, so we have
-;; time for an oops-dump over a 115k2 serial wire. Another 100ms should do.
-
-;; Change the watchdog key to an arbitrary 3-bit value and restart the
-;; watchdog.
-#define WD_INIT 2
- moveq IO_FIELD (R_WATCHDOG, key, WD_INIT), $r10
- move.d R_WATCHDOG, $r11
-
- move.d $r10, [$r11]
- moveq IO_FIELD (R_WATCHDOG, key, \
- IO_EXTRACT (R_WATCHDOG, key, \
- IO_MASK (R_WATCHDOG, key)) \
- ^ WD_INIT) \
- | IO_STATE (R_WATCHDOG, enable, start), $r10
- move.d $r10, [$r11]
-
-#endif
-
-;; Note that we don't do "setf m" here (or after two necessary NOPs),
-;; since *not* doing that saves us from re-entrancy checks. We don't want
-;; to get here again due to possible subsequent NMIs; we want the watchdog
-;; to reset us.
-
- move.d _watchdogmsg,$r10
- jsr printk
-
- move.d $sp, $r10
- jsr watchdog_bite_hook
-
-;; This nop is here so we see the "Watchdog_bite" label in ksymoops dumps
-;; rather than "spurious_interrupt".
- nop
-;; At this point we drop down into spurious_interrupt, which will do a
-;; hard reset.
-
- .section .rodata,"a"
-_watchdogmsg:
- .ascii "Oops: bitten by watchdog\n\0"
- .previous
-
-#endif /* CONFIG_ETRAX_WATCHDOG */
-
-spurious_interrupt:
- di
- jump hard_reset_now
-
- ;; this handles the case when multiple interrupts arrive at the same time
- ;; we jump to the first set interrupt bit in a priority fashion
- ;; the hardware will call the unserved interrupts after the handler finishes
-
-multiple_interrupt:
- ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
- move $irp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
- push $srp
- push $dccr
- push $mof
- di
- subq 14*4, $sp
- movem $r13, [$sp]
- push $r10 ; push orig_r10
- clear.d [$sp=$sp-4] ; frametype == 0, normal frame
-
- move.d $sp, $r10
- jsr do_multiple_IRQ
-
- jump ret_from_intr
-
-do_sigtrap:
- ;;
- ;; SIGTRAP the process that executed the break instruction.
- ;; Make a frame that Rexit in entry.S expects.
- ;;
- move $brp, [$sp=$sp-16] ; Push BRP while faking a cpu status record.
- push $srp ; Push subroutine return pointer.
- push $dccr ; Push condition codes.
- push $mof ; Push multiply overflow reg.
- di ; Need to disable irq's at this point.
- subq 14*4, $sp ; Make room for r0-r13.
- movem $r13, [$sp] ; Push the r0-r13 registers.
- push $r10 ; Push orig_r10.
- clear.d [$sp=$sp-4] ; Frametype - this is a normal stackframe.
-
- movs.w -8192,$r9 ; THREAD_SIZE == 8192
- and.d $sp, $r9
- move.d [$r9+TI_task], $r10
- move.d [$r10+TASK_pid], $r10 ; current->pid as arg1.
- moveq 5, $r11 ; SIGTRAP as arg2.
- jsr sys_kill
- jump ret_from_intr ; Use the return routine for interrupts.
-
-gdb_handle_breakpoint:
- push $dccr
- push $r0
-#ifdef CONFIG_ETRAX_KGDB
- move $dccr, $r0 ; U-flag not affected by previous insns.
- btstq 8, $r0 ; Test the U-flag.
- bmi _ugdb_handle_breakpoint ; Go to user mode debugging.
- nop ; Empty delay slot (cannot pop r0 here).
- pop $r0 ; Restore r0.
- ba kgdb_handle_breakpoint ; Go to kernel debugging.
- pop $dccr ; Restore dccr in delay slot.
-#endif
-
-_ugdb_handle_breakpoint:
- move $brp, $r0 ; Use r0 temporarily for calculation.
- subq 2, $r0 ; Set to address of previous instruction.
- move $r0, $brp
- pop $r0 ; Restore r0.
- ba do_sigtrap ; SIGTRAP the offending process.
- pop $dccr ; Restore dccr in delay slot.
-
- .data
-
-hw_bp_trigs:
- .space 64*4
-hw_bp_trig_ptr:
- .dword hw_bp_trigs
-
- .section .rodata,"a"
-sys_call_table:
- .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys( */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old sys_olduname holder */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_sgetmask
- .long sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_select /* was old_select in Linux/E100 */
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_old_readdir
- .long sys_old_mmap /* 90 */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* sys_ioperm in i386 */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* old sys_uname holder */
- .long sys_ni_syscall /* 110 */ /* sys_iopl in i386 */
- .long sys_vhangup
- .long sys_ni_syscall /* old "idle" system call */
- .long sys_ni_syscall /* vm86old in i386 */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* sys_modify_ldt */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* sys_vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* old nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap2 /* mmap_pgoff */
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall /* sys_set_thread_area */
- .long sys_ni_syscall /* sys_get_thread_area */
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_ni_syscall /* sys_mbind */
- .long sys_ni_syscall /* 275 sys_get_mempolicy */
- .long sys_ni_syscall /* sys_set_mempolicy */
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate
- .long sys_timerfd_settime /* 325 */
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1
- .long sys_dup3 /* 330 */
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev
- .long sys_setns /* 335 */
- .long sys_name_to_handle_at
- .long sys_open_by_handle_at
- .long sys_rt_tgsigqueueinfo
- .long sys_perf_event_open
- .long sys_recvmmsg /* 340 */
- .long sys_accept4
- .long sys_fanotify_init
- .long sys_fanotify_mark
- .long sys_prlimit64
- .long sys_clock_adjtime /* 345 */
- .long sys_syncfs
- .long sys_sendmmsg
- .long sys_process_vm_readv
- .long sys_process_vm_writev
- .long sys_kcmp /* 350 */
- .long sys_finit_module
- .long sys_sched_setattr
- .long sys_sched_getattr
- .long sys_renameat2
- .long sys_seccomp /* 355 */
- .long sys_getrandom
- .long sys_memfd_create
- .long sys_bpf
- .long sys_execveat
-
- /*
- * NOTE!! This doesn't have to be exact - we just have
- * to make sure we have _enough_ of the "sys_ni_syscall"
- * entries. Don't panic if you notice that this hasn't
- * been shrunk every time we add a new system call.
- */
-
- .rept NR_syscalls-(.-sys_call_table)/4
- .long sys_ni_syscall
- .endr
-
diff --git a/arch/cris/arch-v10/kernel/fasttimer.c b/arch/cris/arch-v10/kernel/fasttimer.c
deleted file mode 100644
index 94abbff557ff..000000000000
--- a/arch/cris/arch-v10/kernel/fasttimer.c
+++ /dev/null
@@ -1,835 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/fasttimer.c
- *
- * Fast timers for ETRAX100/ETRAX100LX
- *
- * Copyright (C) 2000-2007 Axis Communications AB, Lund, Sweden
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-
-#include <asm/segment.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/delay.h>
-
-#include <arch/svinto.h>
-#include <asm/fasttimer.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-
-#define DEBUG_LOG_INCLUDED
-#define FAST_TIMER_LOG
-/* #define FAST_TIMER_TEST */
-
-#define FAST_TIMER_SANITY_CHECKS
-
-#ifdef FAST_TIMER_SANITY_CHECKS
-static int sanity_failed;
-#endif
-
-#define D1(x)
-#define D2(x)
-#define DP(x)
-
-static unsigned int fast_timer_running;
-static unsigned int fast_timers_added;
-static unsigned int fast_timers_started;
-static unsigned int fast_timers_expired;
-static unsigned int fast_timers_deleted;
-static unsigned int fast_timer_is_init;
-static unsigned int fast_timer_ints;
-
-struct fast_timer *fast_timer_list = NULL;
-
-#ifdef DEBUG_LOG_INCLUDED
-#define DEBUG_LOG_MAX 128
-static const char * debug_log_string[DEBUG_LOG_MAX];
-static unsigned long debug_log_value[DEBUG_LOG_MAX];
-static unsigned int debug_log_cnt;
-static unsigned int debug_log_cnt_wrapped;
-
-#define DEBUG_LOG(string, value) \
-{ \
- unsigned long log_flags; \
- local_irq_save(log_flags); \
- debug_log_string[debug_log_cnt] = (string); \
- debug_log_value[debug_log_cnt] = (unsigned long)(value); \
- if (++debug_log_cnt >= DEBUG_LOG_MAX) \
- { \
- debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \
- debug_log_cnt_wrapped = 1; \
- } \
- local_irq_restore(log_flags); \
-}
-#else
-#define DEBUG_LOG(string, value)
-#endif
-
-
-/* The frequencies for index = clkselx number in R_TIMER_CTRL */
-#define NUM_TIMER_FREQ 15
-#define MAX_USABLE_TIMER_FREQ 7
-#define MAX_DELAY_US 853333L
-const unsigned long timer_freq_100[NUM_TIMER_FREQ] =
-{
- 3, /* 0 3333 - 853333 us */
- 6, /* 1 1666 - 426666 us */
- 12, /* 2 833 - 213333 us */
- 24, /* 3 416 - 106666 us */
- 48, /* 4 208 - 53333 us */
- 96, /* 5 104 - 26666 us */
- 192, /* 6 52 - 13333 us */
- 384, /* 7 26 - 6666 us */
- 576,
- 1152,
- 2304,
- 4608,
- 9216,
- 18432,
- 62500,
- /* 15 = cascade */
-};
-#define NUM_TIMER_STATS 16
-#ifdef FAST_TIMER_LOG
-struct fast_timer timer_added_log[NUM_TIMER_STATS];
-struct fast_timer timer_started_log[NUM_TIMER_STATS];
-struct fast_timer timer_expired_log[NUM_TIMER_STATS];
-#endif
-
-int timer_div_settings[NUM_TIMER_STATS];
-int timer_freq_settings[NUM_TIMER_STATS];
-int timer_delay_settings[NUM_TIMER_STATS];
-
-/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */
-inline void do_gettimeofday_fast(struct fasttime_t *tv)
-{
- tv->tv_jiff = jiffies;
- tv->tv_usec = GET_JIFFIES_USEC();
-}
-
-inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1)
-{
- /* Compare jiffies. Takes care of wrapping */
- if (time_before(t0->tv_jiff, t1->tv_jiff))
- return -1;
- else if (time_after(t0->tv_jiff, t1->tv_jiff))
- return 1;
-
- /* Compare us */
- if (t0->tv_usec < t1->tv_usec)
- return -1;
- else if (t0->tv_usec > t1->tv_usec)
- return 1;
- return 0;
-}
-
-inline void start_timer1(unsigned long delay_us)
-{
- int freq_index = 0; /* This is the lowest resolution */
- unsigned long upper_limit = MAX_DELAY_US;
-
- unsigned long div;
- /* Start/Restart the timer to the new shorter value */
- /* t = 1/freq = 1/19200 = 53us
- * T=div*t, div = T/t = delay_us*freq/1000000
- */
-#if 1 /* Adaptive timer settings */
- while (delay_us < upper_limit && freq_index < MAX_USABLE_TIMER_FREQ)
- {
- freq_index++;
- upper_limit >>= 1; /* Divide by 2 using shift */
- }
- if (freq_index > 0)
- {
- freq_index--;
- }
-#else
- freq_index = 6;
-#endif
- div = delay_us * timer_freq_100[freq_index]/10000;
- if (div < 2)
- {
- /* Maybe increase timer freq? */
- div = 2;
- }
- if (div > 255)
- {
- div = 0; /* This means 256, the max the timer takes */
- /* If a longer timeout than the timer can handle is used,
- * then we must restart it when it goes off.
- */
- }
-
- timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = div;
- timer_freq_settings[fast_timers_started % NUM_TIMER_STATS] = freq_index;
- timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
-
- D1(printk(KERN_DEBUG "start_timer1 : %d us freq: %i div: %i\n",
- delay_us, freq_index, div));
- /* Clear timer1 irq */
- *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr);
-
- /* Set timer values */
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- (r_timer_ctrl_shadow &
- ~IO_MASK(R_TIMER_CTRL, timerdiv1) &
- ~IO_MASK(R_TIMER_CTRL, tm1) &
- ~IO_MASK(R_TIMER_CTRL, clksel1)) |
- IO_FIELD(R_TIMER_CTRL, timerdiv1, div) |
- IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
- IO_FIELD(R_TIMER_CTRL, clksel1, freq_index ); /* 6=c19k2Hz */
-
- /* Ack interrupt */
- *R_TIMER_CTRL = r_timer_ctrl_shadow |
- IO_STATE(R_TIMER_CTRL, i1, clr);
-
- /* Start timer */
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) |
- IO_STATE(R_TIMER_CTRL, tm1, run);
-
- /* Enable timer1 irq */
- *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer1, set);
- fast_timers_started++;
- fast_timer_running = 1;
-}
-
-/* In version 1.4 this function takes 27 - 50 us */
-void start_one_shot_timer(struct fast_timer *t,
- fast_timer_function_type *function,
- unsigned long data,
- unsigned long delay_us,
- const char *name)
-{
- unsigned long flags;
- struct fast_timer *tmp;
-
- D1(printk("sft %s %d us\n", name, delay_us));
-
- local_irq_save(flags);
-
- do_gettimeofday_fast(&t->tv_set);
- tmp = fast_timer_list;
-
-#ifdef FAST_TIMER_SANITY_CHECKS
- /* Check so this is not in the list already... */
- while (tmp != NULL) {
- if (tmp == t) {
- printk(KERN_WARNING "timer name: %s data: "
- "0x%08lX already in list!\n", name, data);
- sanity_failed++;
- goto done;
- } else
- tmp = tmp->next;
- }
- tmp = fast_timer_list;
-#endif
-
- t->delay_us = delay_us;
- t->function = function;
- t->data = data;
- t->name = name;
-
- t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000;
- t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ;
- if (t->tv_expires.tv_usec > 1000000)
- {
- t->tv_expires.tv_usec -= 1000000;
- t->tv_expires.tv_jiff += HZ;
- }
-#ifdef FAST_TIMER_LOG
- timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_added++;
-
- /* Check if this should timeout before anything else */
- if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0)
- {
- /* Put first in list and modify the timer value */
- t->prev = NULL;
- t->next = fast_timer_list;
- if (fast_timer_list)
- {
- fast_timer_list->prev = t;
- }
- fast_timer_list = t;
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer1(delay_us);
- } else {
- /* Put in correct place in list */
- while (tmp->next && fasttime_cmp(&t->tv_expires,
- &tmp->next->tv_expires) > 0)
- {
- tmp = tmp->next;
- }
- /* Insert t after tmp */
- t->prev = tmp;
- t->next = tmp->next;
- if (tmp->next)
- {
- tmp->next->prev = t;
- }
- tmp->next = t;
- }
-
- D2(printk("start_one_shot_timer: %d us done\n", delay_us));
-
-done:
- local_irq_restore(flags);
-} /* start_one_shot_timer */
-
-static inline int fast_timer_pending (const struct fast_timer * t)
-{
- return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list);
-}
-
-static inline int detach_fast_timer (struct fast_timer *t)
-{
- struct fast_timer *next, *prev;
- if (!fast_timer_pending(t))
- return 0;
- next = t->next;
- prev = t->prev;
- if (next)
- next->prev = prev;
- if (prev)
- prev->next = next;
- else
- fast_timer_list = next;
- fast_timers_deleted++;
- return 1;
-}
-
-int del_fast_timer(struct fast_timer * t)
-{
- unsigned long flags;
- int ret;
-
- local_irq_save(flags);
- ret = detach_fast_timer(t);
- t->next = t->prev = NULL;
- local_irq_restore(flags);
- return ret;
-} /* del_fast_timer */
-
-
-/* Interrupt routines or functions called in interrupt context */
-
-/* Timer 1 interrupt handler */
-
-static irqreturn_t
-timer1_handler(int irq, void *dev_id)
-{
- struct fast_timer *t;
- unsigned long flags;
-
- /* We keep interrupts disabled not only when we modify the
- * fast timer list, but any time we hold a reference to a
- * timer in the list, since del_fast_timer may be called
- * from (another) interrupt context. Thus, the only time
- * when interrupts are enabled is when calling the timer
- * callback function.
- */
- local_irq_save(flags);
-
- /* Clear timer1 irq */
- *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr);
-
- /* First stop timer, then ack interrupt */
- /* Stop timer */
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) |
- IO_STATE(R_TIMER_CTRL, tm1, stop_ld);
-
- /* Ack interrupt */
- *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i1, clr);
-
- fast_timer_running = 0;
- fast_timer_ints++;
-
- t = fast_timer_list;
- while (t)
- {
- struct fasttime_t tv;
- fast_timer_function_type *f;
- unsigned long d;
-
- /* Has it really expired? */
- do_gettimeofday_fast(&tv);
- D1(printk(KERN_DEBUG "t: %is %06ius\n",
- tv.tv_jiff, tv.tv_usec));
-
- if (fasttime_cmp(&t->tv_expires, &tv) <= 0)
- {
- /* Yes it has expired */
-#ifdef FAST_TIMER_LOG
- timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_expired++;
-
- /* Remove this timer before call, since it may reuse the timer */
- if (t->prev)
- {
- t->prev->next = t->next;
- }
- else
- {
- fast_timer_list = t->next;
- }
- if (t->next)
- {
- t->next->prev = t->prev;
- }
- t->prev = NULL;
- t->next = NULL;
-
- /* Save function callback data before enabling
- * interrupts, since the timer may be removed and
- * we don't know how it was allocated
- * (e.g. ->function and ->data may become overwritten
- * after deletion if the timer was stack-allocated).
- */
- f = t->function;
- d = t->data;
-
- if (f != NULL) {
- /* Run callback with interrupts enabled. */
- local_irq_restore(flags);
- f(d);
- local_irq_save(flags);
- } else
- DEBUG_LOG("!timer1 %i function==NULL!\n", fast_timer_ints);
- }
- else
- {
- /* Timer is to early, let's set it again using the normal routines */
- D1(printk(".\n"));
- }
-
- if ((t = fast_timer_list) != NULL)
- {
- /* Start next timer.. */
- long us = 0;
- struct fasttime_t tv;
-
- do_gettimeofday_fast(&tv);
-
- /* time_after_eq takes care of wrapping */
- if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff))
- us = ((t->tv_expires.tv_jiff - tv.tv_jiff) *
- 1000000 / HZ + t->tv_expires.tv_usec -
- tv.tv_usec);
-
- if (us > 0)
- {
- if (!fast_timer_running)
- {
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer1(us);
- }
- break;
- }
- else
- {
- /* Timer already expired, let's handle it better late than never.
- * The normal loop handles it
- */
- D1(printk("e! %d\n", us));
- }
- }
- }
-
- local_irq_restore(flags);
-
- if (!t)
- {
- D1(printk("t1 stop!\n"));
- }
-
- return IRQ_HANDLED;
-}
-
-static void wake_up_func(unsigned long data)
-{
- wait_queue_head_t *sleep_wait_p = (wait_queue_head_t *)data;
- wake_up(sleep_wait_p);
-}
-
-
-/* Useful API */
-
-void schedule_usleep(unsigned long us)
-{
- struct fast_timer t;
- wait_queue_head_t sleep_wait;
- init_waitqueue_head(&sleep_wait);
-
- D1(printk("schedule_usleep(%d)\n", us));
- start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us,
- "usleep");
- /* Uninterruptible sleep on the fast timer. (The condition is somewhat
- * redundant since the timer is what wakes us up.) */
- wait_event(sleep_wait, !fast_timer_pending(&t));
-
- D1(printk("done schedule_usleep(%d)\n", us));
-}
-
-#ifdef CONFIG_PROC_FS
-/* This value is very much based on testing */
-#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
-
-static int proc_fasttimer_show(struct seq_file *m, void *v)
-{
- unsigned long flags;
- int i = 0;
- int num_to_show;
- struct fasttime_t tv;
- struct fast_timer *t, *nextt;
-
- do_gettimeofday_fast(&tv);
-
- seq_printf(m, "Fast timers added: %i\n", fast_timers_added);
- seq_printf(m, "Fast timers started: %i\n", fast_timers_started);
- seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints);
- seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired);
- seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted);
- seq_printf(m, "Fast timer running: %s\n",
- fast_timer_running ? "yes" : "no");
- seq_printf(m, "Current time: %lu.%06lu\n",
- (unsigned long)tv.tv_jiff,
- (unsigned long)tv.tv_usec);
-#ifdef FAST_TIMER_SANITY_CHECKS
- seq_printf(m, "Sanity failed: %i\n", sanity_failed);
-#endif
- seq_putc(m, '\n');
-
-#ifdef DEBUG_LOG_INCLUDED
- {
- int end_i = debug_log_cnt;
- i = 0;
-
- if (debug_log_cnt_wrapped)
- i = debug_log_cnt;
-
- while (i != end_i || debug_log_cnt_wrapped) {
- seq_printf(m, debug_log_string[i], debug_log_value[i]);
- if (seq_has_overflowed(m))
- return 0;
- i = (i+1) % DEBUG_LOG_MAX;
- }
- }
- seq_putc(m, '\n');
-#endif
-
- num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers started: %i\n", fast_timers_started);
- for (i = 0; i < num_to_show; i++) {
- int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
-
-#if 1 //ndef FAST_TIMER_LOG
- seq_printf(m, "div: %i freq: %i delay: %i\n",
- timer_div_settings[cur],
- timer_freq_settings[cur],
- timer_delay_settings[cur]);
-#endif
-#ifdef FAST_TIMER_LOG
- t = &timer_started_log[cur];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
-#endif
- }
- seq_putc(m, '\n');
-
-#ifdef FAST_TIMER_LOG
- num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers added: %i\n", fast_timers_added);
- for (i = 0; i < num_to_show; i++) {
- t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-
- num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers expired: %i\n", fast_timers_expired);
- for (i = 0; i < num_to_show; i++) {
- t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-#endif
-
- seq_puts(m, "Active timers:\n");
- local_irq_save(flags);
- t = fast_timer_list;
- while (t) {
- nextt = t->next;
- local_irq_restore(flags);
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- local_irq_save(flags);
- if (t->next != nextt)
- printk(KERN_WARNING "timer removed!\n");
- t = nextt;
- }
- local_irq_restore(flags);
-
- return 0;
-}
-
-static int proc_fasttimer_open(struct inode *inode, struct file *file)
-{
- return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE);
-}
-
-static const struct file_operations proc_fasttimer_fops = {
- .open = proc_fasttimer_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-#endif /* PROC_FS */
-
-#ifdef FAST_TIMER_TEST
-static volatile unsigned long i = 0;
-static volatile int num_test_timeout = 0;
-static struct fast_timer tr[10];
-static int exp_num[10];
-
-static struct fasttime_t tv_exp[100];
-
-static void test_timeout(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
-
- num_test_timeout++;
-}
-
-static void test_timeout1(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
- if (data < 7)
- {
- start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1");
- i++;
- }
- num_test_timeout++;
-}
-
-DP(
-static char buf0[2000];
-static char buf1[2000];
-static char buf2[2000];
-static char buf3[2000];
-static char buf4[2000];
-);
-
-static char buf5[6000];
-static int j_u[1000];
-
-static void fast_timer_test(void)
-{
- int prev_num;
- int j;
-
- struct fasttime_t tv, tv0, tv1, tv2;
-
- printk("fast_timer_test() start\n");
- do_gettimeofday_fast(&tv);
-
- for (j = 0; j < 1000; j++)
- {
- j_u[j] = GET_JIFFIES_USEC();
- }
- for (j = 0; j < 100; j++)
- {
- do_gettimeofday_fast(&tv_exp[j]);
- }
- printk(KERN_DEBUG "fast_timer_test() %is %06i\n",
- tv.tv_jiff, tv.tv_usec);
-
- for (j = 0; j < 1000; j++)
- {
- printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
- j += 4;
- }
- for (j = 0; j < 100; j++)
- {
- printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n",
- tv_exp[j].tv_jiff, tv_exp[j].tv_usec,
- tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec,
- tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec,
- tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec,
- tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec);
- j += 4;
- }
- do_gettimeofday_fast(&tv0);
- start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0");
- DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1");
- DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2");
- DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3");
- DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx");
- DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0));
- i++;
- do_gettimeofday_fast(&tv1);
-
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
-
- prev_num = num_test_timeout;
- while (num_test_timeout < i)
- {
- if (num_test_timeout != prev_num)
- {
- prev_num = num_test_timeout;
- }
- }
- do_gettimeofday_fast(&tv2);
- printk(KERN_DEBUG "Timers started %is %06i\n",
- tv0.tv_jiff, tv0.tv_usec);
- printk(KERN_DEBUG "Timers started at %is %06i\n",
- tv1.tv_jiff, tv1.tv_usec);
- printk(KERN_DEBUG "Timers done %is %06i\n",
- tv2.tv_jiff, tv2.tv_usec);
- DP(printk("buf0:\n");
- printk(buf0);
- printk("buf1:\n");
- printk(buf1);
- printk("buf2:\n");
- printk(buf2);
- printk("buf3:\n");
- printk(buf3);
- printk("buf4:\n");
- printk(buf4);
- );
- printk("buf5:\n");
- printk(buf5);
-
- printk("timers set:\n");
- for(j = 0; j<i; j++)
- {
- struct fast_timer *t = &tr[j];
- printk("%-10s set: %6is %06ius exp: %6is %06ius "
- "data: 0x%08X func: 0x%08X\n",
- t->name,
- t->tv_set.tv_jiff,
- t->tv_set.tv_usec,
- t->tv_expires.tv_jiff,
- t->tv_expires.tv_usec,
- t->data,
- t->function
- );
-
- printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n",
- t->delay_us,
- tv_exp[j].tv_jiff,
- tv_exp[j].tv_usec,
- exp_num[j],
- (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) *
- 1000000 + tv_exp[j].tv_usec -
- t->tv_expires.tv_usec);
- }
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
- printk("buf5 after all done:\n");
- printk(buf5);
- printk("fast_timer_test() done\n");
-}
-#endif
-
-
-int fast_timer_init(void)
-{
- /* For some reason, request_irq() hangs when called froom time_init() */
- if (!fast_timer_is_init)
- {
-#if 0 && defined(FAST_TIMER_TEST)
- int i;
-#endif
-
- printk(KERN_INFO "fast_timer_init()\n");
-
-#if 0 && defined(FAST_TIMER_TEST)
- for (i = 0; i <= TIMER0_DIV; i++)
- {
- /* We must be careful not to get overflow... */
- printk("%3i %6u\n", i, timer0_value_us[i]);
- }
-#endif
-#ifdef CONFIG_PROC_FS
- proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
-#endif /* PROC_FS */
- if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0,
- "fast timer int", NULL))
- {
- printk("err: timer1 irq\n");
- }
- fast_timer_is_init = 1;
-#ifdef FAST_TIMER_TEST
- printk("do test\n");
- fast_timer_test();
-#endif
- }
- return 0;
-}
-__initcall(fast_timer_init);
diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S
deleted file mode 100644
index b260a8833903..000000000000
--- a/arch/cris/arch-v10/kernel/head.S
+++ /dev/null
@@ -1,620 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Head of the kernel - alter with care
- *
- * Copyright (C) 2000, 2001, 2010 Axis Communications AB
- *
- */
-
-#include <linux/init.h>
-
-#define ASSEMBLER_MACROS_ONLY
-/* The IO_* macros use the ## token concatenation operator, so
- -traditional must not be used when assembling this file. */
-#include <arch/sv_addr_ag.h>
-
-#define CRAMFS_MAGIC 0x28cd3d45
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-
-#define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\
- IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk)
-
- ;; exported symbols
-
- .globl etrax_irv
- .globl romfs_start
- .globl romfs_length
- .globl romfs_in_flash
- .globl swapper_pg_dir
-
- __HEAD
-
- ;; This is the entry point of the kernel. We are in supervisor mode.
- ;; 0x00000000 if Flash, 0x40004000 if DRAM
- ;; since etrax actually starts at address 2 when booting from flash, we
- ;; put a nop (2 bytes) here first so we dont accidentally skip the di
- ;;
- ;; NOTICE! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below until read.
-
- nop
- di
-
- ;; First setup the kseg_c mapping from where the kernel is linked
- ;; to 0x40000000 (where the actual DRAM resides) otherwise
- ;; we cannot do very much! See arch/cris/README.mm
- ;;
- ;; Notice that since we're potentially running at 0x00 or 0x40 right now,
- ;; we will get a fault as soon as we enable the MMU if we dont
- ;; temporarily map those segments linearily.
- ;;
- ;; Due to a bug in Etrax-100 LX version 1 we need to map the memory
- ;; slightly different. The bug is that you can't remap bit 31 of
- ;; an address. Though we can check the version register for
- ;; whether the bug is present, some constants would then have to
- ;; be variables, so we don't. The drawback is that you can "only" map
- ;; 1G per process with CONFIG_CRIS_LOW_MAP.
-
-#ifdef CONFIG_CRIS_LOW_MAP
- ; kseg mappings, temporary map of 0xc0->0x40
- move.d IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \
- | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb) \
- | IO_FIELD (R_MMU_KBASE_HI, base_9, 9) \
- | IO_FIELD (R_MMU_KBASE_HI, base_8, 8), $r0
- move.d $r0, [R_MMU_KBASE_HI]
-
- ; temporary map of 0x40->0x40 and 0x60->0x40
- move.d IO_FIELD (R_MMU_KBASE_LO, base_6, 4) \
- | IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0
- move.d $r0, [R_MMU_KBASE_LO]
-
- ; mmu enable, segs e,c,b,a,6,5,4,0 segment mapped
- move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \
- | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, we_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, seg_f, page) \
- | IO_STATE (R_MMU_CONFIG, seg_e, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_d, page) \
- | IO_STATE (R_MMU_CONFIG, seg_c, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_b, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_a, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_9, page) \
- | IO_STATE (R_MMU_CONFIG, seg_8, page) \
- | IO_STATE (R_MMU_CONFIG, seg_7, page) \
- | IO_STATE (R_MMU_CONFIG, seg_6, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_5, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_4, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_3, page) \
- | IO_STATE (R_MMU_CONFIG, seg_2, page) \
- | IO_STATE (R_MMU_CONFIG, seg_1, page) \
- | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0
- move.d $r0, [R_MMU_CONFIG]
-#else
- ; kseg mappings
- move.d IO_FIELD (R_MMU_KBASE_HI, base_e, 8) \
- | IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \
- | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb), $r0
- move.d $r0, [R_MMU_KBASE_HI]
-
- ; temporary map of 0x40->0x40 and 0x00->0x00
- move.d IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0
- move.d $r0, [R_MMU_KBASE_LO]
-
- ; mmu enable, segs f,e,c,b,4,0 segment mapped
- move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \
- | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, we_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, seg_f, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_e, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_d, page) \
- | IO_STATE (R_MMU_CONFIG, seg_c, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_b, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_a, page) \
- | IO_STATE (R_MMU_CONFIG, seg_9, page) \
- | IO_STATE (R_MMU_CONFIG, seg_8, page) \
- | IO_STATE (R_MMU_CONFIG, seg_7, page) \
- | IO_STATE (R_MMU_CONFIG, seg_6, page) \
- | IO_STATE (R_MMU_CONFIG, seg_5, page) \
- | IO_STATE (R_MMU_CONFIG, seg_4, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_3, page) \
- | IO_STATE (R_MMU_CONFIG, seg_2, page) \
- | IO_STATE (R_MMU_CONFIG, seg_1, page) \
- | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0
- move.d $r0, [R_MMU_CONFIG]
-#endif
-
- ;; Now we need to sort out the segments and their locations in RAM or
- ;; Flash. The image in the Flash (or in DRAM) consists of 3 pieces:
- ;; 1) kernel text, 2) kernel data, 3) ROM filesystem image
- ;; But the linker has linked the kernel to expect this layout in
- ;; DRAM memory:
- ;; 1) kernel text, 2) kernel data, 3) kernel BSS
- ;; (the location of the ROM filesystem is determined by the krom driver)
- ;; If we boot this from Flash, we want to keep the ROM filesystem in
- ;; the flash, we want to copy the text and need to copy the data to DRAM.
- ;; But if we boot from DRAM, we need to move the ROMFS image
- ;; from its position after kernel data, to after kernel BSS, BEFORE the
- ;; kernel starts using the BSS area (since its "overlayed" with the ROMFS)
- ;;
- ;; In both cases, we start in un-cached mode, and need to jump into a
- ;; cached PC after we're done fiddling around with the segments.
- ;;
- ;; arch/etrax100/etrax100.ld sets some symbols that define the start
- ;; and end of each segment.
-
- ;; Check if we start from DRAM or FLASH by testing PC
-
- move.d $pc,$r0
- and.d 0x7fffffff,$r0 ; get rid of the non-cache bit
- cmp.d 0x10000,$r0 ; arbitrary... just something above this code
- blo _inflash0
- nop
-
- jump _inram ; enter cached ram
-
- ;; Jumpgate for branches.
-_inflash0:
- jump _inflash
-
- ;; Put this in a suitable section where we can reclaim storage
- ;; after init.
- __INIT
-_inflash:
-#ifdef CONFIG_ETRAX_ETHERNET
- ;; Start MII clock to make sure it is running when tranceiver is reset
- move.d START_ETHERNET_CLOCK, $r0
- move.d $r0, [R_NETWORK_GEN_CONFIG]
-#endif
-
- ;; Set up waitstates etc according to kernel configuration.
- move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
- move.d $r0, [R_WAITSTATES]
-
- move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
- move.d $r0, [R_BUS_CONFIG]
-
- ;; We need to initialze DRAM registers before we start using the DRAM
-
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq _dram_init_finished
- nop
-
-#include "../lib/dram_init.S"
-
-_dram_init_finished:
- ;; Copy text+data to DRAM
- ;; This is fragile - the calculation of r4 as the image size depends
- ;; on that the labels below actually are the first and last positions
- ;; in the linker-script.
- ;;
- ;; Then the locating of the cramfs image depends on the aforementioned
- ;; image being located in the flash at 0. This is most often not true,
- ;; thus the following does not work (normally there is a rescue-block
- ;; between the physical start of the flash and the flash-image start,
- ;; and when run with compression, the kernel is actually unpacked to
- ;; DRAM and we never get here in the first place :))
-
- moveq 0, $r0 ; source
- move.d text_start, $r1 ; destination
- move.d __vmlinux_end, $r2 ; end destination
- move.d $r2, $r4
- sub.d $r1, $r4 ; r4=__vmlinux_end in flash, used below
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
- blo 1b
- nop
-
- ;; We keep the cramfs in the flash.
- ;; There might be none, but that does not matter because
- ;; we don't do anything than read some bytes here.
-
- moveq 0, $r0
- move.d $r0, [romfs_length] ; default if there is no cramfs
-
- move.d [$r4], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne 1f
- nop
- move.d [$r4 + 4], $r0 ; cramfs_super.size
- move.d $r0, [romfs_length]
-#ifdef CONFIG_CRIS_LOW_MAP
- add.d 0x50000000, $r4 ; add flash start in virtual memory (cached)
-#else
- add.d 0xf0000000, $r4 ; add flash start in virtual memory (cached)
-#endif
- move.d $r4, [romfs_start]
-1:
- moveq 1, $r0
- move.d $r0, [romfs_in_flash]
-
- jump _start_it ; enter code, cached this time
-
-_inram:
- ;; Move the ROM fs to after BSS end. This assumes that the cramfs
- ;; second longword contains the length of the cramfs
-
- moveq 0, $r0
- move.d $r0, [romfs_length] ; default if there is no cramfs
-
- ;; The kernel could have been unpacked to DRAM by the loader, but
- ;; the cramfs image could still be in the Flash directly after the
- ;; compressed kernel image. The loader passes the address of the
- ;; byte succeeding the last compressed byte in the flash in the
- ;; register r9 when starting the kernel. Check if r9 points to a
- ;; decent cramfs image!
- ;; (Notice that if this is not booted from the loader, r9 will be
- ;; garbage but we do sanity checks on it, the chance that it points
- ;; to a cramfs magic is small.. )
-
- cmp.d 0x0ffffff8, $r9
- bhs _no_romfs_in_flash ; r9 points outside the flash area
- nop
- move.d [$r9], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne _no_romfs_in_flash
- nop
- move.d [$r9+4], $r0 ; cramfs_super.length
- move.d $r0, [romfs_length]
-#ifdef CONFIG_CRIS_LOW_MAP
- add.d 0x50000000, $r9 ; add flash start in virtual memory (cached)
-#else
- add.d 0xf0000000, $r9 ; add flash start in virtual memory (cached)
-#endif
- move.d $r9, [romfs_start]
-
- moveq 1, $r0
- move.d $r0, [romfs_in_flash]
-
- jump _start_it ; enter code, cached this time
-
-_no_romfs_in_flash:
-
- ;; Check if there is a cramfs (magic value).
- ;; Notice that we check for cramfs magic value - which is
- ;; the "rom fs" we'll possibly use in 2.4 if not JFFS (which does
- ;; not need this mechanism anyway)
-
- move.d __init_end, $r0; the image will be after the end of init
- move.d [$r0], $r1 ; cramfs assumes same endian on host/target
- cmp.d CRAMFS_MAGIC, $r1; magic value in cramfs superblock
- bne 2f
- nop
-
- ;; Ok. What is its size ?
-
- move.d [$r0 + 4], $r2 ; cramfs_super.size (again, no need to swapwb)
-
- ;; We want to copy it to the end of the BSS
-
- move.d _end, $r1
-
- ;; Remember values so cramfs and setup can find this info
-
- move.d $r1, [romfs_start] ; new romfs location
- move.d $r2, [romfs_length]
-
- ;; We need to copy it backwards, since they can be overlapping
-
- add.d $r2, $r0
- add.d $r2, $r1
-
- ;; Go ahead. Make my loop.
-
- lsrq 1, $r2 ; size is in bytes, we copy words
-
-1: move.w [$r0=$r0-2],$r3
- move.w $r3,[$r1=$r1-2]
- subq 1, $r2
- bne 1b
- nop
-
-2:
- ;; Dont worry that the BSS is tainted. It will be cleared later.
-
- moveq 0, $r0
- move.d $r0, [romfs_in_flash]
-
- jump _start_it ; better skip the additional cramfs check below
-
-_start_it:
-
- ;; Check if kernel command line is supplied
- cmp.d COMMAND_LINE_MAGIC, $r10
- bne no_command_line
- nop
-
- move.d 256, $r13
- move.d cris_command_line, $r10
- or.d 0x80000000, $r11 ; Make it virtual
-1:
- move.b [$r11+], $r12
- move.b $r12, [$r10+]
- subq 1, $r13
- bne 1b
- nop
-
-no_command_line:
-
- ;; the kernel stack is overlayed with the task structure for each
- ;; task. thus the initial kernel stack is in the same page as the
- ;; init_task (but starts in the top of the page, size 8192)
- move.d init_thread_union + 8192, $sp
- move.d ibr_start,$r0 ; this symbol is set by the linker script
- move $r0,$ibr
- move.d $r0,[etrax_irv] ; set the interrupt base register and pointer
-
- ;; Clear BSS region, from _bss_start to _end
-
- move.d __bss_start, $r0
- move.d _end, $r1
-1: clear.d [$r0+]
- cmp.d $r1, $r0
- blo 1b
- nop
-
- ;; Etrax product HW genconfig setup
-
- moveq 0,$r0
-
- ;; Select or disable serial port 2
-#ifdef CONFIG_ETRAX_SERIAL_PORT2
- or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
-#else
- or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0
-#endif
-
- ;; Init interfaces (disable them).
- or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \
- | IO_STATE (R_GEN_CONFIG, ata, disable) \
- | IO_STATE (R_GEN_CONFIG, par0, disable) \
- | IO_STATE (R_GEN_CONFIG, mio, disable) \
- | IO_STATE (R_GEN_CONFIG, scsi1, disable) \
- | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \
- | IO_STATE (R_GEN_CONFIG, par1, disable) \
- | IO_STATE (R_GEN_CONFIG, ser3, disable) \
- | IO_STATE (R_GEN_CONFIG, mio_w, disable) \
- | IO_STATE (R_GEN_CONFIG, usb1, disable) \
- | IO_STATE (R_GEN_CONFIG, usb2, disable) \
- | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0
-
- ;; Init DMA channel muxing (set to unused clients).
- or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \
- | IO_STATE (R_GEN_CONFIG, dma3, ata) \
- | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \
- | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \
- | IO_STATE (R_GEN_CONFIG, dma6, unused) \
- | IO_STATE (R_GEN_CONFIG, dma7, unused) \
- | IO_STATE (R_GEN_CONFIG, dma8, usb) \
- | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
-
-
- move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
-
- move.d $r0,[R_GEN_CONFIG]
-
-#if 0
- moveq 4,$r0
- move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out)
- move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in)
-1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish
- and.b 7,$r0
- cmp.b 4,$r0
- beq 1b
- nop
-1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish
- and.b 7,$r0
- cmp.b 4,$r0
- beq 1b
- nop
-#endif
-
- moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
- move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out)
- move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in)
-1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish
- andq IO_MASK (R_DMA_CH8_CMD, cmd),$r0
- cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
- beq 1b
- nop
-1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
- andq IO_MASK (R_DMA_CH9_CMD, cmd),$r0
- cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0
- beq 1b
- nop
-
- ;; setup port PA and PB default initial directions and data
- ;; including their shadow registers
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
- move.b $r0,[port_pa_dir_shadow]
- move.b $r0,[R_PORT_PA_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0
- move.b $r0,[port_pa_data_shadow]
- move.b $r0,[R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG,$r0
- move.b $r0,[port_pb_config_shadow]
- move.b $r0,[R_PORT_PB_CONFIG]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0
- move.b $r0,[port_pb_dir_shadow]
- move.b $r0,[R_PORT_PB_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0
- move.b $r0,[port_pb_data_shadow]
- move.b $r0,[R_PORT_PB_DATA]
-
- moveq 0, $r0
- move.d $r0,[port_pb_i2c_shadow]
- move.d $r0, [R_PORT_PB_I2C]
-
- moveq 0,$r0
- move.d $r0,[port_g_data_shadow]
- move.d $r0,[R_PORT_G_DATA]
-
- ;; setup the serial port 0 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL0_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL0_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL0_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL0_BAUD]
-
- ; Set up and enable the serial0 receiver.
- move.b IO_STATE (R_SERIAL0_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL0_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL0_REC_CTRL]
-
- ; Set up and enable the serial0 transmitter.
- move.b IO_FIELD (R_SERIAL0_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL0_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL0_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL0_TR_CTRL]
-
- ;; setup the serial port 1 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL1_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL1_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL1_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL1_BAUD]
-
- ; Set up and enable the serial1 receiver.
- move.b IO_STATE (R_SERIAL1_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL1_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL1_REC_CTRL]
-
- ; Set up and enable the serial1 transmitter.
- move.b IO_FIELD (R_SERIAL1_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL1_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL1_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL1_TR_CTRL]
-
-#ifdef CONFIG_ETRAX_SERIAL_PORT2
- ;; setup the serial port 2 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL2_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL2_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL2_BAUD]
-
- ; Set up and enable the serial2 receiver.
- move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL2_REC_CTRL]
-
- ; Set up and enable the serial2 transmitter.
- move.b IO_FIELD (R_SERIAL2_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL2_TR_CTRL]
-#endif
-
-#ifdef CONFIG_ETRAX_SERIAL_PORT3
- ;; setup the serial port 3 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL3_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL3_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL3_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL3_BAUD]
-
- ; Set up and enable the serial3 receiver.
- move.b IO_STATE (R_SERIAL3_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL3_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL3_REC_CTRL]
-
- ; Set up and enable the serial3 transmitter.
- move.b IO_FIELD (R_SERIAL3_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL3_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL3_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL3_TR_CTRL]
-#endif
-
- jump start_kernel ; jump into the C-function start_kernel in init/main.c
-
- .data
-etrax_irv:
- .dword 0
-romfs_start:
- .dword 0
-romfs_length:
- .dword 0
-romfs_in_flash:
- .dword 0
-
- ;; put some special pages at the beginning of the kernel aligned
- ;; to page boundaries - the kernel cannot start until after this
-
-#ifdef CONFIG_CRIS_LOW_MAP
-swapper_pg_dir = 0x60002000
-#else
-swapper_pg_dir = 0xc0002000
-#endif
-
- .section ".init.data", "aw"
-#include "../lib/hw_settings.S"
diff --git a/arch/cris/arch-v10/kernel/io_interface_mux.c b/arch/cris/arch-v10/kernel/io_interface_mux.c
deleted file mode 100644
index 13a887ce115a..000000000000
--- a/arch/cris/arch-v10/kernel/io_interface_mux.c
+++ /dev/null
@@ -1,1183 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* IO interface mux allocator for ETRAX100LX.
- * Copyright 2004-2007, Axis Communications AB
- */
-
-
-/* C.f. ETRAX100LX Designer's Reference chapter 19.9 */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <arch/svinto.h>
-#include <asm/io.h>
-#include <arch/io_interface_mux.h>
-#include <arch/system.h>
-
-
-#define DBG(s)
-
-/* Macro to access ETRAX 100 registers */
-#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_STATE_(reg##_, field##_, _##val)
-
-enum io_if_group {
- group_a = (1<<0),
- group_b = (1<<1),
- group_c = (1<<2),
- group_d = (1<<3),
- group_e = (1<<4),
- group_f = (1<<5)
-};
-
-struct watcher
-{
- void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available);
- struct watcher *next;
-};
-
-
-struct if_group
-{
- enum io_if_group group;
- /* name - the name of the group 'A' to 'F' */
- char *name;
- /* used - a bit mask of all pins in the group in the order listed
- * in the tables in 19.9.1 to 19.9.6. Note that no
- * distinction is made between in, out and in/out pins. */
- unsigned int used;
-};
-
-
-struct interface
-{
- enum cris_io_interface ioif;
- /* name - the name of the interface */
- char *name;
- /* groups - OR'ed together io_if_group flags describing what pin groups
- * the interface uses pins in. */
- unsigned char groups;
- /* used - set when the interface is allocated. */
- unsigned char used;
- char *owner;
- /* group_a through group_f - bit masks describing what pins in the
- * pin groups the interface uses. */
- unsigned int group_a;
- unsigned int group_b;
- unsigned int group_c;
- unsigned int group_d;
- unsigned int group_e;
- unsigned int group_f;
-
- /* gpio_g_in, gpio_g_out, gpio_b - bit masks telling what pins in the
- * GPIO ports the interface uses. This could be reconstucted using
- * the group_X masks and a table of what pins the GPIO ports use,
- * but that would be messy. */
- unsigned int gpio_g_in;
- unsigned int gpio_g_out;
- unsigned char gpio_b;
-};
-
-static struct if_group if_groups[6] = {
- {
- .group = group_a,
- .name = "A",
- .used = 0,
- },
- {
- .group = group_b,
- .name = "B",
- .used = 0,
- },
- {
- .group = group_c,
- .name = "C",
- .used = 0,
- },
- {
- .group = group_d,
- .name = "D",
- .used = 0,
- },
- {
- .group = group_e,
- .name = "E",
- .used = 0,
- },
- {
- .group = group_f,
- .name = "F",
- .used = 0,
- }
-};
-
-/* The order in the array must match the order of enum
- * cris_io_interface in io_interface_mux.h */
-static struct interface interfaces[] = {
- /* Begin Non-multiplexed interfaces */
- {
- .ioif = if_eth,
- .name = "ethernet",
- .groups = 0,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0,
- .gpio_g_out = 0,
- .gpio_b = 0
- },
- {
- .ioif = if_serial_0,
- .name = "serial_0",
- .groups = 0,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0,
- .gpio_g_out = 0,
- .gpio_b = 0
- },
- /* End Non-multiplexed interfaces */
- {
- .ioif = if_serial_1,
- .name = "serial_1",
- .groups = group_e,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x0f,
- .group_f = 0,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_serial_2,
- .name = "serial_2",
- .groups = group_b,
-
- .group_a = 0,
- .group_b = 0x0f,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x000000c0,
- .gpio_g_out = 0x000000c0,
- .gpio_b = 0x00
- },
- {
- .ioif = if_serial_3,
- .name = "serial_3",
- .groups = group_c,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0x0f,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0xc0000000,
- .gpio_g_out = 0xc0000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_sync_serial_1,
- .name = "sync_serial_1",
- .groups = group_e | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x0f,
- .group_f = 0x10,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x10
- },
- {
- .ioif = if_sync_serial_3,
- .name = "sync_serial_3",
- .groups = group_c | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0x0f,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0x80,
-
- .gpio_g_in = 0xc0000000,
- .gpio_g_out = 0xc0000000,
- .gpio_b = 0x80
- },
- {
- .ioif = if_shared_ram,
- .name = "shared_ram",
- .groups = group_a,
-
- .group_a = 0x7f8ff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x0000ff3e,
- .gpio_g_out = 0x0000ff38,
- .gpio_b = 0x00
- },
- {
- .ioif = if_shared_ram_w,
- .name = "shared_ram_w",
- .groups = group_a | group_d,
-
- .group_a = 0x7f8ff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0xff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00ffff3e,
- .gpio_g_out = 0x00ffff38,
- .gpio_b = 0x00
- },
- {
- .ioif = if_par_0,
- .name = "par_0",
- .groups = group_a,
-
- .group_a = 0x7fbff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x0000ff3e,
- .gpio_g_out = 0x0000ff3e,
- .gpio_b = 0x00
- },
- {
- .ioif = if_par_1,
- .name = "par_1",
- .groups = group_d,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0x7feff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x3eff0000,
- .gpio_g_out = 0x3eff0000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_par_w,
- .name = "par_w",
- .groups = group_a | group_d,
-
- .group_a = 0x7fbff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0xff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00ffff3e,
- .gpio_g_out = 0x00ffff3e,
- .gpio_b = 0x00
- },
- {
- .ioif = if_scsi8_0,
- .name = "scsi8_0",
- .groups = group_a | group_b | group_f,
-
- .group_a = 0x7ffff,
- .group_b = 0x0f,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0x10,
-
- .gpio_g_in = 0x0000ffff,
- .gpio_g_out = 0x0000ffff,
- .gpio_b = 0x10
- },
- {
- .ioif = if_scsi8_1,
- .name = "scsi8_1",
- .groups = group_c | group_d | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0x0f,
- .group_d = 0x7ffff,
- .group_e = 0,
- .group_f = 0x80,
-
- .gpio_g_in = 0xffff0000,
- .gpio_g_out = 0xffff0000,
- .gpio_b = 0x80
- },
- {
- .ioif = if_scsi_w,
- .name = "scsi_w",
- .groups = group_a | group_b | group_d | group_f,
-
- .group_a = 0x7ffff,
- .group_b = 0x0f,
- .group_c = 0,
- .group_d = 0x601ff,
- .group_e = 0,
- .group_f = 0x90,
-
- .gpio_g_in = 0x01ffffff,
- .gpio_g_out = 0x07ffffff,
- .gpio_b = 0x80
- },
- {
- .ioif = if_ata,
- .name = "ata",
- .groups = group_a | group_b | group_c | group_d,
-
- .group_a = 0x7ffff,
- .group_b = 0x0f,
- .group_c = 0x0f,
- .group_d = 0x7cfff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0xf9ffffff,
- .gpio_g_out = 0xffffffff,
- .gpio_b = 0x80
- },
- {
- .ioif = if_csp,
- .name = "csp",
- .groups = group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0xfc,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0xfc
- },
- {
- .ioif = if_i2c,
- .name = "i2c",
- .groups = group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0x03,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x03
- },
- {
- .ioif = if_usb_1,
- .name = "usb_1",
- .groups = group_e | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x0f,
- .group_f = 0x2c,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x2c
- },
- {
- .ioif = if_usb_2,
- .name = "usb_2",
- .groups = group_d,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x33e00,
- .group_f = 0,
-
- .gpio_g_in = 0x3e000000,
- .gpio_g_out = 0x0c000000,
- .gpio_b = 0x00
- },
- /* GPIO pins */
- {
- .ioif = if_gpio_grp_a,
- .name = "gpio_a",
- .groups = group_a,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x0000ff3f,
- .gpio_g_out = 0x0000ff3f,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_b,
- .name = "gpio_b",
- .groups = group_b,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x000000c0,
- .gpio_g_out = 0x000000c0,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_c,
- .name = "gpio_c",
- .groups = group_c,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0xc0000000,
- .gpio_g_out = 0xc0000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_d,
- .name = "gpio_d",
- .groups = group_d,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x3fff0000,
- .gpio_g_out = 0x3fff0000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_e,
- .name = "gpio_e",
- .groups = group_e,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_f,
- .name = "gpio_f",
- .groups = group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0xff
- }
- /* Array end */
-};
-
-static struct watcher *watchers = NULL;
-
-/* The pins that are free to use in the GPIO ports. */
-static unsigned int gpio_in_pins = 0xffffffff;
-static unsigned int gpio_out_pins = 0xffffffff;
-static unsigned char gpio_pb_pins = 0xff;
-static unsigned char gpio_pa_pins = 0xff;
-
-/* Identifiers for the owners of the GPIO pins. */
-static enum cris_io_interface gpio_pa_owners[8];
-static enum cris_io_interface gpio_pb_owners[8];
-static enum cris_io_interface gpio_pg_owners[32];
-
-static int cris_io_interface_init(void);
-
-static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group)
-{
- return (groups & ~group->group);
-}
-
-
-static struct if_group *get_group(const unsigned char groups)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(if_groups); i++) {
- if (groups & if_groups[i].group) {
- return &if_groups[i];
- }
- }
- return NULL;
-}
-
-
-static void notify_watchers(void)
-{
- struct watcher *w = watchers;
-
- DBG(printk("io_interface_mux: notifying watchers\n"));
-
- while (NULL != w) {
- w->notify((const unsigned int)gpio_in_pins,
- (const unsigned int)gpio_out_pins,
- (const unsigned char)gpio_pa_pins,
- (const unsigned char)gpio_pb_pins);
- w = w->next;
- }
-}
-
-
-int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id)
-{
- int set_gen_config = 0;
- int set_gen_config_ii = 0;
- unsigned long int gens;
- unsigned long int gens_ii;
- struct if_group *grp;
- unsigned char group_set;
- unsigned long flags;
- int res = 0;
-
- (void)cris_io_interface_init();
-
- DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id));
-
- if ((ioif >= if_max_interfaces) || (ioif < 0)) {
- printk(KERN_CRIT "cris_request_io_interface: Bad interface "
- "%u submitted for %s\n",
- ioif,
- device_id);
- return -EINVAL;
- }
-
- local_irq_save(flags);
-
- if (interfaces[ioif].used) {
- printk(KERN_CRIT "cris_io_interface: Cannot allocate interface "
- "%s for %s, in use by %s\n",
- interfaces[ioif].name,
- device_id,
- interfaces[ioif].owner);
- res = -EBUSY;
- goto exit;
- }
-
- /* Check that all required pins in the used groups are free
- * before allocating. */
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- unsigned int if_group_use = 0;
-
- switch (grp->group) {
- case group_a:
- if_group_use = interfaces[ioif].group_a;
- break;
- case group_b:
- if_group_use = interfaces[ioif].group_b;
- break;
- case group_c:
- if_group_use = interfaces[ioif].group_c;
- break;
- case group_d:
- if_group_use = interfaces[ioif].group_d;
- break;
- case group_e:
- if_group_use = interfaces[ioif].group_e;
- break;
- case group_f:
- if_group_use = interfaces[ioif].group_f;
- break;
- default:
- BUG_ON(1);
- }
-
- if (if_group_use & grp->used) {
- printk(KERN_INFO "cris_request_io_interface: group "
- "%s needed by %s not available\n",
- grp->name, interfaces[ioif].name);
- res = -EBUSY;
- goto exit;
- }
-
- group_set = clear_group_from_set(group_set, grp);
- }
-
- /* Are the required GPIO pins available too? */
- if (((interfaces[ioif].gpio_g_in & gpio_in_pins) !=
- interfaces[ioif].gpio_g_in) ||
- ((interfaces[ioif].gpio_g_out & gpio_out_pins) !=
- interfaces[ioif].gpio_g_out) ||
- ((interfaces[ioif].gpio_b & gpio_pb_pins) !=
- interfaces[ioif].gpio_b)) {
- printk(KERN_CRIT "cris_request_io_interface: Could not get "
- "required pins for interface %u\n", ioif);
- res = -EBUSY;
- goto exit;
- }
-
- /* Check which registers need to be reconfigured. */
- gens = genconfig_shadow;
- gens_ii = gen_config_ii_shadow;
-
- set_gen_config = 1;
- switch (ioif)
- {
- /* Begin Non-multiplexed interfaces */
- case if_eth:
- /* fall through */
- case if_serial_0:
- set_gen_config = 0;
- break;
- /* End Non-multiplexed interfaces */
- case if_serial_1:
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async);
- break;
- case if_serial_2:
- SETS(gens, R_GEN_CONFIG, ser2, select);
- break;
- case if_serial_3:
- SETS(gens, R_GEN_CONFIG, ser3, select);
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async);
- break;
- case if_sync_serial_1:
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync);
- break;
- case if_sync_serial_3:
- SETS(gens, R_GEN_CONFIG, ser3, select);
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync);
- break;
- case if_shared_ram:
- SETS(gens, R_GEN_CONFIG, mio, select);
- break;
- case if_shared_ram_w:
- SETS(gens, R_GEN_CONFIG, mio_w, select);
- break;
- case if_par_0:
- SETS(gens, R_GEN_CONFIG, par0, select);
- break;
- case if_par_1:
- SETS(gens, R_GEN_CONFIG, par1, select);
- break;
- case if_par_w:
- SETS(gens, R_GEN_CONFIG, par0, select);
- SETS(gens, R_GEN_CONFIG, par_w, select);
- break;
- case if_scsi8_0:
- SETS(gens, R_GEN_CONFIG, scsi0, select);
- break;
- case if_scsi8_1:
- SETS(gens, R_GEN_CONFIG, scsi1, select);
- break;
- case if_scsi_w:
- SETS(gens, R_GEN_CONFIG, scsi0, select);
- SETS(gens, R_GEN_CONFIG, scsi0w, select);
- break;
- case if_ata:
- SETS(gens, R_GEN_CONFIG, ata, select);
- break;
- case if_csp:
- /* fall through */
- case if_i2c:
- set_gen_config = 0;
- break;
- case if_usb_1:
- SETS(gens, R_GEN_CONFIG, usb1, select);
- break;
- case if_usb_2:
- SETS(gens, R_GEN_CONFIG, usb2, select);
- break;
- case if_gpio_grp_a:
- /* GPIO groups are only accounted, don't do configuration changes. */
- /* fall through */
- case if_gpio_grp_b:
- /* fall through */
- case if_gpio_grp_c:
- /* fall through */
- case if_gpio_grp_d:
- /* fall through */
- case if_gpio_grp_e:
- /* fall through */
- case if_gpio_grp_f:
- set_gen_config = 0;
- break;
- default:
- printk(KERN_INFO "cris_request_io_interface: Bad interface "
- "%u submitted for %s\n",
- ioif, device_id);
- res = -EBUSY;
- goto exit;
- }
-
- /* All needed I/O pins and pin groups are free, allocate. */
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- unsigned int if_group_use = 0;
-
- switch (grp->group) {
- case group_a:
- if_group_use = interfaces[ioif].group_a;
- break;
- case group_b:
- if_group_use = interfaces[ioif].group_b;
- break;
- case group_c:
- if_group_use = interfaces[ioif].group_c;
- break;
- case group_d:
- if_group_use = interfaces[ioif].group_d;
- break;
- case group_e:
- if_group_use = interfaces[ioif].group_e;
- break;
- case group_f:
- if_group_use = interfaces[ioif].group_f;
- break;
- default:
- BUG_ON(1);
- }
- grp->used |= if_group_use;
-
- group_set = clear_group_from_set(group_set, grp);
- }
-
- interfaces[ioif].used = 1;
- interfaces[ioif].owner = (char*)device_id;
-
- if (set_gen_config) {
- volatile int i;
- genconfig_shadow = gens;
- *R_GEN_CONFIG = genconfig_shadow;
- /* Wait 12 cycles before doing any DMA command */
- for(i = 6; i > 0; i--)
- nop();
- }
- if (set_gen_config_ii) {
- gen_config_ii_shadow = gens_ii;
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
- }
-
- DBG(printk(KERN_DEBUG "GPIO pins: available before: "
- "g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
- DBG(printk(KERN_DEBUG
- "grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- interfaces[ioif].gpio_g_in,
- interfaces[ioif].gpio_g_out,
- interfaces[ioif].gpio_b));
-
- gpio_in_pins &= ~interfaces[ioif].gpio_g_in;
- gpio_out_pins &= ~interfaces[ioif].gpio_g_out;
- gpio_pb_pins &= ~interfaces[ioif].gpio_b;
-
- DBG(printk(KERN_DEBUG "GPIO pins: available after: "
- "g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
-
-exit:
- local_irq_restore(flags);
- if (res == 0)
- notify_watchers();
- return res;
-}
-
-
-void cris_free_io_interface(enum cris_io_interface ioif)
-{
- struct if_group *grp;
- unsigned char group_set;
- unsigned long flags;
-
- (void)cris_io_interface_init();
-
- if ((ioif >= if_max_interfaces) || (ioif < 0)) {
- printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n",
- ioif);
- return;
- }
- local_irq_save(flags);
- if (!interfaces[ioif].used) {
- printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n",
- ioif);
- local_irq_restore(flags);
- return;
- }
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- unsigned int if_group_use = 0;
-
- switch (grp->group) {
- case group_a:
- if_group_use = interfaces[ioif].group_a;
- break;
- case group_b:
- if_group_use = interfaces[ioif].group_b;
- break;
- case group_c:
- if_group_use = interfaces[ioif].group_c;
- break;
- case group_d:
- if_group_use = interfaces[ioif].group_d;
- break;
- case group_e:
- if_group_use = interfaces[ioif].group_e;
- break;
- case group_f:
- if_group_use = interfaces[ioif].group_f;
- break;
- default:
- BUG_ON(1);
- }
-
- if ((grp->used & if_group_use) != if_group_use)
- BUG_ON(1);
- grp->used = grp->used & ~if_group_use;
-
- group_set = clear_group_from_set(group_set, grp);
- }
- interfaces[ioif].used = 0;
- interfaces[ioif].owner = NULL;
-
- DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
- DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- interfaces[ioif].gpio_g_in,
- interfaces[ioif].gpio_g_out,
- interfaces[ioif].gpio_b));
-
- gpio_in_pins |= interfaces[ioif].gpio_g_in;
- gpio_out_pins |= interfaces[ioif].gpio_g_out;
- gpio_pb_pins |= interfaces[ioif].gpio_b;
-
- DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
-
- local_irq_restore(flags);
-
- notify_watchers();
-}
-
-/* Create a bitmask from bit 0 (inclusive) to bit stop_bit
- (non-inclusive). stop_bit == 0 returns 0x0 */
-static inline unsigned int create_mask(const unsigned stop_bit)
-{
- /* Avoid overflow */
- if (stop_bit >= 32) {
- return 0xffffffff;
- }
- return (1<<stop_bit)-1;
-}
-
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit)
-{
- unsigned int i;
- unsigned int mask = 0;
- unsigned int tmp_mask;
- unsigned long int flags;
- enum cris_io_interface *owners;
-
- (void)cris_io_interface_init();
-
- DBG(printk("cris_io_interface_allocate_pins: if=%d port=%c start=%u stop=%u\n",
- ioif, port, start_bit, stop_bit));
-
- if (!((start_bit <= stop_bit) &&
- ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
- ((port == 'g') && (stop_bit < 32))))) {
- return -EINVAL;
- }
-
- mask = create_mask(stop_bit + 1);
- tmp_mask = create_mask(start_bit);
- mask &= ~tmp_mask;
-
- DBG(printk("cris_io_interface_allocate_pins: port=%c start=%u stop=%u mask=0x%08x\n",
- port, start_bit, stop_bit, mask));
-
- local_irq_save(flags);
-
- switch (port) {
- case 'a':
- if ((gpio_pa_pins & mask) != mask) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- owners = gpio_pa_owners;
- gpio_pa_pins &= ~mask;
- break;
- case 'b':
- if ((gpio_pb_pins & mask) != mask) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- owners = gpio_pb_owners;
- gpio_pb_pins &= ~mask;
- break;
- case 'g':
- if (((gpio_in_pins & mask) != mask) ||
- ((gpio_out_pins & mask) != mask)) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- owners = gpio_pg_owners;
- gpio_in_pins &= ~mask;
- gpio_out_pins &= ~mask;
- break;
- default:
- local_irq_restore(flags);
- return -EINVAL;
- }
-
- for (i = start_bit; i <= stop_bit; i++) {
- owners[i] = ioif;
- }
- local_irq_restore(flags);
-
- notify_watchers();
- return 0;
-}
-
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_free_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit)
-{
- unsigned int i;
- unsigned int mask = 0;
- unsigned int tmp_mask;
- unsigned long int flags;
- enum cris_io_interface *owners;
-
- (void)cris_io_interface_init();
-
- if (!((start_bit <= stop_bit) &&
- ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
- ((port == 'g') && (stop_bit < 32))))) {
- return -EINVAL;
- }
-
- mask = create_mask(stop_bit + 1);
- tmp_mask = create_mask(start_bit);
- mask &= ~tmp_mask;
-
- DBG(printk("cris_io_interface_free_pins: port=%c start=%u stop=%u mask=0x%08x\n",
- port, start_bit, stop_bit, mask));
-
- local_irq_save(flags);
-
- switch (port) {
- case 'a':
- if ((~gpio_pa_pins & mask) != mask) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
- }
- owners = gpio_pa_owners;
- break;
- case 'b':
- if ((~gpio_pb_pins & mask) != mask) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
- }
- owners = gpio_pb_owners;
- break;
- case 'g':
- if (((~gpio_in_pins & mask) != mask) ||
- ((~gpio_out_pins & mask) != mask)) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
- }
- owners = gpio_pg_owners;
- break;
- default:
- owners = NULL; /* Cannot happen. Shut up, gcc! */
- }
-
- for (i = start_bit; i <= stop_bit; i++) {
- if (owners[i] != ioif) {
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing unowned pins");
- }
- }
-
- /* All was ok, change data. */
- switch (port) {
- case 'a':
- gpio_pa_pins |= mask;
- break;
- case 'b':
- gpio_pb_pins |= mask;
- break;
- case 'g':
- gpio_in_pins |= mask;
- gpio_out_pins |= mask;
- break;
- }
-
- for (i = start_bit; i <= stop_bit; i++) {
- owners[i] = if_unclaimed;
- }
- local_irq_restore(flags);
- notify_watchers();
-
- return 0;
-}
-
-
-int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available))
-{
- struct watcher *w;
-
- (void)cris_io_interface_init();
-
- if (NULL == notify) {
- return -EINVAL;
- }
- w = kmalloc(sizeof(*w), GFP_KERNEL);
- if (!w) {
- return -ENOMEM;
- }
- w->notify = notify;
- w->next = watchers;
- watchers = w;
-
- w->notify((const unsigned int)gpio_in_pins,
- (const unsigned int)gpio_out_pins,
- (const unsigned char)gpio_pa_pins,
- (const unsigned char)gpio_pb_pins);
-
- return 0;
-}
-
-void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available))
-{
- struct watcher *w = watchers, *prev = NULL;
-
- (void)cris_io_interface_init();
-
- while ((NULL != w) && (w->notify != notify)){
- prev = w;
- w = w->next;
- }
- if (NULL != w) {
- if (NULL != prev) {
- prev->next = w->next;
- } else {
- watchers = w->next;
- }
- kfree(w);
- return;
- }
- printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify);
-}
-
-
-static int cris_io_interface_init(void)
-{
- static int first = 1;
- int i;
-
- if (!first) {
- return 0;
- }
- first = 0;
-
- for (i = 0; i<8; i++) {
- gpio_pa_owners[i] = if_unclaimed;
- gpio_pb_owners[i] = if_unclaimed;
- gpio_pg_owners[i] = if_unclaimed;
- }
- for (; i<32; i++) {
- gpio_pg_owners[i] = if_unclaimed;
- }
- return 0;
-}
-
-
-module_init(cris_io_interface_init);
-
-
-EXPORT_SYMBOL(cris_request_io_interface);
-EXPORT_SYMBOL(cris_free_io_interface);
-EXPORT_SYMBOL(cris_io_interface_allocate_pins);
-EXPORT_SYMBOL(cris_io_interface_free_pins);
-EXPORT_SYMBOL(cris_io_interface_register_watcher);
-EXPORT_SYMBOL(cris_io_interface_delete_watcher);
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c
deleted file mode 100644
index df11e383acdd..000000000000
--- a/arch/cris/arch-v10/kernel/irq.c
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/irq.c
- *
- * Copyright (c) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * This file contains the interrupt vectors and some
- * helper functions
- *
- */
-
-#include <asm/irq.h>
-#include <asm/current.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
-#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
-
-extern void kgdb_init(void);
-extern void breakpoint(void);
-
-/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
- * global just so that the kernel gdb can use it.
- */
-
-void
-set_int_vector(int n, irqvectptr addr)
-{
- etrax_irv->v[n + 0x20] = (irqvectptr)addr;
-}
-
-/* the breakpoint vector is obviously not made just like the normal irq handlers
- * but needs to contain _code_ to jump to addr.
- *
- * the BREAK n instruction jumps to IBR + n * 8
- */
-
-void
-set_break_vector(int n, irqvectptr addr)
-{
- unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2];
- unsigned long *jaddr = (unsigned long *)(jinstr + 1);
-
- /* if you don't know what this does, do not touch it! */
-
- *jinstr = 0x0d3f;
- *jaddr = (unsigned long)addr;
-
- /* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */
-}
-
-/*
- * This builds up the IRQ handler stubs using some ugly macros in irq.h
- *
- * These macros create the low-level assembly IRQ routines that do all
- * the operations that are needed. They are also written to be fast - and to
- * disable interrupts as little as humanly possible.
- *
- */
-
-/* IRQ0 and 1 are special traps */
-void hwbreakpoint(void);
-void IRQ1_interrupt(void);
-BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */
-BUILD_IRQ(3, 0x08)
-BUILD_IRQ(4, 0x10)
-BUILD_IRQ(5, 0x20)
-BUILD_IRQ(6, 0x40)
-BUILD_IRQ(7, 0x80)
-BUILD_IRQ(8, 0x100)
-BUILD_IRQ(9, 0x200)
-BUILD_IRQ(10, 0x400)
-BUILD_IRQ(11, 0x800)
-BUILD_IRQ(12, 0x1000)
-BUILD_IRQ(13, 0x2000)
-void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */
-void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */
-BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */
-BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */
-BUILD_IRQ(18, 0x40000)
-BUILD_IRQ(19, 0x80000)
-BUILD_IRQ(20, 0x100000)
-BUILD_IRQ(21, 0x200000)
-BUILD_IRQ(22, 0x400000)
-BUILD_IRQ(23, 0x800000)
-BUILD_IRQ(24, 0x1000000)
-BUILD_IRQ(25, 0x2000000)
-/* IRQ 26-30 are reserved */
-BUILD_IRQ(31, 0x80000000)
-
-/*
- * Pointers to the low-level handlers
- */
-
-static void (*interrupt[NR_IRQS])(void) = {
- NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,
- IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,
- IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,
- IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,
- IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,
- IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,
- IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,
- IRQ31_interrupt
-};
-
-static void enable_crisv10_irq(struct irq_data *data)
-{
- crisv10_unmask_irq(data->irq);
-}
-
-static void disable_crisv10_irq(struct irq_data *data)
-{
- crisv10_mask_irq(data->irq);
-}
-
-static struct irq_chip crisv10_irq_type = {
- .name = "CRISv10",
- .irq_shutdown = disable_crisv10_irq,
- .irq_enable = enable_crisv10_irq,
- .irq_disable = disable_crisv10_irq,
-};
-
-void weird_irq(void);
-void system_call(void); /* from entry.S */
-void do_sigtrap(void); /* from entry.S */
-void gdb_handle_breakpoint(void); /* from entry.S */
-
-extern void do_IRQ(int irq, struct pt_regs * regs);
-
-/* Handle multiple IRQs */
-void do_multiple_IRQ(struct pt_regs* regs)
-{
- int bit;
- unsigned masked;
- unsigned mask;
- unsigned ethmask = 0;
-
- /* Get interrupts to mask and handle */
- mask = masked = *R_VECT_MASK_RD;
-
- /* Never mask timer IRQ */
- mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
-
- /*
- * If either ethernet interrupt (rx or tx) is active then block
- * the other one too. Unblock afterwards also.
- */
- if (mask &
- (IO_STATE(R_VECT_MASK_RD, dma0, active) |
- IO_STATE(R_VECT_MASK_RD, dma1, active))) {
- ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
- IO_MASK(R_VECT_MASK_RD, dma1));
- }
-
- /* Block them */
- *R_VECT_MASK_CLR = (mask | ethmask);
-
- /* An extra irq_enter here to prevent softIRQs to run after
- * each do_IRQ. This will decrease the interrupt latency.
- */
- irq_enter();
-
- /* Handle all IRQs */
- for (bit = 2; bit < 32; bit++) {
- if (masked & (1 << bit)) {
- do_IRQ(bit, regs);
- }
- }
-
- /* This irq_exit() will trigger the soft IRQs. */
- irq_exit();
-
- /* Unblock the IRQs again */
- *R_VECT_MASK_SET = (masked | ethmask);
-}
-
-/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
- setting the irq vector table.
-*/
-
-void __init init_IRQ(void)
-{
- int i;
-
- /* clear all interrupt masks */
- *R_IRQ_MASK0_CLR = 0xffffffff;
- *R_IRQ_MASK1_CLR = 0xffffffff;
- *R_IRQ_MASK2_CLR = 0xffffffff;
- *R_VECT_MASK_CLR = 0xffffffff;
-
- for (i = 0; i < 256; i++)
- etrax_irv->v[i] = weird_irq;
-
- /* Initialize IRQ handler descriptors. */
- for(i = 2; i < NR_IRQS; i++) {
- irq_set_chip_and_handler(i, &crisv10_irq_type,
- handle_simple_irq);
- set_int_vector(i, interrupt[i]);
- }
-
- /* the entries in the break vector contain actual code to be
- executed by the associated break handler, rather than just a jump
- address. therefore we need to setup a default breakpoint handler
- for all breakpoints */
- for (i = 0; i < 16; i++)
- set_break_vector(i, do_sigtrap);
-
- /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
- set_int_vector(15, multiple_interrupt);
-
- /* 0 and 1 which are special breakpoint/NMI traps */
- set_int_vector(0, hwbreakpoint);
- set_int_vector(1, IRQ1_interrupt);
-
- /* and irq 14 which is the mmu bus fault handler */
- set_int_vector(14, mmu_bus_fault);
-
- /* setup the system-call trap, which is reached by BREAK 13 */
- set_break_vector(13, system_call);
-
- /* setup a breakpoint handler for debugging used for both user and
- kernel mode debugging (which is why it is not inside an ifdef
- CONFIG_ETRAX_KGDB) */
- set_break_vector(8, gdb_handle_breakpoint);
-
-#ifdef CONFIG_ETRAX_KGDB
- /* setup kgdb if its enabled, and break into the debugger */
- kgdb_init();
- breakpoint();
-#endif
-}
diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c
deleted file mode 100644
index 79b13564d15c..000000000000
--- a/arch/cris/arch-v10/kernel/kgdb.c
+++ /dev/null
@@ -1,1128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*!**************************************************************************
-*!
-*! FILE NAME : kgdb.c
-*!
-*! DESCRIPTION: Implementation of the gdb stub with respect to ETRAX 100.
-*! It is a mix of arch/m68k/kernel/kgdb.c and cris_stub.c.
-*!
-*!---------------------------------------------------------------------------
-*! HISTORY
-*!
-*! DATE NAME CHANGES
-*! ---- ---- -------
-*! Apr 26 1999 Hendrik Ruijter Initial version.
-*! May 6 1999 Hendrik Ruijter Removed call to strlen in libc and removed
-*! struct assignment as it generates calls to
-*! memcpy in libc.
-*! Jun 17 1999 Hendrik Ruijter Added gdb 4.18 support. 'X', 'qC' and 'qL'.
-*! Jul 21 1999 Bjorn Wesen eLinux port
-*!
-*!---------------------------------------------------------------------------
-*!
-*! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN
-*!
-*!**************************************************************************/
-/* @(#) cris_stub.c 1.3 06/17/99 */
-
-/*
- * kgdb usage notes:
- * -----------------
- *
- * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
- * built with different gcc flags: "-g" is added to get debug infos, and
- * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
- * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
- * before compresion. Such a kernel will behave just as usually, except if
- * given a "debug=<device>" command line option. (Only serial devices are
- * allowed for <device>, i.e. no printers or the like; possible values are
- * machine depedend and are the same as for the usual debug device, the one
- * for logging kernel messages.) If that option is given and the device can be
- * initialized, the kernel will connect to the remote gdb in trap_init(). The
- * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
- * implementation.
- *
- * To start a debugging session, start that gdb with the debugging kernel
- * image (the one with the symbols, vmlinux.debug) named on the command line.
- * This file will be used by gdb to get symbol and debugging infos about the
- * kernel. Next, select remote debug mode by
- * target remote <device>
- * where <device> is the name of the serial device over which the debugged
- * machine is connected. Maybe you have to adjust the baud rate by
- * set remotebaud <rate>
- * or also other parameters with stty:
- * shell stty ... </dev/...
- * If the kernel to debug has already booted, it waited for gdb and now
- * connects, and you'll see a breakpoint being reported. If the kernel isn't
- * running yet, start it now. The order of gdb and the kernel doesn't matter.
- * Another thing worth knowing about in the getting-started phase is how to
- * debug the remote protocol itself. This is activated with
- * set remotedebug 1
- * gdb will then print out each packet sent or received. You'll also get some
- * messages about the gdb stub on the console of the debugged machine.
- *
- * If all that works, you can use lots of the usual debugging techniques on
- * the kernel, e.g. inspecting and changing variables/memory, setting
- * breakpoints, single stepping and so on. It's also possible to interrupt the
- * debugged kernel by pressing C-c in gdb. Have fun! :-)
- *
- * The gdb stub is entered (and thus the remote gdb gets control) in the
- * following situations:
- *
- * - If breakpoint() is called. This is just after kgdb initialization, or if
- * a breakpoint() call has been put somewhere into the kernel source.
- * (Breakpoints can of course also be set the usual way in gdb.)
- * In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
- *
- * - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
- * are entered. All the CPU exceptions are mapped to (more or less..., see
- * the hard_trap_info array below) appropriate signal, which are reported
- * to gdb. die_if_kernel() is usually called after some kind of access
- * error and thus is reported as SIGSEGV.
- *
- * - When panic() is called. This is reported as SIGABRT.
- *
- * - If C-c is received over the serial line, which is treated as
- * SIGINT.
- *
- * Of course, all these signals are just faked for gdb, since there is no
- * signal concept as such for the kernel. It also isn't possible --obviously--
- * to set signal handlers from inside gdb, or restart the kernel with a
- * signal.
- *
- * Current limitations:
- *
- * - While the kernel is stopped, interrupts are disabled for safety reasons
- * (i.e., variables not changing magically or the like). But this also
- * means that the clock isn't running anymore, and that interrupts from the
- * hardware may get lost/not be served in time. This can cause some device
- * errors...
- *
- * - When single-stepping, only one instruction of the current thread is
- * executed, but interrupts are allowed for that time and will be serviced
- * if pending. Be prepared for that.
- *
- * - All debugging happens in kernel virtual address space. There's no way to
- * access physical memory not mapped in kernel space, or to access user
- * space. A way to work around this is using get_user_long & Co. in gdb
- * expressions, but only for the current process.
- *
- * - Interrupting the kernel only works if interrupts are currently allowed,
- * and the interrupt of the serial line isn't blocked by some other means
- * (IPL too high, disabled, ...)
- *
- * - The gdb stub is currently not reentrant, i.e. errors that happen therein
- * (e.g. accessing invalid memory) may not be caught correctly. This could
- * be removed in future by introducing a stack of struct registers.
- *
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to kgdb_init() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint().
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- */
-
-
-#include <linux/string.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/linkage.h>
-#include <linux/reboot.h>
-
-#include <asm/setup.h>
-#include <asm/ptrace.h>
-
-#include <arch/svinto.h>
-#include <asm/irq.h>
-
-static int kgdb_started = 0;
-
-/********************************* Register image ****************************/
-/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's
- Reference", p. 1-1, with the additional register definitions of the
- ETRAX 100LX in cris-opc.h.
- There are 16 general 32-bit registers, R0-R15, where R14 is the stack
- pointer, SP, and R15 is the program counter, PC.
- There are 16 special registers, P0-P15, where three of the unimplemented
- registers, P0, P4 and P8, are reserved as zero-registers. A read from
- any of these registers returns zero and a write has no effect. */
-
-typedef
-struct register_image
-{
- /* Offset */
- unsigned int r0; /* 0x00 */
- unsigned int r1; /* 0x04 */
- unsigned int r2; /* 0x08 */
- unsigned int r3; /* 0x0C */
- unsigned int r4; /* 0x10 */
- unsigned int r5; /* 0x14 */
- unsigned int r6; /* 0x18 */
- unsigned int r7; /* 0x1C */
- unsigned int r8; /* 0x20 Frame pointer */
- unsigned int r9; /* 0x24 */
- unsigned int r10; /* 0x28 */
- unsigned int r11; /* 0x2C */
- unsigned int r12; /* 0x30 */
- unsigned int r13; /* 0x34 */
- unsigned int sp; /* 0x38 Stack pointer */
- unsigned int pc; /* 0x3C Program counter */
-
- unsigned char p0; /* 0x40 8-bit zero-register */
- unsigned char vr; /* 0x41 Version register */
-
- unsigned short p4; /* 0x42 16-bit zero-register */
- unsigned short ccr; /* 0x44 Condition code register */
-
- unsigned int mof; /* 0x46 Multiply overflow register */
-
- unsigned int p8; /* 0x4A 32-bit zero-register */
- unsigned int ibr; /* 0x4E Interrupt base register */
- unsigned int irp; /* 0x52 Interrupt return pointer */
- unsigned int srp; /* 0x56 Subroutine return pointer */
- unsigned int bar; /* 0x5A Breakpoint address register */
- unsigned int dccr; /* 0x5E Double condition code register */
- unsigned int brp; /* 0x62 Breakpoint return pointer (pc in caller) */
- unsigned int usp; /* 0x66 User mode stack pointer */
-} registers;
-
-/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
-int getDebugChar (void);
-
-/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
-void putDebugChar (int val);
-
-void enableDebugIRQ (void);
-
-/******************** Prototypes for global functions. ***********************/
-
-/* The string str is prepended with the GDB printout token and sent. */
-void putDebugString (const unsigned char *str, int length); /* used by etrax100ser.c */
-
-/* The hook for both static (compiled) and dynamic breakpoints set by GDB.
- ETRAX 100 specific. */
-void handle_breakpoint (void); /* used by irq.c */
-
-/* The hook for an interrupt generated by GDB. ETRAX 100 specific. */
-void handle_interrupt (void); /* used by irq.c */
-
-/* A static breakpoint to be used at startup. */
-void breakpoint (void); /* called by init/main.c */
-
-/* From osys_int.c, executing_task contains the number of the current
- executing task in osys. Does not know of object-oriented threads. */
-extern unsigned char executing_task;
-
-/* The number of characters used for a 64 bit thread identifier. */
-#define HEXCHARS_IN_THREAD_ID 16
-
-/********************************** Packet I/O ******************************/
-/* BUFMAX defines the maximum number of characters in
- inbound/outbound buffers */
-#define BUFMAX 512
-
-/* Run-length encoding maximum length. Send 64 at most. */
-#define RUNLENMAX 64
-
-/* The inbound/outbound buffers used in packet I/O */
-static char remcomInBuffer[BUFMAX];
-static char remcomOutBuffer[BUFMAX];
-
-/* Error and warning messages. */
-enum error_type
-{
- SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
-};
-static char *error_message[] =
-{
- "",
- "E01 Set current or general thread - H[c,g] - internal error.",
- "E02 Change register content - P - cannot change read-only register.",
- "E03 Thread is not alive.", /* T, not used. */
- "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
- "E05 Change register content - P - the register is not implemented..",
- "E06 Change memory content - M - internal error.",
- "E07 Change register content - P - the register is not stored on the stack",
- "E08 Invalid parameter"
-};
-/********************************* Register image ****************************/
-/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's
- Reference", p. 1-1, with the additional register definitions of the
- ETRAX 100LX in cris-opc.h.
- There are 16 general 32-bit registers, R0-R15, where R14 is the stack
- pointer, SP, and R15 is the program counter, PC.
- There are 16 special registers, P0-P15, where three of the unimplemented
- registers, P0, P4 and P8, are reserved as zero-registers. A read from
- any of these registers returns zero and a write has no effect. */
-enum register_name
-{
- R0, R1, R2, R3,
- R4, R5, R6, R7,
- R8, R9, R10, R11,
- R12, R13, SP, PC,
- P0, VR, P2, P3,
- P4, CCR, P6, MOF,
- P8, IBR, IRP, SRP,
- BAR, DCCR, BRP, USP
-};
-
-/* The register sizes of the registers in register_name. An unimplemented register
- is designated by size 0 in this array. */
-static int register_size[] =
-{
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 1, 1, 0, 0,
- 2, 2, 0, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4
-};
-
-/* Contains the register image of the executing thread in the assembler
- part of the code in order to avoid horrible addressing modes. */
-registers cris_reg;
-
-/* FIXME: Should this be used? Delete otherwise. */
-/* Contains the assumed consistency state of the register image. Uses the
- enum error_type for state information. */
-static int consistency_status = SUCCESS;
-
-/********************************** Handle exceptions ************************/
-/* The variable cris_reg contains the register image associated with the
- current_thread_c variable. It is a complete register image created at
- entry. The reg_g contains a register image of a task where the general
- registers are taken from the stack and all special registers are taken
- from the executing task. It is associated with current_thread_g and used
- in order to provide access mainly for 'g', 'G' and 'P'.
-*/
-
-/********************************** Breakpoint *******************************/
-/* Use an internal stack in the breakpoint and interrupt response routines */
-#define INTERNAL_STACK_SIZE 1024
-char internal_stack[INTERNAL_STACK_SIZE];
-
-/* Due to the breakpoint return pointer, a state variable is needed to keep
- track of whether it is a static (compiled) or dynamic (gdb-invoked)
- breakpoint to be handled. A static breakpoint uses the content of register
- BRP as it is whereas a dynamic breakpoint requires subtraction with 2
- in order to execute the instruction. The first breakpoint is static. */
-static unsigned char __used is_dyn_brkp;
-
-/********************************* String library ****************************/
-/* Single-step over library functions creates trap loops. */
-
-/* Copy char s2[] to s1[]. */
-static char*
-gdb_cris_strcpy (char *s1, const char *s2)
-{
- char *s = s1;
-
- for (s = s1; (*s++ = *s2++) != '\0'; )
- ;
- return (s1);
-}
-
-/* Find length of s[]. */
-static int
-gdb_cris_strlen (const char *s)
-{
- const char *sc;
-
- for (sc = s; *sc != '\0'; sc++)
- ;
- return (sc - s);
-}
-
-/* Find first occurrence of c in s[n]. */
-static void*
-gdb_cris_memchr (const void *s, int c, int n)
-{
- const unsigned char uc = c;
- const unsigned char *su;
-
- for (su = s; 0 < n; ++su, --n)
- if (*su == uc)
- return ((void *)su);
- return (NULL);
-}
-/******************************* Standard library ****************************/
-/* Single-step over library functions creates trap loops. */
-/* Convert string to long. */
-static int
-gdb_cris_strtol (const char *s, char **endptr, int base)
-{
- char *s1;
- char *sd;
- int x = 0;
-
- for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
- x = x * base + (sd - hex_asc);
-
- if (endptr)
- {
- /* Unconverted suffix is stored in endptr unless endptr is NULL. */
- *endptr = s1;
- }
-
- return x;
-}
-
-/********************************** Packet I/O ******************************/
-
-/* Convert the memory, pointed to by mem into hexadecimal representation.
- Put the result in buf, and return a pointer to the last character
- in buf (null). */
-
-static char *
-mem2hex(char *buf, unsigned char *mem, int count)
-{
- int i;
- int ch;
-
- if (mem == NULL) {
- /* Bogus read from m0. FIXME: What constitutes a valid address? */
- for (i = 0; i < count; i++) {
- *buf++ = '0';
- *buf++ = '0';
- }
- } else {
- /* Valid mem address. */
- for (i = 0; i < count; i++) {
- ch = *mem++;
- buf = hex_byte_pack(buf, ch);
- }
- }
-
- /* Terminate properly. */
- *buf = '\0';
- return (buf);
-}
-
-/* Put the content of the array, in binary representation, pointed to by buf
- into memory pointed to by mem, and return a pointer to the character after
- the last byte written.
- Gdb will escape $, #, and the escape char (0x7d). */
-static unsigned char*
-bin2mem (unsigned char *mem, unsigned char *buf, int count)
-{
- int i;
- unsigned char *next;
- for (i = 0; i < count; i++) {
- /* Check for any escaped characters. Be paranoid and
- only unescape chars that should be escaped. */
- if (*buf == 0x7d) {
- next = buf + 1;
- if (*next == 0x3 || *next == 0x4 || *next == 0x5D) /* #, $, ESC */
- {
- buf++;
- *buf += 0x20;
- }
- }
- *mem++ = *buf++;
- }
- return (mem);
-}
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
- returned. */
-static void
-getpacket (char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- int i;
- int count;
- char ch;
- do {
- while ((ch = getDebugChar ()) != '$')
- /* Wait for the start character $ and ignore all other characters */;
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- /* Read until a # or the end of the buffer is reached */
- while (count < BUFMAX - 1) {
- ch = getDebugChar ();
- if (ch == '#')
- break;
- checksum = checksum + ch;
- buffer[count] = ch;
- count = count + 1;
- }
- buffer[count] = '\0';
-
- if (ch == '#') {
- xmitcsum = hex_to_bin(getDebugChar()) << 4;
- xmitcsum += hex_to_bin(getDebugChar());
- if (checksum != xmitcsum) {
- /* Wrong checksum */
- putDebugChar ('-');
- }
- else {
- /* Correct checksum */
- putDebugChar ('+');
- /* If sequence characters are received, reply with them */
- if (buffer[2] == ':') {
- putDebugChar (buffer[0]);
- putDebugChar (buffer[1]);
- /* Remove the sequence characters from the buffer */
- count = gdb_cris_strlen (buffer);
- for (i = 3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
- }
- }
- } while (checksum != xmitcsum);
-}
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-
-static void
-putpacket(char *buffer)
-{
- int checksum;
- int runlen;
- int encode;
-
- do {
- char *src = buffer;
- putDebugChar ('$');
- checksum = 0;
- while (*src) {
- /* Do run length encoding */
- putDebugChar (*src);
- checksum += *src;
- runlen = 0;
- while (runlen < RUNLENMAX && *src == src[runlen]) {
- runlen++;
- }
- if (runlen > 3) {
- /* Got a useful amount */
- putDebugChar ('*');
- checksum += '*';
- encode = runlen + ' ' - 4;
- putDebugChar (encode);
- checksum += encode;
- src += runlen;
- }
- else {
- src++;
- }
- }
- putDebugChar('#');
- putDebugChar(hex_asc_hi(checksum));
- putDebugChar(hex_asc_lo(checksum));
- } while(kgdb_started && (getDebugChar() != '+'));
-}
-
-/* The string str is prepended with the GDB printout token and sent. Required
- in traditional implementations. */
-void
-putDebugString (const unsigned char *str, int length)
-{
- remcomOutBuffer[0] = 'O';
- mem2hex(&remcomOutBuffer[1], (unsigned char *)str, length);
- putpacket(remcomOutBuffer);
-}
-
-/********************************* Register image ****************************/
-/* Write a value to a specified register in the register image of the current
- thread. Returns status code SUCCESS, E02, E05 or E08. */
-static int
-write_register (int regno, char *val)
-{
- int status = SUCCESS;
- registers *current_reg = &cris_reg;
-
- if (regno >= R0 && regno <= PC) {
- /* 32-bit register with simple offset. */
- if (hex2bin((unsigned char *)current_reg + regno * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
- }
- else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
- /* Do not support read-only registers. */
- status = E02;
- }
- else if (regno == CCR) {
- /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented,
- and P7 (MOF) is 32 bits in ETRAX 100LX. */
- if (hex2bin((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
- val, sizeof(unsigned short)))
- status = E08;
- }
- else if (regno >= MOF && regno <= USP) {
- /* 32 bit register with complex offset. (P8 has been taken care of.) */
- if (hex2bin((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
- }
- else {
- /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
- status = E05;
- }
- return status;
-}
-
-/* Read a value from a specified register in the register image. Returns the
- value in the register or -1 for non-implemented registers.
- Should check consistency_status after a call which may be E05 after changes
- in the implementation. */
-static int
-read_register (char regno, unsigned int *valptr)
-{
- registers *current_reg = &cris_reg;
-
- if (regno >= R0 && regno <= PC) {
- /* 32-bit register with simple offset. */
- *valptr = *(unsigned int *)((char *)current_reg + regno * sizeof(unsigned int));
- return SUCCESS;
- }
- else if (regno == P0 || regno == VR) {
- /* 8 bit register with complex offset. */
- *valptr = (unsigned int)(*(unsigned char *)
- ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char)));
- return SUCCESS;
- }
- else if (regno == P4 || regno == CCR) {
- /* 16 bit register with complex offset. */
- *valptr = (unsigned int)(*(unsigned short *)
- ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short)));
- return SUCCESS;
- }
- else if (regno >= MOF && regno <= USP) {
- /* 32 bit register with complex offset. */
- *valptr = *(unsigned int *)((char *)&(current_reg->p8)
- + (regno-P8) * sizeof(unsigned int));
- return SUCCESS;
- }
- else {
- /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
- consistency_status = E05;
- return E05;
- }
-}
-
-/********************************** Handle exceptions ************************/
-/* Build and send a response packet in order to inform the host the
- stub is stopped. TAAn...:r...;n...:r...;n...:r...;
- AA = signal number
- n... = register number (hex)
- r... = register contents
- n... = `thread'
- r... = thread process ID. This is a hex integer.
- n... = other string not starting with valid hex digit.
- gdb should ignore this n,r pair and go on to the next.
- This way we can extend the protocol. */
-static void
-stub_is_stopped(int sigval)
-{
- char *ptr = remcomOutBuffer;
- int regno;
-
- unsigned int reg_cont;
- int status;
-
- /* Send trap type (converted to signal) */
-
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- /* Send register contents. We probably only need to send the
- * PC, frame pointer and stack pointer here. Other registers will be
- * explicitly asked for. But for now, send all.
- */
-
- for (regno = R0; regno <= USP; regno++) {
- /* Store n...:r...; for the registers in the buffer. */
-
- status = read_register (regno, &reg_cont);
-
- if (status == SUCCESS) {
- ptr = hex_byte_pack(ptr, regno);
- *ptr++ = ':';
-
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont,
- register_size[regno]);
- *ptr++ = ';';
- }
-
- }
-
- /* null-terminate and send it off */
-
- *ptr = 0;
-
- putpacket (remcomOutBuffer);
-}
-
-/* Performs a complete re-start from scratch. */
-static void
-kill_restart (void)
-{
- machine_restart("");
-}
-
-/* All expected commands are sent from remote.c. Send a response according
- to the description in remote.c. */
-void
-handle_exception (int sigval)
-{
- /* Send response. */
-
- stub_is_stopped (sigval);
-
- for (;;) {
- remcomOutBuffer[0] = '\0';
- getpacket (remcomInBuffer);
- switch (remcomInBuffer[0]) {
- case 'g':
- /* Read registers: g
- Success: Each byte of register data is described by two hex digits.
- Registers are in the internal order for GDB, and the bytes
- in a register are in the same order the machine uses.
- Failure: void. */
-
- mem2hex(remcomOutBuffer, (char *)&cris_reg, sizeof(registers));
- break;
-
- case 'G':
- /* Write registers. GXX..XX
- Each byte of register data is described by two hex digits.
- Success: OK
- Failure: E08. */
- if (hex2bin((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers)))
- gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
- else
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- break;
-
- case 'P':
- /* Write register. Pn...=r...
- Write register n..., hex value without 0x, with value r...,
- which contains a hex value without 0x and two hex digits
- for each byte in the register (target byte order). P1f=11223344 means
- set register 31 to 44332211.
- Success: OK
- Failure: E02, E05, E08 */
- {
- char *suffix;
- int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16);
- int status;
- status = write_register (regno, suffix+1);
-
- switch (status) {
- case E02:
- /* Do not support read-only registers. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E02]);
- break;
- case E05:
- /* Do not support non-existing registers. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E05]);
- break;
- case E07:
- /* Do not support non-existing registers on the stack. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E07]);
- break;
- case E08:
- /* Invalid parameter. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
- break;
- default:
- /* Valid register number. */
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- break;
- }
- }
- break;
-
- case 'm':
- /* Read from memory. mAA..AA,LLLL
- AA..AA is the address and LLLL is the length.
- Success: XX..XX is the memory content. Can be fewer bytes than
- requested if only part of the data may be read. m6000120a,6c means
- retrieve 108 byte from base address 6000120a.
- Failure: void. */
- {
- char *suffix;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1],
- &suffix, 16); int length = gdb_cris_strtol(suffix+1, 0, 16);
-
- mem2hex(remcomOutBuffer, addr, length);
- }
- break;
-
- case 'X':
- /* Write to memory. XAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the binary data.
- Success: OK
- Failure: void. */
- case 'M':
- /* Write to memory. MAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the hexadecimal data.
- Success: OK
- Failure: E08. */
- {
- char *lenptr;
- char *dataptr;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1],
- &lenptr, 16);
- int length = gdb_cris_strtol(lenptr+1, &dataptr, 16);
- if (*lenptr == ',' && *dataptr == ':') {
- if (remcomInBuffer[0] == 'M') {
- if (hex2bin(addr, dataptr + 1, length))
- gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
- else
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- } else /* X */ {
- bin2mem(addr, dataptr + 1, length);
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- }
- } else {
- gdb_cris_strcpy (remcomOutBuffer, error_message[E06]);
- }
- }
- break;
-
- case 'c':
- /* Continue execution. cAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address.
- Success: return to the executing thread.
- Failure: will never know. */
- if (remcomInBuffer[1] != '\0') {
- cris_reg.pc = gdb_cris_strtol (&remcomInBuffer[1], 0, 16);
- }
- enableDebugIRQ();
- return;
-
- case 's':
- /* Step. sAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address. Success: return to the
- executing thread. Failure: will never know.
-
- Should never be invoked. The single-step is implemented on
- the host side. If ever invoked, it is an internal error E04. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E04]);
- putpacket (remcomOutBuffer);
- return;
-
- case '?':
- /* The last signal which caused a stop. ?
- Success: SAA, where AA is the signal number.
- Failure: void. */
- remcomOutBuffer[0] = 'S';
- remcomOutBuffer[1] = hex_asc_hi(sigval);
- remcomOutBuffer[2] = hex_asc_lo(sigval);
- remcomOutBuffer[3] = 0;
- break;
-
- case 'D':
- /* Detach from host. D
- Success: OK, and return to the executing thread.
- Failure: will never know */
- putpacket ("OK");
- return;
-
- case 'k':
- case 'r':
- /* kill request or reset request.
- Success: restart of target.
- Failure: will never know. */
- kill_restart ();
- break;
-
- case 'C':
- case 'S':
- case '!':
- case 'R':
- case 'd':
- /* Continue with signal sig. Csig;AA..AA
- Step with signal sig. Ssig;AA..AA
- Use the extended remote protocol. !
- Restart the target system. R0
- Toggle debug flag. d
- Search backwards. tAA:PP,MM
- Not supported: E04 */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E04]);
- break;
-
- default:
- /* The stub should ignore other request and send an empty
- response ($#<checksum>). This way we can extend the protocol and GDB
- can tell whether the stub it is talking to uses the old or the new. */
- remcomOutBuffer[0] = 0;
- break;
- }
- putpacket(remcomOutBuffer);
- }
-}
-
-/********************************** Breakpoint *******************************/
-/* The hook for both a static (compiled) and a dynamic breakpoint set by GDB.
- An internal stack is used by the stub. The register image of the caller is
- stored in the structure register_image.
- Interactive communication with the host is handled by handle_exception and
- finally the register image is restored. */
-
-void kgdb_handle_breakpoint(void);
-
-asm ("\n"
-" .global kgdb_handle_breakpoint\n"
-"kgdb_handle_breakpoint:\n"
-";;\n"
-";; Response to the break-instruction\n"
-";;\n"
-";; Create a register image of the caller\n"
-";;\n"
-" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR before disable interrupts\n"
-" di ; Disable interrupts\n"
-" move.d $r0,[cris_reg] ; Save R0\n"
-" move.d $r1,[cris_reg+0x04] ; Save R1\n"
-" move.d $r2,[cris_reg+0x08] ; Save R2\n"
-" move.d $r3,[cris_reg+0x0C] ; Save R3\n"
-" move.d $r4,[cris_reg+0x10] ; Save R4\n"
-" move.d $r5,[cris_reg+0x14] ; Save R5\n"
-" move.d $r6,[cris_reg+0x18] ; Save R6\n"
-" move.d $r7,[cris_reg+0x1C] ; Save R7\n"
-" move.d $r8,[cris_reg+0x20] ; Save R8\n"
-" move.d $r9,[cris_reg+0x24] ; Save R9\n"
-" move.d $r10,[cris_reg+0x28] ; Save R10\n"
-" move.d $r11,[cris_reg+0x2C] ; Save R11\n"
-" move.d $r12,[cris_reg+0x30] ; Save R12\n"
-" move.d $r13,[cris_reg+0x34] ; Save R13\n"
-" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n"
-";; Due to the old assembler-versions BRP might not be recognized\n"
-" .word 0xE670 ; move brp,$r0\n"
-" subq 2,$r0 ; Set to address of previous instruction.\n"
-" move.d $r0,[cris_reg+0x3c] ; Save the address in PC (R15)\n"
-" clear.b [cris_reg+0x40] ; Clear P0\n"
-" move $vr,[cris_reg+0x41] ; Save special register P1\n"
-" clear.w [cris_reg+0x42] ; Clear P4\n"
-" move $ccr,[cris_reg+0x44] ; Save special register CCR\n"
-" move $mof,[cris_reg+0x46] ; P7\n"
-" clear.d [cris_reg+0x4A] ; Clear P8\n"
-" move $ibr,[cris_reg+0x4E] ; P9,\n"
-" move $irp,[cris_reg+0x52] ; P10,\n"
-" move $srp,[cris_reg+0x56] ; P11,\n"
-" move $bar,[cris_reg+0x5A] ; P12,\n"
-" ; P13, register DCCR already saved\n"
-";; Due to the old assembler-versions BRP might not be recognized\n"
-" .word 0xE670 ; move brp,r0\n"
-";; Static (compiled) breakpoints must return to the next instruction in order\n"
-";; to avoid infinite loops. Dynamic (gdb-invoked) must restore the instruction\n"
-";; in order to execute it when execution is continued.\n"
-" test.b [is_dyn_brkp] ; Is this a dynamic breakpoint?\n"
-" beq is_static ; No, a static breakpoint\n"
-" nop\n"
-" subq 2,$r0 ; rerun the instruction the break replaced\n"
-"is_static:\n"
-" moveq 1,$r1\n"
-" move.b $r1,[is_dyn_brkp] ; Set the state variable to dynamic breakpoint\n"
-" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n"
-" move $usp,[cris_reg+0x66] ; USP\n"
-";;\n"
-";; Handle the communication\n"
-";;\n"
-" move.d internal_stack+1020,$sp ; Use the internal stack which grows upward\n"
-" moveq 5,$r10 ; SIGTRAP\n"
-" jsr handle_exception ; Interactive routine\n"
-";;\n"
-";; Return to the caller\n"
-";;\n"
-" move.d [cris_reg],$r0 ; Restore R0\n"
-" move.d [cris_reg+0x04],$r1 ; Restore R1\n"
-" move.d [cris_reg+0x08],$r2 ; Restore R2\n"
-" move.d [cris_reg+0x0C],$r3 ; Restore R3\n"
-" move.d [cris_reg+0x10],$r4 ; Restore R4\n"
-" move.d [cris_reg+0x14],$r5 ; Restore R5\n"
-" move.d [cris_reg+0x18],$r6 ; Restore R6\n"
-" move.d [cris_reg+0x1C],$r7 ; Restore R7\n"
-" move.d [cris_reg+0x20],$r8 ; Restore R8\n"
-" move.d [cris_reg+0x24],$r9 ; Restore R9\n"
-" move.d [cris_reg+0x28],$r10 ; Restore R10\n"
-" move.d [cris_reg+0x2C],$r11 ; Restore R11\n"
-" move.d [cris_reg+0x30],$r12 ; Restore R12\n"
-" move.d [cris_reg+0x34],$r13 ; Restore R13\n"
-";;\n"
-";; FIXME: Which registers should be restored?\n"
-";;\n"
-" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n"
-" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n"
-" move [cris_reg+0x5E],$dccr ; Restore DCCR\n"
-" move [cris_reg+0x66],$usp ; Restore USP\n"
-" jump [cris_reg+0x62] ; A jump to the content in register BRP works.\n"
-" nop ;\n"
-"\n");
-
-/* The hook for an interrupt generated by GDB. An internal stack is used
- by the stub. The register image of the caller is stored in the structure
- register_image. Interactive communication with the host is handled by
- handle_exception and finally the register image is restored. Due to the
- old assembler which does not recognise the break instruction and the
- breakpoint return pointer hex-code is used. */
-
-void kgdb_handle_serial(void);
-
-asm ("\n"
-" .global kgdb_handle_serial\n"
-"kgdb_handle_serial:\n"
-";;\n"
-";; Response to a serial interrupt\n"
-";;\n"
-"\n"
-" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR\n"
-" di ; Disable interrupts\n"
-" move.d $r0,[cris_reg] ; Save R0\n"
-" move.d $r1,[cris_reg+0x04] ; Save R1\n"
-" move.d $r2,[cris_reg+0x08] ; Save R2\n"
-" move.d $r3,[cris_reg+0x0C] ; Save R3\n"
-" move.d $r4,[cris_reg+0x10] ; Save R4\n"
-" move.d $r5,[cris_reg+0x14] ; Save R5\n"
-" move.d $r6,[cris_reg+0x18] ; Save R6\n"
-" move.d $r7,[cris_reg+0x1C] ; Save R7\n"
-" move.d $r8,[cris_reg+0x20] ; Save R8\n"
-" move.d $r9,[cris_reg+0x24] ; Save R9\n"
-" move.d $r10,[cris_reg+0x28] ; Save R10\n"
-" move.d $r11,[cris_reg+0x2C] ; Save R11\n"
-" move.d $r12,[cris_reg+0x30] ; Save R12\n"
-" move.d $r13,[cris_reg+0x34] ; Save R13\n"
-" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n"
-" move $irp,[cris_reg+0x3c] ; Save the address in PC (R15)\n"
-" clear.b [cris_reg+0x40] ; Clear P0\n"
-" move $vr,[cris_reg+0x41] ; Save special register P1,\n"
-" clear.w [cris_reg+0x42] ; Clear P4\n"
-" move $ccr,[cris_reg+0x44] ; Save special register CCR\n"
-" move $mof,[cris_reg+0x46] ; P7\n"
-" clear.d [cris_reg+0x4A] ; Clear P8\n"
-" move $ibr,[cris_reg+0x4E] ; P9,\n"
-" move $irp,[cris_reg+0x52] ; P10,\n"
-" move $srp,[cris_reg+0x56] ; P11,\n"
-" move $bar,[cris_reg+0x5A] ; P12,\n"
-" ; P13, register DCCR already saved\n"
-";; Due to the old assembler-versions BRP might not be recognized\n"
-" .word 0xE670 ; move brp,r0\n"
-" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n"
-" move $usp,[cris_reg+0x66] ; USP\n"
-"\n"
-";; get the serial character (from debugport.c) and check if it is a ctrl-c\n"
-"\n"
-" jsr getDebugChar\n"
-" cmp.b 3, $r10\n"
-" bne goback\n"
-" nop\n"
-"\n"
-" move.d [cris_reg+0x5E], $r10 ; Get DCCR\n"
-" btstq 8, $r10 ; Test the U-flag.\n"
-" bmi goback\n"
-" nop\n"
-"\n"
-";;\n"
-";; Handle the communication\n"
-";;\n"
-" move.d internal_stack+1020,$sp ; Use the internal stack\n"
-" moveq 2,$r10 ; SIGINT\n"
-" jsr handle_exception ; Interactive routine\n"
-"\n"
-"goback:\n"
-";;\n"
-";; Return to the caller\n"
-";;\n"
-" move.d [cris_reg],$r0 ; Restore R0\n"
-" move.d [cris_reg+0x04],$r1 ; Restore R1\n"
-" move.d [cris_reg+0x08],$r2 ; Restore R2\n"
-" move.d [cris_reg+0x0C],$r3 ; Restore R3\n"
-" move.d [cris_reg+0x10],$r4 ; Restore R4\n"
-" move.d [cris_reg+0x14],$r5 ; Restore R5\n"
-" move.d [cris_reg+0x18],$r6 ; Restore R6\n"
-" move.d [cris_reg+0x1C],$r7 ; Restore R7\n"
-" move.d [cris_reg+0x20],$r8 ; Restore R8\n"
-" move.d [cris_reg+0x24],$r9 ; Restore R9\n"
-" move.d [cris_reg+0x28],$r10 ; Restore R10\n"
-" move.d [cris_reg+0x2C],$r11 ; Restore R11\n"
-" move.d [cris_reg+0x30],$r12 ; Restore R12\n"
-" move.d [cris_reg+0x34],$r13 ; Restore R13\n"
-";;\n"
-";; FIXME: Which registers should be restored?\n"
-";;\n"
-" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n"
-" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n"
-" move [cris_reg+0x5E],$dccr ; Restore DCCR\n"
-" move [cris_reg+0x66],$usp ; Restore USP\n"
-" reti ; Return from the interrupt routine\n"
-" nop\n"
-"\n");
-
-/* Use this static breakpoint in the start-up only. */
-
-void
-breakpoint(void)
-{
- kgdb_started = 1;
- is_dyn_brkp = 0; /* This is a static, not a dynamic breakpoint. */
- __asm__ volatile ("break 8"); /* Jump to handle_breakpoint. */
-}
-
-/* initialize kgdb. doesn't break into the debugger, but sets up irq and ports */
-
-void
-kgdb_init(void)
-{
- /* could initialize debug port as well but it's done in head.S already... */
-
- /* breakpoint handler is now set in irq.c */
- set_int_vector(8, kgdb_handle_serial);
-
- enableDebugIRQ();
-}
-
-/****************************** End of file **********************************/
diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c
deleted file mode 100644
index 16848b2c61c8..000000000000
--- a/arch/cris/arch-v10/kernel/process.c
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/process.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Mikael Starvik (starvik@axis.com)
- *
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <arch/svinto.h>
-#include <linux/init.h>
-#include <arch/system.h>
-#include <linux/ptrace.h>
-
-#ifdef CONFIG_ETRAX_GPIO
-void etrax_gpio_wake_up_check(void); /* drivers/gpio.c */
-#endif
-
-/*
- * We use this if we don't have any better
- * idle routine..
- */
-void default_idle(void)
-{
-#ifdef CONFIG_ETRAX_GPIO
- etrax_gpio_wake_up_check();
-#endif
- local_irq_enable();
-}
-
-/* if the watchdog is enabled, we can simply disable interrupts and go
- * into an eternal loop, and the watchdog will reset the CPU after 0.1s
- * if on the other hand the watchdog wasn't enabled, we just enable it and wait
- */
-
-void hard_reset_now (void)
-{
- /*
- * Don't declare this variable elsewhere. We don't want any other
- * code to know about it than the watchdog handler in entry.S and
- * this code, implementing hard reset through the watchdog.
- */
-#if defined(CONFIG_ETRAX_WATCHDOG)
- extern int cause_of_death;
-#endif
-
- printk("*** HARD RESET ***\n");
- local_irq_disable();
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
- cause_of_death = 0xbedead;
-#else
- /* Since we dont plan to keep on resetting the watchdog,
- the key can be arbitrary hence three */
- *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, 3) |
- IO_STATE(R_WATCHDOG, enable, start);
-#endif
-
- while(1) /* waiting for RETRIBUTION! */ ;
-}
-
-/* setup the child's kernel stack with a pt_regs and switch_stack on it.
- * it will be un-nested during _resume and _ret_from_sys_call when the
- * new thread is scheduled.
- *
- * also setup the thread switching structure which is used to keep
- * thread-specific data during _resumes.
- *
- */
-asmlinkage void ret_from_fork(void);
-asmlinkage void ret_from_kernel_thread(void);
-
-int copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long arg, struct task_struct *p)
-{
- struct pt_regs *childregs = task_pt_regs(p);
- struct switch_stack *swstack = ((struct switch_stack *)childregs) - 1;
-
- /* put the pt_regs structure at the end of the new kernel stack page and fix it up
- * remember that the task_struct doubles as the kernel stack for the task
- */
-
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(swstack, 0,
- sizeof(struct switch_stack) + sizeof(struct pt_regs));
- swstack->r1 = usp;
- swstack->r2 = arg;
- childregs->dccr = 1 << I_DCCR_BITNR;
- swstack->return_ip = (unsigned long) ret_from_kernel_thread;
- p->thread.ksp = (unsigned long) swstack;
- p->thread.usp = 0;
- return 0;
- }
- *childregs = *current_pt_regs(); /* struct copy of pt_regs */
-
- childregs->r10 = 0; /* child returns 0 after a fork/clone */
-
- /* put the switch stack right below the pt_regs */
-
- swstack->r9 = 0; /* parameter to ret_from_sys_call, 0 == dont restart the syscall */
-
- /* we want to return into ret_from_sys_call after the _resume */
-
- swstack->return_ip = (unsigned long) ret_from_fork; /* Will call ret_from_sys_call */
-
- /* fix the user-mode stackpointer */
-
- p->thread.usp = usp ?: rdusp();
-
- /* and the kernel-mode one */
-
- p->thread.ksp = (unsigned long) swstack;
-
-#ifdef DEBUG
- printk("copy_thread: new regs at 0x%p, as shown below:\n", childregs);
- show_registers(childregs);
-#endif
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
-#if 0
- /* YURGH. TODO. */
-
- unsigned long ebp, esp, eip;
- unsigned long stack_page;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
- stack_page = (unsigned long)p;
- esp = p->thread.esp;
- if (!stack_page || esp < stack_page || esp > 8188+stack_page)
- return 0;
- /* include/asm-i386/system.h:switch_to() pushes ebp last. */
- ebp = *(unsigned long *) esp;
- do {
- if (ebp < stack_page || ebp > 8184+stack_page)
- return 0;
- eip = *(unsigned long *) (ebp+4);
- if (!in_sched_functions(eip))
- return eip;
- ebp = *(unsigned long *) ebp;
- } while (count++ < 16);
-#endif
- return 0;
-}
-#undef last_sched
-#undef first_sched
-
-void show_regs(struct pt_regs * regs)
-{
- unsigned long usp = rdusp();
-
- show_regs_print_info(KERN_DEFAULT);
-
- printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
- regs->irp, regs->srp, regs->dccr, usp, regs->mof );
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
- printk("r12: %08lx r13: %08lx oR10: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10);
-}
-
diff --git a/arch/cris/arch-v10/kernel/ptrace.c b/arch/cris/arch-v10/kernel/ptrace.c
deleted file mode 100644
index b89f57ae096e..000000000000
--- a/arch/cris/arch-v10/kernel/ptrace.c
+++ /dev/null
@@ -1,204 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2000-2003, Axis Communications AB.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/signal.h>
-#include <linux/security.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-
-/*
- * Determines which bits in DCCR the user has access to.
- * 1 = access, 0 = no access.
- */
-#define DCCR_MASK 0x0000001f /* XNZVC */
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-inline long get_reg(struct task_struct *task, unsigned int regno)
-{
- /* USP is a special case, it's not in the pt_regs struct but
- * in the tasks thread struct
- */
-
- if (regno == PT_USP)
- return task->thread.usp;
- else if (regno < PT_MAX)
- return ((unsigned long *)task_pt_regs(task))[regno];
- else
- return 0;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-inline int put_reg(struct task_struct *task, unsigned int regno,
- unsigned long data)
-{
- if (regno == PT_USP)
- task->thread.usp = data;
- else if (regno < PT_MAX)
- ((unsigned long *)task_pt_regs(task))[regno] = data;
- else
- return -1;
- return 0;
-}
-
-/*
- * Called by kernel/ptrace.c when detaching.
- *
- * Make sure the single step bit is not set.
- */
-void
-ptrace_disable(struct task_struct *child)
-{
- /* Todo - pending singlesteps? */
- clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-}
-
-/*
- * Note that this implementation of ptrace behaves differently from vanilla
- * ptrace. Contrary to what the man page says, in the PTRACE_PEEKTEXT,
- * PTRACE_PEEKDATA, and PTRACE_PEEKUSER requests the data variable is not
- * ignored. Instead, the data variable is expected to point at a location
- * (in user space) where the result of the ptrace call is written (instead of
- * being returned).
- */
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned int regno = addr >> 2;
- unsigned long __user *datap = (unsigned long __user *)data;
-
- switch (request) {
- /* Read word at location address. */
- case PTRACE_PEEKTEXT:
- case PTRACE_PEEKDATA:
- ret = generic_ptrace_peekdata(child, addr, data);
- break;
-
- /* Read the word at location address in the USER area. */
- case PTRACE_PEEKUSR: {
- unsigned long tmp;
-
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- tmp = get_reg(child, regno);
- ret = put_user(tmp, datap);
- break;
- }
-
- /* Write the word at location address. */
- case PTRACE_POKETEXT:
- case PTRACE_POKEDATA:
- ret = generic_ptrace_pokedata(child, addr, data);
- break;
-
- /* Write the word at location address in the USER area. */
- case PTRACE_POKEUSR:
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- if (regno == PT_DCCR) {
- /* don't allow the tracing process to change stuff like
- * interrupt enable, kernel/user bit, dma enables etc.
- */
- data &= DCCR_MASK;
- data |= get_reg(child, PT_DCCR) & ~DCCR_MASK;
- }
- if (put_reg(child, regno, data))
- break;
- ret = 0;
- break;
-
- /* Get all GP registers from the child. */
- case PTRACE_GETREGS: {
- int i;
- unsigned long tmp;
-
- ret = 0;
- for (i = 0; i <= PT_MAX; i++) {
- tmp = get_reg(child, i);
-
- if (put_user(tmp, datap)) {
- ret = -EFAULT;
- break;
- }
-
- datap++;
- }
-
- break;
- }
-
- /* Set all GP registers in the child. */
- case PTRACE_SETREGS: {
- int i;
- unsigned long tmp;
-
- ret = 0;
- for (i = 0; i <= PT_MAX; i++) {
- if (get_user(tmp, datap)) {
- ret = -EFAULT;
- break;
- }
-
- if (i == PT_DCCR) {
- tmp &= DCCR_MASK;
- tmp |= get_reg(child, PT_DCCR) & ~DCCR_MASK;
- }
-
- put_reg(child, i, tmp);
- datap++;
- }
-
- break;
- }
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-void do_syscall_trace(void)
-{
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
-
- if (!(current->ptrace & PT_PTRACED))
- return;
-
- /* the 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
-
- /*
- * This isn't the same as continuing with a signal, but it will do for
- * normal use.
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-}
diff --git a/arch/cris/arch-v10/kernel/setup.c b/arch/cris/arch-v10/kernel/setup.c
deleted file mode 100644
index 8e4fc248f96f..000000000000
--- a/arch/cris/arch-v10/kernel/setup.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- *
- * linux/arch/cris/arch-v10/kernel/setup.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (c) 2001-2002 Axis Communications AB
- */
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
-#include <linux/seq_file.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <linux/param.h>
-#include <arch/system.h>
-
-#ifdef CONFIG_PROC_FS
-#define HAS_FPU 0x0001
-#define HAS_MMU 0x0002
-#define HAS_ETHERNET100 0x0004
-#define HAS_TOKENRING 0x0008
-#define HAS_SCSI 0x0010
-#define HAS_ATA 0x0020
-#define HAS_USB 0x0040
-#define HAS_IRQ_BUG 0x0080
-#define HAS_MMU_BUG 0x0100
-
-static struct cpu_info {
- char *model;
- unsigned short cache;
- unsigned short flags;
-} cpu_info[] = {
- /* The first four models will never ever run this code and are
- only here for display. */
- { "ETRAX 1", 0, 0 },
- { "ETRAX 2", 0, 0 },
- { "ETRAX 3", 0, HAS_TOKENRING },
- { "ETRAX 4", 0, HAS_TOKENRING | HAS_SCSI },
- { "Unknown", 0, 0 },
- { "Unknown", 0, 0 },
- { "Unknown", 0, 0 },
- { "Simulator", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA },
- { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG },
- { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA },
- { "ETRAX 100LX", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU | HAS_MMU_BUG },
- { "ETRAX 100LX v2", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU },
- { "Unknown", 0, 0 } /* This entry MUST be the last */
-};
-
-int show_cpuinfo(struct seq_file *m, void *v)
-{
- unsigned long revision;
- struct cpu_info *info;
-
- /* read the version register in the CPU and print some stuff */
-
- revision = rdvr();
-
- if (revision >= ARRAY_SIZE(cpu_info))
- info = &cpu_info[ARRAY_SIZE(cpu_info) - 1];
- else
- info = &cpu_info[revision];
-
- seq_printf(m,
- "processor\t: 0\n"
- "cpu\t\t: CRIS\n"
- "cpu revision\t: %lu\n"
- "cpu model\t: %s\n"
- "cache size\t: %d kB\n"
- "fpu\t\t: %s\n"
- "mmu\t\t: %s\n"
- "mmu DMA bug\t: %s\n"
- "ethernet\t: %s Mbps\n"
- "token ring\t: %s\n"
- "scsi\t\t: %s\n"
- "ata\t\t: %s\n"
- "usb\t\t: %s\n"
- "bogomips\t: %lu.%02lu\n",
-
- revision,
- info->model,
- info->cache,
- info->flags & HAS_FPU ? "yes" : "no",
- info->flags & HAS_MMU ? "yes" : "no",
- info->flags & HAS_MMU_BUG ? "yes" : "no",
- info->flags & HAS_ETHERNET100 ? "10/100" : "10",
- info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no",
- info->flags & HAS_SCSI ? "yes" : "no",
- info->flags & HAS_ATA ? "yes" : "no",
- info->flags & HAS_USB ? "yes" : "no",
- (loops_per_jiffy * HZ + 500) / 500000,
- ((loops_per_jiffy * HZ + 500) / 5000) % 100);
-
- return 0;
-}
-
-#endif /* CONFIG_PROC_FS */
-
-void
-show_etrax_copyright(void)
-{
- printk(KERN_INFO
- "Linux/CRIS port on ETRAX 100LX (c) 2001 Axis Communications AB\n");
-}
diff --git a/arch/cris/arch-v10/kernel/shadows.c b/arch/cris/arch-v10/kernel/shadows.c
deleted file mode 100644
index 2e9565e868f2..000000000000
--- a/arch/cris/arch-v10/kernel/shadows.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Various shadow registers. Defines for these are in include/asm-etrax100/io.h
- */
-
-/* Shadows for internal Etrax-registers */
-
-unsigned long genconfig_shadow;
-unsigned long gen_config_ii_shadow;
-unsigned long port_g_data_shadow;
-unsigned char port_pa_dir_shadow;
-unsigned char port_pa_data_shadow;
-unsigned char port_pb_i2c_shadow;
-unsigned char port_pb_config_shadow;
-unsigned char port_pb_dir_shadow;
-unsigned char port_pb_data_shadow;
-unsigned long r_timer_ctrl_shadow;
-
-/* Shadows for external I/O port registers.
- * These are only usable if there actually IS a latch connected
- * to the corresponding external chip-select pin.
- *
- * A common usage is that CSP0 controls LEDs and CSP4 video chips.
- */
-
-unsigned long port_cse1_shadow;
-unsigned long port_csp0_shadow;
-unsigned long port_csp4_shadow;
-
-/* Corresponding addresses for the ports.
- * These are initialized in arch/cris/mm/init.c using ioremap.
- */
-
-volatile unsigned long *port_cse1_addr;
-volatile unsigned long *port_csp0_addr;
-volatile unsigned long *port_csp4_addr;
-
diff --git a/arch/cris/arch-v10/kernel/signal.c b/arch/cris/arch-v10/kernel/signal.c
deleted file mode 100644
index 2beffc37faf8..000000000000
--- a/arch/cris/arch-v10/kernel/signal.c
+++ /dev/null
@@ -1,440 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/signal.c
- *
- * Based on arch/i386/kernel/signal.c by
- * Copyright (C) 1991, 1992 Linus Torvalds
- * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson *
- *
- * Ideas also taken from arch/arm.
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-
-#include <asm/processor.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <arch/system.h>
-
-#define DEBUG_SIG 0
-
-/* a syscall in Linux/CRIS is a break 13 instruction which is 2 bytes */
-/* manipulate regs so that upon return, it will be re-executed */
-
-/* We rely on that pc points to the instruction after "break 13", so the
- * library must never do strange things like putting it in a delay slot.
- */
-#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->irp -= 2;
-
-void do_signal(int canrestart, struct pt_regs *regs);
-
-/*
- * Do a signal return; undo the signal stack.
- */
-
-struct sigframe {
- struct sigcontext sc;
- unsigned long extramask[_NSIG_WORDS-1];
- unsigned char retcode[8]; /* trampoline code */
-};
-
-struct rt_sigframe {
- struct siginfo *pinfo;
- void *puc;
- struct siginfo info;
- struct ucontext uc;
- unsigned char retcode[8]; /* trampoline code */
-};
-
-
-static int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
-{
- unsigned int err = 0;
- unsigned long old_usp;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- /* restore the regs from &sc->regs (same as sc, since regs is first)
- * (sc is already checked for VERIFY_READ since the sigframe was
- * checked in sys_sigreturn previously)
- */
-
- if (__copy_from_user(regs, sc, sizeof(struct pt_regs)))
- goto badframe;
-
- /* make sure the U-flag is set so user-mode cannot fool us */
-
- regs->dccr |= 1 << 8;
-
- /* restore the old USP as it was before we stacked the sc etc.
- * (we cannot just pop the sigcontext since we aligned the sp and
- * stuff after pushing it)
- */
-
- err |= __get_user(old_usp, &sc->usp);
-
- wrusp(old_usp);
-
- /* TODO: the other ports use regs->orig_XX to disable syscall checks
- * after this completes, but we don't use that mechanism. maybe we can
- * use it now ?
- */
-
- return err;
-
-badframe:
- return 1;
-}
-
-asmlinkage int sys_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- struct sigframe __user *frame = (struct sigframe *)rdusp();
- sigset_t set;
-
- /*
- * Since we stacked the signal on a dword boundary,
- * then frame should be dword aligned here. If it's
- * not, then the user is trying to mess with us.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__get_user(set.sig[0], &frame->sc.oldmask)
- || (_NSIG_WORDS > 1
- && __copy_from_user(&set.sig[1], frame->extramask,
- sizeof(frame->extramask))))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->sc))
- goto badframe;
-
- /* TODO: SIGTRAP when single-stepping as in arm ? */
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- struct rt_sigframe __user *frame = (struct rt_sigframe *)rdusp();
- sigset_t set;
-
- /*
- * Since we stacked the signal on a dword boundary,
- * then frame should be dword aligned here. If it's
- * not, then the user is trying to mess with us.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * Set up a signal frame.
- */
-
-static int setup_sigcontext(struct sigcontext __user *sc,
- struct pt_regs *regs, unsigned long mask)
-{
- int err = 0;
- unsigned long usp = rdusp();
-
- /* copy the regs. they are first in sc so we can use sc directly */
-
- err |= __copy_to_user(sc, regs, sizeof(struct pt_regs));
-
- /* Set the frametype to CRIS_FRAME_NORMAL for the execution of
- the signal handler. The frametype will be restored to its previous
- value in restore_sigcontext. */
- regs->frametype = CRIS_FRAME_NORMAL;
-
- /* then some other stuff */
-
- err |= __put_user(mask, &sc->oldmask);
-
- err |= __put_user(usp, &sc->usp);
-
- return err;
-}
-
-/* Figure out where we want to put the new signal frame
- * - usually on the stack. */
-
-static inline void __user *
-get_sigframe(struct ksignal *ksig, size_t frame_size)
-{
- unsigned long sp = sigsp(rdusp(), ksig);
-
- /* make sure the frame is dword-aligned */
-
- sp &= ~3;
-
- return (void __user*)(sp - frame_size);
-}
-
-/* grab and setup a signal frame.
- *
- * basically we stack a lot of state info, and arrange for the
- * user-mode program to return to the kernel using either a
- * trampoline which performs the syscall sigreturn, or a provided
- * user-mode trampoline.
- */
-
-static int setup_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct sigframe __user *frame;
- unsigned long return_ip;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
- if (err)
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- err |= __copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask));
- }
- if (err)
- return -EFAULT;
-
- /* Set up to return from userspace. If provided, use a stub
- already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long)ksig->ka.sa.sa_restorer;
- } else {
- /* trampoline - the desired return ip is the retcode itself */
- return_ip = (unsigned long)&frame->retcode;
- /* This is movu.w __NR_sigreturn, r9; break 13; */
- err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
- err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2));
- err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
-
- regs->irp = (unsigned long) ksig->ka.sa.sa_handler; /* what we enter NOW */
- regs->srp = return_ip; /* what we enter LATER */
- regs->r10 = ksig->sig; /* first argument is signo */
-
- /* actually move the usp to reflect the stacked frame */
-
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame;
- unsigned long return_ip;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
- if (err)
- return -EFAULT;
-
- /* Clear all the bits of the ucontext we don't use. */
- err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
-
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
-
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
-
- if (err)
- return -EFAULT;
-
- /* Set up to return from userspace. If provided, use a stub
- already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long)ksig->ka.sa.sa_restorer;
- } else {
- /* trampoline - the desired return ip is the retcode itself */
- return_ip = (unsigned long)&frame->retcode;
- /* This is movu.w __NR_rt_sigreturn, r9; break 13; */
- err |= __put_user(0x9c5f, (short __user *)(frame->retcode+0));
- err |= __put_user(__NR_rt_sigreturn,
- (short __user *)(frame->retcode+2));
- err |= __put_user(0xe93d, (short __user *)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
-
- /* What we enter NOW */
- regs->irp = (unsigned long) ksig->ka.sa.sa_handler;
- /* What we enter LATER */
- regs->srp = return_ip;
- /* First argument is signo */
- regs->r10 = ksig->sig;
- /* Second argument is (siginfo_t *) */
- regs->r11 = (unsigned long)&frame->info;
- /* Third argument is unused */
- regs->r12 = 0;
-
- /* Actually move the usp to reflect the stacked frame */
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-/*
- * OK, we're invoking a handler
- */
-
-static inline void handle_signal(int canrestart, struct ksignal *ksig,
- struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Are we from a system call? */
- if (canrestart) {
- /* If so, check system call restarting.. */
- switch (regs->r10) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- /* ERESTARTNOHAND means that the syscall should
- * only be restarted if there was no handler for
- * the signal, and since we only get here if there
- * is a handler, we don't restart */
- regs->r10 = -EINTR;
- break;
- case -ERESTARTSYS:
- /* ERESTARTSYS means to restart the syscall if
- * there is no handler or the handler was
- * registered with SA_RESTART */
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->r10 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- /* ERESTARTNOINTR means that the syscall should
- * be called again after the signal handler returns. */
- RESTART_CRIS_SYS(regs);
- }
- }
-
- /* Set up the stack frame */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset, regs);
- else
- ret = setup_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, 0);
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Also note that the regs structure given here as an argument, is the latest
- * pushed pt_regs. It may or may not be the same as the first pushed registers
- * when the initial usermode->kernelmode transition took place. Therefore
- * we can use user_mode(regs) to see if we came directly from kernel or user
- * mode below.
- */
-
-void do_signal(int canrestart, struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- /*
- * We want the common case to go fast, which
- * is why we may in certain cases get here from
- * kernel mode. Just return without doing anything
- * if so.
- */
- if (!user_mode(regs))
- return;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(canrestart, &ksig, regs);
- return;
- }
-
- /* Did we come from a system call? */
- if (canrestart) {
- /* Restart the system call - no handlers present */
- if (regs->r10 == -ERESTARTNOHAND ||
- regs->r10 == -ERESTARTSYS ||
- regs->r10 == -ERESTARTNOINTR) {
- RESTART_CRIS_SYS(regs);
- }
- if (regs->r10 == -ERESTART_RESTARTBLOCK) {
- regs->r9 = __NR_restart_syscall;
- regs->irp -= 2;
- }
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c
deleted file mode 100644
index 3d78373db254..000000000000
--- a/arch/cris/arch-v10/kernel/time.c
+++ /dev/null
@@ -1,268 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v10/kernel/time.c
- *
- * Copyright (C) 1991, 1992, 1995 Linus Torvalds
- * Copyright (C) 1999-2002 Axis Communications AB
- *
- */
-
-#include <linux/timex.h>
-#include <linux/time.h>
-#include <linux/jiffies.h>
-#include <linux/interrupt.h>
-#include <linux/swap.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <asm/types.h>
-#include <asm/signal.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq_regs.h>
-
-/* define this if you need to use print_timestamp */
-/* it will make jiffies at 96 hz instead of 100 hz though */
-#undef USE_CASCADE_TIMERS
-
-unsigned long get_ns_in_jiffie(void)
-{
- unsigned char timer_count, t1;
- unsigned short presc_count;
- unsigned long ns;
- unsigned long flags;
-
- local_irq_save(flags);
- timer_count = *R_TIMER0_DATA;
- presc_count = *R_TIM_PRESC_STATUS;
- /* presc_count might be wrapped */
- t1 = *R_TIMER0_DATA;
-
- if (timer_count != t1){
- /* it wrapped, read prescaler again... */
- presc_count = *R_TIM_PRESC_STATUS;
- timer_count = t1;
- }
- local_irq_restore(flags);
- if (presc_count >= PRESCALE_VALUE/2 ){
- presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
- } else {
- presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
- }
-
- ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
- ( (presc_count) * (1000000000/PRESCALE_FREQ));
- return ns;
-}
-
-static u32 cris_v10_gettimeoffset(void)
-{
- u32 count;
-
- /* The timer interrupt comes from Etrax timer 0. In order to get
- * better precision, we check the current value. It might have
- * underflowed already though.
- */
- count = *R_TIMER0_DATA;
-
- /* Convert timer value to nsec */
- return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV;
-}
-
-/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
- *
- * 3.10.4 Watchdog timer
-
- * When the watchdog timer is started, it generates an NMI if the watchdog
- * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
- * stopped after an additional 3.3 ms, the watchdog resets the chip.
- * The watchdog timer is stopped after reset. The watchdog timer is controlled
- * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
- * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
- * described in the table below:
- *
- * Watchdog Value written:
- * state: To enable: To key: Operation:
- * -------- ---------- ------- ----------
- * stopped 0 X No effect.
- * stopped 1 key_val Start watchdog with key = key_val.
- * started 0 ~key Stop watchdog
- * started 1 ~key Restart watchdog with key = ~key.
- * started X new_key_val Change key to new_key_val.
- *
- * Note: '~' is the bitwise NOT operator.
- *
- */
-
-/* right now, starting the watchdog is the same as resetting it */
-#define start_watchdog reset_watchdog
-
-#ifdef CONFIG_ETRAX_WATCHDOG
-static int watchdog_key = 0; /* arbitrary number */
-#endif
-
-/* number of pages to consider "out of memory". it is normal that the memory
- * is used though, so put this really low.
- */
-
-#define WATCHDOG_MIN_FREE_PAGES 8
-
-void reset_watchdog(void)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- /* only keep watchdog happy as long as we have memory left! */
- if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
- /* reset the watchdog with the inverse of the old key */
- watchdog_key ^= 0x7; /* invert key, which is 3 bits */
- *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
- IO_STATE(R_WATCHDOG, enable, start);
- }
-#endif
-}
-
-/* stop the watchdog - we still need the correct key */
-
-void stop_watchdog(void)
-{
-#ifdef CONFIG_ETRAX_WATCHDOG
- watchdog_key ^= 0x7; /* invert key, which is 3 bits */
- *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
- IO_STATE(R_WATCHDOG, enable, stop);
-#endif
-}
-
-
-extern void cris_do_profile(struct pt_regs *regs);
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
- struct pt_regs *regs = get_irq_regs();
- /* acknowledge the timer irq */
-
-#ifdef USE_CASCADE_TIMERS
- *R_TIMER_CTRL =
- IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
- IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
- IO_STATE( R_TIMER_CTRL, i1, clr) |
- IO_STATE( R_TIMER_CTRL, tm1, run) |
- IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
- IO_STATE( R_TIMER_CTRL, i0, clr) |
- IO_STATE( R_TIMER_CTRL, tm0, run) |
- IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-#else
- *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
-#endif
-
- /* reset watchdog otherwise it resets us! */
- reset_watchdog();
-
- /* Update statistics. */
- update_process_times(user_mode(regs));
-
- /* call the real timer interrupt handler */
- xtime_update(1);
-
- cris_do_profile(regs); /* Save profiling information */
- return IRQ_HANDLED;
-}
-
-/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */
-
-static struct irqaction irq2 = {
- .handler = timer_interrupt,
- .flags = IRQF_SHARED,
- .name = "timer",
-};
-
-void __init time_init(void)
-{
- arch_gettimeoffset = cris_v10_gettimeoffset;
-
- /* probe for the RTC and read it if it exists
- * Before the RTC can be probed the loops_per_usec variable needs
- * to be initialized to make usleep work. A better value for
- * loops_per_usec is calculated by the kernel later once the
- * clock has started.
- */
- loops_per_usec = 50;
-
- /* Setup the etrax timers
- * Base frequency is 25000 hz, divider 250 -> 100 HZ
- * In normal mode, we use timer0, so timer1 is free. In cascade
- * mode (which we sometimes use for debugging) both timers are used.
- * Remember that linux/timex.h contains #defines that rely on the
- * timer settings below (hz and divide factor) !!!
- */
-
-#ifdef USE_CASCADE_TIMERS
- *R_TIMER_CTRL =
- IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
- IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
- IO_STATE( R_TIMER_CTRL, i1, nop) |
- IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
- IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
- IO_STATE( R_TIMER_CTRL, i0, nop) |
- IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
- IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
- IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
- IO_STATE( R_TIMER_CTRL, i1, nop) |
- IO_STATE( R_TIMER_CTRL, tm1, run) |
- IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
- IO_STATE( R_TIMER_CTRL, i0, nop) |
- IO_STATE( R_TIMER_CTRL, tm0, run) |
- IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-#else
- *R_TIMER_CTRL =
- IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
- IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
- IO_STATE(R_TIMER_CTRL, i1, nop) |
- IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
- IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
- IO_STATE(R_TIMER_CTRL, i0, nop) |
- IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
- IO_STATE(R_TIMER_CTRL, clksel0, flexible);
-
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
- IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
- IO_STATE(R_TIMER_CTRL, i1, nop) |
- IO_STATE(R_TIMER_CTRL, tm1, run) |
- IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
- IO_STATE(R_TIMER_CTRL, i0, nop) |
- IO_STATE(R_TIMER_CTRL, tm0, run) |
- IO_STATE(R_TIMER_CTRL, clksel0, flexible);
-
- *R_TIMER_PRESCALE = PRESCALE_VALUE;
-#endif
-
- /* unmask the timer irq */
- *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
-
- /* now actually register the irq handler that calls timer_interrupt() */
- setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
-
- /* enable watchdog if we should use one */
-#if defined(CONFIG_ETRAX_WATCHDOG)
- printk("Enabling watchdog...\n");
- start_watchdog();
-
- /* If we use the hardware watchdog, we want to trap it as an NMI
- and dump registers before it resets us. For this to happen, we
- must set the "m" NMI enable flag (which once set, is unset only
- when an NMI is taken).
-
- The same goes for the external NMI, but that doesn't have any
- driver or infrastructure support yet. */
- asm ("setf m");
-
- *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
- *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
-#endif
-}
diff --git a/arch/cris/arch-v10/kernel/traps.c b/arch/cris/arch-v10/kernel/traps.c
deleted file mode 100644
index 876d45b957f4..000000000000
--- a/arch/cris/arch-v10/kernel/traps.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Helper functions for trap handlers
- *
- * Copyright (C) 2000-2007, Axis Communications AB.
- *
- * Authors: Bjorn Wesen
- * Hans-Peter Nilsson
- *
- */
-
-#include <linux/ptrace.h>
-#include <linux/uaccess.h>
-#include <linux/sched/debug.h>
-
-#include <arch/sv_addr_ag.h>
-#include <arch/system.h>
-
-void
-show_registers(struct pt_regs *regs)
-{
- /*
- * It's possible to use either the USP register or current->thread.usp.
- * USP might not correspond to the current process for all cases this
- * function is called, and current->thread.usp isn't up to date for the
- * current process. Experience shows that using USP is the way to go.
- */
- unsigned long usp = rdusp();
-
- printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
- regs->irp, regs->srp, regs->dccr, usp, regs->mof);
-
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
-
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
-
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
-
- printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, (long unsigned)regs);
-
- printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE);
-
- printk("Process %s (pid: %d, stackpage=%08lx)\n",
- current->comm, current->pid, (unsigned long)current);
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- int i;
-
- show_stack(NULL, (unsigned long *)usp);
-
- /*
- * If the previous stack-dump wasn't a kernel one, dump the
- * kernel stack now.
- */
- if (usp != 0)
- show_stack(NULL, NULL);
-
- printk("\nCode: ");
-
- if (regs->irp < PAGE_OFFSET)
- goto bad_value;
-
- /*
- * Quite often the value at regs->irp doesn't point to the
- * interesting instruction, which often is the previous
- * instruction. So dump at an offset large enough that the
- * instruction decoding should be in sync at the interesting
- * point, but small enough to fit on a row. The regs->irp
- * location is pointed out in a ksymoops-friendly way by
- * wrapping the byte for that address in parenthesises.
- */
- for (i = -12; i < 12; i++) {
- unsigned char c;
-
- if (__get_user(c, &((unsigned char *)regs->irp)[i])) {
-bad_value:
- printk(" Bad IP value.");
- break;
- }
-
- if (i == 0)
- printk("(%02x) ", c);
- else
- printk("%02x ", c);
- }
- printk("\n");
- }
-}
-
-void
-arch_enable_nmi(void)
-{
- asm volatile ("setf m");
-}
-
-extern void (*nmi_handler)(struct pt_regs *);
-void handle_nmi(struct pt_regs *regs)
-{
- if (nmi_handler)
- nmi_handler(regs);
-
- /* Wait until nmi is no longer active. (We enable NMI immediately after
- returning from this function, and we don't want it happening while
- exiting from the NMI interrupt handler.) */
- while (*R_IRQ_MASK0_RD & IO_STATE(R_IRQ_MASK0_RD, nmi_pin, active))
- ;
-}
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-void
-handle_BUG(struct pt_regs *regs)
-{
- struct bug_frame f;
- unsigned char c;
- unsigned long irp = regs->irp;
-
- if (__copy_from_user(&f, (const void __user *)(irp - 8), sizeof f))
- return;
- if (f.prefix != BUG_PREFIX || f.magic != BUG_MAGIC)
- return;
- if (__get_user(c, f.filename))
- f.filename = "<bad filename>";
-
- printk("kernel BUG at %s:%d!\n", f.filename, f.line);
-}
-#endif
diff --git a/arch/cris/arch-v10/lib/Makefile b/arch/cris/arch-v10/lib/Makefile
deleted file mode 100644
index 725153edb764..000000000000
--- a/arch/cris/arch-v10/lib/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for Etrax-specific library files..
-#
-
-lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o
-
diff --git a/arch/cris/arch-v10/lib/checksum.S b/arch/cris/arch-v10/lib/checksum.S
deleted file mode 100644
index a3b96391706f..000000000000
--- a/arch/cris/arch-v10/lib/checksum.S
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum routine using movem
- * Copyright (c) 1998-2001 Axis Communications AB
- *
- * csum_partial(const unsigned char * buff, int len, unsigned int sum)
- */
-
- .globl csum_partial
-csum_partial:
-
- ;; r10 - src
- ;; r11 - length
- ;; r12 - checksum
-
- ;; check for breakeven length between movem and normal word looping versions
- ;; we also do _NOT_ want to compute a checksum over more than the
- ;; actual length when length < 40
-
- cmpu.w 80,$r11
- blo _word_loop
- nop
-
- ;; need to save the registers we use below in the movem loop
- ;; this overhead is why we have a check above for breakeven length
- ;; only r0 - r8 have to be saved, the other ones are clobber-able
- ;; according to the ABI
-
- subq 9*4,$sp
- movem $r8,[$sp]
-
- ;; do a movem checksum
-
- subq 10*4,$r11 ; update length for the first loop
-
-_mloop: movem [$r10+],$r9 ; read 10 longwords
-
- ;; perform dword checksumming on the 10 longwords
-
- add.d $r0,$r12
- ax
- add.d $r1,$r12
- ax
- add.d $r2,$r12
- ax
- add.d $r3,$r12
- ax
- add.d $r4,$r12
- ax
- add.d $r5,$r12
- ax
- add.d $r6,$r12
- ax
- add.d $r7,$r12
- ax
- add.d $r8,$r12
- ax
- add.d $r9,$r12
-
- ;; fold the carry into the checksum, to avoid having to loop the carry
- ;; back into the top
-
- ax
- addq 0,$r12
-
- subq 10*4,$r11
- bge _mloop
- nop
-
- addq 10*4,$r11 ; compensate for last loop underflowing length
-
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- ;; only fold if there is anything to fold.
-
- cmpq 0,$r12
- beq _no_fold
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below.
- ;; r9 and r13 can be used as temporaries.
-
- moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9
- lsrq 16,$r9
-
- move.d $r12,$r13
- lsrq 16,$r13 ; r13 = checksum >> 16
- and.d $r9,$r12 ; checksum = checksum & 0xffff
- add.d $r13,$r12 ; checksum += r13
-
-_no_fold:
- cmpq 2,$r11
- blt _no_words
- nop
-
- ;; checksum the rest of the words
-
- subq 2,$r11
-
-_wloop: subq 2,$r11
- bge _wloop
- addu.w [$r10+],$r12
-
- addq 2,$r11
-
-_no_words:
- ;; see if we have one odd byte more
- cmpq 1,$r11
- beq _do_byte
- nop
- ret
- move.d $r12, $r10
-
-_do_byte:
- ;; copy and checksum the last byte
- addu.b [$r10],$r12
- ret
- move.d $r12, $r10
-
diff --git a/arch/cris/arch-v10/lib/checksumcopy.S b/arch/cris/arch-v10/lib/checksumcopy.S
deleted file mode 100644
index b21449cb1ad3..000000000000
--- a/arch/cris/arch-v10/lib/checksumcopy.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum+copy routine using movem
- * Copyright (c) 1998, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * csum_partial_copy_nocheck(const char *src, char *dst,
- * int len, unsigned int sum)
- */
-
- .globl csum_partial_copy_nocheck
-csum_partial_copy_nocheck:
-
- ;; r10 - src
- ;; r11 - dst
- ;; r12 - length
- ;; r13 - checksum
-
- ;; check for breakeven length between movem and normal word looping versions
- ;; we also do _NOT_ want to compute a checksum over more than the
- ;; actual length when length < 40
-
- cmpu.w 80, $r12
- blo _word_loop
- nop
-
- ;; need to save the registers we use below in the movem loop
- ;; this overhead is why we have a check above for breakeven length
- ;; only r0 - r8 have to be saved, the other ones are clobber-able
- ;; according to the ABI
-
- subq 9*4, $sp
- movem $r8, [$sp]
-
- ;; do a movem copy and checksum
-
- subq 10*4, $r12 ; update length for the first loop
-
-_mloop: movem [$r10+],$r9 ; read 10 longwords
-1: ;; A failing userspace access will have this as PC.
- movem $r9,[$r11+] ; write 10 longwords
-
- ;; perform dword checksumming on the 10 longwords
-
- add.d $r0,$r13
- ax
- add.d $r1,$r13
- ax
- add.d $r2,$r13
- ax
- add.d $r3,$r13
- ax
- add.d $r4,$r13
- ax
- add.d $r5,$r13
- ax
- add.d $r6,$r13
- ax
- add.d $r7,$r13
- ax
- add.d $r8,$r13
- ax
- add.d $r9,$r13
-
- ;; fold the carry into the checksum, to avoid having to loop the carry
- ;; back into the top
-
- ax
- addq 0,$r13
-
- subq 10*4,$r12
- bge _mloop
- nop
-
- addq 10*4,$r12 ; compensate for last loop underflowing length
-
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- ;; only fold if there is anything to fold.
-
- cmpq 0,$r13
- beq _no_fold
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below
- ;; r9 can be used as temporary.
-
- move.d $r13,$r9
- lsrq 16,$r9 ; r0 = checksum >> 16
- and.d 0xffff,$r13 ; checksum = checksum & 0xffff
- add.d $r9,$r13 ; checksum += r0
-
-_no_fold:
- cmpq 2,$r12
- blt _no_words
- nop
-
- ;; copy and checksum the rest of the words
-
- subq 2,$r12
-
-_wloop: move.w [$r10+],$r9
-2: ;; A failing userspace access will have this as PC.
- addu.w $r9,$r13
- subq 2,$r12
- bge _wloop
- move.w $r9,[$r11+]
-
- addq 2,$r12
-
-_no_words:
- ;; see if we have one odd byte more
- cmpq 1,$r12
- beq _do_byte
- nop
- ret
- move.d $r13, $r10
-
-_do_byte:
- ;; copy and checksum the last byte
- move.b [$r10],$r9
-3: ;; A failing userspace access will have this as PC.
- addu.b $r9,$r13
- move.b $r9,[$r11]
- ret
- move.d $r13, $r10
diff --git a/arch/cris/arch-v10/lib/csumcpfruser.S b/arch/cris/arch-v10/lib/csumcpfruser.S
deleted file mode 100644
index beb8992ed478..000000000000
--- a/arch/cris/arch-v10/lib/csumcpfruser.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into
- * csum_partial_copy_from_user by adding exception records.
- *
- * Copyright (C) 2001 Axis Communications AB.
- *
- * Author: Hans-Peter Nilsson.
- */
-
-#include <asm/errno.h>
-
-/* Same function body, but a different name. If we just added exception
- records to _csum_partial_copy_nocheck and made it generic, we wouldn't
- know a user fault from a kernel fault and we would have overhead in
- each kernel caller for the error-pointer argument.
-
- unsigned int csum_partial_copy_from_user
- (const char *src, char *dst, int len, unsigned int sum, int *errptr);
-
- Note that the errptr argument is only set if we encounter an error.
- It is conveniently located on the stack, so the normal function body
- does not have to handle it. */
-
-#define csum_partial_copy_nocheck csum_partial_copy_from_user
-
-/* There are local labels numbered 1, 2 and 3 present to mark the
- different from-user accesses. */
-#include "checksumcopy.S"
-
- .section .fixup,"ax"
-
-;; Here from the movem loop; restore stack.
-4:
- movem [$sp+],$r8
-;; r12 is already decremented. Add back chunk_size-2.
- addq 40-2,$r12
-
-;; Here from the word loop; r12 is off by 2; add it back.
-5:
- addq 2,$r12
-
-;; Here from a failing single byte.
-6:
-
-;; Signal in *errptr that we had a failing access.
- moveq -EFAULT,$r9
- move.d $r9,[[$sp]]
-
-;; Clear the rest of the destination area using memset. Preserve the
-;; checksum for the readable bytes.
- push $srp
- push $r13
- move.d $r11,$r10
- clear.d $r11
- jsr memset
- pop $r10
- jump [$sp+]
-
- .previous
- .section __ex_table,"a"
- .dword 1b,4b
- .dword 2b,5b
- .dword 3b,6b
- .previous
diff --git a/arch/cris/arch-v10/lib/dram_init.S b/arch/cris/arch-v10/lib/dram_init.S
deleted file mode 100644
index fd7437577938..000000000000
--- a/arch/cris/arch-v10/lib/dram_init.S
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DRAM/SDRAM initialization - alter with care
- * This file is intended to be included from other assembler files
- *
- * Note: This file may not modify r9 because r9 is used to carry
- * information from the decompressor to the kernel
- *
- * Copyright (C) 2000-2012 Axis Communications AB
- *
- */
-
-/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
- * uses this code.
- */
-
-
- ;; WARNING! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below.
-
- move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
- move.d $r0, [R_WAITSTATES]
-
- move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
- move.d $r0, [R_BUS_CONFIG]
-
-#ifndef CONFIG_ETRAX_SDRAM
- move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
- move.d $r0, [R_DRAM_CONFIG]
-
- move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
- move.d $r0, [R_DRAM_TIMING]
-#else
- ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
- moveq 2, $r6
-_sdram_init:
-
- ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
-
- ; Bank configuration
- move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
- move.d $r0, [R_SDRAM_CONFIG]
-
- ; Calculate value of mrs_data
- ; CAS latency = 2 && bus_width = 32 => 0x40
- ; CAS latency = 3 && bus_width = 32 => 0x60
- ; CAS latency = 2 && bus_width = 16 => 0x20
- ; CAS latency = 3 && bus_width = 16 => 0x30
-
- ; Check if value is already supplied in kernel config
- move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
- and.d 0x00ff0000, $r2
- bne _set_timing
- lsrq 16, $r2
-
- move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
- move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
- move.d $r1, $r3
- and.d 0x03, $r1 ; Get CAS latency
- and.d 0x1000, $r3 ; 50 or 100 MHz?
- beq _speed_50
- nop
-_speed_100:
- cmp.d 0x00, $r1 ; CAS latency = 2?
- beq _bw_check
- nop
- or.d 0x20, $r2 ; CAS latency = 3
- ba _bw_check
- nop
-_speed_50:
- cmp.d 0x01, $r1 ; CAS latency = 2?
- beq _bw_check
- nop
- or.d 0x20, $r2 ; CAS latency = 3
-_bw_check:
- move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
- and.d 0x800000, $r1 ; DRAM width is bit 23
- bne _set_timing
- nop
- lsrq 1, $r2 ; 16 bits. Shift down value.
-
- ; Set timing parameters. Starts master clock
-_set_timing:
- move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
- and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
- or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
- move.d $r1, $r5
- or.d 0x0000c000, $r1 ; ref = disable
- lslq 16, $r2 ; mrs data starts at bit 16
- or.d $r2, $r1
- move.d $r1, [R_SDRAM_TIMING]
-
- ; Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Issue initialization command sequence
- move.d _sdram_commands_start, $r2
- and.d 0x000fffff, $r2 ; Make sure commands are read from flash
- move.d _sdram_commands_end, $r3
- and.d 0x000fffff, $r3
-1: clear.d $r4
- move.b [$r2+], $r4
- lslq 9, $r4 ; Command starts at bit 9
- or.d $r1, $r4
- move.d $r4, [R_SDRAM_TIMING]
- nop ; Wait five nop cycles between each command
- nop
- nop
- nop
- nop
- cmp.d $r2, $r3
- bne 1b
- nop
- move.d $r5, [R_SDRAM_TIMING]
- subq 1, $r6
- bne _sdram_init
- nop
- ba _sdram_commands_end
- nop
-
-_sdram_commands_start:
- .byte 3 ; Precharge
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 1 ; mrs
- .byte 0 ; nop
-_sdram_commands_end:
-#endif
diff --git a/arch/cris/arch-v10/lib/hw_settings.S b/arch/cris/arch-v10/lib/hw_settings.S
deleted file mode 100644
index 0d449852517e..000000000000
--- a/arch/cris/arch-v10/lib/hw_settings.S
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This table is used by some tools to extract hardware parameters.
- * The table should be included in the kernel and the decompressor.
- * Don't forget to update the tools if you change this table.
- *
- * Copyright (C) 2001 Axis Communications AB
- *
- * Authors: Mikael Starvik (starvik@axis.com)
- */
-
-#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
- (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
-#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
- (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
- (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
-
- .ascii "HW_PARAM_MAGIC" ; Magic number
- .dword 0xc0004000 ; Kernel start address
-
- ; Debug port
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- .dword 0
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- .dword 1
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- .dword 2
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- .dword 3
-#else
- .dword 4 ; No debug
-#endif
-
- ; SDRAM or EDO DRAM?
-#ifdef CONFIG_ETRAX_SDRAM
- .dword 1
-#else
- .dword 0
-#endif
-
- ; Register values
- .dword R_WAITSTATES
- .dword CONFIG_ETRAX_DEF_R_WAITSTATES
- .dword R_BUS_CONFIG
- .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
-#ifdef CONFIG_ETRAX_SDRAM
- .dword R_SDRAM_CONFIG
- .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG
- .dword R_SDRAM_TIMING
- .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING
-#else
- .dword R_DRAM_CONFIG
- .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
- .dword R_DRAM_TIMING
- .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
-#endif
- .dword R_PORT_PA_SET
- .dword PA_SET_VALUE
- .dword R_PORT_PB_SET
- .dword PB_SET_VALUE
- .dword 0 ; No more register values
diff --git a/arch/cris/arch-v10/lib/memset.c b/arch/cris/arch-v10/lib/memset.c
deleted file mode 100644
index c94ea9b3ec29..000000000000
--- a/arch/cris/arch-v10/lib/memset.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* A memset for CRIS.
- Copyright (C) 1999-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-/* Note the multiple occurrence of the expression "12*4", including the
- asm. It is hard to get it into the asm in a good way. Thus better to
- expose the problem everywhere: no macro. */
-
-/* Assuming one cycle per dword written or read (ok, not really true; the
- world is not ideal), and one cycle per instruction, then 43+3*(n/48-1)
- <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full
- 48-byte block to set. */
-
-#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *memset(void *pdst, int c, unsigned int plen)
-{
- /* Now we want the parameters in special registers. Make sure the
- compiler does something usable with this. */
-
- register char *return_dst __asm__ ("r10") = pdst;
- register int n __asm__ ("r12") = plen;
- register int lc __asm__ ("r11") = c;
-
- /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get
- penalized here compared to the generic implementation. */
-
- /* This is fragile performancewise at best. Check with newer GCC
- releases, if they compile cascaded "x |= x << 8" to sane code. */
- __asm__("movu.b %0,r13 \n\
- lslq 8,r13 \n\
- move.b %0,r13 \n\
- move.d r13,%0 \n\
- lslq 16,r13 \n\
- or.d r13,%0"
- : "=r" (lc) /* Inputs. */
- : "0" (lc) /* Outputs. */
- : "r13"); /* Trash. */
-
- {
- register char *dst __asm__ ("r13") = pdst;
-
- if (((unsigned long) pdst & 3) != 0
- /* Oops! n = 0 must be a valid call, regardless of alignment. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- *dst = (char) lc;
- n--;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- *(short *) dst = lc;
- n -= 2;
- dst += 2;
- }
- }
-
- /* Decide which setting method to use. */
- if (n >= MEMSET_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-block sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%4,$r13-$r12-$r11 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- move.d r11,r0 \n\
- move.d r11,r1 \n\
- move.d r11,r2 \n\
- move.d r11,r3 \n\
- move.d r11,r4 \n\
- move.d r11,r5 \n\
- move.d r11,r6 \n\
- move.d r11,r7 \n\
- move.d r11,r8 \n\
- move.d r11,r9 \n\
- move.d r11,r10 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" subq 12*4,r12 \n\
- bge 0b \n\
- movem r11,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 12*4,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (n), "r" (lc));
- }
-
- /* An ad-hoc unroll, used for 4*12-1..16 bytes. */
- while (n >= 16)
- {
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = (char) lc;
- break;
-
- case 2:
- *(short *) dst = (short) lc;
- break;
-
- case 3:
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 4:
- *(long *) dst = lc;
- break;
-
- case 5:
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 6:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 7:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 8:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 9:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 10:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 11:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 12:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 13:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 14:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 15:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
- }
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v10/lib/string.c b/arch/cris/arch-v10/lib/string.c
deleted file mode 100644
index c7bd6ebdc93c..000000000000
--- a/arch/cris/arch-v10/lib/string.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* A memcpy for CRIS.
- Copyright (C) 1994-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-#include <stddef.h>
-
-/* Break even between movem and move16 is really at 38.7 * 2, but
- modulo 44, so up to the next multiple of 44, we use ordinary code. */
-#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *
-memcpy(void *pdst, const void *psrc, size_t pn)
-{
- /* Now we want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- If gcc was allright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register void *return_dst __asm__ ("r10") = pdst;
- register unsigned char *dst __asm__ ("r13") = pdst;
- register unsigned const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- n--;
- *dst = *src;
- src++;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- n -= 2;
- *(short *) dst = *(short *) src;
- src += 2;
- dst += 2;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= MEMCPY_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%2,$r13-$r11-$r12 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop. \n\
- subq 44,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" movem [r11+],r10 \n\
- subq 44,r12 \n\
- bge 0b \n\
- movem r10,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 44,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (src), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (src), "2" (n));
- }
-
- while (n >= 16)
- {
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
-
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = *src;
- break;
-
- case 2:
- *(short *) dst = *(short *) src;
- break;
-
- case 3:
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 4:
- *(long *) dst = *(long *) src;
- break;
-
- case 5:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 6:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 7:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 8:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 9:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 10:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 11:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 12:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 13:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 14:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 15:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v10/lib/usercopy.c b/arch/cris/arch-v10/lib/usercopy.c
deleted file mode 100644
index 3f1e2f4680f7..000000000000
--- a/arch/cris/arch-v10/lib/usercopy.c
+++ /dev/null
@@ -1,511 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * User address space access functions.
- * The non-inlined parts of asm-cris/uaccess.h are here.
- *
- * Copyright (C) 2000, Axis Communications AB.
- *
- * Written by Hans-Peter Nilsson.
- * Pieces used from memcpy, originally by Kenny Ranerup long time ago.
- */
-
-#include <linux/uaccess.h>
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
- satisfactory results for "gcc version 2.96 20000427 (experimental)".
-
- Check regularly...
-
- Note that the PC saved at a bus-fault is the address *after* the
- faulting instruction, which means the branch-target for instructions in
- delay-slots for taken branches. Note also that the postincrement in
- the instruction is performed regardless of bus-fault; the register is
- seen updated in fault handlers.
-
- Oh, and on the code formatting issue, to whomever feels like "fixing
- it" to Conformity: I'm too "lazy", but why don't you go ahead and "fix"
- string.c too. I just don't think too many people will hack this file
- for the code format to be an issue. */
-
-
-/* Copy to userspace. This is based on the memcpy used for
- kernel-to-kernel copying; see "string.c". */
-
-unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_copy_to_user_1 (dst, src, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_copy_to_user_2 (dst, src, retn);
- n -= 2;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= 44*2) /* Break even between movem and
- move16 is at 38.7*2, but modulo 44. */
- {
- /* For large copies we use 'movem'. */
-
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- "r13=r13, r11=r11, r12=r12". */
- __asm__ volatile ("\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
- \n\
-; Since the noted PC of a faulting instruction in a delay-slot of a taken \n\
-; branch, is that of the branch target, we actually point at the from-movem \n\
-; for this case. There is no ambiguity here; if there was a fault in that \n\
-; instruction (meaning a kernel oops), the faulted PC would be the address \n\
-; after *that* movem. \n\
- \n\
-0: \n\
- movem [$r11+],$r10 \n\
- subq 44,$r12 \n\
- bge 0b \n\
- movem $r10,[$r13+] \n\
-1: \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
- \n\
-; To provide a correct count in r10 of bytes that failed to be copied, \n\
-; we jump back into the loop if the loop-branch was taken. There is no \n\
-; performance penalty for sany use; the program will segfault soon enough.\n\
- \n\
-3: \n\
- move.d [$sp],$r10 \n\
- addq 44,$r10 \n\
- move.d $r10,[$sp] \n\
- jump 0b \n\
-4: \n\
- movem [$sp+],$r10 \n\
- addq 44,$r10 \n\
- addq 44,$r12 \n\
- jump 2b \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 0b,3b \n\
- .dword 1b,4b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
-
- }
-
- /* Either we directly start copying, using dword copying in a loop, or
- we copy as much as possible with 'movem' and then the last block (<44
- bytes) is copied here. This will work since 'movem' will have
- updated SRC, DST and N. */
-
- while (n >= 16)
- {
- __asm_copy_to_user_16 (dst, src, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_copy_to_user_4 (dst, src, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_copy_to_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_to_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_to_user_3 (dst, src, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__copy_user);
-
-/* Copy from user to kernel. The return-value is the number of bytes that were
- inaccessible. */
-
-unsigned long __copy_user_in(void *pdst, const void __user *psrc,
- unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
- /* The best reason to align src is that we then know that a read-fault
- was for aligned bytes; there's no 1..3 remaining good bytes to
- pickle. */
- if (((unsigned long) src & 3) != 0)
- {
- if (((unsigned long) src & 1) && n != 0)
- {
- __asm_copy_from_user_1 (dst, src, retn);
- n--;
- if (retn)
- goto exception;
- }
-
- if (((unsigned long) src & 2) && n >= 2)
- {
- __asm_copy_from_user_2 (dst, src, retn);
- n -= 2;
- if (retn)
- goto exception;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= 44*2) /* Break even between movem and
- move16 is at 38.7*2, but modulo 44.
- FIXME: We use move4 now. */
- {
- /* For large copies we use 'movem' */
-
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- "r13=r13, r11=r11, r12=r12" */
- __asm__ volatile ("\n\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
-0: \n\
- movem [$r11+],$r10 \n\
-1: \n\
- subq 44,$r12 \n\
- bge 0b \n\
- movem $r10,[$r13+] \n\
- \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-4: \n\
- .section .fixup,\"ax\" \n\
- \n\
-;; Do not jump back into the loop if we fail. For some uses, we get a \n\
-;; page fault somewhere on the line. Without checking for page limits, \n\
-;; we don't know where, but we need to copy accurately and keep an \n\
-;; accurate count; not just clear the whole line. To do that, we fall \n\
-;; down in the code below, proceeding with smaller amounts. It should \n\
-;; be kept in mind that we have to cater to code like what at one time \n\
-;; was in fs/super.c: \n\
-;; i = size - copy_from_user((void *)page, data, size); \n\
-;; which would cause repeated faults while clearing the remainder of \n\
-;; the SIZE bytes at PAGE after the first fault. \n\
-;; A caveat here is that we must not fall through from a failing page \n\
-;; to a valid page. \n\
- \n\
-3: \n\
- movem [$sp+],$r10 \n\
- addq 44,$r12 ;; Get back count before faulting point. \n\
- subq 44,$r11 ;; Get back pointer to faulting movem-line. \n\
- jump 4b ;; Fall through, pretending the fault didn't happen.\n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 1b,3b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
-
- }
-
- /* Either we directly start copying here, using dword copying in a loop,
- or we copy as much as possible with 'movem' and then the last block
- (<44 bytes) is copied here. This will work since 'movem' will have
- updated src, dst and n. (Except with failing src.)
-
- Since we want to keep src accurate, we can't use
- __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and
- retn, but not src (by design; it's value is ignored elsewhere). */
-
- while (n >= 4)
- {
- __asm_copy_from_user_4 (dst, src, retn);
- n -= 4;
-
- if (retn)
- goto exception;
- }
-
- /* If we get here, there were no memory read faults. */
- switch (n)
- {
- /* These copies are at least "naturally aligned" (so we don't have
- to check each byte), due to the src alignment code before the
- movem loop. The *_3 case *will* get the correct count for retn. */
- case 0:
- /* This case deliberately left in (if you have doubts check the
- generated assembly code). */
- break;
- case 1:
- __asm_copy_from_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_from_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_from_user_3 (dst, src, retn);
- break;
- }
-
- /* If we get here, retn correctly reflects the number of failing
- bytes. */
- return retn;
-
-exception:
- return retn + n;
-}
-EXPORT_SYMBOL(__copy_user_in);
-
-/* Zero userspace. */
-unsigned long __do_clear_user(void __user *pto, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pto;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_clear_1 (dst, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_clear_2 (dst, retn);
- n -= 2;
- }
- }
-
- /* Decide which copying method to use.
- FIXME: This number is from the "ordinary" kernel memset. */
- if (n >= (1*48))
- {
- /* For large clears we use 'movem' */
-
- /* It is not optimal to tell the compiler about clobbering any
- call-saved registers; that will move the saving/restoring of
- those registers to the function prologue/epilogue, and make
- non-movem sizes suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- something like "r13=r13, r11=r11, r12=r12". */
- __asm__ volatile ("\n\
- .ifnc %0%1%2,$r13$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- clear.d $r0 \n\
- clear.d $r1 \n\
- clear.d $r2 \n\
- clear.d $r3 \n\
- clear.d $r4 \n\
- clear.d $r5 \n\
- clear.d $r6 \n\
- clear.d $r7 \n\
- clear.d $r8 \n\
- clear.d $r9 \n\
- clear.d $r10 \n\
- clear.d $r11 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,$r12 \n\
-0: \n\
- subq 12*4,$r12 \n\
- bge 0b \n\
- movem $r11,[$r13+] \n\
-1: \n\
- addq 12*4,$r12 ;; compensate for last loop underflowing n\n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
-3: \n\
- move.d [$sp],$r10 \n\
- addq 12*4,$r10 \n\
- move.d $r10,[$sp] \n\
- clear.d $r10 \n\
- jump 0b \n\
- \n\
-4: \n\
- movem [$sp+],$r10 \n\
- addq 12*4,$r10 \n\
- addq 12*4,$r12 \n\
- jump 2b \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 0b,3b \n\
- .dword 1b,4b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (n), "2" (retn)
- /* Clobber */ : "r11");
- }
-
- while (n >= 16)
- {
- __asm_clear_16 (dst, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_clear_4 (dst, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_clear_1 (dst, retn);
- break;
- case 2:
- __asm_clear_2 (dst, retn);
- break;
- case 3:
- __asm_clear_3 (dst, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__do_clear_user);
diff --git a/arch/cris/arch-v10/mm/Makefile b/arch/cris/arch-v10/mm/Makefile
deleted file mode 100644
index 588b4baee85e..000000000000
--- a/arch/cris/arch-v10/mm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for the linux cris-specific parts of the memory manager.
-#
-
-obj-y := fault.o init.o tlb.o
-
diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c
deleted file mode 100644
index e6c225169642..000000000000
--- a/arch/cris/arch-v10/mm/fault.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/mm/fault.c
- *
- * Low level bus fault handler
- *
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- */
-
-#include <linux/mm.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <arch/svinto.h>
-#include <asm/mmu_context.h>
-
-/* debug of low-level TLB reload */
-#undef DEBUG
-
-#ifdef DEBUG
-#define D(x) x
-#else
-#define D(x)
-#endif
-
-extern const struct exception_table_entry
- *search_exception_tables(unsigned long addr);
-
-asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs,
- int protection, int writeaccess);
-
-/* fast TLB-fill fault handler
- * this is called from entry.S with interrupts disabled
- */
-
-void
-handle_mmu_bus_fault(struct pt_regs *regs)
-{
- int cause;
- int select;
-#ifdef DEBUG
- int index;
- int page_id;
- int acc, inv;
-#endif
- pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
- pmd_t *pmd;
- pte_t pte;
- int miss, we, writeac;
- unsigned long address;
- unsigned long flags;
-
- cause = *R_MMU_CAUSE;
-
- address = cause & PAGE_MASK; /* get faulting address */
- select = *R_TLB_SELECT;
-
-#ifdef DEBUG
- page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause);
- acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause);
- inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
- index = IO_EXTRACT(R_TLB_SELECT, index, select);
-#endif
- miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause);
- we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause);
- writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause);
-
- D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",
- regs->irp, address, miss, inv, we, acc, index, page_id));
-
- /* leave it to the MM system fault handler */
- if (miss)
- do_page_fault(address, regs, 0, writeac);
- else
- do_page_fault(address, regs, 1, we);
-
- /* Reload TLB with new entry to avoid an extra miss exception.
- * do_page_fault may have flushed the TLB so we have to restore
- * the MMU registers.
- */
- local_irq_save(flags);
- pmd = (pmd_t *)(pgd + pgd_index(address));
- if (pmd_none(*pmd))
- goto exit;
- pte = *pte_offset_kernel(pmd, address);
- if (!pte_present(pte))
- goto exit;
- *R_TLB_SELECT = select;
- *R_TLB_HI = cause;
- *R_TLB_LO = pte_val(pte);
-exit:
- local_irq_restore(flags);
-}
diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c
deleted file mode 100644
index 4da99a0e3b57..000000000000
--- a/arch/cris/arch-v10/mm/init.c
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v10/mm/init.c
- *
- */
-#include <linux/mmzone.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/types.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <arch/svinto.h>
-
-extern void tlb_init(void);
-
-/*
- * The kernel is already mapped with a kernel segment at kseg_c so
- * we don't need to map it with a page table. However head.S also
- * temporarily mapped it at kseg_4 so we should set up the ksegs again,
- * clear the TLB and do some other paging setup stuff.
- */
-
-void __init
-paging_init(void)
-{
- int i;
- unsigned long zones_size[MAX_NR_ZONES];
-
- printk("Setting up paging and the MMU.\n");
-
- /* clear out the init_mm.pgd that will contain the kernel's mappings */
-
- for(i = 0; i < PTRS_PER_PGD; i++)
- swapper_pg_dir[i] = __pgd(0);
-
- /* make sure the current pgd table points to something sane
- * (even if it is most probably not used until the next
- * switch_mm)
- */
-
- per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
-
- /* initialise the TLB (tlb.c) */
-
- tlb_init();
-
- /* see README.mm for details on the KSEG setup */
-
-#ifdef CONFIG_CRIS_LOW_MAP
- /* Etrax-100 LX version 1 has a bug so that we cannot map anything
- * across the 0x80000000 boundary, so we need to shrink the user-virtual
- * area to 0x50000000 instead of 0xb0000000 and map things slightly
- * different. The unused areas are marked as paged so that we can catch
- * freak kernel accesses there.
- *
- * The ARTPEC chip is mapped at 0xa so we pass that segment straight
- * through. We cannot vremap it because the vmalloc area is below 0x8
- * and Juliette needs an uncached area above 0x8.
- *
- * Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards.
- * We map them straight over in LOW_MAP, but use vremap in LX version 2.
- */
-
-#define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
-
- *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
- IO_STATE(R_MMU_KSEG, seg_e, page ) |
- IO_STATE(R_MMU_KSEG, seg_d, page ) |
- IO_STATE(R_MMU_KSEG, seg_c, page ) |
- IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
- IO_STATE(R_MMU_KSEG, seg_a, page ) |
- IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
- IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
- IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
- IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */
- IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */
- IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
-
- *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
- IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
-
- *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
-#else
- /* This code is for the corrected Etrax-100 LX version 2... */
-
-#define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
-
- *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */
- IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */
- IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
- IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */
- IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
- IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */
- IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_8, page ) |
- IO_STATE(R_MMU_KSEG, seg_7, page ) |
- IO_STATE(R_MMU_KSEG, seg_6, page ) |
- IO_STATE(R_MMU_KSEG, seg_5, page ) |
- IO_STATE(R_MMU_KSEG, seg_4, page ) |
- IO_STATE(R_MMU_KSEG, seg_3, page ) |
- IO_STATE(R_MMU_KSEG, seg_2, page ) |
- IO_STATE(R_MMU_KSEG, seg_1, page ) |
- IO_STATE(R_MMU_KSEG, seg_0, page ) );
-
- *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
- IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
-
- *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
-#endif
-
- *R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) );
-
- /* The MMU has been enabled ever since head.S but just to make
- * it totally obvious we do it here as well.
- */
-
- *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) |
- IO_STATE(R_MMU_CTRL, acc_excp, enable ) |
- IO_STATE(R_MMU_CTRL, we_excp, enable ) );
-
- *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable);
-
- /*
- * initialize the bad page table and bad page to point
- * to a couple of allocated pages
- */
-
- empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
- memset((void *)empty_zero_page, 0, PAGE_SIZE);
-
- /* All pages are DMA'able in Etrax, so put all in the DMA'able zone */
-
- zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
- for (i = 1; i < MAX_NR_ZONES; i++)
- zones_size[i] = 0;
-
- /* Use free_area_init_node instead of free_area_init, because the former
- * is designed for systems where the DRAM starts at an address substantially
- * higher than 0, like us (we start at PAGE_OFFSET). This saves space in the
- * mem_map page array.
- */
-
- free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
-}
-
-/* Initialize remaps of some I/O-ports. It is important that this
- * is called before any driver is initialized.
- */
-
-static int
-__init init_ioremap(void)
-{
-
- /* Give the external I/O-port addresses their values */
-
-#ifdef CONFIG_CRIS_LOW_MAP
- /* Simply a linear map (see the KSEG map above in paging_init) */
- port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START |
- MEM_NON_CACHEABLE);
- port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START |
- MEM_NON_CACHEABLE);
- port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START |
- MEM_NON_CACHEABLE);
-#else
- /* Note that nothing blows up just because we do this remapping
- * it's ok even if the ports are not used or connected
- * to anything (or connected to a non-I/O thing) */
- port_cse1_addr = (volatile unsigned long *)
- ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16);
- port_csp0_addr = (volatile unsigned long *)
- ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16);
- port_csp4_addr = (volatile unsigned long *)
- ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16);
-#endif
- return 0;
-}
-
-__initcall(init_ioremap);
-
-/* Helper function for the two below */
-
-static inline void
-flush_etrax_cacherange(void *startadr, int length)
-{
- /* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
- * we can use to get fast dummy-reads of cachelines
- */
-
- volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
- CACHED_BOOTROM);
-
- length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */
-
- while(length > 0) {
- *flushadr; /* dummy read to flush */
- flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */
- length -= 32;
- }
-}
-
-/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
- * will occasionally corrupt certain CPU writes if the DMA buffers
- * happen to be hot in the cache.
- *
- * As a workaround, we have to flush the relevant parts of the cache
- * before (re) inserting any receiving descriptor into the DMA HW.
- */
-
-void
-prepare_rx_descriptor(struct etrax_dma_descr *desc)
-{
- flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
-}
-
-/* Do the same thing but flush the entire cache */
-
-void
-flush_etrax_cache(void)
-{
- flush_etrax_cacherange(0, 8192);
-}
diff --git a/arch/cris/arch-v10/mm/tlb.c b/arch/cris/arch-v10/mm/tlb.c
deleted file mode 100644
index 7f1f752f2445..000000000000
--- a/arch/cris/arch-v10/mm/tlb.c
+++ /dev/null
@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v10/mm/tlb.c
- *
- * Low level TLB handling
- *
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/mm_types.h>
-
-#include <asm/tlb.h>
-#include <asm/mmu_context.h>
-#include <arch/svinto.h>
-
-#define D(x)
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The running context is R_MMU_CONTEXT, and each TLB entry contains a
- * page_id that has to match to give a hit. In page_id_map, we keep track
- * of which mm's we have assigned which page_id's, so that we know when
- * to invalidate TLB entries.
- *
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match.
- *
- * Notice that we need to make the flushes atomic, otherwise an interrupt
- * handler that uses vmalloced memory might cause a TLB load in the middle
- * of a flush causing.
- */
-
-/* invalidate all TLB entries */
-
-void
-flush_tlb_all(void)
-{
- int i;
- unsigned long flags;
-
- /* the vpn of i & 0xf is so we dont write similar TLB entries
- * in the same 4-way entry group. details...
- */
-
- local_irq_save(flags);
- for(i = 0; i < NUM_TLB_ENTRIES; i++) {
- *R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) );
- *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
- IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
-
- *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
- IO_STATE(R_TLB_LO, valid, no ) |
- IO_STATE(R_TLB_LO, kernel,no ) |
- IO_STATE(R_TLB_LO, we, no ) |
- IO_FIELD(R_TLB_LO, pfn, 0 ) );
- }
- local_irq_restore(flags);
- D(printk("tlb: flushed all\n"));
-}
-
-/* invalidate the selected mm context only */
-
-void
-flush_tlb_mm(struct mm_struct *mm)
-{
- int i;
- int page_id = mm->context.page_id;
- unsigned long flags;
-
- D(printk("tlb: flush mm context %d (%p)\n", page_id, mm));
-
- if(page_id == NO_CONTEXT)
- return;
-
- /* mark the TLB entries that match the page_id as invalid.
- * here we could also check the _PAGE_GLOBAL bit and NOT flush
- * global pages. is it worth the extra I/O ?
- */
-
- local_irq_save(flags);
- for(i = 0; i < NUM_TLB_ENTRIES; i++) {
- *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
- if (IO_EXTRACT(R_TLB_HI, page_id, *R_TLB_HI) == page_id) {
- *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
- IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
-
- *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
- IO_STATE(R_TLB_LO, valid, no ) |
- IO_STATE(R_TLB_LO, kernel,no ) |
- IO_STATE(R_TLB_LO, we, no ) |
- IO_FIELD(R_TLB_LO, pfn, 0 ) );
- }
- }
- local_irq_restore(flags);
-}
-
-/* invalidate a single page */
-
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
- struct mm_struct *mm = vma->vm_mm;
- int page_id = mm->context.page_id;
- int i;
- unsigned long flags;
-
- D(printk("tlb: flush page %p in context %d (%p)\n", addr, page_id, mm));
-
- if(page_id == NO_CONTEXT)
- return;
-
- addr &= PAGE_MASK; /* perhaps not necessary */
-
- /* invalidate those TLB entries that match both the mm context
- * and the virtual address requested
- */
-
- local_irq_save(flags);
- for(i = 0; i < NUM_TLB_ENTRIES; i++) {
- unsigned long tlb_hi;
- *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
- tlb_hi = *R_TLB_HI;
- if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id &&
- (tlb_hi & PAGE_MASK) == addr) {
- *R_TLB_HI = IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
- addr; /* same addr as before works. */
-
- *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
- IO_STATE(R_TLB_LO, valid, no ) |
- IO_STATE(R_TLB_LO, kernel,no ) |
- IO_STATE(R_TLB_LO, we, no ) |
- IO_FIELD(R_TLB_LO, pfn, 0 ) );
- }
- }
- local_irq_restore(flags);
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-
-int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- mm->context.page_id = NO_CONTEXT;
- return 0;
-}
-
-/* called in schedule() just before actually doing the switch_to */
-
-void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (prev != next) {
- /* make sure we have a context */
- get_mmu_context(next);
-
- /* remember the pgd for the fault handlers
- * this is similar to the pgd register in some other CPU's.
- * we need our own copy of it because current and active_mm
- * might be invalid at points where we still need to derefer
- * the pgd.
- */
-
- per_cpu(current_pgd, smp_processor_id()) = next->pgd;
-
- /* switch context in the MMU */
-
- D(printk(KERN_DEBUG "switching mmu_context to %d (%p)\n",
- next->context, next));
-
- *R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT,
- page_id, next->context.page_id);
- }
-}
-
diff --git a/arch/cris/arch-v10/output_arch.ld b/arch/cris/arch-v10/output_arch.ld
deleted file mode 100644
index 2f3288006991..000000000000
--- a/arch/cris/arch-v10/output_arch.ld
+++ /dev/null
@@ -1,2 +0,0 @@
-/* At the time of this writing, there's no equivalent ld option. */
-OUTPUT_ARCH (cris)
diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig
deleted file mode 100644
index 958dabfca7eb..000000000000
--- a/arch/cris/arch-v32/Kconfig
+++ /dev/null
@@ -1,211 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V32
-
-source arch/cris/arch-v32/mach-fs/Kconfig
-source arch/cris/arch-v32/mach-a3/Kconfig
-
-source drivers/cpufreq/Kconfig
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- depends on ETRAX_ARCH_V32
- default "c0000000"
-
-choice
- prompt "Kernel GDB port"
- depends on ETRAX_KGDB
- default ETRAX_KGDB_PORT0
- help
- Choose a serial port for kernel debugging. NOTE: This port should
- not be enabled under Drivers for built-in interfaces (as it has its
- own initialization code) and should not be the same as the debug port.
-
-config ETRAX_KGDB_PORT4
- bool "Serial-4"
- depends on ETRAX_SERIAL_PORTS = 5
- help
- Use serial port 4 for kernel debugging.
-
-endchoice
-
-config ETRAX_MEM_GRP1_CONFIG
- hex "MEM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "4044a"
- help
- Waitstates for flash. The default value is suitable for the
- standard flashes used in axis products (120 ns).
-
-config ETRAX_MEM_GRP2_CONFIG
- hex "MEM_GRP2_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for SRAM. 0 is a good choice for most Axis products.
-
-config ETRAX_MEM_GRP3_CONFIG
- hex "MEM_GRP3_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP0-3. 0 is a good choice for most Axis products.
- It may need to be changed if external devices such as extra
- register-mapped LEDs are used.
-
-config ETRAX_MEM_GRP4_CONFIG
- hex "MEM_GRP4_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP4-6. 0 is a good choice for most Axis products.
-
-config ETRAX_SDRAM_GRP0_CONFIG
- hex "SDRAM_GRP0_CONFIG"
- depends on ETRAX_ARCH_V32
- default "336"
- help
- SDRAM configuration for group 0. The value depends on the
- hardware configuration. The default value is suitable
- for 32 MB organized as two 16 bits chips (e.g. Axis
- part number 18550) connected as one 32 bit device (i.e. in
- the same group).
-
-config ETRAX_SDRAM_GRP1_CONFIG
- hex "SDRAM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM configuration for group 1. The default value is 0
- because group 1 is not used in the default configuration,
- described in the help for SDRAM_GRP0_CONFIG.
-
-config ETRAX_SDRAM_TIMING
- hex "SDRAM_TIMING"
- depends on ETRAX_ARCH_V32
- default "104a"
- help
- SDRAM timing parameters. The default value is ok for
- most hardwares but large SDRAMs may require a faster
- refresh (a.k.a 8K refresh). The default value implies
- 100MHz clock and SDR mode.
-
-config ETRAX_SDRAM_COMMAND
- hex "SDRAM_COMMAND"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM command. Should be 0 unless you really know what
- you are doing (may be != 0 for unusual address line
- mappings such as in a MCM)..
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- depends on ETRAX_ARCH_V32
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- depends on ETRAX_ARCH_V32
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PD_OE
- hex "GIO_PD_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port D bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PD_OUT
- hex "GIO_PD_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port D bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PE_OE
- hex "GIO_PE_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port E bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PE_OUT
- hex "GIO_PE_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port E bits. Most
- products should use 00000 here.
-
-endif
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
deleted file mode 100644
index 4d2d744bced2..000000000000
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ /dev/null
@@ -1,263 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V32
-
-config ETRAX_ETHERNET
- bool "Ethernet support"
- depends on ETRAX_ARCH_V32 && NETDEVICES
- select MII
- help
- This option enables the ETRAX FS built-in 10/100Mbit Ethernet
- controller.
-
-config ETRAX_NO_PHY
- bool "PHY not present"
- depends on ETRAX_ETHERNET
- help
- This option disables all MDIO communication with an ethernet
- transceiver connected to the MII interface. This option shall
- typically be enabled if the MII interface is connected to a
- switch. This option should normally be disabled. If enabled,
- speed and duplex will be locked to 100 Mbit and full duplex.
-
-config ETRAXFS_SERIAL
- bool "Serial-port support"
- depends on ETRAX_ARCH_V32
- select SERIAL_CORE
- select SERIAL_CORE_CONSOLE
- help
- Enables the ETRAX FS serial driver for ser0 (ttyS0)
- You probably want this enabled.
-
-config ETRAX_RS485
- bool "RS-485 support"
- depends on ETRAXFS_SERIAL
- help
- Enables support for RS-485 serial communication.
-
-config ETRAX_RS485_DISABLE_RECEIVER
- bool "Disable serial receiver"
- depends on ETRAX_RS485
- help
- It is necessary to disable the serial receiver to avoid serial
- loopback. Not all products are able to do this in software only.
-
-config ETRAX_SERIAL_PORT0
- bool "Serial port 0 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser0 (ttyS0)
- Normally you want this on. You can control what DMA channels to use
- if you do not need DMA to something else.
- ser0 can use dma4 or dma6 for output and dma5 or dma7 for input.
-
-config ETRAX_SERIAL_PORT1
- bool "Serial port 1 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser1 (ttyS1).
-
-config ETRAX_SERIAL_PORT2
- bool "Serial port 2 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser2 (ttyS2).
-
-config ETRAX_SERIAL_PORT3
- bool "Serial port 3 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser3 (ttyS3).
-
-config ETRAX_SYNCHRONOUS_SERIAL
- bool "Synchronous serial-port support"
- depends on ETRAX_ARCH_V32
- help
- Enables the ETRAX FS synchronous serial driver.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT0
- bool "Synchronous serial port 0 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL
- help
- Enabled synchronous serial port 0.
-
-config ETRAX_SYNCHRONOUS_SERIAL0_DMA
- bool "Enable DMA on synchronous serial port 0."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT1
- bool "Synchronous serial port 1 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL && ETRAXFS
- help
- Enabled synchronous serial port 1.
-
-config ETRAX_SYNCHRONOUS_SERIAL1_DMA
- bool "Enable DMA on synchronous serial port 1."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-config ETRAX_AXISFLASHMAP
- bool "Axis flash-map support"
- depends on ETRAX_ARCH_V32
- select MTD
- select MTD_CFI
- select MTD_CFI_AMDSTD
- select MTD_JEDECPROBE
- select MTD_BLOCK
- select MTD_COMPLEX_MAPPINGS
- select MTD_MTDRAM
- help
- This option enables MTD mapping of flash devices. Needed to use
- flash memories. If unsure, say Y.
-
-config ETRAX_AXISFLASHMAP_MTD0WHOLE
- bool "MTD0 is whole boot flash device"
- depends on ETRAX_AXISFLASHMAP
- help
- When this option is not set, mtd0 refers to the first partition
- on the boot flash device. When set, mtd0 refers to the whole
- device, with mtd1 referring to the first partition etc.
-
-config ETRAX_PTABLE_SECTOR
- int "Byte-offset of partition table sector"
- depends on ETRAX_AXISFLASHMAP
- default "65536"
- help
- Byte-offset of the partition table in the first flash chip.
- The default value is 64kB and should not be changed unless
- you know exactly what you are doing. The only valid reason
- for changing this is when the flash block size is bigger
- than 64kB (e.g. when using two parallel 16 bit flashes).
-
-config ETRAX_NANDFLASH
- bool "NAND flash support"
- depends on ETRAX_ARCH_V32
- select MTD_NAND
- help
- This option enables MTD mapping of NAND flash devices. Needed to use
- NAND flash memories. If unsure, say Y.
-
-config ETRAX_NANDBOOT
- bool "Boot from NAND flash"
- depends on ETRAX_NANDFLASH
- help
- This options enables booting from NAND flash devices.
- Say Y if your boot code, kernel and root file system is in
- NAND flash. Say N if they are in NOR flash.
-
-config ETRAX_CARDBUS
- bool "Cardbus support"
- depends on ETRAX_ARCH_V32
- help
- Enabled the ETRAX Cardbus driver.
-
-config PCI
- bool
- depends on ETRAX_CARDBUS
- default y
- select HAVE_GENERIC_DMA_COHERENT
-
-config ETRAX_IOP_FW_LOAD
- tristate "IO-processor hotplug firmware loading support"
- depends on ETRAX_ARCH_V32
- select FW_LOADER
- help
- Enables IO-processor hotplug firmware loading support.
-
-config ETRAX_STREAMCOPROC
- tristate "Stream co-processor driver enabled"
- depends on ETRAX_ARCH_V32
- help
- This option enables a driver for the stream co-processor
- for cryptographic operations.
-
-config ETRAX_MMC_IOP
- tristate "MMC/SD host driver using IO-processor"
- depends on ETRAX_ARCH_V32 && MMC
- help
- This option enables the SD/MMC host controller interface.
- The host controller is implemented using the built in
- IO-Processor. Only the SPU is used in this implementation.
-
-config ETRAX_SPI_MMC
-# Make this one of several "choices" (possible simultaneously but
-# suggested uniquely) when an IOP driver emerges for "real" MMC/SD
-# protocol support.
- tristate
- depends on !ETRAX_MMC_IOP
- default MMC
- select SPI
- select MMC_SPI
-
-# While the board info is MMC_SPI only, the drivers are written to be
-# independent of MMC_SPI, so we'll keep SPI non-dependent on the
-# MMC_SPI config choices (well, except for a single depends-on-line
-# for the board-info file until a separate non-MMC SPI board file
-# emerges).
-# FIXME: When that happens, we'll need to be able to ask for and
-# configure non-MMC SPI ports together with MMC_SPI ports (if multiple
-# SPI ports are enabled).
-
-config SPI_ETRAX_SSER
- tristate
- depends on SPI_MASTER && ETRAX_ARCH_V32
- select SPI_BITBANG
- help
- This enables using an synchronous serial (sser) port as a
- SPI master controller on Axis ETRAX FS and later. The
- driver can be configured to use any sser port.
-
-config SPI_ETRAX_GPIO
- tristate
- depends on SPI_MASTER && ETRAX_ARCH_V32
- select SPI_BITBANG
- help
- This enables using GPIO pins port as a SPI master controller
- on Axis ETRAX FS and later. The driver can be configured to
- use any GPIO pins.
-
-config ETRAX_SPI_SSER0
- tristate "SPI using synchronous serial port 0 (sser0)"
- depends on ETRAX_SPI_MMC
- default m if MMC_SPI=m
- default y if MMC_SPI=y
- default y if MMC_SPI=n
- select SPI_ETRAX_SSER
- help
- Say Y for an MMC/SD socket connected to synchronous serial port 0,
- or for devices using the SPI protocol on that port. Say m if you
- want to build it as a module, which will be named spi_crisv32_sser.
- (You need to select MMC separately.)
-
-config ETRAX_SPI_SSER1
- tristate "SPI using synchronous serial port 1 (sser1)"
- depends on ETRAX_SPI_MMC
- default m if MMC_SPI=m && ETRAX_SPI_SSER0=n
- default y if MMC_SPI=y && ETRAX_SPI_SSER0=n
- default y if MMC_SPI=n && ETRAX_SPI_SSER0=n
- select SPI_ETRAX_SSER
- help
- Say Y for an MMC/SD socket connected to synchronous serial port 1,
- or for devices using the SPI protocol on that port. Say m if you
- want to build it as a module, which will be named spi_crisv32_sser.
- (You need to select MMC separately.)
-
-config ETRAX_SPI_GPIO
- tristate "Bitbanged SPI using gpio pins"
- depends on ETRAX_SPI_MMC
- select SPI_ETRAX_GPIO
- default m if MMC_SPI=m && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
- default y if MMC_SPI=y && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
- default y if MMC_SPI=n && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
- help
- Say Y for an MMC/SD socket connected to general I/O pins (but not
- a complete synchronous serial ports), or for devices using the SPI
- protocol on general I/O pins. Slow and slows down the system.
- Say m to build it as a module, which will be called spi_crisv32_gpio.
- (You need to select MMC separately.)
-
-endif
diff --git a/arch/cris/arch-v32/drivers/Makefile b/arch/cris/arch-v32/drivers/Makefile
deleted file mode 100644
index 57c9568707b0..000000000000
--- a/arch/cris/arch-v32/drivers/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_STREAMCOPROC) += cryptocop.o
-obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
-obj-$(CONFIG_ETRAXFS) += mach-fs/
-obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/
-obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o
-obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
-obj-$(CONFIG_PCI) += pci/
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
deleted file mode 100644
index 87656c41fec7..000000000000
--- a/arch/cris/arch-v32/drivers/axisflashmap.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * Physical mapping layer for MTD using the Axis partitiontable format
- *
- * Copyright (c) 2001-2007 Axis Communications AB
- *
- * This file is under the GPL.
- *
- * First partition is always sector 0 regardless of if we find a partitiontable
- * or not. In the start of the next sector, there can be a partitiontable that
- * tells us what other partitions to define. If there isn't, we use a default
- * partition split defined below.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-
-#include <linux/mtd/concat.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/mtdram.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/axisflashmap.h>
-#include <asm/mmu.h>
-
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-
-#define FLASH_UNCACHED_ADDR KSEG_E
-#define FLASH_CACHED_ADDR KSEG_F
-
-#define PAGESIZE (512)
-
-#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
-#define flash_data __u8
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
-#define flash_data __u16
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
-#define flash_data __u32
-#endif
-
-/* From head.S */
-extern unsigned long romfs_in_flash; /* 1 when romfs_start, _length in flash */
-extern unsigned long romfs_start, romfs_length;
-extern unsigned long nand_boot; /* 1 when booted from nand flash */
-
-struct partition_name {
- char name[6];
-};
-
-/* The master mtd for the entire flash. */
-struct mtd_info* axisflash_mtd = NULL;
-
-/* Map driver functions. */
-
-static map_word flash_read(struct map_info *map, unsigned long ofs)
-{
- map_word tmp;
- tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs);
- return tmp;
-}
-
-static void flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- memcpy(to, (void *)(map->map_priv_1 + from), len);
-}
-
-static void flash_write(struct map_info *map, map_word d, unsigned long adr)
-{
- *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0];
-}
-
-/*
- * The map for chip select e0.
- *
- * We run into tricky coherence situations if we mix cached with uncached
- * accesses to we only use the uncached version here.
- *
- * The size field is the total size where the flash chips may be mapped on the
- * chip select. MTD probes should find all devices there and it does not matter
- * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD
- * probes will ignore them.
- *
- * The start address in map_priv_1 is in virtual memory so we cannot use
- * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start
- * address of cse0.
- */
-static struct map_info map_cse0 = {
- .name = "cse0",
- .size = MEM_CSE0_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR
-};
-
-/*
- * The map for chip select e1.
- *
- * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong
- * address, but there isn't.
- */
-static struct map_info map_cse1 = {
- .name = "cse1",
- .size = MEM_CSE1_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
-};
-
-#define MAX_PARTITIONS 7
-#ifdef CONFIG_ETRAX_NANDBOOT
-#define NUM_DEFAULT_PARTITIONS 4
-#define DEFAULT_ROOTFS_PARTITION_NO 2
-#define DEFAULT_MEDIA_SIZE 0x2000000 /* 32 megs */
-#else
-#define NUM_DEFAULT_PARTITIONS 3
-#define DEFAULT_ROOTFS_PARTITION_NO (-1)
-#define DEFAULT_MEDIA_SIZE 0x800000 /* 8 megs */
-#endif
-
-#if (MAX_PARTITIONS < NUM_DEFAULT_PARTITIONS)
-#error MAX_PARTITIONS must be >= than NUM_DEFAULT_PARTITIONS
-#endif
-
-/* Initialize the ones normally used. */
-static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
- {
- .name = "part0",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "part1",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part2",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part3",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part4",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part5",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part6",
- .size = 0,
- .offset = 0
- },
-};
-
-
-/* If no partition-table was found, we use this default-set.
- * Default flash size is 8MB (NOR). CONFIG_ETRAX_PTABLE_SECTOR is most
- * likely the size of one flash block and "filesystem"-partition needs
- * to be >=5 blocks to be able to use JFFS.
- */
-static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
- {
- .name = "boot firmware",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "kernel",
- .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = CONFIG_ETRAX_PTABLE_SECTOR
- },
-#define FILESYSTEM_SECTOR (11 * CONFIG_ETRAX_PTABLE_SECTOR)
-#ifdef CONFIG_ETRAX_NANDBOOT
- {
- .name = "rootfs",
- .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = FILESYSTEM_SECTOR
- },
-#undef FILESYSTEM_SECTOR
-#define FILESYSTEM_SECTOR (21 * CONFIG_ETRAX_PTABLE_SECTOR)
-#endif
- {
- .name = "rwfs",
- .size = DEFAULT_MEDIA_SIZE - FILESYSTEM_SECTOR,
- .offset = FILESYSTEM_SECTOR
- }
-};
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
-/* Main flash device */
-static struct mtd_partition main_partition = {
- .name = "main",
- .size = 0,
- .offset = 0
-};
-#endif
-
-/* Auxiliary partition if we find another flash */
-static struct mtd_partition aux_partition = {
- .name = "aux",
- .size = 0,
- .offset = 0
-};
-
-/*
- * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
- * chips in that order (because the amd_flash-driver is faster).
- */
-static struct mtd_info *probe_cs(struct map_info *map_cs)
-{
- struct mtd_info *mtd_cs = NULL;
-
- printk(KERN_INFO
- "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n",
- map_cs->name, map_cs->size, map_cs->map_priv_1);
-
-#ifdef CONFIG_MTD_CFI
- mtd_cs = do_map_probe("cfi_probe", map_cs);
-#endif
-#ifdef CONFIG_MTD_JEDECPROBE
- if (!mtd_cs)
- mtd_cs = do_map_probe("jedec_probe", map_cs);
-#endif
-
- return mtd_cs;
-}
-
-/*
- * Probe each chip select individually for flash chips. If there are chips on
- * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
- * so that MTD partitions can cross chip boundaries.
- *
- * The only known restriction to how you can mount your chips is that each
- * chip select must hold similar flash chips. But you need external hardware
- * to do that anyway and you can put totally different chips on cse0 and cse1
- * so it isn't really much of a restriction.
- */
-extern struct mtd_info* __init crisv32_nand_flash_probe (void);
-static struct mtd_info *flash_probe(void)
-{
- struct mtd_info *mtd_cse0;
- struct mtd_info *mtd_cse1;
- struct mtd_info *mtd_total;
- struct mtd_info *mtds[2];
- int count = 0;
-
- if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL)
- mtds[count++] = mtd_cse0;
- if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL)
- mtds[count++] = mtd_cse1;
-
- if (!mtd_cse0 && !mtd_cse1) {
- /* No chip found. */
- return NULL;
- }
-
- if (count > 1) {
- /* Since the concatenation layer adds a small overhead we
- * could try to figure out if the chips in cse0 and cse1 are
- * identical and reprobe the whole cse0+cse1 window. But since
- * flash chips are slow, the overhead is relatively small.
- * So we use the MTD concatenation layer instead of further
- * complicating the probing procedure.
- */
- mtd_total = mtd_concat_create(mtds, count, "cse0+cse1");
- if (!mtd_total) {
- printk(KERN_ERR "%s and %s: Concatenation failed!\n",
- map_cse0.name, map_cse1.name);
-
- /* The best we can do now is to only use what we found
- * at cse0. */
- mtd_total = mtd_cse0;
- map_destroy(mtd_cse1);
- }
- } else
- mtd_total = mtd_cse0 ? mtd_cse0 : mtd_cse1;
-
- return mtd_total;
-}
-
-/*
- * Probe the flash chip(s) and, if it succeeds, read the partition-table
- * and register the partitions with MTD.
- */
-static int __init init_axis_flash(void)
-{
- struct mtd_info *main_mtd;
- struct mtd_info *aux_mtd = NULL;
- int err = 0;
- int pidx = 0;
- struct partitiontable_head *ptable_head = NULL;
- struct partitiontable_entry *ptable;
- int ptable_ok = 0;
- static char page[PAGESIZE];
- size_t len;
- int ram_rootfs_partition = -1; /* -1 => no RAM rootfs partition */
- int part;
- struct mtd_partition *partition;
-
- /* We need a root fs. If it resides in RAM, we need to use an
- * MTDRAM device, so it must be enabled in the kernel config,
- * but its size must be configured as 0 so as not to conflict
- * with our usage.
- */
-#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0)
- if (!romfs_in_flash && !nand_boot) {
- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
- "device; configure CONFIG_MTD_MTDRAM with size = 0!\n");
- panic("This kernel cannot boot from RAM!\n");
- }
-#endif
-
- main_mtd = flash_probe();
- if (main_mtd)
- printk(KERN_INFO "%s: 0x%08llx bytes of NOR flash memory.\n",
- main_mtd->name, main_mtd->size);
-
-#ifdef CONFIG_ETRAX_NANDFLASH
- aux_mtd = crisv32_nand_flash_probe();
- if (aux_mtd)
- printk(KERN_INFO "%s: 0x%08x bytes of NAND flash memory.\n",
- aux_mtd->name, aux_mtd->size);
-
-#ifdef CONFIG_ETRAX_NANDBOOT
- {
- struct mtd_info *tmp_mtd;
-
- printk(KERN_INFO "axisflashmap: Set to boot from NAND flash, "
- "making NAND flash primary device.\n");
- tmp_mtd = main_mtd;
- main_mtd = aux_mtd;
- aux_mtd = tmp_mtd;
- }
-#endif /* CONFIG_ETRAX_NANDBOOT */
-#endif /* CONFIG_ETRAX_NANDFLASH */
-
- if (!main_mtd && !aux_mtd) {
- /* There's no reason to use this module if no flash chip can
- * be identified. Make sure that's understood.
- */
- printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
- }
-
-#if 0 /* Dump flash memory so we can see what is going on */
- if (main_mtd) {
- int sectoraddr;
- for (sectoraddr = 0; sectoraddr < 2*65536+4096;
- sectoraddr += PAGESIZE) {
- main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len,
- page);
- printk(KERN_INFO
- "Sector at %d (length %d):\n",
- sectoraddr, len);
- print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, page, PAGESIZE, false);
- }
- }
-#endif
-
- if (main_mtd) {
- loff_t ptable_sector = CONFIG_ETRAX_PTABLE_SECTOR;
- main_mtd->owner = THIS_MODULE;
- axisflash_mtd = main_mtd;
-
-
- /* First partition (rescue) is always set to the default. */
- pidx++;
-#ifdef CONFIG_ETRAX_NANDBOOT
- /* We know where the partition table should be located,
- * it will be in first good block after that.
- */
- int blockstat;
- do {
- blockstat = mtd_block_isbad(main_mtd, ptable_sector);
- if (blockstat < 0)
- ptable_sector = 0; /* read error */
- else if (blockstat)
- ptable_sector += main_mtd->erasesize;
- } while (blockstat && ptable_sector);
-#endif
- if (ptable_sector) {
- mtd_read(main_mtd, ptable_sector, PAGESIZE, &len,
- page);
- ptable_head = &((struct partitiontable *) page)->head;
- }
-
-#if 0 /* Dump partition table so we can see what is going on */
- printk(KERN_INFO
- "axisflashmap: flash read %d bytes at 0x%08x, data: %8ph\n",
- len, CONFIG_ETRAX_PTABLE_SECTOR, page);
- printk(KERN_INFO
- "axisflashmap: partition table offset %d, data: %8ph\n",
- PARTITION_TABLE_OFFSET, page + PARTITION_TABLE_OFFSET);
-#endif
- }
-
- if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
- && (ptable_head->size <
- (MAX_PARTITIONS * sizeof(struct partitiontable_entry) +
- PARTITIONTABLE_END_MARKER_SIZE))
- && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) +
- ptable_head->size -
- PARTITIONTABLE_END_MARKER_SIZE)
- == PARTITIONTABLE_END_MARKER)) {
- /* Looks like a start, sane length and end of a
- * partition table, lets check csum etc.
- */
- struct partitiontable_entry *max_addr =
- (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head) +
- ptable_head->size);
- unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
- unsigned char *p;
- unsigned long csum = 0;
-
- ptable = (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head));
-
- /* Lets be PARANOID, and check the checksum. */
- p = (unsigned char*) ptable;
-
- while (p <= (unsigned char*)max_addr) {
- csum += *p++;
- csum += *p++;
- csum += *p++;
- csum += *p++;
- }
- ptable_ok = (csum == ptable_head->checksum);
-
- /* Read the entries and use/show the info. */
- printk(KERN_INFO "axisflashmap: "
- "Found a%s partition table at 0x%p-0x%p.\n",
- (ptable_ok ? " valid" : "n invalid"), ptable_head,
- max_addr);
-
- /* We have found a working bootblock. Now read the
- * partition table. Scan the table. It ends with 0xffffffff.
- */
- while (ptable_ok
- && ptable->offset != PARTITIONTABLE_END_MARKER
- && ptable < max_addr
- && pidx < MAX_PARTITIONS - 1) {
-
- axis_partitions[pidx].offset = offset + ptable->offset;
-#ifdef CONFIG_ETRAX_NANDFLASH
- if (main_mtd->type == MTD_NANDFLASH) {
- axis_partitions[pidx].size =
- (((ptable+1)->offset ==
- PARTITIONTABLE_END_MARKER) ?
- main_mtd->size :
- ((ptable+1)->offset + offset)) -
- (ptable->offset + offset);
-
- } else
-#endif /* CONFIG_ETRAX_NANDFLASH */
- axis_partitions[pidx].size = ptable->size;
-#ifdef CONFIG_ETRAX_NANDBOOT
- /* Save partition number of jffs2 ro partition.
- * Needed if RAM booting or root file system in RAM.
- */
- if (!nand_boot &&
- ram_rootfs_partition < 0 && /* not already set */
- ptable->type == PARTITION_TYPE_JFFS2 &&
- (ptable->flags & PARTITION_FLAGS_READONLY_MASK) ==
- PARTITION_FLAGS_READONLY)
- ram_rootfs_partition = pidx;
-#endif /* CONFIG_ETRAX_NANDBOOT */
- pidx++;
- ptable++;
- }
- }
-
- /* Decide whether to use default partition table. */
- /* Only use default table if we actually have a device (main_mtd) */
-
- partition = &axis_partitions[0];
- if (main_mtd && !ptable_ok) {
- memcpy(axis_partitions, axis_default_partitions,
- sizeof(axis_default_partitions));
- pidx = NUM_DEFAULT_PARTITIONS;
- ram_rootfs_partition = DEFAULT_ROOTFS_PARTITION_NO;
- }
-
- /* Add artificial partitions for rootfs if necessary */
- if (romfs_in_flash) {
- /* rootfs is in directly accessible flash memory = NOR flash.
- Add an overlapping device for the rootfs partition. */
- printk(KERN_INFO "axisflashmap: Adding partition for "
- "overlapping root file system image\n");
- axis_partitions[pidx].size = romfs_length;
- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
- axis_partitions[pidx].name = "romfs";
- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
- ram_rootfs_partition = -1;
- pidx++;
- } else if (romfs_length && !nand_boot) {
- /* romfs exists in memory, but not in flash, so must be in RAM.
- * Configure an MTDRAM partition. */
- if (ram_rootfs_partition < 0) {
- /* None set yet, put it at the end */
- ram_rootfs_partition = pidx;
- pidx++;
- }
- printk(KERN_INFO "axisflashmap: Adding partition for "
- "root file system image in RAM\n");
- axis_partitions[ram_rootfs_partition].size = romfs_length;
- axis_partitions[ram_rootfs_partition].offset = romfs_start;
- axis_partitions[ram_rootfs_partition].name = "romfs";
- axis_partitions[ram_rootfs_partition].mask_flags |=
- MTD_WRITEABLE;
- }
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
- if (main_mtd) {
- main_partition.size = main_mtd->size;
- err = mtd_device_register(main_mtd, &main_partition, 1);
- if (err)
- panic("axisflashmap: Could not initialize "
- "partition for whole main mtd device!\n");
- }
-#endif
-
- /* Now, register all partitions with mtd.
- * We do this one at a time so we can slip in an MTDRAM device
- * in the proper place if required. */
-
- for (part = 0; part < pidx; part++) {
- if (part == ram_rootfs_partition) {
- /* add MTDRAM partition here */
- struct mtd_info *mtd_ram;
-
- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
- if (!mtd_ram)
- panic("axisflashmap: Couldn't allocate memory "
- "for mtd_info!\n");
- printk(KERN_INFO "axisflashmap: Adding RAM partition "
- "for rootfs image.\n");
- err = mtdram_init_device(mtd_ram,
- (void *)(u_int32_t)partition[part].offset,
- partition[part].size,
- partition[part].name);
- if (err)
- panic("axisflashmap: Could not initialize "
- "MTD RAM device!\n");
- /* JFFS2 likes to have an erasesize. Keep potential
- * JFFS2 rootfs happy by providing one. Since image
- * was most likely created for main mtd, use that
- * erasesize, if available. Otherwise, make a guess. */
- mtd_ram->erasesize = (main_mtd ? main_mtd->erasesize :
- CONFIG_ETRAX_PTABLE_SECTOR);
- } else {
- err = mtd_device_register(main_mtd, &partition[part],
- 1);
- if (err)
- panic("axisflashmap: Could not add mtd "
- "partition %d\n", part);
- }
- }
-
- if (aux_mtd) {
- aux_partition.size = aux_mtd->size;
- err = mtd_device_register(aux_mtd, &aux_partition, 1);
- if (err)
- panic("axisflashmap: Could not initialize "
- "aux mtd device!\n");
-
- }
-
- return err;
-}
-
-/* This adds the above to the kernels init-call chain. */
-module_init(init_axis_flash);
-
-EXPORT_SYMBOL(axisflash_mtd);
diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c
deleted file mode 100644
index a3c353472a8c..000000000000
--- a/arch/cris/arch-v32/drivers/cryptocop.c
+++ /dev/null
@@ -1,3522 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Stream co-processor driver for the ETRAX FS
- *
- * Copyright (C) 2003-2007 Axis Communications AB
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/spinlock.h>
-#include <linux/stddef.h>
-
-#include <linux/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-
-#include <linux/list.h>
-#include <linux/interrupt.h>
-
-#include <asm/signal.h>
-#include <asm/irq.h>
-
-#include <dma.h>
-#include <hwregs/dma.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect_defs.h>
-
-#include <hwregs/strcop.h>
-#include <hwregs/strcop_defs.h>
-#include <cryptocop.h>
-
-#ifdef CONFIG_ETRAXFS
-#define IN_DMA 9
-#define OUT_DMA 8
-#define IN_DMA_INST regi_dma9
-#define OUT_DMA_INST regi_dma8
-#define DMA_IRQ DMA9_INTR_VECT
-#else
-#define IN_DMA 3
-#define OUT_DMA 2
-#define IN_DMA_INST regi_dma3
-#define OUT_DMA_INST regi_dma2
-#define DMA_IRQ DMA3_INTR_VECT
-#endif
-
-#define DESCR_ALLOC_PAD (31)
-
-struct cryptocop_dma_desc {
- char *free_buf; /* If non-null will be kfreed in free_cdesc() */
- dma_descr_data *dma_descr;
-
- unsigned char dma_descr_buf[sizeof(dma_descr_data) + DESCR_ALLOC_PAD];
-
- unsigned int from_pool:1; /* If 1 'allocated' from the descriptor pool. */
- struct cryptocop_dma_desc *next;
-};
-
-
-struct cryptocop_int_operation{
- void *alloc_ptr;
- cryptocop_session_id sid;
-
- dma_descr_context ctx_out;
- dma_descr_context ctx_in;
-
- /* DMA descriptors allocated by driver. */
- struct cryptocop_dma_desc *cdesc_out;
- struct cryptocop_dma_desc *cdesc_in;
-
- /* Strcop config to use. */
- cryptocop_3des_mode tdes_mode;
- cryptocop_csum_type csum_mode;
-
- /* DMA descrs provided by consumer. */
- dma_descr_data *ddesc_out;
- dma_descr_data *ddesc_in;
-};
-
-
-struct cryptocop_tfrm_ctx {
- cryptocop_tfrm_id tid;
- unsigned int blocklength;
-
- unsigned int start_ix;
-
- struct cryptocop_tfrm_cfg *tcfg;
- struct cryptocop_transform_ctx *tctx;
-
- unsigned char previous_src;
- unsigned char current_src;
-
- /* Values to use in metadata out. */
- unsigned char hash_conf;
- unsigned char hash_mode;
- unsigned char ciph_conf;
- unsigned char cbcmode;
- unsigned char decrypt;
-
- unsigned int requires_padding:1;
- unsigned int strict_block_length:1;
- unsigned int active:1;
- unsigned int done:1;
- size_t consumed;
- size_t produced;
-
- /* Pad (input) descriptors to put in the DMA out list when the transform
- * output is put on the DMA in list. */
- struct cryptocop_dma_desc *pad_descs;
-
- struct cryptocop_tfrm_ctx *prev_src;
- struct cryptocop_tfrm_ctx *curr_src;
-
- /* Mapping to HW. */
- unsigned char unit_no;
-};
-
-
-struct cryptocop_private{
- cryptocop_session_id sid;
- struct cryptocop_private *next;
-};
-
-/* Session list. */
-
-struct cryptocop_transform_ctx{
- struct cryptocop_transform_init init;
- unsigned char dec_key[CRYPTOCOP_MAX_KEY_LENGTH];
- unsigned int dec_key_set:1;
-
- struct cryptocop_transform_ctx *next;
-};
-
-
-struct cryptocop_session{
- cryptocop_session_id sid;
-
- struct cryptocop_transform_ctx *tfrm_ctx;
-
- struct cryptocop_session *next;
-};
-
-/* Priority levels for jobs sent to the cryptocop. Checksum operations from
- kernel have highest priority since TCPIP stack processing must not
- be a bottleneck. */
-typedef enum {
- cryptocop_prio_kernel_csum = 0,
- cryptocop_prio_kernel = 1,
- cryptocop_prio_user = 2,
- cryptocop_prio_no_prios = 3
-} cryptocop_queue_priority;
-
-struct cryptocop_prio_queue{
- struct list_head jobs;
- cryptocop_queue_priority prio;
-};
-
-struct cryptocop_prio_job{
- struct list_head node;
- cryptocop_queue_priority prio;
-
- struct cryptocop_operation *oper;
- struct cryptocop_int_operation *iop;
-};
-
-struct ioctl_job_cb_ctx {
- unsigned int processed:1;
-};
-
-
-static struct cryptocop_session *cryptocop_sessions = NULL;
-spinlock_t cryptocop_sessions_lock;
-
-/* Next Session ID to assign. */
-static cryptocop_session_id next_sid = 1;
-
-/* Pad for checksum. */
-static const char csum_zero_pad[1] = {0x00};
-
-/* Trash buffer for mem2mem operations. */
-#define MEM2MEM_DISCARD_BUF_LENGTH (512)
-static unsigned char mem2mem_discard_buf[MEM2MEM_DISCARD_BUF_LENGTH];
-
-/* Descriptor pool. */
-/* FIXME Tweak this value. */
-#define CRYPTOCOP_DESCRIPTOR_POOL_SIZE (100)
-static struct cryptocop_dma_desc descr_pool[CRYPTOCOP_DESCRIPTOR_POOL_SIZE];
-static struct cryptocop_dma_desc *descr_pool_free_list;
-static int descr_pool_no_free;
-static spinlock_t descr_pool_lock;
-
-/* Lock to stop cryptocop to start processing of a new operation. The holder
- of this lock MUST call cryptocop_start_job() after it is unlocked. */
-spinlock_t cryptocop_process_lock;
-
-static struct cryptocop_prio_queue cryptocop_job_queues[cryptocop_prio_no_prios];
-static spinlock_t cryptocop_job_queue_lock;
-static struct cryptocop_prio_job *cryptocop_running_job = NULL;
-static spinlock_t running_job_lock;
-
-/* The interrupt handler appends completed jobs to this list. The scehduled
- * tasklet removes them upon sending the response to the crypto consumer. */
-static struct list_head cryptocop_completed_jobs;
-static spinlock_t cryptocop_completed_jobs_lock;
-
-DECLARE_WAIT_QUEUE_HEAD(cryptocop_ioc_process_wq);
-
-
-/** Local functions. **/
-
-static int cryptocop_open(struct inode *, struct file *);
-
-static int cryptocop_release(struct inode *, struct file *);
-
-static long cryptocop_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg);
-
-static void cryptocop_start_job(void);
-
-static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation);
-static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation);
-
-static int cryptocop_job_queue_init(void);
-static void cryptocop_job_queue_close(void);
-
-static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length);
-
-static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length);
-
-static int transform_ok(struct cryptocop_transform_init *tinit);
-
-static struct cryptocop_session *get_session(cryptocop_session_id sid);
-
-static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid);
-
-static void delete_internal_operation(struct cryptocop_int_operation *iop);
-
-static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength);
-
-static int init_stream_coprocessor(void);
-
-static void __exit exit_stream_coprocessor(void);
-
-/*#define LDEBUG*/
-#ifdef LDEBUG
-#define DEBUG(s) s
-#define DEBUG_API(s) s
-static void print_cryptocop_operation(struct cryptocop_operation *cop);
-static void print_dma_descriptors(struct cryptocop_int_operation *iop);
-static void print_strcop_crypto_op(struct strcop_crypto_op *cop);
-static void print_lock_status(void);
-static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op);
-#define assert(s) do{if (!(s)) panic(#s);} while(0);
-#else
-#define DEBUG(s)
-#define DEBUG_API(s)
-#define assert(s)
-#endif
-
-
-/* Transform constants. */
-#define DES_BLOCK_LENGTH (8)
-#define AES_BLOCK_LENGTH (16)
-#define MD5_BLOCK_LENGTH (64)
-#define SHA1_BLOCK_LENGTH (64)
-#define CSUM_BLOCK_LENGTH (2)
-#define MD5_STATE_LENGTH (16)
-#define SHA1_STATE_LENGTH (20)
-
-/* The device number. */
-#define CRYPTOCOP_MAJOR (254)
-#define CRYPTOCOP_MINOR (0)
-
-
-
-const struct file_operations cryptocop_fops = {
- .owner = THIS_MODULE,
- .open = cryptocop_open,
- .release = cryptocop_release,
- .unlocked_ioctl = cryptocop_ioctl,
- .llseek = noop_llseek,
-};
-
-
-static void free_cdesc(struct cryptocop_dma_desc *cdesc)
-{
- DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool));
- kfree(cdesc->free_buf);
-
- if (cdesc->from_pool) {
- unsigned long int flags;
- spin_lock_irqsave(&descr_pool_lock, flags);
- cdesc->next = descr_pool_free_list;
- descr_pool_free_list = cdesc;
- ++descr_pool_no_free;
- spin_unlock_irqrestore(&descr_pool_lock, flags);
- } else {
- kfree(cdesc);
- }
-}
-
-
-static struct cryptocop_dma_desc *alloc_cdesc(int alloc_flag)
-{
- int use_pool = (alloc_flag & GFP_ATOMIC) ? 1 : 0;
- struct cryptocop_dma_desc *cdesc;
-
- if (use_pool) {
- unsigned long int flags;
- spin_lock_irqsave(&descr_pool_lock, flags);
- if (!descr_pool_free_list) {
- spin_unlock_irqrestore(&descr_pool_lock, flags);
- DEBUG_API(printk("alloc_cdesc: pool is empty\n"));
- return NULL;
- }
- cdesc = descr_pool_free_list;
- descr_pool_free_list = descr_pool_free_list->next;
- --descr_pool_no_free;
- spin_unlock_irqrestore(&descr_pool_lock, flags);
- cdesc->from_pool = 1;
- } else {
- cdesc = kmalloc(sizeof(struct cryptocop_dma_desc), alloc_flag);
- if (!cdesc) {
- DEBUG_API(printk("alloc_cdesc: kmalloc\n"));
- return NULL;
- }
- cdesc->from_pool = 0;
- }
- cdesc->dma_descr = (dma_descr_data*)(((unsigned long int)cdesc + offsetof(struct cryptocop_dma_desc, dma_descr_buf) + DESCR_ALLOC_PAD) & ~0x0000001F);
-
- cdesc->next = NULL;
-
- cdesc->free_buf = NULL;
- cdesc->dma_descr->out_eop = 0;
- cdesc->dma_descr->in_eop = 0;
- cdesc->dma_descr->intr = 0;
- cdesc->dma_descr->eol = 0;
- cdesc->dma_descr->wait = 0;
- cdesc->dma_descr->buf = NULL;
- cdesc->dma_descr->after = NULL;
-
- DEBUG_API(printk("alloc_cdesc: return 0x%p, cdesc->dma_descr=0x%p, from_pool=%d\n", cdesc, cdesc->dma_descr, cdesc->from_pool));
- return cdesc;
-}
-
-
-static void setup_descr_chain(struct cryptocop_dma_desc *cd)
-{
- DEBUG(printk("setup_descr_chain: entering\n"));
- while (cd) {
- if (cd->next) {
- cd->dma_descr->next = (dma_descr_data*)virt_to_phys(cd->next->dma_descr);
- } else {
- cd->dma_descr->next = NULL;
- }
- cd = cd->next;
- }
- DEBUG(printk("setup_descr_chain: exit\n"));
-}
-
-
-/* Create a pad descriptor for the transform.
- * Return -1 for error, 0 if pad created. */
-static int create_pad_descriptor(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **pad_desc, int alloc_flag)
-{
- struct cryptocop_dma_desc *cdesc = NULL;
- int error = 0;
- struct strcop_meta_out mo = {
- .ciphsel = src_none,
- .hashsel = src_none,
- .csumsel = src_none
- };
- char *pad;
- size_t plen;
-
- DEBUG(printk("create_pad_descriptor: start.\n"));
- /* Setup pad descriptor. */
-
- DEBUG(printk("create_pad_descriptor: setting up padding.\n"));
- cdesc = alloc_cdesc(alloc_flag);
- if (!cdesc){
- DEBUG_API(printk("create_pad_descriptor: alloc pad desc\n"));
- goto error_cleanup;
- }
- switch (tc->unit_no) {
- case src_md5:
- error = create_md5_pad(alloc_flag, tc->consumed, &pad, &plen);
- if (error){
- DEBUG_API(printk("create_pad_descriptor: create_md5_pad_failed\n"));
- goto error_cleanup;
- }
- cdesc->free_buf = pad;
- mo.hashsel = src_dma;
- mo.hashconf = tc->hash_conf;
- mo.hashmode = tc->hash_mode;
- break;
- case src_sha1:
- error = create_sha1_pad(alloc_flag, tc->consumed, &pad, &plen);
- if (error){
- DEBUG_API(printk("create_pad_descriptor: create_sha1_pad_failed\n"));
- goto error_cleanup;
- }
- cdesc->free_buf = pad;
- mo.hashsel = src_dma;
- mo.hashconf = tc->hash_conf;
- mo.hashmode = tc->hash_mode;
- break;
- case src_csum:
- if (tc->consumed % tc->blocklength){
- pad = (char*)csum_zero_pad;
- plen = 1;
- } else {
- pad = (char*)cdesc; /* Use any pointer. */
- plen = 0;
- }
- mo.csumsel = src_dma;
- break;
- }
- cdesc->dma_descr->wait = 1;
- cdesc->dma_descr->out_eop = 1; /* Since this is a pad output is pushed. EOP is ok here since the padded unit is the only one active. */
- cdesc->dma_descr->buf = (char*)virt_to_phys((char*)pad);
- cdesc->dma_descr->after = cdesc->dma_descr->buf + plen;
-
- cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
- *pad_desc = cdesc;
-
- return 0;
-
- error_cleanup:
- if (cdesc) free_cdesc(cdesc);
- return -1;
-}
-
-
-static int setup_key_dl_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **kd, int alloc_flag)
-{
- struct cryptocop_dma_desc *key_desc = alloc_cdesc(alloc_flag);
- struct strcop_meta_out mo = {0};
-
- DEBUG(printk("setup_key_dl_desc\n"));
-
- if (!key_desc) {
- DEBUG_API(printk("setup_key_dl_desc: failed descriptor allocation.\n"));
- return -ENOMEM;
- }
-
- /* Download key. */
- if ((tc->tctx->init.alg == cryptocop_alg_aes) && (tc->tcfg->flags & CRYPTOCOP_DECRYPT)) {
- /* Precook the AES decrypt key. */
- if (!tc->tctx->dec_key_set){
- get_aes_decrypt_key(tc->tctx->dec_key, tc->tctx->init.key, tc->tctx->init.keylen);
- tc->tctx->dec_key_set = 1;
- }
- key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->dec_key);
- key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8;
- } else {
- key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->init.key);
- key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8;
- }
- /* Setup metadata. */
- mo.dlkey = 1;
- switch (tc->tctx->init.keylen) {
- case 64:
- mo.decrypt = 0;
- mo.hashmode = 0;
- break;
- case 128:
- mo.decrypt = 0;
- mo.hashmode = 1;
- break;
- case 192:
- mo.decrypt = 1;
- mo.hashmode = 0;
- break;
- case 256:
- mo.decrypt = 1;
- mo.hashmode = 1;
- break;
- default:
- break;
- }
- mo.ciphsel = mo.hashsel = mo.csumsel = src_none;
- key_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
-
- key_desc->dma_descr->out_eop = 1;
- key_desc->dma_descr->wait = 1;
- key_desc->dma_descr->intr = 0;
-
- *kd = key_desc;
- return 0;
-}
-
-static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag)
-{
- struct cryptocop_dma_desc *iv_desc = alloc_cdesc(alloc_flag);
- struct strcop_meta_out mo = {0};
-
- DEBUG(printk("setup_cipher_iv_desc\n"));
-
- if (!iv_desc) {
- DEBUG_API(printk("setup_cipher_iv_desc: failed CBC IV descriptor allocation.\n"));
- return -ENOMEM;
- }
- /* Download IV. */
- iv_desc->dma_descr->buf = (char*)virt_to_phys(tc->tcfg->iv);
- iv_desc->dma_descr->after = iv_desc->dma_descr->buf + tc->blocklength;
-
- /* Setup metadata. */
- mo.hashsel = mo.csumsel = src_none;
- mo.ciphsel = src_dma;
- mo.ciphconf = tc->ciph_conf;
- mo.cbcmode = tc->cbcmode;
-
- iv_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
-
- iv_desc->dma_descr->out_eop = 0;
- iv_desc->dma_descr->wait = 1;
- iv_desc->dma_descr->intr = 0;
-
- *id = iv_desc;
- return 0;
-}
-
-/* Map the output length of the transform to operation output starting on the inject index. */
-static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag)
-{
- int err = 0;
- struct cryptocop_dma_desc head = {0};
- struct cryptocop_dma_desc *outdesc = &head;
- size_t iov_offset = 0;
- size_t out_ix = 0;
- int outiov_ix = 0;
- struct strcop_meta_in mi = {0};
-
- size_t out_length = tc->produced;
- int rem_length;
- int dlength;
-
- assert(out_length != 0);
- if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operation->tfrm_op.outlen == 0))) {
- DEBUG_API(printk("create_input_descriptors: operation outdata too small\n"));
- return -EINVAL;
- }
- /* Traverse the out iovec until the result inject index is reached. */
- while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_ix].iov_len) <= tc->tcfg->inject_ix)){
- out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len;
- outiov_ix++;
- }
- if (outiov_ix >= operation->tfrm_op.outcount){
- DEBUG_API(printk("create_input_descriptors: operation outdata too small\n"));
- return -EINVAL;
- }
- iov_offset = tc->tcfg->inject_ix - out_ix;
- mi.dmasel = tc->unit_no;
-
- /* Setup the output descriptors. */
- while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) {
- outdesc->next = alloc_cdesc(alloc_flag);
- if (!outdesc->next) {
- DEBUG_API(printk("create_input_descriptors: alloc_cdesc\n"));
- err = -ENOMEM;
- goto error_cleanup;
- }
- outdesc = outdesc->next;
- rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset;
- dlength = (out_length < rem_length) ? out_length : rem_length;
-
- DEBUG(printk("create_input_descriptors:\n"
- "outiov_ix=%d, rem_length=%d, dlength=%d\n"
- "iov_offset=%d, outdata[outiov_ix].iov_len=%d\n"
- "outcount=%d, outiov_ix=%d\n",
- outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operation->tfrm_op.outcount, outiov_ix));
-
- outdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.outdata[outiov_ix].iov_base + iov_offset);
- outdesc->dma_descr->after = outdesc->dma_descr->buf + dlength;
- outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
-
- out_length -= dlength;
- iov_offset += dlength;
- if (iov_offset >= operation->tfrm_op.outdata[outiov_ix].iov_len) {
- iov_offset = 0;
- ++outiov_ix;
- }
- }
- if (out_length > 0){
- DEBUG_API(printk("create_input_descriptors: not enough room for output, %d remained\n", out_length));
- err = -EINVAL;
- goto error_cleanup;
- }
- /* Set sync in last descriptor. */
- mi.sync = 1;
- outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
-
- *id = head.next;
- return 0;
-
- error_cleanup:
- while (head.next) {
- outdesc = head.next->next;
- free_cdesc(head.next);
- head.next = outdesc;
- }
- return err;
-}
-
-
-static int create_output_descriptors(struct cryptocop_operation *operation, int *iniov_ix, int *iniov_offset, size_t desc_len, struct cryptocop_dma_desc **current_out_cdesc, struct strcop_meta_out *meta_out, int alloc_flag)
-{
- while (desc_len != 0) {
- struct cryptocop_dma_desc *cdesc;
- int rem_length = operation->tfrm_op.indata[*iniov_ix].iov_len - *iniov_offset;
- int dlength = (desc_len < rem_length) ? desc_len : rem_length;
-
- cdesc = alloc_cdesc(alloc_flag);
- if (!cdesc) {
- DEBUG_API(printk("create_output_descriptors: alloc_cdesc\n"));
- return -ENOMEM;
- }
- (*current_out_cdesc)->next = cdesc;
- (*current_out_cdesc) = cdesc;
-
- cdesc->free_buf = NULL;
-
- cdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.indata[*iniov_ix].iov_base + *iniov_offset);
- cdesc->dma_descr->after = cdesc->dma_descr->buf + dlength;
-
- assert(desc_len >= dlength);
- desc_len -= dlength;
- *iniov_offset += dlength;
- if (*iniov_offset >= operation->tfrm_op.indata[*iniov_ix].iov_len) {
- *iniov_offset = 0;
- ++(*iniov_ix);
- if (*iniov_ix > operation->tfrm_op.incount) {
- DEBUG_API(printk("create_output_descriptors: not enough indata in operation."));
- return -EINVAL;
- }
- }
- cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, (*meta_out));
- } /* while (desc_len != 0) */
- /* Last DMA descriptor gets a 'wait' bit to signal expected change in metadata. */
- (*current_out_cdesc)->dma_descr->wait = 1; /* This will set extraneous WAIT in some situations, e.g. when padding hashes and checksums. */
-
- return 0;
-}
-
-
-static int append_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_dma_desc **current_in_cdesc, struct cryptocop_dma_desc **current_out_cdesc, struct cryptocop_tfrm_ctx *tc, int alloc_flag)
-{
- DEBUG(printk("append_input_descriptors, tc=0x%p, unit_no=%d\n", tc, tc->unit_no));
- if (tc->tcfg) {
- int failed = 0;
- struct cryptocop_dma_desc *idescs = NULL;
- DEBUG(printk("append_input_descriptors: pushing output, consumed %d produced %d bytes.\n", tc->consumed, tc->produced));
- if (tc->pad_descs) {
- DEBUG(printk("append_input_descriptors: append pad descriptors to DMA out list.\n"));
- while (tc->pad_descs) {
- DEBUG(printk("append descriptor 0x%p\n", tc->pad_descs));
- (*current_out_cdesc)->next = tc->pad_descs;
- tc->pad_descs = tc->pad_descs->next;
- (*current_out_cdesc) = (*current_out_cdesc)->next;
- }
- }
-
- /* Setup and append output descriptors to DMA in list. */
- if (tc->unit_no == src_dma){
- /* mem2mem. Setup DMA in descriptors to discard all input prior to the requested mem2mem data. */
- struct strcop_meta_in mi = {.sync = 0, .dmasel = src_dma};
- unsigned int start_ix = tc->start_ix;
- while (start_ix){
- unsigned int desclen = start_ix < MEM2MEM_DISCARD_BUF_LENGTH ? start_ix : MEM2MEM_DISCARD_BUF_LENGTH;
- (*current_in_cdesc)->next = alloc_cdesc(alloc_flag);
- if (!(*current_in_cdesc)->next){
- DEBUG_API(printk("append_input_descriptors: alloc_cdesc mem2mem discard failed\n"));
- return -ENOMEM;
- }
- (*current_in_cdesc) = (*current_in_cdesc)->next;
- (*current_in_cdesc)->dma_descr->buf = (char*)virt_to_phys(mem2mem_discard_buf);
- (*current_in_cdesc)->dma_descr->after = (*current_in_cdesc)->dma_descr->buf + desclen;
- (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
- start_ix -= desclen;
- }
- mi.sync = 1;
- (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
- }
-
- failed = create_input_descriptors(operation, tc, &idescs, alloc_flag);
- if (failed){
- DEBUG_API(printk("append_input_descriptors: output descriptor setup failed\n"));
- return failed;
- }
- DEBUG(printk("append_input_descriptors: append output descriptors to DMA in list.\n"));
- while (idescs) {
- DEBUG(printk("append descriptor 0x%p\n", idescs));
- (*current_in_cdesc)->next = idescs;
- idescs = idescs->next;
- (*current_in_cdesc) = (*current_in_cdesc)->next;
- }
- }
- return 0;
-}
-
-
-
-static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struct cryptocop_int_operation **int_op, int alloc_flag)
-{
- struct cryptocop_session *sess;
- struct cryptocop_transform_ctx *tctx;
-
- struct cryptocop_tfrm_ctx digest_ctx = {
- .previous_src = src_none,
- .current_src = src_none,
- .start_ix = 0,
- .requires_padding = 1,
- .strict_block_length = 0,
- .hash_conf = 0,
- .hash_mode = 0,
- .ciph_conf = 0,
- .cbcmode = 0,
- .decrypt = 0,
- .consumed = 0,
- .produced = 0,
- .pad_descs = NULL,
- .active = 0,
- .done = 0,
- .prev_src = NULL,
- .curr_src = NULL,
- .tcfg = NULL};
- struct cryptocop_tfrm_ctx cipher_ctx = {
- .previous_src = src_none,
- .current_src = src_none,
- .start_ix = 0,
- .requires_padding = 0,
- .strict_block_length = 1,
- .hash_conf = 0,
- .hash_mode = 0,
- .ciph_conf = 0,
- .cbcmode = 0,
- .decrypt = 0,
- .consumed = 0,
- .produced = 0,
- .pad_descs = NULL,
- .active = 0,
- .done = 0,
- .prev_src = NULL,
- .curr_src = NULL,
- .tcfg = NULL};
- struct cryptocop_tfrm_ctx csum_ctx = {
- .previous_src = src_none,
- .current_src = src_none,
- .start_ix = 0,
- .blocklength = 2,
- .requires_padding = 1,
- .strict_block_length = 0,
- .hash_conf = 0,
- .hash_mode = 0,
- .ciph_conf = 0,
- .cbcmode = 0,
- .decrypt = 0,
- .consumed = 0,
- .produced = 0,
- .pad_descs = NULL,
- .active = 0,
- .done = 0,
- .tcfg = NULL,
- .prev_src = NULL,
- .curr_src = NULL,
- .unit_no = src_csum};
- struct cryptocop_tfrm_cfg *tcfg = operation->tfrm_op.tfrm_cfg;
-
- unsigned int indata_ix = 0;
-
- /* iovec accounting. */
- int iniov_ix = 0;
- int iniov_offset = 0;
-
- /* Operation descriptor cfg traversal pointer. */
- struct cryptocop_desc *odsc;
-
- int failed = 0;
- /* List heads for allocated descriptors. */
- struct cryptocop_dma_desc out_cdesc_head = {0};
- struct cryptocop_dma_desc in_cdesc_head = {0};
-
- struct cryptocop_dma_desc *current_out_cdesc = &out_cdesc_head;
- struct cryptocop_dma_desc *current_in_cdesc = &in_cdesc_head;
-
- struct cryptocop_tfrm_ctx *output_tc = NULL;
- void *iop_alloc_ptr;
-
- assert(operation != NULL);
- assert(int_op != NULL);
-
- DEBUG(printk("cryptocop_setup_dma_list: start\n"));
- DEBUG(print_cryptocop_operation(operation));
-
- sess = get_session(operation->sid);
- if (!sess) {
- DEBUG_API(printk("cryptocop_setup_dma_list: no session found for operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag);
- if (!iop_alloc_ptr) {
- DEBUG_API(printk("cryptocop_setup_dma_list: kmalloc cryptocop_int_operation\n"));
- failed = -ENOMEM;
- goto error_cleanup;
- }
- (*int_op) = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out));
- DEBUG(memset((*int_op), 0xff, sizeof(struct cryptocop_int_operation)));
- (*int_op)->alloc_ptr = iop_alloc_ptr;
- DEBUG(printk("cryptocop_setup_dma_list: *int_op=0x%p, alloc_ptr=0x%p\n", *int_op, (*int_op)->alloc_ptr));
-
- (*int_op)->sid = operation->sid;
- (*int_op)->cdesc_out = NULL;
- (*int_op)->cdesc_in = NULL;
- (*int_op)->tdes_mode = cryptocop_3des_ede;
- (*int_op)->csum_mode = cryptocop_csum_le;
- (*int_op)->ddesc_out = NULL;
- (*int_op)->ddesc_in = NULL;
-
- /* Scan operation->tfrm_op.tfrm_cfg for bad configuration and set up the local contexts. */
- if (!tcfg) {
- DEBUG_API(printk("cryptocop_setup_dma_list: no configured transforms in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- while (tcfg) {
- tctx = get_transform_ctx(sess, tcfg->tid);
- if (!tctx) {
- DEBUG_API(printk("cryptocop_setup_dma_list: no transform id %d in session.\n", tcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (tcfg->inject_ix > operation->tfrm_op.outlen){
- DEBUG_API(printk("cryptocop_setup_dma_list: transform id %d inject_ix (%d) > operation->tfrm_op.outlen(%d)", tcfg->tid, tcfg->inject_ix, operation->tfrm_op.outlen));
- failed = -EINVAL;
- goto error_cleanup;
- }
- switch (tctx->init.alg){
- case cryptocop_alg_mem2mem:
- if (cipher_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- /* mem2mem is handled as a NULL cipher. */
- cipher_ctx.cbcmode = 0;
- cipher_ctx.decrypt = 0;
- cipher_ctx.blocklength = 1;
- cipher_ctx.ciph_conf = 0;
- cipher_ctx.unit_no = src_dma;
- cipher_ctx.tcfg = tcfg;
- cipher_ctx.tctx = tctx;
- break;
- case cryptocop_alg_des:
- case cryptocop_alg_3des:
- case cryptocop_alg_aes:
- /* cipher */
- if (cipher_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- cipher_ctx.tcfg = tcfg;
- cipher_ctx.tctx = tctx;
- if (cipher_ctx.tcfg->flags & CRYPTOCOP_DECRYPT){
- cipher_ctx.decrypt = 1;
- }
- switch (tctx->init.cipher_mode) {
- case cryptocop_cipher_mode_ecb:
- cipher_ctx.cbcmode = 0;
- break;
- case cryptocop_cipher_mode_cbc:
- cipher_ctx.cbcmode = 1;
- break;
- default:
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher_ctx, bad cipher mode==%d\n", tctx->init.cipher_mode));
- failed = -EINVAL;
- goto error_cleanup;
- }
- DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx, set CBC mode==%d\n", cipher_ctx.cbcmode));
- switch (tctx->init.alg){
- case cryptocop_alg_des:
- cipher_ctx.ciph_conf = 0;
- cipher_ctx.unit_no = src_des;
- cipher_ctx.blocklength = DES_BLOCK_LENGTH;
- break;
- case cryptocop_alg_3des:
- cipher_ctx.ciph_conf = 1;
- cipher_ctx.unit_no = src_des;
- cipher_ctx.blocklength = DES_BLOCK_LENGTH;
- break;
- case cryptocop_alg_aes:
- cipher_ctx.ciph_conf = 2;
- cipher_ctx.unit_no = src_aes;
- cipher_ctx.blocklength = AES_BLOCK_LENGTH;
- break;
- default:
- panic("cryptocop_setup_dma_list: impossible algorithm %d\n", tctx->init.alg);
- }
- (*int_op)->tdes_mode = tctx->init.tdes_mode;
- break;
- case cryptocop_alg_md5:
- case cryptocop_alg_sha1:
- /* digest */
- if (digest_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple digests in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- digest_ctx.tcfg = tcfg;
- digest_ctx.tctx = tctx;
- digest_ctx.hash_mode = 0; /* Don't use explicit IV in this API. */
- switch (tctx->init.alg){
- case cryptocop_alg_md5:
- digest_ctx.blocklength = MD5_BLOCK_LENGTH;
- digest_ctx.unit_no = src_md5;
- digest_ctx.hash_conf = 1; /* 1 => MD-5 */
- break;
- case cryptocop_alg_sha1:
- digest_ctx.blocklength = SHA1_BLOCK_LENGTH;
- digest_ctx.unit_no = src_sha1;
- digest_ctx.hash_conf = 0; /* 0 => SHA-1 */
- break;
- default:
- panic("cryptocop_setup_dma_list: impossible digest algorithm\n");
- }
- break;
- case cryptocop_alg_csum:
- /* digest */
- if (csum_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple checksums in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- (*int_op)->csum_mode = tctx->init.csum_mode;
- csum_ctx.tcfg = tcfg;
- csum_ctx.tctx = tctx;
- break;
- default:
- /* no algorithm. */
- DEBUG_API(printk("cryptocop_setup_dma_list: invalid algorithm %d specified in tfrm %d.\n", tctx->init.alg, tcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- tcfg = tcfg->next;
- }
- /* Download key if a cipher is used. */
- if (cipher_ctx.tcfg && (cipher_ctx.tctx->init.alg != cryptocop_alg_mem2mem)){
- struct cryptocop_dma_desc *key_desc = NULL;
-
- failed = setup_key_dl_desc(&cipher_ctx, &key_desc, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: setup key dl\n"));
- goto error_cleanup;
- }
- current_out_cdesc->next = key_desc;
- current_out_cdesc = key_desc;
- indata_ix += (unsigned int)(key_desc->dma_descr->after - key_desc->dma_descr->buf);
-
- /* Download explicit IV if a cipher is used and CBC mode and explicit IV selected. */
- if ((cipher_ctx.tctx->init.cipher_mode == cryptocop_cipher_mode_cbc) && (cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV)) {
- struct cryptocop_dma_desc *iv_desc = NULL;
-
- DEBUG(printk("cryptocop_setup_dma_list: setup cipher CBC IV descriptor.\n"));
-
- failed = setup_cipher_iv_desc(&cipher_ctx, &iv_desc, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: CBC IV descriptor.\n"));
- goto error_cleanup;
- }
- current_out_cdesc->next = iv_desc;
- current_out_cdesc = iv_desc;
- indata_ix += (unsigned int)(iv_desc->dma_descr->after - iv_desc->dma_descr->buf);
- }
- }
-
- /* Process descriptors. */
- odsc = operation->tfrm_op.desc;
- while (odsc) {
- struct cryptocop_desc_cfg *dcfg = odsc->cfg;
- struct strcop_meta_out meta_out = {0};
- size_t desc_len = odsc->length;
- int active_count, eop_needed_count;
-
- output_tc = NULL;
-
- DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor\n"));
-
- while (dcfg) {
- struct cryptocop_tfrm_ctx *tc = NULL;
-
- DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor configuration.\n"));
- /* Get the local context for the transform and mark it as the output unit if it produces output. */
- if (digest_ctx.tcfg && (digest_ctx.tcfg->tid == dcfg->tid)){
- tc = &digest_ctx;
- } else if (cipher_ctx.tcfg && (cipher_ctx.tcfg->tid == dcfg->tid)){
- tc = &cipher_ctx;
- } else if (csum_ctx.tcfg && (csum_ctx.tcfg->tid == dcfg->tid)){
- tc = &csum_ctx;
- }
- if (!tc) {
- DEBUG_API(printk("cryptocop_setup_dma_list: invalid transform %d specified in descriptor.\n", dcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (tc->done) {
- DEBUG_API(printk("cryptocop_setup_dma_list: completed transform %d reused.\n", dcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (!tc->active) {
- tc->start_ix = indata_ix;
- tc->active = 1;
- }
-
- tc->previous_src = tc->current_src;
- tc->prev_src = tc->curr_src;
- /* Map source unit id to DMA source config. */
- switch (dcfg->src){
- case cryptocop_source_dma:
- tc->current_src = src_dma;
- break;
- case cryptocop_source_des:
- tc->current_src = src_des;
- break;
- case cryptocop_source_3des:
- tc->current_src = src_des;
- break;
- case cryptocop_source_aes:
- tc->current_src = src_aes;
- break;
- case cryptocop_source_md5:
- case cryptocop_source_sha1:
- case cryptocop_source_csum:
- case cryptocop_source_none:
- default:
- /* We do not allow using accumulating style units (SHA-1, MD5, checksum) as sources to other units.
- */
- DEBUG_API(printk("cryptocop_setup_dma_list: bad unit source configured %d.\n", dcfg->src));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (tc->current_src != src_dma) {
- /* Find the unit we are sourcing from. */
- if (digest_ctx.unit_no == tc->current_src){
- tc->curr_src = &digest_ctx;
- } else if (cipher_ctx.unit_no == tc->current_src){
- tc->curr_src = &cipher_ctx;
- } else if (csum_ctx.unit_no == tc->current_src){
- tc->curr_src = &csum_ctx;
- }
- if ((tc->curr_src == tc) && (tc->unit_no != src_dma)){
- DEBUG_API(printk("cryptocop_setup_dma_list: unit %d configured to source from itself.\n", tc->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
- } else {
- tc->curr_src = NULL;
- }
-
- /* Detect source switch. */
- DEBUG(printk("cryptocop_setup_dma_list: tc->active=%d tc->unit_no=%d tc->current_src=%d tc->previous_src=%d, tc->curr_src=0x%p, tc->prev_srv=0x%p\n", tc->active, tc->unit_no, tc->current_src, tc->previous_src, tc->curr_src, tc->prev_src));
- if (tc->active && (tc->current_src != tc->previous_src)) {
- /* Only allow source switch when both the old source unit and the new one have
- * no pending data to process (i.e. the consumed length must be a multiple of the
- * transform blocklength). */
- /* Note: if the src == NULL we are actually sourcing from DMA out. */
- if (((tc->prev_src != NULL) && (tc->prev_src->consumed % tc->prev_src->blocklength)) ||
- ((tc->curr_src != NULL) && (tc->curr_src->consumed % tc->curr_src->blocklength)))
- {
- DEBUG_API(printk("cryptocop_setup_dma_list: can only disconnect from or connect to a unit on a multiple of the blocklength, old: cons=%d, prod=%d, block=%d, new: cons=%d prod=%d, block=%d.\n", tc->prev_src ? tc->prev_src->consumed : INT_MIN, tc->prev_src ? tc->prev_src->produced : INT_MIN, tc->prev_src ? tc->prev_src->blocklength : INT_MIN, tc->curr_src ? tc->curr_src->consumed : INT_MIN, tc->curr_src ? tc->curr_src->produced : INT_MIN, tc->curr_src ? tc->curr_src->blocklength : INT_MIN));
- failed = -EINVAL;
- goto error_cleanup;
- }
- }
- /* Detect unit deactivation. */
- if (dcfg->last) {
- /* Length check of this is handled below. */
- tc->done = 1;
- }
- dcfg = dcfg->next;
- } /* while (dcfg) */
- DEBUG(printk("cryptocop_setup_dma_list: parsing operation descriptor configuration complete.\n"));
-
- if (cipher_ctx.active && (cipher_ctx.curr_src != NULL) && !cipher_ctx.curr_src->active){
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", cipher_ctx.curr_src->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (digest_ctx.active && (digest_ctx.curr_src != NULL) && !digest_ctx.curr_src->active){
- DEBUG_API(printk("cryptocop_setup_dma_list: digest source from inactive unit %d\n", digest_ctx.curr_src->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (csum_ctx.active && (csum_ctx.curr_src != NULL) && !csum_ctx.curr_src->active){
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", csum_ctx.curr_src->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
-
- /* Update consumed and produced lengths.
-
- The consumed length accounting here is actually cheating. If a unit source from DMA (or any
- other unit that process data in blocks of one octet) it is correct, but if it source from a
- block processing unit, i.e. a cipher, it will be temporarily incorrect at some times. However
- since it is only allowed--by the HW--to change source to or from a block processing unit at times where that
- unit has processed an exact multiple of its block length the end result will be correct.
- Beware that if the source change restriction change this code will need to be (much) reworked.
- */
- DEBUG(printk("cryptocop_setup_dma_list: desc->length=%d, desc_len=%d.\n", odsc->length, desc_len));
-
- if (csum_ctx.active) {
- csum_ctx.consumed += desc_len;
- if (csum_ctx.done) {
- csum_ctx.produced = 2;
- }
- DEBUG(printk("cryptocop_setup_dma_list: csum_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", csum_ctx.consumed, csum_ctx.produced, csum_ctx.blocklength));
- }
- if (digest_ctx.active) {
- digest_ctx.consumed += desc_len;
- if (digest_ctx.done) {
- if (digest_ctx.unit_no == src_md5) {
- digest_ctx.produced = MD5_STATE_LENGTH;
- } else {
- digest_ctx.produced = SHA1_STATE_LENGTH;
- }
- }
- DEBUG(printk("cryptocop_setup_dma_list: digest_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", digest_ctx.consumed, digest_ctx.produced, digest_ctx.blocklength));
- }
- if (cipher_ctx.active) {
- /* Ciphers are allowed only to source from DMA out. That is filtered above. */
- assert(cipher_ctx.current_src == src_dma);
- cipher_ctx.consumed += desc_len;
- cipher_ctx.produced = cipher_ctx.blocklength * (cipher_ctx.consumed / cipher_ctx.blocklength);
- if (cipher_ctx.cbcmode && !(cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV) && cipher_ctx.produced){
- cipher_ctx.produced -= cipher_ctx.blocklength; /* Compensate for CBC iv. */
- }
- DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", cipher_ctx.consumed, cipher_ctx.produced, cipher_ctx.blocklength));
- }
-
- /* Setup the DMA out descriptors. */
- /* Configure the metadata. */
- active_count = 0;
- eop_needed_count = 0;
- if (cipher_ctx.active) {
- ++active_count;
- if (cipher_ctx.unit_no == src_dma){
- /* mem2mem */
- meta_out.ciphsel = src_none;
- } else {
- meta_out.ciphsel = cipher_ctx.current_src;
- }
- meta_out.ciphconf = cipher_ctx.ciph_conf;
- meta_out.cbcmode = cipher_ctx.cbcmode;
- meta_out.decrypt = cipher_ctx.decrypt;
- DEBUG(printk("set ciphsel=%d ciphconf=%d cbcmode=%d decrypt=%d\n", meta_out.ciphsel, meta_out.ciphconf, meta_out.cbcmode, meta_out.decrypt));
- if (cipher_ctx.done) ++eop_needed_count;
- } else {
- meta_out.ciphsel = src_none;
- }
-
- if (digest_ctx.active) {
- ++active_count;
- meta_out.hashsel = digest_ctx.current_src;
- meta_out.hashconf = digest_ctx.hash_conf;
- meta_out.hashmode = 0; /* Explicit mode is not used here. */
- DEBUG(printk("set hashsel=%d hashconf=%d hashmode=%d\n", meta_out.hashsel, meta_out.hashconf, meta_out.hashmode));
- if (digest_ctx.done) {
- assert(digest_ctx.pad_descs == NULL);
- failed = create_pad_descriptor(&digest_ctx, &digest_ctx.pad_descs, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: failed digest pad creation.\n"));
- goto error_cleanup;
- }
- }
- } else {
- meta_out.hashsel = src_none;
- }
-
- if (csum_ctx.active) {
- ++active_count;
- meta_out.csumsel = csum_ctx.current_src;
- if (csum_ctx.done) {
- assert(csum_ctx.pad_descs == NULL);
- failed = create_pad_descriptor(&csum_ctx, &csum_ctx.pad_descs, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: failed csum pad creation.\n"));
- goto error_cleanup;
- }
- }
- } else {
- meta_out.csumsel = src_none;
- }
- DEBUG(printk("cryptocop_setup_dma_list: %d eop needed, %d active units\n", eop_needed_count, active_count));
- /* Setup DMA out descriptors for the indata. */
- failed = create_output_descriptors(operation, &iniov_ix, &iniov_offset, desc_len, &current_out_cdesc, &meta_out, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: create_output_descriptors %d\n", failed));
- goto error_cleanup;
- }
- /* Setup out EOP. If there are active units that are not done here they cannot get an EOP
- * so we ust setup a zero length descriptor to DMA to signal EOP only to done units.
- * If there is a pad descriptor EOP for the padded unit will be EOPed by it.
- */
- assert(active_count >= eop_needed_count);
- assert((eop_needed_count == 0) || (eop_needed_count == 1));
- if (eop_needed_count) {
- /* This means that the bulk operation (cipher/m2m) is terminated. */
- if (active_count > 1) {
- /* Use zero length EOP descriptor. */
- struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag);
- struct strcop_meta_out ed_mo = {0};
- if (!ed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: alloc EOP descriptor for cipher\n"));
- failed = -ENOMEM;
- goto error_cleanup;
- }
-
- assert(cipher_ctx.active && cipher_ctx.done);
-
- if (cipher_ctx.unit_no == src_dma){
- /* mem2mem */
- ed_mo.ciphsel = src_none;
- } else {
- ed_mo.ciphsel = cipher_ctx.current_src;
- }
- ed_mo.ciphconf = cipher_ctx.ciph_conf;
- ed_mo.cbcmode = cipher_ctx.cbcmode;
- ed_mo.decrypt = cipher_ctx.decrypt;
-
- ed->free_buf = NULL;
- ed->dma_descr->wait = 1;
- ed->dma_descr->out_eop = 1;
-
- ed->dma_descr->buf = (char*)virt_to_phys(&ed); /* Use any valid physical address for zero length descriptor. */
- ed->dma_descr->after = ed->dma_descr->buf;
- ed->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, ed_mo);
- current_out_cdesc->next = ed;
- current_out_cdesc = ed;
- } else {
- /* Set EOP in the current out descriptor since the only active module is
- * the one needing the EOP. */
-
- current_out_cdesc->dma_descr->out_eop = 1;
- }
- }
-
- if (cipher_ctx.done && cipher_ctx.active) cipher_ctx.active = 0;
- if (digest_ctx.done && digest_ctx.active) digest_ctx.active = 0;
- if (csum_ctx.done && csum_ctx.active) csum_ctx.active = 0;
- indata_ix += odsc->length;
- odsc = odsc->next;
- } /* while (odsc) */ /* Process descriptors. */
- DEBUG(printk("cryptocop_setup_dma_list: done parsing operation descriptors\n"));
- if (cipher_ctx.tcfg && (cipher_ctx.active || !cipher_ctx.done)){
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher operation not terminated.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (digest_ctx.tcfg && (digest_ctx.active || !digest_ctx.done)){
- DEBUG_API(printk("cryptocop_setup_dma_list: digest operation not terminated.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (csum_ctx.tcfg && (csum_ctx.active || !csum_ctx.done)){
- DEBUG_API(printk("cryptocop_setup_dma_list: csum operation not terminated.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
-
- failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &cipher_ctx, alloc_flag);
- if (failed){
- DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
- goto error_cleanup;
- }
- failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &digest_ctx, alloc_flag);
- if (failed){
- DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
- goto error_cleanup;
- }
- failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &csum_ctx, alloc_flag);
- if (failed){
- DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
- goto error_cleanup;
- }
-
- DEBUG(printk("cryptocop_setup_dma_list: int_op=0x%p, *int_op=0x%p\n", int_op, *int_op));
- (*int_op)->cdesc_out = out_cdesc_head.next;
- (*int_op)->cdesc_in = in_cdesc_head.next;
- DEBUG(printk("cryptocop_setup_dma_list: out_cdesc_head=0x%p in_cdesc_head=0x%p\n", (*int_op)->cdesc_out, (*int_op)->cdesc_in));
-
- setup_descr_chain(out_cdesc_head.next);
- setup_descr_chain(in_cdesc_head.next);
-
- /* Last but not least: mark the last DMA in descriptor for a INTR and EOL and the the
- * last DMA out descriptor for EOL.
- */
- current_in_cdesc->dma_descr->intr = 1;
- current_in_cdesc->dma_descr->eol = 1;
- current_out_cdesc->dma_descr->eol = 1;
-
- /* Setup DMA contexts. */
- (*int_op)->ctx_out.next = NULL;
- (*int_op)->ctx_out.eol = 1;
- (*int_op)->ctx_out.intr = 0;
- (*int_op)->ctx_out.store_mode = 0;
- (*int_op)->ctx_out.en = 0;
- (*int_op)->ctx_out.dis = 0;
- (*int_op)->ctx_out.md0 = 0;
- (*int_op)->ctx_out.md1 = 0;
- (*int_op)->ctx_out.md2 = 0;
- (*int_op)->ctx_out.md3 = 0;
- (*int_op)->ctx_out.md4 = 0;
- (*int_op)->ctx_out.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_out->dma_descr);
- (*int_op)->ctx_out.saved_data_buf = (*int_op)->cdesc_out->dma_descr->buf; /* Already physical address. */
-
- (*int_op)->ctx_in.next = NULL;
- (*int_op)->ctx_in.eol = 1;
- (*int_op)->ctx_in.intr = 0;
- (*int_op)->ctx_in.store_mode = 0;
- (*int_op)->ctx_in.en = 0;
- (*int_op)->ctx_in.dis = 0;
- (*int_op)->ctx_in.md0 = 0;
- (*int_op)->ctx_in.md1 = 0;
- (*int_op)->ctx_in.md2 = 0;
- (*int_op)->ctx_in.md3 = 0;
- (*int_op)->ctx_in.md4 = 0;
-
- (*int_op)->ctx_in.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_in->dma_descr);
- (*int_op)->ctx_in.saved_data_buf = (*int_op)->cdesc_in->dma_descr->buf; /* Already physical address. */
-
- DEBUG(printk("cryptocop_setup_dma_list: done\n"));
- return 0;
-
-error_cleanup:
- {
- /* Free all allocated resources. */
- struct cryptocop_dma_desc *tmp_cdesc;
- while (digest_ctx.pad_descs){
- tmp_cdesc = digest_ctx.pad_descs->next;
- free_cdesc(digest_ctx.pad_descs);
- digest_ctx.pad_descs = tmp_cdesc;
- }
- while (csum_ctx.pad_descs){
- tmp_cdesc = csum_ctx.pad_descs->next;
- free_cdesc(csum_ctx.pad_descs);
- csum_ctx.pad_descs = tmp_cdesc;
- }
- assert(cipher_ctx.pad_descs == NULL); /* The ciphers are never padded. */
-
- if (*int_op != NULL) delete_internal_operation(*int_op);
- }
- DEBUG_API(printk("cryptocop_setup_dma_list: done with error %d\n", failed));
- return failed;
-}
-
-
-static void delete_internal_operation(struct cryptocop_int_operation *iop)
-{
- void *ptr = iop->alloc_ptr;
- struct cryptocop_dma_desc *cd = iop->cdesc_out;
- struct cryptocop_dma_desc *next;
-
- DEBUG(printk("delete_internal_operation: iop=0x%p, alloc_ptr=0x%p\n", iop, ptr));
-
- while (cd) {
- next = cd->next;
- free_cdesc(cd);
- cd = next;
- }
- cd = iop->cdesc_in;
- while (cd) {
- next = cd->next;
- free_cdesc(cd);
- cd = next;
- }
- kfree(ptr);
-}
-
-#define MD5_MIN_PAD_LENGTH (9)
-#define MD5_PAD_LENGTH_FIELD_LENGTH (8)
-
-static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length)
-{
- size_t padlen = MD5_BLOCK_LENGTH - (hashed_length % MD5_BLOCK_LENGTH);
- unsigned char *p;
- int i;
- unsigned long long int bit_length = hashed_length << 3;
-
- if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH;
-
- p = kzalloc(padlen, alloc_flag);
- if (!p) return -ENOMEM;
-
- *p = 0x80;
-
- DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length));
-
- i = padlen - MD5_PAD_LENGTH_FIELD_LENGTH;
- while (bit_length != 0){
- p[i++] = bit_length % 0x100;
- bit_length >>= 8;
- }
-
- *pad = (char*)p;
- *pad_length = padlen;
-
- return 0;
-}
-
-#define SHA1_MIN_PAD_LENGTH (9)
-#define SHA1_PAD_LENGTH_FIELD_LENGTH (8)
-
-static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length)
-{
- size_t padlen = SHA1_BLOCK_LENGTH - (hashed_length % SHA1_BLOCK_LENGTH);
- unsigned char *p;
- int i;
- unsigned long long int bit_length = hashed_length << 3;
-
- if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH;
-
- p = kzalloc(padlen, alloc_flag);
- if (!p) return -ENOMEM;
-
- *p = 0x80;
-
- DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length));
-
- i = padlen - 1;
- while (bit_length != 0){
- p[i--] = bit_length % 0x100;
- bit_length >>= 8;
- }
-
- *pad = (char*)p;
- *pad_length = padlen;
-
- return 0;
-}
-
-
-static int transform_ok(struct cryptocop_transform_init *tinit)
-{
- switch (tinit->alg){
- case cryptocop_alg_csum:
- switch (tinit->csum_mode){
- case cryptocop_csum_le:
- case cryptocop_csum_be:
- break;
- default:
- DEBUG_API(printk("transform_ok: Bad mode set for csum transform\n"));
- return -EINVAL;
- }
- case cryptocop_alg_mem2mem:
- case cryptocop_alg_md5:
- case cryptocop_alg_sha1:
- if (tinit->keylen != 0) {
- DEBUG_API(printk("transform_ok: non-zero keylength, %d, for a digest/csum algorithm\n", tinit->keylen));
- return -EINVAL; /* This check is a bit strict. */
- }
- break;
- case cryptocop_alg_des:
- if (tinit->keylen != 64) {
- DEBUG_API(printk("transform_ok: keylen %d invalid for DES\n", tinit->keylen));
- return -EINVAL;
- }
- break;
- case cryptocop_alg_3des:
- if (tinit->keylen != 192) {
- DEBUG_API(printk("transform_ok: keylen %d invalid for 3DES\n", tinit->keylen));
- return -EINVAL;
- }
- break;
- case cryptocop_alg_aes:
- if (tinit->keylen != 128 && tinit->keylen != 192 && tinit->keylen != 256) {
- DEBUG_API(printk("transform_ok: keylen %d invalid for AES\n", tinit->keylen));
- return -EINVAL;
- }
- break;
- case cryptocop_no_alg:
- default:
- DEBUG_API(printk("transform_ok: no such algorithm %d\n", tinit->alg));
- return -EINVAL;
- }
-
- switch (tinit->alg){
- case cryptocop_alg_des:
- case cryptocop_alg_3des:
- case cryptocop_alg_aes:
- if (tinit->cipher_mode != cryptocop_cipher_mode_ecb && tinit->cipher_mode != cryptocop_cipher_mode_cbc) return -EINVAL;
- default:
- break;
- }
- return 0;
-}
-
-
-int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag)
-{
- struct cryptocop_session *sess;
- struct cryptocop_transform_init *tfrm_in = tinit;
- struct cryptocop_transform_init *tmp_in;
- int no_tfrms = 0;
- int i;
- unsigned long int flags;
-
- init_stream_coprocessor(); /* For safety if we are called early */
-
- while (tfrm_in){
- int err;
- ++no_tfrms;
- if ((err = transform_ok(tfrm_in))) {
- DEBUG_API(printk("cryptocop_new_session, bad transform\n"));
- return err;
- }
- tfrm_in = tfrm_in->next;
- }
- if (0 == no_tfrms) {
- DEBUG_API(printk("cryptocop_new_session, no transforms specified\n"));
- return -EINVAL;
- }
-
- sess = kmalloc(sizeof(struct cryptocop_session), alloc_flag);
- if (!sess){
- DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_session\n"));
- return -ENOMEM;
- }
-
- sess->tfrm_ctx = kmalloc(no_tfrms * sizeof(struct cryptocop_transform_ctx), alloc_flag);
- if (!sess->tfrm_ctx) {
- DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_transform_ctx\n"));
- kfree(sess);
- return -ENOMEM;
- }
-
- tfrm_in = tinit;
- for (i = 0; i < no_tfrms; i++){
- tmp_in = tfrm_in->next;
- while (tmp_in){
- if (tmp_in->tid == tfrm_in->tid) {
- DEBUG_API(printk("cryptocop_new_session, duplicate transform ids\n"));
- kfree(sess->tfrm_ctx);
- kfree(sess);
- return -EINVAL;
- }
- tmp_in = tmp_in->next;
- }
- memcpy(&sess->tfrm_ctx[i].init, tfrm_in, sizeof(struct cryptocop_transform_init));
- sess->tfrm_ctx[i].dec_key_set = 0;
- sess->tfrm_ctx[i].next = &sess->tfrm_ctx[i] + 1;
-
- tfrm_in = tfrm_in->next;
- }
- sess->tfrm_ctx[i-1].next = NULL;
-
- spin_lock_irqsave(&cryptocop_sessions_lock, flags);
- sess->sid = next_sid;
- next_sid++;
- /* TODO If we are really paranoid we should do duplicate check to handle sid wraparound.
- * OTOH 2^64 is a really large number of session. */
- if (next_sid == 0) next_sid = 1;
-
- /* Prepend to session list. */
- sess->next = cryptocop_sessions;
- cryptocop_sessions = sess;
- spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
- *sid = sess->sid;
- return 0;
-}
-
-
-int cryptocop_free_session(cryptocop_session_id sid)
-{
- struct cryptocop_transform_ctx *tc;
- struct cryptocop_session *sess = NULL;
- struct cryptocop_session *psess = NULL;
- unsigned long int flags;
- int i;
- LIST_HEAD(remove_list);
- struct list_head *node, *tmp;
- struct cryptocop_prio_job *pj;
-
- DEBUG(printk("cryptocop_free_session: sid=%lld\n", sid));
-
- spin_lock_irqsave(&cryptocop_sessions_lock, flags);
- sess = cryptocop_sessions;
- while (sess && sess->sid != sid){
- psess = sess;
- sess = sess->next;
- }
- if (sess){
- if (psess){
- psess->next = sess->next;
- } else {
- cryptocop_sessions = sess->next;
- }
- }
- spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
-
- if (!sess) return -EINVAL;
-
- /* Remove queued jobs. */
- spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
-
- for (i = 0; i < cryptocop_prio_no_prios; i++){
- if (!list_empty(&(cryptocop_job_queues[i].jobs))){
- list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) {
- pj = list_entry(node, struct cryptocop_prio_job, node);
- if (pj->oper->sid == sid) {
- list_move_tail(node, &remove_list);
- }
- }
- }
- }
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
-
- list_for_each_safe(node, tmp, &remove_list) {
- list_del(node);
- pj = list_entry(node, struct cryptocop_prio_job, node);
- pj->oper->operation_status = -EAGAIN; /* EAGAIN is not ideal for job/session terminated but it's the best choice I know of. */
- DEBUG(printk("cryptocop_free_session: pj=0x%p, pj->oper=0x%p, pj->iop=0x%p\n", pj, pj->oper, pj->iop));
- pj->oper->cb(pj->oper, pj->oper->cb_data);
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
-
- tc = sess->tfrm_ctx;
- /* Erase keying data. */
- while (tc){
- DEBUG(printk("cryptocop_free_session: memset keys, tfrm id=%d\n", tc->init.tid));
- memset(tc->init.key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH);
- memset(tc->dec_key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH);
- tc = tc->next;
- }
- kfree(sess->tfrm_ctx);
- kfree(sess);
-
- return 0;
-}
-
-static struct cryptocop_session *get_session(cryptocop_session_id sid)
-{
- struct cryptocop_session *sess;
- unsigned long int flags;
-
- spin_lock_irqsave(&cryptocop_sessions_lock, flags);
- sess = cryptocop_sessions;
- while (sess && (sess->sid != sid)){
- sess = sess->next;
- }
- spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
-
- return sess;
-}
-
-static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid)
-{
- struct cryptocop_transform_ctx *tc = sess->tfrm_ctx;
-
- DEBUG(printk("get_transform_ctx, sess=0x%p, tid=%d\n", sess, tid));
- assert(sess != NULL);
- while (tc && tc->init.tid != tid){
- DEBUG(printk("tc=0x%p, tc->next=0x%p\n", tc, tc->next));
- tc = tc->next;
- }
- DEBUG(printk("get_transform_ctx, returning tc=0x%p\n", tc));
- return tc;
-}
-
-
-
-/* The AES s-transform matrix (s-box). */
-static const u8 aes_sbox[256] = {
- 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118,
- 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192,
- 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21,
- 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117,
- 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132,
- 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207,
- 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168,
- 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210,
- 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115,
- 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219,
- 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121,
- 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8,
- 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138,
- 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158,
- 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223,
- 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22
-};
-
-/* AES has a 32 bit word round constants for each round in the
- * key schedule. round_constant[i] is really Rcon[i+1] in FIPS187.
- */
-static u32 round_constant[11] = {
- 0x01000000, 0x02000000, 0x04000000, 0x08000000,
- 0x10000000, 0x20000000, 0x40000000, 0x80000000,
- 0x1B000000, 0x36000000, 0x6C000000
-};
-
-/* Apply the s-box to each of the four occtets in w. */
-static u32 aes_ks_subword(const u32 w)
-{
- u8 bytes[4];
-
- *(u32*)(&bytes[0]) = w;
- bytes[0] = aes_sbox[bytes[0]];
- bytes[1] = aes_sbox[bytes[1]];
- bytes[2] = aes_sbox[bytes[2]];
- bytes[3] = aes_sbox[bytes[3]];
- return *(u32*)(&bytes[0]);
-}
-
-/* The encrypt (forward) Rijndael key schedule algorithm pseudo code:
- * (Note that AES words are 32 bit long)
- *
- * KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk){
- * word temp
- * i = 0
- * while (i < Nk) {
- * w[i] = word(key[4*i, 4*i + 1, 4*i + 2, 4*i + 3])
- * i = i + 1
- * }
- * i = Nk
- *
- * while (i < (Nb * (Nr + 1))) {
- * temp = w[i - 1]
- * if ((i mod Nk) == 0) {
- * temp = SubWord(RotWord(temp)) xor Rcon[i/Nk]
- * }
- * else if ((Nk > 6) && ((i mod Nk) == 4)) {
- * temp = SubWord(temp)
- * }
- * w[i] = w[i - Nk] xor temp
- * }
- * RotWord(t) does a 8 bit cyclic shift left on a 32 bit word.
- * SubWord(t) applies the AES s-box individually to each octet
- * in a 32 bit word.
- *
- * For AES Nk can have the values 4, 6, and 8 (corresponding to
- * values for Nr of 10, 12, and 14). Nb is always 4.
- *
- * To construct w[i], w[i - 1] and w[i - Nk] must be
- * available. Consequently we must keep a state of the last Nk words
- * to be able to create the last round keys.
- */
-static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength)
-{
- u32 temp;
- u32 w_ring[8]; /* nk is max 8, use elements 0..(nk - 1) as a ringbuffer */
- u8 w_last_ix;
- int i;
- u8 nr, nk;
-
- switch (keylength){
- case 128:
- nk = 4;
- nr = 10;
- break;
- case 192:
- nk = 6;
- nr = 12;
- break;
- case 256:
- nk = 8;
- nr = 14;
- break;
- default:
- panic("stream co-processor: bad aes key length in get_aes_decrypt_key\n");
- };
-
- /* Need to do host byte order correction here since key is byte oriented and the
- * kx algorithm is word (u32) oriented. */
- for (i = 0; i < nk; i+=1) {
- w_ring[i] = be32_to_cpu(*(u32*)&key[4*i]);
- }
-
- i = (int)nk;
- w_last_ix = i - 1;
- while (i < (4 * (nr + 2))) {
- temp = w_ring[w_last_ix];
- if (!(i % nk)) {
- /* RotWord(temp) */
- temp = (temp << 8) | (temp >> 24);
- temp = aes_ks_subword(temp);
- temp ^= round_constant[i/nk - 1];
- } else if ((nk > 6) && ((i % nk) == 4)) {
- temp = aes_ks_subword(temp);
- }
- w_last_ix = (w_last_ix + 1) % nk; /* This is the same as (i-Nk) mod Nk */
- temp ^= w_ring[w_last_ix];
- w_ring[w_last_ix] = temp;
-
- /* We need the round keys for round Nr+1 and Nr+2 (round key
- * Nr+2 is the round key beyond the last one used when
- * encrypting). Rounds are numbered starting from 0, Nr=10
- * implies 11 rounds are used in encryption/decryption.
- */
- if (i >= (4 * nr)) {
- /* Need to do host byte order correction here, the key
- * is byte oriented. */
- *(u32*)dec_key = cpu_to_be32(temp);
- dec_key += 4;
- }
- ++i;
- }
-}
-
-
-/**** Job/operation management. ****/
-
-int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation)
-{
- return cryptocop_job_queue_insert(cryptocop_prio_kernel_csum, operation);
-}
-
-int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation)
-{
- return cryptocop_job_queue_insert(cryptocop_prio_kernel, operation);
-}
-
-int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation)
-{
- return cryptocop_job_queue_insert(cryptocop_prio_user, operation);
-}
-
-static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation)
-{
- int ret;
- struct cryptocop_prio_job *pj = NULL;
- unsigned long int flags;
-
- DEBUG(printk("cryptocop_job_queue_insert(%d, 0x%p)\n", prio, operation));
-
- if (!operation || !operation->cb){
- DEBUG_API(printk("cryptocop_job_queue_insert oper=0x%p, NULL operation or callback\n", operation));
- return -EINVAL;
- }
-
- if ((ret = cryptocop_job_setup(&pj, operation)) != 0){
- DEBUG_API(printk("cryptocop_job_queue_insert: job setup failed\n"));
- return ret;
- }
- assert(pj != NULL);
-
- spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
- list_add_tail(&pj->node, &cryptocop_job_queues[prio].jobs);
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
-
- /* Make sure a job is running */
- cryptocop_start_job();
- return 0;
-}
-
-static void cryptocop_do_tasklet(unsigned long unused);
-DECLARE_TASKLET (cryptocop_tasklet, cryptocop_do_tasklet, 0);
-
-static void cryptocop_do_tasklet(unsigned long unused)
-{
- struct list_head *node;
- struct cryptocop_prio_job *pj = NULL;
- unsigned long flags;
-
- DEBUG(printk("cryptocop_do_tasklet: entering\n"));
-
- do {
- spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags);
- if (!list_empty(&cryptocop_completed_jobs)){
- node = cryptocop_completed_jobs.next;
- list_del(node);
- pj = list_entry(node, struct cryptocop_prio_job, node);
- } else {
- pj = NULL;
- }
- spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags);
- if (pj) {
- assert(pj->oper != NULL);
-
- /* Notify consumer of operation completeness. */
- DEBUG(printk("cryptocop_do_tasklet: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
-
- pj->oper->operation_status = 0; /* Job is completed. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- } while (pj != NULL);
-
- DEBUG(printk("cryptocop_do_tasklet: exiting\n"));
-}
-
-static irqreturn_t
-dma_done_interrupt(int irq, void *dev_id)
-{
- struct cryptocop_prio_job *done_job;
- reg_dma_rw_ack_intr ack_intr = {
- .data = 1,
- };
-
- REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
-
- DEBUG(printk("cryptocop DMA done\n"));
-
- spin_lock(&running_job_lock);
- if (cryptocop_running_job == NULL){
- printk("stream co-processor got interrupt when not busy\n");
- spin_unlock(&running_job_lock);
- return IRQ_HANDLED;
- }
- done_job = cryptocop_running_job;
- cryptocop_running_job = NULL;
- spin_unlock(&running_job_lock);
-
- /* Start processing a job. */
- if (!spin_trylock(&cryptocop_process_lock)){
- DEBUG(printk("cryptocop irq handler, not starting a job\n"));
- } else {
- cryptocop_start_job();
- spin_unlock(&cryptocop_process_lock);
- }
-
- done_job->oper->operation_status = 0; /* Job is completed. */
- if (done_job->oper->fast_callback){
- /* This operation wants callback from interrupt. */
- done_job->oper->cb(done_job->oper, done_job->oper->cb_data);
- delete_internal_operation(done_job->iop);
- kfree(done_job);
- } else {
- spin_lock(&cryptocop_completed_jobs_lock);
- list_add_tail(&(done_job->node), &cryptocop_completed_jobs);
- spin_unlock(&cryptocop_completed_jobs_lock);
- tasklet_schedule(&cryptocop_tasklet);
- }
-
- DEBUG(printk("cryptocop leave irq handler\n"));
- return IRQ_HANDLED;
-}
-
-
-/* Setup interrupts and DMA channels. */
-static int init_cryptocop(void)
-{
- unsigned long flags;
- reg_dma_rw_cfg dma_cfg = {.en = 1};
- reg_dma_rw_intr_mask intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */
- reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 };
- reg_strcop_rw_cfg strcop_cfg = {
- .ipend = regk_strcop_little,
- .td1 = regk_strcop_e,
- .td2 = regk_strcop_d,
- .td3 = regk_strcop_e,
- .ignore_sync = 0,
- .en = 1
- };
-
- if (request_irq(DMA_IRQ, dma_done_interrupt, 0,
- "stream co-processor DMA", NULL))
- panic("request_irq stream co-processor irq dma9");
-
- (void)crisv32_request_dma(OUT_DMA, "strcop", DMA_PANIC_ON_ERROR,
- 0, dma_strp);
- (void)crisv32_request_dma(IN_DMA, "strcop", DMA_PANIC_ON_ERROR,
- 0, dma_strp);
-
- local_irq_save(flags);
-
- /* Reset and enable the cryptocop. */
- strcop_cfg.en = 0;
- REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
- strcop_cfg.en = 1;
- REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
-
- /* Enable DMAs. */
- REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */
- REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */
-
- /* Set up wordsize = 4 for DMAs. */
- DMA_WR_CMD(OUT_DMA_INST, regk_dma_set_w_size4);
- DMA_WR_CMD(IN_DMA_INST, regk_dma_set_w_size4);
-
- /* Enable interrupts. */
- REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in);
-
- /* Clear intr ack. */
- REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-/* Free used cryptocop hw resources (interrupt and DMA channels). */
-static void release_cryptocop(void)
-{
- unsigned long flags;
- reg_dma_rw_cfg dma_cfg = {.en = 0};
- reg_dma_rw_intr_mask intr_mask_in = {0};
- reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 };
-
- local_irq_save(flags);
-
- /* Clear intr ack. */
- REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
-
- /* Disable DMAs. */
- REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */
- REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */
-
- /* Disable interrupts. */
- REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in);
-
- local_irq_restore(flags);
-
- free_irq(DMA_IRQ, NULL);
-
- (void)crisv32_free_dma(OUT_DMA);
- (void)crisv32_free_dma(IN_DMA);
-}
-
-
-/* Init job queue. */
-static int cryptocop_job_queue_init(void)
-{
- int i;
-
- INIT_LIST_HEAD(&cryptocop_completed_jobs);
-
- for (i = 0; i < cryptocop_prio_no_prios; i++){
- cryptocop_job_queues[i].prio = (cryptocop_queue_priority)i;
- INIT_LIST_HEAD(&cryptocop_job_queues[i].jobs);
- }
- return 0;
-}
-
-
-static void cryptocop_job_queue_close(void)
-{
- struct list_head *node, *tmp;
- struct cryptocop_prio_job *pj = NULL;
- unsigned long int process_flags, flags;
- int i;
-
- /* FIXME: This is as yet untested code. */
-
- /* Stop strcop from getting an operation to process while we are closing the
- module. */
- spin_lock_irqsave(&cryptocop_process_lock, process_flags);
-
- /* Empty the job queue. */
- for (i = 0; i < cryptocop_prio_no_prios; i++){
- if (!list_empty(&(cryptocop_job_queues[i].jobs))){
- list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) {
- pj = list_entry(node, struct cryptocop_prio_job, node);
- list_del(node);
-
- /* Call callback to notify consumer of job removal. */
- DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
- pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
-
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- }
- }
- spin_unlock_irqrestore(&cryptocop_process_lock, process_flags);
-
- /* Remove the running job, if any. */
- spin_lock_irqsave(&running_job_lock, flags);
- if (cryptocop_running_job){
- reg_strcop_rw_cfg rw_cfg;
- reg_dma_rw_cfg dma_out_cfg, dma_in_cfg;
-
- /* Stop DMA. */
- dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg);
- dma_out_cfg.en = regk_dma_no;
- REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_out_cfg);
-
- dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg);
- dma_in_cfg.en = regk_dma_no;
- REG_WR(dma, IN_DMA_INST, rw_cfg, dma_in_cfg);
-
- /* Disable the cryptocop. */
- rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg);
- rw_cfg.en = 0;
- REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg);
-
- pj = cryptocop_running_job;
- cryptocop_running_job = NULL;
-
- /* Call callback to notify consumer of job removal. */
- DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
- pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
-
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- spin_unlock_irqrestore(&running_job_lock, flags);
-
- /* Remove completed jobs, if any. */
- spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags);
-
- list_for_each_safe(node, tmp, &cryptocop_completed_jobs) {
- pj = list_entry(node, struct cryptocop_prio_job, node);
- list_del(node);
- /* Call callback to notify consumer of job removal. */
- DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
- pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
-
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags);
-}
-
-
-static void cryptocop_start_job(void)
-{
- int i;
- struct cryptocop_prio_job *pj;
- unsigned long int flags;
- unsigned long int running_job_flags;
- reg_strcop_rw_cfg rw_cfg = {.en = 1, .ignore_sync = 0};
-
- DEBUG(printk("cryptocop_start_job: entering\n"));
-
- spin_lock_irqsave(&running_job_lock, running_job_flags);
- if (cryptocop_running_job != NULL){
- /* Already running. */
- DEBUG(printk("cryptocop_start_job: already running, exit\n"));
- spin_unlock_irqrestore(&running_job_lock, running_job_flags);
- return;
- }
- spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
-
- /* Check the queues in priority order. */
- for (i = cryptocop_prio_kernel_csum; (i < cryptocop_prio_no_prios) && list_empty(&cryptocop_job_queues[i].jobs); i++);
- if (i == cryptocop_prio_no_prios) {
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
- spin_unlock_irqrestore(&running_job_lock, running_job_flags);
- DEBUG(printk("cryptocop_start_job: no jobs to run\n"));
- return; /* No jobs to run */
- }
- DEBUG(printk("starting job for prio %d\n", i));
-
- /* TODO: Do not starve lower priority jobs. Let in a lower
- * prio job for every N-th processed higher prio job or some
- * other scheduling policy. This could reasonably be
- * tweakable since the optimal balance would depend on the
- * type of load on the system. */
-
- /* Pull the DMA lists from the job and start the DMA client. */
- pj = list_entry(cryptocop_job_queues[i].jobs.next, struct cryptocop_prio_job, node);
- list_del(&pj->node);
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
- cryptocop_running_job = pj;
-
- /* Set config register (3DES and CSUM modes). */
- switch (pj->iop->tdes_mode){
- case cryptocop_3des_eee:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_eed:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_d;
- break;
- case cryptocop_3des_ede:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_edd:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_d;
- break;
- case cryptocop_3des_dee:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_ded:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_d;
- break;
- case cryptocop_3des_dde:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_ddd:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_d;
- break;
- default:
- DEBUG(printk("cryptocop_setup_dma_list: bad 3DES mode\n"));
- }
- switch (pj->iop->csum_mode){
- case cryptocop_csum_le:
- rw_cfg.ipend = regk_strcop_little;
- break;
- case cryptocop_csum_be:
- rw_cfg.ipend = regk_strcop_big;
- break;
- default:
- DEBUG(printk("cryptocop_setup_dma_list: bad checksum mode\n"));
- }
- REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg);
-
- DEBUG(printk("cryptocop_start_job: starting DMA, new cryptocop_running_job=0x%p\n"
- "ctx_in: 0x%p, phys: 0x%p\n"
- "ctx_out: 0x%p, phys: 0x%p\n",
- pj,
- &pj->iop->ctx_in, (char*)virt_to_phys(&pj->iop->ctx_in),
- &pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out)));
-
- /* Start input DMA. */
- flush_dma_context(&pj->iop->ctx_in);
- DMA_START_CONTEXT(IN_DMA_INST, virt_to_phys(&pj->iop->ctx_in));
-
- /* Start output DMA. */
- DMA_START_CONTEXT(OUT_DMA_INST, virt_to_phys(&pj->iop->ctx_out));
-
- spin_unlock_irqrestore(&running_job_lock, running_job_flags);
- DEBUG(printk("cryptocop_start_job: exiting\n"));
-}
-
-
-static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation)
-{
- int err;
- int alloc_flag = operation->in_interrupt ? GFP_ATOMIC : GFP_KERNEL;
- void *iop_alloc_ptr = NULL;
-
- *pj = kmalloc(sizeof (struct cryptocop_prio_job), alloc_flag);
- if (!*pj) return -ENOMEM;
-
- DEBUG(printk("cryptocop_job_setup: operation=0x%p\n", operation));
-
- (*pj)->oper = operation;
- DEBUG(printk("cryptocop_job_setup, cb=0x%p cb_data=0x%p\n", (*pj)->oper->cb, (*pj)->oper->cb_data));
-
- if (operation->use_dmalists) {
- DEBUG(print_user_dma_lists(&operation->list_op));
- if (!operation->list_op.inlist || !operation->list_op.outlist || !operation->list_op.out_data_buf || !operation->list_op.in_data_buf){
- DEBUG_API(printk("cryptocop_job_setup: bad indata (use_dmalists)\n"));
- kfree(*pj);
- return -EINVAL;
- }
- iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag);
- if (!iop_alloc_ptr) {
- DEBUG_API(printk("cryptocop_job_setup: kmalloc cryptocop_int_operation\n"));
- kfree(*pj);
- return -ENOMEM;
- }
- (*pj)->iop = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out));
- DEBUG(memset((*pj)->iop, 0xff, sizeof(struct cryptocop_int_operation)));
- (*pj)->iop->alloc_ptr = iop_alloc_ptr;
- (*pj)->iop->sid = operation->sid;
- (*pj)->iop->cdesc_out = NULL;
- (*pj)->iop->cdesc_in = NULL;
- (*pj)->iop->tdes_mode = operation->list_op.tdes_mode;
- (*pj)->iop->csum_mode = operation->list_op.csum_mode;
- (*pj)->iop->ddesc_out = operation->list_op.outlist;
- (*pj)->iop->ddesc_in = operation->list_op.inlist;
-
- /* Setup DMA contexts. */
- (*pj)->iop->ctx_out.next = NULL;
- (*pj)->iop->ctx_out.eol = 1;
- (*pj)->iop->ctx_out.saved_data = operation->list_op.outlist;
- (*pj)->iop->ctx_out.saved_data_buf = operation->list_op.out_data_buf;
-
- (*pj)->iop->ctx_in.next = NULL;
- (*pj)->iop->ctx_in.eol = 1;
- (*pj)->iop->ctx_in.saved_data = operation->list_op.inlist;
- (*pj)->iop->ctx_in.saved_data_buf = operation->list_op.in_data_buf;
- } else {
- if ((err = cryptocop_setup_dma_list(operation, &(*pj)->iop, alloc_flag))) {
- DEBUG_API(printk("cryptocop_job_setup: cryptocop_setup_dma_list failed %d\n", err));
- kfree(*pj);
- return err;
- }
- }
- DEBUG(print_dma_descriptors((*pj)->iop));
-
- DEBUG(printk("cryptocop_job_setup, DMA list setup successful\n"));
-
- return 0;
-}
-
-static int cryptocop_open(struct inode *inode, struct file *filp)
-{
- int p = iminor(inode);
-
- if (p != CRYPTOCOP_MINOR) return -EINVAL;
-
- filp->private_data = NULL;
- return 0;
-}
-
-
-static int cryptocop_release(struct inode *inode, struct file *filp)
-{
- struct cryptocop_private *dev = filp->private_data;
- struct cryptocop_private *dev_next;
-
- while (dev){
- dev_next = dev->next;
- if (dev->sid != CRYPTOCOP_SESSION_ID_NONE) {
- (void)cryptocop_free_session(dev->sid);
- }
- kfree(dev);
- dev = dev_next;
- }
-
- return 0;
-}
-
-
-static int cryptocop_ioctl_close_session(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
-{
- struct cryptocop_private *dev = filp->private_data;
- struct cryptocop_private *prev_dev = NULL;
- struct strcop_session_op *sess_op = (struct strcop_session_op *)arg;
- struct strcop_session_op sop;
- int err;
-
- DEBUG(printk("cryptocop_ioctl_close_session\n"));
-
- if (!access_ok(VERIFY_READ, sess_op, sizeof(struct strcop_session_op)))
- return -EFAULT;
- err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op));
- if (err) return -EFAULT;
-
- while (dev && (dev->sid != sop.ses_id)) {
- prev_dev = dev;
- dev = dev->next;
- }
- if (dev){
- if (prev_dev){
- prev_dev->next = dev->next;
- } else {
- filp->private_data = dev->next;
- }
- err = cryptocop_free_session(dev->sid);
- if (err) return -EFAULT;
- } else {
- DEBUG_API(printk("cryptocop_ioctl_close_session: session %lld not found\n", sop.ses_id));
- return -EINVAL;
- }
- return 0;
-}
-
-
-static void ioctl_process_job_callback(struct cryptocop_operation *op, void*cb_data)
-{
- struct ioctl_job_cb_ctx *jc = (struct ioctl_job_cb_ctx *)cb_data;
-
- DEBUG(printk("ioctl_process_job_callback: op=0x%p, cb_data=0x%p\n", op, cb_data));
-
- jc->processed = 1;
- wake_up(&cryptocop_ioc_process_wq);
-}
-
-
-#define CRYPTOCOP_IOCTL_CIPHER_TID (1)
-#define CRYPTOCOP_IOCTL_DIGEST_TID (2)
-#define CRYPTOCOP_IOCTL_CSUM_TID (3)
-
-static size_t first_cfg_change_ix(struct strcop_crypto_op *crp_op)
-{
- size_t ch_ix = 0;
-
- if (crp_op->do_cipher) ch_ix = crp_op->cipher_start;
- if (crp_op->do_digest && (crp_op->digest_start < ch_ix)) ch_ix = crp_op->digest_start;
- if (crp_op->do_csum && (crp_op->csum_start < ch_ix)) ch_ix = crp_op->csum_start;
-
- DEBUG(printk("first_cfg_change_ix: ix=%d\n", ch_ix));
- return ch_ix;
-}
-
-
-static size_t next_cfg_change_ix(struct strcop_crypto_op *crp_op, size_t ix)
-{
- size_t ch_ix = INT_MAX;
- size_t tmp_ix = 0;
-
- if (crp_op->do_cipher && ((crp_op->cipher_start + crp_op->cipher_len) > ix)){
- if (crp_op->cipher_start > ix) {
- ch_ix = crp_op->cipher_start;
- } else {
- ch_ix = crp_op->cipher_start + crp_op->cipher_len;
- }
- }
- if (crp_op->do_digest && ((crp_op->digest_start + crp_op->digest_len) > ix)){
- if (crp_op->digest_start > ix) {
- tmp_ix = crp_op->digest_start;
- } else {
- tmp_ix = crp_op->digest_start + crp_op->digest_len;
- }
- if (tmp_ix < ch_ix) ch_ix = tmp_ix;
- }
- if (crp_op->do_csum && ((crp_op->csum_start + crp_op->csum_len) > ix)){
- if (crp_op->csum_start > ix) {
- tmp_ix = crp_op->csum_start;
- } else {
- tmp_ix = crp_op->csum_start + crp_op->csum_len;
- }
- if (tmp_ix < ch_ix) ch_ix = tmp_ix;
- }
- if (ch_ix == INT_MAX) ch_ix = ix;
- DEBUG(printk("next_cfg_change_ix prev ix=%d, next ix=%d\n", ix, ch_ix));
- return ch_ix;
-}
-
-
-/* Map map_length bytes from the pages starting on *pageix and *pageoffset to iovecs starting on *iovix.
- * Return -1 for ok, 0 for fail. */
-static int map_pages_to_iovec(struct iovec *iov, int iovlen, int *iovix, struct page **pages, int nopages, int *pageix, int *pageoffset, int map_length )
-{
- int tmplen;
-
- assert(iov != NULL);
- assert(iovix != NULL);
- assert(pages != NULL);
- assert(pageix != NULL);
- assert(pageoffset != NULL);
-
- DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset));
-
- while (map_length > 0){
- DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset));
- if (*iovix >= iovlen){
- DEBUG_API(printk("map_page_to_iovec: *iovix=%d >= iovlen=%d\n", *iovix, iovlen));
- return 0;
- }
- if (*pageix >= nopages){
- DEBUG_API(printk("map_page_to_iovec: *pageix=%d >= nopages=%d\n", *pageix, nopages));
- return 0;
- }
- iov[*iovix].iov_base = (unsigned char*)page_address(pages[*pageix]) + *pageoffset;
- tmplen = PAGE_SIZE - *pageoffset;
- if (tmplen < map_length){
- (*pageoffset) = 0;
- (*pageix)++;
- } else {
- tmplen = map_length;
- (*pageoffset) += map_length;
- }
- DEBUG(printk("mapping %d bytes from page %d (or %d) to iovec %d\n", tmplen, *pageix, *pageix-1, *iovix));
- iov[*iovix].iov_len = tmplen;
- map_length -= tmplen;
- (*iovix)++;
- }
- DEBUG(printk("map_page_to_iovec, exit, *iovix=%d\n", *iovix));
- return -1;
-}
-
-
-
-static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int i;
- struct cryptocop_private *dev = filp->private_data;
- struct strcop_crypto_op *crp_oper = (struct strcop_crypto_op *)arg;
- struct strcop_crypto_op oper = {0};
- int err = 0;
- struct cryptocop_operation *cop = NULL;
-
- struct ioctl_job_cb_ctx *jc = NULL;
-
- struct page **inpages = NULL;
- struct page **outpages = NULL;
- int noinpages = 0;
- int nooutpages = 0;
-
- struct cryptocop_desc descs[5]; /* Max 5 descriptors are needed, there are three transforms that
- * can get connected/disconnected on different places in the indata. */
- struct cryptocop_desc_cfg dcfgs[5*3];
- int desc_ix = 0;
- int dcfg_ix = 0;
- struct cryptocop_tfrm_cfg ciph_tcfg = {0};
- struct cryptocop_tfrm_cfg digest_tcfg = {0};
- struct cryptocop_tfrm_cfg csum_tcfg = {0};
-
- unsigned char *digest_result = NULL;
- int digest_length = 0;
- int cblocklen = 0;
- unsigned char csum_result[CSUM_BLOCK_LENGTH];
- struct cryptocop_session *sess;
-
- int iovlen = 0;
- int iovix = 0;
- int pageix = 0;
- int pageoffset = 0;
-
- size_t prev_ix = 0;
- size_t next_ix;
-
- int cipher_active, digest_active, csum_active;
- int end_digest, end_csum;
- int digest_done = 0;
- int cipher_done = 0;
- int csum_done = 0;
-
- DEBUG(printk("cryptocop_ioctl_process\n"));
-
- if (!access_ok(VERIFY_WRITE, crp_oper, sizeof(struct strcop_crypto_op))){
- DEBUG_API(printk("cryptocop_ioctl_process: !access_ok crp_oper!\n"));
- return -EFAULT;
- }
- if (copy_from_user(&oper, crp_oper, sizeof(struct strcop_crypto_op))) {
- DEBUG_API(printk("cryptocop_ioctl_process: copy_from_user\n"));
- return -EFAULT;
- }
- DEBUG(print_strcop_crypto_op(&oper));
-
- while (dev && dev->sid != oper.ses_id) dev = dev->next;
- if (!dev){
- DEBUG_API(printk("cryptocop_ioctl_process: session %lld not found\n", oper.ses_id));
- return -EINVAL;
- }
-
- /* Check buffers. */
- if (((oper.indata + oper.inlen) < oper.indata) || ((oper.cipher_outdata + oper.cipher_outlen) < oper.cipher_outdata)){
- DEBUG_API(printk("cryptocop_ioctl_process: user buffers wrapped around, bad user!\n"));
- return -EINVAL;
- }
-
- if (!access_ok(VERIFY_WRITE, oper.cipher_outdata, oper.cipher_outlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: !access_ok out data!\n"));
- return -EFAULT;
- }
- if (!access_ok(VERIFY_READ, oper.indata, oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: !access_ok in data!\n"));
- return -EFAULT;
- }
-
- cop = kmalloc(sizeof(struct cryptocop_operation), GFP_KERNEL);
- if (!cop) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n"));
- return -ENOMEM;
- }
- jc = kmalloc(sizeof(struct ioctl_job_cb_ctx), GFP_KERNEL);
- if (!jc) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n"));
- err = -ENOMEM;
- goto error_cleanup;
- }
- jc->processed = 0;
-
- cop->cb_data = jc;
- cop->cb = ioctl_process_job_callback;
- cop->operation_status = 0;
- cop->use_dmalists = 0;
- cop->in_interrupt = 0;
- cop->fast_callback = 0;
- cop->tfrm_op.tfrm_cfg = NULL;
- cop->tfrm_op.desc = NULL;
- cop->tfrm_op.indata = NULL;
- cop->tfrm_op.incount = 0;
- cop->tfrm_op.inlen = 0;
- cop->tfrm_op.outdata = NULL;
- cop->tfrm_op.outcount = 0;
- cop->tfrm_op.outlen = 0;
-
- sess = get_session(oper.ses_id);
- if (!sess){
- DEBUG_API(printk("cryptocop_ioctl_process: bad session id.\n"));
- kfree(cop);
- kfree(jc);
- return -EINVAL;
- }
-
- if (oper.do_cipher) {
- unsigned int cipher_outlen = 0;
- struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_CIPHER_TID);
- if (!tc) {
- DEBUG_API(printk("cryptocop_ioctl_process: no cipher transform in session.\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
- ciph_tcfg.tid = CRYPTOCOP_IOCTL_CIPHER_TID;
- ciph_tcfg.inject_ix = 0;
- ciph_tcfg.flags = 0;
- if ((oper.cipher_start < 0) || (oper.cipher_len <= 0) || (oper.cipher_start > oper.inlen) || ((oper.cipher_start + oper.cipher_len) > oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: bad cipher length\n"));
- kfree(cop);
- kfree(jc);
- return -EINVAL;
- }
- cblocklen = tc->init.alg == cryptocop_alg_aes ? AES_BLOCK_LENGTH : DES_BLOCK_LENGTH;
- if (oper.cipher_len % cblocklen) {
- kfree(cop);
- kfree(jc);
- DEBUG_API(printk("cryptocop_ioctl_process: cipher inlength not multiple of block length.\n"));
- return -EINVAL;
- }
- cipher_outlen = oper.cipher_len;
- if (tc->init.cipher_mode == cryptocop_cipher_mode_cbc){
- if (oper.cipher_explicit) {
- ciph_tcfg.flags |= CRYPTOCOP_EXPLICIT_IV;
- memcpy(ciph_tcfg.iv, oper.cipher_iv, cblocklen);
- } else {
- cipher_outlen = oper.cipher_len - cblocklen;
- }
- } else {
- if (oper.cipher_explicit){
- kfree(cop);
- kfree(jc);
- DEBUG_API(printk("cryptocop_ioctl_process: explicit_iv when not CBC mode\n"));
- return -EINVAL;
- }
- }
- if (oper.cipher_outlen != cipher_outlen) {
- kfree(cop);
- kfree(jc);
- DEBUG_API(printk("cryptocop_ioctl_process: cipher_outlen incorrect, should be %d not %d.\n", cipher_outlen, oper.cipher_outlen));
- return -EINVAL;
- }
-
- if (oper.decrypt){
- ciph_tcfg.flags |= CRYPTOCOP_DECRYPT;
- } else {
- ciph_tcfg.flags |= CRYPTOCOP_ENCRYPT;
- }
- ciph_tcfg.next = cop->tfrm_op.tfrm_cfg;
- cop->tfrm_op.tfrm_cfg = &ciph_tcfg;
- }
- if (oper.do_digest){
- struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_DIGEST_TID);
- if (!tc) {
- DEBUG_API(printk("cryptocop_ioctl_process: no digest transform in session.\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
- digest_length = tc->init.alg == cryptocop_alg_md5 ? 16 : 20;
- digest_result = kmalloc(digest_length, GFP_KERNEL);
- if (!digest_result) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc digest_result\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
- DEBUG(memset(digest_result, 0xff, digest_length));
-
- digest_tcfg.tid = CRYPTOCOP_IOCTL_DIGEST_TID;
- digest_tcfg.inject_ix = 0;
- ciph_tcfg.inject_ix += digest_length;
- if ((oper.digest_start < 0) || (oper.digest_len <= 0) || (oper.digest_start > oper.inlen) || ((oper.digest_start + oper.digest_len) > oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: bad digest length\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
-
- digest_tcfg.next = cop->tfrm_op.tfrm_cfg;
- cop->tfrm_op.tfrm_cfg = &digest_tcfg;
- }
- if (oper.do_csum){
- csum_tcfg.tid = CRYPTOCOP_IOCTL_CSUM_TID;
- csum_tcfg.inject_ix = digest_length;
- ciph_tcfg.inject_ix += 2;
-
- if ((oper.csum_start < 0) || (oper.csum_len <= 0) || (oper.csum_start > oper.inlen) || ((oper.csum_start + oper.csum_len) > oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: bad csum length\n"));
- kfree(cop);
- kfree(jc);
- return -EINVAL;
- }
-
- csum_tcfg.next = cop->tfrm_op.tfrm_cfg;
- cop->tfrm_op.tfrm_cfg = &csum_tcfg;
- }
-
- prev_ix = first_cfg_change_ix(&oper);
- if (prev_ix > oper.inlen) {
- DEBUG_API(printk("cryptocop_ioctl_process: length mismatch\n"));
- nooutpages = noinpages = 0;
- err = -EINVAL;
- goto error_cleanup;
- }
- DEBUG(printk("cryptocop_ioctl_process: inlen=%d, cipher_outlen=%d\n", oper.inlen, oper.cipher_outlen));
-
- /* Map user pages for in and out data of the operation. */
- noinpages = (((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK) + oper.inlen - 1 - prev_ix + ~PAGE_MASK) >> PAGE_SHIFT;
- DEBUG(printk("cryptocop_ioctl_process: noinpages=%d\n", noinpages));
- inpages = kmalloc(noinpages * sizeof(struct page*), GFP_KERNEL);
- if (!inpages){
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc inpages\n"));
- nooutpages = noinpages = 0;
- err = -ENOMEM;
- goto error_cleanup;
- }
- if (oper.do_cipher){
- nooutpages = (((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) + oper.cipher_outlen - 1 + ~PAGE_MASK) >> PAGE_SHIFT;
- DEBUG(printk("cryptocop_ioctl_process: nooutpages=%d\n", nooutpages));
- outpages = kmalloc(nooutpages * sizeof(struct page*), GFP_KERNEL);
- if (!outpages){
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc outpages\n"));
- nooutpages = noinpages = 0;
- err = -ENOMEM;
- goto error_cleanup;
- }
- }
-
- err = get_user_pages_fast((unsigned long)(oper.indata + prev_ix),
- noinpages,
- false, /* read access only for in data */
- inpages);
-
- if (err < 0) {
- nooutpages = noinpages = 0;
- DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages indata\n"));
- goto error_cleanup;
- }
- noinpages = err;
- if (oper.do_cipher) {
- err = get_user_pages_fast((unsigned long)oper.cipher_outdata,
- nooutpages,
- true, /* write access for out data */
- outpages);
- if (err < 0) {
- nooutpages = 0;
- DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages outdata\n"));
- goto error_cleanup;
- }
- nooutpages = err;
- }
-
- /* Add 6 to nooutpages to make room for possibly inserted buffers for storing digest and
- * csum output and splits when units are (dis-)connected. */
- cop->tfrm_op.indata = kmalloc((noinpages) * sizeof(struct iovec), GFP_KERNEL);
- cop->tfrm_op.outdata = kmalloc((6 + nooutpages) * sizeof(struct iovec), GFP_KERNEL);
- if (!cop->tfrm_op.indata || !cop->tfrm_op.outdata) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc iovecs\n"));
- err = -ENOMEM;
- goto error_cleanup;
- }
-
- cop->tfrm_op.inlen = oper.inlen - prev_ix;
- cop->tfrm_op.outlen = 0;
- if (oper.do_cipher) cop->tfrm_op.outlen += oper.cipher_outlen;
- if (oper.do_digest) cop->tfrm_op.outlen += digest_length;
- if (oper.do_csum) cop->tfrm_op.outlen += 2;
-
- /* Setup the in iovecs. */
- cop->tfrm_op.incount = noinpages;
- if (noinpages > 1){
- size_t tmplen = cop->tfrm_op.inlen;
-
- cop->tfrm_op.indata[0].iov_len = PAGE_SIZE - ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
- cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
- tmplen -= cop->tfrm_op.indata[0].iov_len;
- for (i = 1; i<noinpages; i++){
- cop->tfrm_op.indata[i].iov_len = tmplen < PAGE_SIZE ? tmplen : PAGE_SIZE;
- cop->tfrm_op.indata[i].iov_base = (unsigned char*)page_address(inpages[i]);
- tmplen -= PAGE_SIZE;
- }
- } else {
- cop->tfrm_op.indata[0].iov_len = oper.inlen - prev_ix;
- cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
- }
-
- iovlen = nooutpages + 6;
- pageoffset = oper.do_cipher ? ((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) : 0;
-
- next_ix = next_cfg_change_ix(&oper, prev_ix);
- if (prev_ix == next_ix){
- DEBUG_API(printk("cryptocop_ioctl_process: length configuration broken.\n"));
- err = -EINVAL; /* This should be impossible barring bugs. */
- goto error_cleanup;
- }
- while (prev_ix != next_ix){
- end_digest = end_csum = cipher_active = digest_active = csum_active = 0;
- descs[desc_ix].cfg = NULL;
- descs[desc_ix].length = next_ix - prev_ix;
-
- if (oper.do_cipher && (oper.cipher_start < next_ix) && (prev_ix < (oper.cipher_start + oper.cipher_len))) {
- dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CIPHER_TID;
- dcfgs[dcfg_ix].src = cryptocop_source_dma;
- cipher_active = 1;
-
- if (next_ix == (oper.cipher_start + oper.cipher_len)){
- cipher_done = 1;
- dcfgs[dcfg_ix].last = 1;
- } else {
- dcfgs[dcfg_ix].last = 0;
- }
- dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
- descs[desc_ix].cfg = &dcfgs[dcfg_ix];
- ++dcfg_ix;
- }
- if (oper.do_digest && (oper.digest_start < next_ix) && (prev_ix < (oper.digest_start + oper.digest_len))) {
- digest_active = 1;
- dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_DIGEST_TID;
- dcfgs[dcfg_ix].src = cryptocop_source_dma;
- if (next_ix == (oper.digest_start + oper.digest_len)){
- assert(!digest_done);
- digest_done = 1;
- dcfgs[dcfg_ix].last = 1;
- } else {
- dcfgs[dcfg_ix].last = 0;
- }
- dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
- descs[desc_ix].cfg = &dcfgs[dcfg_ix];
- ++dcfg_ix;
- }
- if (oper.do_csum && (oper.csum_start < next_ix) && (prev_ix < (oper.csum_start + oper.csum_len))){
- csum_active = 1;
- dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CSUM_TID;
- dcfgs[dcfg_ix].src = cryptocop_source_dma;
- if (next_ix == (oper.csum_start + oper.csum_len)){
- csum_done = 1;
- dcfgs[dcfg_ix].last = 1;
- } else {
- dcfgs[dcfg_ix].last = 0;
- }
- dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
- descs[desc_ix].cfg = &dcfgs[dcfg_ix];
- ++dcfg_ix;
- }
- if (!descs[desc_ix].cfg){
- DEBUG_API(printk("cryptocop_ioctl_process: data segment %d (%d to %d) had no active transforms\n", desc_ix, prev_ix, next_ix));
- err = -EINVAL;
- goto error_cleanup;
- }
- descs[desc_ix].next = &(descs[desc_ix]) + 1;
- ++desc_ix;
- prev_ix = next_ix;
- next_ix = next_cfg_change_ix(&oper, prev_ix);
- }
- if (desc_ix > 0){
- descs[desc_ix-1].next = NULL;
- } else {
- descs[0].next = NULL;
- }
- if (oper.do_digest) {
- DEBUG(printk("cryptocop_ioctl_process: mapping %d byte digest output to iovec %d\n", digest_length, iovix));
- /* Add outdata iovec, length == <length of type of digest> */
- cop->tfrm_op.outdata[iovix].iov_base = digest_result;
- cop->tfrm_op.outdata[iovix].iov_len = digest_length;
- ++iovix;
- }
- if (oper.do_csum) {
- /* Add outdata iovec, length == 2, the length of csum. */
- DEBUG(printk("cryptocop_ioctl_process: mapping 2 byte csum output to iovec %d\n", iovix));
- /* Add outdata iovec, length == <length of type of digest> */
- cop->tfrm_op.outdata[iovix].iov_base = csum_result;
- cop->tfrm_op.outdata[iovix].iov_len = 2;
- ++iovix;
- }
- if (oper.do_cipher) {
- if (!map_pages_to_iovec(cop->tfrm_op.outdata, iovlen, &iovix, outpages, nooutpages, &pageix, &pageoffset, oper.cipher_outlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: failed to map pages to iovec.\n"));
- err = -ENOSYS; /* This should be impossible barring bugs. */
- goto error_cleanup;
- }
- }
- DEBUG(printk("cryptocop_ioctl_process: setting cop->tfrm_op.outcount %d\n", iovix));
- cop->tfrm_op.outcount = iovix;
- assert(iovix <= (nooutpages + 6));
-
- cop->sid = oper.ses_id;
- cop->tfrm_op.desc = &descs[0];
-
- DEBUG(printk("cryptocop_ioctl_process: inserting job, cb_data=0x%p\n", cop->cb_data));
-
- if ((err = cryptocop_job_queue_insert_user_job(cop)) != 0) {
- DEBUG_API(printk("cryptocop_ioctl_process: insert job %d\n", err));
- err = -EINVAL;
- goto error_cleanup;
- }
-
- DEBUG(printk("cryptocop_ioctl_process: begin wait for result\n"));
-
- wait_event(cryptocop_ioc_process_wq, (jc->processed != 0));
- DEBUG(printk("cryptocop_ioctl_process: end wait for result\n"));
- if (!jc->processed){
- printk(KERN_WARNING "cryptocop_ioctl_process: job not processed at completion\n");
- err = -EIO;
- goto error_cleanup;
- }
-
- /* Job process done. Cipher output should already be correct in job so no post processing of outdata. */
- DEBUG(printk("cryptocop_ioctl_process: operation_status = %d\n", cop->operation_status));
- if (cop->operation_status == 0){
- if (oper.do_digest){
- DEBUG(printk("cryptocop_ioctl_process: copy %d bytes digest to user\n", digest_length));
- err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, digest), digest_result, digest_length);
- if (0 != err){
- DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, digest length %d, err %d\n", digest_length, err));
- err = -EFAULT;
- goto error_cleanup;
- }
- }
- if (oper.do_csum){
- DEBUG(printk("cryptocop_ioctl_process: copy 2 bytes checksum to user\n"));
- err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, csum), csum_result, 2);
- if (0 != err){
- DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, csum, err %d\n", err));
- err = -EFAULT;
- goto error_cleanup;
- }
- }
- err = 0;
- } else {
- DEBUG(printk("cryptocop_ioctl_process: returning err = operation_status = %d\n", cop->operation_status));
- err = cop->operation_status;
- }
-
- error_cleanup:
- /* Release page caches. */
- for (i = 0; i < noinpages; i++){
- put_page(inpages[i]);
- }
- for (i = 0; i < nooutpages; i++){
- int spdl_err;
- /* Mark output pages dirty. */
- spdl_err = set_page_dirty_lock(outpages[i]);
- DEBUG(if (spdl_err < 0)printk("cryptocop_ioctl_process: set_page_dirty_lock returned %d\n", spdl_err));
- }
- for (i = 0; i < nooutpages; i++){
- put_page(outpages[i]);
- }
-
- kfree(digest_result);
- kfree(inpages);
- kfree(outpages);
- if (cop){
- kfree(cop->tfrm_op.indata);
- kfree(cop->tfrm_op.outdata);
- kfree(cop);
- }
- kfree(jc);
-
- DEBUG(print_lock_status());
-
- return err;
-}
-
-
-static int cryptocop_ioctl_create_session(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
-{
- cryptocop_session_id sid;
- int err;
- struct cryptocop_private *dev;
- struct strcop_session_op *sess_op = (struct strcop_session_op *)arg;
- struct strcop_session_op sop;
- struct cryptocop_transform_init *tis = NULL;
- struct cryptocop_transform_init ti_cipher = {0};
- struct cryptocop_transform_init ti_digest = {0};
- struct cryptocop_transform_init ti_csum = {0};
-
- if (!access_ok(VERIFY_WRITE, sess_op, sizeof(struct strcop_session_op)))
- return -EFAULT;
- err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op));
- if (err) return -EFAULT;
- if (sop.cipher != cryptocop_cipher_none) {
- if (!access_ok(VERIFY_READ, sop.key, sop.keylen)) return -EFAULT;
- }
- DEBUG(printk("cryptocop_ioctl_create_session, sess_op:\n"));
-
- DEBUG(printk("\tcipher:%d\n"
- "\tcipher_mode:%d\n"
- "\tdigest:%d\n"
- "\tcsum:%d\n",
- (int)sop.cipher,
- (int)sop.cmode,
- (int)sop.digest,
- (int)sop.csum));
-
- if (sop.cipher != cryptocop_cipher_none){
- /* Init the cipher. */
- switch (sop.cipher){
- case cryptocop_cipher_des:
- ti_cipher.alg = cryptocop_alg_des;
- break;
- case cryptocop_cipher_3des:
- ti_cipher.alg = cryptocop_alg_3des;
- break;
- case cryptocop_cipher_aes:
- ti_cipher.alg = cryptocop_alg_aes;
- break;
- default:
- DEBUG_API(printk("create session, bad cipher algorithm %d\n", sop.cipher));
- return -EINVAL;
- };
- DEBUG(printk("setting cipher transform %d\n", ti_cipher.alg));
- copy_from_user(ti_cipher.key, sop.key, sop.keylen/8);
- ti_cipher.keylen = sop.keylen;
- switch (sop.cmode){
- case cryptocop_cipher_mode_cbc:
- case cryptocop_cipher_mode_ecb:
- ti_cipher.cipher_mode = sop.cmode;
- break;
- default:
- DEBUG_API(printk("create session, bad cipher mode %d\n", sop.cmode));
- return -EINVAL;
- }
- DEBUG(printk("cryptocop_ioctl_create_session: setting CBC mode %d\n", ti_cipher.cipher_mode));
- switch (sop.des3_mode){
- case cryptocop_3des_eee:
- case cryptocop_3des_eed:
- case cryptocop_3des_ede:
- case cryptocop_3des_edd:
- case cryptocop_3des_dee:
- case cryptocop_3des_ded:
- case cryptocop_3des_dde:
- case cryptocop_3des_ddd:
- ti_cipher.tdes_mode = sop.des3_mode;
- break;
- default:
- DEBUG_API(printk("create session, bad 3DES mode %d\n", sop.des3_mode));
- return -EINVAL;
- }
- ti_cipher.tid = CRYPTOCOP_IOCTL_CIPHER_TID;
- ti_cipher.next = tis;
- tis = &ti_cipher;
- } /* if (sop.cipher != cryptocop_cipher_none) */
- if (sop.digest != cryptocop_digest_none){
- DEBUG(printk("setting digest transform\n"));
- switch (sop.digest){
- case cryptocop_digest_md5:
- ti_digest.alg = cryptocop_alg_md5;
- break;
- case cryptocop_digest_sha1:
- ti_digest.alg = cryptocop_alg_sha1;
- break;
- default:
- DEBUG_API(printk("create session, bad digest algorithm %d\n", sop.digest));
- return -EINVAL;
- }
- ti_digest.tid = CRYPTOCOP_IOCTL_DIGEST_TID;
- ti_digest.next = tis;
- tis = &ti_digest;
- } /* if (sop.digest != cryptocop_digest_none) */
- if (sop.csum != cryptocop_csum_none){
- DEBUG(printk("setting csum transform\n"));
- switch (sop.csum){
- case cryptocop_csum_le:
- case cryptocop_csum_be:
- ti_csum.csum_mode = sop.csum;
- break;
- default:
- DEBUG_API(printk("create session, bad checksum algorithm %d\n", sop.csum));
- return -EINVAL;
- }
- ti_csum.alg = cryptocop_alg_csum;
- ti_csum.tid = CRYPTOCOP_IOCTL_CSUM_TID;
- ti_csum.next = tis;
- tis = &ti_csum;
- } /* (sop.csum != cryptocop_csum_none) */
- dev = kmalloc(sizeof(struct cryptocop_private), GFP_KERNEL);
- if (!dev){
- DEBUG_API(printk("create session, alloc dev\n"));
- return -ENOMEM;
- }
-
- err = cryptocop_new_session(&sid, tis, GFP_KERNEL);
- DEBUG({ if (err) printk("create session, cryptocop_new_session %d\n", err);});
-
- if (err) {
- kfree(dev);
- return err;
- }
- sess_op->ses_id = sid;
- dev->sid = sid;
- dev->next = filp->private_data;
- filp->private_data = dev;
-
- return 0;
-}
-
-static long cryptocop_ioctl_unlocked(struct inode *inode,
- struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int err = 0;
- if (_IOC_TYPE(cmd) != ETRAXCRYPTOCOP_IOCTYPE) {
- DEBUG_API(printk("cryptocop_ioctl: wrong type\n"));
- return -ENOTTY;
- }
- if (_IOC_NR(cmd) > CRYPTOCOP_IO_MAXNR){
- return -ENOTTY;
- }
- /* Access check of the argument. Some commands, e.g. create session and process op,
- needs additional checks. Those are handled in the command handling functions. */
- if (_IOC_DIR(cmd) & _IOC_READ)
- err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
- else if (_IOC_DIR(cmd) & _IOC_WRITE)
- err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
- if (err) return -EFAULT;
-
- switch (cmd) {
- case CRYPTOCOP_IO_CREATE_SESSION:
- return cryptocop_ioctl_create_session(inode, filp, cmd, arg);
- case CRYPTOCOP_IO_CLOSE_SESSION:
- return cryptocop_ioctl_close_session(inode, filp, cmd, arg);
- case CRYPTOCOP_IO_PROCESS_OP:
- return cryptocop_ioctl_process(inode, filp, cmd, arg);
- default:
- DEBUG_API(printk("cryptocop_ioctl: unknown command\n"));
- return -ENOTTY;
- }
- return 0;
-}
-
-static long
-cryptocop_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- long ret;
-
- mutex_lock(&cryptocop_mutex);
- ret = cryptocop_ioctl_unlocked(file_inode(filp), filp, cmd, arg);
- mutex_unlock(&cryptocop_mutex);
-
- return ret;
-}
-
-
-#ifdef LDEBUG
-static void print_dma_descriptors(struct cryptocop_int_operation *iop)
-{
- struct cryptocop_dma_desc *cdesc_out = iop->cdesc_out;
- struct cryptocop_dma_desc *cdesc_in = iop->cdesc_in;
- int i;
-
- printk("print_dma_descriptors start\n");
-
- printk("iop:\n");
- printk("\tsid: 0x%llx\n", iop->sid);
-
- printk("\tcdesc_out: 0x%p\n", iop->cdesc_out);
- printk("\tcdesc_in: 0x%p\n", iop->cdesc_in);
- printk("\tddesc_out: 0x%p\n", iop->ddesc_out);
- printk("\tddesc_in: 0x%p\n", iop->ddesc_in);
-
- printk("\niop->ctx_out: 0x%p phys: 0x%p\n", &iop->ctx_out, (char*)virt_to_phys(&iop->ctx_out));
- printk("\tnext: 0x%p\n"
- "\tsaved_data: 0x%p\n"
- "\tsaved_data_buf: 0x%p\n",
- iop->ctx_out.next,
- iop->ctx_out.saved_data,
- iop->ctx_out.saved_data_buf);
-
- printk("\niop->ctx_in: 0x%p phys: 0x%p\n", &iop->ctx_in, (char*)virt_to_phys(&iop->ctx_in));
- printk("\tnext: 0x%p\n"
- "\tsaved_data: 0x%p\n"
- "\tsaved_data_buf: 0x%p\n",
- iop->ctx_in.next,
- iop->ctx_in.saved_data,
- iop->ctx_in.saved_data_buf);
-
- i = 0;
- while (cdesc_out) {
- dma_descr_data *td;
- printk("cdesc_out %d, desc=0x%p\n", i, cdesc_out->dma_descr);
- printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_out->dma_descr));
- td = cdesc_out->dma_descr;
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- td->buf,
- td->after,
- td->md,
- td->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- td->wait,
- td->eol,
- td->out_eop,
- td->in_eop,
- td->intr);
- cdesc_out = cdesc_out->next;
- i++;
- }
- i = 0;
- while (cdesc_in) {
- dma_descr_data *td;
- printk("cdesc_in %d, desc=0x%p\n", i, cdesc_in->dma_descr);
- printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_in->dma_descr));
- td = cdesc_in->dma_descr;
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- td->buf,
- td->after,
- td->md,
- td->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- td->wait,
- td->eol,
- td->out_eop,
- td->in_eop,
- td->intr);
- cdesc_in = cdesc_in->next;
- i++;
- }
-
- printk("print_dma_descriptors end\n");
-}
-
-
-static void print_strcop_crypto_op(struct strcop_crypto_op *cop)
-{
- printk("print_strcop_crypto_op, 0x%p\n", cop);
-
- /* Indata. */
- printk("indata=0x%p\n"
- "inlen=%d\n"
- "do_cipher=%d\n"
- "decrypt=%d\n"
- "cipher_explicit=%d\n"
- "cipher_start=%d\n"
- "cipher_len=%d\n"
- "outdata=0x%p\n"
- "outlen=%d\n",
- cop->indata,
- cop->inlen,
- cop->do_cipher,
- cop->decrypt,
- cop->cipher_explicit,
- cop->cipher_start,
- cop->cipher_len,
- cop->cipher_outdata,
- cop->cipher_outlen);
-
- printk("do_digest=%d\n"
- "digest_start=%d\n"
- "digest_len=%d\n",
- cop->do_digest,
- cop->digest_start,
- cop->digest_len);
-
- printk("do_csum=%d\n"
- "csum_start=%d\n"
- "csum_len=%d\n",
- cop->do_csum,
- cop->csum_start,
- cop->csum_len);
-}
-
-static void print_cryptocop_operation(struct cryptocop_operation *cop)
-{
- struct cryptocop_desc *d;
- struct cryptocop_tfrm_cfg *tc;
- struct cryptocop_desc_cfg *dc;
- int i;
-
- printk("print_cryptocop_operation, cop=0x%p\n\n", cop);
- printk("sid: %lld\n", cop->sid);
- printk("operation_status=%d\n"
- "use_dmalists=%d\n"
- "in_interrupt=%d\n"
- "fast_callback=%d\n",
- cop->operation_status,
- cop->use_dmalists,
- cop->in_interrupt,
- cop->fast_callback);
-
- if (cop->use_dmalists){
- print_user_dma_lists(&cop->list_op);
- } else {
- printk("cop->tfrm_op\n"
- "tfrm_cfg=0x%p\n"
- "desc=0x%p\n"
- "indata=0x%p\n"
- "incount=%d\n"
- "inlen=%d\n"
- "outdata=0x%p\n"
- "outcount=%d\n"
- "outlen=%d\n\n",
- cop->tfrm_op.tfrm_cfg,
- cop->tfrm_op.desc,
- cop->tfrm_op.indata,
- cop->tfrm_op.incount,
- cop->tfrm_op.inlen,
- cop->tfrm_op.outdata,
- cop->tfrm_op.outcount,
- cop->tfrm_op.outlen);
-
- tc = cop->tfrm_op.tfrm_cfg;
- while (tc){
- printk("tfrm_cfg, 0x%p\n"
- "tid=%d\n"
- "flags=%d\n"
- "inject_ix=%d\n"
- "next=0x%p\n",
- tc,
- tc->tid,
- tc->flags,
- tc->inject_ix,
- tc->next);
- tc = tc->next;
- }
- d = cop->tfrm_op.desc;
- while (d){
- printk("\n======================desc, 0x%p\n"
- "length=%d\n"
- "cfg=0x%p\n"
- "next=0x%p\n",
- d,
- d->length,
- d->cfg,
- d->next);
- dc = d->cfg;
- while (dc){
- printk("=========desc_cfg, 0x%p\n"
- "tid=%d\n"
- "src=%d\n"
- "last=%d\n"
- "next=0x%p\n",
- dc,
- dc->tid,
- dc->src,
- dc->last,
- dc->next);
- dc = dc->next;
- }
- d = d->next;
- }
- printk("\n====iniov\n");
- for (i = 0; i < cop->tfrm_op.incount; i++){
- printk("indata[%d]\n"
- "base=0x%p\n"
- "len=%d\n",
- i,
- cop->tfrm_op.indata[i].iov_base,
- cop->tfrm_op.indata[i].iov_len);
- }
- printk("\n====outiov\n");
- for (i = 0; i < cop->tfrm_op.outcount; i++){
- printk("outdata[%d]\n"
- "base=0x%p\n"
- "len=%d\n",
- i,
- cop->tfrm_op.outdata[i].iov_base,
- cop->tfrm_op.outdata[i].iov_len);
- }
- }
- printk("------------end print_cryptocop_operation\n");
-}
-
-
-static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op)
-{
- dma_descr_data *dd;
- int i;
-
- printk("print_user_dma_lists, dma_op=0x%p\n", dma_op);
-
- printk("out_data_buf = 0x%p, phys_to_virt(out_data_buf) = 0x%p\n", dma_op->out_data_buf, phys_to_virt((unsigned long int)dma_op->out_data_buf));
- printk("in_data_buf = 0x%p, phys_to_virt(in_data_buf) = 0x%p\n", dma_op->in_data_buf, phys_to_virt((unsigned long int)dma_op->in_data_buf));
-
- printk("##############outlist\n");
- dd = phys_to_virt((unsigned long int)dma_op->outlist);
- i = 0;
- while (dd != NULL) {
- printk("#%d phys_to_virt(desc) 0x%p\n", i, dd);
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- dd->buf,
- dd->after,
- dd->md,
- dd->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- dd->wait,
- dd->eol,
- dd->out_eop,
- dd->in_eop,
- dd->intr);
- if (dd->eol)
- dd = NULL;
- else
- dd = phys_to_virt((unsigned long int)dd->next);
- ++i;
- }
-
- printk("##############inlist\n");
- dd = phys_to_virt((unsigned long int)dma_op->inlist);
- i = 0;
- while (dd != NULL) {
- printk("#%d phys_to_virt(desc) 0x%p\n", i, dd);
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- dd->buf,
- dd->after,
- dd->md,
- dd->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- dd->wait,
- dd->eol,
- dd->out_eop,
- dd->in_eop,
- dd->intr);
- if (dd->eol)
- dd = NULL;
- else
- dd = phys_to_virt((unsigned long int)dd->next);
- ++i;
- }
-}
-
-
-static void print_lock_status(void)
-{
- printk("**********************print_lock_status\n");
- printk("cryptocop_completed_jobs_lock %d\n", spin_is_locked(&cryptocop_completed_jobs_lock));
- printk("cryptocop_job_queue_lock %d\n", spin_is_locked(&cryptocop_job_queue_lock));
- printk("descr_pool_lock %d\n", spin_is_locked(&descr_pool_lock));
- printk("cryptocop_sessions_lock %d\n", spin_is_locked(cryptocop_sessions_lock));
- printk("running_job_lock %d\n", spin_is_locked(running_job_lock));
- printk("cryptocop_process_lock %d\n", spin_is_locked(cryptocop_process_lock));
-}
-#endif /* LDEBUG */
-
-
-static const char cryptocop_name[] = "ETRAX FS stream co-processor";
-
-static int init_stream_coprocessor(void)
-{
- int err;
- int i;
- static int initialized = 0;
-
- if (initialized)
- return 0;
-
- initialized = 1;
-
- printk("ETRAX FS stream co-processor driver v0.01, (c) 2003 Axis Communications AB\n");
-
- err = register_chrdev(CRYPTOCOP_MAJOR, cryptocop_name, &cryptocop_fops);
- if (err < 0) {
- printk(KERN_ERR "stream co-processor: could not get major number.\n");
- return err;
- }
-
- err = init_cryptocop();
- if (err) {
- (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name);
- return err;
- }
- err = cryptocop_job_queue_init();
- if (err) {
- release_cryptocop();
- (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name);
- return err;
- }
- /* Init the descriptor pool. */
- for (i = 0; i < CRYPTOCOP_DESCRIPTOR_POOL_SIZE - 1; i++) {
- descr_pool[i].from_pool = 1;
- descr_pool[i].next = &descr_pool[i + 1];
- }
- descr_pool[i].from_pool = 1;
- descr_pool[i].next = NULL;
- descr_pool_free_list = &descr_pool[0];
- descr_pool_no_free = CRYPTOCOP_DESCRIPTOR_POOL_SIZE;
-
- spin_lock_init(&cryptocop_completed_jobs_lock);
- spin_lock_init(&cryptocop_job_queue_lock);
- spin_lock_init(&descr_pool_lock);
- spin_lock_init(&cryptocop_sessions_lock);
- spin_lock_init(&running_job_lock);
- spin_lock_init(&cryptocop_process_lock);
-
- cryptocop_sessions = NULL;
- next_sid = 1;
-
- cryptocop_running_job = NULL;
-
- printk("stream co-processor: init done.\n");
- return 0;
-}
-
-static void __exit exit_stream_coprocessor(void)
-{
- release_cryptocop();
- cryptocop_job_queue_close();
-}
-
-module_init(init_stream_coprocessor);
-module_exit(exit_stream_coprocessor);
-
diff --git a/arch/cris/arch-v32/drivers/iop_fw_load.c b/arch/cris/arch-v32/drivers/iop_fw_load.c
deleted file mode 100644
index 2f8ea0f7a63c..000000000000
--- a/arch/cris/arch-v32/drivers/iop_fw_load.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * Firmware loader for ETRAX FS IO-Processor
- *
- * Copyright (C) 2004 Axis Communications AB
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/firmware.h>
-
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/iop/iop_reg_space.h>
-#include <hwregs/iop/iop_mpu_macros.h>
-#include <hwregs/iop/iop_mpu_defs.h>
-#include <hwregs/iop/iop_spu_defs.h>
-#include <hwregs/iop/iop_sw_cpu_defs.h>
-
-#define IOP_TIMEOUT 100
-
-#error "This driver is broken with regard to its driver core usage."
-#error "Please contact <greg@kroah.com> for details on how to fix it properly."
-
-static struct device iop_spu_device[2] = {
- { .init_name = "iop-spu0", },
- { .init_name = "iop-spu1", },
-};
-
-static struct device iop_mpu_device = {
- .init_name = "iop-mpu",
-};
-
-static int wait_mpu_idle(void)
-{
- reg_iop_mpu_r_stat mpu_stat;
- unsigned int timeout = IOP_TIMEOUT;
-
- do {
- mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat);
- } while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0);
- if (timeout == 0) {
- printk(KERN_ERR "Timeout waiting for MPU to be idle\n");
- return -EBUSY;
- }
- return 0;
-}
-
-int iop_fw_load_spu(const unsigned char *fw_name, unsigned int spu_inst)
-{
- reg_iop_sw_cpu_rw_mc_ctrl mc_ctrl = {
- .wr_spu0_mem = regk_iop_sw_cpu_no,
- .wr_spu1_mem = regk_iop_sw_cpu_no,
- .size = 4,
- .cmd = regk_iop_sw_cpu_reg_copy,
- .keep_owner = regk_iop_sw_cpu_yes
- };
- reg_iop_spu_rw_ctrl spu_ctrl = {
- .en = regk_iop_spu_no,
- .fsm = regk_iop_spu_no,
- };
- reg_iop_sw_cpu_r_mc_stat mc_stat;
- const struct firmware *fw_entry;
- u32 *data;
- unsigned int timeout;
- int retval, i;
-
- if (spu_inst > 1)
- return -ENODEV;
-
- /* get firmware */
- retval = request_firmware(&fw_entry,
- fw_name,
- &iop_spu_device[spu_inst]);
- if (retval != 0)
- {
- printk(KERN_ERR
- "iop_load_spu: Failed to load firmware \"%s\"\n",
- fw_name);
- return retval;
- }
- data = (u32 *) fw_entry->data;
-
- /* acquire ownership of memory controller */
- switch (spu_inst) {
- case 0:
- mc_ctrl.wr_spu0_mem = regk_iop_sw_cpu_yes;
- REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl);
- break;
- case 1:
- mc_ctrl.wr_spu1_mem = regk_iop_sw_cpu_yes;
- REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl);
- break;
- }
- timeout = IOP_TIMEOUT;
- do {
- REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl);
- mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat);
- } while (mc_stat.owned_by_cpu == regk_iop_sw_cpu_no && --timeout > 0);
- if (timeout == 0) {
- printk(KERN_ERR "Timeout waiting to acquire MC\n");
- retval = -EBUSY;
- goto out;
- }
-
- /* write to SPU memory */
- for (i = 0; i < (fw_entry->size/4); i++) {
- switch (spu_inst) {
- case 0:
- REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4));
- break;
- case 1:
- REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4));
- break;
- }
- REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data);
- data++;
- }
-
- /* release ownership of memory controller */
- (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data);
-
- out:
- release_firmware(fw_entry);
- return retval;
-}
-
-int iop_fw_load_mpu(unsigned char *fw_name)
-{
- const unsigned int start_addr = 0;
- reg_iop_mpu_rw_ctrl mpu_ctrl;
- const struct firmware *fw_entry;
- u32 *data;
- int retval, i;
-
- /* get firmware */
- retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device);
- if (retval != 0)
- {
- printk(KERN_ERR
- "iop_load_spu: Failed to load firmware \"%s\"\n",
- fw_name);
- return retval;
- }
- data = (u32 *) fw_entry->data;
-
- /* disable MPU */
- mpu_ctrl.en = regk_iop_mpu_no;
- REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
- /* put start address in R0 */
- REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, 0, start_addr);
- /* write to memory by executing 'SWX i, 4, R0' for each word */
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0));
- for (i = 0; i < (fw_entry->size / 4); i++) {
- REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data);
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- data++;
- }
-
- out:
- release_firmware(fw_entry);
- return retval;
-}
-
-int iop_start_mpu(unsigned int start_addr)
-{
- reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes };
- int retval;
-
- /* disable MPU */
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT());
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- /* set PC and wait for it to bite */
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr));
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- /* make sure the MPU starts executing with interrupts disabled */
- REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI());
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- /* enable MPU */
- REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
- out:
- return retval;
-}
-
-static int __init iop_fw_load_init(void)
-{
-#if 0
- /*
- * static struct devices can not be added directly to sysfs by ignoring
- * the driver model infrastructure. To fix this properly, please use
- * the platform_bus to register these devices to be able to properly
- * use the firmware infrastructure.
- */
- device_initialize(&iop_spu_device[0]);
- kobject_set_name(&iop_spu_device[0].kobj, "iop-spu0");
- kobject_add(&iop_spu_device[0].kobj);
- device_initialize(&iop_spu_device[1]);
- kobject_set_name(&iop_spu_device[1].kobj, "iop-spu1");
- kobject_add(&iop_spu_device[1].kobj);
- device_initialize(&iop_mpu_device);
- kobject_set_name(&iop_mpu_device.kobj, "iop-mpu");
- kobject_add(&iop_mpu_device.kobj);
-#endif
- return 0;
-}
-
-static void __exit iop_fw_load_exit(void)
-{
-}
-
-module_init(iop_fw_load_init);
-module_exit(iop_fw_load_exit);
-
-MODULE_DESCRIPTION("ETRAX FS IO-Processor Firmware Loader");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(iop_fw_load_spu);
-EXPORT_SYMBOL(iop_fw_load_mpu);
-EXPORT_SYMBOL(iop_start_mpu);
diff --git a/arch/cris/arch-v32/drivers/mach-a3/Makefile b/arch/cris/arch-v32/drivers/mach-a3/Makefile
deleted file mode 100644
index 59028d0b981c..000000000000
--- a/arch/cris/arch-v32/drivers/mach-a3/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
deleted file mode 100644
index 925a98eb6d68..000000000000
--- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * arch/cris/arch-v32/drivers/nandflash.c
- *
- * Copyright (c) 2007
- *
- * Derived from drivers/mtd/nand/spia.c
- * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <arch/memmap.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/pio_defs.h>
-#include <pinmux.h>
-#include <asm/io.h>
-
-#define MANUAL_ALE_CLE_CONTROL 1
-
-#define regf_ALE a0
-#define regf_CLE a1
-#define regf_NCE ce0_n
-
-#define CLE_BIT 10
-#define ALE_BIT 11
-#define CE_BIT 12
-
-struct mtd_info_wrapper {
- struct nand_chip chip;
-};
-
-/* Bitmask for control pins */
-#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
-
-static struct mtd_info *crisv32_mtd;
-/*
- * hardware specific access to control-lines
- */
-static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- unsigned long flags;
- reg_pio_rw_dout dout;
- struct nand_chip *this = mtd_to_nand(mtd);
-
- local_irq_save(flags);
-
- /* control bits change */
- if (ctrl & NAND_CTRL_CHANGE) {
- dout = REG_RD(pio, regi_pio, rw_dout);
- dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
-
-#if !MANUAL_ALE_CLE_CONTROL
- if (ctrl & NAND_ALE) {
- /* A0 = ALE high */
- this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
- regi_pio, rw_io_access1);
- } else if (ctrl & NAND_CLE) {
- /* A1 = CLE high */
- this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
- regi_pio, rw_io_access2);
- } else {
- /* A1 = CLE and A0 = ALE low */
- this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
- regi_pio, rw_io_access0);
- }
-#else
-
- dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
- dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
-#endif
- REG_WR(pio, regi_pio, rw_dout, dout);
- }
-
- /* command to chip */
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
- local_irq_restore(flags);
-}
-
-/*
-* read device ready pin
-*/
-static int crisv32_device_ready(struct mtd_info *mtd)
-{
- reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
- return din.rdy;
-}
-
-/*
- * Main initialization routine
- */
-struct mtd_info *__init crisv32_nand_flash_probe(void)
-{
- void __iomem *read_cs;
- void __iomem *write_cs;
-
- struct mtd_info_wrapper *wrapper;
- struct nand_chip *this;
- int err = 0;
-
- reg_pio_rw_man_ctrl man_ctrl = {
- .regf_NCE = regk_pio_yes,
-#if MANUAL_ALE_CLE_CONTROL
- .regf_ALE = regk_pio_yes,
- .regf_CLE = regk_pio_yes
-#endif
- };
- reg_pio_rw_oe oe = {
- .regf_NCE = regk_pio_yes,
-#if MANUAL_ALE_CLE_CONTROL
- .regf_ALE = regk_pio_yes,
- .regf_CLE = regk_pio_yes
-#endif
- };
- reg_pio_rw_dout dout = { .regf_NCE = 1 };
-
- /* Allocate pio pins to pio */
- crisv32_pinmux_alloc_fixed(pinmux_pio);
- /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
- REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
- REG_WR(pio, regi_pio, rw_dout, dout);
- REG_WR(pio, regi_pio, rw_oe, oe);
-
- /* Allocate memory for MTD device structure and private data */
- wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
- if (!wrapper) {
- printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
- "device structure.\n");
- err = -ENOMEM;
- return NULL;
- }
-
- read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
- rw_io_access0);
-
- /* Get pointer to private data */
- this = &wrapper->chip;
- crisv32_mtd = nand_to_mtd(this);
-
- /* Set address of NAND IO lines */
- this->IO_ADDR_R = read_cs;
- this->IO_ADDR_W = write_cs;
- this->cmd_ctrl = crisv32_hwcontrol;
- this->dev_ready = crisv32_device_ready;
- /* 20 us command delay time */
- this->chip_delay = 20;
- this->ecc.mode = NAND_ECC_SOFT;
- this->ecc.algo = NAND_ECC_HAMMING;
-
- /* Enable the following for a flash based bad block table */
- /* this->bbt_options = NAND_BBT_USE_FLASH; */
-
- /* Scan to find existence of the device */
- if (nand_scan(crisv32_mtd, 1)) {
- err = -ENXIO;
- goto out_mtd;
- }
-
- return crisv32_mtd;
-
-out_mtd:
- kfree(wrapper);
- return NULL;
-}
-
diff --git a/arch/cris/arch-v32/drivers/mach-fs/Makefile b/arch/cris/arch-v32/drivers/mach-fs/Makefile
deleted file mode 100644
index 59028d0b981c..000000000000
--- a/arch/cris/arch-v32/drivers/mach-fs/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
deleted file mode 100644
index 53b56a429dde..000000000000
--- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * arch/cris/arch-v32/drivers/nandflash.c
- *
- * Copyright (c) 2004
- *
- * Derived from drivers/mtd/nand/spia.c
- * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <arch/memmap.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/gio_defs.h>
-#include <hwregs/bif_core_defs.h>
-#include <asm/io.h>
-
-#define CE_BIT 4
-#define CLE_BIT 5
-#define ALE_BIT 6
-#define BY_BIT 7
-
-struct mtd_info_wrapper {
- struct nand_chip chip;
-};
-
-/* Bitmask for control pins */
-#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
-
-/* Bitmask for mtd nand control bits */
-#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
-
-
-static struct mtd_info *crisv32_mtd;
-/*
- * hardware specific access to control-lines
- */
-static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- unsigned long flags;
- reg_gio_rw_pa_dout dout;
- struct nand_chip *this = mtd_to_nand(mtd);
-
- local_irq_save(flags);
-
- /* control bits change */
- if (ctrl & NAND_CTRL_CHANGE) {
- dout = REG_RD(gio, regi_gio, rw_pa_dout);
- dout.data &= ~PIN_BITMASK;
-
-#if (CE_BIT == 4 && NAND_NCE == 1 && \
- CLE_BIT == 5 && NAND_CLE == 2 && \
- ALE_BIT == 6 && NAND_ALE == 4)
- /* Pins in same order as control bits, but shifted.
- * Optimize for this case; works for 2.6.18 */
- dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
-#else
- /* the slow way */
- if (!(ctrl & NAND_NCE))
- dout.data |= (1 << CE_BIT);
- if (ctrl & NAND_CLE)
- dout.data |= (1 << CLE_BIT);
- if (ctrl & NAND_ALE)
- dout.data |= (1 << ALE_BIT);
-#endif
- REG_WR(gio, regi_gio, rw_pa_dout, dout);
- }
-
- /* command to chip */
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
- local_irq_restore(flags);
-}
-
-/*
-* read device ready pin
-*/
-static int crisv32_device_ready(struct mtd_info *mtd)
-{
- reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
- return ((din.data & (1 << BY_BIT)) >> BY_BIT);
-}
-
-/*
- * Main initialization routine
- */
-struct mtd_info *__init crisv32_nand_flash_probe(void)
-{
- void __iomem *read_cs;
- void __iomem *write_cs;
-
- reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
- rw_grp3_cfg);
- reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
- struct mtd_info_wrapper *wrapper;
- struct nand_chip *this;
- int err = 0;
-
- /* Allocate memory for MTD device structure and private data */
- wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
- if (!wrapper) {
- printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
- "device structure.\n");
- err = -ENOMEM;
- return NULL;
- }
-
- read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
- write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
-
- if (!read_cs || !write_cs) {
- printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
- err = -EIO;
- goto out_mtd;
- }
-
- /* Get pointer to private data */
- this = &wrapper->chip;
- crisv32_mtd = nand_to_mtd(this);
-
- pa_oe.oe |= 1 << CE_BIT;
- pa_oe.oe |= 1 << ALE_BIT;
- pa_oe.oe |= 1 << CLE_BIT;
- pa_oe.oe &= ~(1 << BY_BIT);
- REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
-
- bif_cfg.gated_csp0 = regk_bif_core_rd;
- bif_cfg.gated_csp1 = regk_bif_core_wr;
- REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
-
- /* Set address of NAND IO lines */
- this->IO_ADDR_R = read_cs;
- this->IO_ADDR_W = write_cs;
- this->cmd_ctrl = crisv32_hwcontrol;
- this->dev_ready = crisv32_device_ready;
- /* 20 us command delay time */
- this->chip_delay = 20;
- this->ecc.mode = NAND_ECC_SOFT;
- this->ecc.algo = NAND_ECC_HAMMING;
-
- /* Enable the following for a flash based bad block table */
- /* this->bbt_options = NAND_BBT_USE_FLASH; */
-
- /* Scan to find existence of the device */
- if (nand_scan(crisv32_mtd, 1)) {
- err = -ENXIO;
- goto out_ior;
- }
-
- return crisv32_mtd;
-
-out_ior:
- iounmap((void *)read_cs);
- iounmap((void *)write_cs);
-out_mtd:
- kfree(wrapper);
- return NULL;
-}
-
diff --git a/arch/cris/arch-v32/drivers/pci/Makefile b/arch/cris/arch-v32/drivers/pci/Makefile
deleted file mode 100644
index 93c8be6170b1..000000000000
--- a/arch/cris/arch-v32/drivers/pci/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for Etrax cardbus driver
-#
-
-obj-$(CONFIG_ETRAX_CARDBUS) += bios.o
diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c
deleted file mode 100644
index 6b9e6cfaa29e..000000000000
--- a/arch/cris/arch-v32/drivers/pci/bios.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <hwregs/intr_vect.h>
-
-void pcibios_set_master(struct pci_dev *dev)
-{
- u8 lat;
- pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
- printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
-}
-
-resource_size_t
-pcibios_align_resource(void *data, const struct resource *res,
- resource_size_t size, resource_size_t align)
-{
- resource_size_t start = res->start;
-
- if ((res->flags & IORESOURCE_IO) && (start & 0x300))
- start = (start + 0x3ff) & ~0x3ff;
-
- return start;
-}
-
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for(idx=0; idx<6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
-int pcibios_enable_irq(struct pci_dev *dev)
-{
- dev->irq = EXT_INTR_VECT;
- return 0;
-}
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- int err;
-
- if ((err = pcibios_enable_resources(dev, mask)) < 0)
- return err;
-
- if (!dev->msi_enabled)
- pcibios_enable_irq(dev);
- return 0;
-}
diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c
deleted file mode 100644
index 1b0ce8a8af16..000000000000
--- a/arch/cris/arch-v32/drivers/sync_serial.c
+++ /dev/null
@@ -1,1715 +0,0 @@
-/*
- * Simple synchronous serial port driver for ETRAX FS and ARTPEC-3.
- *
- * Copyright (c) 2005, 2008 Axis Communications AB
- * Author: Mikael Starvik
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/major.h>
-#include <linux/sched/signal.h>
-#include <linux/mutex.h>
-#include <linux/interrupt.h>
-#include <linux/poll.h>
-#include <linux/fs.h>
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/wait.h>
-
-#include <asm/io.h>
-#include <mach/dma.h>
-#include <pinmux.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/sser_defs.h>
-#include <hwregs/timer_defs.h>
-#include <hwregs/dma_defs.h>
-#include <hwregs/dma.h>
-#include <hwregs/intr_vect_defs.h>
-#include <hwregs/intr_vect.h>
-#include <hwregs/reg_map.h>
-#include <asm/sync_serial.h>
-
-
-/* The receiver is a bit tricky because of the continuous stream of data.*/
-/* */
-/* Three DMA descriptors are linked together. Each DMA descriptor is */
-/* responsible for port->bufchunk of a common buffer. */
-/* */
-/* +---------------------------------------------+ */
-/* | +----------+ +----------+ +----------+ | */
-/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
-/* +----------+ +----------+ +----------+ */
-/* | | | */
-/* v v v */
-/* +-------------------------------------+ */
-/* | BUFFER | */
-/* +-------------------------------------+ */
-/* |<- data_avail ->| */
-/* readp writep */
-/* */
-/* If the application keeps up the pace readp will be right after writep.*/
-/* If the application can't keep the pace we have to throw away data. */
-/* The idea is that readp should be ready with the data pointed out by */
-/* Descr[i] when the DMA has filled in Descr[i+1]. */
-/* Otherwise we will discard */
-/* the rest of the data pointed out by Descr1 and set readp to the start */
-/* of Descr2 */
-
-/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
-/* words can be handled */
-#define IN_DESCR_SIZE SSP_INPUT_CHUNK_SIZE
-#define NBR_IN_DESCR (8*6)
-#define IN_BUFFER_SIZE (IN_DESCR_SIZE * NBR_IN_DESCR)
-
-#define NBR_OUT_DESCR 8
-#define OUT_BUFFER_SIZE (1024 * NBR_OUT_DESCR)
-
-#define DEFAULT_FRAME_RATE 0
-#define DEFAULT_WORD_RATE 7
-
-/* To be removed when we move to pure udev. */
-#define SYNC_SERIAL_MAJOR 125
-
-/* NOTE: Enabling some debug will likely cause overrun or underrun,
- * especially if manual mode is used.
- */
-#define DEBUG(x)
-#define DEBUGREAD(x)
-#define DEBUGWRITE(x)
-#define DEBUGPOLL(x)
-#define DEBUGRXINT(x)
-#define DEBUGTXINT(x)
-#define DEBUGTRDMA(x)
-#define DEBUGOUTBUF(x)
-
-enum syncser_irq_setup {
- no_irq_setup = 0,
- dma_irq_setup = 1,
- manual_irq_setup = 2,
-};
-
-struct sync_port {
- unsigned long regi_sser;
- unsigned long regi_dmain;
- unsigned long regi_dmaout;
-
- /* Interrupt vectors. */
- unsigned long dma_in_intr_vect; /* Used for DMA in. */
- unsigned long dma_out_intr_vect; /* Used for DMA out. */
- unsigned long syncser_intr_vect; /* Used when no DMA. */
-
- /* DMA number for in and out. */
- unsigned int dma_in_nbr;
- unsigned int dma_out_nbr;
-
- /* DMA owner. */
- enum dma_owner req_dma;
-
- char started; /* 1 if port has been started */
- char port_nbr; /* Port 0 or 1 */
- char busy; /* 1 if port is busy */
-
- char enabled; /* 1 if port is enabled */
- char use_dma; /* 1 if port uses dma */
- char tr_running;
-
- enum syncser_irq_setup init_irqs;
- int output;
- int input;
-
- /* Next byte to be read by application */
- unsigned char *readp;
- /* Next byte to be written by etrax */
- unsigned char *writep;
-
- unsigned int in_buffer_size;
- unsigned int in_buffer_len;
- unsigned int inbufchunk;
- /* Data buffers for in and output. */
- unsigned char out_buffer[OUT_BUFFER_SIZE] __aligned(32);
- unsigned char in_buffer[IN_BUFFER_SIZE] __aligned(32);
- unsigned char flip[IN_BUFFER_SIZE] __aligned(32);
- struct timespec timestamp[NBR_IN_DESCR];
- struct dma_descr_data *next_rx_desc;
- struct dma_descr_data *prev_rx_desc;
-
- struct timeval last_timestamp;
- int read_ts_idx;
- int write_ts_idx;
-
- /* Pointer to the first available descriptor in the ring,
- * unless active_tr_descr == catch_tr_descr and a dma
- * transfer is active */
- struct dma_descr_data *active_tr_descr;
-
- /* Pointer to the first allocated descriptor in the ring */
- struct dma_descr_data *catch_tr_descr;
-
- /* Pointer to the descriptor with the current end-of-list */
- struct dma_descr_data *prev_tr_descr;
- int full;
-
- /* Pointer to the first byte being read by DMA
- * or current position in out_buffer if not using DMA. */
- unsigned char *out_rd_ptr;
-
- /* Number of bytes currently locked for being read by DMA */
- int out_buf_count;
-
- dma_descr_context in_context __aligned(32);
- dma_descr_context out_context __aligned(32);
- dma_descr_data in_descr[NBR_IN_DESCR] __aligned(16);
- dma_descr_data out_descr[NBR_OUT_DESCR] __aligned(16);
-
- wait_queue_head_t out_wait_q;
- wait_queue_head_t in_wait_q;
-
- spinlock_t lock;
-};
-
-static DEFINE_MUTEX(sync_serial_mutex);
-static int etrax_sync_serial_init(void);
-static void initialize_port(int portnbr);
-static inline int sync_data_avail(struct sync_port *port);
-
-static int sync_serial_open(struct inode *, struct file *);
-static int sync_serial_release(struct inode *, struct file *);
-static __poll_t sync_serial_poll(struct file *filp, poll_table *wait);
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg);
-static int sync_serial_ioctl_unlocked(struct file *file,
- unsigned int cmd, unsigned long arg);
-static ssize_t sync_serial_write(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos);
-static ssize_t sync_serial_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos);
-
-#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
- (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
-#define SYNC_SER_DMA
-#else
-#define SYNC_SER_MANUAL
-#endif
-
-#ifdef SYNC_SER_DMA
-static void start_dma_out(struct sync_port *port, const char *data, int count);
-static void start_dma_in(struct sync_port *port);
-static irqreturn_t tr_interrupt(int irq, void *dev_id);
-static irqreturn_t rx_interrupt(int irq, void *dev_id);
-#endif
-#ifdef SYNC_SER_MANUAL
-static void send_word(struct sync_port *port);
-static irqreturn_t manual_interrupt(int irq, void *dev_id);
-#endif
-
-#define artpec_pinmux_alloc_fixed crisv32_pinmux_alloc_fixed
-#define artpec_request_dma crisv32_request_dma
-#define artpec_free_dma crisv32_free_dma
-
-#ifdef CONFIG_ETRAXFS
-/* ETRAX FS */
-#define DMA_OUT_NBR0 SYNC_SER0_TX_DMA_NBR
-#define DMA_IN_NBR0 SYNC_SER0_RX_DMA_NBR
-#define DMA_OUT_NBR1 SYNC_SER1_TX_DMA_NBR
-#define DMA_IN_NBR1 SYNC_SER1_RX_DMA_NBR
-#define PINMUX_SSER0 pinmux_sser0
-#define PINMUX_SSER1 pinmux_sser1
-#define SYNCSER_INST0 regi_sser0
-#define SYNCSER_INST1 regi_sser1
-#define SYNCSER_INTR_VECT0 SSER0_INTR_VECT
-#define SYNCSER_INTR_VECT1 SSER1_INTR_VECT
-#define OUT_DMA_INST0 regi_dma4
-#define IN_DMA_INST0 regi_dma5
-#define DMA_OUT_INTR_VECT0 DMA4_INTR_VECT
-#define DMA_OUT_INTR_VECT1 DMA7_INTR_VECT
-#define DMA_IN_INTR_VECT0 DMA5_INTR_VECT
-#define DMA_IN_INTR_VECT1 DMA6_INTR_VECT
-#define REQ_DMA_SYNCSER0 dma_sser0
-#define REQ_DMA_SYNCSER1 dma_sser1
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
-#define PORT1_DMA 1
-#else
-#define PORT1_DMA 0
-#endif
-#elif defined(CONFIG_CRIS_MACH_ARTPEC3)
-/* ARTPEC-3 */
-#define DMA_OUT_NBR0 SYNC_SER_TX_DMA_NBR
-#define DMA_IN_NBR0 SYNC_SER_RX_DMA_NBR
-#define PINMUX_SSER0 pinmux_sser
-#define SYNCSER_INST0 regi_sser
-#define SYNCSER_INTR_VECT0 SSER_INTR_VECT
-#define OUT_DMA_INST0 regi_dma6
-#define IN_DMA_INST0 regi_dma7
-#define DMA_OUT_INTR_VECT0 DMA6_INTR_VECT
-#define DMA_IN_INTR_VECT0 DMA7_INTR_VECT
-#define REQ_DMA_SYNCSER0 dma_sser
-#define REQ_DMA_SYNCSER1 dma_sser
-#endif
-
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
-#define PORT0_DMA 1
-#else
-#define PORT0_DMA 0
-#endif
-
-/* The ports */
-static struct sync_port ports[] = {
- {
- .regi_sser = SYNCSER_INST0,
- .regi_dmaout = OUT_DMA_INST0,
- .regi_dmain = IN_DMA_INST0,
- .use_dma = PORT0_DMA,
- .dma_in_intr_vect = DMA_IN_INTR_VECT0,
- .dma_out_intr_vect = DMA_OUT_INTR_VECT0,
- .dma_in_nbr = DMA_IN_NBR0,
- .dma_out_nbr = DMA_OUT_NBR0,
- .req_dma = REQ_DMA_SYNCSER0,
- .syncser_intr_vect = SYNCSER_INTR_VECT0,
- },
-#ifdef CONFIG_ETRAXFS
- {
- .regi_sser = SYNCSER_INST1,
- .regi_dmaout = regi_dma6,
- .regi_dmain = regi_dma7,
- .use_dma = PORT1_DMA,
- .dma_in_intr_vect = DMA_IN_INTR_VECT1,
- .dma_out_intr_vect = DMA_OUT_INTR_VECT1,
- .dma_in_nbr = DMA_IN_NBR1,
- .dma_out_nbr = DMA_OUT_NBR1,
- .req_dma = REQ_DMA_SYNCSER1,
- .syncser_intr_vect = SYNCSER_INTR_VECT1,
- },
-#endif
-};
-
-#define NBR_PORTS ARRAY_SIZE(ports)
-
-static const struct file_operations syncser_fops = {
- .owner = THIS_MODULE,
- .write = sync_serial_write,
- .read = sync_serial_read,
- .poll = sync_serial_poll,
- .unlocked_ioctl = sync_serial_ioctl,
- .open = sync_serial_open,
- .release = sync_serial_release,
- .llseek = noop_llseek,
-};
-
-static dev_t syncser_first;
-static int minor_count = NBR_PORTS;
-#define SYNCSER_NAME "syncser"
-static struct cdev *syncser_cdev;
-static struct class *syncser_class;
-
-static void sync_serial_start_port(struct sync_port *port)
-{
- reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- reg_sser_rw_tr_cfg tr_cfg =
- REG_RD(sser, port->regi_sser, rw_tr_cfg);
- reg_sser_rw_rec_cfg rec_cfg =
- REG_RD(sser, port->regi_sser, rw_rec_cfg);
- cfg.en = regk_sser_yes;
- tr_cfg.tr_en = regk_sser_yes;
- rec_cfg.rec_en = regk_sser_yes;
- REG_WR(sser, port->regi_sser, rw_cfg, cfg);
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
- port->started = 1;
-}
-
-static void __init initialize_port(int portnbr)
-{
- struct sync_port *port = &ports[portnbr];
- reg_sser_rw_cfg cfg = { 0 };
- reg_sser_rw_frm_cfg frm_cfg = { 0 };
- reg_sser_rw_tr_cfg tr_cfg = { 0 };
- reg_sser_rw_rec_cfg rec_cfg = { 0 };
-
- DEBUG(pr_info("Init sync serial port %d\n", portnbr));
-
- port->port_nbr = portnbr;
- port->init_irqs = no_irq_setup;
-
- port->out_rd_ptr = port->out_buffer;
- port->out_buf_count = 0;
-
- port->output = 1;
- port->input = 0;
-
- port->readp = port->flip;
- port->writep = port->flip;
- port->in_buffer_size = IN_BUFFER_SIZE;
- port->in_buffer_len = 0;
- port->inbufchunk = IN_DESCR_SIZE;
-
- port->read_ts_idx = 0;
- port->write_ts_idx = 0;
-
- init_waitqueue_head(&port->out_wait_q);
- init_waitqueue_head(&port->in_wait_q);
-
- spin_lock_init(&port->lock);
-
- cfg.out_clk_src = regk_sser_intern_clk;
- cfg.out_clk_pol = regk_sser_pos;
- cfg.clk_od_mode = regk_sser_no;
- cfg.clk_dir = regk_sser_out;
- cfg.gate_clk = regk_sser_no;
- cfg.base_freq = regk_sser_f29_493;
- cfg.clk_div = 256;
- REG_WR(sser, port->regi_sser, rw_cfg, cfg);
-
- frm_cfg.wordrate = DEFAULT_WORD_RATE;
- frm_cfg.type = regk_sser_edge;
- frm_cfg.frame_pin_dir = regk_sser_out;
- frm_cfg.frame_pin_use = regk_sser_frm;
- frm_cfg.status_pin_dir = regk_sser_in;
- frm_cfg.status_pin_use = regk_sser_hold;
- frm_cfg.out_on = regk_sser_tr;
- frm_cfg.tr_delay = 1;
- REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
-
- tr_cfg.urun_stop = regk_sser_no;
- tr_cfg.sample_size = 7;
- tr_cfg.sh_dir = regk_sser_msbfirst;
- tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
-#if 0
- tr_cfg.rate_ctrl = regk_sser_bulk;
- tr_cfg.data_pin_use = regk_sser_dout;
-#else
- tr_cfg.rate_ctrl = regk_sser_iso;
- tr_cfg.data_pin_use = regk_sser_dout;
-#endif
- tr_cfg.bulk_wspace = 1;
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
-
- rec_cfg.sample_size = 7;
- rec_cfg.sh_dir = regk_sser_msbfirst;
- rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
- rec_cfg.fifo_thr = regk_sser_inf;
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
-
-#ifdef SYNC_SER_DMA
- {
- int i;
- /* Setup the descriptor ring for dma out/transmit. */
- for (i = 0; i < NBR_OUT_DESCR; i++) {
- dma_descr_data *descr = &port->out_descr[i];
- descr->wait = 0;
- descr->intr = 1;
- descr->eol = 0;
- descr->out_eop = 0;
- descr->next =
- (dma_descr_data *)virt_to_phys(&descr[i+1]);
- }
- }
-
- /* Create a ring from the list. */
- port->out_descr[NBR_OUT_DESCR-1].next =
- (dma_descr_data *)virt_to_phys(&port->out_descr[0]);
-
- /* Setup context for traversing the ring. */
- port->active_tr_descr = &port->out_descr[0];
- port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1];
- port->catch_tr_descr = &port->out_descr[0];
-#endif
-}
-
-static inline int sync_data_avail(struct sync_port *port)
-{
- return port->in_buffer_len;
-}
-
-static int sync_serial_open(struct inode *inode, struct file *file)
-{
- int ret = 0;
- int dev = iminor(inode);
- struct sync_port *port;
-#ifdef SYNC_SER_DMA
- reg_dma_rw_cfg cfg = { .en = regk_dma_yes };
- reg_dma_rw_intr_mask intr_mask = { .data = regk_dma_yes };
-#endif
-
- DEBUG(pr_debug("Open sync serial port %d\n", dev));
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
- /* Allow open this device twice (assuming one reader and one writer) */
- if (port->busy == 2) {
- DEBUG(pr_info("syncser%d is busy\n", dev));
- return -EBUSY;
- }
-
- mutex_lock(&sync_serial_mutex);
-
- /* Clear any stale date left in the flip buffer */
- port->readp = port->writep = port->flip;
- port->in_buffer_len = 0;
- port->read_ts_idx = 0;
- port->write_ts_idx = 0;
-
- if (port->init_irqs != no_irq_setup) {
- /* Init only on first call. */
- port->busy++;
- mutex_unlock(&sync_serial_mutex);
- return 0;
- }
- if (port->use_dma) {
-#ifdef SYNC_SER_DMA
- const char *tmp;
- DEBUG(pr_info("Using DMA for syncser%d\n", dev));
-
- tmp = dev == 0 ? "syncser0 tx" : "syncser1 tx";
- if (request_irq(port->dma_out_intr_vect, tr_interrupt, 0,
- tmp, port)) {
- pr_err("Can't alloc syncser%d TX IRQ", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- if (artpec_request_dma(port->dma_out_nbr, tmp,
- DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) {
- free_irq(port->dma_out_intr_vect, port);
- pr_err("Can't alloc syncser%d TX DMA", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- tmp = dev == 0 ? "syncser0 rx" : "syncser1 rx";
- if (request_irq(port->dma_in_intr_vect, rx_interrupt, 0,
- tmp, port)) {
- artpec_free_dma(port->dma_out_nbr);
- free_irq(port->dma_out_intr_vect, port);
- pr_err("Can't alloc syncser%d RX IRQ", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- if (artpec_request_dma(port->dma_in_nbr, tmp,
- DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) {
- artpec_free_dma(port->dma_out_nbr);
- free_irq(port->dma_out_intr_vect, port);
- free_irq(port->dma_in_intr_vect, port);
- pr_err("Can't alloc syncser%d RX DMA", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- /* Enable DMAs */
- REG_WR(dma, port->regi_dmain, rw_cfg, cfg);
- REG_WR(dma, port->regi_dmaout, rw_cfg, cfg);
- /* Enable DMA IRQs */
- REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask);
- REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask);
- /* Set up wordsize = 1 for DMAs. */
- DMA_WR_CMD(port->regi_dmain, regk_dma_set_w_size1);
- DMA_WR_CMD(port->regi_dmaout, regk_dma_set_w_size1);
-
- start_dma_in(port);
- port->init_irqs = dma_irq_setup;
-#endif
- } else { /* !port->use_dma */
-#ifdef SYNC_SER_MANUAL
- const char *tmp = dev == 0 ? "syncser0 manual irq" :
- "syncser1 manual irq";
- if (request_irq(port->syncser_intr_vect, manual_interrupt,
- 0, tmp, port)) {
- pr_err("Can't alloc syncser%d manual irq",
- dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- port->init_irqs = manual_irq_setup;
-#else
- panic("sync_serial: Manual mode not supported\n");
-#endif /* SYNC_SER_MANUAL */
- }
- port->busy++;
- ret = 0;
-
-unlock_and_exit:
- mutex_unlock(&sync_serial_mutex);
- return ret;
-}
-
-static int sync_serial_release(struct inode *inode, struct file *file)
-{
- int dev = iminor(inode);
- struct sync_port *port;
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
- if (port->busy)
- port->busy--;
- if (!port->busy)
- /* XXX */;
- return 0;
-}
-
-static __poll_t sync_serial_poll(struct file *file, poll_table *wait)
-{
- int dev = iminor(file_inode(file));
- __poll_t mask = 0;
- struct sync_port *port;
- DEBUGPOLL(
- static __poll_t prev_mask;
- );
-
- port = &ports[dev];
-
- if (!port->started)
- sync_serial_start_port(port);
-
- poll_wait(file, &port->out_wait_q, wait);
- poll_wait(file, &port->in_wait_q, wait);
-
- /* No active transfer, descriptors are available */
- if (port->output && !port->tr_running)
- mask |= EPOLLOUT | EPOLLWRNORM;
-
- /* Descriptor and buffer space available. */
- if (port->output &&
- port->active_tr_descr != port->catch_tr_descr &&
- port->out_buf_count < OUT_BUFFER_SIZE)
- mask |= EPOLLOUT | EPOLLWRNORM;
-
- /* At least an inbufchunk of data */
- if (port->input && sync_data_avail(port) >= port->inbufchunk)
- mask |= EPOLLIN | EPOLLRDNORM;
-
- DEBUGPOLL(
- if (mask != prev_mask)
- pr_info("sync_serial_poll: mask 0x%08X %s %s\n",
- mask,
- mask & EPOLLOUT ? "POLLOUT" : "",
- mask & EPOLLIN ? "POLLIN" : "");
- prev_mask = mask;
- );
- return mask;
-}
-
-static ssize_t __sync_serial_read(struct file *file,
- char __user *buf,
- size_t count,
- loff_t *ppos,
- struct timespec *ts)
-{
- unsigned long flags;
- int dev = MINOR(file_inode(file)->i_rdev);
- int avail;
- struct sync_port *port;
- unsigned char *start;
- unsigned char *end;
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- if (!port->started)
- sync_serial_start_port(port);
-
- /* Calculate number of available bytes */
- /* Save pointers to avoid that they are modified by interrupt */
- spin_lock_irqsave(&port->lock, flags);
- start = port->readp;
- end = port->writep;
- spin_unlock_irqrestore(&port->lock, flags);
-
- while ((start == end) && !port->in_buffer_len) {
- if (file->f_flags & O_NONBLOCK)
- return -EAGAIN;
-
- wait_event_interruptible(port->in_wait_q,
- !(start == end && !port->full));
-
- if (signal_pending(current))
- return -EINTR;
-
- spin_lock_irqsave(&port->lock, flags);
- start = port->readp;
- end = port->writep;
- spin_unlock_irqrestore(&port->lock, flags);
- }
-
- DEBUGREAD(pr_info("R%d c %d ri %u wi %u /%u\n",
- dev, count,
- start - port->flip, end - port->flip,
- port->in_buffer_size));
-
- /* Lazy read, never return wrapped data. */
- if (end > start)
- avail = end - start;
- else
- avail = port->flip + port->in_buffer_size - start;
-
- count = count > avail ? avail : count;
- if (copy_to_user(buf, start, count))
- return -EFAULT;
-
- /* If timestamp requested, find timestamp of first returned byte
- * and copy it.
- * N.B: Applications that request timstamps MUST read data in
- * chunks that are multiples of IN_DESCR_SIZE.
- * Otherwise the timestamps will not be aligned to the data read.
- */
- if (ts != NULL) {
- int idx = port->read_ts_idx;
- memcpy(ts, &port->timestamp[idx], sizeof(struct timespec));
- port->read_ts_idx += count / IN_DESCR_SIZE;
- if (port->read_ts_idx >= NBR_IN_DESCR)
- port->read_ts_idx = 0;
- }
-
- spin_lock_irqsave(&port->lock, flags);
- port->readp += count;
- /* Check for wrap */
- if (port->readp >= port->flip + port->in_buffer_size)
- port->readp = port->flip;
- port->in_buffer_len -= count;
- port->full = 0;
- spin_unlock_irqrestore(&port->lock, flags);
-
- DEBUGREAD(pr_info("r %d\n", count));
-
- return count;
-}
-
-static ssize_t sync_serial_input(struct file *file, unsigned long arg)
-{
- struct ssp_request req;
- int count;
- int ret;
-
- /* Copy the request structure from user-mode. */
- ret = copy_from_user(&req, (struct ssp_request __user *)arg,
- sizeof(struct ssp_request));
-
- if (ret) {
- DEBUG(pr_info("sync_serial_input copy from user failed\n"));
- return -EFAULT;
- }
-
- /* To get the timestamps aligned, make sure that 'len'
- * is a multiple of IN_DESCR_SIZE.
- */
- if ((req.len % IN_DESCR_SIZE) != 0) {
- DEBUG(pr_info("sync_serial: req.len %x, IN_DESCR_SIZE %x\n",
- req.len, IN_DESCR_SIZE));
- return -EFAULT;
- }
-
- /* Do the actual read. */
- /* Note that req.buf is actually a pointer to user space. */
- count = __sync_serial_read(file, req.buf, req.len,
- NULL, &req.ts);
-
- if (count < 0) {
- DEBUG(pr_info("sync_serial_input read failed\n"));
- return count;
- }
-
- /* Copy the request back to user-mode. */
- ret = copy_to_user((struct ssp_request __user *)arg, &req,
- sizeof(struct ssp_request));
-
- if (ret) {
- DEBUG(pr_info("syncser input copy2user failed\n"));
- return -EFAULT;
- }
-
- /* Return the number of bytes read. */
- return count;
-}
-
-
-static int sync_serial_ioctl_unlocked(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int return_val = 0;
- int dma_w_size = regk_dma_set_w_size1;
- int dev = iminor(file_inode(file));
- struct sync_port *port;
- reg_sser_rw_tr_cfg tr_cfg;
- reg_sser_rw_rec_cfg rec_cfg;
- reg_sser_rw_frm_cfg frm_cfg;
- reg_sser_rw_cfg gen_cfg;
- reg_sser_rw_intr_mask intr_mask;
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -1;
- }
-
- if (cmd == SSP_INPUT)
- return sync_serial_input(file, arg);
-
- port = &ports[dev];
- spin_lock_irq(&port->lock);
-
- tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
- rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
- frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg);
- gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
-
- switch (cmd) {
- case SSP_SPEED:
- if (GET_SPEED(arg) == CODEC) {
- unsigned int freq;
-
- gen_cfg.base_freq = regk_sser_f32;
-
- /* Clock divider will internally be
- * gen_cfg.clk_div + 1.
- */
-
- freq = GET_FREQ(arg);
- switch (freq) {
- case FREQ_32kHz:
- case FREQ_64kHz:
- case FREQ_128kHz:
- case FREQ_256kHz:
- gen_cfg.clk_div = 125 *
- (1 << (freq - FREQ_256kHz)) - 1;
- break;
- case FREQ_512kHz:
- gen_cfg.clk_div = 62;
- break;
- case FREQ_1MHz:
- case FREQ_2MHz:
- case FREQ_4MHz:
- gen_cfg.clk_div = 8 * (1 << freq) - 1;
- break;
- }
- } else if (GET_SPEED(arg) == CODEC_f32768) {
- gen_cfg.base_freq = regk_sser_f32_768;
- switch (GET_FREQ(arg)) {
- case FREQ_4096kHz:
- gen_cfg.clk_div = 7;
- break;
- default:
- spin_unlock_irq(&port->lock);
- return -EINVAL;
- }
- } else {
- gen_cfg.base_freq = regk_sser_f29_493;
- switch (GET_SPEED(arg)) {
- case SSP150:
- gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
- break;
- case SSP300:
- gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
- break;
- case SSP600:
- gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
- break;
- case SSP1200:
- gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
- break;
- case SSP2400:
- gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
- break;
- case SSP4800:
- gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
- break;
- case SSP9600:
- gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
- break;
- case SSP19200:
- gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
- break;
- case SSP28800:
- gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
- break;
- case SSP57600:
- gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
- break;
- case SSP115200:
- gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
- break;
- case SSP230400:
- gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
- break;
- case SSP460800:
- gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
- break;
- case SSP921600:
- gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
- break;
- case SSP3125000:
- gen_cfg.base_freq = regk_sser_f100;
- gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
- break;
-
- }
- }
- frm_cfg.wordrate = GET_WORD_RATE(arg);
-
- break;
- case SSP_MODE:
- switch (arg) {
- case MASTER_OUTPUT:
- port->output = 1;
- port->input = 0;
- frm_cfg.out_on = regk_sser_tr;
- frm_cfg.frame_pin_dir = regk_sser_out;
- gen_cfg.clk_dir = regk_sser_out;
- break;
- case SLAVE_OUTPUT:
- port->output = 1;
- port->input = 0;
- frm_cfg.frame_pin_dir = regk_sser_in;
- gen_cfg.clk_dir = regk_sser_in;
- break;
- case MASTER_INPUT:
- port->output = 0;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_out;
- frm_cfg.out_on = regk_sser_intern_tb;
- gen_cfg.clk_dir = regk_sser_out;
- break;
- case SLAVE_INPUT:
- port->output = 0;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_in;
- gen_cfg.clk_dir = regk_sser_in;
- break;
- case MASTER_BIDIR:
- port->output = 1;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_out;
- frm_cfg.out_on = regk_sser_intern_tb;
- gen_cfg.clk_dir = regk_sser_out;
- break;
- case SLAVE_BIDIR:
- port->output = 1;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_in;
- gen_cfg.clk_dir = regk_sser_in;
- break;
- default:
- spin_unlock_irq(&port->lock);
- return -EINVAL;
- }
- if (!port->use_dma || arg == MASTER_OUTPUT ||
- arg == SLAVE_OUTPUT)
- intr_mask.rdav = regk_sser_yes;
- break;
- case SSP_FRAME_SYNC:
- if (arg & NORMAL_SYNC) {
- frm_cfg.rec_delay = 1;
- frm_cfg.tr_delay = 1;
- } else if (arg & EARLY_SYNC)
- frm_cfg.rec_delay = frm_cfg.tr_delay = 0;
- else if (arg & LATE_SYNC) {
- frm_cfg.tr_delay = 2;
- frm_cfg.rec_delay = 2;
- } else if (arg & SECOND_WORD_SYNC) {
- frm_cfg.rec_delay = 7;
- frm_cfg.tr_delay = 1;
- }
-
- tr_cfg.bulk_wspace = frm_cfg.tr_delay;
- frm_cfg.early_wend = regk_sser_yes;
- if (arg & BIT_SYNC)
- frm_cfg.type = regk_sser_edge;
- else if (arg & WORD_SYNC)
- frm_cfg.type = regk_sser_level;
- else if (arg & EXTENDED_SYNC)
- frm_cfg.early_wend = regk_sser_no;
-
- if (arg & SYNC_ON)
- frm_cfg.frame_pin_use = regk_sser_frm;
- else if (arg & SYNC_OFF)
- frm_cfg.frame_pin_use = regk_sser_gio0;
-
- dma_w_size = regk_dma_set_w_size2;
- if (arg & WORD_SIZE_8) {
- rec_cfg.sample_size = tr_cfg.sample_size = 7;
- dma_w_size = regk_dma_set_w_size1;
- } else if (arg & WORD_SIZE_12)
- rec_cfg.sample_size = tr_cfg.sample_size = 11;
- else if (arg & WORD_SIZE_16)
- rec_cfg.sample_size = tr_cfg.sample_size = 15;
- else if (arg & WORD_SIZE_24)
- rec_cfg.sample_size = tr_cfg.sample_size = 23;
- else if (arg & WORD_SIZE_32)
- rec_cfg.sample_size = tr_cfg.sample_size = 31;
-
- if (arg & BIT_ORDER_MSB)
- rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
- else if (arg & BIT_ORDER_LSB)
- rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst;
-
- if (arg & FLOW_CONTROL_ENABLE) {
- frm_cfg.status_pin_use = regk_sser_frm;
- rec_cfg.fifo_thr = regk_sser_thr16;
- } else if (arg & FLOW_CONTROL_DISABLE) {
- frm_cfg.status_pin_use = regk_sser_gio0;
- rec_cfg.fifo_thr = regk_sser_inf;
- }
-
- if (arg & CLOCK_NOT_GATED)
- gen_cfg.gate_clk = regk_sser_no;
- else if (arg & CLOCK_GATED)
- gen_cfg.gate_clk = regk_sser_yes;
-
- break;
- case SSP_IPOLARITY:
- /* NOTE!! negedge is considered NORMAL */
- if (arg & CLOCK_NORMAL)
- rec_cfg.clk_pol = regk_sser_neg;
- else if (arg & CLOCK_INVERT)
- rec_cfg.clk_pol = regk_sser_pos;
-
- if (arg & FRAME_NORMAL)
- frm_cfg.level = regk_sser_pos_hi;
- else if (arg & FRAME_INVERT)
- frm_cfg.level = regk_sser_neg_lo;
-
- if (arg & STATUS_NORMAL)
- gen_cfg.hold_pol = regk_sser_pos;
- else if (arg & STATUS_INVERT)
- gen_cfg.hold_pol = regk_sser_neg;
- break;
- case SSP_OPOLARITY:
- if (arg & CLOCK_NORMAL)
- gen_cfg.out_clk_pol = regk_sser_pos;
- else if (arg & CLOCK_INVERT)
- gen_cfg.out_clk_pol = regk_sser_neg;
-
- if (arg & FRAME_NORMAL)
- frm_cfg.level = regk_sser_pos_hi;
- else if (arg & FRAME_INVERT)
- frm_cfg.level = regk_sser_neg_lo;
-
- if (arg & STATUS_NORMAL)
- gen_cfg.hold_pol = regk_sser_pos;
- else if (arg & STATUS_INVERT)
- gen_cfg.hold_pol = regk_sser_neg;
- break;
- case SSP_SPI:
- rec_cfg.fifo_thr = regk_sser_inf;
- rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
- rec_cfg.sample_size = tr_cfg.sample_size = 7;
- frm_cfg.frame_pin_use = regk_sser_frm;
- frm_cfg.type = regk_sser_level;
- frm_cfg.tr_delay = 1;
- frm_cfg.level = regk_sser_neg_lo;
- if (arg & SPI_SLAVE) {
- rec_cfg.clk_pol = regk_sser_neg;
- gen_cfg.clk_dir = regk_sser_in;
- port->input = 1;
- port->output = 0;
- } else {
- gen_cfg.out_clk_pol = regk_sser_pos;
- port->input = 0;
- port->output = 1;
- gen_cfg.clk_dir = regk_sser_out;
- }
- break;
- case SSP_INBUFCHUNK:
- break;
- default:
- return_val = -1;
- }
-
-
- if (port->started) {
- rec_cfg.rec_en = port->input;
- gen_cfg.en = (port->output | port->input);
- }
-
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
- REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
- REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
- REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
-
-
- if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 |
- WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) {
- int en = gen_cfg.en;
- gen_cfg.en = 0;
- REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
- /* ##### Should DMA be stoped before we change dma size? */
- DMA_WR_CMD(port->regi_dmain, dma_w_size);
- DMA_WR_CMD(port->regi_dmaout, dma_w_size);
- gen_cfg.en = en;
- REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
- }
-
- spin_unlock_irq(&port->lock);
- return return_val;
-}
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- long ret;
-
- mutex_lock(&sync_serial_mutex);
- ret = sync_serial_ioctl_unlocked(file, cmd, arg);
- mutex_unlock(&sync_serial_mutex);
-
- return ret;
-}
-
-/* NOTE: sync_serial_write does not support concurrency */
-static ssize_t sync_serial_write(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- int dev = iminor(file_inode(file));
- DECLARE_WAITQUEUE(wait, current);
- struct sync_port *port;
- int trunc_count;
- unsigned long flags;
- int bytes_free;
- int out_buf_count;
-
- unsigned char *rd_ptr; /* First allocated byte in the buffer */
- unsigned char *wr_ptr; /* First free byte in the buffer */
- unsigned char *buf_stop_ptr; /* Last byte + 1 */
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- /* |<- OUT_BUFFER_SIZE ->|
- * |<- out_buf_count ->|
- * |<- trunc_count ->| ...->|
- * ______________________________________________________
- * | free | data | free |
- * |_________|___________________|________________________|
- * ^ rd_ptr ^ wr_ptr
- */
- DEBUGWRITE(pr_info("W d%d c %u a: %p c: %p\n",
- port->port_nbr, count, port->active_tr_descr,
- port->catch_tr_descr));
-
- /* Read variables that may be updated by interrupts */
- spin_lock_irqsave(&port->lock, flags);
- rd_ptr = port->out_rd_ptr;
- out_buf_count = port->out_buf_count;
- spin_unlock_irqrestore(&port->lock, flags);
-
- /* Check if resources are available */
- if (port->tr_running &&
- ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) ||
- out_buf_count >= OUT_BUFFER_SIZE)) {
- DEBUGWRITE(pr_info("sser%d full\n", dev));
- return -EAGAIN;
- }
-
- buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE;
-
- /* Determine pointer to the first free byte, before copying. */
- wr_ptr = rd_ptr + out_buf_count;
- if (wr_ptr >= buf_stop_ptr)
- wr_ptr -= OUT_BUFFER_SIZE;
-
- /* If we wrap the ring buffer, let the user space program handle it by
- * truncating the data. This could be more elegant, small buffer
- * fragments may occur.
- */
- bytes_free = OUT_BUFFER_SIZE - out_buf_count;
- if (wr_ptr + bytes_free > buf_stop_ptr)
- bytes_free = buf_stop_ptr - wr_ptr;
- trunc_count = (count < bytes_free) ? count : bytes_free;
-
- if (copy_from_user(wr_ptr, buf, trunc_count))
- return -EFAULT;
-
- DEBUGOUTBUF(pr_info("%-4d + %-4d = %-4d %p %p %p\n",
- out_buf_count, trunc_count,
- port->out_buf_count, port->out_buffer,
- wr_ptr, buf_stop_ptr));
-
- /* Make sure transmitter/receiver is running */
- if (!port->started) {
- reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- reg_sser_rw_rec_cfg rec_cfg =
- REG_RD(sser, port->regi_sser, rw_rec_cfg);
- cfg.en = regk_sser_yes;
- rec_cfg.rec_en = port->input;
- REG_WR(sser, port->regi_sser, rw_cfg, cfg);
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
- port->started = 1;
- }
-
- /* Setup wait if blocking */
- if (!(file->f_flags & O_NONBLOCK)) {
- add_wait_queue(&port->out_wait_q, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
- }
-
- spin_lock_irqsave(&port->lock, flags);
- port->out_buf_count += trunc_count;
- if (port->use_dma) {
-#ifdef SYNC_SER_DMA
- start_dma_out(port, wr_ptr, trunc_count);
-#endif
- } else if (!port->tr_running) {
-#ifdef SYNC_SER_MANUAL
- reg_sser_rw_intr_mask intr_mask;
- intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- intr_mask.trdy = 1;
- REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
-#endif
- }
- spin_unlock_irqrestore(&port->lock, flags);
-
- /* Exit if non blocking */
- if (file->f_flags & O_NONBLOCK) {
- DEBUGWRITE(pr_info("w d%d c %u %08x\n",
- port->port_nbr, trunc_count,
- REG_RD_INT(dma, port->regi_dmaout, r_intr)));
- return trunc_count;
- }
-
- schedule();
- remove_wait_queue(&port->out_wait_q, &wait);
-
- if (signal_pending(current))
- return -EINTR;
-
- DEBUGWRITE(pr_info("w d%d c %u\n", port->port_nbr, trunc_count));
- return trunc_count;
-}
-
-static ssize_t sync_serial_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- return __sync_serial_read(file, buf, count, ppos, NULL);
-}
-
-#ifdef SYNC_SER_MANUAL
-static void send_word(struct sync_port *port)
-{
- reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
- reg_sser_rw_tr_data tr_data = {0};
-
- switch (tr_cfg.sample_size) {
- case 8:
- port->out_buf_count--;
- tr_data.data = *port->out_rd_ptr++;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- case 12:
- {
- int data = (*port->out_rd_ptr++) << 8;
- data |= *port->out_rd_ptr++;
- port->out_buf_count -= 2;
- tr_data.data = data;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- }
- case 16:
- port->out_buf_count -= 2;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- case 24:
- port->out_buf_count -= 3;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- tr_data.data = *port->out_rd_ptr++;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- case 32:
- port->out_buf_count -= 4;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- }
-}
-#endif
-
-#ifdef SYNC_SER_DMA
-static void start_dma_out(struct sync_port *port, const char *data, int count)
-{
- port->active_tr_descr->buf = (char *)virt_to_phys((char *)data);
- port->active_tr_descr->after = port->active_tr_descr->buf + count;
- port->active_tr_descr->intr = 1;
-
- port->active_tr_descr->eol = 1;
- port->prev_tr_descr->eol = 0;
-
- DEBUGTRDMA(pr_info("Inserting eolr:%p eol@:%p\n",
- port->prev_tr_descr, port->active_tr_descr));
- port->prev_tr_descr = port->active_tr_descr;
- port->active_tr_descr = phys_to_virt((int)port->active_tr_descr->next);
-
- if (!port->tr_running) {
- reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser,
- rw_tr_cfg);
-
- port->out_context.next = NULL;
- port->out_context.saved_data =
- (dma_descr_data *)virt_to_phys(port->prev_tr_descr);
- port->out_context.saved_data_buf = port->prev_tr_descr->buf;
-
- DMA_START_CONTEXT(port->regi_dmaout,
- virt_to_phys((char *)&port->out_context));
-
- tr_cfg.tr_en = regk_sser_yes;
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- DEBUGTRDMA(pr_info("dma s\n"););
- } else {
- DMA_CONTINUE_DATA(port->regi_dmaout);
- DEBUGTRDMA(pr_info("dma c\n"););
- }
-
- port->tr_running = 1;
-}
-
-static void start_dma_in(struct sync_port *port)
-{
- int i;
- char *buf;
- unsigned long flags;
- spin_lock_irqsave(&port->lock, flags);
- port->writep = port->flip;
- spin_unlock_irqrestore(&port->lock, flags);
-
- buf = (char *)virt_to_phys(port->in_buffer);
- for (i = 0; i < NBR_IN_DESCR; i++) {
- port->in_descr[i].buf = buf;
- port->in_descr[i].after = buf + port->inbufchunk;
- port->in_descr[i].intr = 1;
- port->in_descr[i].next =
- (dma_descr_data *)virt_to_phys(&port->in_descr[i+1]);
- port->in_descr[i].buf = buf;
- buf += port->inbufchunk;
- }
- /* Link the last descriptor to the first */
- port->in_descr[i-1].next =
- (dma_descr_data *)virt_to_phys(&port->in_descr[0]);
- port->in_descr[i-1].eol = regk_sser_yes;
- port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1];
- port->in_context.saved_data =
- (dma_descr_data *)virt_to_phys(&port->in_descr[0]);
- port->in_context.saved_data_buf = port->in_descr[0].buf;
- DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context));
-}
-
-static irqreturn_t tr_interrupt(int irq, void *dev_id)
-{
- reg_dma_r_masked_intr masked;
- reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes };
- reg_dma_rw_stat stat;
- int i;
- int found = 0;
- int stop_sser = 0;
-
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
- if (!port->enabled || !port->use_dma)
- continue;
-
- /* IRQ active for the port? */
- masked = REG_RD(dma, port->regi_dmaout, r_masked_intr);
- if (!masked.data)
- continue;
-
- found = 1;
-
- /* Check if we should stop the DMA transfer */
- stat = REG_RD(dma, port->regi_dmaout, rw_stat);
- if (stat.list_state == regk_dma_data_at_eol)
- stop_sser = 1;
-
- /* Clear IRQ */
- REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
-
- if (!stop_sser) {
- /* The DMA has completed a descriptor, EOL was not
- * encountered, so step relevant descriptor and
- * datapointers forward. */
- int sent;
- sent = port->catch_tr_descr->after -
- port->catch_tr_descr->buf;
- DEBUGTXINT(pr_info("%-4d - %-4d = %-4d\t"
- "in descr %p (ac: %p)\n",
- port->out_buf_count, sent,
- port->out_buf_count - sent,
- port->catch_tr_descr,
- port->active_tr_descr););
- port->out_buf_count -= sent;
- port->catch_tr_descr =
- phys_to_virt((int) port->catch_tr_descr->next);
- port->out_rd_ptr =
- phys_to_virt((int) port->catch_tr_descr->buf);
- } else {
- reg_sser_rw_tr_cfg tr_cfg;
- int j, sent;
- /* EOL handler.
- * Note that if an EOL was encountered during the irq
- * locked section of sync_ser_write the DMA will be
- * restarted and the eol flag will be cleared.
- * The remaining descriptors will be traversed by
- * the descriptor interrupts as usual.
- */
- j = 0;
- while (!port->catch_tr_descr->eol) {
- sent = port->catch_tr_descr->after -
- port->catch_tr_descr->buf;
- DEBUGOUTBUF(pr_info(
- "traversing descr %p -%d (%d)\n",
- port->catch_tr_descr,
- sent,
- port->out_buf_count));
- port->out_buf_count -= sent;
- port->catch_tr_descr = phys_to_virt(
- (int)port->catch_tr_descr->next);
- j++;
- if (j >= NBR_OUT_DESCR) {
- /* TODO: Reset and recover */
- panic("sync_serial: missing eol");
- }
- }
- sent = port->catch_tr_descr->after -
- port->catch_tr_descr->buf;
- DEBUGOUTBUF(pr_info("eol at descr %p -%d (%d)\n",
- port->catch_tr_descr,
- sent,
- port->out_buf_count));
-
- port->out_buf_count -= sent;
-
- /* Update read pointer to first free byte, we
- * may already be writing data there. */
- port->out_rd_ptr =
- phys_to_virt((int) port->catch_tr_descr->after);
- if (port->out_rd_ptr > port->out_buffer +
- OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
-
- tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
- DEBUGTXINT(pr_info(
- "tr_int DMA stop %d, set catch @ %p\n",
- port->out_buf_count,
- port->active_tr_descr));
- if (port->out_buf_count != 0)
- pr_err("sync_ser: buf not empty after eol\n");
- port->catch_tr_descr = port->active_tr_descr;
- port->tr_running = 0;
- tr_cfg.tr_en = regk_sser_no;
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- }
- /* wake up the waiting process */
- wake_up_interruptible(&port->out_wait_q);
- }
- return IRQ_RETVAL(found);
-} /* tr_interrupt */
-
-
-static inline void handle_rx_packet(struct sync_port *port)
-{
- int idx;
- reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes };
- unsigned long flags;
-
- DEBUGRXINT(pr_info("!"));
- spin_lock_irqsave(&port->lock, flags);
-
- /* If we overrun the user experience is crap regardless if we
- * drop new or old data. Its much easier to get it right when
- * dropping new data so lets do that.
- */
- if ((port->writep + port->inbufchunk <=
- port->flip + port->in_buffer_size) &&
- (port->in_buffer_len + port->inbufchunk < IN_BUFFER_SIZE)) {
- memcpy(port->writep,
- phys_to_virt((unsigned)port->next_rx_desc->buf),
- port->inbufchunk);
- port->writep += port->inbufchunk;
- if (port->writep >= port->flip + port->in_buffer_size)
- port->writep = port->flip;
-
- /* Timestamp the new data chunk. */
- if (port->write_ts_idx == NBR_IN_DESCR)
- port->write_ts_idx = 0;
- idx = port->write_ts_idx++;
- ktime_get_ts(&port->timestamp[idx]);
- port->in_buffer_len += port->inbufchunk;
- }
- spin_unlock_irqrestore(&port->lock, flags);
-
- port->next_rx_desc->eol = 1;
- port->prev_rx_desc->eol = 0;
- /* Cache bug workaround */
- flush_dma_descr(port->prev_rx_desc, 0);
- port->prev_rx_desc = port->next_rx_desc;
- port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next);
- /* Cache bug workaround */
- flush_dma_descr(port->prev_rx_desc, 1);
- /* wake up the waiting process */
- wake_up_interruptible(&port->in_wait_q);
- DMA_CONTINUE(port->regi_dmain);
- REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr);
-
-}
-
-static irqreturn_t rx_interrupt(int irq, void *dev_id)
-{
- reg_dma_r_masked_intr masked;
-
- int i;
- int found = 0;
-
- DEBUG(pr_info("rx_interrupt\n"));
-
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || !port->use_dma)
- continue;
-
- masked = REG_RD(dma, port->regi_dmain, r_masked_intr);
-
- if (!masked.data)
- continue;
-
- /* Descriptor interrupt */
- found = 1;
- while (REG_RD(dma, port->regi_dmain, rw_data) !=
- virt_to_phys(port->next_rx_desc))
- handle_rx_packet(port);
- }
- return IRQ_RETVAL(found);
-} /* rx_interrupt */
-#endif /* SYNC_SER_DMA */
-
-#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id)
-{
- unsigned long flags;
- int i;
- int found = 0;
- reg_sser_r_masked_intr masked;
-
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || port->use_dma)
- continue;
-
- masked = REG_RD(sser, port->regi_sser, r_masked_intr);
- /* Data received? */
- if (masked.rdav) {
- reg_sser_rw_rec_cfg rec_cfg =
- REG_RD(sser, port->regi_sser, rw_rec_cfg);
- reg_sser_r_rec_data data = REG_RD(sser,
- port->regi_sser, r_rec_data);
- found = 1;
- /* Read data */
- spin_lock_irqsave(&port->lock, flags);
- switch (rec_cfg.sample_size) {
- case 8:
- *port->writep++ = data.data & 0xff;
- break;
- case 12:
- *port->writep = (data.data & 0x0ff0) >> 4;
- *(port->writep + 1) = data.data & 0x0f;
- port->writep += 2;
- break;
- case 16:
- *(unsigned short *)port->writep = data.data;
- port->writep += 2;
- break;
- case 24:
- *(unsigned int *)port->writep = data.data;
- port->writep += 3;
- break;
- case 32:
- *(unsigned int *)port->writep = data.data;
- port->writep += 4;
- break;
- }
-
- /* Wrap? */
- if (port->writep >= port->flip + port->in_buffer_size)
- port->writep = port->flip;
- if (port->writep == port->readp) {
- /* Receive buf overrun, discard oldest data */
- port->readp++;
- /* Wrap? */
- if (port->readp >= port->flip +
- port->in_buffer_size)
- port->readp = port->flip;
- }
- spin_unlock_irqrestore(&port->lock, flags);
- if (sync_data_avail(port) >= port->inbufchunk)
- /* Wake up application */
- wake_up_interruptible(&port->in_wait_q);
- }
-
- /* Transmitter ready? */
- if (masked.trdy) {
- found = 1;
- /* More data to send */
- if (port->out_buf_count > 0)
- send_word(port);
- else {
- /* Transmission finished */
- reg_sser_rw_intr_mask intr_mask;
- intr_mask = REG_RD(sser, port->regi_sser,
- rw_intr_mask);
- intr_mask.trdy = 0;
- REG_WR(sser, port->regi_sser,
- rw_intr_mask, intr_mask);
- /* Wake up application */
- wake_up_interruptible(&port->out_wait_q);
- }
- }
- }
- return IRQ_RETVAL(found);
-}
-#endif
-
-static int __init etrax_sync_serial_init(void)
-{
-#if 1
- /* This code will be removed when we move to udev for all devices. */
- syncser_first = MKDEV(SYNC_SERIAL_MAJOR, 0);
- if (register_chrdev_region(syncser_first, minor_count, SYNCSER_NAME)) {
- pr_err("Failed to register major %d\n", SYNC_SERIAL_MAJOR);
- return -1;
- }
-#else
- /* Allocate dynamic major number. */
- if (alloc_chrdev_region(&syncser_first, 0, minor_count, SYNCSER_NAME)) {
- pr_err("Failed to allocate character device region\n");
- return -1;
- }
-#endif
- syncser_cdev = cdev_alloc();
- if (!syncser_cdev) {
- pr_err("Failed to allocate cdev for syncser\n");
- unregister_chrdev_region(syncser_first, minor_count);
- return -1;
- }
- cdev_init(syncser_cdev, &syncser_fops);
-
- /* Create a sysfs class for syncser */
- syncser_class = class_create(THIS_MODULE, "syncser_class");
- if (IS_ERR(syncser_class)) {
- pr_err("Failed to create a sysfs class for syncser\n");
- unregister_chrdev_region(syncser_first, minor_count);
- cdev_del(syncser_cdev);
- return -1;
- }
-
- /* Initialize Ports */
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- if (artpec_pinmux_alloc_fixed(PINMUX_SSER0)) {
- pr_warn("Unable to alloc pins for synchronous serial port 0\n");
- unregister_chrdev_region(syncser_first, minor_count);
- return -EIO;
- }
- initialize_port(0);
- ports[0].enabled = 1;
- /* Register with sysfs so udev can pick it up. */
- device_create(syncser_class, NULL, syncser_first, NULL,
- "%s%d", SYNCSER_NAME, 0);
-#endif
-
-#if defined(CONFIG_ETRAXFS) && defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- if (artpec_pinmux_alloc_fixed(PINMUX_SSER1)) {
- pr_warn("Unable to alloc pins for synchronous serial port 1\n");
- unregister_chrdev_region(syncser_first, minor_count);
- class_destroy(syncser_class);
- return -EIO;
- }
- initialize_port(1);
- ports[1].enabled = 1;
- /* Register with sysfs so udev can pick it up. */
- device_create(syncser_class, NULL, syncser_first, NULL,
- "%s%d", SYNCSER_NAME, 0);
-#endif
-
- /* Add it to system */
- if (cdev_add(syncser_cdev, syncser_first, minor_count) < 0) {
- pr_err("Failed to add syncser as char device\n");
- device_destroy(syncser_class, syncser_first);
- class_destroy(syncser_class);
- cdev_del(syncser_cdev);
- unregister_chrdev_region(syncser_first, minor_count);
- return -1;
- }
-
-
- pr_info("ARTPEC synchronous serial port (%s: %d, %d)\n",
- SYNCSER_NAME, MAJOR(syncser_first), MINOR(syncser_first));
-
- return 0;
-}
-
-static void __exit etrax_sync_serial_exit(void)
-{
- int i;
- device_destroy(syncser_class, syncser_first);
- class_destroy(syncser_class);
-
- if (syncser_cdev) {
- cdev_del(syncser_cdev);
- unregister_chrdev_region(syncser_first, minor_count);
- }
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
- if (port->init_irqs == dma_irq_setup) {
- /* Free dma irqs and dma channels. */
-#ifdef SYNC_SER_DMA
- artpec_free_dma(port->dma_in_nbr);
- artpec_free_dma(port->dma_out_nbr);
- free_irq(port->dma_out_intr_vect, port);
- free_irq(port->dma_in_intr_vect, port);
-#endif
- } else if (port->init_irqs == manual_irq_setup) {
- /* Free manual irq. */
- free_irq(port->syncser_intr_vect, port);
- }
- }
-
- pr_info("ARTPEC synchronous serial port unregistered\n");
-}
-
-module_init(etrax_sync_serial_init);
-module_exit(etrax_sync_serial_exit);
-
-MODULE_LICENSE("GPL");
-
diff --git a/arch/cris/arch-v32/kernel/Makefile b/arch/cris/arch-v32/kernel/Makefile
deleted file mode 100644
index 2db7e4f7c1fa..000000000000
--- a/arch/cris/arch-v32/kernel/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-extra-y := head.o
-
-
-obj-y := entry.o traps.o irq.o debugport.o \
- process.o ptrace.o setup.o signal.o traps.o time.o \
- cache.o cacheflush.o
-
-obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o
-obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
-obj-$(CONFIG_MODULES) += crisksyms.o
-
-clean:
-
diff --git a/arch/cris/arch-v32/kernel/cache.c b/arch/cris/arch-v32/kernel/cache.c
deleted file mode 100644
index a080d2fa4803..000000000000
--- a/arch/cris/arch-v32/kernel/cache.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <asm/io.h>
-#include <arch/cache.h>
-#include <arch/hwregs/dma.h>
-
-/* This file is used to workaround a cache bug, Guinness TR 106. */
-
-inline void flush_dma_descr(struct dma_descr_data *descr, int flush_buf)
-{
- /* Flush descriptor to make sure we get correct in_eop and after. */
- asm volatile ("ftagd [%0]" :: "r" (descr));
- /* Flush buffer pointed out by descriptor. */
- if (flush_buf)
- cris_flush_cache_range(phys_to_virt((unsigned)descr->buf),
- (unsigned)(descr->after - descr->buf));
-}
-EXPORT_SYMBOL(flush_dma_descr);
-
-void flush_dma_list(struct dma_descr_data *descr)
-{
- while (1) {
- flush_dma_descr(descr, 1);
- if (descr->eol)
- break;
- descr = phys_to_virt((unsigned)descr->next);
- }
-}
-EXPORT_SYMBOL(flush_dma_list);
-
-/* From cacheflush.S */
-EXPORT_SYMBOL(cris_flush_cache);
-/* From cacheflush.S */
-EXPORT_SYMBOL(cris_flush_cache_range);
diff --git a/arch/cris/arch-v32/kernel/cacheflush.S b/arch/cris/arch-v32/kernel/cacheflush.S
deleted file mode 100644
index 2a54d793f96c..000000000000
--- a/arch/cris/arch-v32/kernel/cacheflush.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
- .global cris_flush_cache_range
- .type cris_flush_cache_range, @function
-cris_flush_cache_range:
- move.d 1024, $r12
- cmp.d $r11, $r12
- bhi cris_flush_1KB
- nop
- add.d $r10, $r11
- ftagd [$r10]
-cris_flush_last:
- addq 32, $r10
- cmp.d $r11, $r10
- blt cris_flush_last
- ftagd [$r10]
- ret
- nop
-cris_flush_1KB:
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ba cris_flush_cache_range
- sub.d $r12, $r11
- .size cris_flush_cache_range, . - cris_flush_cache_range
-
- .global cris_flush_cache
- .type cris_flush_cache, @function
-cris_flush_cache:
- moveq 0, $r10
-cris_flush_line:
- move.d 16*1024, $r11
- addq 16, $r10
- cmp.d $r10, $r11
- blt cris_flush_line
- fidxd [$r10]
- ret
- nop
- .size cris_flush_cache, . - cris_flush_cache
-
diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c
deleted file mode 100644
index 8cc8ad1cb532..000000000000
--- a/arch/cris/arch-v32/kernel/crisksyms.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <arch/dma.h>
-#include <arch/intmem.h>
-#include <mach/pinmux.h>
-
-/* Functions for allocating DMA channels */
-EXPORT_SYMBOL(crisv32_request_dma);
-EXPORT_SYMBOL(crisv32_free_dma);
-
-/* Functions for handling internal RAM */
-EXPORT_SYMBOL(crisv32_intmem_alloc);
-EXPORT_SYMBOL(crisv32_intmem_free);
-EXPORT_SYMBOL(crisv32_intmem_phys_to_virt);
-EXPORT_SYMBOL(crisv32_intmem_virt_to_phys);
-
-/* Functions for handling pinmux */
-EXPORT_SYMBOL(crisv32_pinmux_alloc);
-EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
-EXPORT_SYMBOL(crisv32_pinmux_dealloc);
-EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
-
-/* Functions masking/unmasking interrupts */
-EXPORT_SYMBOL(crisv32_mask_irq);
-EXPORT_SYMBOL(crisv32_unmask_irq);
diff --git a/arch/cris/arch-v32/kernel/debugport.c b/arch/cris/arch-v32/kernel/debugport.c
deleted file mode 100644
index 69247fd2090a..000000000000
--- a/arch/cris/arch-v32/kernel/debugport.c
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <linux/console.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/ser_defs.h>
-#include <hwregs/dma_defs.h>
-#include <mach/pinmux.h>
-
-struct dbg_port
-{
- unsigned char nbr;
- unsigned long instance;
- unsigned int started;
- unsigned long baudrate;
- unsigned char parity;
- unsigned int bits;
-};
-
-struct dbg_port ports[] =
-{
- {
- 0,
- regi_ser0,
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 1,
- regi_ser1,
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 2,
- regi_ser2,
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 3,
- regi_ser3,
- 0,
- 115200,
- 'N',
- 8
- },
-#if CONFIG_ETRAX_SERIAL_PORTS == 5
- {
- 4,
- regi_ser4,
- 0,
- 115200,
- 'N',
- 8
- },
-#endif
-};
-
-static struct dbg_port *port =
-#if defined(CONFIG_ETRAX_DEBUG_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- &ports[3];
-#else
- NULL;
-#endif
-
-#ifdef CONFIG_ETRAX_KGDB
-static struct dbg_port *kgdb_port =
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- &ports[3];
-#elif defined(CONFIG_ETRAX_KGDB_PORT4)
- &ports[4];
-#else
- NULL;
-#endif
-#endif
-
-static void start_port(struct dbg_port *p)
-{
- /* Set up serial port registers */
- reg_ser_rw_tr_ctrl tr_ctrl = {0};
- reg_ser_rw_tr_dma_en tr_dma_en = {0};
-
- reg_ser_rw_rec_ctrl rec_ctrl = {0};
- reg_ser_rw_tr_baud_div tr_baud_div = {0};
- reg_ser_rw_rec_baud_div rec_baud_div = {0};
-
- if (!p || p->started)
- return;
-
- p->started = 1;
-
- if (p->nbr == 1)
- crisv32_pinmux_alloc_fixed(pinmux_ser1);
- else if (p->nbr == 2)
- crisv32_pinmux_alloc_fixed(pinmux_ser2);
- else if (p->nbr == 3)
- crisv32_pinmux_alloc_fixed(pinmux_ser3);
-#if CONFIG_ETRAX_SERIAL_PORTS == 5
- else if (p->nbr == 4)
- crisv32_pinmux_alloc_fixed(pinmux_ser4);
-#endif
-
- tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493;
- tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no;
- tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8;
- tr_ctrl.en = rec_ctrl.en = 1;
-
- if (p->parity == 'O') {
- tr_ctrl.par_en = regk_ser_yes;
- tr_ctrl.par = regk_ser_odd;
- rec_ctrl.par_en = regk_ser_yes;
- rec_ctrl.par = regk_ser_odd;
- } else if (p->parity == 'E') {
- tr_ctrl.par_en = regk_ser_yes;
- tr_ctrl.par = regk_ser_even;
- rec_ctrl.par_en = regk_ser_yes;
- rec_ctrl.par = regk_ser_odd;
- }
-
- if (p->bits == 7) {
- tr_ctrl.data_bits = regk_ser_bits7;
- rec_ctrl.data_bits = regk_ser_bits7;
- }
-
- REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div);
- REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div);
- REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en);
- REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl);
- REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl);
-}
-
-#ifdef CONFIG_ETRAX_KGDB
-/* Use polling to get a single character from the kernel debug port */
-int getDebugChar(void)
-{
- reg_ser_rs_stat_din stat;
- reg_ser_rw_ack_intr ack_intr = { 0 };
-
- do {
- stat = REG_RD(ser, kgdb_port->instance, rs_stat_din);
- } while (!stat.dav);
-
- /* Ack the data_avail interrupt. */
- ack_intr.dav = 1;
- REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr);
-
- return stat.data;
-}
-
-/* Use polling to put a single character to the kernel debug port */
-void putDebugChar(int val)
-{
- reg_ser_r_stat_din stat;
- do {
- stat = REG_RD(ser, kgdb_port->instance, r_stat_din);
- } while (!stat.tr_rdy);
- REG_WR_INT(ser, kgdb_port->instance, rw_dout, val);
-}
-#endif /* CONFIG_ETRAX_KGDB */
-
-static void __init early_putch(int c)
-{
- reg_ser_r_stat_din stat;
- /* Wait until transmitter is ready and send. */
- do
- stat = REG_RD(ser, port->instance, r_stat_din);
- while (!stat.tr_rdy);
- REG_WR_INT(ser, port->instance, rw_dout, c);
-}
-
-static void __init
-early_console_write(struct console *con, const char *s, unsigned n)
-{
- extern void reset_watchdog(void);
- int i;
-
- /* Send data. */
- for (i = 0; i < n; i++) {
- /* TODO: the '\n' -> '\n\r' translation should be done at the
- receiver. Remove it when the serial driver removes it. */
- if (s[i] == '\n')
- early_putch('\r');
- early_putch(s[i]);
- reset_watchdog();
- }
-}
-
-static struct console early_console_dev __initdata = {
- .name = "early",
- .write = early_console_write,
- .flags = CON_PRINTBUFFER | CON_BOOT,
- .index = -1
-};
-
-/* Register console for printk's, etc. */
-int __init init_etrax_debug(void)
-{
- start_port(port);
-
- /* Register an early console if a debug port was chosen. */
- register_console(&early_console_dev);
-
-#ifdef CONFIG_ETRAX_KGDB
- start_port(kgdb_port);
-#endif /* CONFIG_ETRAX_KGDB */
- return 0;
-}
diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S
deleted file mode 100644
index 0793a52b2c34..000000000000
--- a/arch/cris/arch-v32/kernel/entry.S
+++ /dev/null
@@ -1,909 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2000-2003 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Tobias Anderberg (tobiasa@axis.com), CRISv32 port.
- *
- * Code for the system-call and fault low-level handling routines.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- * Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
- * if the order here is changed, it needs to be
- * updated in fork.c:copy_process, signal.c:do_signal,
- * ptrace.c and ptrace.h
- *
- */
-
-#include <linux/linkage.h>
-#include <linux/sys.h>
-#include <asm/unistd.h>
-#include <asm/errno.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/intr_vect_defs_asm.h>
-
- ;; Exported functions.
- .globl system_call
- .globl ret_from_intr
- .globl ret_from_fork
- .globl ret_from_kernel_thread
- .globl resume
- .globl multiple_interrupt
- .globl nmi_interrupt
- .globl spurious_interrupt
- .globl do_sigtrap
- .globl gdb_handle_exception
- .globl sys_call_table
-
- ; Check if preemptive kernel scheduling should be done.
-#ifdef CONFIG_PREEMPT
-_resume_kernel:
- di
- ; Load current task struct.
- movs.w -8192, $r0 ; THREAD_SIZE = 8192
- and.d $sp, $r0
-
- addoq +TI_preempt_count, $r0, $acr
- move.d [$acr], $r10 ; Preemption disabled?
- bne _Rexit
- nop
-
-_need_resched:
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r10
- btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set.
- bpl _Rexit
- nop
-
- ; Do preemptive kernel scheduling.
- jsr preempt_schedule_irq
- nop
-
- ; Load new task struct.
- movs.w -8192, $r0 ; THREAD_SIZE = 8192.
- and.d $sp, $r0
-
- ; One more time with new task.
- ba _need_resched
- nop
-#else
-#define _resume_kernel _Rexit
-#endif
-
- ; Called at exit from fork. schedule_tail must be called to drop
- ; spinlock if CONFIG_PREEMPT.
- .type ret_from_fork,@function
-ret_from_fork:
- jsr schedule_tail
- nop
- ba ret_from_sys_call
- nop
- .size ret_from_fork, . - ret_from_fork
-
- .type ret_from_kernel_thread,@function
-ret_from_kernel_thread:
- jsr schedule_tail
- nop
- move.d $r2, $r10
- jsr $r1
- nop
- moveq 0, $r9 ; no syscall restarts, TYVM...
- ba ret_from_sys_call
- nop
- .size ret_from_kernel_thread, . - ret_from_kernel_thread
-
- .type ret_from_intr,@function
-ret_from_intr:
- moveq 0, $r9 ; not a syscall
-
- ;; Check for resched if preemptive kernel, or if we're going back to
- ;; user-mode. This test matches the user_regs(regs) macro. Don't simply
- ;; test CCS since that doesn't necessarily reflect what mode we'll
- ;; return into.
- addoq +PT_ccs, $sp, $acr
- move.d [$acr], $r0
- btstq 16, $r0 ; User-mode flag.
- bpl _resume_kernel
- .size ret_from_intr, . - ret_from_intr + 2 ; +2 includes the dslot.
-
- ; Note that di below is in delay slot.
- .type _resume_userspace,@function
-_resume_userspace:
- di ; So need_resched and sigpending don't change.
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- addoq +TI_flags, $r0, $acr ; current->work
- move.d [$acr], $r10
- and.d _TIF_WORK_MASK, $r10 ; Work to be done on return?
- bne _work_pending
- nop
- ba _Rexit
- nop
- .size _resume_userspace, . - _resume_userspace
-
- ;; The system_call is called by a BREAK instruction, which looks pretty
- ;; much like any other exception.
- ;;
- ;; System calls can't be made from interrupts but we still stack ERP
- ;; to have a complete stack frame.
- ;;
- ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,
- ;; r13,mof,srp
- ;;
- ;; This function looks on the _surface_ like spaghetti programming, but it's
- ;; really designed so that the fast-path does not force cache-loading of
- ;; non-used instructions. Only the non-common cases cause the outlined code
- ;; to run..
-
- .type system_call,@function
-system_call:
- ;; Stack-frame similar to the irq heads, which is reversed in
- ;; ret_from_sys_call.
-
- sub.d 92, $sp ; Skip EDA.
- movem $r13, [$sp]
- move.d $sp, $r8
- addq 14*4, $r8
- move.d $acr, $r0
- move $srs, $r1
- move $mof, $r2
- move $spc, $r3
- move $ccs, $r4
- move $srp, $r5
- move $erp, $r6
- move.d $r9, $r7 ; Store syscall number in EXS
- subq 4, $sp
- movem $r7, [$r8]
- ei ; Enable interrupts while processing syscalls.
- move.d $r10, [$sp]
-
- ; Set S-bit when kernel debugging to keep hardware breakpoints active.
-#ifdef CONFIG_ETRAX_KGDB
- move $ccs, $r0
- or.d (1<<9), $r0
- move $r0, $ccs
-#endif
-
- movs.w -ENOSYS, $r0
- addoq +PT_r10, $sp, $acr
- move.d $r0, [$acr]
-
- ;; Check if this process is syscall-traced.
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r0
- btstq TIF_SYSCALL_TRACE, $r0
- bmi _syscall_trace_entry
- nop
-
-_syscall_traced:
- ;; Check for sanity in the requested syscall number.
- cmpu.w NR_syscalls, $r9
- bhs ret_from_sys_call
- lslq 2, $r9 ; Multiply by 4, in the delay slot.
-
- ;; The location on the stack for the register structure is passed as a
- ;; seventh argument. Some system calls need this.
- move.d $sp, $r0
- subq 4, $sp
- move.d $r0, [$sp]
-
- ;; The registers carrying parameters (R10-R13) are intact. The optional
- ;; fifth and sixth parameters is in MOF and SRP respectively. Put them
- ;; back on the stack.
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $mof, [$sp]
-
- ;; Actually to the system call.
- addo.d +sys_call_table, $r9, $acr
- move.d [$acr], $acr
- jsr $acr
- nop
-
- addq 3*4, $sp ; Pop the mof, srp and regs parameters.
- addoq +PT_r10, $sp, $acr
- move.d $r10, [$acr] ; Save the return value.
-
- moveq 1, $r9 ; "Parameter" to ret_from_sys_call to
- ; show it was a sys call.
-
- ;; Fall through into ret_from_sys_call to return.
-
-ret_from_sys_call:
- ;; R9 is a parameter:
- ;; >= 1 from syscall
- ;; 0 from irq
-
- ;; Get the current task-struct pointer.
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- di ; Make sure need_resched and sigpending don't change.
-
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r1
- and.d _TIF_ALLWORK_MASK, $r1
- bne _syscall_exit_work
- nop
- .size system_call, . - system_call
-
- .type _Rexit,@function
-_Rexit:
-#if defined(CONFIG_TRACE_IRQFLAGS)
- addoq +PT_ccs, $sp, $acr
- move.d [$acr], $r0
- btstq 15, $r0 ; I1
- bpl 1f
- nop
- jsr trace_hardirqs_on
- nop
-1:
-#endif
-
- ;; This epilogue MUST match the prologues in multiple_interrupt, irq.h
- ;; and ptregs.h.
- addq 4, $sp ; Skip orig_r10.
- movem [$sp+], $r13 ; Registers R0-R13.
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- move [$sp+], $mof
- move [$sp+], $spc
- move [$sp+], $ccs
- move [$sp+], $srp
- move [$sp+], $erp
- addq 8, $sp ; Skip EXS, EDA.
- jump $erp
- rfe ; Restore condition code stack in delay-slot.
- .size _Rexit, . - _Rexit
-
- ;; We get here after doing a syscall if extra work might need to be done
- ;; perform syscall exit tracing if needed.
-
- .type _syscall_exit_work,@function
-_syscall_exit_work:
- ;; R0 contains current at this point and irq's are disabled.
-
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r1
- btstq TIF_SYSCALL_TRACE, $r1
- bpl _work_pending
- nop
- ei
- move.d $r9, $r1 ; Preserve R9.
- jsr do_syscall_trace
- nop
- move.d $r1, $r9
- ba _resume_userspace
- nop
- .size _syscall_exit_work, . - _syscall_exit_work
-
- .type _work_pending,@function
-_work_pending:
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r12 ; The thread_info_flags parameter.
- move.d $sp, $r11 ; The regs param.
- jsr do_work_pending
- move.d $r9, $r10 ; The syscall/irq param.
-
- ba _Rexit
- nop
- .size _work_pending, . - _work_pending
-
- ;; We get here as a sidetrack when we've entered a syscall with the
- ;; trace-bit set. We need to call do_syscall_trace and then continue
- ;; with the call.
-
-_syscall_trace_entry:
- ;; PT_r10 in the frame contains -ENOSYS as required, at this point.
-
- jsr do_syscall_trace
- nop
-
- ;; Now re-enter the syscall code to do the syscall itself. We need to
- ;; restore R9 here to contain the wanted syscall, and the other
- ;; parameter-bearing registers.
- addoq +PT_r9, $sp, $acr
- move.d [$acr], $r9
- addoq +PT_orig_r10, $sp, $acr
- move.d [$acr], $r10 ; PT_r10 is already -ENOSYS.
- addoq +PT_r11, $sp, $acr
- move.d [$acr], $r11
- addoq +PT_r12, $sp, $acr
- move.d [$acr], $r12
- addoq +PT_r13, $sp, $acr
- move.d [$acr], $r13
- addoq +PT_mof, $sp, $acr
- move [$acr], $mof
- addoq +PT_srp, $sp, $acr
- move [$acr], $srp
-
- ba _syscall_traced
- nop
-
- ;; Resume performs the actual task-switching, by switching stack
- ;; pointers. Input arguments are:
- ;;
- ;; R10 = prev
- ;; R11 = next
- ;; R12 = thread offset in task struct.
- ;;
- ;; Returns old current in R10.
-
- .type resume,@function
-resume:
- subq 4, $sp ; Make space for srp.
-
- add.d $r12, $r10 ; R10 = current tasks tss.
- addoq +THREAD_ccs, $r10, $acr
- move $srp, [$sp] ; Keep old/new PC on the stack.
- move $ccs, [$acr] ; Save IRQ enable state.
- di
-
- addoq +THREAD_usp, $r10, $acr
- subq 10*4, $sp ; Make room for R9.
- move $usp, [$acr] ; Save user-mode stackpointer.
-
- ;; See copy_thread for the reason why register R9 is saved.
- movem $r9, [$sp] ; Save non-scratch registers and R9.
-
- addoq +THREAD_ksp, $r10, $acr
- move.d $sp, $r10 ; Return last running task in R10.
- move.d $sp, [$acr] ; Save kernel SP for old task.
-
- and.d -8192, $r10 ; Get thread_info from stackpointer.
- addoq +TI_task, $r10, $acr
- add.d $r12, $r11 ; Find the new tasks tss.
- move.d [$acr], $r10 ; Get task.
- addoq +THREAD_ksp, $r11, $acr
- move.d [$acr], $sp ; Switch to new stackframe.
- addoq +THREAD_usp, $r11, $acr
- movem [$sp+], $r9 ; Restore non-scratch registers and R9.
-
- move [$acr], $usp ; Restore user-mode stackpointer.
-
- addoq +THREAD_ccs, $r11, $acr
- move.d [$sp+], $r11
- jump $r11 ; Restore PC.
- move [$acr], $ccs ; Restore IRQ enable status.
- .size resume, . - resume
-
-nmi_interrupt:
-
-;; If we receive a watchdog interrupt while it is not expected, then set
-;; up a canonical frame and dump register contents before dying.
-
- ;; This prologue MUST match the one in irq.h and the struct in ptregs.h!
- subq 12, $sp ; Skip EXS, EDA.
- move $nrp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- subq 14*4, $sp ; Make room for R0-R13.
- movem $r13, [$sp] ; Push R0-R13.
- subq 4, $sp
- move.d $r10, [$sp] ; Push orig_r10.
- move.d REG_ADDR(intr_vect, regi_irq, r_nmi), $r0
- move.d [$r0], $r0
- btstq REG_BIT(intr_vect, r_nmi, watchdog), $r0
- bpl 1f
- nop
- jsr handle_watchdog_bite ; In time.c.
- move.d $sp, $r10 ; Pointer to registers
-1: btstq REG_BIT(intr_vect, r_nmi, ext), $r0
- bpl 1f
- nop
- jsr handle_nmi
- move.d $sp, $r10 ; Pointer to registers
-1: addq 4, $sp ; Skip orig_r10
- movem [$sp+], $r13
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- move [$sp+], $mof
- move [$sp+], $spc
- move [$sp+], $ccs
- move [$sp+], $srp
- move [$sp+], $nrp
- addq 8, $sp ; Skip EXS, EDA.
- jump $nrp
- rfn
-
- .comm cause_of_death, 4 ;; Don't declare this anywhere.
-
-spurious_interrupt:
- di
- jump hard_reset_now
- nop
-
- ;; This handles the case when multiple interrupts arrive at the same
- ;; time. Jump to the first set interrupt bit in a priority fashion. The
- ;; hardware will call the unserved interrupts after the handler
- ;; finishes.
- .type multiple_interrupt, @function
-multiple_interrupt:
- ;; This prologue MUST match the one in irq.h and the struct in ptregs.h!
- subq 12, $sp ; Skip EXS, EDA.
- move $erp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- subq 14*4, $sp ; Make room for R0-R13.
- movem $r13, [$sp] ; Push R0-R13.
- subq 4, $sp
- move.d $r10, [$sp] ; Push orig_r10.
-
-; Set S-bit when kernel debugging to keep hardware breakpoints active.
-#ifdef CONFIG_ETRAX_KGDB
- move $ccs, $r0
- or.d (1<<9), $r0
- move $r0, $ccs
-#endif
-
- jsr crisv32_do_multiple
- move.d $sp, $r10
- jump ret_from_intr
- nop
- .size multiple_interrupt, . - multiple_interrupt
-
-do_sigtrap:
- ;; Sigtraps the process that executed the BREAK instruction. Creates a
- ;; frame that Rexit expects.
- subq 4, $sp
- move $eda, [$sp]
- subq 4, $sp
- move $exs, [$sp]
- subq 4, $sp
- move $erp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- di ; Need to disable irq's at this point.
- subq 14*4, $sp ; Make room for r0-r13.
- movem $r13, [$sp] ; Push the r0-r13 registers.
- subq 4, $sp
- move.d $r10, [$sp] ; Push orig_r10.
-
- movs.w -8192, $r9 ; THREAD_SIZE == 8192
- and.d $sp, $r9
-
- ;; thread_info as first parameter
- move.d $r9, $r10
- moveq 5, $r11 ; SIGTRAP as second argument.
- jsr ugdb_trap_user
- nop
- jump ret_from_intr ; Use the return routine for interrupts.
- nop
-
-gdb_handle_exception:
- subq 4, $sp
- move.d $r0, [$sp]
-#ifdef CONFIG_ETRAX_KGDB
- move $ccs, $r0 ; U-flag not affected by previous insns.
- btstq 16, $r0 ; Test the U-flag.
- bmi _ugdb_handle_exception ; Go to user mode debugging.
- nop ; Empty delay-slot (cannot pop R0 here).
- ba kgdb_handle_exception ; Go to kernel debugging.
- move.d [$sp+], $r0 ; Restore R0 in delay slot.
-#endif
-
-_ugdb_handle_exception:
- ba do_sigtrap ; SIGTRAP the offending process.
- move.d [$sp+], $r0 ; Restore R0 in delay slot.
-
- .data
-
- .section .rodata,"a"
-sys_call_table:
- .long sys_restart_syscall ; 0 - old "setup()" system call, used
- ; for restarting.
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys( */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old sys_olduname holder */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_sgetmask
- .long sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_select /* was old_select in Linux/E100 */
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_old_readdir
- .long sys_old_mmap /* 90 */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* sys_ioperm in i386 */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* old sys_uname holder */
- .long sys_ni_syscall /* sys_iopl in i386 */
- .long sys_vhangup
- .long sys_ni_syscall /* old "idle" system call */
- .long sys_ni_syscall /* vm86old in i386 */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* sys_modify_ldt */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* sys_vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* Old nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap2
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall /* sys_set_thread_area */
- .long sys_ni_syscall /* sys_get_thread_area */
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_ni_syscall /* sys_mbind */
- .long sys_ni_syscall /* 275 sys_get_mempolicy */
- .long sys_ni_syscall /* sys_set_mempolicy */
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall /* reserved for kexec */
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate
- .long sys_timerfd_settime /* 325 */
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1
- .long sys_dup3 /* 330 */
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev
- .long sys_setns /* 335 */
- .long sys_name_to_handle_at
- .long sys_open_by_handle_at
- .long sys_rt_tgsigqueueinfo
- .long sys_perf_event_open
- .long sys_recvmmsg /* 340 */
- .long sys_accept4
- .long sys_fanotify_init
- .long sys_fanotify_mark
- .long sys_prlimit64
- .long sys_clock_adjtime /* 345 */
- .long sys_syncfs
- .long sys_sendmmsg
- .long sys_process_vm_readv
- .long sys_process_vm_writev
- .long sys_kcmp /* 350 */
- .long sys_finit_module
- .long sys_sched_setattr
- .long sys_sched_getattr
- .long sys_renameat2
- .long sys_seccomp /* 355 */
- .long sys_getrandom
- .long sys_memfd_create
- .long sys_bpf
- .long sys_execveat
-
- /*
- * NOTE!! This doesn't have to be exact - we just have
- * to make sure we have _enough_ of the "sys_ni_syscall"
- * entries. Don't panic if you notice that this hasn't
- * been shrunk every time we add a new system call.
- */
-
- .rept NR_syscalls - (.-sys_call_table) / 4
- .long sys_ni_syscall
- .endr
-
diff --git a/arch/cris/arch-v32/kernel/fasttimer.c b/arch/cris/arch-v32/kernel/fasttimer.c
deleted file mode 100644
index 7452c70f61ff..000000000000
--- a/arch/cris/arch-v32/kernel/fasttimer.c
+++ /dev/null
@@ -1,793 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/fasttimer.c
- *
- * Fast timers for ETRAX FS
- *
- * Copyright (C) 2000-2006 Axis Communications AB, Lund, Sweden
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-
-#include <asm/irq.h>
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-#include <asm/fasttimer.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-/*
- * timer0 is running at 100MHz and generating jiffies timer ticks
- * at 100 or 1000 HZ.
- * fasttimer gives an API that gives timers that expire "between" the jiffies
- * giving microsecond resolution (10 ns).
- * fasttimer uses reg_timer_rw_trig register to get interrupt when
- * r_time reaches a certain value.
- */
-
-
-#define DEBUG_LOG_INCLUDED
-#define FAST_TIMER_LOG
-/* #define FAST_TIMER_TEST */
-
-#define FAST_TIMER_SANITY_CHECKS
-
-#ifdef FAST_TIMER_SANITY_CHECKS
-static int sanity_failed;
-#endif
-
-#define D1(x)
-#define D2(x)
-#define DP(x)
-
-static unsigned int fast_timer_running;
-static unsigned int fast_timers_added;
-static unsigned int fast_timers_started;
-static unsigned int fast_timers_expired;
-static unsigned int fast_timers_deleted;
-static unsigned int fast_timer_is_init;
-static unsigned int fast_timer_ints;
-
-struct fast_timer *fast_timer_list = NULL;
-
-#ifdef DEBUG_LOG_INCLUDED
-#define DEBUG_LOG_MAX 128
-static const char * debug_log_string[DEBUG_LOG_MAX];
-static unsigned long debug_log_value[DEBUG_LOG_MAX];
-static unsigned int debug_log_cnt;
-static unsigned int debug_log_cnt_wrapped;
-
-#define DEBUG_LOG(string, value) \
-{ \
- unsigned long log_flags; \
- local_irq_save(log_flags); \
- debug_log_string[debug_log_cnt] = (string); \
- debug_log_value[debug_log_cnt] = (unsigned long)(value); \
- if (++debug_log_cnt >= DEBUG_LOG_MAX) \
- { \
- debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \
- debug_log_cnt_wrapped = 1; \
- } \
- local_irq_restore(log_flags); \
-}
-#else
-#define DEBUG_LOG(string, value)
-#endif
-
-
-#define NUM_TIMER_STATS 16
-#ifdef FAST_TIMER_LOG
-struct fast_timer timer_added_log[NUM_TIMER_STATS];
-struct fast_timer timer_started_log[NUM_TIMER_STATS];
-struct fast_timer timer_expired_log[NUM_TIMER_STATS];
-#endif
-
-int timer_div_settings[NUM_TIMER_STATS];
-int timer_delay_settings[NUM_TIMER_STATS];
-
-struct work_struct fast_work;
-
-static void
-timer_trig_handler(struct work_struct *work);
-
-
-
-/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */
-inline void do_gettimeofday_fast(struct fasttime_t *tv)
-{
- tv->tv_jiff = jiffies;
- tv->tv_usec = GET_JIFFIES_USEC();
-}
-
-inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1)
-{
- /* Compare jiffies. Takes care of wrapping */
- if (time_before(t0->tv_jiff, t1->tv_jiff))
- return -1;
- else if (time_after(t0->tv_jiff, t1->tv_jiff))
- return 1;
-
- /* Compare us */
- if (t0->tv_usec < t1->tv_usec)
- return -1;
- else if (t0->tv_usec > t1->tv_usec)
- return 1;
- return 0;
-}
-
-/* Called with ints off */
-inline void start_timer_trig(unsigned long delay_us)
-{
- reg_timer_rw_ack_intr ack_intr = { 0 };
- reg_timer_rw_intr_mask intr_mask;
- reg_timer_rw_trig trig;
- reg_timer_rw_trig_cfg trig_cfg = { 0 };
- reg_timer_r_time r_time0;
- reg_timer_r_time r_time1;
- unsigned char trig_wrap;
- unsigned char time_wrap;
-
- r_time0 = REG_RD(timer, regi_timer0, r_time);
-
- D1(printk("start_timer_trig : %d us freq: %i div: %i\n",
- delay_us, freq_index, div));
- /* Clear trig irq */
- intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
- intr_mask.trig = 0;
- REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
-
- /* Set timer values and check if trigger wraps. */
- /* r_time is 100MHz (10 ns resolution) */
- trig_wrap = (trig = r_time0 + delay_us*(1000/10)) < r_time0;
-
- timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig;
- timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
-
- /* Ack interrupt */
- ack_intr.trig = 1;
- REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
-
- /* Start timer */
- REG_WR(timer, regi_timer0, rw_trig, trig);
- trig_cfg.tmr = regk_timer_time;
- REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
-
- /* Check if we have already passed the trig time */
- r_time1 = REG_RD(timer, regi_timer0, r_time);
- time_wrap = r_time1 < r_time0;
-
- if ((trig_wrap && !time_wrap) || (r_time1 < trig)) {
- /* No, Enable trig irq */
- intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
- intr_mask.trig = 1;
- REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
- fast_timers_started++;
- fast_timer_running = 1;
- } else {
- /* We have passed the time, disable trig point, ack intr */
- trig_cfg.tmr = regk_timer_off;
- REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
- REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
- /* call the int routine */
- INIT_WORK(&fast_work, timer_trig_handler);
- schedule_work(&fast_work);
- }
-
-}
-
-/* In version 1.4 this function takes 27 - 50 us */
-void start_one_shot_timer(struct fast_timer *t,
- fast_timer_function_type *function,
- unsigned long data,
- unsigned long delay_us,
- const char *name)
-{
- unsigned long flags;
- struct fast_timer *tmp;
-
- D1(printk("sft %s %d us\n", name, delay_us));
-
- local_irq_save(flags);
-
- do_gettimeofday_fast(&t->tv_set);
- tmp = fast_timer_list;
-
-#ifdef FAST_TIMER_SANITY_CHECKS
- /* Check so this is not in the list already... */
- while (tmp != NULL) {
- if (tmp == t) {
- printk(KERN_DEBUG
- "timer name: %s data: 0x%08lX already "
- "in list!\n", name, data);
- sanity_failed++;
- goto done;
- } else
- tmp = tmp->next;
- }
- tmp = fast_timer_list;
-#endif
-
- t->delay_us = delay_us;
- t->function = function;
- t->data = data;
- t->name = name;
-
- t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000;
- t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ;
- if (t->tv_expires.tv_usec > 1000000) {
- t->tv_expires.tv_usec -= 1000000;
- t->tv_expires.tv_jiff += HZ;
- }
-#ifdef FAST_TIMER_LOG
- timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_added++;
-
- /* Check if this should timeout before anything else */
- if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) {
- /* Put first in list and modify the timer value */
- t->prev = NULL;
- t->next = fast_timer_list;
- if (fast_timer_list)
- fast_timer_list->prev = t;
- fast_timer_list = t;
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer_trig(delay_us);
- } else {
- /* Put in correct place in list */
- while (tmp->next &&
- fasttime_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0)
- tmp = tmp->next;
- /* Insert t after tmp */
- t->prev = tmp;
- t->next = tmp->next;
- if (tmp->next)
- {
- tmp->next->prev = t;
- }
- tmp->next = t;
- }
-
- D2(printk("start_one_shot_timer: %d us done\n", delay_us));
-
-done:
- local_irq_restore(flags);
-} /* start_one_shot_timer */
-
-static inline int fast_timer_pending (const struct fast_timer * t)
-{
- return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list);
-}
-
-static inline int detach_fast_timer (struct fast_timer *t)
-{
- struct fast_timer *next, *prev;
- if (!fast_timer_pending(t))
- return 0;
- next = t->next;
- prev = t->prev;
- if (next)
- next->prev = prev;
- if (prev)
- prev->next = next;
- else
- fast_timer_list = next;
- fast_timers_deleted++;
- return 1;
-}
-
-int del_fast_timer(struct fast_timer * t)
-{
- unsigned long flags;
- int ret;
-
- local_irq_save(flags);
- ret = detach_fast_timer(t);
- t->next = t->prev = NULL;
- local_irq_restore(flags);
- return ret;
-} /* del_fast_timer */
-
-
-/* Interrupt routines or functions called in interrupt context */
-
-/* Timer interrupt handler for trig interrupts */
-
-static irqreturn_t
-timer_trig_interrupt(int irq, void *dev_id)
-{
- reg_timer_r_masked_intr masked_intr;
- /* Check if the timer interrupt is for us (a trig int) */
- masked_intr = REG_RD(timer, regi_timer0, r_masked_intr);
- if (!masked_intr.trig)
- return IRQ_NONE;
- timer_trig_handler(NULL);
- return IRQ_HANDLED;
-}
-
-static void timer_trig_handler(struct work_struct *work)
-{
- reg_timer_rw_ack_intr ack_intr = { 0 };
- reg_timer_rw_intr_mask intr_mask;
- reg_timer_rw_trig_cfg trig_cfg = { 0 };
- struct fast_timer *t;
- fast_timer_function_type *f;
- unsigned long d;
- unsigned long flags;
-
- /* We keep interrupts disabled not only when we modify the
- * fast timer list, but any time we hold a reference to a
- * timer in the list, since del_fast_timer may be called
- * from (another) interrupt context. Thus, the only time
- * when interrupts are enabled is when calling the timer
- * callback function.
- */
- local_irq_save(flags);
-
- /* Clear timer trig interrupt */
- intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
- intr_mask.trig = 0;
- REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
-
- /* First stop timer, then ack interrupt */
- /* Stop timer */
- trig_cfg.tmr = regk_timer_off;
- REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
-
- /* Ack interrupt */
- ack_intr.trig = 1;
- REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
-
- fast_timer_running = 0;
- fast_timer_ints++;
-
- t = fast_timer_list;
- while (t) {
- struct fasttime_t tv;
-
- /* Has it really expired? */
- do_gettimeofday_fast(&tv);
- D1(printk(KERN_DEBUG
- "t: %is %06ius\n", tv.tv_jiff, tv.tv_usec));
-
- if (fasttime_cmp(&t->tv_expires, &tv) <= 0) {
- /* Yes it has expired */
-#ifdef FAST_TIMER_LOG
- timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_expired++;
-
- /* Remove this timer before call, since it may reuse the timer */
- if (t->prev)
- t->prev->next = t->next;
- else
- fast_timer_list = t->next;
- if (t->next)
- t->next->prev = t->prev;
- t->prev = NULL;
- t->next = NULL;
-
- /* Save function callback data before enabling
- * interrupts, since the timer may be removed and we
- * don't know how it was allocated (e.g. ->function
- * and ->data may become overwritten after deletion
- * if the timer was stack-allocated).
- */
- f = t->function;
- d = t->data;
-
- if (f != NULL) {
- /* Run the callback function with interrupts
- * enabled. */
- local_irq_restore(flags);
- f(d);
- local_irq_save(flags);
- } else
- DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints);
- } else {
- /* Timer is to early, let's set it again using the normal routines */
- D1(printk(".\n"));
- }
-
- t = fast_timer_list;
- if (t != NULL) {
- /* Start next timer.. */
- long us = 0;
- struct fasttime_t tv;
-
- do_gettimeofday_fast(&tv);
-
- /* time_after_eq takes care of wrapping */
- if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff))
- us = ((t->tv_expires.tv_jiff - tv.tv_jiff) *
- 1000000 / HZ + t->tv_expires.tv_usec -
- tv.tv_usec);
-
- if (us > 0) {
- if (!fast_timer_running) {
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer_trig(us);
- }
- break;
- } else {
- /* Timer already expired, let's handle it better late than never.
- * The normal loop handles it
- */
- D1(printk("e! %d\n", us));
- }
- }
- }
-
- local_irq_restore(flags);
-
- if (!t)
- D1(printk("ttrig stop!\n"));
-}
-
-static void wake_up_func(unsigned long data)
-{
- wait_queue_head_t *sleep_wait_p = (wait_queue_head_t*)data;
- wake_up(sleep_wait_p);
-}
-
-
-/* Useful API */
-
-void schedule_usleep(unsigned long us)
-{
- struct fast_timer t;
- wait_queue_head_t sleep_wait;
- init_waitqueue_head(&sleep_wait);
-
- D1(printk("schedule_usleep(%d)\n", us));
- start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us,
- "usleep");
- /* Uninterruptible sleep on the fast timer. (The condition is
- * somewhat redundant since the timer is what wakes us up.) */
- wait_event(sleep_wait, !fast_timer_pending(&t));
-
- D1(printk("done schedule_usleep(%d)\n", us));
-}
-
-#ifdef CONFIG_PROC_FS
-/* This value is very much based on testing */
-#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
-
-static int proc_fasttimer_show(struct seq_file *m, void *v)
-{
- unsigned long flags;
- int i = 0;
- int num_to_show;
- struct fasttime_t tv;
- struct fast_timer *t, *nextt;
-
- do_gettimeofday_fast(&tv);
-
- seq_printf(m, "Fast timers added: %i\n", fast_timers_added);
- seq_printf(m, "Fast timers started: %i\n", fast_timers_started);
- seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints);
- seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired);
- seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted);
- seq_printf(m, "Fast timer running: %s\n",
- fast_timer_running ? "yes" : "no");
- seq_printf(m, "Current time: %lu.%06lu\n",
- (unsigned long)tv.tv_jiff,
- (unsigned long)tv.tv_usec);
-#ifdef FAST_TIMER_SANITY_CHECKS
- seq_printf(m, "Sanity failed: %i\n", sanity_failed);
-#endif
- seq_putc(m, '\n');
-
-#ifdef DEBUG_LOG_INCLUDED
- {
- int end_i = debug_log_cnt;
- i = 0;
-
- if (debug_log_cnt_wrapped)
- i = debug_log_cnt;
-
- while ((i != end_i || debug_log_cnt_wrapped)) {
- seq_printf(m, debug_log_string[i], debug_log_value[i]);
- if (seq_has_overflowed(m))
- return 0;
- i = (i+1) % DEBUG_LOG_MAX;
- }
- }
- seq_putc(m, '\n');
-#endif
-
- num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers started: %i\n", fast_timers_started);
- for (i = 0; i < num_to_show; i++) {
- int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
-
-#if 1 //ndef FAST_TIMER_LOG
- seq_printf(m, "div: %i delay: %i\n",
- timer_div_settings[cur],
- timer_delay_settings[cur]);
-#endif
-#ifdef FAST_TIMER_LOG
- t = &timer_started_log[cur];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
-#endif
- }
- seq_putc(m, '\n');
-
-#ifdef FAST_TIMER_LOG
- num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers added: %i\n", fast_timers_added);
- for (i = 0; i < num_to_show; i++) {
- t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-
- num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers expired: %i\n", fast_timers_expired);
- for (i = 0; i < num_to_show; i++){
- t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-#endif
-
- seq_puts(m, "Active timers:\n");
- local_irq_save(flags);
- t = fast_timer_list;
- while (t != NULL){
- nextt = t->next;
- local_irq_restore(flags);
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- local_irq_save(flags);
- if (t->next != nextt)
- printk("timer removed!\n");
- t = nextt;
- }
- local_irq_restore(flags);
- return 0;
-}
-
-static int proc_fasttimer_open(struct inode *inode, struct file *file)
-{
- return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE);
-}
-
-static const struct file_operations proc_fasttimer_fops = {
- .open = proc_fasttimer_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-#endif /* PROC_FS */
-
-#ifdef FAST_TIMER_TEST
-static volatile unsigned long i = 0;
-static volatile int num_test_timeout = 0;
-static struct fast_timer tr[10];
-static int exp_num[10];
-
-static struct fasttime_t tv_exp[100];
-
-static void test_timeout(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
-
- num_test_timeout++;
-}
-
-static void test_timeout1(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
- if (data < 7)
- {
- start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1");
- i++;
- }
- num_test_timeout++;
-}
-
-DP(
-static char buf0[2000];
-static char buf1[2000];
-static char buf2[2000];
-static char buf3[2000];
-static char buf4[2000];
-);
-
-static char buf5[6000];
-static int j_u[1000];
-
-static void fast_timer_test(void)
-{
- int prev_num;
- int j;
-
- struct fasttime_t tv, tv0, tv1, tv2;
-
- printk("fast_timer_test() start\n");
- do_gettimeofday_fast(&tv);
-
- for (j = 0; j < 1000; j++)
- {
- j_u[j] = GET_JIFFIES_USEC();
- }
- for (j = 0; j < 100; j++)
- {
- do_gettimeofday_fast(&tv_exp[j]);
- }
- printk(KERN_DEBUG "fast_timer_test() %is %06i\n", tv.tv_jiff, tv.tv_usec);
-
- for (j = 0; j < 1000; j++)
- {
- printk(KERN_DEBUG "%i %i %i %i %i\n",
- j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
- j += 4;
- }
- for (j = 0; j < 100; j++)
- {
- printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n",
- tv_exp[j].tv_jiff, tv_exp[j].tv_usec,
- tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec,
- tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec,
- tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec,
- tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec);
- j += 4;
- }
- do_gettimeofday_fast(&tv0);
- start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0");
- DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1");
- DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2");
- DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3");
- DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx");
- DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0));
- i++;
- do_gettimeofday_fast(&tv1);
-
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
-
- prev_num = num_test_timeout;
- while (num_test_timeout < i)
- {
- if (num_test_timeout != prev_num)
- prev_num = num_test_timeout;
- }
- do_gettimeofday_fast(&tv2);
- printk(KERN_INFO "Timers started %is %06i\n",
- tv0.tv_jiff, tv0.tv_usec);
- printk(KERN_INFO "Timers started at %is %06i\n",
- tv1.tv_jiff, tv1.tv_usec);
- printk(KERN_INFO "Timers done %is %06i\n",
- tv2.tv_jiff, tv2.tv_usec);
- DP(printk("buf0:\n");
- printk(buf0);
- printk("buf1:\n");
- printk(buf1);
- printk("buf2:\n");
- printk(buf2);
- printk("buf3:\n");
- printk(buf3);
- printk("buf4:\n");
- printk(buf4);
- );
- printk("buf5:\n");
- printk(buf5);
-
- printk("timers set:\n");
- for(j = 0; j<i; j++)
- {
- struct fast_timer *t = &tr[j];
- printk("%-10s set: %6is %06ius exp: %6is %06ius "
- "data: 0x%08X func: 0x%08X\n",
- t->name,
- t->tv_set.tv_jiff,
- t->tv_set.tv_usec,
- t->tv_expires.tv_jiff,
- t->tv_expires.tv_usec,
- t->data,
- t->function
- );
-
- printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n",
- t->delay_us,
- tv_exp[j].tv_jiff,
- tv_exp[j].tv_usec,
- exp_num[j],
- (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) *
- 1000000 + tv_exp[j].tv_usec -
- t->tv_expires.tv_usec);
- }
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
- printk("buf5 after all done:\n");
- printk(buf5);
- printk("fast_timer_test() done\n");
-}
-#endif
-
-
-int fast_timer_init(void)
-{
- /* For some reason, request_irq() hangs when called froom time_init() */
- if (!fast_timer_is_init)
- {
- printk("fast_timer_init()\n");
-
-#ifdef CONFIG_PROC_FS
- proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
-#endif /* PROC_FS */
- if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt,
- IRQF_SHARED,
- "fast timer int", &fast_timer_list))
- printk(KERN_ERR "err: fasttimer irq\n");
- fast_timer_is_init = 1;
-#ifdef FAST_TIMER_TEST
- printk("do test\n");
- fast_timer_test();
-#endif
- }
- return 0;
-}
-__initcall(fast_timer_init);
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
deleted file mode 100644
index 92f9fb1f6845..000000000000
--- a/arch/cris/arch-v32/kernel/head.S
+++ /dev/null
@@ -1,439 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRISv32 kernel startup code.
- *
- * Copyright (C) 2003, Axis Communications AB
- */
-
-#include <linux/init.h>
-
-#define ASSEMBLER_MACROS_ONLY
-
-/*
- * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
- * -traditional must not be used when assembling this file.
- */
-#include <arch/memmap.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect.h>
-#include <hwregs/asm/mmu_defs_asm.h>
-#include <hwregs/asm/reg_map_asm.h>
-#include <mach/startup.inc>
-
-#define CRAMFS_MAGIC 0x28cd3d45
-#define JHEAD_MAGIC 0x1FF528A6
-#define JHEAD_SIZE 8
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-#define NAND_BOOT_MAGIC 0x9a9db001
-
- ;; NOTE: R8 and R9 carry information from the decompressor (if the
- ;; kernel was compressed). They must not be used in the code below
- ;; until they are read!
-
- ;; Exported symbols.
- .global etrax_irv
- .global romfs_start
- .global romfs_length
- .global romfs_in_flash
- .global nand_boot
- .global swapper_pg_dir
-
- __HEAD
-tstart:
- ;; This is the entry point of the kernel. The CPU is currently in
- ;; supervisor mode.
- ;;
- ;; 0x00000000 if flash.
- ;; 0x40004000 if DRAM.
- ;;
- di
-
- START_CLOCKS
-
- SETUP_WAIT_STATES
-
- GIO_INIT
-
- ;; Setup and enable the MMU. Use same configuration for both the data
- ;; and the instruction MMU.
- ;;
- ;; Note; 3 cycles is needed for a bank-select to take effect. Further;
- ;; bank 1 is the instruction MMU, bank 2 is the data MMU.
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 5) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
-#else
- move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
-#endif
-
- ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
- move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \
- | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
-
- ;; Enable certain page protections and setup linear mapping
- ;; for f,e,c,b,4,0.
-
- ;; ARTPEC-3:
- ;; c,d used for linear kernel mapping, up to 512 MB
- ;; e used for vmalloc
- ;; f unused, but page mapped to get page faults
-
- ;; ETRAX FS:
- ;; c used for linear kernel mapping, up to 256 MB
- ;; d used for vmalloc
- ;; e,f used for memory-mapped NOR flash
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
- | REG_STATE(mmu, rw_mm_cfg, acc, on) \
- | REG_STATE(mmu, rw_mm_cfg, ex, on) \
- | REG_STATE(mmu, rw_mm_cfg, inv, on) \
- | REG_STATE(mmu, rw_mm_cfg, seg_f, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_e, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_d, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
-#else
- move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
- | REG_STATE(mmu, rw_mm_cfg, acc, on) \
- | REG_STATE(mmu, rw_mm_cfg, ex, on) \
- | REG_STATE(mmu, rw_mm_cfg, inv, on) \
- | REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_d, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
-#endif
-
- ;; Update instruction MMU.
- move 1, $srs
- nop
- nop
- nop
- move $r0, $s2 ; kbase_hi.
- move $r1, $s1 ; kbase_lo.
- move $r2, $s0 ; mm_cfg, virtual memory configuration.
-
- ;; Update data MMU.
- move 2, $srs
- nop
- nop
- nop
- move $r0, $s2 ; kbase_hi.
- move $r1, $s1 ; kbase_lo
- move $r2, $s0 ; mm_cfg, virtual memory configuration.
-
- ;; Enable data and instruction MMU.
- move 0, $srs
- moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on
- nop
- nop
- nop
- move $r0, $s0
- nop
- nop
- nop
-
- ; Check if starting from DRAM (network->RAM boot or unpacked
- ; compressed kernel), or directly from flash.
- lapcq ., $r0
- and.d 0x7fffffff, $r0 ; Mask off the non-cache bit.
- cmp.d 0x10000, $r0 ; Arbitrary, something above this code.
- blo _inflash0
- nop
-
- jump _inram ; Jump to cached RAM.
- nop
-
- ;; Jumpgate.
-_inflash0:
- jump _inflash
- nop
-
- ;; Put the following in a section so that storage for it can be
- ;; reclaimed after init is finished.
- __INIT
-
-_inflash:
-
- ;; Initialize DRAM.
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq _dram_initialized
- nop
-
-#if defined CONFIG_ETRAXFS
-#include "../mach-fs/dram_init.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../mach-a3/dram_init.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
-
-
-_dram_initialized:
- ;; Copy the text and data section to DRAM. This depends on that the
- ;; variables used below are correctly set up by the linker script.
- ;; The calculated value stored in R4 is used below.
- ;; Leave the cramfs file system (piggybacked after the kernel) in flash.
- moveq 0, $r0 ; Source.
- move.d text_start, $r1 ; Destination.
- move.d __vmlinux_end, $r2
- move.d $r2, $r4
- sub.d $r1, $r4
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
- blo 1b
- nop
-
- ;; Check for cramfs.
- moveq 0, $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
- move.d [$r4], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne 1f
- nop
-
- ;; Set length and start of cramfs, set romfs_in_flash flag
- addoq +4, $r4, $acr
- move.d [$acr], $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
- add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory.
- move.d romfs_start, $r1
- move.d $r4, [$r1]
-1: moveq 1, $r0
- move.d romfs_in_flash, $r1
- move.d $r0, [$r1]
-
- jump _start_it ; Jump to cached code.
- nop
-
-_inram:
- ;; Check if booting from NAND flash; if so, set appropriate flags
- ;; and move on.
- cmp.d NAND_BOOT_MAGIC, $r12
- bne move_cramfs ; not nand, jump
- moveq 1, $r0
- move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND
- move.d $r0, [$r1]
- moveq 0, $r0 ; tell axisflashmap romfs is not in
- move.d romfs_in_flash, $r1 ; (directly accessed) flash
- move.d $r0, [$r1]
- jump _start_it ; continue with boot
- nop
-
-move_cramfs:
- ;; kernel is in DRAM.
- ;; Must figure out if there is a piggybacked rootfs image or not.
- ;; Set romfs_length to 0 => no rootfs image available by default.
- moveq 0, $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
-
- ;; The kernel could have been unpacked to DRAM by the loader, but
- ;; the cramfs image could still be in the flash immediately
- ;; following the compressed kernel image. The loader passes the address
- ;; of the byte succeeding the last compressed byte in the flash in
- ;; register R9 when starting the kernel.
- cmp.d 0x0ffffff8, $r9
- bhs _no_romfs_in_flash ; R9 points outside the flash area.
- nop
- ;; cramfs rootfs might to be in flash. Check for it.
- move.d [$r9], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne _no_romfs_in_flash
- nop
-
- ;; found cramfs in flash. set address and size, and romfs_in_flash flag.
- addoq +4, $r9, $acr
- move.d [$acr], $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
- add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory.
- move.d romfs_start, $r1
- move.d $r9, [$r1]
- moveq 1, $r0
- move.d romfs_in_flash, $r1
- move.d $r0, [$r1]
-
- jump _start_it ; Jump to cached code.
- nop
-
-_no_romfs_in_flash:
- ;; No romfs in flash, so look for cramfs, or jffs2 with jhead,
- ;; after kernel in RAM, as is the case with network->RAM boot.
- ;; For cramfs, partition starts with magic and length.
- ;; For jffs2, a jhead is prepended which contains with magic and length.
- ;; The jhead is not part of the jffs2 partition however.
- move.d __bss_start, $r0
- move.d [$r0], $r1
- cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
- beq 2f ; yes, jump
- nop
- cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
- bne 4f ; no, skip copy
- nop
- addq 4, $r0 ; location of jffs2 size
- move.d [$r0+], $r2 ; fetch jffs2 size -> r2
- ; r0 now points to start of jffs2
- ba 3f
- nop
-2:
- addoq +4, $r0, $acr ; location of cramfs size
- move.d [$acr], $r2 ; fetch cramfs size -> r2
- ; r0 still points to start of cramfs
-3:
- ;; Now, move the root fs to after kernel's BSS
-
- move.d _end, $r1 ; start of cramfs -> r1
- move.d romfs_start, $r3
- move.d $r1, [$r3] ; store at romfs_start (for axisflashmap)
- move.d romfs_length, $r3
- move.d $r2, [$r3] ; store size at romfs_length
-
- add.d $r2, $r0 ; copy from end and downwards
- add.d $r2, $r1
-
- lsrq 1, $r2 ; Size is in bytes, we copy words.
- addq 1, $r2
-1:
- move.w [$r0], $r3
- move.w $r3, [$r1]
- subq 2, $r0
- subq 2, $r1
- subq 1, $r2
- bne 1b
- nop
-
-4:
- ;; BSS move done.
- ;; Clear romfs_in_flash flag, as we now know romfs is in DRAM
- ;; Also clear nand_boot flag; if we got here, we know we've not
- ;; booted from NAND flash.
- moveq 0, $r0
- move.d romfs_in_flash, $r1
- move.d $r0, [$r1]
- moveq 0, $r0
- move.d nand_boot, $r1
- move.d $r0, [$r1]
-
- jump _start_it ; Jump to cached code.
- nop
-
-_start_it:
-
- ;; Check if kernel command line is supplied
- cmp.d COMMAND_LINE_MAGIC, $r10
- bne no_command_line
- nop
-
- move.d 256, $r13
- move.d cris_command_line, $r10
- or.d 0x80000000, $r11 ; Make it virtual
-1:
- move.b [$r11+], $r1
- move.b $r1, [$r10+]
- subq 1, $r13
- bne 1b
- nop
-
-no_command_line:
-
- ;; The kernel stack contains a task structure for each task. This
- ;; the initial kernel stack is in the same page as the init_task,
- ;; but starts at the top of the page, i.e. + 8192 bytes.
- move.d init_thread_union + 8192, $sp
- move.d ebp_start, $r0 ; Defined in linker-script.
- move $r0, $ebp
- move.d etrax_irv, $r1 ; Set the exception base register and pointer.
- move.d $r0, [$r1]
-
- ;; Clear the BSS region from _bss_start to _end.
- move.d __bss_start, $r0
- move.d _end, $r1
-1: clear.d [$r0+]
- cmp.d $r1, $r0
- blo 1b
- nop
-
- ; Initialize registers to increase determinism
- move.d __bss_start, $r0
- movem [$r0], $r13
-
-#ifdef CONFIG_ETRAX_L2CACHE
- jsr l2cache_init
- nop
-#endif
-
- jump start_kernel ; Jump to start_kernel() in init/main.c.
- nop
-
- .data
-etrax_irv:
- .dword 0
-
-; Variables for communication with the Axis flash map driver (axisflashmap),
-; and for setting up memory in arch/cris/kernel/setup.c .
-
-; romfs_start is set to the start of the root file system, if it exists
-; in directly accessible memory (i.e. NOR Flash when booting from Flash,
-; or RAM when booting directly from a network-downloaded RAM image)
-romfs_start:
- .dword 0
-
-; romfs_length is set to the size of the root file system image, if it exists
-; in directly accessible memory (see romfs_start). Otherwise it is set to 0.
-romfs_length:
- .dword 0
-
-; romfs_in_flash is set to 1 if the root file system resides in directly
-; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot
-; or NAND flash boot.
-romfs_in_flash:
- .dword 0
-
-; nand_boot is set to 1 when the kernel has been booted from NAND flash
-nand_boot:
- .dword 0
-
-swapper_pg_dir = 0xc0002000
-
- .section ".init.data", "aw"
-
-#if defined CONFIG_ETRAXFS
-#include "../mach-fs/hw_settings.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../mach-a3/hw_settings.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
deleted file mode 100644
index 414afd543232..000000000000
--- a/arch/cris/arch-v32/kernel/irq.c
+++ /dev/null
@@ -1,520 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <asm/irq.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/threads.h>
-#include <linux/spinlock.h>
-#include <linux/kernel_stat.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect.h>
-#include <hwregs/intr_vect_defs.h>
-
-#define CPU_FIXED -1
-
-/* IRQ masks (refer to comment for crisv32_do_multiple) */
-#if TIMER0_INTR_VECT - FIRST_IRQ < 32
-#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
-#undef TIMER_VECT1
-#else
-#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
-#define TIMER_VECT1
-#endif
-#ifdef CONFIG_ETRAX_KGDB
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
-#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
-#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
-#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
-#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
-#endif
-#endif
-
-DEFINE_SPINLOCK(irq_lock);
-
-struct cris_irq_allocation
-{
- int cpu; /* The CPU to which the IRQ is currently allocated. */
- cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
-};
-
-struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
- { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
-
-static unsigned long irq_regs[NR_CPUS] =
-{
- regi_irq,
-};
-
-#if NR_REAL_IRQS > 32
-#define NBR_REGS 2
-#else
-#define NBR_REGS 1
-#endif
-
-unsigned long cpu_irq_counters[NR_CPUS];
-unsigned long irq_counters[NR_REAL_IRQS];
-
-/* From irq.c. */
-extern void weird_irq(void);
-
-/* From entry.S. */
-extern void system_call(void);
-extern void nmi_interrupt(void);
-extern void multiple_interrupt(void);
-extern void gdb_handle_exception(void);
-extern void i_mmu_refill(void);
-extern void i_mmu_invalid(void);
-extern void i_mmu_access(void);
-extern void i_mmu_execute(void);
-extern void d_mmu_refill(void);
-extern void d_mmu_invalid(void);
-extern void d_mmu_access(void);
-extern void d_mmu_write(void);
-
-/* From kgdb.c. */
-extern void kgdb_init(void);
-extern void breakpoint(void);
-
-/* From traps.c. */
-extern void breakh_BUG(void);
-
-/*
- * Build the IRQ handler stubs using macros from irq.h.
- */
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-BUILD_TIMER_IRQ(0x31, 0)
-#else
-BUILD_IRQ(0x31)
-#endif
-BUILD_IRQ(0x32)
-BUILD_IRQ(0x33)
-BUILD_IRQ(0x34)
-BUILD_IRQ(0x35)
-BUILD_IRQ(0x36)
-BUILD_IRQ(0x37)
-BUILD_IRQ(0x38)
-BUILD_IRQ(0x39)
-BUILD_IRQ(0x3a)
-BUILD_IRQ(0x3b)
-BUILD_IRQ(0x3c)
-BUILD_IRQ(0x3d)
-BUILD_IRQ(0x3e)
-BUILD_IRQ(0x3f)
-BUILD_IRQ(0x40)
-BUILD_IRQ(0x41)
-BUILD_IRQ(0x42)
-BUILD_IRQ(0x43)
-BUILD_IRQ(0x44)
-BUILD_IRQ(0x45)
-BUILD_IRQ(0x46)
-BUILD_IRQ(0x47)
-BUILD_IRQ(0x48)
-BUILD_IRQ(0x49)
-BUILD_IRQ(0x4a)
-#ifdef CONFIG_ETRAXFS
-BUILD_TIMER_IRQ(0x4b, 0)
-#else
-BUILD_IRQ(0x4b)
-#endif
-BUILD_IRQ(0x4c)
-BUILD_IRQ(0x4d)
-BUILD_IRQ(0x4e)
-BUILD_IRQ(0x4f)
-BUILD_IRQ(0x50)
-#if MACH_IRQS > 32
-BUILD_IRQ(0x51)
-BUILD_IRQ(0x52)
-BUILD_IRQ(0x53)
-BUILD_IRQ(0x54)
-BUILD_IRQ(0x55)
-BUILD_IRQ(0x56)
-BUILD_IRQ(0x57)
-BUILD_IRQ(0x58)
-BUILD_IRQ(0x59)
-BUILD_IRQ(0x5a)
-BUILD_IRQ(0x5b)
-BUILD_IRQ(0x5c)
-BUILD_IRQ(0x5d)
-BUILD_IRQ(0x5e)
-BUILD_IRQ(0x5f)
-BUILD_IRQ(0x60)
-BUILD_IRQ(0x61)
-BUILD_IRQ(0x62)
-BUILD_IRQ(0x63)
-BUILD_IRQ(0x64)
-BUILD_IRQ(0x65)
-BUILD_IRQ(0x66)
-BUILD_IRQ(0x67)
-BUILD_IRQ(0x68)
-BUILD_IRQ(0x69)
-BUILD_IRQ(0x6a)
-BUILD_IRQ(0x6b)
-BUILD_IRQ(0x6c)
-BUILD_IRQ(0x6d)
-BUILD_IRQ(0x6e)
-BUILD_IRQ(0x6f)
-BUILD_IRQ(0x70)
-#endif
-
-/* Pointers to the low-level handlers. */
-static void (*interrupt[MACH_IRQS])(void) = {
- IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
- IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
- IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
- IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
- IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
- IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
- IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
- IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
- IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
- IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
- IRQ0x4f_interrupt, IRQ0x50_interrupt,
-#if MACH_IRQS > 32
- IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
- IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
- IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
- IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
- IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
- IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
- IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
- IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
- IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
- IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
- IRQ0x6f_interrupt, IRQ0x70_interrupt,
-#endif
-};
-
-void
-block_irq(int irq, int cpu)
-{
- int intr_mask;
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- /* Remember, 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32) {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 0);
- intr_mask &= ~(1 << (irq - FIRST_IRQ));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 0, intr_mask);
- } else {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
- intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 1, intr_mask);
- }
- spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-void
-unblock_irq(int irq, int cpu)
-{
- int intr_mask;
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- /* Remember, 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32) {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 0);
- intr_mask |= (1 << (irq - FIRST_IRQ));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 0, intr_mask);
- } else {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
- intr_mask |= (1 << (irq - FIRST_IRQ - 32));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 1, intr_mask);
- }
- spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-/* Find out which CPU the irq should be allocated to. */
-static int irq_cpu(int irq)
-{
- int cpu;
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- cpu = irq_allocations[irq - FIRST_IRQ].cpu;
-
- /* Fixed interrupts stay on the local CPU. */
- if (cpu == CPU_FIXED)
- {
- spin_unlock_irqrestore(&irq_lock, flags);
- return smp_processor_id();
- }
-
-
- /* Let the interrupt stay if possible */
- if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
- goto out;
-
- /* IRQ must be moved to another CPU. */
- cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
- irq_allocations[irq - FIRST_IRQ].cpu = cpu;
-out:
- spin_unlock_irqrestore(&irq_lock, flags);
- return cpu;
-}
-
-void crisv32_mask_irq(int irq)
-{
- int cpu;
-
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- block_irq(irq, cpu);
-}
-
-void crisv32_unmask_irq(int irq)
-{
- unblock_irq(irq, irq_cpu(irq));
-}
-
-
-static void enable_crisv32_irq(struct irq_data *data)
-{
- crisv32_unmask_irq(data->irq);
-}
-
-static void disable_crisv32_irq(struct irq_data *data)
-{
- crisv32_mask_irq(data->irq);
-}
-
-static int set_affinity_crisv32_irq(struct irq_data *data,
- const struct cpumask *dest, bool force)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
- spin_unlock_irqrestore(&irq_lock, flags);
- return 0;
-}
-
-static struct irq_chip crisv32_irq_type = {
- .name = "CRISv32",
- .irq_shutdown = disable_crisv32_irq,
- .irq_enable = enable_crisv32_irq,
- .irq_disable = disable_crisv32_irq,
- .irq_set_affinity = set_affinity_crisv32_irq,
-};
-
-void
-set_exception_vector(int n, irqvectptr addr)
-{
- etrax_irv->v[n] = (irqvectptr) addr;
-}
-
-extern void do_IRQ(int irq, struct pt_regs * regs);
-
-void
-crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
-{
- /* Interrupts that may not be moved to another CPU may
- * skip blocking. This is currently only valid for the
- * timer IRQ and the IPI and is used for the timer
- * interrupt to avoid watchdog starvation.
- */
- if (!block) {
- do_IRQ(irq, regs);
- return;
- }
-
- block_irq(irq, smp_processor_id());
- do_IRQ(irq, regs);
-
- unblock_irq(irq, irq_cpu(irq));
-}
-
-/* If multiple interrupts occur simultaneously we get a multiple
- * interrupt from the CPU and software has to sort out which
- * interrupts that happened. There are two special cases here:
- *
- * 1. Timer interrupts may never be blocked because of the
- * watchdog (refer to comment in include/asr/arch/irq.h)
- * 2. GDB serial port IRQs are unhandled here and will be handled
- * as a single IRQ when it strikes again because the GDB
- * stubb wants to save the registers in its own fashion.
- */
-void
-crisv32_do_multiple(struct pt_regs* regs)
-{
- int cpu;
- int mask;
- int masked[NBR_REGS];
- int bit;
- int i;
-
- cpu = smp_processor_id();
-
- /* An extra irq_enter here to prevent softIRQs to run after
- * each do_IRQ. This will decrease the interrupt latency.
- */
- irq_enter();
-
- for (i = 0; i < NBR_REGS; i++) {
- /* Get which IRQs that happened. */
- masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- r_masked_vect, i);
-
- /* Calculate new IRQ mask with these IRQs disabled. */
- mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
- mask &= ~masked[i];
-
- /* Timer IRQ is never masked */
-#ifdef TIMER_VECT1
- if ((i == 1) && (masked[0] & TIMER_MASK))
- mask |= TIMER_MASK;
-#else
- if ((i == 0) && (masked[0] & TIMER_MASK))
- mask |= TIMER_MASK;
-#endif
- /* Block all the IRQs */
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
-
- /* Check for timer IRQ and handle it special. */
-#ifdef TIMER_VECT1
- if ((i == 1) && (masked[i] & TIMER_MASK)) {
- masked[i] &= ~TIMER_MASK;
- do_IRQ(TIMER0_INTR_VECT, regs);
- }
-#else
- if ((i == 0) && (masked[i] & TIMER_MASK)) {
- masked[i] &= ~TIMER_MASK;
- do_IRQ(TIMER0_INTR_VECT, regs);
- }
-#endif
- }
-
-#ifdef IGNORE_MASK
- /* Remove IRQs that can't be handled as multiple. */
- masked[0] &= ~IGNORE_MASK;
-#endif
-
- /* Handle the rest of the IRQs. */
- for (i = 0; i < NBR_REGS; i++) {
- for (bit = 0; bit < 32; bit++) {
- if (masked[i] & (1 << bit))
- do_IRQ(bit + FIRST_IRQ + i*32, regs);
- }
- }
-
- /* Unblock all the IRQs. */
- for (i = 0; i < NBR_REGS; i++) {
- mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
- mask |= masked[i];
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
- }
-
- /* This irq_exit() will trigger the soft IRQs. */
- irq_exit();
-}
-
-static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw_irq_num)
-{
- irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);
-
- return 0;
-}
-
-static struct irq_domain_ops crisv32_irq_ops = {
- .map = crisv32_irq_map,
- .xlate = irq_domain_xlate_onecell,
-};
-
-/*
- * This is called by start_kernel. It fixes the IRQ masks and setup the
- * interrupt vector table to point to bad_interrupt pointers.
- */
-void __init
-init_IRQ(void)
-{
- int i;
- int j;
- reg_intr_vect_rw_mask vect_mask = {0};
- struct device_node *np;
- struct irq_domain *domain;
-
- /* Clear all interrupts masks. */
- for (i = 0; i < NBR_REGS; i++)
- REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
-
- for (i = 0; i < 256; i++)
- etrax_irv->v[i] = weird_irq;
-
- np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
- domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ,
- FIRST_IRQ, FIRST_IRQ,
- &crisv32_irq_ops, NULL);
- BUG_ON(!domain);
- irq_set_default_host(domain);
- of_node_put(np);
-
- for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT && j < MACH_IRQS; i++, j++)
- set_exception_vector(i, interrupt[j]);
-
- /* Mark Timer and IPI IRQs as CPU local */
- irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
- irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU);
- irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
- irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU);
-
- set_exception_vector(0x00, nmi_interrupt);
- set_exception_vector(0x30, multiple_interrupt);
-
- /* Set up handler for various MMU bus faults. */
- set_exception_vector(0x04, i_mmu_refill);
- set_exception_vector(0x05, i_mmu_invalid);
- set_exception_vector(0x06, i_mmu_access);
- set_exception_vector(0x07, i_mmu_execute);
- set_exception_vector(0x08, d_mmu_refill);
- set_exception_vector(0x09, d_mmu_invalid);
- set_exception_vector(0x0a, d_mmu_access);
- set_exception_vector(0x0b, d_mmu_write);
-
-#ifdef CONFIG_BUG
- /* Break 14 handler, used to implement cheap BUG(). */
- set_exception_vector(0x1e, breakh_BUG);
-#endif
-
- /* The system-call trap is reached by "break 13". */
- set_exception_vector(0x1d, system_call);
-
- /* Exception handlers for debugging, both user-mode and kernel-mode. */
-
- /* Break 8. */
- set_exception_vector(0x18, gdb_handle_exception);
- /* Hardware single step. */
- set_exception_vector(0x3, gdb_handle_exception);
- /* Hardware breakpoint. */
- set_exception_vector(0xc, gdb_handle_exception);
-
-#ifdef CONFIG_ETRAX_KGDB
- kgdb_init();
- /* Everything is set up; now trap the kernel. */
- breakpoint();
-#endif
-}
-
diff --git a/arch/cris/arch-v32/kernel/kgdb.c b/arch/cris/arch-v32/kernel/kgdb.c
deleted file mode 100644
index 3d6f516763a5..000000000000
--- a/arch/cris/arch-v32/kernel/kgdb.c
+++ /dev/null
@@ -1,1593 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/cris/arch-v32/kernel/kgdb.c
- *
- * CRIS v32 version by Orjan Friberg, Axis Communications AB.
- *
- * S390 version
- * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
- *
- * Originally written by Glenn Engel, Lake Stevens Instrument Division
- *
- * Contributed by HP Systems
- *
- * Modified for SPARC by Stu Grossman, Cygnus Support.
- *
- * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
- * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
- *
- * Copyright (C) 1995 Andreas Busse
- */
-
-/* FIXME: Check the documentation. */
-
-/*
- * kgdb usage notes:
- * -----------------
- *
- * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
- * built with different gcc flags: "-g" is added to get debug infos, and
- * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
- * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
- * before compresion. Such a kernel will behave just as usually, except if
- * given a "debug=<device>" command line option. (Only serial devices are
- * allowed for <device>, i.e. no printers or the like; possible values are
- * machine depedend and are the same as for the usual debug device, the one
- * for logging kernel messages.) If that option is given and the device can be
- * initialized, the kernel will connect to the remote gdb in trap_init(). The
- * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
- * implementation.
- *
- * To start a debugging session, start that gdb with the debugging kernel
- * image (the one with the symbols, vmlinux.debug) named on the command line.
- * This file will be used by gdb to get symbol and debugging infos about the
- * kernel. Next, select remote debug mode by
- * target remote <device>
- * where <device> is the name of the serial device over which the debugged
- * machine is connected. Maybe you have to adjust the baud rate by
- * set remotebaud <rate>
- * or also other parameters with stty:
- * shell stty ... </dev/...
- * If the kernel to debug has already booted, it waited for gdb and now
- * connects, and you'll see a breakpoint being reported. If the kernel isn't
- * running yet, start it now. The order of gdb and the kernel doesn't matter.
- * Another thing worth knowing about in the getting-started phase is how to
- * debug the remote protocol itself. This is activated with
- * set remotedebug 1
- * gdb will then print out each packet sent or received. You'll also get some
- * messages about the gdb stub on the console of the debugged machine.
- *
- * If all that works, you can use lots of the usual debugging techniques on
- * the kernel, e.g. inspecting and changing variables/memory, setting
- * breakpoints, single stepping and so on. It's also possible to interrupt the
- * debugged kernel by pressing C-c in gdb. Have fun! :-)
- *
- * The gdb stub is entered (and thus the remote gdb gets control) in the
- * following situations:
- *
- * - If breakpoint() is called. This is just after kgdb initialization, or if
- * a breakpoint() call has been put somewhere into the kernel source.
- * (Breakpoints can of course also be set the usual way in gdb.)
- * In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
- *
- * - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
- * are entered. All the CPU exceptions are mapped to (more or less..., see
- * the hard_trap_info array below) appropriate signal, which are reported
- * to gdb. die_if_kernel() is usually called after some kind of access
- * error and thus is reported as SIGSEGV.
- *
- * - When panic() is called. This is reported as SIGABRT.
- *
- * - If C-c is received over the serial line, which is treated as
- * SIGINT.
- *
- * Of course, all these signals are just faked for gdb, since there is no
- * signal concept as such for the kernel. It also isn't possible --obviously--
- * to set signal handlers from inside gdb, or restart the kernel with a
- * signal.
- *
- * Current limitations:
- *
- * - While the kernel is stopped, interrupts are disabled for safety reasons
- * (i.e., variables not changing magically or the like). But this also
- * means that the clock isn't running anymore, and that interrupts from the
- * hardware may get lost/not be served in time. This can cause some device
- * errors...
- *
- * - When single-stepping, only one instruction of the current thread is
- * executed, but interrupts are allowed for that time and will be serviced
- * if pending. Be prepared for that.
- *
- * - All debugging happens in kernel virtual address space. There's no way to
- * access physical memory not mapped in kernel space, or to access user
- * space. A way to work around this is using get_user_long & Co. in gdb
- * expressions, but only for the current process.
- *
- * - Interrupting the kernel only works if interrupts are currently allowed,
- * and the interrupt of the serial line isn't blocked by some other means
- * (IPL too high, disabled, ...)
- *
- * - The gdb stub is currently not reentrant, i.e. errors that happen therein
- * (e.g. accessing invalid memory) may not be caught correctly. This could
- * be removed in future by introducing a stack of struct registers.
- *
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to kgdb_init() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint().
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- */
-
-
-#include <linux/string.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/linkage.h>
-#include <linux/reboot.h>
-
-#include <asm/setup.h>
-#include <asm/ptrace.h>
-
-#include <asm/irq.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect_defs.h>
-#include <hwregs/ser_defs.h>
-
-/* From entry.S. */
-extern void gdb_handle_exception(void);
-/* From kgdb_asm.S. */
-extern void kgdb_handle_exception(void);
-
-static int kgdb_started = 0;
-
-/********************************* Register image ****************************/
-
-typedef
-struct register_image
-{
- /* Offset */
- unsigned int r0; /* 0x00 */
- unsigned int r1; /* 0x04 */
- unsigned int r2; /* 0x08 */
- unsigned int r3; /* 0x0C */
- unsigned int r4; /* 0x10 */
- unsigned int r5; /* 0x14 */
- unsigned int r6; /* 0x18 */
- unsigned int r7; /* 0x1C */
- unsigned int r8; /* 0x20; Frame pointer (if any) */
- unsigned int r9; /* 0x24 */
- unsigned int r10; /* 0x28 */
- unsigned int r11; /* 0x2C */
- unsigned int r12; /* 0x30 */
- unsigned int r13; /* 0x34 */
- unsigned int sp; /* 0x38; R14, Stack pointer */
- unsigned int acr; /* 0x3C; R15, Address calculation register. */
-
- unsigned char bz; /* 0x40; P0, 8-bit zero register */
- unsigned char vr; /* 0x41; P1, Version register (8-bit) */
- unsigned int pid; /* 0x42; P2, Process ID */
- unsigned char srs; /* 0x46; P3, Support register select (8-bit) */
- unsigned short wz; /* 0x47; P4, 16-bit zero register */
- unsigned int exs; /* 0x49; P5, Exception status */
- unsigned int eda; /* 0x4D; P6, Exception data address */
- unsigned int mof; /* 0x51; P7, Multiply overflow register */
- unsigned int dz; /* 0x55; P8, 32-bit zero register */
- unsigned int ebp; /* 0x59; P9, Exception base pointer */
- unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
- unsigned int srp; /* 0x61; P11, Subroutine return pointer */
- unsigned int nrp; /* 0x65; P12, NMI return pointer */
- unsigned int ccs; /* 0x69; P13, Condition code stack */
- unsigned int usp; /* 0x6D; P14, User mode stack pointer */
- unsigned int spc; /* 0x71; P15, Single step PC */
- unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */
-
-} registers;
-
-typedef
-struct bp_register_image
-{
- /* Support register bank 0. */
- unsigned int s0_0;
- unsigned int s1_0;
- unsigned int s2_0;
- unsigned int s3_0;
- unsigned int s4_0;
- unsigned int s5_0;
- unsigned int s6_0;
- unsigned int s7_0;
- unsigned int s8_0;
- unsigned int s9_0;
- unsigned int s10_0;
- unsigned int s11_0;
- unsigned int s12_0;
- unsigned int s13_0;
- unsigned int s14_0;
- unsigned int s15_0;
-
- /* Support register bank 1. */
- unsigned int s0_1;
- unsigned int s1_1;
- unsigned int s2_1;
- unsigned int s3_1;
- unsigned int s4_1;
- unsigned int s5_1;
- unsigned int s6_1;
- unsigned int s7_1;
- unsigned int s8_1;
- unsigned int s9_1;
- unsigned int s10_1;
- unsigned int s11_1;
- unsigned int s12_1;
- unsigned int s13_1;
- unsigned int s14_1;
- unsigned int s15_1;
-
- /* Support register bank 2. */
- unsigned int s0_2;
- unsigned int s1_2;
- unsigned int s2_2;
- unsigned int s3_2;
- unsigned int s4_2;
- unsigned int s5_2;
- unsigned int s6_2;
- unsigned int s7_2;
- unsigned int s8_2;
- unsigned int s9_2;
- unsigned int s10_2;
- unsigned int s11_2;
- unsigned int s12_2;
- unsigned int s13_2;
- unsigned int s14_2;
- unsigned int s15_2;
-
- /* Support register bank 3. */
- unsigned int s0_3; /* BP_CTRL */
- unsigned int s1_3; /* BP_I0_START */
- unsigned int s2_3; /* BP_I0_END */
- unsigned int s3_3; /* BP_D0_START */
- unsigned int s4_3; /* BP_D0_END */
- unsigned int s5_3; /* BP_D1_START */
- unsigned int s6_3; /* BP_D1_END */
- unsigned int s7_3; /* BP_D2_START */
- unsigned int s8_3; /* BP_D2_END */
- unsigned int s9_3; /* BP_D3_START */
- unsigned int s10_3; /* BP_D3_END */
- unsigned int s11_3; /* BP_D4_START */
- unsigned int s12_3; /* BP_D4_END */
- unsigned int s13_3; /* BP_D5_START */
- unsigned int s14_3; /* BP_D5_END */
- unsigned int s15_3; /* BP_RESERVED */
-
-} support_registers;
-
-enum register_name
-{
- R0, R1, R2, R3,
- R4, R5, R6, R7,
- R8, R9, R10, R11,
- R12, R13, SP, ACR,
-
- BZ, VR, PID, SRS,
- WZ, EXS, EDA, MOF,
- DZ, EBP, ERP, SRP,
- NRP, CCS, USP, SPC,
- PC,
-
- S0, S1, S2, S3,
- S4, S5, S6, S7,
- S8, S9, S10, S11,
- S12, S13, S14, S15
-
-};
-
-/* The register sizes of the registers in register_name. An unimplemented register
- is designated by size 0 in this array. */
-static int register_size[] =
-{
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
-
- 1, 1, 4, 1,
- 2, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
-
- 4,
-
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4
-
-};
-
-/* Contains the register image of the kernel.
- (Global so that they can be reached from assembler code.) */
-registers reg;
-support_registers sreg;
-
-/************** Prototypes for local library functions ***********************/
-
-/* Copy of strcpy from libc. */
-static char *gdb_cris_strcpy(char *s1, const char *s2);
-
-/* Copy of strlen from libc. */
-static int gdb_cris_strlen(const char *s);
-
-/* Copy of memchr from libc. */
-static void *gdb_cris_memchr(const void *s, int c, int n);
-
-/* Copy of strtol from libc. Does only support base 16. */
-static int gdb_cris_strtol(const char *s, char **endptr, int base);
-
-/********************** Prototypes for local functions. **********************/
-
-/* Write a value to a specified register regno in the register image
- of the current thread. */
-static int write_register(int regno, char *val);
-
-/* Read a value from a specified register in the register image. Returns the
- status of the read operation. The register value is returned in valptr. */
-static int read_register(char regno, unsigned int *valptr);
-
-/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
-int getDebugChar(void);
-
-/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
-void putDebugChar(int val);
-
-/* Convert the memory, pointed to by mem into hexadecimal representation.
- Put the result in buf, and return a pointer to the last character
- in buf (null). */
-static char *mem2hex(char *buf, unsigned char *mem, int count);
-
-/* Put the content of the array, in binary representation, pointed to by buf
- into memory pointed to by mem, and return a pointer to
- the character after the last byte written. */
-static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
- returned. */
-static void getpacket(char *buffer);
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-static void putpacket(char *buffer);
-
-/* Build and send a response packet in order to inform the host the
- stub is stopped. */
-static void stub_is_stopped(int sigval);
-
-/* All expected commands are sent from remote.c. Send a response according
- to the description in remote.c. Not static since it needs to be reached
- from assembler code. */
-void handle_exception(int sigval);
-
-/* Performs a complete re-start from scratch. ETRAX specific. */
-static void kill_restart(void);
-
-/******************** Prototypes for global functions. ***********************/
-
-/* The string str is prepended with the GDB printout token and sent. */
-void putDebugString(const unsigned char *str, int len);
-
-/* A static breakpoint to be used at startup. */
-void breakpoint(void);
-
-/* Avoid warning as the internal_stack is not used in the C-code. */
-#define USEDVAR(name) { if (name) { ; } }
-#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
-
-/********************************** Packet I/O ******************************/
-/* BUFMAX defines the maximum number of characters in
- inbound/outbound buffers */
-/* FIXME: How do we know it's enough? */
-#define BUFMAX 512
-
-/* Run-length encoding maximum length. Send 64 at most. */
-#define RUNLENMAX 64
-
-/* The inbound/outbound buffers used in packet I/O */
-static char input_buffer[BUFMAX];
-static char output_buffer[BUFMAX];
-
-/* Error and warning messages. */
-enum error_type
-{
- SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
-};
-
-static char *error_message[] =
-{
- "",
- "E01 Set current or general thread - H[c,g] - internal error.",
- "E02 Change register content - P - cannot change read-only register.",
- "E03 Thread is not alive.", /* T, not used. */
- "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
- "E05 Change register content - P - the register is not implemented..",
- "E06 Change memory content - M - internal error.",
- "E07 Change register content - P - the register is not stored on the stack",
- "E08 Invalid parameter"
-};
-
-/********************************** Breakpoint *******************************/
-/* Use an internal stack in the breakpoint and interrupt response routines.
- FIXME: How do we know the size of this stack is enough?
- Global so it can be reached from assembler code. */
-#define INTERNAL_STACK_SIZE 1024
-char internal_stack[INTERNAL_STACK_SIZE];
-
-/* Due to the breakpoint return pointer, a state variable is needed to keep
- track of whether it is a static (compiled) or dynamic (gdb-invoked)
- breakpoint to be handled. A static breakpoint uses the content of register
- ERP as it is whereas a dynamic breakpoint requires subtraction with 2
- in order to execute the instruction. The first breakpoint is static; all
- following are assumed to be dynamic. */
-static int dynamic_bp = 0;
-
-/********************************* String library ****************************/
-/* Single-step over library functions creates trap loops. */
-
-/* Copy char s2[] to s1[]. */
-static char*
-gdb_cris_strcpy(char *s1, const char *s2)
-{
- char *s = s1;
-
- for (s = s1; (*s++ = *s2++) != '\0'; )
- ;
- return s1;
-}
-
-/* Find length of s[]. */
-static int
-gdb_cris_strlen(const char *s)
-{
- const char *sc;
-
- for (sc = s; *sc != '\0'; sc++)
- ;
- return (sc - s);
-}
-
-/* Find first occurrence of c in s[n]. */
-static void*
-gdb_cris_memchr(const void *s, int c, int n)
-{
- const unsigned char uc = c;
- const unsigned char *su;
-
- for (su = s; 0 < n; ++su, --n)
- if (*su == uc)
- return (void *)su;
- return NULL;
-}
-/******************************* Standard library ****************************/
-/* Single-step over library functions creates trap loops. */
-/* Convert string to long. */
-static int
-gdb_cris_strtol(const char *s, char **endptr, int base)
-{
- char *s1;
- char *sd;
- int x = 0;
-
- for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
- x = x * base + (sd - hex_asc);
-
- if (endptr) {
- /* Unconverted suffix is stored in endptr unless endptr is NULL. */
- *endptr = s1;
- }
-
- return x;
-}
-
-/********************************* Register image ****************************/
-
-/* Write a value to a specified register in the register image of the current
- thread. Returns status code SUCCESS, E02, E05 or E08. */
-static int
-write_register(int regno, char *val)
-{
- int status = SUCCESS;
-
- if (regno >= R0 && regno <= ACR) {
- /* Consecutive 32-bit registers. */
- if (hex2bin((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
-
- } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
- /* Read-only registers. */
- status = E02;
-
- } else if (regno == PID) {
- /* 32-bit register. (Even though we already checked SRS and WZ, we cannot
- combine this with the EXS - SPC write since SRS and WZ have different size.) */
- if (hex2bin((unsigned char *)&reg.pid, val, sizeof(unsigned int)))
- status = E08;
-
- } else if (regno == SRS) {
- /* 8-bit register. */
- if (hex2bin((unsigned char *)&reg.srs, val, sizeof(unsigned char)))
- status = E08;
-
- } else if (regno >= EXS && regno <= SPC) {
- /* Consecutive 32-bit registers. */
- if (hex2bin((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
-
- } else if (regno == PC) {
- /* Pseudo-register. Treat as read-only. */
- status = E02;
-
- } else if (regno >= S0 && regno <= S15) {
- /* 32-bit registers. */
- if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
- } else {
- /* Non-existing register. */
- status = E05;
- }
- return status;
-}
-
-/* Read a value from a specified register in the register image. Returns the
- value in the register or -1 for non-implemented registers. */
-static int
-read_register(char regno, unsigned int *valptr)
-{
- int status = SUCCESS;
-
- /* We read the zero registers from the register struct (instead of just returning 0)
- to catch errors. */
-
- if (regno >= R0 && regno <= ACR) {
- /* Consecutive 32-bit registers. */
- *valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int));
-
- } else if (regno == BZ || regno == VR) {
- /* Consecutive 8-bit registers. */
- *valptr = (unsigned int)(*(unsigned char *)
- ((char *)&reg.bz + (regno - BZ) * sizeof(char)));
-
- } else if (regno == PID) {
- /* 32-bit register. */
- *valptr = *(unsigned int *)((char *)&reg.pid);
-
- } else if (regno == SRS) {
- /* 8-bit register. */
- *valptr = (unsigned int)(*(unsigned char *)((char *)&reg.srs));
-
- } else if (regno == WZ) {
- /* 16-bit register. */
- *valptr = (unsigned int)(*(unsigned short *)(char *)&reg.wz);
-
- } else if (regno >= EXS && regno <= PC) {
- /* Consecutive 32-bit registers. */
- *valptr = *(unsigned int *)((char *)&reg.exs + (regno - EXS) * sizeof(unsigned int));
-
- } else if (regno >= S0 && regno <= S15) {
- /* Consecutive 32-bit registers, located elsewhere. */
- *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
-
- } else {
- /* Non-existing register. */
- status = E05;
- }
- return status;
-
-}
-
-/********************************** Packet I/O ******************************/
-/* Convert the memory, pointed to by mem into hexadecimal representation.
- Put the result in buf, and return a pointer to the last character
- in buf (null). */
-
-static char *
-mem2hex(char *buf, unsigned char *mem, int count)
-{
- int i;
- int ch;
-
- if (mem == NULL) {
- /* Invalid address, caught by 'm' packet handler. */
- for (i = 0; i < count; i++) {
- *buf++ = '0';
- *buf++ = '0';
- }
- } else {
- /* Valid mem address. */
- for (i = 0; i < count; i++) {
- ch = *mem++;
- buf = hex_byte_pack(buf, ch);
- }
- }
- /* Terminate properly. */
- *buf = '\0';
- return buf;
-}
-
-/* Same as mem2hex, but puts it in network byte order. */
-static char *
-mem2hex_nbo(char *buf, unsigned char *mem, int count)
-{
- int i;
- int ch;
-
- mem += count - 1;
- for (i = 0; i < count; i++) {
- ch = *mem--;
- buf = hex_byte_pack(buf, ch);
- }
-
- /* Terminate properly. */
- *buf = '\0';
- return buf;
-}
-
-/* Put the content of the array, in binary representation, pointed to by buf
- into memory pointed to by mem, and return a pointer to the character after
- the last byte written.
- Gdb will escape $, #, and the escape char (0x7d). */
-static unsigned char*
-bin2mem(unsigned char *mem, unsigned char *buf, int count)
-{
- int i;
- unsigned char *next;
- for (i = 0; i < count; i++) {
- /* Check for any escaped characters. Be paranoid and
- only unescape chars that should be escaped. */
- if (*buf == 0x7d) {
- next = buf + 1;
- if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
- /* #, $, ESC */
- buf++;
- *buf += 0x20;
- }
- }
- *mem++ = *buf++;
- }
- return mem;
-}
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
- returned. */
-static void
-getpacket(char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- int i;
- int count;
- char ch;
-
- do {
- while((ch = getDebugChar ()) != '$')
- /* Wait for the start character $ and ignore all other characters */;
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- /* Read until a # or the end of the buffer is reached */
- while (count < BUFMAX) {
- ch = getDebugChar();
- if (ch == '#')
- break;
- checksum = checksum + ch;
- buffer[count] = ch;
- count = count + 1;
- }
-
- if (count >= BUFMAX)
- continue;
-
- buffer[count] = 0;
-
- if (ch == '#') {
- xmitcsum = hex_to_bin(getDebugChar()) << 4;
- xmitcsum += hex_to_bin(getDebugChar());
- if (checksum != xmitcsum) {
- /* Wrong checksum */
- putDebugChar('-');
- } else {
- /* Correct checksum */
- putDebugChar('+');
- /* If sequence characters are received, reply with them */
- if (buffer[2] == ':') {
- putDebugChar(buffer[0]);
- putDebugChar(buffer[1]);
- /* Remove the sequence characters from the buffer */
- count = gdb_cris_strlen(buffer);
- for (i = 3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
- }
- }
- } while (checksum != xmitcsum);
-}
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-
-static void
-putpacket(char *buffer)
-{
- int checksum;
- int runlen;
- int encode;
-
- do {
- char *src = buffer;
- putDebugChar('$');
- checksum = 0;
- while (*src) {
- /* Do run length encoding */
- putDebugChar(*src);
- checksum += *src;
- runlen = 0;
- while (runlen < RUNLENMAX && *src == src[runlen]) {
- runlen++;
- }
- if (runlen > 3) {
- /* Got a useful amount */
- putDebugChar ('*');
- checksum += '*';
- encode = runlen + ' ' - 4;
- putDebugChar(encode);
- checksum += encode;
- src += runlen;
- } else {
- src++;
- }
- }
- putDebugChar('#');
- putDebugChar(hex_asc_hi(checksum));
- putDebugChar(hex_asc_lo(checksum));
- } while(kgdb_started && (getDebugChar() != '+'));
-}
-
-/* The string str is prepended with the GDB printout token and sent. Required
- in traditional implementations. */
-void
-putDebugString(const unsigned char *str, int len)
-{
- /* Move SPC forward if we are single-stepping. */
- asm("spchere:");
- asm("move $spc, $r10");
- asm("cmp.d spchere, $r10");
- asm("bne nosstep");
- asm("nop");
- asm("move.d spccont, $r10");
- asm("move $r10, $spc");
- asm("nosstep:");
-
- output_buffer[0] = 'O';
- mem2hex(&output_buffer[1], (unsigned char *)str, len);
- putpacket(output_buffer);
-
- asm("spccont:");
-}
-
-/********************************** Handle exceptions ************************/
-/* Build and send a response packet in order to inform the host the
- stub is stopped. TAAn...:r...;n...:r...;n...:r...;
- AA = signal number
- n... = register number (hex)
- r... = register contents
- n... = `thread'
- r... = thread process ID. This is a hex integer.
- n... = other string not starting with valid hex digit.
- gdb should ignore this n,r pair and go on to the next.
- This way we can extend the protocol. */
-static void
-stub_is_stopped(int sigval)
-{
- char *ptr = output_buffer;
- unsigned int reg_cont;
-
- /* Send trap type (converted to signal) */
-
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- if (((reg.exs & 0xff00) >> 8) == 0xc) {
-
- /* Some kind of hardware watchpoint triggered. Find which one
- and determine its type (read/write/access). */
- int S, bp, trig_bits = 0, rw_bits = 0;
- int trig_mask = 0;
- unsigned int *bp_d_regs = &sreg.s3_3;
- /* In a lot of cases, the stopped data address will simply be EDA.
- In some cases, we adjust it to match the watched data range.
- (We don't want to change the actual EDA though). */
- unsigned int stopped_data_address;
- /* The S field of EXS. */
- S = (reg.exs & 0xffff0000) >> 16;
-
- if (S & 1) {
- /* Instruction watchpoint. */
- /* FIXME: Check against, and possibly adjust reported EDA. */
- } else {
- /* Data watchpoint. Find the one that triggered. */
- for (bp = 0; bp < 6; bp++) {
-
- /* Dx_RD, Dx_WR in the S field of EXS for this BP. */
- int bitpos_trig = 1 + bp * 2;
- /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
- int bitpos_config = 2 + bp * 4;
-
- /* Get read/write trig bits for this BP. */
- trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
-
- /* Read/write config bits for this BP. */
- rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
- if (trig_bits) {
- /* Sanity check: the BP shouldn't trigger for accesses
- that it isn't configured for. */
- if ((rw_bits == 0x1 && trig_bits != 0x1) ||
- (rw_bits == 0x2 && trig_bits != 0x2))
- panic("Invalid r/w trigging for this BP");
-
- /* Mark this BP as trigged for future reference. */
- trig_mask |= (1 << bp);
-
- if (reg.eda >= bp_d_regs[bp * 2] &&
- reg.eda <= bp_d_regs[bp * 2 + 1]) {
- /* EDA within range for this BP; it must be the one
- we're looking for. */
- stopped_data_address = reg.eda;
- break;
- }
- }
- }
- if (bp < 6) {
- /* Found a trigged BP with EDA within its configured data range. */
- } else if (trig_mask) {
- /* Something triggered, but EDA doesn't match any BP's range. */
- for (bp = 0; bp < 6; bp++) {
- /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
- int bitpos_config = 2 + bp * 4;
-
- /* Read/write config bits for this BP (needed later). */
- rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
-
- if (trig_mask & (1 << bp)) {
- /* EDA within 31 bytes of the configured start address? */
- if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
- /* Changing the reported address to match
- the start address of the first applicable BP. */
- stopped_data_address = bp_d_regs[bp * 2];
- break;
- } else {
- /* We continue since we might find another useful BP. */
- printk("EDA doesn't match trigged BP's range");
- }
- }
- }
- }
-
- /* No match yet? */
- BUG_ON(bp >= 6);
- /* Note that we report the type according to what the BP is configured
- for (otherwise we'd never report an 'awatch'), not according to how
- it trigged. We did check that the trigged bits match what the BP is
- configured for though. */
- if (rw_bits == 0x1) {
- /* read */
- strncpy(ptr, "rwatch", 6);
- ptr += 6;
- } else if (rw_bits == 0x2) {
- /* write */
- strncpy(ptr, "watch", 5);
- ptr += 5;
- } else if (rw_bits == 0x3) {
- /* access */
- strncpy(ptr, "awatch", 6);
- ptr += 6;
- } else {
- panic("Invalid r/w bits for this BP.");
- }
-
- *ptr++ = ':';
- /* Note that we don't read_register(EDA, ...) */
- ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
- *ptr++ = ';';
- }
- }
- /* Only send PC, frame and stack pointer. */
- read_register(PC, &reg_cont);
- ptr = hex_byte_pack(ptr, PC);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[PC]);
- *ptr++ = ';';
-
- read_register(R8, &reg_cont);
- ptr = hex_byte_pack(ptr, R8);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[R8]);
- *ptr++ = ';';
-
- read_register(SP, &reg_cont);
- ptr = hex_byte_pack(ptr, SP);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[SP]);
- *ptr++ = ';';
-
- /* Send ERP as well; this will save us an entire register fetch in some cases. */
- read_register(ERP, &reg_cont);
- ptr = hex_byte_pack(ptr, ERP);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[ERP]);
- *ptr++ = ';';
-
- /* null-terminate and send it off */
- *ptr = 0;
- putpacket(output_buffer);
-}
-
-/* Returns the size of an instruction that has a delay slot. */
-
-int insn_size(unsigned long pc)
-{
- unsigned short opcode = *(unsigned short *)pc;
- int size = 0;
-
- switch ((opcode & 0x0f00) >> 8) {
- case 0x0:
- case 0x9:
- case 0xb:
- size = 2;
- break;
- case 0xe:
- case 0xf:
- size = 6;
- break;
- case 0xd:
- /* Could be 4 or 6; check more bits. */
- if ((opcode & 0xff) == 0xff)
- size = 4;
- else
- size = 6;
- break;
- default:
- panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
- }
-
- return size;
-}
-
-void register_fixup(int sigval)
-{
- /* Compensate for ACR push at the beginning of exception handler. */
- reg.sp += 4;
-
- /* Standard case. */
- reg.pc = reg.erp;
- if (reg.erp & 0x1) {
- /* Delay slot bit set. Report as stopped on proper instruction. */
- if (reg.spc) {
- /* Rely on SPC if set. */
- reg.pc = reg.spc;
- } else {
- /* Calculate the PC from the size of the instruction
- that the delay slot we're in belongs to. */
- reg.pc += insn_size(reg.erp & ~1) - 1 ;
- }
- }
-
- if ((reg.exs & 0x3) == 0x0) {
- /* Bits 1 - 0 indicate the type of memory operation performed
- by the interrupted instruction. 0 means no memory operation,
- and EDA is undefined in that case. We zero it to avoid confusion. */
- reg.eda = 0;
- }
-
- if (sigval == SIGTRAP) {
- /* Break 8, single step or hardware breakpoint exception. */
-
- /* Check IDX field of EXS. */
- if (((reg.exs & 0xff00) >> 8) == 0x18) {
-
- /* Break 8. */
-
- /* Static (compiled) breakpoints must return to the next instruction
- in order to avoid infinite loops (default value of ERP). Dynamic
- (gdb-invoked) must subtract the size of the break instruction from
- the ERP so that the instruction that was originally in the break
- instruction's place will be run when we return from the exception. */
- if (!dynamic_bp) {
- /* Assuming that all breakpoints are dynamic from now on. */
- dynamic_bp = 1;
- } else {
-
- /* Only if not in a delay slot. */
- if (!(reg.erp & 0x1)) {
- reg.erp -= 2;
- reg.pc -= 2;
- }
- }
-
- } else if (((reg.exs & 0xff00) >> 8) == 0x3) {
- /* Single step. */
- /* Don't fiddle with S1. */
-
- } else if (((reg.exs & 0xff00) >> 8) == 0xc) {
-
- /* Hardware watchpoint exception. */
-
- /* SPC has been updated so that we will get a single step exception
- when we return, but we don't want that. */
- reg.spc = 0;
-
- /* Don't fiddle with S1. */
- }
-
- } else if (sigval == SIGINT) {
- /* Nothing special. */
- }
-}
-
-static void insert_watchpoint(char type, int addr, int len)
-{
- /* Breakpoint/watchpoint types (GDB terminology):
- 0 = memory breakpoint for instructions
- (not supported; done via memory write instead)
- 1 = hardware breakpoint for instructions (supported)
- 2 = write watchpoint (supported)
- 3 = read watchpoint (supported)
- 4 = access watchpoint (supported) */
-
- if (type < '1' || type > '4') {
- output_buffer[0] = 0;
- return;
- }
-
- /* Read watchpoints are set as access watchpoints, because of GDB's
- inability to deal with pure read watchpoints. */
- if (type == '3')
- type = '4';
-
- if (type == '1') {
- /* Hardware (instruction) breakpoint. */
- /* Bit 0 in BP_CTRL holds the configuration for I0. */
- if (sreg.s0_3 & 0x1) {
- /* Already in use. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
- /* Configure. */
- sreg.s1_3 = addr;
- sreg.s2_3 = (addr + len - 1);
- sreg.s0_3 |= 1;
- } else {
- int bp;
- unsigned int *bp_d_regs = &sreg.s3_3;
-
- /* The watchpoint allocation scheme is the simplest possible.
- For example, if a region is watched for read and
- a write watch is requested, a new watchpoint will
- be used. Also, if a watch for a region that is already
- covered by one or more existing watchpoints, a new
- watchpoint will be used. */
-
- /* First, find a free data watchpoint. */
- for (bp = 0; bp < 6; bp++) {
- /* Each data watchpoint's control registers occupy 2 bits
- (hence the 3), starting at bit 2 for D0 (hence the 2)
- with 4 bits between for each watchpoint (yes, the 4). */
- if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
- break;
- }
- }
-
- if (bp > 5) {
- /* We're out of watchpoints. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
-
- /* Configure the control register first. */
- if (type == '3' || type == '4') {
- /* Trigger on read. */
- sreg.s0_3 |= (1 << (2 + bp * 4));
- }
- if (type == '2' || type == '4') {
- /* Trigger on write. */
- sreg.s0_3 |= (2 << (2 + bp * 4));
- }
-
- /* Ugly pointer arithmetics to configure the watched range. */
- bp_d_regs[bp * 2] = addr;
- bp_d_regs[bp * 2 + 1] = (addr + len - 1);
- }
-
- /* Set the S1 flag to enable watchpoints. */
- reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- gdb_cris_strcpy(output_buffer, "OK");
-}
-
-static void remove_watchpoint(char type, int addr, int len)
-{
- /* Breakpoint/watchpoint types:
- 0 = memory breakpoint for instructions
- (not supported; done via memory write instead)
- 1 = hardware breakpoint for instructions (supported)
- 2 = write watchpoint (supported)
- 3 = read watchpoint (supported)
- 4 = access watchpoint (supported) */
- if (type < '1' || type > '4') {
- output_buffer[0] = 0;
- return;
- }
-
- /* Read watchpoints are set as access watchpoints, because of GDB's
- inability to deal with pure read watchpoints. */
- if (type == '3')
- type = '4';
-
- if (type == '1') {
- /* Hardware breakpoint. */
- /* Bit 0 in BP_CTRL holds the configuration for I0. */
- if (!(sreg.s0_3 & 0x1)) {
- /* Not in use. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
- /* Deconfigure. */
- sreg.s1_3 = 0;
- sreg.s2_3 = 0;
- sreg.s0_3 &= ~1;
- } else {
- int bp;
- unsigned int *bp_d_regs = &sreg.s3_3;
- /* Try to find a watchpoint that is configured for the
- specified range, then check that read/write also matches. */
-
- /* Ugly pointer arithmetic, since I cannot rely on a
- single switch (addr) as there may be several watchpoints with
- the same start address for example. */
-
- for (bp = 0; bp < 6; bp++) {
- if (bp_d_regs[bp * 2] == addr &&
- bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
- /* Matching range. */
- int bitpos = 2 + bp * 4;
- int rw_bits;
-
- /* Read/write bits for this BP. */
- rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
-
- if ((type == '3' && rw_bits == 0x1) ||
- (type == '2' && rw_bits == 0x2) ||
- (type == '4' && rw_bits == 0x3)) {
- /* Read/write matched. */
- break;
- }
- }
- }
-
- if (bp > 5) {
- /* No watchpoint matched. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
-
- /* Found a matching watchpoint. Now, deconfigure it by
- both disabling read/write in bp_ctrl and zeroing its
- start/end addresses. */
- sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
- bp_d_regs[bp * 2] = 0;
- bp_d_regs[bp * 2 + 1] = 0;
- }
-
- /* Note that we don't clear the S1 flag here. It's done when continuing. */
- gdb_cris_strcpy(output_buffer, "OK");
-}
-
-
-
-/* All expected commands are sent from remote.c. Send a response according
- to the description in remote.c. */
-void
-handle_exception(int sigval)
-{
- /* Avoid warning of not used. */
-
- USEDFUN(handle_exception);
- USEDVAR(internal_stack[0]);
-
- register_fixup(sigval);
-
- /* Send response. */
- stub_is_stopped(sigval);
-
- for (;;) {
- output_buffer[0] = '\0';
- getpacket(input_buffer);
- switch (input_buffer[0]) {
- case 'g':
- /* Read registers: g
- Success: Each byte of register data is described by two hex digits.
- Registers are in the internal order for GDB, and the bytes
- in a register are in the same order the machine uses.
- Failure: void. */
- {
- char *buf;
- /* General and special registers. */
- buf = mem2hex(output_buffer, (char *)&reg, sizeof(registers));
- /* Support registers. */
- /* -1 because of the null termination that mem2hex adds. */
- mem2hex(buf,
- (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
- 16 * sizeof(unsigned int));
- break;
- }
- case 'G':
- /* Write registers. GXX..XX
- Each byte of register data is described by two hex digits.
- Success: OK
- Failure: E08. */
- /* General and special registers. */
- if (hex2bin((char *)&reg, &input_buffer[1], sizeof(registers)))
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- /* Support registers. */
- else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
- &input_buffer[1] + sizeof(registers),
- 16 * sizeof(unsigned int)))
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- else
- gdb_cris_strcpy(output_buffer, "OK");
- break;
-
- case 'P':
- /* Write register. Pn...=r...
- Write register n..., hex value without 0x, with value r...,
- which contains a hex value without 0x and two hex digits
- for each byte in the register (target byte order). P1f=11223344 means
- set register 31 to 44332211.
- Success: OK
- Failure: E02, E05 */
- {
- char *suffix;
- int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
- int status;
-
- status = write_register(regno, suffix+1);
-
- switch (status) {
- case E02:
- /* Do not support read-only registers. */
- gdb_cris_strcpy(output_buffer, error_message[E02]);
- break;
- case E05:
- /* Do not support non-existing registers. */
- gdb_cris_strcpy(output_buffer, error_message[E05]);
- break;
- case E08:
- /* Invalid parameter. */
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- break;
- default:
- /* Valid register number. */
- gdb_cris_strcpy(output_buffer, "OK");
- break;
- }
- }
- break;
-
- case 'm':
- /* Read from memory. mAA..AA,LLLL
- AA..AA is the address and LLLL is the length.
- Success: XX..XX is the memory content. Can be fewer bytes than
- requested if only part of the data may be read. m6000120a,6c means
- retrieve 108 byte from base address 6000120a.
- Failure: void. */
- {
- char *suffix;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
- &suffix, 16);
- int len = gdb_cris_strtol(suffix+1, 0, 16);
-
- /* Bogus read (i.e. outside the kernel's
- segment)? . */
- if (!((unsigned int)addr >= 0xc0000000 &&
- (unsigned int)addr < 0xd0000000))
- addr = NULL;
-
- mem2hex(output_buffer, addr, len);
- }
- break;
-
- case 'X':
- /* Write to memory. XAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the binary data.
- Success: OK
- Failure: void. */
- case 'M':
- /* Write to memory. MAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the hexadecimal data.
- Success: OK
- Failure: E08. */
- {
- char *lenptr;
- char *dataptr;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
- &lenptr, 16);
- int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
- if (*lenptr == ',' && *dataptr == ':') {
- if (input_buffer[0] == 'M') {
- if (hex2bin(addr, dataptr + 1, len))
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- else
- gdb_cris_strcpy(output_buffer, "OK");
- } else /* X */ {
- bin2mem(addr, dataptr + 1, len);
- gdb_cris_strcpy(output_buffer, "OK");
- }
- } else {
- gdb_cris_strcpy(output_buffer, error_message[E06]);
- }
- }
- break;
-
- case 'c':
- /* Continue execution. cAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address.
- Success: return to the executing thread.
- Failure: will never know. */
-
- if (input_buffer[1] != '\0') {
- /* FIXME: Doesn't handle address argument. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- break;
- }
-
- /* Before continuing, make sure everything is set up correctly. */
-
- /* Set the SPC to some unlikely value. */
- reg.spc = 0;
- /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
- S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
- are reserved, so don't check against those). */
- if ((sreg.s0_3 & 0x3fff) == 0) {
- reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
- }
-
- return;
-
- case 's':
- /* Step. sAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address. Success: return to the
- executing thread. Failure: will never know. */
-
- if (input_buffer[1] != '\0') {
- /* FIXME: Doesn't handle address argument. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- break;
- }
-
- /* Set the SPC to PC, which is where we'll return
- (deduced previously). */
- reg.spc = reg.pc;
-
- /* Set the S1 (first stacked, not current) flag, which will
- kick into action when we rfe. */
- reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- return;
-
- case 'Z':
-
- /* Insert breakpoint or watchpoint, Ztype,addr,length.
- Remote protocol says: A remote target shall return an empty string
- for an unrecognized breakpoint or watchpoint packet type. */
- {
- char *lenptr;
- char *dataptr;
- int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
- int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
- char type = input_buffer[1];
-
- insert_watchpoint(type, addr, len);
- break;
- }
-
- case 'z':
- /* Remove breakpoint or watchpoint, Ztype,addr,length.
- Remote protocol says: A remote target shall return an empty string
- for an unrecognized breakpoint or watchpoint packet type. */
- {
- char *lenptr;
- char *dataptr;
- int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
- int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
- char type = input_buffer[1];
-
- remove_watchpoint(type, addr, len);
- break;
- }
-
-
- case '?':
- /* The last signal which caused a stop. ?
- Success: SAA, where AA is the signal number.
- Failure: void. */
- output_buffer[0] = 'S';
- output_buffer[1] = hex_asc_hi(sigval);
- output_buffer[2] = hex_asc_lo(sigval);
- output_buffer[3] = 0;
- break;
-
- case 'D':
- /* Detach from host. D
- Success: OK, and return to the executing thread.
- Failure: will never know */
- putpacket("OK");
- return;
-
- case 'k':
- case 'r':
- /* kill request or reset request.
- Success: restart of target.
- Failure: will never know. */
- kill_restart();
- break;
-
- case 'C':
- case 'S':
- case '!':
- case 'R':
- case 'd':
- /* Continue with signal sig. Csig;AA..AA
- Step with signal sig. Ssig;AA..AA
- Use the extended remote protocol. !
- Restart the target system. R0
- Toggle debug flag. d
- Search backwards. tAA:PP,MM
- Not supported: E04 */
-
- /* FIXME: What's the difference between not supported
- and ignored (below)? */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- break;
-
- default:
- /* The stub should ignore other request and send an empty
- response ($#<checksum>). This way we can extend the protocol and GDB
- can tell whether the stub it is talking to uses the old or the new. */
- output_buffer[0] = 0;
- break;
- }
- putpacket(output_buffer);
- }
-}
-
-void
-kgdb_init(void)
-{
- reg_intr_vect_rw_mask intr_mask;
- reg_ser_rw_intr_mask ser_intr_mask;
-
- /* Configure the kgdb serial port. */
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser0 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser1 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser2 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser3 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
-#endif
-
-}
-/* Performs a complete re-start from scratch. */
-static void
-kill_restart(void)
-{
- machine_restart("");
-}
-
-/* Use this static breakpoint in the start-up only. */
-
-void
-breakpoint(void)
-{
- kgdb_started = 1;
- dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */
- __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
-}
-
-/****************************** End of file **********************************/
diff --git a/arch/cris/arch-v32/kernel/kgdb_asm.S b/arch/cris/arch-v32/kernel/kgdb_asm.S
deleted file mode 100644
index c26ea6b0e334..000000000000
--- a/arch/cris/arch-v32/kernel/kgdb_asm.S
+++ /dev/null
@@ -1,552 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2004 Axis Communications AB
- *
- * Code for handling break 8, hardware breakpoint, single step, and serial
- * port exceptions for kernel debugging purposes.
- */
-
-#include <hwregs/intr_vect.h>
-
- ;; Exported functions.
- .globl kgdb_handle_exception
-
-kgdb_handle_exception:
-
-;; Create a register image of the caller.
-;;
-;; First of all, save the ACR on the stack since we need it for address calculations.
-;; We put it into the register struct later.
-
- subq 4, $sp
- move.d $acr, [$sp]
-
-;; Now we are free to use ACR all we want.
-;; If we were running this handler with interrupts on, we would have to be careful
-;; to save and restore CCS manually, but since we aren't we treat it like every other
-;; register.
-
- move.d reg, $acr
- move.d $r0, [$acr] ; Save R0 (start of register struct)
- addq 4, $acr
- move.d $r1, [$acr] ; Save R1
- addq 4, $acr
- move.d $r2, [$acr] ; Save R2
- addq 4, $acr
- move.d $r3, [$acr] ; Save R3
- addq 4, $acr
- move.d $r4, [$acr] ; Save R4
- addq 4, $acr
- move.d $r5, [$acr] ; Save R5
- addq 4, $acr
- move.d $r6, [$acr] ; Save R6
- addq 4, $acr
- move.d $r7, [$acr] ; Save R7
- addq 4, $acr
- move.d $r8, [$acr] ; Save R8
- addq 4, $acr
- move.d $r9, [$acr] ; Save R9
- addq 4, $acr
- move.d $r10, [$acr] ; Save R10
- addq 4, $acr
- move.d $r11, [$acr] ; Save R11
- addq 4, $acr
- move.d $r12, [$acr] ; Save R12
- addq 4, $acr
- move.d $r13, [$acr] ; Save R13
- addq 4, $acr
- move.d $sp, [$acr] ; Save SP (R14)
- addq 4, $acr
-
- ;; The ACR register is already saved on the stack, so pop it from there.
- move.d [$sp],$r0
- move.d $r0, [$acr]
- addq 4, $acr
-
- move $bz, [$acr]
- addq 1, $acr
- move $vr, [$acr]
- addq 1, $acr
- move $pid, [$acr]
- addq 4, $acr
- move $srs, [$acr]
- addq 1, $acr
- move $wz, [$acr]
- addq 2, $acr
- move $exs, [$acr]
- addq 4, $acr
- move $eda, [$acr]
- addq 4, $acr
- move $mof, [$acr]
- addq 4, $acr
- move $dz, [$acr]
- addq 4, $acr
- move $ebp, [$acr]
- addq 4, $acr
- move $erp, [$acr]
- addq 4, $acr
- move $srp, [$acr]
- addq 4, $acr
- move $nrp, [$acr]
- addq 4, $acr
- move $ccs, [$acr]
- addq 4, $acr
- move $usp, [$acr]
- addq 4, $acr
- move $spc, [$acr]
- addq 4, $acr
-
-;; Skip the pseudo-PC.
- addq 4, $acr
-
-;; Save the support registers in bank 0 - 3.
- clear.d $r1 ; Bank counter
- move.d sreg, $acr
-
-;; Bank 0
- move $r1, $srs
- nop
- nop
- nop
- move $s0, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s1, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s2, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s3, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s4, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s5, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s6, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s7, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s8, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s9, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s10, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s11, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s12, $r0
- move.d $r0, [$acr]
- addq 4, $acr
-
- ;; Nothing in S13 - S15, bank 0
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
-
-;; Bank 1 and bank 2 have the same layout, hence the loop.
- addq 1, $r1
-1:
- move $r1, $srs
- nop
- nop
- nop
- move $s0, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s1, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s2, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s3, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s4, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s5, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s6, $r0
- move.d $r0, [$acr]
- addq 4, $acr
-
- ;; Nothing in S7 - S15, bank 1 and 2
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
-
- addq 1, $r1
- cmpq 3, $r1
- bne 1b
- nop
-
-;; Bank 3
- move $r1, $srs
- nop
- nop
- nop
- move $s0, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s1, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s2, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s3, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s4, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s5, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s6, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s7, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s8, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s9, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s10, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s11, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s12, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s13, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s14, $r0
- move.d $r0, [$acr]
- addq 4, $acr
-;; Nothing in S15, bank 3
- clear.d [$acr]
- addq 4, $acr
-
-;; Check what got us here: get IDX field of EXS.
- move $exs, $r10
- and.d 0xff00, $r10
- lsrq 8, $r10
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- cmp.d SER0_INTR_VECT, $r10 ; IRQ for serial port 0
- beq sigint
- nop
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- cmp.d SER1_INTR_VECT, $r10 ; IRQ for serial port 1
- beq sigint
- nop
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- cmp.d SER2_INTR_VECT, $r10 ; IRQ for serial port 2
- beq sigint
- nop
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- cmp.d SER3_INTR_VECT, $r10 ; IRQ for serial port 3
- beq sigint
- nop
-#endif
-;; Multiple interrupt must be due to serial break.
- cmp.d 0x30, $r10 ; Multiple interrupt
- beq sigint
- nop
-;; Neither of those? Then it's a sigtrap.
- ba handle_comm
- moveq 5, $r10 ; Set SIGTRAP (delay slot)
-
-sigint:
- ;; Serial interrupt; get character
- jsr getDebugChar
- nop ; Delay slot
- cmp.b 3, $r10 ; \003 (Ctrl-C)?
- bne return ; No, get out of here
- nop
- moveq 2, $r10 ; Set SIGINT
-
-;;
-;; Handle the communication
-;;
-handle_comm:
- move.d internal_stack+1020, $sp ; Use the internal stack which grows upwards
- jsr handle_exception ; Interactive routine
- nop
-
-;;
-;; Return to the caller
-;;
-return:
-
-;; First of all, write the support registers.
- clear.d $r1 ; Bank counter
- move.d sreg, $acr
-
-;; Bank 0
- move $r1, $srs
- nop
- nop
- nop
- move.d [$acr], $r0
- move $r0, $s0
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s1
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s2
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s3
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s4
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s5
- addq 4, $acr
-
-;; Nothing in S6 - S7, bank 0.
- addq 4, $acr
- addq 4, $acr
-
- move.d [$acr], $r0
- move $r0, $s8
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s9
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s10
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s11
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s12
- addq 4, $acr
-
-;; Nothing in S13 - S15, bank 0
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
-
-;; Bank 1 and bank 2 have the same layout, hence the loop.
- addq 1, $r1
-2:
- move $r1, $srs
- nop
- nop
- nop
- move.d [$acr], $r0
- move $r0, $s0
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s1
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s2
- addq 4, $acr
-
-;; S3 (MM_CAUSE) is read-only.
- addq 4, $acr
-
- move.d [$acr], $r0
- move $r0, $s4
- addq 4, $acr
-
-;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.)
- addq 4, $acr
- addq 4, $acr
-
-;; Nothing in S7 - S15, bank 1 and 2
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
-
- addq 1, $r1
- cmpq 3, $r1
- bne 2b
- nop
-
-;; Bank 3
- move $r1, $srs
- nop
- nop
- nop
- move.d [$acr], $r0
- move $r0, $s0
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s1
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s2
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s3
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s4
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s5
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s6
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s7
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s8
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s9
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s10
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s11
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s12
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s13
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s14
- addq 4, $acr
-
-;; Nothing in S15, bank 3
- addq 4, $acr
-
-;; Now, move on to the regular register restoration process.
-
- move.d reg, $acr ; Reset ACR to point at the beginning of the register image
- move.d [$acr], $r0 ; Restore R0
- addq 4, $acr
- move.d [$acr], $r1 ; Restore R1
- addq 4, $acr
- move.d [$acr], $r2 ; Restore R2
- addq 4, $acr
- move.d [$acr], $r3 ; Restore R3
- addq 4, $acr
- move.d [$acr], $r4 ; Restore R4
- addq 4, $acr
- move.d [$acr], $r5 ; Restore R5
- addq 4, $acr
- move.d [$acr], $r6 ; Restore R6
- addq 4, $acr
- move.d [$acr], $r7 ; Restore R7
- addq 4, $acr
- move.d [$acr], $r8 ; Restore R8
- addq 4, $acr
- move.d [$acr], $r9 ; Restore R9
- addq 4, $acr
- move.d [$acr], $r10 ; Restore R10
- addq 4, $acr
- move.d [$acr], $r11 ; Restore R11
- addq 4, $acr
- move.d [$acr], $r12 ; Restore R12
- addq 4, $acr
- move.d [$acr], $r13 ; Restore R13
-
-;;
-;; We restore all registers, even though some of them probably haven't changed.
-;;
-
- addq 4, $acr
- move.d [$acr], $sp ; Restore SP (R14)
-
- ;; ACR cannot be restored just yet.
- addq 8, $acr
-
- ;; Skip BZ, VR.
- addq 2, $acr
-
- move [$acr], $pid ; Restore PID
- addq 4, $acr
- move [$acr], $srs ; Restore SRS
- nop
- nop
- nop
- addq 1, $acr
-
- ;; Skip WZ.
- addq 2, $acr
-
- move [$acr], $exs ; Restore EXS.
- addq 4, $acr
- move [$acr], $eda ; Restore EDA.
- addq 4, $acr
- move [$acr], $mof ; Restore MOF.
-
- ;; Skip DZ.
- addq 8, $acr
-
- move [$acr], $ebp ; Restore EBP.
- addq 4, $acr
- move [$acr], $erp ; Restore ERP.
- addq 4, $acr
- move [$acr], $srp ; Restore SRP.
- addq 4, $acr
- move [$acr], $nrp ; Restore NRP.
- addq 4, $acr
- move [$acr], $ccs ; Restore CCS like an ordinary register.
- addq 4, $acr
- move [$acr], $usp ; Restore USP
- addq 4, $acr
- move [$acr], $spc ; Restore SPC
- ; No restoration of pseudo-PC of course.
-
- move.d reg, $acr ; Reset ACR to point at the beginning of the register image
- add.d 15*4, $acr
- move.d [$acr], $acr ; Finally, restore ACR.
- rete ; Same as jump ERP
- rfe ; Shifts CCS
diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c
deleted file mode 100644
index a02f276d0ed4..000000000000
--- a/arch/cris/arch-v32/kernel/process.c
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2000-2003 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Mikael Starvik (starvik@axis.com)
- * Tobias Anderberg (tobiasa@axis.com), CRISv32 port.
- *
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/timer_defs.h>
-#include <hwregs/intr_vect_defs.h>
-#include <linux/ptrace.h>
-
-extern void stop_watchdog(void);
-
-/* We use this if we don't have any better idle routine. */
-void default_idle(void)
-{
- local_irq_enable();
- /* Halt until exception. */
- __asm__ volatile("halt");
-}
-
-/*
- * Free current thread data structures etc..
- */
-
-extern void deconfigure_bp(long pid);
-void exit_thread(struct task_struct *tsk)
-{
- deconfigure_bp(tsk->pid);
-}
-
-/*
- * If the watchdog is enabled, disable interrupts and enter an infinite loop.
- * The watchdog will reset the CPU after 0.1s. If the watchdog isn't enabled
- * then enable it and wait.
- */
-extern void arch_enable_nmi(void);
-
-void
-hard_reset_now(void)
-{
- /*
- * Don't declare this variable elsewhere. We don't want any other
- * code to know about it than the watchdog handler in entry.S and
- * this code, implementing hard reset through the watchdog.
- */
-#if defined(CONFIG_ETRAX_WATCHDOG)
- extern int cause_of_death;
-#endif
-
- printk("*** HARD RESET ***\n");
- local_irq_disable();
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
- cause_of_death = 0xbedead;
-#else
-{
- reg_timer_rw_wd_ctrl wd_ctrl = {0};
-
- stop_watchdog();
-
- wd_ctrl.key = 16; /* Arbitrary key. */
- wd_ctrl.cnt = 1; /* Minimum time. */
- wd_ctrl.cmd = regk_timer_start;
-
- arch_enable_nmi();
- REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
-}
-#endif
-
- while (1)
- ; /* Wait for reset. */
-}
-
-/*
- * Setup the child's kernel stack with a pt_regs and call switch_stack() on it.
- * It will be unnested during _resume and _ret_from_sys_call when the new thread
- * is scheduled.
- *
- * Also setup the thread switching structure which is used to keep
- * thread-specific data during _resumes.
- */
-
-extern asmlinkage void ret_from_fork(void);
-extern asmlinkage void ret_from_kernel_thread(void);
-
-int
-copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long arg, struct task_struct *p)
-{
- struct pt_regs *childregs = task_pt_regs(p);
- struct switch_stack *swstack = ((struct switch_stack *) childregs) - 1;
-
- /*
- * Put the pt_regs structure at the end of the new kernel stack page and
- * fix it up. Note: the task_struct doubles as the kernel stack for the
- * task.
- */
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(swstack, 0,
- sizeof(struct switch_stack) + sizeof(struct pt_regs));
- swstack->r1 = usp;
- swstack->r2 = arg;
- childregs->ccs = 1 << (I_CCS_BITNR + CCS_SHIFT);
- swstack->return_ip = (unsigned long) ret_from_kernel_thread;
- p->thread.ksp = (unsigned long) swstack;
- p->thread.usp = 0;
- return 0;
- }
- *childregs = *current_pt_regs(); /* Struct copy of pt_regs. */
- childregs->r10 = 0; /* Child returns 0 after a fork/clone. */
-
- /* Set a new TLS ?
- * The TLS is in $mof because it is the 5th argument to sys_clone.
- */
- if (p->mm && (clone_flags & CLONE_SETTLS)) {
- task_thread_info(p)->tls = childregs->mof;
- }
-
- /* Put the switch stack right below the pt_regs. */
-
- /* Parameter to ret_from_sys_call. 0 is don't restart the syscall. */
- swstack->r9 = 0;
-
- /*
- * We want to return into ret_from_sys_call after the _resume.
- * ret_from_fork will call ret_from_sys_call.
- */
- swstack->return_ip = (unsigned long) ret_from_fork;
-
- /* Fix the user-mode and kernel-mode stackpointer. */
- p->thread.usp = usp ?: rdusp();
- p->thread.ksp = (unsigned long) swstack;
-
- return 0;
-}
-
-unsigned long
-get_wchan(struct task_struct *p)
-{
- /* TODO */
- return 0;
-}
-#undef last_sched
-#undef first_sched
-
-void show_regs(struct pt_regs * regs)
-{
- unsigned long usp = rdusp();
-
- show_regs_print_info(KERN_DEFAULT);
-
- printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
- regs->erp, regs->srp, regs->ccs, usp, regs->mof);
-
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
-
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
-
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
-
- printk("r12: %08lx r13: %08lx oR10: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10);
-}
diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c
deleted file mode 100644
index ccac1aaadc8a..000000000000
--- a/arch/cris/arch-v32/kernel/ptrace.c
+++ /dev/null
@@ -1,492 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2000-2007, Axis Communications AB.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/signal.h>
-#include <linux/security.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <arch/hwregs/supp_reg.h>
-
-/*
- * Determines which bits in CCS the user has access to.
- * 1 = access, 0 = no access.
- */
-#define CCS_MASK 0x00087c00 /* SXNZVC */
-
-#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT))
-
-static int put_debugreg(long pid, unsigned int regno, long data);
-static long get_debugreg(long pid, unsigned int regno);
-static unsigned long get_pseudo_pc(struct task_struct *child);
-void deconfigure_bp(long pid);
-
-extern unsigned long cris_signal_return_page;
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-long get_reg(struct task_struct *task, unsigned int regno)
-{
- /* USP is a special case, it's not in the pt_regs struct but
- * in the tasks thread struct
- */
- unsigned long ret;
-
- if (regno <= PT_EDA)
- ret = ((unsigned long *)task_pt_regs(task))[regno];
- else if (regno == PT_USP)
- ret = task->thread.usp;
- else if (regno == PT_PPC)
- ret = get_pseudo_pc(task);
- else if (regno <= PT_MAX)
- ret = get_debugreg(task->pid, regno);
- else
- ret = 0;
-
- return ret;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-int put_reg(struct task_struct *task, unsigned int regno, unsigned long data)
-{
- if (regno <= PT_EDA)
- ((unsigned long *)task_pt_regs(task))[regno] = data;
- else if (regno == PT_USP)
- task->thread.usp = data;
- else if (regno == PT_PPC) {
- /* Write pseudo-PC to ERP only if changed. */
- if (data != get_pseudo_pc(task))
- task_pt_regs(task)->erp = data;
- } else if (regno <= PT_MAX)
- return put_debugreg(task->pid, regno, data);
- else
- return -1;
- return 0;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- unsigned long tmp;
-
- /*
- * Set up SPC if not set already (in which case we have no other
- * choice but to trust it).
- */
- if (!get_reg(child, PT_SPC)) {
- /* In case we're stopped in a delay slot. */
- tmp = get_reg(child, PT_ERP) & ~1;
- put_reg(child, PT_SPC, tmp);
- }
- tmp = get_reg(child, PT_CCS) | SBIT_USER;
- put_reg(child, PT_CCS, tmp);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- put_reg(child, PT_SPC, 0);
-
- if (!get_debugreg(child->pid, PT_BP_CTRL)) {
- unsigned long tmp;
- /* If no h/w bp configured, disable S bit. */
- tmp = get_reg(child, PT_CCS) & ~SBIT_USER;
- put_reg(child, PT_CCS, tmp);
- }
-}
-
-/*
- * Called by kernel/ptrace.c when detaching.
- *
- * Make sure the single step bit is not set.
- */
-void
-ptrace_disable(struct task_struct *child)
-{
- /* Deconfigure SPC and S-bit. */
- user_disable_single_step(child);
- put_reg(child, PT_SPC, 0);
-
- /* Deconfigure any watchpoints associated with the child. */
- deconfigure_bp(child->pid);
-}
-
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned int regno = addr >> 2;
- unsigned long __user *datap = (unsigned long __user *)data;
-
- switch (request) {
- /* Read word at location address. */
- case PTRACE_PEEKTEXT:
- case PTRACE_PEEKDATA: {
- unsigned long tmp;
- int copied;
-
- ret = -EIO;
-
- /* The signal trampoline page is outside the normal user-addressable
- * space but still accessible. This is hack to make it possible to
- * access the signal handler code in GDB.
- */
- if ((addr & PAGE_MASK) == cris_signal_return_page) {
- /* The trampoline page is globally mapped, no page table to traverse.*/
- tmp = *(unsigned long*)addr;
- } else {
- copied = ptrace_access_vm(child, addr, &tmp, sizeof(tmp), FOLL_FORCE);
-
- if (copied != sizeof(tmp))
- break;
- }
-
- ret = put_user(tmp,datap);
- break;
- }
-
- /* Read the word at location address in the USER area. */
- case PTRACE_PEEKUSR: {
- unsigned long tmp;
-
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- tmp = get_reg(child, regno);
- ret = put_user(tmp, datap);
- break;
- }
-
- /* Write the word at location address. */
- case PTRACE_POKETEXT:
- case PTRACE_POKEDATA:
- ret = generic_ptrace_pokedata(child, addr, data);
- break;
-
- /* Write the word at location address in the USER area. */
- case PTRACE_POKEUSR:
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- if (regno == PT_CCS) {
- /* don't allow the tracing process to change stuff like
- * interrupt enable, kernel/user bit, dma enables etc.
- */
- data &= CCS_MASK;
- data |= get_reg(child, PT_CCS) & ~CCS_MASK;
- }
- if (put_reg(child, regno, data))
- break;
- ret = 0;
- break;
-
- /* Get all GP registers from the child. */
- case PTRACE_GETREGS: {
- int i;
- unsigned long tmp;
-
- for (i = 0; i <= PT_MAX; i++) {
- tmp = get_reg(child, i);
-
- if (put_user(tmp, datap)) {
- ret = -EFAULT;
- goto out_tsk;
- }
-
- datap++;
- }
-
- ret = 0;
- break;
- }
-
- /* Set all GP registers in the child. */
- case PTRACE_SETREGS: {
- int i;
- unsigned long tmp;
-
- for (i = 0; i <= PT_MAX; i++) {
- if (get_user(tmp, datap)) {
- ret = -EFAULT;
- goto out_tsk;
- }
-
- if (i == PT_CCS) {
- tmp &= CCS_MASK;
- tmp |= get_reg(child, PT_CCS) & ~CCS_MASK;
- }
-
- put_reg(child, i, tmp);
- datap++;
- }
-
- ret = 0;
- break;
- }
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
-out_tsk:
- return ret;
-}
-
-void do_syscall_trace(void)
-{
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
-
- if (!(current->ptrace & PT_PTRACED))
- return;
-
- /* the 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
-
- /*
- * This isn't the same as continuing with a signal, but it will do for
- * normal use.
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-}
-
-/* Returns the size of an instruction that has a delay slot. */
-
-static int insn_size(struct task_struct *child, unsigned long pc)
-{
- unsigned long opcode;
- int copied;
- int opsize = 0;
-
- /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */
- copied = access_process_vm(child, pc, &opcode, sizeof(opcode), FOLL_FORCE);
- if (copied != sizeof(opcode))
- return 0;
-
- switch ((opcode & 0x0f00) >> 8) {
- case 0x0:
- case 0x9:
- case 0xb:
- opsize = 2;
- break;
- case 0xe:
- case 0xf:
- opsize = 6;
- break;
- case 0xd:
- /* Could be 4 or 6; check more bits. */
- if ((opcode & 0xff) == 0xff)
- opsize = 4;
- else
- opsize = 6;
- break;
- default:
- panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n",
- opcode, pc);
- }
-
- return opsize;
-}
-
-static unsigned long get_pseudo_pc(struct task_struct *child)
-{
- /* Default value for PC is ERP. */
- unsigned long pc = get_reg(child, PT_ERP);
-
- if (pc & 0x1) {
- unsigned long spc = get_reg(child, PT_SPC);
- /* Delay slot bit set. Report as stopped on proper
- instruction. */
- if (spc) {
- /* Rely on SPC if set. FIXME: We might want to check
- that EXS indicates we stopped due to a single-step
- exception. */
- pc = spc;
- } else {
- /* Calculate the PC from the size of the instruction
- that the delay slot we're in belongs to. */
- pc += insn_size(child, pc & ~1) - 1;
- }
- }
- return pc;
-}
-
-static long bp_owner = 0;
-
-/* Reachable from exit_thread in signal.c, so not static. */
-void deconfigure_bp(long pid)
-{
- int bp;
-
- /* Only deconfigure if the pid is the owner. */
- if (bp_owner != pid)
- return;
-
- for (bp = 0; bp < 6; bp++) {
- unsigned long tmp;
- /* Deconfigure start and end address (also gets rid of ownership). */
- put_debugreg(pid, PT_BP + 3 + (bp * 2), 0);
- put_debugreg(pid, PT_BP + 4 + (bp * 2), 0);
-
- /* Deconfigure relevant bits in control register. */
- tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4)));
- put_debugreg(pid, PT_BP_CTRL, tmp);
- }
- /* No owner now. */
- bp_owner = 0;
-}
-
-static int put_debugreg(long pid, unsigned int regno, long data)
-{
- int ret = 0;
- register int old_srs;
-
-#ifdef CONFIG_ETRAX_KGDB
- /* Ignore write, but pretend it was ok if value is 0
- (we don't want POKEUSR/SETREGS failing unnessecarily). */
- return (data == 0) ? ret : -1;
-#endif
-
- /* Simple owner management. */
- if (!bp_owner)
- bp_owner = pid;
- else if (bp_owner != pid) {
- /* Ignore write, but pretend it was ok if value is 0
- (we don't want POKEUSR/SETREGS failing unnessecarily). */
- return (data == 0) ? ret : -1;
- }
-
- /* Remember old SRS. */
- SPEC_REG_RD(SPEC_REG_SRS, old_srs);
- /* Switch to BP bank. */
- SUPP_BANK_SEL(BANK_BP);
-
- switch (regno - PT_BP) {
- case 0:
- SUPP_REG_WR(0, data); break;
- case 1:
- case 2:
- if (data)
- ret = -1;
- break;
- case 3:
- SUPP_REG_WR(3, data); break;
- case 4:
- SUPP_REG_WR(4, data); break;
- case 5:
- SUPP_REG_WR(5, data); break;
- case 6:
- SUPP_REG_WR(6, data); break;
- case 7:
- SUPP_REG_WR(7, data); break;
- case 8:
- SUPP_REG_WR(8, data); break;
- case 9:
- SUPP_REG_WR(9, data); break;
- case 10:
- SUPP_REG_WR(10, data); break;
- case 11:
- SUPP_REG_WR(11, data); break;
- case 12:
- SUPP_REG_WR(12, data); break;
- case 13:
- SUPP_REG_WR(13, data); break;
- case 14:
- SUPP_REG_WR(14, data); break;
- default:
- ret = -1;
- break;
- }
-
- /* Restore SRS. */
- SPEC_REG_WR(SPEC_REG_SRS, old_srs);
- /* Just for show. */
- NOP();
- NOP();
- NOP();
-
- return ret;
-}
-
-static long get_debugreg(long pid, unsigned int regno)
-{
- register int old_srs;
- register long data;
-
- if (pid != bp_owner) {
- return 0;
- }
-
- /* Remember old SRS. */
- SPEC_REG_RD(SPEC_REG_SRS, old_srs);
- /* Switch to BP bank. */
- SUPP_BANK_SEL(BANK_BP);
-
- switch (regno - PT_BP) {
- case 0:
- SUPP_REG_RD(0, data); break;
- case 1:
- case 2:
- /* error return value? */
- data = 0;
- break;
- case 3:
- SUPP_REG_RD(3, data); break;
- case 4:
- SUPP_REG_RD(4, data); break;
- case 5:
- SUPP_REG_RD(5, data); break;
- case 6:
- SUPP_REG_RD(6, data); break;
- case 7:
- SUPP_REG_RD(7, data); break;
- case 8:
- SUPP_REG_RD(8, data); break;
- case 9:
- SUPP_REG_RD(9, data); break;
- case 10:
- SUPP_REG_RD(10, data); break;
- case 11:
- SUPP_REG_RD(11, data); break;
- case 12:
- SUPP_REG_RD(12, data); break;
- case 13:
- SUPP_REG_RD(13, data); break;
- case 14:
- SUPP_REG_RD(14, data); break;
- default:
- /* error return value? */
- data = 0;
- }
-
- /* Restore SRS. */
- SPEC_REG_WR(SPEC_REG_SRS, old_srs);
- /* Just for show. */
- NOP();
- NOP();
- NOP();
-
- return data;
-}
diff --git a/arch/cris/arch-v32/kernel/setup.c b/arch/cris/arch-v32/kernel/setup.c
deleted file mode 100644
index a36372e35e96..000000000000
--- a/arch/cris/arch-v32/kernel/setup.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Display CPU info in /proc/cpuinfo.
- *
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <linux/seq_file.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <linux/param.h>
-
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-
-#ifdef CONFIG_PROC_FS
-
-#define HAS_FPU 0x0001
-#define HAS_MMU 0x0002
-#define HAS_ETHERNET100 0x0004
-#define HAS_TOKENRING 0x0008
-#define HAS_SCSI 0x0010
-#define HAS_ATA 0x0020
-#define HAS_USB 0x0040
-#define HAS_IRQ_BUG 0x0080
-#define HAS_MMU_BUG 0x0100
-
-struct cpu_info {
- char *cpu_model;
- unsigned short rev;
- unsigned short cache_size;
- unsigned short flags;
-};
-
-/* Some of these model are here for historical reasons only. */
-static struct cpu_info cpinfo[] = {
- {"ETRAX 1", 0, 0, 0},
- {"ETRAX 2", 1, 0, 0},
- {"ETRAX 3", 2, 0, 0},
- {"ETRAX 4", 3, 0, 0},
- {"Simulator", 7, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA},
- {"ETRAX 100", 8, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG},
- {"ETRAX 100", 9, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA},
-
- {"ETRAX 100LX", 10, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB
- | HAS_MMU | HAS_MMU_BUG},
-
- {"ETRAX 100LX v2", 11, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB
- | HAS_MMU},
-#ifdef CONFIG_ETRAXFS
- {"ETRAX FS", 32, 32, HAS_ETHERNET100 | HAS_ATA | HAS_MMU},
-#else
- {"ARTPEC-3", 32, 32, HAS_ETHERNET100 | HAS_MMU},
-#endif
- {"Unknown", 0, 0, 0}
-};
-
-int show_cpuinfo(struct seq_file *m, void *v)
-{
- int i;
- int cpu = (int)v - 1;
- unsigned long revision;
- struct cpu_info *info;
-
- info = &cpinfo[ARRAY_SIZE(cpinfo) - 1];
-
- revision = rdvr();
-
- for (i = 0; i < ARRAY_SIZE(cpinfo); i++) {
- if (cpinfo[i].rev == revision) {
- info = &cpinfo[i];
- break;
- }
- }
-
- seq_printf(m,
- "processor\t: %d\n"
- "cpu\t\t: CRIS\n"
- "cpu revision\t: %lu\n"
- "cpu model\t: %s\n"
- "cache size\t: %d KB\n"
- "fpu\t\t: %s\n"
- "mmu\t\t: %s\n"
- "mmu DMA bug\t: %s\n"
- "ethernet\t: %s Mbps\n"
- "token ring\t: %s\n"
- "scsi\t\t: %s\n"
- "ata\t\t: %s\n"
- "usb\t\t: %s\n"
- "bogomips\t: %lu.%02lu\n\n",
-
- cpu,
- revision,
- info->cpu_model,
- info->cache_size,
- info->flags & HAS_FPU ? "yes" : "no",
- info->flags & HAS_MMU ? "yes" : "no",
- info->flags & HAS_MMU_BUG ? "yes" : "no",
- info->flags & HAS_ETHERNET100 ? "10/100" : "10",
- info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no",
- info->flags & HAS_SCSI ? "yes" : "no",
- info->flags & HAS_ATA ? "yes" : "no",
- info->flags & HAS_USB ? "yes" : "no",
- (loops_per_jiffy * HZ + 500) / 500000,
- ((loops_per_jiffy * HZ + 500) / 5000) % 100);
-
- return 0;
-}
-
-#endif /* CONFIG_PROC_FS */
-
-void show_etrax_copyright(void)
-{
-#ifdef CONFIG_ETRAXFS
- printk(KERN_INFO "Linux/CRISv32 port on ETRAX FS "
- "(C) 2003, 2004 Axis Communications AB\n");
-#else
- printk(KERN_INFO "Linux/CRISv32 port on ARTPEC-3 "
- "(C) 2003-2009 Axis Communications AB\n");
-#endif
-}
-
-static struct i2c_board_info __initdata i2c_info[] = {
- {I2C_BOARD_INFO("camblock", 0x43)},
- {I2C_BOARD_INFO("tmp100", 0x48)},
- {I2C_BOARD_INFO("tmp100", 0x4A)},
- {I2C_BOARD_INFO("tmp100", 0x4C)},
- {I2C_BOARD_INFO("tmp100", 0x4D)},
- {I2C_BOARD_INFO("tmp100", 0x4E)},
-#ifdef CONFIG_RTC_DRV_PCF8563
- {I2C_BOARD_INFO("pcf8563", 0x51)},
-#endif
- {I2C_BOARD_INFO("pca9536", 0x41)},
- {I2C_BOARD_INFO("fnp300", 0x40)},
- {I2C_BOARD_INFO("fnp300", 0x42)},
- {I2C_BOARD_INFO("adc101", 0x54)},
-};
-
-static struct i2c_board_info __initdata i2c_info2[] = {
- {I2C_BOARD_INFO("camblock", 0x43)},
- {I2C_BOARD_INFO("tmp100", 0x48)},
- {I2C_BOARD_INFO("tmp100", 0x4A)},
- {I2C_BOARD_INFO("tmp100", 0x4C)},
- {I2C_BOARD_INFO("tmp100", 0x4D)},
- {I2C_BOARD_INFO("tmp100", 0x4E)},
- {I2C_BOARD_INFO("pca9536", 0x41)},
- {I2C_BOARD_INFO("fnp300", 0x40)},
- {I2C_BOARD_INFO("fnp300", 0x42)},
- {I2C_BOARD_INFO("adc101", 0x54)},
-};
-
-static struct i2c_board_info __initdata i2c_info3[] = {
- {I2C_BOARD_INFO("adc101", 0x54)},
-};
-
-static int __init etrax_init(void)
-{
- i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
- i2c_register_board_info(1, i2c_info2, ARRAY_SIZE(i2c_info2));
- i2c_register_board_info(2, i2c_info3, ARRAY_SIZE(i2c_info3));
- return 0;
-}
-arch_initcall(etrax_init);
diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c
deleted file mode 100644
index 4f2e3ba3bf40..000000000000
--- a/arch/cris/arch-v32/kernel/signal.c
+++ /dev/null
@@ -1,541 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/syscalls.h>
-#include <linux/vmalloc.h>
-
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <arch/hwregs/cpu_vect.h>
-
-extern unsigned long cris_signal_return_page;
-
-/*
- * A syscall in CRIS is really a "break 13" instruction, which is 2
- * bytes. The registers is manipulated so upon return the instruction
- * will be executed again.
- *
- * This relies on that PC points to the instruction after the break call.
- */
-#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->erp -= 2;
-
-/* Signal frames. */
-struct signal_frame {
- struct sigcontext sc;
- unsigned long extramask[_NSIG_WORDS - 1];
- unsigned char retcode[8]; /* Trampoline code. */
-};
-
-struct rt_signal_frame {
- struct siginfo *pinfo;
- void *puc;
- struct siginfo info;
- struct ucontext uc;
- unsigned char retcode[8]; /* Trampoline code. */
-};
-
-void do_signal(int restart, struct pt_regs *regs);
-void keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
- struct pt_regs *regs);
-
-static int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
-{
- unsigned int err = 0;
- unsigned long old_usp;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- /*
- * Restore the registers from &sc->regs. sc is already checked
- * for VERIFY_READ since the signal_frame was previously
- * checked in sys_sigreturn().
- */
- if (__copy_from_user(regs, sc, sizeof(struct pt_regs)))
- goto badframe;
-
- /* Make that the user-mode flag is set. */
- regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT));
-
- /* Don't perform syscall restarting */
- regs->exs = -1;
-
- /* Restore the old USP. */
- err |= __get_user(old_usp, &sc->usp);
- wrusp(old_usp);
-
- return err;
-
-badframe:
- return 1;
-}
-
-asmlinkage int sys_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- sigset_t set;
- struct signal_frame __user *frame;
- unsigned long oldspc = regs->spc;
- unsigned long oldccs = regs->ccs;
-
- frame = (struct signal_frame *) rdusp();
-
- /*
- * Since the signal is stacked on a dword boundary, the frame
- * should be dword aligned here as well. It it's not, then the
- * user is trying some funny business.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
-
- if (__get_user(set.sig[0], &frame->sc.oldmask) ||
- (_NSIG_WORDS > 1 && __copy_from_user(&set.sig[1],
- frame->extramask,
- sizeof(frame->extramask))))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->sc))
- goto badframe;
-
- keep_debug_flags(oldccs, oldspc, regs);
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- sigset_t set;
- struct rt_signal_frame __user *frame;
- unsigned long oldspc = regs->spc;
- unsigned long oldccs = regs->ccs;
-
- frame = (struct rt_signal_frame *) rdusp();
-
- /*
- * Since the signal is stacked on a dword boundary, the frame
- * should be dword aligned here as well. It it's not, then the
- * user is trying some funny business.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
-
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- keep_debug_flags(oldccs, oldspc, regs);
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/* Setup a signal frame. */
-static int
-setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
- unsigned long mask)
-{
- int err;
- unsigned long usp;
-
- err = 0;
- usp = rdusp();
-
- /*
- * Copy the registers. They are located first in sc, so it's
- * possible to use sc directly.
- */
- err |= __copy_to_user(sc, regs, sizeof(struct pt_regs));
-
- err |= __put_user(mask, &sc->oldmask);
- err |= __put_user(usp, &sc->usp);
-
- return err;
-}
-
-/* Figure out where to put the new signal frame - usually on the stack. */
-static inline void __user *
-get_sigframe(struct ksignal *ksig, size_t frame_size)
-{
- unsigned long sp = sigsp(rdusp(), ksig);
-
- /* Make sure the frame is dword-aligned. */
- sp &= ~3;
-
- return (void __user *)(sp - frame_size);
-}
-
-/* Grab and setup a signal frame.
- *
- * Basically a lot of state-info is stacked, and arranged for the
- * user-mode program to return to the kernel using either a trampiline
- * which performs the syscall sigreturn(), or a provided user-mode
- * trampoline.
- */
-static int
-setup_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- int err;
- unsigned long return_ip;
- struct signal_frame __user *frame;
-
- err = 0;
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
-
- if (err)
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- err |= __copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask));
- }
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up to return from user-space. If provided, use a stub
- * already located in user-space.
- */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long)ksig->ka.sa.sa_restorer;
- } else {
- /* Trampoline - the desired return ip is in the signal return page. */
- return_ip = cris_signal_return_page;
-
- /*
- * This is movu.w __NR_sigreturn, r9; break 13;
- *
- * WE DO NOT USE IT ANY MORE! It's only left here for historical
- * reasons and because gdb uses it as a signature to notice
- * signal handler stack frames.
- */
- err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
- err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2));
- err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up registers for signal handler.
- *
- * Where the code enters now.
- * Where the code enter later.
- * First argument, signo.
- */
- regs->erp = (unsigned long) ksig->ka.sa.sa_handler;
- regs->srp = return_ip;
- regs->r10 = ksig->sig;
-
- /* Actually move the USP to reflect the stacked frame. */
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-static int
-setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- int err;
- unsigned long return_ip;
- struct rt_signal_frame __user *frame;
-
- err = 0;
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
-
- if (err)
- return -EFAULT;
-
- /* Clear all the bits of the ucontext we don't use. */
- err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up to return from user-space. If provided, use a stub
- * already located in user-space.
- */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long) ksig->ka.sa.sa_restorer;
- } else {
- /* Trampoline - the desired return ip is in the signal return page. */
- return_ip = cris_signal_return_page + 6;
-
- /*
- * This is movu.w __NR_rt_sigreturn, r9; break 13;
- *
- * WE DO NOT USE IT ANY MORE! It's only left here for historical
- * reasons and because gdb uses it as a signature to notice
- * signal handler stack frames.
- */
- err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
-
- err |= __put_user(__NR_rt_sigreturn,
- (short __user*)(frame->retcode+2));
-
- err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up registers for signal handler.
- *
- * Where the code enters now.
- * Where the code enters later.
- * First argument is signo.
- * Second argument is (siginfo_t *).
- * Third argument is unused.
- */
- regs->erp = (unsigned long) ksig->ka.sa.sa_handler;
- regs->srp = return_ip;
- regs->r10 = ksig->sig;
- regs->r11 = (unsigned long) &frame->info;
- regs->r12 = 0;
-
- /* Actually move the usp to reflect the stacked frame. */
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-/* Invoke a signal handler to, well, handle the signal. */
-static inline void
-handle_signal(int canrestart, struct ksignal *ksig, struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Check if this got called from a system call. */
- if (canrestart) {
- /* If so, check system call restarting. */
- switch (regs->r10) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- /*
- * This means that the syscall should
- * only be restarted if there was no
- * handler for the signal, and since
- * this point isn't reached unless
- * there is a handler, there's no need
- * to restart.
- */
- regs->r10 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- /*
- * This means restart the syscall if
- * there is no handler, or the handler
- * was registered with SA_RESTART.
- */
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->r10 = -EINTR;
- break;
- }
-
- /* Fall through. */
-
- case -ERESTARTNOINTR:
- /*
- * This means that the syscall should
- * be called again after the signal
- * handler returns.
- */
- RESTART_CRIS_SYS(regs);
- break;
- }
- }
-
- /* Set up the stack frame. */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset, regs);
- else
- ret = setup_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, 0);
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Also note that the regs structure given here as an argument, is the latest
- * pushed pt_regs. It may or may not be the same as the first pushed registers
- * when the initial usermode->kernelmode transition took place. Therefore
- * we can use user_mode(regs) to see if we came directly from kernel or user
- * mode below.
- */
-void
-do_signal(int canrestart, struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- canrestart = canrestart && ((int)regs->exs >= 0);
-
- /*
- * The common case should go fast, which is why this point is
- * reached from kernel-mode. If that's the case, just return
- * without doing anything.
- */
- if (!user_mode(regs))
- return;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(canrestart, &ksig, regs);
- return;
- }
-
- /* Got here from a system call? */
- if (canrestart) {
- /* Restart the system call - no handlers present. */
- if (regs->r10 == -ERESTARTNOHAND ||
- regs->r10 == -ERESTARTSYS ||
- regs->r10 == -ERESTARTNOINTR) {
- RESTART_CRIS_SYS(regs);
- }
-
- if (regs->r10 == -ERESTART_RESTARTBLOCK){
- regs->r9 = __NR_restart_syscall;
- regs->erp -= 2;
- }
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-asmlinkage void
-ugdb_trap_user(struct thread_info *ti, int sig)
-{
- if (((user_regs(ti)->exs & 0xff00) >> 8) != SINGLE_STEP_INTR_VECT) {
- /* Zero single-step PC if the reason we stopped wasn't a single
- step exception. This is to avoid relying on it when it isn't
- reliable. */
- user_regs(ti)->spc = 0;
- }
- /* FIXME: Filter out false h/w breakpoint hits (i.e. EDA
- not within any configured h/w breakpoint range). Synchronize with
- what already exists for kernel debugging. */
- if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) {
- /* Break 8: subtract 2 from ERP unless in a delay slot. */
- if (!(user_regs(ti)->erp & 0x1))
- user_regs(ti)->erp -= 2;
- }
- sys_kill(ti->task->pid, sig);
-}
-
-void
-keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
- struct pt_regs *regs)
-{
- if (oldccs & (1 << Q_CCS_BITNR)) {
- /* Pending single step due to single-stepping the break 13
- in the signal trampoline: keep the Q flag. */
- regs->ccs |= (1 << Q_CCS_BITNR);
- /* S flag should be set - complain if it's not. */
- if (!(oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT)))) {
- printk("Q flag but no S flag?");
- }
- regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- /* Assume the SPC is valid and interesting. */
- regs->spc = oldspc;
-
- } else if (oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT))) {
- /* If a h/w bp was set in the signal handler we need
- to keep the S flag. */
- regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- /* Don't keep the old SPC though; if we got here due to
- a single-step, the Q flag should have been set. */
- } else if (regs->spc) {
- /* If we were single-stepping *before* the signal was taken,
- we don't want to restore that state now, because GDB will
- have forgotten all about it. */
- regs->spc = 0;
- regs->ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
- }
-}
-
-/* Set up the trampolines on the signal return page. */
-int __init
-cris_init_signal(void)
-{
- u16* data = kmalloc(PAGE_SIZE, GFP_KERNEL);
-
- /* This is movu.w __NR_sigreturn, r9; break 13; */
- data[0] = 0x9c5f;
- data[1] = __NR_sigreturn;
- data[2] = 0xe93d;
- /* This is movu.w __NR_rt_sigreturn, r9; break 13; */
- data[3] = 0x9c5f;
- data[4] = __NR_rt_sigreturn;
- data[5] = 0xe93d;
-
- /* Map to userspace with appropriate permissions (no write access...) */
- cris_signal_return_page = (unsigned long)
- __ioremap_prot(virt_to_phys(data), PAGE_SIZE, PAGE_SIGNAL_TRAMPOLINE);
-
- return 0;
-}
-
-__initcall(cris_init_signal);
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
deleted file mode 100644
index d07a3912687e..000000000000
--- a/arch/cris/arch-v32/kernel/time.c
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v32/kernel/time.c
- *
- * Copyright (C) 2003-2010 Axis Communications AB
- *
- */
-
-#include <linux/timex.h>
-#include <linux/time.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/swap.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/cpufreq.h>
-#include <linux/sched_clock.h>
-#include <linux/mm.h>
-#include <asm/types.h>
-#include <asm/signal.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irq_regs.h>
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-#include <hwregs/intr_vect_defs.h>
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#include <hwregs/clkgen_defs.h>
-#endif
-
-/* Watchdog defines */
-#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
-#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
-/* Number of 763 counts before watchdog bites */
-#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
-
-#define CRISV32_TIMER_FREQ (100000000lu)
-
-unsigned long timer_regs[NR_CPUS] =
-{
- regi_timer0,
-};
-
-extern int set_rtc_mmss(unsigned long nowtime);
-
-#ifdef CONFIG_CPU_FREQ
-static int cris_time_freq_notifier(struct notifier_block *nb,
- unsigned long val, void *data);
-
-static struct notifier_block cris_time_freq_notifier_block = {
- .notifier_call = cris_time_freq_notifier,
-};
-#endif
-
-unsigned long get_ns_in_jiffie(void)
-{
- reg_timer_r_tmr0_data data;
- unsigned long ns;
-
- data = REG_RD(timer, regi_timer0, r_tmr0_data);
- ns = (TIMER0_DIV - data) * 10;
- return ns;
-}
-
-/* From timer MDS describing the hardware watchdog:
- * 4.3.1 Watchdog Operation
- * The watchdog timer is an 8-bit timer with a configurable start value.
- * Once started the watchdog counts downwards with a frequency of 763 Hz
- * (100/131072 MHz). When the watchdog counts down to 1, it generates an
- * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
- * chip.
- */
-/* This gives us 1.3 ms to do something useful when the NMI comes */
-
-/* Right now, starting the watchdog is the same as resetting it */
-#define start_watchdog reset_watchdog
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
-static short int watchdog_key = 42; /* arbitrary 7 bit number */
-#endif
-
-/* Number of pages to consider "out of memory". It is normal that the memory
- * is used though, so set this really low. */
-#define WATCHDOG_MIN_FREE_PAGES 8
-
-#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
-/* for reliable NICE_DOGGY behaviour */
-static int bite_in_progress;
-#endif
-
-void reset_watchdog(void)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
-
-#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
- if (unlikely(bite_in_progress))
- return;
-#endif
- /* Only keep watchdog happy as long as we have memory left! */
- if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
- /* Reset the watchdog with the inverse of the old key */
- /* Invert key, which is 7 bits */
- watchdog_key ^= ETRAX_WD_KEY_MASK;
- wd_ctrl.cnt = ETRAX_WD_CNT;
- wd_ctrl.cmd = regk_timer_start;
- wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
- }
-#endif
-}
-
-/* stop the watchdog - we still need the correct key */
-
-void stop_watchdog(void)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
- watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
- wd_ctrl.cnt = ETRAX_WD_CNT;
- wd_ctrl.cmd = regk_timer_stop;
- wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
-#endif
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-void handle_watchdog_bite(struct pt_regs *regs)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- extern int cause_of_death;
-
- nmi_enter();
- oops_in_progress = 1;
-#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
- bite_in_progress = 1;
-#endif
- printk(KERN_WARNING "Watchdog bite\n");
-
- /* Check if forced restart or unexpected watchdog */
- if (cause_of_death == 0xbedead) {
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- /* There is a bug in Artpec-3 (voodoo TR 78) that requires
- * us to go to lower frequency for the reset to be reliable
- */
- reg_clkgen_rw_clk_ctrl ctrl =
- REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
- ctrl.pll = 0;
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
-#endif
- while(1);
- }
-
- /* Unexpected watchdog, stop the watchdog and dump registers. */
- stop_watchdog();
- printk(KERN_WARNING "Oops: bitten by watchdog\n");
- show_registers(regs);
- oops_in_progress = 0;
- printk("\n"); /* Flush mtdoops. */
-#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
- while(1) /* nothing */;
-#endif
-}
-
-extern void cris_profile_sample(struct pt_regs *regs);
-static void __iomem *timer_base;
-
-static int crisv32_clkevt_switch_state(struct clock_event_device *dev)
-{
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_hold,
- .freq = regk_timer_f100,
- };
-
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
- return 0;
-}
-
-static int crisv32_clkevt_next_event(unsigned long evt,
- struct clock_event_device *dev)
-{
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_ld,
- .freq = regk_timer_f100,
- };
-
- REG_WR(timer, timer_base, rw_tmr0_div, evt);
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
-
- ctrl.op = regk_timer_run;
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
-
- return 0;
-}
-
-static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_hold,
- .freq = regk_timer_f100,
- };
- reg_timer_rw_ack_intr ack = { .tmr0 = 1 };
- reg_timer_r_masked_intr intr;
-
- intr = REG_RD(timer, timer_base, r_masked_intr);
- if (!intr.tmr0)
- return IRQ_NONE;
-
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
- REG_WR(timer, timer_base, rw_ack_intr, ack);
-
- reset_watchdog();
-#ifdef CONFIG_SYSTEM_PROFILER
- cris_profile_sample(get_irq_regs());
-#endif
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct clock_event_device crisv32_clockevent = {
- .name = "crisv32-timer",
- .rating = 300,
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .set_state_oneshot = crisv32_clkevt_switch_state,
- .set_state_shutdown = crisv32_clkevt_switch_state,
- .tick_resume = crisv32_clkevt_switch_state,
- .set_next_event = crisv32_clkevt_next_event,
-};
-
-/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
-static struct irqaction irq_timer = {
- .handler = crisv32_timer_interrupt,
- .flags = IRQF_TIMER | IRQF_SHARED,
- .name = "crisv32-timer",
- .dev_id = &crisv32_clockevent,
-};
-
-static u64 notrace crisv32_timer_sched_clock(void)
-{
- return REG_RD(timer, timer_base, r_time);
-}
-
-static void __init crisv32_timer_init(void)
-{
- reg_timer_rw_intr_mask timer_intr_mask;
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_hold,
- .freq = regk_timer_f100,
- };
-
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
-
- timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask);
- timer_intr_mask.tmr0 = 1;
- REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask);
-}
-
-void __init time_init(void)
-{
- int irq;
- int ret;
-
- /* Probe for the RTC and read it if it exists.
- * Before the RTC can be probed the loops_per_usec variable needs
- * to be initialized to make usleep work. A better value for
- * loops_per_usec is calculated by the kernel later once the
- * clock has started.
- */
- loops_per_usec = 50;
-
- irq = TIMER0_INTR_VECT;
- timer_base = (void __iomem *) regi_timer0;
-
- crisv32_timer_init();
-
- sched_clock_register(crisv32_timer_sched_clock, 32,
- CRISV32_TIMER_FREQ);
-
- clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
- "crisv32-timer", CRISV32_TIMER_FREQ,
- 300, 32, clocksource_mmio_readl_up);
-
- crisv32_clockevent.cpumask = cpu_possible_mask;
- crisv32_clockevent.irq = irq;
-
- ret = setup_irq(irq, &irq_timer);
- if (ret)
- pr_warn("failed to setup irq %d\n", irq);
-
- clockevents_config_and_register(&crisv32_clockevent,
- CRISV32_TIMER_FREQ,
- 2, 0xffffffff);
-
- /* Enable watchdog if we should use one. */
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
- printk(KERN_INFO "Enabling watchdog...\n");
- start_watchdog();
-
- /* If we use the hardware watchdog, we want to trap it as an NMI
- * and dump registers before it resets us. For this to happen, we
- * must set the "m" NMI enable flag (which once set, is unset only
- * when an NMI is taken). */
- {
- unsigned long flags;
- local_save_flags(flags);
- flags |= (1<<30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
- }
-#endif
-
-#ifdef CONFIG_CPU_FREQ
- cpufreq_register_notifier(&cris_time_freq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-#endif
-}
-
-#ifdef CONFIG_CPU_FREQ
-static int cris_time_freq_notifier(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_freqs *freqs = data;
- if (val == CPUFREQ_POSTCHANGE) {
- reg_timer_r_tmr0_data data;
- reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
- do {
- data = REG_RD(timer, timer_regs[freqs->cpu],
- r_tmr0_data);
- } while (data > 20);
- REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
- }
- return 0;
-}
-#endif
diff --git a/arch/cris/arch-v32/kernel/traps.c b/arch/cris/arch-v32/kernel/traps.c
deleted file mode 100644
index ba54c7eccbaa..000000000000
--- a/arch/cris/arch-v32/kernel/traps.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003-2006, Axis Communications AB.
- */
-
-#include <linux/ptrace.h>
-#include <linux/extable.h>
-#include <linux/uaccess.h>
-#include <linux/sched/debug.h>
-
-#include <hwregs/supp_reg.h>
-#include <hwregs/intr_vect_defs.h>
-#include <asm/irq.h>
-
-void show_registers(struct pt_regs *regs)
-{
- /*
- * It's possible to use either the USP register or current->thread.usp.
- * USP might not correspond to the current process for all cases this
- * function is called, and current->thread.usp isn't up to date for the
- * current process. Experience shows that using USP is the way to go.
- */
- unsigned long usp = rdusp();
- unsigned long d_mmu_cause;
- unsigned long i_mmu_cause;
-
- printk("CPU: %d\n", smp_processor_id());
-
- printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
- regs->erp, regs->srp, regs->ccs, usp, regs->mof);
-
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
-
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
-
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
-
- printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, regs->acr);
-
- printk(" sp: %08lx\n", (unsigned long)regs);
-
- SUPP_BANK_SEL(BANK_IM);
- SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause);
-
- SUPP_BANK_SEL(BANK_DM);
- SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause);
-
- printk(" Data MMU Cause: %08lx\n", d_mmu_cause);
- printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);
-
- printk("Process %s (pid: %d, stackpage=%08lx)\n",
- current->comm, current->pid, (unsigned long)current);
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- int i;
-
- show_stack(NULL, (unsigned long *)usp);
-
- /*
- * If the previous stack-dump wasn't a kernel one, dump the
- * kernel stack now.
- */
- if (usp != 0)
- show_stack(NULL, NULL);
-
- printk("\nCode: ");
-
- if (regs->erp < PAGE_OFFSET)
- goto bad_value;
-
- /*
- * Quite often the value at regs->erp doesn't point to the
- * interesting instruction, which often is the previous
- * instruction. So dump at an offset large enough that the
- * instruction decoding should be in sync at the interesting
- * point, but small enough to fit on a row. The regs->erp
- * location is pointed out in a ksymoops-friendly way by
- * wrapping the byte for that address in parenthesises.
- */
- for (i = -12; i < 12; i++) {
- unsigned char c;
-
- if (__get_user(c, &((unsigned char *)regs->erp)[i])) {
-bad_value:
- printk(" Bad IP value.");
- break;
- }
-
- if (i == 0)
- printk("(%02x) ", c);
- else
- printk("%02x ", c);
- }
- printk("\n");
- }
-}
-
-void arch_enable_nmi(void)
-{
- unsigned long flags;
-
- local_save_flags(flags);
- flags |= (1 << 30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
-}
-
-extern void (*nmi_handler)(struct pt_regs *);
-void handle_nmi(struct pt_regs *regs)
-{
-#ifdef CONFIG_ETRAXFS
- reg_intr_vect_r_nmi r;
-#endif
-
- if (nmi_handler)
- nmi_handler(regs);
-
-#ifdef CONFIG_ETRAXFS
- /* Wait until nmi is no longer active. */
- do {
- r = REG_RD(intr_vect, regi_irq, r_nmi);
- } while (r.ext == regk_intr_vect_on);
-#endif
-}
-
-
-#ifdef CONFIG_BUG
-extern void die_if_kernel(const char *str, struct pt_regs *regs, long err);
-
-/* Copy of the regs at BUG() time. */
-struct pt_regs BUG_regs;
-
-void do_BUG(char *file, unsigned int line)
-{
- printk("kernel BUG at %s:%d!\n", file, line);
- die_if_kernel("Oops", &BUG_regs, 0);
-}
-EXPORT_SYMBOL(do_BUG);
-
-void fixup_BUG(struct pt_regs *regs)
-{
- BUG_regs = *regs;
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
- /*
- * Fixup the BUG arguments through exception handlers.
- */
- {
- const struct exception_table_entry *fixup;
-
- /*
- * ERP points at the "break 14" + 2, compensate for the 2
- * bytes.
- */
- fixup = search_exception_tables(instruction_pointer(regs) - 2);
- if (fixup) {
- /* Adjust the instruction pointer in the stackframe. */
- instruction_pointer(regs) = fixup->fixup;
- arch_fixup(regs);
- }
- }
-#else
- /* Dont try to lookup the filename + line, just dump regs. */
- do_BUG("unknown", 0);
-#endif
-}
-
-/*
- * Break 14 handler. Save regs and jump into the fixup_BUG.
- */
-__asm__ ( ".text\n\t"
- ".global breakh_BUG\n\t"
- "breakh_BUG:\n\t"
- SAVE_ALL
- KGDB_FIXUP
- "move.d $sp, $r10\n\t"
- "jsr fixup_BUG\n\t"
- "nop\n\t"
- "jump ret_from_intr\n\t"
- "nop\n\t");
-
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-void
-handle_BUG(struct pt_regs *regs)
-{
-}
-#endif
-#endif
diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile
deleted file mode 100644
index e91cf02f625d..000000000000
--- a/arch/cris/arch-v32/lib/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for Etrax-specific library files..
-#
-
-lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \
- csumcpfruser.o delay.o strcmp.o
-
diff --git a/arch/cris/arch-v32/lib/checksum.S b/arch/cris/arch-v32/lib/checksum.S
deleted file mode 100644
index f773d4d93609..000000000000
--- a/arch/cris/arch-v32/lib/checksum.S
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum routine using movem
- * Copyright (c) 1998-2007 Axis Communications AB
- *
- * csum_partial(const unsigned char * buff, int len, unsigned int sum)
- */
-
- .globl csum_partial
- .type csum_partial,@function
-csum_partial:
-
- ;; r10 - src
- ;; r11 - length
- ;; r12 - checksum
-
- ;; Optimized for large packets
- subq 10*4, $r11
- blt _word_loop
- move.d $r11, $acr
-
- subq 9*4,$sp
- clearf c
- movem $r8,[$sp]
-
- ;; do a movem checksum
-
-_mloop: movem [$r10+],$r9 ; read 10 longwords
- ;; Loop count without touching the c flag.
- addoq -10*4, $acr, $acr
- ;; perform dword checksumming on the 10 longwords
-
- addc $r0,$r12
- addc $r1,$r12
- addc $r2,$r12
- addc $r3,$r12
- addc $r4,$r12
- addc $r5,$r12
- addc $r6,$r12
- addc $r7,$r12
- addc $r8,$r12
- addc $r9,$r12
-
- ;; test $acr without trashing carry.
- move.d $acr, $acr
- bpl _mloop
- ;; r11 <= acr is not really needed in the mloop, just using the dslot
- ;; to prepare for what is needed after mloop.
- move.d $acr, $r11
-
- ;; fold the last carry into r13
- addc 0, $r12
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- addq 10*4,$r11 ; compensate for last loop underflowing length
-
- moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9
- lsrq 16,$r9
-
- move.d $r12,$r13
- lsrq 16,$r13 ; r13 = checksum >> 16
- and.d $r9,$r12 ; checksum = checksum & 0xffff
-
-_no_fold:
- subq 2,$r11
- blt _no_words
- add.d $r13,$r12 ; checksum += r13
-
- ;; checksum the rest of the words
-_wloop: subq 2,$r11
- bge _wloop
- addu.w [$r10+],$r12
-
-_no_words:
- addq 2,$r11
- ;; see if we have one odd byte more
- bne _do_byte
- nop
- ret
- move.d $r12,$r10
-
-_do_byte:
- ;; copy and checksum the last byte
- addu.b [$r10],$r12
- ret
- move.d $r12,$r10
-
- .size csum_partial, .-csum_partial
diff --git a/arch/cris/arch-v32/lib/checksumcopy.S b/arch/cris/arch-v32/lib/checksumcopy.S
deleted file mode 100644
index a76e586d4114..000000000000
--- a/arch/cris/arch-v32/lib/checksumcopy.S
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum+copy routine using movem
- * Copyright (c) 1998-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * csum_partial_copy_nocheck(const char *src, char *dst,
- * int len, unsigned int sum)
- */
-
- .globl csum_partial_copy_nocheck
- .type csum_partial_copy_nocheck,@function
-csum_partial_copy_nocheck:
-
- ;; r10 - src
- ;; r11 - dst
- ;; r12 - length
- ;; r13 - checksum
-
- ;; Optimized for large packets
- subq 10*4, $r12
- blt _word_loop
- move.d $r12, $acr
-
- subq 9*4,$sp
- clearf c
- movem $r8,[$sp]
-
- ;; do a movem copy and checksum
-1: ;; A failing userspace access (the read) will have this as PC.
-_mloop: movem [$r10+],$r9 ; read 10 longwords
- addoq -10*4, $acr, $acr ; loop counter in latency cycle
- movem $r9,[$r11+] ; write 10 longwords
-
- ;; perform dword checksumming on the 10 longwords
- addc $r0,$r13
- addc $r1,$r13
- addc $r2,$r13
- addc $r3,$r13
- addc $r4,$r13
- addc $r5,$r13
- addc $r6,$r13
- addc $r7,$r13
- addc $r8,$r13
- addc $r9,$r13
-
- ;; test $acr, without trashing carry.
- move.d $acr, $acr
- bpl _mloop
- ;; r12 <= acr is needed after mloop and in the exception handlers.
- move.d $acr, $r12
-
- ;; fold the last carry into r13
- addc 0, $r13
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- addq 10*4,$r12 ; compensate for last loop underflowing length
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below
- ;; r9 can be used as temporary.
- move.d $r13,$r9
- lsrq 16,$r9 ; r0 = checksum >> 16
- and.d 0xffff,$r13 ; checksum = checksum & 0xffff
-
- subq 2, $r12
- blt _no_words
- add.d $r9,$r13 ; checksum += r0
-
- ;; copy and checksum the rest of the words
-2: ;; A failing userspace access for the read below will have this as PC.
-_wloop: move.w [$r10+],$r9
- addu.w $r9,$r13
- subq 2,$r12
- bge _wloop
- move.w $r9,[$r11+]
-
-_no_words:
- addq 2,$r12
- bne _do_byte
- nop
- ret
- move.d $r13,$r10
-
-_do_byte:
- ;; copy and checksum the last byte
-3: ;; A failing userspace access for the read below will have this as PC.
- move.b [$r10],$r9
- addu.b $r9,$r13
- move.b $r9,[$r11]
- ret
- move.d $r13,$r10
-
- .size csum_partial_copy_nocheck, . - csum_partial_copy_nocheck
diff --git a/arch/cris/arch-v32/lib/csumcpfruser.S b/arch/cris/arch-v32/lib/csumcpfruser.S
deleted file mode 100644
index 093cd757fcfa..000000000000
--- a/arch/cris/arch-v32/lib/csumcpfruser.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into
- * csum_partial_copy_from_user by adding exception records.
- *
- * Copyright (C) 2001, 2003 Axis Communications AB.
- *
- * Author: Hans-Peter Nilsson.
- */
-
-#include <asm/errno.h>
-
-/* Same function body, but a different name. If we just added exception
- records to _csum_partial_copy_nocheck and made it generic, we wouldn't
- know a user fault from a kernel fault and we would have overhead in
- each kernel caller for the error-pointer argument.
-
- unsigned int csum_partial_copy_from_user
- (const char *src, char *dst, int len, unsigned int sum, int *errptr);
-
- Note that the errptr argument is only set if we encounter an error.
- It is conveniently located on the stack, so the normal function body
- does not have to handle it. */
-
-#define csum_partial_copy_nocheck csum_partial_copy_from_user
-
-/* There are local labels numbered 1, 2 and 3 present to mark the
- different from-user accesses. */
-#include "checksumcopy.S"
-
- .section .fixup,"ax"
-
-;; Here from the movem loop; restore stack.
-4:
- movem [$sp+],$r8
-;; r12 is already decremented. Add back chunk_size-2.
- addq 40-2,$r12
-
-;; Here from the word loop; r12 is off by 2; add it back.
-5:
- addq 2,$r12
-
-;; Here from a failing single byte.
-6:
-
-;; Signal in *errptr that we had a failing access.
- move.d [$sp],$acr
- moveq -EFAULT,$r9
- subq 4,$sp
- move.d $r9,[$acr]
-
-;; Clear the rest of the destination area using memset. Preserve the
-;; checksum for the readable bytes.
- move.d $r13,[$sp]
- subq 4,$sp
- move.d $r11,$r10
- move $srp,[$sp]
- jsr memset
- clear.d $r11
-
- move [$sp+],$srp
- ret
- move.d [$sp+],$r10
-
- .previous
- .section __ex_table,"a"
- .dword 1b,4b
- .dword 2b,5b
- .dword 3b,6b
- .previous
diff --git a/arch/cris/arch-v32/lib/delay.c b/arch/cris/arch-v32/lib/delay.c
deleted file mode 100644
index db06a94ef646..000000000000
--- a/arch/cris/arch-v32/lib/delay.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Precise Delay Loops for ETRAX FS
- *
- * Copyright (C) 2006 Axis Communications AB.
- *
- */
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-
-/*
- * On ETRAX FS, we can check the free-running read-only 100MHz timer
- * getting 32-bit 10ns precision, theoretically good for 42.94967295
- * seconds. Unsigned arithmetic and careful expression handles
- * wrapping.
- */
-
-void cris_delay10ns(u32 n10ns)
-{
- u32 t0 = REG_RD(timer, regi_timer0, r_time);
- while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns)
- ;
-}
-EXPORT_SYMBOL(cris_delay10ns);
diff --git a/arch/cris/arch-v32/lib/memset.c b/arch/cris/arch-v32/lib/memset.c
deleted file mode 100644
index c94ea9b3ec29..000000000000
--- a/arch/cris/arch-v32/lib/memset.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* A memset for CRIS.
- Copyright (C) 1999-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-/* Note the multiple occurrence of the expression "12*4", including the
- asm. It is hard to get it into the asm in a good way. Thus better to
- expose the problem everywhere: no macro. */
-
-/* Assuming one cycle per dword written or read (ok, not really true; the
- world is not ideal), and one cycle per instruction, then 43+3*(n/48-1)
- <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full
- 48-byte block to set. */
-
-#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *memset(void *pdst, int c, unsigned int plen)
-{
- /* Now we want the parameters in special registers. Make sure the
- compiler does something usable with this. */
-
- register char *return_dst __asm__ ("r10") = pdst;
- register int n __asm__ ("r12") = plen;
- register int lc __asm__ ("r11") = c;
-
- /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get
- penalized here compared to the generic implementation. */
-
- /* This is fragile performancewise at best. Check with newer GCC
- releases, if they compile cascaded "x |= x << 8" to sane code. */
- __asm__("movu.b %0,r13 \n\
- lslq 8,r13 \n\
- move.b %0,r13 \n\
- move.d r13,%0 \n\
- lslq 16,r13 \n\
- or.d r13,%0"
- : "=r" (lc) /* Inputs. */
- : "0" (lc) /* Outputs. */
- : "r13"); /* Trash. */
-
- {
- register char *dst __asm__ ("r13") = pdst;
-
- if (((unsigned long) pdst & 3) != 0
- /* Oops! n = 0 must be a valid call, regardless of alignment. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- *dst = (char) lc;
- n--;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- *(short *) dst = lc;
- n -= 2;
- dst += 2;
- }
- }
-
- /* Decide which setting method to use. */
- if (n >= MEMSET_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-block sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%4,$r13-$r12-$r11 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- move.d r11,r0 \n\
- move.d r11,r1 \n\
- move.d r11,r2 \n\
- move.d r11,r3 \n\
- move.d r11,r4 \n\
- move.d r11,r5 \n\
- move.d r11,r6 \n\
- move.d r11,r7 \n\
- move.d r11,r8 \n\
- move.d r11,r9 \n\
- move.d r11,r10 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" subq 12*4,r12 \n\
- bge 0b \n\
- movem r11,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 12*4,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (n), "r" (lc));
- }
-
- /* An ad-hoc unroll, used for 4*12-1..16 bytes. */
- while (n >= 16)
- {
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = (char) lc;
- break;
-
- case 2:
- *(short *) dst = (short) lc;
- break;
-
- case 3:
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 4:
- *(long *) dst = lc;
- break;
-
- case 5:
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 6:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 7:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 8:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 9:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 10:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 11:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 12:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 13:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 14:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 15:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
- }
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v32/lib/strcmp.S b/arch/cris/arch-v32/lib/strcmp.S
deleted file mode 100644
index 8f7a1ee62591..000000000000
--- a/arch/cris/arch-v32/lib/strcmp.S
+++ /dev/null
@@ -1,21 +0,0 @@
-; strcmp.S -- CRISv32 version.
-; Copyright (C) 2008 AXIS Communications AB
-; Written by Edgar E. Iglesias
-;
-; This source code is licensed under the GNU General Public License,
-; Version 2. See the file COPYING for more details.
-
- .global strcmp
- .type strcmp,@function
-strcmp:
-1:
- move.b [$r10+], $r12
- seq $r13
- sub.b [$r11+], $r12
- or.b $r12, $r13
- beq 1b
- nop
-
- ret
- movs.b $r12, $r10
- .size strcmp, . - strcmp
diff --git a/arch/cris/arch-v32/lib/string.c b/arch/cris/arch-v32/lib/string.c
deleted file mode 100644
index c7bd6ebdc93c..000000000000
--- a/arch/cris/arch-v32/lib/string.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* A memcpy for CRIS.
- Copyright (C) 1994-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-#include <stddef.h>
-
-/* Break even between movem and move16 is really at 38.7 * 2, but
- modulo 44, so up to the next multiple of 44, we use ordinary code. */
-#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *
-memcpy(void *pdst, const void *psrc, size_t pn)
-{
- /* Now we want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- If gcc was allright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register void *return_dst __asm__ ("r10") = pdst;
- register unsigned char *dst __asm__ ("r13") = pdst;
- register unsigned const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- n--;
- *dst = *src;
- src++;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- n -= 2;
- *(short *) dst = *(short *) src;
- src += 2;
- dst += 2;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= MEMCPY_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%2,$r13-$r11-$r12 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop. \n\
- subq 44,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" movem [r11+],r10 \n\
- subq 44,r12 \n\
- bge 0b \n\
- movem r10,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 44,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (src), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (src), "2" (n));
- }
-
- while (n >= 16)
- {
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
-
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = *src;
- break;
-
- case 2:
- *(short *) dst = *(short *) src;
- break;
-
- case 3:
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 4:
- *(long *) dst = *(long *) src;
- break;
-
- case 5:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 6:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 7:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 8:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 9:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 10:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 11:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 12:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 13:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 14:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 15:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v32/lib/usercopy.c b/arch/cris/arch-v32/lib/usercopy.c
deleted file mode 100644
index 04e78b6ffa22..000000000000
--- a/arch/cris/arch-v32/lib/usercopy.c
+++ /dev/null
@@ -1,458 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * User address space access functions.
- * The non-inlined parts of asm-cris/uaccess.h are here.
- *
- * Copyright (C) 2000, 2003 Axis Communications AB.
- *
- * Written by Hans-Peter Nilsson.
- * Pieces used from memcpy, originally by Kenny Ranerup long time ago.
- */
-
-#include <linux/uaccess.h>
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
- satisfactory results for "gcc version 3.2.1 Axis release R53/1.53-v32".
-
- Check regularly...
-
- Note that for CRISv32, the PC saved at a bus-fault is the address
- *at* the faulting instruction, with a special case for instructions
- in delay slots: then it's the address of the branch. Note also that
- in contrast to v10, a postincrement in the instruction is *not*
- performed at a bus-fault; the register is seen having the original
- value in fault handlers. */
-
-
-/* Copy to userspace. This is based on the memcpy used for
- kernel-to-kernel copying; see "string.c". */
-
-unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_copy_to_user_1 (dst, src, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_copy_to_user_2 (dst, src, retn);
- n -= 2;
- }
- }
-
- /* Movem is dirt cheap. The overheap is low enough to always use the
- minimum possible block size as the threshold. */
- if (n >= 44)
- {
- /* For large copies we use 'movem'. */
-
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile ("\
- ;; Check that the register asm declaration got right. \n\
- ;; The GCC manual explicitly says TRT will happen. \n\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
-0: \n\
- movem [$r11+],$r10 \n\
- subq 44,$r12 \n\
-1: bge 0b \n\
- movem $r10,[$r13+] \n\
-3: \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
-4: \n\
-; When failing on any of the 1..44 bytes in a chunk, we adjust back the \n\
-; source pointer and just drop through to the by-16 and by-4 loops to \n\
-; get the correct number of failing bytes. This necessarily means a \n\
-; few extra exceptions, but invalid user pointers shouldn't happen in \n\
-; time-critical code anyway. \n\
- jump 3b \n\
- subq 44,$r11 \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 1b,4b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
-
- }
-
- while (n >= 16)
- {
- __asm_copy_to_user_16 (dst, src, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_copy_to_user_4 (dst, src, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_copy_to_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_to_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_to_user_3 (dst, src, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__copy_user);
-
-/* Copy from user to kernel. The return-value is the number of bytes that were
- inaccessible. */
-unsigned long __copy_user_in(void *pdst, const void __user *psrc,
- unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
- /* The best reason to align src is that we then know that a read-fault
- was for aligned bytes; there's no 1..3 remaining good bytes to
- pickle. */
- if (((unsigned long) src & 3) != 0)
- {
- if (((unsigned long) src & 1) && n != 0)
- {
- __asm_copy_from_user_1 (dst, src, retn);
- n--;
- if (retn != 0)
- goto exception;
- }
-
- if (((unsigned long) src & 2) && n >= 2)
- {
- __asm_copy_from_user_2 (dst, src, retn);
- n -= 2;
- if (retn != 0)
- goto exception;
- }
-
- }
-
- /* Movem is dirt cheap. The overheap is low enough to always use the
- minimum possible block size as the threshold. */
- if (n >= 44)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile ("\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
-0: \n\
- movem [$r11+],$r10 \n\
- \n\
- subq 44,$r12 \n\
- bge 0b \n\
- movem $r10,[$r13+] \n\
- \n\
-4: \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
- .section .fixup,\"ax\" \n\
- \n\
-;; Do not jump back into the loop if we fail. For some uses, we get a \n\
-;; page fault somewhere on the line. Without checking for page limits, \n\
-;; we don't know where, but we need to copy accurately and keep an \n\
-;; accurate count; not just clear the whole line. To do that, we fall \n\
-;; down in the code below, proceeding with smaller amounts. It should \n\
-;; be kept in mind that we have to cater to code like what at one time \n\
-;; was in fs/super.c: \n\
-;; i = size - copy_from_user((void *)page, data, size); \n\
-;; which would cause repeated faults while clearing the remainder of \n\
-;; the SIZE bytes at PAGE after the first fault. \n\
-;; A caveat here is that we must not fall through from a failing page \n\
-;; to a valid page. \n\
- \n\
-3: \n\
- jump 4b ;; Fall through, pretending the fault didn't happen. \n\
- nop \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 0b,3b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
- }
-
- /* Either we directly start copying here, using dword copying in a loop,
- or we copy as much as possible with 'movem' and then the last block
- (<44 bytes) is copied here. This will work since 'movem' will have
- updated src, dst and n. (Except with failing src.)
-
- Since we want to keep src accurate, we can't use
- __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and
- retn, but not src (by design; it's value is ignored elsewhere). */
-
- while (n >= 4)
- {
- __asm_copy_from_user_4 (dst, src, retn);
- n -= 4;
-
- if (retn)
- goto exception;
- }
-
- /* If we get here, there were no memory read faults. */
- switch (n)
- {
- /* These copies are at least "naturally aligned" (so we don't have
- to check each byte), due to the src alignment code before the
- movem loop. The *_3 case *will* get the correct count for retn. */
- case 0:
- /* This case deliberately left in (if you have doubts check the
- generated assembly code). */
- break;
- case 1:
- __asm_copy_from_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_from_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_from_user_3 (dst, src, retn);
- break;
- }
-
- /* If we get here, retn correctly reflects the number of failing
- bytes. */
- return retn;
-
-exception:
- return retn + n;
-}
-EXPORT_SYMBOL(__copy_user_in);
-
-/* Zero userspace. */
-unsigned long __do_clear_user(void __user *pto, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pto;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_clear_1 (dst, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_clear_2 (dst, retn);
- n -= 2;
- }
- }
-
- /* Decide which copying method to use.
- FIXME: This number is from the "ordinary" kernel memset. */
- if (n >= 48)
- {
- /* For large clears we use 'movem' */
-
- /* It is not optimal to tell the compiler about clobbering any
- call-saved registers; that will move the saving/restoring of
- those registers to the function prologue/epilogue, and make
- non-movem sizes suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- something like "r13=r13, r11=r11, r12=r12". */
- __asm__ volatile ("\
- .ifnc %0%1%2,$r13$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- clear.d $r0 \n\
- clear.d $r1 \n\
- clear.d $r2 \n\
- clear.d $r3 \n\
- clear.d $r4 \n\
- clear.d $r5 \n\
- clear.d $r6 \n\
- clear.d $r7 \n\
- clear.d $r8 \n\
- clear.d $r9 \n\
- clear.d $r10 \n\
- clear.d $r11 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,$r12 \n\
-0: \n\
- subq 12*4,$r12 \n\
-1: \n\
- bge 0b \n\
- movem $r11,[$r13+] \n\
- \n\
- addq 12*4,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
-3: \n\
- movem [$sp],$r10 \n\
- addq 12*4,$r10 \n\
- addq 12*4,$r13 \n\
- movem $r10,[$sp] \n\
- jump 0b \n\
- clear.d $r10 \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 1b,3b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (n), "2" (retn)
- /* Clobber */ : "r11");
- }
-
- while (n >= 16)
- {
- __asm_clear_16 (dst, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_clear_4 (dst, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_clear_1 (dst, retn);
- break;
- case 2:
- __asm_clear_2 (dst, retn);
- break;
- case 3:
- __asm_clear_3 (dst, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__do_clear_user);
diff --git a/arch/cris/arch-v32/mach-a3/Kconfig b/arch/cris/arch-v32/mach-a3/Kconfig
deleted file mode 100644
index 7b63755544dd..000000000000
--- a/arch/cris/arch-v32/mach-a3/Kconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if CRIS_MACH_ARTPEC3
-
-menu "Artpec-3 options"
- depends on CRIS_MACH_ARTPEC3
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- default "c0000000"
-
-config ETRAX_L2CACHE
- bool
- default y
-
-config ETRAX_SERIAL_PORTS
- int
- default 5
-
-config ETRAX_DDR2_MRS
- hex "DDR2 MRS"
- default "0"
-
-config ETRAX_DDR2_TIMING
- hex "DDR2 SDRAM timing"
- default "0"
- help
- SDRAM timing parameters.
-
-config ETRAX_DDR2_CONFIG
- hex "DDR2 config"
- default "0"
-
-config ETRAX_DDR2_LATENCY
- hex "DDR2 latency"
- default "0"
-
-config ETRAX_PIO_CE0_CFG
- hex "PIO CE0 configuration"
- default "0"
-
-config ETRAX_PIO_CE1_CFG
- hex "PIO CE1 configuration"
- default "0"
-
-config ETRAX_PIO_CE2_CFG
- hex "PIO CE2 configuration"
- default "0"
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- default "00000000"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- default "00000000"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- default "000000000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- default "000000000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-endmenu
-
-endif
diff --git a/arch/cris/arch-v32/mach-a3/Makefile b/arch/cris/arch-v32/mach-a3/Makefile
deleted file mode 100644
index 0cc6eebacbed..000000000000
--- a/arch/cris/arch-v32/mach-a3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := dma.o pinmux.o arbiter.o
-
-clean:
-
diff --git a/arch/cris/arch-v32/mach-a3/arbiter.c b/arch/cris/arch-v32/mach-a3/arbiter.c
deleted file mode 100644
index 076182cc65a3..000000000000
--- a/arch/cris/arch-v32/mach-a3/arbiter.c
+++ /dev/null
@@ -1,635 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Memory arbiter functions. Allocates bandwidth through the
- * arbiter and sets up arbiter breakpoints.
- *
- * The algorithm first assigns slots to the clients that has specified
- * bandwidth (e.g. ethernet) and then the remaining slots are divided
- * on all the active clients.
- *
- * Copyright (c) 2004-2007 Axis Communications AB.
- *
- * The artpec-3 has two arbiters. The memory hierarchy looks like this:
- *
- *
- * CPU DMAs
- * | |
- * | |
- * -------------- ------------------
- * | foo arbiter|----| Internal memory|
- * -------------- ------------------
- * |
- * --------------
- * | L2 cache |
- * --------------
- * |
- * h264 etc |
- * | |
- * | |
- * --------------
- * | bar arbiter|
- * --------------
- * |
- * ---------
- * | SDRAM |
- * ---------
- *
- */
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_foo_defs.h>
-#include <hwregs/marb_bar_defs.h>
-#include <arbiter.h>
-#include <hwregs/intr_vect.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <asm/io.h>
-#include <asm/irq_regs.h>
-
-#define D(x)
-
-struct crisv32_watch_entry {
- unsigned long instance;
- watch_callback *cb;
- unsigned long start;
- unsigned long end;
- int used;
-};
-
-#define NUMBER_OF_BP 4
-#define SDRAM_BANDWIDTH 400000000
-#define INTMEM_BANDWIDTH 400000000
-#define NBR_OF_SLOTS 64
-#define NBR_OF_REGIONS 2
-#define NBR_OF_CLIENTS 15
-#define ARBITERS 2
-#define UNASSIGNED 100
-
-struct arbiter {
- unsigned long instance;
- int nbr_regions;
- int nbr_clients;
- int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
- int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-};
-
-static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] =
-{
- {
- {regi_marb_foo_bp0},
- {regi_marb_foo_bp1},
- {regi_marb_foo_bp2},
- {regi_marb_foo_bp3}
- },
- {
- {regi_marb_bar_bp0},
- {regi_marb_bar_bp1},
- {regi_marb_bar_bp2},
- {regi_marb_bar_bp3}
- }
-};
-
-struct arbiter arbiters[ARBITERS] =
-{
- { /* L2 cache arbiter */
- .instance = regi_marb_foo,
- .nbr_regions = 2,
- .nbr_clients = 15
- },
- { /* DDR2 arbiter */
- .instance = regi_marb_bar,
- .nbr_regions = 1,
- .nbr_clients = 9
- }
-};
-
-static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
-
-DEFINE_SPINLOCK(arbiter_lock);
-
-static irqreturn_t
-crisv32_foo_arbiter_irq(int irq, void *dev_id);
-static irqreturn_t
-crisv32_bar_arbiter_irq(int irq, void *dev_id);
-
-/*
- * "I'm the arbiter, I know the score.
- * From square one I'll be watching all 64."
- * (memory arbiter slots, that is)
- *
- * Or in other words:
- * Program the memory arbiter slots for "region" according to what's
- * in requested_slots[] and active_clients[], while minimizing
- * latency. A caller may pass a non-zero positive amount for
- * "unused_slots", which must then be the unallocated, remaining
- * number of slots, free to hand out to any client.
- */
-
-static void crisv32_arbiter_config(int arbiter, int region, int unused_slots)
-{
- int slot;
- int client;
- int interval = 0;
-
- /*
- * This vector corresponds to the hardware arbiter slots (see
- * the hardware documentation for semantics). We initialize
- * each slot with a suitable sentinel value outside the valid
- * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
- * client indexes. Then it's fed to the hardware.
- */
- s8 val[NBR_OF_SLOTS];
-
- for (slot = 0; slot < NBR_OF_SLOTS; slot++)
- val[slot] = -1;
-
- for (client = 0; client < arbiters[arbiter].nbr_clients; client++) {
- int pos;
- /* Allocate the requested non-zero number of slots, but
- * also give clients with zero-requests one slot each
- * while stocks last. We do the latter here, in client
- * order. This makes sure zero-request clients are the
- * first to get to any spare slots, else those slots
- * could, when bandwidth is allocated close to the limit,
- * all be allocated to low-index non-zero-request clients
- * in the default-fill loop below. Another positive but
- * secondary effect is a somewhat better spread of the
- * zero-bandwidth clients in the vector, avoiding some of
- * the latency that could otherwise be caused by the
- * partitioning of non-zero-bandwidth clients at low
- * indexes and zero-bandwidth clients at high
- * indexes. (Note that this spreading can only affect the
- * unallocated bandwidth.) All the above only matters for
- * memory-intensive situations, of course.
- */
- if (!arbiters[arbiter].requested_slots[region][client]) {
- /*
- * Skip inactive clients. Also skip zero-slot
- * allocations in this pass when there are no known
- * free slots.
- */
- if (!arbiters[arbiter].active_clients[region][client] ||
- unused_slots <= 0)
- continue;
-
- unused_slots--;
-
- /* Only allocate one slot for this client. */
- interval = NBR_OF_SLOTS;
- } else
- interval = NBR_OF_SLOTS /
- arbiters[arbiter].requested_slots[region][client];
-
- pos = 0;
- while (pos < NBR_OF_SLOTS) {
- if (val[pos] >= 0)
- pos++;
- else {
- val[pos] = client;
- pos += interval;
- }
- }
- }
-
- client = 0;
- for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
- /*
- * Allocate remaining slots in round-robin
- * client-number order for active clients. For this
- * pass, we ignore requested bandwidth and previous
- * allocations.
- */
- if (val[slot] < 0) {
- int first = client;
- while (!arbiters[arbiter].active_clients[region][client]) {
- client = (client + 1) %
- arbiters[arbiter].nbr_clients;
- if (client == first)
- break;
- }
- val[slot] = client;
- client = (client + 1) % arbiters[arbiter].nbr_clients;
- }
- if (arbiter == 0) {
- if (region == EXT_REGION)
- REG_WR_INT_VECT(marb_foo, regi_marb_foo,
- rw_l2_slots, slot, val[slot]);
- else if (region == INT_REGION)
- REG_WR_INT_VECT(marb_foo, regi_marb_foo,
- rw_intm_slots, slot, val[slot]);
- } else {
- REG_WR_INT_VECT(marb_bar, regi_marb_bar,
- rw_ddr2_slots, slot, val[slot]);
- }
- }
-}
-
-extern char _stext[], _etext[];
-
-static void crisv32_arbiter_init(void)
-{
- static int initialized;
-
- if (initialized)
- return;
-
- initialized = 1;
-
- /*
- * CPU caches are always set to active, but with zero
- * bandwidth allocated. It should be ok to allocate zero
- * bandwidth for the caches, because DMA for other channels
- * will supposedly finish, once their programmed amount is
- * done, and then the caches will get access according to the
- * "fixed scheme" for unclaimed slots. Though, if for some
- * use-case somewhere, there's a maximum CPU latency for
- * e.g. some interrupt, we have to start allocating specific
- * bandwidth for the CPU caches too.
- */
- arbiters[0].active_clients[EXT_REGION][11] = 1;
- arbiters[0].active_clients[EXT_REGION][12] = 1;
- crisv32_arbiter_config(0, EXT_REGION, 0);
- crisv32_arbiter_config(0, INT_REGION, 0);
- crisv32_arbiter_config(1, EXT_REGION, 0);
-
- if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq,
- 0, "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
- if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq,
- 0, "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
-#ifndef CONFIG_ETRAX_KGDB
- /* Global watch for writes to kernel text segment. */
- crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext,
- MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients),
- arbiter_all_write, NULL);
-#endif
-
- /* Set up max burst sizes by default */
- REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3);
-}
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth)
-{
- int i;
- int total_assigned = 0;
- int total_clients = 0;
- int req;
- int arbiter = 0;
-
- crisv32_arbiter_init();
-
- if (client & 0xffff0000) {
- arbiter = 1;
- client >>= 16;
- }
-
- for (i = 0; i < arbiters[arbiter].nbr_clients; i++) {
- total_assigned += arbiters[arbiter].requested_slots[region][i];
- total_clients += arbiters[arbiter].active_clients[region][i];
- }
-
- /* Avoid division by 0 for 0-bandwidth requests. */
- req = bandwidth == 0
- ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
-
- /*
- * We make sure that there are enough slots only for non-zero
- * requests. Requesting 0 bandwidth *may* allocate slots,
- * though if all bandwidth is allocated, such a client won't
- * get any and will have to rely on getting memory access
- * according to the fixed scheme that's the default when one
- * of the slot-allocated clients doesn't claim their slot.
- */
- if (total_assigned + req > NBR_OF_SLOTS)
- return -ENOMEM;
-
- arbiters[arbiter].active_clients[region][client] = 1;
- arbiters[arbiter].requested_slots[region][client] = req;
- crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
-
- /* Propagate allocation from foo to bar */
- if (arbiter == 0)
- crisv32_arbiter_allocate_bandwidth(8 << 16,
- EXT_REGION, bandwidth);
- return 0;
-}
-
-/*
- * Main entry for bandwidth deallocation.
- *
- * Strictly speaking, for a somewhat constant set of clients where
- * each client gets a constant bandwidth and is just enabled or
- * disabled (somewhat dynamically), no action is necessary here to
- * avoid starvation for non-zero-allocation clients, as the allocated
- * slots will just be unused. However, handing out those unused slots
- * to active clients avoids needless latency if the "fixed scheme"
- * would give unclaimed slots to an eager low-index client.
- */
-
-void crisv32_arbiter_deallocate_bandwidth(int client, int region)
-{
- int i;
- int total_assigned = 0;
- int arbiter = 0;
-
- if (client & 0xffff0000)
- arbiter = 1;
-
- arbiters[arbiter].requested_slots[region][client] = 0;
- arbiters[arbiter].active_clients[region][client] = 0;
-
- for (i = 0; i < arbiters[arbiter].nbr_clients; i++)
- total_assigned += arbiters[arbiter].requested_slots[region][i];
-
- crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
-}
-
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback *cb)
-{
- int i;
- int arbiter;
- int used[2];
- int ret = 0;
-
- crisv32_arbiter_init();
-
- if (start > 0x80000000) {
- printk(KERN_ERR "Arbiter: %lX doesn't look like a "
- "physical address", start);
- return -EFAULT;
- }
-
- spin_lock(&arbiter_lock);
-
- if (clients & 0xffff)
- used[0] = 1;
- if (clients & 0xffff0000)
- used[1] = 1;
-
- for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
- if (!used[arbiter])
- continue;
-
- for (i = 0; i < NUMBER_OF_BP; i++) {
- if (!watches[arbiter][i].used) {
- unsigned intr_mask;
- if (arbiter)
- intr_mask = REG_RD_INT(marb_bar,
- regi_marb_bar, rw_intr_mask);
- else
- intr_mask = REG_RD_INT(marb_foo,
- regi_marb_foo, rw_intr_mask);
-
- watches[arbiter][i].used = 1;
- watches[arbiter][i].start = start;
- watches[arbiter][i].end = start + size;
- watches[arbiter][i].cb = cb;
-
- ret |= (i + 1) << (arbiter + 8);
- if (arbiter) {
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_first_addr,
- watches[arbiter][i].start);
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_last_addr,
- watches[arbiter][i].end);
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_op, accesses);
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_clients,
- clients & 0xffff);
- } else {
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_first_addr,
- watches[arbiter][i].start);
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_last_addr,
- watches[arbiter][i].end);
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_op, accesses);
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_clients, clients >> 16);
- }
-
- if (i == 0)
- intr_mask |= 1;
- else if (i == 1)
- intr_mask |= 2;
- else if (i == 2)
- intr_mask |= 4;
- else if (i == 3)
- intr_mask |= 8;
-
- if (arbiter)
- REG_WR_INT(marb_bar, regi_marb_bar,
- rw_intr_mask, intr_mask);
- else
- REG_WR_INT(marb_foo, regi_marb_foo,
- rw_intr_mask, intr_mask);
-
- spin_unlock(&arbiter_lock);
-
- break;
- }
- }
- }
- spin_unlock(&arbiter_lock);
- if (ret)
- return ret;
- else
- return -ENOMEM;
-}
-
-int crisv32_arbiter_unwatch(int id)
-{
- int arbiter;
- int intr_mask;
-
- crisv32_arbiter_init();
-
- spin_lock(&arbiter_lock);
-
- for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
- int id2;
-
- if (arbiter)
- intr_mask = REG_RD_INT(marb_bar, regi_marb_bar,
- rw_intr_mask);
- else
- intr_mask = REG_RD_INT(marb_foo, regi_marb_foo,
- rw_intr_mask);
-
- id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8);
- if (id2 == 0)
- continue;
- id2--;
- if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) {
- spin_unlock(&arbiter_lock);
- return -EINVAL;
- }
-
- memset(&watches[arbiter][id2], 0,
- sizeof(struct crisv32_watch_entry));
-
- if (id2 == 0)
- intr_mask &= ~1;
- else if (id2 == 1)
- intr_mask &= ~2;
- else if (id2 == 2)
- intr_mask &= ~4;
- else if (id2 == 3)
- intr_mask &= ~8;
-
- if (arbiter)
- REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask,
- intr_mask);
- else
- REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask,
- intr_mask);
- }
-
- spin_unlock(&arbiter_lock);
- return 0;
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-
-static irqreturn_t
-crisv32_foo_arbiter_irq(int irq, void *dev_id)
-{
- reg_marb_foo_r_masked_intr masked_intr =
- REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
- reg_marb_foo_bp_r_brk_clients r_clients;
- reg_marb_foo_bp_r_brk_addr r_addr;
- reg_marb_foo_bp_r_brk_op r_op;
- reg_marb_foo_bp_r_brk_first_client r_first;
- reg_marb_foo_bp_r_brk_size r_size;
- reg_marb_foo_bp_rw_ack ack = {0};
- reg_marb_foo_rw_ack_intr ack_intr = {
- .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
- };
- struct crisv32_watch_entry *watch;
- unsigned arbiter = (unsigned)dev_id;
-
- masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
-
- if (masked_intr.bp0)
- watch = &watches[arbiter][0];
- else if (masked_intr.bp1)
- watch = &watches[arbiter][1];
- else if (masked_intr.bp2)
- watch = &watches[arbiter][2];
- else if (masked_intr.bp3)
- watch = &watches[arbiter][3];
- else
- return IRQ_NONE;
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size);
-
- printk(KERN_DEBUG "Arbiter IRQ\n");
- printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size));
-
- REG_WR(marb_foo_bp, watch->instance, rw_ack, ack);
- REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr);
-
- printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs());
-
- if (watch->cb)
- watch->cb();
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t
-crisv32_bar_arbiter_irq(int irq, void *dev_id)
-{
- reg_marb_bar_r_masked_intr masked_intr =
- REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
- reg_marb_bar_bp_r_brk_clients r_clients;
- reg_marb_bar_bp_r_brk_addr r_addr;
- reg_marb_bar_bp_r_brk_op r_op;
- reg_marb_bar_bp_r_brk_first_client r_first;
- reg_marb_bar_bp_r_brk_size r_size;
- reg_marb_bar_bp_rw_ack ack = {0};
- reg_marb_bar_rw_ack_intr ack_intr = {
- .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
- };
- struct crisv32_watch_entry *watch;
- unsigned arbiter = (unsigned)dev_id;
-
- masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
-
- if (masked_intr.bp0)
- watch = &watches[arbiter][0];
- else if (masked_intr.bp1)
- watch = &watches[arbiter][1];
- else if (masked_intr.bp2)
- watch = &watches[arbiter][2];
- else if (masked_intr.bp3)
- watch = &watches[arbiter][3];
- else
- return IRQ_NONE;
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size);
-
- printk(KERN_DEBUG "Arbiter IRQ\n");
- printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size));
-
- REG_WR(marb_bar_bp, watch->instance, rw_ack, ack);
- REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr);
-
- printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp);
-
- if (watch->cb)
- watch->cb();
-
- return IRQ_HANDLED;
-}
-
diff --git a/arch/cris/arch-v32/mach-a3/dma.c b/arch/cris/arch-v32/mach-a3/dma.c
deleted file mode 100644
index 3f4e923b2527..000000000000
--- a/arch/cris/arch-v32/mach-a3/dma.c
+++ /dev/null
@@ -1,184 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Wrapper for DMA channel allocator that starts clocks etc */
-
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <mach/dma.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_defs.h>
-#include <hwregs/clkgen_defs.h>
-#include <hwregs/strmux_defs.h>
-#include <linux/errno.h>
-#include <arbiter.h>
-
-static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
-
-static DEFINE_SPINLOCK(dma_lock);
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned int bandwidth, enum dma_owner owner)
-{
- unsigned long flags;
- reg_clkgen_rw_clk_ctrl clk_ctrl;
- reg_strmux_rw_cfg strmux_cfg;
-
- if (crisv32_arbiter_allocate_bandwidth(dmanr,
- options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
- bandwidth))
- return -ENOMEM;
-
- spin_lock_irqsave(&dma_lock, flags);
-
- if (used_dma_channels[dmanr]) {
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR)
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "already allocated by %s\n",
- dmanr,
- device_id,
- used_dma_channels_users[dmanr]);
-
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EBUSY;
- }
- clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
- strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
-
- switch (dmanr) {
- case 0:
- case 1:
- clk_ctrl.dma0_1_eth = 1;
- break;
- case 2:
- case 3:
- clk_ctrl.dma2_3_strcop = 1;
- break;
- case 4:
- case 5:
- clk_ctrl.dma4_5_iop = 1;
- break;
- case 6:
- case 7:
- clk_ctrl.sser_ser_dma6_7 = 1;
- break;
- case 9:
- case 11:
- clk_ctrl.dma9_11 = 1;
- break;
-#if MAX_DMA_CHANNELS-1 != 11
-#error Check dma.c
-#endif
- default:
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR)
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "only 0-%i valid)\n",
- dmanr, device_id, MAX_DMA_CHANNELS-1);
-
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EINVAL;
- }
-
- switch (owner) {
- case dma_eth:
- if (dmanr == 0)
- strmux_cfg.dma0 = regk_strmux_eth;
- else if (dmanr == 1)
- strmux_cfg.dma1 = regk_strmux_eth;
- else
- panic("Invalid DMA channel for eth\n");
- break;
- case dma_ser0:
- if (dmanr == 0)
- strmux_cfg.dma0 = regk_strmux_ser0;
- else if (dmanr == 1)
- strmux_cfg.dma1 = regk_strmux_ser0;
- else
- panic("Invalid DMA channel for ser0\n");
- break;
- case dma_ser3:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ser3;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ser3;
- else
- panic("Invalid DMA channel for ser3\n");
- break;
- case dma_strp:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_strcop;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_strcop;
- else
- panic("Invalid DMA channel for strp\n");
- break;
- case dma_ser1:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_ser1;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_ser1;
- else
- panic("Invalid DMA channel for ser1\n");
- break;
- case dma_iop:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_iop;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_iop;
- else
- panic("Invalid DMA channel for iop\n");
- break;
- case dma_ser2:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_ser2;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_ser2;
- else
- panic("Invalid DMA channel for ser2\n");
- break;
- case dma_sser:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_sser;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_sser;
- else
- panic("Invalid DMA channel for sser\n");
- break;
- case dma_ser4:
- if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_ser4;
- else
- panic("Invalid DMA channel for ser4\n");
- break;
- case dma_jpeg:
- if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_jpeg;
- else
- panic("Invalid DMA channel for JPEG\n");
- break;
- case dma_h264:
- if (dmanr == 11)
- strmux_cfg.dma11 = regk_strmux_h264;
- else
- panic("Invalid DMA channel for H264\n");
- break;
- }
-
- used_dma_channels[dmanr] = 1;
- used_dma_channels_users[dmanr] = device_id;
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
- REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
- spin_unlock_irqrestore(&dma_lock, flags);
- return 0;
-}
-
-void crisv32_free_dma(unsigned int dmanr)
-{
- spin_lock(&dma_lock);
- used_dma_channels[dmanr] = 0;
- spin_unlock(&dma_lock);
-}
diff --git a/arch/cris/arch-v32/mach-a3/dram_init.S b/arch/cris/arch-v32/mach-a3/dram_init.S
deleted file mode 100644
index 733c3564ad79..000000000000
--- a/arch/cris/arch-v32/mach-a3/dram_init.S
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DDR SDRAM initialization - alter with care
- * This file is intended to be included from other assembler files
- *
- * Note: This file may not modify r8 or r9 because they are used to
- * carry information from the decompressor to the kernel
- *
- * Copyright (C) 2005-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
- * uses this code.
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/ddr2_defs_asm.h>
-
- ;; WARNING! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below.
-
- ;; Refer to ddr2 MDS for initialization sequence
-
- ; 2. Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Start clock
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
- move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
- move.d $r1, [$r0]
-
- ; 2. Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Reset phy and start calibration
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
- move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
- REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
- move.d $r1, [$r0]
- move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
- move.d $r1, [$r0]
-
- ; 2. Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Issue commands
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
- move.d sdram_commands_start, $r2
-command_loop:
- movu.b [$r2+], $r1
- movu.w [$r2+], $r3
-do_cmd:
- lslq 16, $r1
- or.d $r3, $r1
- move.d $r1, [$r0]
- ; 2. Wait 200us
- move.d 10000, $r4
-1: bne 1b
- subq 1, $r4
- cmp.d sdram_commands_end, $r2
- blo command_loop
- nop
-
- ; Set timing
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
- move.d CONFIG_ETRAX_DDR2_TIMING, $r1
- move.d $r1, [$r0]
-
- ; Set latency
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
- move.d CONFIG_ETRAX_DDR2_LATENCY, $r1
- move.d $r1, [$r0]
-
- ; Set configuration
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
- move.d CONFIG_ETRAX_DDR2_CONFIG, $r1
- move.d $r1, [$r0]
-
- ba after_sdram_commands
- nop
-
-sdram_commands_start:
- .byte regk_ddr2_deselect
- .word 0
- .byte regk_ddr2_pre
- .word regk_ddr2_pre_all
- .byte regk_ddr2_emrs2
- .word 0
- .byte regk_ddr2_emrs3
- .word 0
- .byte regk_ddr2_emrs
- .word regk_ddr2_dll_en
- .byte regk_ddr2_mrs
- .word regk_ddr2_dll_rst
- .byte regk_ddr2_pre
- .word regk_ddr2_pre_all
- .byte regk_ddr2_ref
- .word 0
- .byte regk_ddr2_ref
- .word 0
- .byte regk_ddr2_mrs
- .word CONFIG_ETRAX_DDR2_MRS & 0xffff
- .byte regk_ddr2_emrs
- .word regk_ddr2_ocd_default | regk_ddr2_dll_en
- .byte regk_ddr2_emrs
- .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
-sdram_commands_end:
- .align 1
-after_sdram_commands:
diff --git a/arch/cris/arch-v32/mach-a3/hw_settings.S b/arch/cris/arch-v32/mach-a3/hw_settings.S
deleted file mode 100644
index 7c325cc59e1f..000000000000
--- a/arch/cris/arch-v32/mach-a3/hw_settings.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This table is used by some tools to extract hardware parameters.
- * The table should be included in the kernel and the decompressor.
- * Don't forget to update the tools if you change this table.
- *
- * Copyright (C) 2001-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/ddr2_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-
- .ascii "HW_PARAM_MAGIC" ; Magic number
- .dword 0xc0004000 ; Kernel start address
-
- ; Debug port
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- .dword 0
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- .dword 1
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- .dword 2
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- .dword 3
-#else
- .dword 4 ; No debug
-#endif
-
- ; Register values
- .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
- .dword CONFIG_ETRAX_DDR2_CONFIG
- .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency)
- .dword CONFIG_ETRAX_DDR2_LATENCY
- .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
- .dword CONFIG_ETRAX_DDR2_TIMING
- .dword CONFIG_ETRAX_DDR2_MRS
-
- .dword REG_ADDR(gio, regi_gio, rw_pa_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pa_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OE
- .dword REG_ADDR(gio, regi_gio, rw_pb_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pb_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OE
- .dword REG_ADDR(gio, regi_gio, rw_pc_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pc_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OE
-
- .dword 0 ; No more register values
diff --git a/arch/cris/arch-v32/mach-a3/pinmux.c b/arch/cris/arch-v32/mach-a3/pinmux.c
deleted file mode 100644
index 4875bf7aa53f..000000000000
--- a/arch/cris/arch-v32/mach-a3/pinmux.c
+++ /dev/null
@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
- * Unassigned pins and GPIO pins can be allocated to a fixed interface
- * or the I/O processor instead.
- *
- * Copyright (c) 2005-2007 Axis Communications AB.
- */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <pinmux.h>
-#include <hwregs/pinmux_defs.h>
-#include <hwregs/clkgen_defs.h>
-
-#undef DEBUG
-
-#define PINS 80
-#define PORT_PINS 32
-#define PORTS 3
-
-static char pins[PINS];
-static DEFINE_SPINLOCK(pinmux_lock);
-
-static void crisv32_pinmux_set(int port);
-
-int
-crisv32_pinmux_init(void)
-{
- static int initialized;
-
- if (!initialized) {
- initialized = 1;
- REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
- crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio);
- crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio);
- crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio);
- }
-
- return 0;
-}
-
-int
-crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
-{
- int i;
- unsigned long flags;
-
- crisv32_pinmux_init();
-
- if (port >= PORTS)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- for (i = first_pin; i <= last_pin; i++) {
- if ((pins[port * PORT_PINS + i] != pinmux_none) &&
- (pins[port * PORT_PINS + i] != pinmux_gpio) &&
- (pins[port * PORT_PINS + i] != mode)) {
- spin_unlock_irqrestore(&pinmux_lock, flags);
-#ifdef DEBUG
- panic("Pinmux alloc failed!\n");
-#endif
- return -EPERM;
- }
- }
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port * PORT_PINS + i] = mode;
-
- crisv32_pinmux_set(port);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return 0;
-}
-
-int
-crisv32_pinmux_alloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
- reg_clkgen_rw_clk_ctrl clk_ctrl;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
- clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
-
- switch (function) {
- case pinmux_eth:
- clk_ctrl.eth = regk_clkgen_yes;
- clk_ctrl.dma0_1_eth = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed);
- hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes;
- break;
- case pinmux_geth:
- ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed);
- hwprot.geth = regk_pinmux_yes;
- break;
- case pinmux_tg_cmos:
- clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed);
- hwprot.tg_clk = regk_pinmux_yes;
- break;
- case pinmux_tg_ccd:
- clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed);
- hwprot.tg = hwprot.tg_clk = regk_pinmux_yes;
- break;
- case pinmux_vout:
- clk_ctrl.strdma0_2_video = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed);
- hwprot.vout = hwprot.vout_sync = regk_pinmux_yes;
- break;
- case pinmux_ser1:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed);
- hwprot.ser1 = regk_pinmux_yes;
- break;
- case pinmux_ser2:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed);
- hwprot.ser2 = regk_pinmux_yes;
- break;
- case pinmux_ser3:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed);
- hwprot.ser3 = regk_pinmux_yes;
- break;
- case pinmux_ser4:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed);
- hwprot.ser4 = regk_pinmux_yes;
- break;
- case pinmux_sser:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed);
- hwprot.sser = regk_pinmux_yes;
- break;
- case pinmux_pio:
- hwprot.pio = regk_pinmux_yes;
- ret = 0;
- break;
- case pinmux_pwm0:
- ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed);
- hwprot.pwm0 = regk_pinmux_yes;
- break;
- case pinmux_pwm1:
- ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed);
- hwprot.pwm1 = regk_pinmux_yes;
- break;
- case pinmux_pwm2:
- ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed);
- hwprot.pwm2 = regk_pinmux_yes;
- break;
- case pinmux_i2c0:
- ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed);
- hwprot.i2c0 = regk_pinmux_yes;
- break;
- case pinmux_i2c1:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- hwprot.i2c1 = regk_pinmux_yes;
- break;
- case pinmux_i2c1_3wire:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes;
- break;
- case pinmux_i2c1_sda1:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes;
- break;
- case pinmux_i2c1_sda2:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes;
- break;
- case pinmux_i2c1_sda3:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- if (!ret) {
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
- } else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-void
-crisv32_pinmux_set(int port)
-{
- int i;
- int gpio_val = 0;
- int iop_val = 0;
- int pin = port * PORT_PINS;
-
- for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) {
- if (pins[pin] == pinmux_gpio)
- gpio_val |= (1 << i);
- else if (pins[pin] == pinmux_iop)
- iop_val |= (1 << i);
- }
-
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port,
- gpio_val);
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port,
- iop_val);
-
-#ifdef DEBUG
- crisv32_pinmux_dump();
-#endif
-}
-
-int
-crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
-{
- int i;
- unsigned long flags;
-
- crisv32_pinmux_init();
-
- if (port > PORTS || port < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port * PORT_PINS + i] = pinmux_none;
-
- crisv32_pinmux_set(port);
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return 0;
-}
-
-int
-crisv32_pinmux_dealloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-
- switch (function) {
- case pinmux_eth:
- ret = crisv32_pinmux_dealloc(PORT_B, 8, 23);
- ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25);
- ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7);
- hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no;
- break;
- case pinmux_tg_cmos:
- ret = crisv32_pinmux_dealloc(PORT_B, 27, 29);
- hwprot.tg_clk = regk_pinmux_no;
- break;
- case pinmux_tg_ccd:
- ret = crisv32_pinmux_dealloc(PORT_B, 27, 31);
- ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15);
- hwprot.tg = hwprot.tg_clk = regk_pinmux_no;
- break;
- case pinmux_vout:
- ret = crisv32_pinmux_dealloc(PORT_A, 8, 18);
- hwprot.vout = hwprot.vout_sync = regk_pinmux_no;
- break;
- case pinmux_ser1:
- ret = crisv32_pinmux_dealloc(PORT_A, 24, 25);
- hwprot.ser1 = regk_pinmux_no;
- break;
- case pinmux_ser2:
- ret = crisv32_pinmux_dealloc(PORT_A, 26, 27);
- hwprot.ser2 = regk_pinmux_no;
- break;
- case pinmux_ser3:
- ret = crisv32_pinmux_dealloc(PORT_A, 28, 29);
- hwprot.ser3 = regk_pinmux_no;
- break;
- case pinmux_ser4:
- ret = crisv32_pinmux_dealloc(PORT_A, 30, 31);
- hwprot.ser4 = regk_pinmux_no;
- break;
- case pinmux_sser:
- ret = crisv32_pinmux_dealloc(PORT_A, 19, 23);
- hwprot.sser = regk_pinmux_no;
- break;
- case pinmux_pwm0:
- ret = crisv32_pinmux_dealloc(PORT_A, 30, 30);
- hwprot.pwm0 = regk_pinmux_no;
- break;
- case pinmux_pwm1:
- ret = crisv32_pinmux_dealloc(PORT_A, 31, 31);
- hwprot.pwm1 = regk_pinmux_no;
- break;
- case pinmux_pwm2:
- ret = crisv32_pinmux_dealloc(PORT_B, 26, 26);
- hwprot.pwm2 = regk_pinmux_no;
- break;
- case pinmux_i2c0:
- ret = crisv32_pinmux_dealloc(PORT_A, 0, 1);
- hwprot.i2c0 = regk_pinmux_no;
- break;
- case pinmux_i2c1:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- hwprot.i2c1 = regk_pinmux_no;
- break;
- case pinmux_i2c1_3wire:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7);
- hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no;
- break;
- case pinmux_i2c1_sda1:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 4);
- hwprot.i2c1_sda1 = regk_pinmux_no;
- break;
- case pinmux_i2c1_sda2:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5);
- hwprot.i2c1_sda2 = regk_pinmux_no;
- break;
- case pinmux_i2c1_sda3:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6);
- hwprot.i2c1_sda3 = regk_pinmux_no;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- if (!ret)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-void
-crisv32_pinmux_dump(void)
-{
- int i, j;
- int pin = 0;
-
- crisv32_pinmux_init();
-
- for (i = 0; i < PORTS; i++) {
- pin++;
- printk(KERN_DEBUG "Port %c\n", 'A'+i);
- for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++)
- printk(KERN_DEBUG
- " Pin %d = %d\n", j, pins[i * PORT_PINS + j]);
- }
-}
-
-__initcall(crisv32_pinmux_init);
diff --git a/arch/cris/arch-v32/mach-fs/Kconfig b/arch/cris/arch-v32/mach-fs/Kconfig
deleted file mode 100644
index 743ba3bcbaec..000000000000
--- a/arch/cris/arch-v32/mach-fs/Kconfig
+++ /dev/null
@@ -1,198 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAXFS
-
-menu "ETRAX FS options"
- depends on ETRAXFS
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- depends on ETRAX_ARCH_V32
- default "c0000000"
-
-config ETRAX_SERIAL_PORTS
- int
- default 4
-
-config ETRAX_MEM_GRP1_CONFIG
- hex "MEM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "4044a"
- help
- Waitstates for flash. The default value is suitable for the
- standard flashes used in axis products (120 ns).
-
-config ETRAX_MEM_GRP2_CONFIG
- hex "MEM_GRP2_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for SRAM. 0 is a good choice for most Axis products.
-
-config ETRAX_MEM_GRP3_CONFIG
- hex "MEM_GRP3_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP0-3. 0 is a good choice for most Axis products.
- It may need to be changed if external devices such as extra
- register-mapped LEDs are used.
-
-config ETRAX_MEM_GRP4_CONFIG
- hex "MEM_GRP4_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP4-6. 0 is a good choice for most Axis products.
-
-config ETRAX_SDRAM_GRP0_CONFIG
- hex "SDRAM_GRP0_CONFIG"
- depends on ETRAX_ARCH_V32
- default "336"
- help
- SDRAM configuration for group 0. The value depends on the
- hardware configuration. The default value is suitable
- for 32 MB organized as two 16 bits chips (e.g. Axis
- part number 18550) connected as one 32 bit device (i.e. in
- the same group).
-
-config ETRAX_SDRAM_GRP1_CONFIG
- hex "SDRAM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM configuration for group 1. The default value is 0
- because group 1 is not used in the default configuration,
- described in the help for SDRAM_GRP0_CONFIG.
-
-config ETRAX_SDRAM_TIMING
- hex "SDRAM_TIMING"
- depends on ETRAX_ARCH_V32
- default "104a"
- help
- SDRAM timing parameters. The default value is ok for
- most hardwares but large SDRAMs may require a faster
- refresh (a.k.a 8K refresh). The default value implies
- 100MHz clock and SDR mode.
-
-config ETRAX_SDRAM_COMMAND
- hex "SDRAM_COMMAND"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM command. Should be 0 unless you really know what
- you are doing (may be != 0 for unusual address line
- mappings such as in a MCM)..
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- depends on ETRAX_ARCH_V32
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- depends on ETRAX_ARCH_V32
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PD_OE
- hex "GIO_PD_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port D bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PD_OUT
- hex "GIO_PD_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port D bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PE_OE
- hex "GIO_PE_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port E bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PE_OUT
- hex "GIO_PE_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port E bits. Most
- products should use 00000 here.
-
-endmenu
-
-endif
diff --git a/arch/cris/arch-v32/mach-fs/Makefile b/arch/cris/arch-v32/mach-fs/Makefile
deleted file mode 100644
index 0cc6eebacbed..000000000000
--- a/arch/cris/arch-v32/mach-fs/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := dma.o pinmux.o arbiter.o
-
-clean:
-
diff --git a/arch/cris/arch-v32/mach-fs/arbiter.c b/arch/cris/arch-v32/mach-fs/arbiter.c
deleted file mode 100644
index c4750d97e46c..000000000000
--- a/arch/cris/arch-v32/mach-fs/arbiter.c
+++ /dev/null
@@ -1,405 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Memory arbiter functions. Allocates bandwidth through the
- * arbiter and sets up arbiter breakpoints.
- *
- * The algorithm first assigns slots to the clients that has specified
- * bandwidth (e.g. ethernet) and then the remaining slots are divided
- * on all the active clients.
- *
- * Copyright (c) 2004-2007 Axis Communications AB.
- */
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_defs.h>
-#include <arbiter.h>
-#include <hwregs/intr_vect.h>
-#include <linux/interrupt.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <asm/io.h>
-#include <asm/irq_regs.h>
-
-struct crisv32_watch_entry {
- unsigned long instance;
- watch_callback *cb;
- unsigned long start;
- unsigned long end;
- int used;
-};
-
-#define NUMBER_OF_BP 4
-#define NBR_OF_CLIENTS 14
-#define NBR_OF_SLOTS 64
-#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */
-#define INTMEM_BANDWIDTH 400000000
-#define NBR_OF_REGIONS 2
-
-static struct crisv32_watch_entry watches[NUMBER_OF_BP] = {
- {regi_marb_bp0},
- {regi_marb_bp1},
- {regi_marb_bp2},
- {regi_marb_bp3}
-};
-
-static u8 requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-static u8 active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-static int max_bandwidth[NBR_OF_REGIONS] =
- { SDRAM_BANDWIDTH, INTMEM_BANDWIDTH };
-
-DEFINE_SPINLOCK(arbiter_lock);
-
-static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id);
-
-/*
- * "I'm the arbiter, I know the score.
- * From square one I'll be watching all 64."
- * (memory arbiter slots, that is)
- *
- * Or in other words:
- * Program the memory arbiter slots for "region" according to what's
- * in requested_slots[] and active_clients[], while minimizing
- * latency. A caller may pass a non-zero positive amount for
- * "unused_slots", which must then be the unallocated, remaining
- * number of slots, free to hand out to any client.
- */
-
-static void crisv32_arbiter_config(int region, int unused_slots)
-{
- int slot;
- int client;
- int interval = 0;
-
- /*
- * This vector corresponds to the hardware arbiter slots (see
- * the hardware documentation for semantics). We initialize
- * each slot with a suitable sentinel value outside the valid
- * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
- * client indexes. Then it's fed to the hardware.
- */
- s8 val[NBR_OF_SLOTS];
-
- for (slot = 0; slot < NBR_OF_SLOTS; slot++)
- val[slot] = -1;
-
- for (client = 0; client < NBR_OF_CLIENTS; client++) {
- int pos;
- /* Allocate the requested non-zero number of slots, but
- * also give clients with zero-requests one slot each
- * while stocks last. We do the latter here, in client
- * order. This makes sure zero-request clients are the
- * first to get to any spare slots, else those slots
- * could, when bandwidth is allocated close to the limit,
- * all be allocated to low-index non-zero-request clients
- * in the default-fill loop below. Another positive but
- * secondary effect is a somewhat better spread of the
- * zero-bandwidth clients in the vector, avoiding some of
- * the latency that could otherwise be caused by the
- * partitioning of non-zero-bandwidth clients at low
- * indexes and zero-bandwidth clients at high
- * indexes. (Note that this spreading can only affect the
- * unallocated bandwidth.) All the above only matters for
- * memory-intensive situations, of course.
- */
- if (!requested_slots[region][client]) {
- /*
- * Skip inactive clients. Also skip zero-slot
- * allocations in this pass when there are no known
- * free slots.
- */
- if (!active_clients[region][client]
- || unused_slots <= 0)
- continue;
-
- unused_slots--;
-
- /* Only allocate one slot for this client. */
- interval = NBR_OF_SLOTS;
- } else
- interval =
- NBR_OF_SLOTS / requested_slots[region][client];
-
- pos = 0;
- while (pos < NBR_OF_SLOTS) {
- if (val[pos] >= 0)
- pos++;
- else {
- val[pos] = client;
- pos += interval;
- }
- }
- }
-
- client = 0;
- for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
- /*
- * Allocate remaining slots in round-robin
- * client-number order for active clients. For this
- * pass, we ignore requested bandwidth and previous
- * allocations.
- */
- if (val[slot] < 0) {
- int first = client;
- while (!active_clients[region][client]) {
- client = (client + 1) % NBR_OF_CLIENTS;
- if (client == first)
- break;
- }
- val[slot] = client;
- client = (client + 1) % NBR_OF_CLIENTS;
- }
- if (region == EXT_REGION)
- REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot,
- val[slot]);
- else if (region == INT_REGION)
- REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot,
- val[slot]);
- }
-}
-
-extern char _stext[], _etext[];
-
-static void crisv32_arbiter_init(void)
-{
- static int initialized;
-
- if (initialized)
- return;
-
- initialized = 1;
-
- /*
- * CPU caches are always set to active, but with zero
- * bandwidth allocated. It should be ok to allocate zero
- * bandwidth for the caches, because DMA for other channels
- * will supposedly finish, once their programmed amount is
- * done, and then the caches will get access according to the
- * "fixed scheme" for unclaimed slots. Though, if for some
- * use-case somewhere, there's a maximum CPU latency for
- * e.g. some interrupt, we have to start allocating specific
- * bandwidth for the CPU caches too.
- */
- active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1;
- crisv32_arbiter_config(EXT_REGION, 0);
- crisv32_arbiter_config(INT_REGION, 0);
-
- if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, 0,
- "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
-#ifndef CONFIG_ETRAX_KGDB
- /* Global watch for writes to kernel text segment. */
- crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext,
- arbiter_all_clients, arbiter_all_write, NULL);
-#endif
-}
-
-/* Main entry for bandwidth allocation. */
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth)
-{
- int i;
- int total_assigned = 0;
- int total_clients = 0;
- int req;
-
- crisv32_arbiter_init();
-
- for (i = 0; i < NBR_OF_CLIENTS; i++) {
- total_assigned += requested_slots[region][i];
- total_clients += active_clients[region][i];
- }
-
- /* Avoid division by 0 for 0-bandwidth requests. */
- req = bandwidth == 0
- ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
-
- /*
- * We make sure that there are enough slots only for non-zero
- * requests. Requesting 0 bandwidth *may* allocate slots,
- * though if all bandwidth is allocated, such a client won't
- * get any and will have to rely on getting memory access
- * according to the fixed scheme that's the default when one
- * of the slot-allocated clients doesn't claim their slot.
- */
- if (total_assigned + req > NBR_OF_SLOTS)
- return -ENOMEM;
-
- active_clients[region][client] = 1;
- requested_slots[region][client] = req;
- crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned);
-
- return 0;
-}
-
-/*
- * Main entry for bandwidth deallocation.
- *
- * Strictly speaking, for a somewhat constant set of clients where
- * each client gets a constant bandwidth and is just enabled or
- * disabled (somewhat dynamically), no action is necessary here to
- * avoid starvation for non-zero-allocation clients, as the allocated
- * slots will just be unused. However, handing out those unused slots
- * to active clients avoids needless latency if the "fixed scheme"
- * would give unclaimed slots to an eager low-index client.
- */
-
-void crisv32_arbiter_deallocate_bandwidth(int client, int region)
-{
- int i;
- int total_assigned = 0;
-
- requested_slots[region][client] = 0;
- active_clients[region][client] = 0;
-
- for (i = 0; i < NBR_OF_CLIENTS; i++)
- total_assigned += requested_slots[region][i];
-
- crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned);
-}
-
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback *cb)
-{
- int i;
-
- crisv32_arbiter_init();
-
- if (start > 0x80000000) {
- printk(KERN_ERR "Arbiter: %lX doesn't look like a "
- "physical address", start);
- return -EFAULT;
- }
-
- spin_lock(&arbiter_lock);
-
- for (i = 0; i < NUMBER_OF_BP; i++) {
- if (!watches[i].used) {
- reg_marb_rw_intr_mask intr_mask =
- REG_RD(marb, regi_marb, rw_intr_mask);
-
- watches[i].used = 1;
- watches[i].start = start;
- watches[i].end = start + size;
- watches[i].cb = cb;
-
- REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr,
- watches[i].start);
- REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr,
- watches[i].end);
- REG_WR_INT(marb_bp, watches[i].instance, rw_op,
- accesses);
- REG_WR_INT(marb_bp, watches[i].instance, rw_clients,
- clients);
-
- if (i == 0)
- intr_mask.bp0 = regk_marb_yes;
- else if (i == 1)
- intr_mask.bp1 = regk_marb_yes;
- else if (i == 2)
- intr_mask.bp2 = regk_marb_yes;
- else if (i == 3)
- intr_mask.bp3 = regk_marb_yes;
-
- REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
- spin_unlock(&arbiter_lock);
-
- return i;
- }
- }
- spin_unlock(&arbiter_lock);
- return -ENOMEM;
-}
-
-int crisv32_arbiter_unwatch(int id)
-{
- reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
-
- crisv32_arbiter_init();
-
- spin_lock(&arbiter_lock);
-
- if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) {
- spin_unlock(&arbiter_lock);
- return -EINVAL;
- }
-
- memset(&watches[id], 0, sizeof(struct crisv32_watch_entry));
-
- if (id == 0)
- intr_mask.bp0 = regk_marb_no;
- else if (id == 1)
- intr_mask.bp1 = regk_marb_no;
- else if (id == 2)
- intr_mask.bp2 = regk_marb_no;
- else if (id == 3)
- intr_mask.bp3 = regk_marb_no;
-
- REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
-
- spin_unlock(&arbiter_lock);
- return 0;
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id)
-{
- reg_marb_r_masked_intr masked_intr =
- REG_RD(marb, regi_marb, r_masked_intr);
- reg_marb_bp_r_brk_clients r_clients;
- reg_marb_bp_r_brk_addr r_addr;
- reg_marb_bp_r_brk_op r_op;
- reg_marb_bp_r_brk_first_client r_first;
- reg_marb_bp_r_brk_size r_size;
- reg_marb_bp_rw_ack ack = { 0 };
- reg_marb_rw_ack_intr ack_intr = {
- .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
- };
- struct crisv32_watch_entry *watch;
-
- if (masked_intr.bp0) {
- watch = &watches[0];
- ack_intr.bp0 = regk_marb_yes;
- } else if (masked_intr.bp1) {
- watch = &watches[1];
- ack_intr.bp1 = regk_marb_yes;
- } else if (masked_intr.bp2) {
- watch = &watches[2];
- ack_intr.bp2 = regk_marb_yes;
- } else if (masked_intr.bp3) {
- watch = &watches[3];
- ack_intr.bp3 = regk_marb_yes;
- } else {
- return IRQ_NONE;
- }
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_bp, watch->instance, r_brk_size);
-
- printk(KERN_INFO "Arbiter IRQ\n");
- printk(KERN_INFO "Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size));
-
- REG_WR(marb_bp, watch->instance, rw_ack, ack);
- REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
-
- printk(KERN_INFO "IRQ occurred at %lX\n", get_irq_regs()->erp);
-
- if (watch->cb)
- watch->cb();
-
- return IRQ_HANDLED;
-}
diff --git a/arch/cris/arch-v32/mach-fs/dma.c b/arch/cris/arch-v32/mach-fs/dma.c
deleted file mode 100644
index c0347a4f8c65..000000000000
--- a/arch/cris/arch-v32/mach-fs/dma.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Wrapper for DMA channel allocator that starts clocks etc */
-
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <asm/dma.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_defs.h>
-#include <hwregs/config_defs.h>
-#include <hwregs/strmux_defs.h>
-#include <linux/errno.h>
-#include <mach/arbiter.h>
-
-static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
-
-static DEFINE_SPINLOCK(dma_lock);
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned int bandwidth,
- enum dma_owner owner)
-{
- unsigned long flags;
- reg_config_rw_clk_ctrl clk_ctrl;
- reg_strmux_rw_cfg strmux_cfg;
-
- if (crisv32_arbiter_allocate_bandwidth(dmanr,
- options & DMA_INT_MEM ?
- INT_REGION : EXT_REGION,
- bandwidth))
- return -ENOMEM;
-
- spin_lock_irqsave(&dma_lock, flags);
-
- if (used_dma_channels[dmanr]) {
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR) {
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "already allocated by %s\n",
- dmanr,
- device_id,
- used_dma_channels_users[dmanr]);
- }
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EBUSY;
- }
- clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
- strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
-
- switch (dmanr) {
- case 0:
- case 1:
- clk_ctrl.dma01_eth0 = 1;
- break;
- case 2:
- case 3:
- clk_ctrl.dma23 = 1;
- break;
- case 4:
- case 5:
- clk_ctrl.dma45 = 1;
- break;
- case 6:
- case 7:
- clk_ctrl.dma67 = 1;
- break;
- case 8:
- case 9:
- clk_ctrl.dma89_strcop = 1;
- break;
-#if MAX_DMA_CHANNELS-1 != 9
-#error Check dma.c
-#endif
- default:
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR) {
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "only 0-%i valid)\n",
- dmanr, device_id, MAX_DMA_CHANNELS - 1);
- }
-
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EINVAL;
- }
-
- switch (owner) {
- case dma_eth0:
- if (dmanr == 0)
- strmux_cfg.dma0 = regk_strmux_eth0;
- else if (dmanr == 1)
- strmux_cfg.dma1 = regk_strmux_eth0;
- else
- panic("Invalid DMA channel for eth0\n");
- break;
- case dma_eth1:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_eth1;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_eth1;
- else
- panic("Invalid DMA channel for eth1\n");
- break;
- case dma_iop0:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_iop0;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_iop0;
- else
- panic("Invalid DMA channel for iop0\n");
- break;
- case dma_iop1:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_iop1;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_iop1;
- else
- panic("Invalid DMA channel for iop1\n");
- break;
- case dma_ser0:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_ser0;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_ser0;
- else
- panic("Invalid DMA channel for ser0\n");
- break;
- case dma_ser1:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_ser1;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_ser1;
- else
- panic("Invalid DMA channel for ser1\n");
- break;
- case dma_ser2:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ser2;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ser2;
- else
- panic("Invalid DMA channel for ser2\n");
- break;
- case dma_ser3:
- if (dmanr == 8)
- strmux_cfg.dma8 = regk_strmux_ser3;
- else if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_ser3;
- else
- panic("Invalid DMA channel for ser3\n");
- break;
- case dma_sser0:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_sser0;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_sser0;
- else
- panic("Invalid DMA channel for sser0\n");
- break;
- case dma_sser1:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_sser1;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_sser1;
- else
- panic("Invalid DMA channel for sser1\n");
- break;
- case dma_ata:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ata;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ata;
- else
- panic("Invalid DMA channel for ata\n");
- break;
- case dma_strp:
- if (dmanr == 8)
- strmux_cfg.dma8 = regk_strmux_strcop;
- else if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_strcop;
- else
- panic("Invalid DMA channel for strp\n");
- break;
- case dma_ext0:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_ext0;
- else
- panic("Invalid DMA channel for ext0\n");
- break;
- case dma_ext1:
- if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_ext1;
- else
- panic("Invalid DMA channel for ext1\n");
- break;
- case dma_ext2:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ext2;
- else if (dmanr == 8)
- strmux_cfg.dma8 = regk_strmux_ext2;
- else
- panic("Invalid DMA channel for ext2\n");
- break;
- case dma_ext3:
- if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ext3;
- else if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_ext2;
- else
- panic("Invalid DMA channel for ext2\n");
- break;
- }
-
- used_dma_channels[dmanr] = 1;
- used_dma_channels_users[dmanr] = device_id;
- REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
- REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
- spin_unlock_irqrestore(&dma_lock, flags);
- return 0;
-}
-
-void crisv32_free_dma(unsigned int dmanr)
-{
- spin_lock(&dma_lock);
- used_dma_channels[dmanr] = 0;
- spin_unlock(&dma_lock);
-}
diff --git a/arch/cris/arch-v32/mach-fs/dram_init.S b/arch/cris/arch-v32/mach-fs/dram_init.S
deleted file mode 100644
index e1a01fa4c272..000000000000
--- a/arch/cris/arch-v32/mach-fs/dram_init.S
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DRAM/SDRAM initialization - alter with care
- * This file is intended to be included from other assembler files
- *
- * Note: This file may not modify r8 or r9 because they are used to
- * carry information from the decompressor to the kernel
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
- * uses this code.
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-
- ;; WARNING! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below.
-
- ; Refer to BIF MDS for a description of SDRAM initialization
-
- ; Bank configuration
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
- move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
- move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
- move.d $r1, [$r0]
-
- ; Calculate value of mrs_data
- ; CAS latency = 2 && bus_width = 32 => 0x40
- ; CAS latency = 3 && bus_width = 32 => 0x60
- ; CAS latency = 2 && bus_width = 16 => 0x20
- ; CAS latency = 3 && bus_width = 16 => 0x30
-
- ; Check if value is already supplied in kernel config
- move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2
- bne _set_timing
- nop
-
- move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2
- move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- and.d 0x07, $r1 ; Get CAS latency
- cmpq 2, $r1 ; CL = 2 ?
- beq _bw_check
- nop
- move.d 0x60, $r4
-
-_bw_check:
- ; Assume that group 0 width is equal to group 1. This assumption
- ; is wrong for a group 1 only hardware (such as the grand old
- ; StorPoint+).
- move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
- and.d 0x200, $r1 ; DRAM width is bit 9
- beq _set_timing
- lslq 2, $r4 ; mrs_data starts at bit 2
- lsrq 1, $r4 ; 16 bits. Shift down value.
-
- ; Set timing parameters (refresh off to avoid Guinness TR 83)
-_set_timing:
- move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
- move.d $r1, [$r0]
-
- ; Issue NOP command
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
- moveq regk_bif_core_nop, $r1
- move.d $r1, [$r5]
-
- ; Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Issue initialization command sequence
- lapc _sdram_commands_start, $r2
- lapc _sdram_commands_end, $r3
-1: clear.d $r6
- move.b [$r2+], $r6 ; Load command
- or.d $r4, $r6 ; Add calculated mrs
- move.d $r6, [$r5] ; Write rw_sdram_cmd
- ; Wait 80 ns between each command
- move.d 4000, $r7
-2: bne 2b
- subq 1, $r7
- cmp.d $r2, $r3 ; Last command?
- bne 1b
- nop
-
- ; Start refresh
- move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
- move.d $r1, [$r0]
-
- ; Initialization finished
- ba _sdram_commands_end
- nop
-
-_sdram_commands_start:
- .byte regk_bif_core_pre ; Precharge
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_mrs ; mrs
-_sdram_commands_end:
diff --git a/arch/cris/arch-v32/mach-fs/hw_settings.S b/arch/cris/arch-v32/mach-fs/hw_settings.S
deleted file mode 100644
index 7fbadcc48c0c..000000000000
--- a/arch/cris/arch-v32/mach-fs/hw_settings.S
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This table is used by some tools to extract hardware parameters.
- * The table should be included in the kernel and the decompressor.
- * Don't forget to update the tools if you change this table.
- *
- * Copyright (C) 2001-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-
- .ascii "HW_PARAM_MAGIC" ; Magic number
- .dword 0xc0004000 ; Kernel start address
-
- ; Debug port
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- .dword 0
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- .dword 1
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- .dword 2
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- .dword 3
-#else
- .dword 4 ; No debug
-#endif
-
- ; Register values
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg)
- .dword CONFIG_ETRAX_MEM_GRP1_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg)
- .dword CONFIG_ETRAX_MEM_GRP2_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg)
- .dword CONFIG_ETRAX_MEM_GRP3_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg)
- .dword CONFIG_ETRAX_MEM_GRP4_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0)
- .dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1)
- .dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing)
- .dword CONFIG_ETRAX_SDRAM_TIMING
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd)
- .dword CONFIG_ETRAX_SDRAM_COMMAND
-
- .dword REG_ADDR(gio, regi_gio, rw_pa_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pa_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OE
- .dword REG_ADDR(gio, regi_gio, rw_pb_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pb_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OE
- .dword REG_ADDR(gio, regi_gio, rw_pc_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pc_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OE
- .dword REG_ADDR(gio, regi_gio, rw_pd_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PD_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pd_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PD_OE
- .dword REG_ADDR(gio, regi_gio, rw_pe_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PE_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pe_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PE_OE
-
- .dword 0 ; No more register values
diff --git a/arch/cris/arch-v32/mach-fs/pinmux.c b/arch/cris/arch-v32/mach-fs/pinmux.c
deleted file mode 100644
index a0b2f101003a..000000000000
--- a/arch/cris/arch-v32/mach-fs/pinmux.c
+++ /dev/null
@@ -1,328 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
- * Unassigned pins and GPIO pins can be allocated to a fixed interface
- * or the I/O processor instead.
- *
- * Copyright (c) 2004-2007 Axis Communications AB.
- */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <pinmux.h>
-#include <hwregs/pinmux_defs.h>
-
-#undef DEBUG
-
-#define PORT_PINS 18
-#define PORTS 4
-
-static char pins[PORTS][PORT_PINS];
-static DEFINE_SPINLOCK(pinmux_lock);
-
-static void crisv32_pinmux_set(int port);
-
-static int __crisv32_pinmux_alloc(int port, int first_pin, int last_pin,
- enum pin_mode mode)
-{
- int i;
-
- for (i = first_pin; i <= last_pin; i++) {
- if ((pins[port][i] != pinmux_none)
- && (pins[port][i] != pinmux_gpio)
- && (pins[port][i] != mode)) {
-#ifdef DEBUG
- panic("Pinmux alloc failed!\n");
-#endif
- return -EPERM;
- }
- }
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port][i] = mode;
-
- crisv32_pinmux_set(port);
-
- return 0;
-}
-
-static int crisv32_pinmux_init(void)
-{
- static int initialized;
-
- if (!initialized) {
- reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa);
- initialized = 1;
- REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
- pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 =
- pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes;
- REG_WR(pinmux, regi_pinmux, rw_pa, pa);
- __crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio);
- __crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio);
- __crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio);
- __crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio);
- }
-
- return 0;
-}
-
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin,
- enum pin_mode mode)
-{
- unsigned long flags;
- int ret;
-
- crisv32_pinmux_init();
-
- if (port > PORTS || port < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- ret = __crisv32_pinmux_alloc(port, first_pin, last_pin, mode);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-int crisv32_pinmux_alloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-
- switch (function) {
- case pinmux_ser1:
- ret = __crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed);
- hwprot.ser1 = regk_pinmux_yes;
- break;
- case pinmux_ser2:
- ret = __crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed);
- hwprot.ser2 = regk_pinmux_yes;
- break;
- case pinmux_ser3:
- ret = __crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed);
- hwprot.ser3 = regk_pinmux_yes;
- break;
- case pinmux_sser0:
- ret = __crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
- hwprot.sser0 = regk_pinmux_yes;
- break;
- case pinmux_sser1:
- ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
- hwprot.sser1 = regk_pinmux_yes;
- break;
- case pinmux_ata0:
- ret = __crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed);
- hwprot.ata0 = regk_pinmux_yes;
- break;
- case pinmux_ata1:
- ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed);
- hwprot.ata1 = regk_pinmux_yes;
- break;
- case pinmux_ata2:
- ret = __crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed);
- hwprot.ata2 = regk_pinmux_yes;
- break;
- case pinmux_ata3:
- ret = __crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed);
- hwprot.ata2 = regk_pinmux_yes;
- break;
- case pinmux_ata:
- ret = __crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed);
- hwprot.ata = regk_pinmux_yes;
- break;
- case pinmux_eth1:
- ret = __crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed);
- hwprot.eth1 = regk_pinmux_yes;
- hwprot.eth1_mgm = regk_pinmux_yes;
- break;
- case pinmux_timer:
- ret = __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
- hwprot.timer = regk_pinmux_yes;
- spin_unlock_irqrestore(&pinmux_lock, flags);
- return ret;
- }
-
- if (!ret)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-void crisv32_pinmux_set(int port)
-{
- int i;
- int gpio_val = 0;
- int iop_val = 0;
-
- for (i = 0; i < PORT_PINS; i++) {
- if (pins[port][i] == pinmux_gpio)
- gpio_val |= (1 << i);
- else if (pins[port][i] == pinmux_iop)
- iop_val |= (1 << i);
- }
-
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port,
- gpio_val);
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port,
- iop_val);
-
-#ifdef DEBUG
- crisv32_pinmux_dump();
-#endif
-}
-
-static int __crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
-{
- int i;
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port][i] = pinmux_none;
-
- crisv32_pinmux_set(port);
- return 0;
-}
-
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
-{
- unsigned long flags;
-
- crisv32_pinmux_init();
-
- if (port > PORTS || port < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
- __crisv32_pinmux_dealloc(port, first_pin, last_pin);
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return 0;
-}
-
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-
- switch (function) {
- case pinmux_ser1:
- ret = __crisv32_pinmux_dealloc(PORT_C, 4, 7);
- hwprot.ser1 = regk_pinmux_no;
- break;
- case pinmux_ser2:
- ret = __crisv32_pinmux_dealloc(PORT_C, 8, 11);
- hwprot.ser2 = regk_pinmux_no;
- break;
- case pinmux_ser3:
- ret = __crisv32_pinmux_dealloc(PORT_C, 12, 15);
- hwprot.ser3 = regk_pinmux_no;
- break;
- case pinmux_sser0:
- ret = __crisv32_pinmux_dealloc(PORT_C, 0, 3);
- ret |= __crisv32_pinmux_dealloc(PORT_C, 16, 16);
- hwprot.sser0 = regk_pinmux_no;
- break;
- case pinmux_sser1:
- ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4);
- hwprot.sser1 = regk_pinmux_no;
- break;
- case pinmux_ata0:
- ret = __crisv32_pinmux_dealloc(PORT_D, 5, 7);
- ret |= __crisv32_pinmux_dealloc(PORT_D, 15, 17);
- hwprot.ata0 = regk_pinmux_no;
- break;
- case pinmux_ata1:
- ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4);
- ret |= __crisv32_pinmux_dealloc(PORT_E, 17, 17);
- hwprot.ata1 = regk_pinmux_no;
- break;
- case pinmux_ata2:
- ret = __crisv32_pinmux_dealloc(PORT_C, 11, 15);
- ret |= __crisv32_pinmux_dealloc(PORT_E, 3, 3);
- hwprot.ata2 = regk_pinmux_no;
- break;
- case pinmux_ata3:
- ret = __crisv32_pinmux_dealloc(PORT_C, 8, 10);
- ret |= __crisv32_pinmux_dealloc(PORT_C, 0, 2);
- hwprot.ata2 = regk_pinmux_no;
- break;
- case pinmux_ata:
- ret = __crisv32_pinmux_dealloc(PORT_B, 0, 15);
- ret |= __crisv32_pinmux_dealloc(PORT_D, 8, 15);
- hwprot.ata = regk_pinmux_no;
- break;
- case pinmux_eth1:
- ret = __crisv32_pinmux_dealloc(PORT_E, 0, 17);
- hwprot.eth1 = regk_pinmux_no;
- hwprot.eth1_mgm = regk_pinmux_no;
- break;
- case pinmux_timer:
- ret = __crisv32_pinmux_dealloc(PORT_C, 16, 16);
- hwprot.timer = regk_pinmux_no;
- spin_unlock_irqrestore(&pinmux_lock, flags);
- return ret;
- }
-
- if (!ret)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-#ifdef DEBUG
-static void crisv32_pinmux_dump(void)
-{
- int i, j;
-
- crisv32_pinmux_init();
-
- for (i = 0; i < PORTS; i++) {
- printk(KERN_DEBUG "Port %c\n", 'B' + i);
- for (j = 0; j < PORT_PINS; j++)
- printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]);
- }
-}
-#endif
-__initcall(crisv32_pinmux_init);
diff --git a/arch/cris/arch-v32/mm/Makefile b/arch/cris/arch-v32/mm/Makefile
deleted file mode 100644
index 0b801f2964ac..000000000000
--- a/arch/cris/arch-v32/mm/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# Makefile for the Linux/cris parts of the memory manager.
-
-obj-y += mmu.o init.o tlb.o intmem.o
-obj-$(CONFIG_ETRAX_L2CACHE) += l2cache.o
diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
deleted file mode 100644
index 784876afa001..000000000000
--- a/arch/cris/arch-v32/mm/init.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Set up paging and the MMU.
- *
- * Copyright (C) 2000-2003, Axis Communications AB.
- *
- * Authors: Bjorn Wesen <bjornw@axis.com>
- * Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
- */
-#include <linux/mmzone.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/types.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <arch/hwregs/asm/mmu_defs_asm.h>
-#include <arch/hwregs/supp_reg.h>
-
-extern void tlb_init(void);
-
-/*
- * The kernel is already mapped with linear mapping at kseg_c so there's no
- * need to map it with a page table. However, head.S also temporarily mapped it
- * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various
- * other paging stuff.
- */
-void __init cris_mmu_init(void)
-{
- unsigned long mmu_config;
- unsigned long mmu_kbase_hi;
- unsigned long mmu_kbase_lo;
- unsigned short mmu_page_id;
-
- /*
- * Make sure the current pgd table points to something sane, even if it
- * is most probably not used until the next switch_mm.
- */
- per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
-
- /* Initialise the TLB. Function found in tlb.c. */
- tlb_init();
-
- /*
- * Enable exceptions and initialize the kernel segments.
- * See head.S for differences between ARTPEC-3 and ETRAX FS.
- */
- mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) |
- REG_STATE(mmu, rw_mm_cfg, acc, on) |
- REG_STATE(mmu, rw_mm_cfg, ex, on) |
- REG_STATE(mmu, rw_mm_cfg, inv, on) |
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- REG_STATE(mmu, rw_mm_cfg, seg_f, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_e, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_d, linear) |
-#else
- REG_STATE(mmu, rw_mm_cfg, seg_f, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_e, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_d, page) |
-#endif
- REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_a, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_9, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_8, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_7, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_6, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_5, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_4, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_3, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_2, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_1, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_0, page));
-
- /* See head.S for differences between ARTPEC-3 and ETRAX FS. */
- mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) |
-#else
- REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
-#endif
- REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0));
-
- mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0));
-
- mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0);
-
- /* Update the instruction MMU. */
- SUPP_BANK_SEL(BANK_IM);
- SUPP_REG_WR(RW_MM_CFG, mmu_config);
- SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
- SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
- SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
-
- /* Update the data MMU. */
- SUPP_BANK_SEL(BANK_DM);
- SUPP_REG_WR(RW_MM_CFG, mmu_config);
- SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
- SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
- SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
-
- SPEC_REG_WR(SPEC_REG_PID, 0);
-
- /*
- * The MMU has been enabled ever since head.S but just to make it
- * totally obvious enable it here as well.
- */
- SUPP_BANK_SEL(BANK_GC);
- SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */
-}
-
-void __init paging_init(void)
-{
- int i;
- unsigned long zones_size[MAX_NR_ZONES];
-
- printk("Setting up paging and the MMU.\n");
-
- /* Clear out the init_mm.pgd that will contain the kernel's mappings. */
- for(i = 0; i < PTRS_PER_PGD; i++)
- swapper_pg_dir[i] = __pgd(0);
-
- cris_mmu_init();
-
- /*
- * Initialize the bad page table and bad page to point to a couple of
- * allocated pages.
- */
- empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
- memset((void *) empty_zero_page, 0, PAGE_SIZE);
-
- /* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */
- zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
- for (i = 1; i < MAX_NR_ZONES; i++)
- zones_size[i] = 0;
-
- /*
- * Use free_area_init_node instead of free_area_init, because it is
- * designed for systems where the DRAM starts at an address
- * substantially higher than 0, like us (we start at PAGE_OFFSET). This
- * saves space in the mem_map page array.
- */
- free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
-
- mem_map = contig_page_data.node_mem_map;
-}
diff --git a/arch/cris/arch-v32/mm/intmem.c b/arch/cris/arch-v32/mm/intmem.c
deleted file mode 100644
index 928b94d1d320..000000000000
--- a/arch/cris/arch-v32/mm/intmem.c
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simple allocator for internal RAM in ETRAX FS
- *
- * Copyright (c) 2004 Axis Communications AB.
- */
-
-#include <linux/list.h>
-#include <linux/slab.h>
-#include <asm/io.h>
-#include <memmap.h>
-
-#define STATUS_FREE 0
-#define STATUS_ALLOCATED 1
-
-#ifdef CONFIG_ETRAX_L2CACHE
-#define RESERVED_SIZE 66*1024
-#else
-#define RESERVED_SIZE 0
-#endif
-
-struct intmem_allocation {
- struct list_head entry;
- unsigned int size;
- unsigned offset;
- char status;
-};
-
-
-static struct list_head intmem_allocations;
-static void* intmem_virtual;
-
-static void crisv32_intmem_init(void)
-{
- static int initiated = 0;
- if (!initiated) {
- struct intmem_allocation* alloc;
- alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
- INIT_LIST_HEAD(&intmem_allocations);
- intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE,
- MEM_INTMEM_SIZE - RESERVED_SIZE);
- initiated = 1;
- alloc->size = MEM_INTMEM_SIZE - RESERVED_SIZE;
- alloc->offset = 0;
- alloc->status = STATUS_FREE;
- list_add_tail(&alloc->entry, &intmem_allocations);
- }
-}
-
-void* crisv32_intmem_alloc(unsigned size, unsigned align)
-{
- struct intmem_allocation* allocation;
- struct intmem_allocation* tmp;
- void* ret = NULL;
-
- preempt_disable();
- crisv32_intmem_init();
-
- list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
- int alignment = allocation->offset % align;
- alignment = alignment ? align - alignment : alignment;
-
- if (allocation->status == STATUS_FREE &&
- allocation->size >= size + alignment) {
- if (allocation->size > size + alignment) {
- struct intmem_allocation* alloc;
- alloc = kmalloc(sizeof *alloc, GFP_ATOMIC);
- alloc->status = STATUS_FREE;
- alloc->size = allocation->size - size -
- alignment;
- alloc->offset = allocation->offset + size +
- alignment;
- list_add(&alloc->entry, &allocation->entry);
-
- if (alignment) {
- struct intmem_allocation *tmp;
- tmp = kmalloc(sizeof *tmp, GFP_ATOMIC);
- tmp->offset = allocation->offset;
- tmp->size = alignment;
- tmp->status = STATUS_FREE;
- allocation->offset += alignment;
- list_add_tail(&tmp->entry,
- &allocation->entry);
- }
- }
- allocation->status = STATUS_ALLOCATED;
- allocation->size = size;
- ret = (void*)((int)intmem_virtual + allocation->offset);
- }
- }
- preempt_enable();
- return ret;
-}
-
-void crisv32_intmem_free(void* addr)
-{
- struct intmem_allocation* allocation;
- struct intmem_allocation* tmp;
-
- if (addr == NULL)
- return;
-
- preempt_disable();
- crisv32_intmem_init();
-
- list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
- if (allocation->offset == (int)(addr - intmem_virtual)) {
- struct intmem_allocation *prev =
- list_entry(allocation->entry.prev,
- struct intmem_allocation, entry);
- struct intmem_allocation *next =
- list_entry(allocation->entry.next,
- struct intmem_allocation, entry);
-
- allocation->status = STATUS_FREE;
- /* Join with prev and/or next if also free */
- if ((&prev->entry != &intmem_allocations) &&
- (prev->status == STATUS_FREE)) {
- prev->size += allocation->size;
- list_del(&allocation->entry);
- kfree(allocation);
- allocation = prev;
- }
- if ((&next->entry != &intmem_allocations) &&
- (next->status == STATUS_FREE)) {
- allocation->size += next->size;
- list_del(&next->entry);
- kfree(next);
- }
- preempt_enable();
- return;
- }
- }
- preempt_enable();
-}
-
-void* crisv32_intmem_phys_to_virt(unsigned long addr)
-{
- return (void *)(addr - (MEM_INTMEM_START + RESERVED_SIZE) +
- (unsigned long)intmem_virtual);
-}
-
-unsigned long crisv32_intmem_virt_to_phys(void* addr)
-{
- return (unsigned long)((unsigned long )addr -
- (unsigned long)intmem_virtual + MEM_INTMEM_START +
- RESERVED_SIZE);
-}
-
-static int __init crisv32_intmem_setup(void)
-{
- crisv32_intmem_init();
-
- return 0;
-}
-device_initcall(crisv32_intmem_setup);
-
diff --git a/arch/cris/arch-v32/mm/l2cache.c b/arch/cris/arch-v32/mm/l2cache.c
deleted file mode 100644
index 4fef321d5606..000000000000
--- a/arch/cris/arch-v32/mm/l2cache.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <memmap.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/l2cache_defs.h>
-#include <asm/io.h>
-
-#define L2CACHE_SIZE 64
-
-int __init l2cache_init(void)
-{
- reg_l2cache_rw_ctrl ctrl = {0};
- reg_l2cache_rw_cfg cfg = {.en = regk_l2cache_yes};
-
- ctrl.csize = L2CACHE_SIZE;
- ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0);
- REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl);
-
- /* Flush the tag memory */
- memset((void *)(MEM_INTMEM_START | MEM_NON_CACHEABLE), 0, 2*1024);
-
- /* Enable the cache */
- REG_WR(l2cache, regi_l2cache, rw_cfg, cfg);
-
- return 0;
-}
-
diff --git a/arch/cris/arch-v32/mm/mmu.S b/arch/cris/arch-v32/mm/mmu.S
deleted file mode 100644
index f24965703f6d..000000000000
--- a/arch/cris/arch-v32/mm/mmu.S
+++ /dev/null
@@ -1,211 +0,0 @@
-; SPDX-License-Identifier: GPL-2.0
-; WARNING : The refill handler has been modified, see below !!!
-
-/*
- * Copyright (C) 2003 Axis Communications AB
- *
- * Authors: Mikael Starvik (starvik@axis.com)
- *
- * Code for the fault low-level handling routines.
- *
- */
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-; Save all register. Must save in same order as struct pt_regs.
-.macro SAVE_ALL
- subq 12, $sp
- move $erp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- subq 14*4, $sp
- movem $r13, [$sp]
- subq 4, $sp
- move.d $r10, [$sp]
-.endm
-
-; Bus fault handler. Extracts relevant information and calls mm subsystem
-; to handle the fault.
-.macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex
- .globl \handler
- .type \handler,"function"
-\handler:
- SAVE_ALL
- move \mmu, $srs ; Select MMU support register bank
- move.d $sp, $r11 ; regs
- moveq 1, $r12 ; protection fault
- moveq \we, $r13 ; write exception?
- orq \ex << 1, $r13 ; execute?
- move $s3, $r10 ; rw_mm_cause
- and.d ~8191, $r10 ; Get faulting page start address
-
- jsr do_page_fault
- nop
- ba ret_from_intr
- nop
- .size \handler, . - \handler
-.endm
-
-; Refill handler. Three cases may occur:
-; 1. PMD and PTE exists in mm subsystem but not in TLB
-; 2. PMD exists but not PTE
-; 3. PMD doesn't exist
-; The code below handles case 1 and calls the mm subsystem for case 2 and 3.
-; Do not touch this code without very good reasons and extensive testing.
-; Note that the code is optimized to minimize stalls (makes the code harder
-; to read).
-;
-; WARNING !!!
-; Modified by Mikael Asker 060725: added a workaround for strange TLB
-; behavior. If the same PTE is present in more than one set, the TLB
-; doesn't recognize it and we get stuck in a loop of refill exceptions.
-; The workaround detects such loops and exits them by flushing
-; the TLB contents. The problem and workaround were verified
-; in VCS by Mikael Starvik.
-;
-; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each
-; PMD holds 16 MB of virtual memory.
-; Bits 0-12 : Offset within a page
-; Bits 13-23 : PTE offset within a PMD
-; Bits 24-31 : PMD offset within the PGD
-
-.macro MMU_REFILL_HANDLER handler, mmu
- .data
-1: .dword 0 ; refill_count
- ; == 0 <=> last_refill_cause is invalid
-2: .dword 0 ; last_refill_cause
- .text
- .globl \handler
- .type \handler, "function"
-\handler:
- subq 4, $sp
-; (The pipeline stalls for one cycle; $sp used as address in the next cycle.)
- move $srs, [$sp]
- subq 4, $sp
- move \mmu, $srs ; Select MMU support register bank
- move.d $acr, [$sp]
- subq 12, $sp
- move.d 1b, $acr ; Point to refill_count
- movem $r2, [$sp]
-
- test.d [$acr] ; refill_count == 0 ?
- beq 5f ; yes, last_refill_cause is invalid
- move.d $acr, $r1
-
- ; last_refill_cause is valid, investigate cause
- addq 4, $r1 ; Point to last_refill_cause
- move $s3, $r0 ; Get rw_mm_cause
- move.d [$r1], $r2 ; Get last_refill_cause
- cmp.d $r0, $r2 ; rw_mm_cause == last_refill_cause ?
- beq 6f ; yes, increment count
- moveq 1, $r2
-
- ; rw_mm_cause != last_refill_cause
- move.d $r2, [$acr] ; refill_count = 1
- move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
-
-3: ; Probably not in a loop, continue normal processing
- move.d current_pgd, $acr ; PGD
- ; Look up PMD in PGD
- lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
- move.d [$acr], $acr ; PGD for the current process
- addi $r0.d, $acr, $acr
- move $s3, $r0 ; rw_mm_cause
- move.d [$acr], $acr ; Get PMD
- beq 8f
- ; Look up PTE in PMD
- lsrq PAGE_SHIFT, $r0
- and.w PAGE_MASK, $acr ; Remove PMD flags
- and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23)
- addi $r0.d, $acr, $acr
- move.d [$acr], $acr ; Get PTE
- beq 9f
- movem [$sp], $r2 ; Restore r0-r2 in delay slot
- addq 12, $sp
- ; Store in TLB
- move $acr, $s5
-4: ; Return
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- rete
- rfe
-
-5: ; last_refill_cause is invalid
- moveq 1, $r2
- addq 4, $r1 ; Point to last_refill_cause
- move.d $r2, [$acr] ; refill_count = 1
- move $s3, $r0 ; Get rw_mm_cause
- ba 3b ; Continue normal processing
- move.d $r0,[$r1] ; last_refill_cause = rw_mm_cause
-
-6: ; rw_mm_cause == last_refill_cause
- move.d [$acr], $r2 ; Get refill_count
- cmpq 4, $r2 ; refill_count > 4 ?
- bhi 7f ; yes
- addq 1, $r2 ; refill_count++
- ba 3b ; Continue normal processing
- move.d $r2, [$acr]
-
-7: ; refill_count > 4, error
- move.d $acr, $r0 ; Save pointer to refill_count
- clear.d [$r0] ; refill_count = 0
-
- ;; rewind the short stack
- movem [$sp], $r2 ; Restore r0-r2
- addq 12, $sp
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- ;; Keep it simple (slow), save all the regs.
- SAVE_ALL
- jsr __flush_tlb_all
- nop
- ba ret_from_intr ; Return
- nop
-
-8: ; PMD missing, let the mm subsystem fix it up.
- movem [$sp], $r2 ; Restore r0-r2
-9: ; PTE missing, let the mm subsystem fix it up.
- addq 12, $sp
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- SAVE_ALL
- move \mmu, $srs
- move.d $sp, $r11 ; regs
- clear.d $r12 ; Not a protection fault
- move.w PAGE_MASK, $acr
- move $s3, $r10 ; rw_mm_cause
- btstq 9, $r10 ; Check if write access
- smi $r13
- and.w PAGE_MASK, $r10 ; Get VPN (virtual address)
- jsr do_page_fault
- and.w $acr, $r10
- ; Return
- ba ret_from_intr
- nop
- .size \handler, . - \handler
-.endm
-
- ; This is the MMU bus fault handlers.
-
-MMU_REFILL_HANDLER i_mmu_refill, 1
-MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0
-MMU_BUS_FAULT_HANDLER i_mmu_access, 1, 0, 0
-MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1
-MMU_REFILL_HANDLER d_mmu_refill, 2
-MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0
-MMU_BUS_FAULT_HANDLER d_mmu_access, 2, 0, 0
-MMU_BUS_FAULT_HANDLER d_mmu_write, 2, 1, 0
diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c
deleted file mode 100644
index 9e4b5ab4971d..000000000000
--- a/arch/cris/arch-v32/mm/tlb.c
+++ /dev/null
@@ -1,209 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Low level TLB handling.
- *
- * Copyright (C) 2000-2003, Axis Communications AB.
- *
- * Authors: Bjorn Wesen <bjornw@axis.com>
- * Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
- */
-#include <linux/mm_types.h>
-
-#include <asm/tlb.h>
-#include <asm/mmu_context.h>
-#include <arch/hwregs/asm/mmu_defs_asm.h>
-#include <arch/hwregs/supp_reg.h>
-
-#define UPDATE_TLB_SEL_IDX(val) \
-do { \
- unsigned long tlb_sel; \
- \
- tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \
- SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \
-} while(0)
-
-#define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \
-do { \
- SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \
- SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \
-} while(0)
-
-/*
- * The TLB can host up to 256 different mm contexts at the same time. The running
- * context is found in the PID register. Each TLB entry contains a page_id that
- * has to match the PID register to give a hit. page_id_map keeps track of which
- * mm's is assigned to which page_id's, making sure it's known when to
- * invalidate TLB entries.
- *
- * The last page_id is never running, it is used as an invalid page_id so that
- * it's possible to make TLB entries that will nerver match.
- *
- * Note; the flushes needs to be atomic otherwise an interrupt hander that uses
- * vmalloc'ed memory might cause a TLB load in the middle of a flush.
- */
-
-/* Flush all TLB entries. */
-void
-__flush_tlb_all(void)
-{
- int i;
- int mmu;
- unsigned long flags;
- unsigned long mmu_tlb_hi;
- unsigned long mmu_tlb_sel;
-
- /*
- * Mask with 0xf so similar TLB entries aren't written in the same 4-way
- * entry group.
- */
- local_irq_save(flags);
-
- for (mmu = 1; mmu <= 2; mmu++) {
- SUPP_BANK_SEL(mmu); /* Select the MMU */
- for (i = 0; i < NUM_TLB_ENTRIES; i++) {
- /* Store invalid entry */
- mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i);
-
- mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID)
- | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf));
-
- SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel);
- SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi);
- SUPP_REG_WR(RW_MM_TLB_LO, 0);
- }
- }
-
- local_irq_restore(flags);
-}
-
-/* Flush an entire user address space. */
-void
-__flush_tlb_mm(struct mm_struct *mm)
-{
- int i;
- int mmu;
- unsigned long flags;
- unsigned long page_id;
- unsigned long tlb_hi;
- unsigned long mmu_tlb_hi;
-
- page_id = mm->context.page_id;
-
- if (page_id == NO_CONTEXT)
- return;
-
- /* Mark the TLB entries that match the page_id as invalid. */
- local_irq_save(flags);
-
- for (mmu = 1; mmu <= 2; mmu++) {
- SUPP_BANK_SEL(mmu);
- for (i = 0; i < NUM_TLB_ENTRIES; i++) {
- UPDATE_TLB_SEL_IDX(i);
-
- /* Get the page_id */
- SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
-
- /* Check if the page_id match. */
- if ((tlb_hi & 0xff) == page_id) {
- mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid,
- INVALID_PAGEID)
- | REG_FIELD(mmu, rw_mm_tlb_hi, vpn,
- i & 0xf));
-
- UPDATE_TLB_HILO(mmu_tlb_hi, 0);
- }
- }
- }
-
- local_irq_restore(flags);
-}
-
-/* Invalidate a single page. */
-void
-__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
- int i;
- int mmu;
- unsigned long page_id;
- unsigned long flags;
- unsigned long tlb_hi;
- unsigned long mmu_tlb_hi;
-
- page_id = vma->vm_mm->context.page_id;
-
- if (page_id == NO_CONTEXT)
- return;
-
- addr &= PAGE_MASK;
-
- /*
- * Invalidate those TLB entries that match both the mm context and the
- * requested virtual address.
- */
- local_irq_save(flags);
-
- for (mmu = 1; mmu <= 2; mmu++) {
- SUPP_BANK_SEL(mmu);
- for (i = 0; i < NUM_TLB_ENTRIES; i++) {
- UPDATE_TLB_SEL_IDX(i);
- SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
-
- /* Check if page_id and address matches */
- if (((tlb_hi & 0xff) == page_id) &&
- ((tlb_hi & PAGE_MASK) == addr)) {
- mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid,
- INVALID_PAGEID) | addr;
-
- UPDATE_TLB_HILO(mmu_tlb_hi, 0);
- }
- }
- }
-
- local_irq_restore(flags);
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-
-int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- mm->context.page_id = NO_CONTEXT;
- return 0;
-}
-
-static DEFINE_SPINLOCK(mmu_context_lock);
-
-/* Called in schedule() just before actually doing the switch_to. */
-void
-switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (prev != next) {
- int cpu = smp_processor_id();
-
- /* Make sure there is a MMU context. */
- spin_lock(&mmu_context_lock);
- get_mmu_context(next);
- cpumask_set_cpu(cpu, mm_cpumask(next));
- spin_unlock(&mmu_context_lock);
-
- /*
- * Remember the pgd for the fault handlers. Keep a separate
- * copy of it because current and active_mm might be invalid
- * at points where * there's still a need to derefer the pgd.
- */
- per_cpu(current_pgd, cpu) = next->pgd;
-
- /* Switch context in the MMU. */
- if (tsk && task_thread_info(tsk)) {
- SPEC_REG_WR(SPEC_REG_PID, next->context.page_id |
- task_thread_info(tsk)->tls);
- } else {
- SPEC_REG_WR(SPEC_REG_PID, next->context.page_id);
- }
- }
-}
-
diff --git a/arch/cris/arch-v32/output_arch.ld b/arch/cris/arch-v32/output_arch.ld
deleted file mode 100644
index d60a57db0ec2..000000000000
--- a/arch/cris/arch-v32/output_arch.ld
+++ /dev/null
@@ -1,2 +0,0 @@
-/* At the time of this writing, there's no equivalent ld option. */
-OUTPUT_ARCH (crisv32)
diff --git a/arch/cris/boot/.gitignore b/arch/cris/boot/.gitignore
deleted file mode 100644
index 171a0853caf8..000000000000
--- a/arch/cris/boot/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Image
-zImage
diff --git a/arch/cris/boot/Makefile b/arch/cris/boot/Makefile
deleted file mode 100644
index 859d275f862b..000000000000
--- a/arch/cris/boot/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/cris/boot/Makefile
-#
-
-objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment
-objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id
-
-OBJCOPYFLAGS = -O binary $(objcopyflags-y)
-
-
-subdir- := compressed rescue
-targets := Image
-
-$(obj)/Image: vmlinux FORCE
- $(call if_changed,objcopy)
- @echo ' Kernel: $@ is ready'
-
-$(obj)/compressed/vmlinux: $(obj)/Image FORCE
- $(Q)$(MAKE) $(build)=$(obj)/compressed $@
- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin
-
-$(obj)/zImage: $(obj)/compressed/vmlinux
- @cp $< $@
- @echo ' Kernel: $@ is ready'
diff --git a/arch/cris/boot/compressed/Makefile b/arch/cris/boot/compressed/Makefile
deleted file mode 100644
index e149c3467c93..000000000000
--- a/arch/cris/boot/compressed/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/cris/boot/compressed/Makefile
-#
-
-# asflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/mach \
-# -I$(srctree)/include/asm/arch
-# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -O2 -I$(srctree)/include/asm/mach
-# -I$(srctree)/include/asm/arch
-
-arch-$(CONFIG_ETRAX_ARCH_V10) = v10
-arch-$(CONFIG_ETRAX_ARCH_V32) = v32
-
-ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds
-
-OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o
-OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o
-OBJECTS= $(OBJECTS-y) $(obj)/misc.o
-OBJCOPYFLAGS = -O binary --remove-section=.bss
-
-quiet_cmd_image = BUILD $@
-cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@
-
-targets := vmlinux piggy.gz decompress.o decompress.bin
-
-$(obj)/decompress.o: $(OBJECTS) FORCE
- $(call if_changed,ld)
-
-$(obj)/decompress.bin: $(obj)/decompress.o FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE
- $(call if_changed,image)
-
-$(obj)/piggy.gz: $(obj)/../Image FORCE
- $(call if_changed,gzip)
diff --git a/arch/cris/boot/compressed/README b/arch/cris/boot/compressed/README
deleted file mode 100644
index 182c5d75784b..000000000000
--- a/arch/cris/boot/compressed/README
+++ /dev/null
@@ -1,24 +0,0 @@
-Creation of the self-extracting compressed kernel image (vmlinuz)
------------------------------------------------------------------
-
-This can be slightly confusing because it's a process with many steps.
-
-The kernel object built by the arch/etrax100/Makefile, vmlinux, is split
-by that makefile into text and data binary files, vmlinux.text and
-vmlinux.data.
-
-Those files together with a ROM filesystem can be catted together and
-burned into a flash or executed directly at the DRAM origin.
-
-They can also be catted together and compressed with gzip, which is what
-happens in this makefile. Together they make up piggy.img.
-
-The decompressor is built into the file decompress.o. It is turned into
-the binary file decompress.bin, which is catted together with piggy.img
-into the file vmlinuz. It can be executed in an arbitrary place in flash.
-
-Be careful - it assumes some things about free locations in DRAM. It
-assumes the DRAM starts at 0x40000000 and that it is at least 8 MB,
-so it puts its code at 0x40700000, and initial stack at 0x40800000.
-
--Bjorn
diff --git a/arch/cris/boot/compressed/decompress_v10.lds b/arch/cris/boot/compressed/decompress_v10.lds
deleted file mode 100644
index d8326779dda2..000000000000
--- a/arch/cris/boot/compressed/decompress_v10.lds
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* OUTPUT_FORMAT(elf32-us-cris) */
-OUTPUT_FORMAT(elf32-cris)
-
-MEMORY
- {
- dram : ORIGIN = 0x40700000,
- LENGTH = 0x00100000
- }
-
-SECTIONS
-{
- .text :
- {
- _stext = . ;
- *(.text)
- *(.rodata)
- *(.rodata.*)
- _etext = . ;
- } > dram
- .data :
- {
- *(.data)
- _edata = . ;
- } > dram
- .bss :
- {
- *(.bss)
- _end = ALIGN( 0x10 ) ;
- } > dram
-}
diff --git a/arch/cris/boot/compressed/decompress_v32.lds b/arch/cris/boot/compressed/decompress_v32.lds
deleted file mode 100644
index 91d311c243ed..000000000000
--- a/arch/cris/boot/compressed/decompress_v32.lds
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*#OUTPUT_FORMAT(elf32-us-cris) */
-OUTPUT_ARCH (crisv32)
-
-MEMORY
- {
- dram : ORIGIN = 0x40700000,
- LENGTH = 0x00100000
- }
-
-SECTIONS
-{
- .text :
- {
- _stext = . ;
- *(.text)
- *(.rodata)
- *(.rodata.*)
- _etext = . ;
- } > dram
- .data :
- {
- *(.data)
- _edata = . ;
- } > dram
- .bss :
- {
- *(.bss)
- _end = ALIGN( 0x10 ) ;
- } > dram
-}
diff --git a/arch/cris/boot/compressed/head_v10.S b/arch/cris/boot/compressed/head_v10.S
deleted file mode 100644
index 08198d8cd37f..000000000000
--- a/arch/cris/boot/compressed/head_v10.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/cris/boot/compressed/head.S
- *
- * Copyright (C) 1999, 2001 Axis Communications AB
- *
- * Code that sets up the DRAM registers, calls the
- * decompressor to unpack the piggybacked kernel, and jumps.
- *
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-
- ;; Exported symbols
-
- .globl input_data
-
-
- .text
-
- nop
- di
-
-;; We need to initialze DRAM registers before we start using the DRAM
-
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq dram_init_finished
- nop
-
-#include "../../arch-v10/lib/dram_init.S"
-
-dram_init_finished:
-
- ;; Initiate the PA and PB ports
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
- move.b $r0, [R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
- move.b $r0, [R_PORT_PA_DIR]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
- move.b $r0, [R_PORT_PB_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
- move.b $r0, [R_PORT_PB_DIR]
-
- ;; Setup the stack to a suitably high address.
- ;; We assume 8 MB is the minimum DRAM in an eLinux
- ;; product and put the sp at the top for now.
-
- move.d 0x40800000, $sp
-
- ;; Figure out where the compressed piggyback image is
- ;; in the flash (since we wont try to copy it to DRAM
- ;; before unpacking). It is at _edata, but in flash.
- ;; Use (_edata - basse) as offset to the current PC.
-
-basse: move.d $pc, $r5
- and.d 0x7fffffff, $r5 ; strip any non-cache bit
- subq 2, $r5 ; compensate for the move.d $pc instr
- move.d $r5, $r0 ; save for later - flash address of 'basse'
- add.d _edata, $r5
- sub.d basse, $r5 ; $r5 = flash address of '_edata'
-
- ;; Copy text+data to DRAM
-
- move.d basse, $r1 ; destination
- move.d _edata, $r2 ; end destination
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
- bcs 1b
- nop
-
- move.d $r5, [input_data] ; for the decompressor
-
-
- ;; Clear the decompressors BSS (between _edata and _end)
-
- moveq 0, $r0
- move.d _edata, $r1
- move.d _end, $r2
-1: move.w $r0, [$r1+]
- cmp.d $r2, $r1
- bcs 1b
- nop
-
- ;; Save command line magic and address.
- move.d _cmd_line_magic, $r12
- move.d $r10, [$r12]
- move.d _cmd_line_addr, $r12
- move.d $r11, [$r12]
-
- ;; Do the decompression and save compressed size in inptr
-
- jsr decompress_kernel
-
- ;; Put start address of root partition in $r9 so the kernel can use it
- ;; when mounting from flash
-
- move.d [input_data], $r9 ; flash address of compressed kernel
- add.d [inptr], $r9 ; size of compressed kernel
-
- ;; Restore command line magic and address.
- move.d _cmd_line_magic, $r10
- move.d [$r10], $r10
- move.d _cmd_line_addr, $r11
- move.d [$r11], $r11
-
- ;; Enter the decompressed kernel
- move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized
- jump 0x40004000 ; kernel is linked to this address
-
- .data
-
-input_data:
- .dword 0 ; used by the decompressor
-_cmd_line_magic:
- .dword 0
-_cmd_line_addr:
- .dword 0
-#include "../../arch-v10/lib/hw_settings.S"
diff --git a/arch/cris/boot/compressed/head_v32.S b/arch/cris/boot/compressed/head_v32.S
deleted file mode 100644
index a997947d31e3..000000000000
--- a/arch/cris/boot/compressed/head_v32.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Code that sets up the DRAM registers, calls the
- * decompressor to unpack the piggybacked kernel, and jumps.
- *
- * Copyright (C) 1999 - 2006, Axis Communications AB
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <hwregs/asm/reg_map_asm.h>
-#include <mach/startup.inc>
-
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-
- ;; Exported symbols
-
- .globl input_data
-
- .text
-start:
- di
-
- ;; Start clocks for used blocks.
- START_CLOCKS
-
- ;; Initialize the DRAM registers.
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq dram_init_finished
- nop
-
-#if defined CONFIG_ETRAXFS
-#include "../../arch-v32/mach-fs/dram_init.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../../arch-v32/mach-a3/dram_init.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
-
-dram_init_finished:
-
- GIO_INIT
- ;; Setup the stack to a suitably high address.
- ;; We assume 8 MB is the minimum DRAM and put
- ;; the SP at the top for now.
-
- move.d 0x40800000, $sp
-
- ;; Figure out where the compressed piggyback image is.
- ;; It is either in [NOR] flash (we don't want to copy it
- ;; to DRAM before unpacking), or copied to DRAM
- ;; by the [NAND] flash boot loader.
- ;; The piggyback image is at _edata, but relative to where the
- ;; image is actually located in memory, not where it is linked
- ;; (the decompressor is linked at 0x40700000+ and runs there).
- ;; Use (_edata - herami) as offset to the current PC.
-
-hereami:
- lapcq ., $r5 ; get PC
- and.d 0x7fffffff, $r5 ; strip any non-cache bit
- move.d $r5, $r0 ; source address of 'herami'
- add.d _edata, $r5
- sub.d hereami, $r5 ; r5 = flash address of '_edata'
- move.d hereami, $r1 ; destination
-
- ;; Copy text+data to DRAM
-
- move.d _edata, $r2 ; end destination
-1: move.w [$r0+], $r3 ; from herami+ source
- move.w $r3, [$r1+] ; to hereami+ destination (linked address)
- cmp.d $r2, $r1 ; finish when destination == _edata
- bcs 1b
- nop
- move.d input_data, $r0 ; for the decompressor
- move.d $r5, [$r0] ; for the decompressor
-
- ;; Clear the decompressors BSS (between _edata and _end)
-
- moveq 0, $r0
- move.d _edata, $r1
- move.d _end, $r2
-1: move.w $r0, [$r1+]
- cmp.d $r2, $r1
- bcs 1b
- nop
-
- ;; Save command line magic and address.
- move.d _cmd_line_magic, $r0
- move.d $r10, [$r0]
- move.d _cmd_line_addr, $r0
- move.d $r11, [$r0]
-
- ;; Save boot source indicator
- move.d _boot_source, $r0
- move.d $r12, [$r0]
-
- ;; Do the decompression and save compressed size in _inptr
-
- jsr decompress_kernel
- nop
-
- ;; Restore boot source indicator
- move.d _boot_source, $r12
- move.d [$r12], $r12
-
- ;; Restore command line magic and address.
- move.d _cmd_line_magic, $r10
- move.d [$r10], $r10
- move.d _cmd_line_addr, $r11
- move.d [$r11], $r11
-
- ;; Put start address of root partition in r9 so the kernel can use it
- ;; when mounting from flash
- move.d input_data, $r0
- move.d [$r0], $r9 ; flash address of compressed kernel
- move.d inptr, $r0
- add.d [$r0], $r9 ; size of compressed kernel
- cmp.d 0x40000000, $r9 ; image in DRAM ?
- blo enter_kernel ; no, must be [NOR] flash, jump
- nop ; delay slot
- and.d 0x001fffff, $r9 ; assume compressed kernel was < 2M
-
-enter_kernel:
- ;; Enter the decompressed kernel
- move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized
- jump 0x40004000 ; kernel is linked to this address
- nop
-
- .data
-
-input_data:
- .dword 0 ; used by the decompressor
-_cmd_line_magic:
- .dword 0
-_cmd_line_addr:
- .dword 0
-_boot_source:
- .dword 0
-
-#if defined CONFIG_ETRAXFS
-#include "../../arch-v32/mach-fs/hw_settings.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../../arch-v32/mach-a3/hw_settings.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
diff --git a/arch/cris/boot/compressed/misc.c b/arch/cris/boot/compressed/misc.c
deleted file mode 100644
index 1ad464a117b8..000000000000
--- a/arch/cris/boot/compressed/misc.c
+++ /dev/null
@@ -1,377 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * misc.c
- *
- * This is a collection of several routines from gzip-1.0.3
- * adapted for Linux.
- *
- * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
- * puts by Nick Holloway 1993, better puts by Martin Mares 1995
- * adaptation for Linux/CRIS Axis Communications AB, 1999
- *
- */
-
-/* where the piggybacked kernel image expects itself to live.
- * it is the same address we use when we network load an uncompressed
- * image into DRAM, and it is the address the kernel is linked to live
- * at by vmlinux.lds.S
- */
-
-#define KERNEL_LOAD_ADR 0x40004000
-
-#include <linux/types.h>
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/ser_defs.h>
-#include <hwregs/pinmux_defs.h>
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#include <hwregs/clkgen_defs.h>
-#endif
-#else
-#include <arch/svinto.h>
-#endif
-
-/*
- * gzip declarations
- */
-
-#define OF(args) args
-#define STATIC static
-
-void *memset(void *s, int c, size_t n);
-void *memcpy(void *__dest, __const void *__src, size_t __n);
-
-#define memzero(s, n) memset((s), 0, (n))
-
-typedef unsigned char uch;
-typedef unsigned short ush;
-typedef unsigned long ulg;
-
-#define WSIZE 0x8000 /* Window size must be at least 32k, */
- /* and a power of two */
-
-static uch *inbuf; /* input buffer */
-static uch window[WSIZE]; /* Sliding window buffer */
-
-unsigned inptr = 0; /* index of next byte to be processed in inbuf
- * After decompression it will contain the
- * compressed size, and head.S will read it.
- */
-
-static unsigned outcnt = 0; /* bytes in output buffer */
-
-/* gzip flag byte */
-#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
-#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
-#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
-#define COMMENT 0x10 /* bit 4 set: file comment present */
-#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
-#define RESERVED 0xC0 /* bit 6,7: reserved */
-
-#define get_byte() (inbuf[inptr++])
-
-/* Diagnostic functions */
-#ifdef DEBUG
-# define Assert(cond, msg) do { \
- if (!(cond)) \
- error(msg); \
- } while (0)
-# define Trace(x) fprintf x
-# define Tracev(x) do { \
- if (verbose) \
- fprintf x; \
- } while (0)
-# define Tracevv(x) do { \
- if (verbose > 1) \
- fprintf x; \
- } while (0)
-# define Tracec(c, x) do { \
- if (verbose && (c)) \
- fprintf x; \
- } while (0)
-# define Tracecv(c, x) do { \
- if (verbose > 1 && (c)) \
- fprintf x; \
- } while (0)
-#else
-# define Assert(cond, msg)
-# define Trace(x)
-# define Tracev(x)
-# define Tracevv(x)
-# define Tracec(c, x)
-# define Tracecv(c, x)
-#endif
-
-static void flush_window(void);
-static void error(char *m);
-static void aputs(const char *s);
-
-extern char *input_data; /* lives in head.S */
-
-static long bytes_out;
-static uch *output_data;
-static unsigned long output_ptr;
-
-/* the "heap" is put directly after the BSS ends, at end */
-
-extern int _end;
-static long free_mem_ptr = (long)&_end;
-static long free_mem_end_ptr;
-
-#include "../../../../../lib/inflate.c"
-
-/* decompressor info and error messages to serial console */
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-static inline void serout(const char *s, reg_scope_instances regi_ser)
-{
- reg_ser_rs_stat_din rs;
- reg_ser_rw_dout dout = {.data = *s};
-
- do {
- rs = REG_RD(ser, regi_ser, rs_stat_din);
- }
- while (!rs.tr_rdy);/* Wait for transceiver. */
-
- REG_WR(ser, regi_ser, rw_dout, dout);
-}
-#define SEROUT(S, N) \
- do { \
- serout(S, regi_ser ## N); \
- s++; \
- } while (0)
-#else
-#define SEROUT(S, N) do { \
- while (!(*R_SERIAL ## N ## _STATUS & (1 << 5))) \
- ; \
- *R_SERIAL ## N ## _TR_DATA = *s++; \
- } while (0)
-#endif
-
-static void aputs(const char *s)
-{
-#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL
- while (*s) {
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- SEROUT(s, 0);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT1
- SEROUT(s, 1);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT2
- SEROUT(s, 2);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT3
- SEROUT(s, 3);
-#endif
- }
-#endif /* CONFIG_ETRAX_DEBUG_PORT_NULL */
-}
-
-void *memset(void *s, int c, size_t n)
-{
- int i;
- char *ss = (char*)s;
-
- for (i=0;i<n;i++) ss[i] = c;
-
- return s;
-}
-
-void *memcpy(void *__dest, __const void *__src, size_t __n)
-{
- int i;
- char *d = (char *)__dest, *s = (char *)__src;
-
- for (i = 0; i < __n; i++)
- d[i] = s[i];
-
- return __dest;
-}
-
-/* ===========================================================================
- * Write the output window window[0..outcnt-1] and update crc and bytes_out.
- * (Used for the decompressed data only.)
- */
-
-static void flush_window(void)
-{
- ulg c = crc; /* temporary variable */
- unsigned n;
- uch *in, *out, ch;
-
- in = window;
- out = &output_data[output_ptr];
- for (n = 0; n < outcnt; n++) {
- ch = *out = *in;
- out++;
- in++;
- c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
- }
- crc = c;
- bytes_out += (ulg)outcnt;
- output_ptr += (ulg)outcnt;
- outcnt = 0;
-}
-
-static void error(char *x)
-{
- aputs("\n\n");
- aputs(x);
- aputs("\n\n -- System halted\n");
-
- while(1); /* Halt */
-}
-
-void setup_normal_output_buffer(void)
-{
- output_data = (char *)KERNEL_LOAD_ADR;
-}
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-static inline void serial_setup(reg_scope_instances regi_ser)
-{
- reg_ser_rw_xoff xoff;
- reg_ser_rw_tr_ctrl tr_ctrl;
- reg_ser_rw_rec_ctrl rec_ctrl;
- reg_ser_rw_tr_baud_div tr_baud;
- reg_ser_rw_rec_baud_div rec_baud;
-
- /* Turn off XOFF. */
- xoff = REG_RD(ser, regi_ser, rw_xoff);
-
- xoff.chr = 0;
- xoff.automatic = regk_ser_no;
-
- REG_WR(ser, regi_ser, rw_xoff, xoff);
-
- /* Set baudrate and stopbits. */
- tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
- rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl);
- tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div);
- rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div);
-
- tr_ctrl.stop_bits = 1; /* 2 stop bits. */
- tr_ctrl.en = 1; /* enable transmitter */
- rec_ctrl.en = 1; /* enabler receiver */
-
- /*
- * The baudrate setup used to be a bit fishy, but now transmitter and
- * receiver are both set to the intended baud rate, 115200.
- * The magic value is 29.493 MHz.
- */
- tr_ctrl.base_freq = regk_ser_f29_493;
- rec_ctrl.base_freq = regk_ser_f29_493;
- tr_baud.div = (29493000 / 8) / 115200;
- rec_baud.div = (29493000 / 8) / 115200;
-
- REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
- REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud);
- REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl);
- REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud);
-}
-#endif
-
-void decompress_kernel(void)
-{
- char revision;
- char compile_rev;
-
-#ifdef CONFIG_ETRAX_ARCH_V32
- /* Need at least a CRISv32 to run. */
- compile_rev = 32;
-#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \
- defined(CONFIG_ETRAX_DEBUG_PORT2) || \
- defined(CONFIG_ETRAX_DEBUG_PORT3)
- reg_pinmux_rw_hwprot hwprot;
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- reg_clkgen_rw_clk_ctrl clk_ctrl;
-
- /* Enable corresponding clock region when serial 1..3 selected */
-
- clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
-#endif
-
- /* pinmux setup for ports 1..3 */
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-#endif
-
-
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- serial_setup(regi_ser0);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT1
- hwprot.ser1 = regk_pinmux_yes;
- serial_setup(regi_ser1);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT2
- hwprot.ser2 = regk_pinmux_yes;
- serial_setup(regi_ser2);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT3
- hwprot.ser3 = regk_pinmux_yes;
- serial_setup(regi_ser3);
-#endif
-#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \
- defined(CONFIG_ETRAX_DEBUG_PORT2) || \
- defined(CONFIG_ETRAX_DEBUG_PORT3)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
-#endif
-
- /* input_data is set in head.S */
- inbuf = input_data;
-#else /* CRISv10 */
- /* Need at least a crisv10 to run. */
- compile_rev = 10;
-
- /* input_data is set in head.S */
- inbuf = input_data;
-
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- *R_SERIAL0_XOFF = 0;
- *R_SERIAL0_BAUD = 0x99;
- *R_SERIAL0_TR_CTRL = 0x40;
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT1
- *R_SERIAL1_XOFF = 0;
- *R_SERIAL1_BAUD = 0x99;
- *R_SERIAL1_TR_CTRL = 0x40;
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT2
- *R_GEN_CONFIG = 0x08;
- *R_SERIAL2_XOFF = 0;
- *R_SERIAL2_BAUD = 0x99;
- *R_SERIAL2_TR_CTRL = 0x40;
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT3
- *R_GEN_CONFIG = 0x100;
- *R_SERIAL3_XOFF = 0;
- *R_SERIAL3_BAUD = 0x99;
- *R_SERIAL3_TR_CTRL = 0x40;
-#endif
-#endif
-
- setup_normal_output_buffer();
-
- makecrc();
-
- __asm__ volatile ("move $vr,%0" : "=rm" (revision));
- if (revision < compile_rev) {
-#ifdef CONFIG_ETRAX_ARCH_V32
- aputs("You need at least ETRAX FS to run Linux 2.6/crisv32\n");
-#else
- aputs("You need an ETRAX 100LX to run linux 2.6/crisv10\n");
-#endif
- while(1);
- }
-
- aputs("Uncompressing Linux...\n");
- gunzip();
- aputs("Done. Now booting the kernel\n");
-}
diff --git a/arch/cris/boot/dts/Makefile b/arch/cris/boot/dts/Makefile
deleted file mode 100644
index 118fe990a173..000000000000
--- a/arch/cris/boot/dts/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
-ifneq ($(CONFIG_BUILTIN_DTB),"")
-obj-$(CONFIG_OF) += $(BUILTIN_DTB)
-endif
diff --git a/arch/cris/boot/dts/artpec3.dtsi b/arch/cris/boot/dts/artpec3.dtsi
deleted file mode 100644
index f857300f4edd..000000000000
--- a/arch/cris/boot/dts/artpec3.dtsi
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "axis,crisv32";
- reg = <0>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- model = "artpec3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- intc: interrupt-controller {
- compatible = "axis,crisv32-intc";
- reg = <0xb002a000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- gio: gpio@b0020000 {
- compatible = "axis,artpec3-gio";
- reg = <0xb0020000 0x1000>;
- interrupts = <61>;
- gpio-controller;
- #gpio-cells = <3>;
- };
-
- serial@b003e000 {
- compatible = "axis,etraxfs-uart";
- reg = <0xb003e000 0x1000>;
- interrupts = <64>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/cris/boot/dts/dev88.dts b/arch/cris/boot/dts/dev88.dts
deleted file mode 100644
index 415270ea5309..000000000000
--- a/arch/cris/boot/dts/dev88.dts
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/include/ "etraxfs.dtsi"
-
-/ {
- model = "Axis 88 Developer Board";
- compatible = "axis,dev88";
-
- aliases {
- serial0 = &uart0;
- };
-
- soc {
- uart0: serial@b00260000 {
- status = "okay";
- };
- };
-
- spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&gio 1 0 0xd>;
- gpio-miso = <&gio 4 0 0xd>;
- gpio-mosi = <&gio 0 0 0xd>;
- cs-gpios = <&gio 3 0 0xd>;
- num-chipselects = <1>;
-
- temp-sensor@0 {
- compatible = "ti,lm70";
- reg = <0>;
-
- spi-max-frequency = <100000>;
- };
- };
-
- i2c {
- compatible = "i2c-gpio";
- gpios = <&gio 5 0 0xd>, <&gio 6 0 0xd>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- network {
- label = "network";
- gpios = <&gio 2 GPIO_ACTIVE_LOW 0xa>;
- };
-
- status {
- label = "status";
- gpios = <&gio 3 GPIO_ACTIVE_LOW 0xa>;
- linux,default-trigger = "heartbeat";
- };
- };
-};
diff --git a/arch/cris/boot/dts/etraxfs.dtsi b/arch/cris/boot/dts/etraxfs.dtsi
deleted file mode 100644
index 4513edf72545..000000000000
--- a/arch/cris/boot/dts/etraxfs.dtsi
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "axis,crisv32";
- reg = <0>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- model = "etraxfs";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- intc: interrupt-controller {
- compatible = "axis,crisv32-intc";
- reg = <0xb001c000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- gio: gpio@b001a000 {
- compatible = "axis,etraxfs-gio";
- reg = <0xb001a000 0x1000>;
- interrupts = <50>;
- gpio-controller;
- #gpio-cells = <3>;
- };
-
- serial@b00260000 {
- compatible = "axis,etraxfs-uart";
- reg = <0xb0026000 0x1000>;
- interrupts = <68>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/cris/boot/dts/p1343.dts b/arch/cris/boot/dts/p1343.dts
deleted file mode 100644
index 6030561d4574..000000000000
--- a/arch/cris/boot/dts/p1343.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/include/ "artpec3.dtsi"
-
-/ {
- model = "Axis P1343 Network Camera";
- compatible = "axis,p1343";
-
- aliases {
- serial0 = &uart0;
- };
-
- soc {
- uart0: serial@b003e000 {
- status = "okay";
- };
- };
-
- i2c {
- compatible = "i2c-gpio";
- gpios = <&gio 3 0 0xa>, <&gio 2 0 0xa>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_green {
- label = "status:green";
- gpios = <&gio 0 GPIO_ACTIVE_LOW 0xc>;
- linux,default-trigger = "heartbeat";
- };
-
- status_red {
- label = "status:red";
- gpios = <&gio 1 GPIO_ACTIVE_LOW 0xc>;
- };
-
- network_green {
- label = "network:green";
- gpios = <&gio 2 GPIO_ACTIVE_LOW 0xc>;
- };
-
- network_red {
- label = "network:red";
- gpios = <&gio 3 GPIO_ACTIVE_LOW 0xc>;
- };
-
- power_red {
- label = "power:red";
- gpios = <&gio 4 GPIO_ACTIVE_LOW 0xc>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- activity-button@0 {
- label = "Activity Button";
- linux,code = <KEY_FN>;
- gpios = <&gio 13 GPIO_ACTIVE_LOW 0xd>;
- };
- };
-};
diff --git a/arch/cris/boot/rescue/Makefile b/arch/cris/boot/rescue/Makefile
deleted file mode 100644
index f73ac4c83b96..000000000000
--- a/arch/cris/boot/rescue/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for rescue (bootstrap) code
-#
-
-# CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE)
-# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/arch/mach/ \
-# -I$(srctree)/include/asm/arch
-# asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch
-# LD = gcc-cris -mlinux -march=v32 -nostdlib
-
-ifdef CONFIG_ETRAX_AXISFLASHMAP
-
-arch-$(CONFIG_ETRAX_ARCH_V10) = v10
-arch-$(CONFIG_ETRAX_ARCH_V32) = v32
-
-ldflags-y += -T $(srctree)/$(src)/rescue_$(arch-y).lds
-OBJCOPYFLAGS = -O binary --remove-section=.bss
-obj-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o
-obj-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o
-OBJECTS := $(obj-y)
-
-targets := rescue.o rescue.bin
-
-$(obj)/rescue.o: $(OBJECTS) FORCE
- $(call if_changed,ld)
-
-$(obj)/rescue.bin: $(obj)/rescue.o FORCE
- $(call if_changed,objcopy)
- cp -p $(obj)/rescue.bin $(objtree)
-
-else
-$(obj)/rescue.bin:
-
-endif
-
-$(obj)/testrescue.bin: $(obj)/testrescue.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/testrescue.o tr.bin
-# Pad it to 784 bytes
- dd if=/dev/zero of=tmp2423 bs=1 count=784
- cat tr.bin tmp2423 >testrescue_tmp.bin
- dd if=testrescue_tmp.bin of=$(obj)/testrescue.bin bs=1 count=784
- rm tr.bin tmp2423 testrescue_tmp.bin
-
-
-$(obj)/kimagerescue.bin: $(obj)/kimagerescue.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/kimagerescue.o ktr.bin
-# Pad it to 784 bytes, that's what the rescue loader expects
- dd if=/dev/zero of=tmp2423 bs=1 count=784
- cat ktr.bin tmp2423 >kimagerescue_tmp.bin
- dd if=kimagerescue_tmp.bin of=$(obj)/kimagerescue.bin bs=1 count=784
- rm ktr.bin tmp2423 kimagerescue_tmp.bin
-
diff --git a/arch/cris/boot/rescue/head_v10.S b/arch/cris/boot/rescue/head_v10.S
deleted file mode 100644
index 11eedb1bf31a..000000000000
--- a/arch/cris/boot/rescue/head_v10.S
+++ /dev/null
@@ -1,358 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Rescue code, made to reside at the beginning of the
- * flash-memory. when it starts, it checks a partition
- * table at the first sector after the rescue sector.
- * the partition table was generated by the product builder
- * script and contains offsets, lengths, types and checksums
- * for each partition that this code should check.
- *
- * If any of the checksums fail, we assume the flash is so
- * corrupt that we can't use it to boot into the ftp flash
- * loader, and instead we initialize the serial port to
- * receive a flash-loader and new flash image. we dont include
- * any flash code here, but just accept a certain amount of
- * bytes from the serial port and jump into it. the downloaded
- * code is put in the cache.
- *
- * The partitiontable is designed so that it is transparent to
- * code execution - it has a relative branch opcode in the
- * beginning that jumps over it. each entry contains extra
- * data so we can add stuff later.
- *
- * Partition table format:
- *
- * Code transparency:
- *
- * 2 bytes [opcode 'nop']
- * 2 bytes [opcode 'di']
- * 4 bytes [opcode 'ba <offset>', 8-bit or 16-bit version]
- * 2 bytes [opcode 'nop', delay slot]
- *
- * Table validation (at +10):
- *
- * 2 bytes [magic/version word for partitiontable - 0xef, 0xbe]
- * 2 bytes [length of all entries plus the end marker]
- * 4 bytes [checksum for the partitiontable itself]
- *
- * Entries, each with the following format, last has offset -1:
- *
- * 4 bytes [offset in bytes, from start of flash]
- * 4 bytes [length in bytes of partition]
- * 4 bytes [checksum, simple longword sum]
- * 2 bytes [partition type]
- * 2 bytes [flags, only bit 0 used, ro/rw = 1/0]
- * 16 bytes [reserved for future use]
- *
- * End marker
- *
- * 4 bytes [-1]
- *
- * 10 bytes [0, padding]
- *
- * Bit 0 in flags signifies RW or RO. The rescue code only bothers
- * to check the checksum for RO partitions, since the others will
- * change their data without updating the checksums. A 1 in bit 0
- * means RO, 0 means RW. That way, it is possible to set a partition
- * in RO mode initially, and later mark it as RW, since you can always
- * write 0's to the flash.
- *
- * During the wait for serial input, the status LED will flash so the
- * user knows something went wrong.
- *
- * Copyright (C) 1999-2007 Axis Communications AB
- */
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
- ;; The partitiontable is looked for at the first sector after the boot
- ;; sector. Sector size is 65536 bytes in all flashes we use.
-
-#define PTABLE_START CONFIG_ETRAX_PTABLE_SECTOR
-#define PTABLE_MAGIC 0xbeef
-
- ;; The normal Etrax100 on-chip boot ROM does serial boot at 0x380000f0.
- ;; That is not where we put our downloaded serial boot-code.
- ;; The length is enough for downloading code that loads the rest
- ;; of itself (after having setup the DRAM etc).
- ;; It is the same length as the on-chip ROM loads, so the same
- ;; host loader can be used to load a rescued product as well as
- ;; one booted through the Etrax serial boot code.
-
-#define CODE_START 0x40000000
-#define CODE_LENGTH 784
-
-#ifdef CONFIG_ETRAX_RESCUE_SER0
-#define SERXOFF R_SERIAL0_XOFF
-#define SERBAUD R_SERIAL0_BAUD
-#define SERRECC R_SERIAL0_REC_CTRL
-#define SERRDAT R_SERIAL0_REC_DATA
-#define SERSTAT R_SERIAL0_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER1
-#define SERXOFF R_SERIAL1_XOFF
-#define SERBAUD R_SERIAL1_BAUD
-#define SERRECC R_SERIAL1_REC_CTRL
-#define SERRDAT R_SERIAL1_REC_DATA
-#define SERSTAT R_SERIAL1_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER2
-#define SERXOFF R_SERIAL2_XOFF
-#define SERBAUD R_SERIAL2_BAUD
-#define SERRECC R_SERIAL2_REC_CTRL
-#define SERRDAT R_SERIAL2_REC_DATA
-#define SERSTAT R_SERIAL2_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER3
-#define SERXOFF R_SERIAL3_XOFF
-#define SERBAUD R_SERIAL3_BAUD
-#define SERRECC R_SERIAL3_REC_CTRL
-#define SERRDAT R_SERIAL3_REC_DATA
-#define SERSTAT R_SERIAL3_STATUS
-#endif
-
-#define NOP_DI 0xf025050f
-#define RAM_INIT_MAGIC 0x56902387
-
- .text
-
- ;; This is the entry point of the rescue code
- ;; 0x80000000 if loaded in flash (as it should be)
- ;; Since etrax actually starts at address 2 when booting from flash, we
- ;; put a nop (2 bytes) here first so we dont accidentally skip the di
-
- nop
- di
-
- jump in_cache ; enter cached area instead
-in_cache:
-
-
- ;; First put a jump test to give a possibility of upgrading the
- ;; rescue code without erasing/reflashing the sector.
- ;; We put a longword of -1 here and if it is not -1, we jump using
- ;; the value as jump target. Since we can always change 1's to 0's
- ;; without erasing the sector, it is possible to add new
- ;; code after this and altering the jumptarget in an upgrade.
-
-jtcd: move.d [jumptarget], $r0
- cmp.d 0xffffffff, $r0
- beq no_newjump
- nop
-
- jump [$r0]
-
-jumptarget:
- .dword 0xffffffff ; can be overwritten later to insert new code
-
-no_newjump:
-#ifdef CONFIG_ETRAX_ETHERNET
- ;; Start MII clock to make sure it is running when tranceiver is reset
- move.d 0x3, $r0 ; enable = on, phy = mii_clk
- move.d $r0, [R_NETWORK_GEN_CONFIG]
-#endif
-
- ;; We need to setup the bus registers before we start using the DRAM
-#include "../../../arch-v10/lib/dram_init.S"
-
- ;; we now should go through the checksum-table and check the listed
- ;; partitions for errors.
-
- move.d PTABLE_START, $r3
- move.d [$r3], $r0
- cmp.d NOP_DI, $r0 ; make sure the nop/di is there...
- bne do_rescue
- nop
-
- ;; skip the code transparency block (10 bytes).
-
- addq 10, $r3
-
- ;; check for correct magic
-
- move.w [$r3+], $r0
- cmp.w PTABLE_MAGIC, $r0
- bne do_rescue ; didn't recognize - trig rescue
- nop
-
- ;; check for correct ptable checksum
-
- movu.w [$r3+], $r2 ; ptable length
- move.d $r2, $r8 ; save for later, length of total ptable
- addq 28, $r8 ; account for the rest
- move.d [$r3+], $r4 ; ptable checksum
- move.d $r3, $r1
- jsr checksum ; r1 source, r2 length, returns in r0
-
- cmp.d $r0, $r4
- bne do_rescue ; didn't match - trig rescue
- nop
-
- ;; ptable is ok. validate each entry.
-
- moveq -1, $r7
-
-ploop: move.d [$r3+], $r1 ; partition offset (from ptable start)
- bne notfirst ; check if it is the partition containing ptable
- nop ; yes..
- move.d $r8, $r1 ; for its checksum check, skip the ptable
- move.d [$r3+], $r2 ; partition length
- sub.d $r8, $r2 ; minus the ptable length
- ba bosse
- nop
-notfirst:
- cmp.d -1, $r1 ; the end of the ptable ?
- beq flash_ok ; if so, the flash is validated
- move.d [$r3+], $r2 ; partition length
-bosse: move.d [$r3+], $r5 ; checksum
- move.d [$r3+], $r4 ; type and flags
- addq 16, $r3 ; skip the reserved bytes
- btstq 16, $r4 ; check ro flag
- bpl ploop ; rw partition, skip validation
- nop
- btstq 17, $r4 ; check bootable flag
- bpl 1f
- nop
- move.d $r1, $r7 ; remember boot partition offset
-1:
- add.d PTABLE_START, $r1
-
- jsr checksum ; checksum the partition
-
- cmp.d $r0, $r5
- beq ploop ; checksums matched, go to next entry
- nop
-
- ;; otherwise fall through to the rescue code.
-
-do_rescue:
- ;; setup port PA and PB default initial directions and data
- ;; (so we can flash LEDs, and so that DTR and others are set)
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
- move.b $r0, [R_PORT_PA_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
- move.b $r0, [R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
- move.b $r0, [R_PORT_PB_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
- move.b $r0, [R_PORT_PB_DATA]
-
- ;; setup the serial port at 115200 baud
-
- moveq 0, $r0
- move.d $r0, [SERXOFF]
-
- move.b 0x99, $r0
- move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive
-
- move.b 0x40, $r0 ; rec enable
- move.b $r0, [SERRECC]
-
- moveq 0, $r1 ; "timer" to clock out a LED red flash
- move.d CODE_START, $r3 ; destination counter
- movu.w CODE_LENGTH, $r4; length
-
-wait_ser:
- addq 1, $r1
-#ifndef CONFIG_ETRAX_NO_LEDS
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2
-#endif
- move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0
- btstq 16, $r1
- bpl 1f
- nop
- or.d $r0, $r2 ; set bit
- ba 2f
- nop
-1: not $r0 ; clear bit
- and.d $r0, $r2
-2:
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b $r2, [R_PORT_PA_DATA]
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b $r2, [R_PORT_PB_DATA]
-#endif
-#endif
-
- ;; check if we got something on the serial port
-
- move.b [SERSTAT], $r0
- btstq 0, $r0 ; data_avail
- bpl wait_ser
- nop
-
- ;; got something - copy the byte and loop
-
- move.b [SERRDAT], $r0
- move.b $r0, [$r3+]
-
- subq 1, $r4 ; decrease length
- bne wait_ser
- nop
-
- ;; jump into downloaded code
-
- move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is
- ; initialized
- jump CODE_START
-
-flash_ok:
- ;; check r7, which contains either -1 or the partition to boot from
-
- cmp.d -1, $r7
- bne 1f
- nop
- move.d PTABLE_START, $r7; otherwise use the ptable start
-1:
- move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is
- ; initialized
- jump $r7 ; boot!
-
-
- ;; Helper subroutines
-
- ;; Will checksum by simple addition
- ;; r1 - source
- ;; r2 - length in bytes
- ;; result will be in r0
-checksum:
- moveq 0, $r0
- moveq CONFIG_ETRAX_FLASH1_SIZE, $r6
-
- ;; If the first physical flash memory is exceeded wrap to the
- ;; second one
- btstq 26, $r1 ; Are we addressing first flash?
- bpl 1f
- nop
- clear.d $r6
-
-1: test.d $r6 ; 0 = no wrapping
- beq 2f
- nop
- lslq 20, $r6 ; Convert MB to bytes
- sub.d $r1, $r6
-
-2: addu.b [$r1+], $r0
- subq 1, $r6 ; Flash memory left
- beq 3f
- subq 1, $r2 ; Length left
- bne 2b
- nop
- ret
- nop
-
-3: move.d MEM_CSE1_START, $r1 ; wrap to second flash
- ba 2b
- nop
-
-#endif
diff --git a/arch/cris/boot/rescue/head_v32.S b/arch/cris/boot/rescue/head_v32.S
deleted file mode 100644
index 9eb04abaa0c0..000000000000
--- a/arch/cris/boot/rescue/head_v32.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Just get started by jumping to CONFIG_ETRAX_PTABLE_SECTOR to start
- * kernel decompressor.
- *
- * In practice, this only works for NOR flash (or some convoluted RAM boot)
- * and hence is not really useful for Artpec-3, so it's Etrax FS / NOR only.
- *
- */
-
-#include <mach/startup.inc>
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP
-
-;; Code
-
- .text
-start:
-
- ;; Start clocks for used blocks.
- START_CLOCKS
-
- move.d CONFIG_ETRAX_PTABLE_SECTOR, $r10
- jump $r10 ; Jump to decompressor
- nop
-
-#endif
diff --git a/arch/cris/boot/rescue/kimagerescue.S b/arch/cris/boot/rescue/kimagerescue.S
deleted file mode 100644
index 3306098dee15..000000000000
--- a/arch/cris/boot/rescue/kimagerescue.S
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Rescue code to be prepended on a kimage and copied to the
- * rescue serial port.
- * This is called from the rescue code, it will copy received data to
- * 4004000 and after a timeout jump to it.
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
-#define CODE_START 0x40004000
-#define CODE_LENGTH 784
-#define TIMEOUT_VALUE 1000
-
-
-#ifdef CONFIG_ETRAX_RESCUE_SER0
-#define SERXOFF R_SERIAL0_XOFF
-#define SERBAUD R_SERIAL0_BAUD
-#define SERRECC R_SERIAL0_REC_CTRL
-#define SERRDAT R_SERIAL0_REC_DATA
-#define SERSTAT R_SERIAL0_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER1
-#define SERXOFF R_SERIAL1_XOFF
-#define SERBAUD R_SERIAL1_BAUD
-#define SERRECC R_SERIAL1_REC_CTRL
-#define SERRDAT R_SERIAL1_REC_DATA
-#define SERSTAT R_SERIAL1_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER2
-#define SERXOFF R_SERIAL2_XOFF
-#define SERBAUD R_SERIAL2_BAUD
-#define SERRECC R_SERIAL2_REC_CTRL
-#define SERRDAT R_SERIAL2_REC_DATA
-#define SERSTAT R_SERIAL2_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER3
-#define SERXOFF R_SERIAL3_XOFF
-#define SERBAUD R_SERIAL3_BAUD
-#define SERRECC R_SERIAL3_REC_CTRL
-#define SERRDAT R_SERIAL3_REC_DATA
-#define SERSTAT R_SERIAL3_STATUS
-#endif
-
- .text
- ;; This is the entry point of the rescue code
- ;; 0x80000000 if loaded in flash (as it should be)
- ;; since etrax actually starts at address 2 when booting from flash, we
- ;; put a nop (2 bytes) here first so we dont accidentally skip the di
-
- nop
- di
- ;; setup port PA and PB default initial directions and data
- ;; (so we can flash LEDs, and so that DTR and others are set)
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
- move.b $r0, [R_PORT_PA_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
- move.b $r0, [R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
- move.b $r0, [R_PORT_PB_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
- move.b $r0, [R_PORT_PB_DATA]
-
- ;; We need to setup the bus registers before we start using the DRAM
-#include "../../lib/dram_init.S"
-
- ;; Setup the stack to a suitably high address.
- ;; We assume 8 MB is the minimum DRAM in an eLinux
- ;; product and put the sp at the top for now.
-
- move.d 0x40800000, $sp
-
- ;; setup the serial port at 115200 baud
-
- moveq 0, $r0
- move.d $r0, [SERXOFF]
-
- move.b 0x99, $r0
- move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit
- ; and receive
-
- move.b 0x40, $r0 ; rec enable
- move.b $r0, [SERRECC]
-
-
- moveq 0, $r1 ; "timer" to clock out a LED red flash
- move.d CODE_START, $r3 ; destination counter
- move.d CODE_LENGTH, $r4 ; length
- move.d TIMEOUT_VALUE, $r5 ; "timeout" until jump
-
-wait_ser:
- addq 1, $r1
- subq 1, $r5 ; decrease timeout
- beq jump_start ; timed out
- nop
-#ifndef CONFIG_ETRAX_NO_LEDS
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2
-#endif
- move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0
- btstq 16, $r1
- bpl 1f
- nop
- or.d $r0, $r2 ; set bit
- ba 2f
- nop
-1: not $r0 ; clear bit
- and.d $r0, $r2
-2:
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b $r2, [R_PORT_PA_DATA]
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b $r2, [R_PORT_PB_DATA]
-#endif
-#endif
-
- ;; check if we got something on the serial port
-
- move.b [SERSTAT], $r0
- btstq 0, $r0 ; data_avail
- bpl wait_ser
- nop
-
- ;; got something - copy the byte and loop
-
- move.b [SERRDAT], $r0
- move.b $r0, [$r3+]
- move.d TIMEOUT_VALUE, $r5 ; reset "timeout"
- subq 1, $r4 ; decrease length
- bne wait_ser
- nop
-jump_start:
- ;; jump into downloaded code
-
- jump CODE_START
diff --git a/arch/cris/boot/rescue/rescue_v10.lds b/arch/cris/boot/rescue/rescue_v10.lds
deleted file mode 100644
index e58a53f91728..000000000000
--- a/arch/cris/boot/rescue/rescue_v10.lds
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-MEMORY
- {
- flash : ORIGIN = 0x00000000,
- LENGTH = 0x00100000
- }
-
-SECTIONS
-{
- .text :
- {
- stext = . ;
- *(.text)
- etext = . ;
- } > flash
- .data :
- {
- *(.data)
- edata = . ;
- } > flash
-}
diff --git a/arch/cris/boot/rescue/rescue_v32.lds b/arch/cris/boot/rescue/rescue_v32.lds
deleted file mode 100644
index f1542183f263..000000000000
--- a/arch/cris/boot/rescue/rescue_v32.lds
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*#OUTPUT_FORMAT(elf32-us-cris) */
-OUTPUT_ARCH (crisv32)
-/* Now that NAND support has been stripped, this file could be simplified,
- * but it doesn't do any harm on the other hand so why bother. */
-
-MEMORY
- {
- bootblk : ORIGIN = 0x38000000,
- LENGTH = 0x00004000
- intmem : ORIGIN = 0x38004000,
- LENGTH = 0x00005000
- }
-
-SECTIONS
-{
- .text :
- {
- _stext = . ;
- *(.text)
- *(.init.text)
- *(.rodata)
- *(.rodata.*)
- _etext = . ;
- } > bootblk
- .data :
- {
- *(.data)
- _edata = . ;
- } > bootblk
- .bss :
- {
- _bss = . ;
- *(.bss)
- _end = ALIGN( 0x10 ) ;
- } > intmem
-
- /* Get rid of stuff from EXPORT_SYMBOL(foo). */
- /DISCARD/ :
- {
- *(__ksymtab_strings)
- *(__ksymtab)
- }
-}
diff --git a/arch/cris/boot/rescue/testrescue.S b/arch/cris/boot/rescue/testrescue.S
deleted file mode 100644
index 06f78a0b0622..000000000000
--- a/arch/cris/boot/rescue/testrescue.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Simple testcode to download by the rescue block.
- * Just lights some LEDs to show it was downloaded correctly.
- *
- * Copyright (C) 1999 Axis Communications AB
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
- .text
-
- nop
- nop
- moveq -1, $r2
- move.b $r2, [R_PORT_PA_DIR]
- moveq 0, $r2
- move.b $r2, [R_PORT_PA_DATA]
-
-endless:
- nop
- ba endless
- nop
-
diff --git a/arch/cris/boot/tools/build.c b/arch/cris/boot/tools/build.c
deleted file mode 100644
index 3ae485049779..000000000000
--- a/arch/cris/boot/tools/build.c
+++ /dev/null
@@ -1,288 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/tools/build.c
- *
- * Copyright (C) 1991, 1992 Linus Torvalds
- */
-
-/*
- * This file builds a disk-image from three different files:
- *
- * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest
- * - setup: 8086 machine code, sets up system parm
- * - system: 80386 code for actual system
- *
- * It does some checking that all files are of the correct type, and
- * just writes the result to stdout, removing headers and padding to
- * the right amount. It also writes some system data to stderr.
- */
-
-/*
- * Changes by tytso to allow root device specification
- * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
- * Cross compiling fixes by Gertjan van Wingerde, July 1996
- */
-
-#include <stdio.h> /* fprintf */
-#include <string.h>
-#include <stdlib.h> /* contains exit */
-#include <sys/types.h> /* unistd.h needs this */
-#include <sys/stat.h>
-#include <sys/sysmacros.h>
-#include <unistd.h> /* contains read/write */
-#include <fcntl.h>
-#include <errno.h>
-
-#define MINIX_HEADER 32
-
-#define N_MAGIC_OFFSET 1024
-#ifndef __BFD__
-static int GCC_HEADER = sizeof(struct exec);
-#endif
-
-#ifdef __BIG_KERNEL__
-#define SYS_SIZE 0xffff
-#else
-#define SYS_SIZE DEF_SYSSIZE
-#endif
-
-#define DEFAULT_MAJOR_ROOT 0
-#define DEFAULT_MINOR_ROOT 0
-
-/* max nr of sectors of setup: don't change unless you also change
- * bootsect etc */
-#define SETUP_SECTS 4
-
-#define STRINGIFY(x) #x
-
-typedef union {
- int i;
- long l;
- short s[2];
- char b[4];
-} conv;
-
-long intel_long(long l)
-{
- conv t;
-
- t.b[0] = l & 0xff; l >>= 8;
- t.b[1] = l & 0xff; l >>= 8;
- t.b[2] = l & 0xff; l >>= 8;
- t.b[3] = l & 0xff; l >>= 8;
- return t.l;
-}
-
-int intel_int(int i)
-{
- conv t;
-
- t.b[0] = i & 0xff; i >>= 8;
- t.b[1] = i & 0xff; i >>= 8;
- t.b[2] = i & 0xff; i >>= 8;
- t.b[3] = i & 0xff; i >>= 8;
- return t.i;
-}
-
-short intel_short(short l)
-{
- conv t;
-
- t.b[0] = l & 0xff; l >>= 8;
- t.b[1] = l & 0xff; l >>= 8;
- return t.s[0];
-}
-
-void die(const char * str)
-{
- fprintf(stderr,"%s\n",str);
- exit(1);
-}
-
-void usage(void)
-{
- die("Usage: build bootsect setup system [rootdev] [> image]");
-}
-
-int main(int argc, char ** argv)
-{
- int i,c,id,sz,tmp_int;
- unsigned long sys_size, tmp_long;
- char buf[1024];
-#ifndef __BFD__
- struct exec *ex = (struct exec *)buf;
-#endif
- char major_root, minor_root;
- struct stat sb;
- unsigned char setup_sectors;
-
- if ((argc < 4) || (argc > 5))
- usage();
- if (argc > 4) {
- if (!strcmp(argv[4], "CURRENT")) {
- if (stat("/", &sb)) {
- perror("/");
- die("Couldn't stat /");
- }
- major_root = major(sb.st_dev);
- minor_root = minor(sb.st_dev);
- } else if (strcmp(argv[4], "FLOPPY")) {
- if (stat(argv[4], &sb)) {
- perror(argv[4]);
- die("Couldn't stat root device.");
- }
- major_root = major(sb.st_rdev);
- minor_root = minor(sb.st_rdev);
- } else {
- major_root = 0;
- minor_root = 0;
- }
- } else {
- major_root = DEFAULT_MAJOR_ROOT;
- minor_root = DEFAULT_MINOR_ROOT;
- }
- fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
- for (i=0;i<sizeof buf; i++) buf[i]=0;
- if ((id=open(argv[1],O_RDONLY,0))<0)
- die("Unable to open 'boot'");
- if (read(id,buf,MINIX_HEADER) != MINIX_HEADER)
- die("Unable to read header of 'boot'");
- if (((long *) buf)[0]!=intel_long(0x04100301))
- die("Non-Minix header of 'boot'");
- if (((long *) buf)[1]!=intel_long(MINIX_HEADER))
- die("Non-Minix header of 'boot'");
- if (((long *) buf)[3] != 0)
- die("Illegal data segment in 'boot'");
- if (((long *) buf)[4] != 0)
- die("Illegal bss in 'boot'");
- if (((long *) buf)[5] != 0)
- die("Non-Minix header of 'boot'");
- if (((long *) buf)[7] != 0)
- die("Illegal symbol table in 'boot'");
- i=read(id,buf,sizeof buf);
- fprintf(stderr,"Boot sector %d bytes.\n",i);
- if (i != 512)
- die("Boot block must be exactly 512 bytes");
- if ((*(unsigned short *)(buf+510)) != (unsigned short)intel_short(0xAA55))
- die("Boot block hasn't got boot flag (0xAA55)");
- buf[508] = (char) minor_root;
- buf[509] = (char) major_root;
- i=write(1,buf,512);
- if (i!=512)
- die("Write call failed");
- close (id);
-
- if ((id=open(argv[2],O_RDONLY,0))<0)
- die("Unable to open 'setup'");
- if (read(id,buf,MINIX_HEADER) != MINIX_HEADER)
- die("Unable to read header of 'setup'");
- if (((long *) buf)[0]!=intel_long(0x04100301))
- die("Non-Minix header of 'setup'");
- if (((long *) buf)[1]!=intel_long(MINIX_HEADER))
- die("Non-Minix header of 'setup'");
- if (((long *) buf)[3] != 0)
- die("Illegal data segment in 'setup'");
- if (((long *) buf)[4] != 0)
- die("Illegal bss in 'setup'");
- if (((long *) buf)[5] != 0)
- die("Non-Minix header of 'setup'");
- if (((long *) buf)[7] != 0)
- die("Illegal symbol table in 'setup'");
- for (i=0 ; (c=read(id,buf,sizeof buf))>0 ; i+=c )
-#ifdef __BIG_KERNEL__
- {
- if (!i) {
- /* Working with memcpy because of alignment constraints
- on Sparc - Gertjan */
- memcpy(&tmp_long, &buf[2], sizeof(long));
- if (tmp_long != intel_long(0x53726448) )
- die("Wrong magic in loader header of 'setup'");
- memcpy(&tmp_int, &buf[6], sizeof(int));
- if (tmp_int < intel_int(0x200))
- die("Wrong version of loader header of 'setup'");
- buf[0x11] = 1; /* LOADED_HIGH */
- tmp_long = intel_long(0x100000);
- memcpy(&buf[0x14], &tmp_long, sizeof(long)); /* code32_start */
- }
-#endif
- if (write(1,buf,c)!=c)
- die("Write call failed");
-#ifdef __BIG_KERNEL__
- }
-#endif
- if (c != 0)
- die("read-error on 'setup'");
- close (id);
- setup_sectors = (unsigned char)((i + 511) / 512);
- /* for compatibility with LILO */
- if (setup_sectors < SETUP_SECTS)
- setup_sectors = SETUP_SECTS;
- fprintf(stderr,"Setup is %d bytes.\n",i);
- for (c=0 ; c<sizeof(buf) ; c++)
- buf[c] = '\0';
- while (i < setup_sectors * 512) {
- c = setup_sectors * 512 - i;
- if (c > sizeof(buf))
- c = sizeof(buf);
- if (write(1,buf,c) != c)
- die("Write call failed");
- i += c;
- }
-
- if ((id=open(argv[3],O_RDONLY,0))<0)
- die("Unable to open 'system'");
-#ifndef __BFD__
- if (read(id,buf,GCC_HEADER) != GCC_HEADER)
- die("Unable to read header of 'system'");
- if (N_MAGIC(*ex) == ZMAGIC) {
- GCC_HEADER = N_MAGIC_OFFSET;
- lseek(id, GCC_HEADER, SEEK_SET);
- } else if (N_MAGIC(*ex) != QMAGIC)
- die("Non-GCC header of 'system'");
- fprintf(stderr,"System is %d kB (%d kB code, %d kB data and %d kB bss)\n",
- (ex->a_text+ex->a_data+ex->a_bss)/1024,
- ex->a_text /1024,
- ex->a_data /1024,
- ex->a_bss /1024);
- sz = N_SYMOFF(*ex) - GCC_HEADER + 4;
-#else
- if (fstat (id, &sb)) {
- perror ("fstat");
- die ("Unable to stat 'system'");
- }
- sz = sb.st_size;
- fprintf (stderr, "System is %d kB\n", sz/1024);
-#endif
- sys_size = (sz + 15) / 16;
- if (sys_size > SYS_SIZE)
- die("System is too big");
- while (sz > 0) {
- int l, n;
-
- l = sz;
- if (l > sizeof(buf))
- l = sizeof(buf);
- if ((n=read(id, buf, l)) != l) {
- if (n == -1)
- perror(argv[1]);
- else
- fprintf(stderr, "Unexpected EOF\n");
- die("Can't read 'system'");
- }
- if (write(1, buf, l) != l)
- die("Write failed");
- sz -= l;
- }
- close(id);
- if (lseek(1, 497, 0) == 497) {
- if (write(1, &setup_sectors, 1) != 1)
- die("Write of setup sectors failed");
- }
- if (lseek(1,500,0) == 500) {
- buf[0] = (sys_size & 0xff);
- buf[1] = ((sys_size >> 8) & 0xff);
- if (write(1, buf, 2) != 2)
- die("Write failed");
- }
- return(0);
-}
diff --git a/arch/cris/configs/artpec_3_defconfig b/arch/cris/configs/artpec_3_defconfig
deleted file mode 100644
index d31851f29db8..000000000000
--- a/arch/cris/configs/artpec_3_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_CRIS_MACH_ARTPEC3=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_MTDRAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ETRAX_GPIO=y
diff --git a/arch/cris/configs/dev88_defconfig b/arch/cris/configs/dev88_defconfig
deleted file mode 100644
index beff4ee6edb3..000000000000
--- a/arch/cris/configs/dev88_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_BUILTIN_DTB="dev88"
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_ETRAXFS=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_ETRAX_MEM_GRP1_CONFIG=0x40688
-CONFIG_ETRAX_MEM_GRP3_CONFIG=0x3
-CONFIG_ETRAX_MEM_GRP4_CONFIG=0x10040
-CONFIG_ETRAX_SDRAM_GRP0_CONFIG=0x958
-CONFIG_ETRAX_SDRAM_TIMING=0x824a
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_DEVTMPFS=y
-CONFIG_MTD_RAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_ETRAXFS=y
-CONFIG_SERIAL_ETRAXFS_CONSOLE=y
-CONFIG_GPIO_ETRAXFS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
diff --git a/arch/cris/configs/etrax-100lx_defconfig b/arch/cris/configs/etrax-100lx_defconfig
deleted file mode 100644
index cbbcefeaa8fc..000000000000
--- a/arch/cris/configs/etrax-100lx_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_ETRAX_LED1R=2
-CONFIG_ETRAX_LED2G=2
-CONFIG_ETRAX_LED2R=2
-CONFIG_ETRAX_DEF_R_PORT_PA_DIR=1d
-CONFIG_ETRAX_DEF_R_PORT_PA_DATA=f0
-CONFIG_ETRAX_DEF_R_PORT_PB_DIR=1e
-CONFIG_ETRAX_DEF_R_PORT_PB_DATA=f3
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_SERIAL=y
-CONFIG_ETRAX_SERIAL_PORT0=y
-CONFIG_ETRAX_SERIAL_PORT1=y
-CONFIG_ETRAX_I2C=y
-CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C=y
-CONFIG_ETRAX_GPIO=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_NETDEVICES=y
-CONFIG_CRAMFS=y
diff --git a/arch/cris/configs/etrax-100lx_v2_defconfig b/arch/cris/configs/etrax-100lx_v2_defconfig
deleted file mode 100644
index d90ac95c1e44..000000000000
--- a/arch/cris/configs/etrax-100lx_v2_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_ETRAX100LX_V2=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_ETRAX_DEBUG_PORT_NULL=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_SERIAL=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_MTDRAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
diff --git a/arch/cris/configs/etraxfs_defconfig b/arch/cris/configs/etraxfs_defconfig
deleted file mode 100644
index f714e9dfef9b..000000000000
--- a/arch/cris/configs/etraxfs_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_ETRAXFS=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_MTDRAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ETRAX_GPIO=y
diff --git a/arch/cris/include/arch-v10/arch/bitops.h b/arch/cris/include/arch-v10/arch/bitops.h
deleted file mode 100644
index c18f81858899..000000000000
--- a/arch/cris/include/arch-v10/arch/bitops.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* asm/arch/bitops.h for Linux/CRISv10 */
-
-#ifndef _CRIS_ARCH_BITOPS_H
-#define _CRIS_ARCH_BITOPS_H
-
-/*
- * Helper functions for the core of the ff[sz] functions, wrapping the
- * syntactically awkward asms. The asms compute the number of leading
- * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped
- * number. They differ in that the first function also inverts all bits
- * in the input.
- */
-static inline unsigned long cris_swapnwbrlz(unsigned long w)
-{
- /* Let's just say we return the result in the same register as the
- input. Saying we clobber the input but can return the result
- in another register:
- ! __asm__ ("swapnwbr %2\n\tlz %2,%0"
- ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w));
- confuses gcc (core.c, gcc from cris-dist-1.14). */
-
- unsigned long res;
- __asm__ ("swapnwbr %0 \n\t"
- "lz %0,%0"
- : "=r" (res) : "0" (w));
- return res;
-}
-
-static inline unsigned long cris_swapwbrlz(unsigned long w)
-{
- unsigned res;
- __asm__ ("swapwbr %0 \n\t"
- "lz %0,%0"
- : "=r" (res)
- : "0" (w));
- return res;
-}
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long w)
-{
- return cris_swapnwbrlz(w);
-}
-
-/**
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
- return cris_swapnwbrlz(~word);
-}
-
-/**
- * ffs - find first bit set
- * @x: the word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-
-static inline unsigned long kernel_ffs(unsigned long w)
-{
- return w ? cris_swapwbrlz (w) + 1 : 0;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h
deleted file mode 100644
index 06da9d49152a..000000000000
--- a/arch/cris/include/arch-v10/arch/bug.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRISv10_ARCH_BUG_H
-#define __ASM_CRISv10_ARCH_BUG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_BUG
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-/* The BUG() macro is used for marking obviously incorrect code paths.
- * It will cause a message with the file name and line number to be printed,
- * and then cause an oops. The message is actually printed by handle_BUG()
- * in arch/cris/kernel/traps.c, and the reason we use this method of storing
- * the file name and line number is that we do not want to affect the registers
- * by calling printk() before causing the oops.
- */
-
-#define BUG_PREFIX 0x0D7F
-#define BUG_MAGIC 0x00001234
-
-struct bug_frame {
- unsigned short prefix;
- unsigned int magic;
- unsigned short clear;
- unsigned short movu;
- unsigned short line;
- unsigned short jump;
- unsigned char *filename;
-};
-
-#if 0
-/* Unfortunately this version of the macro does not work due to a problem
- * with the compiler (aka a bug) when compiling with -O2, which sometimes
- * erroneously causes the second input to be stored in a register...
- */
-#define BUG() \
- __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
- "movu.w %0,$r0\n\t" \
- "jump %1\n\t" \
- : : "i" (__LINE__), "i" (__FILE__))
-#else
-/* This version will have to do for now, until the compiler is fixed.
- * The drawbacks of this version are that the file name will appear multiple
- * times in the .rodata section, and that __LINE__ and __FILE__ can probably
- * not be used like this with newer versions of gcc.
- */
-#define BUG() \
-do { \
- __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
- "movu.w " __stringify(__LINE__) ",$r0\n\t"\
- "jump 0f\n\t" \
- ".section .rodata\n" \
- "0:\t.string \"" __FILE__ "\"\n\t" \
- ".previous"); \
- unreachable(); \
-} while (0)
-#endif
-
-#else
-
-/* This just causes an oops. */
-#define BUG() \
-do { \
- barrier_before_unreachable(); \
- __builtin_trap(); \
-} while (0)
-
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/cache.h b/arch/cris/include/arch-v10/arch/cache.h
deleted file mode 100644
index d4049bcab3c5..000000000000
--- a/arch/cris/include/arch-v10/arch/cache.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CACHE_H
-#define _ASM_ARCH_CACHE_H
-
-/* Etrax 100LX have 32-byte cache-lines. */
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-
-#endif /* _ASM_ARCH_CACHE_H */
diff --git a/arch/cris/include/arch-v10/arch/checksum.h b/arch/cris/include/arch-v10/arch/checksum.h
deleted file mode 100644
index eb186be4fb32..000000000000
--- a/arch/cris/include/arch-v10/arch/checksum.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_CHECKSUM_H
-#define _CRIS_ARCH_CHECKSUM_H
-
-/* Checksum some values used in TCP/UDP headers.
- *
- * The gain by doing this in asm is that C will not generate carry-additions
- * for the 32-bit components of the checksum, so otherwise we would have had
- * to split all of those into 16-bit components, then add.
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- __wsum res;
- __asm__ ("add.d %2, %0\n\t"
- "ax\n\t"
- "add.d %3, %0\n\t"
- "ax\n\t"
- "add.d %4, %0\n\t"
- "ax\n\t"
- "addq 0, %0\n"
- : "=r" (res)
- : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8));
-
- return res;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/delay.h b/arch/cris/include/arch-v10/arch/delay.h
deleted file mode 100644
index a57d2cc0baf7..000000000000
--- a/arch/cris/include/arch-v10/arch/delay.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_DELAY_H
-#define _CRIS_ARCH_DELAY_H
-
-static inline void __delay(int loops)
-{
- __asm__ __volatile__ (
- "move.d %0,$r9\n\t"
- "beq 2f\n\t"
- "subq 1,$r9\n\t"
- "1:\n\t"
- "bne 1b\n\t"
- "subq 1,$r9\n"
- "2:"
- : : "g" (loops) : "r9");
-}
-
-#endif /* defined(_CRIS_ARCH_DELAY_H) */
-
-
-
diff --git a/arch/cris/include/arch-v10/arch/dma.h b/arch/cris/include/arch-v10/arch/dma.h
deleted file mode 100644
index ea794a32cf5e..000000000000
--- a/arch/cris/include/arch-v10/arch/dma.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Defines for using and allocating dma channels. */
-
-#ifndef _ASM_ARCH_DMA_H
-#define _ASM_ARCH_DMA_H
-
-#define MAX_DMA_CHANNELS 10
-
-/* dma0 and dma1 used for network (ethernet) */
-#define NETWORK_TX_DMA_NBR 0
-#define NETWORK_RX_DMA_NBR 1
-
-/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
-#define PAR0_TX_DMA_NBR 2
-#define PAR0_RX_DMA_NBR 3
-#define SCSI0_TX_DMA_NBR 2
-#define SCSI0_RX_DMA_NBR 3
-#define SER2_TX_DMA_NBR 2
-#define SER2_RX_DMA_NBR 3
-#define ATA_TX_DMA_NBR 2
-#define ATA_RX_DMA_NBR 3
-
-/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
-#define PAR1_TX_DMA_NBR 4
-#define PAR1_RX_DMA_NBR 5
-#define SCSI1_TX_DMA_NBR 4
-#define SCSI1_RX_DMA_NBR 5
-#define SER3_TX_DMA_NBR 4
-#define SER3_RX_DMA_NBR 5
-#define EXTDMA0_TX_DMA_NBR 4
-#define EXTDMA0_RX_DMA_NBR 5
-
-/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
-#define SER0_TX_DMA_NBR 6
-#define SER0_RX_DMA_NBR 7
-#define EXTDMA1_TX_DMA_NBR 6
-#define EXTDMA1_RX_DMA_NBR 7
-#define MEM2MEM_TX_DMA_NBR 6
-#define MEM2MEM_RX_DMA_NBR 7
-
-/* dma8 and dma9 shared by ser1 and usb */
-#define SER1_TX_DMA_NBR 8
-#define SER1_RX_DMA_NBR 9
-#define USB_TX_DMA_NBR 8
-#define USB_RX_DMA_NBR 9
-
-#endif
-
-enum dma_owner
-{
- dma_eth,
- dma_ser0,
- dma_ser1, /* Async and sync */
- dma_ser2,
- dma_ser3, /* Async and sync */
- dma_ata,
- dma_par0,
- dma_par1,
- dma_ext0,
- dma_ext1,
- dma_int6,
- dma_int7,
- dma_usb,
- dma_scsi0,
- dma_scsi1
-};
-
-/* Masks used by cris_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR (1<<0)
-#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR)
-
-int cris_request_dma(unsigned int dmanr, const char * device_id,
- unsigned options, enum dma_owner owner);
-
-void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/arch/cris/include/arch-v10/arch/io.h b/arch/cris/include/arch-v10/arch/io.h
deleted file mode 100644
index bae5f77cfabc..000000000000
--- a/arch/cris/include/arch-v10/arch/io.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CRIS_IO_H
-#define _ASM_ARCH_CRIS_IO_H
-
-/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
-
-extern unsigned long gen_config_ii_shadow;
-extern unsigned long port_g_data_shadow;
-extern unsigned char port_pa_dir_shadow;
-extern unsigned char port_pa_data_shadow;
-extern unsigned char port_pb_i2c_shadow;
-extern unsigned char port_pb_config_shadow;
-extern unsigned char port_pb_dir_shadow;
-extern unsigned char port_pb_data_shadow;
-extern unsigned long r_timer_ctrl_shadow;
-
-extern unsigned long port_cse1_shadow;
-extern unsigned long port_csp0_shadow;
-extern unsigned long port_csp4_shadow;
-
-extern volatile unsigned long *port_cse1_addr;
-extern volatile unsigned long *port_csp0_addr;
-extern volatile unsigned long *port_csp4_addr;
-
-/* macro for setting regs through a shadow -
- * r = register name (like R_PORT_PA_DATA)
- * s = shadow name (like port_pa_data_shadow)
- * b = bit number
- * v = value (0 or 1)
- */
-
-#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b))
-
-/* The LED's on various Etrax-based products are set differently. */
-
-#if defined(CONFIG_ETRAX_NO_LEDS)
-#undef CONFIG_ETRAX_PA_LEDS
-#undef CONFIG_ETRAX_PB_LEDS
-#undef CONFIG_ETRAX_CSP0_LEDS
-#define CRIS_LED_NETWORK_SET_G(x)
-#define CRIS_LED_NETWORK_SET_R(x)
-#define CRIS_LED_ACTIVE_SET_G(x)
-#define CRIS_LED_ACTIVE_SET_R(x)
-#define CRIS_LED_DISK_WRITE(x)
-#define CRIS_LED_DISK_READ(x)
-#endif
-
-#if !defined(CONFIG_ETRAX_CSP0_LEDS)
-#define CRIS_LED_BIT_SET(x)
-#define CRIS_LED_BIT_CLR(x)
-#endif
-
-#define CRIS_LED_OFF 0x00
-#define CRIS_LED_GREEN 0x01
-#define CRIS_LED_RED 0x02
-#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
-
-#if defined(CONFIG_ETRAX_NO_LEDS)
-#define CRIS_LED_NETWORK_SET(x)
-#else
-#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
-#define CRIS_LED_NETWORK_SET(x) \
- do { \
- CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
- } while (0)
-#else
-#define CRIS_LED_NETWORK_SET(x) \
- do { \
- CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
- CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \
- } while (0)
-#endif
-#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
-#define CRIS_LED_ACTIVE_SET(x) \
- do { \
- CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
- } while (0)
-#else
-#define CRIS_LED_ACTIVE_SET(x) \
- do { \
- CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
- CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
- } while (0)
-#endif
-#endif
-
-#ifdef CONFIG_ETRAX_PA_LEDS
-#define CRIS_LED_NETWORK_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
- do{\
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
- }while(0)
-#define CRIS_LED_DISK_READ(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \
- CONFIG_ETRAX_LED3G, !(x))
-#endif
-
-#ifdef CONFIG_ETRAX_PB_LEDS
-#define CRIS_LED_NETWORK_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
- do{\
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
- }while(0)
-#define CRIS_LED_DISK_READ(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \
- CONFIG_ETRAX_LED3G, !(x))
-#endif
-
-#ifdef CONFIG_ETRAX_CSP0_LEDS
-#define CONFIGURABLE_LEDS\
- ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\
- (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\
- (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\
- (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\
- (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\
- (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\
- (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\
- (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\
- (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\
- (1 << CONFIG_ETRAX_LED12R ))
-
-#define CRIS_LED_NETWORK_SET_G(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
- do{\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\
- }while(0)
-#define CRIS_LED_DISK_READ(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x))
-#define CRIS_LED_BIT_SET(x)\
- do{\
- if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\
- }while(0)
-#define CRIS_LED_BIT_CLR(x)\
- do{\
- if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\
- }while(0)
-#endif
-
-#
-#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN
-#define SOFT_SHUTDOWN() \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1)
-#else
-#define SOFT_SHUTDOWN()
-#endif
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/io_interface_mux.h b/arch/cris/include/arch-v10/arch/io_interface_mux.h
deleted file mode 100644
index 2d5617e67ab0..000000000000
--- a/arch/cris/include/arch-v10/arch/io_interface_mux.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* IO interface mux allocator for ETRAX100LX.
- * Copyright 2004, Axis Communications AB
- * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
- */
-
-
-#ifndef _IO_INTERFACE_MUX_H
-#define _IO_INTERFACE_MUX_H
-
-
-/* C.f. ETRAX100LX Designer's Reference 20.9 */
-
-/* The order in enum must match the order of interfaces[] in
- * io_interface_mux.c */
-enum cris_io_interface {
- /* Begin Non-multiplexed interfaces */
- if_eth = 0,
- if_serial_0,
- /* End Non-multiplexed interfaces */
- if_serial_1,
- if_serial_2,
- if_serial_3,
- if_sync_serial_1,
- if_sync_serial_3,
- if_shared_ram,
- if_shared_ram_w,
- if_par_0,
- if_par_1,
- if_par_w,
- if_scsi8_0,
- if_scsi8_1,
- if_scsi_w,
- if_ata,
- if_csp,
- if_i2c,
- if_usb_1,
- if_usb_2,
- /* GPIO pins */
- if_gpio_grp_a,
- if_gpio_grp_b,
- if_gpio_grp_c,
- if_gpio_grp_d,
- if_gpio_grp_e,
- if_gpio_grp_f,
- if_max_interfaces,
- if_unclaimed
-};
-
-int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
-
-void cris_free_io_interface(enum cris_io_interface ioif);
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit);
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_free_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit);
-
-int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available));
-
-void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available));
-
-#endif /* _IO_INTERFACE_MUX_H */
diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h
deleted file mode 100644
index c4e8a78e33d1..000000000000
--- a/arch/cris/include/arch-v10/arch/irq.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Interrupt handling assembler and defines for Linux/CRISv10
- */
-
-#ifndef _ASM_ARCH_IRQ_H
-#define _ASM_ARCH_IRQ_H
-
-#include <arch/sv_addr_ag.h>
-
-#define NR_IRQS 32
-
-/* The first vector number used for IRQs in v10 is really 0x20 */
-/* but all the code and constants are offseted to make 0 the first */
-#define FIRST_IRQ 0
-
-#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */
-#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */
-#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */
-#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */
-/* mio, ata, par0, scsi0 on 4 */
-/* par1, scsi1 on 5 */
-#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */
-
-#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */
-#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */
-/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */
-#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0)
-#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1)
-
-/* dma0-9 is irq 16..25 */
-/* 16,17: network */
-#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0)
-#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1)
-#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR
-#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR
-
-/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */
-#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2)
-#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3)
-#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR
-#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR
-
-/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
-#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4)
-#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5)
-#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR
-#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR
-
-/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */
-#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6)
-#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7)
-#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
-#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
-#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
-#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
-
-/* 24,25: dma8 and dma9 shared by ser1 and usb */
-#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8)
-#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9)
-#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
-#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
-#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
-#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
-
-/* usb: controller at irq 31 + uses DMA8 and DMA9 */
-#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb)
-
-/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */
-
-typedef void (*irqvectptr)(void);
-
-struct etrax_interrupt_vector {
- irqvectptr v[256];
-};
-
-extern struct etrax_interrupt_vector *etrax_irv;
-void set_int_vector(int n, irqvectptr addr);
-void set_break_vector(int n, irqvectptr addr);
-
-#define __STR(x) #x
-#define STR(x) __STR(x)
-
-/* SAVE_ALL saves registers so they match pt_regs */
-
-#define SAVE_ALL \
- "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \
- "push $srp\n\t" /* push subroutine return pointer */ \
- "push $dccr\n\t" /* push condition codes */ \
- "push $mof\n\t" /* push multiply overflow reg */ \
- "di\n\t" /* need to disable irq's at this point */\
- "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \
- "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \
- "push $r10\n\t" /* push orig_r10 */ \
- "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
-
-/* BLOCK_IRQ and UNBLOCK_IRQ do the same as
- * crisv10_mask_irq and crisv10_unmask_irq */
-
-#define BLOCK_IRQ(mask,nr) \
- "move.d " #mask ",$r0\n\t" \
- "move.d $r0,[0xb00000d8]\n\t"
-
-#define UNBLOCK_IRQ(mask) \
- "move.d " #mask ",$r0\n\t" \
- "move.d $r0,[0xb00000dc]\n\t"
-
-#define IRQ_NAME2(nr) nr##_interrupt(void)
-#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
-#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr)
-#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
-
- /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls
- * do_IRQ (with irq disabled still). after that it unblocks and jumps to
- * ret_from_intr (entry.S)
- *
- * The reason the IRQ is blocked is to allow an sti() before the handler which
- * will acknowledge the interrupt is run.
- */
-
-#define BUILD_IRQ(nr,mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
- "moveq "#nr",$r10\n\t" \
- "move.d $sp,$r11\n\t" \
- "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
- UNBLOCK_IRQ(mask) \
- "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
- "jump ret_from_intr\n\t");
-
-/* This is subtle. The timer interrupt is crucial and it should not be disabled for
- * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
- * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK.
- * If the softirq's take too much time to run, the timer irq won't run and the
- * watchdog will kill us.
- *
- * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq
- * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
- * it here, we would not get the multiple_irq at all.
- *
- * The non-blocking here is based on the knowledge that the timer interrupt runs
- * with interrupts disabled, and therefore there will not be an sti() before the
- * timer irq handler is run to acknowledge the interrupt.
- */
-
-#define BUILD_TIMER_IRQ(nr,mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- "moveq "#nr",$r10\n\t" \
- "move.d $sp,$r11\n\t" \
- "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
- "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
- "jump ret_from_intr\n\t");
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/irqflags.h b/arch/cris/include/arch-v10/arch/irqflags.h
deleted file mode 100644
index 9959b0a8a58c..000000000000
--- a/arch/cris/include/arch-v10/arch/irqflags.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
-#define __ASM_CRIS_ARCH_IRQFLAGS_H
-
-#include <linux/types.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
- asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory");
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
- asm volatile("di" : : : "memory");
-}
-
-static inline void arch_local_irq_enable(void)
-{
- asm volatile("ei" : : : "memory");
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("move %0,$ccr" : : "rm" (flags) : "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & (1 << 5));
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */
diff --git a/arch/cris/include/arch-v10/arch/memmap.h b/arch/cris/include/arch-v10/arch/memmap.h
deleted file mode 100644
index b6b171f48b29..000000000000
--- a/arch/cris/include/arch-v10/arch/memmap.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/mmu.h b/arch/cris/include/arch-v10/arch/mmu.h
deleted file mode 100644
index 74c53048be79..000000000000
--- a/arch/cris/include/arch-v10/arch/mmu.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRIS MMU constants and PTE layout
- */
-
-#ifndef _CRIS_ARCH_MMU_H
-#define _CRIS_ARCH_MMU_H
-
-/* type used in struct mm to couple an MMU context to an active mm */
-
-typedef struct
-{
- unsigned int page_id;
-} mm_context_t;
-
-/* kernel memory segments */
-
-#define KSEG_F 0xf0000000UL
-#define KSEG_E 0xe0000000UL
-#define KSEG_D 0xd0000000UL
-#define KSEG_C 0xc0000000UL
-#define KSEG_B 0xb0000000UL
-#define KSEG_A 0xa0000000UL
-#define KSEG_9 0x90000000UL
-#define KSEG_8 0x80000000UL
-#define KSEG_7 0x70000000UL
-#define KSEG_6 0x60000000UL
-#define KSEG_5 0x50000000UL
-#define KSEG_4 0x40000000UL
-#define KSEG_3 0x30000000UL
-#define KSEG_2 0x20000000UL
-#define KSEG_1 0x10000000UL
-#define KSEG_0 0x00000000UL
-
-/* CRIS PTE bits (see R_TLB_LO in the register description)
- *
- * Bit: 31 30-13 12-------4 3 2 1 0
- * _______________________________________________________
- * | cache |pfn | reserved | global | valid | kernel | we |
- * |_______|____|__________|________|_______|________|_____|
- *
- * (pfn = physical frame number)
- */
-
-/* Real HW-based PTE bits. We use some synonym names so that
- * things become less confusing in combination with the SW-based
- * bits further below.
- *
- */
-
-#define _PAGE_WE (1<<0) /* page is write-enabled */
-#define _PAGE_SILENT_WRITE (1<<0) /* synonym */
-#define _PAGE_KERNEL (1<<1) /* page is kernel only */
-#define _PAGE_VALID (1<<2) /* page is valid */
-#define _PAGE_SILENT_READ (1<<2) /* synonym */
-#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */
-#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */
-
-/* Bits the HW doesn't care about but the kernel uses them in SW */
-
-#define _PAGE_PRESENT (1<<4) /* page present in memory */
-#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */
-#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */
-#define _PAGE_READ (1<<7) /* read-enabled */
-#define _PAGE_WRITE (1<<8) /* write-enabled */
-
-/* Define some higher level generic page attributes. */
-
-#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
-
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
- _PAGE_ACCESSED)
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
- _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
-
-/*
- * CRIS can't do page protection for execute, and considers read the same.
- * Also, write permissions imply read permissions. This is the closest we can
- * get..
- */
-
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY
-#define __P101 PAGE_READONLY
-#define __P110 PAGE_COPY
-#define __P111 PAGE_COPY
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY
-#define __S101 PAGE_READONLY
-#define __S110 PAGE_SHARED
-#define __S111 PAGE_SHARED
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/offset.h b/arch/cris/include/arch-v10/arch/offset.h
deleted file mode 100644
index 6f0f2b4a163f..000000000000
--- a/arch/cris/include/arch-v10/arch/offset.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/cris/Makefile
- *
- */
-
-#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */
-#define PT_r13 8 /* offsetof(struct pt_regs, r13) */
-#define PT_r12 12 /* offsetof(struct pt_regs, r12) */
-#define PT_r11 16 /* offsetof(struct pt_regs, r11) */
-#define PT_r10 20 /* offsetof(struct pt_regs, r10) */
-#define PT_r9 24 /* offsetof(struct pt_regs, r9) */
-#define PT_mof 64 /* offsetof(struct pt_regs, mof) */
-#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */
-#define PT_srp 72 /* offsetof(struct pt_regs, srp) */
-
-#define TI_task 0 /* offsetof(struct thread_info, task) */
-#define TI_flags 8 /* offsetof(struct thread_info, flags) */
-#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
-
-#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
-
-#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
-
-#define LCLONE_VM 256 /* CLONE_VM */
-#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/page.h b/arch/cris/include/arch-v10/arch/page.h
deleted file mode 100644
index a4bbff64868c..000000000000
--- a/arch/cris/include/arch-v10/arch/page.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_PAGE_H
-#define _CRIS_ARCH_PAGE_H
-
-
-#ifdef __KERNEL__
-
-/* This handles the memory map.. */
-#ifdef CONFIG_CRIS_LOW_MAP
-#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */
-#else
-#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */
-#endif
-
-/* macros to convert between really physical and virtual addresses
- * by stripping a selected bit, we can convert between KSEG_x and
- * 0x40000000 where the DRAM really resides
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-/* we have DRAM virtually at 0x6 */
-#define __pa(x) ((unsigned long)(x) & 0xdfffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x20000000))
-#else
-/* we have DRAM virtually at 0xc */
-#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
-#endif
-
-#endif
-#endif
diff --git a/arch/cris/include/arch-v10/arch/pgtable.h b/arch/cris/include/arch-v10/arch/pgtable.h
deleted file mode 100644
index a61532d06acb..000000000000
--- a/arch/cris/include/arch-v10/arch/pgtable.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_PGTABLE_H
-#define _CRIS_ARCH_PGTABLE_H
-
-/*
- * Kernels own virtual memory area.
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define VMALLOC_START KSEG_7
-#define VMALLOC_END KSEG_8
-#else
-#define VMALLOC_START KSEG_D
-#define VMALLOC_END KSEG_E
-#endif
-
-#endif
-
diff --git a/arch/cris/include/arch-v10/arch/processor.h b/arch/cris/include/arch-v10/arch/processor.h
deleted file mode 100644
index b2df646bc1eb..000000000000
--- a/arch/cris/include/arch-v10/arch/processor.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_PROCESSOR_H
-#define __ASM_CRIS_ARCH_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; })
-
-/* CRIS has no problems with write protection */
-#define wp_works_ok 1
-
-/* CRIS thread_struct. this really has nothing to do with the processor itself, since
- * CRIS does not do any hardware task-switching, but it's here for legacy reasons.
- * The thread_struct here is used when task-switching using _resume defined in entry.S.
- * The offsets here are hardcoded into _resume - if you change this struct, you need to
- * change them as well!!!
-*/
-
-struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned long dccr; /* saved flag register */
-};
-
-/*
- * User space process size. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define TASK_SIZE (0x50000000UL) /* 1.25 GB */
-#else
-#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */
-#endif
-
-#define INIT_THREAD { \
- 0, 0, 0x20 } /* ccr = int enable, nothing else */
-
-#define KSTK_EIP(tsk) \
-({ \
- unsigned long eip = 0; \
- unsigned long regs = (unsigned long)task_pt_regs(tsk); \
- if (regs > PAGE_SIZE && \
- virt_addr_valid(regs)) \
- eip = ((struct pt_regs *)regs)->irp; \
- eip; \
-})
-
-/* give the thread a program location
- * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8)
- * switch user-stackpointer
- */
-
-#define start_thread(regs, ip, usp) do { \
- regs->irp = ip; \
- regs->dccr |= 1 << U_DCCR_BITNR; \
- wrusp(usp); \
-} while(0)
-
-/* Called when handling a kernel bus fault fixup.
- *
- * After a fixup we do not want to return by restoring the CPU-state
- * anymore, so switch frame-types (see ptrace.h)
- */
-#define arch_fixup(regs) \
- regs->frametype = CRIS_FRAME_NORMAL;
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/swab.h b/arch/cris/include/arch-v10/arch/swab.h
deleted file mode 100644
index 8cc27dfb9d3a..000000000000
--- a/arch/cris/include/arch-v10/arch/swab.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_SWAB_H
-#define _CRIS_ARCH_SWAB_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#define __SWAB_64_THRU_32__
-
-/* we just define these two (as we can do the swap in a single
- * asm instruction in CRIS) and the arch-independent files will put
- * them together into ntohl etc.
- */
-
-static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
-{
- __asm__ ("swapwb %0" : "=r" (x) : "0" (x));
-
- return(x);
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
-{
- __asm__ ("swapb %0" : "=r" (x) : "0" (x));
-
- return(x);
-}
-#define __arch_swab16 __arch_swab16
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/system.h b/arch/cris/include/arch-v10/arch/system.h
deleted file mode 100644
index 4c63f728122b..000000000000
--- a/arch/cris/include/arch-v10/arch/system.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_SYSTEM_H
-#define __ASM_CRIS_ARCH_SYSTEM_H
-
-
-/* read the CPU version register */
-
-static inline unsigned long rdvr(void) {
- unsigned char vr;
- __asm__ volatile ("move $vr,%0" : "=rm" (vr));
- return vr;
-}
-
-#define cris_machine_name "cris"
-
-/* read/write the user-mode stackpointer */
-
-static inline unsigned long rdusp(void) {
- unsigned long usp;
- __asm__ __volatile__("move $usp,%0" : "=rm" (usp));
- return usp;
-}
-
-#define wrusp(usp) \
- __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp))
-
-/* read the current stackpointer */
-
-static inline unsigned long rdsp(void) {
- unsigned long sp;
- __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp));
- return sp;
-}
-
-static inline unsigned long _get_base(char * addr)
-{
- return 0;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/thread_info.h b/arch/cris/include/arch-v10/arch/thread_info.h
deleted file mode 100644
index 0ef1223998c1..000000000000
--- a/arch/cris/include/arch-v10/arch/thread_info.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_THREAD_INFO_H
-#define _ASM_ARCH_THREAD_INFO_H
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL));
- return ti;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/timex.h b/arch/cris/include/arch-v10/arch/timex.h
deleted file mode 100644
index 9c9583e5aed6..000000000000
--- a/arch/cris/include/arch-v10/arch/timex.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Use prescale timer at 25000 Hz instead of the baudrate timer at
- * 19200 to get rid of the 64ppm to fast timer (and we get better
- * resolution within a jiffie as well.
- */
-#ifndef _ASM_CRIS_ARCH_TIMEX_H
-#define _ASM_CRIS_ARCH_TIMEX_H
-
-/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */
-/* If you change anything here you must check time.c as well... */
-#define PRESCALE_FREQ 25000000
-#define PRESCALE_VALUE 1000
-#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */
-/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/
-#define TIMER0_FREQ (CLOCK_TICK_RATE)
-#define TIMER0_CLKSEL flexible
-#define TIMER0_DIV (TIMER0_FREQ/(HZ))
-
-
-#define GET_JIFFIES_USEC() \
- ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV )
-
-unsigned long get_ns_in_jiffie(void);
-
-static inline unsigned long get_us_in_jiffie_highres(void)
-{
- return get_ns_in_jiffie()/1000;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/tlb.h b/arch/cris/include/arch-v10/arch/tlb.h
deleted file mode 100644
index 9f039d83f21b..000000000000
--- a/arch/cris/include/arch-v10/arch/tlb.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_TLB_H
-#define _CRIS_ARCH_TLB_H
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match.
- */
-#define NUM_TLB_ENTRIES 64
-#define NUM_PAGEID 64
-#define INVALID_PAGEID 63
-#define NO_CONTEXT -1
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/uaccess.h b/arch/cris/include/arch-v10/arch/uaccess.h
deleted file mode 100644
index 8d033c534f1f..000000000000
--- a/arch/cris/include/arch-v10/arch/uaccess.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Hans-Peter Nilsson (hp@axis.com)
- *
- */
-#ifndef _CRIS_ARCH_UACCESS_H
-#define _CRIS_ARCH_UACCESS_H
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- *
- * Note that PC at a fault is the address *after* the faulting
- * instruction.
- */
-#define __put_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- " "op" %1,[%2]\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err) \
- : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __put_user_asm_64(x, addr, err) \
- __asm__ __volatile__( \
- " move.d %M1,[%2]\n" \
- "2: move.d %H1,[%2+4]\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 4b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err) \
- : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-/* See comment before __put_user_asm. */
-
-#define __get_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- " "op" [%2],%1\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " moveq 0,%1\n" \
- " jump 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x) \
- : "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __get_user_asm_64(x, addr, err) \
- __asm__ __volatile__( \
- " move.d [%2],%M1\n" \
- "2: move.d [%2+4],%H1\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " moveq 0,%1\n" \
- " jump 4b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x) \
- : "r" (addr), "g" (-EFAULT), "0" (err))
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT for an exception
- * count if we hit the buffer limit
- * bytes copied if we hit a null byte
- * (without the null byte)
- */
-static inline long
-__do_strncpy_from_user(char *dst, const char *src, long count)
-{
- long res;
-
- if (count == 0)
- return 0;
-
- /*
- * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
- * So do we.
- *
- * This code is deduced from:
- *
- * char tmp2;
- * long tmp1, tmp3
- * tmp1 = count;
- * while ((*dst++ = (tmp2 = *src++)) != 0
- * && --tmp1)
- * ;
- *
- * res = count - tmp1;
- *
- * with tweaks.
- */
-
- __asm__ __volatile__ (
- " move.d %3,%0\n"
- " move.b [%2+],$r9\n"
- "1: beq 2f\n"
- " move.b $r9,[%1+]\n"
-
- " subq 1,%0\n"
- " bne 1b\n"
- " move.b [%2+],$r9\n"
-
- "2: sub.d %3,%0\n"
- " neg.d %0,%0\n"
- "3:\n"
- " .section .fixup,\"ax\"\n"
- "4: move.d %7,%0\n"
- " jump 3b\n"
-
- /* There's one address for a fault at the first move, and
- two possible PC values for a fault at the second move,
- being a delay-slot filler. However, the branch-target
- for the second move is the same as the first address.
- Just so you don't get confused... */
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 1b,4b\n"
- " .dword 2b,4b\n"
- " .previous"
- : "=r" (res), "=r" (dst), "=r" (src), "=r" (count)
- : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
- : "r9");
-
- return res;
-}
-
-/* A few copy asms to build up the more complex ones from.
-
- Note again, a post-increment is performed regardless of whether a bus
- fault occurred in that instruction, and PC for a faulted insn is the
- address *after* the insn. */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- COPY \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " jump 1b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous\n" \
- : "=r" (to), "=r" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "r9", "memory")
-
-#define __asm_copy_from_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "2: move.b $r9,[%0+]\n", \
- "3: addq 1,%2\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "2: move.w $r9,[%0+]\n" COPY, \
- "3: addq 2,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_2(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "4: move.b $r9,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "2: move.d $r9,[%0+]\n" COPY, \
- "3: addq 4,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_4(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_5(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "4: move.b $r9,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "4: move.w $r9,[%0+]\n" COPY, \
- "5: addq 2,%2\n" \
- FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_from_user_6(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_7(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "6: move.b $r9,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "4: move.d $r9,[%0+]\n" COPY, \
- "5: addq 4,%2\n" \
- FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_from_user_8(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_9(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "6: move.b $r9,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "6: move.w $r9,[%0+]\n" COPY, \
- "7: addq 2,%2\n" \
- FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_from_user_10(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_11(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "8: move.b $r9,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "6: move.d $r9,[%0+]\n" COPY, \
- "7: addq 4,%2\n" \
- FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_from_user_12(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_13(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "8: move.b $r9,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "8: move.w $r9,[%0+]\n" COPY, \
- "9: addq 2,%2\n" \
- FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_from_user_14(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_15(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "10: move.b $r9,[%0+]\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "8: move.d $r9,[%0+]\n" COPY, \
- "9: addq 4,%2\n" \
- FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_from_user_16(to, from, ret) \
- __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_16x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "10: move.d $r9,[%0+]\n" COPY, \
- "11: addq 4,%2\n" \
- FIXUP, \
- " .dword 10b,11b\n" TENTRY)
-
-#define __asm_copy_from_user_20(to, from, ret) \
- __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_20x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "12: move.d $r9,[%0+]\n" COPY, \
- "13: addq 4,%2\n" \
- FIXUP, \
- " .dword 12b,13b\n" TENTRY)
-
-#define __asm_copy_from_user_24(to, from, ret) \
- __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
-
-/* And now, the to-user ones. */
-
-#define __asm_copy_to_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n2:\n", \
- "3: addq 1,%2\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n2:\n" COPY, \
- "3: addq 2,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_2(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n4:\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n2:\n" COPY, \
- "3: addq 4,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_4(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n4:\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n4:\n" COPY, \
- "5: addq 2,%2\n" FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_6(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n6:\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n4:\n" COPY, \
- "5: addq 4,%2\n" FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_8(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n6:\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n6:\n" COPY, \
- "7: addq 2,%2\n" FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_10(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n8:\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n6:\n" COPY, \
- "7: addq 4,%2\n" FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_12(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n8:\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n8:\n" COPY, \
- "9: addq 2,%2\n" FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_14(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n10:\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n8:\n" COPY, \
- "9: addq 4,%2\n" FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_16(to, from, ret) \
- __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_16x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n10:\n" COPY, \
- "11: addq 4,%2\n" FIXUP, \
- " .dword 10b,11b\n" TENTRY)
-
-#define __asm_copy_to_user_20(to, from, ret) \
- __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_20x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n12:\n" COPY, \
- "13: addq 4,%2\n" FIXUP, \
- " .dword 12b,13b\n" TENTRY)
-
-#define __asm_copy_to_user_24(to, from, ret) \
- __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
-
-/* Define a few clearing asms with exception handlers. */
-
-/* This frame-asm is like the __asm_copy_user_cont one, but has one less
- input. */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- CLEAR \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " jump 1b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous" \
- : "=r" (to), "=r" (ret) \
- : "0" (to), "1" (ret) \
- : "memory")
-
-#define __asm_clear_1(to, ret) \
- __asm_clear(to, ret, \
- " clear.b [%0+]\n2:\n", \
- "3: addq 1,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
- __asm_clear(to, ret, \
- " clear.w [%0+]\n2:\n", \
- "3: addq 2,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
- __asm_clear(to, ret, \
- " clear.w [%0+]\n" \
- "2: clear.b [%0+]\n3:\n", \
- "4: addq 2,%1\n" \
- "5: addq 1,%1\n", \
- " .dword 2b,4b\n" \
- " .dword 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear(to, ret, \
- " clear.d [%0+]\n2:\n" CLEAR, \
- "3: addq 4,%1\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_clear_4(to, ret) \
- __asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_4x_cont(to, ret, \
- " clear.d [%0+]\n4:\n" CLEAR, \
- "5: addq 4,%1\n" FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_clear_8(to, ret) \
- __asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_8x_cont(to, ret, \
- " clear.d [%0+]\n6:\n" CLEAR, \
- "7: addq 4,%1\n" FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_clear_12(to, ret) \
- __asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_12x_cont(to, ret, \
- " clear.d [%0+]\n8:\n" CLEAR, \
- "9: addq 4,%1\n" FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_clear_16(to, ret) \
- __asm_clear_16x_cont(to, ret, "", "", "")
-
-#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_16x_cont(to, ret, \
- " clear.d [%0+]\n10:\n" CLEAR, \
- "11: addq 4,%1\n" FIXUP, \
- " .dword 10b,11b\n" TENTRY)
-
-#define __asm_clear_20(to, ret) \
- __asm_clear_20x_cont(to, ret, "", "", "")
-
-#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_20x_cont(to, ret, \
- " clear.d [%0+]\n12:\n" CLEAR, \
- "13: addq 4,%1\n" FIXUP, \
- " .dword 12b,13b\n" TENTRY)
-
-#define __asm_clear_24(to, ret) \
- __asm_clear_24x_cont(to, ret, "", "", "")
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return length of string in userspace including terminating 0
- * or 0 for error. Return a value greater than N if too long.
- */
-
-static inline long
-strnlen_user(const char *s, long n)
-{
- long res, tmp1;
-
- if (!access_ok(VERIFY_READ, s, 0))
- return 0;
-
- /*
- * This code is deduced from:
- *
- * tmp1 = n;
- * while (tmp1-- > 0 && *s++)
- * ;
- *
- * res = n - tmp1;
- *
- * (with tweaks).
- */
-
- __asm__ __volatile__ (
- " move.d %1,$r9\n"
- "0:\n"
- " ble 1f\n"
- " subq 1,$r9\n"
-
- " test.b [%0+]\n"
- " bne 0b\n"
- " test.d $r9\n"
- "1:\n"
- " move.d %1,%0\n"
- " sub.d $r9,%0\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
-
- "3: clear.d %0\n"
- " jump 2b\n"
-
- /* There's one address for a fault at the first move, and
- two possible PC values for a fault at the second move,
- being a delay-slot filler. However, the branch-target
- for the second move is the same as the first address.
- Just so you don't get confused... */
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 0b,3b\n"
- " .dword 1b,3b\n"
- " .previous\n"
- : "=r" (res), "=r" (tmp1)
- : "0" (s), "1" (n)
- : "r9");
-
- return res;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/unistd.h b/arch/cris/include/arch-v10/arch/unistd.h
deleted file mode 100644
index 03cd0b8652f4..000000000000
--- a/arch/cris/include/arch-v10/arch/unistd.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_UNISTD_H_
-#define _ASM_CRIS_ARCH_UNISTD_H_
-
-/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
-/*
- * Don't remove the .ifnc tests; they are an insurance against
- * any hard-to-spot gcc register allocation bugs.
- */
-#define _syscall0(type,name) \
-type name(void) \
-{ \
- register long __a __asm__ ("r10"); \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall1(type,name,type1,arg1) \
-type name(type1 arg1) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2) \
-type name(type1 arg1,type2 arg2) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
-type name(type1 arg1,type2 arg2,type3 arg3) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "move %6,$mof\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "g" (arg5)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5,type6,arg6) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "move %6,$mof\n\tmove %7,$srp\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\
- : "srp"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/bitops.h b/arch/cris/include/arch-v32/arch/bitops.h
deleted file mode 100644
index 7df94798f063..000000000000
--- a/arch/cris/include/arch-v32/arch/bitops.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_BITOPS_H
-#define _ASM_CRIS_ARCH_BITOPS_H
-
-/*
- * Helper functions for the core of the ff[sz] functions. They compute the
- * number of leading zeroes of a bits-in-byte, byte-in-word and
- * word-in-dword-swapped number. They differ in that the first function also
- * inverts all bits in the input.
- */
-
-static inline unsigned long
-cris_swapnwbrlz(unsigned long w)
-{
- unsigned long res;
-
- __asm__ __volatile__ ("swapnwbr %0\n\t"
- "lz %0,%0"
- : "=r" (res) : "0" (w));
-
- return res;
-}
-
-static inline unsigned long
-cris_swapwbrlz(unsigned long w)
-{
- unsigned long res;
-
- __asm__ __volatile__ ("swapwbr %0\n\t"
- "lz %0,%0"
- : "=r" (res) : "0" (w));
-
- return res;
-}
-
-/*
- * Find First Zero in word. Undefined if no zero exist, so the caller should
- * check against ~0 first.
- */
-static inline unsigned long
-ffz(unsigned long w)
-{
- return cris_swapnwbrlz(w);
-}
-
-/*
- * Find First Set bit in word. Undefined if no 1 exist, so the caller
- * should check against 0 first.
- */
-static inline unsigned long
-__ffs(unsigned long w)
-{
- return cris_swapnwbrlz(~w);
-}
-
-/*
- * Find First Bit that is set.
- */
-static inline unsigned long
-kernel_ffs(unsigned long w)
-{
- return w ? cris_swapwbrlz (w) + 1 : 0;
-}
-
-#endif /* _ASM_CRIS_ARCH_BITOPS_H */
diff --git a/arch/cris/include/arch-v32/arch/bug.h b/arch/cris/include/arch-v32/arch/bug.h
deleted file mode 100644
index 982c6b08fdf1..000000000000
--- a/arch/cris/include/arch-v32/arch/bug.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRISv32_ARCH_BUG_H
-#define __ASM_CRISv32_ARCH_BUG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_BUG
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-/*
- * The penalty for the in-band code path will be the size of break 14.
- * All other stuff is done out-of-band with exception handlers.
- */
-#define BUG() \
-do { \
- __asm__ __volatile__ ("0: break 14\n\t" \
- ".section .fixup,\"ax\"\n" \
- "1:\n\t" \
- "move.d %0, $r10\n\t" \
- "move.d %1, $r11\n\t" \
- "jump do_BUG\n\t" \
- "nop\n\t" \
- ".previous\n\t" \
- ".section __ex_table,\"a\"\n\t" \
- ".dword 0b, 1b\n\t" \
- ".previous\n\t" \
- : : "ri" (__FILE__), "i" (__LINE__)); \
- unreachable(); \
-} while (0)
-#else
-#define BUG() \
-do { \
- __asm__ __volatile__ ("break 14\n\t"); \
- unreachable(); \
-} while (0)
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-#endif
diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h
deleted file mode 100644
index f61f3088c45b..000000000000
--- a/arch/cris/include/arch-v32/arch/cache.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_CACHE_H
-#define _ASM_CRIS_ARCH_CACHE_H
-
-#include <arch/hwregs/dma.h>
-
-/* A cache-line is 32 bytes. */
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-
-void flush_dma_list(dma_descr_data *descr);
-void flush_dma_descr(dma_descr_data *descr, int flush_buf);
-
-#define flush_dma_context(c) \
- flush_dma_list(phys_to_virt((c)->saved_data));
-
-void cris_flush_cache_range(void *buf, unsigned long len);
-void cris_flush_cache(void);
-
-#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/arch/cris/include/arch-v32/arch/checksum.h b/arch/cris/include/arch-v32/arch/checksum.h
deleted file mode 100644
index fea1341ef244..000000000000
--- a/arch/cris/include/arch-v32/arch/checksum.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
-#define _ASM_CRIS_ARCH_CHECKSUM_H
-
-/*
- * Check values used in TCP/UDP headers.
- *
- * The gain of doing this in assembler instead of C, is that C doesn't
- * generate carry-additions for the 32-bit components of the
- * checksum. Which means it would be necessary to split all those into
- * 16-bit components and then add.
- */
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto, __wsum sum)
-{
- __wsum res;
-
- __asm__ __volatile__ ("add.d %2, %0\n\t"
- "addc %3, %0\n\t"
- "addc %4, %0\n\t"
- "addc 0, %0\n\t"
- : "=r" (res)
- : "0" (sum), "r" (daddr), "r" (saddr), \
- "r" ((len + proto) << 8));
-
- return res;
-}
-
-#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */
diff --git a/arch/cris/include/arch-v32/arch/cryptocop.h b/arch/cris/include/arch-v32/arch/cryptocop.h
deleted file mode 100644
index f2f8eda1ffb1..000000000000
--- a/arch/cris/include/arch-v32/arch/cryptocop.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * The device /dev/cryptocop is accessible using this driver using
- * CRYPTOCOP_MAJOR (254) and minor number 0.
- */
-#ifndef CRYPTOCOP_H
-#define CRYPTOCOP_H
-
-#include <uapi/arch-v32/arch/cryptocop.h>
-
-
-/********** The API to use from inside the kernel. ************/
-
-#include <arch/hwregs/dma.h>
-
-typedef enum {
- cryptocop_alg_csum = 0,
- cryptocop_alg_mem2mem,
- cryptocop_alg_md5,
- cryptocop_alg_sha1,
- cryptocop_alg_des,
- cryptocop_alg_3des,
- cryptocop_alg_aes,
- cryptocop_no_alg,
-} cryptocop_algorithm;
-
-typedef u8 cryptocop_tfrm_id;
-
-
-struct cryptocop_operation;
-
-typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
-
-struct cryptocop_transform_init {
- cryptocop_algorithm alg;
- /* Keydata for ciphers. */
- unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH];
- unsigned int keylen;
- cryptocop_cipher_mode cipher_mode;
- cryptocop_3des_mode tdes_mode;
- cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
-
- cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
- struct cryptocop_transform_init *next;
-};
-
-
-typedef enum {
- cryptocop_source_dma = 0,
- cryptocop_source_des,
- cryptocop_source_3des,
- cryptocop_source_aes,
- cryptocop_source_md5,
- cryptocop_source_sha1,
- cryptocop_source_csum,
- cryptocop_source_none,
-} cryptocop_source;
-
-
-struct cryptocop_desc_cfg {
- cryptocop_tfrm_id tid;
- cryptocop_source src;
- unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */
- struct cryptocop_desc_cfg *next;
-};
-
-struct cryptocop_desc {
- size_t length;
- struct cryptocop_desc_cfg *cfg;
- struct cryptocop_desc *next;
-};
-
-
-/* Flags for cryptocop_tfrm_cfg */
-#define CRYPTOCOP_NO_FLAG (0x00)
-#define CRYPTOCOP_ENCRYPT (0x01)
-#define CRYPTOCOP_DECRYPT (0x02)
-#define CRYPTOCOP_EXPLICIT_IV (0x04)
-
-struct cryptocop_tfrm_cfg {
- cryptocop_tfrm_id tid;
-
- unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
-
- /* CBC initialisation vector for ciphers. */
- u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
-
- /* The position in output where to write the transform output. The order
- in which the driver writes the output is unspecified, hence if several
- transforms write on the same positions in the output the result is
- unspecified. */
- size_t inject_ix;
-
- struct cryptocop_tfrm_cfg *next;
-};
-
-
-
-struct cryptocop_dma_list_operation{
- /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in
- struct cryptocop_operation must be set for the driver to use them. outlist,
- out_data_buf, inlist and in_data_buf must all be physical addresses since they will
- be loaded to DMA . */
- dma_descr_data *outlist; /* Out from memory to the co-processor. */
- char *out_data_buf;
- dma_descr_data *inlist; /* In from the co-processor to memory. */
- char *in_data_buf;
-
- cryptocop_3des_mode tdes_mode;
- cryptocop_csum_type csum_mode;
-};
-
-
-struct cryptocop_tfrm_operation{
- /* Operation configuration, if not 'use_dmalists' is set. */
- struct cryptocop_tfrm_cfg *tfrm_cfg;
- struct cryptocop_desc *desc;
-
- struct iovec *indata;
- size_t incount;
- size_t inlen; /* Total inlength. */
-
- struct iovec *outdata;
- size_t outcount;
- size_t outlen; /* Total outlength. */
-};
-
-
-struct cryptocop_operation {
- cryptocop_callback *cb;
- void *cb_data;
-
- cryptocop_session_id sid;
-
- /* The status of the operation when returned to consumer. */
- int operation_status; /* 0, -EAGAIN */
-
- /* Flags */
- unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
- unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */
- unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
-
- union{
- struct cryptocop_dma_list_operation list_op;
- struct cryptocop_tfrm_operation tfrm_op;
- };
-};
-
-
-int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
-int cryptocop_free_session(cryptocop_session_id sid);
-
-int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
-
-int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
-
-int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
-
-#endif /* CRYPTOCOP_H */
diff --git a/arch/cris/include/arch-v32/arch/delay.h b/arch/cris/include/arch-v32/arch/delay.h
deleted file mode 100644
index 94307c1fbb1c..000000000000
--- a/arch/cris/include/arch-v32/arch/delay.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_DELAY_H
-#define _ASM_CRIS_ARCH_DELAY_H
-
-extern void cris_delay10ns(u32 n10ns);
-#define udelay(u) cris_delay10ns((u)*100)
-#define ndelay(n) cris_delay10ns(((n)+9)/10)
-
-/*
- * Not used anymore for udelay or ndelay. Referenced by
- * e.g. init/calibrate.c. All other references are likely bugs;
- * should be replaced by mdelay, udelay or ndelay.
- */
-
-static inline void
-__delay(int loops)
-{
- __asm__ __volatile__ (
- "move.d %0, $r9\n\t"
- "beq 2f\n\t"
- "subq 1, $r9\n\t"
- "1:\n\t"
- "bne 1b\n\t"
- "subq 1, $r9\n"
- "2:"
- : : "g" (loops) : "r9");
-}
-
-#endif /* _ASM_CRIS_ARCH_DELAY_H */
diff --git a/arch/cris/include/arch-v32/arch/dma.h b/arch/cris/include/arch-v32/arch/dma.h
deleted file mode 100644
index 6f92f4f23f28..000000000000
--- a/arch/cris/include/arch-v32/arch/dma.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach/dma.h>
diff --git a/arch/cris/include/arch-v32/arch/hwregs/Makefile b/arch/cris/include/arch-v32/arch/hwregs/Makefile
deleted file mode 100644
index bb5ffa7ff9f4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/Makefile
+++ /dev/null
@@ -1,187 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# Makefile to generate or copy the latest register definitions
-# and related datastructures and helpermacros.
-# The official place for these files is at:
-RELEASE ?= r1_alfa5
-OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
-
-# which is updated on each new release.
-INCL_ASMFILES =
-INCL_FILES = ata_defs.h
-INCL_FILES += bif_core_defs.h
-INCL_ASMFILES += bif_core_defs_asm.h
-INCL_FILES += bif_slave_defs.h
-#INCL_FILES += bif_slave_ext_defs.h
-INCL_FILES += config_defs.h
-INCL_ASMFILES += config_defs_asm.h
-INCL_FILES += cpu_vect.h
-#INCL_FILES += cris_defs.h
-#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h
-INCL_FILES += dma.h
-INCL_FILES += dma_defs.h
-INCL_FILES += eth_defs.h
-INCL_FILES += extmem_defs.h
-INCL_FILES += gio_defs.h
-INCL_ASMFILES += gio_defs_asm.h
-INCL_FILES += intr_vect.h
-INCL_FILES += intr_vect_defs.h
-INCL_ASMFILES += intr_vect_defs_asm.h
-INCL_FILES += marb_bp_defs.h
-INCL_FILES += marb_defs.h
-INCL_ASMFILES += mmu_defs_asm.h
-#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h
-#INCL_FILES += par_defs.h # No useful content
-INCL_FILES += pinmux_defs.h
-INCL_FILES += reg_map.h
-INCL_ASMFILES += reg_map_asm.h
-INCL_FILES += reg_rdwr.h
-INCL_FILES += ser_defs.h
-#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h
-INCL_FILES += sser_defs.h
-INCL_FILES += strcop_defs.h
-#INCL_FILES += strcop.h # Where is this?
-INCL_FILES += strmux_defs.h
-#INCL_FILES += supp_reg.h # Handcrafted instead
-INCL_FILES += timer_defs.h
-
-REGDESC =
-REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
-REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
-REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
-#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
-REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
-REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
-REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
-REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
-REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
-REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
-REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
-#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
-REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
-REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
-REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
-REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
-REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
-#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
-
-
-BASEDIR = /n/asic/design
-DESIGNDIR = /n/asic/projects/guinness/design
-RDES2C = /n/asic/bin/rdes2c
-RDES2C = /n/asic/design/tools/rdesc/rdes2c
-RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
-RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
-
-## all - Just print help - you probably want to do 'make gen'
-all: help
-
-# Disable implicit rule that may generate deleted files from RCS/ directory.
-%.r:
-
-%.h:
-
-## help - This help
-help:
- @grep '^## ' Makefile
-
-## gen - Generate include files
-gen: $(INCL_FILES) $(INCL_ASMFILES)
-
-ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
- $(RDES2C) $<
-config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
- $(RDES2C) $<
-config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
- $(RDES2C) -asm $<
-# Can't generate cpu_vect.h yet
-#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
-# $(RDES2INTR) $<
-cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
- $(RDES2C) $<
-$(BASEDIR)/core/dma/sw/dma.h:
-dma.h: $(BASEDIR)/core/dma/sw/dma.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
- $(RDES2C) $<
-extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
- $(RDES2C) $<
-gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
- $(RDES2C) $<
-intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
- $(RDES2C) $<
-intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
- $(RDES2C) -asm $<
-# Can't generate intr_vect.h yet
-#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-# $(RDES2INTR) $<
-intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
- $(RDES2C) -asm $<
-par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
- $(RDES2C) $<
-
-# From /n/asic/projects/guinness/design/
-reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
- $(RDES2C) -base 0xb0000000 $^
-reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
- $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
-
-reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-
-ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
- $(RDES2C) $<
-strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
- $(RDES2C) $<
-strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
- $(RDES2C) $<
-timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
- $(RDES2C) $<
-usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
- $(RDES2C) $<
-
-## copy - Copy files from official location
-copy:
- @for HFILE in $(INCL_FILES); do \
- echo " $$HFILE"; \
- cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
- @for HFILE in $(INCL_ASMFILES); do \
- echo " $$HFILE"; \
- cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
-## ls_official - List official location
-ls_official:
- (cd $(OFFICIAL_INCDIR); ls -l *.h )
-
-## diff_official - Diff current directory with official location
-diff_official:
- diff . $(OFFICIAL_INCDIR)
-
-## doc - Generate .axw files from register description.
-doc: $(REGDESC)
- for RDES in $^; do \
- $(RDES2TXT) $$RDES; \
- done
-
-.PHONY: axw
-## %.axw - Generate the specified .axw file (doesn't work for all files
-## due to inconsistent naming ir .r files.
-%.axw: axw
- @for RDES in $(REGDESC); do \
- if echo "$$RDES" | grep $* ; then \
- $(RDES2TXT) $$RDES; \
- fi \
- done
-
-.PHONY: clean
-## clean - Remove .h files and .axw files.
-clean:
- rm -rf $(INCL_FILES) *.axw
-
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h
deleted file mode 100644
index 6886ba3c2d53..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ata_defs_asm_h
-#define __ata_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ata/rtl/ata_regs.r
- * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
- * last modfied: Mon Apr 11 16:06:25 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
- * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ctrl0, scope ata, type rw */
-#define reg_ata_rw_ctrl0___pio_hold___lsb 0
-#define reg_ata_rw_ctrl0___pio_hold___width 6
-#define reg_ata_rw_ctrl0___pio_strb___lsb 6
-#define reg_ata_rw_ctrl0___pio_strb___width 6
-#define reg_ata_rw_ctrl0___pio_setup___lsb 12
-#define reg_ata_rw_ctrl0___pio_setup___width 6
-#define reg_ata_rw_ctrl0___dma_hold___lsb 18
-#define reg_ata_rw_ctrl0___dma_hold___width 6
-#define reg_ata_rw_ctrl0___dma_strb___lsb 24
-#define reg_ata_rw_ctrl0___dma_strb___width 6
-#define reg_ata_rw_ctrl0___rst___lsb 30
-#define reg_ata_rw_ctrl0___rst___width 1
-#define reg_ata_rw_ctrl0___rst___bit 30
-#define reg_ata_rw_ctrl0___en___lsb 31
-#define reg_ata_rw_ctrl0___en___width 1
-#define reg_ata_rw_ctrl0___en___bit 31
-#define reg_ata_rw_ctrl0_offset 12
-
-/* Register rw_ctrl1, scope ata, type rw */
-#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
-#define reg_ata_rw_ctrl1___udma_tcyc___width 4
-#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
-#define reg_ata_rw_ctrl1___udma_tdvs___width 4
-#define reg_ata_rw_ctrl1_offset 16
-
-/* Register rw_ctrl2, scope ata, type rw */
-#define reg_ata_rw_ctrl2___data___lsb 0
-#define reg_ata_rw_ctrl2___data___width 16
-#define reg_ata_rw_ctrl2___dma_size___lsb 19
-#define reg_ata_rw_ctrl2___dma_size___width 1
-#define reg_ata_rw_ctrl2___dma_size___bit 19
-#define reg_ata_rw_ctrl2___multi___lsb 20
-#define reg_ata_rw_ctrl2___multi___width 1
-#define reg_ata_rw_ctrl2___multi___bit 20
-#define reg_ata_rw_ctrl2___hsh___lsb 21
-#define reg_ata_rw_ctrl2___hsh___width 2
-#define reg_ata_rw_ctrl2___trf_mode___lsb 23
-#define reg_ata_rw_ctrl2___trf_mode___width 1
-#define reg_ata_rw_ctrl2___trf_mode___bit 23
-#define reg_ata_rw_ctrl2___rw___lsb 24
-#define reg_ata_rw_ctrl2___rw___width 1
-#define reg_ata_rw_ctrl2___rw___bit 24
-#define reg_ata_rw_ctrl2___addr___lsb 25
-#define reg_ata_rw_ctrl2___addr___width 3
-#define reg_ata_rw_ctrl2___cs0___lsb 28
-#define reg_ata_rw_ctrl2___cs0___width 1
-#define reg_ata_rw_ctrl2___cs0___bit 28
-#define reg_ata_rw_ctrl2___cs1___lsb 29
-#define reg_ata_rw_ctrl2___cs1___width 1
-#define reg_ata_rw_ctrl2___cs1___bit 29
-#define reg_ata_rw_ctrl2___sel___lsb 30
-#define reg_ata_rw_ctrl2___sel___width 2
-#define reg_ata_rw_ctrl2_offset 0
-
-/* Register rs_stat_data, scope ata, type rs */
-#define reg_ata_rs_stat_data___data___lsb 0
-#define reg_ata_rs_stat_data___data___width 16
-#define reg_ata_rs_stat_data___dav___lsb 16
-#define reg_ata_rs_stat_data___dav___width 1
-#define reg_ata_rs_stat_data___dav___bit 16
-#define reg_ata_rs_stat_data___busy___lsb 17
-#define reg_ata_rs_stat_data___busy___width 1
-#define reg_ata_rs_stat_data___busy___bit 17
-#define reg_ata_rs_stat_data_offset 4
-
-/* Register r_stat_data, scope ata, type r */
-#define reg_ata_r_stat_data___data___lsb 0
-#define reg_ata_r_stat_data___data___width 16
-#define reg_ata_r_stat_data___dav___lsb 16
-#define reg_ata_r_stat_data___dav___width 1
-#define reg_ata_r_stat_data___dav___bit 16
-#define reg_ata_r_stat_data___busy___lsb 17
-#define reg_ata_r_stat_data___busy___width 1
-#define reg_ata_r_stat_data___busy___bit 17
-#define reg_ata_r_stat_data_offset 8
-
-/* Register rw_trf_cnt, scope ata, type rw */
-#define reg_ata_rw_trf_cnt___cnt___lsb 0
-#define reg_ata_rw_trf_cnt___cnt___width 17
-#define reg_ata_rw_trf_cnt_offset 20
-
-/* Register r_stat_misc, scope ata, type r */
-#define reg_ata_r_stat_misc___crc___lsb 0
-#define reg_ata_r_stat_misc___crc___width 16
-#define reg_ata_r_stat_misc_offset 24
-
-/* Register rw_intr_mask, scope ata, type rw */
-#define reg_ata_rw_intr_mask___bus0___lsb 0
-#define reg_ata_rw_intr_mask___bus0___width 1
-#define reg_ata_rw_intr_mask___bus0___bit 0
-#define reg_ata_rw_intr_mask___bus1___lsb 1
-#define reg_ata_rw_intr_mask___bus1___width 1
-#define reg_ata_rw_intr_mask___bus1___bit 1
-#define reg_ata_rw_intr_mask___bus2___lsb 2
-#define reg_ata_rw_intr_mask___bus2___width 1
-#define reg_ata_rw_intr_mask___bus2___bit 2
-#define reg_ata_rw_intr_mask___bus3___lsb 3
-#define reg_ata_rw_intr_mask___bus3___width 1
-#define reg_ata_rw_intr_mask___bus3___bit 3
-#define reg_ata_rw_intr_mask_offset 28
-
-/* Register rw_ack_intr, scope ata, type rw */
-#define reg_ata_rw_ack_intr___bus0___lsb 0
-#define reg_ata_rw_ack_intr___bus0___width 1
-#define reg_ata_rw_ack_intr___bus0___bit 0
-#define reg_ata_rw_ack_intr___bus1___lsb 1
-#define reg_ata_rw_ack_intr___bus1___width 1
-#define reg_ata_rw_ack_intr___bus1___bit 1
-#define reg_ata_rw_ack_intr___bus2___lsb 2
-#define reg_ata_rw_ack_intr___bus2___width 1
-#define reg_ata_rw_ack_intr___bus2___bit 2
-#define reg_ata_rw_ack_intr___bus3___lsb 3
-#define reg_ata_rw_ack_intr___bus3___width 1
-#define reg_ata_rw_ack_intr___bus3___bit 3
-#define reg_ata_rw_ack_intr_offset 32
-
-/* Register r_intr, scope ata, type r */
-#define reg_ata_r_intr___bus0___lsb 0
-#define reg_ata_r_intr___bus0___width 1
-#define reg_ata_r_intr___bus0___bit 0
-#define reg_ata_r_intr___bus1___lsb 1
-#define reg_ata_r_intr___bus1___width 1
-#define reg_ata_r_intr___bus1___bit 1
-#define reg_ata_r_intr___bus2___lsb 2
-#define reg_ata_r_intr___bus2___width 1
-#define reg_ata_r_intr___bus2___bit 2
-#define reg_ata_r_intr___bus3___lsb 3
-#define reg_ata_r_intr___bus3___width 1
-#define reg_ata_r_intr___bus3___bit 3
-#define reg_ata_r_intr_offset 36
-
-/* Register r_masked_intr, scope ata, type r */
-#define reg_ata_r_masked_intr___bus0___lsb 0
-#define reg_ata_r_masked_intr___bus0___width 1
-#define reg_ata_r_masked_intr___bus0___bit 0
-#define reg_ata_r_masked_intr___bus1___lsb 1
-#define reg_ata_r_masked_intr___bus1___width 1
-#define reg_ata_r_masked_intr___bus1___bit 1
-#define reg_ata_r_masked_intr___bus2___lsb 2
-#define reg_ata_r_masked_intr___bus2___width 1
-#define reg_ata_r_masked_intr___bus2___bit 2
-#define reg_ata_r_masked_intr___bus3___lsb 3
-#define reg_ata_r_masked_intr___bus3___width 1
-#define reg_ata_r_masked_intr___bus3___bit 3
-#define reg_ata_r_masked_intr_offset 40
-
-
-/* Constants */
-#define regk_ata_active 0x00000001
-#define regk_ata_byte 0x00000001
-#define regk_ata_data 0x00000001
-#define regk_ata_dma 0x00000001
-#define regk_ata_inactive 0x00000000
-#define regk_ata_no 0x00000000
-#define regk_ata_nodata 0x00000000
-#define regk_ata_pio 0x00000000
-#define regk_ata_rd 0x00000001
-#define regk_ata_reg 0x00000000
-#define regk_ata_rw_ctrl0_default 0x00000000
-#define regk_ata_rw_ctrl2_default 0x00000000
-#define regk_ata_rw_intr_mask_default 0x00000000
-#define regk_ata_udma 0x00000002
-#define regk_ata_word 0x00000000
-#define regk_ata_wr 0x00000000
-#define regk_ata_yes 0x00000001
-#endif /* __ata_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h
deleted file mode 100644
index 1d75d8c31cc0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_asm_h
-#define __bif_core_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp1_cfg___lw___width 6
-#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp1_cfg___ew___width 3
-#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp1_cfg___zw___width 3
-#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp1_cfg___aw___width 2
-#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp1_cfg___dw___width 2
-#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp1_cfg___ewb___width 2
-#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp1_cfg___bw___width 1
-#define reg_bif_core_rw_grp1_cfg___bw___bit 18
-#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp1_cfg___mode___width 1
-#define reg_bif_core_rw_grp1_cfg___mode___bit 21
-#define reg_bif_core_rw_grp1_cfg_offset 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp2_cfg___lw___width 6
-#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp2_cfg___ew___width 3
-#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp2_cfg___zw___width 3
-#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp2_cfg___aw___width 2
-#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp2_cfg___dw___width 2
-#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp2_cfg___ewb___width 2
-#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp2_cfg___bw___width 1
-#define reg_bif_core_rw_grp2_cfg___bw___bit 18
-#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp2_cfg___mode___width 1
-#define reg_bif_core_rw_grp2_cfg___mode___bit 21
-#define reg_bif_core_rw_grp2_cfg_offset 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp3_cfg___lw___width 6
-#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp3_cfg___ew___width 3
-#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp3_cfg___zw___width 3
-#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp3_cfg___aw___width 2
-#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp3_cfg___dw___width 2
-#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp3_cfg___ewb___width 2
-#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp3_cfg___bw___width 1
-#define reg_bif_core_rw_grp3_cfg___bw___bit 18
-#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp3_cfg___mode___width 1
-#define reg_bif_core_rw_grp3_cfg___mode___bit 21
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
-#define reg_bif_core_rw_grp3_cfg_offset 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp4_cfg___lw___width 6
-#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp4_cfg___ew___width 3
-#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp4_cfg___zw___width 3
-#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp4_cfg___aw___width 2
-#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp4_cfg___dw___width 2
-#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp4_cfg___ewb___width 2
-#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp4_cfg___bw___width 1
-#define reg_bif_core_rw_grp4_cfg___bw___bit 18
-#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp4_cfg___mode___width 1
-#define reg_bif_core_rw_grp4_cfg___mode___bit 21
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
-#define reg_bif_core_rw_grp4_cfg_offset 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_timing___cl___lsb 0
-#define reg_bif_core_rw_sdram_timing___cl___width 3
-#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
-#define reg_bif_core_rw_sdram_timing___rcd___width 3
-#define reg_bif_core_rw_sdram_timing___rp___lsb 6
-#define reg_bif_core_rw_sdram_timing___rp___width 3
-#define reg_bif_core_rw_sdram_timing___rc___lsb 9
-#define reg_bif_core_rw_sdram_timing___rc___width 2
-#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
-#define reg_bif_core_rw_sdram_timing___dpl___width 2
-#define reg_bif_core_rw_sdram_timing___pde___lsb 13
-#define reg_bif_core_rw_sdram_timing___pde___width 1
-#define reg_bif_core_rw_sdram_timing___pde___bit 13
-#define reg_bif_core_rw_sdram_timing___ref___lsb 14
-#define reg_bif_core_rw_sdram_timing___ref___width 2
-#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
-#define reg_bif_core_rw_sdram_timing___cpd___width 1
-#define reg_bif_core_rw_sdram_timing___cpd___bit 16
-#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
-#define reg_bif_core_rw_sdram_timing___sdcke___width 1
-#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
-#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
-#define reg_bif_core_rw_sdram_timing___sdclk___width 1
-#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
-#define reg_bif_core_rw_sdram_timing_offset 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
-#define reg_bif_core_rw_sdram_cmd___cmd___width 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
-#define reg_bif_core_rw_sdram_cmd_offset 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
-#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_rs_sdram_ref_stat_offset 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_r_sdram_ref_stat___ok___width 1
-#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_r_sdram_ref_stat_offset 36
-
-
-/* Constants */
-#define regk_bif_core_bank2 0x00000000
-#define regk_bif_core_bank4 0x00000001
-#define regk_bif_core_bit10 0x0000000a
-#define regk_bif_core_bit11 0x0000000b
-#define regk_bif_core_bit12 0x0000000c
-#define regk_bif_core_bit13 0x0000000d
-#define regk_bif_core_bit14 0x0000000e
-#define regk_bif_core_bit15 0x0000000f
-#define regk_bif_core_bit16 0x00000010
-#define regk_bif_core_bit17 0x00000011
-#define regk_bif_core_bit18 0x00000012
-#define regk_bif_core_bit19 0x00000013
-#define regk_bif_core_bit20 0x00000014
-#define regk_bif_core_bit21 0x00000015
-#define regk_bif_core_bit22 0x00000016
-#define regk_bif_core_bit23 0x00000017
-#define regk_bif_core_bit24 0x00000018
-#define regk_bif_core_bit25 0x00000019
-#define regk_bif_core_bit26 0x0000001a
-#define regk_bif_core_bit27 0x0000001b
-#define regk_bif_core_bit28 0x0000001c
-#define regk_bif_core_bit29 0x0000001d
-#define regk_bif_core_bit9 0x00000009
-#define regk_bif_core_bw16 0x00000001
-#define regk_bif_core_bw32 0x00000000
-#define regk_bif_core_bwe 0x00000000
-#define regk_bif_core_cwe 0x00000001
-#define regk_bif_core_e15us 0x00000001
-#define regk_bif_core_e7800ns 0x00000002
-#define regk_bif_core_grp0 0x00000000
-#define regk_bif_core_grp1 0x00000001
-#define regk_bif_core_mrs 0x00000003
-#define regk_bif_core_no 0x00000000
-#define regk_bif_core_none 0x00000000
-#define regk_bif_core_nop 0x00000000
-#define regk_bif_core_off 0x00000000
-#define regk_bif_core_pre 0x00000002
-#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rd 0x00000002
-#define regk_bif_core_ref 0x00000001
-#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
-#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
-#define regk_bif_core_slf 0x00000004
-#define regk_bif_core_wr 0x00000001
-#define regk_bif_core_yes 0x00000001
-#endif /* __bif_core_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h
deleted file mode 100644
index a07447fa75f8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h
+++ /dev/null
@@ -1,496 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_dma_defs_asm_h
-#define __bif_dma_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_dma_regs.r
- * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
- * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
-#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
-#define reg_bif_dma_rw_ch0_ctrl_offset 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch0_addr___addr___width 32
-#define reg_bif_dma_rw_ch0_addr_offset 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_start___run___lsb 0
-#define reg_bif_dma_rw_ch0_start___run___width 1
-#define reg_bif_dma_rw_ch0_start___run___bit 0
-#define reg_bif_dma_rw_ch0_start_offset 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch0_cnt_offset 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch0_stat___cnt___width 16
-#define reg_bif_dma_r_ch0_stat___run___lsb 31
-#define reg_bif_dma_r_ch0_stat___run___width 1
-#define reg_bif_dma_r_ch0_stat___run___bit 31
-#define reg_bif_dma_r_ch0_stat_offset 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
-#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch1_ctrl_offset 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch1_addr___addr___width 32
-#define reg_bif_dma_rw_ch1_addr_offset 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_start___run___lsb 0
-#define reg_bif_dma_rw_ch1_start___run___width 1
-#define reg_bif_dma_rw_ch1_start___run___bit 0
-#define reg_bif_dma_rw_ch1_start_offset 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch1_cnt_offset 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch1_stat___cnt___width 16
-#define reg_bif_dma_r_ch1_stat___run___lsb 31
-#define reg_bif_dma_r_ch1_stat___run___width 1
-#define reg_bif_dma_r_ch1_stat___run___bit 31
-#define reg_bif_dma_r_ch1_stat_offset 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
-#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
-#define reg_bif_dma_rw_ch2_ctrl_offset 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch2_addr___addr___width 32
-#define reg_bif_dma_rw_ch2_addr_offset 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_start___run___lsb 0
-#define reg_bif_dma_rw_ch2_start___run___width 1
-#define reg_bif_dma_rw_ch2_start___run___bit 0
-#define reg_bif_dma_rw_ch2_start_offset 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch2_cnt_offset 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch2_stat___cnt___width 16
-#define reg_bif_dma_r_ch2_stat___run___lsb 31
-#define reg_bif_dma_r_ch2_stat___run___width 1
-#define reg_bif_dma_r_ch2_stat___run___bit 31
-#define reg_bif_dma_r_ch2_stat_offset 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
-#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch3_ctrl_offset 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch3_addr___addr___width 32
-#define reg_bif_dma_rw_ch3_addr_offset 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_start___run___lsb 0
-#define reg_bif_dma_rw_ch3_start___run___width 1
-#define reg_bif_dma_rw_ch3_start___run___bit 0
-#define reg_bif_dma_rw_ch3_start_offset 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch3_cnt_offset 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch3_stat___cnt___width 16
-#define reg_bif_dma_r_ch3_stat___run___lsb 31
-#define reg_bif_dma_r_ch3_stat___run___width 1
-#define reg_bif_dma_r_ch3_stat___run___bit 31
-#define reg_bif_dma_r_ch3_stat_offset 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
-#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
-#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
-#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
-#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
-#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
-#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
-#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
-#define reg_bif_dma_rw_intr_mask_offset 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
-#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
-#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
-#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
-#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
-#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
-#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
-#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
-#define reg_bif_dma_rw_ack_intr_offset 132
-
-/* Register r_intr, scope bif_dma, type r */
-#define reg_bif_dma_r_intr___ext_dma0___lsb 0
-#define reg_bif_dma_r_intr___ext_dma0___width 1
-#define reg_bif_dma_r_intr___ext_dma0___bit 0
-#define reg_bif_dma_r_intr___ext_dma1___lsb 1
-#define reg_bif_dma_r_intr___ext_dma1___width 1
-#define reg_bif_dma_r_intr___ext_dma1___bit 1
-#define reg_bif_dma_r_intr___ext_dma2___lsb 2
-#define reg_bif_dma_r_intr___ext_dma2___width 1
-#define reg_bif_dma_r_intr___ext_dma2___bit 2
-#define reg_bif_dma_r_intr___ext_dma3___lsb 3
-#define reg_bif_dma_r_intr___ext_dma3___width 1
-#define reg_bif_dma_r_intr___ext_dma3___bit 3
-#define reg_bif_dma_r_intr_offset 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
-#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
-#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
-#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
-#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
-#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
-#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
-#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
-#define reg_bif_dma_r_masked_intr_offset 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin0_cfg_offset 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin1_cfg_offset 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin2_cfg_offset 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin3_cfg_offset 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin4_cfg_offset 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin5_cfg_offset 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin6_cfg_offset 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin7_cfg_offset 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_pin_stat___pin0___lsb 0
-#define reg_bif_dma_r_pin_stat___pin0___width 1
-#define reg_bif_dma_r_pin_stat___pin0___bit 0
-#define reg_bif_dma_r_pin_stat___pin1___lsb 1
-#define reg_bif_dma_r_pin_stat___pin1___width 1
-#define reg_bif_dma_r_pin_stat___pin1___bit 1
-#define reg_bif_dma_r_pin_stat___pin2___lsb 2
-#define reg_bif_dma_r_pin_stat___pin2___width 1
-#define reg_bif_dma_r_pin_stat___pin2___bit 2
-#define reg_bif_dma_r_pin_stat___pin3___lsb 3
-#define reg_bif_dma_r_pin_stat___pin3___width 1
-#define reg_bif_dma_r_pin_stat___pin3___bit 3
-#define reg_bif_dma_r_pin_stat___pin4___lsb 4
-#define reg_bif_dma_r_pin_stat___pin4___width 1
-#define reg_bif_dma_r_pin_stat___pin4___bit 4
-#define reg_bif_dma_r_pin_stat___pin5___lsb 5
-#define reg_bif_dma_r_pin_stat___pin5___width 1
-#define reg_bif_dma_r_pin_stat___pin5___bit 5
-#define reg_bif_dma_r_pin_stat___pin6___lsb 6
-#define reg_bif_dma_r_pin_stat___pin6___width 1
-#define reg_bif_dma_r_pin_stat___pin6___bit 6
-#define reg_bif_dma_r_pin_stat___pin7___lsb 7
-#define reg_bif_dma_r_pin_stat___pin7___width 1
-#define reg_bif_dma_r_pin_stat___pin7___bit 7
-#define reg_bif_dma_r_pin_stat_offset 192
-
-
-/* Constants */
-#define regk_bif_dma_as_master 0x00000001
-#define regk_bif_dma_as_slave 0x00000001
-#define regk_bif_dma_burst1 0x00000000
-#define regk_bif_dma_burst8 0x00000001
-#define regk_bif_dma_bw16 0x00000001
-#define regk_bif_dma_bw32 0x00000002
-#define regk_bif_dma_bw8 0x00000000
-#define regk_bif_dma_dack 0x00000006
-#define regk_bif_dma_dack_inv 0x00000007
-#define regk_bif_dma_force 0x00000001
-#define regk_bif_dma_hi 0x00000003
-#define regk_bif_dma_inv 0x00000003
-#define regk_bif_dma_lo 0x00000002
-#define regk_bif_dma_master 0x00000001
-#define regk_bif_dma_no 0x00000000
-#define regk_bif_dma_norm 0x00000002
-#define regk_bif_dma_off 0x00000000
-#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch0_start_default 0x00000000
-#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch1_start_default 0x00000000
-#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch2_start_default 0x00000000
-#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch3_start_default 0x00000000
-#define regk_bif_dma_rw_intr_mask_default 0x00000000
-#define regk_bif_dma_rw_pin0_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin1_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin2_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin3_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin4_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin5_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin6_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin7_cfg_default 0x00000000
-#define regk_bif_dma_slave 0x00000002
-#define regk_bif_dma_sreq 0x00000006
-#define regk_bif_dma_sreq_inv 0x00000007
-#define regk_bif_dma_tc 0x00000004
-#define regk_bif_dma_tc_inv 0x00000005
-#define regk_bif_dma_yes 0x00000001
-#endif /* __bif_dma_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h
deleted file mode 100644
index 55697fec603e..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_slave_defs_asm_h
-#define __bif_slave_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_slave_regs.r
- * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- * last modfied: Mon Apr 11 16:06:34 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
- * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
-#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
-#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
-#define reg_bif_slave_rw_slave_cfg___loopback___width 1
-#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
-#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
-#define reg_bif_slave_rw_slave_cfg___dis___width 1
-#define reg_bif_slave_rw_slave_cfg___dis___bit 6
-#define reg_bif_slave_rw_slave_cfg_offset 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
-#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
-#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
-#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
-#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
-#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
-#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
-#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
-#define reg_bif_slave_r_slave_mode_offset 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch0_cfg_offset 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch1_cfg_offset 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch2_cfg_offset 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch3_cfg_offset 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
-#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
-#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
-#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
-#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
-#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
-#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
-#define reg_bif_slave_rw_arb_cfg___release___lsb 7
-#define reg_bif_slave_rw_arb_cfg___release___width 2
-#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
-#define reg_bif_slave_rw_arb_cfg___acquire___width 1
-#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
-#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
-#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
-#define reg_bif_slave_rw_arb_cfg_offset 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
-#define reg_bif_slave_r_arb_stat___init_mode___width 1
-#define reg_bif_slave_r_arb_stat___init_mode___bit 0
-#define reg_bif_slave_r_arb_stat___mode___lsb 1
-#define reg_bif_slave_r_arb_stat___mode___width 1
-#define reg_bif_slave_r_arb_stat___mode___bit 1
-#define reg_bif_slave_r_arb_stat___brin___lsb 2
-#define reg_bif_slave_r_arb_stat___brin___width 1
-#define reg_bif_slave_r_arb_stat___brin___bit 2
-#define reg_bif_slave_r_arb_stat___brout___lsb 3
-#define reg_bif_slave_r_arb_stat___brout___width 1
-#define reg_bif_slave_r_arb_stat___brout___bit 3
-#define reg_bif_slave_r_arb_stat___bg___lsb 4
-#define reg_bif_slave_r_arb_stat___bg___width 1
-#define reg_bif_slave_r_arb_stat___bg___bit 4
-#define reg_bif_slave_r_arb_stat_offset 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
-#define reg_bif_slave_rw_intr_mask___bus_release___width 1
-#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
-#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
-#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
-#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
-#define reg_bif_slave_rw_intr_mask_offset 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
-#define reg_bif_slave_rw_ack_intr___bus_release___width 1
-#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
-#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
-#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
-#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
-#define reg_bif_slave_rw_ack_intr_offset 68
-
-/* Register r_intr, scope bif_slave, type r */
-#define reg_bif_slave_r_intr___bus_release___lsb 0
-#define reg_bif_slave_r_intr___bus_release___width 1
-#define reg_bif_slave_r_intr___bus_release___bit 0
-#define reg_bif_slave_r_intr___bus_acquire___lsb 1
-#define reg_bif_slave_r_intr___bus_acquire___width 1
-#define reg_bif_slave_r_intr___bus_acquire___bit 1
-#define reg_bif_slave_r_intr_offset 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
-#define reg_bif_slave_r_masked_intr___bus_release___width 1
-#define reg_bif_slave_r_masked_intr___bus_release___bit 0
-#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
-#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
-#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
-#define reg_bif_slave_r_masked_intr_offset 76
-
-
-/* Constants */
-#define regk_bif_slave_active_hi 0x00000003
-#define regk_bif_slave_active_lo 0x00000002
-#define regk_bif_slave_addr 0x00000000
-#define regk_bif_slave_always 0x00000001
-#define regk_bif_slave_at_idle 0x00000002
-#define regk_bif_slave_burst_end 0x00000003
-#define regk_bif_slave_dma 0x00000001
-#define regk_bif_slave_hi 0x00000003
-#define regk_bif_slave_inv 0x00000001
-#define regk_bif_slave_lo 0x00000002
-#define regk_bif_slave_local 0x00000001
-#define regk_bif_slave_master 0x00000000
-#define regk_bif_slave_mode_reg 0x00000001
-#define regk_bif_slave_no 0x00000000
-#define regk_bif_slave_norm 0x00000000
-#define regk_bif_slave_on_access 0x00000000
-#define regk_bif_slave_rw_arb_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch0_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch1_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch2_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch3_cfg_default 0x00000000
-#define regk_bif_slave_rw_intr_mask_default 0x00000000
-#define regk_bif_slave_rw_slave_cfg_default 0x00000000
-#define regk_bif_slave_shared 0x00000000
-#define regk_bif_slave_slave 0x00000001
-#define regk_bif_slave_t0ns 0x00000003
-#define regk_bif_slave_t10ns 0x00000002
-#define regk_bif_slave_t20ns 0x00000003
-#define regk_bif_slave_t30ns 0x00000002
-#define regk_bif_slave_t40ns 0x00000001
-#define regk_bif_slave_t50ns 0x00000000
-#define regk_bif_slave_yes 0x00000001
-#define regk_bif_slave_z 0x00000004
-#endif /* __bif_slave_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h
deleted file mode 100644
index 6455b4897bcc..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_asm_h
-#define __config_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
- * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope config, type r */
-#define reg_config_r_bootsel___boot_mode___lsb 0
-#define reg_config_r_bootsel___boot_mode___width 3
-#define reg_config_r_bootsel___full_duplex___lsb 3
-#define reg_config_r_bootsel___full_duplex___width 1
-#define reg_config_r_bootsel___full_duplex___bit 3
-#define reg_config_r_bootsel___user___lsb 4
-#define reg_config_r_bootsel___user___width 1
-#define reg_config_r_bootsel___user___bit 4
-#define reg_config_r_bootsel___pll___lsb 5
-#define reg_config_r_bootsel___pll___width 1
-#define reg_config_r_bootsel___pll___bit 5
-#define reg_config_r_bootsel___flash_bw___lsb 6
-#define reg_config_r_bootsel___flash_bw___width 1
-#define reg_config_r_bootsel___flash_bw___bit 6
-#define reg_config_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-#define reg_config_rw_clk_ctrl___pll___lsb 0
-#define reg_config_rw_clk_ctrl___pll___width 1
-#define reg_config_rw_clk_ctrl___pll___bit 0
-#define reg_config_rw_clk_ctrl___cpu___lsb 1
-#define reg_config_rw_clk_ctrl___cpu___width 1
-#define reg_config_rw_clk_ctrl___cpu___bit 1
-#define reg_config_rw_clk_ctrl___iop___lsb 2
-#define reg_config_rw_clk_ctrl___iop___width 1
-#define reg_config_rw_clk_ctrl___iop___bit 2
-#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
-#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
-#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
-#define reg_config_rw_clk_ctrl___dma23___lsb 4
-#define reg_config_rw_clk_ctrl___dma23___width 1
-#define reg_config_rw_clk_ctrl___dma23___bit 4
-#define reg_config_rw_clk_ctrl___dma45___lsb 5
-#define reg_config_rw_clk_ctrl___dma45___width 1
-#define reg_config_rw_clk_ctrl___dma45___bit 5
-#define reg_config_rw_clk_ctrl___dma67___lsb 6
-#define reg_config_rw_clk_ctrl___dma67___width 1
-#define reg_config_rw_clk_ctrl___dma67___bit 6
-#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
-#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
-#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
-#define reg_config_rw_clk_ctrl___bif___lsb 8
-#define reg_config_rw_clk_ctrl___bif___width 1
-#define reg_config_rw_clk_ctrl___bif___bit 8
-#define reg_config_rw_clk_ctrl___fix_io___lsb 9
-#define reg_config_rw_clk_ctrl___fix_io___width 1
-#define reg_config_rw_clk_ctrl___fix_io___bit 9
-#define reg_config_rw_clk_ctrl_offset 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
-#define reg_config_rw_pad_ctrl___usb_susp___width 1
-#define reg_config_rw_pad_ctrl___usb_susp___bit 0
-#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
-#define reg_config_rw_pad_ctrl___phyrst_n___width 1
-#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
-#define reg_config_rw_pad_ctrl_offset 8
-
-
-/* Constants */
-#define regk_config_bw16 0x00000000
-#define regk_config_bw32 0x00000001
-#define regk_config_master 0x00000005
-#define regk_config_nand 0x00000003
-#define regk_config_net_rx 0x00000001
-#define regk_config_net_tx_rx 0x00000002
-#define regk_config_no 0x00000000
-#define regk_config_none 0x00000007
-#define regk_config_nor 0x00000000
-#define regk_config_rw_clk_ctrl_default 0x00000002
-#define regk_config_rw_pad_ctrl_default 0x00000000
-#define regk_config_ser 0x00000004
-#define regk_config_slave 0x00000006
-#define regk_config_yes 0x00000001
-#endif /* __config_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h
deleted file mode 100644
index 8370aee8a14a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/crisp/doc/cpu_vect.r
-version . */
-
-#ifndef _______INST_CRISP_DOC_CPU_VECT_R
-#define _______INST_CRISP_DOC_CPU_VECT_R
-#define NMI_INTR_VECT 0x00
-#define RESERVED_1_INTR_VECT 0x01
-#define RESERVED_2_INTR_VECT 0x02
-#define SINGLE_STEP_INTR_VECT 0x03
-#define INSTR_TLB_REFILL_INTR_VECT 0x04
-#define INSTR_TLB_INV_INTR_VECT 0x05
-#define INSTR_TLB_ACC_INTR_VECT 0x06
-#define TLB_EX_INTR_VECT 0x07
-#define DATA_TLB_REFILL_INTR_VECT 0x08
-#define DATA_TLB_INV_INTR_VECT 0x09
-#define DATA_TLB_ACC_INTR_VECT 0x0a
-#define DATA_TLB_WE_INTR_VECT 0x0b
-#define HW_BP_INTR_VECT 0x0c
-#define RESERVED_D_INTR_VECT 0x0d
-#define RESERVED_E_INTR_VECT 0x0e
-#define RESERVED_F_INTR_VECT 0x0f
-#define BREAK_0_INTR_VECT 0x10
-#define BREAK_1_INTR_VECT 0x11
-#define BREAK_2_INTR_VECT 0x12
-#define BREAK_3_INTR_VECT 0x13
-#define BREAK_4_INTR_VECT 0x14
-#define BREAK_5_INTR_VECT 0x15
-#define BREAK_6_INTR_VECT 0x16
-#define BREAK_7_INTR_VECT 0x17
-#define BREAK_8_INTR_VECT 0x18
-#define BREAK_9_INTR_VECT 0x19
-#define BREAK_10_INTR_VECT 0x1a
-#define BREAK_11_INTR_VECT 0x1b
-#define BREAK_12_INTR_VECT 0x1c
-#define BREAK_13_INTR_VECT 0x1d
-#define BREAK_14_INTR_VECT 0x1e
-#define BREAK_15_INTR_VECT 0x1f
-#define MULTIPLE_INTR_VECT 0x30
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h
deleted file mode 100644
index bd048296d2f8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __cris_defs_asm_h
-#define __cris_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/crisp/doc/cris.r
- * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
- * last modfied: Mon Apr 11 16:06:39 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
- * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gc_cfg, scope cris, type rw */
-#define reg_cris_rw_gc_cfg___ic___lsb 0
-#define reg_cris_rw_gc_cfg___ic___width 1
-#define reg_cris_rw_gc_cfg___ic___bit 0
-#define reg_cris_rw_gc_cfg___dc___lsb 1
-#define reg_cris_rw_gc_cfg___dc___width 1
-#define reg_cris_rw_gc_cfg___dc___bit 1
-#define reg_cris_rw_gc_cfg___im___lsb 2
-#define reg_cris_rw_gc_cfg___im___width 1
-#define reg_cris_rw_gc_cfg___im___bit 2
-#define reg_cris_rw_gc_cfg___dm___lsb 3
-#define reg_cris_rw_gc_cfg___dm___width 1
-#define reg_cris_rw_gc_cfg___dm___bit 3
-#define reg_cris_rw_gc_cfg___gb___lsb 4
-#define reg_cris_rw_gc_cfg___gb___width 1
-#define reg_cris_rw_gc_cfg___gb___bit 4
-#define reg_cris_rw_gc_cfg___gk___lsb 5
-#define reg_cris_rw_gc_cfg___gk___width 1
-#define reg_cris_rw_gc_cfg___gk___bit 5
-#define reg_cris_rw_gc_cfg___gp___lsb 6
-#define reg_cris_rw_gc_cfg___gp___width 1
-#define reg_cris_rw_gc_cfg___gp___bit 6
-#define reg_cris_rw_gc_cfg_offset 0
-
-/* Register rw_gc_ccs, scope cris, type rw */
-#define reg_cris_rw_gc_ccs_offset 4
-
-/* Register rw_gc_srs, scope cris, type rw */
-#define reg_cris_rw_gc_srs___srs___lsb 0
-#define reg_cris_rw_gc_srs___srs___width 8
-#define reg_cris_rw_gc_srs_offset 8
-
-/* Register rw_gc_nrp, scope cris, type rw */
-#define reg_cris_rw_gc_nrp_offset 12
-
-/* Register rw_gc_exs, scope cris, type rw */
-#define reg_cris_rw_gc_exs_offset 16
-
-/* Register rw_gc_eda, scope cris, type rw */
-#define reg_cris_rw_gc_eda_offset 20
-
-/* Register rw_gc_r0, scope cris, type rw */
-#define reg_cris_rw_gc_r0_offset 32
-
-/* Register rw_gc_r1, scope cris, type rw */
-#define reg_cris_rw_gc_r1_offset 36
-
-/* Register rw_gc_r2, scope cris, type rw */
-#define reg_cris_rw_gc_r2_offset 40
-
-/* Register rw_gc_r3, scope cris, type rw */
-#define reg_cris_rw_gc_r3_offset 44
-
-
-/* Constants */
-#define regk_cris_no 0x00000000
-#define regk_cris_rw_gc_cfg_default 0x00000000
-#define regk_cris_yes 0x00000001
-#endif /* __cris_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h
deleted file mode 100644
index 429fe0d4ffe4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define RW_GC_CFG 0
-#define RW_GC_CCS 1
-#define RW_GC_SRS 2
-#define RW_GC_NRP 3
-#define RW_GC_EXS 4
-#define RW_GC_EDA 5
-#define RW_GC_R0 8
-#define RW_GC_R1 9
-#define RW_GC_R2 10
-#define RW_GC_R3 11
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h
deleted file mode 100644
index fec451d2a3db..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __dma_defs_asm_h
-#define __dma_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
- * last modfied: Mon Apr 11 16:06:51 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_data, scope dma, type rw */
-#define reg_dma_rw_data_offset 0
-
-/* Register rw_data_next, scope dma, type rw */
-#define reg_dma_rw_data_next_offset 4
-
-/* Register rw_data_buf, scope dma, type rw */
-#define reg_dma_rw_data_buf_offset 8
-
-/* Register rw_data_ctrl, scope dma, type rw */
-#define reg_dma_rw_data_ctrl___eol___lsb 0
-#define reg_dma_rw_data_ctrl___eol___width 1
-#define reg_dma_rw_data_ctrl___eol___bit 0
-#define reg_dma_rw_data_ctrl___out_eop___lsb 3
-#define reg_dma_rw_data_ctrl___out_eop___width 1
-#define reg_dma_rw_data_ctrl___out_eop___bit 3
-#define reg_dma_rw_data_ctrl___intr___lsb 4
-#define reg_dma_rw_data_ctrl___intr___width 1
-#define reg_dma_rw_data_ctrl___intr___bit 4
-#define reg_dma_rw_data_ctrl___wait___lsb 5
-#define reg_dma_rw_data_ctrl___wait___width 1
-#define reg_dma_rw_data_ctrl___wait___bit 5
-#define reg_dma_rw_data_ctrl_offset 12
-
-/* Register rw_data_stat, scope dma, type rw */
-#define reg_dma_rw_data_stat___in_eop___lsb 3
-#define reg_dma_rw_data_stat___in_eop___width 1
-#define reg_dma_rw_data_stat___in_eop___bit 3
-#define reg_dma_rw_data_stat_offset 16
-
-/* Register rw_data_md, scope dma, type rw */
-#define reg_dma_rw_data_md___md___lsb 0
-#define reg_dma_rw_data_md___md___width 16
-#define reg_dma_rw_data_md_offset 20
-
-/* Register rw_data_md_s, scope dma, type rw */
-#define reg_dma_rw_data_md_s___md_s___lsb 0
-#define reg_dma_rw_data_md_s___md_s___width 16
-#define reg_dma_rw_data_md_s_offset 24
-
-/* Register rw_data_after, scope dma, type rw */
-#define reg_dma_rw_data_after_offset 28
-
-/* Register rw_ctxt, scope dma, type rw */
-#define reg_dma_rw_ctxt_offset 32
-
-/* Register rw_ctxt_next, scope dma, type rw */
-#define reg_dma_rw_ctxt_next_offset 36
-
-/* Register rw_ctxt_ctrl, scope dma, type rw */
-#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
-#define reg_dma_rw_ctxt_ctrl___eol___width 1
-#define reg_dma_rw_ctxt_ctrl___eol___bit 0
-#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
-#define reg_dma_rw_ctxt_ctrl___intr___width 1
-#define reg_dma_rw_ctxt_ctrl___intr___bit 4
-#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
-#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
-#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
-#define reg_dma_rw_ctxt_ctrl___en___lsb 7
-#define reg_dma_rw_ctxt_ctrl___en___width 1
-#define reg_dma_rw_ctxt_ctrl___en___bit 7
-#define reg_dma_rw_ctxt_ctrl_offset 40
-
-/* Register rw_ctxt_stat, scope dma, type rw */
-#define reg_dma_rw_ctxt_stat___dis___lsb 7
-#define reg_dma_rw_ctxt_stat___dis___width 1
-#define reg_dma_rw_ctxt_stat___dis___bit 7
-#define reg_dma_rw_ctxt_stat_offset 44
-
-/* Register rw_ctxt_md0, scope dma, type rw */
-#define reg_dma_rw_ctxt_md0___md0___lsb 0
-#define reg_dma_rw_ctxt_md0___md0___width 16
-#define reg_dma_rw_ctxt_md0_offset 48
-
-/* Register rw_ctxt_md0_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
-#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
-#define reg_dma_rw_ctxt_md0_s_offset 52
-
-/* Register rw_ctxt_md1, scope dma, type rw */
-#define reg_dma_rw_ctxt_md1_offset 56
-
-/* Register rw_ctxt_md1_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md1_s_offset 60
-
-/* Register rw_ctxt_md2, scope dma, type rw */
-#define reg_dma_rw_ctxt_md2_offset 64
-
-/* Register rw_ctxt_md2_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md2_s_offset 68
-
-/* Register rw_ctxt_md3, scope dma, type rw */
-#define reg_dma_rw_ctxt_md3_offset 72
-
-/* Register rw_ctxt_md3_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md3_s_offset 76
-
-/* Register rw_ctxt_md4, scope dma, type rw */
-#define reg_dma_rw_ctxt_md4_offset 80
-
-/* Register rw_ctxt_md4_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md4_s_offset 84
-
-/* Register rw_saved_data, scope dma, type rw */
-#define reg_dma_rw_saved_data_offset 88
-
-/* Register rw_saved_data_buf, scope dma, type rw */
-#define reg_dma_rw_saved_data_buf_offset 92
-
-/* Register rw_group, scope dma, type rw */
-#define reg_dma_rw_group_offset 96
-
-/* Register rw_group_next, scope dma, type rw */
-#define reg_dma_rw_group_next_offset 100
-
-/* Register rw_group_ctrl, scope dma, type rw */
-#define reg_dma_rw_group_ctrl___eol___lsb 0
-#define reg_dma_rw_group_ctrl___eol___width 1
-#define reg_dma_rw_group_ctrl___eol___bit 0
-#define reg_dma_rw_group_ctrl___tol___lsb 1
-#define reg_dma_rw_group_ctrl___tol___width 1
-#define reg_dma_rw_group_ctrl___tol___bit 1
-#define reg_dma_rw_group_ctrl___bol___lsb 2
-#define reg_dma_rw_group_ctrl___bol___width 1
-#define reg_dma_rw_group_ctrl___bol___bit 2
-#define reg_dma_rw_group_ctrl___intr___lsb 4
-#define reg_dma_rw_group_ctrl___intr___width 1
-#define reg_dma_rw_group_ctrl___intr___bit 4
-#define reg_dma_rw_group_ctrl___en___lsb 7
-#define reg_dma_rw_group_ctrl___en___width 1
-#define reg_dma_rw_group_ctrl___en___bit 7
-#define reg_dma_rw_group_ctrl_offset 104
-
-/* Register rw_group_stat, scope dma, type rw */
-#define reg_dma_rw_group_stat___dis___lsb 7
-#define reg_dma_rw_group_stat___dis___width 1
-#define reg_dma_rw_group_stat___dis___bit 7
-#define reg_dma_rw_group_stat_offset 108
-
-/* Register rw_group_md, scope dma, type rw */
-#define reg_dma_rw_group_md___md___lsb 0
-#define reg_dma_rw_group_md___md___width 16
-#define reg_dma_rw_group_md_offset 112
-
-/* Register rw_group_md_s, scope dma, type rw */
-#define reg_dma_rw_group_md_s___md_s___lsb 0
-#define reg_dma_rw_group_md_s___md_s___width 16
-#define reg_dma_rw_group_md_s_offset 116
-
-/* Register rw_group_up, scope dma, type rw */
-#define reg_dma_rw_group_up_offset 120
-
-/* Register rw_group_down, scope dma, type rw */
-#define reg_dma_rw_group_down_offset 124
-
-/* Register rw_cmd, scope dma, type rw */
-#define reg_dma_rw_cmd___cont_data___lsb 0
-#define reg_dma_rw_cmd___cont_data___width 1
-#define reg_dma_rw_cmd___cont_data___bit 0
-#define reg_dma_rw_cmd_offset 128
-
-/* Register rw_cfg, scope dma, type rw */
-#define reg_dma_rw_cfg___en___lsb 0
-#define reg_dma_rw_cfg___en___width 1
-#define reg_dma_rw_cfg___en___bit 0
-#define reg_dma_rw_cfg___stop___lsb 1
-#define reg_dma_rw_cfg___stop___width 1
-#define reg_dma_rw_cfg___stop___bit 1
-#define reg_dma_rw_cfg_offset 132
-
-/* Register rw_stat, scope dma, type rw */
-#define reg_dma_rw_stat___mode___lsb 0
-#define reg_dma_rw_stat___mode___width 5
-#define reg_dma_rw_stat___list_state___lsb 5
-#define reg_dma_rw_stat___list_state___width 3
-#define reg_dma_rw_stat___stream_cmd_src___lsb 8
-#define reg_dma_rw_stat___stream_cmd_src___width 8
-#define reg_dma_rw_stat___buf___lsb 24
-#define reg_dma_rw_stat___buf___width 8
-#define reg_dma_rw_stat_offset 136
-
-/* Register rw_intr_mask, scope dma, type rw */
-#define reg_dma_rw_intr_mask___group___lsb 0
-#define reg_dma_rw_intr_mask___group___width 1
-#define reg_dma_rw_intr_mask___group___bit 0
-#define reg_dma_rw_intr_mask___ctxt___lsb 1
-#define reg_dma_rw_intr_mask___ctxt___width 1
-#define reg_dma_rw_intr_mask___ctxt___bit 1
-#define reg_dma_rw_intr_mask___data___lsb 2
-#define reg_dma_rw_intr_mask___data___width 1
-#define reg_dma_rw_intr_mask___data___bit 2
-#define reg_dma_rw_intr_mask___in_eop___lsb 3
-#define reg_dma_rw_intr_mask___in_eop___width 1
-#define reg_dma_rw_intr_mask___in_eop___bit 3
-#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
-#define reg_dma_rw_intr_mask___stream_cmd___width 1
-#define reg_dma_rw_intr_mask___stream_cmd___bit 4
-#define reg_dma_rw_intr_mask_offset 140
-
-/* Register rw_ack_intr, scope dma, type rw */
-#define reg_dma_rw_ack_intr___group___lsb 0
-#define reg_dma_rw_ack_intr___group___width 1
-#define reg_dma_rw_ack_intr___group___bit 0
-#define reg_dma_rw_ack_intr___ctxt___lsb 1
-#define reg_dma_rw_ack_intr___ctxt___width 1
-#define reg_dma_rw_ack_intr___ctxt___bit 1
-#define reg_dma_rw_ack_intr___data___lsb 2
-#define reg_dma_rw_ack_intr___data___width 1
-#define reg_dma_rw_ack_intr___data___bit 2
-#define reg_dma_rw_ack_intr___in_eop___lsb 3
-#define reg_dma_rw_ack_intr___in_eop___width 1
-#define reg_dma_rw_ack_intr___in_eop___bit 3
-#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
-#define reg_dma_rw_ack_intr___stream_cmd___width 1
-#define reg_dma_rw_ack_intr___stream_cmd___bit 4
-#define reg_dma_rw_ack_intr_offset 144
-
-/* Register r_intr, scope dma, type r */
-#define reg_dma_r_intr___group___lsb 0
-#define reg_dma_r_intr___group___width 1
-#define reg_dma_r_intr___group___bit 0
-#define reg_dma_r_intr___ctxt___lsb 1
-#define reg_dma_r_intr___ctxt___width 1
-#define reg_dma_r_intr___ctxt___bit 1
-#define reg_dma_r_intr___data___lsb 2
-#define reg_dma_r_intr___data___width 1
-#define reg_dma_r_intr___data___bit 2
-#define reg_dma_r_intr___in_eop___lsb 3
-#define reg_dma_r_intr___in_eop___width 1
-#define reg_dma_r_intr___in_eop___bit 3
-#define reg_dma_r_intr___stream_cmd___lsb 4
-#define reg_dma_r_intr___stream_cmd___width 1
-#define reg_dma_r_intr___stream_cmd___bit 4
-#define reg_dma_r_intr_offset 148
-
-/* Register r_masked_intr, scope dma, type r */
-#define reg_dma_r_masked_intr___group___lsb 0
-#define reg_dma_r_masked_intr___group___width 1
-#define reg_dma_r_masked_intr___group___bit 0
-#define reg_dma_r_masked_intr___ctxt___lsb 1
-#define reg_dma_r_masked_intr___ctxt___width 1
-#define reg_dma_r_masked_intr___ctxt___bit 1
-#define reg_dma_r_masked_intr___data___lsb 2
-#define reg_dma_r_masked_intr___data___width 1
-#define reg_dma_r_masked_intr___data___bit 2
-#define reg_dma_r_masked_intr___in_eop___lsb 3
-#define reg_dma_r_masked_intr___in_eop___width 1
-#define reg_dma_r_masked_intr___in_eop___bit 3
-#define reg_dma_r_masked_intr___stream_cmd___lsb 4
-#define reg_dma_r_masked_intr___stream_cmd___width 1
-#define reg_dma_r_masked_intr___stream_cmd___bit 4
-#define reg_dma_r_masked_intr_offset 152
-
-/* Register rw_stream_cmd, scope dma, type rw */
-#define reg_dma_rw_stream_cmd___cmd___lsb 0
-#define reg_dma_rw_stream_cmd___cmd___width 10
-#define reg_dma_rw_stream_cmd___n___lsb 16
-#define reg_dma_rw_stream_cmd___n___width 8
-#define reg_dma_rw_stream_cmd___busy___lsb 31
-#define reg_dma_rw_stream_cmd___busy___width 1
-#define reg_dma_rw_stream_cmd___busy___bit 31
-#define reg_dma_rw_stream_cmd_offset 156
-
-
-/* Constants */
-#define regk_dma_ack_pkt 0x00000100
-#define regk_dma_anytime 0x00000001
-#define regk_dma_array 0x00000008
-#define regk_dma_burst 0x00000020
-#define regk_dma_client 0x00000002
-#define regk_dma_copy_next 0x00000010
-#define regk_dma_copy_up 0x00000020
-#define regk_dma_data_at_eol 0x00000001
-#define regk_dma_dis_c 0x00000010
-#define regk_dma_dis_g 0x00000020
-#define regk_dma_idle 0x00000001
-#define regk_dma_intern 0x00000004
-#define regk_dma_load_c 0x00000200
-#define regk_dma_load_c_n 0x00000280
-#define regk_dma_load_c_next 0x00000240
-#define regk_dma_load_d 0x00000140
-#define regk_dma_load_g 0x00000300
-#define regk_dma_load_g_down 0x000003c0
-#define regk_dma_load_g_next 0x00000340
-#define regk_dma_load_g_up 0x00000380
-#define regk_dma_next_en 0x00000010
-#define regk_dma_next_pkt 0x00000010
-#define regk_dma_no 0x00000000
-#define regk_dma_only_at_wait 0x00000000
-#define regk_dma_restore 0x00000020
-#define regk_dma_rst 0x00000001
-#define regk_dma_running 0x00000004
-#define regk_dma_rw_cfg_default 0x00000000
-#define regk_dma_rw_cmd_default 0x00000000
-#define regk_dma_rw_intr_mask_default 0x00000000
-#define regk_dma_rw_stat_default 0x00000101
-#define regk_dma_rw_stream_cmd_default 0x00000000
-#define regk_dma_save_down 0x00000020
-#define regk_dma_save_up 0x00000020
-#define regk_dma_set_reg 0x00000050
-#define regk_dma_set_w_size1 0x00000190
-#define regk_dma_set_w_size2 0x000001a0
-#define regk_dma_set_w_size4 0x000001c0
-#define regk_dma_stopped 0x00000002
-#define regk_dma_store_c 0x00000002
-#define regk_dma_store_descr 0x00000000
-#define regk_dma_store_g 0x00000004
-#define regk_dma_store_md 0x00000001
-#define regk_dma_sw 0x00000008
-#define regk_dma_update_down 0x00000020
-#define regk_dma_yes 0x00000001
-#endif /* __dma_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h
deleted file mode 100644
index 97fe523d4d72..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __eth_defs_asm_h
-#define __eth_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/eth/rtl/eth_regs.r
- * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
- * last modfied: Mon Apr 11 16:07:03 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
- * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ma0_lo, scope eth, type rw */
-#define reg_eth_rw_ma0_lo___addr___lsb 0
-#define reg_eth_rw_ma0_lo___addr___width 32
-#define reg_eth_rw_ma0_lo_offset 0
-
-/* Register rw_ma0_hi, scope eth, type rw */
-#define reg_eth_rw_ma0_hi___addr___lsb 0
-#define reg_eth_rw_ma0_hi___addr___width 16
-#define reg_eth_rw_ma0_hi_offset 4
-
-/* Register rw_ma1_lo, scope eth, type rw */
-#define reg_eth_rw_ma1_lo___addr___lsb 0
-#define reg_eth_rw_ma1_lo___addr___width 32
-#define reg_eth_rw_ma1_lo_offset 8
-
-/* Register rw_ma1_hi, scope eth, type rw */
-#define reg_eth_rw_ma1_hi___addr___lsb 0
-#define reg_eth_rw_ma1_hi___addr___width 16
-#define reg_eth_rw_ma1_hi_offset 12
-
-/* Register rw_ga_lo, scope eth, type rw */
-#define reg_eth_rw_ga_lo___table___lsb 0
-#define reg_eth_rw_ga_lo___table___width 32
-#define reg_eth_rw_ga_lo_offset 16
-
-/* Register rw_ga_hi, scope eth, type rw */
-#define reg_eth_rw_ga_hi___table___lsb 0
-#define reg_eth_rw_ga_hi___table___width 32
-#define reg_eth_rw_ga_hi_offset 20
-
-/* Register rw_gen_ctrl, scope eth, type rw */
-#define reg_eth_rw_gen_ctrl___en___lsb 0
-#define reg_eth_rw_gen_ctrl___en___width 1
-#define reg_eth_rw_gen_ctrl___en___bit 0
-#define reg_eth_rw_gen_ctrl___phy___lsb 1
-#define reg_eth_rw_gen_ctrl___phy___width 2
-#define reg_eth_rw_gen_ctrl___protocol___lsb 3
-#define reg_eth_rw_gen_ctrl___protocol___width 1
-#define reg_eth_rw_gen_ctrl___protocol___bit 3
-#define reg_eth_rw_gen_ctrl___loopback___lsb 4
-#define reg_eth_rw_gen_ctrl___loopback___width 1
-#define reg_eth_rw_gen_ctrl___loopback___bit 4
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
-#define reg_eth_rw_gen_ctrl_offset 24
-
-/* Register rw_rec_ctrl, scope eth, type rw */
-#define reg_eth_rw_rec_ctrl___ma0___lsb 0
-#define reg_eth_rw_rec_ctrl___ma0___width 1
-#define reg_eth_rw_rec_ctrl___ma0___bit 0
-#define reg_eth_rw_rec_ctrl___ma1___lsb 1
-#define reg_eth_rw_rec_ctrl___ma1___width 1
-#define reg_eth_rw_rec_ctrl___ma1___bit 1
-#define reg_eth_rw_rec_ctrl___individual___lsb 2
-#define reg_eth_rw_rec_ctrl___individual___width 1
-#define reg_eth_rw_rec_ctrl___individual___bit 2
-#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
-#define reg_eth_rw_rec_ctrl___broadcast___width 1
-#define reg_eth_rw_rec_ctrl___broadcast___bit 3
-#define reg_eth_rw_rec_ctrl___undersize___lsb 4
-#define reg_eth_rw_rec_ctrl___undersize___width 1
-#define reg_eth_rw_rec_ctrl___undersize___bit 4
-#define reg_eth_rw_rec_ctrl___oversize___lsb 5
-#define reg_eth_rw_rec_ctrl___oversize___width 1
-#define reg_eth_rw_rec_ctrl___oversize___bit 5
-#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
-#define reg_eth_rw_rec_ctrl___bad_crc___width 1
-#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
-#define reg_eth_rw_rec_ctrl___duplex___lsb 7
-#define reg_eth_rw_rec_ctrl___duplex___width 1
-#define reg_eth_rw_rec_ctrl___duplex___bit 7
-#define reg_eth_rw_rec_ctrl___max_size___lsb 8
-#define reg_eth_rw_rec_ctrl___max_size___width 1
-#define reg_eth_rw_rec_ctrl___max_size___bit 8
-#define reg_eth_rw_rec_ctrl_offset 28
-
-/* Register rw_tr_ctrl, scope eth, type rw */
-#define reg_eth_rw_tr_ctrl___crc___lsb 0
-#define reg_eth_rw_tr_ctrl___crc___width 1
-#define reg_eth_rw_tr_ctrl___crc___bit 0
-#define reg_eth_rw_tr_ctrl___pad___lsb 1
-#define reg_eth_rw_tr_ctrl___pad___width 1
-#define reg_eth_rw_tr_ctrl___pad___bit 1
-#define reg_eth_rw_tr_ctrl___retry___lsb 2
-#define reg_eth_rw_tr_ctrl___retry___width 1
-#define reg_eth_rw_tr_ctrl___retry___bit 2
-#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
-#define reg_eth_rw_tr_ctrl___ignore_col___width 1
-#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
-#define reg_eth_rw_tr_ctrl___cancel___lsb 4
-#define reg_eth_rw_tr_ctrl___cancel___width 1
-#define reg_eth_rw_tr_ctrl___cancel___bit 4
-#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
-#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
-#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
-#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
-#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
-#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
-#define reg_eth_rw_tr_ctrl_offset 32
-
-/* Register rw_clr_err, scope eth, type rw */
-#define reg_eth_rw_clr_err___clr___lsb 0
-#define reg_eth_rw_clr_err___clr___width 1
-#define reg_eth_rw_clr_err___clr___bit 0
-#define reg_eth_rw_clr_err_offset 36
-
-/* Register rw_mgm_ctrl, scope eth, type rw */
-#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
-#define reg_eth_rw_mgm_ctrl___mdio___width 1
-#define reg_eth_rw_mgm_ctrl___mdio___bit 0
-#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
-#define reg_eth_rw_mgm_ctrl___mdoe___width 1
-#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
-#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
-#define reg_eth_rw_mgm_ctrl___mdc___width 1
-#define reg_eth_rw_mgm_ctrl___mdc___bit 2
-#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
-#define reg_eth_rw_mgm_ctrl___phyclk___width 1
-#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
-#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
-#define reg_eth_rw_mgm_ctrl___txdata___width 4
-#define reg_eth_rw_mgm_ctrl___txen___lsb 8
-#define reg_eth_rw_mgm_ctrl___txen___width 1
-#define reg_eth_rw_mgm_ctrl___txen___bit 8
-#define reg_eth_rw_mgm_ctrl_offset 40
-
-/* Register r_stat, scope eth, type r */
-#define reg_eth_r_stat___mdio___lsb 0
-#define reg_eth_r_stat___mdio___width 1
-#define reg_eth_r_stat___mdio___bit 0
-#define reg_eth_r_stat___exc_col___lsb 1
-#define reg_eth_r_stat___exc_col___width 1
-#define reg_eth_r_stat___exc_col___bit 1
-#define reg_eth_r_stat___urun___lsb 2
-#define reg_eth_r_stat___urun___width 1
-#define reg_eth_r_stat___urun___bit 2
-#define reg_eth_r_stat___phyclk___lsb 3
-#define reg_eth_r_stat___phyclk___width 1
-#define reg_eth_r_stat___phyclk___bit 3
-#define reg_eth_r_stat___txdata___lsb 4
-#define reg_eth_r_stat___txdata___width 4
-#define reg_eth_r_stat___txen___lsb 8
-#define reg_eth_r_stat___txen___width 1
-#define reg_eth_r_stat___txen___bit 8
-#define reg_eth_r_stat___col___lsb 9
-#define reg_eth_r_stat___col___width 1
-#define reg_eth_r_stat___col___bit 9
-#define reg_eth_r_stat___crs___lsb 10
-#define reg_eth_r_stat___crs___width 1
-#define reg_eth_r_stat___crs___bit 10
-#define reg_eth_r_stat___txclk___lsb 11
-#define reg_eth_r_stat___txclk___width 1
-#define reg_eth_r_stat___txclk___bit 11
-#define reg_eth_r_stat___rxdata___lsb 12
-#define reg_eth_r_stat___rxdata___width 4
-#define reg_eth_r_stat___rxer___lsb 16
-#define reg_eth_r_stat___rxer___width 1
-#define reg_eth_r_stat___rxer___bit 16
-#define reg_eth_r_stat___rxdv___lsb 17
-#define reg_eth_r_stat___rxdv___width 1
-#define reg_eth_r_stat___rxdv___bit 17
-#define reg_eth_r_stat___rxclk___lsb 18
-#define reg_eth_r_stat___rxclk___width 1
-#define reg_eth_r_stat___rxclk___bit 18
-#define reg_eth_r_stat_offset 44
-
-/* Register rs_rec_cnt, scope eth, type rs */
-#define reg_eth_rs_rec_cnt___crc_err___lsb 0
-#define reg_eth_rs_rec_cnt___crc_err___width 8
-#define reg_eth_rs_rec_cnt___align_err___lsb 8
-#define reg_eth_rs_rec_cnt___align_err___width 8
-#define reg_eth_rs_rec_cnt___oversize___lsb 16
-#define reg_eth_rs_rec_cnt___oversize___width 8
-#define reg_eth_rs_rec_cnt___congestion___lsb 24
-#define reg_eth_rs_rec_cnt___congestion___width 8
-#define reg_eth_rs_rec_cnt_offset 48
-
-/* Register r_rec_cnt, scope eth, type r */
-#define reg_eth_r_rec_cnt___crc_err___lsb 0
-#define reg_eth_r_rec_cnt___crc_err___width 8
-#define reg_eth_r_rec_cnt___align_err___lsb 8
-#define reg_eth_r_rec_cnt___align_err___width 8
-#define reg_eth_r_rec_cnt___oversize___lsb 16
-#define reg_eth_r_rec_cnt___oversize___width 8
-#define reg_eth_r_rec_cnt___congestion___lsb 24
-#define reg_eth_r_rec_cnt___congestion___width 8
-#define reg_eth_r_rec_cnt_offset 52
-
-/* Register rs_tr_cnt, scope eth, type rs */
-#define reg_eth_rs_tr_cnt___single_col___lsb 0
-#define reg_eth_rs_tr_cnt___single_col___width 8
-#define reg_eth_rs_tr_cnt___mult_col___lsb 8
-#define reg_eth_rs_tr_cnt___mult_col___width 8
-#define reg_eth_rs_tr_cnt___late_col___lsb 16
-#define reg_eth_rs_tr_cnt___late_col___width 8
-#define reg_eth_rs_tr_cnt___deferred___lsb 24
-#define reg_eth_rs_tr_cnt___deferred___width 8
-#define reg_eth_rs_tr_cnt_offset 56
-
-/* Register r_tr_cnt, scope eth, type r */
-#define reg_eth_r_tr_cnt___single_col___lsb 0
-#define reg_eth_r_tr_cnt___single_col___width 8
-#define reg_eth_r_tr_cnt___mult_col___lsb 8
-#define reg_eth_r_tr_cnt___mult_col___width 8
-#define reg_eth_r_tr_cnt___late_col___lsb 16
-#define reg_eth_r_tr_cnt___late_col___width 8
-#define reg_eth_r_tr_cnt___deferred___lsb 24
-#define reg_eth_r_tr_cnt___deferred___width 8
-#define reg_eth_r_tr_cnt_offset 60
-
-/* Register rs_phy_cnt, scope eth, type rs */
-#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
-#define reg_eth_rs_phy_cnt___carrier_loss___width 8
-#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
-#define reg_eth_rs_phy_cnt___sqe_err___width 8
-#define reg_eth_rs_phy_cnt_offset 64
-
-/* Register r_phy_cnt, scope eth, type r */
-#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
-#define reg_eth_r_phy_cnt___carrier_loss___width 8
-#define reg_eth_r_phy_cnt___sqe_err___lsb 8
-#define reg_eth_r_phy_cnt___sqe_err___width 8
-#define reg_eth_r_phy_cnt_offset 68
-
-/* Register rw_test_ctrl, scope eth, type rw */
-#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
-#define reg_eth_rw_test_ctrl___snmp_inc___width 1
-#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
-#define reg_eth_rw_test_ctrl___snmp___lsb 1
-#define reg_eth_rw_test_ctrl___snmp___width 1
-#define reg_eth_rw_test_ctrl___snmp___bit 1
-#define reg_eth_rw_test_ctrl___backoff___lsb 2
-#define reg_eth_rw_test_ctrl___backoff___width 1
-#define reg_eth_rw_test_ctrl___backoff___bit 2
-#define reg_eth_rw_test_ctrl_offset 72
-
-/* Register rw_intr_mask, scope eth, type rw */
-#define reg_eth_rw_intr_mask___crc___lsb 0
-#define reg_eth_rw_intr_mask___crc___width 1
-#define reg_eth_rw_intr_mask___crc___bit 0
-#define reg_eth_rw_intr_mask___align___lsb 1
-#define reg_eth_rw_intr_mask___align___width 1
-#define reg_eth_rw_intr_mask___align___bit 1
-#define reg_eth_rw_intr_mask___oversize___lsb 2
-#define reg_eth_rw_intr_mask___oversize___width 1
-#define reg_eth_rw_intr_mask___oversize___bit 2
-#define reg_eth_rw_intr_mask___congestion___lsb 3
-#define reg_eth_rw_intr_mask___congestion___width 1
-#define reg_eth_rw_intr_mask___congestion___bit 3
-#define reg_eth_rw_intr_mask___single_col___lsb 4
-#define reg_eth_rw_intr_mask___single_col___width 1
-#define reg_eth_rw_intr_mask___single_col___bit 4
-#define reg_eth_rw_intr_mask___mult_col___lsb 5
-#define reg_eth_rw_intr_mask___mult_col___width 1
-#define reg_eth_rw_intr_mask___mult_col___bit 5
-#define reg_eth_rw_intr_mask___late_col___lsb 6
-#define reg_eth_rw_intr_mask___late_col___width 1
-#define reg_eth_rw_intr_mask___late_col___bit 6
-#define reg_eth_rw_intr_mask___deferred___lsb 7
-#define reg_eth_rw_intr_mask___deferred___width 1
-#define reg_eth_rw_intr_mask___deferred___bit 7
-#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
-#define reg_eth_rw_intr_mask___carrier_loss___width 1
-#define reg_eth_rw_intr_mask___carrier_loss___bit 8
-#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
-#define reg_eth_rw_intr_mask___sqe_test_err___width 1
-#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
-#define reg_eth_rw_intr_mask___orun___lsb 10
-#define reg_eth_rw_intr_mask___orun___width 1
-#define reg_eth_rw_intr_mask___orun___bit 10
-#define reg_eth_rw_intr_mask___urun___lsb 11
-#define reg_eth_rw_intr_mask___urun___width 1
-#define reg_eth_rw_intr_mask___urun___bit 11
-#define reg_eth_rw_intr_mask___excessive_col___lsb 12
-#define reg_eth_rw_intr_mask___excessive_col___width 1
-#define reg_eth_rw_intr_mask___excessive_col___bit 12
-#define reg_eth_rw_intr_mask___mdio___lsb 13
-#define reg_eth_rw_intr_mask___mdio___width 1
-#define reg_eth_rw_intr_mask___mdio___bit 13
-#define reg_eth_rw_intr_mask_offset 76
-
-/* Register rw_ack_intr, scope eth, type rw */
-#define reg_eth_rw_ack_intr___crc___lsb 0
-#define reg_eth_rw_ack_intr___crc___width 1
-#define reg_eth_rw_ack_intr___crc___bit 0
-#define reg_eth_rw_ack_intr___align___lsb 1
-#define reg_eth_rw_ack_intr___align___width 1
-#define reg_eth_rw_ack_intr___align___bit 1
-#define reg_eth_rw_ack_intr___oversize___lsb 2
-#define reg_eth_rw_ack_intr___oversize___width 1
-#define reg_eth_rw_ack_intr___oversize___bit 2
-#define reg_eth_rw_ack_intr___congestion___lsb 3
-#define reg_eth_rw_ack_intr___congestion___width 1
-#define reg_eth_rw_ack_intr___congestion___bit 3
-#define reg_eth_rw_ack_intr___single_col___lsb 4
-#define reg_eth_rw_ack_intr___single_col___width 1
-#define reg_eth_rw_ack_intr___single_col___bit 4
-#define reg_eth_rw_ack_intr___mult_col___lsb 5
-#define reg_eth_rw_ack_intr___mult_col___width 1
-#define reg_eth_rw_ack_intr___mult_col___bit 5
-#define reg_eth_rw_ack_intr___late_col___lsb 6
-#define reg_eth_rw_ack_intr___late_col___width 1
-#define reg_eth_rw_ack_intr___late_col___bit 6
-#define reg_eth_rw_ack_intr___deferred___lsb 7
-#define reg_eth_rw_ack_intr___deferred___width 1
-#define reg_eth_rw_ack_intr___deferred___bit 7
-#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
-#define reg_eth_rw_ack_intr___carrier_loss___width 1
-#define reg_eth_rw_ack_intr___carrier_loss___bit 8
-#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
-#define reg_eth_rw_ack_intr___sqe_test_err___width 1
-#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
-#define reg_eth_rw_ack_intr___orun___lsb 10
-#define reg_eth_rw_ack_intr___orun___width 1
-#define reg_eth_rw_ack_intr___orun___bit 10
-#define reg_eth_rw_ack_intr___urun___lsb 11
-#define reg_eth_rw_ack_intr___urun___width 1
-#define reg_eth_rw_ack_intr___urun___bit 11
-#define reg_eth_rw_ack_intr___excessive_col___lsb 12
-#define reg_eth_rw_ack_intr___excessive_col___width 1
-#define reg_eth_rw_ack_intr___excessive_col___bit 12
-#define reg_eth_rw_ack_intr___mdio___lsb 13
-#define reg_eth_rw_ack_intr___mdio___width 1
-#define reg_eth_rw_ack_intr___mdio___bit 13
-#define reg_eth_rw_ack_intr_offset 80
-
-/* Register r_intr, scope eth, type r */
-#define reg_eth_r_intr___crc___lsb 0
-#define reg_eth_r_intr___crc___width 1
-#define reg_eth_r_intr___crc___bit 0
-#define reg_eth_r_intr___align___lsb 1
-#define reg_eth_r_intr___align___width 1
-#define reg_eth_r_intr___align___bit 1
-#define reg_eth_r_intr___oversize___lsb 2
-#define reg_eth_r_intr___oversize___width 1
-#define reg_eth_r_intr___oversize___bit 2
-#define reg_eth_r_intr___congestion___lsb 3
-#define reg_eth_r_intr___congestion___width 1
-#define reg_eth_r_intr___congestion___bit 3
-#define reg_eth_r_intr___single_col___lsb 4
-#define reg_eth_r_intr___single_col___width 1
-#define reg_eth_r_intr___single_col___bit 4
-#define reg_eth_r_intr___mult_col___lsb 5
-#define reg_eth_r_intr___mult_col___width 1
-#define reg_eth_r_intr___mult_col___bit 5
-#define reg_eth_r_intr___late_col___lsb 6
-#define reg_eth_r_intr___late_col___width 1
-#define reg_eth_r_intr___late_col___bit 6
-#define reg_eth_r_intr___deferred___lsb 7
-#define reg_eth_r_intr___deferred___width 1
-#define reg_eth_r_intr___deferred___bit 7
-#define reg_eth_r_intr___carrier_loss___lsb 8
-#define reg_eth_r_intr___carrier_loss___width 1
-#define reg_eth_r_intr___carrier_loss___bit 8
-#define reg_eth_r_intr___sqe_test_err___lsb 9
-#define reg_eth_r_intr___sqe_test_err___width 1
-#define reg_eth_r_intr___sqe_test_err___bit 9
-#define reg_eth_r_intr___orun___lsb 10
-#define reg_eth_r_intr___orun___width 1
-#define reg_eth_r_intr___orun___bit 10
-#define reg_eth_r_intr___urun___lsb 11
-#define reg_eth_r_intr___urun___width 1
-#define reg_eth_r_intr___urun___bit 11
-#define reg_eth_r_intr___excessive_col___lsb 12
-#define reg_eth_r_intr___excessive_col___width 1
-#define reg_eth_r_intr___excessive_col___bit 12
-#define reg_eth_r_intr___mdio___lsb 13
-#define reg_eth_r_intr___mdio___width 1
-#define reg_eth_r_intr___mdio___bit 13
-#define reg_eth_r_intr_offset 84
-
-/* Register r_masked_intr, scope eth, type r */
-#define reg_eth_r_masked_intr___crc___lsb 0
-#define reg_eth_r_masked_intr___crc___width 1
-#define reg_eth_r_masked_intr___crc___bit 0
-#define reg_eth_r_masked_intr___align___lsb 1
-#define reg_eth_r_masked_intr___align___width 1
-#define reg_eth_r_masked_intr___align___bit 1
-#define reg_eth_r_masked_intr___oversize___lsb 2
-#define reg_eth_r_masked_intr___oversize___width 1
-#define reg_eth_r_masked_intr___oversize___bit 2
-#define reg_eth_r_masked_intr___congestion___lsb 3
-#define reg_eth_r_masked_intr___congestion___width 1
-#define reg_eth_r_masked_intr___congestion___bit 3
-#define reg_eth_r_masked_intr___single_col___lsb 4
-#define reg_eth_r_masked_intr___single_col___width 1
-#define reg_eth_r_masked_intr___single_col___bit 4
-#define reg_eth_r_masked_intr___mult_col___lsb 5
-#define reg_eth_r_masked_intr___mult_col___width 1
-#define reg_eth_r_masked_intr___mult_col___bit 5
-#define reg_eth_r_masked_intr___late_col___lsb 6
-#define reg_eth_r_masked_intr___late_col___width 1
-#define reg_eth_r_masked_intr___late_col___bit 6
-#define reg_eth_r_masked_intr___deferred___lsb 7
-#define reg_eth_r_masked_intr___deferred___width 1
-#define reg_eth_r_masked_intr___deferred___bit 7
-#define reg_eth_r_masked_intr___carrier_loss___lsb 8
-#define reg_eth_r_masked_intr___carrier_loss___width 1
-#define reg_eth_r_masked_intr___carrier_loss___bit 8
-#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
-#define reg_eth_r_masked_intr___sqe_test_err___width 1
-#define reg_eth_r_masked_intr___sqe_test_err___bit 9
-#define reg_eth_r_masked_intr___orun___lsb 10
-#define reg_eth_r_masked_intr___orun___width 1
-#define reg_eth_r_masked_intr___orun___bit 10
-#define reg_eth_r_masked_intr___urun___lsb 11
-#define reg_eth_r_masked_intr___urun___width 1
-#define reg_eth_r_masked_intr___urun___bit 11
-#define reg_eth_r_masked_intr___excessive_col___lsb 12
-#define reg_eth_r_masked_intr___excessive_col___width 1
-#define reg_eth_r_masked_intr___excessive_col___bit 12
-#define reg_eth_r_masked_intr___mdio___lsb 13
-#define reg_eth_r_masked_intr___mdio___width 1
-#define reg_eth_r_masked_intr___mdio___bit 13
-#define reg_eth_r_masked_intr_offset 88
-
-
-/* Constants */
-#define regk_eth_discard 0x00000000
-#define regk_eth_ether 0x00000000
-#define regk_eth_full 0x00000001
-#define regk_eth_half 0x00000000
-#define regk_eth_hsh 0x00000001
-#define regk_eth_mii 0x00000001
-#define regk_eth_mii_clk 0x00000000
-#define regk_eth_mii_rec 0x00000002
-#define regk_eth_no 0x00000000
-#define regk_eth_rec 0x00000001
-#define regk_eth_rw_ga_hi_default 0x00000000
-#define regk_eth_rw_ga_lo_default 0x00000000
-#define regk_eth_rw_gen_ctrl_default 0x00000000
-#define regk_eth_rw_intr_mask_default 0x00000000
-#define regk_eth_rw_ma0_hi_default 0x00000000
-#define regk_eth_rw_ma0_lo_default 0x00000000
-#define regk_eth_rw_ma1_hi_default 0x00000000
-#define regk_eth_rw_ma1_lo_default 0x00000000
-#define regk_eth_rw_mgm_ctrl_default 0x00000000
-#define regk_eth_rw_test_ctrl_default 0x00000000
-#define regk_eth_size1518 0x00000000
-#define regk_eth_size1522 0x00000001
-#define regk_eth_yes 0x00000001
-#endif /* __eth_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 41bc2f83795c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/gio/rtl/gio_regs.r
- * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- * last modfied: Mon Apr 11 16:07:47 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
- * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 8
-#define reg_gio_rw_pa_dout_offset 0
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 8
-#define reg_gio_r_pa_din_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 8
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___pa0___lsb 0
-#define reg_gio_rw_intr_cfg___pa0___width 3
-#define reg_gio_rw_intr_cfg___pa1___lsb 3
-#define reg_gio_rw_intr_cfg___pa1___width 3
-#define reg_gio_rw_intr_cfg___pa2___lsb 6
-#define reg_gio_rw_intr_cfg___pa2___width 3
-#define reg_gio_rw_intr_cfg___pa3___lsb 9
-#define reg_gio_rw_intr_cfg___pa3___width 3
-#define reg_gio_rw_intr_cfg___pa4___lsb 12
-#define reg_gio_rw_intr_cfg___pa4___width 3
-#define reg_gio_rw_intr_cfg___pa5___lsb 15
-#define reg_gio_rw_intr_cfg___pa5___width 3
-#define reg_gio_rw_intr_cfg___pa6___lsb 18
-#define reg_gio_rw_intr_cfg___pa6___width 3
-#define reg_gio_rw_intr_cfg___pa7___lsb 21
-#define reg_gio_rw_intr_cfg___pa7___width 3
-#define reg_gio_rw_intr_cfg_offset 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___pa0___lsb 0
-#define reg_gio_rw_intr_mask___pa0___width 1
-#define reg_gio_rw_intr_mask___pa0___bit 0
-#define reg_gio_rw_intr_mask___pa1___lsb 1
-#define reg_gio_rw_intr_mask___pa1___width 1
-#define reg_gio_rw_intr_mask___pa1___bit 1
-#define reg_gio_rw_intr_mask___pa2___lsb 2
-#define reg_gio_rw_intr_mask___pa2___width 1
-#define reg_gio_rw_intr_mask___pa2___bit 2
-#define reg_gio_rw_intr_mask___pa3___lsb 3
-#define reg_gio_rw_intr_mask___pa3___width 1
-#define reg_gio_rw_intr_mask___pa3___bit 3
-#define reg_gio_rw_intr_mask___pa4___lsb 4
-#define reg_gio_rw_intr_mask___pa4___width 1
-#define reg_gio_rw_intr_mask___pa4___bit 4
-#define reg_gio_rw_intr_mask___pa5___lsb 5
-#define reg_gio_rw_intr_mask___pa5___width 1
-#define reg_gio_rw_intr_mask___pa5___bit 5
-#define reg_gio_rw_intr_mask___pa6___lsb 6
-#define reg_gio_rw_intr_mask___pa6___width 1
-#define reg_gio_rw_intr_mask___pa6___bit 6
-#define reg_gio_rw_intr_mask___pa7___lsb 7
-#define reg_gio_rw_intr_mask___pa7___width 1
-#define reg_gio_rw_intr_mask___pa7___bit 7
-#define reg_gio_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___pa0___lsb 0
-#define reg_gio_rw_ack_intr___pa0___width 1
-#define reg_gio_rw_ack_intr___pa0___bit 0
-#define reg_gio_rw_ack_intr___pa1___lsb 1
-#define reg_gio_rw_ack_intr___pa1___width 1
-#define reg_gio_rw_ack_intr___pa1___bit 1
-#define reg_gio_rw_ack_intr___pa2___lsb 2
-#define reg_gio_rw_ack_intr___pa2___width 1
-#define reg_gio_rw_ack_intr___pa2___bit 2
-#define reg_gio_rw_ack_intr___pa3___lsb 3
-#define reg_gio_rw_ack_intr___pa3___width 1
-#define reg_gio_rw_ack_intr___pa3___bit 3
-#define reg_gio_rw_ack_intr___pa4___lsb 4
-#define reg_gio_rw_ack_intr___pa4___width 1
-#define reg_gio_rw_ack_intr___pa4___bit 4
-#define reg_gio_rw_ack_intr___pa5___lsb 5
-#define reg_gio_rw_ack_intr___pa5___width 1
-#define reg_gio_rw_ack_intr___pa5___bit 5
-#define reg_gio_rw_ack_intr___pa6___lsb 6
-#define reg_gio_rw_ack_intr___pa6___width 1
-#define reg_gio_rw_ack_intr___pa6___bit 6
-#define reg_gio_rw_ack_intr___pa7___lsb 7
-#define reg_gio_rw_ack_intr___pa7___width 1
-#define reg_gio_rw_ack_intr___pa7___bit 7
-#define reg_gio_rw_ack_intr_offset 20
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___pa0___lsb 0
-#define reg_gio_r_intr___pa0___width 1
-#define reg_gio_r_intr___pa0___bit 0
-#define reg_gio_r_intr___pa1___lsb 1
-#define reg_gio_r_intr___pa1___width 1
-#define reg_gio_r_intr___pa1___bit 1
-#define reg_gio_r_intr___pa2___lsb 2
-#define reg_gio_r_intr___pa2___width 1
-#define reg_gio_r_intr___pa2___bit 2
-#define reg_gio_r_intr___pa3___lsb 3
-#define reg_gio_r_intr___pa3___width 1
-#define reg_gio_r_intr___pa3___bit 3
-#define reg_gio_r_intr___pa4___lsb 4
-#define reg_gio_r_intr___pa4___width 1
-#define reg_gio_r_intr___pa4___bit 4
-#define reg_gio_r_intr___pa5___lsb 5
-#define reg_gio_r_intr___pa5___width 1
-#define reg_gio_r_intr___pa5___bit 5
-#define reg_gio_r_intr___pa6___lsb 6
-#define reg_gio_r_intr___pa6___width 1
-#define reg_gio_r_intr___pa6___bit 6
-#define reg_gio_r_intr___pa7___lsb 7
-#define reg_gio_r_intr___pa7___width 1
-#define reg_gio_r_intr___pa7___bit 7
-#define reg_gio_r_intr_offset 24
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___pa0___lsb 0
-#define reg_gio_r_masked_intr___pa0___width 1
-#define reg_gio_r_masked_intr___pa0___bit 0
-#define reg_gio_r_masked_intr___pa1___lsb 1
-#define reg_gio_r_masked_intr___pa1___width 1
-#define reg_gio_r_masked_intr___pa1___bit 1
-#define reg_gio_r_masked_intr___pa2___lsb 2
-#define reg_gio_r_masked_intr___pa2___width 1
-#define reg_gio_r_masked_intr___pa2___bit 2
-#define reg_gio_r_masked_intr___pa3___lsb 3
-#define reg_gio_r_masked_intr___pa3___width 1
-#define reg_gio_r_masked_intr___pa3___bit 3
-#define reg_gio_r_masked_intr___pa4___lsb 4
-#define reg_gio_r_masked_intr___pa4___width 1
-#define reg_gio_r_masked_intr___pa4___bit 4
-#define reg_gio_r_masked_intr___pa5___lsb 5
-#define reg_gio_r_masked_intr___pa5___width 1
-#define reg_gio_r_masked_intr___pa5___bit 5
-#define reg_gio_r_masked_intr___pa6___lsb 6
-#define reg_gio_r_masked_intr___pa6___width 1
-#define reg_gio_r_masked_intr___pa6___bit 6
-#define reg_gio_r_masked_intr___pa7___lsb 7
-#define reg_gio_r_masked_intr___pa7___width 1
-#define reg_gio_r_masked_intr___pa7___bit 7
-#define reg_gio_r_masked_intr_offset 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 18
-#define reg_gio_rw_pb_dout_offset 32
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 18
-#define reg_gio_r_pb_din_offset 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 18
-#define reg_gio_rw_pb_oe_offset 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 18
-#define reg_gio_rw_pc_dout_offset 48
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 18
-#define reg_gio_r_pc_din_offset 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 18
-#define reg_gio_rw_pc_oe_offset 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-#define reg_gio_rw_pd_dout___data___lsb 0
-#define reg_gio_rw_pd_dout___data___width 18
-#define reg_gio_rw_pd_dout_offset 64
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 18
-#define reg_gio_r_pd_din_offset 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-#define reg_gio_rw_pd_oe___oe___lsb 0
-#define reg_gio_rw_pd_oe___oe___width 18
-#define reg_gio_rw_pd_oe_offset 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-#define reg_gio_rw_pe_dout___data___lsb 0
-#define reg_gio_rw_pe_dout___data___width 18
-#define reg_gio_rw_pe_dout_offset 80
-
-/* Register r_pe_din, scope gio, type r */
-#define reg_gio_r_pe_din___data___lsb 0
-#define reg_gio_r_pe_din___data___width 18
-#define reg_gio_r_pe_din_offset 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-#define reg_gio_rw_pe_oe___oe___lsb 0
-#define reg_gio_rw_pe_oe___oe___width 18
-#define reg_gio_rw_pe_oe_offset 88
-
-
-/* Constants */
-#define regk_gio_anyedge 0x00000007
-#define regk_gio_hi 0x00000001
-#define regk_gio_lo 0x00000002
-#define regk_gio_negedge 0x00000006
-#define regk_gio_no 0x00000000
-#define regk_gio_off 0x00000000
-#define regk_gio_posedge 0x00000005
-#define regk_gio_rw_intr_cfg_default 0x00000000
-#define regk_gio_rw_intr_mask_default 0x00000000
-#define regk_gio_rw_pa_oe_default 0x00000000
-#define regk_gio_rw_pb_oe_default 0x00000000
-#define regk_gio_rw_pc_oe_default 0x00000000
-#define regk_gio_rw_pd_oe_default 0x00000000
-#define regk_gio_rw_pe_oe_default 0x00000000
-#define regk_gio_set 0x00000003
-#define regk_gio_yes 0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h
deleted file mode 100644
index e371052fa1bc..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define MEMARB_INTR_VECT 0x31
-#define GEN_IO_INTR_VECT 0x32
-#define IOP0_INTR_VECT 0x33
-#define IOP1_INTR_VECT 0x34
-#define IOP2_INTR_VECT 0x35
-#define IOP3_INTR_VECT 0x36
-#define DMA0_INTR_VECT 0x37
-#define DMA1_INTR_VECT 0x38
-#define DMA2_INTR_VECT 0x39
-#define DMA3_INTR_VECT 0x3a
-#define DMA4_INTR_VECT 0x3b
-#define DMA5_INTR_VECT 0x3c
-#define DMA6_INTR_VECT 0x3d
-#define DMA7_INTR_VECT 0x3e
-#define DMA8_INTR_VECT 0x3f
-#define DMA9_INTR_VECT 0x40
-#define ATA_INTR_VECT 0x41
-#define SSER0_INTR_VECT 0x42
-#define SSER1_INTR_VECT 0x43
-#define SER0_INTR_VECT 0x44
-#define SER1_INTR_VECT 0x45
-#define SER2_INTR_VECT 0x46
-#define SER3_INTR_VECT 0x47
-#define P21_INTR_VECT 0x48
-#define ETH0_INTR_VECT 0x49
-#define ETH1_INTR_VECT 0x4a
-#define TIMER_INTR_VECT 0x4b
-#define BIF_ARB_INTR_VECT 0x4c
-#define BIF_DMA_INTR_VECT 0x4d
-#define EXT_INTR_VECT 0x4e
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h
deleted file mode 100644
index 8d0c788b286b..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __intr_vect_defs_asm_h
-#define __intr_vect_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
- * last modfied: Mon Apr 11 16:08:03 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mask, scope intr_vect, type rw */
-#define reg_intr_vect_rw_mask___memarb___lsb 0
-#define reg_intr_vect_rw_mask___memarb___width 1
-#define reg_intr_vect_rw_mask___memarb___bit 0
-#define reg_intr_vect_rw_mask___gen_io___lsb 1
-#define reg_intr_vect_rw_mask___gen_io___width 1
-#define reg_intr_vect_rw_mask___gen_io___bit 1
-#define reg_intr_vect_rw_mask___iop0___lsb 2
-#define reg_intr_vect_rw_mask___iop0___width 1
-#define reg_intr_vect_rw_mask___iop0___bit 2
-#define reg_intr_vect_rw_mask___iop1___lsb 3
-#define reg_intr_vect_rw_mask___iop1___width 1
-#define reg_intr_vect_rw_mask___iop1___bit 3
-#define reg_intr_vect_rw_mask___iop2___lsb 4
-#define reg_intr_vect_rw_mask___iop2___width 1
-#define reg_intr_vect_rw_mask___iop2___bit 4
-#define reg_intr_vect_rw_mask___iop3___lsb 5
-#define reg_intr_vect_rw_mask___iop3___width 1
-#define reg_intr_vect_rw_mask___iop3___bit 5
-#define reg_intr_vect_rw_mask___dma0___lsb 6
-#define reg_intr_vect_rw_mask___dma0___width 1
-#define reg_intr_vect_rw_mask___dma0___bit 6
-#define reg_intr_vect_rw_mask___dma1___lsb 7
-#define reg_intr_vect_rw_mask___dma1___width 1
-#define reg_intr_vect_rw_mask___dma1___bit 7
-#define reg_intr_vect_rw_mask___dma2___lsb 8
-#define reg_intr_vect_rw_mask___dma2___width 1
-#define reg_intr_vect_rw_mask___dma2___bit 8
-#define reg_intr_vect_rw_mask___dma3___lsb 9
-#define reg_intr_vect_rw_mask___dma3___width 1
-#define reg_intr_vect_rw_mask___dma3___bit 9
-#define reg_intr_vect_rw_mask___dma4___lsb 10
-#define reg_intr_vect_rw_mask___dma4___width 1
-#define reg_intr_vect_rw_mask___dma4___bit 10
-#define reg_intr_vect_rw_mask___dma5___lsb 11
-#define reg_intr_vect_rw_mask___dma5___width 1
-#define reg_intr_vect_rw_mask___dma5___bit 11
-#define reg_intr_vect_rw_mask___dma6___lsb 12
-#define reg_intr_vect_rw_mask___dma6___width 1
-#define reg_intr_vect_rw_mask___dma6___bit 12
-#define reg_intr_vect_rw_mask___dma7___lsb 13
-#define reg_intr_vect_rw_mask___dma7___width 1
-#define reg_intr_vect_rw_mask___dma7___bit 13
-#define reg_intr_vect_rw_mask___dma8___lsb 14
-#define reg_intr_vect_rw_mask___dma8___width 1
-#define reg_intr_vect_rw_mask___dma8___bit 14
-#define reg_intr_vect_rw_mask___dma9___lsb 15
-#define reg_intr_vect_rw_mask___dma9___width 1
-#define reg_intr_vect_rw_mask___dma9___bit 15
-#define reg_intr_vect_rw_mask___ata___lsb 16
-#define reg_intr_vect_rw_mask___ata___width 1
-#define reg_intr_vect_rw_mask___ata___bit 16
-#define reg_intr_vect_rw_mask___sser0___lsb 17
-#define reg_intr_vect_rw_mask___sser0___width 1
-#define reg_intr_vect_rw_mask___sser0___bit 17
-#define reg_intr_vect_rw_mask___sser1___lsb 18
-#define reg_intr_vect_rw_mask___sser1___width 1
-#define reg_intr_vect_rw_mask___sser1___bit 18
-#define reg_intr_vect_rw_mask___ser0___lsb 19
-#define reg_intr_vect_rw_mask___ser0___width 1
-#define reg_intr_vect_rw_mask___ser0___bit 19
-#define reg_intr_vect_rw_mask___ser1___lsb 20
-#define reg_intr_vect_rw_mask___ser1___width 1
-#define reg_intr_vect_rw_mask___ser1___bit 20
-#define reg_intr_vect_rw_mask___ser2___lsb 21
-#define reg_intr_vect_rw_mask___ser2___width 1
-#define reg_intr_vect_rw_mask___ser2___bit 21
-#define reg_intr_vect_rw_mask___ser3___lsb 22
-#define reg_intr_vect_rw_mask___ser3___width 1
-#define reg_intr_vect_rw_mask___ser3___bit 22
-#define reg_intr_vect_rw_mask___p21___lsb 23
-#define reg_intr_vect_rw_mask___p21___width 1
-#define reg_intr_vect_rw_mask___p21___bit 23
-#define reg_intr_vect_rw_mask___eth0___lsb 24
-#define reg_intr_vect_rw_mask___eth0___width 1
-#define reg_intr_vect_rw_mask___eth0___bit 24
-#define reg_intr_vect_rw_mask___eth1___lsb 25
-#define reg_intr_vect_rw_mask___eth1___width 1
-#define reg_intr_vect_rw_mask___eth1___bit 25
-#define reg_intr_vect_rw_mask___timer___lsb 26
-#define reg_intr_vect_rw_mask___timer___width 1
-#define reg_intr_vect_rw_mask___timer___bit 26
-#define reg_intr_vect_rw_mask___bif_arb___lsb 27
-#define reg_intr_vect_rw_mask___bif_arb___width 1
-#define reg_intr_vect_rw_mask___bif_arb___bit 27
-#define reg_intr_vect_rw_mask___bif_dma___lsb 28
-#define reg_intr_vect_rw_mask___bif_dma___width 1
-#define reg_intr_vect_rw_mask___bif_dma___bit 28
-#define reg_intr_vect_rw_mask___ext___lsb 29
-#define reg_intr_vect_rw_mask___ext___width 1
-#define reg_intr_vect_rw_mask___ext___bit 29
-#define reg_intr_vect_rw_mask_offset 0
-
-/* Register r_vect, scope intr_vect, type r */
-#define reg_intr_vect_r_vect___memarb___lsb 0
-#define reg_intr_vect_r_vect___memarb___width 1
-#define reg_intr_vect_r_vect___memarb___bit 0
-#define reg_intr_vect_r_vect___gen_io___lsb 1
-#define reg_intr_vect_r_vect___gen_io___width 1
-#define reg_intr_vect_r_vect___gen_io___bit 1
-#define reg_intr_vect_r_vect___iop0___lsb 2
-#define reg_intr_vect_r_vect___iop0___width 1
-#define reg_intr_vect_r_vect___iop0___bit 2
-#define reg_intr_vect_r_vect___iop1___lsb 3
-#define reg_intr_vect_r_vect___iop1___width 1
-#define reg_intr_vect_r_vect___iop1___bit 3
-#define reg_intr_vect_r_vect___iop2___lsb 4
-#define reg_intr_vect_r_vect___iop2___width 1
-#define reg_intr_vect_r_vect___iop2___bit 4
-#define reg_intr_vect_r_vect___iop3___lsb 5
-#define reg_intr_vect_r_vect___iop3___width 1
-#define reg_intr_vect_r_vect___iop3___bit 5
-#define reg_intr_vect_r_vect___dma0___lsb 6
-#define reg_intr_vect_r_vect___dma0___width 1
-#define reg_intr_vect_r_vect___dma0___bit 6
-#define reg_intr_vect_r_vect___dma1___lsb 7
-#define reg_intr_vect_r_vect___dma1___width 1
-#define reg_intr_vect_r_vect___dma1___bit 7
-#define reg_intr_vect_r_vect___dma2___lsb 8
-#define reg_intr_vect_r_vect___dma2___width 1
-#define reg_intr_vect_r_vect___dma2___bit 8
-#define reg_intr_vect_r_vect___dma3___lsb 9
-#define reg_intr_vect_r_vect___dma3___width 1
-#define reg_intr_vect_r_vect___dma3___bit 9
-#define reg_intr_vect_r_vect___dma4___lsb 10
-#define reg_intr_vect_r_vect___dma4___width 1
-#define reg_intr_vect_r_vect___dma4___bit 10
-#define reg_intr_vect_r_vect___dma5___lsb 11
-#define reg_intr_vect_r_vect___dma5___width 1
-#define reg_intr_vect_r_vect___dma5___bit 11
-#define reg_intr_vect_r_vect___dma6___lsb 12
-#define reg_intr_vect_r_vect___dma6___width 1
-#define reg_intr_vect_r_vect___dma6___bit 12
-#define reg_intr_vect_r_vect___dma7___lsb 13
-#define reg_intr_vect_r_vect___dma7___width 1
-#define reg_intr_vect_r_vect___dma7___bit 13
-#define reg_intr_vect_r_vect___dma8___lsb 14
-#define reg_intr_vect_r_vect___dma8___width 1
-#define reg_intr_vect_r_vect___dma8___bit 14
-#define reg_intr_vect_r_vect___dma9___lsb 15
-#define reg_intr_vect_r_vect___dma9___width 1
-#define reg_intr_vect_r_vect___dma9___bit 15
-#define reg_intr_vect_r_vect___ata___lsb 16
-#define reg_intr_vect_r_vect___ata___width 1
-#define reg_intr_vect_r_vect___ata___bit 16
-#define reg_intr_vect_r_vect___sser0___lsb 17
-#define reg_intr_vect_r_vect___sser0___width 1
-#define reg_intr_vect_r_vect___sser0___bit 17
-#define reg_intr_vect_r_vect___sser1___lsb 18
-#define reg_intr_vect_r_vect___sser1___width 1
-#define reg_intr_vect_r_vect___sser1___bit 18
-#define reg_intr_vect_r_vect___ser0___lsb 19
-#define reg_intr_vect_r_vect___ser0___width 1
-#define reg_intr_vect_r_vect___ser0___bit 19
-#define reg_intr_vect_r_vect___ser1___lsb 20
-#define reg_intr_vect_r_vect___ser1___width 1
-#define reg_intr_vect_r_vect___ser1___bit 20
-#define reg_intr_vect_r_vect___ser2___lsb 21
-#define reg_intr_vect_r_vect___ser2___width 1
-#define reg_intr_vect_r_vect___ser2___bit 21
-#define reg_intr_vect_r_vect___ser3___lsb 22
-#define reg_intr_vect_r_vect___ser3___width 1
-#define reg_intr_vect_r_vect___ser3___bit 22
-#define reg_intr_vect_r_vect___p21___lsb 23
-#define reg_intr_vect_r_vect___p21___width 1
-#define reg_intr_vect_r_vect___p21___bit 23
-#define reg_intr_vect_r_vect___eth0___lsb 24
-#define reg_intr_vect_r_vect___eth0___width 1
-#define reg_intr_vect_r_vect___eth0___bit 24
-#define reg_intr_vect_r_vect___eth1___lsb 25
-#define reg_intr_vect_r_vect___eth1___width 1
-#define reg_intr_vect_r_vect___eth1___bit 25
-#define reg_intr_vect_r_vect___timer___lsb 26
-#define reg_intr_vect_r_vect___timer___width 1
-#define reg_intr_vect_r_vect___timer___bit 26
-#define reg_intr_vect_r_vect___bif_arb___lsb 27
-#define reg_intr_vect_r_vect___bif_arb___width 1
-#define reg_intr_vect_r_vect___bif_arb___bit 27
-#define reg_intr_vect_r_vect___bif_dma___lsb 28
-#define reg_intr_vect_r_vect___bif_dma___width 1
-#define reg_intr_vect_r_vect___bif_dma___bit 28
-#define reg_intr_vect_r_vect___ext___lsb 29
-#define reg_intr_vect_r_vect___ext___width 1
-#define reg_intr_vect_r_vect___ext___bit 29
-#define reg_intr_vect_r_vect_offset 4
-
-/* Register r_masked_vect, scope intr_vect, type r */
-#define reg_intr_vect_r_masked_vect___memarb___lsb 0
-#define reg_intr_vect_r_masked_vect___memarb___width 1
-#define reg_intr_vect_r_masked_vect___memarb___bit 0
-#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
-#define reg_intr_vect_r_masked_vect___gen_io___width 1
-#define reg_intr_vect_r_masked_vect___gen_io___bit 1
-#define reg_intr_vect_r_masked_vect___iop0___lsb 2
-#define reg_intr_vect_r_masked_vect___iop0___width 1
-#define reg_intr_vect_r_masked_vect___iop0___bit 2
-#define reg_intr_vect_r_masked_vect___iop1___lsb 3
-#define reg_intr_vect_r_masked_vect___iop1___width 1
-#define reg_intr_vect_r_masked_vect___iop1___bit 3
-#define reg_intr_vect_r_masked_vect___iop2___lsb 4
-#define reg_intr_vect_r_masked_vect___iop2___width 1
-#define reg_intr_vect_r_masked_vect___iop2___bit 4
-#define reg_intr_vect_r_masked_vect___iop3___lsb 5
-#define reg_intr_vect_r_masked_vect___iop3___width 1
-#define reg_intr_vect_r_masked_vect___iop3___bit 5
-#define reg_intr_vect_r_masked_vect___dma0___lsb 6
-#define reg_intr_vect_r_masked_vect___dma0___width 1
-#define reg_intr_vect_r_masked_vect___dma0___bit 6
-#define reg_intr_vect_r_masked_vect___dma1___lsb 7
-#define reg_intr_vect_r_masked_vect___dma1___width 1
-#define reg_intr_vect_r_masked_vect___dma1___bit 7
-#define reg_intr_vect_r_masked_vect___dma2___lsb 8
-#define reg_intr_vect_r_masked_vect___dma2___width 1
-#define reg_intr_vect_r_masked_vect___dma2___bit 8
-#define reg_intr_vect_r_masked_vect___dma3___lsb 9
-#define reg_intr_vect_r_masked_vect___dma3___width 1
-#define reg_intr_vect_r_masked_vect___dma3___bit 9
-#define reg_intr_vect_r_masked_vect___dma4___lsb 10
-#define reg_intr_vect_r_masked_vect___dma4___width 1
-#define reg_intr_vect_r_masked_vect___dma4___bit 10
-#define reg_intr_vect_r_masked_vect___dma5___lsb 11
-#define reg_intr_vect_r_masked_vect___dma5___width 1
-#define reg_intr_vect_r_masked_vect___dma5___bit 11
-#define reg_intr_vect_r_masked_vect___dma6___lsb 12
-#define reg_intr_vect_r_masked_vect___dma6___width 1
-#define reg_intr_vect_r_masked_vect___dma6___bit 12
-#define reg_intr_vect_r_masked_vect___dma7___lsb 13
-#define reg_intr_vect_r_masked_vect___dma7___width 1
-#define reg_intr_vect_r_masked_vect___dma7___bit 13
-#define reg_intr_vect_r_masked_vect___dma8___lsb 14
-#define reg_intr_vect_r_masked_vect___dma8___width 1
-#define reg_intr_vect_r_masked_vect___dma8___bit 14
-#define reg_intr_vect_r_masked_vect___dma9___lsb 15
-#define reg_intr_vect_r_masked_vect___dma9___width 1
-#define reg_intr_vect_r_masked_vect___dma9___bit 15
-#define reg_intr_vect_r_masked_vect___ata___lsb 16
-#define reg_intr_vect_r_masked_vect___ata___width 1
-#define reg_intr_vect_r_masked_vect___ata___bit 16
-#define reg_intr_vect_r_masked_vect___sser0___lsb 17
-#define reg_intr_vect_r_masked_vect___sser0___width 1
-#define reg_intr_vect_r_masked_vect___sser0___bit 17
-#define reg_intr_vect_r_masked_vect___sser1___lsb 18
-#define reg_intr_vect_r_masked_vect___sser1___width 1
-#define reg_intr_vect_r_masked_vect___sser1___bit 18
-#define reg_intr_vect_r_masked_vect___ser0___lsb 19
-#define reg_intr_vect_r_masked_vect___ser0___width 1
-#define reg_intr_vect_r_masked_vect___ser0___bit 19
-#define reg_intr_vect_r_masked_vect___ser1___lsb 20
-#define reg_intr_vect_r_masked_vect___ser1___width 1
-#define reg_intr_vect_r_masked_vect___ser1___bit 20
-#define reg_intr_vect_r_masked_vect___ser2___lsb 21
-#define reg_intr_vect_r_masked_vect___ser2___width 1
-#define reg_intr_vect_r_masked_vect___ser2___bit 21
-#define reg_intr_vect_r_masked_vect___ser3___lsb 22
-#define reg_intr_vect_r_masked_vect___ser3___width 1
-#define reg_intr_vect_r_masked_vect___ser3___bit 22
-#define reg_intr_vect_r_masked_vect___p21___lsb 23
-#define reg_intr_vect_r_masked_vect___p21___width 1
-#define reg_intr_vect_r_masked_vect___p21___bit 23
-#define reg_intr_vect_r_masked_vect___eth0___lsb 24
-#define reg_intr_vect_r_masked_vect___eth0___width 1
-#define reg_intr_vect_r_masked_vect___eth0___bit 24
-#define reg_intr_vect_r_masked_vect___eth1___lsb 25
-#define reg_intr_vect_r_masked_vect___eth1___width 1
-#define reg_intr_vect_r_masked_vect___eth1___bit 25
-#define reg_intr_vect_r_masked_vect___timer___lsb 26
-#define reg_intr_vect_r_masked_vect___timer___width 1
-#define reg_intr_vect_r_masked_vect___timer___bit 26
-#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
-#define reg_intr_vect_r_masked_vect___bif_arb___width 1
-#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
-#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
-#define reg_intr_vect_r_masked_vect___bif_dma___width 1
-#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
-#define reg_intr_vect_r_masked_vect___ext___lsb 29
-#define reg_intr_vect_r_masked_vect___ext___width 1
-#define reg_intr_vect_r_masked_vect___ext___bit 29
-#define reg_intr_vect_r_masked_vect_offset 8
-
-/* Register r_nmi, scope intr_vect, type r */
-#define reg_intr_vect_r_nmi___ext___lsb 0
-#define reg_intr_vect_r_nmi___ext___width 1
-#define reg_intr_vect_r_nmi___ext___bit 0
-#define reg_intr_vect_r_nmi___watchdog___lsb 1
-#define reg_intr_vect_r_nmi___watchdog___width 1
-#define reg_intr_vect_r_nmi___watchdog___bit 1
-#define reg_intr_vect_r_nmi_offset 12
-
-/* Register r_guru, scope intr_vect, type r */
-#define reg_intr_vect_r_guru___jtag___lsb 0
-#define reg_intr_vect_r_guru___jtag___width 1
-#define reg_intr_vect_r_guru___jtag___bit 0
-#define reg_intr_vect_r_guru_offset 16
-
-
-/* Constants */
-#define regk_intr_vect_off 0x00000000
-#define regk_intr_vect_on 0x00000001
-#define regk_intr_vect_rw_mask_default 0x00000000
-#endif /* __intr_vect_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h
deleted file mode 100644
index f624468346af..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __irq_nmi_defs_asm_h
-#define __irq_nmi_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/irq_nmi.r
- * id: <not found>
- * last modfied: Thu Jan 22 09:22:43 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
- * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cmd, scope irq_nmi, type rw */
-#define reg_irq_nmi_rw_cmd___delay___lsb 0
-#define reg_irq_nmi_rw_cmd___delay___width 16
-#define reg_irq_nmi_rw_cmd___op___lsb 16
-#define reg_irq_nmi_rw_cmd___op___width 2
-#define reg_irq_nmi_rw_cmd_offset 0
-
-
-/* Constants */
-#define regk_irq_nmi_ack_irq 0x00000002
-#define regk_irq_nmi_ack_nmi 0x00000003
-#define regk_irq_nmi_irq 0x00000000
-#define regk_irq_nmi_nmi 0x00000001
-#endif /* __irq_nmi_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h
deleted file mode 100644
index 6a5ce2141860..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_defs_asm_h
-#define __marb_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-#define reg_marb_rw_int_slots___owner___lsb 0
-#define reg_marb_rw_int_slots___owner___width 4
-#define reg_marb_rw_int_slots_offset 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-#define reg_marb_rw_ext_slots___owner___lsb 0
-#define reg_marb_rw_ext_slots___owner___width 4
-#define reg_marb_rw_ext_slots_offset 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-#define reg_marb_rw_regs_slots___owner___lsb 0
-#define reg_marb_rw_regs_slots___owner___width 4
-#define reg_marb_rw_regs_slots_offset 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-#define reg_marb_rw_intr_mask___bp0___lsb 0
-#define reg_marb_rw_intr_mask___bp0___width 1
-#define reg_marb_rw_intr_mask___bp0___bit 0
-#define reg_marb_rw_intr_mask___bp1___lsb 1
-#define reg_marb_rw_intr_mask___bp1___width 1
-#define reg_marb_rw_intr_mask___bp1___bit 1
-#define reg_marb_rw_intr_mask___bp2___lsb 2
-#define reg_marb_rw_intr_mask___bp2___width 1
-#define reg_marb_rw_intr_mask___bp2___bit 2
-#define reg_marb_rw_intr_mask___bp3___lsb 3
-#define reg_marb_rw_intr_mask___bp3___width 1
-#define reg_marb_rw_intr_mask___bp3___bit 3
-#define reg_marb_rw_intr_mask_offset 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-#define reg_marb_rw_ack_intr___bp0___lsb 0
-#define reg_marb_rw_ack_intr___bp0___width 1
-#define reg_marb_rw_ack_intr___bp0___bit 0
-#define reg_marb_rw_ack_intr___bp1___lsb 1
-#define reg_marb_rw_ack_intr___bp1___width 1
-#define reg_marb_rw_ack_intr___bp1___bit 1
-#define reg_marb_rw_ack_intr___bp2___lsb 2
-#define reg_marb_rw_ack_intr___bp2___width 1
-#define reg_marb_rw_ack_intr___bp2___bit 2
-#define reg_marb_rw_ack_intr___bp3___lsb 3
-#define reg_marb_rw_ack_intr___bp3___width 1
-#define reg_marb_rw_ack_intr___bp3___bit 3
-#define reg_marb_rw_ack_intr_offset 532
-
-/* Register r_intr, scope marb, type r */
-#define reg_marb_r_intr___bp0___lsb 0
-#define reg_marb_r_intr___bp0___width 1
-#define reg_marb_r_intr___bp0___bit 0
-#define reg_marb_r_intr___bp1___lsb 1
-#define reg_marb_r_intr___bp1___width 1
-#define reg_marb_r_intr___bp1___bit 1
-#define reg_marb_r_intr___bp2___lsb 2
-#define reg_marb_r_intr___bp2___width 1
-#define reg_marb_r_intr___bp2___bit 2
-#define reg_marb_r_intr___bp3___lsb 3
-#define reg_marb_r_intr___bp3___width 1
-#define reg_marb_r_intr___bp3___bit 3
-#define reg_marb_r_intr_offset 536
-
-/* Register r_masked_intr, scope marb, type r */
-#define reg_marb_r_masked_intr___bp0___lsb 0
-#define reg_marb_r_masked_intr___bp0___width 1
-#define reg_marb_r_masked_intr___bp0___bit 0
-#define reg_marb_r_masked_intr___bp1___lsb 1
-#define reg_marb_r_masked_intr___bp1___width 1
-#define reg_marb_r_masked_intr___bp1___bit 1
-#define reg_marb_r_masked_intr___bp2___lsb 2
-#define reg_marb_r_masked_intr___bp2___width 1
-#define reg_marb_r_masked_intr___bp2___bit 2
-#define reg_marb_r_masked_intr___bp3___lsb 3
-#define reg_marb_r_masked_intr___bp3___width 1
-#define reg_marb_r_masked_intr___bp3___bit 3
-#define reg_marb_r_masked_intr_offset 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-#define reg_marb_rw_stop_mask___dma0___lsb 0
-#define reg_marb_rw_stop_mask___dma0___width 1
-#define reg_marb_rw_stop_mask___dma0___bit 0
-#define reg_marb_rw_stop_mask___dma1___lsb 1
-#define reg_marb_rw_stop_mask___dma1___width 1
-#define reg_marb_rw_stop_mask___dma1___bit 1
-#define reg_marb_rw_stop_mask___dma2___lsb 2
-#define reg_marb_rw_stop_mask___dma2___width 1
-#define reg_marb_rw_stop_mask___dma2___bit 2
-#define reg_marb_rw_stop_mask___dma3___lsb 3
-#define reg_marb_rw_stop_mask___dma3___width 1
-#define reg_marb_rw_stop_mask___dma3___bit 3
-#define reg_marb_rw_stop_mask___dma4___lsb 4
-#define reg_marb_rw_stop_mask___dma4___width 1
-#define reg_marb_rw_stop_mask___dma4___bit 4
-#define reg_marb_rw_stop_mask___dma5___lsb 5
-#define reg_marb_rw_stop_mask___dma5___width 1
-#define reg_marb_rw_stop_mask___dma5___bit 5
-#define reg_marb_rw_stop_mask___dma6___lsb 6
-#define reg_marb_rw_stop_mask___dma6___width 1
-#define reg_marb_rw_stop_mask___dma6___bit 6
-#define reg_marb_rw_stop_mask___dma7___lsb 7
-#define reg_marb_rw_stop_mask___dma7___width 1
-#define reg_marb_rw_stop_mask___dma7___bit 7
-#define reg_marb_rw_stop_mask___dma8___lsb 8
-#define reg_marb_rw_stop_mask___dma8___width 1
-#define reg_marb_rw_stop_mask___dma8___bit 8
-#define reg_marb_rw_stop_mask___dma9___lsb 9
-#define reg_marb_rw_stop_mask___dma9___width 1
-#define reg_marb_rw_stop_mask___dma9___bit 9
-#define reg_marb_rw_stop_mask___cpui___lsb 10
-#define reg_marb_rw_stop_mask___cpui___width 1
-#define reg_marb_rw_stop_mask___cpui___bit 10
-#define reg_marb_rw_stop_mask___cpud___lsb 11
-#define reg_marb_rw_stop_mask___cpud___width 1
-#define reg_marb_rw_stop_mask___cpud___bit 11
-#define reg_marb_rw_stop_mask___iop___lsb 12
-#define reg_marb_rw_stop_mask___iop___width 1
-#define reg_marb_rw_stop_mask___iop___bit 12
-#define reg_marb_rw_stop_mask___slave___lsb 13
-#define reg_marb_rw_stop_mask___slave___width 1
-#define reg_marb_rw_stop_mask___slave___bit 13
-#define reg_marb_rw_stop_mask_offset 544
-
-/* Register r_stopped, scope marb, type r */
-#define reg_marb_r_stopped___dma0___lsb 0
-#define reg_marb_r_stopped___dma0___width 1
-#define reg_marb_r_stopped___dma0___bit 0
-#define reg_marb_r_stopped___dma1___lsb 1
-#define reg_marb_r_stopped___dma1___width 1
-#define reg_marb_r_stopped___dma1___bit 1
-#define reg_marb_r_stopped___dma2___lsb 2
-#define reg_marb_r_stopped___dma2___width 1
-#define reg_marb_r_stopped___dma2___bit 2
-#define reg_marb_r_stopped___dma3___lsb 3
-#define reg_marb_r_stopped___dma3___width 1
-#define reg_marb_r_stopped___dma3___bit 3
-#define reg_marb_r_stopped___dma4___lsb 4
-#define reg_marb_r_stopped___dma4___width 1
-#define reg_marb_r_stopped___dma4___bit 4
-#define reg_marb_r_stopped___dma5___lsb 5
-#define reg_marb_r_stopped___dma5___width 1
-#define reg_marb_r_stopped___dma5___bit 5
-#define reg_marb_r_stopped___dma6___lsb 6
-#define reg_marb_r_stopped___dma6___width 1
-#define reg_marb_r_stopped___dma6___bit 6
-#define reg_marb_r_stopped___dma7___lsb 7
-#define reg_marb_r_stopped___dma7___width 1
-#define reg_marb_r_stopped___dma7___bit 7
-#define reg_marb_r_stopped___dma8___lsb 8
-#define reg_marb_r_stopped___dma8___width 1
-#define reg_marb_r_stopped___dma8___bit 8
-#define reg_marb_r_stopped___dma9___lsb 9
-#define reg_marb_r_stopped___dma9___width 1
-#define reg_marb_r_stopped___dma9___bit 9
-#define reg_marb_r_stopped___cpui___lsb 10
-#define reg_marb_r_stopped___cpui___width 1
-#define reg_marb_r_stopped___cpui___bit 10
-#define reg_marb_r_stopped___cpud___lsb 11
-#define reg_marb_r_stopped___cpud___width 1
-#define reg_marb_r_stopped___cpud___bit 11
-#define reg_marb_r_stopped___iop___lsb 12
-#define reg_marb_r_stopped___iop___width 1
-#define reg_marb_r_stopped___iop___bit 12
-#define reg_marb_r_stopped___slave___lsb 13
-#define reg_marb_r_stopped___slave___width 1
-#define reg_marb_r_stopped___slave___bit 13
-#define reg_marb_r_stopped_offset 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-#define reg_marb_rw_no_snoop___dma0___lsb 0
-#define reg_marb_rw_no_snoop___dma0___width 1
-#define reg_marb_rw_no_snoop___dma0___bit 0
-#define reg_marb_rw_no_snoop___dma1___lsb 1
-#define reg_marb_rw_no_snoop___dma1___width 1
-#define reg_marb_rw_no_snoop___dma1___bit 1
-#define reg_marb_rw_no_snoop___dma2___lsb 2
-#define reg_marb_rw_no_snoop___dma2___width 1
-#define reg_marb_rw_no_snoop___dma2___bit 2
-#define reg_marb_rw_no_snoop___dma3___lsb 3
-#define reg_marb_rw_no_snoop___dma3___width 1
-#define reg_marb_rw_no_snoop___dma3___bit 3
-#define reg_marb_rw_no_snoop___dma4___lsb 4
-#define reg_marb_rw_no_snoop___dma4___width 1
-#define reg_marb_rw_no_snoop___dma4___bit 4
-#define reg_marb_rw_no_snoop___dma5___lsb 5
-#define reg_marb_rw_no_snoop___dma5___width 1
-#define reg_marb_rw_no_snoop___dma5___bit 5
-#define reg_marb_rw_no_snoop___dma6___lsb 6
-#define reg_marb_rw_no_snoop___dma6___width 1
-#define reg_marb_rw_no_snoop___dma6___bit 6
-#define reg_marb_rw_no_snoop___dma7___lsb 7
-#define reg_marb_rw_no_snoop___dma7___width 1
-#define reg_marb_rw_no_snoop___dma7___bit 7
-#define reg_marb_rw_no_snoop___dma8___lsb 8
-#define reg_marb_rw_no_snoop___dma8___width 1
-#define reg_marb_rw_no_snoop___dma8___bit 8
-#define reg_marb_rw_no_snoop___dma9___lsb 9
-#define reg_marb_rw_no_snoop___dma9___width 1
-#define reg_marb_rw_no_snoop___dma9___bit 9
-#define reg_marb_rw_no_snoop___cpui___lsb 10
-#define reg_marb_rw_no_snoop___cpui___width 1
-#define reg_marb_rw_no_snoop___cpui___bit 10
-#define reg_marb_rw_no_snoop___cpud___lsb 11
-#define reg_marb_rw_no_snoop___cpud___width 1
-#define reg_marb_rw_no_snoop___cpud___bit 11
-#define reg_marb_rw_no_snoop___iop___lsb 12
-#define reg_marb_rw_no_snoop___iop___width 1
-#define reg_marb_rw_no_snoop___iop___bit 12
-#define reg_marb_rw_no_snoop___slave___lsb 13
-#define reg_marb_rw_no_snoop___slave___width 1
-#define reg_marb_rw_no_snoop___slave___bit 13
-#define reg_marb_rw_no_snoop_offset 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
-#define reg_marb_rw_no_snoop_rq___cpui___width 1
-#define reg_marb_rw_no_snoop_rq___cpui___bit 10
-#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
-#define reg_marb_rw_no_snoop_rq___cpud___width 1
-#define reg_marb_rw_no_snoop_rq___cpud___bit 11
-#define reg_marb_rw_no_snoop_rq_offset 836
-
-
-/* Constants */
-#define regk_marb_cpud 0x0000000b
-#define regk_marb_cpui 0x0000000a
-#define regk_marb_dma0 0x00000000
-#define regk_marb_dma1 0x00000001
-#define regk_marb_dma2 0x00000002
-#define regk_marb_dma3 0x00000003
-#define regk_marb_dma4 0x00000004
-#define regk_marb_dma5 0x00000005
-#define regk_marb_dma6 0x00000006
-#define regk_marb_dma7 0x00000007
-#define regk_marb_dma8 0x00000008
-#define regk_marb_dma9 0x00000009
-#define regk_marb_iop 0x0000000c
-#define regk_marb_no 0x00000000
-#define regk_marb_r_stopped_default 0x00000000
-#define regk_marb_rw_ext_slots_default 0x00000000
-#define regk_marb_rw_ext_slots_size 0x00000040
-#define regk_marb_rw_int_slots_default 0x00000000
-#define regk_marb_rw_int_slots_size 0x00000040
-#define regk_marb_rw_intr_mask_default 0x00000000
-#define regk_marb_rw_no_snoop_default 0x00000000
-#define regk_marb_rw_no_snoop_rq_default 0x00000000
-#define regk_marb_rw_regs_slots_default 0x00000000
-#define regk_marb_rw_regs_slots_size 0x00000004
-#define regk_marb_rw_stop_mask_default 0x00000000
-#define regk_marb_slave 0x0000000d
-#define regk_marb_yes 0x00000001
-#endif /* __marb_defs_asm_h */
-#ifndef __marb_bp_defs_asm_h
-#define __marb_bp_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-#define reg_marb_bp_rw_first_addr_offset 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-#define reg_marb_bp_rw_last_addr_offset 4
-
-/* Register rw_op, scope marb_bp, type rw */
-#define reg_marb_bp_rw_op___rd___lsb 0
-#define reg_marb_bp_rw_op___rd___width 1
-#define reg_marb_bp_rw_op___rd___bit 0
-#define reg_marb_bp_rw_op___wr___lsb 1
-#define reg_marb_bp_rw_op___wr___width 1
-#define reg_marb_bp_rw_op___wr___bit 1
-#define reg_marb_bp_rw_op___rd_excl___lsb 2
-#define reg_marb_bp_rw_op___rd_excl___width 1
-#define reg_marb_bp_rw_op___rd_excl___bit 2
-#define reg_marb_bp_rw_op___pri_wr___lsb 3
-#define reg_marb_bp_rw_op___pri_wr___width 1
-#define reg_marb_bp_rw_op___pri_wr___bit 3
-#define reg_marb_bp_rw_op___us_rd___lsb 4
-#define reg_marb_bp_rw_op___us_rd___width 1
-#define reg_marb_bp_rw_op___us_rd___bit 4
-#define reg_marb_bp_rw_op___us_wr___lsb 5
-#define reg_marb_bp_rw_op___us_wr___width 1
-#define reg_marb_bp_rw_op___us_wr___bit 5
-#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
-#define reg_marb_bp_rw_op___us_rd_excl___width 1
-#define reg_marb_bp_rw_op___us_rd_excl___bit 6
-#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
-#define reg_marb_bp_rw_op___us_pri_wr___width 1
-#define reg_marb_bp_rw_op___us_pri_wr___bit 7
-#define reg_marb_bp_rw_op_offset 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-#define reg_marb_bp_rw_clients___dma0___lsb 0
-#define reg_marb_bp_rw_clients___dma0___width 1
-#define reg_marb_bp_rw_clients___dma0___bit 0
-#define reg_marb_bp_rw_clients___dma1___lsb 1
-#define reg_marb_bp_rw_clients___dma1___width 1
-#define reg_marb_bp_rw_clients___dma1___bit 1
-#define reg_marb_bp_rw_clients___dma2___lsb 2
-#define reg_marb_bp_rw_clients___dma2___width 1
-#define reg_marb_bp_rw_clients___dma2___bit 2
-#define reg_marb_bp_rw_clients___dma3___lsb 3
-#define reg_marb_bp_rw_clients___dma3___width 1
-#define reg_marb_bp_rw_clients___dma3___bit 3
-#define reg_marb_bp_rw_clients___dma4___lsb 4
-#define reg_marb_bp_rw_clients___dma4___width 1
-#define reg_marb_bp_rw_clients___dma4___bit 4
-#define reg_marb_bp_rw_clients___dma5___lsb 5
-#define reg_marb_bp_rw_clients___dma5___width 1
-#define reg_marb_bp_rw_clients___dma5___bit 5
-#define reg_marb_bp_rw_clients___dma6___lsb 6
-#define reg_marb_bp_rw_clients___dma6___width 1
-#define reg_marb_bp_rw_clients___dma6___bit 6
-#define reg_marb_bp_rw_clients___dma7___lsb 7
-#define reg_marb_bp_rw_clients___dma7___width 1
-#define reg_marb_bp_rw_clients___dma7___bit 7
-#define reg_marb_bp_rw_clients___dma8___lsb 8
-#define reg_marb_bp_rw_clients___dma8___width 1
-#define reg_marb_bp_rw_clients___dma8___bit 8
-#define reg_marb_bp_rw_clients___dma9___lsb 9
-#define reg_marb_bp_rw_clients___dma9___width 1
-#define reg_marb_bp_rw_clients___dma9___bit 9
-#define reg_marb_bp_rw_clients___cpui___lsb 10
-#define reg_marb_bp_rw_clients___cpui___width 1
-#define reg_marb_bp_rw_clients___cpui___bit 10
-#define reg_marb_bp_rw_clients___cpud___lsb 11
-#define reg_marb_bp_rw_clients___cpud___width 1
-#define reg_marb_bp_rw_clients___cpud___bit 11
-#define reg_marb_bp_rw_clients___iop___lsb 12
-#define reg_marb_bp_rw_clients___iop___width 1
-#define reg_marb_bp_rw_clients___iop___bit 12
-#define reg_marb_bp_rw_clients___slave___lsb 13
-#define reg_marb_bp_rw_clients___slave___width 1
-#define reg_marb_bp_rw_clients___slave___bit 13
-#define reg_marb_bp_rw_clients_offset 12
-
-/* Register rw_options, scope marb_bp, type rw */
-#define reg_marb_bp_rw_options___wrap___lsb 0
-#define reg_marb_bp_rw_options___wrap___width 1
-#define reg_marb_bp_rw_options___wrap___bit 0
-#define reg_marb_bp_rw_options_offset 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_addr_offset 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_op___rd___lsb 0
-#define reg_marb_bp_r_brk_op___rd___width 1
-#define reg_marb_bp_r_brk_op___rd___bit 0
-#define reg_marb_bp_r_brk_op___wr___lsb 1
-#define reg_marb_bp_r_brk_op___wr___width 1
-#define reg_marb_bp_r_brk_op___wr___bit 1
-#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
-#define reg_marb_bp_r_brk_op___rd_excl___width 1
-#define reg_marb_bp_r_brk_op___rd_excl___bit 2
-#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
-#define reg_marb_bp_r_brk_op___pri_wr___width 1
-#define reg_marb_bp_r_brk_op___pri_wr___bit 3
-#define reg_marb_bp_r_brk_op___us_rd___lsb 4
-#define reg_marb_bp_r_brk_op___us_rd___width 1
-#define reg_marb_bp_r_brk_op___us_rd___bit 4
-#define reg_marb_bp_r_brk_op___us_wr___lsb 5
-#define reg_marb_bp_r_brk_op___us_wr___width 1
-#define reg_marb_bp_r_brk_op___us_wr___bit 5
-#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
-#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
-#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
-#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
-#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
-#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
-#define reg_marb_bp_r_brk_op_offset 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_clients___dma0___lsb 0
-#define reg_marb_bp_r_brk_clients___dma0___width 1
-#define reg_marb_bp_r_brk_clients___dma0___bit 0
-#define reg_marb_bp_r_brk_clients___dma1___lsb 1
-#define reg_marb_bp_r_brk_clients___dma1___width 1
-#define reg_marb_bp_r_brk_clients___dma1___bit 1
-#define reg_marb_bp_r_brk_clients___dma2___lsb 2
-#define reg_marb_bp_r_brk_clients___dma2___width 1
-#define reg_marb_bp_r_brk_clients___dma2___bit 2
-#define reg_marb_bp_r_brk_clients___dma3___lsb 3
-#define reg_marb_bp_r_brk_clients___dma3___width 1
-#define reg_marb_bp_r_brk_clients___dma3___bit 3
-#define reg_marb_bp_r_brk_clients___dma4___lsb 4
-#define reg_marb_bp_r_brk_clients___dma4___width 1
-#define reg_marb_bp_r_brk_clients___dma4___bit 4
-#define reg_marb_bp_r_brk_clients___dma5___lsb 5
-#define reg_marb_bp_r_brk_clients___dma5___width 1
-#define reg_marb_bp_r_brk_clients___dma5___bit 5
-#define reg_marb_bp_r_brk_clients___dma6___lsb 6
-#define reg_marb_bp_r_brk_clients___dma6___width 1
-#define reg_marb_bp_r_brk_clients___dma6___bit 6
-#define reg_marb_bp_r_brk_clients___dma7___lsb 7
-#define reg_marb_bp_r_brk_clients___dma7___width 1
-#define reg_marb_bp_r_brk_clients___dma7___bit 7
-#define reg_marb_bp_r_brk_clients___dma8___lsb 8
-#define reg_marb_bp_r_brk_clients___dma8___width 1
-#define reg_marb_bp_r_brk_clients___dma8___bit 8
-#define reg_marb_bp_r_brk_clients___dma9___lsb 9
-#define reg_marb_bp_r_brk_clients___dma9___width 1
-#define reg_marb_bp_r_brk_clients___dma9___bit 9
-#define reg_marb_bp_r_brk_clients___cpui___lsb 10
-#define reg_marb_bp_r_brk_clients___cpui___width 1
-#define reg_marb_bp_r_brk_clients___cpui___bit 10
-#define reg_marb_bp_r_brk_clients___cpud___lsb 11
-#define reg_marb_bp_r_brk_clients___cpud___width 1
-#define reg_marb_bp_r_brk_clients___cpud___bit 11
-#define reg_marb_bp_r_brk_clients___iop___lsb 12
-#define reg_marb_bp_r_brk_clients___iop___width 1
-#define reg_marb_bp_r_brk_clients___iop___bit 12
-#define reg_marb_bp_r_brk_clients___slave___lsb 13
-#define reg_marb_bp_r_brk_clients___slave___width 1
-#define reg_marb_bp_r_brk_clients___slave___bit 13
-#define reg_marb_bp_r_brk_clients_offset 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
-#define reg_marb_bp_r_brk_first_client___dma0___width 1
-#define reg_marb_bp_r_brk_first_client___dma0___bit 0
-#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
-#define reg_marb_bp_r_brk_first_client___dma1___width 1
-#define reg_marb_bp_r_brk_first_client___dma1___bit 1
-#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
-#define reg_marb_bp_r_brk_first_client___dma2___width 1
-#define reg_marb_bp_r_brk_first_client___dma2___bit 2
-#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
-#define reg_marb_bp_r_brk_first_client___dma3___width 1
-#define reg_marb_bp_r_brk_first_client___dma3___bit 3
-#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
-#define reg_marb_bp_r_brk_first_client___dma4___width 1
-#define reg_marb_bp_r_brk_first_client___dma4___bit 4
-#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
-#define reg_marb_bp_r_brk_first_client___dma5___width 1
-#define reg_marb_bp_r_brk_first_client___dma5___bit 5
-#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
-#define reg_marb_bp_r_brk_first_client___dma6___width 1
-#define reg_marb_bp_r_brk_first_client___dma6___bit 6
-#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
-#define reg_marb_bp_r_brk_first_client___dma7___width 1
-#define reg_marb_bp_r_brk_first_client___dma7___bit 7
-#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
-#define reg_marb_bp_r_brk_first_client___dma8___width 1
-#define reg_marb_bp_r_brk_first_client___dma8___bit 8
-#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
-#define reg_marb_bp_r_brk_first_client___dma9___width 1
-#define reg_marb_bp_r_brk_first_client___dma9___bit 9
-#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
-#define reg_marb_bp_r_brk_first_client___cpui___width 1
-#define reg_marb_bp_r_brk_first_client___cpui___bit 10
-#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
-#define reg_marb_bp_r_brk_first_client___cpud___width 1
-#define reg_marb_bp_r_brk_first_client___cpud___bit 11
-#define reg_marb_bp_r_brk_first_client___iop___lsb 12
-#define reg_marb_bp_r_brk_first_client___iop___width 1
-#define reg_marb_bp_r_brk_first_client___iop___bit 12
-#define reg_marb_bp_r_brk_first_client___slave___lsb 13
-#define reg_marb_bp_r_brk_first_client___slave___width 1
-#define reg_marb_bp_r_brk_first_client___slave___bit 13
-#define reg_marb_bp_r_brk_first_client_offset 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_size_offset 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-#define reg_marb_bp_rw_ack_offset 40
-
-
-/* Constants */
-#define regk_marb_bp_no 0x00000000
-#define regk_marb_bp_rw_op_default 0x00000000
-#define regk_marb_bp_rw_options_default 0x00000000
-#define regk_marb_bp_yes 0x00000001
-#endif /* __marb_bp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h
deleted file mode 100644
index 083174678961..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __mmu_defs_asm_h
-#define __mmu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/mmu/doc/mmu_regs.r
- * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
- * last modfied: Mon Apr 11 17:03:20 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
- * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mm_cfg, scope mmu, type rw */
-#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
-#define reg_mmu_rw_mm_cfg___seg_0___width 1
-#define reg_mmu_rw_mm_cfg___seg_0___bit 0
-#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
-#define reg_mmu_rw_mm_cfg___seg_1___width 1
-#define reg_mmu_rw_mm_cfg___seg_1___bit 1
-#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
-#define reg_mmu_rw_mm_cfg___seg_2___width 1
-#define reg_mmu_rw_mm_cfg___seg_2___bit 2
-#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
-#define reg_mmu_rw_mm_cfg___seg_3___width 1
-#define reg_mmu_rw_mm_cfg___seg_3___bit 3
-#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
-#define reg_mmu_rw_mm_cfg___seg_4___width 1
-#define reg_mmu_rw_mm_cfg___seg_4___bit 4
-#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
-#define reg_mmu_rw_mm_cfg___seg_5___width 1
-#define reg_mmu_rw_mm_cfg___seg_5___bit 5
-#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
-#define reg_mmu_rw_mm_cfg___seg_6___width 1
-#define reg_mmu_rw_mm_cfg___seg_6___bit 6
-#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
-#define reg_mmu_rw_mm_cfg___seg_7___width 1
-#define reg_mmu_rw_mm_cfg___seg_7___bit 7
-#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
-#define reg_mmu_rw_mm_cfg___seg_8___width 1
-#define reg_mmu_rw_mm_cfg___seg_8___bit 8
-#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
-#define reg_mmu_rw_mm_cfg___seg_9___width 1
-#define reg_mmu_rw_mm_cfg___seg_9___bit 9
-#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
-#define reg_mmu_rw_mm_cfg___seg_a___width 1
-#define reg_mmu_rw_mm_cfg___seg_a___bit 10
-#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
-#define reg_mmu_rw_mm_cfg___seg_b___width 1
-#define reg_mmu_rw_mm_cfg___seg_b___bit 11
-#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
-#define reg_mmu_rw_mm_cfg___seg_c___width 1
-#define reg_mmu_rw_mm_cfg___seg_c___bit 12
-#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
-#define reg_mmu_rw_mm_cfg___seg_d___width 1
-#define reg_mmu_rw_mm_cfg___seg_d___bit 13
-#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
-#define reg_mmu_rw_mm_cfg___seg_e___width 1
-#define reg_mmu_rw_mm_cfg___seg_e___bit 14
-#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
-#define reg_mmu_rw_mm_cfg___seg_f___width 1
-#define reg_mmu_rw_mm_cfg___seg_f___bit 15
-#define reg_mmu_rw_mm_cfg___inv___lsb 16
-#define reg_mmu_rw_mm_cfg___inv___width 1
-#define reg_mmu_rw_mm_cfg___inv___bit 16
-#define reg_mmu_rw_mm_cfg___ex___lsb 17
-#define reg_mmu_rw_mm_cfg___ex___width 1
-#define reg_mmu_rw_mm_cfg___ex___bit 17
-#define reg_mmu_rw_mm_cfg___acc___lsb 18
-#define reg_mmu_rw_mm_cfg___acc___width 1
-#define reg_mmu_rw_mm_cfg___acc___bit 18
-#define reg_mmu_rw_mm_cfg___we___lsb 19
-#define reg_mmu_rw_mm_cfg___we___width 1
-#define reg_mmu_rw_mm_cfg___we___bit 19
-#define reg_mmu_rw_mm_cfg_offset 0
-
-/* Register rw_mm_kbase_lo, scope mmu, type rw */
-#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
-#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
-#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
-#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
-#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
-#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
-#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
-#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
-#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
-#define reg_mmu_rw_mm_kbase_lo_offset 4
-
-/* Register rw_mm_kbase_hi, scope mmu, type rw */
-#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
-#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
-#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
-#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
-#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
-#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
-#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
-#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
-#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
-#define reg_mmu_rw_mm_kbase_hi_offset 8
-
-/* Register r_mm_cause, scope mmu, type r */
-#define reg_mmu_r_mm_cause___pid___lsb 0
-#define reg_mmu_r_mm_cause___pid___width 8
-#define reg_mmu_r_mm_cause___op___lsb 8
-#define reg_mmu_r_mm_cause___op___width 2
-#define reg_mmu_r_mm_cause___vpn___lsb 13
-#define reg_mmu_r_mm_cause___vpn___width 19
-#define reg_mmu_r_mm_cause_offset 12
-
-/* Register rw_mm_tlb_sel, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
-#define reg_mmu_rw_mm_tlb_sel___idx___width 4
-#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
-#define reg_mmu_rw_mm_tlb_sel___set___width 2
-#define reg_mmu_rw_mm_tlb_sel_offset 16
-
-/* Register rw_mm_tlb_lo, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
-#define reg_mmu_rw_mm_tlb_lo___x___width 1
-#define reg_mmu_rw_mm_tlb_lo___x___bit 0
-#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
-#define reg_mmu_rw_mm_tlb_lo___w___width 1
-#define reg_mmu_rw_mm_tlb_lo___w___bit 1
-#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
-#define reg_mmu_rw_mm_tlb_lo___k___width 1
-#define reg_mmu_rw_mm_tlb_lo___k___bit 2
-#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
-#define reg_mmu_rw_mm_tlb_lo___v___width 1
-#define reg_mmu_rw_mm_tlb_lo___v___bit 3
-#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
-#define reg_mmu_rw_mm_tlb_lo___g___width 1
-#define reg_mmu_rw_mm_tlb_lo___g___bit 4
-#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
-#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
-#define reg_mmu_rw_mm_tlb_lo_offset 20
-
-/* Register rw_mm_tlb_hi, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
-#define reg_mmu_rw_mm_tlb_hi___pid___width 8
-#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
-#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
-#define reg_mmu_rw_mm_tlb_hi_offset 24
-
-
-/* Constants */
-#define regk_mmu_execute 0x00000000
-#define regk_mmu_flush 0x00000003
-#define regk_mmu_linear 0x00000001
-#define regk_mmu_no 0x00000000
-#define regk_mmu_off 0x00000000
-#define regk_mmu_on 0x00000001
-#define regk_mmu_page 0x00000000
-#define regk_mmu_read 0x00000001
-#define regk_mmu_write 0x00000002
-#define regk_mmu_yes 0x00000001
-#endif /* __mmu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h
deleted file mode 100644
index fd66daa79259..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define RW_MM_CFG 0
-#define RW_MM_KBASE_LO 1
-#define RW_MM_KBASE_HI 2
-#define R_MM_CAUSE 3
-#define RW_MM_TLB_SEL 4
-#define RW_MM_TLB_LO 5
-#define RW_MM_TLB_HI 6
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h
deleted file mode 100644
index 72b3d231d80f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __rt_trace_defs_asm_h
-#define __rt_trace_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/rt_trace/rtl/rt_regs.r
- * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
- * last modfied: Mon Apr 11 16:09:14 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
- * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope rt_trace, type rw */
-#define reg_rt_trace_rw_cfg___en___lsb 0
-#define reg_rt_trace_rw_cfg___en___width 1
-#define reg_rt_trace_rw_cfg___en___bit 0
-#define reg_rt_trace_rw_cfg___mode___lsb 1
-#define reg_rt_trace_rw_cfg___mode___width 1
-#define reg_rt_trace_rw_cfg___mode___bit 1
-#define reg_rt_trace_rw_cfg___owner___lsb 2
-#define reg_rt_trace_rw_cfg___owner___width 1
-#define reg_rt_trace_rw_cfg___owner___bit 2
-#define reg_rt_trace_rw_cfg___wp___lsb 3
-#define reg_rt_trace_rw_cfg___wp___width 1
-#define reg_rt_trace_rw_cfg___wp___bit 3
-#define reg_rt_trace_rw_cfg___stall___lsb 4
-#define reg_rt_trace_rw_cfg___stall___width 1
-#define reg_rt_trace_rw_cfg___stall___bit 4
-#define reg_rt_trace_rw_cfg___wp_start___lsb 8
-#define reg_rt_trace_rw_cfg___wp_start___width 7
-#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
-#define reg_rt_trace_rw_cfg___wp_stop___width 7
-#define reg_rt_trace_rw_cfg_offset 0
-
-/* Register rw_tap_ctrl, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
-#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
-#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
-#define reg_rt_trace_rw_tap_ctrl_offset 4
-
-/* Register r_tap_stat, scope rt_trace, type r */
-#define reg_rt_trace_r_tap_stat___dav___lsb 0
-#define reg_rt_trace_r_tap_stat___dav___width 1
-#define reg_rt_trace_r_tap_stat___dav___bit 0
-#define reg_rt_trace_r_tap_stat___empty___lsb 1
-#define reg_rt_trace_r_tap_stat___empty___width 1
-#define reg_rt_trace_r_tap_stat___empty___bit 1
-#define reg_rt_trace_r_tap_stat_offset 8
-
-/* Register rw_tap_data, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_data_offset 12
-
-/* Register rw_tap_hdata, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_hdata___op___lsb 0
-#define reg_rt_trace_rw_tap_hdata___op___width 4
-#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
-#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
-#define reg_rt_trace_rw_tap_hdata_offset 16
-
-/* Register r_redir, scope rt_trace, type r */
-#define reg_rt_trace_r_redir_offset 20
-
-
-/* Constants */
-#define regk_rt_trace_brk 0x0000000c
-#define regk_rt_trace_dbg 0x00000003
-#define regk_rt_trace_dbgdi 0x00000004
-#define regk_rt_trace_dbgdo 0x00000005
-#define regk_rt_trace_gmode 0x00000000
-#define regk_rt_trace_no 0x00000000
-#define regk_rt_trace_nop 0x00000000
-#define regk_rt_trace_normal 0x00000000
-#define regk_rt_trace_rdmem 0x00000007
-#define regk_rt_trace_rdmemb 0x00000009
-#define regk_rt_trace_rdpreg 0x00000002
-#define regk_rt_trace_rdreg 0x00000001
-#define regk_rt_trace_rdsreg 0x00000003
-#define regk_rt_trace_redir 0x00000006
-#define regk_rt_trace_ret 0x0000000b
-#define regk_rt_trace_rw_cfg_default 0x00000000
-#define regk_rt_trace_trcfg 0x00000001
-#define regk_rt_trace_wp 0x00000001
-#define regk_rt_trace_wp0 0x00000001
-#define regk_rt_trace_wp1 0x00000002
-#define regk_rt_trace_wp2 0x00000004
-#define regk_rt_trace_wp3 0x00000008
-#define regk_rt_trace_wp4 0x00000010
-#define regk_rt_trace_wp5 0x00000020
-#define regk_rt_trace_wp6 0x00000040
-#define regk_rt_trace_wrmem 0x00000008
-#define regk_rt_trace_wrmemb 0x0000000a
-#define regk_rt_trace_wrpreg 0x00000005
-#define regk_rt_trace_wrreg 0x00000004
-#define regk_rt_trace_wrsreg 0x00000006
-#define regk_rt_trace_yes 0x00000001
-#endif /* __rt_trace_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h
deleted file mode 100644
index 944f4c7666b4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ser_defs_asm_h
-#define __ser_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ser/rtl/ser_regs.r
- * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
- * last modfied: Mon Apr 11 16:09:21 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
- * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tr_ctrl, scope ser, type rw */
-#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
-#define reg_ser_rw_tr_ctrl___base_freq___width 3
-#define reg_ser_rw_tr_ctrl___en___lsb 3
-#define reg_ser_rw_tr_ctrl___en___width 1
-#define reg_ser_rw_tr_ctrl___en___bit 3
-#define reg_ser_rw_tr_ctrl___par___lsb 4
-#define reg_ser_rw_tr_ctrl___par___width 2
-#define reg_ser_rw_tr_ctrl___par_en___lsb 6
-#define reg_ser_rw_tr_ctrl___par_en___width 1
-#define reg_ser_rw_tr_ctrl___par_en___bit 6
-#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
-#define reg_ser_rw_tr_ctrl___data_bits___width 1
-#define reg_ser_rw_tr_ctrl___data_bits___bit 7
-#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
-#define reg_ser_rw_tr_ctrl___stop_bits___width 1
-#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
-#define reg_ser_rw_tr_ctrl___stop___lsb 9
-#define reg_ser_rw_tr_ctrl___stop___width 1
-#define reg_ser_rw_tr_ctrl___stop___bit 9
-#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
-#define reg_ser_rw_tr_ctrl___rts_delay___width 3
-#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
-#define reg_ser_rw_tr_ctrl___rts_setup___width 1
-#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
-#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
-#define reg_ser_rw_tr_ctrl___auto_rts___width 1
-#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
-#define reg_ser_rw_tr_ctrl___txd___lsb 15
-#define reg_ser_rw_tr_ctrl___txd___width 1
-#define reg_ser_rw_tr_ctrl___txd___bit 15
-#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
-#define reg_ser_rw_tr_ctrl___auto_cts___width 1
-#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
-#define reg_ser_rw_tr_ctrl_offset 0
-
-/* Register rw_tr_dma_en, scope ser, type rw */
-#define reg_ser_rw_tr_dma_en___en___lsb 0
-#define reg_ser_rw_tr_dma_en___en___width 1
-#define reg_ser_rw_tr_dma_en___en___bit 0
-#define reg_ser_rw_tr_dma_en_offset 4
-
-/* Register rw_rec_ctrl, scope ser, type rw */
-#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
-#define reg_ser_rw_rec_ctrl___base_freq___width 3
-#define reg_ser_rw_rec_ctrl___en___lsb 3
-#define reg_ser_rw_rec_ctrl___en___width 1
-#define reg_ser_rw_rec_ctrl___en___bit 3
-#define reg_ser_rw_rec_ctrl___par___lsb 4
-#define reg_ser_rw_rec_ctrl___par___width 2
-#define reg_ser_rw_rec_ctrl___par_en___lsb 6
-#define reg_ser_rw_rec_ctrl___par_en___width 1
-#define reg_ser_rw_rec_ctrl___par_en___bit 6
-#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
-#define reg_ser_rw_rec_ctrl___data_bits___width 1
-#define reg_ser_rw_rec_ctrl___data_bits___bit 7
-#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
-#define reg_ser_rw_rec_ctrl___dma_mode___width 1
-#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
-#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
-#define reg_ser_rw_rec_ctrl___dma_err___width 1
-#define reg_ser_rw_rec_ctrl___dma_err___bit 9
-#define reg_ser_rw_rec_ctrl___sampling___lsb 10
-#define reg_ser_rw_rec_ctrl___sampling___width 1
-#define reg_ser_rw_rec_ctrl___sampling___bit 10
-#define reg_ser_rw_rec_ctrl___timeout___lsb 11
-#define reg_ser_rw_rec_ctrl___timeout___width 3
-#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
-#define reg_ser_rw_rec_ctrl___auto_eop___width 1
-#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
-#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
-#define reg_ser_rw_rec_ctrl___half_duplex___width 1
-#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
-#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
-#define reg_ser_rw_rec_ctrl___rts_n___width 1
-#define reg_ser_rw_rec_ctrl___rts_n___bit 16
-#define reg_ser_rw_rec_ctrl___loopback___lsb 17
-#define reg_ser_rw_rec_ctrl___loopback___width 1
-#define reg_ser_rw_rec_ctrl___loopback___bit 17
-#define reg_ser_rw_rec_ctrl_offset 8
-
-/* Register rw_tr_baud_div, scope ser, type rw */
-#define reg_ser_rw_tr_baud_div___div___lsb 0
-#define reg_ser_rw_tr_baud_div___div___width 16
-#define reg_ser_rw_tr_baud_div_offset 12
-
-/* Register rw_rec_baud_div, scope ser, type rw */
-#define reg_ser_rw_rec_baud_div___div___lsb 0
-#define reg_ser_rw_rec_baud_div___div___width 16
-#define reg_ser_rw_rec_baud_div_offset 16
-
-/* Register rw_xoff, scope ser, type rw */
-#define reg_ser_rw_xoff___chr___lsb 0
-#define reg_ser_rw_xoff___chr___width 8
-#define reg_ser_rw_xoff___automatic___lsb 8
-#define reg_ser_rw_xoff___automatic___width 1
-#define reg_ser_rw_xoff___automatic___bit 8
-#define reg_ser_rw_xoff_offset 20
-
-/* Register rw_xoff_clr, scope ser, type rw */
-#define reg_ser_rw_xoff_clr___clr___lsb 0
-#define reg_ser_rw_xoff_clr___clr___width 1
-#define reg_ser_rw_xoff_clr___clr___bit 0
-#define reg_ser_rw_xoff_clr_offset 24
-
-/* Register rw_dout, scope ser, type rw */
-#define reg_ser_rw_dout___data___lsb 0
-#define reg_ser_rw_dout___data___width 8
-#define reg_ser_rw_dout_offset 28
-
-/* Register rs_stat_din, scope ser, type rs */
-#define reg_ser_rs_stat_din___data___lsb 0
-#define reg_ser_rs_stat_din___data___width 8
-#define reg_ser_rs_stat_din___dav___lsb 16
-#define reg_ser_rs_stat_din___dav___width 1
-#define reg_ser_rs_stat_din___dav___bit 16
-#define reg_ser_rs_stat_din___framing_err___lsb 17
-#define reg_ser_rs_stat_din___framing_err___width 1
-#define reg_ser_rs_stat_din___framing_err___bit 17
-#define reg_ser_rs_stat_din___par_err___lsb 18
-#define reg_ser_rs_stat_din___par_err___width 1
-#define reg_ser_rs_stat_din___par_err___bit 18
-#define reg_ser_rs_stat_din___orun___lsb 19
-#define reg_ser_rs_stat_din___orun___width 1
-#define reg_ser_rs_stat_din___orun___bit 19
-#define reg_ser_rs_stat_din___rec_err___lsb 20
-#define reg_ser_rs_stat_din___rec_err___width 1
-#define reg_ser_rs_stat_din___rec_err___bit 20
-#define reg_ser_rs_stat_din___rxd___lsb 21
-#define reg_ser_rs_stat_din___rxd___width 1
-#define reg_ser_rs_stat_din___rxd___bit 21
-#define reg_ser_rs_stat_din___tr_idle___lsb 22
-#define reg_ser_rs_stat_din___tr_idle___width 1
-#define reg_ser_rs_stat_din___tr_idle___bit 22
-#define reg_ser_rs_stat_din___tr_empty___lsb 23
-#define reg_ser_rs_stat_din___tr_empty___width 1
-#define reg_ser_rs_stat_din___tr_empty___bit 23
-#define reg_ser_rs_stat_din___tr_rdy___lsb 24
-#define reg_ser_rs_stat_din___tr_rdy___width 1
-#define reg_ser_rs_stat_din___tr_rdy___bit 24
-#define reg_ser_rs_stat_din___cts_n___lsb 25
-#define reg_ser_rs_stat_din___cts_n___width 1
-#define reg_ser_rs_stat_din___cts_n___bit 25
-#define reg_ser_rs_stat_din___xoff_detect___lsb 26
-#define reg_ser_rs_stat_din___xoff_detect___width 1
-#define reg_ser_rs_stat_din___xoff_detect___bit 26
-#define reg_ser_rs_stat_din___rts_n___lsb 27
-#define reg_ser_rs_stat_din___rts_n___width 1
-#define reg_ser_rs_stat_din___rts_n___bit 27
-#define reg_ser_rs_stat_din___txd___lsb 28
-#define reg_ser_rs_stat_din___txd___width 1
-#define reg_ser_rs_stat_din___txd___bit 28
-#define reg_ser_rs_stat_din_offset 32
-
-/* Register r_stat_din, scope ser, type r */
-#define reg_ser_r_stat_din___data___lsb 0
-#define reg_ser_r_stat_din___data___width 8
-#define reg_ser_r_stat_din___dav___lsb 16
-#define reg_ser_r_stat_din___dav___width 1
-#define reg_ser_r_stat_din___dav___bit 16
-#define reg_ser_r_stat_din___framing_err___lsb 17
-#define reg_ser_r_stat_din___framing_err___width 1
-#define reg_ser_r_stat_din___framing_err___bit 17
-#define reg_ser_r_stat_din___par_err___lsb 18
-#define reg_ser_r_stat_din___par_err___width 1
-#define reg_ser_r_stat_din___par_err___bit 18
-#define reg_ser_r_stat_din___orun___lsb 19
-#define reg_ser_r_stat_din___orun___width 1
-#define reg_ser_r_stat_din___orun___bit 19
-#define reg_ser_r_stat_din___rec_err___lsb 20
-#define reg_ser_r_stat_din___rec_err___width 1
-#define reg_ser_r_stat_din___rec_err___bit 20
-#define reg_ser_r_stat_din___rxd___lsb 21
-#define reg_ser_r_stat_din___rxd___width 1
-#define reg_ser_r_stat_din___rxd___bit 21
-#define reg_ser_r_stat_din___tr_idle___lsb 22
-#define reg_ser_r_stat_din___tr_idle___width 1
-#define reg_ser_r_stat_din___tr_idle___bit 22
-#define reg_ser_r_stat_din___tr_empty___lsb 23
-#define reg_ser_r_stat_din___tr_empty___width 1
-#define reg_ser_r_stat_din___tr_empty___bit 23
-#define reg_ser_r_stat_din___tr_rdy___lsb 24
-#define reg_ser_r_stat_din___tr_rdy___width 1
-#define reg_ser_r_stat_din___tr_rdy___bit 24
-#define reg_ser_r_stat_din___cts_n___lsb 25
-#define reg_ser_r_stat_din___cts_n___width 1
-#define reg_ser_r_stat_din___cts_n___bit 25
-#define reg_ser_r_stat_din___xoff_detect___lsb 26
-#define reg_ser_r_stat_din___xoff_detect___width 1
-#define reg_ser_r_stat_din___xoff_detect___bit 26
-#define reg_ser_r_stat_din___rts_n___lsb 27
-#define reg_ser_r_stat_din___rts_n___width 1
-#define reg_ser_r_stat_din___rts_n___bit 27
-#define reg_ser_r_stat_din___txd___lsb 28
-#define reg_ser_r_stat_din___txd___width 1
-#define reg_ser_r_stat_din___txd___bit 28
-#define reg_ser_r_stat_din_offset 36
-
-/* Register rw_rec_eop, scope ser, type rw */
-#define reg_ser_rw_rec_eop___set___lsb 0
-#define reg_ser_rw_rec_eop___set___width 1
-#define reg_ser_rw_rec_eop___set___bit 0
-#define reg_ser_rw_rec_eop_offset 40
-
-/* Register rw_intr_mask, scope ser, type rw */
-#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
-#define reg_ser_rw_intr_mask___tr_rdy___width 1
-#define reg_ser_rw_intr_mask___tr_rdy___bit 0
-#define reg_ser_rw_intr_mask___tr_empty___lsb 1
-#define reg_ser_rw_intr_mask___tr_empty___width 1
-#define reg_ser_rw_intr_mask___tr_empty___bit 1
-#define reg_ser_rw_intr_mask___tr_idle___lsb 2
-#define reg_ser_rw_intr_mask___tr_idle___width 1
-#define reg_ser_rw_intr_mask___tr_idle___bit 2
-#define reg_ser_rw_intr_mask___dav___lsb 3
-#define reg_ser_rw_intr_mask___dav___width 1
-#define reg_ser_rw_intr_mask___dav___bit 3
-#define reg_ser_rw_intr_mask_offset 44
-
-/* Register rw_ack_intr, scope ser, type rw */
-#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
-#define reg_ser_rw_ack_intr___tr_rdy___width 1
-#define reg_ser_rw_ack_intr___tr_rdy___bit 0
-#define reg_ser_rw_ack_intr___tr_empty___lsb 1
-#define reg_ser_rw_ack_intr___tr_empty___width 1
-#define reg_ser_rw_ack_intr___tr_empty___bit 1
-#define reg_ser_rw_ack_intr___tr_idle___lsb 2
-#define reg_ser_rw_ack_intr___tr_idle___width 1
-#define reg_ser_rw_ack_intr___tr_idle___bit 2
-#define reg_ser_rw_ack_intr___dav___lsb 3
-#define reg_ser_rw_ack_intr___dav___width 1
-#define reg_ser_rw_ack_intr___dav___bit 3
-#define reg_ser_rw_ack_intr_offset 48
-
-/* Register r_intr, scope ser, type r */
-#define reg_ser_r_intr___tr_rdy___lsb 0
-#define reg_ser_r_intr___tr_rdy___width 1
-#define reg_ser_r_intr___tr_rdy___bit 0
-#define reg_ser_r_intr___tr_empty___lsb 1
-#define reg_ser_r_intr___tr_empty___width 1
-#define reg_ser_r_intr___tr_empty___bit 1
-#define reg_ser_r_intr___tr_idle___lsb 2
-#define reg_ser_r_intr___tr_idle___width 1
-#define reg_ser_r_intr___tr_idle___bit 2
-#define reg_ser_r_intr___dav___lsb 3
-#define reg_ser_r_intr___dav___width 1
-#define reg_ser_r_intr___dav___bit 3
-#define reg_ser_r_intr_offset 52
-
-/* Register r_masked_intr, scope ser, type r */
-#define reg_ser_r_masked_intr___tr_rdy___lsb 0
-#define reg_ser_r_masked_intr___tr_rdy___width 1
-#define reg_ser_r_masked_intr___tr_rdy___bit 0
-#define reg_ser_r_masked_intr___tr_empty___lsb 1
-#define reg_ser_r_masked_intr___tr_empty___width 1
-#define reg_ser_r_masked_intr___tr_empty___bit 1
-#define reg_ser_r_masked_intr___tr_idle___lsb 2
-#define reg_ser_r_masked_intr___tr_idle___width 1
-#define reg_ser_r_masked_intr___tr_idle___bit 2
-#define reg_ser_r_masked_intr___dav___lsb 3
-#define reg_ser_r_masked_intr___dav___width 1
-#define reg_ser_r_masked_intr___dav___bit 3
-#define reg_ser_r_masked_intr_offset 56
-
-
-/* Constants */
-#define regk_ser_active 0x00000000
-#define regk_ser_bits1 0x00000000
-#define regk_ser_bits2 0x00000001
-#define regk_ser_bits7 0x00000001
-#define regk_ser_bits8 0x00000000
-#define regk_ser_del0_5 0x00000000
-#define regk_ser_del1 0x00000001
-#define regk_ser_del1_5 0x00000002
-#define regk_ser_del2 0x00000003
-#define regk_ser_del2_5 0x00000004
-#define regk_ser_del3 0x00000005
-#define regk_ser_del3_5 0x00000006
-#define regk_ser_del4 0x00000007
-#define regk_ser_even 0x00000000
-#define regk_ser_ext 0x00000001
-#define regk_ser_f100 0x00000007
-#define regk_ser_f29_493 0x00000004
-#define regk_ser_f32 0x00000005
-#define regk_ser_f32_768 0x00000006
-#define regk_ser_ignore 0x00000001
-#define regk_ser_inactive 0x00000001
-#define regk_ser_majority 0x00000001
-#define regk_ser_mark 0x00000002
-#define regk_ser_middle 0x00000000
-#define regk_ser_no 0x00000000
-#define regk_ser_odd 0x00000001
-#define regk_ser_off 0x00000000
-#define regk_ser_rw_intr_mask_default 0x00000000
-#define regk_ser_rw_rec_baud_div_default 0x00000000
-#define regk_ser_rw_rec_ctrl_default 0x00010000
-#define regk_ser_rw_tr_baud_div_default 0x00000000
-#define regk_ser_rw_tr_ctrl_default 0x00008000
-#define regk_ser_rw_tr_dma_en_default 0x00000000
-#define regk_ser_rw_xoff_default 0x00000000
-#define regk_ser_space 0x00000003
-#define regk_ser_stop 0x00000000
-#define regk_ser_yes 0x00000001
-#endif /* __ser_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h
deleted file mode 100644
index 607b505100fa..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __sser_defs_asm_h
-#define __sser_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/syncser/rtl/sser_regs.r
- * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
- * last modfied: Mon Apr 11 16:09:48 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
- * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope sser, type rw */
-#define reg_sser_rw_cfg___clk_div___lsb 0
-#define reg_sser_rw_cfg___clk_div___width 16
-#define reg_sser_rw_cfg___base_freq___lsb 16
-#define reg_sser_rw_cfg___base_freq___width 3
-#define reg_sser_rw_cfg___gate_clk___lsb 19
-#define reg_sser_rw_cfg___gate_clk___width 1
-#define reg_sser_rw_cfg___gate_clk___bit 19
-#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
-#define reg_sser_rw_cfg___clkgate_ctrl___width 1
-#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
-#define reg_sser_rw_cfg___clkgate_in___lsb 21
-#define reg_sser_rw_cfg___clkgate_in___width 1
-#define reg_sser_rw_cfg___clkgate_in___bit 21
-#define reg_sser_rw_cfg___clk_dir___lsb 22
-#define reg_sser_rw_cfg___clk_dir___width 1
-#define reg_sser_rw_cfg___clk_dir___bit 22
-#define reg_sser_rw_cfg___clk_od_mode___lsb 23
-#define reg_sser_rw_cfg___clk_od_mode___width 1
-#define reg_sser_rw_cfg___clk_od_mode___bit 23
-#define reg_sser_rw_cfg___out_clk_pol___lsb 24
-#define reg_sser_rw_cfg___out_clk_pol___width 1
-#define reg_sser_rw_cfg___out_clk_pol___bit 24
-#define reg_sser_rw_cfg___out_clk_src___lsb 25
-#define reg_sser_rw_cfg___out_clk_src___width 2
-#define reg_sser_rw_cfg___clk_in_sel___lsb 27
-#define reg_sser_rw_cfg___clk_in_sel___width 1
-#define reg_sser_rw_cfg___clk_in_sel___bit 27
-#define reg_sser_rw_cfg___hold_pol___lsb 28
-#define reg_sser_rw_cfg___hold_pol___width 1
-#define reg_sser_rw_cfg___hold_pol___bit 28
-#define reg_sser_rw_cfg___prepare___lsb 29
-#define reg_sser_rw_cfg___prepare___width 1
-#define reg_sser_rw_cfg___prepare___bit 29
-#define reg_sser_rw_cfg___en___lsb 30
-#define reg_sser_rw_cfg___en___width 1
-#define reg_sser_rw_cfg___en___bit 30
-#define reg_sser_rw_cfg_offset 0
-
-/* Register rw_frm_cfg, scope sser, type rw */
-#define reg_sser_rw_frm_cfg___wordrate___lsb 0
-#define reg_sser_rw_frm_cfg___wordrate___width 10
-#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
-#define reg_sser_rw_frm_cfg___rec_delay___width 3
-#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
-#define reg_sser_rw_frm_cfg___tr_delay___width 3
-#define reg_sser_rw_frm_cfg___early_wend___lsb 16
-#define reg_sser_rw_frm_cfg___early_wend___width 1
-#define reg_sser_rw_frm_cfg___early_wend___bit 16
-#define reg_sser_rw_frm_cfg___level___lsb 17
-#define reg_sser_rw_frm_cfg___level___width 2
-#define reg_sser_rw_frm_cfg___type___lsb 19
-#define reg_sser_rw_frm_cfg___type___width 1
-#define reg_sser_rw_frm_cfg___type___bit 19
-#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
-#define reg_sser_rw_frm_cfg___clk_pol___width 1
-#define reg_sser_rw_frm_cfg___clk_pol___bit 20
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
-#define reg_sser_rw_frm_cfg___clk_src___lsb 22
-#define reg_sser_rw_frm_cfg___clk_src___width 1
-#define reg_sser_rw_frm_cfg___clk_src___bit 22
-#define reg_sser_rw_frm_cfg___out_off___lsb 23
-#define reg_sser_rw_frm_cfg___out_off___width 1
-#define reg_sser_rw_frm_cfg___out_off___bit 23
-#define reg_sser_rw_frm_cfg___out_on___lsb 24
-#define reg_sser_rw_frm_cfg___out_on___width 1
-#define reg_sser_rw_frm_cfg___out_on___bit 24
-#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
-#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
-#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
-#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
-#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
-#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
-#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
-#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
-#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
-#define reg_sser_rw_frm_cfg___status_pin_use___width 2
-#define reg_sser_rw_frm_cfg_offset 4
-
-/* Register rw_tr_cfg, scope sser, type rw */
-#define reg_sser_rw_tr_cfg___tr_en___lsb 0
-#define reg_sser_rw_tr_cfg___tr_en___width 1
-#define reg_sser_rw_tr_cfg___tr_en___bit 0
-#define reg_sser_rw_tr_cfg___stop___lsb 1
-#define reg_sser_rw_tr_cfg___stop___width 1
-#define reg_sser_rw_tr_cfg___stop___bit 1
-#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
-#define reg_sser_rw_tr_cfg___urun_stop___width 1
-#define reg_sser_rw_tr_cfg___urun_stop___bit 2
-#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
-#define reg_sser_rw_tr_cfg___eop_stop___width 1
-#define reg_sser_rw_tr_cfg___eop_stop___bit 3
-#define reg_sser_rw_tr_cfg___sample_size___lsb 4
-#define reg_sser_rw_tr_cfg___sample_size___width 6
-#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
-#define reg_sser_rw_tr_cfg___sh_dir___width 1
-#define reg_sser_rw_tr_cfg___sh_dir___bit 10
-#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
-#define reg_sser_rw_tr_cfg___clk_pol___width 1
-#define reg_sser_rw_tr_cfg___clk_pol___bit 11
-#define reg_sser_rw_tr_cfg___clk_src___lsb 12
-#define reg_sser_rw_tr_cfg___clk_src___width 1
-#define reg_sser_rw_tr_cfg___clk_src___bit 12
-#define reg_sser_rw_tr_cfg___use_dma___lsb 13
-#define reg_sser_rw_tr_cfg___use_dma___width 1
-#define reg_sser_rw_tr_cfg___use_dma___bit 13
-#define reg_sser_rw_tr_cfg___mode___lsb 14
-#define reg_sser_rw_tr_cfg___mode___width 2
-#define reg_sser_rw_tr_cfg___frm_src___lsb 16
-#define reg_sser_rw_tr_cfg___frm_src___width 1
-#define reg_sser_rw_tr_cfg___frm_src___bit 16
-#define reg_sser_rw_tr_cfg___use60958___lsb 17
-#define reg_sser_rw_tr_cfg___use60958___width 1
-#define reg_sser_rw_tr_cfg___use60958___bit 17
-#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
-#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
-#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
-#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
-#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
-#define reg_sser_rw_tr_cfg___use_md___lsb 21
-#define reg_sser_rw_tr_cfg___use_md___width 1
-#define reg_sser_rw_tr_cfg___use_md___bit 21
-#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
-#define reg_sser_rw_tr_cfg___dual_i2s___width 1
-#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
-#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
-#define reg_sser_rw_tr_cfg___data_pin_use___width 2
-#define reg_sser_rw_tr_cfg___od_mode___lsb 25
-#define reg_sser_rw_tr_cfg___od_mode___width 1
-#define reg_sser_rw_tr_cfg___od_mode___bit 25
-#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
-#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
-#define reg_sser_rw_tr_cfg_offset 8
-
-/* Register rw_rec_cfg, scope sser, type rw */
-#define reg_sser_rw_rec_cfg___rec_en___lsb 0
-#define reg_sser_rw_rec_cfg___rec_en___width 1
-#define reg_sser_rw_rec_cfg___rec_en___bit 0
-#define reg_sser_rw_rec_cfg___force_eop___lsb 1
-#define reg_sser_rw_rec_cfg___force_eop___width 1
-#define reg_sser_rw_rec_cfg___force_eop___bit 1
-#define reg_sser_rw_rec_cfg___stop___lsb 2
-#define reg_sser_rw_rec_cfg___stop___width 1
-#define reg_sser_rw_rec_cfg___stop___bit 2
-#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
-#define reg_sser_rw_rec_cfg___orun_stop___width 1
-#define reg_sser_rw_rec_cfg___orun_stop___bit 3
-#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
-#define reg_sser_rw_rec_cfg___eop_stop___width 1
-#define reg_sser_rw_rec_cfg___eop_stop___bit 4
-#define reg_sser_rw_rec_cfg___sample_size___lsb 5
-#define reg_sser_rw_rec_cfg___sample_size___width 6
-#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
-#define reg_sser_rw_rec_cfg___sh_dir___width 1
-#define reg_sser_rw_rec_cfg___sh_dir___bit 11
-#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
-#define reg_sser_rw_rec_cfg___clk_pol___width 1
-#define reg_sser_rw_rec_cfg___clk_pol___bit 12
-#define reg_sser_rw_rec_cfg___clk_src___lsb 13
-#define reg_sser_rw_rec_cfg___clk_src___width 1
-#define reg_sser_rw_rec_cfg___clk_src___bit 13
-#define reg_sser_rw_rec_cfg___use_dma___lsb 14
-#define reg_sser_rw_rec_cfg___use_dma___width 1
-#define reg_sser_rw_rec_cfg___use_dma___bit 14
-#define reg_sser_rw_rec_cfg___mode___lsb 15
-#define reg_sser_rw_rec_cfg___mode___width 2
-#define reg_sser_rw_rec_cfg___frm_src___lsb 17
-#define reg_sser_rw_rec_cfg___frm_src___width 2
-#define reg_sser_rw_rec_cfg___use60958___lsb 19
-#define reg_sser_rw_rec_cfg___use60958___width 1
-#define reg_sser_rw_rec_cfg___use60958___bit 19
-#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
-#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
-#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
-#define reg_sser_rw_rec_cfg___slave2_en___width 1
-#define reg_sser_rw_rec_cfg___slave2_en___bit 25
-#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
-#define reg_sser_rw_rec_cfg___slave3_en___width 1
-#define reg_sser_rw_rec_cfg___slave3_en___bit 26
-#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
-#define reg_sser_rw_rec_cfg___fifo_thr___width 2
-#define reg_sser_rw_rec_cfg_offset 12
-
-/* Register rw_tr_data, scope sser, type rw */
-#define reg_sser_rw_tr_data___data___lsb 0
-#define reg_sser_rw_tr_data___data___width 16
-#define reg_sser_rw_tr_data___md___lsb 16
-#define reg_sser_rw_tr_data___md___width 1
-#define reg_sser_rw_tr_data___md___bit 16
-#define reg_sser_rw_tr_data_offset 16
-
-/* Register r_rec_data, scope sser, type r */
-#define reg_sser_r_rec_data___data___lsb 0
-#define reg_sser_r_rec_data___data___width 16
-#define reg_sser_r_rec_data___md___lsb 16
-#define reg_sser_r_rec_data___md___width 1
-#define reg_sser_r_rec_data___md___bit 16
-#define reg_sser_r_rec_data___ext_clk___lsb 17
-#define reg_sser_r_rec_data___ext_clk___width 1
-#define reg_sser_r_rec_data___ext_clk___bit 17
-#define reg_sser_r_rec_data___status_in___lsb 18
-#define reg_sser_r_rec_data___status_in___width 1
-#define reg_sser_r_rec_data___status_in___bit 18
-#define reg_sser_r_rec_data___frame_in___lsb 19
-#define reg_sser_r_rec_data___frame_in___width 1
-#define reg_sser_r_rec_data___frame_in___bit 19
-#define reg_sser_r_rec_data___din___lsb 20
-#define reg_sser_r_rec_data___din___width 1
-#define reg_sser_r_rec_data___din___bit 20
-#define reg_sser_r_rec_data___data_in___lsb 21
-#define reg_sser_r_rec_data___data_in___width 1
-#define reg_sser_r_rec_data___data_in___bit 21
-#define reg_sser_r_rec_data___clk_in___lsb 22
-#define reg_sser_r_rec_data___clk_in___width 1
-#define reg_sser_r_rec_data___clk_in___bit 22
-#define reg_sser_r_rec_data_offset 20
-
-/* Register rw_extra, scope sser, type rw */
-#define reg_sser_rw_extra___clkoff_cycles___lsb 0
-#define reg_sser_rw_extra___clkoff_cycles___width 20
-#define reg_sser_rw_extra___clkoff_en___lsb 20
-#define reg_sser_rw_extra___clkoff_en___width 1
-#define reg_sser_rw_extra___clkoff_en___bit 20
-#define reg_sser_rw_extra___clkon_en___lsb 21
-#define reg_sser_rw_extra___clkon_en___width 1
-#define reg_sser_rw_extra___clkon_en___bit 21
-#define reg_sser_rw_extra___dout_delay___lsb 22
-#define reg_sser_rw_extra___dout_delay___width 5
-#define reg_sser_rw_extra_offset 24
-
-/* Register rw_intr_mask, scope sser, type rw */
-#define reg_sser_rw_intr_mask___trdy___lsb 0
-#define reg_sser_rw_intr_mask___trdy___width 1
-#define reg_sser_rw_intr_mask___trdy___bit 0
-#define reg_sser_rw_intr_mask___rdav___lsb 1
-#define reg_sser_rw_intr_mask___rdav___width 1
-#define reg_sser_rw_intr_mask___rdav___bit 1
-#define reg_sser_rw_intr_mask___tidle___lsb 2
-#define reg_sser_rw_intr_mask___tidle___width 1
-#define reg_sser_rw_intr_mask___tidle___bit 2
-#define reg_sser_rw_intr_mask___rstop___lsb 3
-#define reg_sser_rw_intr_mask___rstop___width 1
-#define reg_sser_rw_intr_mask___rstop___bit 3
-#define reg_sser_rw_intr_mask___urun___lsb 4
-#define reg_sser_rw_intr_mask___urun___width 1
-#define reg_sser_rw_intr_mask___urun___bit 4
-#define reg_sser_rw_intr_mask___orun___lsb 5
-#define reg_sser_rw_intr_mask___orun___width 1
-#define reg_sser_rw_intr_mask___orun___bit 5
-#define reg_sser_rw_intr_mask___md_rec___lsb 6
-#define reg_sser_rw_intr_mask___md_rec___width 1
-#define reg_sser_rw_intr_mask___md_rec___bit 6
-#define reg_sser_rw_intr_mask___md_sent___lsb 7
-#define reg_sser_rw_intr_mask___md_sent___width 1
-#define reg_sser_rw_intr_mask___md_sent___bit 7
-#define reg_sser_rw_intr_mask___r958err___lsb 8
-#define reg_sser_rw_intr_mask___r958err___width 1
-#define reg_sser_rw_intr_mask___r958err___bit 8
-#define reg_sser_rw_intr_mask_offset 28
-
-/* Register rw_ack_intr, scope sser, type rw */
-#define reg_sser_rw_ack_intr___trdy___lsb 0
-#define reg_sser_rw_ack_intr___trdy___width 1
-#define reg_sser_rw_ack_intr___trdy___bit 0
-#define reg_sser_rw_ack_intr___rdav___lsb 1
-#define reg_sser_rw_ack_intr___rdav___width 1
-#define reg_sser_rw_ack_intr___rdav___bit 1
-#define reg_sser_rw_ack_intr___tidle___lsb 2
-#define reg_sser_rw_ack_intr___tidle___width 1
-#define reg_sser_rw_ack_intr___tidle___bit 2
-#define reg_sser_rw_ack_intr___rstop___lsb 3
-#define reg_sser_rw_ack_intr___rstop___width 1
-#define reg_sser_rw_ack_intr___rstop___bit 3
-#define reg_sser_rw_ack_intr___urun___lsb 4
-#define reg_sser_rw_ack_intr___urun___width 1
-#define reg_sser_rw_ack_intr___urun___bit 4
-#define reg_sser_rw_ack_intr___orun___lsb 5
-#define reg_sser_rw_ack_intr___orun___width 1
-#define reg_sser_rw_ack_intr___orun___bit 5
-#define reg_sser_rw_ack_intr___md_rec___lsb 6
-#define reg_sser_rw_ack_intr___md_rec___width 1
-#define reg_sser_rw_ack_intr___md_rec___bit 6
-#define reg_sser_rw_ack_intr___md_sent___lsb 7
-#define reg_sser_rw_ack_intr___md_sent___width 1
-#define reg_sser_rw_ack_intr___md_sent___bit 7
-#define reg_sser_rw_ack_intr___r958err___lsb 8
-#define reg_sser_rw_ack_intr___r958err___width 1
-#define reg_sser_rw_ack_intr___r958err___bit 8
-#define reg_sser_rw_ack_intr_offset 32
-
-/* Register r_intr, scope sser, type r */
-#define reg_sser_r_intr___trdy___lsb 0
-#define reg_sser_r_intr___trdy___width 1
-#define reg_sser_r_intr___trdy___bit 0
-#define reg_sser_r_intr___rdav___lsb 1
-#define reg_sser_r_intr___rdav___width 1
-#define reg_sser_r_intr___rdav___bit 1
-#define reg_sser_r_intr___tidle___lsb 2
-#define reg_sser_r_intr___tidle___width 1
-#define reg_sser_r_intr___tidle___bit 2
-#define reg_sser_r_intr___rstop___lsb 3
-#define reg_sser_r_intr___rstop___width 1
-#define reg_sser_r_intr___rstop___bit 3
-#define reg_sser_r_intr___urun___lsb 4
-#define reg_sser_r_intr___urun___width 1
-#define reg_sser_r_intr___urun___bit 4
-#define reg_sser_r_intr___orun___lsb 5
-#define reg_sser_r_intr___orun___width 1
-#define reg_sser_r_intr___orun___bit 5
-#define reg_sser_r_intr___md_rec___lsb 6
-#define reg_sser_r_intr___md_rec___width 1
-#define reg_sser_r_intr___md_rec___bit 6
-#define reg_sser_r_intr___md_sent___lsb 7
-#define reg_sser_r_intr___md_sent___width 1
-#define reg_sser_r_intr___md_sent___bit 7
-#define reg_sser_r_intr___r958err___lsb 8
-#define reg_sser_r_intr___r958err___width 1
-#define reg_sser_r_intr___r958err___bit 8
-#define reg_sser_r_intr_offset 36
-
-/* Register r_masked_intr, scope sser, type r */
-#define reg_sser_r_masked_intr___trdy___lsb 0
-#define reg_sser_r_masked_intr___trdy___width 1
-#define reg_sser_r_masked_intr___trdy___bit 0
-#define reg_sser_r_masked_intr___rdav___lsb 1
-#define reg_sser_r_masked_intr___rdav___width 1
-#define reg_sser_r_masked_intr___rdav___bit 1
-#define reg_sser_r_masked_intr___tidle___lsb 2
-#define reg_sser_r_masked_intr___tidle___width 1
-#define reg_sser_r_masked_intr___tidle___bit 2
-#define reg_sser_r_masked_intr___rstop___lsb 3
-#define reg_sser_r_masked_intr___rstop___width 1
-#define reg_sser_r_masked_intr___rstop___bit 3
-#define reg_sser_r_masked_intr___urun___lsb 4
-#define reg_sser_r_masked_intr___urun___width 1
-#define reg_sser_r_masked_intr___urun___bit 4
-#define reg_sser_r_masked_intr___orun___lsb 5
-#define reg_sser_r_masked_intr___orun___width 1
-#define reg_sser_r_masked_intr___orun___bit 5
-#define reg_sser_r_masked_intr___md_rec___lsb 6
-#define reg_sser_r_masked_intr___md_rec___width 1
-#define reg_sser_r_masked_intr___md_rec___bit 6
-#define reg_sser_r_masked_intr___md_sent___lsb 7
-#define reg_sser_r_masked_intr___md_sent___width 1
-#define reg_sser_r_masked_intr___md_sent___bit 7
-#define reg_sser_r_masked_intr___r958err___lsb 8
-#define reg_sser_r_masked_intr___r958err___width 1
-#define reg_sser_r_masked_intr___r958err___bit 8
-#define reg_sser_r_masked_intr_offset 40
-
-
-/* Constants */
-#define regk_sser_both 0x00000002
-#define regk_sser_bulk 0x00000001
-#define regk_sser_clk100 0x00000000
-#define regk_sser_clk_in 0x00000000
-#define regk_sser_const0 0x00000003
-#define regk_sser_dout 0x00000002
-#define regk_sser_edge 0x00000000
-#define regk_sser_ext 0x00000001
-#define regk_sser_ext_clk 0x00000001
-#define regk_sser_f100 0x00000000
-#define regk_sser_f29_493 0x00000004
-#define regk_sser_f32 0x00000005
-#define regk_sser_f32_768 0x00000006
-#define regk_sser_frm 0x00000003
-#define regk_sser_gio0 0x00000000
-#define regk_sser_gio1 0x00000001
-#define regk_sser_hispeed 0x00000001
-#define regk_sser_hold 0x00000002
-#define regk_sser_in 0x00000000
-#define regk_sser_inf 0x00000003
-#define regk_sser_intern 0x00000000
-#define regk_sser_intern_clk 0x00000001
-#define regk_sser_intern_tb 0x00000000
-#define regk_sser_iso 0x00000000
-#define regk_sser_level 0x00000001
-#define regk_sser_lospeed 0x00000000
-#define regk_sser_lsbfirst 0x00000000
-#define regk_sser_msbfirst 0x00000001
-#define regk_sser_neg 0x00000001
-#define regk_sser_neg_lo 0x00000000
-#define regk_sser_no 0x00000000
-#define regk_sser_no_clk 0x00000007
-#define regk_sser_nojitter 0x00000002
-#define regk_sser_out 0x00000001
-#define regk_sser_pos 0x00000000
-#define regk_sser_pos_hi 0x00000001
-#define regk_sser_rec 0x00000000
-#define regk_sser_rw_cfg_default 0x00000000
-#define regk_sser_rw_extra_default 0x00000000
-#define regk_sser_rw_frm_cfg_default 0x00000000
-#define regk_sser_rw_intr_mask_default 0x00000000
-#define regk_sser_rw_rec_cfg_default 0x00000000
-#define regk_sser_rw_tr_cfg_default 0x01800000
-#define regk_sser_rw_tr_data_default 0x00000000
-#define regk_sser_thr16 0x00000001
-#define regk_sser_thr32 0x00000002
-#define regk_sser_thr8 0x00000000
-#define regk_sser_tr 0x00000001
-#define regk_sser_ts_out 0x00000003
-#define regk_sser_tx_bulk 0x00000002
-#define regk_sser_wiresave 0x00000002
-#define regk_sser_yes 0x00000001
-#endif /* __sser_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h
deleted file mode 100644
index fab117b00ab6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strcop_defs_asm_h
-#define __strcop_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strcop/rtl/strcop_regs.r
- * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
- * last modfied: Mon Apr 11 16:09:38 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
- * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope strcop, type rw */
-#define reg_strcop_rw_cfg___td3___lsb 0
-#define reg_strcop_rw_cfg___td3___width 1
-#define reg_strcop_rw_cfg___td3___bit 0
-#define reg_strcop_rw_cfg___td2___lsb 1
-#define reg_strcop_rw_cfg___td2___width 1
-#define reg_strcop_rw_cfg___td2___bit 1
-#define reg_strcop_rw_cfg___td1___lsb 2
-#define reg_strcop_rw_cfg___td1___width 1
-#define reg_strcop_rw_cfg___td1___bit 2
-#define reg_strcop_rw_cfg___ipend___lsb 3
-#define reg_strcop_rw_cfg___ipend___width 1
-#define reg_strcop_rw_cfg___ipend___bit 3
-#define reg_strcop_rw_cfg___ignore_sync___lsb 4
-#define reg_strcop_rw_cfg___ignore_sync___width 1
-#define reg_strcop_rw_cfg___ignore_sync___bit 4
-#define reg_strcop_rw_cfg___en___lsb 5
-#define reg_strcop_rw_cfg___en___width 1
-#define reg_strcop_rw_cfg___en___bit 5
-#define reg_strcop_rw_cfg_offset 0
-
-
-/* Constants */
-#define regk_strcop_big 0x00000001
-#define regk_strcop_d 0x00000001
-#define regk_strcop_e 0x00000000
-#define regk_strcop_little 0x00000000
-#define regk_strcop_rw_cfg_default 0x00000002
-#endif /* __strcop_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h
deleted file mode 100644
index 73755fa8a526..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strmux_defs_asm_h
-#define __strmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
- * last modfied: Mon Apr 11 16:09:43 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope strmux, type rw */
-#define reg_strmux_rw_cfg___dma0___lsb 0
-#define reg_strmux_rw_cfg___dma0___width 3
-#define reg_strmux_rw_cfg___dma1___lsb 3
-#define reg_strmux_rw_cfg___dma1___width 3
-#define reg_strmux_rw_cfg___dma2___lsb 6
-#define reg_strmux_rw_cfg___dma2___width 3
-#define reg_strmux_rw_cfg___dma3___lsb 9
-#define reg_strmux_rw_cfg___dma3___width 3
-#define reg_strmux_rw_cfg___dma4___lsb 12
-#define reg_strmux_rw_cfg___dma4___width 3
-#define reg_strmux_rw_cfg___dma5___lsb 15
-#define reg_strmux_rw_cfg___dma5___width 3
-#define reg_strmux_rw_cfg___dma6___lsb 18
-#define reg_strmux_rw_cfg___dma6___width 3
-#define reg_strmux_rw_cfg___dma7___lsb 21
-#define reg_strmux_rw_cfg___dma7___width 3
-#define reg_strmux_rw_cfg___dma8___lsb 24
-#define reg_strmux_rw_cfg___dma8___width 3
-#define reg_strmux_rw_cfg___dma9___lsb 27
-#define reg_strmux_rw_cfg___dma9___width 3
-#define reg_strmux_rw_cfg_offset 0
-
-
-/* Constants */
-#define regk_strmux_ata 0x00000003
-#define regk_strmux_eth0 0x00000001
-#define regk_strmux_eth1 0x00000004
-#define regk_strmux_ext0 0x00000001
-#define regk_strmux_ext1 0x00000001
-#define regk_strmux_ext2 0x00000001
-#define regk_strmux_ext3 0x00000001
-#define regk_strmux_iop0 0x00000002
-#define regk_strmux_iop1 0x00000001
-#define regk_strmux_off 0x00000000
-#define regk_strmux_p21 0x00000004
-#define regk_strmux_rw_cfg_default 0x00000000
-#define regk_strmux_ser0 0x00000002
-#define regk_strmux_ser1 0x00000002
-#define regk_strmux_ser2 0x00000004
-#define regk_strmux_ser3 0x00000003
-#define regk_strmux_sser0 0x00000003
-#define regk_strmux_sser1 0x00000003
-#define regk_strmux_strcop 0x00000002
-#endif /* __strmux_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index cc67986d7437..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- * last modfied: Mon Apr 11 16:09:53 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext 0x00000001
-#define regk_timer_f100 0x00000007
-#define regk_timer_f29_493 0x00000004
-#define regk_timer_f32 0x00000005
-#define regk_timer_f32_768 0x00000006
-#define regk_timer_hold 0x00000001
-#define regk_timer_ld 0x00000000
-#define regk_timer_no 0x00000000
-#define regk_timer_off 0x00000000
-#define regk_timer_run 0x00000002
-#define regk_timer_rw_cnt_cfg_default 0x00000000
-#define regk_timer_rw_intr_mask_default 0x00000000
-#define regk_timer_rw_out_default 0x00000000
-#define regk_timer_rw_test_default 0x00000000
-#define regk_timer_rw_tmr0_ctrl_default 0x00000000
-#define regk_timer_rw_tmr1_ctrl_default 0x00000000
-#define regk_timer_rw_trig_cfg_default 0x00000000
-#define regk_timer_start 0x00000001
-#define regk_timer_stop 0x00000000
-#define regk_timer_time 0x00000001
-#define regk_timer_tmr0 0x00000002
-#define regk_timer_tmr1 0x00000003
-#define regk_timer_yes 0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h
deleted file mode 100644
index 2a8adbcf75d8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ata_defs_h
-#define __ata_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ata/rtl/ata_regs.r
- * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
- * last modfied: Mon Apr 11 16:06:25 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
- * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ata */
-
-/* Register rw_ctrl0, scope ata, type rw */
-typedef struct {
- unsigned int pio_hold : 6;
- unsigned int pio_strb : 6;
- unsigned int pio_setup : 6;
- unsigned int dma_hold : 6;
- unsigned int dma_strb : 6;
- unsigned int rst : 1;
- unsigned int en : 1;
-} reg_ata_rw_ctrl0;
-#define REG_RD_ADDR_ata_rw_ctrl0 12
-#define REG_WR_ADDR_ata_rw_ctrl0 12
-
-/* Register rw_ctrl1, scope ata, type rw */
-typedef struct {
- unsigned int udma_tcyc : 4;
- unsigned int udma_tdvs : 4;
- unsigned int dummy1 : 24;
-} reg_ata_rw_ctrl1;
-#define REG_RD_ADDR_ata_rw_ctrl1 16
-#define REG_WR_ADDR_ata_rw_ctrl1 16
-
-/* Register rw_ctrl2, scope ata, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 3;
- unsigned int dma_size : 1;
- unsigned int multi : 1;
- unsigned int hsh : 2;
- unsigned int trf_mode : 1;
- unsigned int rw : 1;
- unsigned int addr : 3;
- unsigned int cs0 : 1;
- unsigned int cs1 : 1;
- unsigned int sel : 2;
-} reg_ata_rw_ctrl2;
-#define REG_RD_ADDR_ata_rw_ctrl2 0
-#define REG_WR_ADDR_ata_rw_ctrl2 0
-
-/* Register rs_stat_data, scope ata, type rs */
-typedef struct {
- unsigned int data : 16;
- unsigned int dav : 1;
- unsigned int busy : 1;
- unsigned int dummy1 : 14;
-} reg_ata_rs_stat_data;
-#define REG_RD_ADDR_ata_rs_stat_data 4
-
-/* Register r_stat_data, scope ata, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int dav : 1;
- unsigned int busy : 1;
- unsigned int dummy1 : 14;
-} reg_ata_r_stat_data;
-#define REG_RD_ADDR_ata_r_stat_data 8
-
-/* Register rw_trf_cnt, scope ata, type rw */
-typedef struct {
- unsigned int cnt : 17;
- unsigned int dummy1 : 15;
-} reg_ata_rw_trf_cnt;
-#define REG_RD_ADDR_ata_rw_trf_cnt 20
-#define REG_WR_ADDR_ata_rw_trf_cnt 20
-
-/* Register r_stat_misc, scope ata, type r */
-typedef struct {
- unsigned int crc : 16;
- unsigned int dummy1 : 16;
-} reg_ata_r_stat_misc;
-#define REG_RD_ADDR_ata_r_stat_misc 24
-
-/* Register rw_intr_mask, scope ata, type rw */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_rw_intr_mask;
-#define REG_RD_ADDR_ata_rw_intr_mask 28
-#define REG_WR_ADDR_ata_rw_intr_mask 28
-
-/* Register rw_ack_intr, scope ata, type rw */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_rw_ack_intr;
-#define REG_RD_ADDR_ata_rw_ack_intr 32
-#define REG_WR_ADDR_ata_rw_ack_intr 32
-
-/* Register r_intr, scope ata, type r */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_r_intr;
-#define REG_RD_ADDR_ata_r_intr 36
-
-/* Register r_masked_intr, scope ata, type r */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_r_masked_intr;
-#define REG_RD_ADDR_ata_r_masked_intr 40
-
-
-/* Constants */
-enum {
- regk_ata_active = 0x00000001,
- regk_ata_byte = 0x00000001,
- regk_ata_data = 0x00000001,
- regk_ata_dma = 0x00000001,
- regk_ata_inactive = 0x00000000,
- regk_ata_no = 0x00000000,
- regk_ata_nodata = 0x00000000,
- regk_ata_pio = 0x00000000,
- regk_ata_rd = 0x00000001,
- regk_ata_reg = 0x00000000,
- regk_ata_rw_ctrl0_default = 0x00000000,
- regk_ata_rw_ctrl2_default = 0x00000000,
- regk_ata_rw_intr_mask_default = 0x00000000,
- regk_ata_udma = 0x00000002,
- regk_ata_word = 0x00000000,
- regk_ata_wr = 0x00000000,
- regk_ata_yes = 0x00000001
-};
-#endif /* __ata_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h
deleted file mode 100644
index 054841c45466..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_h
-#define __bif_core_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_core */
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp1_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
-#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp2_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
-#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 2;
- unsigned int gated_csp0 : 2;
- unsigned int gated_csp1 : 2;
- unsigned int gated_csp2 : 2;
- unsigned int gated_csp3 : 2;
-} reg_bif_core_rw_grp3_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
-#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 4;
- unsigned int gated_csp4 : 2;
- unsigned int gated_csp5 : 2;
- unsigned int gated_csp6 : 2;
-} reg_bif_core_rw_grp4_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
-#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int grp_sel : 5;
- unsigned int dummy1 : 12;
-} reg_bif_core_rw_sdram_cfg_grp0;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int dummy1 : 17;
-} reg_bif_core_rw_sdram_cfg_grp1;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-typedef struct {
- unsigned int cl : 3;
- unsigned int rcd : 3;
- unsigned int rp : 3;
- unsigned int rc : 2;
- unsigned int dpl : 2;
- unsigned int pde : 1;
- unsigned int ref : 2;
- unsigned int cpd : 1;
- unsigned int sdcke : 1;
- unsigned int sdclk : 1;
- unsigned int dummy1 : 13;
-} reg_bif_core_rw_sdram_timing;
-#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
-#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-typedef struct {
- unsigned int cmd : 3;
- unsigned int mrs_data : 15;
- unsigned int dummy1 : 14;
-} reg_bif_core_rw_sdram_cmd;
-#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
-#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_rs_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_r_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
-
-
-/* Constants */
-enum {
- regk_bif_core_bank2 = 0x00000000,
- regk_bif_core_bank4 = 0x00000001,
- regk_bif_core_bit10 = 0x0000000a,
- regk_bif_core_bit11 = 0x0000000b,
- regk_bif_core_bit12 = 0x0000000c,
- regk_bif_core_bit13 = 0x0000000d,
- regk_bif_core_bit14 = 0x0000000e,
- regk_bif_core_bit15 = 0x0000000f,
- regk_bif_core_bit16 = 0x00000010,
- regk_bif_core_bit17 = 0x00000011,
- regk_bif_core_bit18 = 0x00000012,
- regk_bif_core_bit19 = 0x00000013,
- regk_bif_core_bit20 = 0x00000014,
- regk_bif_core_bit21 = 0x00000015,
- regk_bif_core_bit22 = 0x00000016,
- regk_bif_core_bit23 = 0x00000017,
- regk_bif_core_bit24 = 0x00000018,
- regk_bif_core_bit25 = 0x00000019,
- regk_bif_core_bit26 = 0x0000001a,
- regk_bif_core_bit27 = 0x0000001b,
- regk_bif_core_bit28 = 0x0000001c,
- regk_bif_core_bit29 = 0x0000001d,
- regk_bif_core_bit9 = 0x00000009,
- regk_bif_core_bw16 = 0x00000001,
- regk_bif_core_bw32 = 0x00000000,
- regk_bif_core_bwe = 0x00000000,
- regk_bif_core_cwe = 0x00000001,
- regk_bif_core_e15us = 0x00000001,
- regk_bif_core_e7800ns = 0x00000002,
- regk_bif_core_grp0 = 0x00000000,
- regk_bif_core_grp1 = 0x00000001,
- regk_bif_core_mrs = 0x00000003,
- regk_bif_core_no = 0x00000000,
- regk_bif_core_none = 0x00000000,
- regk_bif_core_nop = 0x00000000,
- regk_bif_core_off = 0x00000000,
- regk_bif_core_pre = 0x00000002,
- regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rd = 0x00000002,
- regk_bif_core_ref = 0x00000001,
- regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
- regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
- regk_bif_core_slf = 0x00000004,
- regk_bif_core_wr = 0x00000001,
- regk_bif_core_yes = 0x00000001
-};
-#endif /* __bif_core_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h
deleted file mode 100644
index 5c4abf5c0167..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_dma_defs_h
-#define __bif_dma_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_dma_regs.r
- * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
- * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_dma */
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch0_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
-#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch0_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
-#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch0_start;
-#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
-#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch0_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
-#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch0_stat;
-#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch1_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
-#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch1_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
-#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch1_start;
-#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
-#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch1_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
-#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch1_stat;
-#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch2_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
-#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch2_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
-#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch2_start;
-#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
-#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch2_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
-#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch2_stat;
-#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch3_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
-#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch3_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
-#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch3_start;
-#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
-#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch3_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
-#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch3_stat;
-#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_intr_mask;
-#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
-#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_ack_intr;
-#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
-#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
-
-/* Register r_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_intr;
-#define REG_RD_ADDR_bif_dma_r_intr 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_masked_intr;
-#define REG_RD_ADDR_bif_dma_r_masked_intr 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin0_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
-#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin1_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
-#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin2_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
-#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin3_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
-#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin4_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
-#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin5_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
-#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin6_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
-#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin7_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
-#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int pin0 : 1;
- unsigned int pin1 : 1;
- unsigned int pin2 : 1;
- unsigned int pin3 : 1;
- unsigned int pin4 : 1;
- unsigned int pin5 : 1;
- unsigned int pin6 : 1;
- unsigned int pin7 : 1;
- unsigned int dummy1 : 24;
-} reg_bif_dma_r_pin_stat;
-#define REG_RD_ADDR_bif_dma_r_pin_stat 192
-
-
-/* Constants */
-enum {
- regk_bif_dma_as_master = 0x00000001,
- regk_bif_dma_as_slave = 0x00000001,
- regk_bif_dma_burst1 = 0x00000000,
- regk_bif_dma_burst8 = 0x00000001,
- regk_bif_dma_bw16 = 0x00000001,
- regk_bif_dma_bw32 = 0x00000002,
- regk_bif_dma_bw8 = 0x00000000,
- regk_bif_dma_dack = 0x00000006,
- regk_bif_dma_dack_inv = 0x00000007,
- regk_bif_dma_force = 0x00000001,
- regk_bif_dma_hi = 0x00000003,
- regk_bif_dma_inv = 0x00000003,
- regk_bif_dma_lo = 0x00000002,
- regk_bif_dma_master = 0x00000001,
- regk_bif_dma_no = 0x00000000,
- regk_bif_dma_norm = 0x00000002,
- regk_bif_dma_off = 0x00000000,
- regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch0_start_default = 0x00000000,
- regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch1_start_default = 0x00000000,
- regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch2_start_default = 0x00000000,
- regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch3_start_default = 0x00000000,
- regk_bif_dma_rw_intr_mask_default = 0x00000000,
- regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
- regk_bif_dma_slave = 0x00000002,
- regk_bif_dma_sreq = 0x00000006,
- regk_bif_dma_sreq_inv = 0x00000007,
- regk_bif_dma_tc = 0x00000004,
- regk_bif_dma_tc_inv = 0x00000005,
- regk_bif_dma_yes = 0x00000001
-};
-#endif /* __bif_dma_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h
deleted file mode 100644
index 80c740b3c785..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_slave_defs_h
-#define __bif_slave_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_slave_regs.r
- * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- * last modfied: Mon Apr 11 16:06:34 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
- * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_slave */
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int slave_id : 3;
- unsigned int use_slave_id : 1;
- unsigned int boot_rdy : 1;
- unsigned int loopback : 1;
- unsigned int dis : 1;
- unsigned int dummy1 : 25;
-} reg_bif_slave_rw_slave_cfg;
-#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
-#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-typedef struct {
- unsigned int ch0_mode : 1;
- unsigned int ch1_mode : 1;
- unsigned int ch2_mode : 1;
- unsigned int ch3_mode : 1;
- unsigned int dummy1 : 28;
-} reg_bif_slave_r_slave_mode;
-#define REG_RD_ADDR_bif_slave_r_slave_mode 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch0_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
-#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch1_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
-#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch2_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
-#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch3_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
-#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int brin_mode : 1;
- unsigned int brout_mode : 3;
- unsigned int bg_mode : 3;
- unsigned int release : 2;
- unsigned int acquire : 1;
- unsigned int settle_time : 2;
- unsigned int dram_ctrl : 1;
- unsigned int dummy1 : 19;
-} reg_bif_slave_rw_arb_cfg;
-#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
-#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-typedef struct {
- unsigned int init_mode : 1;
- unsigned int mode : 1;
- unsigned int brin : 1;
- unsigned int brout : 1;
- unsigned int bg : 1;
- unsigned int dummy1 : 27;
-} reg_bif_slave_r_arb_stat;
-#define REG_RD_ADDR_bif_slave_r_arb_stat 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_intr_mask;
-#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
-#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_ack_intr;
-#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
-#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
-
-/* Register r_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_intr;
-#define REG_RD_ADDR_bif_slave_r_intr 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_masked_intr;
-#define REG_RD_ADDR_bif_slave_r_masked_intr 76
-
-
-/* Constants */
-enum {
- regk_bif_slave_active_hi = 0x00000003,
- regk_bif_slave_active_lo = 0x00000002,
- regk_bif_slave_addr = 0x00000000,
- regk_bif_slave_always = 0x00000001,
- regk_bif_slave_at_idle = 0x00000002,
- regk_bif_slave_burst_end = 0x00000003,
- regk_bif_slave_dma = 0x00000001,
- regk_bif_slave_hi = 0x00000003,
- regk_bif_slave_inv = 0x00000001,
- regk_bif_slave_lo = 0x00000002,
- regk_bif_slave_local = 0x00000001,
- regk_bif_slave_master = 0x00000000,
- regk_bif_slave_mode_reg = 0x00000001,
- regk_bif_slave_no = 0x00000000,
- regk_bif_slave_norm = 0x00000000,
- regk_bif_slave_on_access = 0x00000000,
- regk_bif_slave_rw_arb_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
- regk_bif_slave_rw_intr_mask_default = 0x00000000,
- regk_bif_slave_rw_slave_cfg_default = 0x00000000,
- regk_bif_slave_shared = 0x00000000,
- regk_bif_slave_slave = 0x00000001,
- regk_bif_slave_t0ns = 0x00000003,
- regk_bif_slave_t10ns = 0x00000002,
- regk_bif_slave_t20ns = 0x00000003,
- regk_bif_slave_t30ns = 0x00000002,
- regk_bif_slave_t40ns = 0x00000001,
- regk_bif_slave_t50ns = 0x00000000,
- regk_bif_slave_yes = 0x00000001,
- regk_bif_slave_z = 0x00000004
-};
-#endif /* __bif_slave_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h b/arch/cris/include/arch-v32/arch/hwregs/config_defs.h
deleted file mode 100644
index 1c5da14f27f3..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_h
-#define __config_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
- * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope config */
-
-/* Register r_bootsel, scope config, type r */
-typedef struct {
- unsigned int boot_mode : 3;
- unsigned int full_duplex : 1;
- unsigned int user : 1;
- unsigned int pll : 1;
- unsigned int flash_bw : 1;
- unsigned int dummy1 : 25;
-} reg_config_r_bootsel;
-#define REG_RD_ADDR_config_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-typedef struct {
- unsigned int pll : 1;
- unsigned int cpu : 1;
- unsigned int iop : 1;
- unsigned int dma01_eth0 : 1;
- unsigned int dma23 : 1;
- unsigned int dma45 : 1;
- unsigned int dma67 : 1;
- unsigned int dma89_strcop : 1;
- unsigned int bif : 1;
- unsigned int fix_io : 1;
- unsigned int dummy1 : 22;
-} reg_config_rw_clk_ctrl;
-#define REG_RD_ADDR_config_rw_clk_ctrl 4
-#define REG_WR_ADDR_config_rw_clk_ctrl 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-typedef struct {
- unsigned int usb_susp : 1;
- unsigned int phyrst_n : 1;
- unsigned int dummy1 : 30;
-} reg_config_rw_pad_ctrl;
-#define REG_RD_ADDR_config_rw_pad_ctrl 8
-#define REG_WR_ADDR_config_rw_pad_ctrl 8
-
-
-/* Constants */
-enum {
- regk_config_bw16 = 0x00000000,
- regk_config_bw32 = 0x00000001,
- regk_config_master = 0x00000005,
- regk_config_nand = 0x00000003,
- regk_config_net_rx = 0x00000001,
- regk_config_net_tx_rx = 0x00000002,
- regk_config_no = 0x00000000,
- regk_config_none = 0x00000007,
- regk_config_nor = 0x00000000,
- regk_config_rw_clk_ctrl_default = 0x00000002,
- regk_config_rw_pad_ctrl_default = 0x00000000,
- regk_config_ser = 0x00000004,
- regk_config_slave = 0x00000006,
- regk_config_yes = 0x00000001
-};
-#endif /* __config_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h
deleted file mode 100644
index 913f918bba14..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/crisp/doc/cpu_vect.r
-version . */
-
-#ifndef _______INST_CRISP_DOC_CPU_VECT_R
-#define _______INST_CRISP_DOC_CPU_VECT_R
-#define NMI_INTR_VECT 0x00
-#define RESERVED_1_INTR_VECT 0x01
-#define RESERVED_2_INTR_VECT 0x02
-#define SINGLE_STEP_INTR_VECT 0x03
-#define INSTR_TLB_REFILL_INTR_VECT 0x04
-#define INSTR_TLB_INV_INTR_VECT 0x05
-#define INSTR_TLB_ACC_INTR_VECT 0x06
-#define TLB_EX_INTR_VECT 0x07
-#define DATA_TLB_REFILL_INTR_VECT 0x08
-#define DATA_TLB_INV_INTR_VECT 0x09
-#define DATA_TLB_ACC_INTR_VECT 0x0a
-#define DATA_TLB_WE_INTR_VECT 0x0b
-#define HW_BP_INTR_VECT 0x0c
-#define RESERVED_D_INTR_VECT 0x0d
-#define RESERVED_E_INTR_VECT 0x0e
-#define RESERVED_F_INTR_VECT 0x0f
-#define BREAK_0_INTR_VECT 0x10
-#define BREAK_1_INTR_VECT 0x11
-#define BREAK_2_INTR_VECT 0x12
-#define BREAK_3_INTR_VECT 0x13
-#define BREAK_4_INTR_VECT 0x14
-#define BREAK_5_INTR_VECT 0x15
-#define BREAK_6_INTR_VECT 0x16
-#define BREAK_7_INTR_VECT 0x17
-#define BREAK_8_INTR_VECT 0x18
-#define BREAK_9_INTR_VECT 0x19
-#define BREAK_10_INTR_VECT 0x1a
-#define BREAK_11_INTR_VECT 0x1b
-#define BREAK_12_INTR_VECT 0x1c
-#define BREAK_13_INTR_VECT 0x1d
-#define BREAK_14_INTR_VECT 0x1e
-#define BREAK_15_INTR_VECT 0x1f
-#define MULTIPLE_INTR_VECT 0x30
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma.h b/arch/cris/include/arch-v32/arch/hwregs/dma.h
deleted file mode 100644
index dd24c6da09e0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/dma.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DMA C definitions and help macros
- *
- */
-
-#ifndef dma_h
-#define dma_h
-
-/* registers */ /* Really needed, since both are listed in sw.list? */
-#include <arch/hwregs/dma_defs.h>
-
-
-/* descriptors */
-
-// ------------------------------------------------------------ dma_descr_group
-typedef struct dma_descr_group {
- struct dma_descr_group *next;
- unsigned eol : 1;
- unsigned tol : 1;
- unsigned bol : 1;
- unsigned : 1;
- unsigned intr : 1;
- unsigned : 2;
- unsigned en : 1;
- unsigned : 7;
- unsigned dis : 1;
- unsigned md : 16;
- struct dma_descr_group *up;
- union {
- struct dma_descr_context *context;
- struct dma_descr_group *group;
- } down;
-} dma_descr_group;
-
-// ---------------------------------------------------------- dma_descr_context
-typedef struct dma_descr_context {
- struct dma_descr_context *next;
- unsigned eol : 1;
- unsigned : 3;
- unsigned intr : 1;
- unsigned : 1;
- unsigned store_mode : 1;
- unsigned en : 1;
- unsigned : 7;
- unsigned dis : 1;
- unsigned md0 : 16;
- unsigned md1;
- unsigned md2;
- unsigned md3;
- unsigned md4;
- struct dma_descr_data *saved_data;
- char *saved_data_buf;
-} dma_descr_context;
-
-// ------------------------------------------------------------- dma_descr_data
-typedef struct dma_descr_data {
- struct dma_descr_data *next;
- char *buf;
- unsigned eol : 1;
- unsigned : 2;
- unsigned out_eop : 1;
- unsigned intr : 1;
- unsigned wait : 1;
- unsigned : 2;
- unsigned : 3;
- unsigned in_eop : 1;
- unsigned : 4;
- unsigned md : 16;
- char *after;
-} dma_descr_data;
-
-// --------------------------------------------------------------------- macros
-
-// enable DMA channel
-#define DMA_ENABLE( inst ) \
- do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
- e.en = regk_dma_yes; \
- REG_WR( dma, inst, rw_cfg, e); } while( 0 )
-
-// reset DMA channel
-#define DMA_RESET( inst ) \
- do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
- r.en = regk_dma_no; \
- REG_WR( dma, inst, rw_cfg, r); } while( 0 )
-
-// stop DMA channel
-#define DMA_STOP( inst ) \
- do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
- s.stop = regk_dma_yes; \
- REG_WR( dma, inst, rw_cfg, s); } while( 0 )
-
-// continue DMA channel operation
-#define DMA_CONTINUE( inst ) \
- do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
- c.stop = regk_dma_no; \
- REG_WR( dma, inst, rw_cfg, c); } while( 0 )
-
-// give stream command
-#define DMA_WR_CMD( inst, cmd_par ) \
- do { reg_dma_rw_stream_cmd __x = {0}; \
- do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
- __x.cmd = (cmd_par); \
- REG_WR(dma, inst, rw_stream_cmd, __x); \
- } while (0)
-
-// load: g,c,d:burst
-#define DMA_START_GROUP( inst, group_descr ) \
- do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
- DMA_WR_CMD( inst, regk_dma_load_g ); \
- DMA_WR_CMD( inst, regk_dma_load_c ); \
- DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
- } while( 0 )
-
-// load: c,d:burst
-#define DMA_START_CONTEXT( inst, ctx_descr ) \
- do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
- DMA_WR_CMD( inst, regk_dma_load_c ); \
- DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
- } while( 0 )
-
-// if the DMA is at the end of the data list, the last data descr is reloaded
-#define DMA_CONTINUE_DATA( inst ) \
-do { reg_dma_rw_cmd c = {0}; \
- c.cont_data = regk_dma_yes;\
- REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h
deleted file mode 100644
index a67826f5fe21..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __dma_defs_h
-#define __dma_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
- * last modfied: Mon Apr 11 16:06:51 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope dma */
-
-/* Register rw_data, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data;
-#define REG_RD_ADDR_dma_rw_data 0
-#define REG_WR_ADDR_dma_rw_data 0
-
-/* Register rw_data_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_next;
-#define REG_RD_ADDR_dma_rw_data_next 4
-#define REG_WR_ADDR_dma_rw_data_next 4
-
-/* Register rw_data_buf, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_buf;
-#define REG_RD_ADDR_dma_rw_data_buf 8
-#define REG_WR_ADDR_dma_rw_data_buf 8
-
-/* Register rw_data_ctrl, scope dma, type rw */
-typedef struct {
- unsigned int eol : 1;
- unsigned int dummy1 : 2;
- unsigned int out_eop : 1;
- unsigned int intr : 1;
- unsigned int wait : 1;
- unsigned int dummy2 : 26;
-} reg_dma_rw_data_ctrl;
-#define REG_RD_ADDR_dma_rw_data_ctrl 12
-#define REG_WR_ADDR_dma_rw_data_ctrl 12
-
-/* Register rw_data_stat, scope dma, type rw */
-typedef struct {
- unsigned int dummy1 : 3;
- unsigned int in_eop : 1;
- unsigned int dummy2 : 28;
-} reg_dma_rw_data_stat;
-#define REG_RD_ADDR_dma_rw_data_stat 16
-#define REG_WR_ADDR_dma_rw_data_stat 16
-
-/* Register rw_data_md, scope dma, type rw */
-typedef struct {
- unsigned int md : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_data_md;
-#define REG_RD_ADDR_dma_rw_data_md 20
-#define REG_WR_ADDR_dma_rw_data_md 20
-
-/* Register rw_data_md_s, scope dma, type rw */
-typedef struct {
- unsigned int md_s : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_data_md_s;
-#define REG_RD_ADDR_dma_rw_data_md_s 24
-#define REG_WR_ADDR_dma_rw_data_md_s 24
-
-/* Register rw_data_after, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_after;
-#define REG_RD_ADDR_dma_rw_data_after 28
-#define REG_WR_ADDR_dma_rw_data_after 28
-
-/* Register rw_ctxt, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt;
-#define REG_RD_ADDR_dma_rw_ctxt 32
-#define REG_WR_ADDR_dma_rw_ctxt 32
-
-/* Register rw_ctxt_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_next;
-#define REG_RD_ADDR_dma_rw_ctxt_next 36
-#define REG_WR_ADDR_dma_rw_ctxt_next 36
-
-/* Register rw_ctxt_ctrl, scope dma, type rw */
-typedef struct {
- unsigned int eol : 1;
- unsigned int dummy1 : 3;
- unsigned int intr : 1;
- unsigned int dummy2 : 1;
- unsigned int store_mode : 1;
- unsigned int en : 1;
- unsigned int dummy3 : 24;
-} reg_dma_rw_ctxt_ctrl;
-#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
-#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
-
-/* Register rw_ctxt_stat, scope dma, type rw */
-typedef struct {
- unsigned int dummy1 : 7;
- unsigned int dis : 1;
- unsigned int dummy2 : 24;
-} reg_dma_rw_ctxt_stat;
-#define REG_RD_ADDR_dma_rw_ctxt_stat 44
-#define REG_WR_ADDR_dma_rw_ctxt_stat 44
-
-/* Register rw_ctxt_md0, scope dma, type rw */
-typedef struct {
- unsigned int md0 : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_ctxt_md0;
-#define REG_RD_ADDR_dma_rw_ctxt_md0 48
-#define REG_WR_ADDR_dma_rw_ctxt_md0 48
-
-/* Register rw_ctxt_md0_s, scope dma, type rw */
-typedef struct {
- unsigned int md0_s : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_ctxt_md0_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
-#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
-
-/* Register rw_ctxt_md1, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md1;
-#define REG_RD_ADDR_dma_rw_ctxt_md1 56
-#define REG_WR_ADDR_dma_rw_ctxt_md1 56
-
-/* Register rw_ctxt_md1_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md1_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
-#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
-
-/* Register rw_ctxt_md2, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md2;
-#define REG_RD_ADDR_dma_rw_ctxt_md2 64
-#define REG_WR_ADDR_dma_rw_ctxt_md2 64
-
-/* Register rw_ctxt_md2_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md2_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
-#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
-
-/* Register rw_ctxt_md3, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md3;
-#define REG_RD_ADDR_dma_rw_ctxt_md3 72
-#define REG_WR_ADDR_dma_rw_ctxt_md3 72
-
-/* Register rw_ctxt_md3_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md3_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
-#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
-
-/* Register rw_ctxt_md4, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md4;
-#define REG_RD_ADDR_dma_rw_ctxt_md4 80
-#define REG_WR_ADDR_dma_rw_ctxt_md4 80
-
-/* Register rw_ctxt_md4_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md4_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
-#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
-
-/* Register rw_saved_data, scope dma, type rw */
-typedef unsigned int reg_dma_rw_saved_data;
-#define REG_RD_ADDR_dma_rw_saved_data 88
-#define REG_WR_ADDR_dma_rw_saved_data 88
-
-/* Register rw_saved_data_buf, scope dma, type rw */
-typedef unsigned int reg_dma_rw_saved_data_buf;
-#define REG_RD_ADDR_dma_rw_saved_data_buf 92
-#define REG_WR_ADDR_dma_rw_saved_data_buf 92
-
-/* Register rw_group, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group;
-#define REG_RD_ADDR_dma_rw_group 96
-#define REG_WR_ADDR_dma_rw_group 96
-
-/* Register rw_group_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_next;
-#define REG_RD_ADDR_dma_rw_group_next 100
-#define REG_WR_ADDR_dma_rw_group_next 100
-
-/* Register rw_group_ctrl, scope dma, type rw */
-typedef struct {
- unsigned int eol : 1;
- unsigned int tol : 1;
- unsigned int bol : 1;
- unsigned int dummy1 : 1;
- unsigned int intr : 1;
- unsigned int dummy2 : 2;
- unsigned int en : 1;
- unsigned int dummy3 : 24;
-} reg_dma_rw_group_ctrl;
-#define REG_RD_ADDR_dma_rw_group_ctrl 104
-#define REG_WR_ADDR_dma_rw_group_ctrl 104
-
-/* Register rw_group_stat, scope dma, type rw */
-typedef struct {
- unsigned int dummy1 : 7;
- unsigned int dis : 1;
- unsigned int dummy2 : 24;
-} reg_dma_rw_group_stat;
-#define REG_RD_ADDR_dma_rw_group_stat 108
-#define REG_WR_ADDR_dma_rw_group_stat 108
-
-/* Register rw_group_md, scope dma, type rw */
-typedef struct {
- unsigned int md : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_group_md;
-#define REG_RD_ADDR_dma_rw_group_md 112
-#define REG_WR_ADDR_dma_rw_group_md 112
-
-/* Register rw_group_md_s, scope dma, type rw */
-typedef struct {
- unsigned int md_s : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_group_md_s;
-#define REG_RD_ADDR_dma_rw_group_md_s 116
-#define REG_WR_ADDR_dma_rw_group_md_s 116
-
-/* Register rw_group_up, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_up;
-#define REG_RD_ADDR_dma_rw_group_up 120
-#define REG_WR_ADDR_dma_rw_group_up 120
-
-/* Register rw_group_down, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_down;
-#define REG_RD_ADDR_dma_rw_group_down 124
-#define REG_WR_ADDR_dma_rw_group_down 124
-
-/* Register rw_cmd, scope dma, type rw */
-typedef struct {
- unsigned int cont_data : 1;
- unsigned int dummy1 : 31;
-} reg_dma_rw_cmd;
-#define REG_RD_ADDR_dma_rw_cmd 128
-#define REG_WR_ADDR_dma_rw_cmd 128
-
-/* Register rw_cfg, scope dma, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int stop : 1;
- unsigned int dummy1 : 30;
-} reg_dma_rw_cfg;
-#define REG_RD_ADDR_dma_rw_cfg 132
-#define REG_WR_ADDR_dma_rw_cfg 132
-
-/* Register rw_stat, scope dma, type rw */
-typedef struct {
- unsigned int mode : 5;
- unsigned int list_state : 3;
- unsigned int stream_cmd_src : 8;
- unsigned int dummy1 : 8;
- unsigned int buf : 8;
-} reg_dma_rw_stat;
-#define REG_RD_ADDR_dma_rw_stat 136
-#define REG_WR_ADDR_dma_rw_stat 136
-
-/* Register rw_intr_mask, scope dma, type rw */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_rw_intr_mask;
-#define REG_RD_ADDR_dma_rw_intr_mask 140
-#define REG_WR_ADDR_dma_rw_intr_mask 140
-
-/* Register rw_ack_intr, scope dma, type rw */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_rw_ack_intr;
-#define REG_RD_ADDR_dma_rw_ack_intr 144
-#define REG_WR_ADDR_dma_rw_ack_intr 144
-
-/* Register r_intr, scope dma, type r */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_r_intr;
-#define REG_RD_ADDR_dma_r_intr 148
-
-/* Register r_masked_intr, scope dma, type r */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_r_masked_intr;
-#define REG_RD_ADDR_dma_r_masked_intr 152
-
-/* Register rw_stream_cmd, scope dma, type rw */
-typedef struct {
- unsigned int cmd : 10;
- unsigned int dummy1 : 6;
- unsigned int n : 8;
- unsigned int dummy2 : 7;
- unsigned int busy : 1;
-} reg_dma_rw_stream_cmd;
-#define REG_RD_ADDR_dma_rw_stream_cmd 156
-#define REG_WR_ADDR_dma_rw_stream_cmd 156
-
-
-/* Constants */
-enum {
- regk_dma_ack_pkt = 0x00000100,
- regk_dma_anytime = 0x00000001,
- regk_dma_array = 0x00000008,
- regk_dma_burst = 0x00000020,
- regk_dma_client = 0x00000002,
- regk_dma_copy_next = 0x00000010,
- regk_dma_copy_up = 0x00000020,
- regk_dma_data_at_eol = 0x00000001,
- regk_dma_dis_c = 0x00000010,
- regk_dma_dis_g = 0x00000020,
- regk_dma_idle = 0x00000001,
- regk_dma_intern = 0x00000004,
- regk_dma_load_c = 0x00000200,
- regk_dma_load_c_n = 0x00000280,
- regk_dma_load_c_next = 0x00000240,
- regk_dma_load_d = 0x00000140,
- regk_dma_load_g = 0x00000300,
- regk_dma_load_g_down = 0x000003c0,
- regk_dma_load_g_next = 0x00000340,
- regk_dma_load_g_up = 0x00000380,
- regk_dma_next_en = 0x00000010,
- regk_dma_next_pkt = 0x00000010,
- regk_dma_no = 0x00000000,
- regk_dma_only_at_wait = 0x00000000,
- regk_dma_restore = 0x00000020,
- regk_dma_rst = 0x00000001,
- regk_dma_running = 0x00000004,
- regk_dma_rw_cfg_default = 0x00000000,
- regk_dma_rw_cmd_default = 0x00000000,
- regk_dma_rw_intr_mask_default = 0x00000000,
- regk_dma_rw_stat_default = 0x00000101,
- regk_dma_rw_stream_cmd_default = 0x00000000,
- regk_dma_save_down = 0x00000020,
- regk_dma_save_up = 0x00000020,
- regk_dma_set_reg = 0x00000050,
- regk_dma_set_w_size1 = 0x00000190,
- regk_dma_set_w_size2 = 0x000001a0,
- regk_dma_set_w_size4 = 0x000001c0,
- regk_dma_stopped = 0x00000002,
- regk_dma_store_c = 0x00000002,
- regk_dma_store_descr = 0x00000000,
- regk_dma_store_g = 0x00000004,
- regk_dma_store_md = 0x00000001,
- regk_dma_sw = 0x00000008,
- regk_dma_update_down = 0x00000020,
- regk_dma_yes = 0x00000001
-};
-#endif /* __dma_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h
deleted file mode 100644
index d8021b44e5e6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __eth_defs_h
-#define __eth_defs_h
-
-/*
- * This file is autogenerated from
- * file: eth.r
- * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
- * last modfied: Mon Jan 9 06:06:41 2006
- *
- * by /n/asic/design/tools/rdesc/rdes2c eth.r
- * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope eth */
-
-/* Register rw_ma0_lo, scope eth, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_eth_rw_ma0_lo;
-#define REG_RD_ADDR_eth_rw_ma0_lo 0
-#define REG_WR_ADDR_eth_rw_ma0_lo 0
-
-/* Register rw_ma0_hi, scope eth, type rw */
-typedef struct {
- unsigned int addr : 16;
- unsigned int dummy1 : 16;
-} reg_eth_rw_ma0_hi;
-#define REG_RD_ADDR_eth_rw_ma0_hi 4
-#define REG_WR_ADDR_eth_rw_ma0_hi 4
-
-/* Register rw_ma1_lo, scope eth, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_eth_rw_ma1_lo;
-#define REG_RD_ADDR_eth_rw_ma1_lo 8
-#define REG_WR_ADDR_eth_rw_ma1_lo 8
-
-/* Register rw_ma1_hi, scope eth, type rw */
-typedef struct {
- unsigned int addr : 16;
- unsigned int dummy1 : 16;
-} reg_eth_rw_ma1_hi;
-#define REG_RD_ADDR_eth_rw_ma1_hi 12
-#define REG_WR_ADDR_eth_rw_ma1_hi 12
-
-/* Register rw_ga_lo, scope eth, type rw */
-typedef struct {
- unsigned int tbl : 32;
-} reg_eth_rw_ga_lo;
-#define REG_RD_ADDR_eth_rw_ga_lo 16
-#define REG_WR_ADDR_eth_rw_ga_lo 16
-
-/* Register rw_ga_hi, scope eth, type rw */
-typedef struct {
- unsigned int tbl : 32;
-} reg_eth_rw_ga_hi;
-#define REG_RD_ADDR_eth_rw_ga_hi 20
-#define REG_WR_ADDR_eth_rw_ga_hi 20
-
-/* Register rw_gen_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int phy : 2;
- unsigned int protocol : 1;
- unsigned int loopback : 1;
- unsigned int flow_ctrl : 1;
- unsigned int gtxclk_out : 1;
- unsigned int phyrst_n : 1;
- unsigned int dummy1 : 24;
-} reg_eth_rw_gen_ctrl;
-#define REG_RD_ADDR_eth_rw_gen_ctrl 24
-#define REG_WR_ADDR_eth_rw_gen_ctrl 24
-
-/* Register rw_rec_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int ma0 : 1;
- unsigned int ma1 : 1;
- unsigned int individual : 1;
- unsigned int broadcast : 1;
- unsigned int undersize : 1;
- unsigned int oversize : 1;
- unsigned int bad_crc : 1;
- unsigned int duplex : 1;
- unsigned int max_size : 16;
- unsigned int dummy1 : 8;
-} reg_eth_rw_rec_ctrl;
-#define REG_RD_ADDR_eth_rw_rec_ctrl 28
-#define REG_WR_ADDR_eth_rw_rec_ctrl 28
-
-/* Register rw_tr_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int crc : 1;
- unsigned int pad : 1;
- unsigned int retry : 1;
- unsigned int ignore_col : 1;
- unsigned int cancel : 1;
- unsigned int hsh_delay : 1;
- unsigned int ignore_crs : 1;
- unsigned int carrier_ext : 1;
- unsigned int dummy1 : 24;
-} reg_eth_rw_tr_ctrl;
-#define REG_RD_ADDR_eth_rw_tr_ctrl 32
-#define REG_WR_ADDR_eth_rw_tr_ctrl 32
-
-/* Register rw_clr_err, scope eth, type rw */
-typedef struct {
- unsigned int clr : 1;
- unsigned int dummy1 : 31;
-} reg_eth_rw_clr_err;
-#define REG_RD_ADDR_eth_rw_clr_err 36
-#define REG_WR_ADDR_eth_rw_clr_err 36
-
-/* Register rw_mgm_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int mdio : 1;
- unsigned int mdoe : 1;
- unsigned int mdc : 1;
- unsigned int dummy1 : 29;
-} reg_eth_rw_mgm_ctrl;
-#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
-#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
-
-/* Register r_stat, scope eth, type r */
-typedef struct {
- unsigned int mdio : 1;
- unsigned int exc_col : 1;
- unsigned int urun : 1;
- unsigned int clk_125 : 1;
- unsigned int dummy1 : 28;
-} reg_eth_r_stat;
-#define REG_RD_ADDR_eth_r_stat 44
-
-/* Register rs_rec_cnt, scope eth, type rs */
-typedef struct {
- unsigned int crc_err : 8;
- unsigned int align_err : 8;
- unsigned int oversize : 8;
- unsigned int congestion : 8;
-} reg_eth_rs_rec_cnt;
-#define REG_RD_ADDR_eth_rs_rec_cnt 48
-
-/* Register r_rec_cnt, scope eth, type r */
-typedef struct {
- unsigned int crc_err : 8;
- unsigned int align_err : 8;
- unsigned int oversize : 8;
- unsigned int congestion : 8;
-} reg_eth_r_rec_cnt;
-#define REG_RD_ADDR_eth_r_rec_cnt 52
-
-/* Register rs_tr_cnt, scope eth, type rs */
-typedef struct {
- unsigned int single_col : 8;
- unsigned int mult_col : 8;
- unsigned int late_col : 8;
- unsigned int deferred : 8;
-} reg_eth_rs_tr_cnt;
-#define REG_RD_ADDR_eth_rs_tr_cnt 56
-
-/* Register r_tr_cnt, scope eth, type r */
-typedef struct {
- unsigned int single_col : 8;
- unsigned int mult_col : 8;
- unsigned int late_col : 8;
- unsigned int deferred : 8;
-} reg_eth_r_tr_cnt;
-#define REG_RD_ADDR_eth_r_tr_cnt 60
-
-/* Register rs_phy_cnt, scope eth, type rs */
-typedef struct {
- unsigned int carrier_loss : 8;
- unsigned int sqe_err : 8;
- unsigned int dummy1 : 16;
-} reg_eth_rs_phy_cnt;
-#define REG_RD_ADDR_eth_rs_phy_cnt 64
-
-/* Register r_phy_cnt, scope eth, type r */
-typedef struct {
- unsigned int carrier_loss : 8;
- unsigned int sqe_err : 8;
- unsigned int dummy1 : 16;
-} reg_eth_r_phy_cnt;
-#define REG_RD_ADDR_eth_r_phy_cnt 68
-
-/* Register rw_test_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int snmp_inc : 1;
- unsigned int snmp : 1;
- unsigned int backoff : 1;
- unsigned int dummy1 : 29;
-} reg_eth_rw_test_ctrl;
-#define REG_RD_ADDR_eth_rw_test_ctrl 72
-#define REG_WR_ADDR_eth_rw_test_ctrl 72
-
-/* Register rw_intr_mask, scope eth, type rw */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_rw_intr_mask;
-#define REG_RD_ADDR_eth_rw_intr_mask 76
-#define REG_WR_ADDR_eth_rw_intr_mask 76
-
-/* Register rw_ack_intr, scope eth, type rw */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_rw_ack_intr;
-#define REG_RD_ADDR_eth_rw_ack_intr 80
-#define REG_WR_ADDR_eth_rw_ack_intr 80
-
-/* Register r_intr, scope eth, type r */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_r_intr;
-#define REG_RD_ADDR_eth_r_intr 84
-
-/* Register r_masked_intr, scope eth, type r */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_r_masked_intr;
-#define REG_RD_ADDR_eth_r_masked_intr 88
-
-
-/* Constants */
-enum {
- regk_eth_discard = 0x00000000,
- regk_eth_ether = 0x00000000,
- regk_eth_full = 0x00000001,
- regk_eth_gmii = 0x00000003,
- regk_eth_gtxclk = 0x00000001,
- regk_eth_half = 0x00000000,
- regk_eth_hsh = 0x00000001,
- regk_eth_mii = 0x00000001,
- regk_eth_mii_arec = 0x00000002,
- regk_eth_mii_clk = 0x00000000,
- regk_eth_no = 0x00000000,
- regk_eth_phyrst = 0x00000000,
- regk_eth_rec = 0x00000001,
- regk_eth_rw_ga_hi_default = 0x00000000,
- regk_eth_rw_ga_lo_default = 0x00000000,
- regk_eth_rw_gen_ctrl_default = 0x00000000,
- regk_eth_rw_intr_mask_default = 0x00000000,
- regk_eth_rw_ma0_hi_default = 0x00000000,
- regk_eth_rw_ma0_lo_default = 0x00000000,
- regk_eth_rw_ma1_hi_default = 0x00000000,
- regk_eth_rw_ma1_lo_default = 0x00000000,
- regk_eth_rw_mgm_ctrl_default = 0x00000000,
- regk_eth_rw_test_ctrl_default = 0x00000000,
- regk_eth_size1518 = 0x000005ee,
- regk_eth_size1522 = 0x000005f2,
- regk_eth_yes = 0x00000001
-};
-#endif /* __eth_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h b/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h
deleted file mode 100644
index 5937ed7a5228..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __extmem_defs_h
-#define __extmem_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ext_mem/mod/extmem_regs.r
- * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
- * last modfied: Tue Mar 30 22:26:21 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
- * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope extmem */
-
-/* Register rw_cse0_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_cse0_cfg;
-#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
-#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
-
-/* Register rw_cse1_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_cse1_cfg;
-#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
-#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
-
-/* Register rw_csr0_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csr0_cfg;
-#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
-#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
-
-/* Register rw_csr1_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csr1_cfg;
-#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
-#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
-
-/* Register rw_csp0_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp0_cfg;
-#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
-#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
-
-/* Register rw_csp1_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp1_cfg;
-#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
-#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
-
-/* Register rw_csp2_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp2_cfg;
-#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
-#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
-
-/* Register rw_csp3_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp3_cfg;
-#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
-#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
-
-/* Register rw_csp4_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp4_cfg;
-#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
-#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
-
-/* Register rw_csp5_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp5_cfg;
-#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
-#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
-
-/* Register rw_csp6_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp6_cfg;
-#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
-#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
-
-/* Register rw_css_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_css_cfg;
-#define REG_RD_ADDR_extmem_rw_css_cfg 44
-#define REG_WR_ADDR_extmem_rw_css_cfg 44
-
-/* Register rw_status_handle, scope extmem, type rw */
-typedef struct {
- unsigned int h : 32;
-} reg_extmem_rw_status_handle;
-#define REG_RD_ADDR_extmem_rw_status_handle 48
-#define REG_WR_ADDR_extmem_rw_status_handle 48
-
-/* Register rw_wait_pin, scope extmem, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 15;
- unsigned int start : 1;
-} reg_extmem_rw_wait_pin;
-#define REG_RD_ADDR_extmem_rw_wait_pin 52
-#define REG_WR_ADDR_extmem_rw_wait_pin 52
-
-/* Register rw_gated_csp, scope extmem, type rw */
-typedef struct {
- unsigned int dummy1 : 31;
- unsigned int en : 1;
-} reg_extmem_rw_gated_csp;
-#define REG_RD_ADDR_extmem_rw_gated_csp 56
-#define REG_WR_ADDR_extmem_rw_gated_csp 56
-
-
-/* Constants */
-enum {
- regk_extmem_b16 = 0x00000001,
- regk_extmem_b32 = 0x00000000,
- regk_extmem_bwe = 0x00000000,
- regk_extmem_cwe = 0x00000001,
- regk_extmem_no = 0x00000000,
- regk_extmem_rw_cse0_cfg_default = 0x000006cf,
- regk_extmem_rw_cse1_cfg_default = 0x000006cf,
- regk_extmem_rw_csp0_cfg_default = 0x000006cf,
- regk_extmem_rw_csp1_cfg_default = 0x000006cf,
- regk_extmem_rw_csp2_cfg_default = 0x000006cf,
- regk_extmem_rw_csp3_cfg_default = 0x000006cf,
- regk_extmem_rw_csp4_cfg_default = 0x000006cf,
- regk_extmem_rw_csp5_cfg_default = 0x000006cf,
- regk_extmem_rw_csp6_cfg_default = 0x000006cf,
- regk_extmem_rw_csr0_cfg_default = 0x000006cf,
- regk_extmem_rw_csr1_cfg_default = 0x000006cf,
- regk_extmem_rw_css_cfg_default = 0x000006cf,
- regk_extmem_s128KB = 0x00000000,
- regk_extmem_s16MB = 0x00000005,
- regk_extmem_s1MB = 0x00000001,
- regk_extmem_s2MB = 0x00000002,
- regk_extmem_s32MB = 0x00000006,
- regk_extmem_s4MB = 0x00000003,
- regk_extmem_s64MB = 0x00000007,
- regk_extmem_s8MB = 0x00000004,
- regk_extmem_yes = 0x00000001
-};
-#endif /* __extmem_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile
deleted file mode 100644
index 1b9467ae65c1..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile
+++ /dev/null
@@ -1,147 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
-# Makefile to generate or copy the latest register definitions
-# and related datastructures and helpermacros.
-# The official place for these files is probably at:
-RELEASE ?= r1_alfa5
-IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
-
-IOPROCDIR = /n/asic/design/io/io_proc/rtl
-
-IOPROCINCL_FILES =
-IOPROCINCL_FILES2=
-IOPROCINCL_FILES += iop_crc_par_defs.h
-IOPROCINCL_FILES += iop_dmc_in_defs.h
-IOPROCINCL_FILES += iop_dmc_out_defs.h
-IOPROCINCL_FILES += iop_fifo_in_defs.h
-IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
-IOPROCINCL_FILES += iop_fifo_out_defs.h
-IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
-IOPROCINCL_FILES += iop_mpu_defs.h
-IOPROCINCL_FILES2+= iop_mpu_macros.h
-IOPROCINCL_FILES2+= iop_reg_space.h
-IOPROCINCL_FILES += iop_sap_in_defs.h
-IOPROCINCL_FILES += iop_sap_out_defs.h
-IOPROCINCL_FILES += iop_scrc_in_defs.h
-IOPROCINCL_FILES += iop_scrc_out_defs.h
-IOPROCINCL_FILES += iop_spu_defs.h
-# in guiness/
-IOPROCINCL_FILES += iop_sw_cfg_defs.h
-IOPROCINCL_FILES += iop_sw_cpu_defs.h
-IOPROCINCL_FILES += iop_sw_mpu_defs.h
-IOPROCINCL_FILES += iop_sw_spu_defs.h
-#
-IOPROCINCL_FILES += iop_timer_grp_defs.h
-IOPROCINCL_FILES += iop_trigger_grp_defs.h
-# in guiness/
-IOPROCINCL_FILES += iop_version_defs.h
-
-IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
-IOPROCASMINCL_FILES+= iop_reg_space_asm.h
-
-
-IOPROCREGDESC =
-IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
-#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
-
-
-RDES2C = /n/asic/bin/rdes2c
-RDES2C = /n/asic/design/tools/rdesc/rdes2c
-RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
-RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
-
-## all - Just print help - you probably want to do 'make gen'
-all: help
-
-## help - This help
-help:
- @grep '^## ' Makefile
-
-## gen - Generate include files
-gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
- echo "INCL: $(IOPROCINCL_FILES)"
- echo "INCL2: $(IOPROCINCL_FILES2)"
- echo "ASMINCL: $(IOPROCASMINCL_FILES)"
-
-# From the official location...
-iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-
-## copy - Copy files from official location
-copy:
- @echo "## Copying and fixing iop files ##"
- @for HFILE in $(IOPROCINCL_FILES); do \
- echo " $$HFILE"; \
- cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
- @for HFILE in $(IOPROCINCL_FILES2); do \
- echo " $$HFILE"; \
- cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
- @echo "## Copying and fixing iop asm files ##"
- @for HFILE in $(IOPROCASMINCL_FILES); do \
- echo " $$HFILE"; \
- cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
- done
-
-# I/O processor files:
-## iop - Generate I/O processor include files
-iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
-iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
- $(RDES2C) $<
-iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
- $(RDES2C) $<
-%_defs.h: $(IOPROCDIR)/%.r
- $(RDES2C) $<
-%_defs_asm.h: $(IOPROCDIR)/%.r
- $(RDES2C) -asm $<
-iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
- $(RDES2C) -asm $<
-
-## doc - Generate .axw files from register description.
-doc: $(IOPROCREGDESC)
- for RDES in $^; do \
- $(RDES2TXT) $$RDES; \
- done
-
-.PHONY: axw
-## %.axw - Generate the specified .axw file (doesn't work for all files
-## due to inconsistent naming of .r files.
-%.axw: axw
- @for RDES in $(IOPROCREGDESC); do \
- if echo "$$RDES" | grep $* ; then \
- $(RDES2TXT) $$RDES; \
- fi \
- done
-
-.PHONY: clean
-## clean - Remove .h files and .axw files.
-clean:
- rm -rf $(IOPROCINCL_FILES) *.axw
-
-.PHONY: cleandoc
-## cleandoc - Remove .axw files.
-cleandoc:
- rm -rf *.axw
-
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h
deleted file mode 100644
index 10443d789a66..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_crc_par_defs_asm_h
-#define __iop_crc_par_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_crc_par.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
- * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_cfg___mode___lsb 0
-#define reg_iop_crc_par_rw_cfg___mode___width 1
-#define reg_iop_crc_par_rw_cfg___mode___bit 0
-#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
-#define reg_iop_crc_par_rw_cfg___crc_out___width 1
-#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
-#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
-#define reg_iop_crc_par_rw_cfg___rev_out___width 1
-#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
-#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
-#define reg_iop_crc_par_rw_cfg___inv_out___width 1
-#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
-#define reg_iop_crc_par_rw_cfg___trig___lsb 4
-#define reg_iop_crc_par_rw_cfg___trig___width 2
-#define reg_iop_crc_par_rw_cfg___poly___lsb 6
-#define reg_iop_crc_par_rw_cfg___poly___width 3
-#define reg_iop_crc_par_rw_cfg_offset 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_init_crc_offset 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_correct_crc_offset 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_ctrl___en___lsb 0
-#define reg_iop_crc_par_rw_ctrl___en___width 1
-#define reg_iop_crc_par_rw_ctrl___en___bit 0
-#define reg_iop_crc_par_rw_ctrl_offset 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
-#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
-#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
-#define reg_iop_crc_par_rw_set_last_offset 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_offset 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_offset 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_offset 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_offset 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_last_offset 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_last_offset 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_last_offset 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_last_offset 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_stat___err___lsb 0
-#define reg_iop_crc_par_r_stat___err___width 1
-#define reg_iop_crc_par_r_stat___err___bit 0
-#define reg_iop_crc_par_r_stat___busy___lsb 1
-#define reg_iop_crc_par_r_stat___busy___width 1
-#define reg_iop_crc_par_r_stat___busy___bit 1
-#define reg_iop_crc_par_r_stat_offset 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_sh_reg_offset 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_crc_offset 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
-#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
-
-
-/* Constants */
-#define regk_iop_crc_par_calc 0x00000001
-#define regk_iop_crc_par_ccitt 0x00000002
-#define regk_iop_crc_par_check 0x00000000
-#define regk_iop_crc_par_crc16 0x00000001
-#define regk_iop_crc_par_crc32 0x00000000
-#define regk_iop_crc_par_crc5 0x00000003
-#define regk_iop_crc_par_crc5_11 0x00000004
-#define regk_iop_crc_par_dif_in 0x00000002
-#define regk_iop_crc_par_hi 0x00000000
-#define regk_iop_crc_par_neg 0x00000002
-#define regk_iop_crc_par_no 0x00000000
-#define regk_iop_crc_par_pos 0x00000001
-#define regk_iop_crc_par_pos_neg 0x00000003
-#define regk_iop_crc_par_rw_cfg_default 0x00000000
-#define regk_iop_crc_par_rw_ctrl_default 0x00000000
-#define regk_iop_crc_par_yes 0x00000001
-#endif /* __iop_crc_par_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h
deleted file mode 100644
index fdee9bbe1fd4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_in_defs_asm_h
-#define __iop_dmc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
-#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
-#define reg_iop_dmc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
-#define reg_iop_dmc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_in_r_stat___dif_en___width 1
-#define reg_iop_dmc_in_r_stat___dif_en___bit 0
-#define reg_iop_dmc_in_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_in_rw_stream_cmd_offset 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
-#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
-#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
-#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
-#define reg_iop_dmc_in_r_stream_stat___sth___width 7
-#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
-#define reg_iop_dmc_in_r_stream_stat___full___width 1
-#define reg_iop_dmc_in_r_stream_stat___full___bit 16
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
-#define reg_iop_dmc_in_r_stream_stat_offset 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_data_descr___stat___width 8
-#define reg_iop_dmc_in_r_data_descr___md___lsb 16
-#define reg_iop_dmc_in_r_data_descr___md___width 16
-#define reg_iop_dmc_in_r_data_descr_offset 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_r_ctxt_descr_offset 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_group_descr___stat___width 8
-#define reg_iop_dmc_in_r_group_descr___md___lsb 16
-#define reg_iop_dmc_in_r_group_descr___md___width 16
-#define reg_iop_dmc_in_r_group_descr_offset 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_data_descr___md___width 16
-#define reg_iop_dmc_in_rw_data_descr_offset 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_group_descr___md___width 16
-#define reg_iop_dmc_in_rw_group_descr_offset 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
-#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
-#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
-#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
-#define reg_iop_dmc_in_rw_intr_mask___full___width 1
-#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
-#define reg_iop_dmc_in_rw_intr_mask_offset 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
-#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
-#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
-#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
-#define reg_iop_dmc_in_rw_ack_intr___full___width 1
-#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
-#define reg_iop_dmc_in_rw_ack_intr_offset 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_intr___data_md___width 1
-#define reg_iop_dmc_in_r_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_intr___group_md___width 1
-#define reg_iop_dmc_in_r_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_intr___sth___width 1
-#define reg_iop_dmc_in_r_intr___sth___bit 4
-#define reg_iop_dmc_in_r_intr___full___lsb 5
-#define reg_iop_dmc_in_r_intr___full___width 1
-#define reg_iop_dmc_in_r_intr___full___bit 5
-#define reg_iop_dmc_in_r_intr_offset 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_masked_intr___sth___width 1
-#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
-#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
-#define reg_iop_dmc_in_r_masked_intr___full___width 1
-#define reg_iop_dmc_in_r_masked_intr___full___bit 5
-#define reg_iop_dmc_in_r_masked_intr_offset 100
-
-
-/* Constants */
-#define regk_iop_dmc_in_ack_pkt 0x00000100
-#define regk_iop_dmc_in_array 0x00000008
-#define regk_iop_dmc_in_burst 0x00000020
-#define regk_iop_dmc_in_copy_next 0x00000010
-#define regk_iop_dmc_in_copy_up 0x00000020
-#define regk_iop_dmc_in_dis_c 0x00000010
-#define regk_iop_dmc_in_dis_g 0x00000020
-#define regk_iop_dmc_in_lim1 0x00000000
-#define regk_iop_dmc_in_lim16 0x00000004
-#define regk_iop_dmc_in_lim2 0x00000001
-#define regk_iop_dmc_in_lim32 0x00000005
-#define regk_iop_dmc_in_lim4 0x00000002
-#define regk_iop_dmc_in_lim64 0x00000006
-#define regk_iop_dmc_in_lim8 0x00000003
-#define regk_iop_dmc_in_load_c 0x00000200
-#define regk_iop_dmc_in_load_c_n 0x00000280
-#define regk_iop_dmc_in_load_c_next 0x00000240
-#define regk_iop_dmc_in_load_d 0x00000140
-#define regk_iop_dmc_in_load_g 0x00000300
-#define regk_iop_dmc_in_load_g_down 0x000003c0
-#define regk_iop_dmc_in_load_g_next 0x00000340
-#define regk_iop_dmc_in_load_g_up 0x00000380
-#define regk_iop_dmc_in_next_en 0x00000010
-#define regk_iop_dmc_in_next_pkt 0x00000010
-#define regk_iop_dmc_in_no 0x00000000
-#define regk_iop_dmc_in_restore 0x00000020
-#define regk_iop_dmc_in_rw_cfg_default 0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000
-#define regk_iop_dmc_in_rw_data_descr_default 0x00000000
-#define regk_iop_dmc_in_rw_group_descr_default 0x00000000
-#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000
-#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000
-#define regk_iop_dmc_in_save_down 0x00000020
-#define regk_iop_dmc_in_save_up 0x00000020
-#define regk_iop_dmc_in_set_reg 0x00000050
-#define regk_iop_dmc_in_set_w_size1 0x00000190
-#define regk_iop_dmc_in_set_w_size2 0x000001a0
-#define regk_iop_dmc_in_set_w_size4 0x000001c0
-#define regk_iop_dmc_in_store_c 0x00000002
-#define regk_iop_dmc_in_store_descr 0x00000000
-#define regk_iop_dmc_in_store_g 0x00000004
-#define regk_iop_dmc_in_store_md 0x00000001
-#define regk_iop_dmc_in_update_down 0x00000020
-#define regk_iop_dmc_in_yes 0x00000001
-#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h
deleted file mode 100644
index a97b741bd36a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_out_defs_asm_h
-#define __iop_dmc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
-#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
-#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
-#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
-#define reg_iop_dmc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_out_r_stat___dif_en___width 1
-#define reg_iop_dmc_out_r_stat___dif_en___bit 0
-#define reg_iop_dmc_out_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_out_rw_stream_cmd_offset 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-#define reg_iop_dmc_out_rs_stream_data_offset 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_data_offset 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
-#define reg_iop_dmc_out_r_stream_stat___dth___width 7
-#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
-#define reg_iop_dmc_out_r_stream_stat___dv___width 1
-#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
-#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
-#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
-#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
-#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
-#define reg_iop_dmc_out_r_stream_stat___last___width 1
-#define reg_iop_dmc_out_r_stream_stat___last___bit 18
-#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
-#define reg_iop_dmc_out_r_stream_stat___size___width 3
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
-#define reg_iop_dmc_out_r_stream_stat_offset 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_data_descr___stat___width 8
-#define reg_iop_dmc_out_r_data_descr___md___lsb 16
-#define reg_iop_dmc_out_r_data_descr___md___width 16
-#define reg_iop_dmc_out_r_data_descr_offset 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_r_ctxt_descr_offset 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_group_descr___stat___width 8
-#define reg_iop_dmc_out_r_group_descr___md___lsb 16
-#define reg_iop_dmc_out_r_group_descr___md___width 16
-#define reg_iop_dmc_out_r_group_descr_offset 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_data_descr___md___width 16
-#define reg_iop_dmc_out_rw_data_descr_offset 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_group_descr___md___width 16
-#define reg_iop_dmc_out_rw_group_descr_offset 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
-#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
-#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
-#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
-#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
-#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
-#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_intr_mask_offset 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
-#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
-#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
-#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
-#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
-#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
-#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_ack_intr_offset 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_intr___data_md___width 1
-#define reg_iop_dmc_out_r_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_intr___group_md___width 1
-#define reg_iop_dmc_out_r_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_intr___dth___width 1
-#define reg_iop_dmc_out_r_intr___dth___bit 4
-#define reg_iop_dmc_out_r_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_intr___dv___width 1
-#define reg_iop_dmc_out_r_intr___dv___bit 5
-#define reg_iop_dmc_out_r_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_intr___last_data___width 1
-#define reg_iop_dmc_out_r_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_intr_offset 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_masked_intr___dth___width 1
-#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
-#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_masked_intr___dv___width 1
-#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
-#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
-#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_masked_intr_offset 96
-
-
-/* Constants */
-#define regk_iop_dmc_out_ack_pkt 0x00000100
-#define regk_iop_dmc_out_array 0x00000008
-#define regk_iop_dmc_out_burst 0x00000020
-#define regk_iop_dmc_out_copy_next 0x00000010
-#define regk_iop_dmc_out_copy_up 0x00000020
-#define regk_iop_dmc_out_dis_c 0x00000010
-#define regk_iop_dmc_out_dis_g 0x00000020
-#define regk_iop_dmc_out_lim1 0x00000000
-#define regk_iop_dmc_out_lim16 0x00000004
-#define regk_iop_dmc_out_lim2 0x00000001
-#define regk_iop_dmc_out_lim32 0x00000005
-#define regk_iop_dmc_out_lim4 0x00000002
-#define regk_iop_dmc_out_lim64 0x00000006
-#define regk_iop_dmc_out_lim8 0x00000003
-#define regk_iop_dmc_out_load_c 0x00000200
-#define regk_iop_dmc_out_load_c_n 0x00000280
-#define regk_iop_dmc_out_load_c_next 0x00000240
-#define regk_iop_dmc_out_load_d 0x00000140
-#define regk_iop_dmc_out_load_g 0x00000300
-#define regk_iop_dmc_out_load_g_down 0x000003c0
-#define regk_iop_dmc_out_load_g_next 0x00000340
-#define regk_iop_dmc_out_load_g_up 0x00000380
-#define regk_iop_dmc_out_next_en 0x00000010
-#define regk_iop_dmc_out_next_pkt 0x00000010
-#define regk_iop_dmc_out_no 0x00000000
-#define regk_iop_dmc_out_restore 0x00000020
-#define regk_iop_dmc_out_rw_cfg_default 0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000
-#define regk_iop_dmc_out_rw_data_descr_default 0x00000000
-#define regk_iop_dmc_out_rw_group_descr_default 0x00000000
-#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000
-#define regk_iop_dmc_out_save_down 0x00000020
-#define regk_iop_dmc_out_save_up 0x00000020
-#define regk_iop_dmc_out_set_reg 0x00000050
-#define regk_iop_dmc_out_set_w_size1 0x00000190
-#define regk_iop_dmc_out_set_w_size2 0x000001a0
-#define regk_iop_dmc_out_set_w_size4 0x000001c0
-#define regk_iop_dmc_out_store_c 0x00000002
-#define regk_iop_dmc_out_store_descr 0x00000000
-#define regk_iop_dmc_out_store_g 0x00000004
-#define regk_iop_dmc_out_store_md 0x00000001
-#define regk_iop_dmc_out_update_down 0x00000020
-#define regk_iop_dmc_out_yes 0x00000001
-#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h
deleted file mode 100644
index e2c0990246f2..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_defs_asm_h
-#define __iop_fifo_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:07 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
-#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_in_rw_cfg___trig___width 2
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_in_rw_cfg___mode___width 2
-#define reg_iop_fifo_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_r_stat___last___lsb 4
-#define reg_iop_fifo_in_r_stat___last___width 8
-#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_r_stat_offset 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd1byte___data___width 8
-#define reg_iop_fifo_in_rs_rd1byte_offset 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd1byte___data___width 8
-#define reg_iop_fifo_in_r_rd1byte_offset 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd2byte___data___width 16
-#define reg_iop_fifo_in_rs_rd2byte_offset 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd2byte___data___width 16
-#define reg_iop_fifo_in_r_rd2byte_offset 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd3byte___data___width 24
-#define reg_iop_fifo_in_rs_rd3byte_offset 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd3byte___data___width 24
-#define reg_iop_fifo_in_r_rd3byte_offset 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd4byte___data___width 32
-#define reg_iop_fifo_in_rs_rd4byte_offset 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd4byte___data___width 32
-#define reg_iop_fifo_in_r_rd4byte_offset 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_set_last_offset 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_rw_intr_mask_offset 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_rw_ack_intr_offset 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_intr___urun___width 1
-#define reg_iop_fifo_in_r_intr___urun___bit 0
-#define reg_iop_fifo_in_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_intr___last_data___width 1
-#define reg_iop_fifo_in_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_intr___dav___width 1
-#define reg_iop_fifo_in_r_intr___dav___bit 2
-#define reg_iop_fifo_in_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_intr___avail___width 1
-#define reg_iop_fifo_in_r_intr___avail___bit 3
-#define reg_iop_fifo_in_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_intr___orun___width 1
-#define reg_iop_fifo_in_r_intr___orun___bit 4
-#define reg_iop_fifo_in_r_intr_offset 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_r_masked_intr_offset 64
-
-
-/* Constants */
-#define regk_iop_fifo_in_dif_in 0x00000002
-#define regk_iop_fifo_in_hi 0x00000000
-#define regk_iop_fifo_in_neg 0x00000002
-#define regk_iop_fifo_in_no 0x00000000
-#define regk_iop_fifo_in_order16 0x00000001
-#define regk_iop_fifo_in_order24 0x00000002
-#define regk_iop_fifo_in_order32 0x00000003
-#define regk_iop_fifo_in_order8 0x00000000
-#define regk_iop_fifo_in_pos 0x00000001
-#define regk_iop_fifo_in_pos_neg 0x00000003
-#define regk_iop_fifo_in_rw_cfg_default 0x00000024
-#define regk_iop_fifo_in_rw_ctrl_default 0x00000000
-#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_in_rw_set_last_default 0x00000000
-#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000
-#define regk_iop_fifo_in_size16 0x00000002
-#define regk_iop_fifo_in_size24 0x00000001
-#define regk_iop_fifo_in_size32 0x00000000
-#define regk_iop_fifo_in_size8 0x00000003
-#define regk_iop_fifo_in_yes 0x00000001
-#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
deleted file mode 100644
index 50837b989c90..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_extra_defs_asm_h
-#define __iop_fifo_in_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:08 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_in_extra_r_stat___last___width 8
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_extra_r_stat_offset 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_intr_offset 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
-
-
-/* Constants */
-#define regk_iop_fifo_in_extra_fifo_in 0x00000002
-#define regk_iop_fifo_in_extra_no 0x00000000
-#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_in_extra_yes 0x00000001
-#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h
deleted file mode 100644
index 9f06dddf33a0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_defs_asm_h
-#define __iop_fifo_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:09 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
-#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_out_rw_cfg___trig___width 2
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_out_rw_cfg___mode___width 2
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
-#define reg_iop_fifo_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_r_stat___last___lsb 4
-#define reg_iop_fifo_out_r_stat___last___width 8
-#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_r_stat_offset 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_offset 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_offset 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_offset 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_offset 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_set_last_offset 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-#define reg_iop_fifo_out_rs_rd_data_offset 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_rd_data_offset 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_rw_intr_mask_offset 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_rw_ack_intr_offset 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_intr___urun___width 1
-#define reg_iop_fifo_out_r_intr___urun___bit 0
-#define reg_iop_fifo_out_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_intr___last_data___width 1
-#define reg_iop_fifo_out_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_intr___dav___width 1
-#define reg_iop_fifo_out_r_intr___dav___bit 2
-#define reg_iop_fifo_out_r_intr___free___lsb 3
-#define reg_iop_fifo_out_r_intr___free___width 1
-#define reg_iop_fifo_out_r_intr___free___bit 3
-#define reg_iop_fifo_out_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_intr___orun___width 1
-#define reg_iop_fifo_out_r_intr___orun___bit 4
-#define reg_iop_fifo_out_r_intr_offset 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_r_masked_intr_offset 72
-
-
-/* Constants */
-#define regk_iop_fifo_out_hi 0x00000000
-#define regk_iop_fifo_out_neg 0x00000002
-#define regk_iop_fifo_out_no 0x00000000
-#define regk_iop_fifo_out_order16 0x00000001
-#define regk_iop_fifo_out_order24 0x00000002
-#define regk_iop_fifo_out_order32 0x00000003
-#define regk_iop_fifo_out_order8 0x00000000
-#define regk_iop_fifo_out_pos 0x00000001
-#define regk_iop_fifo_out_pos_neg 0x00000003
-#define regk_iop_fifo_out_rw_cfg_default 0x00000024
-#define regk_iop_fifo_out_rw_ctrl_default 0x00000000
-#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_out_rw_set_last_default 0x00000000
-#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000
-#define regk_iop_fifo_out_size16 0x00000002
-#define regk_iop_fifo_out_size24 0x00000001
-#define regk_iop_fifo_out_size32 0x00000000
-#define regk_iop_fifo_out_size8 0x00000003
-#define regk_iop_fifo_out_yes 0x00000001
-#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
deleted file mode 100644
index e8c488c389e4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_extra_defs_asm_h
-#define __iop_fifo_out_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:10 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_rd_data_offset 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_out_extra_r_stat___last___width 8
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_extra_r_stat_offset 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_intr_offset 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
-
-
-/* Constants */
-#define regk_iop_fifo_out_extra_no 0x00000000
-#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_out_extra_yes 0x00000001
-#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h
deleted file mode 100644
index 48869d445e07..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_mpu_defs_asm_h
-#define __iop_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_mpu.r
- * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
- * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_r_offset 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_ctrl___en___lsb 0
-#define reg_iop_mpu_rw_ctrl___en___width 1
-#define reg_iop_mpu_rw_ctrl___en___bit 0
-#define reg_iop_mpu_rw_ctrl_offset 128
-
-/* Register r_pc, scope iop_mpu, type r */
-#define reg_iop_mpu_r_pc___addr___lsb 0
-#define reg_iop_mpu_r_pc___addr___width 12
-#define reg_iop_mpu_r_pc_offset 132
-
-/* Register r_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
-#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
-#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
-#define reg_iop_mpu_r_stat___intr_busy___lsb 1
-#define reg_iop_mpu_r_stat___intr_busy___width 1
-#define reg_iop_mpu_r_stat___intr_busy___bit 1
-#define reg_iop_mpu_r_stat___intr_vect___lsb 2
-#define reg_iop_mpu_r_stat___intr_vect___width 16
-#define reg_iop_mpu_r_stat_offset 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_instr_offset 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_immediate_offset 144
-
-/* Register r_trace, scope iop_mpu, type r */
-#define reg_iop_mpu_r_trace___intr_vect___lsb 0
-#define reg_iop_mpu_r_trace___intr_vect___width 16
-#define reg_iop_mpu_r_trace___pc___lsb 16
-#define reg_iop_mpu_r_trace___pc___width 12
-#define reg_iop_mpu_r_trace___en___lsb 28
-#define reg_iop_mpu_r_trace___en___width 1
-#define reg_iop_mpu_r_trace___en___bit 28
-#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
-#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
-#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
-#define reg_iop_mpu_r_trace___intr_busy___lsb 30
-#define reg_iop_mpu_r_trace___intr_busy___width 1
-#define reg_iop_mpu_r_trace___intr_busy___bit 30
-#define reg_iop_mpu_r_trace_offset 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_wr_stat___r0___lsb 0
-#define reg_iop_mpu_r_wr_stat___r0___width 1
-#define reg_iop_mpu_r_wr_stat___r0___bit 0
-#define reg_iop_mpu_r_wr_stat___r1___lsb 1
-#define reg_iop_mpu_r_wr_stat___r1___width 1
-#define reg_iop_mpu_r_wr_stat___r1___bit 1
-#define reg_iop_mpu_r_wr_stat___r2___lsb 2
-#define reg_iop_mpu_r_wr_stat___r2___width 1
-#define reg_iop_mpu_r_wr_stat___r2___bit 2
-#define reg_iop_mpu_r_wr_stat___r3___lsb 3
-#define reg_iop_mpu_r_wr_stat___r3___width 1
-#define reg_iop_mpu_r_wr_stat___r3___bit 3
-#define reg_iop_mpu_r_wr_stat___r4___lsb 4
-#define reg_iop_mpu_r_wr_stat___r4___width 1
-#define reg_iop_mpu_r_wr_stat___r4___bit 4
-#define reg_iop_mpu_r_wr_stat___r5___lsb 5
-#define reg_iop_mpu_r_wr_stat___r5___width 1
-#define reg_iop_mpu_r_wr_stat___r5___bit 5
-#define reg_iop_mpu_r_wr_stat___r6___lsb 6
-#define reg_iop_mpu_r_wr_stat___r6___width 1
-#define reg_iop_mpu_r_wr_stat___r6___bit 6
-#define reg_iop_mpu_r_wr_stat___r7___lsb 7
-#define reg_iop_mpu_r_wr_stat___r7___width 1
-#define reg_iop_mpu_r_wr_stat___r7___bit 7
-#define reg_iop_mpu_r_wr_stat___r8___lsb 8
-#define reg_iop_mpu_r_wr_stat___r8___width 1
-#define reg_iop_mpu_r_wr_stat___r8___bit 8
-#define reg_iop_mpu_r_wr_stat___r9___lsb 9
-#define reg_iop_mpu_r_wr_stat___r9___width 1
-#define reg_iop_mpu_r_wr_stat___r9___bit 9
-#define reg_iop_mpu_r_wr_stat___r10___lsb 10
-#define reg_iop_mpu_r_wr_stat___r10___width 1
-#define reg_iop_mpu_r_wr_stat___r10___bit 10
-#define reg_iop_mpu_r_wr_stat___r11___lsb 11
-#define reg_iop_mpu_r_wr_stat___r11___width 1
-#define reg_iop_mpu_r_wr_stat___r11___bit 11
-#define reg_iop_mpu_r_wr_stat___r12___lsb 12
-#define reg_iop_mpu_r_wr_stat___r12___width 1
-#define reg_iop_mpu_r_wr_stat___r12___bit 12
-#define reg_iop_mpu_r_wr_stat___r13___lsb 13
-#define reg_iop_mpu_r_wr_stat___r13___width 1
-#define reg_iop_mpu_r_wr_stat___r13___bit 13
-#define reg_iop_mpu_r_wr_stat___r14___lsb 14
-#define reg_iop_mpu_r_wr_stat___r14___width 1
-#define reg_iop_mpu_r_wr_stat___r14___bit 14
-#define reg_iop_mpu_r_wr_stat___r15___lsb 15
-#define reg_iop_mpu_r_wr_stat___r15___width 1
-#define reg_iop_mpu_r_wr_stat___r15___bit 15
-#define reg_iop_mpu_r_wr_stat_offset 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_thread___addr___lsb 0
-#define reg_iop_mpu_rw_thread___addr___width 12
-#define reg_iop_mpu_rw_thread_offset 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_intr___addr___lsb 0
-#define reg_iop_mpu_rw_intr___addr___width 12
-#define reg_iop_mpu_rw_intr_offset 196
-
-
-/* Constants */
-#define regk_iop_mpu_no 0x00000000
-#define regk_iop_mpu_r_pc_default 0x00000000
-#define regk_iop_mpu_rw_ctrl_default 0x00000000
-#define regk_iop_mpu_rw_intr_size 0x00000010
-#define regk_iop_mpu_rw_r_size 0x00000010
-#define regk_iop_mpu_rw_thread_default 0x00000000
-#define regk_iop_mpu_rw_thread_size 0x00000004
-#define regk_iop_mpu_yes 0x00000001
-#endif /* __iop_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index 615f869a6de9..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define iop_version 0
-#define iop_fifo_in0_extra 64
-#define iop_fifo_in1_extra 128
-#define iop_fifo_out0_extra 192
-#define iop_fifo_out1_extra 256
-#define iop_trigger_grp0 320
-#define iop_trigger_grp1 384
-#define iop_trigger_grp2 448
-#define iop_trigger_grp3 512
-#define iop_trigger_grp4 576
-#define iop_trigger_grp5 640
-#define iop_trigger_grp6 704
-#define iop_trigger_grp7 768
-#define iop_crc_par0 896
-#define iop_crc_par1 1024
-#define iop_dmc_in0 1152
-#define iop_dmc_in1 1280
-#define iop_dmc_out0 1408
-#define iop_dmc_out1 1536
-#define iop_fifo_in0 1664
-#define iop_fifo_in1 1792
-#define iop_fifo_out0 1920
-#define iop_fifo_out1 2048
-#define iop_scrc_in0 2176
-#define iop_scrc_in1 2304
-#define iop_scrc_out0 2432
-#define iop_scrc_out1 2560
-#define iop_timer_grp0 2688
-#define iop_timer_grp1 2816
-#define iop_timer_grp2 2944
-#define iop_timer_grp3 3072
-#define iop_sap_in 3328
-#define iop_sap_out 3584
-#define iop_spu0 3840
-#define iop_spu1 4096
-#define iop_sw_cfg 4352
-#define iop_sw_cpu 4608
-#define iop_sw_mpu 4864
-#define iop_sw_spu0 5120
-#define iop_sw_spu1 5376
-#define iop_mpu 5632
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index fe8c90e015b0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
- * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus0_sync_offset 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus1_sync_offset 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 1
-#define reg_iop_sap_in_rw_gio___delay___bit 7
-#define reg_iop_sap_in_rw_gio___logic___lsb 8
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 8
-
-
-/* Constants */
-#define regk_iop_sap_in_and 0x00000002
-#define regk_iop_sap_in_ext_clk200 0x00000003
-#define regk_iop_sap_in_gio1 0x00000000
-#define regk_iop_sap_in_gio13 0x00000005
-#define regk_iop_sap_in_gio18 0x00000003
-#define regk_iop_sap_in_gio19 0x00000004
-#define regk_iop_sap_in_gio21 0x00000006
-#define regk_iop_sap_in_gio23 0x00000005
-#define regk_iop_sap_in_gio29 0x00000007
-#define regk_iop_sap_in_gio5 0x00000004
-#define regk_iop_sap_in_gio6 0x00000001
-#define regk_iop_sap_in_gio7 0x00000002
-#define regk_iop_sap_in_inv 0x00000001
-#define regk_iop_sap_in_neg 0x00000002
-#define regk_iop_sap_in_no 0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200 0x00000001
-#define regk_iop_sap_in_none 0x00000000
-#define regk_iop_sap_in_or 0x00000003
-#define regk_iop_sap_in_pos 0x00000001
-#define regk_iop_sap_in_pos_neg 0x00000003
-#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202
-#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202
-#define regk_iop_sap_in_rw_gio_default 0x00000002
-#define regk_iop_sap_in_rw_gio_size 0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006
-#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004
-#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005
-#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007
-#define regk_iop_sap_in_tmr_clk200 0x00000000
-#define regk_iop_sap_in_two_clk200 0x00000002
-#define regk_iop_sap_in_yes 0x00000001
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index a5e46f0bbf6f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
- * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus0_offset 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus1_offset 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic___width 1
-#define reg_iop_sap_out_rw_gio___out_logic___bit 10
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio_offset 28
-
-
-/* Constants */
-#define regk_iop_sap_out_and 0x00000002
-#define regk_iop_sap_out_clk0 0x00000000
-#define regk_iop_sap_out_clk1 0x00000001
-#define regk_iop_sap_out_clk12 0x00000002
-#define regk_iop_sap_out_clk2 0x00000002
-#define regk_iop_sap_out_clk200 0x00000001
-#define regk_iop_sap_out_clk3 0x00000003
-#define regk_iop_sap_out_ext 0x00000003
-#define regk_iop_sap_out_gated 0x00000004
-#define regk_iop_sap_out_gio1 0x00000000
-#define regk_iop_sap_out_gio13 0x00000002
-#define regk_iop_sap_out_gio13_clk 0x0000000c
-#define regk_iop_sap_out_gio15 0x00000001
-#define regk_iop_sap_out_gio18 0x00000003
-#define regk_iop_sap_out_gio18_clk 0x0000000d
-#define regk_iop_sap_out_gio1_clk 0x00000008
-#define regk_iop_sap_out_gio21_clk 0x0000000e
-#define regk_iop_sap_out_gio23 0x00000002
-#define regk_iop_sap_out_gio29_clk 0x0000000f
-#define regk_iop_sap_out_gio31 0x00000003
-#define regk_iop_sap_out_gio5 0x00000001
-#define regk_iop_sap_out_gio5_clk 0x00000009
-#define regk_iop_sap_out_gio6_clk 0x0000000a
-#define regk_iop_sap_out_gio7 0x00000000
-#define regk_iop_sap_out_gio7_clk 0x0000000b
-#define regk_iop_sap_out_gio_in13 0x00000001
-#define regk_iop_sap_out_gio_in21 0x00000002
-#define regk_iop_sap_out_gio_in29 0x00000003
-#define regk_iop_sap_out_gio_in5 0x00000000
-#define regk_iop_sap_out_inv 0x00000001
-#define regk_iop_sap_out_nand 0x00000003
-#define regk_iop_sap_out_no 0x00000000
-#define regk_iop_sap_out_none 0x00000000
-#define regk_iop_sap_out_rw_bus0_default 0x00000000
-#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus1_default 0x00000000
-#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
-#define regk_iop_sap_out_rw_gio_default 0x00000000
-#define regk_iop_sap_out_rw_gio_size 0x00000020
-#define regk_iop_sap_out_spu0_gio0 0x00000002
-#define regk_iop_sap_out_spu0_gio1 0x00000003
-#define regk_iop_sap_out_spu0_gio12 0x00000004
-#define regk_iop_sap_out_spu0_gio13 0x00000004
-#define regk_iop_sap_out_spu0_gio14 0x00000004
-#define regk_iop_sap_out_spu0_gio15 0x00000004
-#define regk_iop_sap_out_spu0_gio2 0x00000002
-#define regk_iop_sap_out_spu0_gio3 0x00000003
-#define regk_iop_sap_out_spu0_gio4 0x00000002
-#define regk_iop_sap_out_spu0_gio5 0x00000003
-#define regk_iop_sap_out_spu0_gio6 0x00000002
-#define regk_iop_sap_out_spu0_gio7 0x00000003
-#define regk_iop_sap_out_spu1_gio0 0x00000005
-#define regk_iop_sap_out_spu1_gio1 0x00000006
-#define regk_iop_sap_out_spu1_gio12 0x00000007
-#define regk_iop_sap_out_spu1_gio13 0x00000007
-#define regk_iop_sap_out_spu1_gio14 0x00000007
-#define regk_iop_sap_out_spu1_gio15 0x00000007
-#define regk_iop_sap_out_spu1_gio2 0x00000005
-#define regk_iop_sap_out_spu1_gio3 0x00000006
-#define regk_iop_sap_out_spu1_gio4 0x00000005
-#define regk_iop_sap_out_spu1_gio5 0x00000006
-#define regk_iop_sap_out_spu1_gio6 0x00000005
-#define regk_iop_sap_out_spu1_gio7 0x00000006
-#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004
-#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005
-#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006
-#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007
-#define regk_iop_sap_out_tmr 0x00000005
-#define regk_iop_sap_out_yes 0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h
deleted file mode 100644
index 169aaf8d44b2..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_in_defs_asm_h
-#define __iop_scrc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_in_rw_cfg___trig___width 2
-#define reg_iop_scrc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_scrc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_stat___err___lsb 0
-#define reg_iop_scrc_in_r_stat___err___width 1
-#define reg_iop_scrc_in_r_stat___err___bit 0
-#define reg_iop_scrc_in_r_stat_offset 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_init_crc_offset 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-#define reg_iop_scrc_in_rs_computed_crc_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_computed_crc_offset 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_crc_offset 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_correct_crc_offset 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
-#define reg_iop_scrc_in_rw_wr1bit___data___width 2
-#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
-#define reg_iop_scrc_in_rw_wr1bit___last___width 2
-#define reg_iop_scrc_in_rw_wr1bit_offset 32
-
-
-/* Constants */
-#define regk_iop_scrc_in_dif_in 0x00000002
-#define regk_iop_scrc_in_hi 0x00000000
-#define regk_iop_scrc_in_neg 0x00000002
-#define regk_iop_scrc_in_no 0x00000000
-#define regk_iop_scrc_in_pos 0x00000001
-#define regk_iop_scrc_in_pos_neg 0x00000003
-#define regk_iop_scrc_in_r_computed_crc_default 0x00000000
-#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000
-#define regk_iop_scrc_in_rw_cfg_default 0x00000000
-#define regk_iop_scrc_in_rw_ctrl_default 0x00000000
-#define regk_iop_scrc_in_rw_init_crc_default 0x00000000
-#define regk_iop_scrc_in_set0 0x00000000
-#define regk_iop_scrc_in_set1 0x00000001
-#define regk_iop_scrc_in_yes 0x00000001
-#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h
deleted file mode 100644
index 0e9bca149bc6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_out_defs_asm_h
-#define __iop_scrc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_out_rw_cfg___trig___width 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
-#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
-#define reg_iop_scrc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
-#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
-#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
-#define reg_iop_scrc_out_rw_ctrl_offset 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_init_crc_offset 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_crc_offset 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_data___val___lsb 0
-#define reg_iop_scrc_out_rw_data___val___width 1
-#define reg_iop_scrc_out_rw_data___val___bit 0
-#define reg_iop_scrc_out_rw_data_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-#define reg_iop_scrc_out_r_computed_crc_offset 20
-
-
-/* Constants */
-#define regk_iop_scrc_out_crc 0x00000001
-#define regk_iop_scrc_out_data 0x00000000
-#define regk_iop_scrc_out_dif 0x00000001
-#define regk_iop_scrc_out_hi 0x00000000
-#define regk_iop_scrc_out_neg 0x00000002
-#define regk_iop_scrc_out_no 0x00000000
-#define regk_iop_scrc_out_pos 0x00000001
-#define regk_iop_scrc_out_pos_neg 0x00000003
-#define regk_iop_scrc_out_reg 0x00000000
-#define regk_iop_scrc_out_rw_cfg_default 0x00000000
-#define regk_iop_scrc_out_rw_crc_default 0x00000000
-#define regk_iop_scrc_out_rw_ctrl_default 0x00000000
-#define regk_iop_scrc_out_rw_data_default 0x00000000
-#define regk_iop_scrc_out_rw_init_crc_default 0x00000000
-#define regk_iop_scrc_out_yes 0x00000001
-#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h
deleted file mode 100644
index cf2b64a9d42c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h
+++ /dev/null
@@ -1,574 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_spu_defs_asm_h
-#define __iop_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
- * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-#define reg_iop_spu_rw_r_offset 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_seq_pc___addr___lsb 0
-#define reg_iop_spu_rw_seq_pc___addr___width 12
-#define reg_iop_spu_rw_seq_pc_offset 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
-#define reg_iop_spu_rw_fsm_pc___addr___width 12
-#define reg_iop_spu_rw_fsm_pc_offset 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-#define reg_iop_spu_rw_ctrl___fsm___lsb 0
-#define reg_iop_spu_rw_ctrl___fsm___width 1
-#define reg_iop_spu_rw_ctrl___fsm___bit 0
-#define reg_iop_spu_rw_ctrl___en___lsb 1
-#define reg_iop_spu_rw_ctrl___en___width 1
-#define reg_iop_spu_rw_ctrl___en___bit 1
-#define reg_iop_spu_rw_ctrl_offset 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_offset 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus0_out_offset 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus1_out_offset 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-#define reg_iop_spu_r_gio_in_offset 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus0_in_offset 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus1_in_offset 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_set_offset 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_clr_offset 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-#define reg_iop_spu_rs_wr_stat___r0___lsb 0
-#define reg_iop_spu_rs_wr_stat___r0___width 1
-#define reg_iop_spu_rs_wr_stat___r0___bit 0
-#define reg_iop_spu_rs_wr_stat___r1___lsb 1
-#define reg_iop_spu_rs_wr_stat___r1___width 1
-#define reg_iop_spu_rs_wr_stat___r1___bit 1
-#define reg_iop_spu_rs_wr_stat___r2___lsb 2
-#define reg_iop_spu_rs_wr_stat___r2___width 1
-#define reg_iop_spu_rs_wr_stat___r2___bit 2
-#define reg_iop_spu_rs_wr_stat___r3___lsb 3
-#define reg_iop_spu_rs_wr_stat___r3___width 1
-#define reg_iop_spu_rs_wr_stat___r3___bit 3
-#define reg_iop_spu_rs_wr_stat___r4___lsb 4
-#define reg_iop_spu_rs_wr_stat___r4___width 1
-#define reg_iop_spu_rs_wr_stat___r4___bit 4
-#define reg_iop_spu_rs_wr_stat___r5___lsb 5
-#define reg_iop_spu_rs_wr_stat___r5___width 1
-#define reg_iop_spu_rs_wr_stat___r5___bit 5
-#define reg_iop_spu_rs_wr_stat___r6___lsb 6
-#define reg_iop_spu_rs_wr_stat___r6___width 1
-#define reg_iop_spu_rs_wr_stat___r6___bit 6
-#define reg_iop_spu_rs_wr_stat___r7___lsb 7
-#define reg_iop_spu_rs_wr_stat___r7___width 1
-#define reg_iop_spu_rs_wr_stat___r7___bit 7
-#define reg_iop_spu_rs_wr_stat___r8___lsb 8
-#define reg_iop_spu_rs_wr_stat___r8___width 1
-#define reg_iop_spu_rs_wr_stat___r8___bit 8
-#define reg_iop_spu_rs_wr_stat___r9___lsb 9
-#define reg_iop_spu_rs_wr_stat___r9___width 1
-#define reg_iop_spu_rs_wr_stat___r9___bit 9
-#define reg_iop_spu_rs_wr_stat___r10___lsb 10
-#define reg_iop_spu_rs_wr_stat___r10___width 1
-#define reg_iop_spu_rs_wr_stat___r10___bit 10
-#define reg_iop_spu_rs_wr_stat___r11___lsb 11
-#define reg_iop_spu_rs_wr_stat___r11___width 1
-#define reg_iop_spu_rs_wr_stat___r11___bit 11
-#define reg_iop_spu_rs_wr_stat___r12___lsb 12
-#define reg_iop_spu_rs_wr_stat___r12___width 1
-#define reg_iop_spu_rs_wr_stat___r12___bit 12
-#define reg_iop_spu_rs_wr_stat___r13___lsb 13
-#define reg_iop_spu_rs_wr_stat___r13___width 1
-#define reg_iop_spu_rs_wr_stat___r13___bit 13
-#define reg_iop_spu_rs_wr_stat___r14___lsb 14
-#define reg_iop_spu_rs_wr_stat___r14___width 1
-#define reg_iop_spu_rs_wr_stat___r14___bit 14
-#define reg_iop_spu_rs_wr_stat___r15___lsb 15
-#define reg_iop_spu_rs_wr_stat___r15___width 1
-#define reg_iop_spu_rs_wr_stat___r15___bit 15
-#define reg_iop_spu_rs_wr_stat_offset 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_wr_stat___r0___lsb 0
-#define reg_iop_spu_r_wr_stat___r0___width 1
-#define reg_iop_spu_r_wr_stat___r0___bit 0
-#define reg_iop_spu_r_wr_stat___r1___lsb 1
-#define reg_iop_spu_r_wr_stat___r1___width 1
-#define reg_iop_spu_r_wr_stat___r1___bit 1
-#define reg_iop_spu_r_wr_stat___r2___lsb 2
-#define reg_iop_spu_r_wr_stat___r2___width 1
-#define reg_iop_spu_r_wr_stat___r2___bit 2
-#define reg_iop_spu_r_wr_stat___r3___lsb 3
-#define reg_iop_spu_r_wr_stat___r3___width 1
-#define reg_iop_spu_r_wr_stat___r3___bit 3
-#define reg_iop_spu_r_wr_stat___r4___lsb 4
-#define reg_iop_spu_r_wr_stat___r4___width 1
-#define reg_iop_spu_r_wr_stat___r4___bit 4
-#define reg_iop_spu_r_wr_stat___r5___lsb 5
-#define reg_iop_spu_r_wr_stat___r5___width 1
-#define reg_iop_spu_r_wr_stat___r5___bit 5
-#define reg_iop_spu_r_wr_stat___r6___lsb 6
-#define reg_iop_spu_r_wr_stat___r6___width 1
-#define reg_iop_spu_r_wr_stat___r6___bit 6
-#define reg_iop_spu_r_wr_stat___r7___lsb 7
-#define reg_iop_spu_r_wr_stat___r7___width 1
-#define reg_iop_spu_r_wr_stat___r7___bit 7
-#define reg_iop_spu_r_wr_stat___r8___lsb 8
-#define reg_iop_spu_r_wr_stat___r8___width 1
-#define reg_iop_spu_r_wr_stat___r8___bit 8
-#define reg_iop_spu_r_wr_stat___r9___lsb 9
-#define reg_iop_spu_r_wr_stat___r9___width 1
-#define reg_iop_spu_r_wr_stat___r9___bit 9
-#define reg_iop_spu_r_wr_stat___r10___lsb 10
-#define reg_iop_spu_r_wr_stat___r10___width 1
-#define reg_iop_spu_r_wr_stat___r10___bit 10
-#define reg_iop_spu_r_wr_stat___r11___lsb 11
-#define reg_iop_spu_r_wr_stat___r11___width 1
-#define reg_iop_spu_r_wr_stat___r11___bit 11
-#define reg_iop_spu_r_wr_stat___r12___lsb 12
-#define reg_iop_spu_r_wr_stat___r12___width 1
-#define reg_iop_spu_r_wr_stat___r12___bit 12
-#define reg_iop_spu_r_wr_stat___r13___lsb 13
-#define reg_iop_spu_r_wr_stat___r13___width 1
-#define reg_iop_spu_r_wr_stat___r13___bit 13
-#define reg_iop_spu_r_wr_stat___r14___lsb 14
-#define reg_iop_spu_r_wr_stat___r14___width 1
-#define reg_iop_spu_r_wr_stat___r14___bit 14
-#define reg_iop_spu_r_wr_stat___r15___lsb 15
-#define reg_iop_spu_r_wr_stat___r15___width 1
-#define reg_iop_spu_r_wr_stat___r15___bit 15
-#define reg_iop_spu_r_wr_stat_offset 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
-#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
-#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
-#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
-#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
-#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
-#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
-#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
-#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
-#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
-#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
-#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
-#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
-#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
-#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
-#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
-#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
-#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
-#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
-#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
-#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
-#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
-#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
-#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
-#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
-#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
-#define reg_iop_spu_r_stat_in___sync_clk12___width 1
-#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
-#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
-#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
-#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
-#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
-#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
-#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
-#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
-#define reg_iop_spu_r_stat_in___mc_busy___width 1
-#define reg_iop_spu_r_stat_in___mc_busy___bit 30
-#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
-#define reg_iop_spu_r_stat_in___mc_owned___width 1
-#define reg_iop_spu_r_stat_in___mc_owned___bit 31
-#define reg_iop_spu_r_stat_in_offset 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-#define reg_iop_spu_r_trigger_in_offset 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_special_stat___c_flag___lsb 0
-#define reg_iop_spu_r_special_stat___c_flag___width 1
-#define reg_iop_spu_r_special_stat___c_flag___bit 0
-#define reg_iop_spu_r_special_stat___v_flag___lsb 1
-#define reg_iop_spu_r_special_stat___v_flag___width 1
-#define reg_iop_spu_r_special_stat___v_flag___bit 1
-#define reg_iop_spu_r_special_stat___z_flag___lsb 2
-#define reg_iop_spu_r_special_stat___z_flag___width 1
-#define reg_iop_spu_r_special_stat___z_flag___bit 2
-#define reg_iop_spu_r_special_stat___n_flag___lsb 3
-#define reg_iop_spu_r_special_stat___n_flag___width 1
-#define reg_iop_spu_r_special_stat___n_flag___bit 3
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
-#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
-#define reg_iop_spu_r_special_stat___fsm_in0___width 1
-#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
-#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
-#define reg_iop_spu_r_special_stat___fsm_in1___width 1
-#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
-#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
-#define reg_iop_spu_r_special_stat___fsm_in2___width 1
-#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
-#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
-#define reg_iop_spu_r_special_stat___fsm_in3___width 1
-#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
-#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
-#define reg_iop_spu_r_special_stat___fsm_in4___width 1
-#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
-#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
-#define reg_iop_spu_r_special_stat___fsm_in5___width 1
-#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
-#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
-#define reg_iop_spu_r_special_stat___fsm_in6___width 1
-#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
-#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
-#define reg_iop_spu_r_special_stat___fsm_in7___width 1
-#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
-#define reg_iop_spu_r_special_stat___event0___lsb 16
-#define reg_iop_spu_r_special_stat___event0___width 1
-#define reg_iop_spu_r_special_stat___event0___bit 16
-#define reg_iop_spu_r_special_stat___event1___lsb 17
-#define reg_iop_spu_r_special_stat___event1___width 1
-#define reg_iop_spu_r_special_stat___event1___bit 17
-#define reg_iop_spu_r_special_stat___event2___lsb 18
-#define reg_iop_spu_r_special_stat___event2___width 1
-#define reg_iop_spu_r_special_stat___event2___bit 18
-#define reg_iop_spu_r_special_stat___event3___lsb 19
-#define reg_iop_spu_r_special_stat___event3___width 1
-#define reg_iop_spu_r_special_stat___event3___bit 19
-#define reg_iop_spu_r_special_stat_offset 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-#define reg_iop_spu_rw_reg_access___addr___lsb 0
-#define reg_iop_spu_rw_reg_access___addr___width 13
-#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
-#define reg_iop_spu_rw_reg_access___imm_hi___width 16
-#define reg_iop_spu_rw_reg_access_offset 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_cfg___addr___lsb 0
-#define reg_iop_spu_rw_event_cfg___addr___width 12
-#define reg_iop_spu_rw_event_cfg___src___lsb 12
-#define reg_iop_spu_rw_event_cfg___src___width 2
-#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
-#define reg_iop_spu_rw_event_cfg___eq_en___width 1
-#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
-#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
-#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
-#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
-#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
-#define reg_iop_spu_rw_event_cfg___gt_en___width 1
-#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
-#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
-#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
-#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
-#define reg_iop_spu_rw_event_cfg_offset 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_mask_offset 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_val_offset 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_ret___addr___lsb 0
-#define reg_iop_spu_rw_event_ret___addr___width 12
-#define reg_iop_spu_rw_event_ret_offset 192
-
-/* Register r_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_trace___fsm___lsb 0
-#define reg_iop_spu_r_trace___fsm___width 1
-#define reg_iop_spu_r_trace___fsm___bit 0
-#define reg_iop_spu_r_trace___en___lsb 1
-#define reg_iop_spu_r_trace___en___width 1
-#define reg_iop_spu_r_trace___en___bit 1
-#define reg_iop_spu_r_trace___c_flag___lsb 2
-#define reg_iop_spu_r_trace___c_flag___width 1
-#define reg_iop_spu_r_trace___c_flag___bit 2
-#define reg_iop_spu_r_trace___v_flag___lsb 3
-#define reg_iop_spu_r_trace___v_flag___width 1
-#define reg_iop_spu_r_trace___v_flag___bit 3
-#define reg_iop_spu_r_trace___z_flag___lsb 4
-#define reg_iop_spu_r_trace___z_flag___width 1
-#define reg_iop_spu_r_trace___z_flag___bit 4
-#define reg_iop_spu_r_trace___n_flag___lsb 5
-#define reg_iop_spu_r_trace___n_flag___width 1
-#define reg_iop_spu_r_trace___n_flag___bit 5
-#define reg_iop_spu_r_trace___seq_addr___lsb 6
-#define reg_iop_spu_r_trace___seq_addr___width 12
-#define reg_iop_spu_r_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_trace___fsm_addr___width 12
-#define reg_iop_spu_r_trace_offset 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
-#define reg_iop_spu_r_fsm_trace___fsm___width 1
-#define reg_iop_spu_r_fsm_trace___fsm___bit 0
-#define reg_iop_spu_r_fsm_trace___en___lsb 1
-#define reg_iop_spu_r_fsm_trace___en___width 1
-#define reg_iop_spu_r_fsm_trace___en___bit 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
-#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
-#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
-#define reg_iop_spu_r_fsm_trace___inp0___width 1
-#define reg_iop_spu_r_fsm_trace___inp0___bit 3
-#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
-#define reg_iop_spu_r_fsm_trace___inp1___width 1
-#define reg_iop_spu_r_fsm_trace___inp1___bit 4
-#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
-#define reg_iop_spu_r_fsm_trace___inp2___width 1
-#define reg_iop_spu_r_fsm_trace___inp2___bit 5
-#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
-#define reg_iop_spu_r_fsm_trace___inp3___width 1
-#define reg_iop_spu_r_fsm_trace___inp3___bit 6
-#define reg_iop_spu_r_fsm_trace___event0___lsb 7
-#define reg_iop_spu_r_fsm_trace___event0___width 1
-#define reg_iop_spu_r_fsm_trace___event0___bit 7
-#define reg_iop_spu_r_fsm_trace___event1___lsb 8
-#define reg_iop_spu_r_fsm_trace___event1___width 1
-#define reg_iop_spu_r_fsm_trace___event1___bit 8
-#define reg_iop_spu_r_fsm_trace___event2___lsb 9
-#define reg_iop_spu_r_fsm_trace___event2___width 1
-#define reg_iop_spu_r_fsm_trace___event2___bit 9
-#define reg_iop_spu_r_fsm_trace___event3___lsb 10
-#define reg_iop_spu_r_fsm_trace___event3___width 1
-#define reg_iop_spu_r_fsm_trace___event3___bit 10
-#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
-#define reg_iop_spu_r_fsm_trace___gio_out___width 8
-#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
-#define reg_iop_spu_r_fsm_trace_offset 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-#define reg_iop_spu_rw_brp___addr___lsb 0
-#define reg_iop_spu_rw_brp___addr___width 12
-#define reg_iop_spu_rw_brp___fsm___lsb 12
-#define reg_iop_spu_rw_brp___fsm___width 1
-#define reg_iop_spu_rw_brp___fsm___bit 12
-#define reg_iop_spu_rw_brp___en___lsb 13
-#define reg_iop_spu_rw_brp___en___width 1
-#define reg_iop_spu_rw_brp___en___bit 13
-#define reg_iop_spu_rw_brp_offset 204
-
-
-/* Constants */
-#define regk_iop_spu_attn_hi 0x00000005
-#define regk_iop_spu_attn_lo 0x00000005
-#define regk_iop_spu_attn_r0 0x00000000
-#define regk_iop_spu_attn_r1 0x00000001
-#define regk_iop_spu_attn_r10 0x00000002
-#define regk_iop_spu_attn_r11 0x00000003
-#define regk_iop_spu_attn_r12 0x00000004
-#define regk_iop_spu_attn_r13 0x00000005
-#define regk_iop_spu_attn_r14 0x00000006
-#define regk_iop_spu_attn_r15 0x00000007
-#define regk_iop_spu_attn_r2 0x00000002
-#define regk_iop_spu_attn_r3 0x00000003
-#define regk_iop_spu_attn_r4 0x00000004
-#define regk_iop_spu_attn_r5 0x00000005
-#define regk_iop_spu_attn_r6 0x00000006
-#define regk_iop_spu_attn_r7 0x00000007
-#define regk_iop_spu_attn_r8 0x00000000
-#define regk_iop_spu_attn_r9 0x00000001
-#define regk_iop_spu_c 0x00000000
-#define regk_iop_spu_flag 0x00000002
-#define regk_iop_spu_gio_in 0x00000000
-#define regk_iop_spu_gio_out 0x00000005
-#define regk_iop_spu_gio_out0 0x00000008
-#define regk_iop_spu_gio_out1 0x00000009
-#define regk_iop_spu_gio_out2 0x0000000a
-#define regk_iop_spu_gio_out3 0x0000000b
-#define regk_iop_spu_gio_out4 0x0000000c
-#define regk_iop_spu_gio_out5 0x0000000d
-#define regk_iop_spu_gio_out6 0x0000000e
-#define regk_iop_spu_gio_out7 0x0000000f
-#define regk_iop_spu_n 0x00000003
-#define regk_iop_spu_no 0x00000000
-#define regk_iop_spu_r0 0x00000008
-#define regk_iop_spu_r1 0x00000009
-#define regk_iop_spu_r10 0x0000000a
-#define regk_iop_spu_r11 0x0000000b
-#define regk_iop_spu_r12 0x0000000c
-#define regk_iop_spu_r13 0x0000000d
-#define regk_iop_spu_r14 0x0000000e
-#define regk_iop_spu_r15 0x0000000f
-#define regk_iop_spu_r2 0x0000000a
-#define regk_iop_spu_r3 0x0000000b
-#define regk_iop_spu_r4 0x0000000c
-#define regk_iop_spu_r5 0x0000000d
-#define regk_iop_spu_r6 0x0000000e
-#define regk_iop_spu_r7 0x0000000f
-#define regk_iop_spu_r8 0x00000008
-#define regk_iop_spu_r9 0x00000009
-#define regk_iop_spu_reg_hi 0x00000002
-#define regk_iop_spu_reg_lo 0x00000002
-#define regk_iop_spu_rw_brp_default 0x00000000
-#define regk_iop_spu_rw_brp_size 0x00000004
-#define regk_iop_spu_rw_ctrl_default 0x00000000
-#define regk_iop_spu_rw_event_cfg_size 0x00000004
-#define regk_iop_spu_rw_event_mask_size 0x00000004
-#define regk_iop_spu_rw_event_val_size 0x00000004
-#define regk_iop_spu_rw_gio_out_default 0x00000000
-#define regk_iop_spu_rw_r_size 0x00000010
-#define regk_iop_spu_rw_reg_access_default 0x00000000
-#define regk_iop_spu_stat_in 0x00000002
-#define regk_iop_spu_statin_hi 0x00000004
-#define regk_iop_spu_statin_lo 0x00000004
-#define regk_iop_spu_trig 0x00000003
-#define regk_iop_spu_trigger 0x00000006
-#define regk_iop_spu_v 0x00000001
-#define regk_iop_spu_wsts_gioout_spec 0x00000001
-#define regk_iop_spu_xor 0x00000003
-#define regk_iop_spu_xor_bus0_r2_0 0x00000000
-#define regk_iop_spu_xor_bus0m_r2_0 0x00000002
-#define regk_iop_spu_xor_bus1_r3_0 0x00000001
-#define regk_iop_spu_xor_bus1m_r3_0 0x00000003
-#define regk_iop_spu_yes 0x00000001
-#define regk_iop_spu_z 0x00000002
-#endif /* __iop_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index 4f4c7340d39a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,1053 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a 0x00000001
-#define regk_iop_sw_cfg_b 0x00000002
-#define regk_iop_sw_cfg_bus0 0x00000000
-#define regk_iop_sw_cfg_bus0_rot16 0x00000004
-#define regk_iop_sw_cfg_bus0_rot24 0x00000006
-#define regk_iop_sw_cfg_bus0_rot8 0x00000002
-#define regk_iop_sw_cfg_bus1 0x00000001
-#define regk_iop_sw_cfg_bus1_rot16 0x00000005
-#define regk_iop_sw_cfg_bus1_rot24 0x00000007
-#define regk_iop_sw_cfg_bus1_rot8 0x00000003
-#define regk_iop_sw_cfg_clk12 0x00000000
-#define regk_iop_sw_cfg_cpu 0x00000000
-#define regk_iop_sw_cfg_dmc0 0x00000000
-#define regk_iop_sw_cfg_dmc1 0x00000001
-#define regk_iop_sw_cfg_gated_clk0 0x00000010
-#define regk_iop_sw_cfg_gated_clk1 0x00000011
-#define regk_iop_sw_cfg_gated_clk2 0x00000012
-#define regk_iop_sw_cfg_gated_clk3 0x00000013
-#define regk_iop_sw_cfg_gio0 0x00000004
-#define regk_iop_sw_cfg_gio1 0x00000001
-#define regk_iop_sw_cfg_gio2 0x00000005
-#define regk_iop_sw_cfg_gio3 0x00000002
-#define regk_iop_sw_cfg_gio4 0x00000006
-#define regk_iop_sw_cfg_gio5 0x00000003
-#define regk_iop_sw_cfg_gio6 0x00000007
-#define regk_iop_sw_cfg_gio7 0x00000004
-#define regk_iop_sw_cfg_gio_in0 0x00000000
-#define regk_iop_sw_cfg_gio_in1 0x00000001
-#define regk_iop_sw_cfg_gio_in10 0x00000002
-#define regk_iop_sw_cfg_gio_in11 0x00000003
-#define regk_iop_sw_cfg_gio_in14 0x00000004
-#define regk_iop_sw_cfg_gio_in15 0x00000005
-#define regk_iop_sw_cfg_gio_in18 0x00000002
-#define regk_iop_sw_cfg_gio_in19 0x00000003
-#define regk_iop_sw_cfg_gio_in20 0x00000004
-#define regk_iop_sw_cfg_gio_in21 0x00000005
-#define regk_iop_sw_cfg_gio_in26 0x00000006
-#define regk_iop_sw_cfg_gio_in27 0x00000007
-#define regk_iop_sw_cfg_gio_in28 0x00000006
-#define regk_iop_sw_cfg_gio_in29 0x00000007
-#define regk_iop_sw_cfg_gio_in4 0x00000000
-#define regk_iop_sw_cfg_gio_in5 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002
-#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003
-#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002
-#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003
-#define regk_iop_sw_cfg_mpu 0x00000001
-#define regk_iop_sw_cfg_none 0x00000000
-#define regk_iop_sw_cfg_par0 0x00000000
-#define regk_iop_sw_cfg_par1 0x00000001
-#define regk_iop_sw_cfg_pdp_out0 0x00000002
-#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001
-#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005
-#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000
-#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004
-#define regk_iop_sw_cfg_pdp_out1 0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005
-#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002
-#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004
-#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
-#define regk_iop_sw_cfg_sdp_out0 0x00000008
-#define regk_iop_sw_cfg_sdp_out1 0x00000009
-#define regk_iop_sw_cfg_size16 0x00000002
-#define regk_iop_sw_cfg_size24 0x00000003
-#define regk_iop_sw_cfg_size32 0x00000004
-#define regk_iop_sw_cfg_size8 0x00000001
-#define regk_iop_sw_cfg_spu0 0x00000002
-#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007
-#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007
-#define regk_iop_sw_cfg_spu0_g0 0x0000000e
-#define regk_iop_sw_cfg_spu0_g1 0x0000000e
-#define regk_iop_sw_cfg_spu0_g2 0x0000000e
-#define regk_iop_sw_cfg_spu0_g3 0x0000000e
-#define regk_iop_sw_cfg_spu0_g4 0x0000000e
-#define regk_iop_sw_cfg_spu0_g5 0x0000000e
-#define regk_iop_sw_cfg_spu0_g6 0x0000000e
-#define regk_iop_sw_cfg_spu0_g7 0x0000000e
-#define regk_iop_sw_cfg_spu0_gio0 0x00000000
-#define regk_iop_sw_cfg_spu0_gio1 0x00000001
-#define regk_iop_sw_cfg_spu0_gio2 0x00000000
-#define regk_iop_sw_cfg_spu0_gio5 0x00000005
-#define regk_iop_sw_cfg_spu0_gio6 0x00000006
-#define regk_iop_sw_cfg_spu0_gio7 0x00000007
-#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008
-#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009
-#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a
-#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b
-#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c
-#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d
-#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e
-#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f
-#define regk_iop_sw_cfg_spu0_gioout0 0x00000000
-#define regk_iop_sw_cfg_spu0_gioout1 0x00000000
-#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout2 0x00000002
-#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout3 0x00000002
-#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout4 0x00000004
-#define regk_iop_sw_cfg_spu0_gioout5 0x00000004
-#define regk_iop_sw_cfg_spu0_gioout6 0x00000006
-#define regk_iop_sw_cfg_spu0_gioout7 0x00000006
-#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e
-#define regk_iop_sw_cfg_spu1 0x00000003
-#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007
-#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007
-#define regk_iop_sw_cfg_spu1_g0 0x0000000f
-#define regk_iop_sw_cfg_spu1_g1 0x0000000f
-#define regk_iop_sw_cfg_spu1_g2 0x0000000f
-#define regk_iop_sw_cfg_spu1_g3 0x0000000f
-#define regk_iop_sw_cfg_spu1_g4 0x0000000f
-#define regk_iop_sw_cfg_spu1_g5 0x0000000f
-#define regk_iop_sw_cfg_spu1_g6 0x0000000f
-#define regk_iop_sw_cfg_spu1_g7 0x0000000f
-#define regk_iop_sw_cfg_spu1_gio0 0x00000002
-#define regk_iop_sw_cfg_spu1_gio1 0x00000003
-#define regk_iop_sw_cfg_spu1_gio2 0x00000002
-#define regk_iop_sw_cfg_spu1_gio5 0x00000005
-#define regk_iop_sw_cfg_spu1_gio6 0x00000006
-#define regk_iop_sw_cfg_spu1_gio7 0x00000007
-#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008
-#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009
-#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a
-#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b
-#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c
-#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d
-#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e
-#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout0 0x00000001
-#define regk_iop_sw_cfg_spu1_gioout1 0x00000001
-#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout2 0x00000003
-#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout3 0x00000003
-#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout4 0x00000005
-#define regk_iop_sw_cfg_spu1_gioout5 0x00000005
-#define regk_iop_sw_cfg_spu1_gioout6 0x00000007
-#define regk_iop_sw_cfg_spu1_gioout7 0x00000007
-#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002
-#define regk_iop_sw_cfg_timer_grp0 0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004
-#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004
-#define regk_iop_sw_cfg_timer_grp1 0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005
-#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005
-#define regk_iop_sw_cfg_timer_grp2 0x00000000
-#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006
-#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006
-#define regk_iop_sw_cfg_timer_grp3 0x00000000
-#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007
-#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007
-#define regk_iop_sw_cfg_trig0_0 0x00000000
-#define regk_iop_sw_cfg_trig0_1 0x00000000
-#define regk_iop_sw_cfg_trig0_2 0x00000000
-#define regk_iop_sw_cfg_trig0_3 0x00000000
-#define regk_iop_sw_cfg_trig1_0 0x00000000
-#define regk_iop_sw_cfg_trig1_1 0x00000000
-#define regk_iop_sw_cfg_trig1_2 0x00000000
-#define regk_iop_sw_cfg_trig1_3 0x00000000
-#define regk_iop_sw_cfg_trig2_0 0x00000000
-#define regk_iop_sw_cfg_trig2_1 0x00000000
-#define regk_iop_sw_cfg_trig2_2 0x00000000
-#define regk_iop_sw_cfg_trig2_3 0x00000000
-#define regk_iop_sw_cfg_trig3_0 0x00000000
-#define regk_iop_sw_cfg_trig3_1 0x00000000
-#define regk_iop_sw_cfg_trig3_2 0x00000000
-#define regk_iop_sw_cfg_trig3_3 0x00000000
-#define regk_iop_sw_cfg_trig4_0 0x00000001
-#define regk_iop_sw_cfg_trig4_1 0x00000001
-#define regk_iop_sw_cfg_trig4_2 0x00000001
-#define regk_iop_sw_cfg_trig4_3 0x00000001
-#define regk_iop_sw_cfg_trig5_0 0x00000001
-#define regk_iop_sw_cfg_trig5_1 0x00000001
-#define regk_iop_sw_cfg_trig5_2 0x00000001
-#define regk_iop_sw_cfg_trig5_3 0x00000001
-#define regk_iop_sw_cfg_trig6_0 0x00000001
-#define regk_iop_sw_cfg_trig6_1 0x00000001
-#define regk_iop_sw_cfg_trig6_2 0x00000001
-#define regk_iop_sw_cfg_trig6_3 0x00000001
-#define regk_iop_sw_cfg_trig7_0 0x00000001
-#define regk_iop_sw_cfg_trig7_1 0x00000001
-#define regk_iop_sw_cfg_trig7_2 0x00000001
-#define regk_iop_sw_cfg_trig7_3 0x00000001
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index ef04a57a0680..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,1759 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_cpu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr2_offset 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr2_offset 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
-#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_intr3_offset 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_masked_intr3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy 0x00000000
-#define regk_iop_sw_cpu_no 0x00000000
-#define regk_iop_sw_cpu_rd 0x00000002
-#define regk_iop_sw_cpu_reg_copy 0x00000001
-#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000
-#define regk_iop_sw_cpu_wr 0x00000003
-#define regk_iop_sw_cpu_yes 0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index 22292069e4fd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1777 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_mpu_r_mc_stat_offset 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus0_in_offset 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus1_in_offset 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp0_offset 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp1_offset 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp2_offset 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp3_offset 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy 0x00000000
-#define regk_iop_sw_mpu_cpu 0x00000000
-#define regk_iop_sw_mpu_mpu 0x00000001
-#define regk_iop_sw_mpu_no 0x00000000
-#define regk_iop_sw_mpu_nop 0x00000000
-#define regk_iop_sw_mpu_rd 0x00000002
-#define regk_iop_sw_mpu_reg_copy 0x00000001
-#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
-#define regk_iop_sw_mpu_set 0x00000001
-#define regk_iop_sw_mpu_spu0 0x00000002
-#define regk_iop_sw_mpu_spu1 0x00000003
-#define regk_iop_sw_mpu_wr 0x00000003
-#define regk_iop_sw_mpu_yes 0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 82729218621c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_spu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
-#define reg_iop_sw_spu_r_hw_intr_offset 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
-#define reg_iop_sw_spu_r_mpu_intr_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy 0x00000000
-#define regk_iop_sw_spu_no 0x00000000
-#define regk_iop_sw_spu_nop 0x00000000
-#define regk_iop_sw_spu_rd 0x00000002
-#define regk_iop_sw_spu_reg_copy 0x00000001
-#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_spu_set 0x00000001
-#define regk_iop_sw_spu_wr 0x00000003
-#define regk_iop_sw_spu_yes 0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h
deleted file mode 100644
index 4f1cf73d86cd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_timer_grp_defs_asm_h
-#define __iop_timer_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
-#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
-#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
-#define reg_iop_timer_grp_rw_cfg___trig___width 2
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
-#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
-#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
-#define reg_iop_timer_grp_rw_cfg_offset 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
-#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
-#define reg_iop_timer_grp_rw_half_period_offset 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period_len_offset 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
-#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
-#define reg_iop_timer_grp_rw_tmr_len___val___width 16
-#define reg_iop_timer_grp_rw_tmr_len_offset 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
-#define reg_iop_timer_grp_rw_cmd___rst___width 4
-#define reg_iop_timer_grp_rw_cmd___en___lsb 4
-#define reg_iop_timer_grp_rw_cmd___en___width 4
-#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
-#define reg_iop_timer_grp_rw_cmd___dis___width 4
-#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
-#define reg_iop_timer_grp_rw_cmd___strb___width 4
-#define reg_iop_timer_grp_rw_cmd_offset 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_r_tmr_cnt_offset 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
-#define reg_iop_timer_grp_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
-#define reg_iop_timer_grp_rw_ack_intr_offset 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_intr_offset 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_iop_timer_grp_clk200 0x00000000
-#define regk_iop_timer_grp_clk_gen 0x00000002
-#define regk_iop_timer_grp_complete 0x00000002
-#define regk_iop_timer_grp_div_clk200 0x00000001
-#define regk_iop_timer_grp_div_clk_gen 0x00000003
-#define regk_iop_timer_grp_ext 0x00000001
-#define regk_iop_timer_grp_hi 0x00000000
-#define regk_iop_timer_grp_long_period 0x00000001
-#define regk_iop_timer_grp_neg 0x00000002
-#define regk_iop_timer_grp_no 0x00000000
-#define regk_iop_timer_grp_once 0x00000003
-#define regk_iop_timer_grp_pause 0x00000001
-#define regk_iop_timer_grp_pos 0x00000001
-#define regk_iop_timer_grp_pos_neg 0x00000003
-#define regk_iop_timer_grp_pulse 0x00000000
-#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004
-#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004
-#define regk_iop_timer_grp_rw_cfg_default 0x00000002
-#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000
-#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000
-#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900
-#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200
-#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00
-#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004
-#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000
-#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004
-#define regk_iop_timer_grp_short_period 0x00000000
-#define regk_iop_timer_grp_stop 0x00000000
-#define regk_iop_timer_grp_tmr 0x00000004
-#define regk_iop_timer_grp_toggle 0x00000001
-#define regk_iop_timer_grp_yes 0x00000001
-#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
deleted file mode 100644
index 7bc882c62952..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_trigger_grp_defs_asm_h
-#define __iop_trigger_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
-#define reg_iop_trigger_grp_rw_cfg___action___width 2
-#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
-#define reg_iop_trigger_grp_rw_cfg___once___width 1
-#define reg_iop_trigger_grp_rw_cfg___once___bit 2
-#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
-#define reg_iop_trigger_grp_rw_cfg___trig___width 3
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
-#define reg_iop_trigger_grp_rw_cfg_offset 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
-#define reg_iop_trigger_grp_rw_cmd___dis___width 4
-#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
-#define reg_iop_trigger_grp_rw_cmd___en___width 4
-#define reg_iop_trigger_grp_rw_cmd_offset 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
-#define reg_iop_trigger_grp_rw_intr_mask_offset 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
-#define reg_iop_trigger_grp_rw_ack_intr_offset 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_intr_offset 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_masked_intr_offset 32
-
-
-/* Constants */
-#define regk_iop_trigger_grp_fall 0x00000002
-#define regk_iop_trigger_grp_fall_lo 0x00000006
-#define regk_iop_trigger_grp_no 0x00000000
-#define regk_iop_trigger_grp_off 0x00000000
-#define regk_iop_trigger_grp_pulse 0x00000000
-#define regk_iop_trigger_grp_rise 0x00000001
-#define regk_iop_trigger_grp_rise_fall 0x00000003
-#define regk_iop_trigger_grp_rise_fall_hi 0x00000007
-#define regk_iop_trigger_grp_rise_fall_lo 0x00000004
-#define regk_iop_trigger_grp_rise_hi 0x00000005
-#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0
-#define regk_iop_trigger_grp_rw_cfg_size 0x00000004
-#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000
-#define regk_iop_trigger_grp_toggle 0x00000003
-#define regk_iop_trigger_grp_yes 0x00000001
-#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index 2e239957e34a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- * last modfied: Mon Apr 11 16:08:44 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v1_0 0x00000001
-#endif /* __iop_version_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h
deleted file mode 100644
index 8690034d9bec..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_crc_par_defs_h
-#define __iop_crc_par_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_crc_par.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
- * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_crc_par */
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int mode : 1;
- unsigned int crc_out : 1;
- unsigned int rev_out : 1;
- unsigned int inv_out : 1;
- unsigned int trig : 2;
- unsigned int poly : 3;
- unsigned int dummy1 : 23;
-} reg_iop_crc_par_rw_cfg;
-#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
-#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-typedef unsigned int reg_iop_crc_par_rw_init_crc;
-#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
-#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-typedef unsigned int reg_iop_crc_par_rw_correct_crc;
-#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
-#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_crc_par_rw_ctrl;
-#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
-#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int tr_dif : 1;
- unsigned int dummy1 : 31;
-} reg_iop_crc_par_rw_set_last;
-#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
-#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_crc_par_rw_wr1byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
-#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_crc_par_rw_wr2byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
-#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_crc_par_rw_wr3byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
-#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_crc_par_rw_wr4byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
-#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_crc_par_rw_wr1byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
-#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_crc_par_rw_wr2byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
-#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_crc_par_rw_wr3byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
-#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_crc_par_rw_wr4byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
-#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-typedef struct {
- unsigned int err : 1;
- unsigned int busy : 1;
- unsigned int dummy1 : 30;
-} reg_iop_crc_par_r_stat;
-#define REG_RD_ADDR_iop_crc_par_r_stat 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-typedef unsigned int reg_iop_crc_par_r_sh_reg;
-#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-typedef unsigned int reg_iop_crc_par_r_crc;
-#define REG_RD_ADDR_iop_crc_par_r_crc 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int last : 2;
- unsigned int dummy1 : 30;
-} reg_iop_crc_par_rw_strb_rec_dif_in;
-#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
-#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
-
-
-/* Constants */
-enum {
- regk_iop_crc_par_calc = 0x00000001,
- regk_iop_crc_par_ccitt = 0x00000002,
- regk_iop_crc_par_check = 0x00000000,
- regk_iop_crc_par_crc16 = 0x00000001,
- regk_iop_crc_par_crc32 = 0x00000000,
- regk_iop_crc_par_crc5 = 0x00000003,
- regk_iop_crc_par_crc5_11 = 0x00000004,
- regk_iop_crc_par_dif_in = 0x00000002,
- regk_iop_crc_par_hi = 0x00000000,
- regk_iop_crc_par_neg = 0x00000002,
- regk_iop_crc_par_no = 0x00000000,
- regk_iop_crc_par_pos = 0x00000001,
- regk_iop_crc_par_pos_neg = 0x00000003,
- regk_iop_crc_par_rw_cfg_default = 0x00000000,
- regk_iop_crc_par_rw_ctrl_default = 0x00000000,
- regk_iop_crc_par_yes = 0x00000001
-};
-#endif /* __iop_crc_par_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h
deleted file mode 100644
index 3dd4e870a3a5..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_in_defs_h
-#define __iop_dmc_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_dmc_in */
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int sth_intr : 3;
- unsigned int last_dis_dif : 1;
- unsigned int dummy1 : 28;
-} reg_iop_dmc_in_rw_cfg;
-#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
-#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dif_dis : 1;
- unsigned int stream_clr : 1;
- unsigned int dummy1 : 29;
-} reg_iop_dmc_in_rw_ctrl;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_dmc_in_r_stat;
-#define REG_RD_ADDR_iop_dmc_in_r_stat 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int cmd : 10;
- unsigned int dummy1 : 6;
- unsigned int n : 8;
- unsigned int dummy2 : 8;
-} reg_iop_dmc_in_rw_stream_cmd;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int eop : 1;
- unsigned int wait : 1;
- unsigned int keep_md : 1;
- unsigned int size : 3;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_rw_stream_ctrl;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int sth : 7;
- unsigned int dummy1 : 9;
- unsigned int full : 1;
- unsigned int last_pkt : 1;
- unsigned int data_md_valid : 1;
- unsigned int ctxt_md_valid : 1;
- unsigned int group_md_valid : 1;
- unsigned int stream_busy : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dummy2 : 9;
-} reg_iop_dmc_in_r_stream_stat;
-#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_in_r_data_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md0 : 16;
-} reg_iop_dmc_in_r_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_in_r_group_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_in_rw_data_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
-#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md0 : 16;
-} reg_iop_dmc_in_rw_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_in_rw_group_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
-#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_rw_intr_mask;
-#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
-#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_rw_ack_intr;
-#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
-#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_r_intr;
-#define REG_RD_ADDR_iop_dmc_in_r_intr 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_r_masked_intr;
-#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
-
-
-/* Constants */
-enum {
- regk_iop_dmc_in_ack_pkt = 0x00000100,
- regk_iop_dmc_in_array = 0x00000008,
- regk_iop_dmc_in_burst = 0x00000020,
- regk_iop_dmc_in_copy_next = 0x00000010,
- regk_iop_dmc_in_copy_up = 0x00000020,
- regk_iop_dmc_in_dis_c = 0x00000010,
- regk_iop_dmc_in_dis_g = 0x00000020,
- regk_iop_dmc_in_lim1 = 0x00000000,
- regk_iop_dmc_in_lim16 = 0x00000004,
- regk_iop_dmc_in_lim2 = 0x00000001,
- regk_iop_dmc_in_lim32 = 0x00000005,
- regk_iop_dmc_in_lim4 = 0x00000002,
- regk_iop_dmc_in_lim64 = 0x00000006,
- regk_iop_dmc_in_lim8 = 0x00000003,
- regk_iop_dmc_in_load_c = 0x00000200,
- regk_iop_dmc_in_load_c_n = 0x00000280,
- regk_iop_dmc_in_load_c_next = 0x00000240,
- regk_iop_dmc_in_load_d = 0x00000140,
- regk_iop_dmc_in_load_g = 0x00000300,
- regk_iop_dmc_in_load_g_down = 0x000003c0,
- regk_iop_dmc_in_load_g_next = 0x00000340,
- regk_iop_dmc_in_load_g_up = 0x00000380,
- regk_iop_dmc_in_next_en = 0x00000010,
- regk_iop_dmc_in_next_pkt = 0x00000010,
- regk_iop_dmc_in_no = 0x00000000,
- regk_iop_dmc_in_restore = 0x00000020,
- regk_iop_dmc_in_rw_cfg_default = 0x00000000,
- regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000,
- regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
- regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
- regk_iop_dmc_in_rw_data_descr_default = 0x00000000,
- regk_iop_dmc_in_rw_group_descr_default = 0x00000000,
- regk_iop_dmc_in_rw_intr_mask_default = 0x00000000,
- regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000,
- regk_iop_dmc_in_save_down = 0x00000020,
- regk_iop_dmc_in_save_up = 0x00000020,
- regk_iop_dmc_in_set_reg = 0x00000050,
- regk_iop_dmc_in_set_w_size1 = 0x00000190,
- regk_iop_dmc_in_set_w_size2 = 0x000001a0,
- regk_iop_dmc_in_set_w_size4 = 0x000001c0,
- regk_iop_dmc_in_store_c = 0x00000002,
- regk_iop_dmc_in_store_descr = 0x00000000,
- regk_iop_dmc_in_store_g = 0x00000004,
- regk_iop_dmc_in_store_md = 0x00000001,
- regk_iop_dmc_in_update_down = 0x00000020,
- regk_iop_dmc_in_yes = 0x00000001
-};
-#endif /* __iop_dmc_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h
deleted file mode 100644
index 7ed17bc553c3..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_out_defs_h
-#define __iop_dmc_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_dmc_out */
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int trf_lim : 16;
- unsigned int last_at_trf_lim : 1;
- unsigned int dth_intr : 3;
- unsigned int dummy1 : 12;
-} reg_iop_dmc_out_rw_cfg;
-#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
-#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dif_dis : 1;
- unsigned int dummy1 : 30;
-} reg_iop_dmc_out_rw_ctrl;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_dmc_out_r_stat;
-#define REG_RD_ADDR_iop_dmc_out_r_stat 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int cmd : 10;
- unsigned int dummy1 : 6;
- unsigned int n : 8;
- unsigned int dummy2 : 8;
-} reg_iop_dmc_out_rw_stream_cmd;
-#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
-#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-typedef unsigned int reg_iop_dmc_out_rs_stream_data;
-#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_stream_data;
-#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int dth : 7;
- unsigned int dummy1 : 9;
- unsigned int dv : 1;
- unsigned int all_avail : 1;
- unsigned int last : 1;
- unsigned int size : 3;
- unsigned int data_md_valid : 1;
- unsigned int ctxt_md_valid : 1;
- unsigned int group_md_valid : 1;
- unsigned int stream_busy : 1;
- unsigned int cmd_rdy : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy2 : 4;
-} reg_iop_dmc_out_r_stream_stat;
-#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_out_r_data_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md0 : 16;
-} reg_iop_dmc_out_r_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_out_r_group_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_out_rw_data_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
-#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md0 : 16;
-} reg_iop_dmc_out_rw_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_out_rw_group_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
-#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_rw_intr_mask;
-#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
-#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_rw_ack_intr;
-#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
-#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_r_intr;
-#define REG_RD_ADDR_iop_dmc_out_r_intr 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_r_masked_intr;
-#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
-
-
-/* Constants */
-enum {
- regk_iop_dmc_out_ack_pkt = 0x00000100,
- regk_iop_dmc_out_array = 0x00000008,
- regk_iop_dmc_out_burst = 0x00000020,
- regk_iop_dmc_out_copy_next = 0x00000010,
- regk_iop_dmc_out_copy_up = 0x00000020,
- regk_iop_dmc_out_dis_c = 0x00000010,
- regk_iop_dmc_out_dis_g = 0x00000020,
- regk_iop_dmc_out_lim1 = 0x00000000,
- regk_iop_dmc_out_lim16 = 0x00000004,
- regk_iop_dmc_out_lim2 = 0x00000001,
- regk_iop_dmc_out_lim32 = 0x00000005,
- regk_iop_dmc_out_lim4 = 0x00000002,
- regk_iop_dmc_out_lim64 = 0x00000006,
- regk_iop_dmc_out_lim8 = 0x00000003,
- regk_iop_dmc_out_load_c = 0x00000200,
- regk_iop_dmc_out_load_c_n = 0x00000280,
- regk_iop_dmc_out_load_c_next = 0x00000240,
- regk_iop_dmc_out_load_d = 0x00000140,
- regk_iop_dmc_out_load_g = 0x00000300,
- regk_iop_dmc_out_load_g_down = 0x000003c0,
- regk_iop_dmc_out_load_g_next = 0x00000340,
- regk_iop_dmc_out_load_g_up = 0x00000380,
- regk_iop_dmc_out_next_en = 0x00000010,
- regk_iop_dmc_out_next_pkt = 0x00000010,
- regk_iop_dmc_out_no = 0x00000000,
- regk_iop_dmc_out_restore = 0x00000020,
- regk_iop_dmc_out_rw_cfg_default = 0x00000000,
- regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000,
- regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
- regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
- regk_iop_dmc_out_rw_data_descr_default = 0x00000000,
- regk_iop_dmc_out_rw_group_descr_default = 0x00000000,
- regk_iop_dmc_out_rw_intr_mask_default = 0x00000000,
- regk_iop_dmc_out_save_down = 0x00000020,
- regk_iop_dmc_out_save_up = 0x00000020,
- regk_iop_dmc_out_set_reg = 0x00000050,
- regk_iop_dmc_out_set_w_size1 = 0x00000190,
- regk_iop_dmc_out_set_w_size2 = 0x000001a0,
- regk_iop_dmc_out_set_w_size4 = 0x000001c0,
- regk_iop_dmc_out_store_c = 0x00000002,
- regk_iop_dmc_out_store_descr = 0x00000000,
- regk_iop_dmc_out_store_g = 0x00000004,
- regk_iop_dmc_out_store_md = 0x00000001,
- regk_iop_dmc_out_update_down = 0x00000020,
- regk_iop_dmc_out_yes = 0x00000001
-};
-#endif /* __iop_dmc_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h
deleted file mode 100644
index dc14868680e6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_defs_h
-#define __iop_fifo_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:07 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_in */
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int avail_lim : 3;
- unsigned int byte_order : 2;
- unsigned int trig : 2;
- unsigned int last_dis_dif_in : 1;
- unsigned int mode : 2;
- unsigned int dummy1 : 22;
-} reg_iop_fifo_in_rw_cfg;
-#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
-#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_in_rw_ctrl;
-#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 18;
-} reg_iop_fifo_in_r_stat;
-#define REG_RD_ADDR_iop_fifo_in_r_stat 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_in_rs_rd1byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_in_r_rd1byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_in_rs_rd2byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_in_r_rd2byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_in_rs_rd3byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_in_r_rd3byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_in_rs_rd4byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_in_r_rd4byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-typedef unsigned int reg_iop_fifo_in_rw_set_last;
-#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
-#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int last : 2;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_in_rw_strb_dif_in;
-#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
-#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
-#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
-#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_r_intr;
-#define REG_RD_ADDR_iop_fifo_in_r_intr 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
-
-
-/* Constants */
-enum {
- regk_iop_fifo_in_dif_in = 0x00000002,
- regk_iop_fifo_in_hi = 0x00000000,
- regk_iop_fifo_in_neg = 0x00000002,
- regk_iop_fifo_in_no = 0x00000000,
- regk_iop_fifo_in_order16 = 0x00000001,
- regk_iop_fifo_in_order24 = 0x00000002,
- regk_iop_fifo_in_order32 = 0x00000003,
- regk_iop_fifo_in_order8 = 0x00000000,
- regk_iop_fifo_in_pos = 0x00000001,
- regk_iop_fifo_in_pos_neg = 0x00000003,
- regk_iop_fifo_in_rw_cfg_default = 0x00000024,
- regk_iop_fifo_in_rw_ctrl_default = 0x00000000,
- regk_iop_fifo_in_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_in_rw_set_last_default = 0x00000000,
- regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000,
- regk_iop_fifo_in_size16 = 0x00000002,
- regk_iop_fifo_in_size24 = 0x00000001,
- regk_iop_fifo_in_size32 = 0x00000000,
- regk_iop_fifo_in_size8 = 0x00000003,
- regk_iop_fifo_in_yes = 0x00000001
-};
-#endif /* __iop_fifo_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h
deleted file mode 100644
index ee7dc07a7862..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_extra_defs_h
-#define __iop_fifo_in_extra_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:08 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_in_extra */
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 18;
-} reg_iop_fifo_in_extra_r_stat;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-typedef struct {
- unsigned int last : 2;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_in_extra_rw_strb_dif_in;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_r_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
-
-
-/* Constants */
-enum {
- regk_iop_fifo_in_extra_fifo_in = 0x00000002,
- regk_iop_fifo_in_extra_no = 0x00000000,
- regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_in_extra_yes = 0x00000001
-};
-#endif /* __iop_fifo_in_extra_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h
deleted file mode 100644
index ee8194fcfa82..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_defs_h
-#define __iop_fifo_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:09 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_out */
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int free_lim : 3;
- unsigned int byte_order : 2;
- unsigned int trig : 2;
- unsigned int last_dis_dif_in : 1;
- unsigned int mode : 2;
- unsigned int delay_out_last : 1;
- unsigned int last_dis_dif_out : 1;
- unsigned int dummy1 : 20;
-} reg_iop_fifo_out_rw_cfg;
-#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
-#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_out_rw_ctrl;
-#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int zero_data_last : 1;
- unsigned int dummy1 : 17;
-} reg_iop_fifo_out_r_stat;
-#define REG_RD_ADDR_iop_fifo_out_r_stat 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_out_rw_wr1byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
-#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_out_rw_wr2byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
-#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_out_rw_wr3byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
-#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_out_rw_wr4byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
-#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_out_rw_wr1byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
-#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_out_rw_wr2byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
-#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_out_rw_wr3byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
-#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_out_rw_wr4byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
-#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-typedef unsigned int reg_iop_fifo_out_rw_set_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
-#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-typedef unsigned int reg_iop_fifo_out_rs_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-typedef unsigned int reg_iop_fifo_out_r_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
-#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
-#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
-#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
-#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_r_intr;
-#define REG_RD_ADDR_iop_fifo_out_r_intr 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
-
-
-/* Constants */
-enum {
- regk_iop_fifo_out_hi = 0x00000000,
- regk_iop_fifo_out_neg = 0x00000002,
- regk_iop_fifo_out_no = 0x00000000,
- regk_iop_fifo_out_order16 = 0x00000001,
- regk_iop_fifo_out_order24 = 0x00000002,
- regk_iop_fifo_out_order32 = 0x00000003,
- regk_iop_fifo_out_order8 = 0x00000000,
- regk_iop_fifo_out_pos = 0x00000001,
- regk_iop_fifo_out_pos_neg = 0x00000003,
- regk_iop_fifo_out_rw_cfg_default = 0x00000024,
- regk_iop_fifo_out_rw_ctrl_default = 0x00000000,
- regk_iop_fifo_out_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_out_rw_set_last_default = 0x00000000,
- regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
- regk_iop_fifo_out_rw_wr1byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
- regk_iop_fifo_out_rw_wr2byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
- regk_iop_fifo_out_rw_wr3byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
- regk_iop_fifo_out_rw_wr4byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
- regk_iop_fifo_out_size16 = 0x00000002,
- regk_iop_fifo_out_size24 = 0x00000001,
- regk_iop_fifo_out_size32 = 0x00000000,
- regk_iop_fifo_out_size8 = 0x00000003,
- regk_iop_fifo_out_yes = 0x00000001
-};
-#endif /* __iop_fifo_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h
deleted file mode 100644
index b9721649f6fd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_extra_defs_h
-#define __iop_fifo_out_extra_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:10 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_out_extra */
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int zero_data_last : 1;
- unsigned int dummy1 : 17;
-} reg_iop_fifo_out_extra_r_stat;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_r_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
-
-
-/* Constants */
-enum {
- regk_iop_fifo_out_extra_no = 0x00000000,
- regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_out_extra_yes = 0x00000001
-};
-#endif /* __iop_fifo_out_extra_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h
deleted file mode 100644
index 28e1c5903677..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_mpu_defs_h
-#define __iop_mpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_mpu.r
- * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
- * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_mpu */
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_r;
-#define REG_RD_ADDR_iop_mpu_rw_r 0
-#define REG_WR_ADDR_iop_mpu_rw_r 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_mpu_rw_ctrl;
-#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
-#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
-
-/* Register r_pc, scope iop_mpu, type r */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_mpu_r_pc;
-#define REG_RD_ADDR_iop_mpu_r_pc 132
-
-/* Register r_stat, scope iop_mpu, type r */
-typedef struct {
- unsigned int instr_reg_busy : 1;
- unsigned int intr_busy : 1;
- unsigned int intr_vect : 16;
- unsigned int dummy1 : 14;
-} reg_iop_mpu_r_stat;
-#define REG_RD_ADDR_iop_mpu_r_stat 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_instr;
-#define REG_RD_ADDR_iop_mpu_rw_instr 140
-#define REG_WR_ADDR_iop_mpu_rw_instr 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_immediate;
-#define REG_RD_ADDR_iop_mpu_rw_immediate 144
-#define REG_WR_ADDR_iop_mpu_rw_immediate 144
-
-/* Register r_trace, scope iop_mpu, type r */
-typedef struct {
- unsigned int intr_vect : 16;
- unsigned int pc : 12;
- unsigned int en : 1;
- unsigned int instr_reg_busy : 1;
- unsigned int intr_busy : 1;
- unsigned int dummy1 : 1;
-} reg_iop_mpu_r_trace;
-#define REG_RD_ADDR_iop_mpu_r_trace 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-typedef struct {
- unsigned int r0 : 1;
- unsigned int r1 : 1;
- unsigned int r2 : 1;
- unsigned int r3 : 1;
- unsigned int r4 : 1;
- unsigned int r5 : 1;
- unsigned int r6 : 1;
- unsigned int r7 : 1;
- unsigned int r8 : 1;
- unsigned int r9 : 1;
- unsigned int r10 : 1;
- unsigned int r11 : 1;
- unsigned int r12 : 1;
- unsigned int r13 : 1;
- unsigned int r14 : 1;
- unsigned int r15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_mpu_r_wr_stat;
-#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_mpu_rw_thread;
-#define REG_RD_ADDR_iop_mpu_rw_thread 156
-#define REG_WR_ADDR_iop_mpu_rw_thread 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_mpu_rw_intr;
-#define REG_RD_ADDR_iop_mpu_rw_intr 196
-#define REG_WR_ADDR_iop_mpu_rw_intr 196
-
-
-/* Constants */
-enum {
- regk_iop_mpu_no = 0x00000000,
- regk_iop_mpu_r_pc_default = 0x00000000,
- regk_iop_mpu_rw_ctrl_default = 0x00000000,
- regk_iop_mpu_rw_intr_size = 0x00000010,
- regk_iop_mpu_rw_r_size = 0x00000010,
- regk_iop_mpu_rw_thread_default = 0x00000000,
- regk_iop_mpu_rw_thread_size = 0x00000004,
- regk_iop_mpu_yes = 0x00000001
-};
-#endif /* __iop_mpu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h
deleted file mode 100644
index 41f5178a65b8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h
+++ /dev/null
@@ -1,765 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ************************************************************************* */
-/* This file is autogenerated by IOPASM Version 1.2 */
-/* DO NOT EDIT THIS FILE - All changes will be lost! */
-/* ************************************************************************* */
-
-
-
-#ifndef __IOP_MPU_MACROS_H__
-#define __IOP_MPU_MACROS_H__
-
-
-/* ************************************************************************* */
-/* REGISTER DEFINITIONS */
-/* ************************************************************************* */
-#define MPU_R0 (0x0)
-#define MPU_R1 (0x1)
-#define MPU_R2 (0x2)
-#define MPU_R3 (0x3)
-#define MPU_R4 (0x4)
-#define MPU_R5 (0x5)
-#define MPU_R6 (0x6)
-#define MPU_R7 (0x7)
-#define MPU_R8 (0x8)
-#define MPU_R9 (0x9)
-#define MPU_R10 (0xa)
-#define MPU_R11 (0xb)
-#define MPU_R12 (0xc)
-#define MPU_R13 (0xd)
-#define MPU_R14 (0xe)
-#define MPU_R15 (0xf)
-#define MPU_PC (0x2)
-#define MPU_WSTS (0x3)
-#define MPU_JADDR (0x4)
-#define MPU_IRP (0x5)
-#define MPU_SRP (0x6)
-#define MPU_T0 (0x8)
-#define MPU_T1 (0x9)
-#define MPU_T2 (0xa)
-#define MPU_T3 (0xb)
-#define MPU_I0 (0x10)
-#define MPU_I1 (0x11)
-#define MPU_I2 (0x12)
-#define MPU_I3 (0x13)
-#define MPU_I4 (0x14)
-#define MPU_I5 (0x15)
-#define MPU_I6 (0x16)
-#define MPU_I7 (0x17)
-#define MPU_I8 (0x18)
-#define MPU_I9 (0x19)
-#define MPU_I10 (0x1a)
-#define MPU_I11 (0x1b)
-#define MPU_I12 (0x1c)
-#define MPU_I13 (0x1d)
-#define MPU_I14 (0x1e)
-#define MPU_I15 (0x1f)
-#define MPU_P2 (0x2)
-#define MPU_P3 (0x3)
-#define MPU_P5 (0x5)
-#define MPU_P6 (0x6)
-#define MPU_P8 (0x8)
-#define MPU_P9 (0x9)
-#define MPU_P10 (0xa)
-#define MPU_P11 (0xb)
-#define MPU_P16 (0x10)
-#define MPU_P17 (0x12)
-#define MPU_P18 (0x12)
-#define MPU_P19 (0x13)
-#define MPU_P20 (0x14)
-#define MPU_P21 (0x15)
-#define MPU_P22 (0x16)
-#define MPU_P23 (0x17)
-#define MPU_P24 (0x18)
-#define MPU_P25 (0x19)
-#define MPU_P26 (0x1a)
-#define MPU_P27 (0x1b)
-#define MPU_P28 (0x1c)
-#define MPU_P29 (0x1d)
-#define MPU_P30 (0x1e)
-#define MPU_P31 (0x1f)
-#define MPU_P1 (0x1)
-#define MPU_REGA (0x1)
-
-
-
-/* ************************************************************************* */
-/* ADDRESS MACROS */
-/* ************************************************************************* */
-#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
-#define MK_BYTE_ADDR(ADDR) (ADDR)
-
-
-
-/* ************************************************************************* */
-/* INSTRUCTION MACROS */
-/* ************************************************************************* */
-#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 21)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 21)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_DI() (0x40000001)
-
-#define MPU_EI() (0x40000003)
-
-#define MPU_HALT() (0x40000002)
-
-#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JNT() (0x61000000)
-
-#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_NOP() (0x40000000)
-
-#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_RET() (0x63003000)
-
-#define MPU_RETI() (0x63602800)
-
-#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
- | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-
-#endif /* end of __IOP_MPU_MACROS_H__ */
-/* End of iop_mpu_macros.h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h
deleted file mode 100644
index 95e9ce8c042a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define regi_iop_version (regi_iop + 0)
-#define regi_iop_fifo_in0_extra (regi_iop + 64)
-#define regi_iop_fifo_in1_extra (regi_iop + 128)
-#define regi_iop_fifo_out0_extra (regi_iop + 192)
-#define regi_iop_fifo_out1_extra (regi_iop + 256)
-#define regi_iop_trigger_grp0 (regi_iop + 320)
-#define regi_iop_trigger_grp1 (regi_iop + 384)
-#define regi_iop_trigger_grp2 (regi_iop + 448)
-#define regi_iop_trigger_grp3 (regi_iop + 512)
-#define regi_iop_trigger_grp4 (regi_iop + 576)
-#define regi_iop_trigger_grp5 (regi_iop + 640)
-#define regi_iop_trigger_grp6 (regi_iop + 704)
-#define regi_iop_trigger_grp7 (regi_iop + 768)
-#define regi_iop_crc_par0 (regi_iop + 896)
-#define regi_iop_crc_par1 (regi_iop + 1024)
-#define regi_iop_dmc_in0 (regi_iop + 1152)
-#define regi_iop_dmc_in1 (regi_iop + 1280)
-#define regi_iop_dmc_out0 (regi_iop + 1408)
-#define regi_iop_dmc_out1 (regi_iop + 1536)
-#define regi_iop_fifo_in0 (regi_iop + 1664)
-#define regi_iop_fifo_in1 (regi_iop + 1792)
-#define regi_iop_fifo_out0 (regi_iop + 1920)
-#define regi_iop_fifo_out1 (regi_iop + 2048)
-#define regi_iop_scrc_in0 (regi_iop + 2176)
-#define regi_iop_scrc_in1 (regi_iop + 2304)
-#define regi_iop_scrc_out0 (regi_iop + 2432)
-#define regi_iop_scrc_out1 (regi_iop + 2560)
-#define regi_iop_timer_grp0 (regi_iop + 2688)
-#define regi_iop_timer_grp1 (regi_iop + 2816)
-#define regi_iop_timer_grp2 (regi_iop + 2944)
-#define regi_iop_timer_grp3 (regi_iop + 3072)
-#define regi_iop_sap_in (regi_iop + 3328)
-#define regi_iop_sap_out (regi_iop + 3584)
-#define regi_iop_spu0 (regi_iop + 3840)
-#define regi_iop_spu1 (regi_iop + 4096)
-#define regi_iop_sw_cfg (regi_iop + 4352)
-#define regi_iop_sw_cpu (regi_iop + 4608)
-#define regi_iop_sw_mpu (regi_iop + 4864)
-#define regi_iop_sw_spu0 (regi_iop + 5120)
-#define regi_iop_sw_spu1 (regi_iop + 5376)
-#define regi_iop_mpu (regi_iop + 5632)
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h
deleted file mode 100644
index 22a74eafb8b0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_h
-#define __iop_sap_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
- * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_in */
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int byte0_sel : 2;
- unsigned int byte0_ext_src : 3;
- unsigned int byte0_edge : 2;
- unsigned int byte0_delay : 1;
- unsigned int byte1_sel : 2;
- unsigned int byte1_ext_src : 3;
- unsigned int byte1_edge : 2;
- unsigned int byte1_delay : 1;
- unsigned int byte2_sel : 2;
- unsigned int byte2_ext_src : 3;
- unsigned int byte2_edge : 2;
- unsigned int byte2_delay : 1;
- unsigned int byte3_sel : 2;
- unsigned int byte3_ext_src : 3;
- unsigned int byte3_edge : 2;
- unsigned int byte3_delay : 1;
-} reg_iop_sap_in_rw_bus0_sync;
-#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
-#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int byte0_sel : 2;
- unsigned int byte0_ext_src : 3;
- unsigned int byte0_edge : 2;
- unsigned int byte0_delay : 1;
- unsigned int byte1_sel : 2;
- unsigned int byte1_ext_src : 3;
- unsigned int byte1_edge : 2;
- unsigned int byte1_delay : 1;
- unsigned int byte2_sel : 2;
- unsigned int byte2_ext_src : 3;
- unsigned int byte2_edge : 2;
- unsigned int byte2_delay : 1;
- unsigned int byte3_sel : 2;
- unsigned int byte3_ext_src : 3;
- unsigned int byte3_edge : 2;
- unsigned int byte3_delay : 1;
-} reg_iop_sap_in_rw_bus1_sync;
-#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
-#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int sync_sel : 2;
- unsigned int sync_ext_src : 3;
- unsigned int sync_edge : 2;
- unsigned int delay : 1;
- unsigned int logic : 2;
- unsigned int dummy1 : 22;
-} reg_iop_sap_in_rw_gio;
-#define REG_RD_ADDR_iop_sap_in_rw_gio 8
-#define REG_WR_ADDR_iop_sap_in_rw_gio 8
-
-
-/* Constants */
-enum {
- regk_iop_sap_in_and = 0x00000002,
- regk_iop_sap_in_ext_clk200 = 0x00000003,
- regk_iop_sap_in_gio1 = 0x00000000,
- regk_iop_sap_in_gio13 = 0x00000005,
- regk_iop_sap_in_gio18 = 0x00000003,
- regk_iop_sap_in_gio19 = 0x00000004,
- regk_iop_sap_in_gio21 = 0x00000006,
- regk_iop_sap_in_gio23 = 0x00000005,
- regk_iop_sap_in_gio29 = 0x00000007,
- regk_iop_sap_in_gio5 = 0x00000004,
- regk_iop_sap_in_gio6 = 0x00000001,
- regk_iop_sap_in_gio7 = 0x00000002,
- regk_iop_sap_in_inv = 0x00000001,
- regk_iop_sap_in_neg = 0x00000002,
- regk_iop_sap_in_no = 0x00000000,
- regk_iop_sap_in_no_del_ext_clk200 = 0x00000001,
- regk_iop_sap_in_none = 0x00000000,
- regk_iop_sap_in_or = 0x00000003,
- regk_iop_sap_in_pos = 0x00000001,
- regk_iop_sap_in_pos_neg = 0x00000003,
- regk_iop_sap_in_rw_bus0_sync_default = 0x02020202,
- regk_iop_sap_in_rw_bus1_sync_default = 0x02020202,
- regk_iop_sap_in_rw_gio_default = 0x00000002,
- regk_iop_sap_in_rw_gio_size = 0x00000020,
- regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006,
- regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004,
- regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005,
- regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007,
- regk_iop_sap_in_tmr_clk200 = 0x00000000,
- regk_iop_sap_in_two_clk200 = 0x00000002,
- regk_iop_sap_in_yes = 0x00000001
-};
-#endif /* __iop_sap_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h
deleted file mode 100644
index 380133910105..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_h
-#define __iop_sap_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
- * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_out */
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int clk0_src : 2;
- unsigned int clk0_gate_src : 2;
- unsigned int clk0_force_src : 3;
- unsigned int clk1_src : 2;
- unsigned int clk1_gate_src : 2;
- unsigned int clk1_force_src : 3;
- unsigned int clk2_src : 2;
- unsigned int clk2_gate_src : 2;
- unsigned int clk2_force_src : 3;
- unsigned int clk3_src : 2;
- unsigned int clk3_gate_src : 2;
- unsigned int clk3_force_src : 3;
- unsigned int dummy1 : 4;
-} reg_iop_sap_out_rw_gen_gated;
-#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
-#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int dummy1 : 8;
-} reg_iop_sap_out_rw_bus0;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
-#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int dummy1 : 8;
-} reg_iop_sap_out_rw_bus1;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
-#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_clk_ext : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_logic : 2;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_clk_ext : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus0_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
-#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_clk_ext : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_logic : 2;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_clk_ext : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus0_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
-#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_clk_ext : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_logic : 2;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_clk_ext : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus1_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
-#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_clk_ext : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_logic : 2;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_clk_ext : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus1_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
-#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int out_clk_sel : 3;
- unsigned int out_clk_ext : 4;
- unsigned int out_gated_clk : 2;
- unsigned int out_clk_inv : 1;
- unsigned int out_logic : 1;
- unsigned int oe_clk_sel : 3;
- unsigned int oe_clk_ext : 3;
- unsigned int oe_gated_clk : 2;
- unsigned int oe_clk_inv : 1;
- unsigned int oe_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_gio;
-#define REG_RD_ADDR_iop_sap_out_rw_gio 28
-#define REG_WR_ADDR_iop_sap_out_rw_gio 28
-
-
-/* Constants */
-enum {
- regk_iop_sap_out_and = 0x00000002,
- regk_iop_sap_out_clk0 = 0x00000000,
- regk_iop_sap_out_clk1 = 0x00000001,
- regk_iop_sap_out_clk12 = 0x00000002,
- regk_iop_sap_out_clk2 = 0x00000002,
- regk_iop_sap_out_clk200 = 0x00000001,
- regk_iop_sap_out_clk3 = 0x00000003,
- regk_iop_sap_out_ext = 0x00000003,
- regk_iop_sap_out_gated = 0x00000004,
- regk_iop_sap_out_gio1 = 0x00000000,
- regk_iop_sap_out_gio13 = 0x00000002,
- regk_iop_sap_out_gio13_clk = 0x0000000c,
- regk_iop_sap_out_gio15 = 0x00000001,
- regk_iop_sap_out_gio18 = 0x00000003,
- regk_iop_sap_out_gio18_clk = 0x0000000d,
- regk_iop_sap_out_gio1_clk = 0x00000008,
- regk_iop_sap_out_gio21_clk = 0x0000000e,
- regk_iop_sap_out_gio23 = 0x00000002,
- regk_iop_sap_out_gio29_clk = 0x0000000f,
- regk_iop_sap_out_gio31 = 0x00000003,
- regk_iop_sap_out_gio5 = 0x00000001,
- regk_iop_sap_out_gio5_clk = 0x00000009,
- regk_iop_sap_out_gio6_clk = 0x0000000a,
- regk_iop_sap_out_gio7 = 0x00000000,
- regk_iop_sap_out_gio7_clk = 0x0000000b,
- regk_iop_sap_out_gio_in13 = 0x00000001,
- regk_iop_sap_out_gio_in21 = 0x00000002,
- regk_iop_sap_out_gio_in29 = 0x00000003,
- regk_iop_sap_out_gio_in5 = 0x00000000,
- regk_iop_sap_out_inv = 0x00000001,
- regk_iop_sap_out_nand = 0x00000003,
- regk_iop_sap_out_no = 0x00000000,
- regk_iop_sap_out_none = 0x00000000,
- regk_iop_sap_out_rw_bus0_default = 0x00000000,
- regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus1_default = 0x00000000,
- regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000,
- regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
- regk_iop_sap_out_rw_gio_default = 0x00000000,
- regk_iop_sap_out_rw_gio_size = 0x00000020,
- regk_iop_sap_out_spu0_gio0 = 0x00000002,
- regk_iop_sap_out_spu0_gio1 = 0x00000003,
- regk_iop_sap_out_spu0_gio12 = 0x00000004,
- regk_iop_sap_out_spu0_gio13 = 0x00000004,
- regk_iop_sap_out_spu0_gio14 = 0x00000004,
- regk_iop_sap_out_spu0_gio15 = 0x00000004,
- regk_iop_sap_out_spu0_gio2 = 0x00000002,
- regk_iop_sap_out_spu0_gio3 = 0x00000003,
- regk_iop_sap_out_spu0_gio4 = 0x00000002,
- regk_iop_sap_out_spu0_gio5 = 0x00000003,
- regk_iop_sap_out_spu0_gio6 = 0x00000002,
- regk_iop_sap_out_spu0_gio7 = 0x00000003,
- regk_iop_sap_out_spu1_gio0 = 0x00000005,
- regk_iop_sap_out_spu1_gio1 = 0x00000006,
- regk_iop_sap_out_spu1_gio12 = 0x00000007,
- regk_iop_sap_out_spu1_gio13 = 0x00000007,
- regk_iop_sap_out_spu1_gio14 = 0x00000007,
- regk_iop_sap_out_spu1_gio15 = 0x00000007,
- regk_iop_sap_out_spu1_gio2 = 0x00000005,
- regk_iop_sap_out_spu1_gio3 = 0x00000006,
- regk_iop_sap_out_spu1_gio4 = 0x00000005,
- regk_iop_sap_out_spu1_gio5 = 0x00000006,
- regk_iop_sap_out_spu1_gio6 = 0x00000005,
- regk_iop_sap_out_spu1_gio7 = 0x00000006,
- regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004,
- regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005,
- regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006,
- regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007,
- regk_iop_sap_out_tmr = 0x00000005,
- regk_iop_sap_out_yes = 0x00000001
-};
-#endif /* __iop_sap_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h
deleted file mode 100644
index 65d662046ca9..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_in_defs_h
-#define __iop_scrc_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_scrc_in */
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-typedef struct {
- unsigned int trig : 2;
- unsigned int dummy1 : 30;
-} reg_iop_scrc_in_rw_cfg;
-#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
-#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-typedef struct {
- unsigned int dif_in_en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_scrc_in_rw_ctrl;
-#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-typedef struct {
- unsigned int err : 1;
- unsigned int dummy1 : 31;
-} reg_iop_scrc_in_r_stat;
-#define REG_RD_ADDR_iop_scrc_in_r_stat 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_init_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
-#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
-#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-typedef unsigned int reg_iop_scrc_in_r_computed_crc;
-#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
-#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
-#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-typedef struct {
- unsigned int data : 2;
- unsigned int last : 2;
- unsigned int dummy1 : 28;
-} reg_iop_scrc_in_rw_wr1bit;
-#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
-#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
-
-
-/* Constants */
-enum {
- regk_iop_scrc_in_dif_in = 0x00000002,
- regk_iop_scrc_in_hi = 0x00000000,
- regk_iop_scrc_in_neg = 0x00000002,
- regk_iop_scrc_in_no = 0x00000000,
- regk_iop_scrc_in_pos = 0x00000001,
- regk_iop_scrc_in_pos_neg = 0x00000003,
- regk_iop_scrc_in_r_computed_crc_default = 0x00000000,
- regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
- regk_iop_scrc_in_rw_cfg_default = 0x00000000,
- regk_iop_scrc_in_rw_ctrl_default = 0x00000000,
- regk_iop_scrc_in_rw_init_crc_default = 0x00000000,
- regk_iop_scrc_in_set0 = 0x00000000,
- regk_iop_scrc_in_set1 = 0x00000001,
- regk_iop_scrc_in_yes = 0x00000001
-};
-#endif /* __iop_scrc_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h
deleted file mode 100644
index ba39605b9737..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_out_defs_h
-#define __iop_scrc_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_scrc_out */
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-typedef struct {
- unsigned int trig : 2;
- unsigned int inv_crc : 1;
- unsigned int dummy1 : 29;
-} reg_iop_scrc_out_rw_cfg;
-#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0
-#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-typedef struct {
- unsigned int strb_src : 1;
- unsigned int out_src : 1;
- unsigned int dummy1 : 30;
-} reg_iop_scrc_out_rw_ctrl;
-#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-typedef unsigned int reg_iop_scrc_out_rw_init_crc;
-#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8
-#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-typedef unsigned int reg_iop_scrc_out_rw_crc;
-#define REG_RD_ADDR_iop_scrc_out_rw_crc 12
-#define REG_WR_ADDR_iop_scrc_out_rw_crc 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-typedef struct {
- unsigned int val : 1;
- unsigned int dummy1 : 31;
-} reg_iop_scrc_out_rw_data;
-#define REG_RD_ADDR_iop_scrc_out_rw_data 16
-#define REG_WR_ADDR_iop_scrc_out_rw_data 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-typedef unsigned int reg_iop_scrc_out_r_computed_crc;
-#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20
-
-
-/* Constants */
-enum {
- regk_iop_scrc_out_crc = 0x00000001,
- regk_iop_scrc_out_data = 0x00000000,
- regk_iop_scrc_out_dif = 0x00000001,
- regk_iop_scrc_out_hi = 0x00000000,
- regk_iop_scrc_out_neg = 0x00000002,
- regk_iop_scrc_out_no = 0x00000000,
- regk_iop_scrc_out_pos = 0x00000001,
- regk_iop_scrc_out_pos_neg = 0x00000003,
- regk_iop_scrc_out_reg = 0x00000000,
- regk_iop_scrc_out_rw_cfg_default = 0x00000000,
- regk_iop_scrc_out_rw_crc_default = 0x00000000,
- regk_iop_scrc_out_rw_ctrl_default = 0x00000000,
- regk_iop_scrc_out_rw_data_default = 0x00000000,
- regk_iop_scrc_out_rw_init_crc_default = 0x00000000,
- regk_iop_scrc_out_yes = 0x00000001
-};
-#endif /* __iop_scrc_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h
deleted file mode 100644
index 7681fdab93fc..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_spu_defs_h
-#define __iop_spu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
- * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_spu */
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_r;
-#define REG_RD_ADDR_iop_spu_rw_r 0
-#define REG_WR_ADDR_iop_spu_rw_r 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_spu_rw_seq_pc;
-#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
-#define REG_WR_ADDR_iop_spu_rw_seq_pc 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_spu_rw_fsm_pc;
-#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
-#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-typedef struct {
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 30;
-} reg_iop_spu_rw_ctrl;
-#define REG_RD_ADDR_iop_spu_rw_ctrl 72
-#define REG_WR_ADDR_iop_spu_rw_ctrl 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-typedef struct {
- unsigned int val0 : 5;
- unsigned int src0 : 3;
- unsigned int val1 : 5;
- unsigned int src1 : 3;
- unsigned int val2 : 5;
- unsigned int src2 : 3;
- unsigned int val3 : 5;
- unsigned int src3 : 3;
-} reg_iop_spu_rw_fsm_inputs3_0;
-#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
-#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-typedef struct {
- unsigned int val4 : 5;
- unsigned int src4 : 3;
- unsigned int val5 : 5;
- unsigned int src5 : 3;
- unsigned int val6 : 5;
- unsigned int src6 : 3;
- unsigned int val7 : 5;
- unsigned int src7 : 3;
-} reg_iop_spu_rw_fsm_inputs7_4;
-#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
-#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out;
-#define REG_RD_ADDR_iop_spu_rw_gio_out 84
-#define REG_WR_ADDR_iop_spu_rw_gio_out 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_bus0_out;
-#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
-#define REG_WR_ADDR_iop_spu_rw_bus0_out 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_bus1_out;
-#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
-#define REG_WR_ADDR_iop_spu_rw_bus1_out 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_gio_in;
-#define REG_RD_ADDR_iop_spu_r_gio_in 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_bus0_in;
-#define REG_RD_ADDR_iop_spu_r_bus0_in 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_bus1_in;
-#define REG_RD_ADDR_iop_spu_r_bus1_in 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out_set;
-#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
-#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out_clr;
-#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
-#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-typedef struct {
- unsigned int r0 : 1;
- unsigned int r1 : 1;
- unsigned int r2 : 1;
- unsigned int r3 : 1;
- unsigned int r4 : 1;
- unsigned int r5 : 1;
- unsigned int r6 : 1;
- unsigned int r7 : 1;
- unsigned int r8 : 1;
- unsigned int r9 : 1;
- unsigned int r10 : 1;
- unsigned int r11 : 1;
- unsigned int r12 : 1;
- unsigned int r13 : 1;
- unsigned int r14 : 1;
- unsigned int r15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_spu_rs_wr_stat;
-#define REG_RD_ADDR_iop_spu_rs_wr_stat 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-typedef struct {
- unsigned int r0 : 1;
- unsigned int r1 : 1;
- unsigned int r2 : 1;
- unsigned int r3 : 1;
- unsigned int r4 : 1;
- unsigned int r5 : 1;
- unsigned int r6 : 1;
- unsigned int r7 : 1;
- unsigned int r8 : 1;
- unsigned int r9 : 1;
- unsigned int r10 : 1;
- unsigned int r11 : 1;
- unsigned int r12 : 1;
- unsigned int r13 : 1;
- unsigned int r14 : 1;
- unsigned int r15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_spu_r_wr_stat;
-#define REG_RD_ADDR_iop_spu_r_wr_stat 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;
-#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-typedef struct {
- unsigned int timer_grp_lo : 4;
- unsigned int fifo_out_last : 1;
- unsigned int fifo_out_rdy : 1;
- unsigned int fifo_out_all : 1;
- unsigned int fifo_in_rdy : 1;
- unsigned int dmc_out_all : 1;
- unsigned int dmc_out_dth : 1;
- unsigned int dmc_out_eop : 1;
- unsigned int dmc_out_dv : 1;
- unsigned int dmc_out_last : 1;
- unsigned int dmc_out_cmd_rq : 1;
- unsigned int dmc_out_cmd_rdy : 1;
- unsigned int pcrc_correct : 1;
- unsigned int timer_grp_hi : 4;
- unsigned int dmc_in_sth : 1;
- unsigned int dmc_in_full : 1;
- unsigned int dmc_in_cmd_rdy : 1;
- unsigned int spu_gio_out : 4;
- unsigned int sync_clk12 : 1;
- unsigned int scrc_out_data : 1;
- unsigned int scrc_in_err : 1;
- unsigned int mc_busy : 1;
- unsigned int mc_owned : 1;
-} reg_iop_spu_r_stat_in;
-#define REG_RD_ADDR_iop_spu_r_stat_in 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_trigger_in;
-#define REG_RD_ADDR_iop_spu_r_trigger_in 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-typedef struct {
- unsigned int c_flag : 1;
- unsigned int v_flag : 1;
- unsigned int z_flag : 1;
- unsigned int n_flag : 1;
- unsigned int xor_bus0_r2_0 : 1;
- unsigned int xor_bus1_r3_0 : 1;
- unsigned int xor_bus0m_r2_0 : 1;
- unsigned int xor_bus1m_r3_0 : 1;
- unsigned int fsm_in0 : 1;
- unsigned int fsm_in1 : 1;
- unsigned int fsm_in2 : 1;
- unsigned int fsm_in3 : 1;
- unsigned int fsm_in4 : 1;
- unsigned int fsm_in5 : 1;
- unsigned int fsm_in6 : 1;
- unsigned int fsm_in7 : 1;
- unsigned int event0 : 1;
- unsigned int event1 : 1;
- unsigned int event2 : 1;
- unsigned int event3 : 1;
- unsigned int dummy1 : 12;
-} reg_iop_spu_r_special_stat;
-#define REG_RD_ADDR_iop_spu_r_special_stat 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 13;
- unsigned int dummy1 : 3;
- unsigned int imm_hi : 16;
-} reg_iop_spu_rw_reg_access;
-#define REG_RD_ADDR_iop_spu_rw_reg_access 140
-#define REG_WR_ADDR_iop_spu_rw_reg_access 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int src : 2;
- unsigned int eq_en : 1;
- unsigned int eq_inv : 1;
- unsigned int gt_en : 1;
- unsigned int gt_inv : 1;
- unsigned int dummy1 : 14;
-} reg_iop_spu_rw_event_cfg;
-#define REG_RD_ADDR_iop_spu_rw_event_cfg 144
-#define REG_WR_ADDR_iop_spu_rw_event_cfg 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_event_mask;
-#define REG_RD_ADDR_iop_spu_rw_event_mask 160
-#define REG_WR_ADDR_iop_spu_rw_event_mask 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_event_val;
-#define REG_RD_ADDR_iop_spu_rw_event_val 176
-#define REG_WR_ADDR_iop_spu_rw_event_val 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_spu_rw_event_ret;
-#define REG_RD_ADDR_iop_spu_rw_event_ret 192
-#define REG_WR_ADDR_iop_spu_rw_event_ret 192
-
-/* Register r_trace, scope iop_spu, type r */
-typedef struct {
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int c_flag : 1;
- unsigned int v_flag : 1;
- unsigned int z_flag : 1;
- unsigned int n_flag : 1;
- unsigned int seq_addr : 12;
- unsigned int dummy1 : 2;
- unsigned int fsm_addr : 12;
-} reg_iop_spu_r_trace;
-#define REG_RD_ADDR_iop_spu_r_trace 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-typedef struct {
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int tmr_done : 1;
- unsigned int inp0 : 1;
- unsigned int inp1 : 1;
- unsigned int inp2 : 1;
- unsigned int inp3 : 1;
- unsigned int event0 : 1;
- unsigned int event1 : 1;
- unsigned int event2 : 1;
- unsigned int event3 : 1;
- unsigned int gio_out : 8;
- unsigned int dummy1 : 1;
- unsigned int fsm_addr : 12;
-} reg_iop_spu_r_fsm_trace;
-#define REG_RD_ADDR_iop_spu_r_fsm_trace 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 18;
-} reg_iop_spu_rw_brp;
-#define REG_RD_ADDR_iop_spu_rw_brp 204
-#define REG_WR_ADDR_iop_spu_rw_brp 204
-
-
-/* Constants */
-enum {
- regk_iop_spu_attn_hi = 0x00000005,
- regk_iop_spu_attn_lo = 0x00000005,
- regk_iop_spu_attn_r0 = 0x00000000,
- regk_iop_spu_attn_r1 = 0x00000001,
- regk_iop_spu_attn_r10 = 0x00000002,
- regk_iop_spu_attn_r11 = 0x00000003,
- regk_iop_spu_attn_r12 = 0x00000004,
- regk_iop_spu_attn_r13 = 0x00000005,
- regk_iop_spu_attn_r14 = 0x00000006,
- regk_iop_spu_attn_r15 = 0x00000007,
- regk_iop_spu_attn_r2 = 0x00000002,
- regk_iop_spu_attn_r3 = 0x00000003,
- regk_iop_spu_attn_r4 = 0x00000004,
- regk_iop_spu_attn_r5 = 0x00000005,
- regk_iop_spu_attn_r6 = 0x00000006,
- regk_iop_spu_attn_r7 = 0x00000007,
- regk_iop_spu_attn_r8 = 0x00000000,
- regk_iop_spu_attn_r9 = 0x00000001,
- regk_iop_spu_c = 0x00000000,
- regk_iop_spu_flag = 0x00000002,
- regk_iop_spu_gio_in = 0x00000000,
- regk_iop_spu_gio_out = 0x00000005,
- regk_iop_spu_gio_out0 = 0x00000008,
- regk_iop_spu_gio_out1 = 0x00000009,
- regk_iop_spu_gio_out2 = 0x0000000a,
- regk_iop_spu_gio_out3 = 0x0000000b,
- regk_iop_spu_gio_out4 = 0x0000000c,
- regk_iop_spu_gio_out5 = 0x0000000d,
- regk_iop_spu_gio_out6 = 0x0000000e,
- regk_iop_spu_gio_out7 = 0x0000000f,
- regk_iop_spu_n = 0x00000003,
- regk_iop_spu_no = 0x00000000,
- regk_iop_spu_r0 = 0x00000008,
- regk_iop_spu_r1 = 0x00000009,
- regk_iop_spu_r10 = 0x0000000a,
- regk_iop_spu_r11 = 0x0000000b,
- regk_iop_spu_r12 = 0x0000000c,
- regk_iop_spu_r13 = 0x0000000d,
- regk_iop_spu_r14 = 0x0000000e,
- regk_iop_spu_r15 = 0x0000000f,
- regk_iop_spu_r2 = 0x0000000a,
- regk_iop_spu_r3 = 0x0000000b,
- regk_iop_spu_r4 = 0x0000000c,
- regk_iop_spu_r5 = 0x0000000d,
- regk_iop_spu_r6 = 0x0000000e,
- regk_iop_spu_r7 = 0x0000000f,
- regk_iop_spu_r8 = 0x00000008,
- regk_iop_spu_r9 = 0x00000009,
- regk_iop_spu_reg_hi = 0x00000002,
- regk_iop_spu_reg_lo = 0x00000002,
- regk_iop_spu_rw_brp_default = 0x00000000,
- regk_iop_spu_rw_brp_size = 0x00000004,
- regk_iop_spu_rw_ctrl_default = 0x00000000,
- regk_iop_spu_rw_event_cfg_size = 0x00000004,
- regk_iop_spu_rw_event_mask_size = 0x00000004,
- regk_iop_spu_rw_event_val_size = 0x00000004,
- regk_iop_spu_rw_gio_out_default = 0x00000000,
- regk_iop_spu_rw_r_size = 0x00000010,
- regk_iop_spu_rw_reg_access_default = 0x00000000,
- regk_iop_spu_stat_in = 0x00000002,
- regk_iop_spu_statin_hi = 0x00000004,
- regk_iop_spu_statin_lo = 0x00000004,
- regk_iop_spu_trig = 0x00000003,
- regk_iop_spu_trigger = 0x00000006,
- regk_iop_spu_v = 0x00000001,
- regk_iop_spu_wsts_gioout_spec = 0x00000001,
- regk_iop_spu_xor = 0x00000003,
- regk_iop_spu_xor_bus0_r2_0 = 0x00000000,
- regk_iop_spu_xor_bus0m_r2_0 = 0x00000002,
- regk_iop_spu_xor_bus1_r3_0 = 0x00000001,
- regk_iop_spu_xor_bus1m_r3_0 = 0x00000003,
- regk_iop_spu_yes = 0x00000001,
- regk_iop_spu_z = 0x00000002
-};
-#endif /* __iop_spu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h
deleted file mode 100644
index 86e5c9b3e593..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_h
-#define __iop_sw_cfg_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cfg */
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp4_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp5_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp6_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp7_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus0_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus0_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus1_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus1_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_byte0 : 2;
- unsigned int bus0_byte1 : 2;
- unsigned int bus0_byte2 : 2;
- unsigned int bus0_byte3 : 2;
- unsigned int bus1_byte0 : 2;
- unsigned int bus1_byte1 : 2;
- unsigned int bus1_byte2 : 2;
- unsigned int bus1_byte3 : 2;
- unsigned int gio3_0 : 2;
- unsigned int gio7_4 : 2;
- unsigned int gio11_8 : 2;
- unsigned int gio15_12 : 2;
- unsigned int gio19_16 : 2;
- unsigned int gio23_20 : 2;
- unsigned int gio27_24 : 2;
- unsigned int gio31_28 : 2;
-} reg_iop_sw_cfg_rw_pinmapping;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
-#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_lo : 3;
- unsigned int bus0_hi : 3;
- unsigned int bus0_lo_oe : 3;
- unsigned int bus0_hi_oe : 3;
- unsigned int bus1_lo : 3;
- unsigned int bus1_hi : 3;
- unsigned int bus1_lo_oe : 3;
- unsigned int bus1_hi_oe : 3;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_bus_out_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio0 : 4;
- unsigned int gio0_oe : 2;
- unsigned int gio1 : 4;
- unsigned int gio1_oe : 2;
- unsigned int gio2 : 4;
- unsigned int gio2_oe : 2;
- unsigned int gio3 : 4;
- unsigned int gio3_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio4 : 4;
- unsigned int gio4_oe : 2;
- unsigned int gio5 : 4;
- unsigned int gio5_oe : 2;
- unsigned int gio6 : 4;
- unsigned int gio6_oe : 2;
- unsigned int gio7 : 4;
- unsigned int gio7_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio8 : 4;
- unsigned int gio8_oe : 2;
- unsigned int gio9 : 4;
- unsigned int gio9_oe : 2;
- unsigned int gio10 : 4;
- unsigned int gio10_oe : 2;
- unsigned int gio11 : 4;
- unsigned int gio11_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio12 : 4;
- unsigned int gio12_oe : 2;
- unsigned int gio13 : 4;
- unsigned int gio13_oe : 2;
- unsigned int gio14 : 4;
- unsigned int gio14_oe : 2;
- unsigned int gio15 : 4;
- unsigned int gio15_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio16 : 4;
- unsigned int gio16_oe : 2;
- unsigned int gio17 : 4;
- unsigned int gio17_oe : 2;
- unsigned int gio18 : 4;
- unsigned int gio18_oe : 2;
- unsigned int gio19 : 4;
- unsigned int gio19_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio20 : 4;
- unsigned int gio20_oe : 2;
- unsigned int gio21 : 4;
- unsigned int gio21_oe : 2;
- unsigned int gio22 : 4;
- unsigned int gio22_oe : 2;
- unsigned int gio23 : 4;
- unsigned int gio23_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio24 : 4;
- unsigned int gio24_oe : 2;
- unsigned int gio25 : 4;
- unsigned int gio25_oe : 2;
- unsigned int gio26 : 4;
- unsigned int gio26_oe : 2;
- unsigned int gio27 : 4;
- unsigned int gio27_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio28 : 4;
- unsigned int gio28_oe : 2;
- unsigned int gio29 : 4;
- unsigned int gio29_oe : 2;
- unsigned int gio30 : 4;
- unsigned int gio30_oe : 2;
- unsigned int gio31 : 4;
- unsigned int gio31_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_in : 2;
- unsigned int bus1_in : 2;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_spu0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_in : 2;
- unsigned int bus1_in : 2;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_spu1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int grp0_dis : 1;
- unsigned int grp0_en : 1;
- unsigned int grp1_dis : 1;
- unsigned int grp1_en : 1;
- unsigned int grp2_dis : 1;
- unsigned int grp2_en : 1;
- unsigned int grp3_dis : 1;
- unsigned int grp3_en : 1;
- unsigned int grp4_dis : 1;
- unsigned int grp4_en : 1;
- unsigned int grp5_dis : 1;
- unsigned int grp5_en : 1;
- unsigned int grp6_dis : 1;
- unsigned int grp6_en : 1;
- unsigned int grp7_dis : 1;
- unsigned int grp7_en : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_trigger_grps_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int dmc0_usr : 1;
- unsigned int out_strb : 5;
- unsigned int in_src : 3;
- unsigned int in_size : 3;
- unsigned int in_last : 2;
- unsigned int in_strb : 4;
- unsigned int out_src : 1;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_pdp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int dmc1_usr : 1;
- unsigned int out_strb : 5;
- unsigned int in_src : 3;
- unsigned int in_size : 3;
- unsigned int in_last : 2;
- unsigned int in_strb : 4;
- unsigned int out_src : 1;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_pdp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int sdp_out0_strb : 3;
- unsigned int sdp_out1_strb : 3;
- unsigned int sdp_in0_data : 3;
- unsigned int sdp_in0_last : 2;
- unsigned int sdp_in0_strb : 3;
- unsigned int sdp_in1_data : 3;
- unsigned int sdp_in1_last : 2;
- unsigned int sdp_in1_strb : 3;
- unsigned int dummy1 : 10;
-} reg_iop_sw_cfg_rw_sdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
-#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
-
-
-/* Constants */
-enum {
- regk_iop_sw_cfg_a = 0x00000001,
- regk_iop_sw_cfg_b = 0x00000002,
- regk_iop_sw_cfg_bus0 = 0x00000000,
- regk_iop_sw_cfg_bus0_rot16 = 0x00000004,
- regk_iop_sw_cfg_bus0_rot24 = 0x00000006,
- regk_iop_sw_cfg_bus0_rot8 = 0x00000002,
- regk_iop_sw_cfg_bus1 = 0x00000001,
- regk_iop_sw_cfg_bus1_rot16 = 0x00000005,
- regk_iop_sw_cfg_bus1_rot24 = 0x00000007,
- regk_iop_sw_cfg_bus1_rot8 = 0x00000003,
- regk_iop_sw_cfg_clk12 = 0x00000000,
- regk_iop_sw_cfg_cpu = 0x00000000,
- regk_iop_sw_cfg_dmc0 = 0x00000000,
- regk_iop_sw_cfg_dmc1 = 0x00000001,
- regk_iop_sw_cfg_gated_clk0 = 0x00000010,
- regk_iop_sw_cfg_gated_clk1 = 0x00000011,
- regk_iop_sw_cfg_gated_clk2 = 0x00000012,
- regk_iop_sw_cfg_gated_clk3 = 0x00000013,
- regk_iop_sw_cfg_gio0 = 0x00000004,
- regk_iop_sw_cfg_gio1 = 0x00000001,
- regk_iop_sw_cfg_gio2 = 0x00000005,
- regk_iop_sw_cfg_gio3 = 0x00000002,
- regk_iop_sw_cfg_gio4 = 0x00000006,
- regk_iop_sw_cfg_gio5 = 0x00000003,
- regk_iop_sw_cfg_gio6 = 0x00000007,
- regk_iop_sw_cfg_gio7 = 0x00000004,
- regk_iop_sw_cfg_gio_in0 = 0x00000000,
- regk_iop_sw_cfg_gio_in1 = 0x00000001,
- regk_iop_sw_cfg_gio_in10 = 0x00000002,
- regk_iop_sw_cfg_gio_in11 = 0x00000003,
- regk_iop_sw_cfg_gio_in14 = 0x00000004,
- regk_iop_sw_cfg_gio_in15 = 0x00000005,
- regk_iop_sw_cfg_gio_in18 = 0x00000002,
- regk_iop_sw_cfg_gio_in19 = 0x00000003,
- regk_iop_sw_cfg_gio_in20 = 0x00000004,
- regk_iop_sw_cfg_gio_in21 = 0x00000005,
- regk_iop_sw_cfg_gio_in26 = 0x00000006,
- regk_iop_sw_cfg_gio_in27 = 0x00000007,
- regk_iop_sw_cfg_gio_in28 = 0x00000006,
- regk_iop_sw_cfg_gio_in29 = 0x00000007,
- regk_iop_sw_cfg_gio_in4 = 0x00000000,
- regk_iop_sw_cfg_gio_in5 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002,
- regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003,
- regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002,
- regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003,
- regk_iop_sw_cfg_mpu = 0x00000001,
- regk_iop_sw_cfg_none = 0x00000000,
- regk_iop_sw_cfg_par0 = 0x00000000,
- regk_iop_sw_cfg_par1 = 0x00000001,
- regk_iop_sw_cfg_pdp_out0 = 0x00000002,
- regk_iop_sw_cfg_pdp_out0_hi = 0x00000001,
- regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005,
- regk_iop_sw_cfg_pdp_out0_lo = 0x00000000,
- regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004,
- regk_iop_sw_cfg_pdp_out1 = 0x00000003,
- regk_iop_sw_cfg_pdp_out1_hi = 0x00000003,
- regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005,
- regk_iop_sw_cfg_pdp_out1_lo = 0x00000002,
- regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004,
- regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555,
- regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
- regk_iop_sw_cfg_sdp_out0 = 0x00000008,
- regk_iop_sw_cfg_sdp_out1 = 0x00000009,
- regk_iop_sw_cfg_size16 = 0x00000002,
- regk_iop_sw_cfg_size24 = 0x00000003,
- regk_iop_sw_cfg_size32 = 0x00000004,
- regk_iop_sw_cfg_size8 = 0x00000001,
- regk_iop_sw_cfg_spu0 = 0x00000002,
- regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006,
- regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006,
- regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007,
- regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007,
- regk_iop_sw_cfg_spu0_g0 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g1 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g2 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g3 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g4 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g5 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g6 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g7 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gio0 = 0x00000000,
- regk_iop_sw_cfg_spu0_gio1 = 0x00000001,
- regk_iop_sw_cfg_spu0_gio2 = 0x00000000,
- regk_iop_sw_cfg_spu0_gio5 = 0x00000005,
- regk_iop_sw_cfg_spu0_gio6 = 0x00000006,
- regk_iop_sw_cfg_spu0_gio7 = 0x00000007,
- regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008,
- regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009,
- regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a,
- regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b,
- regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c,
- regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d,
- regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f,
- regk_iop_sw_cfg_spu0_gioout0 = 0x00000000,
- regk_iop_sw_cfg_spu0_gioout1 = 0x00000000,
- regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout2 = 0x00000002,
- regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout3 = 0x00000002,
- regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout4 = 0x00000004,
- regk_iop_sw_cfg_spu0_gioout5 = 0x00000004,
- regk_iop_sw_cfg_spu0_gioout6 = 0x00000006,
- regk_iop_sw_cfg_spu0_gioout7 = 0x00000006,
- regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e,
- regk_iop_sw_cfg_spu1 = 0x00000003,
- regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006,
- regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006,
- regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007,
- regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007,
- regk_iop_sw_cfg_spu1_g0 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g1 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g2 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g3 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g4 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g5 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g6 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g7 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gio0 = 0x00000002,
- regk_iop_sw_cfg_spu1_gio1 = 0x00000003,
- regk_iop_sw_cfg_spu1_gio2 = 0x00000002,
- regk_iop_sw_cfg_spu1_gio5 = 0x00000005,
- regk_iop_sw_cfg_spu1_gio6 = 0x00000006,
- regk_iop_sw_cfg_spu1_gio7 = 0x00000007,
- regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008,
- regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009,
- regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a,
- regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b,
- regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c,
- regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d,
- regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e,
- regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout0 = 0x00000001,
- regk_iop_sw_cfg_spu1_gioout1 = 0x00000001,
- regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout2 = 0x00000003,
- regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout3 = 0x00000003,
- regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout4 = 0x00000005,
- regk_iop_sw_cfg_spu1_gioout5 = 0x00000005,
- regk_iop_sw_cfg_spu1_gioout6 = 0x00000007,
- regk_iop_sw_cfg_spu1_gioout7 = 0x00000007,
- regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f,
- regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
- regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001,
- regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003,
- regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003,
- regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002,
- regk_iop_sw_cfg_timer_grp0 = 0x00000000,
- regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004,
- regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004,
- regk_iop_sw_cfg_timer_grp1 = 0x00000000,
- regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005,
- regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005,
- regk_iop_sw_cfg_timer_grp2 = 0x00000000,
- regk_iop_sw_cfg_timer_grp2_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006,
- regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006,
- regk_iop_sw_cfg_timer_grp3 = 0x00000000,
- regk_iop_sw_cfg_timer_grp3_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007,
- regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007,
- regk_iop_sw_cfg_trig0_0 = 0x00000000,
- regk_iop_sw_cfg_trig0_1 = 0x00000000,
- regk_iop_sw_cfg_trig0_2 = 0x00000000,
- regk_iop_sw_cfg_trig0_3 = 0x00000000,
- regk_iop_sw_cfg_trig1_0 = 0x00000000,
- regk_iop_sw_cfg_trig1_1 = 0x00000000,
- regk_iop_sw_cfg_trig1_2 = 0x00000000,
- regk_iop_sw_cfg_trig1_3 = 0x00000000,
- regk_iop_sw_cfg_trig2_0 = 0x00000000,
- regk_iop_sw_cfg_trig2_1 = 0x00000000,
- regk_iop_sw_cfg_trig2_2 = 0x00000000,
- regk_iop_sw_cfg_trig2_3 = 0x00000000,
- regk_iop_sw_cfg_trig3_0 = 0x00000000,
- regk_iop_sw_cfg_trig3_1 = 0x00000000,
- regk_iop_sw_cfg_trig3_2 = 0x00000000,
- regk_iop_sw_cfg_trig3_3 = 0x00000000,
- regk_iop_sw_cfg_trig4_0 = 0x00000001,
- regk_iop_sw_cfg_trig4_1 = 0x00000001,
- regk_iop_sw_cfg_trig4_2 = 0x00000001,
- regk_iop_sw_cfg_trig4_3 = 0x00000001,
- regk_iop_sw_cfg_trig5_0 = 0x00000001,
- regk_iop_sw_cfg_trig5_1 = 0x00000001,
- regk_iop_sw_cfg_trig5_2 = 0x00000001,
- regk_iop_sw_cfg_trig5_3 = 0x00000001,
- regk_iop_sw_cfg_trig6_0 = 0x00000001,
- regk_iop_sw_cfg_trig6_1 = 0x00000001,
- regk_iop_sw_cfg_trig6_2 = 0x00000001,
- regk_iop_sw_cfg_trig6_3 = 0x00000001,
- regk_iop_sw_cfg_trig7_0 = 0x00000001,
- regk_iop_sw_cfg_trig7_1 = 0x00000001,
- regk_iop_sw_cfg_trig7_2 = 0x00000001,
- regk_iop_sw_cfg_trig7_3 = 0x00000001
-};
-#endif /* __iop_sw_cfg_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h
deleted file mode 100644
index 31055d3fcd76..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h
+++ /dev/null
@@ -1,854 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_h
-#define __iop_sw_cpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cpu */
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu0_mem : 1;
- unsigned int wr_spu1_mem : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_cpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu0 : 1;
- unsigned int busy_spu1 : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu0 : 1;
- unsigned int owned_by_spu1 : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_cpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_rw_intr0_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_rw_ack_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_r_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_r_masked_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_rw_intr1_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_rw_ack_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_r_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_r_masked_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_rw_intr2_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_masked_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
-} reg_iop_sw_cpu_rw_intr3_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
-} reg_iop_sw_cpu_r_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
-} reg_iop_sw_cpu_r_masked_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
-
-
-/* Constants */
-enum {
- regk_iop_sw_cpu_copy = 0x00000000,
- regk_iop_sw_cpu_no = 0x00000000,
- regk_iop_sw_cpu_rd = 0x00000002,
- regk_iop_sw_cpu_reg_copy = 0x00000001,
- regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000,
- regk_iop_sw_cpu_wr = 0x00000003,
- regk_iop_sw_cpu_yes = 0x00000001
-};
-#endif /* __iop_sw_cpu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h
deleted file mode 100644
index 5038c08e8a95..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h
+++ /dev/null
@@ -1,894 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_h
-#define __iop_sw_mpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_mpu */
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_mpu_rw_sw_cfg_owner;
-#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu0_mem : 1;
- unsigned int wr_spu1_mem : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_mpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu0 : 1;
- unsigned int busy_spu1 : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu0 : 1;
- unsigned int owned_by_spu1 : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_mpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
-#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp0_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp1_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp2_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp3_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
-
-
-/* Constants */
-enum {
- regk_iop_sw_mpu_copy = 0x00000000,
- regk_iop_sw_mpu_cpu = 0x00000000,
- regk_iop_sw_mpu_mpu = 0x00000001,
- regk_iop_sw_mpu_no = 0x00000000,
- regk_iop_sw_mpu_nop = 0x00000000,
- regk_iop_sw_mpu_rd = 0x00000002,
- regk_iop_sw_mpu_reg_copy = 0x00000001,
- regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
- regk_iop_sw_mpu_set = 0x00000001,
- regk_iop_sw_mpu_spu0 = 0x00000002,
- regk_iop_sw_mpu_spu1 = 0x00000003,
- regk_iop_sw_mpu_wr = 0x00000003,
- regk_iop_sw_mpu_yes = 0x00000001
-};
-#endif /* __iop_sw_mpu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h
deleted file mode 100644
index aeebd57af7f7..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_h
-#define __iop_sw_spu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_spu */
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu0_mem : 1;
- unsigned int wr_spu1_mem : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_spu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-typedef unsigned int reg_iop_sw_spu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu0 : 1;
- unsigned int busy_spu1 : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu0 : 1;
- unsigned int owned_by_spu1 : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_spu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
-#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dummy1 : 8;
-} reg_iop_sw_spu_r_hw_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
-#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int other_spu_intr0 : 1;
- unsigned int other_spu_intr1 : 1;
- unsigned int other_spu_intr2 : 1;
- unsigned int other_spu_intr3 : 1;
- unsigned int other_spu_intr4 : 1;
- unsigned int other_spu_intr5 : 1;
- unsigned int other_spu_intr6 : 1;
- unsigned int other_spu_intr7 : 1;
- unsigned int other_spu_intr8 : 1;
- unsigned int other_spu_intr9 : 1;
- unsigned int other_spu_intr10 : 1;
- unsigned int other_spu_intr11 : 1;
- unsigned int other_spu_intr12 : 1;
- unsigned int other_spu_intr13 : 1;
- unsigned int other_spu_intr14 : 1;
- unsigned int other_spu_intr15 : 1;
-} reg_iop_sw_spu_r_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
-
-
-/* Constants */
-enum {
- regk_iop_sw_spu_copy = 0x00000000,
- regk_iop_sw_spu_no = 0x00000000,
- regk_iop_sw_spu_nop = 0x00000000,
- regk_iop_sw_spu_rd = 0x00000002,
- regk_iop_sw_spu_reg_copy = 0x00000001,
- regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_spu_set = 0x00000001,
- regk_iop_sw_spu_wr = 0x00000003,
- regk_iop_sw_spu_yes = 0x00000001
-};
-#endif /* __iop_sw_spu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h
deleted file mode 100644
index b4095422adf6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_timer_grp_defs_h
-#define __iop_timer_grp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_timer_grp */
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int clk_src : 1;
- unsigned int trig : 2;
- unsigned int clk_gen_div : 8;
- unsigned int clk_div : 8;
- unsigned int dummy1 : 13;
-} reg_iop_timer_grp_rw_cfg;
-#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
-#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int quota_lo : 15;
- unsigned int quota_hi : 15;
- unsigned int quota_hi_sel : 1;
- unsigned int dummy1 : 1;
-} reg_iop_timer_grp_rw_half_period;
-#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
-#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
-#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
-#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int clk_src : 3;
- unsigned int strb : 2;
- unsigned int run_mode : 2;
- unsigned int out_mode : 1;
- unsigned int active_on_tmr : 2;
- unsigned int inv : 1;
- unsigned int en_by_tmr : 2;
- unsigned int dis_by_tmr : 2;
- unsigned int en_only_by_reg : 1;
- unsigned int dis_only_by_reg : 1;
- unsigned int rst_at_en_strb : 1;
- unsigned int dummy1 : 14;
-} reg_iop_timer_grp_rw_tmr_cfg;
-#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
-#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rw_tmr_len;
-#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
-#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int rst : 4;
- unsigned int en : 4;
- unsigned int dis : 4;
- unsigned int strb : 4;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rw_cmd;
-#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
-#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
-#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rs_tmr_cnt;
-#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_r_tmr_cnt;
-#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_rw_intr_mask;
-#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
-#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_rw_ack_intr;
-#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
-#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_r_intr;
-#define REG_RD_ADDR_iop_timer_grp_r_intr 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_r_masked_intr;
-#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
-
-
-/* Constants */
-enum {
- regk_iop_timer_grp_clk200 = 0x00000000,
- regk_iop_timer_grp_clk_gen = 0x00000002,
- regk_iop_timer_grp_complete = 0x00000002,
- regk_iop_timer_grp_div_clk200 = 0x00000001,
- regk_iop_timer_grp_div_clk_gen = 0x00000003,
- regk_iop_timer_grp_ext = 0x00000001,
- regk_iop_timer_grp_hi = 0x00000000,
- regk_iop_timer_grp_long_period = 0x00000001,
- regk_iop_timer_grp_neg = 0x00000002,
- regk_iop_timer_grp_no = 0x00000000,
- regk_iop_timer_grp_once = 0x00000003,
- regk_iop_timer_grp_pause = 0x00000001,
- regk_iop_timer_grp_pos = 0x00000001,
- regk_iop_timer_grp_pos_neg = 0x00000003,
- regk_iop_timer_grp_pulse = 0x00000000,
- regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004,
- regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004,
- regk_iop_timer_grp_rw_cfg_default = 0x00000002,
- regk_iop_timer_grp_rw_intr_mask_default = 0x00000000,
- regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000,
- regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900,
- regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200,
- regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00,
- regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004,
- regk_iop_timer_grp_rw_tmr_len_default = 0x00000000,
- regk_iop_timer_grp_rw_tmr_len_size = 0x00000004,
- regk_iop_timer_grp_short_period = 0x00000000,
- regk_iop_timer_grp_stop = 0x00000000,
- regk_iop_timer_grp_tmr = 0x00000004,
- regk_iop_timer_grp_toggle = 0x00000001,
- regk_iop_timer_grp_yes = 0x00000001
-};
-#endif /* __iop_timer_grp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h
deleted file mode 100644
index aff694506e7f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_trigger_grp_defs_h
-#define __iop_trigger_grp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_trigger_grp */
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int action : 2;
- unsigned int once : 1;
- unsigned int trig : 3;
- unsigned int en_only_by_reg : 1;
- unsigned int dis_only_by_reg : 1;
- unsigned int dummy1 : 24;
-} reg_iop_trigger_grp_rw_cfg;
-#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
-#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int dis : 4;
- unsigned int en : 4;
- unsigned int dummy1 : 24;
-} reg_iop_trigger_grp_rw_cmd;
-#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
-#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_rw_intr_mask;
-#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
-#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_rw_ack_intr;
-#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
-#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_r_intr;
-#define REG_RD_ADDR_iop_trigger_grp_r_intr 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_r_masked_intr;
-#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
-
-
-/* Constants */
-enum {
- regk_iop_trigger_grp_fall = 0x00000002,
- regk_iop_trigger_grp_fall_lo = 0x00000006,
- regk_iop_trigger_grp_no = 0x00000000,
- regk_iop_trigger_grp_off = 0x00000000,
- regk_iop_trigger_grp_pulse = 0x00000000,
- regk_iop_trigger_grp_rise = 0x00000001,
- regk_iop_trigger_grp_rise_fall = 0x00000003,
- regk_iop_trigger_grp_rise_fall_hi = 0x00000007,
- regk_iop_trigger_grp_rise_fall_lo = 0x00000004,
- regk_iop_trigger_grp_rise_hi = 0x00000005,
- regk_iop_trigger_grp_rw_cfg_default = 0x000000c0,
- regk_iop_trigger_grp_rw_cfg_size = 0x00000004,
- regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
- regk_iop_trigger_grp_toggle = 0x00000003,
- regk_iop_trigger_grp_yes = 0x00000001
-};
-#endif /* __iop_trigger_grp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h
deleted file mode 100644
index 53a4b8cda969..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_h
-#define __iop_version_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- * last modfied: Mon Apr 11 16:08:44 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_version */
-
-/* Register r_version, scope iop_version, type r */
-typedef struct {
- unsigned int nr : 8;
- unsigned int dummy1 : 24;
-} reg_iop_version_r_version;
-#define REG_RD_ADDR_iop_version_r_version 0
-
-
-/* Constants */
-enum {
- regk_iop_version_v1_0 = 0x00000001
-};
-#endif /* __iop_version_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h b/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h
deleted file mode 100644
index 63b20dee2fd1..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __irq_nmi_defs_h
-#define __irq_nmi_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/irq_nmi.r
- * id: <not found>
- * last modfied: Thu Jan 22 09:22:43 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r
- * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope irq_nmi */
-
-/* Register rw_cmd, scope irq_nmi, type rw */
-typedef struct {
- unsigned int delay : 16;
- unsigned int op : 2;
- unsigned int dummy1 : 14;
-} reg_irq_nmi_rw_cmd;
-#define REG_RD_ADDR_irq_nmi_rw_cmd 0
-#define REG_WR_ADDR_irq_nmi_rw_cmd 0
-
-
-/* Constants */
-enum {
- regk_irq_nmi_ack_irq = 0x00000002,
- regk_irq_nmi_ack_nmi = 0x00000003,
- regk_irq_nmi_irq = 0x00000000,
- regk_irq_nmi_nmi = 0x00000001
-};
-#endif /* __irq_nmi_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h
deleted file mode 100644
index da29a8a22250..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Fri Nov 7 15:36:04 2003
- *
- * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_break_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_addr;
-#define REG_RD_ADDR_marb_bp_r_break_addr 20
-
-/* Register r_break_op, scope marb_bp, type r */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_break_op;
-#define REG_RD_ADDR_marb_bp_r_break_op 24
-
-/* Register r_break_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_clients;
-#define REG_RD_ADDR_marb_bp_r_break_clients 28
-
-/* Register r_break_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_first_client;
-#define REG_RD_ADDR_marb_bp_r_break_first_client 32
-
-/* Register r_break_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_size;
-#define REG_RD_ADDR_marb_bp_r_break_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h
deleted file mode 100644
index 2858de48a5e0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_defs_h
-#define __marb_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb */
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_int_slots;
-#define REG_RD_ADDR_marb_rw_int_slots 0
-#define REG_WR_ADDR_marb_rw_int_slots 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ext_slots;
-#define REG_RD_ADDR_marb_rw_ext_slots 256
-#define REG_WR_ADDR_marb_rw_ext_slots 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_regs_slots;
-#define REG_RD_ADDR_marb_rw_regs_slots 512
-#define REG_WR_ADDR_marb_rw_regs_slots 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_intr_mask;
-#define REG_RD_ADDR_marb_rw_intr_mask 528
-#define REG_WR_ADDR_marb_rw_intr_mask 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ack_intr;
-#define REG_RD_ADDR_marb_rw_ack_intr 532
-#define REG_WR_ADDR_marb_rw_ack_intr 532
-
-/* Register r_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_intr;
-#define REG_RD_ADDR_marb_r_intr 536
-
-/* Register r_masked_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_masked_intr;
-#define REG_RD_ADDR_marb_r_masked_intr 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_stop_mask;
-#define REG_RD_ADDR_marb_rw_stop_mask 544
-#define REG_WR_ADDR_marb_rw_stop_mask 544
-
-/* Register r_stopped, scope marb, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_r_stopped;
-#define REG_RD_ADDR_marb_r_stopped 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_no_snoop;
-#define REG_RD_ADDR_marb_rw_no_snoop 832
-#define REG_WR_ADDR_marb_rw_no_snoop 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-typedef struct {
- unsigned int dummy1 : 10;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int dummy2 : 20;
-} reg_marb_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
-#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
-
-
-/* Constants */
-enum {
- regk_marb_cpud = 0x0000000b,
- regk_marb_cpui = 0x0000000a,
- regk_marb_dma0 = 0x00000000,
- regk_marb_dma1 = 0x00000001,
- regk_marb_dma2 = 0x00000002,
- regk_marb_dma3 = 0x00000003,
- regk_marb_dma4 = 0x00000004,
- regk_marb_dma5 = 0x00000005,
- regk_marb_dma6 = 0x00000006,
- regk_marb_dma7 = 0x00000007,
- regk_marb_dma8 = 0x00000008,
- regk_marb_dma9 = 0x00000009,
- regk_marb_iop = 0x0000000c,
- regk_marb_no = 0x00000000,
- regk_marb_r_stopped_default = 0x00000000,
- regk_marb_rw_ext_slots_default = 0x00000000,
- regk_marb_rw_ext_slots_size = 0x00000040,
- regk_marb_rw_int_slots_default = 0x00000000,
- regk_marb_rw_int_slots_size = 0x00000040,
- regk_marb_rw_intr_mask_default = 0x00000000,
- regk_marb_rw_no_snoop_default = 0x00000000,
- regk_marb_rw_no_snoop_rq_default = 0x00000000,
- regk_marb_rw_regs_slots_default = 0x00000000,
- regk_marb_rw_regs_slots_size = 0x00000004,
- regk_marb_rw_stop_mask_default = 0x00000000,
- regk_marb_slave = 0x0000000d,
- regk_marb_yes = 0x00000001
-};
-#endif /* __marb_defs_h */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h b/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h
deleted file mode 100644
index 8fabdd211507..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Read/write register macros used by *_defs.h
- */
-
-#ifndef reg_rdwr_h
-#define reg_rdwr_h
-
-#ifndef REG_READ
-#define REG_READ(type, addr) (*((volatile type *) (addr)))
-#endif
-
-#ifndef REG_WRITE
-#define REG_WRITE(type, addr, val) \
- do { *((volatile type *) (addr)) = (val); } while(0)
-#endif
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h b/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h
deleted file mode 100644
index ebb6bbc6e778..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __rt_trace_defs_h
-#define __rt_trace_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/rt_trace/rtl/rt_regs.r
- * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
- * last modfied: Mon Apr 11 16:09:14 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
- * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope rt_trace */
-
-/* Register rw_cfg, scope rt_trace, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int mode : 1;
- unsigned int owner : 1;
- unsigned int wp : 1;
- unsigned int stall : 1;
- unsigned int dummy1 : 3;
- unsigned int wp_start : 7;
- unsigned int dummy2 : 1;
- unsigned int wp_stop : 7;
- unsigned int dummy3 : 9;
-} reg_rt_trace_rw_cfg;
-#define REG_RD_ADDR_rt_trace_rw_cfg 0
-#define REG_WR_ADDR_rt_trace_rw_cfg 0
-
-/* Register rw_tap_ctrl, scope rt_trace, type rw */
-typedef struct {
- unsigned int ack_data : 1;
- unsigned int ack_guru : 1;
- unsigned int dummy1 : 30;
-} reg_rt_trace_rw_tap_ctrl;
-#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
-#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
-
-/* Register r_tap_stat, scope rt_trace, type r */
-typedef struct {
- unsigned int dav : 1;
- unsigned int empty : 1;
- unsigned int dummy1 : 30;
-} reg_rt_trace_r_tap_stat;
-#define REG_RD_ADDR_rt_trace_r_tap_stat 8
-
-/* Register rw_tap_data, scope rt_trace, type rw */
-typedef unsigned int reg_rt_trace_rw_tap_data;
-#define REG_RD_ADDR_rt_trace_rw_tap_data 12
-#define REG_WR_ADDR_rt_trace_rw_tap_data 12
-
-/* Register rw_tap_hdata, scope rt_trace, type rw */
-typedef struct {
- unsigned int op : 4;
- unsigned int sub_op : 4;
- unsigned int dummy1 : 24;
-} reg_rt_trace_rw_tap_hdata;
-#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
-#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
-
-/* Register r_redir, scope rt_trace, type r */
-typedef unsigned int reg_rt_trace_r_redir;
-#define REG_RD_ADDR_rt_trace_r_redir 20
-
-
-/* Constants */
-enum {
- regk_rt_trace_brk = 0x0000000c,
- regk_rt_trace_dbg = 0x00000003,
- regk_rt_trace_dbgdi = 0x00000004,
- regk_rt_trace_dbgdo = 0x00000005,
- regk_rt_trace_gmode = 0x00000000,
- regk_rt_trace_no = 0x00000000,
- regk_rt_trace_nop = 0x00000000,
- regk_rt_trace_normal = 0x00000000,
- regk_rt_trace_rdmem = 0x00000007,
- regk_rt_trace_rdmemb = 0x00000009,
- regk_rt_trace_rdpreg = 0x00000002,
- regk_rt_trace_rdreg = 0x00000001,
- regk_rt_trace_rdsreg = 0x00000003,
- regk_rt_trace_redir = 0x00000006,
- regk_rt_trace_ret = 0x0000000b,
- regk_rt_trace_rw_cfg_default = 0x00000000,
- regk_rt_trace_trcfg = 0x00000001,
- regk_rt_trace_wp = 0x00000001,
- regk_rt_trace_wp0 = 0x00000001,
- regk_rt_trace_wp1 = 0x00000002,
- regk_rt_trace_wp2 = 0x00000004,
- regk_rt_trace_wp3 = 0x00000008,
- regk_rt_trace_wp4 = 0x00000010,
- regk_rt_trace_wp5 = 0x00000020,
- regk_rt_trace_wp6 = 0x00000040,
- regk_rt_trace_wrmem = 0x00000008,
- regk_rt_trace_wrmemb = 0x0000000a,
- regk_rt_trace_wrpreg = 0x00000005,
- regk_rt_trace_wrreg = 0x00000004,
- regk_rt_trace_wrsreg = 0x00000006,
- regk_rt_trace_yes = 0x00000001
-};
-#endif /* __rt_trace_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h
deleted file mode 100644
index 3b04cf9012cf..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ser_defs_h
-#define __ser_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ser/rtl/ser_regs.r
- * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
- * last modfied: Mon Apr 11 16:09:21 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
- * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ser */
-
-/* Register rw_tr_ctrl, scope ser, type rw */
-typedef struct {
- unsigned int base_freq : 3;
- unsigned int en : 1;
- unsigned int par : 2;
- unsigned int par_en : 1;
- unsigned int data_bits : 1;
- unsigned int stop_bits : 1;
- unsigned int stop : 1;
- unsigned int rts_delay : 3;
- unsigned int rts_setup : 1;
- unsigned int auto_rts : 1;
- unsigned int txd : 1;
- unsigned int auto_cts : 1;
- unsigned int dummy1 : 15;
-} reg_ser_rw_tr_ctrl;
-#define REG_RD_ADDR_ser_rw_tr_ctrl 0
-#define REG_WR_ADDR_ser_rw_tr_ctrl 0
-
-/* Register rw_tr_dma_en, scope ser, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_ser_rw_tr_dma_en;
-#define REG_RD_ADDR_ser_rw_tr_dma_en 4
-#define REG_WR_ADDR_ser_rw_tr_dma_en 4
-
-/* Register rw_rec_ctrl, scope ser, type rw */
-typedef struct {
- unsigned int base_freq : 3;
- unsigned int en : 1;
- unsigned int par : 2;
- unsigned int par_en : 1;
- unsigned int data_bits : 1;
- unsigned int dma_mode : 1;
- unsigned int dma_err : 1;
- unsigned int sampling : 1;
- unsigned int timeout : 3;
- unsigned int auto_eop : 1;
- unsigned int half_duplex : 1;
- unsigned int rts_n : 1;
- unsigned int loopback : 1;
- unsigned int dummy1 : 14;
-} reg_ser_rw_rec_ctrl;
-#define REG_RD_ADDR_ser_rw_rec_ctrl 8
-#define REG_WR_ADDR_ser_rw_rec_ctrl 8
-
-/* Register rw_tr_baud_div, scope ser, type rw */
-typedef struct {
- unsigned int div : 16;
- unsigned int dummy1 : 16;
-} reg_ser_rw_tr_baud_div;
-#define REG_RD_ADDR_ser_rw_tr_baud_div 12
-#define REG_WR_ADDR_ser_rw_tr_baud_div 12
-
-/* Register rw_rec_baud_div, scope ser, type rw */
-typedef struct {
- unsigned int div : 16;
- unsigned int dummy1 : 16;
-} reg_ser_rw_rec_baud_div;
-#define REG_RD_ADDR_ser_rw_rec_baud_div 16
-#define REG_WR_ADDR_ser_rw_rec_baud_div 16
-
-/* Register rw_xoff, scope ser, type rw */
-typedef struct {
- unsigned int chr : 8;
- unsigned int automatic : 1;
- unsigned int dummy1 : 23;
-} reg_ser_rw_xoff;
-#define REG_RD_ADDR_ser_rw_xoff 20
-#define REG_WR_ADDR_ser_rw_xoff 20
-
-/* Register rw_xoff_clr, scope ser, type rw */
-typedef struct {
- unsigned int clr : 1;
- unsigned int dummy1 : 31;
-} reg_ser_rw_xoff_clr;
-#define REG_RD_ADDR_ser_rw_xoff_clr 24
-#define REG_WR_ADDR_ser_rw_xoff_clr 24
-
-/* Register rw_dout, scope ser, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_ser_rw_dout;
-#define REG_RD_ADDR_ser_rw_dout 28
-#define REG_WR_ADDR_ser_rw_dout 28
-
-/* Register rs_stat_din, scope ser, type rs */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 8;
- unsigned int dav : 1;
- unsigned int framing_err : 1;
- unsigned int par_err : 1;
- unsigned int orun : 1;
- unsigned int rec_err : 1;
- unsigned int rxd : 1;
- unsigned int tr_idle : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_rdy : 1;
- unsigned int cts_n : 1;
- unsigned int xoff_detect : 1;
- unsigned int rts_n : 1;
- unsigned int txd : 1;
- unsigned int dummy2 : 3;
-} reg_ser_rs_stat_din;
-#define REG_RD_ADDR_ser_rs_stat_din 32
-
-/* Register r_stat_din, scope ser, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 8;
- unsigned int dav : 1;
- unsigned int framing_err : 1;
- unsigned int par_err : 1;
- unsigned int orun : 1;
- unsigned int rec_err : 1;
- unsigned int rxd : 1;
- unsigned int tr_idle : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_rdy : 1;
- unsigned int cts_n : 1;
- unsigned int xoff_detect : 1;
- unsigned int rts_n : 1;
- unsigned int txd : 1;
- unsigned int dummy2 : 3;
-} reg_ser_r_stat_din;
-#define REG_RD_ADDR_ser_r_stat_din 36
-
-/* Register rw_rec_eop, scope ser, type rw */
-typedef struct {
- unsigned int set : 1;
- unsigned int dummy1 : 31;
-} reg_ser_rw_rec_eop;
-#define REG_RD_ADDR_ser_rw_rec_eop 40
-#define REG_WR_ADDR_ser_rw_rec_eop 40
-
-/* Register rw_intr_mask, scope ser, type rw */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_rw_intr_mask;
-#define REG_RD_ADDR_ser_rw_intr_mask 44
-#define REG_WR_ADDR_ser_rw_intr_mask 44
-
-/* Register rw_ack_intr, scope ser, type rw */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_rw_ack_intr;
-#define REG_RD_ADDR_ser_rw_ack_intr 48
-#define REG_WR_ADDR_ser_rw_ack_intr 48
-
-/* Register r_intr, scope ser, type r */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_r_intr;
-#define REG_RD_ADDR_ser_r_intr 52
-
-/* Register r_masked_intr, scope ser, type r */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_r_masked_intr;
-#define REG_RD_ADDR_ser_r_masked_intr 56
-
-
-/* Constants */
-enum {
- regk_ser_active = 0x00000000,
- regk_ser_bits1 = 0x00000000,
- regk_ser_bits2 = 0x00000001,
- regk_ser_bits7 = 0x00000001,
- regk_ser_bits8 = 0x00000000,
- regk_ser_del0_5 = 0x00000000,
- regk_ser_del1 = 0x00000001,
- regk_ser_del1_5 = 0x00000002,
- regk_ser_del2 = 0x00000003,
- regk_ser_del2_5 = 0x00000004,
- regk_ser_del3 = 0x00000005,
- regk_ser_del3_5 = 0x00000006,
- regk_ser_del4 = 0x00000007,
- regk_ser_even = 0x00000000,
- regk_ser_ext = 0x00000001,
- regk_ser_f100 = 0x00000007,
- regk_ser_f29_493 = 0x00000004,
- regk_ser_f32 = 0x00000005,
- regk_ser_f32_768 = 0x00000006,
- regk_ser_ignore = 0x00000001,
- regk_ser_inactive = 0x00000001,
- regk_ser_majority = 0x00000001,
- regk_ser_mark = 0x00000002,
- regk_ser_middle = 0x00000000,
- regk_ser_no = 0x00000000,
- regk_ser_odd = 0x00000001,
- regk_ser_off = 0x00000000,
- regk_ser_rw_intr_mask_default = 0x00000000,
- regk_ser_rw_rec_baud_div_default = 0x00000000,
- regk_ser_rw_rec_ctrl_default = 0x00010000,
- regk_ser_rw_tr_baud_div_default = 0x00000000,
- regk_ser_rw_tr_ctrl_default = 0x00008000,
- regk_ser_rw_tr_dma_en_default = 0x00000000,
- regk_ser_rw_xoff_default = 0x00000000,
- regk_ser_space = 0x00000003,
- regk_ser_stop = 0x00000000,
- regk_ser_yes = 0x00000001
-};
-#endif /* __ser_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h
deleted file mode 100644
index 02971f9b6558..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __sser_defs_h
-#define __sser_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/syncser/rtl/sser_regs.r
- * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
- * last modfied: Mon Apr 11 16:09:48 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
- * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope sser */
-
-/* Register rw_cfg, scope sser, type rw */
-typedef struct {
- unsigned int clk_div : 16;
- unsigned int base_freq : 3;
- unsigned int gate_clk : 1;
- unsigned int clkgate_ctrl : 1;
- unsigned int clkgate_in : 1;
- unsigned int clk_dir : 1;
- unsigned int clk_od_mode : 1;
- unsigned int out_clk_pol : 1;
- unsigned int out_clk_src : 2;
- unsigned int clk_in_sel : 1;
- unsigned int hold_pol : 1;
- unsigned int prepare : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 1;
-} reg_sser_rw_cfg;
-#define REG_RD_ADDR_sser_rw_cfg 0
-#define REG_WR_ADDR_sser_rw_cfg 0
-
-/* Register rw_frm_cfg, scope sser, type rw */
-typedef struct {
- unsigned int wordrate : 10;
- unsigned int rec_delay : 3;
- unsigned int tr_delay : 3;
- unsigned int early_wend : 1;
- unsigned int level : 2;
- unsigned int type : 1;
- unsigned int clk_pol : 1;
- unsigned int fr_in_rxclk : 1;
- unsigned int clk_src : 1;
- unsigned int out_off : 1;
- unsigned int out_on : 1;
- unsigned int frame_pin_dir : 1;
- unsigned int frame_pin_use : 2;
- unsigned int status_pin_dir : 1;
- unsigned int status_pin_use : 2;
- unsigned int dummy1 : 1;
-} reg_sser_rw_frm_cfg;
-#define REG_RD_ADDR_sser_rw_frm_cfg 4
-#define REG_WR_ADDR_sser_rw_frm_cfg 4
-
-/* Register rw_tr_cfg, scope sser, type rw */
-typedef struct {
- unsigned int tr_en : 1;
- unsigned int stop : 1;
- unsigned int urun_stop : 1;
- unsigned int eop_stop : 1;
- unsigned int sample_size : 6;
- unsigned int sh_dir : 1;
- unsigned int clk_pol : 1;
- unsigned int clk_src : 1;
- unsigned int use_dma : 1;
- unsigned int mode : 2;
- unsigned int frm_src : 1;
- unsigned int use60958 : 1;
- unsigned int iec60958_ckdiv : 2;
- unsigned int rate_ctrl : 1;
- unsigned int use_md : 1;
- unsigned int dual_i2s : 1;
- unsigned int data_pin_use : 2;
- unsigned int od_mode : 1;
- unsigned int bulk_wspace : 2;
- unsigned int dummy1 : 4;
-} reg_sser_rw_tr_cfg;
-#define REG_RD_ADDR_sser_rw_tr_cfg 8
-#define REG_WR_ADDR_sser_rw_tr_cfg 8
-
-/* Register rw_rec_cfg, scope sser, type rw */
-typedef struct {
- unsigned int rec_en : 1;
- unsigned int force_eop : 1;
- unsigned int stop : 1;
- unsigned int orun_stop : 1;
- unsigned int eop_stop : 1;
- unsigned int sample_size : 6;
- unsigned int sh_dir : 1;
- unsigned int clk_pol : 1;
- unsigned int clk_src : 1;
- unsigned int use_dma : 1;
- unsigned int mode : 2;
- unsigned int frm_src : 2;
- unsigned int use60958 : 1;
- unsigned int iec60958_ui_len : 5;
- unsigned int slave2_en : 1;
- unsigned int slave3_en : 1;
- unsigned int fifo_thr : 2;
- unsigned int dummy1 : 3;
-} reg_sser_rw_rec_cfg;
-#define REG_RD_ADDR_sser_rw_rec_cfg 12
-#define REG_WR_ADDR_sser_rw_rec_cfg 12
-
-/* Register rw_tr_data, scope sser, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int md : 1;
- unsigned int dummy1 : 15;
-} reg_sser_rw_tr_data;
-#define REG_RD_ADDR_sser_rw_tr_data 16
-#define REG_WR_ADDR_sser_rw_tr_data 16
-
-/* Register r_rec_data, scope sser, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int md : 1;
- unsigned int ext_clk : 1;
- unsigned int status_in : 1;
- unsigned int frame_in : 1;
- unsigned int din : 1;
- unsigned int data_in : 1;
- unsigned int clk_in : 1;
- unsigned int dummy1 : 9;
-} reg_sser_r_rec_data;
-#define REG_RD_ADDR_sser_r_rec_data 20
-
-/* Register rw_extra, scope sser, type rw */
-typedef struct {
- unsigned int clkoff_cycles : 20;
- unsigned int clkoff_en : 1;
- unsigned int clkon_en : 1;
- unsigned int dout_delay : 5;
- unsigned int dummy1 : 5;
-} reg_sser_rw_extra;
-#define REG_RD_ADDR_sser_rw_extra 24
-#define REG_WR_ADDR_sser_rw_extra 24
-
-/* Register rw_intr_mask, scope sser, type rw */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_rw_intr_mask;
-#define REG_RD_ADDR_sser_rw_intr_mask 28
-#define REG_WR_ADDR_sser_rw_intr_mask 28
-
-/* Register rw_ack_intr, scope sser, type rw */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_rw_ack_intr;
-#define REG_RD_ADDR_sser_rw_ack_intr 32
-#define REG_WR_ADDR_sser_rw_ack_intr 32
-
-/* Register r_intr, scope sser, type r */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_r_intr;
-#define REG_RD_ADDR_sser_r_intr 36
-
-/* Register r_masked_intr, scope sser, type r */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_r_masked_intr;
-#define REG_RD_ADDR_sser_r_masked_intr 40
-
-
-/* Constants */
-enum {
- regk_sser_both = 0x00000002,
- regk_sser_bulk = 0x00000001,
- regk_sser_clk100 = 0x00000000,
- regk_sser_clk_in = 0x00000000,
- regk_sser_const0 = 0x00000003,
- regk_sser_dout = 0x00000002,
- regk_sser_edge = 0x00000000,
- regk_sser_ext = 0x00000001,
- regk_sser_ext_clk = 0x00000001,
- regk_sser_f100 = 0x00000000,
- regk_sser_f29_493 = 0x00000004,
- regk_sser_f32 = 0x00000005,
- regk_sser_f32_768 = 0x00000006,
- regk_sser_frm = 0x00000003,
- regk_sser_gio0 = 0x00000000,
- regk_sser_gio1 = 0x00000001,
- regk_sser_hispeed = 0x00000001,
- regk_sser_hold = 0x00000002,
- regk_sser_in = 0x00000000,
- regk_sser_inf = 0x00000003,
- regk_sser_intern = 0x00000000,
- regk_sser_intern_clk = 0x00000001,
- regk_sser_intern_tb = 0x00000000,
- regk_sser_iso = 0x00000000,
- regk_sser_level = 0x00000001,
- regk_sser_lospeed = 0x00000000,
- regk_sser_lsbfirst = 0x00000000,
- regk_sser_msbfirst = 0x00000001,
- regk_sser_neg = 0x00000001,
- regk_sser_neg_lo = 0x00000000,
- regk_sser_no = 0x00000000,
- regk_sser_no_clk = 0x00000007,
- regk_sser_nojitter = 0x00000002,
- regk_sser_out = 0x00000001,
- regk_sser_pos = 0x00000000,
- regk_sser_pos_hi = 0x00000001,
- regk_sser_rec = 0x00000000,
- regk_sser_rw_cfg_default = 0x00000000,
- regk_sser_rw_extra_default = 0x00000000,
- regk_sser_rw_frm_cfg_default = 0x00000000,
- regk_sser_rw_intr_mask_default = 0x00000000,
- regk_sser_rw_rec_cfg_default = 0x00000000,
- regk_sser_rw_tr_cfg_default = 0x01800000,
- regk_sser_rw_tr_data_default = 0x00000000,
- regk_sser_thr16 = 0x00000001,
- regk_sser_thr32 = 0x00000002,
- regk_sser_thr8 = 0x00000000,
- regk_sser_tr = 0x00000001,
- regk_sser_ts_out = 0x00000003,
- regk_sser_tx_bulk = 0x00000002,
- regk_sser_wiresave = 0x00000002,
- regk_sser_yes = 0x00000001
-};
-#endif /* __sser_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop.h b/arch/cris/include/arch-v32/arch/hwregs/strcop.h
deleted file mode 100644
index 2c522b024ee7..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/strcop.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $
-
-// Streamcop meta-data configuration structs
-
-struct strcop_meta_out {
- unsigned char csumsel : 3;
- unsigned char ciphsel : 3;
- unsigned char ciphconf : 2;
- unsigned char hashsel : 3;
- unsigned char hashconf : 1;
- unsigned char hashmode : 1;
- unsigned char decrypt : 1;
- unsigned char dlkey : 1;
- unsigned char cbcmode : 1;
-};
-
-struct strcop_meta_in {
- unsigned char dmasel : 3;
- unsigned char sync : 1;
- unsigned char res1 : 5;
- unsigned char res2;
-};
-
-// Source definitions
-
-enum {
- src_none = 0,
- src_dma = 1,
- src_des = 2,
- src_sha1 = 3,
- src_csum = 4,
- src_aes = 5,
- src_md5 = 6,
- src_res = 7
-};
-
-// Cipher definitions
-
-enum {
- ciph_des = 0,
- ciph_3des = 1,
- ciph_aes = 2
-};
-
-// Hash definitions
-
-enum {
- hash_sha1 = 0,
- hash_md5 = 1
-};
-
-enum {
- hash_noiv = 0,
- hash_iv = 1
-};
-
-
diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h b/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h
deleted file mode 100644
index 069b2ed9def5..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strcop_defs_h
-#define __strcop_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strcop/rtl/strcop_regs.r
- * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
- * last modfied: Mon Apr 11 16:09:38 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
- * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strcop */
-
-/* Register rw_cfg, scope strcop, type rw */
-typedef struct {
- unsigned int td3 : 1;
- unsigned int td2 : 1;
- unsigned int td1 : 1;
- unsigned int ipend : 1;
- unsigned int ignore_sync : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 26;
-} reg_strcop_rw_cfg;
-#define REG_RD_ADDR_strcop_rw_cfg 0
-#define REG_WR_ADDR_strcop_rw_cfg 0
-
-
-/* Constants */
-enum {
- regk_strcop_big = 0x00000001,
- regk_strcop_d = 0x00000001,
- regk_strcop_e = 0x00000000,
- regk_strcop_little = 0x00000000,
- regk_strcop_rw_cfg_default = 0x00000002
-};
-#endif /* __strcop_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h
deleted file mode 100644
index c3fa0c06c558..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SUPP_REG_H__
-#define __SUPP_REG_H__
-
-/* Macros for reading and writing support/special registers. */
-
-#ifndef STRINGIFYFY
-#define STRINGIFYFY(i) #i
-#endif
-
-#ifndef STRINGIFY
-#define STRINGIFY(i) STRINGIFYFY(i)
-#endif
-
-#define SPEC_REG_BZ "BZ"
-#define SPEC_REG_VR "VR"
-#define SPEC_REG_PID "PID"
-#define SPEC_REG_SRS "SRS"
-#define SPEC_REG_WZ "WZ"
-#define SPEC_REG_EXS "EXS"
-#define SPEC_REG_EDA "EDA"
-#define SPEC_REG_MOF "MOF"
-#define SPEC_REG_DZ "DZ"
-#define SPEC_REG_EBP "EBP"
-#define SPEC_REG_ERP "ERP"
-#define SPEC_REG_SRP "SRP"
-#define SPEC_REG_NRP "NRP"
-#define SPEC_REG_CCS "CCS"
-#define SPEC_REG_USP "USP"
-#define SPEC_REG_SPC "SPC"
-
-#define RW_MM_CFG 0
-#define RW_MM_KBASE_LO 1
-#define RW_MM_KBASE_HI 2
-#define RW_MM_CAUSE 3
-#define RW_MM_TLB_SEL 4
-#define RW_MM_TLB_LO 5
-#define RW_MM_TLB_HI 6
-#define RW_MM_TLB_PGD 7
-
-#define BANK_GC 0
-#define BANK_IM 1
-#define BANK_DM 2
-#define BANK_BP 3
-
-#define RW_GC_CFG 0
-#define RW_GC_CCS 1
-#define RW_GC_SRS 2
-#define RW_GC_NRP 3
-#define RW_GC_EXS 4
-#define RW_GC_R0 8
-#define RW_GC_R1 9
-
-#define SPEC_REG_WR(r,v) \
-__asm__ __volatile__ ("move %0, $" r : : "r" (v));
-
-#define SPEC_REG_RD(r,v) \
-__asm__ __volatile__ ("move $" r ",%0" : "=r" (v));
-
-#define NOP() \
- __asm__ __volatile__ ("nop");
-
-#define SUPP_BANK_SEL(b) \
- SPEC_REG_WR(SPEC_REG_SRS,b); \
- NOP(); \
- NOP(); \
- NOP();
-
-#define SUPP_REG_WR(r,v) \
-__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- : : "r" (v));
-
-#define SUPP_REG_RD(r,v) \
-__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v));
-
-#endif /* __SUPP_REG_H__ */
diff --git a/arch/cris/include/arch-v32/arch/intmem.h b/arch/cris/include/arch-v32/arch/intmem.h
deleted file mode 100644
index 2bcb21c9b25f..000000000000
--- a/arch/cris/include/arch-v32/arch/intmem.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_INTMEM_H
-#define _ASM_CRIS_INTMEM_H
-
-void* crisv32_intmem_alloc(unsigned size, unsigned align);
-void crisv32_intmem_free(void* addr);
-void* crisv32_intmem_phys_to_virt(unsigned long addr);
-unsigned long crisv32_intmem_virt_to_phys(void *addr);
-
-#endif /* _ASM_CRIS_ARCH_INTMEM_H */
diff --git a/arch/cris/include/arch-v32/arch/irq.h b/arch/cris/include/arch-v32/arch/irq.h
deleted file mode 100644
index 5259084001d4..000000000000
--- a/arch/cris/include/arch-v32/arch/irq.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_IRQ_H
-#define _ASM_ARCH_IRQ_H
-
-#include <hwregs/intr_vect.h>
-
-/* Number of non-cpu interrupts. */
-#define NR_IRQS (NBR_INTR_VECT + 256) /* Exceptions + IRQs */
-#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
-#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
-#if NR_REAL_IRQS > 32
-#define MACH_IRQS 64
-#else
-#define MACH_IRQS 32
-#endif
-
-#ifndef __ASSEMBLY__
-/* Global IRQ vector. */
-typedef void (*irqvectptr)(void);
-
-struct etrax_interrupt_vector {
- irqvectptr v[256];
-};
-
-extern struct etrax_interrupt_vector *etrax_irv; /* head.S */
-
-void crisv32_mask_irq(int irq);
-void crisv32_unmask_irq(int irq);
-
-void set_exception_vector(int n, irqvectptr addr);
-
-/* Save registers so that they match pt_regs. */
-#define SAVE_ALL \
- "subq 12,$sp\n\t" \
- "move $erp,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $srp,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $ccs,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $spc,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $mof,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $srs,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move.d $acr,[$sp]\n\t" \
- "subq 14*4,$sp\n\t" \
- "movem $r13,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move.d $r10,[$sp]\n"
-
-#define STR2(x) #x
-#define STR(x) STR2(x)
-
-#define IRQ_NAME2(nr) nr##_interrupt(void)
-#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
-
-/*
- * The reason for setting the S-bit when debugging the kernel is that we want
- * hardware breakpoints to remain active while we are in an exception handler.
- * Note that we cannot simply copy S1, since we may come here from user-space,
- * or any context where the S-bit wasn't set.
- */
-#ifdef CONFIG_ETRAX_KGDB
-#define KGDB_FIXUP \
- "move $ccs, $r10\n\t" \
- "or.d (1<<9), $r10\n\t" \
- "move $r10, $ccs\n\t"
-#else
-#define KGDB_FIXUP ""
-#endif
-
-/*
- * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
- * and jump to ret_from_intr which is found in entry.S.
- *
- * The reason for blocking the IRQ is to allow an sti() before the handler,
- * which will acknowledge the interrupt, is run. The actual blocking is made
- * by crisv32_do_IRQ.
- */
-#define BUILD_IRQ(nr) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- KGDB_FIXUP \
- "move.d "#nr",$r10\n\t" \
- "move.d $sp, $r12\n\t" \
- "jsr crisv32_do_IRQ\n\t" \
- "moveq 1, $r11\n\t" \
- "jump ret_from_intr\n\t" \
- "nop\n\t");
-/*
- * This is subtle. The timer interrupt is crucial and it should not be disabled
- * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
- * would have been BLOCK'ed, and then softirq's are run before we return here to
- * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
- * and the watchdog will kill us.
- *
- * Furthermore, if a lot of other irq's occur before we return here, the
- * multiple_irq handler is run and it prioritizes the timer interrupt. However
- * if we had BLOCK'edit here, we would not get the multiple_irq at all.
- *
- * The non-blocking here is based on the knowledge that the timer interrupt runs
- * with interrupts disabled, and therefore there will not be an sti() before the
- * timer irq handler is run to acknowledge the interrupt.
- */
-#define BUILD_TIMER_IRQ(nr, mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- KGDB_FIXUP \
- "move.d "#nr",$r10\n\t" \
- "move.d $sp,$r12\n\t" \
- "jsr crisv32_do_IRQ\n\t" \
- "moveq 0,$r11\n\t" \
- "jump ret_from_intr\n\t" \
- "nop\n\t");
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_ARCH_IRQ_H */
diff --git a/arch/cris/include/arch-v32/arch/irqflags.h b/arch/cris/include/arch-v32/arch/irqflags.h
deleted file mode 100644
index d55bf82de77c..000000000000
--- a/arch/cris/include/arch-v32/arch/irqflags.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
-#define __ASM_CRIS_ARCH_IRQFLAGS_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
- asm volatile("move $ccs,%0" : "=rm" (flags) : : "memory");
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
- asm volatile("di" : : : "memory");
-}
-
-static inline void arch_local_irq_enable(void)
-{
- asm volatile("ei" : : : "memory");
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("move %0,$ccs" : : "rm" (flags) : "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & (1 << I_CCS_BITNR));
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */
diff --git a/arch/cris/include/arch-v32/arch/memmap.h b/arch/cris/include/arch-v32/arch/memmap.h
deleted file mode 100644
index 81985c0a6789..000000000000
--- a/arch/cris/include/arch-v32/arch/memmap.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach/memmap.h>
diff --git a/arch/cris/include/arch-v32/arch/mmu.h b/arch/cris/include/arch-v32/arch/mmu.h
deleted file mode 100644
index a8eec1312de0..000000000000
--- a/arch/cris/include/arch-v32/arch/mmu.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_MMU_H
-#define _ASM_CRIS_ARCH_MMU_H
-
-/* MMU context type. */
-typedef struct
-{
- unsigned int page_id;
-} mm_context_t;
-
-/* Kernel memory segments. */
-#define KSEG_F 0xf0000000UL
-#define KSEG_E 0xe0000000UL
-#define KSEG_D 0xd0000000UL
-#define KSEG_C 0xc0000000UL
-#define KSEG_B 0xb0000000UL
-#define KSEG_A 0xa0000000UL
-#define KSEG_9 0x90000000UL
-#define KSEG_8 0x80000000UL
-#define KSEG_7 0x70000000UL
-#define KSEG_6 0x60000000UL
-#define KSEG_5 0x50000000UL
-#define KSEG_4 0x40000000UL
-#define KSEG_3 0x30000000UL
-#define KSEG_2 0x20000000UL
-#define KSEG_1 0x10000000UL
-#define KSEG_0 0x00000000UL
-
-/*
- * CRISv32 PTE bits:
- *
- * Bit: 31 30-13 12-5 4 3 2 1 0
- * +-------+-----+------+--------+-------+--------+-------+---------+
- * | cache | pfn | zero | global | valid | kernel | write | execute |
- * +-------+-----+------+--------+-------+--------+-------+---------+
- */
-
-/*
- * Defines for accessing the bits. Also define some synonyms for use with
- * the software-based defined bits below.
- */
-#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */
-#define _PAGE_WE (1 << 1) /* Write bit. */
-#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */
-#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */
-#define _PAGE_VALID (1 << 3) /* Page is valid. */
-#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */
-#define _PAGE_GLOBAL (1 << 4) /* Global page. */
-#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */
-
-
-/*
- * The hardware doesn't care about these bits, but the kernel uses them in
- * software.
- */
-#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */
-#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */
-#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */
-#define _PAGE_READ (1 << 8) /* Read enabled. */
-#define _PAGE_WRITE (1 << 9) /* Write enabled. */
-
-/* Define some higher level generic page attributes. */
-#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
-
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
- _PAGE_ACCESSED)
-#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
- _PAGE_ACCESSED | _PAGE_EXECUTE)
-
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED)
-
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE)
-#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
- _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \
- _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \
- _PAGE_PRESENT | __READABLE)
-
-#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
-
-/* CRISv32 can do page protection for execute.
- * Write permissions imply read permissions.
- * Note that the numbers are in Execute-Write-Read order!
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY_EXEC
-#define __P101 PAGE_READONLY_EXEC
-#define __P110 PAGE_COPY_EXEC
-#define __P111 PAGE_COPY_EXEC
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY_EXEC
-#define __S101 PAGE_READONLY_EXEC
-#define __S110 PAGE_SHARED_EXEC
-#define __S111 PAGE_SHARED_EXEC
-
-#endif /* _ASM_CRIS_ARCH_MMU_H */
diff --git a/arch/cris/include/arch-v32/arch/offset.h b/arch/cris/include/arch-v32/arch/offset.h
deleted file mode 100644
index 10a670443386..000000000000
--- a/arch/cris/include/arch-v32/arch/offset.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/cris/Makefile
- *
- */
-
-#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */
-#define PT_r13 56 /* offsetof(struct pt_regs, r13) */
-#define PT_r12 52 /* offsetof(struct pt_regs, r12) */
-#define PT_r11 48 /* offsetof(struct pt_regs, r11) */
-#define PT_r10 44 /* offsetof(struct pt_regs, r10) */
-#define PT_r9 40 /* offsetof(struct pt_regs, r9) */
-#define PT_acr 60 /* offsetof(struct pt_regs, acr) */
-#define PT_srs 64 /* offsetof(struct pt_regs, srs) */
-#define PT_mof 68 /* offsetof(struct pt_regs, mof) */
-#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */
-#define PT_srp 80 /* offsetof(struct pt_regs, srp) */
-
-#define TI_task 0 /* offsetof(struct thread_info, task) */
-#define TI_flags 8 /* offsetof(struct thread_info, flags) */
-#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
-
-#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
-
-#define TASK_pid 151 /* offsetof(struct task_struct, pid) */
-
-#define LCLONE_VM 256 /* CLONE_VM */
-#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/page.h b/arch/cris/include/arch-v32/arch/page.h
deleted file mode 100644
index 7ac04f615193..000000000000
--- a/arch/cris/include/arch-v32/arch/page.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PAGE_H
-#define _ASM_CRIS_ARCH_PAGE_H
-
-
-#ifdef __KERNEL__
-
-#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */
-
-/*
- * Macros to convert between physical and virtual addresses. By stripping a
- * selected bit it's possible to convert between KSEG_x and 0x40000000 where the
- * DRAM really resides. DRAM is virtually at 0xc.
- */
-#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
-
-#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
- VM_MAYREAD | VM_MAYWRITE)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_CRIS_ARCH_PAGE_H */
diff --git a/arch/cris/include/arch-v32/arch/pgtable.h b/arch/cris/include/arch-v32/arch/pgtable.h
deleted file mode 100644
index e787b19b700e..000000000000
--- a/arch/cris/include/arch-v32/arch/pgtable.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PGTABLE_H
-#define _ASM_CRIS_ARCH_PGTABLE_H
-
-/* Define the kernels virtual memory area. */
-
-/* See head.S for differences between ARTPEC-3 and ETRAX FS. */
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#define VMALLOC_START KSEG_E
-#define VMALLOC_END KSEG_F
-#else
-#define VMALLOC_START KSEG_D
-#define VMALLOC_END KSEG_E
-#endif
-
-#define VMALLOC_VMADDR(x) ((unsigned long)(x))
-
-#endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/arch/cris/include/arch-v32/arch/processor.h b/arch/cris/include/arch-v32/arch/processor.h
deleted file mode 100644
index 554088ab5f01..000000000000
--- a/arch/cris/include/arch-v32/arch/processor.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PROCESSOR_H
-#define _ASM_CRIS_ARCH_PROCESSOR_H
-
-
-/* Return current instruction pointer. */
-#define current_text_addr() \
- ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;})
-
-/*
- * Since CRIS doesn't do hardware task-switching this hasn't really anything to
- * do with the proccessor itself, it's just here for legacy reasons. This is
- * used when task-switching using _resume defined in entry.S. The offsets here
- * are hardcoded into _resume, so if this struct is changed, entry.S needs to be
- * changed as well.
- */
-struct thread_struct {
- unsigned long ksp; /* Kernel stack pointer. */
- unsigned long usp; /* User stack pointer. */
- unsigned long ccs; /* Saved flags register. */
-};
-
-/*
- * User-space process size. This is hardcoded into a few places, so don't
- * change it unless everything's clear!
- */
-#define TASK_SIZE (0xB0000000UL)
-
-#define INIT_THREAD { }
-
-#define KSTK_EIP(tsk) \
-({ \
- unsigned long eip = 0; \
- unsigned long regs = (unsigned long)task_pt_regs(tsk); \
- if (regs > PAGE_SIZE && virt_addr_valid(regs)) \
- eip = ((struct pt_regs *)regs)->erp; \
- eip; \
-})
-
-/*
- * Give the thread a program location, set user-mode and switch user
- * stackpointer.
- */
-#define start_thread(regs, ip, usp) \
-do { \
- regs->erp = ip; \
- regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \
- wrusp(usp); \
-} while(0)
-
-/* Nothing special to do for v32 when handling a kernel bus fault fixup. */
-#define arch_fixup(regs) {};
-
-#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */
diff --git a/arch/cris/include/arch-v32/arch/swab.h b/arch/cris/include/arch-v32/arch/swab.h
deleted file mode 100644
index 280dd7093e4f..000000000000
--- a/arch/cris/include/arch-v32/arch/swab.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_SWAB_H
-#define _ASM_CRIS_ARCH_SWAB_H
-
-#include <asm/types.h>
-
-#define __SWAB_64_THRU_32__
-
-static inline __const__ __u32
-__arch_swab32(__u32 x)
-{
- __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x));
- return (x);
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __const__ __u16
-__arch_swab16(__u16 x)
-{
- __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x));
- return (x);
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* _ASM_CRIS_ARCH_SWAB_H */
diff --git a/arch/cris/include/arch-v32/arch/system.h b/arch/cris/include/arch-v32/arch/system.h
deleted file mode 100644
index 84f00e5d4652..000000000000
--- a/arch/cris/include/arch-v32/arch/system.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_SYSTEM_H
-#define _ASM_CRIS_ARCH_SYSTEM_H
-
-
-/* Read the CPU version register. */
-static inline unsigned long rdvr(void)
-{
- unsigned char vr;
-
- __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr));
- return vr;
-}
-
-#define cris_machine_name "crisv32"
-
-/* Read the user-mode stack pointer. */
-static inline unsigned long rdusp(void)
-{
- unsigned long usp;
-
- __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp));
- return usp;
-}
-
-/* Read the current stack pointer. */
-static inline unsigned long rdsp(void)
-{
- unsigned long sp;
-
- __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp));
- return sp;
-}
-
-/* Write the user-mode stack pointer. */
-#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp))
-
-#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
diff --git a/arch/cris/include/arch-v32/arch/thread_info.h b/arch/cris/include/arch-v32/arch/thread_info.h
deleted file mode 100644
index 8514669e5fab..000000000000
--- a/arch/cris/include/arch-v32/arch/thread_info.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H
-#define _ASM_CRIS_ARCH_THREAD_INFO_H
-
-/* Return a thread_info struct. */
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
-
- __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL));
- return ti;
-}
-
-#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */
diff --git a/arch/cris/include/arch-v32/arch/timex.h b/arch/cris/include/arch-v32/arch/timex.h
deleted file mode 100644
index 2cd8e704a73b..000000000000
--- a/arch/cris/include/arch-v32/arch/timex.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_TIMEX_H
-#define _ASM_CRIS_ARCH_TIMEX_H
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-
-/*
- * The clock runs at 100MHz, we divide it by 1000000. If you change anything
- * here you must check time.c as well.
- */
-
-#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */
-
-/* The timer0 values gives 10 ns resolution but interrupts at HZ. */
-#define TIMER0_FREQ (CLOCK_TICK_RATE)
-#define TIMER0_DIV (TIMER0_FREQ/(HZ))
-
-/* Convert the value in step of 10 ns to 1us without overflow: */
-#define GET_JIFFIES_USEC() \
- ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100)
-
-extern unsigned long get_ns_in_jiffie(void);
-
-static inline unsigned long get_us_in_jiffie_highres(void)
-{
- return get_ns_in_jiffie() / 1000;
-}
-
-#endif
-
diff --git a/arch/cris/include/arch-v32/arch/tlb.h b/arch/cris/include/arch-v32/arch/tlb.h
deleted file mode 100644
index 50452802738f..000000000000
--- a/arch/cris/include/arch-v32/arch/tlb.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_TLB_H
-#define _CRIS_ARCH_TLB_H
-
-/*
- * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
- * to store the "process" it belongs to (=> fast mm context switch). The
- * last page_id is never used so we can make TLB entries that never matches.
- */
-#define NUM_TLB_ENTRIES 64
-#define NUM_PAGEID 256
-#define INVALID_PAGEID 255
-#define NO_CONTEXT -1
-
-#endif /* _CRIS_ARCH_TLB_H */
diff --git a/arch/cris/include/arch-v32/arch/uaccess.h b/arch/cris/include/arch-v32/arch/uaccess.h
deleted file mode 100644
index 214bd26efcd9..000000000000
--- a/arch/cris/include/arch-v32/arch/uaccess.h
+++ /dev/null
@@ -1,730 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Authors: Hans-Peter Nilsson (hp@axis.com)
- *
- */
-#ifndef _CRIS_ARCH_UACCESS_H
-#define _CRIS_ARCH_UACCESS_H
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- *
- * Note that PC at a fault is the address *at* the faulting
- * instruction for CRISv32.
- */
-#define __put_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- "2: "op" %1,[%2]\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 4b\n" \
- " nop\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err) \
- : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __put_user_asm_64(x, addr, err) do { \
- int dummy_for_put_user_asm_64_; \
- __asm__ __volatile__( \
- "2: move.d %M2,[%1+]\n" \
- "4: move.d %H2,[%1]\n" \
- "5:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %4,%0\n" \
- " jump 5b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \
- : "r" (x), "1" (addr), "g" (-EFAULT), \
- "0" (err)); \
- } while (0)
-
-/* See comment before __put_user_asm. */
-
-#define __get_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- "2: "op" [%2],%1\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 4b\n" \
- " moveq 0,%1\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x) \
- : "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __get_user_asm_64(x, addr, err) do { \
- int dummy_for_get_user_asm_64_; \
- __asm__ __volatile__( \
- "2: move.d [%2+],%M1\n" \
- "4: move.d [%2],%H1\n" \
- "5:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %4,%0\n" \
- " jump 5b\n" \
- " moveq 0,%1\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x), \
- "=b" (dummy_for_get_user_asm_64_) \
- : "2" (addr), "g" (-EFAULT), "0" (err));\
- } while (0)
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT for an exception
- * count if we hit the buffer limit
- * bytes copied if we hit a null byte
- * (without the null byte)
- */
-static inline long
-__do_strncpy_from_user(char *dst, const char *src, long count)
-{
- long res;
-
- if (count == 0)
- return 0;
-
- /*
- * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
- * So do we.
- *
- * This code is deduced from:
- *
- * char tmp2;
- * long tmp1, tmp3;
- * tmp1 = count;
- * while ((*dst++ = (tmp2 = *src++)) != 0
- * && --tmp1)
- * ;
- *
- * res = count - tmp1;
- *
- * with tweaks.
- */
-
- __asm__ __volatile__ (
- " move.d %3,%0\n"
- "5: move.b [%2+],$acr\n"
- "1: beq 6f\n"
- " move.b $acr,[%1+]\n"
-
- " subq 1,%0\n"
- "2: bne 1b\n"
- " move.b [%2+],$acr\n"
-
- "6: sub.d %3,%0\n"
- " neg.d %0,%0\n"
- "3:\n"
- " .section .fixup,\"ax\"\n"
- "4: move.d %7,%0\n"
- " jump 3b\n"
- " nop\n"
-
- /* The address for a fault at the first move is trivial.
- The address for a fault at the second move is that of
- the preceding branch insn, since the move insn is in
- its delay-slot. Just so you don't get confused... */
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 5b,4b\n"
- " .dword 2b,4b\n"
- " .previous"
- : "=r" (res), "=b" (dst), "=b" (src), "=r" (count)
- : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
- : "acr");
-
- return res;
-}
-
-/* A few copy asms to build up the more complex ones from.
-
- Note again, a post-increment is performed regardless of whether a bus
- fault occurred in that instruction, and PC for a faulted insn is the
- address for the insn, or for the preceding branch when in a delay-slot. */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- COPY \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous\n" \
- : "=b" (to), "=b" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "acr", "memory")
-
-#define __asm_copy_from_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- "2: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "3: addq 1,%2\n" \
- " jump 1b\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- "2: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "3: addq 2,%2\n" \
- " jump 1b\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_2(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, \
- "4: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- "2: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "3: addq 4,%2\n" \
- " jump 1b\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_4(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_5(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- "4: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- COPY \
- "4: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "5: addq 2,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_6(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_7(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, \
- "6: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- COPY \
- "4: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "5: addq 4,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_8(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_9(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- "6: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- COPY \
- "6: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "7: addq 2,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_10(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_11(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, \
- "8: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- COPY \
- "6: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "7: addq 4,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_12(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_13(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- "8: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- COPY \
- "8: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "9: addq 2,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_14(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_15(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, \
- "10: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- COPY \
- "8: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "9: addq 4,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_16(to, from, ret) \
- __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_16x_cont(to, from, ret, \
- COPY \
- "10: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "11: addq 4,%2\n", \
- TENTRY \
- " .dword 10b,11b\n")
-
-#define __asm_copy_from_user_20(to, from, ret) \
- __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_20x_cont(to, from, ret, \
- COPY \
- "12: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "13: addq 4,%2\n", \
- TENTRY \
- " .dword 12b,13b\n")
-
-#define __asm_copy_from_user_24(to, from, ret) \
- __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
-
-/* And now, the to-user ones. */
-
-#define __asm_copy_to_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "2: move.b $acr,[%0+]\n", \
- "3: jump 1b\n" \
- " addq 1,%2\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "2: move.w $acr,[%0+]\n", \
- FIXUP \
- "3: jump 1b\n" \
- " addq 2,%2\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_2(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "4: move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "2: move.d $acr,[%0+]\n", \
- FIXUP \
- "3: jump 1b\n" \
- " addq 4,%2\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_4(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "4: move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "4: move.w $acr,[%0+]\n", \
- FIXUP \
- "5: addq 2,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_6(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "6: move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "4: move.d $acr,[%0+]\n", \
- FIXUP \
- "5: addq 4,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_8(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "6: move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "6: move.w $acr,[%0+]\n", \
- FIXUP \
- "7: addq 2,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_10(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "8: move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "6: move.d $acr,[%0+]\n", \
- FIXUP \
- "7: addq 4,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_12(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "8: move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "8: move.w $acr,[%0+]\n", \
- FIXUP \
- "9: addq 2,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_14(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "10: move.b $acr,[%0+]\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "8: move.d $acr,[%0+]\n", \
- FIXUP \
- "9: addq 4,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_16(to, from, ret) \
- __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_16x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "10: move.d $acr,[%0+]\n", \
- FIXUP \
- "11: addq 4,%2\n", \
- TENTRY \
- " .dword 10b,11b\n")
-
-#define __asm_copy_to_user_20(to, from, ret) \
- __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_20x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "12: move.d $acr,[%0+]\n", \
- FIXUP \
- "13: addq 4,%2\n", \
- TENTRY \
- " .dword 12b,13b\n")
-
-#define __asm_copy_to_user_24(to, from, ret) \
- __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
-
-/* Define a few clearing asms with exception handlers. */
-
-/* This frame-asm is like the __asm_copy_user_cont one, but has one less
- input. */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- CLEAR \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous" \
- : "=b" (to), "=r" (ret) \
- : "0" (to), "1" (ret) \
- : "memory")
-
-#define __asm_clear_1(to, ret) \
- __asm_clear(to, ret, \
- "2: clear.b [%0+]\n", \
- "3: jump 1b\n" \
- " addq 1,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
- __asm_clear(to, ret, \
- "2: clear.w [%0+]\n", \
- "3: jump 1b\n" \
- " addq 2,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
- __asm_clear(to, ret, \
- "2: clear.w [%0+]\n" \
- "3: clear.b [%0+]\n", \
- "4: addq 2,%1\n" \
- "5: jump 1b\n" \
- " addq 1,%1\n", \
- " .dword 2b,4b\n" \
- " .dword 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear(to, ret, \
- CLEAR \
- "2: clear.d [%0+]\n", \
- FIXUP \
- "3: jump 1b\n" \
- " addq 4,%1\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_clear_4(to, ret) \
- __asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_4x_cont(to, ret, \
- CLEAR \
- "4: clear.d [%0+]\n", \
- FIXUP \
- "5: addq 4,%1\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_clear_8(to, ret) \
- __asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_8x_cont(to, ret, \
- CLEAR \
- "6: clear.d [%0+]\n", \
- FIXUP \
- "7: addq 4,%1\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_clear_12(to, ret) \
- __asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_12x_cont(to, ret, \
- CLEAR \
- "8: clear.d [%0+]\n", \
- FIXUP \
- "9: addq 4,%1\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_clear_16(to, ret) \
- __asm_clear_16x_cont(to, ret, "", "", "")
-
-#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_16x_cont(to, ret, \
- CLEAR \
- "10: clear.d [%0+]\n", \
- FIXUP \
- "11: addq 4,%1\n", \
- TENTRY \
- " .dword 10b,11b\n")
-
-#define __asm_clear_20(to, ret) \
- __asm_clear_20x_cont(to, ret, "", "", "")
-
-#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_20x_cont(to, ret, \
- CLEAR \
- "12: clear.d [%0+]\n", \
- FIXUP \
- "13: addq 4,%1\n", \
- TENTRY \
- " .dword 12b,13b\n")
-
-#define __asm_clear_24(to, ret) \
- __asm_clear_24x_cont(to, ret, "", "", "")
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return length of string in userspace including terminating 0
- * or 0 for error. Return a value greater than N if too long.
- */
-
-static inline long
-strnlen_user(const char *s, long n)
-{
- long res, tmp1;
-
- if (!access_ok(VERIFY_READ, s, 0))
- return 0;
-
- /*
- * This code is deduced from:
- *
- * tmp1 = n;
- * while (tmp1-- > 0 && *s++)
- * ;
- *
- * res = n - tmp1;
- *
- * (with tweaks).
- */
-
- __asm__ __volatile__ (
- " move.d %1,$acr\n"
- " cmpq 0,$acr\n"
- "0:\n"
- " ble 1f\n"
- " subq 1,$acr\n"
-
- "4: test.b [%0+]\n"
- " bne 0b\n"
- " cmpq 0,$acr\n"
- "1:\n"
- " move.d %1,%0\n"
- " sub.d $acr,%0\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
-
- "3: jump 2b\n"
- " clear.d %0\n"
-
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 4b,3b\n"
- " .previous\n"
- : "=r" (res), "=r" (tmp1)
- : "0" (s), "1" (n)
- : "acr");
-
- return res;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/unistd.h b/arch/cris/include/arch-v32/arch/unistd.h
deleted file mode 100644
index 764435b3b28e..000000000000
--- a/arch/cris/include/arch-v32/arch/unistd.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_UNISTD_H_
-#define _ASM_CRIS_ARCH_UNISTD_H_
-
-/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
-/*
- * Don't remove the .ifnc tests; they are an insurance against
- * any hard-to-spot gcc register allocation bugs.
- */
-#define _syscall0(type,name) \
-type name(void) \
-{ \
- register long __a __asm__ ("r10"); \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall1(type,name,type1,arg1) \
-type name(type1 arg1) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2) \
-type name(type1 arg1,type2 arg2) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
-type name(type1 arg1,type2 arg2,type3 arg3) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d)\
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __e __asm__ ("mof") = (long) arg5; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "h" (__e) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5,type6,arg6) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __e __asm__ ("mof") = (long) arg5; \
- register long __f __asm__ ("srp") = (long) arg6; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "h" (__e), "x" (__f) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h b/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h
deleted file mode 100644
index 7fafc370def2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum {
- arbiter_all_dmas = 0x7fe,
- arbiter_cpu = 0x1800,
- arbiter_all_clients = 0x7fff
-};
-
-enum {
- arbiter_bar_all_clients = 0x1ff
-};
-
-enum {
- arbiter_all_read = 0x55,
- arbiter_all_write = 0xaa,
- arbiter_all_accesses = 0xff
-};
-
-#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback * cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
deleted file mode 100644
index 92a74eab4395..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/dma.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
-
-#define NETWORK_ETH_TX_DMA_NBR 0 /* Ethernet 0 out. */
-#define NETWORK_ETH_RX_DMA_NBR 1 /* Ethernet 0 in. */
-
-#define IO_PROC_DMA_TX_DMA_NBR 4 /* IO processor DMA0 out. */
-#define IO_PROC_DMA_RX_DMA_NBR 5 /* IO processor DMA0 in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 2 /* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 3 /* Asynchronous serial port 3 in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 6 /* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 7 /* Asynchronous serial port 2 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
-
-#define SYNC_SER_TX_DMA_NBR 6 /* Synchronous serial port 0 out. */
-#define SYNC_SER_RX_DMA_NBR 7 /* Synchronous serial port 0 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 0 /* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 1 /* Asynchronous serial port 0 in. */
-
-#define STRCOP_TX_DMA_NBR 2 /* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 3 /* Stream co-processor in. */
-
-#define dma_eth0 dma_eth
-#define dma_eth1 dma_eth
-
-enum dma_owner {
- dma_eth,
- dma_ser0,
- dma_ser1,
- dma_ser2,
- dma_ser3,
- dma_ser4,
- dma_iop,
- dma_sser,
- dma_strp,
- dma_h264,
- dma_jpeg
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned bandwidth, enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h
deleted file mode 100644
index 3d7f12ec1c54..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __clkgen_defs_asm_h
-#define __clkgen_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: clkgen.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope clkgen, type r */
-#define reg_clkgen_r_bootsel___boot_mode___lsb 0
-#define reg_clkgen_r_bootsel___boot_mode___width 5
-#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
-#define reg_clkgen_r_bootsel___intern_main_clk___width 1
-#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
-#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
-#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
-#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
-#define reg_clkgen_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope clkgen, type rw */
-#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
-#define reg_clkgen_rw_clk_ctrl___pll___width 1
-#define reg_clkgen_rw_clk_ctrl___pll___bit 0
-#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
-#define reg_clkgen_rw_clk_ctrl___cpu___width 1
-#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
-#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
-#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
-#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
-#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
-#define reg_clkgen_rw_clk_ctrl___vin___width 1
-#define reg_clkgen_rw_clk_ctrl___vin___bit 3
-#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
-#define reg_clkgen_rw_clk_ctrl___sclr___width 1
-#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
-#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
-#define reg_clkgen_rw_clk_ctrl___h264___width 1
-#define reg_clkgen_rw_clk_ctrl___h264___bit 5
-#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
-#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
-#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
-#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
-#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
-#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
-#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
-#define reg_clkgen_rw_clk_ctrl___eth___width 1
-#define reg_clkgen_rw_clk_ctrl___eth___bit 8
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
-#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
-#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
-#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
-#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
-#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
-#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
-#define reg_clkgen_rw_clk_ctrl_offset 4
-
-
-/* Constants */
-#define regk_clkgen_eth1000_rx 0x0000000c
-#define regk_clkgen_eth1000_tx 0x0000000e
-#define regk_clkgen_eth100_rx 0x0000001d
-#define regk_clkgen_eth100_rx_half 0x0000001c
-#define regk_clkgen_eth100_tx 0x0000001f
-#define regk_clkgen_eth100_tx_half 0x0000001e
-#define regk_clkgen_nand_3_2 0x00000000
-#define regk_clkgen_nand_3_2_0x30 0x00000002
-#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
-#define regk_clkgen_nand_3_2_pll 0x00000010
-#define regk_clkgen_nand_3_3 0x00000001
-#define regk_clkgen_nand_3_3_0x30 0x00000003
-#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
-#define regk_clkgen_nand_3_3_pll 0x00000011
-#define regk_clkgen_nand_4_2 0x00000004
-#define regk_clkgen_nand_4_2_0x30 0x00000006
-#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
-#define regk_clkgen_nand_4_2_pll 0x00000014
-#define regk_clkgen_nand_4_3 0x00000005
-#define regk_clkgen_nand_4_3_0x30 0x00000007
-#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
-#define regk_clkgen_nand_4_3_pll 0x00000015
-#define regk_clkgen_nand_5_2 0x00000008
-#define regk_clkgen_nand_5_2_0x30 0x0000000a
-#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
-#define regk_clkgen_nand_5_2_pll 0x00000018
-#define regk_clkgen_nand_5_3 0x00000009
-#define regk_clkgen_nand_5_3_0x30 0x0000000b
-#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
-#define regk_clkgen_nand_5_3_pll 0x00000019
-#define regk_clkgen_no 0x00000000
-#define regk_clkgen_rw_clk_ctrl_default 0x00000002
-#define regk_clkgen_ser 0x0000000d
-#define regk_clkgen_ser_pll 0x0000000f
-#define regk_clkgen_yes 0x00000001
-#endif /* __clkgen_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h
deleted file mode 100644
index df79e5a7f02a..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ddr2_defs_asm_h
-#define __ddr2_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ddr2.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope ddr2, type rw */
-#define reg_ddr2_rw_cfg___col_width___lsb 0
-#define reg_ddr2_rw_cfg___col_width___width 4
-#define reg_ddr2_rw_cfg___nr_banks___lsb 4
-#define reg_ddr2_rw_cfg___nr_banks___width 1
-#define reg_ddr2_rw_cfg___nr_banks___bit 4
-#define reg_ddr2_rw_cfg___bw___lsb 5
-#define reg_ddr2_rw_cfg___bw___width 1
-#define reg_ddr2_rw_cfg___bw___bit 5
-#define reg_ddr2_rw_cfg___nr_ref___lsb 6
-#define reg_ddr2_rw_cfg___nr_ref___width 4
-#define reg_ddr2_rw_cfg___ref_interval___lsb 10
-#define reg_ddr2_rw_cfg___ref_interval___width 11
-#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
-#define reg_ddr2_rw_cfg___odt_ctrl___width 2
-#define reg_ddr2_rw_cfg___odt_mem___lsb 23
-#define reg_ddr2_rw_cfg___odt_mem___width 1
-#define reg_ddr2_rw_cfg___odt_mem___bit 23
-#define reg_ddr2_rw_cfg___imp_strength___lsb 24
-#define reg_ddr2_rw_cfg___imp_strength___width 1
-#define reg_ddr2_rw_cfg___imp_strength___bit 24
-#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
-#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
-#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
-#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
-#define reg_ddr2_rw_cfg___imp_cal_override___width 1
-#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
-#define reg_ddr2_rw_cfg___dll_override___lsb 27
-#define reg_ddr2_rw_cfg___dll_override___width 1
-#define reg_ddr2_rw_cfg___dll_override___bit 27
-#define reg_ddr2_rw_cfg_offset 0
-
-/* Register rw_timing, scope ddr2, type rw */
-#define reg_ddr2_rw_timing___wr___lsb 0
-#define reg_ddr2_rw_timing___wr___width 3
-#define reg_ddr2_rw_timing___rcd___lsb 3
-#define reg_ddr2_rw_timing___rcd___width 3
-#define reg_ddr2_rw_timing___rp___lsb 6
-#define reg_ddr2_rw_timing___rp___width 3
-#define reg_ddr2_rw_timing___ras___lsb 9
-#define reg_ddr2_rw_timing___ras___width 4
-#define reg_ddr2_rw_timing___rfc___lsb 13
-#define reg_ddr2_rw_timing___rfc___width 7
-#define reg_ddr2_rw_timing___rc___lsb 20
-#define reg_ddr2_rw_timing___rc___width 5
-#define reg_ddr2_rw_timing___rtp___lsb 25
-#define reg_ddr2_rw_timing___rtp___width 2
-#define reg_ddr2_rw_timing___rtw___lsb 27
-#define reg_ddr2_rw_timing___rtw___width 3
-#define reg_ddr2_rw_timing___wtr___lsb 30
-#define reg_ddr2_rw_timing___wtr___width 2
-#define reg_ddr2_rw_timing_offset 4
-
-/* Register rw_latency, scope ddr2, type rw */
-#define reg_ddr2_rw_latency___cas___lsb 0
-#define reg_ddr2_rw_latency___cas___width 3
-#define reg_ddr2_rw_latency___additive___lsb 3
-#define reg_ddr2_rw_latency___additive___width 3
-#define reg_ddr2_rw_latency_offset 8
-
-/* Register rw_phy_cfg, scope ddr2, type rw */
-#define reg_ddr2_rw_phy_cfg___en___lsb 0
-#define reg_ddr2_rw_phy_cfg___en___width 1
-#define reg_ddr2_rw_phy_cfg___en___bit 0
-#define reg_ddr2_rw_phy_cfg_offset 12
-
-/* Register rw_phy_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
-#define reg_ddr2_rw_phy_ctrl___rst___width 1
-#define reg_ddr2_rw_phy_ctrl___rst___bit 0
-#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
-#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
-#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
-#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
-#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
-#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
-#define reg_ddr2_rw_phy_ctrl_offset 16
-
-/* Register rw_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
-#define reg_ddr2_rw_ctrl___mrs_data___width 16
-#define reg_ddr2_rw_ctrl___cmd___lsb 16
-#define reg_ddr2_rw_ctrl___cmd___width 8
-#define reg_ddr2_rw_ctrl_offset 20
-
-/* Register rw_pwr_down, scope ddr2, type rw */
-#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
-#define reg_ddr2_rw_pwr_down___self_ref___width 2
-#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
-#define reg_ddr2_rw_pwr_down___phy_en___width 1
-#define reg_ddr2_rw_pwr_down___phy_en___bit 2
-#define reg_ddr2_rw_pwr_down_offset 24
-
-/* Register r_stat, scope ddr2, type r */
-#define reg_ddr2_r_stat___dll_lock___lsb 0
-#define reg_ddr2_r_stat___dll_lock___width 1
-#define reg_ddr2_r_stat___dll_lock___bit 0
-#define reg_ddr2_r_stat___dll_delay_code___lsb 1
-#define reg_ddr2_r_stat___dll_delay_code___width 7
-#define reg_ddr2_r_stat___imp_cal_done___lsb 8
-#define reg_ddr2_r_stat___imp_cal_done___width 1
-#define reg_ddr2_r_stat___imp_cal_done___bit 8
-#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
-#define reg_ddr2_r_stat___imp_cal_fault___width 1
-#define reg_ddr2_r_stat___imp_cal_fault___bit 9
-#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
-#define reg_ddr2_r_stat___cal_imp_pu___width 4
-#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
-#define reg_ddr2_r_stat___cal_imp_pd___width 4
-#define reg_ddr2_r_stat_offset 28
-
-/* Register rw_imp_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
-#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
-#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
-#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
-#define reg_ddr2_rw_imp_ctrl_offset 32
-
-#define STRIDE_ddr2_rw_dll_ctrl 4
-/* Register rw_dll_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
-#define reg_ddr2_rw_dll_ctrl___mode___width 1
-#define reg_ddr2_rw_dll_ctrl___mode___bit 0
-#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
-#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
-#define reg_ddr2_rw_dll_ctrl_offset 36
-
-#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
-/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
-
-
-/* Constants */
-#define regk_ddr2_al0 0x00000000
-#define regk_ddr2_al1 0x00000008
-#define regk_ddr2_al2 0x00000010
-#define regk_ddr2_al3 0x00000018
-#define regk_ddr2_al4 0x00000020
-#define regk_ddr2_auto 0x00000003
-#define regk_ddr2_bank4 0x00000000
-#define regk_ddr2_bank8 0x00000001
-#define regk_ddr2_bl4 0x00000002
-#define regk_ddr2_bl8 0x00000003
-#define regk_ddr2_bt_il 0x00000008
-#define regk_ddr2_bt_seq 0x00000000
-#define regk_ddr2_bw16 0x00000001
-#define regk_ddr2_bw32 0x00000000
-#define regk_ddr2_cas2 0x00000020
-#define regk_ddr2_cas3 0x00000030
-#define regk_ddr2_cas4 0x00000040
-#define regk_ddr2_cas5 0x00000050
-#define regk_ddr2_deselect 0x000000c0
-#define regk_ddr2_dic_weak 0x00000002
-#define regk_ddr2_direct 0x00000001
-#define regk_ddr2_dis 0x00000000
-#define regk_ddr2_dll_dis 0x00000001
-#define regk_ddr2_dll_en 0x00000000
-#define regk_ddr2_dll_rst 0x00000100
-#define regk_ddr2_emrs 0x00000081
-#define regk_ddr2_emrs2 0x00000082
-#define regk_ddr2_emrs3 0x00000083
-#define regk_ddr2_full 0x00000001
-#define regk_ddr2_hi_ref_rate 0x00000080
-#define regk_ddr2_mrs 0x00000080
-#define regk_ddr2_no 0x00000000
-#define regk_ddr2_nop 0x000000b8
-#define regk_ddr2_ocd_adj 0x00000200
-#define regk_ddr2_ocd_default 0x00000380
-#define regk_ddr2_ocd_drive0 0x00000100
-#define regk_ddr2_ocd_drive1 0x00000080
-#define regk_ddr2_ocd_exit 0x00000000
-#define regk_ddr2_odt_dis 0x00000000
-#define regk_ddr2_offs 0x00000000
-#define regk_ddr2_pre 0x00000090
-#define regk_ddr2_pre_all 0x00000400
-#define regk_ddr2_pwr_down_fast 0x00000000
-#define regk_ddr2_pwr_down_slow 0x00001000
-#define regk_ddr2_ref 0x00000088
-#define regk_ddr2_rtt150 0x00000040
-#define regk_ddr2_rtt50 0x00000044
-#define regk_ddr2_rtt75 0x00000004
-#define regk_ddr2_rw_cfg_default 0x00186000
-#define regk_ddr2_rw_dll_ctrl_default 0x00000000
-#define regk_ddr2_rw_dll_ctrl_size 0x00000004
-#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
-#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
-#define regk_ddr2_rw_latency_default 0x00000000
-#define regk_ddr2_rw_phy_cfg_default 0x00000000
-#define regk_ddr2_rw_pwr_down_default 0x00000000
-#define regk_ddr2_rw_timing_default 0x00000000
-#define regk_ddr2_s1Gb 0x0000001a
-#define regk_ddr2_s256Mb 0x0000000f
-#define regk_ddr2_s2Gb 0x00000027
-#define regk_ddr2_s4Gb 0x00000042
-#define regk_ddr2_s512Mb 0x00000015
-#define regk_ddr2_temp0_85 0x00000618
-#define regk_ddr2_temp85_95 0x0000030c
-#define regk_ddr2_term150 0x00000002
-#define regk_ddr2_term50 0x00000003
-#define regk_ddr2_term75 0x00000001
-#define regk_ddr2_test 0x00000080
-#define regk_ddr2_weak 0x00000000
-#define regk_ddr2_wr2 0x00000200
-#define regk_ddr2_wr3 0x00000400
-#define regk_ddr2_yes 0x00000001
-#endif /* __ddr2_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 04b7ff3f70a2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: gio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 32
-#define reg_gio_r_pa_din_offset 0
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 32
-#define reg_gio_rw_pa_dout_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 32
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_pa_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte0_dout___data___lsb 0
-#define reg_gio_rw_pa_byte0_dout___data___width 8
-#define reg_gio_rw_pa_byte0_dout_offset 12
-
-/* Register rw_pa_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte0_oe___oe___width 8
-#define reg_gio_rw_pa_byte0_oe_offset 16
-
-/* Register rw_pa_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte1_dout___data___lsb 0
-#define reg_gio_rw_pa_byte1_dout___data___width 8
-#define reg_gio_rw_pa_byte1_dout_offset 20
-
-/* Register rw_pa_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte1_oe___oe___width 8
-#define reg_gio_rw_pa_byte1_oe_offset 24
-
-/* Register rw_pa_byte2_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte2_dout___data___lsb 0
-#define reg_gio_rw_pa_byte2_dout___data___width 8
-#define reg_gio_rw_pa_byte2_dout_offset 28
-
-/* Register rw_pa_byte2_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte2_oe___oe___width 8
-#define reg_gio_rw_pa_byte2_oe_offset 32
-
-/* Register rw_pa_byte3_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte3_dout___data___lsb 0
-#define reg_gio_rw_pa_byte3_dout___data___width 8
-#define reg_gio_rw_pa_byte3_dout_offset 36
-
-/* Register rw_pa_byte3_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte3_oe___oe___width 8
-#define reg_gio_rw_pa_byte3_oe_offset 40
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 32
-#define reg_gio_r_pb_din_offset 44
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 32
-#define reg_gio_rw_pb_dout_offset 48
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 32
-#define reg_gio_rw_pb_oe_offset 52
-
-/* Register rw_pb_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte0_dout___data___lsb 0
-#define reg_gio_rw_pb_byte0_dout___data___width 8
-#define reg_gio_rw_pb_byte0_dout_offset 56
-
-/* Register rw_pb_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte0_oe___oe___width 8
-#define reg_gio_rw_pb_byte0_oe_offset 60
-
-/* Register rw_pb_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte1_dout___data___lsb 0
-#define reg_gio_rw_pb_byte1_dout___data___width 8
-#define reg_gio_rw_pb_byte1_dout_offset 64
-
-/* Register rw_pb_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte1_oe___oe___width 8
-#define reg_gio_rw_pb_byte1_oe_offset 68
-
-/* Register rw_pb_byte2_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte2_dout___data___lsb 0
-#define reg_gio_rw_pb_byte2_dout___data___width 8
-#define reg_gio_rw_pb_byte2_dout_offset 72
-
-/* Register rw_pb_byte2_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte2_oe___oe___width 8
-#define reg_gio_rw_pb_byte2_oe_offset 76
-
-/* Register rw_pb_byte3_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte3_dout___data___lsb 0
-#define reg_gio_rw_pb_byte3_dout___data___width 8
-#define reg_gio_rw_pb_byte3_dout_offset 80
-
-/* Register rw_pb_byte3_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte3_oe___oe___width 8
-#define reg_gio_rw_pb_byte3_oe_offset 84
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 16
-#define reg_gio_r_pc_din_offset 88
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 16
-#define reg_gio_rw_pc_dout_offset 92
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 16
-#define reg_gio_rw_pc_oe_offset 96
-
-/* Register rw_pc_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pc_byte0_dout___data___lsb 0
-#define reg_gio_rw_pc_byte0_dout___data___width 8
-#define reg_gio_rw_pc_byte0_dout_offset 100
-
-/* Register rw_pc_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pc_byte0_oe___oe___width 8
-#define reg_gio_rw_pc_byte0_oe_offset 104
-
-/* Register rw_pc_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pc_byte1_dout___data___lsb 0
-#define reg_gio_rw_pc_byte1_dout___data___width 8
-#define reg_gio_rw_pc_byte1_dout_offset 108
-
-/* Register rw_pc_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pc_byte1_oe___oe___width 8
-#define reg_gio_rw_pc_byte1_oe_offset 112
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 32
-#define reg_gio_r_pd_din_offset 116
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___intr0___lsb 0
-#define reg_gio_rw_intr_cfg___intr0___width 3
-#define reg_gio_rw_intr_cfg___intr1___lsb 3
-#define reg_gio_rw_intr_cfg___intr1___width 3
-#define reg_gio_rw_intr_cfg___intr2___lsb 6
-#define reg_gio_rw_intr_cfg___intr2___width 3
-#define reg_gio_rw_intr_cfg___intr3___lsb 9
-#define reg_gio_rw_intr_cfg___intr3___width 3
-#define reg_gio_rw_intr_cfg___intr4___lsb 12
-#define reg_gio_rw_intr_cfg___intr4___width 3
-#define reg_gio_rw_intr_cfg___intr5___lsb 15
-#define reg_gio_rw_intr_cfg___intr5___width 3
-#define reg_gio_rw_intr_cfg___intr6___lsb 18
-#define reg_gio_rw_intr_cfg___intr6___width 3
-#define reg_gio_rw_intr_cfg___intr7___lsb 21
-#define reg_gio_rw_intr_cfg___intr7___width 3
-#define reg_gio_rw_intr_cfg_offset 120
-
-/* Register rw_intr_pins, scope gio, type rw */
-#define reg_gio_rw_intr_pins___intr0___lsb 0
-#define reg_gio_rw_intr_pins___intr0___width 4
-#define reg_gio_rw_intr_pins___intr1___lsb 4
-#define reg_gio_rw_intr_pins___intr1___width 4
-#define reg_gio_rw_intr_pins___intr2___lsb 8
-#define reg_gio_rw_intr_pins___intr2___width 4
-#define reg_gio_rw_intr_pins___intr3___lsb 12
-#define reg_gio_rw_intr_pins___intr3___width 4
-#define reg_gio_rw_intr_pins___intr4___lsb 16
-#define reg_gio_rw_intr_pins___intr4___width 4
-#define reg_gio_rw_intr_pins___intr5___lsb 20
-#define reg_gio_rw_intr_pins___intr5___width 4
-#define reg_gio_rw_intr_pins___intr6___lsb 24
-#define reg_gio_rw_intr_pins___intr6___width 4
-#define reg_gio_rw_intr_pins___intr7___lsb 28
-#define reg_gio_rw_intr_pins___intr7___width 4
-#define reg_gio_rw_intr_pins_offset 124
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___intr0___lsb 0
-#define reg_gio_rw_intr_mask___intr0___width 1
-#define reg_gio_rw_intr_mask___intr0___bit 0
-#define reg_gio_rw_intr_mask___intr1___lsb 1
-#define reg_gio_rw_intr_mask___intr1___width 1
-#define reg_gio_rw_intr_mask___intr1___bit 1
-#define reg_gio_rw_intr_mask___intr2___lsb 2
-#define reg_gio_rw_intr_mask___intr2___width 1
-#define reg_gio_rw_intr_mask___intr2___bit 2
-#define reg_gio_rw_intr_mask___intr3___lsb 3
-#define reg_gio_rw_intr_mask___intr3___width 1
-#define reg_gio_rw_intr_mask___intr3___bit 3
-#define reg_gio_rw_intr_mask___intr4___lsb 4
-#define reg_gio_rw_intr_mask___intr4___width 1
-#define reg_gio_rw_intr_mask___intr4___bit 4
-#define reg_gio_rw_intr_mask___intr5___lsb 5
-#define reg_gio_rw_intr_mask___intr5___width 1
-#define reg_gio_rw_intr_mask___intr5___bit 5
-#define reg_gio_rw_intr_mask___intr6___lsb 6
-#define reg_gio_rw_intr_mask___intr6___width 1
-#define reg_gio_rw_intr_mask___intr6___bit 6
-#define reg_gio_rw_intr_mask___intr7___lsb 7
-#define reg_gio_rw_intr_mask___intr7___width 1
-#define reg_gio_rw_intr_mask___intr7___bit 7
-#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
-#define reg_gio_rw_intr_mask___i2c0_done___width 1
-#define reg_gio_rw_intr_mask___i2c0_done___bit 8
-#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
-#define reg_gio_rw_intr_mask___i2c1_done___width 1
-#define reg_gio_rw_intr_mask___i2c1_done___bit 9
-#define reg_gio_rw_intr_mask_offset 128
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___intr0___lsb 0
-#define reg_gio_rw_ack_intr___intr0___width 1
-#define reg_gio_rw_ack_intr___intr0___bit 0
-#define reg_gio_rw_ack_intr___intr1___lsb 1
-#define reg_gio_rw_ack_intr___intr1___width 1
-#define reg_gio_rw_ack_intr___intr1___bit 1
-#define reg_gio_rw_ack_intr___intr2___lsb 2
-#define reg_gio_rw_ack_intr___intr2___width 1
-#define reg_gio_rw_ack_intr___intr2___bit 2
-#define reg_gio_rw_ack_intr___intr3___lsb 3
-#define reg_gio_rw_ack_intr___intr3___width 1
-#define reg_gio_rw_ack_intr___intr3___bit 3
-#define reg_gio_rw_ack_intr___intr4___lsb 4
-#define reg_gio_rw_ack_intr___intr4___width 1
-#define reg_gio_rw_ack_intr___intr4___bit 4
-#define reg_gio_rw_ack_intr___intr5___lsb 5
-#define reg_gio_rw_ack_intr___intr5___width 1
-#define reg_gio_rw_ack_intr___intr5___bit 5
-#define reg_gio_rw_ack_intr___intr6___lsb 6
-#define reg_gio_rw_ack_intr___intr6___width 1
-#define reg_gio_rw_ack_intr___intr6___bit 6
-#define reg_gio_rw_ack_intr___intr7___lsb 7
-#define reg_gio_rw_ack_intr___intr7___width 1
-#define reg_gio_rw_ack_intr___intr7___bit 7
-#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
-#define reg_gio_rw_ack_intr___i2c0_done___width 1
-#define reg_gio_rw_ack_intr___i2c0_done___bit 8
-#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
-#define reg_gio_rw_ack_intr___i2c1_done___width 1
-#define reg_gio_rw_ack_intr___i2c1_done___bit 9
-#define reg_gio_rw_ack_intr_offset 132
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___intr0___lsb 0
-#define reg_gio_r_intr___intr0___width 1
-#define reg_gio_r_intr___intr0___bit 0
-#define reg_gio_r_intr___intr1___lsb 1
-#define reg_gio_r_intr___intr1___width 1
-#define reg_gio_r_intr___intr1___bit 1
-#define reg_gio_r_intr___intr2___lsb 2
-#define reg_gio_r_intr___intr2___width 1
-#define reg_gio_r_intr___intr2___bit 2
-#define reg_gio_r_intr___intr3___lsb 3
-#define reg_gio_r_intr___intr3___width 1
-#define reg_gio_r_intr___intr3___bit 3
-#define reg_gio_r_intr___intr4___lsb 4
-#define reg_gio_r_intr___intr4___width 1
-#define reg_gio_r_intr___intr4___bit 4
-#define reg_gio_r_intr___intr5___lsb 5
-#define reg_gio_r_intr___intr5___width 1
-#define reg_gio_r_intr___intr5___bit 5
-#define reg_gio_r_intr___intr6___lsb 6
-#define reg_gio_r_intr___intr6___width 1
-#define reg_gio_r_intr___intr6___bit 6
-#define reg_gio_r_intr___intr7___lsb 7
-#define reg_gio_r_intr___intr7___width 1
-#define reg_gio_r_intr___intr7___bit 7
-#define reg_gio_r_intr___i2c0_done___lsb 8
-#define reg_gio_r_intr___i2c0_done___width 1
-#define reg_gio_r_intr___i2c0_done___bit 8
-#define reg_gio_r_intr___i2c1_done___lsb 9
-#define reg_gio_r_intr___i2c1_done___width 1
-#define reg_gio_r_intr___i2c1_done___bit 9
-#define reg_gio_r_intr_offset 136
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___intr0___lsb 0
-#define reg_gio_r_masked_intr___intr0___width 1
-#define reg_gio_r_masked_intr___intr0___bit 0
-#define reg_gio_r_masked_intr___intr1___lsb 1
-#define reg_gio_r_masked_intr___intr1___width 1
-#define reg_gio_r_masked_intr___intr1___bit 1
-#define reg_gio_r_masked_intr___intr2___lsb 2
-#define reg_gio_r_masked_intr___intr2___width 1
-#define reg_gio_r_masked_intr___intr2___bit 2
-#define reg_gio_r_masked_intr___intr3___lsb 3
-#define reg_gio_r_masked_intr___intr3___width 1
-#define reg_gio_r_masked_intr___intr3___bit 3
-#define reg_gio_r_masked_intr___intr4___lsb 4
-#define reg_gio_r_masked_intr___intr4___width 1
-#define reg_gio_r_masked_intr___intr4___bit 4
-#define reg_gio_r_masked_intr___intr5___lsb 5
-#define reg_gio_r_masked_intr___intr5___width 1
-#define reg_gio_r_masked_intr___intr5___bit 5
-#define reg_gio_r_masked_intr___intr6___lsb 6
-#define reg_gio_r_masked_intr___intr6___width 1
-#define reg_gio_r_masked_intr___intr6___bit 6
-#define reg_gio_r_masked_intr___intr7___lsb 7
-#define reg_gio_r_masked_intr___intr7___width 1
-#define reg_gio_r_masked_intr___intr7___bit 7
-#define reg_gio_r_masked_intr___i2c0_done___lsb 8
-#define reg_gio_r_masked_intr___i2c0_done___width 1
-#define reg_gio_r_masked_intr___i2c0_done___bit 8
-#define reg_gio_r_masked_intr___i2c1_done___lsb 9
-#define reg_gio_r_masked_intr___i2c1_done___width 1
-#define reg_gio_r_masked_intr___i2c1_done___bit 9
-#define reg_gio_r_masked_intr_offset 140
-
-/* Register rw_i2c0_start, scope gio, type rw */
-#define reg_gio_rw_i2c0_start___run___lsb 0
-#define reg_gio_rw_i2c0_start___run___width 1
-#define reg_gio_rw_i2c0_start___run___bit 0
-#define reg_gio_rw_i2c0_start_offset 144
-
-/* Register rw_i2c0_cfg, scope gio, type rw */
-#define reg_gio_rw_i2c0_cfg___en___lsb 0
-#define reg_gio_rw_i2c0_cfg___en___width 1
-#define reg_gio_rw_i2c0_cfg___en___bit 0
-#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
-#define reg_gio_rw_i2c0_cfg___bit_order___width 1
-#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
-#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
-#define reg_gio_rw_i2c0_cfg___scl_io___width 1
-#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
-#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
-#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
-#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
-#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
-#define reg_gio_rw_i2c0_cfg___sda_io___width 1
-#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
-#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
-#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
-#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
-#define reg_gio_rw_i2c0_cfg_offset 148
-
-/* Register rw_i2c0_ctrl, scope gio, type rw */
-#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
-#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
-#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
-#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
-#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
-#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
-#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
-#define reg_gio_rw_i2c0_ctrl___early_end___width 1
-#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
-#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
-#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
-#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
-#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
-#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
-#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
-#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
-#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
-#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
-#define reg_gio_rw_i2c0_ctrl___freq___width 2
-#define reg_gio_rw_i2c0_ctrl_offset 152
-
-/* Register rw_i2c0_data, scope gio, type rw */
-#define reg_gio_rw_i2c0_data___data0___lsb 0
-#define reg_gio_rw_i2c0_data___data0___width 8
-#define reg_gio_rw_i2c0_data___data1___lsb 8
-#define reg_gio_rw_i2c0_data___data1___width 8
-#define reg_gio_rw_i2c0_data___data2___lsb 16
-#define reg_gio_rw_i2c0_data___data2___width 8
-#define reg_gio_rw_i2c0_data___data3___lsb 24
-#define reg_gio_rw_i2c0_data___data3___width 8
-#define reg_gio_rw_i2c0_data_offset 156
-
-/* Register rw_i2c0_data2, scope gio, type rw */
-#define reg_gio_rw_i2c0_data2___data4___lsb 0
-#define reg_gio_rw_i2c0_data2___data4___width 8
-#define reg_gio_rw_i2c0_data2___data5___lsb 8
-#define reg_gio_rw_i2c0_data2___data5___width 8
-#define reg_gio_rw_i2c0_data2___start_val___lsb 16
-#define reg_gio_rw_i2c0_data2___start_val___width 6
-#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
-#define reg_gio_rw_i2c0_data2___ack_val___width 6
-#define reg_gio_rw_i2c0_data2_offset 160
-
-/* Register rw_i2c1_start, scope gio, type rw */
-#define reg_gio_rw_i2c1_start___run___lsb 0
-#define reg_gio_rw_i2c1_start___run___width 1
-#define reg_gio_rw_i2c1_start___run___bit 0
-#define reg_gio_rw_i2c1_start_offset 164
-
-/* Register rw_i2c1_cfg, scope gio, type rw */
-#define reg_gio_rw_i2c1_cfg___en___lsb 0
-#define reg_gio_rw_i2c1_cfg___en___width 1
-#define reg_gio_rw_i2c1_cfg___en___bit 0
-#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
-#define reg_gio_rw_i2c1_cfg___bit_order___width 1
-#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
-#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
-#define reg_gio_rw_i2c1_cfg___scl_io___width 1
-#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
-#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
-#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
-#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
-#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
-#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
-#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
-#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
-#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
-#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
-#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
-#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
-#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
-#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
-#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
-#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
-#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
-#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
-#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
-#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
-#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
-#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
-#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
-#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
-#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
-#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
-#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
-#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
-#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
-#define reg_gio_rw_i2c1_cfg_offset 168
-
-/* Register rw_i2c1_ctrl, scope gio, type rw */
-#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
-#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
-#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
-#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
-#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
-#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
-#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
-#define reg_gio_rw_i2c1_ctrl___early_end___width 1
-#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
-#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
-#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
-#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
-#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
-#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
-#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
-#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
-#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
-#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
-#define reg_gio_rw_i2c1_ctrl___freq___width 2
-#define reg_gio_rw_i2c1_ctrl_offset 172
-
-/* Register rw_i2c1_data, scope gio, type rw */
-#define reg_gio_rw_i2c1_data___data0___lsb 0
-#define reg_gio_rw_i2c1_data___data0___width 8
-#define reg_gio_rw_i2c1_data___data1___lsb 8
-#define reg_gio_rw_i2c1_data___data1___width 8
-#define reg_gio_rw_i2c1_data___data2___lsb 16
-#define reg_gio_rw_i2c1_data___data2___width 8
-#define reg_gio_rw_i2c1_data___data3___lsb 24
-#define reg_gio_rw_i2c1_data___data3___width 8
-#define reg_gio_rw_i2c1_data_offset 176
-
-/* Register rw_i2c1_data2, scope gio, type rw */
-#define reg_gio_rw_i2c1_data2___data4___lsb 0
-#define reg_gio_rw_i2c1_data2___data4___width 8
-#define reg_gio_rw_i2c1_data2___data5___lsb 8
-#define reg_gio_rw_i2c1_data2___data5___width 8
-#define reg_gio_rw_i2c1_data2___start_val___lsb 16
-#define reg_gio_rw_i2c1_data2___start_val___width 6
-#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
-#define reg_gio_rw_i2c1_data2___ack_val___width 6
-#define reg_gio_rw_i2c1_data2_offset 180
-
-/* Register r_ppwm_stat, scope gio, type r */
-#define reg_gio_r_ppwm_stat___freq___lsb 0
-#define reg_gio_r_ppwm_stat___freq___width 2
-#define reg_gio_r_ppwm_stat_offset 184
-
-/* Register rw_ppwm_data, scope gio, type rw */
-#define reg_gio_rw_ppwm_data___data___lsb 0
-#define reg_gio_rw_ppwm_data___data___width 8
-#define reg_gio_rw_ppwm_data_offset 188
-
-/* Register rw_pwm0_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm0_ctrl___mode___width 2
-#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm0_ctrl_offset 192
-
-/* Register rw_pwm0_var, scope gio, type rw */
-#define reg_gio_rw_pwm0_var___lo___lsb 0
-#define reg_gio_rw_pwm0_var___lo___width 13
-#define reg_gio_rw_pwm0_var___hi___lsb 13
-#define reg_gio_rw_pwm0_var___hi___width 13
-#define reg_gio_rw_pwm0_var_offset 196
-
-/* Register rw_pwm0_data, scope gio, type rw */
-#define reg_gio_rw_pwm0_data___data___lsb 0
-#define reg_gio_rw_pwm0_data___data___width 8
-#define reg_gio_rw_pwm0_data_offset 200
-
-/* Register rw_pwm1_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm1_ctrl___mode___width 2
-#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm1_ctrl_offset 204
-
-/* Register rw_pwm1_var, scope gio, type rw */
-#define reg_gio_rw_pwm1_var___lo___lsb 0
-#define reg_gio_rw_pwm1_var___lo___width 13
-#define reg_gio_rw_pwm1_var___hi___lsb 13
-#define reg_gio_rw_pwm1_var___hi___width 13
-#define reg_gio_rw_pwm1_var_offset 208
-
-/* Register rw_pwm1_data, scope gio, type rw */
-#define reg_gio_rw_pwm1_data___data___lsb 0
-#define reg_gio_rw_pwm1_data___data___width 8
-#define reg_gio_rw_pwm1_data_offset 212
-
-/* Register rw_pwm2_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm2_ctrl___mode___width 2
-#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm2_ctrl_offset 216
-
-/* Register rw_pwm2_var, scope gio, type rw */
-#define reg_gio_rw_pwm2_var___lo___lsb 0
-#define reg_gio_rw_pwm2_var___lo___width 13
-#define reg_gio_rw_pwm2_var___hi___lsb 13
-#define reg_gio_rw_pwm2_var___hi___width 13
-#define reg_gio_rw_pwm2_var_offset 220
-
-/* Register rw_pwm2_data, scope gio, type rw */
-#define reg_gio_rw_pwm2_data___data___lsb 0
-#define reg_gio_rw_pwm2_data___data___width 8
-#define reg_gio_rw_pwm2_data_offset 224
-
-/* Register rw_pwm_in_cfg, scope gio, type rw */
-#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
-#define reg_gio_rw_pwm_in_cfg___pin___width 3
-#define reg_gio_rw_pwm_in_cfg_offset 228
-
-/* Register r_pwm_in_lo, scope gio, type r */
-#define reg_gio_r_pwm_in_lo___data___lsb 0
-#define reg_gio_r_pwm_in_lo___data___width 32
-#define reg_gio_r_pwm_in_lo_offset 232
-
-/* Register r_pwm_in_hi, scope gio, type r */
-#define reg_gio_r_pwm_in_hi___data___lsb 0
-#define reg_gio_r_pwm_in_hi___data___width 32
-#define reg_gio_r_pwm_in_hi_offset 236
-
-/* Register r_pwm_in_cnt, scope gio, type r */
-#define reg_gio_r_pwm_in_cnt___data___lsb 0
-#define reg_gio_r_pwm_in_cnt___data___width 32
-#define reg_gio_r_pwm_in_cnt_offset 240
-
-
-/* Constants */
-#define regk_gio_anyedge 0x00000007
-#define regk_gio_f100k 0x00000000
-#define regk_gio_f1562 0x00000000
-#define regk_gio_f195 0x00000003
-#define regk_gio_f1m 0x00000002
-#define regk_gio_f390 0x00000002
-#define regk_gio_f400k 0x00000001
-#define regk_gio_f5m 0x00000003
-#define regk_gio_f781 0x00000001
-#define regk_gio_hi 0x00000001
-#define regk_gio_in 0x00000000
-#define regk_gio_intr_pa0 0x00000000
-#define regk_gio_intr_pa1 0x00000000
-#define regk_gio_intr_pa10 0x00000001
-#define regk_gio_intr_pa11 0x00000001
-#define regk_gio_intr_pa12 0x00000001
-#define regk_gio_intr_pa13 0x00000001
-#define regk_gio_intr_pa14 0x00000001
-#define regk_gio_intr_pa15 0x00000001
-#define regk_gio_intr_pa16 0x00000002
-#define regk_gio_intr_pa17 0x00000002
-#define regk_gio_intr_pa18 0x00000002
-#define regk_gio_intr_pa19 0x00000002
-#define regk_gio_intr_pa2 0x00000000
-#define regk_gio_intr_pa20 0x00000002
-#define regk_gio_intr_pa21 0x00000002
-#define regk_gio_intr_pa22 0x00000002
-#define regk_gio_intr_pa23 0x00000002
-#define regk_gio_intr_pa24 0x00000003
-#define regk_gio_intr_pa25 0x00000003
-#define regk_gio_intr_pa26 0x00000003
-#define regk_gio_intr_pa27 0x00000003
-#define regk_gio_intr_pa28 0x00000003
-#define regk_gio_intr_pa29 0x00000003
-#define regk_gio_intr_pa3 0x00000000
-#define regk_gio_intr_pa30 0x00000003
-#define regk_gio_intr_pa31 0x00000003
-#define regk_gio_intr_pa4 0x00000000
-#define regk_gio_intr_pa5 0x00000000
-#define regk_gio_intr_pa6 0x00000000
-#define regk_gio_intr_pa7 0x00000000
-#define regk_gio_intr_pa8 0x00000001
-#define regk_gio_intr_pa9 0x00000001
-#define regk_gio_intr_pb0 0x00000004
-#define regk_gio_intr_pb1 0x00000004
-#define regk_gio_intr_pb10 0x00000005
-#define regk_gio_intr_pb11 0x00000005
-#define regk_gio_intr_pb12 0x00000005
-#define regk_gio_intr_pb13 0x00000005
-#define regk_gio_intr_pb14 0x00000005
-#define regk_gio_intr_pb15 0x00000005
-#define regk_gio_intr_pb16 0x00000006
-#define regk_gio_intr_pb17 0x00000006
-#define regk_gio_intr_pb18 0x00000006
-#define regk_gio_intr_pb19 0x00000006
-#define regk_gio_intr_pb2 0x00000004
-#define regk_gio_intr_pb20 0x00000006
-#define regk_gio_intr_pb21 0x00000006
-#define regk_gio_intr_pb22 0x00000006
-#define regk_gio_intr_pb23 0x00000006
-#define regk_gio_intr_pb24 0x00000007
-#define regk_gio_intr_pb25 0x00000007
-#define regk_gio_intr_pb26 0x00000007
-#define regk_gio_intr_pb27 0x00000007
-#define regk_gio_intr_pb28 0x00000007
-#define regk_gio_intr_pb29 0x00000007
-#define regk_gio_intr_pb3 0x00000004
-#define regk_gio_intr_pb30 0x00000007
-#define regk_gio_intr_pb31 0x00000007
-#define regk_gio_intr_pb4 0x00000004
-#define regk_gio_intr_pb5 0x00000004
-#define regk_gio_intr_pb6 0x00000004
-#define regk_gio_intr_pb7 0x00000004
-#define regk_gio_intr_pb8 0x00000005
-#define regk_gio_intr_pb9 0x00000005
-#define regk_gio_intr_pc0 0x00000008
-#define regk_gio_intr_pc1 0x00000008
-#define regk_gio_intr_pc10 0x00000009
-#define regk_gio_intr_pc11 0x00000009
-#define regk_gio_intr_pc12 0x00000009
-#define regk_gio_intr_pc13 0x00000009
-#define regk_gio_intr_pc14 0x00000009
-#define regk_gio_intr_pc15 0x00000009
-#define regk_gio_intr_pc2 0x00000008
-#define regk_gio_intr_pc3 0x00000008
-#define regk_gio_intr_pc4 0x00000008
-#define regk_gio_intr_pc5 0x00000008
-#define regk_gio_intr_pc6 0x00000008
-#define regk_gio_intr_pc7 0x00000008
-#define regk_gio_intr_pc8 0x00000009
-#define regk_gio_intr_pc9 0x00000009
-#define regk_gio_intr_pd0 0x0000000c
-#define regk_gio_intr_pd1 0x0000000c
-#define regk_gio_intr_pd10 0x0000000d
-#define regk_gio_intr_pd11 0x0000000d
-#define regk_gio_intr_pd12 0x0000000d
-#define regk_gio_intr_pd13 0x0000000d
-#define regk_gio_intr_pd14 0x0000000d
-#define regk_gio_intr_pd15 0x0000000d
-#define regk_gio_intr_pd16 0x0000000e
-#define regk_gio_intr_pd17 0x0000000e
-#define regk_gio_intr_pd18 0x0000000e
-#define regk_gio_intr_pd19 0x0000000e
-#define regk_gio_intr_pd2 0x0000000c
-#define regk_gio_intr_pd20 0x0000000e
-#define regk_gio_intr_pd21 0x0000000e
-#define regk_gio_intr_pd22 0x0000000e
-#define regk_gio_intr_pd23 0x0000000e
-#define regk_gio_intr_pd24 0x0000000f
-#define regk_gio_intr_pd25 0x0000000f
-#define regk_gio_intr_pd26 0x0000000f
-#define regk_gio_intr_pd27 0x0000000f
-#define regk_gio_intr_pd28 0x0000000f
-#define regk_gio_intr_pd29 0x0000000f
-#define regk_gio_intr_pd3 0x0000000c
-#define regk_gio_intr_pd30 0x0000000f
-#define regk_gio_intr_pd31 0x0000000f
-#define regk_gio_intr_pd4 0x0000000c
-#define regk_gio_intr_pd5 0x0000000c
-#define regk_gio_intr_pd6 0x0000000c
-#define regk_gio_intr_pd7 0x0000000c
-#define regk_gio_intr_pd8 0x0000000d
-#define regk_gio_intr_pd9 0x0000000d
-#define regk_gio_lo 0x00000002
-#define regk_gio_lsb 0x00000000
-#define regk_gio_msb 0x00000001
-#define regk_gio_negedge 0x00000006
-#define regk_gio_no 0x00000000
-#define regk_gio_no_switch 0x0000003f
-#define regk_gio_none 0x00000007
-#define regk_gio_off 0x00000000
-#define regk_gio_opendrain 0x00000000
-#define regk_gio_out 0x00000001
-#define regk_gio_posedge 0x00000005
-#define regk_gio_pwm_hfp 0x00000002
-#define regk_gio_pwm_pa0 0x00000001
-#define regk_gio_pwm_pa19 0x00000004
-#define regk_gio_pwm_pa6 0x00000002
-#define regk_gio_pwm_pa7 0x00000003
-#define regk_gio_pwm_pb26 0x00000005
-#define regk_gio_pwm_pd23 0x00000006
-#define regk_gio_pwm_pd31 0x00000007
-#define regk_gio_pwm_std 0x00000001
-#define regk_gio_pwm_var 0x00000003
-#define regk_gio_rw_i2c0_cfg_default 0x00000020
-#define regk_gio_rw_i2c0_ctrl_default 0x00010000
-#define regk_gio_rw_i2c0_start_default 0x00000000
-#define regk_gio_rw_i2c1_cfg_default 0x00000aa0
-#define regk_gio_rw_i2c1_ctrl_default 0x00010000
-#define regk_gio_rw_i2c1_start_default 0x00000000
-#define regk_gio_rw_intr_cfg_default 0x00000000
-#define regk_gio_rw_intr_mask_default 0x00000000
-#define regk_gio_rw_pa_oe_default 0x00000000
-#define regk_gio_rw_pb_oe_default 0x00000000
-#define regk_gio_rw_pc_oe_default 0x00000000
-#define regk_gio_rw_ppwm_data_default 0x00000000
-#define regk_gio_rw_pwm0_ctrl_default 0x00000000
-#define regk_gio_rw_pwm1_ctrl_default 0x00000000
-#define regk_gio_rw_pwm2_ctrl_default 0x00000000
-#define regk_gio_rw_pwm_in_cfg_default 0x00000000
-#define regk_gio_sda0 0x00000000
-#define regk_gio_sda1 0x00000001
-#define regk_gio_sda2 0x00000002
-#define regk_gio_sda3 0x00000003
-#define regk_gio_sen 0x00000000
-#define regk_gio_set 0x00000003
-#define regk_gio_yes 0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index a73168a8e93a..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,573 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: pinmux.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___eth___lsb 0
-#define reg_pinmux_rw_hwprot___eth___width 1
-#define reg_pinmux_rw_hwprot___eth___bit 0
-#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1
-#define reg_pinmux_rw_hwprot___eth_mdio___width 1
-#define reg_pinmux_rw_hwprot___eth_mdio___bit 1
-#define reg_pinmux_rw_hwprot___geth___lsb 2
-#define reg_pinmux_rw_hwprot___geth___width 1
-#define reg_pinmux_rw_hwprot___geth___bit 2
-#define reg_pinmux_rw_hwprot___tg___lsb 3
-#define reg_pinmux_rw_hwprot___tg___width 1
-#define reg_pinmux_rw_hwprot___tg___bit 3
-#define reg_pinmux_rw_hwprot___tg_clk___lsb 4
-#define reg_pinmux_rw_hwprot___tg_clk___width 1
-#define reg_pinmux_rw_hwprot___tg_clk___bit 4
-#define reg_pinmux_rw_hwprot___vout___lsb 5
-#define reg_pinmux_rw_hwprot___vout___width 1
-#define reg_pinmux_rw_hwprot___vout___bit 5
-#define reg_pinmux_rw_hwprot___vout_sync___lsb 6
-#define reg_pinmux_rw_hwprot___vout_sync___width 1
-#define reg_pinmux_rw_hwprot___vout_sync___bit 6
-#define reg_pinmux_rw_hwprot___ser1___lsb 7
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 7
-#define reg_pinmux_rw_hwprot___ser2___lsb 8
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 8
-#define reg_pinmux_rw_hwprot___ser3___lsb 9
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 9
-#define reg_pinmux_rw_hwprot___ser4___lsb 10
-#define reg_pinmux_rw_hwprot___ser4___width 1
-#define reg_pinmux_rw_hwprot___ser4___bit 10
-#define reg_pinmux_rw_hwprot___sser___lsb 11
-#define reg_pinmux_rw_hwprot___sser___width 1
-#define reg_pinmux_rw_hwprot___sser___bit 11
-#define reg_pinmux_rw_hwprot___pwm0___lsb 12
-#define reg_pinmux_rw_hwprot___pwm0___width 1
-#define reg_pinmux_rw_hwprot___pwm0___bit 12
-#define reg_pinmux_rw_hwprot___pwm1___lsb 13
-#define reg_pinmux_rw_hwprot___pwm1___width 1
-#define reg_pinmux_rw_hwprot___pwm1___bit 13
-#define reg_pinmux_rw_hwprot___pwm2___lsb 14
-#define reg_pinmux_rw_hwprot___pwm2___width 1
-#define reg_pinmux_rw_hwprot___pwm2___bit 14
-#define reg_pinmux_rw_hwprot___timer0___lsb 15
-#define reg_pinmux_rw_hwprot___timer0___width 1
-#define reg_pinmux_rw_hwprot___timer0___bit 15
-#define reg_pinmux_rw_hwprot___timer1___lsb 16
-#define reg_pinmux_rw_hwprot___timer1___width 1
-#define reg_pinmux_rw_hwprot___timer1___bit 16
-#define reg_pinmux_rw_hwprot___pio___lsb 17
-#define reg_pinmux_rw_hwprot___pio___width 1
-#define reg_pinmux_rw_hwprot___pio___bit 17
-#define reg_pinmux_rw_hwprot___i2c0___lsb 18
-#define reg_pinmux_rw_hwprot___i2c0___width 1
-#define reg_pinmux_rw_hwprot___i2c0___bit 18
-#define reg_pinmux_rw_hwprot___i2c1___lsb 19
-#define reg_pinmux_rw_hwprot___i2c1___width 1
-#define reg_pinmux_rw_hwprot___i2c1___bit 19
-#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20
-#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20
-#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21
-#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21
-#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22
-#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22
-#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23
-#define reg_pinmux_rw_hwprot___i2c1_sen___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23
-#define reg_pinmux_rw_hwprot_offset 0
-
-/* Register rw_gio_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pa___pa0___lsb 0
-#define reg_pinmux_rw_gio_pa___pa0___width 1
-#define reg_pinmux_rw_gio_pa___pa0___bit 0
-#define reg_pinmux_rw_gio_pa___pa1___lsb 1
-#define reg_pinmux_rw_gio_pa___pa1___width 1
-#define reg_pinmux_rw_gio_pa___pa1___bit 1
-#define reg_pinmux_rw_gio_pa___pa2___lsb 2
-#define reg_pinmux_rw_gio_pa___pa2___width 1
-#define reg_pinmux_rw_gio_pa___pa2___bit 2
-#define reg_pinmux_rw_gio_pa___pa3___lsb 3
-#define reg_pinmux_rw_gio_pa___pa3___width 1
-#define reg_pinmux_rw_gio_pa___pa3___bit 3
-#define reg_pinmux_rw_gio_pa___pa4___lsb 4
-#define reg_pinmux_rw_gio_pa___pa4___width 1
-#define reg_pinmux_rw_gio_pa___pa4___bit 4
-#define reg_pinmux_rw_gio_pa___pa5___lsb 5
-#define reg_pinmux_rw_gio_pa___pa5___width 1
-#define reg_pinmux_rw_gio_pa___pa5___bit 5
-#define reg_pinmux_rw_gio_pa___pa6___lsb 6
-#define reg_pinmux_rw_gio_pa___pa6___width 1
-#define reg_pinmux_rw_gio_pa___pa6___bit 6
-#define reg_pinmux_rw_gio_pa___pa7___lsb 7
-#define reg_pinmux_rw_gio_pa___pa7___width 1
-#define reg_pinmux_rw_gio_pa___pa7___bit 7
-#define reg_pinmux_rw_gio_pa___pa8___lsb 8
-#define reg_pinmux_rw_gio_pa___pa8___width 1
-#define reg_pinmux_rw_gio_pa___pa8___bit 8
-#define reg_pinmux_rw_gio_pa___pa9___lsb 9
-#define reg_pinmux_rw_gio_pa___pa9___width 1
-#define reg_pinmux_rw_gio_pa___pa9___bit 9
-#define reg_pinmux_rw_gio_pa___pa10___lsb 10
-#define reg_pinmux_rw_gio_pa___pa10___width 1
-#define reg_pinmux_rw_gio_pa___pa10___bit 10
-#define reg_pinmux_rw_gio_pa___pa11___lsb 11
-#define reg_pinmux_rw_gio_pa___pa11___width 1
-#define reg_pinmux_rw_gio_pa___pa11___bit 11
-#define reg_pinmux_rw_gio_pa___pa12___lsb 12
-#define reg_pinmux_rw_gio_pa___pa12___width 1
-#define reg_pinmux_rw_gio_pa___pa12___bit 12
-#define reg_pinmux_rw_gio_pa___pa13___lsb 13
-#define reg_pinmux_rw_gio_pa___pa13___width 1
-#define reg_pinmux_rw_gio_pa___pa13___bit 13
-#define reg_pinmux_rw_gio_pa___pa14___lsb 14
-#define reg_pinmux_rw_gio_pa___pa14___width 1
-#define reg_pinmux_rw_gio_pa___pa14___bit 14
-#define reg_pinmux_rw_gio_pa___pa15___lsb 15
-#define reg_pinmux_rw_gio_pa___pa15___width 1
-#define reg_pinmux_rw_gio_pa___pa15___bit 15
-#define reg_pinmux_rw_gio_pa___pa16___lsb 16
-#define reg_pinmux_rw_gio_pa___pa16___width 1
-#define reg_pinmux_rw_gio_pa___pa16___bit 16
-#define reg_pinmux_rw_gio_pa___pa17___lsb 17
-#define reg_pinmux_rw_gio_pa___pa17___width 1
-#define reg_pinmux_rw_gio_pa___pa17___bit 17
-#define reg_pinmux_rw_gio_pa___pa18___lsb 18
-#define reg_pinmux_rw_gio_pa___pa18___width 1
-#define reg_pinmux_rw_gio_pa___pa18___bit 18
-#define reg_pinmux_rw_gio_pa___pa19___lsb 19
-#define reg_pinmux_rw_gio_pa___pa19___width 1
-#define reg_pinmux_rw_gio_pa___pa19___bit 19
-#define reg_pinmux_rw_gio_pa___pa20___lsb 20
-#define reg_pinmux_rw_gio_pa___pa20___width 1
-#define reg_pinmux_rw_gio_pa___pa20___bit 20
-#define reg_pinmux_rw_gio_pa___pa21___lsb 21
-#define reg_pinmux_rw_gio_pa___pa21___width 1
-#define reg_pinmux_rw_gio_pa___pa21___bit 21
-#define reg_pinmux_rw_gio_pa___pa22___lsb 22
-#define reg_pinmux_rw_gio_pa___pa22___width 1
-#define reg_pinmux_rw_gio_pa___pa22___bit 22
-#define reg_pinmux_rw_gio_pa___pa23___lsb 23
-#define reg_pinmux_rw_gio_pa___pa23___width 1
-#define reg_pinmux_rw_gio_pa___pa23___bit 23
-#define reg_pinmux_rw_gio_pa___pa24___lsb 24
-#define reg_pinmux_rw_gio_pa___pa24___width 1
-#define reg_pinmux_rw_gio_pa___pa24___bit 24
-#define reg_pinmux_rw_gio_pa___pa25___lsb 25
-#define reg_pinmux_rw_gio_pa___pa25___width 1
-#define reg_pinmux_rw_gio_pa___pa25___bit 25
-#define reg_pinmux_rw_gio_pa___pa26___lsb 26
-#define reg_pinmux_rw_gio_pa___pa26___width 1
-#define reg_pinmux_rw_gio_pa___pa26___bit 26
-#define reg_pinmux_rw_gio_pa___pa27___lsb 27
-#define reg_pinmux_rw_gio_pa___pa27___width 1
-#define reg_pinmux_rw_gio_pa___pa27___bit 27
-#define reg_pinmux_rw_gio_pa___pa28___lsb 28
-#define reg_pinmux_rw_gio_pa___pa28___width 1
-#define reg_pinmux_rw_gio_pa___pa28___bit 28
-#define reg_pinmux_rw_gio_pa___pa29___lsb 29
-#define reg_pinmux_rw_gio_pa___pa29___width 1
-#define reg_pinmux_rw_gio_pa___pa29___bit 29
-#define reg_pinmux_rw_gio_pa___pa30___lsb 30
-#define reg_pinmux_rw_gio_pa___pa30___width 1
-#define reg_pinmux_rw_gio_pa___pa30___bit 30
-#define reg_pinmux_rw_gio_pa___pa31___lsb 31
-#define reg_pinmux_rw_gio_pa___pa31___width 1
-#define reg_pinmux_rw_gio_pa___pa31___bit 31
-#define reg_pinmux_rw_gio_pa_offset 4
-
-/* Register rw_gio_pb, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pb___pb0___lsb 0
-#define reg_pinmux_rw_gio_pb___pb0___width 1
-#define reg_pinmux_rw_gio_pb___pb0___bit 0
-#define reg_pinmux_rw_gio_pb___pb1___lsb 1
-#define reg_pinmux_rw_gio_pb___pb1___width 1
-#define reg_pinmux_rw_gio_pb___pb1___bit 1
-#define reg_pinmux_rw_gio_pb___pb2___lsb 2
-#define reg_pinmux_rw_gio_pb___pb2___width 1
-#define reg_pinmux_rw_gio_pb___pb2___bit 2
-#define reg_pinmux_rw_gio_pb___pb3___lsb 3
-#define reg_pinmux_rw_gio_pb___pb3___width 1
-#define reg_pinmux_rw_gio_pb___pb3___bit 3
-#define reg_pinmux_rw_gio_pb___pb4___lsb 4
-#define reg_pinmux_rw_gio_pb___pb4___width 1
-#define reg_pinmux_rw_gio_pb___pb4___bit 4
-#define reg_pinmux_rw_gio_pb___pb5___lsb 5
-#define reg_pinmux_rw_gio_pb___pb5___width 1
-#define reg_pinmux_rw_gio_pb___pb5___bit 5
-#define reg_pinmux_rw_gio_pb___pb6___lsb 6
-#define reg_pinmux_rw_gio_pb___pb6___width 1
-#define reg_pinmux_rw_gio_pb___pb6___bit 6
-#define reg_pinmux_rw_gio_pb___pb7___lsb 7
-#define reg_pinmux_rw_gio_pb___pb7___width 1
-#define reg_pinmux_rw_gio_pb___pb7___bit 7
-#define reg_pinmux_rw_gio_pb___pb8___lsb 8
-#define reg_pinmux_rw_gio_pb___pb8___width 1
-#define reg_pinmux_rw_gio_pb___pb8___bit 8
-#define reg_pinmux_rw_gio_pb___pb9___lsb 9
-#define reg_pinmux_rw_gio_pb___pb9___width 1
-#define reg_pinmux_rw_gio_pb___pb9___bit 9
-#define reg_pinmux_rw_gio_pb___pb10___lsb 10
-#define reg_pinmux_rw_gio_pb___pb10___width 1
-#define reg_pinmux_rw_gio_pb___pb10___bit 10
-#define reg_pinmux_rw_gio_pb___pb11___lsb 11
-#define reg_pinmux_rw_gio_pb___pb11___width 1
-#define reg_pinmux_rw_gio_pb___pb11___bit 11
-#define reg_pinmux_rw_gio_pb___pb12___lsb 12
-#define reg_pinmux_rw_gio_pb___pb12___width 1
-#define reg_pinmux_rw_gio_pb___pb12___bit 12
-#define reg_pinmux_rw_gio_pb___pb13___lsb 13
-#define reg_pinmux_rw_gio_pb___pb13___width 1
-#define reg_pinmux_rw_gio_pb___pb13___bit 13
-#define reg_pinmux_rw_gio_pb___pb14___lsb 14
-#define reg_pinmux_rw_gio_pb___pb14___width 1
-#define reg_pinmux_rw_gio_pb___pb14___bit 14
-#define reg_pinmux_rw_gio_pb___pb15___lsb 15
-#define reg_pinmux_rw_gio_pb___pb15___width 1
-#define reg_pinmux_rw_gio_pb___pb15___bit 15
-#define reg_pinmux_rw_gio_pb___pb16___lsb 16
-#define reg_pinmux_rw_gio_pb___pb16___width 1
-#define reg_pinmux_rw_gio_pb___pb16___bit 16
-#define reg_pinmux_rw_gio_pb___pb17___lsb 17
-#define reg_pinmux_rw_gio_pb___pb17___width 1
-#define reg_pinmux_rw_gio_pb___pb17___bit 17
-#define reg_pinmux_rw_gio_pb___pb18___lsb 18
-#define reg_pinmux_rw_gio_pb___pb18___width 1
-#define reg_pinmux_rw_gio_pb___pb18___bit 18
-#define reg_pinmux_rw_gio_pb___pb19___lsb 19
-#define reg_pinmux_rw_gio_pb___pb19___width 1
-#define reg_pinmux_rw_gio_pb___pb19___bit 19
-#define reg_pinmux_rw_gio_pb___pb20___lsb 20
-#define reg_pinmux_rw_gio_pb___pb20___width 1
-#define reg_pinmux_rw_gio_pb___pb20___bit 20
-#define reg_pinmux_rw_gio_pb___pb21___lsb 21
-#define reg_pinmux_rw_gio_pb___pb21___width 1
-#define reg_pinmux_rw_gio_pb___pb21___bit 21
-#define reg_pinmux_rw_gio_pb___pb22___lsb 22
-#define reg_pinmux_rw_gio_pb___pb22___width 1
-#define reg_pinmux_rw_gio_pb___pb22___bit 22
-#define reg_pinmux_rw_gio_pb___pb23___lsb 23
-#define reg_pinmux_rw_gio_pb___pb23___width 1
-#define reg_pinmux_rw_gio_pb___pb23___bit 23
-#define reg_pinmux_rw_gio_pb___pb24___lsb 24
-#define reg_pinmux_rw_gio_pb___pb24___width 1
-#define reg_pinmux_rw_gio_pb___pb24___bit 24
-#define reg_pinmux_rw_gio_pb___pb25___lsb 25
-#define reg_pinmux_rw_gio_pb___pb25___width 1
-#define reg_pinmux_rw_gio_pb___pb25___bit 25
-#define reg_pinmux_rw_gio_pb___pb26___lsb 26
-#define reg_pinmux_rw_gio_pb___pb26___width 1
-#define reg_pinmux_rw_gio_pb___pb26___bit 26
-#define reg_pinmux_rw_gio_pb___pb27___lsb 27
-#define reg_pinmux_rw_gio_pb___pb27___width 1
-#define reg_pinmux_rw_gio_pb___pb27___bit 27
-#define reg_pinmux_rw_gio_pb___pb28___lsb 28
-#define reg_pinmux_rw_gio_pb___pb28___width 1
-#define reg_pinmux_rw_gio_pb___pb28___bit 28
-#define reg_pinmux_rw_gio_pb___pb29___lsb 29
-#define reg_pinmux_rw_gio_pb___pb29___width 1
-#define reg_pinmux_rw_gio_pb___pb29___bit 29
-#define reg_pinmux_rw_gio_pb___pb30___lsb 30
-#define reg_pinmux_rw_gio_pb___pb30___width 1
-#define reg_pinmux_rw_gio_pb___pb30___bit 30
-#define reg_pinmux_rw_gio_pb___pb31___lsb 31
-#define reg_pinmux_rw_gio_pb___pb31___width 1
-#define reg_pinmux_rw_gio_pb___pb31___bit 31
-#define reg_pinmux_rw_gio_pb_offset 8
-
-/* Register rw_gio_pc, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pc___pc0___lsb 0
-#define reg_pinmux_rw_gio_pc___pc0___width 1
-#define reg_pinmux_rw_gio_pc___pc0___bit 0
-#define reg_pinmux_rw_gio_pc___pc1___lsb 1
-#define reg_pinmux_rw_gio_pc___pc1___width 1
-#define reg_pinmux_rw_gio_pc___pc1___bit 1
-#define reg_pinmux_rw_gio_pc___pc2___lsb 2
-#define reg_pinmux_rw_gio_pc___pc2___width 1
-#define reg_pinmux_rw_gio_pc___pc2___bit 2
-#define reg_pinmux_rw_gio_pc___pc3___lsb 3
-#define reg_pinmux_rw_gio_pc___pc3___width 1
-#define reg_pinmux_rw_gio_pc___pc3___bit 3
-#define reg_pinmux_rw_gio_pc___pc4___lsb 4
-#define reg_pinmux_rw_gio_pc___pc4___width 1
-#define reg_pinmux_rw_gio_pc___pc4___bit 4
-#define reg_pinmux_rw_gio_pc___pc5___lsb 5
-#define reg_pinmux_rw_gio_pc___pc5___width 1
-#define reg_pinmux_rw_gio_pc___pc5___bit 5
-#define reg_pinmux_rw_gio_pc___pc6___lsb 6
-#define reg_pinmux_rw_gio_pc___pc6___width 1
-#define reg_pinmux_rw_gio_pc___pc6___bit 6
-#define reg_pinmux_rw_gio_pc___pc7___lsb 7
-#define reg_pinmux_rw_gio_pc___pc7___width 1
-#define reg_pinmux_rw_gio_pc___pc7___bit 7
-#define reg_pinmux_rw_gio_pc___pc8___lsb 8
-#define reg_pinmux_rw_gio_pc___pc8___width 1
-#define reg_pinmux_rw_gio_pc___pc8___bit 8
-#define reg_pinmux_rw_gio_pc___pc9___lsb 9
-#define reg_pinmux_rw_gio_pc___pc9___width 1
-#define reg_pinmux_rw_gio_pc___pc9___bit 9
-#define reg_pinmux_rw_gio_pc___pc10___lsb 10
-#define reg_pinmux_rw_gio_pc___pc10___width 1
-#define reg_pinmux_rw_gio_pc___pc10___bit 10
-#define reg_pinmux_rw_gio_pc___pc11___lsb 11
-#define reg_pinmux_rw_gio_pc___pc11___width 1
-#define reg_pinmux_rw_gio_pc___pc11___bit 11
-#define reg_pinmux_rw_gio_pc___pc12___lsb 12
-#define reg_pinmux_rw_gio_pc___pc12___width 1
-#define reg_pinmux_rw_gio_pc___pc12___bit 12
-#define reg_pinmux_rw_gio_pc___pc13___lsb 13
-#define reg_pinmux_rw_gio_pc___pc13___width 1
-#define reg_pinmux_rw_gio_pc___pc13___bit 13
-#define reg_pinmux_rw_gio_pc___pc14___lsb 14
-#define reg_pinmux_rw_gio_pc___pc14___width 1
-#define reg_pinmux_rw_gio_pc___pc14___bit 14
-#define reg_pinmux_rw_gio_pc___pc15___lsb 15
-#define reg_pinmux_rw_gio_pc___pc15___width 1
-#define reg_pinmux_rw_gio_pc___pc15___bit 15
-#define reg_pinmux_rw_gio_pc_offset 12
-
-/* Register rw_iop_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pa___pa0___lsb 0
-#define reg_pinmux_rw_iop_pa___pa0___width 1
-#define reg_pinmux_rw_iop_pa___pa0___bit 0
-#define reg_pinmux_rw_iop_pa___pa1___lsb 1
-#define reg_pinmux_rw_iop_pa___pa1___width 1
-#define reg_pinmux_rw_iop_pa___pa1___bit 1
-#define reg_pinmux_rw_iop_pa___pa2___lsb 2
-#define reg_pinmux_rw_iop_pa___pa2___width 1
-#define reg_pinmux_rw_iop_pa___pa2___bit 2
-#define reg_pinmux_rw_iop_pa___pa3___lsb 3
-#define reg_pinmux_rw_iop_pa___pa3___width 1
-#define reg_pinmux_rw_iop_pa___pa3___bit 3
-#define reg_pinmux_rw_iop_pa___pa4___lsb 4
-#define reg_pinmux_rw_iop_pa___pa4___width 1
-#define reg_pinmux_rw_iop_pa___pa4___bit 4
-#define reg_pinmux_rw_iop_pa___pa5___lsb 5
-#define reg_pinmux_rw_iop_pa___pa5___width 1
-#define reg_pinmux_rw_iop_pa___pa5___bit 5
-#define reg_pinmux_rw_iop_pa___pa6___lsb 6
-#define reg_pinmux_rw_iop_pa___pa6___width 1
-#define reg_pinmux_rw_iop_pa___pa6___bit 6
-#define reg_pinmux_rw_iop_pa___pa7___lsb 7
-#define reg_pinmux_rw_iop_pa___pa7___width 1
-#define reg_pinmux_rw_iop_pa___pa7___bit 7
-#define reg_pinmux_rw_iop_pa___pa8___lsb 8
-#define reg_pinmux_rw_iop_pa___pa8___width 1
-#define reg_pinmux_rw_iop_pa___pa8___bit 8
-#define reg_pinmux_rw_iop_pa___pa9___lsb 9
-#define reg_pinmux_rw_iop_pa___pa9___width 1
-#define reg_pinmux_rw_iop_pa___pa9___bit 9
-#define reg_pinmux_rw_iop_pa___pa10___lsb 10
-#define reg_pinmux_rw_iop_pa___pa10___width 1
-#define reg_pinmux_rw_iop_pa___pa10___bit 10
-#define reg_pinmux_rw_iop_pa___pa11___lsb 11
-#define reg_pinmux_rw_iop_pa___pa11___width 1
-#define reg_pinmux_rw_iop_pa___pa11___bit 11
-#define reg_pinmux_rw_iop_pa___pa12___lsb 12
-#define reg_pinmux_rw_iop_pa___pa12___width 1
-#define reg_pinmux_rw_iop_pa___pa12___bit 12
-#define reg_pinmux_rw_iop_pa___pa13___lsb 13
-#define reg_pinmux_rw_iop_pa___pa13___width 1
-#define reg_pinmux_rw_iop_pa___pa13___bit 13
-#define reg_pinmux_rw_iop_pa___pa14___lsb 14
-#define reg_pinmux_rw_iop_pa___pa14___width 1
-#define reg_pinmux_rw_iop_pa___pa14___bit 14
-#define reg_pinmux_rw_iop_pa___pa15___lsb 15
-#define reg_pinmux_rw_iop_pa___pa15___width 1
-#define reg_pinmux_rw_iop_pa___pa15___bit 15
-#define reg_pinmux_rw_iop_pa___pa16___lsb 16
-#define reg_pinmux_rw_iop_pa___pa16___width 1
-#define reg_pinmux_rw_iop_pa___pa16___bit 16
-#define reg_pinmux_rw_iop_pa___pa17___lsb 17
-#define reg_pinmux_rw_iop_pa___pa17___width 1
-#define reg_pinmux_rw_iop_pa___pa17___bit 17
-#define reg_pinmux_rw_iop_pa___pa18___lsb 18
-#define reg_pinmux_rw_iop_pa___pa18___width 1
-#define reg_pinmux_rw_iop_pa___pa18___bit 18
-#define reg_pinmux_rw_iop_pa___pa19___lsb 19
-#define reg_pinmux_rw_iop_pa___pa19___width 1
-#define reg_pinmux_rw_iop_pa___pa19___bit 19
-#define reg_pinmux_rw_iop_pa___pa20___lsb 20
-#define reg_pinmux_rw_iop_pa___pa20___width 1
-#define reg_pinmux_rw_iop_pa___pa20___bit 20
-#define reg_pinmux_rw_iop_pa___pa21___lsb 21
-#define reg_pinmux_rw_iop_pa___pa21___width 1
-#define reg_pinmux_rw_iop_pa___pa21___bit 21
-#define reg_pinmux_rw_iop_pa___pa22___lsb 22
-#define reg_pinmux_rw_iop_pa___pa22___width 1
-#define reg_pinmux_rw_iop_pa___pa22___bit 22
-#define reg_pinmux_rw_iop_pa___pa23___lsb 23
-#define reg_pinmux_rw_iop_pa___pa23___width 1
-#define reg_pinmux_rw_iop_pa___pa23___bit 23
-#define reg_pinmux_rw_iop_pa___pa24___lsb 24
-#define reg_pinmux_rw_iop_pa___pa24___width 1
-#define reg_pinmux_rw_iop_pa___pa24___bit 24
-#define reg_pinmux_rw_iop_pa___pa25___lsb 25
-#define reg_pinmux_rw_iop_pa___pa25___width 1
-#define reg_pinmux_rw_iop_pa___pa25___bit 25
-#define reg_pinmux_rw_iop_pa___pa26___lsb 26
-#define reg_pinmux_rw_iop_pa___pa26___width 1
-#define reg_pinmux_rw_iop_pa___pa26___bit 26
-#define reg_pinmux_rw_iop_pa___pa27___lsb 27
-#define reg_pinmux_rw_iop_pa___pa27___width 1
-#define reg_pinmux_rw_iop_pa___pa27___bit 27
-#define reg_pinmux_rw_iop_pa___pa28___lsb 28
-#define reg_pinmux_rw_iop_pa___pa28___width 1
-#define reg_pinmux_rw_iop_pa___pa28___bit 28
-#define reg_pinmux_rw_iop_pa___pa29___lsb 29
-#define reg_pinmux_rw_iop_pa___pa29___width 1
-#define reg_pinmux_rw_iop_pa___pa29___bit 29
-#define reg_pinmux_rw_iop_pa___pa30___lsb 30
-#define reg_pinmux_rw_iop_pa___pa30___width 1
-#define reg_pinmux_rw_iop_pa___pa30___bit 30
-#define reg_pinmux_rw_iop_pa___pa31___lsb 31
-#define reg_pinmux_rw_iop_pa___pa31___width 1
-#define reg_pinmux_rw_iop_pa___pa31___bit 31
-#define reg_pinmux_rw_iop_pa_offset 16
-
-/* Register rw_iop_pb, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pb___pb0___lsb 0
-#define reg_pinmux_rw_iop_pb___pb0___width 1
-#define reg_pinmux_rw_iop_pb___pb0___bit 0
-#define reg_pinmux_rw_iop_pb___pb1___lsb 1
-#define reg_pinmux_rw_iop_pb___pb1___width 1
-#define reg_pinmux_rw_iop_pb___pb1___bit 1
-#define reg_pinmux_rw_iop_pb___pb2___lsb 2
-#define reg_pinmux_rw_iop_pb___pb2___width 1
-#define reg_pinmux_rw_iop_pb___pb2___bit 2
-#define reg_pinmux_rw_iop_pb___pb3___lsb 3
-#define reg_pinmux_rw_iop_pb___pb3___width 1
-#define reg_pinmux_rw_iop_pb___pb3___bit 3
-#define reg_pinmux_rw_iop_pb___pb4___lsb 4
-#define reg_pinmux_rw_iop_pb___pb4___width 1
-#define reg_pinmux_rw_iop_pb___pb4___bit 4
-#define reg_pinmux_rw_iop_pb___pb5___lsb 5
-#define reg_pinmux_rw_iop_pb___pb5___width 1
-#define reg_pinmux_rw_iop_pb___pb5___bit 5
-#define reg_pinmux_rw_iop_pb___pb6___lsb 6
-#define reg_pinmux_rw_iop_pb___pb6___width 1
-#define reg_pinmux_rw_iop_pb___pb6___bit 6
-#define reg_pinmux_rw_iop_pb___pb7___lsb 7
-#define reg_pinmux_rw_iop_pb___pb7___width 1
-#define reg_pinmux_rw_iop_pb___pb7___bit 7
-#define reg_pinmux_rw_iop_pb_offset 20
-
-/* Register rw_iop_pio, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pio___d0___lsb 0
-#define reg_pinmux_rw_iop_pio___d0___width 1
-#define reg_pinmux_rw_iop_pio___d0___bit 0
-#define reg_pinmux_rw_iop_pio___d1___lsb 1
-#define reg_pinmux_rw_iop_pio___d1___width 1
-#define reg_pinmux_rw_iop_pio___d1___bit 1
-#define reg_pinmux_rw_iop_pio___d2___lsb 2
-#define reg_pinmux_rw_iop_pio___d2___width 1
-#define reg_pinmux_rw_iop_pio___d2___bit 2
-#define reg_pinmux_rw_iop_pio___d3___lsb 3
-#define reg_pinmux_rw_iop_pio___d3___width 1
-#define reg_pinmux_rw_iop_pio___d3___bit 3
-#define reg_pinmux_rw_iop_pio___d4___lsb 4
-#define reg_pinmux_rw_iop_pio___d4___width 1
-#define reg_pinmux_rw_iop_pio___d4___bit 4
-#define reg_pinmux_rw_iop_pio___d5___lsb 5
-#define reg_pinmux_rw_iop_pio___d5___width 1
-#define reg_pinmux_rw_iop_pio___d5___bit 5
-#define reg_pinmux_rw_iop_pio___d6___lsb 6
-#define reg_pinmux_rw_iop_pio___d6___width 1
-#define reg_pinmux_rw_iop_pio___d6___bit 6
-#define reg_pinmux_rw_iop_pio___d7___lsb 7
-#define reg_pinmux_rw_iop_pio___d7___width 1
-#define reg_pinmux_rw_iop_pio___d7___bit 7
-#define reg_pinmux_rw_iop_pio___rd_n___lsb 8
-#define reg_pinmux_rw_iop_pio___rd_n___width 1
-#define reg_pinmux_rw_iop_pio___rd_n___bit 8
-#define reg_pinmux_rw_iop_pio___wr_n___lsb 9
-#define reg_pinmux_rw_iop_pio___wr_n___width 1
-#define reg_pinmux_rw_iop_pio___wr_n___bit 9
-#define reg_pinmux_rw_iop_pio___a0___lsb 10
-#define reg_pinmux_rw_iop_pio___a0___width 1
-#define reg_pinmux_rw_iop_pio___a0___bit 10
-#define reg_pinmux_rw_iop_pio___a1___lsb 11
-#define reg_pinmux_rw_iop_pio___a1___width 1
-#define reg_pinmux_rw_iop_pio___a1___bit 11
-#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12
-#define reg_pinmux_rw_iop_pio___ce0_n___width 1
-#define reg_pinmux_rw_iop_pio___ce0_n___bit 12
-#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13
-#define reg_pinmux_rw_iop_pio___ce1_n___width 1
-#define reg_pinmux_rw_iop_pio___ce1_n___bit 13
-#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14
-#define reg_pinmux_rw_iop_pio___ce2_n___width 1
-#define reg_pinmux_rw_iop_pio___ce2_n___bit 14
-#define reg_pinmux_rw_iop_pio___rdy___lsb 15
-#define reg_pinmux_rw_iop_pio___rdy___width 1
-#define reg_pinmux_rw_iop_pio___rdy___bit 15
-#define reg_pinmux_rw_iop_pio_offset 24
-
-/* Register rw_iop_usb, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_usb___usb0___lsb 0
-#define reg_pinmux_rw_iop_usb___usb0___width 1
-#define reg_pinmux_rw_iop_usb___usb0___bit 0
-#define reg_pinmux_rw_iop_usb_offset 28
-
-
-/* Constants */
-#define regk_pinmux_no 0x00000000
-#define regk_pinmux_rw_gio_pa_default 0x00000000
-#define regk_pinmux_rw_gio_pb_default 0x00000000
-#define regk_pinmux_rw_gio_pc_default 0x00000000
-#define regk_pinmux_rw_hwprot_default 0x00000000
-#define regk_pinmux_rw_iop_pa_default 0x00000000
-#define regk_pinmux_rw_iop_pb_default 0x00000000
-#define regk_pinmux_rw_iop_pio_default 0x00000000
-#define regk_pinmux_rw_iop_usb_default 0x00000001
-#define regk_pinmux_yes 0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h
deleted file mode 100644
index 463bb9e2c38e..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pio_defs_asm_h
-#define __pio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: pio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_data, scope pio, type rw */
-#define reg_pio_rw_data_offset 64
-
-/* Register rw_io_access0, scope pio, type rw */
-#define reg_pio_rw_io_access0___data___lsb 0
-#define reg_pio_rw_io_access0___data___width 8
-#define reg_pio_rw_io_access0_offset 0
-
-/* Register rw_io_access1, scope pio, type rw */
-#define reg_pio_rw_io_access1___data___lsb 0
-#define reg_pio_rw_io_access1___data___width 8
-#define reg_pio_rw_io_access1_offset 4
-
-/* Register rw_io_access2, scope pio, type rw */
-#define reg_pio_rw_io_access2___data___lsb 0
-#define reg_pio_rw_io_access2___data___width 8
-#define reg_pio_rw_io_access2_offset 8
-
-/* Register rw_io_access3, scope pio, type rw */
-#define reg_pio_rw_io_access3___data___lsb 0
-#define reg_pio_rw_io_access3___data___width 8
-#define reg_pio_rw_io_access3_offset 12
-
-/* Register rw_io_access4, scope pio, type rw */
-#define reg_pio_rw_io_access4___data___lsb 0
-#define reg_pio_rw_io_access4___data___width 8
-#define reg_pio_rw_io_access4_offset 16
-
-/* Register rw_io_access5, scope pio, type rw */
-#define reg_pio_rw_io_access5___data___lsb 0
-#define reg_pio_rw_io_access5___data___width 8
-#define reg_pio_rw_io_access5_offset 20
-
-/* Register rw_io_access6, scope pio, type rw */
-#define reg_pio_rw_io_access6___data___lsb 0
-#define reg_pio_rw_io_access6___data___width 8
-#define reg_pio_rw_io_access6_offset 24
-
-/* Register rw_io_access7, scope pio, type rw */
-#define reg_pio_rw_io_access7___data___lsb 0
-#define reg_pio_rw_io_access7___data___width 8
-#define reg_pio_rw_io_access7_offset 28
-
-/* Register rw_io_access8, scope pio, type rw */
-#define reg_pio_rw_io_access8___data___lsb 0
-#define reg_pio_rw_io_access8___data___width 8
-#define reg_pio_rw_io_access8_offset 32
-
-/* Register rw_io_access9, scope pio, type rw */
-#define reg_pio_rw_io_access9___data___lsb 0
-#define reg_pio_rw_io_access9___data___width 8
-#define reg_pio_rw_io_access9_offset 36
-
-/* Register rw_io_access10, scope pio, type rw */
-#define reg_pio_rw_io_access10___data___lsb 0
-#define reg_pio_rw_io_access10___data___width 8
-#define reg_pio_rw_io_access10_offset 40
-
-/* Register rw_io_access11, scope pio, type rw */
-#define reg_pio_rw_io_access11___data___lsb 0
-#define reg_pio_rw_io_access11___data___width 8
-#define reg_pio_rw_io_access11_offset 44
-
-/* Register rw_io_access12, scope pio, type rw */
-#define reg_pio_rw_io_access12___data___lsb 0
-#define reg_pio_rw_io_access12___data___width 8
-#define reg_pio_rw_io_access12_offset 48
-
-/* Register rw_io_access13, scope pio, type rw */
-#define reg_pio_rw_io_access13___data___lsb 0
-#define reg_pio_rw_io_access13___data___width 8
-#define reg_pio_rw_io_access13_offset 52
-
-/* Register rw_io_access14, scope pio, type rw */
-#define reg_pio_rw_io_access14___data___lsb 0
-#define reg_pio_rw_io_access14___data___width 8
-#define reg_pio_rw_io_access14_offset 56
-
-/* Register rw_io_access15, scope pio, type rw */
-#define reg_pio_rw_io_access15___data___lsb 0
-#define reg_pio_rw_io_access15___data___width 8
-#define reg_pio_rw_io_access15_offset 60
-
-/* Register rw_ce0_cfg, scope pio, type rw */
-#define reg_pio_rw_ce0_cfg___lw___lsb 0
-#define reg_pio_rw_ce0_cfg___lw___width 6
-#define reg_pio_rw_ce0_cfg___ew___lsb 6
-#define reg_pio_rw_ce0_cfg___ew___width 3
-#define reg_pio_rw_ce0_cfg___zw___lsb 9
-#define reg_pio_rw_ce0_cfg___zw___width 3
-#define reg_pio_rw_ce0_cfg___aw___lsb 12
-#define reg_pio_rw_ce0_cfg___aw___width 2
-#define reg_pio_rw_ce0_cfg___mode___lsb 14
-#define reg_pio_rw_ce0_cfg___mode___width 2
-#define reg_pio_rw_ce0_cfg_offset 68
-
-/* Register rw_ce1_cfg, scope pio, type rw */
-#define reg_pio_rw_ce1_cfg___lw___lsb 0
-#define reg_pio_rw_ce1_cfg___lw___width 6
-#define reg_pio_rw_ce1_cfg___ew___lsb 6
-#define reg_pio_rw_ce1_cfg___ew___width 3
-#define reg_pio_rw_ce1_cfg___zw___lsb 9
-#define reg_pio_rw_ce1_cfg___zw___width 3
-#define reg_pio_rw_ce1_cfg___aw___lsb 12
-#define reg_pio_rw_ce1_cfg___aw___width 2
-#define reg_pio_rw_ce1_cfg___mode___lsb 14
-#define reg_pio_rw_ce1_cfg___mode___width 2
-#define reg_pio_rw_ce1_cfg_offset 72
-
-/* Register rw_ce2_cfg, scope pio, type rw */
-#define reg_pio_rw_ce2_cfg___lw___lsb 0
-#define reg_pio_rw_ce2_cfg___lw___width 6
-#define reg_pio_rw_ce2_cfg___ew___lsb 6
-#define reg_pio_rw_ce2_cfg___ew___width 3
-#define reg_pio_rw_ce2_cfg___zw___lsb 9
-#define reg_pio_rw_ce2_cfg___zw___width 3
-#define reg_pio_rw_ce2_cfg___aw___lsb 12
-#define reg_pio_rw_ce2_cfg___aw___width 2
-#define reg_pio_rw_ce2_cfg___mode___lsb 14
-#define reg_pio_rw_ce2_cfg___mode___width 2
-#define reg_pio_rw_ce2_cfg_offset 76
-
-/* Register rw_dout, scope pio, type rw */
-#define reg_pio_rw_dout___data___lsb 0
-#define reg_pio_rw_dout___data___width 8
-#define reg_pio_rw_dout___rd_n___lsb 8
-#define reg_pio_rw_dout___rd_n___width 1
-#define reg_pio_rw_dout___rd_n___bit 8
-#define reg_pio_rw_dout___wr_n___lsb 9
-#define reg_pio_rw_dout___wr_n___width 1
-#define reg_pio_rw_dout___wr_n___bit 9
-#define reg_pio_rw_dout___a0___lsb 10
-#define reg_pio_rw_dout___a0___width 1
-#define reg_pio_rw_dout___a0___bit 10
-#define reg_pio_rw_dout___a1___lsb 11
-#define reg_pio_rw_dout___a1___width 1
-#define reg_pio_rw_dout___a1___bit 11
-#define reg_pio_rw_dout___ce0_n___lsb 12
-#define reg_pio_rw_dout___ce0_n___width 1
-#define reg_pio_rw_dout___ce0_n___bit 12
-#define reg_pio_rw_dout___ce1_n___lsb 13
-#define reg_pio_rw_dout___ce1_n___width 1
-#define reg_pio_rw_dout___ce1_n___bit 13
-#define reg_pio_rw_dout___ce2_n___lsb 14
-#define reg_pio_rw_dout___ce2_n___width 1
-#define reg_pio_rw_dout___ce2_n___bit 14
-#define reg_pio_rw_dout___rdy___lsb 15
-#define reg_pio_rw_dout___rdy___width 1
-#define reg_pio_rw_dout___rdy___bit 15
-#define reg_pio_rw_dout_offset 80
-
-/* Register rw_oe, scope pio, type rw */
-#define reg_pio_rw_oe___data___lsb 0
-#define reg_pio_rw_oe___data___width 8
-#define reg_pio_rw_oe___rd_n___lsb 8
-#define reg_pio_rw_oe___rd_n___width 1
-#define reg_pio_rw_oe___rd_n___bit 8
-#define reg_pio_rw_oe___wr_n___lsb 9
-#define reg_pio_rw_oe___wr_n___width 1
-#define reg_pio_rw_oe___wr_n___bit 9
-#define reg_pio_rw_oe___a0___lsb 10
-#define reg_pio_rw_oe___a0___width 1
-#define reg_pio_rw_oe___a0___bit 10
-#define reg_pio_rw_oe___a1___lsb 11
-#define reg_pio_rw_oe___a1___width 1
-#define reg_pio_rw_oe___a1___bit 11
-#define reg_pio_rw_oe___ce0_n___lsb 12
-#define reg_pio_rw_oe___ce0_n___width 1
-#define reg_pio_rw_oe___ce0_n___bit 12
-#define reg_pio_rw_oe___ce1_n___lsb 13
-#define reg_pio_rw_oe___ce1_n___width 1
-#define reg_pio_rw_oe___ce1_n___bit 13
-#define reg_pio_rw_oe___ce2_n___lsb 14
-#define reg_pio_rw_oe___ce2_n___width 1
-#define reg_pio_rw_oe___ce2_n___bit 14
-#define reg_pio_rw_oe___rdy___lsb 15
-#define reg_pio_rw_oe___rdy___width 1
-#define reg_pio_rw_oe___rdy___bit 15
-#define reg_pio_rw_oe_offset 84
-
-/* Register rw_man_ctrl, scope pio, type rw */
-#define reg_pio_rw_man_ctrl___data___lsb 0
-#define reg_pio_rw_man_ctrl___data___width 8
-#define reg_pio_rw_man_ctrl___rd_n___lsb 8
-#define reg_pio_rw_man_ctrl___rd_n___width 1
-#define reg_pio_rw_man_ctrl___rd_n___bit 8
-#define reg_pio_rw_man_ctrl___wr_n___lsb 9
-#define reg_pio_rw_man_ctrl___wr_n___width 1
-#define reg_pio_rw_man_ctrl___wr_n___bit 9
-#define reg_pio_rw_man_ctrl___a0___lsb 10
-#define reg_pio_rw_man_ctrl___a0___width 1
-#define reg_pio_rw_man_ctrl___a0___bit 10
-#define reg_pio_rw_man_ctrl___a1___lsb 11
-#define reg_pio_rw_man_ctrl___a1___width 1
-#define reg_pio_rw_man_ctrl___a1___bit 11
-#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
-#define reg_pio_rw_man_ctrl___ce0_n___width 1
-#define reg_pio_rw_man_ctrl___ce0_n___bit 12
-#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
-#define reg_pio_rw_man_ctrl___ce1_n___width 1
-#define reg_pio_rw_man_ctrl___ce1_n___bit 13
-#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
-#define reg_pio_rw_man_ctrl___ce2_n___width 1
-#define reg_pio_rw_man_ctrl___ce2_n___bit 14
-#define reg_pio_rw_man_ctrl___rdy___lsb 15
-#define reg_pio_rw_man_ctrl___rdy___width 1
-#define reg_pio_rw_man_ctrl___rdy___bit 15
-#define reg_pio_rw_man_ctrl_offset 88
-
-/* Register r_din, scope pio, type r */
-#define reg_pio_r_din___data___lsb 0
-#define reg_pio_r_din___data___width 8
-#define reg_pio_r_din___rd_n___lsb 8
-#define reg_pio_r_din___rd_n___width 1
-#define reg_pio_r_din___rd_n___bit 8
-#define reg_pio_r_din___wr_n___lsb 9
-#define reg_pio_r_din___wr_n___width 1
-#define reg_pio_r_din___wr_n___bit 9
-#define reg_pio_r_din___a0___lsb 10
-#define reg_pio_r_din___a0___width 1
-#define reg_pio_r_din___a0___bit 10
-#define reg_pio_r_din___a1___lsb 11
-#define reg_pio_r_din___a1___width 1
-#define reg_pio_r_din___a1___bit 11
-#define reg_pio_r_din___ce0_n___lsb 12
-#define reg_pio_r_din___ce0_n___width 1
-#define reg_pio_r_din___ce0_n___bit 12
-#define reg_pio_r_din___ce1_n___lsb 13
-#define reg_pio_r_din___ce1_n___width 1
-#define reg_pio_r_din___ce1_n___bit 13
-#define reg_pio_r_din___ce2_n___lsb 14
-#define reg_pio_r_din___ce2_n___width 1
-#define reg_pio_r_din___ce2_n___bit 14
-#define reg_pio_r_din___rdy___lsb 15
-#define reg_pio_r_din___rdy___width 1
-#define reg_pio_r_din___rdy___bit 15
-#define reg_pio_r_din_offset 92
-
-/* Register r_stat, scope pio, type r */
-#define reg_pio_r_stat___busy___lsb 0
-#define reg_pio_r_stat___busy___width 1
-#define reg_pio_r_stat___busy___bit 0
-#define reg_pio_r_stat_offset 96
-
-/* Register rw_intr_mask, scope pio, type rw */
-#define reg_pio_rw_intr_mask___rdy___lsb 0
-#define reg_pio_rw_intr_mask___rdy___width 1
-#define reg_pio_rw_intr_mask___rdy___bit 0
-#define reg_pio_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope pio, type rw */
-#define reg_pio_rw_ack_intr___rdy___lsb 0
-#define reg_pio_rw_ack_intr___rdy___width 1
-#define reg_pio_rw_ack_intr___rdy___bit 0
-#define reg_pio_rw_ack_intr_offset 104
-
-/* Register r_intr, scope pio, type r */
-#define reg_pio_r_intr___rdy___lsb 0
-#define reg_pio_r_intr___rdy___width 1
-#define reg_pio_r_intr___rdy___bit 0
-#define reg_pio_r_intr_offset 108
-
-/* Register r_masked_intr, scope pio, type r */
-#define reg_pio_r_masked_intr___rdy___lsb 0
-#define reg_pio_r_masked_intr___rdy___width 1
-#define reg_pio_r_masked_intr___rdy___bit 0
-#define reg_pio_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_pio_a2 0x00000003
-#define regk_pio_no 0x00000000
-#define regk_pio_normal 0x00000000
-#define regk_pio_rd 0x00000001
-#define regk_pio_rw_ce0_cfg_default 0x00000000
-#define regk_pio_rw_ce1_cfg_default 0x00000000
-#define regk_pio_rw_ce2_cfg_default 0x00000000
-#define regk_pio_rw_intr_mask_default 0x00000000
-#define regk_pio_rw_man_ctrl_default 0x00000000
-#define regk_pio_rw_oe_default 0x00000000
-#define regk_pio_wr 0x00000002
-#define regk_pio_wr_ce2 0x00000003
-#define regk_pio_yes 0x00000001
-#define regk_pio_yes_all 0x000000ff
-#endif /* __pio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index e3bf8e0692a6..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_asm_h
-#define __reg_map_asm_h
-
-/*
- * This file is autogenerated from
- * file: reg.rmap
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_ccd 0xb0000000
-#define regi_ccd_top 0xb0000000
-#define regi_ccd_dp 0xb0000400
-#define regi_ccd_stat 0xb0000800
-#define regi_ccd_tg 0xb0001000
-#define regi_cfg 0xb0002000
-#define regi_clkgen 0xb0004000
-#define regi_ddr2_ctrl 0xb0006000
-#define regi_dma0 0xb0008000
-#define regi_dma1 0xb000a000
-#define regi_dma11 0xb000c000
-#define regi_dma2 0xb000e000
-#define regi_dma3 0xb0010000
-#define regi_dma4 0xb0012000
-#define regi_dma5 0xb0014000
-#define regi_dma6 0xb0016000
-#define regi_dma7 0xb0018000
-#define regi_dma9 0xb001a000
-#define regi_eth 0xb001c000
-#define regi_gio 0xb0020000
-#define regi_h264 0xb0022000
-#define regi_hist 0xb0026000
-#define regi_iop 0xb0028000
-#define regi_iop_version 0xb0028000
-#define regi_iop_fifo_in_extra 0xb0028040
-#define regi_iop_fifo_out_extra 0xb0028080
-#define regi_iop_trigger_grp0 0xb00280c0
-#define regi_iop_trigger_grp1 0xb0028100
-#define regi_iop_trigger_grp2 0xb0028140
-#define regi_iop_trigger_grp3 0xb0028180
-#define regi_iop_trigger_grp4 0xb00281c0
-#define regi_iop_trigger_grp5 0xb0028200
-#define regi_iop_trigger_grp6 0xb0028240
-#define regi_iop_trigger_grp7 0xb0028280
-#define regi_iop_crc_par 0xb0028300
-#define regi_iop_dmc_in 0xb0028380
-#define regi_iop_dmc_out 0xb0028400
-#define regi_iop_fifo_in 0xb0028480
-#define regi_iop_fifo_out 0xb0028500
-#define regi_iop_scrc_in 0xb0028580
-#define regi_iop_scrc_out 0xb0028600
-#define regi_iop_timer_grp0 0xb0028680
-#define regi_iop_timer_grp1 0xb0028700
-#define regi_iop_sap_in 0xb0028800
-#define regi_iop_sap_out 0xb0028900
-#define regi_iop_spu 0xb0028a00
-#define regi_iop_sw_cfg 0xb0028b00
-#define regi_iop_sw_cpu 0xb0028c00
-#define regi_iop_sw_mpu 0xb0028d00
-#define regi_iop_sw_spu 0xb0028e00
-#define regi_iop_mpu 0xb0029000
-#define regi_irq 0xb002a000
-#define regi_jpeg 0xb002c000
-#define regi_l2cache 0xb0030000
-#define regi_marb_bar 0xb0032000
-#define regi_marb_bar_bp0 0xb0032140
-#define regi_marb_bar_bp1 0xb0032180
-#define regi_marb_bar_bp2 0xb00321c0
-#define regi_marb_bar_bp3 0xb0032200
-#define regi_marb_foo 0xb0034000
-#define regi_marb_foo_bp0 0xb0034280
-#define regi_marb_foo_bp1 0xb00342c0
-#define regi_marb_foo_bp2 0xb0034300
-#define regi_marb_foo_bp3 0xb0034340
-#define regi_pinmux 0xb0038000
-#define regi_pio 0xb0036000
-#define regi_sclr 0xb003a000
-#define regi_sclr_fifo 0xb003c000
-#define regi_ser0 0xb003e000
-#define regi_ser1 0xb0040000
-#define regi_ser2 0xb0042000
-#define regi_ser3 0xb0044000
-#define regi_ser4 0xb0046000
-#define regi_sser 0xb0048000
-#define regi_strcop 0xb004a000
-#define regi_strdma0 0xb004e000
-#define regi_strdma1 0xb0050000
-#define regi_strdma2 0xb0052000
-#define regi_strdma3 0xb0054000
-#define regi_strdma5 0xb0056000
-#define regi_strmux 0xb004c000
-#define regi_timer0 0xb0058000
-#define regi_timer1 0xb005a000
-#define regi_trace 0xb005c000
-#define regi_vin 0xb005e000
-#define regi_vout 0xb0060000
-#endif /* __reg_map_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index 82da59c382c2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: timer.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext 0x00000001
-#define regk_timer_f100 0x00000007
-#define regk_timer_f29_493 0x00000004
-#define regk_timer_f32 0x00000005
-#define regk_timer_f32_768 0x00000006
-#define regk_timer_f90 0x00000003
-#define regk_timer_hold 0x00000001
-#define regk_timer_ld 0x00000000
-#define regk_timer_no 0x00000000
-#define regk_timer_off 0x00000000
-#define regk_timer_run 0x00000002
-#define regk_timer_rw_cnt_cfg_default 0x00000000
-#define regk_timer_rw_intr_mask_default 0x00000000
-#define regk_timer_rw_out_default 0x00000000
-#define regk_timer_rw_test_default 0x00000000
-#define regk_timer_rw_tmr0_ctrl_default 0x00000000
-#define regk_timer_rw_tmr1_ctrl_default 0x00000000
-#define regk_timer_rw_trig_cfg_default 0x00000000
-#define regk_timer_start 0x00000001
-#define regk_timer_stop 0x00000000
-#define regk_timer_time 0x00000001
-#define regk_timer_tmr0 0x00000002
-#define regk_timer_tmr1 0x00000003
-#define regk_timer_vclk 0x00000002
-#define regk_timer_yes 0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h
deleted file mode 100644
index 32d58fed3b03..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __clkgen_defs_h
-#define __clkgen_defs_h
-
-/*
- * This file is autogenerated from
- * file: clkgen.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope clkgen */
-
-/* Register r_bootsel, scope clkgen, type r */
-typedef struct {
- unsigned int boot_mode : 5;
- unsigned int intern_main_clk : 1;
- unsigned int extern_usb2_clk : 1;
- unsigned int dummy1 : 25;
-} reg_clkgen_r_bootsel;
-#define REG_RD_ADDR_clkgen_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope clkgen, type rw */
-typedef struct {
- unsigned int pll : 1;
- unsigned int cpu : 1;
- unsigned int iop_usb : 1;
- unsigned int vin : 1;
- unsigned int sclr : 1;
- unsigned int h264 : 1;
- unsigned int ddr2 : 1;
- unsigned int vout_hist : 1;
- unsigned int eth : 1;
- unsigned int ccd_tg_200 : 1;
- unsigned int dma0_1_eth : 1;
- unsigned int ccd_tg_100 : 1;
- unsigned int jpeg : 1;
- unsigned int sser_ser_dma6_7 : 1;
- unsigned int strdma0_2_video : 1;
- unsigned int dma2_3_strcop : 1;
- unsigned int dma4_5_iop : 1;
- unsigned int dma9_11 : 1;
- unsigned int memarb_bar_ddr : 1;
- unsigned int sclr_h264 : 1;
- unsigned int dummy1 : 12;
-} reg_clkgen_rw_clk_ctrl;
-#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
-#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
-
-
-/* Constants */
-enum {
- regk_clkgen_eth1000_rx = 0x0000000c,
- regk_clkgen_eth1000_tx = 0x0000000e,
- regk_clkgen_eth100_rx = 0x0000001d,
- regk_clkgen_eth100_rx_half = 0x0000001c,
- regk_clkgen_eth100_tx = 0x0000001f,
- regk_clkgen_eth100_tx_half = 0x0000001e,
- regk_clkgen_nand_3_2 = 0x00000000,
- regk_clkgen_nand_3_2_0x30 = 0x00000002,
- regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
- regk_clkgen_nand_3_2_pll = 0x00000010,
- regk_clkgen_nand_3_3 = 0x00000001,
- regk_clkgen_nand_3_3_0x30 = 0x00000003,
- regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
- regk_clkgen_nand_3_3_pll = 0x00000011,
- regk_clkgen_nand_4_2 = 0x00000004,
- regk_clkgen_nand_4_2_0x30 = 0x00000006,
- regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
- regk_clkgen_nand_4_2_pll = 0x00000014,
- regk_clkgen_nand_4_3 = 0x00000005,
- regk_clkgen_nand_4_3_0x30 = 0x00000007,
- regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
- regk_clkgen_nand_4_3_pll = 0x00000015,
- regk_clkgen_nand_5_2 = 0x00000008,
- regk_clkgen_nand_5_2_0x30 = 0x0000000a,
- regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
- regk_clkgen_nand_5_2_pll = 0x00000018,
- regk_clkgen_nand_5_3 = 0x00000009,
- regk_clkgen_nand_5_3_0x30 = 0x0000000b,
- regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
- regk_clkgen_nand_5_3_pll = 0x00000019,
- regk_clkgen_no = 0x00000000,
- regk_clkgen_rw_clk_ctrl_default = 0x00000002,
- regk_clkgen_ser = 0x0000000d,
- regk_clkgen_ser_pll = 0x0000000f,
- regk_clkgen_yes = 0x00000001
-};
-#endif /* __clkgen_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h
deleted file mode 100644
index 84684c335d7d..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ddr2_defs_h
-#define __ddr2_defs_h
-
-/*
- * This file is autogenerated from
- * file: ddr2.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ddr2 */
-
-/* Register rw_cfg, scope ddr2, type rw */
-typedef struct {
- unsigned int col_width : 4;
- unsigned int nr_banks : 1;
- unsigned int bw : 1;
- unsigned int nr_ref : 4;
- unsigned int ref_interval : 11;
- unsigned int odt_ctrl : 2;
- unsigned int odt_mem : 1;
- unsigned int imp_strength : 1;
- unsigned int auto_imp_cal : 1;
- unsigned int imp_cal_override : 1;
- unsigned int dll_override : 1;
- unsigned int dummy1 : 4;
-} reg_ddr2_rw_cfg;
-#define REG_RD_ADDR_ddr2_rw_cfg 0
-#define REG_WR_ADDR_ddr2_rw_cfg 0
-
-/* Register rw_timing, scope ddr2, type rw */
-typedef struct {
- unsigned int wr : 3;
- unsigned int rcd : 3;
- unsigned int rp : 3;
- unsigned int ras : 4;
- unsigned int rfc : 7;
- unsigned int rc : 5;
- unsigned int rtp : 2;
- unsigned int rtw : 3;
- unsigned int wtr : 2;
-} reg_ddr2_rw_timing;
-#define REG_RD_ADDR_ddr2_rw_timing 4
-#define REG_WR_ADDR_ddr2_rw_timing 4
-
-/* Register rw_latency, scope ddr2, type rw */
-typedef struct {
- unsigned int cas : 3;
- unsigned int additive : 3;
- unsigned int dummy1 : 26;
-} reg_ddr2_rw_latency;
-#define REG_RD_ADDR_ddr2_rw_latency 8
-#define REG_WR_ADDR_ddr2_rw_latency 8
-
-/* Register rw_phy_cfg, scope ddr2, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_ddr2_rw_phy_cfg;
-#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
-#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
-
-/* Register rw_phy_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int rst : 1;
- unsigned int cal_rst : 1;
- unsigned int cal_start : 1;
- unsigned int dummy1 : 29;
-} reg_ddr2_rw_phy_ctrl;
-#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
-#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
-
-/* Register rw_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int mrs_data : 16;
- unsigned int cmd : 8;
- unsigned int dummy1 : 8;
-} reg_ddr2_rw_ctrl;
-#define REG_RD_ADDR_ddr2_rw_ctrl 20
-#define REG_WR_ADDR_ddr2_rw_ctrl 20
-
-/* Register rw_pwr_down, scope ddr2, type rw */
-typedef struct {
- unsigned int self_ref : 2;
- unsigned int phy_en : 1;
- unsigned int dummy1 : 29;
-} reg_ddr2_rw_pwr_down;
-#define REG_RD_ADDR_ddr2_rw_pwr_down 24
-#define REG_WR_ADDR_ddr2_rw_pwr_down 24
-
-/* Register r_stat, scope ddr2, type r */
-typedef struct {
- unsigned int dll_lock : 1;
- unsigned int dll_delay_code : 7;
- unsigned int imp_cal_done : 1;
- unsigned int imp_cal_fault : 1;
- unsigned int cal_imp_pu : 4;
- unsigned int cal_imp_pd : 4;
- unsigned int dummy1 : 14;
-} reg_ddr2_r_stat;
-#define REG_RD_ADDR_ddr2_r_stat 28
-
-/* Register rw_imp_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int imp_pu : 4;
- unsigned int imp_pd : 4;
- unsigned int dummy1 : 24;
-} reg_ddr2_rw_imp_ctrl;
-#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
-#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
-
-#define STRIDE_ddr2_rw_dll_ctrl 4
-/* Register rw_dll_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int mode : 1;
- unsigned int clk_delay : 7;
- unsigned int dummy1 : 24;
-} reg_ddr2_rw_dll_ctrl;
-#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
-#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
-
-#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
-/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int dqs90_delay : 7;
- unsigned int dqs180_delay : 7;
- unsigned int dqs270_delay : 7;
- unsigned int dqs360_delay : 7;
- unsigned int dummy1 : 4;
-} reg_ddr2_rw_dqs_dll_ctrl;
-#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
-#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
-
-
-/* Constants */
-enum {
- regk_ddr2_al0 = 0x00000000,
- regk_ddr2_al1 = 0x00000008,
- regk_ddr2_al2 = 0x00000010,
- regk_ddr2_al3 = 0x00000018,
- regk_ddr2_al4 = 0x00000020,
- regk_ddr2_auto = 0x00000003,
- regk_ddr2_bank4 = 0x00000000,
- regk_ddr2_bank8 = 0x00000001,
- regk_ddr2_bl4 = 0x00000002,
- regk_ddr2_bl8 = 0x00000003,
- regk_ddr2_bt_il = 0x00000008,
- regk_ddr2_bt_seq = 0x00000000,
- regk_ddr2_bw16 = 0x00000001,
- regk_ddr2_bw32 = 0x00000000,
- regk_ddr2_cas2 = 0x00000020,
- regk_ddr2_cas3 = 0x00000030,
- regk_ddr2_cas4 = 0x00000040,
- regk_ddr2_cas5 = 0x00000050,
- regk_ddr2_deselect = 0x000000c0,
- regk_ddr2_dic_weak = 0x00000002,
- regk_ddr2_direct = 0x00000001,
- regk_ddr2_dis = 0x00000000,
- regk_ddr2_dll_dis = 0x00000001,
- regk_ddr2_dll_en = 0x00000000,
- regk_ddr2_dll_rst = 0x00000100,
- regk_ddr2_emrs = 0x00000081,
- regk_ddr2_emrs2 = 0x00000082,
- regk_ddr2_emrs3 = 0x00000083,
- regk_ddr2_full = 0x00000001,
- regk_ddr2_hi_ref_rate = 0x00000080,
- regk_ddr2_mrs = 0x00000080,
- regk_ddr2_no = 0x00000000,
- regk_ddr2_nop = 0x000000b8,
- regk_ddr2_ocd_adj = 0x00000200,
- regk_ddr2_ocd_default = 0x00000380,
- regk_ddr2_ocd_drive0 = 0x00000100,
- regk_ddr2_ocd_drive1 = 0x00000080,
- regk_ddr2_ocd_exit = 0x00000000,
- regk_ddr2_odt_dis = 0x00000000,
- regk_ddr2_offs = 0x00000000,
- regk_ddr2_pre = 0x00000090,
- regk_ddr2_pre_all = 0x00000400,
- regk_ddr2_pwr_down_fast = 0x00000000,
- regk_ddr2_pwr_down_slow = 0x00001000,
- regk_ddr2_ref = 0x00000088,
- regk_ddr2_rtt150 = 0x00000040,
- regk_ddr2_rtt50 = 0x00000044,
- regk_ddr2_rtt75 = 0x00000004,
- regk_ddr2_rw_cfg_default = 0x00186000,
- regk_ddr2_rw_dll_ctrl_default = 0x00000000,
- regk_ddr2_rw_dll_ctrl_size = 0x00000004,
- regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
- regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
- regk_ddr2_rw_latency_default = 0x00000000,
- regk_ddr2_rw_phy_cfg_default = 0x00000000,
- regk_ddr2_rw_pwr_down_default = 0x00000000,
- regk_ddr2_rw_timing_default = 0x00000000,
- regk_ddr2_s1Gb = 0x0000001a,
- regk_ddr2_s256Mb = 0x0000000f,
- regk_ddr2_s2Gb = 0x00000027,
- regk_ddr2_s4Gb = 0x00000042,
- regk_ddr2_s512Mb = 0x00000015,
- regk_ddr2_temp0_85 = 0x00000618,
- regk_ddr2_temp85_95 = 0x0000030c,
- regk_ddr2_term150 = 0x00000002,
- regk_ddr2_term50 = 0x00000003,
- regk_ddr2_term75 = 0x00000001,
- regk_ddr2_test = 0x00000080,
- regk_ddr2_weak = 0x00000000,
- regk_ddr2_wr2 = 0x00000200,
- regk_ddr2_wr3 = 0x00000400,
- regk_ddr2_yes = 0x00000001
-};
-#endif /* __ddr2_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h
deleted file mode 100644
index 83ab1f495612..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h
+++ /dev/null
@@ -1,838 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- * file: gio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 0
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 4
-#define REG_WR_ADDR_gio_rw_pa_dout 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 32;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_pa_byte0_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
-#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
-
-/* Register rw_pa_byte0_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
-#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
-
-/* Register rw_pa_byte1_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
-#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
-
-/* Register rw_pa_byte1_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
-#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
-
-/* Register rw_pa_byte2_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte2_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
-#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
-
-/* Register rw_pa_byte2_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte2_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
-#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
-
-/* Register rw_pa_byte3_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte3_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
-#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
-
-/* Register rw_pa_byte3_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte3_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
-#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 44
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 48
-#define REG_WR_ADDR_gio_rw_pb_dout 48
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 32;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 52
-#define REG_WR_ADDR_gio_rw_pb_oe 52
-
-/* Register rw_pb_byte0_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
-#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
-
-/* Register rw_pb_byte0_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
-#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
-
-/* Register rw_pb_byte1_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
-#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
-
-/* Register rw_pb_byte1_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
-#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
-
-/* Register rw_pb_byte2_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte2_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
-#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
-
-/* Register rw_pb_byte2_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte2_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
-#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
-
-/* Register rw_pb_byte3_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte3_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
-#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
-
-/* Register rw_pb_byte3_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte3_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
-#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 88
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 92
-#define REG_WR_ADDR_gio_rw_pc_dout 92
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 16;
- unsigned int dummy1 : 16;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 96
-#define REG_WR_ADDR_gio_rw_pc_oe 96
-
-/* Register rw_pc_byte0_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
-#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
-
-/* Register rw_pc_byte0_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
-#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
-
-/* Register rw_pc_byte1_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
-#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
-
-/* Register rw_pc_byte1_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
-#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 116
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 3;
- unsigned int intr1 : 3;
- unsigned int intr2 : 3;
- unsigned int intr3 : 3;
- unsigned int intr4 : 3;
- unsigned int intr5 : 3;
- unsigned int intr6 : 3;
- unsigned int intr7 : 3;
- unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 120
-#define REG_WR_ADDR_gio_rw_intr_cfg 120
-
-/* Register rw_intr_pins, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 4;
- unsigned int intr1 : 4;
- unsigned int intr2 : 4;
- unsigned int intr3 : 4;
- unsigned int intr4 : 4;
- unsigned int intr5 : 4;
- unsigned int intr6 : 4;
- unsigned int intr7 : 4;
-} reg_gio_rw_intr_pins;
-#define REG_RD_ADDR_gio_rw_intr_pins 124
-#define REG_WR_ADDR_gio_rw_intr_pins 124
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 128
-#define REG_WR_ADDR_gio_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 132
-#define REG_WR_ADDR_gio_rw_ack_intr 132
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 136
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 140
-
-/* Register rw_i2c0_start, scope gio, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_gio_rw_i2c0_start;
-#define REG_RD_ADDR_gio_rw_i2c0_start 144
-#define REG_WR_ADDR_gio_rw_i2c0_start 144
-
-/* Register rw_i2c0_cfg, scope gio, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int bit_order : 1;
- unsigned int scl_io : 1;
- unsigned int scl_inv : 1;
- unsigned int sda_io : 1;
- unsigned int sda_idle : 1;
- unsigned int dummy1 : 26;
-} reg_gio_rw_i2c0_cfg;
-#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
-#define REG_WR_ADDR_gio_rw_i2c0_cfg 148
-
-/* Register rw_i2c0_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int trf_bits : 6;
- unsigned int switch_dir : 6;
- unsigned int extra_start : 3;
- unsigned int early_end : 1;
- unsigned int start_stop : 1;
- unsigned int ack_dir0 : 1;
- unsigned int ack_dir1 : 1;
- unsigned int ack_dir2 : 1;
- unsigned int ack_dir3 : 1;
- unsigned int ack_dir4 : 1;
- unsigned int ack_dir5 : 1;
- unsigned int ack_bit : 1;
- unsigned int start_bit : 1;
- unsigned int freq : 2;
- unsigned int dummy1 : 5;
-} reg_gio_rw_i2c0_ctrl;
-#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
-#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
-
-/* Register rw_i2c0_data, scope gio, type rw */
-typedef struct {
- unsigned int data0 : 8;
- unsigned int data1 : 8;
- unsigned int data2 : 8;
- unsigned int data3 : 8;
-} reg_gio_rw_i2c0_data;
-#define REG_RD_ADDR_gio_rw_i2c0_data 156
-#define REG_WR_ADDR_gio_rw_i2c0_data 156
-
-/* Register rw_i2c0_data2, scope gio, type rw */
-typedef struct {
- unsigned int data4 : 8;
- unsigned int data5 : 8;
- unsigned int start_val : 6;
- unsigned int ack_val : 6;
- unsigned int dummy1 : 4;
-} reg_gio_rw_i2c0_data2;
-#define REG_RD_ADDR_gio_rw_i2c0_data2 160
-#define REG_WR_ADDR_gio_rw_i2c0_data2 160
-
-/* Register rw_i2c1_start, scope gio, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_gio_rw_i2c1_start;
-#define REG_RD_ADDR_gio_rw_i2c1_start 164
-#define REG_WR_ADDR_gio_rw_i2c1_start 164
-
-/* Register rw_i2c1_cfg, scope gio, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int bit_order : 1;
- unsigned int scl_io : 1;
- unsigned int scl_inv : 1;
- unsigned int sda0_io : 1;
- unsigned int sda0_idle : 1;
- unsigned int sda1_io : 1;
- unsigned int sda1_idle : 1;
- unsigned int sda2_io : 1;
- unsigned int sda2_idle : 1;
- unsigned int sda3_io : 1;
- unsigned int sda3_idle : 1;
- unsigned int sda_sel : 2;
- unsigned int sen_idle : 1;
- unsigned int sen_inv : 1;
- unsigned int sen_sel : 2;
- unsigned int dummy1 : 14;
-} reg_gio_rw_i2c1_cfg;
-#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
-#define REG_WR_ADDR_gio_rw_i2c1_cfg 168
-
-/* Register rw_i2c1_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int trf_bits : 6;
- unsigned int switch_dir : 6;
- unsigned int extra_start : 3;
- unsigned int early_end : 1;
- unsigned int start_stop : 1;
- unsigned int ack_dir0 : 1;
- unsigned int ack_dir1 : 1;
- unsigned int ack_dir2 : 1;
- unsigned int ack_dir3 : 1;
- unsigned int ack_dir4 : 1;
- unsigned int ack_dir5 : 1;
- unsigned int ack_bit : 1;
- unsigned int start_bit : 1;
- unsigned int freq : 2;
- unsigned int dummy1 : 5;
-} reg_gio_rw_i2c1_ctrl;
-#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
-#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
-
-/* Register rw_i2c1_data, scope gio, type rw */
-typedef struct {
- unsigned int data0 : 8;
- unsigned int data1 : 8;
- unsigned int data2 : 8;
- unsigned int data3 : 8;
-} reg_gio_rw_i2c1_data;
-#define REG_RD_ADDR_gio_rw_i2c1_data 176
-#define REG_WR_ADDR_gio_rw_i2c1_data 176
-
-/* Register rw_i2c1_data2, scope gio, type rw */
-typedef struct {
- unsigned int data4 : 8;
- unsigned int data5 : 8;
- unsigned int start_val : 6;
- unsigned int ack_val : 6;
- unsigned int dummy1 : 4;
-} reg_gio_rw_i2c1_data2;
-#define REG_RD_ADDR_gio_rw_i2c1_data2 180
-#define REG_WR_ADDR_gio_rw_i2c1_data2 180
-
-/* Register r_ppwm_stat, scope gio, type r */
-typedef struct {
- unsigned int freq : 2;
- unsigned int dummy1 : 30;
-} reg_gio_r_ppwm_stat;
-#define REG_RD_ADDR_gio_r_ppwm_stat 184
-
-/* Register rw_ppwm_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_ppwm_data;
-#define REG_RD_ADDR_gio_rw_ppwm_data 188
-#define REG_WR_ADDR_gio_rw_ppwm_data 188
-
-/* Register rw_pwm0_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int mode : 2;
- unsigned int ccd_override : 1;
- unsigned int ccd_val : 1;
- unsigned int dummy1 : 28;
-} reg_gio_rw_pwm0_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
-#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
-
-/* Register rw_pwm0_var, scope gio, type rw */
-typedef struct {
- unsigned int lo : 13;
- unsigned int hi : 13;
- unsigned int dummy1 : 6;
-} reg_gio_rw_pwm0_var;
-#define REG_RD_ADDR_gio_rw_pwm0_var 196
-#define REG_WR_ADDR_gio_rw_pwm0_var 196
-
-/* Register rw_pwm0_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pwm0_data;
-#define REG_RD_ADDR_gio_rw_pwm0_data 200
-#define REG_WR_ADDR_gio_rw_pwm0_data 200
-
-/* Register rw_pwm1_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int mode : 2;
- unsigned int ccd_override : 1;
- unsigned int ccd_val : 1;
- unsigned int dummy1 : 28;
-} reg_gio_rw_pwm1_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
-#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
-
-/* Register rw_pwm1_var, scope gio, type rw */
-typedef struct {
- unsigned int lo : 13;
- unsigned int hi : 13;
- unsigned int dummy1 : 6;
-} reg_gio_rw_pwm1_var;
-#define REG_RD_ADDR_gio_rw_pwm1_var 208
-#define REG_WR_ADDR_gio_rw_pwm1_var 208
-
-/* Register rw_pwm1_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pwm1_data;
-#define REG_RD_ADDR_gio_rw_pwm1_data 212
-#define REG_WR_ADDR_gio_rw_pwm1_data 212
-
-/* Register rw_pwm2_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int mode : 2;
- unsigned int ccd_override : 1;
- unsigned int ccd_val : 1;
- unsigned int dummy1 : 28;
-} reg_gio_rw_pwm2_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
-#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
-
-/* Register rw_pwm2_var, scope gio, type rw */
-typedef struct {
- unsigned int lo : 13;
- unsigned int hi : 13;
- unsigned int dummy1 : 6;
-} reg_gio_rw_pwm2_var;
-#define REG_RD_ADDR_gio_rw_pwm2_var 220
-#define REG_WR_ADDR_gio_rw_pwm2_var 220
-
-/* Register rw_pwm2_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pwm2_data;
-#define REG_RD_ADDR_gio_rw_pwm2_data 224
-#define REG_WR_ADDR_gio_rw_pwm2_data 224
-
-/* Register rw_pwm_in_cfg, scope gio, type rw */
-typedef struct {
- unsigned int pin : 3;
- unsigned int dummy1 : 29;
-} reg_gio_rw_pwm_in_cfg;
-#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
-#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
-
-/* Register r_pwm_in_lo, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pwm_in_lo;
-#define REG_RD_ADDR_gio_r_pwm_in_lo 232
-
-/* Register r_pwm_in_hi, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pwm_in_hi;
-#define REG_RD_ADDR_gio_r_pwm_in_hi 236
-
-/* Register r_pwm_in_cnt, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pwm_in_cnt;
-#define REG_RD_ADDR_gio_r_pwm_in_cnt 240
-
-
-/* Constants */
-enum {
- regk_gio_anyedge = 0x00000007,
- regk_gio_f100k = 0x00000000,
- regk_gio_f1562 = 0x00000000,
- regk_gio_f195 = 0x00000003,
- regk_gio_f1m = 0x00000002,
- regk_gio_f390 = 0x00000002,
- regk_gio_f400k = 0x00000001,
- regk_gio_f5m = 0x00000003,
- regk_gio_f781 = 0x00000001,
- regk_gio_hi = 0x00000001,
- regk_gio_in = 0x00000000,
- regk_gio_intr_pa0 = 0x00000000,
- regk_gio_intr_pa1 = 0x00000000,
- regk_gio_intr_pa10 = 0x00000001,
- regk_gio_intr_pa11 = 0x00000001,
- regk_gio_intr_pa12 = 0x00000001,
- regk_gio_intr_pa13 = 0x00000001,
- regk_gio_intr_pa14 = 0x00000001,
- regk_gio_intr_pa15 = 0x00000001,
- regk_gio_intr_pa16 = 0x00000002,
- regk_gio_intr_pa17 = 0x00000002,
- regk_gio_intr_pa18 = 0x00000002,
- regk_gio_intr_pa19 = 0x00000002,
- regk_gio_intr_pa2 = 0x00000000,
- regk_gio_intr_pa20 = 0x00000002,
- regk_gio_intr_pa21 = 0x00000002,
- regk_gio_intr_pa22 = 0x00000002,
- regk_gio_intr_pa23 = 0x00000002,
- regk_gio_intr_pa24 = 0x00000003,
- regk_gio_intr_pa25 = 0x00000003,
- regk_gio_intr_pa26 = 0x00000003,
- regk_gio_intr_pa27 = 0x00000003,
- regk_gio_intr_pa28 = 0x00000003,
- regk_gio_intr_pa29 = 0x00000003,
- regk_gio_intr_pa3 = 0x00000000,
- regk_gio_intr_pa30 = 0x00000003,
- regk_gio_intr_pa31 = 0x00000003,
- regk_gio_intr_pa4 = 0x00000000,
- regk_gio_intr_pa5 = 0x00000000,
- regk_gio_intr_pa6 = 0x00000000,
- regk_gio_intr_pa7 = 0x00000000,
- regk_gio_intr_pa8 = 0x00000001,
- regk_gio_intr_pa9 = 0x00000001,
- regk_gio_intr_pb0 = 0x00000004,
- regk_gio_intr_pb1 = 0x00000004,
- regk_gio_intr_pb10 = 0x00000005,
- regk_gio_intr_pb11 = 0x00000005,
- regk_gio_intr_pb12 = 0x00000005,
- regk_gio_intr_pb13 = 0x00000005,
- regk_gio_intr_pb14 = 0x00000005,
- regk_gio_intr_pb15 = 0x00000005,
- regk_gio_intr_pb16 = 0x00000006,
- regk_gio_intr_pb17 = 0x00000006,
- regk_gio_intr_pb18 = 0x00000006,
- regk_gio_intr_pb19 = 0x00000006,
- regk_gio_intr_pb2 = 0x00000004,
- regk_gio_intr_pb20 = 0x00000006,
- regk_gio_intr_pb21 = 0x00000006,
- regk_gio_intr_pb22 = 0x00000006,
- regk_gio_intr_pb23 = 0x00000006,
- regk_gio_intr_pb24 = 0x00000007,
- regk_gio_intr_pb25 = 0x00000007,
- regk_gio_intr_pb26 = 0x00000007,
- regk_gio_intr_pb27 = 0x00000007,
- regk_gio_intr_pb28 = 0x00000007,
- regk_gio_intr_pb29 = 0x00000007,
- regk_gio_intr_pb3 = 0x00000004,
- regk_gio_intr_pb30 = 0x00000007,
- regk_gio_intr_pb31 = 0x00000007,
- regk_gio_intr_pb4 = 0x00000004,
- regk_gio_intr_pb5 = 0x00000004,
- regk_gio_intr_pb6 = 0x00000004,
- regk_gio_intr_pb7 = 0x00000004,
- regk_gio_intr_pb8 = 0x00000005,
- regk_gio_intr_pb9 = 0x00000005,
- regk_gio_intr_pc0 = 0x00000008,
- regk_gio_intr_pc1 = 0x00000008,
- regk_gio_intr_pc10 = 0x00000009,
- regk_gio_intr_pc11 = 0x00000009,
- regk_gio_intr_pc12 = 0x00000009,
- regk_gio_intr_pc13 = 0x00000009,
- regk_gio_intr_pc14 = 0x00000009,
- regk_gio_intr_pc15 = 0x00000009,
- regk_gio_intr_pc2 = 0x00000008,
- regk_gio_intr_pc3 = 0x00000008,
- regk_gio_intr_pc4 = 0x00000008,
- regk_gio_intr_pc5 = 0x00000008,
- regk_gio_intr_pc6 = 0x00000008,
- regk_gio_intr_pc7 = 0x00000008,
- regk_gio_intr_pc8 = 0x00000009,
- regk_gio_intr_pc9 = 0x00000009,
- regk_gio_intr_pd0 = 0x0000000c,
- regk_gio_intr_pd1 = 0x0000000c,
- regk_gio_intr_pd10 = 0x0000000d,
- regk_gio_intr_pd11 = 0x0000000d,
- regk_gio_intr_pd12 = 0x0000000d,
- regk_gio_intr_pd13 = 0x0000000d,
- regk_gio_intr_pd14 = 0x0000000d,
- regk_gio_intr_pd15 = 0x0000000d,
- regk_gio_intr_pd16 = 0x0000000e,
- regk_gio_intr_pd17 = 0x0000000e,
- regk_gio_intr_pd18 = 0x0000000e,
- regk_gio_intr_pd19 = 0x0000000e,
- regk_gio_intr_pd2 = 0x0000000c,
- regk_gio_intr_pd20 = 0x0000000e,
- regk_gio_intr_pd21 = 0x0000000e,
- regk_gio_intr_pd22 = 0x0000000e,
- regk_gio_intr_pd23 = 0x0000000e,
- regk_gio_intr_pd24 = 0x0000000f,
- regk_gio_intr_pd25 = 0x0000000f,
- regk_gio_intr_pd26 = 0x0000000f,
- regk_gio_intr_pd27 = 0x0000000f,
- regk_gio_intr_pd28 = 0x0000000f,
- regk_gio_intr_pd29 = 0x0000000f,
- regk_gio_intr_pd3 = 0x0000000c,
- regk_gio_intr_pd30 = 0x0000000f,
- regk_gio_intr_pd31 = 0x0000000f,
- regk_gio_intr_pd4 = 0x0000000c,
- regk_gio_intr_pd5 = 0x0000000c,
- regk_gio_intr_pd6 = 0x0000000c,
- regk_gio_intr_pd7 = 0x0000000c,
- regk_gio_intr_pd8 = 0x0000000d,
- regk_gio_intr_pd9 = 0x0000000d,
- regk_gio_lo = 0x00000002,
- regk_gio_lsb = 0x00000000,
- regk_gio_msb = 0x00000001,
- regk_gio_negedge = 0x00000006,
- regk_gio_no = 0x00000000,
- regk_gio_no_switch = 0x0000003f,
- regk_gio_none = 0x00000007,
- regk_gio_off = 0x00000000,
- regk_gio_opendrain = 0x00000000,
- regk_gio_out = 0x00000001,
- regk_gio_posedge = 0x00000005,
- regk_gio_pwm_hfp = 0x00000002,
- regk_gio_pwm_pa0 = 0x00000001,
- regk_gio_pwm_pa19 = 0x00000004,
- regk_gio_pwm_pa6 = 0x00000002,
- regk_gio_pwm_pa7 = 0x00000003,
- regk_gio_pwm_pb26 = 0x00000005,
- regk_gio_pwm_pd23 = 0x00000006,
- regk_gio_pwm_pd31 = 0x00000007,
- regk_gio_pwm_std = 0x00000001,
- regk_gio_pwm_var = 0x00000003,
- regk_gio_rw_i2c0_cfg_default = 0x00000020,
- regk_gio_rw_i2c0_ctrl_default = 0x00010000,
- regk_gio_rw_i2c0_start_default = 0x00000000,
- regk_gio_rw_i2c1_cfg_default = 0x00000aa0,
- regk_gio_rw_i2c1_ctrl_default = 0x00010000,
- regk_gio_rw_i2c1_start_default = 0x00000000,
- regk_gio_rw_intr_cfg_default = 0x00000000,
- regk_gio_rw_intr_mask_default = 0x00000000,
- regk_gio_rw_pa_oe_default = 0x00000000,
- regk_gio_rw_pb_oe_default = 0x00000000,
- regk_gio_rw_pc_oe_default = 0x00000000,
- regk_gio_rw_ppwm_data_default = 0x00000000,
- regk_gio_rw_pwm0_ctrl_default = 0x00000000,
- regk_gio_rw_pwm1_ctrl_default = 0x00000000,
- regk_gio_rw_pwm2_ctrl_default = 0x00000000,
- regk_gio_rw_pwm_in_cfg_default = 0x00000000,
- regk_gio_sda0 = 0x00000000,
- regk_gio_sda1 = 0x00000001,
- regk_gio_sda2 = 0x00000002,
- regk_gio_sda3 = 0x00000003,
- regk_gio_sen = 0x00000000,
- regk_gio_set = 0x00000003,
- regk_gio_yes = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h
deleted file mode 100644
index 55dab5bd7bd3..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr
- from intr_vect.r */
-
-#ifndef _INTR_VECT_R
-#define _INTR_VECT_R
-#define TIMER0_INTR_VECT 0x31
-#define TIMER1_INTR_VECT 0x32
-#define DMA0_INTR_VECT 0x33
-#define DMA1_INTR_VECT 0x34
-#define DMA2_INTR_VECT 0x35
-#define DMA3_INTR_VECT 0x36
-#define DMA4_INTR_VECT 0x37
-#define DMA5_INTR_VECT 0x38
-#define DMA6_INTR_VECT 0x39
-#define DMA7_INTR_VECT 0x3a
-#define DMA9_INTR_VECT 0x3b
-#define DMA11_INTR_VECT 0x3c
-#define GIO_INTR_VECT 0x3d
-#define IOP0_INTR_VECT 0x3e
-#define IOP1_INTR_VECT 0x3f
-#define SER0_INTR_VECT 0x40
-#define SER1_INTR_VECT 0x41
-#define SER2_INTR_VECT 0x42
-#define SER3_INTR_VECT 0x43
-#define SER4_INTR_VECT 0x44
-#define SSER_INTR_VECT 0x45
-#define STRDMA0_INTR_VECT 0x46
-#define STRDMA1_INTR_VECT 0x47
-#define STRDMA2_INTR_VECT 0x48
-#define STRDMA3_INTR_VECT 0x49
-#define STRDMA5_INTR_VECT 0x4a
-#define VIN_INTR_VECT 0x4b
-#define VOUT_INTR_VECT 0x4c
-#define JPEG_INTR_VECT 0x4d
-#define H264_INTR_VECT 0x4e
-#define HISTO_INTR_VECT 0x4f
-#define CCD_INTR_VECT 0x50
-#define ETH_INTR_VECT 0x51
-#define MEMARB_BAR_INTR_VECT 0x52
-#define MEMARB_FOO_INTR_VECT 0x53
-#define PIO_INTR_VECT 0x54
-#define SCLR_INTR_VECT 0x55
-#define SCLR_FIFO_INTR_VECT 0x56
-#define IPI_INTR_VECT 0x57
-#define NBR_INTR_VECT 0x58
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h
deleted file mode 100644
index 71a28d1ed74a..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __intr_vect_defs_h
-#define __intr_vect_defs_h
-
-/*
- * This file is autogenerated from
- * file: intr_vect.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope intr_vect */
-
-
-#define STRIDE_intr_vect_rw_mask 4
-/* Register rw_mask0, scope intr_vect, type rw */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_rw_mask0;
-#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
-#define REG_RD_ADDR_intr_vect_rw_mask 0
-#define REG_WR_ADDR_intr_vect_rw_mask 0
-#define REG_RD_ADDR_intr_vect_rw_mask0 0
-#define REG_WR_ADDR_intr_vect_rw_mask0 0
-
-#define STRIDE_intr_vect_r_vect 4
-/* Register r_vect0, scope intr_vect, type r */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_r_vect0;
-#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
-#define REG_RD_ADDR_intr_vect_r_vect 8
-#define REG_RD_ADDR_intr_vect_r_vect0 8
-
-#define STRIDE_intr_vect_r_masked_vect 4
-/* Register r_masked_vect0, scope intr_vect, type r */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_r_masked_vect0;
-#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
-#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
-#define REG_RD_ADDR_intr_vect_r_masked_vect 16
-
-#define STRIDE_intr_vect_rw_xmask 4
-/* Register rw_xmask0, scope intr_vect, type rw */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_rw_xmask0;
-#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
-#define REG_RD_ADDR_intr_vect_rw_xmask0 24
-#define REG_WR_ADDR_intr_vect_rw_xmask0 24
-#define REG_RD_ADDR_intr_vect_rw_xmask 24
-#define REG_WR_ADDR_intr_vect_rw_xmask 24
-
-/* Register rw_mask1, scope intr_vect, type rw */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_rw_mask1;
-#define REG_RD_ADDR_intr_vect_rw_mask1 4
-#define REG_WR_ADDR_intr_vect_rw_mask1 4
-
-/* Register r_vect1, scope intr_vect, type r */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_r_vect1;
-#define REG_RD_ADDR_intr_vect_r_vect1 12
-
-/* Register r_masked_vect1, scope intr_vect, type r */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_r_masked_vect1;
-#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
-
-/* Register rw_xmask1, scope intr_vect, type rw */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_rw_xmask1;
-#define REG_RD_ADDR_intr_vect_rw_xmask1 28
-#define REG_WR_ADDR_intr_vect_rw_xmask1 28
-
-/* Register rw_xmask_ctrl, scope intr_vect, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_intr_vect_rw_xmask_ctrl;
-#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
-#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
-
-/* Register r_nmi, scope intr_vect, type r */
-typedef struct {
- unsigned int watchdog0 : 1;
- unsigned int watchdog1 : 1;
- unsigned int dummy1 : 30;
-} reg_intr_vect_r_nmi;
-#define REG_RD_ADDR_intr_vect_r_nmi 64
-
-/* Register r_guru, scope intr_vect, type r */
-typedef struct {
- unsigned int jtag : 1;
- unsigned int dummy1 : 31;
-} reg_intr_vect_r_guru;
-#define REG_RD_ADDR_intr_vect_r_guru 68
-
-
-/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct
-{
- unsigned int vector;
-} reg_intr_vect_rw_ipi;
-#define REG_RD_ADDR_intr_vect_rw_ipi 72
-#define REG_WR_ADDR_intr_vect_rw_ipi 72
-
-/* Constants */
-enum {
- regk_intr_vect_no = 0x00000000,
- regk_intr_vect_rw_mask0_default = 0x00000000,
- regk_intr_vect_rw_mask1_default = 0x00000000,
- regk_intr_vect_rw_xmask0_default = 0x00000000,
- regk_intr_vect_rw_xmask1_default = 0x00000000,
- regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
- regk_intr_vect_yes = 0x00000001
-};
-#endif /* __intr_vect_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index 5e5f4d94aecf..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
- */
-#define iop_version 0
-#define iop_fifo_in_extra 64
-#define iop_fifo_out_extra 128
-#define iop_trigger_grp0 192
-#define iop_trigger_grp1 256
-#define iop_trigger_grp2 320
-#define iop_trigger_grp3 384
-#define iop_trigger_grp4 448
-#define iop_trigger_grp5 512
-#define iop_trigger_grp6 576
-#define iop_trigger_grp7 640
-#define iop_crc_par 768
-#define iop_dmc_in 896
-#define iop_dmc_out 1024
-#define iop_fifo_in 1152
-#define iop_fifo_out 1280
-#define iop_scrc_in 1408
-#define iop_scrc_out 1536
-#define iop_timer_grp0 1664
-#define iop_timer_grp1 1792
-#define iop_sap_in 2048
-#define iop_sap_out 2304
-#define iop_spu 2560
-#define iop_sw_cfg 2816
-#define iop_sw_cpu 3072
-#define iop_sw_mpu 3328
-#define iop_sw_spu 3584
-#define iop_mpu 4096
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index ee0587ec433c..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_in.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_sap_in_rw_bus_byte 4
-/* Register rw_bus_byte, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
-#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
-#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
-#define reg_iop_sap_in_rw_bus_byte___delay___width 2
-#define reg_iop_sap_in_rw_bus_byte_offset 0
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 2
-#define reg_iop_sap_in_rw_gio___logic___lsb 9
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 16
-
-
-/* Constants */
-#define regk_iop_sap_in_and 0x00000002
-#define regk_iop_sap_in_ext_clk200 0x00000003
-#define regk_iop_sap_in_gio0 0x00000000
-#define regk_iop_sap_in_gio12 0x00000003
-#define regk_iop_sap_in_gio16 0x00000004
-#define regk_iop_sap_in_gio20 0x00000005
-#define regk_iop_sap_in_gio24 0x00000006
-#define regk_iop_sap_in_gio28 0x00000007
-#define regk_iop_sap_in_gio4 0x00000001
-#define regk_iop_sap_in_gio8 0x00000002
-#define regk_iop_sap_in_inv 0x00000001
-#define regk_iop_sap_in_neg 0x00000002
-#define regk_iop_sap_in_no 0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200 0x00000002
-#define regk_iop_sap_in_none 0x00000000
-#define regk_iop_sap_in_one 0x00000001
-#define regk_iop_sap_in_or 0x00000003
-#define regk_iop_sap_in_pos 0x00000001
-#define regk_iop_sap_in_pos_neg 0x00000003
-#define regk_iop_sap_in_rw_bus_byte_default 0x00000000
-#define regk_iop_sap_in_rw_bus_byte_size 0x00000004
-#define regk_iop_sap_in_rw_gio_default 0x00000000
-#define regk_iop_sap_in_rw_gio_size 0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
-#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
-#define regk_iop_sap_in_tmr_clk200 0x00000001
-#define regk_iop_sap_in_two 0x00000002
-#define regk_iop_sap_in_two_clk200 0x00000000
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index 9bbe0b920c93..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_out.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
-#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
-#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
-#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
-#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
-#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
-#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
-#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
-#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
-#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
-#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
-#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
-#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
-#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
-#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
-#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
-#define reg_iop_sap_out_rw_bus_offset 4
-
-/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
-
-/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
-#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
-#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
-#define reg_iop_sap_out_rw_gio___out_delay___width 1
-#define reg_iop_sap_out_rw_gio___out_delay___bit 7
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
-#define reg_iop_sap_out_rw_gio___out_logic___width 2
-#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
-#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_delay___width 1
-#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
-#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
-#define reg_iop_sap_out_rw_gio_offset 16
-
-
-/* Constants */
-#define regk_iop_sap_out_always 0x00000001
-#define regk_iop_sap_out_and 0x00000002
-#define regk_iop_sap_out_clk0 0x00000000
-#define regk_iop_sap_out_clk1 0x00000001
-#define regk_iop_sap_out_clk12 0x00000004
-#define regk_iop_sap_out_clk200 0x00000000
-#define regk_iop_sap_out_ext 0x00000002
-#define regk_iop_sap_out_gated 0x00000003
-#define regk_iop_sap_out_gio0 0x00000000
-#define regk_iop_sap_out_gio1 0x00000000
-#define regk_iop_sap_out_gio16 0x00000002
-#define regk_iop_sap_out_gio17 0x00000002
-#define regk_iop_sap_out_gio24 0x00000003
-#define regk_iop_sap_out_gio25 0x00000003
-#define regk_iop_sap_out_gio8 0x00000001
-#define regk_iop_sap_out_gio9 0x00000001
-#define regk_iop_sap_out_gio_out10 0x00000005
-#define regk_iop_sap_out_gio_out18 0x00000006
-#define regk_iop_sap_out_gio_out2 0x00000004
-#define regk_iop_sap_out_gio_out26 0x00000007
-#define regk_iop_sap_out_inv 0x00000001
-#define regk_iop_sap_out_nand 0x00000003
-#define regk_iop_sap_out_no 0x00000000
-#define regk_iop_sap_out_none 0x00000000
-#define regk_iop_sap_out_one 0x00000001
-#define regk_iop_sap_out_rw_bus_default 0x00000000
-#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
-#define regk_iop_sap_out_rw_gio_default 0x00000000
-#define regk_iop_sap_out_rw_gio_size 0x00000020
-#define regk_iop_sap_out_spu_gio6 0x00000002
-#define regk_iop_sap_out_spu_gio7 0x00000003
-#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000
-#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001
-#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002
-#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003
-#define regk_iop_sap_out_tmr200 0x00000001
-#define regk_iop_sap_out_yes 0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index c4b8bc386cb6..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,740 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cfg.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0
-
-/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4
-
-/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8
-
-/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12
-
-/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16
-
-/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20
-
-/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32
-
-/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36
-
-/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40
-
-/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
-#define reg_iop_sw_cfg_rw_spu_owner_offset 44
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84
-
-/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus_mask_offset 88
-
-/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 96
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 104
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140
-
-/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1
-#define reg_iop_sw_cfg_rw_spu_cfg_offset 144
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156
-
-/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
-#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a 0x00000001
-#define regk_iop_sw_cfg_b 0x00000002
-#define regk_iop_sw_cfg_bus 0x00000000
-#define regk_iop_sw_cfg_bus_rot16 0x00000002
-#define regk_iop_sw_cfg_bus_rot24 0x00000003
-#define regk_iop_sw_cfg_bus_rot8 0x00000001
-#define regk_iop_sw_cfg_clk12 0x00000000
-#define regk_iop_sw_cfg_cpu 0x00000000
-#define regk_iop_sw_cfg_gated_clk0 0x0000000e
-#define regk_iop_sw_cfg_gated_clk1 0x0000000f
-#define regk_iop_sw_cfg_gio0 0x00000004
-#define regk_iop_sw_cfg_gio1 0x00000001
-#define regk_iop_sw_cfg_gio2 0x00000005
-#define regk_iop_sw_cfg_gio3 0x00000002
-#define regk_iop_sw_cfg_gio4 0x00000006
-#define regk_iop_sw_cfg_gio5 0x00000003
-#define regk_iop_sw_cfg_gio6 0x00000007
-#define regk_iop_sw_cfg_gio7 0x00000004
-#define regk_iop_sw_cfg_gio_in18 0x00000002
-#define regk_iop_sw_cfg_gio_in19 0x00000003
-#define regk_iop_sw_cfg_gio_in20 0x00000004
-#define regk_iop_sw_cfg_gio_in21 0x00000005
-#define regk_iop_sw_cfg_gio_in26 0x00000006
-#define regk_iop_sw_cfg_gio_in27 0x00000007
-#define regk_iop_sw_cfg_gio_in4 0x00000000
-#define regk_iop_sw_cfg_gio_in5 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002
-#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003
-#define regk_iop_sw_cfg_mpu 0x00000001
-#define regk_iop_sw_cfg_none 0x00000000
-#define regk_iop_sw_cfg_pdp_out 0x00000001
-#define regk_iop_sw_cfg_pdp_out_hi 0x00000001
-#define regk_iop_sw_cfg_pdp_out_lo 0x00000000
-#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
-#define regk_iop_sw_cfg_sdp_out 0x00000004
-#define regk_iop_sw_cfg_size16 0x00000002
-#define regk_iop_sw_cfg_size24 0x00000003
-#define regk_iop_sw_cfg_size32 0x00000004
-#define regk_iop_sw_cfg_size8 0x00000001
-#define regk_iop_sw_cfg_spu 0x00000002
-#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002
-#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002
-#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003
-#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003
-#define regk_iop_sw_cfg_spu_g0 0x00000007
-#define regk_iop_sw_cfg_spu_g1 0x00000007
-#define regk_iop_sw_cfg_spu_g2 0x00000007
-#define regk_iop_sw_cfg_spu_g3 0x00000007
-#define regk_iop_sw_cfg_spu_g4 0x00000007
-#define regk_iop_sw_cfg_spu_g5 0x00000007
-#define regk_iop_sw_cfg_spu_g6 0x00000007
-#define regk_iop_sw_cfg_spu_g7 0x00000007
-#define regk_iop_sw_cfg_spu_gio0 0x00000000
-#define regk_iop_sw_cfg_spu_gio1 0x00000001
-#define regk_iop_sw_cfg_spu_gio5 0x00000005
-#define regk_iop_sw_cfg_spu_gio6 0x00000006
-#define regk_iop_sw_cfg_spu_gio7 0x00000007
-#define regk_iop_sw_cfg_spu_gio_out0 0x00000008
-#define regk_iop_sw_cfg_spu_gio_out1 0x00000009
-#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a
-#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b
-#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c
-#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d
-#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e
-#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f
-#define regk_iop_sw_cfg_spu_gioout0 0x00000000
-#define regk_iop_sw_cfg_spu_gioout1 0x00000000
-#define regk_iop_sw_cfg_spu_gioout10 0x00000007
-#define regk_iop_sw_cfg_spu_gioout11 0x00000007
-#define regk_iop_sw_cfg_spu_gioout12 0x00000007
-#define regk_iop_sw_cfg_spu_gioout13 0x00000007
-#define regk_iop_sw_cfg_spu_gioout14 0x00000007
-#define regk_iop_sw_cfg_spu_gioout15 0x00000007
-#define regk_iop_sw_cfg_spu_gioout16 0x00000007
-#define regk_iop_sw_cfg_spu_gioout17 0x00000007
-#define regk_iop_sw_cfg_spu_gioout18 0x00000007
-#define regk_iop_sw_cfg_spu_gioout19 0x00000007
-#define regk_iop_sw_cfg_spu_gioout2 0x00000001
-#define regk_iop_sw_cfg_spu_gioout20 0x00000007
-#define regk_iop_sw_cfg_spu_gioout21 0x00000007
-#define regk_iop_sw_cfg_spu_gioout22 0x00000007
-#define regk_iop_sw_cfg_spu_gioout23 0x00000007
-#define regk_iop_sw_cfg_spu_gioout24 0x00000007
-#define regk_iop_sw_cfg_spu_gioout25 0x00000007
-#define regk_iop_sw_cfg_spu_gioout26 0x00000007
-#define regk_iop_sw_cfg_spu_gioout27 0x00000007
-#define regk_iop_sw_cfg_spu_gioout28 0x00000007
-#define regk_iop_sw_cfg_spu_gioout29 0x00000007
-#define regk_iop_sw_cfg_spu_gioout3 0x00000001
-#define regk_iop_sw_cfg_spu_gioout30 0x00000007
-#define regk_iop_sw_cfg_spu_gioout31 0x00000007
-#define regk_iop_sw_cfg_spu_gioout4 0x00000002
-#define regk_iop_sw_cfg_spu_gioout5 0x00000002
-#define regk_iop_sw_cfg_spu_gioout6 0x00000003
-#define regk_iop_sw_cfg_spu_gioout7 0x00000003
-#define regk_iop_sw_cfg_spu_gioout8 0x00000007
-#define regk_iop_sw_cfg_spu_gioout9 0x00000007
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
-#define regk_iop_sw_cfg_timer_grp0 0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002
-#define regk_iop_sw_cfg_timer_grp1 0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003
-#define regk_iop_sw_cfg_trig0_0 0x00000000
-#define regk_iop_sw_cfg_trig0_1 0x00000000
-#define regk_iop_sw_cfg_trig0_2 0x00000000
-#define regk_iop_sw_cfg_trig0_3 0x00000000
-#define regk_iop_sw_cfg_trig1_0 0x00000000
-#define regk_iop_sw_cfg_trig1_1 0x00000000
-#define regk_iop_sw_cfg_trig1_2 0x00000000
-#define regk_iop_sw_cfg_trig1_3 0x00000000
-#define regk_iop_sw_cfg_trig2_0 0x00000001
-#define regk_iop_sw_cfg_trig2_1 0x00000001
-#define regk_iop_sw_cfg_trig2_2 0x00000001
-#define regk_iop_sw_cfg_trig2_3 0x00000001
-#define regk_iop_sw_cfg_trig3_0 0x00000001
-#define regk_iop_sw_cfg_trig3_1 0x00000001
-#define regk_iop_sw_cfg_trig3_2 0x00000001
-#define regk_iop_sw_cfg_trig3_3 0x00000001
-#define regk_iop_sw_cfg_trig4_0 0x00000002
-#define regk_iop_sw_cfg_trig4_1 0x00000002
-#define regk_iop_sw_cfg_trig4_2 0x00000002
-#define regk_iop_sw_cfg_trig4_3 0x00000002
-#define regk_iop_sw_cfg_trig5_0 0x00000002
-#define regk_iop_sw_cfg_trig5_1 0x00000002
-#define regk_iop_sw_cfg_trig5_2 0x00000002
-#define regk_iop_sw_cfg_trig5_3 0x00000002
-#define regk_iop_sw_cfg_trig6_0 0x00000003
-#define regk_iop_sw_cfg_trig6_1 0x00000003
-#define regk_iop_sw_cfg_trig6_2 0x00000003
-#define regk_iop_sw_cfg_trig6_3 0x00000003
-#define regk_iop_sw_cfg_trig7_0 0x00000003
-#define regk_iop_sw_cfg_trig7_1 0x00000003
-#define regk_iop_sw_cfg_trig7_2 0x00000003
-#define regk_iop_sw_cfg_trig7_3 0x00000003
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index 89f36dc1f96d..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,951 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_mpu_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mpu_trace_offset 0
-
-/* Register r_spu_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_spu_trace_offset 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 16
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 20
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 24
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 28
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat_offset 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36
-
-/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48
-
-/* Register r_bus_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus_in_offset 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 72
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 76
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 80
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 84
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 88
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 92
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 96
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
-#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
-#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
-#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
-#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
-#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
-#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
-#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
-#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
-#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 100
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 104
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy 0x00000000
-#define regk_iop_sw_cpu_no 0x00000000
-#define regk_iop_sw_cpu_rd 0x00000002
-#define regk_iop_sw_cpu_reg_copy 0x00000001
-#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
-#define regk_iop_sw_cpu_wr 0x00000003
-#define regk_iop_sw_cpu_yes 0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index 45e19d79dba9..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1087 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_mpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register r_spu_trace, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_spu_trace_offset 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 16
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 20
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 24
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 28
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat_offset 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36
-
-/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48
-
-/* Register r_bus_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus_in_offset 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 72
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 76
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 80
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0_offset 92
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1_offset 108
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2_offset 124
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3_offset 140
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy 0x00000000
-#define regk_iop_sw_mpu_cpu 0x00000000
-#define regk_iop_sw_mpu_mpu 0x00000001
-#define regk_iop_sw_mpu_no 0x00000000
-#define regk_iop_sw_mpu_nop 0x00000000
-#define regk_iop_sw_mpu_rd 0x00000002
-#define regk_iop_sw_mpu_reg_copy 0x00000001
-#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
-#define regk_iop_sw_mpu_set 0x00000001
-#define regk_iop_sw_mpu_spu 0x00000002
-#define regk_iop_sw_mpu_wr 0x00000003
-#define regk_iop_sw_mpu_yes 0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 55afb6e320e4..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_spu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_mpu_trace, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_trace_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_spu_r_mc_stat_offset 24
-
-/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28
-
-/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_offset 32
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40
-
-/* Register r_bus_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus_in_offset 44
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 52
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 64
-
-/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68
-
-/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72
-
-/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76
-
-/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 116
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 120
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15
-#define reg_iop_sw_spu_r_hw_intr_offset 124
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 128
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr_offset 132
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy 0x00000000
-#define regk_iop_sw_spu_no 0x00000000
-#define regk_iop_sw_spu_nop 0x00000000
-#define regk_iop_sw_spu_rd 0x00000002
-#define regk_iop_sw_spu_reg_copy 0x00000001
-#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_spu_set 0x00000001
-#define regk_iop_sw_spu_wr 0x00000003
-#define regk_iop_sw_spu_yes 0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index 79ff8fafd3bf..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_version.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v2_0 0x00000002
-#endif /* __iop_version_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h
deleted file mode 100644
index 23d731f36145..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
- */
-#define regi_iop_version (regi_iop + 0)
-#define regi_iop_fifo_in_extra (regi_iop + 64)
-#define regi_iop_fifo_out_extra (regi_iop + 128)
-#define regi_iop_trigger_grp0 (regi_iop + 192)
-#define regi_iop_trigger_grp1 (regi_iop + 256)
-#define regi_iop_trigger_grp2 (regi_iop + 320)
-#define regi_iop_trigger_grp3 (regi_iop + 384)
-#define regi_iop_trigger_grp4 (regi_iop + 448)
-#define regi_iop_trigger_grp5 (regi_iop + 512)
-#define regi_iop_trigger_grp6 (regi_iop + 576)
-#define regi_iop_trigger_grp7 (regi_iop + 640)
-#define regi_iop_crc_par (regi_iop + 768)
-#define regi_iop_dmc_in (regi_iop + 896)
-#define regi_iop_dmc_out (regi_iop + 1024)
-#define regi_iop_fifo_in (regi_iop + 1152)
-#define regi_iop_fifo_out (regi_iop + 1280)
-#define regi_iop_scrc_in (regi_iop + 1408)
-#define regi_iop_scrc_out (regi_iop + 1536)
-#define regi_iop_timer_grp0 (regi_iop + 1664)
-#define regi_iop_timer_grp1 (regi_iop + 1792)
-#define regi_iop_sap_in (regi_iop + 2048)
-#define regi_iop_sap_out (regi_iop + 2304)
-#define regi_iop_spu (regi_iop + 2560)
-#define regi_iop_sw_cfg (regi_iop + 2816)
-#define regi_iop_sw_cpu (regi_iop + 3072)
-#define regi_iop_sw_mpu (regi_iop + 3328)
-#define regi_iop_sw_spu (regi_iop + 3584)
-#define regi_iop_mpu (regi_iop + 4096)
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h
deleted file mode 100644
index 1d6c09a3230d..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_h
-#define __iop_sap_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_in.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_in */
-
-#define STRIDE_iop_sap_in_rw_bus_byte 4
-/* Register rw_bus_byte, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int sync_sel : 2;
- unsigned int sync_ext_src : 3;
- unsigned int sync_edge : 2;
- unsigned int delay : 2;
- unsigned int dummy1 : 23;
-} reg_iop_sap_in_rw_bus_byte;
-#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
-#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int sync_sel : 2;
- unsigned int sync_ext_src : 3;
- unsigned int sync_edge : 2;
- unsigned int delay : 2;
- unsigned int logic : 2;
- unsigned int dummy1 : 21;
-} reg_iop_sap_in_rw_gio;
-#define REG_RD_ADDR_iop_sap_in_rw_gio 16
-#define REG_WR_ADDR_iop_sap_in_rw_gio 16
-
-
-/* Constants */
-enum {
- regk_iop_sap_in_and = 0x00000002,
- regk_iop_sap_in_ext_clk200 = 0x00000003,
- regk_iop_sap_in_gio0 = 0x00000000,
- regk_iop_sap_in_gio12 = 0x00000003,
- regk_iop_sap_in_gio16 = 0x00000004,
- regk_iop_sap_in_gio20 = 0x00000005,
- regk_iop_sap_in_gio24 = 0x00000006,
- regk_iop_sap_in_gio28 = 0x00000007,
- regk_iop_sap_in_gio4 = 0x00000001,
- regk_iop_sap_in_gio8 = 0x00000002,
- regk_iop_sap_in_inv = 0x00000001,
- regk_iop_sap_in_neg = 0x00000002,
- regk_iop_sap_in_no = 0x00000000,
- regk_iop_sap_in_no_del_ext_clk200 = 0x00000002,
- regk_iop_sap_in_none = 0x00000000,
- regk_iop_sap_in_one = 0x00000001,
- regk_iop_sap_in_or = 0x00000003,
- regk_iop_sap_in_pos = 0x00000001,
- regk_iop_sap_in_pos_neg = 0x00000003,
- regk_iop_sap_in_rw_bus_byte_default = 0x00000000,
- regk_iop_sap_in_rw_bus_byte_size = 0x00000004,
- regk_iop_sap_in_rw_gio_default = 0x00000000,
- regk_iop_sap_in_rw_gio_size = 0x00000020,
- regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000,
- regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001,
- regk_iop_sap_in_tmr_clk200 = 0x00000001,
- regk_iop_sap_in_two = 0x00000002,
- regk_iop_sap_in_two_clk200 = 0x00000000
-};
-#endif /* __iop_sap_in_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h
deleted file mode 100644
index 1cbd30efadb7..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_h
-#define __iop_sap_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_out.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_out */
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int clk0_src : 2;
- unsigned int clk0_gate_src : 2;
- unsigned int clk0_force_src : 3;
- unsigned int clk1_src : 2;
- unsigned int clk1_gate_src : 2;
- unsigned int clk1_force_src : 3;
- unsigned int dummy1 : 18;
-} reg_iop_sap_out_rw_gen_gated;
-#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
-#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
-
-/* Register rw_bus, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 2;
- unsigned int byte0_clk_ext : 2;
- unsigned int byte0_gated_clk : 1;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_delay : 1;
- unsigned int byte1_clk_sel : 2;
- unsigned int byte1_clk_ext : 2;
- unsigned int byte1_gated_clk : 1;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_delay : 1;
- unsigned int byte2_clk_sel : 2;
- unsigned int byte2_clk_ext : 2;
- unsigned int byte2_gated_clk : 1;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_delay : 1;
- unsigned int byte3_clk_sel : 2;
- unsigned int byte3_clk_ext : 2;
- unsigned int byte3_gated_clk : 1;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_delay : 1;
- unsigned int dummy1 : 4;
-} reg_iop_sap_out_rw_bus;
-#define REG_RD_ADDR_iop_sap_out_rw_bus 4
-#define REG_WR_ADDR_iop_sap_out_rw_bus 4
-
-/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 2;
- unsigned int byte0_clk_ext : 2;
- unsigned int byte0_gated_clk : 1;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_delay : 1;
- unsigned int byte0_logic : 2;
- unsigned int byte0_logic_src : 2;
- unsigned int byte1_clk_sel : 2;
- unsigned int byte1_clk_ext : 2;
- unsigned int byte1_gated_clk : 1;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_delay : 1;
- unsigned int byte1_logic : 2;
- unsigned int byte1_logic_src : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
-#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
-
-/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte2_clk_sel : 2;
- unsigned int byte2_clk_ext : 2;
- unsigned int byte2_gated_clk : 1;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_delay : 1;
- unsigned int byte2_logic : 2;
- unsigned int byte2_logic_src : 2;
- unsigned int byte3_clk_sel : 2;
- unsigned int byte3_clk_ext : 2;
- unsigned int byte3_gated_clk : 1;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_delay : 1;
- unsigned int byte3_logic : 2;
- unsigned int byte3_logic_src : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
-#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int out_clk_sel : 3;
- unsigned int out_clk_ext : 2;
- unsigned int out_gated_clk : 1;
- unsigned int out_clk_inv : 1;
- unsigned int out_delay : 1;
- unsigned int out_logic : 2;
- unsigned int out_logic_src : 2;
- unsigned int oe_clk_sel : 3;
- unsigned int oe_clk_ext : 2;
- unsigned int oe_gated_clk : 1;
- unsigned int oe_clk_inv : 1;
- unsigned int oe_delay : 1;
- unsigned int oe_logic : 2;
- unsigned int oe_logic_src : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sap_out_rw_gio;
-#define REG_RD_ADDR_iop_sap_out_rw_gio 16
-#define REG_WR_ADDR_iop_sap_out_rw_gio 16
-
-
-/* Constants */
-enum {
- regk_iop_sap_out_always = 0x00000001,
- regk_iop_sap_out_and = 0x00000002,
- regk_iop_sap_out_clk0 = 0x00000000,
- regk_iop_sap_out_clk1 = 0x00000001,
- regk_iop_sap_out_clk12 = 0x00000004,
- regk_iop_sap_out_clk200 = 0x00000000,
- regk_iop_sap_out_ext = 0x00000002,
- regk_iop_sap_out_gated = 0x00000003,
- regk_iop_sap_out_gio0 = 0x00000000,
- regk_iop_sap_out_gio1 = 0x00000000,
- regk_iop_sap_out_gio16 = 0x00000002,
- regk_iop_sap_out_gio17 = 0x00000002,
- regk_iop_sap_out_gio24 = 0x00000003,
- regk_iop_sap_out_gio25 = 0x00000003,
- regk_iop_sap_out_gio8 = 0x00000001,
- regk_iop_sap_out_gio9 = 0x00000001,
- regk_iop_sap_out_gio_out10 = 0x00000005,
- regk_iop_sap_out_gio_out18 = 0x00000006,
- regk_iop_sap_out_gio_out2 = 0x00000004,
- regk_iop_sap_out_gio_out26 = 0x00000007,
- regk_iop_sap_out_inv = 0x00000001,
- regk_iop_sap_out_nand = 0x00000003,
- regk_iop_sap_out_no = 0x00000000,
- regk_iop_sap_out_none = 0x00000000,
- regk_iop_sap_out_one = 0x00000001,
- regk_iop_sap_out_rw_bus_default = 0x00000000,
- regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000,
- regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
- regk_iop_sap_out_rw_gio_default = 0x00000000,
- regk_iop_sap_out_rw_gio_size = 0x00000020,
- regk_iop_sap_out_spu_gio6 = 0x00000002,
- regk_iop_sap_out_spu_gio7 = 0x00000003,
- regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000,
- regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001,
- regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002,
- regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003,
- regk_iop_sap_out_tmr200 = 0x00000001,
- regk_iop_sap_out_yes = 0x00000001
-};
-#endif /* __iop_sap_out_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h
deleted file mode 100644
index 07050b053bb4..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h
+++ /dev/null
@@ -1,726 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_h
-#define __iop_sw_cfg_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cfg.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cfg */
-
-/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0
-
-/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
-
-/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
-
-/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
-
-/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
-
-/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
-
-/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32
-
-/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
-
-/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
-
-/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 1;
- unsigned int dummy1 : 31;
-} reg_iop_sw_cfg_rw_spu_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp4_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp5_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp6_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp7_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
-
-/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88
-
-/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus_byte0 : 2;
- unsigned int bus_byte1 : 2;
- unsigned int bus_byte2 : 2;
- unsigned int bus_byte3 : 2;
- unsigned int gio3_0 : 2;
- unsigned int gio7_4 : 2;
- unsigned int gio11_8 : 2;
- unsigned int gio15_12 : 2;
- unsigned int gio19_16 : 2;
- unsigned int gio23_20 : 2;
- unsigned int gio27_24 : 2;
- unsigned int gio31_28 : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_pinmapping;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
-#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus_lo : 2;
- unsigned int bus_hi : 2;
- unsigned int bus_lo_oe : 2;
- unsigned int bus_hi_oe : 2;
- unsigned int dummy1 : 24;
-} reg_iop_sw_cfg_rw_bus_out_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio0 : 3;
- unsigned int gio0_oe : 1;
- unsigned int gio1 : 3;
- unsigned int gio1_oe : 1;
- unsigned int gio2 : 3;
- unsigned int gio2_oe : 1;
- unsigned int gio3 : 3;
- unsigned int gio3_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio4 : 3;
- unsigned int gio4_oe : 1;
- unsigned int gio5 : 3;
- unsigned int gio5_oe : 1;
- unsigned int gio6 : 3;
- unsigned int gio6_oe : 1;
- unsigned int gio7 : 3;
- unsigned int gio7_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio8 : 3;
- unsigned int gio8_oe : 1;
- unsigned int gio9 : 3;
- unsigned int gio9_oe : 1;
- unsigned int gio10 : 3;
- unsigned int gio10_oe : 1;
- unsigned int gio11 : 3;
- unsigned int gio11_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio12 : 3;
- unsigned int gio12_oe : 1;
- unsigned int gio13 : 3;
- unsigned int gio13_oe : 1;
- unsigned int gio14 : 3;
- unsigned int gio14_oe : 1;
- unsigned int gio15 : 3;
- unsigned int gio15_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio16 : 3;
- unsigned int gio16_oe : 1;
- unsigned int gio17 : 3;
- unsigned int gio17_oe : 1;
- unsigned int gio18 : 3;
- unsigned int gio18_oe : 1;
- unsigned int gio19 : 3;
- unsigned int gio19_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio20 : 3;
- unsigned int gio20_oe : 1;
- unsigned int gio21 : 3;
- unsigned int gio21_oe : 1;
- unsigned int gio22 : 3;
- unsigned int gio22_oe : 1;
- unsigned int gio23 : 3;
- unsigned int gio23_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio24 : 3;
- unsigned int gio24_oe : 1;
- unsigned int gio25 : 3;
- unsigned int gio25_oe : 1;
- unsigned int gio26 : 3;
- unsigned int gio26_oe : 1;
- unsigned int gio27 : 3;
- unsigned int gio27_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio28 : 3;
- unsigned int gio28_oe : 1;
- unsigned int gio29 : 3;
- unsigned int gio29_oe : 1;
- unsigned int gio30 : 3;
- unsigned int gio30_oe : 1;
- unsigned int gio31 : 3;
- unsigned int gio31_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
-
-/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_in : 1;
- unsigned int bus1_in : 1;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 2;
- unsigned int tmr1_en : 2;
- unsigned int tmr2_en : 2;
- unsigned int tmr3_en : 2;
- unsigned int tmr0_dis : 2;
- unsigned int tmr1_dis : 2;
- unsigned int tmr2_dis : 2;
- unsigned int tmr3_dis : 2;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_timer_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 2;
- unsigned int tmr1_en : 2;
- unsigned int tmr2_en : 2;
- unsigned int tmr3_en : 2;
- unsigned int tmr0_dis : 2;
- unsigned int tmr1_dis : 2;
- unsigned int tmr2_dis : 2;
- unsigned int tmr3_dis : 2;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_timer_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int grp0_dis : 1;
- unsigned int grp0_en : 1;
- unsigned int grp1_dis : 1;
- unsigned int grp1_en : 1;
- unsigned int grp2_dis : 1;
- unsigned int grp2_en : 1;
- unsigned int grp3_dis : 1;
- unsigned int grp3_en : 1;
- unsigned int grp4_dis : 1;
- unsigned int grp4_en : 1;
- unsigned int grp5_dis : 1;
- unsigned int grp5_en : 1;
- unsigned int grp6_dis : 1;
- unsigned int grp6_en : 1;
- unsigned int grp7_dis : 1;
- unsigned int grp7_en : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_trigger_grps_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
-
-/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int out_strb : 4;
- unsigned int in_src : 2;
- unsigned int in_size : 3;
- unsigned int in_last : 2;
- unsigned int in_strb : 4;
- unsigned int dummy1 : 17;
-} reg_iop_sw_cfg_rw_pdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int sdp_out_strb : 3;
- unsigned int sdp_in_data : 3;
- unsigned int sdp_in_last : 2;
- unsigned int sdp_in_strb : 3;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_sdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164
-#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164
-
-
-/* Constants */
-enum {
- regk_iop_sw_cfg_a = 0x00000001,
- regk_iop_sw_cfg_b = 0x00000002,
- regk_iop_sw_cfg_bus = 0x00000000,
- regk_iop_sw_cfg_bus_rot16 = 0x00000002,
- regk_iop_sw_cfg_bus_rot24 = 0x00000003,
- regk_iop_sw_cfg_bus_rot8 = 0x00000001,
- regk_iop_sw_cfg_clk12 = 0x00000000,
- regk_iop_sw_cfg_cpu = 0x00000000,
- regk_iop_sw_cfg_gated_clk0 = 0x0000000e,
- regk_iop_sw_cfg_gated_clk1 = 0x0000000f,
- regk_iop_sw_cfg_gio0 = 0x00000004,
- regk_iop_sw_cfg_gio1 = 0x00000001,
- regk_iop_sw_cfg_gio2 = 0x00000005,
- regk_iop_sw_cfg_gio3 = 0x00000002,
- regk_iop_sw_cfg_gio4 = 0x00000006,
- regk_iop_sw_cfg_gio5 = 0x00000003,
- regk_iop_sw_cfg_gio6 = 0x00000007,
- regk_iop_sw_cfg_gio7 = 0x00000004,
- regk_iop_sw_cfg_gio_in18 = 0x00000002,
- regk_iop_sw_cfg_gio_in19 = 0x00000003,
- regk_iop_sw_cfg_gio_in20 = 0x00000004,
- regk_iop_sw_cfg_gio_in21 = 0x00000005,
- regk_iop_sw_cfg_gio_in26 = 0x00000006,
- regk_iop_sw_cfg_gio_in27 = 0x00000007,
- regk_iop_sw_cfg_gio_in4 = 0x00000000,
- regk_iop_sw_cfg_gio_in5 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002,
- regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003,
- regk_iop_sw_cfg_mpu = 0x00000001,
- regk_iop_sw_cfg_none = 0x00000000,
- regk_iop_sw_cfg_pdp_out = 0x00000001,
- regk_iop_sw_cfg_pdp_out_hi = 0x00000001,
- regk_iop_sw_cfg_pdp_out_lo = 0x00000000,
- regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555,
- regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
- regk_iop_sw_cfg_sdp_out = 0x00000004,
- regk_iop_sw_cfg_size16 = 0x00000002,
- regk_iop_sw_cfg_size24 = 0x00000003,
- regk_iop_sw_cfg_size32 = 0x00000004,
- regk_iop_sw_cfg_size8 = 0x00000001,
- regk_iop_sw_cfg_spu = 0x00000002,
- regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002,
- regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002,
- regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003,
- regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003,
- regk_iop_sw_cfg_spu_g0 = 0x00000007,
- regk_iop_sw_cfg_spu_g1 = 0x00000007,
- regk_iop_sw_cfg_spu_g2 = 0x00000007,
- regk_iop_sw_cfg_spu_g3 = 0x00000007,
- regk_iop_sw_cfg_spu_g4 = 0x00000007,
- regk_iop_sw_cfg_spu_g5 = 0x00000007,
- regk_iop_sw_cfg_spu_g6 = 0x00000007,
- regk_iop_sw_cfg_spu_g7 = 0x00000007,
- regk_iop_sw_cfg_spu_gio0 = 0x00000000,
- regk_iop_sw_cfg_spu_gio1 = 0x00000001,
- regk_iop_sw_cfg_spu_gio5 = 0x00000005,
- regk_iop_sw_cfg_spu_gio6 = 0x00000006,
- regk_iop_sw_cfg_spu_gio7 = 0x00000007,
- regk_iop_sw_cfg_spu_gio_out0 = 0x00000008,
- regk_iop_sw_cfg_spu_gio_out1 = 0x00000009,
- regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a,
- regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b,
- regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c,
- regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d,
- regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e,
- regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f,
- regk_iop_sw_cfg_spu_gioout0 = 0x00000000,
- regk_iop_sw_cfg_spu_gioout1 = 0x00000000,
- regk_iop_sw_cfg_spu_gioout10 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout11 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout12 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout13 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout14 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout15 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout16 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout17 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout18 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout19 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout2 = 0x00000001,
- regk_iop_sw_cfg_spu_gioout20 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout21 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout22 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout23 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout24 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout25 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout26 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout27 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout28 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout29 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout3 = 0x00000001,
- regk_iop_sw_cfg_spu_gioout30 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout31 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout4 = 0x00000002,
- regk_iop_sw_cfg_spu_gioout5 = 0x00000002,
- regk_iop_sw_cfg_spu_gioout6 = 0x00000003,
- regk_iop_sw_cfg_spu_gioout7 = 0x00000003,
- regk_iop_sw_cfg_spu_gioout8 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout9 = 0x00000007,
- regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
- regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003,
- regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
- regk_iop_sw_cfg_timer_grp0 = 0x00000000,
- regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002,
- regk_iop_sw_cfg_timer_grp1 = 0x00000000,
- regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003,
- regk_iop_sw_cfg_trig0_0 = 0x00000000,
- regk_iop_sw_cfg_trig0_1 = 0x00000000,
- regk_iop_sw_cfg_trig0_2 = 0x00000000,
- regk_iop_sw_cfg_trig0_3 = 0x00000000,
- regk_iop_sw_cfg_trig1_0 = 0x00000000,
- regk_iop_sw_cfg_trig1_1 = 0x00000000,
- regk_iop_sw_cfg_trig1_2 = 0x00000000,
- regk_iop_sw_cfg_trig1_3 = 0x00000000,
- regk_iop_sw_cfg_trig2_0 = 0x00000001,
- regk_iop_sw_cfg_trig2_1 = 0x00000001,
- regk_iop_sw_cfg_trig2_2 = 0x00000001,
- regk_iop_sw_cfg_trig2_3 = 0x00000001,
- regk_iop_sw_cfg_trig3_0 = 0x00000001,
- regk_iop_sw_cfg_trig3_1 = 0x00000001,
- regk_iop_sw_cfg_trig3_2 = 0x00000001,
- regk_iop_sw_cfg_trig3_3 = 0x00000001,
- regk_iop_sw_cfg_trig4_0 = 0x00000002,
- regk_iop_sw_cfg_trig4_1 = 0x00000002,
- regk_iop_sw_cfg_trig4_2 = 0x00000002,
- regk_iop_sw_cfg_trig4_3 = 0x00000002,
- regk_iop_sw_cfg_trig5_0 = 0x00000002,
- regk_iop_sw_cfg_trig5_1 = 0x00000002,
- regk_iop_sw_cfg_trig5_2 = 0x00000002,
- regk_iop_sw_cfg_trig5_3 = 0x00000002,
- regk_iop_sw_cfg_trig6_0 = 0x00000003,
- regk_iop_sw_cfg_trig6_1 = 0x00000003,
- regk_iop_sw_cfg_trig6_2 = 0x00000003,
- regk_iop_sw_cfg_trig6_3 = 0x00000003,
- regk_iop_sw_cfg_trig7_0 = 0x00000003,
- regk_iop_sw_cfg_trig7_1 = 0x00000003,
- regk_iop_sw_cfg_trig7_2 = 0x00000003,
- regk_iop_sw_cfg_trig7_3 = 0x00000003
-};
-#endif /* __iop_sw_cfg_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h
deleted file mode 100644
index b4acdae4f653..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_h
-#define __iop_sw_cpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cpu */
-
-/* Register r_mpu_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
-
-/* Register r_spu_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu_mem : 1;
- unsigned int dummy1 : 25;
-} reg_iop_sw_cpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu : 1;
- unsigned int dummy1 : 26;
-} reg_iop_sw_cpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
-
-/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
-
-/* Register r_bus_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_rw_intr0_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_rw_ack_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_r_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_r_masked_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dmc_in : 1;
- unsigned int dmc_out : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_rw_intr1_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dmc_in : 1;
- unsigned int dmc_out : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dmc_in : 1;
- unsigned int dmc_out : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_masked_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
-
-
-/* Constants */
-enum {
- regk_iop_sw_cpu_copy = 0x00000000,
- regk_iop_sw_cpu_no = 0x00000000,
- regk_iop_sw_cpu_rd = 0x00000002,
- regk_iop_sw_cpu_reg_copy = 0x00000001,
- regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
- regk_iop_sw_cpu_wr = 0x00000003,
- regk_iop_sw_cpu_yes = 0x00000001
-};
-#endif /* __iop_sw_cpu_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h
deleted file mode 100644
index bc1abb5fb308..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h
+++ /dev/null
@@ -1,649 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_h
-#define __iop_sw_mpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_mpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_mpu */
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_mpu_rw_sw_cfg_owner;
-#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-
-/* Register r_spu_trace, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
-#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
-#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu_mem : 1;
- unsigned int dummy1 : 25;
-} reg_iop_sw_mpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu : 1;
- unsigned int dummy1 : 26;
-} reg_iop_sw_mpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
-
-/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
-
-/* Register r_bus_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
-#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp0_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr1 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr2 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr3 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr5 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr6 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr7 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp1_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr5 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr6 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr7 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr5 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr6 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr7 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr5 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr6 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr7 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp2_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr9 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr10 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr11 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr13 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr14 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr15 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp3_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr13 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr14 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr15 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr13 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr14 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr15 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr13 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr14 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr15 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
-
-
-/* Constants */
-enum {
- regk_iop_sw_mpu_copy = 0x00000000,
- regk_iop_sw_mpu_cpu = 0x00000000,
- regk_iop_sw_mpu_mpu = 0x00000001,
- regk_iop_sw_mpu_no = 0x00000000,
- regk_iop_sw_mpu_nop = 0x00000000,
- regk_iop_sw_mpu_rd = 0x00000002,
- regk_iop_sw_mpu_reg_copy = 0x00000001,
- regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
- regk_iop_sw_mpu_set = 0x00000001,
- regk_iop_sw_mpu_spu = 0x00000002,
- regk_iop_sw_mpu_wr = 0x00000003,
- regk_iop_sw_mpu_yes = 0x00000001
-};
-#endif /* __iop_sw_mpu_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h
deleted file mode 100644
index 82b64360a4d3..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_h
-#define __iop_sw_spu_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_spu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_spu */
-
-/* Register r_mpu_trace, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu_mem : 1;
- unsigned int dummy1 : 25;
-} reg_iop_sw_spu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-typedef unsigned int reg_iop_sw_spu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu : 1;
- unsigned int dummy1 : 26;
-} reg_iop_sw_spu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
-
-/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
-
-/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
-
-/* Register r_bus_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
-
-/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
-
-/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
-
-/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
-
-/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
-#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_hw_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
-#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
-
-
-/* Constants */
-enum {
- regk_iop_sw_spu_copy = 0x00000000,
- regk_iop_sw_spu_no = 0x00000000,
- regk_iop_sw_spu_nop = 0x00000000,
- regk_iop_sw_spu_rd = 0x00000002,
- regk_iop_sw_spu_reg_copy = 0x00000001,
- regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_spu_set = 0x00000001,
- regk_iop_sw_spu_wr = 0x00000003,
- regk_iop_sw_spu_yes = 0x00000001
-};
-#endif /* __iop_sw_spu_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h
deleted file mode 100644
index d944c6ce5f9b..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_h
-#define __iop_version_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_version.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_version */
-
-/* Register r_version, scope iop_version, type r */
-typedef struct {
- unsigned int nr : 8;
- unsigned int dummy1 : 24;
-} reg_iop_version_r_version;
-#define REG_RD_ADDR_iop_version_r_version 0
-
-
-/* Constants */
-enum {
- regk_iop_version_v2_0 = 0x00000002
-};
-#endif /* __iop_version_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h
deleted file mode 100644
index 5c72116f1067..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __l2cache_defs_h
-#define __l2cache_defs_h
-
-/*
- * This file is autogenerated from
- * file: l2cache.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope l2cache */
-
-/* Register rw_cfg, scope l2cache, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_l2cache_rw_cfg;
-#define REG_RD_ADDR_l2cache_rw_cfg 0
-#define REG_WR_ADDR_l2cache_rw_cfg 0
-
-/* Register rw_ctrl, scope l2cache, type rw */
-typedef struct {
- unsigned int dummy1 : 7;
- unsigned int cbase : 9;
- unsigned int dummy2 : 4;
- unsigned int csize : 10;
- unsigned int dummy3 : 2;
-} reg_l2cache_rw_ctrl;
-#define REG_RD_ADDR_l2cache_rw_ctrl 4
-#define REG_WR_ADDR_l2cache_rw_ctrl 4
-
-/* Register rw_idxop, scope l2cache, type rw */
-typedef struct {
- unsigned int idx : 10;
- unsigned int dummy1 : 14;
- unsigned int way : 3;
- unsigned int dummy2 : 2;
- unsigned int cmd : 3;
-} reg_l2cache_rw_idxop;
-#define REG_RD_ADDR_l2cache_rw_idxop 8
-#define REG_WR_ADDR_l2cache_rw_idxop 8
-
-/* Register rw_addrop_addr, scope l2cache, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_l2cache_rw_addrop_addr;
-#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
-#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
-
-/* Register rw_addrop_ctrl, scope l2cache, type rw */
-typedef struct {
- unsigned int size : 16;
- unsigned int dummy1 : 13;
- unsigned int cmd : 3;
-} reg_l2cache_rw_addrop_ctrl;
-#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
-#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
-
-
-/* Constants */
-enum {
- regk_l2cache_flush = 0x00000001,
- regk_l2cache_no = 0x00000000,
- regk_l2cache_rw_addrop_addr_default = 0x00000000,
- regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
- regk_l2cache_rw_cfg_default = 0x00000000,
- regk_l2cache_rw_ctrl_default = 0x00000000,
- regk_l2cache_rw_idxop_default = 0x00000000,
- regk_l2cache_yes = 0x00000001
-};
-#endif /* __l2cache_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h
deleted file mode 100644
index 84f68755a75c..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_bar_defs_h
-#define __marb_bar_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_bar.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bar */
-
-#define STRIDE_marb_bar_rw_ddr2_slots 4
-/* Register rw_ddr2_slots, scope marb_bar, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_bar_rw_ddr2_slots;
-#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
-#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
-
-/* Register rw_h264_rd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_h264_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
-#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
-
-/* Register rw_h264_wr_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_h264_wr_burst;
-#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
-#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
-
-/* Register rw_ccd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_ccd_burst;
-#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
-#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
-
-/* Register rw_vin_wr_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_vin_wr_burst;
-#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
-#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
-
-/* Register rw_vin_rd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_vin_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
-#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
-
-/* Register rw_sclr_rd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_sclr_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
-#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
-
-/* Register rw_vout_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_vout_burst;
-#define REG_RD_ADDR_marb_bar_rw_vout_burst 280
-#define REG_WR_ADDR_marb_bar_rw_vout_burst 280
-
-/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_sclr_fifo_burst;
-#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
-#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
-
-/* Register rw_l2cache_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_l2cache_burst;
-#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
-#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
-
-/* Register rw_intr_mask, scope marb_bar, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_rw_intr_mask;
-#define REG_RD_ADDR_marb_bar_rw_intr_mask 292
-#define REG_WR_ADDR_marb_bar_rw_intr_mask 292
-
-/* Register rw_ack_intr, scope marb_bar, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_rw_ack_intr;
-#define REG_RD_ADDR_marb_bar_rw_ack_intr 296
-#define REG_WR_ADDR_marb_bar_rw_ack_intr 296
-
-/* Register r_intr, scope marb_bar, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_r_intr;
-#define REG_RD_ADDR_marb_bar_r_intr 300
-
-/* Register r_masked_intr, scope marb_bar, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_r_masked_intr;
-#define REG_RD_ADDR_marb_bar_r_masked_intr 304
-
-/* Register rw_stop_mask, scope marb_bar, type rw */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_rw_stop_mask;
-#define REG_RD_ADDR_marb_bar_rw_stop_mask 308
-#define REG_WR_ADDR_marb_bar_rw_stop_mask 308
-
-/* Register r_stopped, scope marb_bar, type r */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_r_stopped;
-#define REG_RD_ADDR_marb_bar_r_stopped 312
-
-/* Register rw_no_snoop, scope marb_bar, type rw */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_rw_no_snoop;
-#define REG_RD_ADDR_marb_bar_rw_no_snoop 576
-#define REG_WR_ADDR_marb_bar_rw_no_snoop 576
-
-
-/* Constants */
-enum {
- regk_marb_bar_ccd = 0x00000002,
- regk_marb_bar_h264_rd = 0x00000000,
- regk_marb_bar_h264_wr = 0x00000001,
- regk_marb_bar_l2cache = 0x00000008,
- regk_marb_bar_no = 0x00000000,
- regk_marb_bar_r_stopped_default = 0x00000000,
- regk_marb_bar_rw_ccd_burst_default = 0x00000000,
- regk_marb_bar_rw_ddr2_slots_default = 0x00000000,
- regk_marb_bar_rw_ddr2_slots_size = 0x00000040,
- regk_marb_bar_rw_h264_rd_burst_default = 0x00000000,
- regk_marb_bar_rw_h264_wr_burst_default = 0x00000000,
- regk_marb_bar_rw_intr_mask_default = 0x00000000,
- regk_marb_bar_rw_l2cache_burst_default = 0x00000000,
- regk_marb_bar_rw_no_snoop_default = 0x00000000,
- regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
- regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000,
- regk_marb_bar_rw_stop_mask_default = 0x00000000,
- regk_marb_bar_rw_vin_rd_burst_default = 0x00000000,
- regk_marb_bar_rw_vin_wr_burst_default = 0x00000000,
- regk_marb_bar_rw_vout_burst_default = 0x00000000,
- regk_marb_bar_sclr_fifo = 0x00000007,
- regk_marb_bar_sclr_rd = 0x00000005,
- regk_marb_bar_vin_rd = 0x00000004,
- regk_marb_bar_vin_wr = 0x00000003,
- regk_marb_bar_vout = 0x00000006,
- regk_marb_bar_yes = 0x00000001
-};
-#endif /* __marb_bar_defs_h */
-#ifndef __marb_bar_bp_defs_h
-#define __marb_bar_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_bar.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bar_bp */
-
-/* Register rw_first_addr, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bar_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bar_bp_rw_op;
-#define REG_RD_ADDR_marb_bar_bp_rw_op 8
-#define REG_WR_ADDR_marb_bar_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bar_bp, type rw */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_bp_rw_clients;
-#define REG_RD_ADDR_marb_bar_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bar_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bar_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bar_bp_rw_options;
-#define REG_RD_ADDR_marb_bar_bp_rw_options 16
-#define REG_WR_ADDR_marb_bar_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bar_bp, type r */
-typedef unsigned int reg_marb_bar_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bar_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bar_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bar_bp, type r */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bar_bp, type r */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bar_bp, type r */
-typedef unsigned int reg_marb_bar_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_ack;
-#define REG_RD_ADDR_marb_bar_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bar_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bar_bp_no = 0x00000000,
- regk_marb_bar_bp_rw_op_default = 0x00000000,
- regk_marb_bar_bp_rw_options_default = 0x00000000,
- regk_marb_bar_bp_yes = 0x00000001
-};
-#endif /* __marb_bar_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h
deleted file mode 100644
index 13539bc5d613..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h
+++ /dev/null
@@ -1,627 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_foo_defs_h
-#define __marb_foo_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_foo.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_foo */
-
-#define STRIDE_marb_foo_rw_intm_slots 4
-/* Register rw_intm_slots, scope marb_foo, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_intm_slots;
-#define REG_RD_ADDR_marb_foo_rw_intm_slots 0
-#define REG_WR_ADDR_marb_foo_rw_intm_slots 0
-
-#define STRIDE_marb_foo_rw_l2_slots 4
-/* Register rw_l2_slots, scope marb_foo, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_l2_slots;
-#define REG_RD_ADDR_marb_foo_rw_l2_slots 256
-#define REG_WR_ADDR_marb_foo_rw_l2_slots 256
-
-#define STRIDE_marb_foo_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb_foo, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_regs_slots;
-#define REG_RD_ADDR_marb_foo_rw_regs_slots 512
-#define REG_WR_ADDR_marb_foo_rw_regs_slots 512
-
-/* Register rw_sclr_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_sclr_burst;
-#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528
-#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528
-
-/* Register rw_dma0_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma0_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532
-#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532
-
-/* Register rw_dma1_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma1_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536
-#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536
-
-/* Register rw_dma2_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma2_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540
-#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540
-
-/* Register rw_dma3_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma3_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544
-#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544
-
-/* Register rw_dma4_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma4_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548
-#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548
-
-/* Register rw_dma5_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma5_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552
-#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552
-
-/* Register rw_dma6_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma6_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556
-#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556
-
-/* Register rw_dma7_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma7_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560
-#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560
-
-/* Register rw_dma9_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma9_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564
-#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564
-
-/* Register rw_dma11_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma11_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568
-#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568
-
-/* Register rw_cpui_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_cpui_burst;
-#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572
-#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572
-
-/* Register rw_cpud_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_cpud_burst;
-#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576
-#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576
-
-/* Register rw_iop_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_iop_burst;
-#define REG_RD_ADDR_marb_foo_rw_iop_burst 580
-#define REG_WR_ADDR_marb_foo_rw_iop_burst 580
-
-/* Register rw_ccdstat_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_ccdstat_burst;
-#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584
-#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584
-
-/* Register rw_intr_mask, scope marb_foo, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_intr_mask;
-#define REG_RD_ADDR_marb_foo_rw_intr_mask 588
-#define REG_WR_ADDR_marb_foo_rw_intr_mask 588
-
-/* Register rw_ack_intr, scope marb_foo, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_ack_intr;
-#define REG_RD_ADDR_marb_foo_rw_ack_intr 592
-#define REG_WR_ADDR_marb_foo_rw_ack_intr 592
-
-/* Register r_intr, scope marb_foo, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_r_intr;
-#define REG_RD_ADDR_marb_foo_r_intr 596
-
-/* Register r_masked_intr, scope marb_foo, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_r_masked_intr;
-#define REG_RD_ADDR_marb_foo_r_masked_intr 600
-
-/* Register rw_stop_mask, scope marb_foo, type rw */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_rw_stop_mask;
-#define REG_RD_ADDR_marb_foo_rw_stop_mask 604
-#define REG_WR_ADDR_marb_foo_rw_stop_mask 604
-
-/* Register r_stopped, scope marb_foo, type r */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_r_stopped;
-#define REG_RD_ADDR_marb_foo_r_stopped 608
-
-/* Register rw_no_snoop, scope marb_foo, type rw */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_rw_no_snoop;
-#define REG_RD_ADDR_marb_foo_rw_no_snoop 896
-#define REG_WR_ADDR_marb_foo_rw_no_snoop 896
-
-/* Register rw_no_snoop_rq, scope marb_foo, type rw */
-typedef struct {
- unsigned int dummy1 : 11;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int dummy2 : 19;
-} reg_marb_foo_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900
-#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900
-
-
-/* Constants */
-enum {
- regk_marb_foo_ccdstat = 0x0000000e,
- regk_marb_foo_cpud = 0x0000000c,
- regk_marb_foo_cpui = 0x0000000b,
- regk_marb_foo_dma0 = 0x00000001,
- regk_marb_foo_dma1 = 0x00000002,
- regk_marb_foo_dma11 = 0x0000000a,
- regk_marb_foo_dma2 = 0x00000003,
- regk_marb_foo_dma3 = 0x00000004,
- regk_marb_foo_dma4 = 0x00000005,
- regk_marb_foo_dma5 = 0x00000006,
- regk_marb_foo_dma6 = 0x00000007,
- regk_marb_foo_dma7 = 0x00000008,
- regk_marb_foo_dma9 = 0x00000009,
- regk_marb_foo_iop = 0x0000000d,
- regk_marb_foo_no = 0x00000000,
- regk_marb_foo_r_stopped_default = 0x00000000,
- regk_marb_foo_rw_ccdstat_burst_default = 0x00000000,
- regk_marb_foo_rw_cpud_burst_default = 0x00000000,
- regk_marb_foo_rw_cpui_burst_default = 0x00000000,
- regk_marb_foo_rw_dma0_burst_default = 0x00000000,
- regk_marb_foo_rw_dma11_burst_default = 0x00000000,
- regk_marb_foo_rw_dma1_burst_default = 0x00000000,
- regk_marb_foo_rw_dma2_burst_default = 0x00000000,
- regk_marb_foo_rw_dma3_burst_default = 0x00000000,
- regk_marb_foo_rw_dma4_burst_default = 0x00000000,
- regk_marb_foo_rw_dma5_burst_default = 0x00000000,
- regk_marb_foo_rw_dma6_burst_default = 0x00000000,
- regk_marb_foo_rw_dma7_burst_default = 0x00000000,
- regk_marb_foo_rw_dma9_burst_default = 0x00000000,
- regk_marb_foo_rw_intm_slots_default = 0x00000000,
- regk_marb_foo_rw_intm_slots_size = 0x00000040,
- regk_marb_foo_rw_intr_mask_default = 0x00000000,
- regk_marb_foo_rw_iop_burst_default = 0x00000000,
- regk_marb_foo_rw_l2_slots_default = 0x00000000,
- regk_marb_foo_rw_l2_slots_size = 0x00000040,
- regk_marb_foo_rw_no_snoop_default = 0x00000000,
- regk_marb_foo_rw_no_snoop_rq_default = 0x00000000,
- regk_marb_foo_rw_regs_slots_default = 0x00000000,
- regk_marb_foo_rw_regs_slots_size = 0x00000004,
- regk_marb_foo_rw_sclr_burst_default = 0x00000000,
- regk_marb_foo_rw_stop_mask_default = 0x00000000,
- regk_marb_foo_sclr = 0x00000000,
- regk_marb_foo_yes = 0x00000001
-};
-#endif /* __marb_foo_defs_h */
-#ifndef __marb_foo_bp_defs_h
-#define __marb_foo_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_foo.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_foo_bp */
-
-/* Register rw_first_addr, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_foo_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_foo_bp_rw_op;
-#define REG_RD_ADDR_marb_foo_bp_rw_op 8
-#define REG_WR_ADDR_marb_foo_bp_rw_op 8
-
-/* Register rw_clients, scope marb_foo_bp, type rw */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_bp_rw_clients;
-#define REG_RD_ADDR_marb_foo_bp_rw_clients 12
-#define REG_WR_ADDR_marb_foo_bp_rw_clients 12
-
-/* Register rw_options, scope marb_foo_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_foo_bp_rw_options;
-#define REG_RD_ADDR_marb_foo_bp_rw_options 16
-#define REG_WR_ADDR_marb_foo_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_foo_bp, type r */
-typedef unsigned int reg_marb_foo_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_foo_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_foo_bp_r_brk_op;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_foo_bp, type r */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_foo_bp, type r */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_foo_bp, type r */
-typedef unsigned int reg_marb_foo_bp_r_brk_size;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_ack;
-#define REG_RD_ADDR_marb_foo_bp_rw_ack 40
-#define REG_WR_ADDR_marb_foo_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_foo_bp_no = 0x00000000,
- regk_marb_foo_bp_rw_op_default = 0x00000000,
- regk_marb_foo_bp_rw_options_default = 0x00000000,
- regk_marb_foo_bp_yes = 0x00000001
-};
-#endif /* __marb_foo_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h
deleted file mode 100644
index d604042a52bf..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: pinmux.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
- unsigned int eth : 1;
- unsigned int eth_mdio : 1;
- unsigned int geth : 1;
- unsigned int tg : 1;
- unsigned int tg_clk : 1;
- unsigned int vout : 1;
- unsigned int vout_sync : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int pwm0 : 1;
- unsigned int pwm1 : 1;
- unsigned int pwm2 : 1;
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int pio : 1;
- unsigned int i2c0 : 1;
- unsigned int i2c1 : 1;
- unsigned int i2c1_sda1 : 1;
- unsigned int i2c1_sda2 : 1;
- unsigned int i2c1_sda3 : 1;
- unsigned int i2c1_sen : 1;
- unsigned int dummy1 : 8;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 0
-#define REG_WR_ADDR_pinmux_rw_hwprot 0
-
-/* Register rw_gio_pa, scope pinmux, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int pa8 : 1;
- unsigned int pa9 : 1;
- unsigned int pa10 : 1;
- unsigned int pa11 : 1;
- unsigned int pa12 : 1;
- unsigned int pa13 : 1;
- unsigned int pa14 : 1;
- unsigned int pa15 : 1;
- unsigned int pa16 : 1;
- unsigned int pa17 : 1;
- unsigned int pa18 : 1;
- unsigned int pa19 : 1;
- unsigned int pa20 : 1;
- unsigned int pa21 : 1;
- unsigned int pa22 : 1;
- unsigned int pa23 : 1;
- unsigned int pa24 : 1;
- unsigned int pa25 : 1;
- unsigned int pa26 : 1;
- unsigned int pa27 : 1;
- unsigned int pa28 : 1;
- unsigned int pa29 : 1;
- unsigned int pa30 : 1;
- unsigned int pa31 : 1;
-} reg_pinmux_rw_gio_pa;
-#define REG_RD_ADDR_pinmux_rw_gio_pa 4
-#define REG_WR_ADDR_pinmux_rw_gio_pa 4
-
-/* Register rw_gio_pb, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int pb8 : 1;
- unsigned int pb9 : 1;
- unsigned int pb10 : 1;
- unsigned int pb11 : 1;
- unsigned int pb12 : 1;
- unsigned int pb13 : 1;
- unsigned int pb14 : 1;
- unsigned int pb15 : 1;
- unsigned int pb16 : 1;
- unsigned int pb17 : 1;
- unsigned int pb18 : 1;
- unsigned int pb19 : 1;
- unsigned int pb20 : 1;
- unsigned int pb21 : 1;
- unsigned int pb22 : 1;
- unsigned int pb23 : 1;
- unsigned int pb24 : 1;
- unsigned int pb25 : 1;
- unsigned int pb26 : 1;
- unsigned int pb27 : 1;
- unsigned int pb28 : 1;
- unsigned int pb29 : 1;
- unsigned int pb30 : 1;
- unsigned int pb31 : 1;
-} reg_pinmux_rw_gio_pb;
-#define REG_RD_ADDR_pinmux_rw_gio_pb 8
-#define REG_WR_ADDR_pinmux_rw_gio_pb 8
-
-/* Register rw_gio_pc, scope pinmux, type rw */
-typedef struct {
- unsigned int pc0 : 1;
- unsigned int pc1 : 1;
- unsigned int pc2 : 1;
- unsigned int pc3 : 1;
- unsigned int pc4 : 1;
- unsigned int pc5 : 1;
- unsigned int pc6 : 1;
- unsigned int pc7 : 1;
- unsigned int pc8 : 1;
- unsigned int pc9 : 1;
- unsigned int pc10 : 1;
- unsigned int pc11 : 1;
- unsigned int pc12 : 1;
- unsigned int pc13 : 1;
- unsigned int pc14 : 1;
- unsigned int pc15 : 1;
- unsigned int dummy1 : 16;
-} reg_pinmux_rw_gio_pc;
-#define REG_RD_ADDR_pinmux_rw_gio_pc 12
-#define REG_WR_ADDR_pinmux_rw_gio_pc 12
-
-/* Register rw_iop_pa, scope pinmux, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int pa8 : 1;
- unsigned int pa9 : 1;
- unsigned int pa10 : 1;
- unsigned int pa11 : 1;
- unsigned int pa12 : 1;
- unsigned int pa13 : 1;
- unsigned int pa14 : 1;
- unsigned int pa15 : 1;
- unsigned int pa16 : 1;
- unsigned int pa17 : 1;
- unsigned int pa18 : 1;
- unsigned int pa19 : 1;
- unsigned int pa20 : 1;
- unsigned int pa21 : 1;
- unsigned int pa22 : 1;
- unsigned int pa23 : 1;
- unsigned int pa24 : 1;
- unsigned int pa25 : 1;
- unsigned int pa26 : 1;
- unsigned int pa27 : 1;
- unsigned int pa28 : 1;
- unsigned int pa29 : 1;
- unsigned int pa30 : 1;
- unsigned int pa31 : 1;
-} reg_pinmux_rw_iop_pa;
-#define REG_RD_ADDR_pinmux_rw_iop_pa 16
-#define REG_WR_ADDR_pinmux_rw_iop_pa 16
-
-/* Register rw_iop_pb, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int dummy1 : 24;
-} reg_pinmux_rw_iop_pb;
-#define REG_RD_ADDR_pinmux_rw_iop_pb 20
-#define REG_WR_ADDR_pinmux_rw_iop_pb 20
-
-/* Register rw_iop_pio, scope pinmux, type rw */
-typedef struct {
- unsigned int d0 : 1;
- unsigned int d1 : 1;
- unsigned int d2 : 1;
- unsigned int d3 : 1;
- unsigned int d4 : 1;
- unsigned int d5 : 1;
- unsigned int d6 : 1;
- unsigned int d7 : 1;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pinmux_rw_iop_pio;
-#define REG_RD_ADDR_pinmux_rw_iop_pio 24
-#define REG_WR_ADDR_pinmux_rw_iop_pio 24
-
-/* Register rw_iop_usb, scope pinmux, type rw */
-typedef struct {
- unsigned int usb0 : 1;
- unsigned int dummy1 : 31;
-} reg_pinmux_rw_iop_usb;
-#define REG_RD_ADDR_pinmux_rw_iop_usb 28
-#define REG_WR_ADDR_pinmux_rw_iop_usb 28
-
-
-/* Constants */
-enum {
- regk_pinmux_no = 0x00000000,
- regk_pinmux_rw_gio_pa_default = 0x00000000,
- regk_pinmux_rw_gio_pb_default = 0x00000000,
- regk_pinmux_rw_gio_pc_default = 0x00000000,
- regk_pinmux_rw_hwprot_default = 0x00000000,
- regk_pinmux_rw_iop_pa_default = 0x00000000,
- regk_pinmux_rw_iop_pb_default = 0x00000000,
- regk_pinmux_rw_iop_pio_default = 0x00000000,
- regk_pinmux_rw_iop_usb_default = 0x00000001,
- regk_pinmux_yes = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h
deleted file mode 100644
index 348e39f419e0..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pio_defs_h
-#define __pio_defs_h
-
-/*
- * This file is autogenerated from
- * file: pio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pio */
-
-/* Register rw_data, scope pio, type rw */
-typedef unsigned int reg_pio_rw_data;
-#define REG_RD_ADDR_pio_rw_data 64
-#define REG_WR_ADDR_pio_rw_data 64
-
-/* Register rw_io_access0, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access0;
-#define REG_RD_ADDR_pio_rw_io_access0 0
-#define REG_WR_ADDR_pio_rw_io_access0 0
-
-/* Register rw_io_access1, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access1;
-#define REG_RD_ADDR_pio_rw_io_access1 4
-#define REG_WR_ADDR_pio_rw_io_access1 4
-
-/* Register rw_io_access2, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access2;
-#define REG_RD_ADDR_pio_rw_io_access2 8
-#define REG_WR_ADDR_pio_rw_io_access2 8
-
-/* Register rw_io_access3, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access3;
-#define REG_RD_ADDR_pio_rw_io_access3 12
-#define REG_WR_ADDR_pio_rw_io_access3 12
-
-/* Register rw_io_access4, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access4;
-#define REG_RD_ADDR_pio_rw_io_access4 16
-#define REG_WR_ADDR_pio_rw_io_access4 16
-
-/* Register rw_io_access5, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access5;
-#define REG_RD_ADDR_pio_rw_io_access5 20
-#define REG_WR_ADDR_pio_rw_io_access5 20
-
-/* Register rw_io_access6, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access6;
-#define REG_RD_ADDR_pio_rw_io_access6 24
-#define REG_WR_ADDR_pio_rw_io_access6 24
-
-/* Register rw_io_access7, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access7;
-#define REG_RD_ADDR_pio_rw_io_access7 28
-#define REG_WR_ADDR_pio_rw_io_access7 28
-
-/* Register rw_io_access8, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access8;
-#define REG_RD_ADDR_pio_rw_io_access8 32
-#define REG_WR_ADDR_pio_rw_io_access8 32
-
-/* Register rw_io_access9, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access9;
-#define REG_RD_ADDR_pio_rw_io_access9 36
-#define REG_WR_ADDR_pio_rw_io_access9 36
-
-/* Register rw_io_access10, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access10;
-#define REG_RD_ADDR_pio_rw_io_access10 40
-#define REG_WR_ADDR_pio_rw_io_access10 40
-
-/* Register rw_io_access11, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access11;
-#define REG_RD_ADDR_pio_rw_io_access11 44
-#define REG_WR_ADDR_pio_rw_io_access11 44
-
-/* Register rw_io_access12, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access12;
-#define REG_RD_ADDR_pio_rw_io_access12 48
-#define REG_WR_ADDR_pio_rw_io_access12 48
-
-/* Register rw_io_access13, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access13;
-#define REG_RD_ADDR_pio_rw_io_access13 52
-#define REG_WR_ADDR_pio_rw_io_access13 52
-
-/* Register rw_io_access14, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access14;
-#define REG_RD_ADDR_pio_rw_io_access14 56
-#define REG_WR_ADDR_pio_rw_io_access14 56
-
-/* Register rw_io_access15, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access15;
-#define REG_RD_ADDR_pio_rw_io_access15 60
-#define REG_WR_ADDR_pio_rw_io_access15 60
-
-/* Register rw_ce0_cfg, scope pio, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int mode : 2;
- unsigned int dummy1 : 16;
-} reg_pio_rw_ce0_cfg;
-#define REG_RD_ADDR_pio_rw_ce0_cfg 68
-#define REG_WR_ADDR_pio_rw_ce0_cfg 68
-
-/* Register rw_ce1_cfg, scope pio, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int mode : 2;
- unsigned int dummy1 : 16;
-} reg_pio_rw_ce1_cfg;
-#define REG_RD_ADDR_pio_rw_ce1_cfg 72
-#define REG_WR_ADDR_pio_rw_ce1_cfg 72
-
-/* Register rw_ce2_cfg, scope pio, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int mode : 2;
- unsigned int dummy1 : 16;
-} reg_pio_rw_ce2_cfg;
-#define REG_RD_ADDR_pio_rw_ce2_cfg 76
-#define REG_WR_ADDR_pio_rw_ce2_cfg 76
-
-/* Register rw_dout, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_rw_dout;
-#define REG_RD_ADDR_pio_rw_dout 80
-#define REG_WR_ADDR_pio_rw_dout 80
-
-/* Register rw_oe, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_rw_oe;
-#define REG_RD_ADDR_pio_rw_oe 84
-#define REG_WR_ADDR_pio_rw_oe 84
-
-/* Register rw_man_ctrl, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_rw_man_ctrl;
-#define REG_RD_ADDR_pio_rw_man_ctrl 88
-#define REG_WR_ADDR_pio_rw_man_ctrl 88
-
-/* Register r_din, scope pio, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_r_din;
-#define REG_RD_ADDR_pio_r_din 92
-
-/* Register r_stat, scope pio, type r */
-typedef struct {
- unsigned int busy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_r_stat;
-#define REG_RD_ADDR_pio_r_stat 96
-
-/* Register rw_intr_mask, scope pio, type rw */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_rw_intr_mask;
-#define REG_RD_ADDR_pio_rw_intr_mask 100
-#define REG_WR_ADDR_pio_rw_intr_mask 100
-
-/* Register rw_ack_intr, scope pio, type rw */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_rw_ack_intr;
-#define REG_RD_ADDR_pio_rw_ack_intr 104
-#define REG_WR_ADDR_pio_rw_ack_intr 104
-
-/* Register r_intr, scope pio, type r */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_r_intr;
-#define REG_RD_ADDR_pio_r_intr 108
-
-/* Register r_masked_intr, scope pio, type r */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_r_masked_intr;
-#define REG_RD_ADDR_pio_r_masked_intr 112
-
-
-/* Constants */
-enum {
- regk_pio_a2 = 0x00000003,
- regk_pio_no = 0x00000000,
- regk_pio_normal = 0x00000000,
- regk_pio_rd = 0x00000001,
- regk_pio_rw_ce0_cfg_default = 0x00000000,
- regk_pio_rw_ce1_cfg_default = 0x00000000,
- regk_pio_rw_ce2_cfg_default = 0x00000000,
- regk_pio_rw_intr_mask_default = 0x00000000,
- regk_pio_rw_man_ctrl_default = 0x00000000,
- regk_pio_rw_oe_default = 0x00000000,
- regk_pio_wr = 0x00000002,
- regk_pio_wr_ce2 = 0x00000003,
- regk_pio_yes = 0x00000001,
- regk_pio_yes_all = 0x000000ff
-};
-#endif /* __pio_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h
deleted file mode 100644
index 04ef87d42513..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- * file: reg.rmap
- *
- * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-typedef enum {
- regi_ccd = 0xb0000000,
- regi_ccd_top = 0xb0000000,
- regi_ccd_dp = 0xb0000400,
- regi_ccd_stat = 0xb0000800,
- regi_ccd_tg = 0xb0001000,
- regi_cfg = 0xb0002000,
- regi_clkgen = 0xb0004000,
- regi_ddr2_ctrl = 0xb0006000,
- regi_dma0 = 0xb0008000,
- regi_dma1 = 0xb000a000,
- regi_dma11 = 0xb000c000,
- regi_dma2 = 0xb000e000,
- regi_dma3 = 0xb0010000,
- regi_dma4 = 0xb0012000,
- regi_dma5 = 0xb0014000,
- regi_dma6 = 0xb0016000,
- regi_dma7 = 0xb0018000,
- regi_dma9 = 0xb001a000,
- regi_eth = 0xb001c000,
- regi_gio = 0xb0020000,
- regi_h264 = 0xb0022000,
- regi_hist = 0xb0026000,
- regi_iop = 0xb0028000,
- regi_iop_version = 0xb0028000,
- regi_iop_fifo_in_extra = 0xb0028040,
- regi_iop_fifo_out_extra = 0xb0028080,
- regi_iop_trigger_grp0 = 0xb00280c0,
- regi_iop_trigger_grp1 = 0xb0028100,
- regi_iop_trigger_grp2 = 0xb0028140,
- regi_iop_trigger_grp3 = 0xb0028180,
- regi_iop_trigger_grp4 = 0xb00281c0,
- regi_iop_trigger_grp5 = 0xb0028200,
- regi_iop_trigger_grp6 = 0xb0028240,
- regi_iop_trigger_grp7 = 0xb0028280,
- regi_iop_crc_par = 0xb0028300,
- regi_iop_dmc_in = 0xb0028380,
- regi_iop_dmc_out = 0xb0028400,
- regi_iop_fifo_in = 0xb0028480,
- regi_iop_fifo_out = 0xb0028500,
- regi_iop_scrc_in = 0xb0028580,
- regi_iop_scrc_out = 0xb0028600,
- regi_iop_timer_grp0 = 0xb0028680,
- regi_iop_timer_grp1 = 0xb0028700,
- regi_iop_sap_in = 0xb0028800,
- regi_iop_sap_out = 0xb0028900,
- regi_iop_spu = 0xb0028a00,
- regi_iop_sw_cfg = 0xb0028b00,
- regi_iop_sw_cpu = 0xb0028c00,
- regi_iop_sw_mpu = 0xb0028d00,
- regi_iop_sw_spu = 0xb0028e00,
- regi_iop_mpu = 0xb0029000,
- regi_irq = 0xb002a000,
- regi_irq2 = 0xb006a000,
- regi_jpeg = 0xb002c000,
- regi_l2cache = 0xb0030000,
- regi_marb_bar = 0xb0032000,
- regi_marb_bar_bp0 = 0xb0032140,
- regi_marb_bar_bp1 = 0xb0032180,
- regi_marb_bar_bp2 = 0xb00321c0,
- regi_marb_bar_bp3 = 0xb0032200,
- regi_marb_foo = 0xb0034000,
- regi_marb_foo_bp0 = 0xb0034280,
- regi_marb_foo_bp1 = 0xb00342c0,
- regi_marb_foo_bp2 = 0xb0034300,
- regi_marb_foo_bp3 = 0xb0034340,
- regi_pinmux = 0xb0038000,
- regi_pio = 0xb0036000,
- regi_sclr = 0xb003a000,
- regi_sclr_fifo = 0xb003c000,
- regi_ser0 = 0xb003e000,
- regi_ser1 = 0xb0040000,
- regi_ser2 = 0xb0042000,
- regi_ser3 = 0xb0044000,
- regi_ser4 = 0xb0046000,
- regi_sser = 0xb0048000,
- regi_strcop = 0xb004a000,
- regi_strdma0 = 0xb004e000,
- regi_strdma1 = 0xb0050000,
- regi_strdma2 = 0xb0052000,
- regi_strdma3 = 0xb0054000,
- regi_strdma5 = 0xb0056000,
- regi_strmux = 0xb004c000,
- regi_timer0 = 0xb0058000,
- regi_timer1 = 0xb005a000,
- regi_timer2 = 0xb006e000,
- regi_trace = 0xb005c000,
- regi_vin = 0xb005e000,
- regi_vout = 0xb0060000
-} reg_scope_instances;
-#endif /* __reg_map_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h
deleted file mode 100644
index a19955fa8d94..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: strmux.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
- unsigned int dma0 : 2;
- unsigned int dma1 : 2;
- unsigned int dma2 : 2;
- unsigned int dma3 : 2;
- unsigned int dma4 : 2;
- unsigned int dma5 : 2;
- unsigned int dma6 : 2;
- unsigned int dma7 : 2;
- unsigned int dummy1 : 2;
- unsigned int dma9 : 2;
- unsigned int dummy2 : 2;
- unsigned int dma11 : 2;
- unsigned int dummy3 : 8;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
- regk_strmux_eth = 0x00000001,
- regk_strmux_h264 = 0x00000001,
- regk_strmux_iop = 0x00000001,
- regk_strmux_jpeg = 0x00000001,
- regk_strmux_off = 0x00000000,
- regk_strmux_rw_cfg_default = 0x00000000,
- regk_strmux_ser0 = 0x00000002,
- regk_strmux_ser1 = 0x00000002,
- regk_strmux_ser2 = 0x00000002,
- regk_strmux_ser3 = 0x00000002,
- regk_strmux_ser4 = 0x00000002,
- regk_strmux_sser = 0x00000001,
- regk_strmux_strcop = 0x00000001
-};
-#endif /* __strmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h
deleted file mode 100644
index de849a6362f6..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_h
-#define __timer_defs_h
-
-/*
- * This file is autogenerated from
- * file: timer.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope timer */
-
-/* Register rw_tmr0_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr0_div;
-#define REG_RD_ADDR_timer_rw_tmr0_div 0
-#define REG_WR_ADDR_timer_rw_tmr0_div 0
-
-/* Register r_tmr0_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr0_data;
-#define REG_RD_ADDR_timer_r_tmr0_data 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr0_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
-#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr1_div;
-#define REG_RD_ADDR_timer_rw_tmr1_div 16
-#define REG_WR_ADDR_timer_rw_tmr1_div 16
-
-/* Register r_tmr1_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr1_data;
-#define REG_RD_ADDR_timer_r_tmr1_data 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr1_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
-#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_rs_cnt_data;
-#define REG_RD_ADDR_timer_rs_cnt_data 32
-
-/* Register r_cnt_data, scope timer, type r */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_r_cnt_data;
-#define REG_RD_ADDR_timer_r_cnt_data 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-typedef struct {
- unsigned int clk : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_cnt_cfg;
-#define REG_RD_ADDR_timer_rw_cnt_cfg 40
-#define REG_WR_ADDR_timer_rw_cnt_cfg 40
-
-/* Register rw_trig, scope timer, type rw */
-typedef unsigned int reg_timer_rw_trig;
-#define REG_RD_ADDR_timer_rw_trig 48
-#define REG_WR_ADDR_timer_rw_trig 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_trig_cfg;
-#define REG_RD_ADDR_timer_rw_trig_cfg 52
-#define REG_WR_ADDR_timer_rw_trig_cfg 52
-
-/* Register r_time, scope timer, type r */
-typedef unsigned int reg_timer_r_time;
-#define REG_RD_ADDR_timer_r_time 56
-
-/* Register rw_out, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_out;
-#define REG_RD_ADDR_timer_rw_out 60
-#define REG_WR_ADDR_timer_rw_out 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int key : 7;
- unsigned int dummy1 : 16;
-} reg_timer_rw_wd_ctrl;
-#define REG_RD_ADDR_timer_rw_wd_ctrl 64
-#define REG_WR_ADDR_timer_rw_wd_ctrl 64
-
-/* Register r_wd_stat, scope timer, type r */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int dummy1 : 23;
-} reg_timer_r_wd_stat;
-#define REG_RD_ADDR_timer_r_wd_stat 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_intr_mask;
-#define REG_RD_ADDR_timer_rw_intr_mask 72
-#define REG_WR_ADDR_timer_rw_intr_mask 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_ack_intr;
-#define REG_RD_ADDR_timer_rw_ack_intr 76
-#define REG_WR_ADDR_timer_rw_ack_intr 76
-
-/* Register r_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_intr;
-#define REG_RD_ADDR_timer_r_intr 80
-
-/* Register r_masked_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_masked_intr;
-#define REG_RD_ADDR_timer_r_masked_intr 84
-
-/* Register rw_test, scope timer, type rw */
-typedef struct {
- unsigned int dis : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 30;
-} reg_timer_rw_test;
-#define REG_RD_ADDR_timer_rw_test 88
-#define REG_WR_ADDR_timer_rw_test 88
-
-
-/* Constants */
-enum {
- regk_timer_ext = 0x00000001,
- regk_timer_f100 = 0x00000007,
- regk_timer_f29_493 = 0x00000004,
- regk_timer_f32 = 0x00000005,
- regk_timer_f32_768 = 0x00000006,
- regk_timer_f90 = 0x00000003,
- regk_timer_hold = 0x00000001,
- regk_timer_ld = 0x00000000,
- regk_timer_no = 0x00000000,
- regk_timer_off = 0x00000000,
- regk_timer_run = 0x00000002,
- regk_timer_rw_cnt_cfg_default = 0x00000000,
- regk_timer_rw_intr_mask_default = 0x00000000,
- regk_timer_rw_out_default = 0x00000000,
- regk_timer_rw_test_default = 0x00000000,
- regk_timer_rw_tmr0_ctrl_default = 0x00000000,
- regk_timer_rw_tmr1_ctrl_default = 0x00000000,
- regk_timer_rw_trig_cfg_default = 0x00000000,
- regk_timer_start = 0x00000001,
- regk_timer_stop = 0x00000000,
- regk_timer_time = 0x00000001,
- regk_timer_tmr0 = 0x00000002,
- regk_timer_tmr1 = 0x00000003,
- regk_timer_vclk = 0x00000002,
- regk_timer_yes = 0x00000001
-};
-#endif /* __timer_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h b/arch/cris/include/arch-v32/mach-a3/mach/memmap.h
deleted file mode 100644
index 7b9a9a5699b2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00018000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h b/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h
deleted file mode 100644
index 35e3fc97d6a3..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_A 0
-#define PORT_B 1
-#define PORT_C 2
-
-enum pin_mode {
- pinmux_none = 0,
- pinmux_fixed,
- pinmux_gpio,
- pinmux_iop
-};
-
-enum fixed_function {
- pinmux_eth,
- pinmux_geth,
- pinmux_tg_ccd,
- pinmux_tg_cmos,
- pinmux_vout,
- pinmux_ser1,
- pinmux_ser2,
- pinmux_ser3,
- pinmux_ser4,
- pinmux_sser,
- pinmux_pio,
- pinmux_pwm0,
- pinmux_pwm1,
- pinmux_pwm2,
- pinmux_i2c0,
- pinmux_i2c1,
- pinmux_i2c1_3wire,
- pinmux_i2c1_sda1,
- pinmux_i2c1_sda2,
- pinmux_i2c1_sda3,
-};
-
-int crisv32_pinmux_init(void);
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-void crisv32_pinmux_dump(void);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
deleted file mode 100644
index 2d52bcc96ed5..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef STARTUP_INC_INCLUDED
-#define STARTUP_INC_INCLUDED
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-#include <hwregs/asm/pio_defs_asm.h>
-#include <hwregs/asm/clkgen_defs_asm.h>
-#include <hwregs/asm/pinmux_defs_asm.h>
-
- .macro GIO_SET_P BITS, OUTREG
- bmi 1f ; btstq: bit -> N flag
- nop
- or.d \BITS, \OUTREG
-1:
- .endm
-
- .macro GIO_INIT
- move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
- move.d $r0, [$r1]
-
- move.d 0xFFFFFFFF, $r0
- move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
- move.d $r0, [$r1]
- move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
- move.d $r0, [$r1]
-
- ;; If eth_mdio, eth, geth bits are set in hwprot, don't
- ;; set them to gpio, as this means they have been configured
- ;; earlier and shouldn't be changed.
- move.d 0xFC000000, $r2 ; pins 25..0 are eth_mdio, eth, geth
- move.d REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1
- move.d [$r1], $r0
- btstq REG_BIT(pinmux, rw_hwprot, eth), $r0
- GIO_SET_P 0x00FFFF00, $r2 ;; pins 8..23 are eth
- btstq REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0
- GIO_SET_P 0x03000000, $r2 ;; pins 24..25 are eth_mdio
- btstq REG_BIT(pinmux, rw_hwprot, geth), $r0
- GIO_SET_P 0x000000FF, $r2 ;; pins 0..7 are geth
- move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
- move.d $r2, [$r1]
- .endm
-
- .macro START_CLOCKS
- move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \
- REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0
- move.d $r0, [$r1]
- .endm
-
- .macro SETUP_WAIT_STATES
- move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0
- move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0
- move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0
- move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
- move.d $r1, [$r0]
- .endm
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h b/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h
deleted file mode 100644
index f9401a3de83c..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum {
- arbiter_all_dmas = 0x3ff,
- arbiter_cpu = 0xc00,
- arbiter_all_clients = 0x3fff
-};
-
-enum {
- arbiter_all_read = 0x55,
- arbiter_all_write = 0xaa,
- arbiter_all_accesses = 0xff
-};
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback * cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/arch/cris/include/arch-v32/mach-fs/mach/dma.h
deleted file mode 100644
index 53a59944a48b..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/dma.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS 10
-
-#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */
-#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */
-
-#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */
-#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */
-
-#define ATA_TX_DMA_NBR 2 /* ATA interface out. */
-#define ATA_RX_DMA_NBR 3 /* ATA interface in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */
-
-#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */
-#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
-
-#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */
-#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */
-
-#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */
-#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */
-
-#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */
-#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */
-
-#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */
-#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */
-
-#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */
-#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */
-
-#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */
-
-enum dma_owner {
- dma_eth0,
- dma_eth1,
- dma_iop0,
- dma_iop1,
- dma_ser0,
- dma_ser1,
- dma_ser2,
- dma_ser3,
- dma_sser0,
- dma_sser1,
- dma_ata,
- dma_strp,
- dma_ext0,
- dma_ext1,
- dma_ext2,
- dma_ext3
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned bandwidth,
- enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h
deleted file mode 100644
index 092cad384b86..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_asm_h
-#define __bif_core_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp1_cfg___lw___width 6
-#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp1_cfg___ew___width 3
-#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp1_cfg___zw___width 3
-#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp1_cfg___aw___width 2
-#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp1_cfg___dw___width 2
-#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp1_cfg___ewb___width 2
-#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp1_cfg___bw___width 1
-#define reg_bif_core_rw_grp1_cfg___bw___bit 18
-#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp1_cfg___mode___width 1
-#define reg_bif_core_rw_grp1_cfg___mode___bit 21
-#define reg_bif_core_rw_grp1_cfg_offset 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp2_cfg___lw___width 6
-#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp2_cfg___ew___width 3
-#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp2_cfg___zw___width 3
-#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp2_cfg___aw___width 2
-#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp2_cfg___dw___width 2
-#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp2_cfg___ewb___width 2
-#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp2_cfg___bw___width 1
-#define reg_bif_core_rw_grp2_cfg___bw___bit 18
-#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp2_cfg___mode___width 1
-#define reg_bif_core_rw_grp2_cfg___mode___bit 21
-#define reg_bif_core_rw_grp2_cfg_offset 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp3_cfg___lw___width 6
-#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp3_cfg___ew___width 3
-#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp3_cfg___zw___width 3
-#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp3_cfg___aw___width 2
-#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp3_cfg___dw___width 2
-#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp3_cfg___ewb___width 2
-#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp3_cfg___bw___width 1
-#define reg_bif_core_rw_grp3_cfg___bw___bit 18
-#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp3_cfg___mode___width 1
-#define reg_bif_core_rw_grp3_cfg___mode___bit 21
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
-#define reg_bif_core_rw_grp3_cfg_offset 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp4_cfg___lw___width 6
-#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp4_cfg___ew___width 3
-#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp4_cfg___zw___width 3
-#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp4_cfg___aw___width 2
-#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp4_cfg___dw___width 2
-#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp4_cfg___ewb___width 2
-#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp4_cfg___bw___width 1
-#define reg_bif_core_rw_grp4_cfg___bw___bit 18
-#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp4_cfg___mode___width 1
-#define reg_bif_core_rw_grp4_cfg___mode___bit 21
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
-#define reg_bif_core_rw_grp4_cfg_offset 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_timing___cl___lsb 0
-#define reg_bif_core_rw_sdram_timing___cl___width 3
-#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
-#define reg_bif_core_rw_sdram_timing___rcd___width 3
-#define reg_bif_core_rw_sdram_timing___rp___lsb 6
-#define reg_bif_core_rw_sdram_timing___rp___width 3
-#define reg_bif_core_rw_sdram_timing___rc___lsb 9
-#define reg_bif_core_rw_sdram_timing___rc___width 2
-#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
-#define reg_bif_core_rw_sdram_timing___dpl___width 2
-#define reg_bif_core_rw_sdram_timing___pde___lsb 13
-#define reg_bif_core_rw_sdram_timing___pde___width 1
-#define reg_bif_core_rw_sdram_timing___pde___bit 13
-#define reg_bif_core_rw_sdram_timing___ref___lsb 14
-#define reg_bif_core_rw_sdram_timing___ref___width 2
-#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
-#define reg_bif_core_rw_sdram_timing___cpd___width 1
-#define reg_bif_core_rw_sdram_timing___cpd___bit 16
-#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
-#define reg_bif_core_rw_sdram_timing___sdcke___width 1
-#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
-#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
-#define reg_bif_core_rw_sdram_timing___sdclk___width 1
-#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
-#define reg_bif_core_rw_sdram_timing_offset 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
-#define reg_bif_core_rw_sdram_cmd___cmd___width 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
-#define reg_bif_core_rw_sdram_cmd_offset 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
-#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_rs_sdram_ref_stat_offset 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_r_sdram_ref_stat___ok___width 1
-#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_r_sdram_ref_stat_offset 36
-
-
-/* Constants */
-#define regk_bif_core_bank2 0x00000000
-#define regk_bif_core_bank4 0x00000001
-#define regk_bif_core_bit10 0x0000000a
-#define regk_bif_core_bit11 0x0000000b
-#define regk_bif_core_bit12 0x0000000c
-#define regk_bif_core_bit13 0x0000000d
-#define regk_bif_core_bit14 0x0000000e
-#define regk_bif_core_bit15 0x0000000f
-#define regk_bif_core_bit16 0x00000010
-#define regk_bif_core_bit17 0x00000011
-#define regk_bif_core_bit18 0x00000012
-#define regk_bif_core_bit19 0x00000013
-#define regk_bif_core_bit20 0x00000014
-#define regk_bif_core_bit21 0x00000015
-#define regk_bif_core_bit22 0x00000016
-#define regk_bif_core_bit23 0x00000017
-#define regk_bif_core_bit24 0x00000018
-#define regk_bif_core_bit25 0x00000019
-#define regk_bif_core_bit26 0x0000001a
-#define regk_bif_core_bit27 0x0000001b
-#define regk_bif_core_bit28 0x0000001c
-#define regk_bif_core_bit29 0x0000001d
-#define regk_bif_core_bit9 0x00000009
-#define regk_bif_core_bw16 0x00000001
-#define regk_bif_core_bw32 0x00000000
-#define regk_bif_core_bwe 0x00000000
-#define regk_bif_core_cwe 0x00000001
-#define regk_bif_core_e15us 0x00000001
-#define regk_bif_core_e7800ns 0x00000002
-#define regk_bif_core_grp0 0x00000000
-#define regk_bif_core_grp1 0x00000001
-#define regk_bif_core_mrs 0x00000003
-#define regk_bif_core_no 0x00000000
-#define regk_bif_core_none 0x00000000
-#define regk_bif_core_nop 0x00000000
-#define regk_bif_core_off 0x00000000
-#define regk_bif_core_pre 0x00000002
-#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rd 0x00000002
-#define regk_bif_core_ref 0x00000001
-#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
-#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
-#define regk_bif_core_slf 0x00000004
-#define regk_bif_core_wr 0x00000001
-#define regk_bif_core_yes 0x00000001
-#endif /* __bif_core_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h
deleted file mode 100644
index 5b38835b42f7..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_asm_h
-#define __config_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
- * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope config, type r */
-#define reg_config_r_bootsel___boot_mode___lsb 0
-#define reg_config_r_bootsel___boot_mode___width 3
-#define reg_config_r_bootsel___full_duplex___lsb 3
-#define reg_config_r_bootsel___full_duplex___width 1
-#define reg_config_r_bootsel___full_duplex___bit 3
-#define reg_config_r_bootsel___user___lsb 4
-#define reg_config_r_bootsel___user___width 1
-#define reg_config_r_bootsel___user___bit 4
-#define reg_config_r_bootsel___pll___lsb 5
-#define reg_config_r_bootsel___pll___width 1
-#define reg_config_r_bootsel___pll___bit 5
-#define reg_config_r_bootsel___flash_bw___lsb 6
-#define reg_config_r_bootsel___flash_bw___width 1
-#define reg_config_r_bootsel___flash_bw___bit 6
-#define reg_config_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-#define reg_config_rw_clk_ctrl___pll___lsb 0
-#define reg_config_rw_clk_ctrl___pll___width 1
-#define reg_config_rw_clk_ctrl___pll___bit 0
-#define reg_config_rw_clk_ctrl___cpu___lsb 1
-#define reg_config_rw_clk_ctrl___cpu___width 1
-#define reg_config_rw_clk_ctrl___cpu___bit 1
-#define reg_config_rw_clk_ctrl___iop___lsb 2
-#define reg_config_rw_clk_ctrl___iop___width 1
-#define reg_config_rw_clk_ctrl___iop___bit 2
-#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
-#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
-#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
-#define reg_config_rw_clk_ctrl___dma23___lsb 4
-#define reg_config_rw_clk_ctrl___dma23___width 1
-#define reg_config_rw_clk_ctrl___dma23___bit 4
-#define reg_config_rw_clk_ctrl___dma45___lsb 5
-#define reg_config_rw_clk_ctrl___dma45___width 1
-#define reg_config_rw_clk_ctrl___dma45___bit 5
-#define reg_config_rw_clk_ctrl___dma67___lsb 6
-#define reg_config_rw_clk_ctrl___dma67___width 1
-#define reg_config_rw_clk_ctrl___dma67___bit 6
-#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
-#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
-#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
-#define reg_config_rw_clk_ctrl___bif___lsb 8
-#define reg_config_rw_clk_ctrl___bif___width 1
-#define reg_config_rw_clk_ctrl___bif___bit 8
-#define reg_config_rw_clk_ctrl___fix_io___lsb 9
-#define reg_config_rw_clk_ctrl___fix_io___width 1
-#define reg_config_rw_clk_ctrl___fix_io___bit 9
-#define reg_config_rw_clk_ctrl_offset 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
-#define reg_config_rw_pad_ctrl___usb_susp___width 1
-#define reg_config_rw_pad_ctrl___usb_susp___bit 0
-#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
-#define reg_config_rw_pad_ctrl___phyrst_n___width 1
-#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
-#define reg_config_rw_pad_ctrl_offset 8
-
-
-/* Constants */
-#define regk_config_bw16 0x00000000
-#define regk_config_bw32 0x00000001
-#define regk_config_master 0x00000005
-#define regk_config_nand 0x00000003
-#define regk_config_net_rx 0x00000001
-#define regk_config_net_tx_rx 0x00000002
-#define regk_config_no 0x00000000
-#define regk_config_none 0x00000007
-#define regk_config_nor 0x00000000
-#define regk_config_rw_clk_ctrl_default 0x00000002
-#define regk_config_rw_pad_ctrl_default 0x00000000
-#define regk_config_ser 0x00000004
-#define regk_config_slave 0x00000006
-#define regk_config_yes 0x00000001
-#endif /* __config_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 3d2056892832..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/gio/rtl/gio_regs.r
- * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- * last modfied: Mon Apr 11 16:07:47 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
- * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 8
-#define reg_gio_rw_pa_dout_offset 0
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 8
-#define reg_gio_r_pa_din_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 8
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___pa0___lsb 0
-#define reg_gio_rw_intr_cfg___pa0___width 3
-#define reg_gio_rw_intr_cfg___pa1___lsb 3
-#define reg_gio_rw_intr_cfg___pa1___width 3
-#define reg_gio_rw_intr_cfg___pa2___lsb 6
-#define reg_gio_rw_intr_cfg___pa2___width 3
-#define reg_gio_rw_intr_cfg___pa3___lsb 9
-#define reg_gio_rw_intr_cfg___pa3___width 3
-#define reg_gio_rw_intr_cfg___pa4___lsb 12
-#define reg_gio_rw_intr_cfg___pa4___width 3
-#define reg_gio_rw_intr_cfg___pa5___lsb 15
-#define reg_gio_rw_intr_cfg___pa5___width 3
-#define reg_gio_rw_intr_cfg___pa6___lsb 18
-#define reg_gio_rw_intr_cfg___pa6___width 3
-#define reg_gio_rw_intr_cfg___pa7___lsb 21
-#define reg_gio_rw_intr_cfg___pa7___width 3
-#define reg_gio_rw_intr_cfg_offset 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___pa0___lsb 0
-#define reg_gio_rw_intr_mask___pa0___width 1
-#define reg_gio_rw_intr_mask___pa0___bit 0
-#define reg_gio_rw_intr_mask___pa1___lsb 1
-#define reg_gio_rw_intr_mask___pa1___width 1
-#define reg_gio_rw_intr_mask___pa1___bit 1
-#define reg_gio_rw_intr_mask___pa2___lsb 2
-#define reg_gio_rw_intr_mask___pa2___width 1
-#define reg_gio_rw_intr_mask___pa2___bit 2
-#define reg_gio_rw_intr_mask___pa3___lsb 3
-#define reg_gio_rw_intr_mask___pa3___width 1
-#define reg_gio_rw_intr_mask___pa3___bit 3
-#define reg_gio_rw_intr_mask___pa4___lsb 4
-#define reg_gio_rw_intr_mask___pa4___width 1
-#define reg_gio_rw_intr_mask___pa4___bit 4
-#define reg_gio_rw_intr_mask___pa5___lsb 5
-#define reg_gio_rw_intr_mask___pa5___width 1
-#define reg_gio_rw_intr_mask___pa5___bit 5
-#define reg_gio_rw_intr_mask___pa6___lsb 6
-#define reg_gio_rw_intr_mask___pa6___width 1
-#define reg_gio_rw_intr_mask___pa6___bit 6
-#define reg_gio_rw_intr_mask___pa7___lsb 7
-#define reg_gio_rw_intr_mask___pa7___width 1
-#define reg_gio_rw_intr_mask___pa7___bit 7
-#define reg_gio_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___pa0___lsb 0
-#define reg_gio_rw_ack_intr___pa0___width 1
-#define reg_gio_rw_ack_intr___pa0___bit 0
-#define reg_gio_rw_ack_intr___pa1___lsb 1
-#define reg_gio_rw_ack_intr___pa1___width 1
-#define reg_gio_rw_ack_intr___pa1___bit 1
-#define reg_gio_rw_ack_intr___pa2___lsb 2
-#define reg_gio_rw_ack_intr___pa2___width 1
-#define reg_gio_rw_ack_intr___pa2___bit 2
-#define reg_gio_rw_ack_intr___pa3___lsb 3
-#define reg_gio_rw_ack_intr___pa3___width 1
-#define reg_gio_rw_ack_intr___pa3___bit 3
-#define reg_gio_rw_ack_intr___pa4___lsb 4
-#define reg_gio_rw_ack_intr___pa4___width 1
-#define reg_gio_rw_ack_intr___pa4___bit 4
-#define reg_gio_rw_ack_intr___pa5___lsb 5
-#define reg_gio_rw_ack_intr___pa5___width 1
-#define reg_gio_rw_ack_intr___pa5___bit 5
-#define reg_gio_rw_ack_intr___pa6___lsb 6
-#define reg_gio_rw_ack_intr___pa6___width 1
-#define reg_gio_rw_ack_intr___pa6___bit 6
-#define reg_gio_rw_ack_intr___pa7___lsb 7
-#define reg_gio_rw_ack_intr___pa7___width 1
-#define reg_gio_rw_ack_intr___pa7___bit 7
-#define reg_gio_rw_ack_intr_offset 20
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___pa0___lsb 0
-#define reg_gio_r_intr___pa0___width 1
-#define reg_gio_r_intr___pa0___bit 0
-#define reg_gio_r_intr___pa1___lsb 1
-#define reg_gio_r_intr___pa1___width 1
-#define reg_gio_r_intr___pa1___bit 1
-#define reg_gio_r_intr___pa2___lsb 2
-#define reg_gio_r_intr___pa2___width 1
-#define reg_gio_r_intr___pa2___bit 2
-#define reg_gio_r_intr___pa3___lsb 3
-#define reg_gio_r_intr___pa3___width 1
-#define reg_gio_r_intr___pa3___bit 3
-#define reg_gio_r_intr___pa4___lsb 4
-#define reg_gio_r_intr___pa4___width 1
-#define reg_gio_r_intr___pa4___bit 4
-#define reg_gio_r_intr___pa5___lsb 5
-#define reg_gio_r_intr___pa5___width 1
-#define reg_gio_r_intr___pa5___bit 5
-#define reg_gio_r_intr___pa6___lsb 6
-#define reg_gio_r_intr___pa6___width 1
-#define reg_gio_r_intr___pa6___bit 6
-#define reg_gio_r_intr___pa7___lsb 7
-#define reg_gio_r_intr___pa7___width 1
-#define reg_gio_r_intr___pa7___bit 7
-#define reg_gio_r_intr_offset 24
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___pa0___lsb 0
-#define reg_gio_r_masked_intr___pa0___width 1
-#define reg_gio_r_masked_intr___pa0___bit 0
-#define reg_gio_r_masked_intr___pa1___lsb 1
-#define reg_gio_r_masked_intr___pa1___width 1
-#define reg_gio_r_masked_intr___pa1___bit 1
-#define reg_gio_r_masked_intr___pa2___lsb 2
-#define reg_gio_r_masked_intr___pa2___width 1
-#define reg_gio_r_masked_intr___pa2___bit 2
-#define reg_gio_r_masked_intr___pa3___lsb 3
-#define reg_gio_r_masked_intr___pa3___width 1
-#define reg_gio_r_masked_intr___pa3___bit 3
-#define reg_gio_r_masked_intr___pa4___lsb 4
-#define reg_gio_r_masked_intr___pa4___width 1
-#define reg_gio_r_masked_intr___pa4___bit 4
-#define reg_gio_r_masked_intr___pa5___lsb 5
-#define reg_gio_r_masked_intr___pa5___width 1
-#define reg_gio_r_masked_intr___pa5___bit 5
-#define reg_gio_r_masked_intr___pa6___lsb 6
-#define reg_gio_r_masked_intr___pa6___width 1
-#define reg_gio_r_masked_intr___pa6___bit 6
-#define reg_gio_r_masked_intr___pa7___lsb 7
-#define reg_gio_r_masked_intr___pa7___width 1
-#define reg_gio_r_masked_intr___pa7___bit 7
-#define reg_gio_r_masked_intr_offset 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 18
-#define reg_gio_rw_pb_dout_offset 32
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 18
-#define reg_gio_r_pb_din_offset 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 18
-#define reg_gio_rw_pb_oe_offset 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 18
-#define reg_gio_rw_pc_dout_offset 48
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 18
-#define reg_gio_r_pc_din_offset 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 18
-#define reg_gio_rw_pc_oe_offset 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-#define reg_gio_rw_pd_dout___data___lsb 0
-#define reg_gio_rw_pd_dout___data___width 18
-#define reg_gio_rw_pd_dout_offset 64
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 18
-#define reg_gio_r_pd_din_offset 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-#define reg_gio_rw_pd_oe___oe___lsb 0
-#define reg_gio_rw_pd_oe___oe___width 18
-#define reg_gio_rw_pd_oe_offset 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-#define reg_gio_rw_pe_dout___data___lsb 0
-#define reg_gio_rw_pe_dout___data___width 18
-#define reg_gio_rw_pe_dout_offset 80
-
-/* Register r_pe_din, scope gio, type r */
-#define reg_gio_r_pe_din___data___lsb 0
-#define reg_gio_r_pe_din___data___width 18
-#define reg_gio_r_pe_din_offset 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-#define reg_gio_rw_pe_oe___oe___lsb 0
-#define reg_gio_rw_pe_oe___oe___width 18
-#define reg_gio_rw_pe_oe_offset 88
-
-
-/* Constants */
-#define regk_gio_anyedge 0x00000007
-#define regk_gio_hi 0x00000001
-#define regk_gio_lo 0x00000002
-#define regk_gio_negedge 0x00000006
-#define regk_gio_no 0x00000000
-#define regk_gio_off 0x00000000
-#define regk_gio_posedge 0x00000005
-#define regk_gio_rw_intr_cfg_default 0x00000000
-#define regk_gio_rw_intr_mask_default 0x00000000
-#define regk_gio_rw_pa_oe_default 0x00000000
-#define regk_gio_rw_pb_oe_default 0x00000000
-#define regk_gio_rw_pc_oe_default 0x00000000
-#define regk_gio_rw_pd_oe_default 0x00000000
-#define regk_gio_rw_pe_oe_default 0x00000000
-#define regk_gio_set 0x00000003
-#define regk_gio_yes 0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index 99968cfa446a..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,633 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
- * last modfied: Mon Apr 11 16:09:11 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_pa___pa0___lsb 0
-#define reg_pinmux_rw_pa___pa0___width 1
-#define reg_pinmux_rw_pa___pa0___bit 0
-#define reg_pinmux_rw_pa___pa1___lsb 1
-#define reg_pinmux_rw_pa___pa1___width 1
-#define reg_pinmux_rw_pa___pa1___bit 1
-#define reg_pinmux_rw_pa___pa2___lsb 2
-#define reg_pinmux_rw_pa___pa2___width 1
-#define reg_pinmux_rw_pa___pa2___bit 2
-#define reg_pinmux_rw_pa___pa3___lsb 3
-#define reg_pinmux_rw_pa___pa3___width 1
-#define reg_pinmux_rw_pa___pa3___bit 3
-#define reg_pinmux_rw_pa___pa4___lsb 4
-#define reg_pinmux_rw_pa___pa4___width 1
-#define reg_pinmux_rw_pa___pa4___bit 4
-#define reg_pinmux_rw_pa___pa5___lsb 5
-#define reg_pinmux_rw_pa___pa5___width 1
-#define reg_pinmux_rw_pa___pa5___bit 5
-#define reg_pinmux_rw_pa___pa6___lsb 6
-#define reg_pinmux_rw_pa___pa6___width 1
-#define reg_pinmux_rw_pa___pa6___bit 6
-#define reg_pinmux_rw_pa___pa7___lsb 7
-#define reg_pinmux_rw_pa___pa7___width 1
-#define reg_pinmux_rw_pa___pa7___bit 7
-#define reg_pinmux_rw_pa___csp2_n___lsb 8
-#define reg_pinmux_rw_pa___csp2_n___width 1
-#define reg_pinmux_rw_pa___csp2_n___bit 8
-#define reg_pinmux_rw_pa___csp3_n___lsb 9
-#define reg_pinmux_rw_pa___csp3_n___width 1
-#define reg_pinmux_rw_pa___csp3_n___bit 9
-#define reg_pinmux_rw_pa___csp5_n___lsb 10
-#define reg_pinmux_rw_pa___csp5_n___width 1
-#define reg_pinmux_rw_pa___csp5_n___bit 10
-#define reg_pinmux_rw_pa___csp6_n___lsb 11
-#define reg_pinmux_rw_pa___csp6_n___width 1
-#define reg_pinmux_rw_pa___csp6_n___bit 11
-#define reg_pinmux_rw_pa___hsh4___lsb 12
-#define reg_pinmux_rw_pa___hsh4___width 1
-#define reg_pinmux_rw_pa___hsh4___bit 12
-#define reg_pinmux_rw_pa___hsh5___lsb 13
-#define reg_pinmux_rw_pa___hsh5___width 1
-#define reg_pinmux_rw_pa___hsh5___bit 13
-#define reg_pinmux_rw_pa___hsh6___lsb 14
-#define reg_pinmux_rw_pa___hsh6___width 1
-#define reg_pinmux_rw_pa___hsh6___bit 14
-#define reg_pinmux_rw_pa___hsh7___lsb 15
-#define reg_pinmux_rw_pa___hsh7___width 1
-#define reg_pinmux_rw_pa___hsh7___bit 15
-#define reg_pinmux_rw_pa_offset 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___ser1___lsb 0
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 0
-#define reg_pinmux_rw_hwprot___ser2___lsb 1
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 1
-#define reg_pinmux_rw_hwprot___ser3___lsb 2
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 2
-#define reg_pinmux_rw_hwprot___sser0___lsb 3
-#define reg_pinmux_rw_hwprot___sser0___width 1
-#define reg_pinmux_rw_hwprot___sser0___bit 3
-#define reg_pinmux_rw_hwprot___sser1___lsb 4
-#define reg_pinmux_rw_hwprot___sser1___width 1
-#define reg_pinmux_rw_hwprot___sser1___bit 4
-#define reg_pinmux_rw_hwprot___ata0___lsb 5
-#define reg_pinmux_rw_hwprot___ata0___width 1
-#define reg_pinmux_rw_hwprot___ata0___bit 5
-#define reg_pinmux_rw_hwprot___ata1___lsb 6
-#define reg_pinmux_rw_hwprot___ata1___width 1
-#define reg_pinmux_rw_hwprot___ata1___bit 6
-#define reg_pinmux_rw_hwprot___ata2___lsb 7
-#define reg_pinmux_rw_hwprot___ata2___width 1
-#define reg_pinmux_rw_hwprot___ata2___bit 7
-#define reg_pinmux_rw_hwprot___ata3___lsb 8
-#define reg_pinmux_rw_hwprot___ata3___width 1
-#define reg_pinmux_rw_hwprot___ata3___bit 8
-#define reg_pinmux_rw_hwprot___ata___lsb 9
-#define reg_pinmux_rw_hwprot___ata___width 1
-#define reg_pinmux_rw_hwprot___ata___bit 9
-#define reg_pinmux_rw_hwprot___eth1___lsb 10
-#define reg_pinmux_rw_hwprot___eth1___width 1
-#define reg_pinmux_rw_hwprot___eth1___bit 10
-#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
-#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
-#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
-#define reg_pinmux_rw_hwprot___timer___lsb 12
-#define reg_pinmux_rw_hwprot___timer___width 1
-#define reg_pinmux_rw_hwprot___timer___bit 12
-#define reg_pinmux_rw_hwprot___p21___lsb 13
-#define reg_pinmux_rw_hwprot___p21___width 1
-#define reg_pinmux_rw_hwprot___p21___bit 13
-#define reg_pinmux_rw_hwprot_offset 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_gio___pb0___lsb 0
-#define reg_pinmux_rw_pb_gio___pb0___width 1
-#define reg_pinmux_rw_pb_gio___pb0___bit 0
-#define reg_pinmux_rw_pb_gio___pb1___lsb 1
-#define reg_pinmux_rw_pb_gio___pb1___width 1
-#define reg_pinmux_rw_pb_gio___pb1___bit 1
-#define reg_pinmux_rw_pb_gio___pb2___lsb 2
-#define reg_pinmux_rw_pb_gio___pb2___width 1
-#define reg_pinmux_rw_pb_gio___pb2___bit 2
-#define reg_pinmux_rw_pb_gio___pb3___lsb 3
-#define reg_pinmux_rw_pb_gio___pb3___width 1
-#define reg_pinmux_rw_pb_gio___pb3___bit 3
-#define reg_pinmux_rw_pb_gio___pb4___lsb 4
-#define reg_pinmux_rw_pb_gio___pb4___width 1
-#define reg_pinmux_rw_pb_gio___pb4___bit 4
-#define reg_pinmux_rw_pb_gio___pb5___lsb 5
-#define reg_pinmux_rw_pb_gio___pb5___width 1
-#define reg_pinmux_rw_pb_gio___pb5___bit 5
-#define reg_pinmux_rw_pb_gio___pb6___lsb 6
-#define reg_pinmux_rw_pb_gio___pb6___width 1
-#define reg_pinmux_rw_pb_gio___pb6___bit 6
-#define reg_pinmux_rw_pb_gio___pb7___lsb 7
-#define reg_pinmux_rw_pb_gio___pb7___width 1
-#define reg_pinmux_rw_pb_gio___pb7___bit 7
-#define reg_pinmux_rw_pb_gio___pb8___lsb 8
-#define reg_pinmux_rw_pb_gio___pb8___width 1
-#define reg_pinmux_rw_pb_gio___pb8___bit 8
-#define reg_pinmux_rw_pb_gio___pb9___lsb 9
-#define reg_pinmux_rw_pb_gio___pb9___width 1
-#define reg_pinmux_rw_pb_gio___pb9___bit 9
-#define reg_pinmux_rw_pb_gio___pb10___lsb 10
-#define reg_pinmux_rw_pb_gio___pb10___width 1
-#define reg_pinmux_rw_pb_gio___pb10___bit 10
-#define reg_pinmux_rw_pb_gio___pb11___lsb 11
-#define reg_pinmux_rw_pb_gio___pb11___width 1
-#define reg_pinmux_rw_pb_gio___pb11___bit 11
-#define reg_pinmux_rw_pb_gio___pb12___lsb 12
-#define reg_pinmux_rw_pb_gio___pb12___width 1
-#define reg_pinmux_rw_pb_gio___pb12___bit 12
-#define reg_pinmux_rw_pb_gio___pb13___lsb 13
-#define reg_pinmux_rw_pb_gio___pb13___width 1
-#define reg_pinmux_rw_pb_gio___pb13___bit 13
-#define reg_pinmux_rw_pb_gio___pb14___lsb 14
-#define reg_pinmux_rw_pb_gio___pb14___width 1
-#define reg_pinmux_rw_pb_gio___pb14___bit 14
-#define reg_pinmux_rw_pb_gio___pb15___lsb 15
-#define reg_pinmux_rw_pb_gio___pb15___width 1
-#define reg_pinmux_rw_pb_gio___pb15___bit 15
-#define reg_pinmux_rw_pb_gio___pb16___lsb 16
-#define reg_pinmux_rw_pb_gio___pb16___width 1
-#define reg_pinmux_rw_pb_gio___pb16___bit 16
-#define reg_pinmux_rw_pb_gio___pb17___lsb 17
-#define reg_pinmux_rw_pb_gio___pb17___width 1
-#define reg_pinmux_rw_pb_gio___pb17___bit 17
-#define reg_pinmux_rw_pb_gio_offset 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_iop___pb0___lsb 0
-#define reg_pinmux_rw_pb_iop___pb0___width 1
-#define reg_pinmux_rw_pb_iop___pb0___bit 0
-#define reg_pinmux_rw_pb_iop___pb1___lsb 1
-#define reg_pinmux_rw_pb_iop___pb1___width 1
-#define reg_pinmux_rw_pb_iop___pb1___bit 1
-#define reg_pinmux_rw_pb_iop___pb2___lsb 2
-#define reg_pinmux_rw_pb_iop___pb2___width 1
-#define reg_pinmux_rw_pb_iop___pb2___bit 2
-#define reg_pinmux_rw_pb_iop___pb3___lsb 3
-#define reg_pinmux_rw_pb_iop___pb3___width 1
-#define reg_pinmux_rw_pb_iop___pb3___bit 3
-#define reg_pinmux_rw_pb_iop___pb4___lsb 4
-#define reg_pinmux_rw_pb_iop___pb4___width 1
-#define reg_pinmux_rw_pb_iop___pb4___bit 4
-#define reg_pinmux_rw_pb_iop___pb5___lsb 5
-#define reg_pinmux_rw_pb_iop___pb5___width 1
-#define reg_pinmux_rw_pb_iop___pb5___bit 5
-#define reg_pinmux_rw_pb_iop___pb6___lsb 6
-#define reg_pinmux_rw_pb_iop___pb6___width 1
-#define reg_pinmux_rw_pb_iop___pb6___bit 6
-#define reg_pinmux_rw_pb_iop___pb7___lsb 7
-#define reg_pinmux_rw_pb_iop___pb7___width 1
-#define reg_pinmux_rw_pb_iop___pb7___bit 7
-#define reg_pinmux_rw_pb_iop___pb8___lsb 8
-#define reg_pinmux_rw_pb_iop___pb8___width 1
-#define reg_pinmux_rw_pb_iop___pb8___bit 8
-#define reg_pinmux_rw_pb_iop___pb9___lsb 9
-#define reg_pinmux_rw_pb_iop___pb9___width 1
-#define reg_pinmux_rw_pb_iop___pb9___bit 9
-#define reg_pinmux_rw_pb_iop___pb10___lsb 10
-#define reg_pinmux_rw_pb_iop___pb10___width 1
-#define reg_pinmux_rw_pb_iop___pb10___bit 10
-#define reg_pinmux_rw_pb_iop___pb11___lsb 11
-#define reg_pinmux_rw_pb_iop___pb11___width 1
-#define reg_pinmux_rw_pb_iop___pb11___bit 11
-#define reg_pinmux_rw_pb_iop___pb12___lsb 12
-#define reg_pinmux_rw_pb_iop___pb12___width 1
-#define reg_pinmux_rw_pb_iop___pb12___bit 12
-#define reg_pinmux_rw_pb_iop___pb13___lsb 13
-#define reg_pinmux_rw_pb_iop___pb13___width 1
-#define reg_pinmux_rw_pb_iop___pb13___bit 13
-#define reg_pinmux_rw_pb_iop___pb14___lsb 14
-#define reg_pinmux_rw_pb_iop___pb14___width 1
-#define reg_pinmux_rw_pb_iop___pb14___bit 14
-#define reg_pinmux_rw_pb_iop___pb15___lsb 15
-#define reg_pinmux_rw_pb_iop___pb15___width 1
-#define reg_pinmux_rw_pb_iop___pb15___bit 15
-#define reg_pinmux_rw_pb_iop___pb16___lsb 16
-#define reg_pinmux_rw_pb_iop___pb16___width 1
-#define reg_pinmux_rw_pb_iop___pb16___bit 16
-#define reg_pinmux_rw_pb_iop___pb17___lsb 17
-#define reg_pinmux_rw_pb_iop___pb17___width 1
-#define reg_pinmux_rw_pb_iop___pb17___bit 17
-#define reg_pinmux_rw_pb_iop_offset 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_gio___pc0___lsb 0
-#define reg_pinmux_rw_pc_gio___pc0___width 1
-#define reg_pinmux_rw_pc_gio___pc0___bit 0
-#define reg_pinmux_rw_pc_gio___pc1___lsb 1
-#define reg_pinmux_rw_pc_gio___pc1___width 1
-#define reg_pinmux_rw_pc_gio___pc1___bit 1
-#define reg_pinmux_rw_pc_gio___pc2___lsb 2
-#define reg_pinmux_rw_pc_gio___pc2___width 1
-#define reg_pinmux_rw_pc_gio___pc2___bit 2
-#define reg_pinmux_rw_pc_gio___pc3___lsb 3
-#define reg_pinmux_rw_pc_gio___pc3___width 1
-#define reg_pinmux_rw_pc_gio___pc3___bit 3
-#define reg_pinmux_rw_pc_gio___pc4___lsb 4
-#define reg_pinmux_rw_pc_gio___pc4___width 1
-#define reg_pinmux_rw_pc_gio___pc4___bit 4
-#define reg_pinmux_rw_pc_gio___pc5___lsb 5
-#define reg_pinmux_rw_pc_gio___pc5___width 1
-#define reg_pinmux_rw_pc_gio___pc5___bit 5
-#define reg_pinmux_rw_pc_gio___pc6___lsb 6
-#define reg_pinmux_rw_pc_gio___pc6___width 1
-#define reg_pinmux_rw_pc_gio___pc6___bit 6
-#define reg_pinmux_rw_pc_gio___pc7___lsb 7
-#define reg_pinmux_rw_pc_gio___pc7___width 1
-#define reg_pinmux_rw_pc_gio___pc7___bit 7
-#define reg_pinmux_rw_pc_gio___pc8___lsb 8
-#define reg_pinmux_rw_pc_gio___pc8___width 1
-#define reg_pinmux_rw_pc_gio___pc8___bit 8
-#define reg_pinmux_rw_pc_gio___pc9___lsb 9
-#define reg_pinmux_rw_pc_gio___pc9___width 1
-#define reg_pinmux_rw_pc_gio___pc9___bit 9
-#define reg_pinmux_rw_pc_gio___pc10___lsb 10
-#define reg_pinmux_rw_pc_gio___pc10___width 1
-#define reg_pinmux_rw_pc_gio___pc10___bit 10
-#define reg_pinmux_rw_pc_gio___pc11___lsb 11
-#define reg_pinmux_rw_pc_gio___pc11___width 1
-#define reg_pinmux_rw_pc_gio___pc11___bit 11
-#define reg_pinmux_rw_pc_gio___pc12___lsb 12
-#define reg_pinmux_rw_pc_gio___pc12___width 1
-#define reg_pinmux_rw_pc_gio___pc12___bit 12
-#define reg_pinmux_rw_pc_gio___pc13___lsb 13
-#define reg_pinmux_rw_pc_gio___pc13___width 1
-#define reg_pinmux_rw_pc_gio___pc13___bit 13
-#define reg_pinmux_rw_pc_gio___pc14___lsb 14
-#define reg_pinmux_rw_pc_gio___pc14___width 1
-#define reg_pinmux_rw_pc_gio___pc14___bit 14
-#define reg_pinmux_rw_pc_gio___pc15___lsb 15
-#define reg_pinmux_rw_pc_gio___pc15___width 1
-#define reg_pinmux_rw_pc_gio___pc15___bit 15
-#define reg_pinmux_rw_pc_gio___pc16___lsb 16
-#define reg_pinmux_rw_pc_gio___pc16___width 1
-#define reg_pinmux_rw_pc_gio___pc16___bit 16
-#define reg_pinmux_rw_pc_gio___pc17___lsb 17
-#define reg_pinmux_rw_pc_gio___pc17___width 1
-#define reg_pinmux_rw_pc_gio___pc17___bit 17
-#define reg_pinmux_rw_pc_gio_offset 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_iop___pc0___lsb 0
-#define reg_pinmux_rw_pc_iop___pc0___width 1
-#define reg_pinmux_rw_pc_iop___pc0___bit 0
-#define reg_pinmux_rw_pc_iop___pc1___lsb 1
-#define reg_pinmux_rw_pc_iop___pc1___width 1
-#define reg_pinmux_rw_pc_iop___pc1___bit 1
-#define reg_pinmux_rw_pc_iop___pc2___lsb 2
-#define reg_pinmux_rw_pc_iop___pc2___width 1
-#define reg_pinmux_rw_pc_iop___pc2___bit 2
-#define reg_pinmux_rw_pc_iop___pc3___lsb 3
-#define reg_pinmux_rw_pc_iop___pc3___width 1
-#define reg_pinmux_rw_pc_iop___pc3___bit 3
-#define reg_pinmux_rw_pc_iop___pc4___lsb 4
-#define reg_pinmux_rw_pc_iop___pc4___width 1
-#define reg_pinmux_rw_pc_iop___pc4___bit 4
-#define reg_pinmux_rw_pc_iop___pc5___lsb 5
-#define reg_pinmux_rw_pc_iop___pc5___width 1
-#define reg_pinmux_rw_pc_iop___pc5___bit 5
-#define reg_pinmux_rw_pc_iop___pc6___lsb 6
-#define reg_pinmux_rw_pc_iop___pc6___width 1
-#define reg_pinmux_rw_pc_iop___pc6___bit 6
-#define reg_pinmux_rw_pc_iop___pc7___lsb 7
-#define reg_pinmux_rw_pc_iop___pc7___width 1
-#define reg_pinmux_rw_pc_iop___pc7___bit 7
-#define reg_pinmux_rw_pc_iop___pc8___lsb 8
-#define reg_pinmux_rw_pc_iop___pc8___width 1
-#define reg_pinmux_rw_pc_iop___pc8___bit 8
-#define reg_pinmux_rw_pc_iop___pc9___lsb 9
-#define reg_pinmux_rw_pc_iop___pc9___width 1
-#define reg_pinmux_rw_pc_iop___pc9___bit 9
-#define reg_pinmux_rw_pc_iop___pc10___lsb 10
-#define reg_pinmux_rw_pc_iop___pc10___width 1
-#define reg_pinmux_rw_pc_iop___pc10___bit 10
-#define reg_pinmux_rw_pc_iop___pc11___lsb 11
-#define reg_pinmux_rw_pc_iop___pc11___width 1
-#define reg_pinmux_rw_pc_iop___pc11___bit 11
-#define reg_pinmux_rw_pc_iop___pc12___lsb 12
-#define reg_pinmux_rw_pc_iop___pc12___width 1
-#define reg_pinmux_rw_pc_iop___pc12___bit 12
-#define reg_pinmux_rw_pc_iop___pc13___lsb 13
-#define reg_pinmux_rw_pc_iop___pc13___width 1
-#define reg_pinmux_rw_pc_iop___pc13___bit 13
-#define reg_pinmux_rw_pc_iop___pc14___lsb 14
-#define reg_pinmux_rw_pc_iop___pc14___width 1
-#define reg_pinmux_rw_pc_iop___pc14___bit 14
-#define reg_pinmux_rw_pc_iop___pc15___lsb 15
-#define reg_pinmux_rw_pc_iop___pc15___width 1
-#define reg_pinmux_rw_pc_iop___pc15___bit 15
-#define reg_pinmux_rw_pc_iop___pc16___lsb 16
-#define reg_pinmux_rw_pc_iop___pc16___width 1
-#define reg_pinmux_rw_pc_iop___pc16___bit 16
-#define reg_pinmux_rw_pc_iop___pc17___lsb 17
-#define reg_pinmux_rw_pc_iop___pc17___width 1
-#define reg_pinmux_rw_pc_iop___pc17___bit 17
-#define reg_pinmux_rw_pc_iop_offset 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_gio___pd0___lsb 0
-#define reg_pinmux_rw_pd_gio___pd0___width 1
-#define reg_pinmux_rw_pd_gio___pd0___bit 0
-#define reg_pinmux_rw_pd_gio___pd1___lsb 1
-#define reg_pinmux_rw_pd_gio___pd1___width 1
-#define reg_pinmux_rw_pd_gio___pd1___bit 1
-#define reg_pinmux_rw_pd_gio___pd2___lsb 2
-#define reg_pinmux_rw_pd_gio___pd2___width 1
-#define reg_pinmux_rw_pd_gio___pd2___bit 2
-#define reg_pinmux_rw_pd_gio___pd3___lsb 3
-#define reg_pinmux_rw_pd_gio___pd3___width 1
-#define reg_pinmux_rw_pd_gio___pd3___bit 3
-#define reg_pinmux_rw_pd_gio___pd4___lsb 4
-#define reg_pinmux_rw_pd_gio___pd4___width 1
-#define reg_pinmux_rw_pd_gio___pd4___bit 4
-#define reg_pinmux_rw_pd_gio___pd5___lsb 5
-#define reg_pinmux_rw_pd_gio___pd5___width 1
-#define reg_pinmux_rw_pd_gio___pd5___bit 5
-#define reg_pinmux_rw_pd_gio___pd6___lsb 6
-#define reg_pinmux_rw_pd_gio___pd6___width 1
-#define reg_pinmux_rw_pd_gio___pd6___bit 6
-#define reg_pinmux_rw_pd_gio___pd7___lsb 7
-#define reg_pinmux_rw_pd_gio___pd7___width 1
-#define reg_pinmux_rw_pd_gio___pd7___bit 7
-#define reg_pinmux_rw_pd_gio___pd8___lsb 8
-#define reg_pinmux_rw_pd_gio___pd8___width 1
-#define reg_pinmux_rw_pd_gio___pd8___bit 8
-#define reg_pinmux_rw_pd_gio___pd9___lsb 9
-#define reg_pinmux_rw_pd_gio___pd9___width 1
-#define reg_pinmux_rw_pd_gio___pd9___bit 9
-#define reg_pinmux_rw_pd_gio___pd10___lsb 10
-#define reg_pinmux_rw_pd_gio___pd10___width 1
-#define reg_pinmux_rw_pd_gio___pd10___bit 10
-#define reg_pinmux_rw_pd_gio___pd11___lsb 11
-#define reg_pinmux_rw_pd_gio___pd11___width 1
-#define reg_pinmux_rw_pd_gio___pd11___bit 11
-#define reg_pinmux_rw_pd_gio___pd12___lsb 12
-#define reg_pinmux_rw_pd_gio___pd12___width 1
-#define reg_pinmux_rw_pd_gio___pd12___bit 12
-#define reg_pinmux_rw_pd_gio___pd13___lsb 13
-#define reg_pinmux_rw_pd_gio___pd13___width 1
-#define reg_pinmux_rw_pd_gio___pd13___bit 13
-#define reg_pinmux_rw_pd_gio___pd14___lsb 14
-#define reg_pinmux_rw_pd_gio___pd14___width 1
-#define reg_pinmux_rw_pd_gio___pd14___bit 14
-#define reg_pinmux_rw_pd_gio___pd15___lsb 15
-#define reg_pinmux_rw_pd_gio___pd15___width 1
-#define reg_pinmux_rw_pd_gio___pd15___bit 15
-#define reg_pinmux_rw_pd_gio___pd16___lsb 16
-#define reg_pinmux_rw_pd_gio___pd16___width 1
-#define reg_pinmux_rw_pd_gio___pd16___bit 16
-#define reg_pinmux_rw_pd_gio___pd17___lsb 17
-#define reg_pinmux_rw_pd_gio___pd17___width 1
-#define reg_pinmux_rw_pd_gio___pd17___bit 17
-#define reg_pinmux_rw_pd_gio_offset 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_iop___pd0___lsb 0
-#define reg_pinmux_rw_pd_iop___pd0___width 1
-#define reg_pinmux_rw_pd_iop___pd0___bit 0
-#define reg_pinmux_rw_pd_iop___pd1___lsb 1
-#define reg_pinmux_rw_pd_iop___pd1___width 1
-#define reg_pinmux_rw_pd_iop___pd1___bit 1
-#define reg_pinmux_rw_pd_iop___pd2___lsb 2
-#define reg_pinmux_rw_pd_iop___pd2___width 1
-#define reg_pinmux_rw_pd_iop___pd2___bit 2
-#define reg_pinmux_rw_pd_iop___pd3___lsb 3
-#define reg_pinmux_rw_pd_iop___pd3___width 1
-#define reg_pinmux_rw_pd_iop___pd3___bit 3
-#define reg_pinmux_rw_pd_iop___pd4___lsb 4
-#define reg_pinmux_rw_pd_iop___pd4___width 1
-#define reg_pinmux_rw_pd_iop___pd4___bit 4
-#define reg_pinmux_rw_pd_iop___pd5___lsb 5
-#define reg_pinmux_rw_pd_iop___pd5___width 1
-#define reg_pinmux_rw_pd_iop___pd5___bit 5
-#define reg_pinmux_rw_pd_iop___pd6___lsb 6
-#define reg_pinmux_rw_pd_iop___pd6___width 1
-#define reg_pinmux_rw_pd_iop___pd6___bit 6
-#define reg_pinmux_rw_pd_iop___pd7___lsb 7
-#define reg_pinmux_rw_pd_iop___pd7___width 1
-#define reg_pinmux_rw_pd_iop___pd7___bit 7
-#define reg_pinmux_rw_pd_iop___pd8___lsb 8
-#define reg_pinmux_rw_pd_iop___pd8___width 1
-#define reg_pinmux_rw_pd_iop___pd8___bit 8
-#define reg_pinmux_rw_pd_iop___pd9___lsb 9
-#define reg_pinmux_rw_pd_iop___pd9___width 1
-#define reg_pinmux_rw_pd_iop___pd9___bit 9
-#define reg_pinmux_rw_pd_iop___pd10___lsb 10
-#define reg_pinmux_rw_pd_iop___pd10___width 1
-#define reg_pinmux_rw_pd_iop___pd10___bit 10
-#define reg_pinmux_rw_pd_iop___pd11___lsb 11
-#define reg_pinmux_rw_pd_iop___pd11___width 1
-#define reg_pinmux_rw_pd_iop___pd11___bit 11
-#define reg_pinmux_rw_pd_iop___pd12___lsb 12
-#define reg_pinmux_rw_pd_iop___pd12___width 1
-#define reg_pinmux_rw_pd_iop___pd12___bit 12
-#define reg_pinmux_rw_pd_iop___pd13___lsb 13
-#define reg_pinmux_rw_pd_iop___pd13___width 1
-#define reg_pinmux_rw_pd_iop___pd13___bit 13
-#define reg_pinmux_rw_pd_iop___pd14___lsb 14
-#define reg_pinmux_rw_pd_iop___pd14___width 1
-#define reg_pinmux_rw_pd_iop___pd14___bit 14
-#define reg_pinmux_rw_pd_iop___pd15___lsb 15
-#define reg_pinmux_rw_pd_iop___pd15___width 1
-#define reg_pinmux_rw_pd_iop___pd15___bit 15
-#define reg_pinmux_rw_pd_iop___pd16___lsb 16
-#define reg_pinmux_rw_pd_iop___pd16___width 1
-#define reg_pinmux_rw_pd_iop___pd16___bit 16
-#define reg_pinmux_rw_pd_iop___pd17___lsb 17
-#define reg_pinmux_rw_pd_iop___pd17___width 1
-#define reg_pinmux_rw_pd_iop___pd17___bit 17
-#define reg_pinmux_rw_pd_iop_offset 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_gio___pe0___lsb 0
-#define reg_pinmux_rw_pe_gio___pe0___width 1
-#define reg_pinmux_rw_pe_gio___pe0___bit 0
-#define reg_pinmux_rw_pe_gio___pe1___lsb 1
-#define reg_pinmux_rw_pe_gio___pe1___width 1
-#define reg_pinmux_rw_pe_gio___pe1___bit 1
-#define reg_pinmux_rw_pe_gio___pe2___lsb 2
-#define reg_pinmux_rw_pe_gio___pe2___width 1
-#define reg_pinmux_rw_pe_gio___pe2___bit 2
-#define reg_pinmux_rw_pe_gio___pe3___lsb 3
-#define reg_pinmux_rw_pe_gio___pe3___width 1
-#define reg_pinmux_rw_pe_gio___pe3___bit 3
-#define reg_pinmux_rw_pe_gio___pe4___lsb 4
-#define reg_pinmux_rw_pe_gio___pe4___width 1
-#define reg_pinmux_rw_pe_gio___pe4___bit 4
-#define reg_pinmux_rw_pe_gio___pe5___lsb 5
-#define reg_pinmux_rw_pe_gio___pe5___width 1
-#define reg_pinmux_rw_pe_gio___pe5___bit 5
-#define reg_pinmux_rw_pe_gio___pe6___lsb 6
-#define reg_pinmux_rw_pe_gio___pe6___width 1
-#define reg_pinmux_rw_pe_gio___pe6___bit 6
-#define reg_pinmux_rw_pe_gio___pe7___lsb 7
-#define reg_pinmux_rw_pe_gio___pe7___width 1
-#define reg_pinmux_rw_pe_gio___pe7___bit 7
-#define reg_pinmux_rw_pe_gio___pe8___lsb 8
-#define reg_pinmux_rw_pe_gio___pe8___width 1
-#define reg_pinmux_rw_pe_gio___pe8___bit 8
-#define reg_pinmux_rw_pe_gio___pe9___lsb 9
-#define reg_pinmux_rw_pe_gio___pe9___width 1
-#define reg_pinmux_rw_pe_gio___pe9___bit 9
-#define reg_pinmux_rw_pe_gio___pe10___lsb 10
-#define reg_pinmux_rw_pe_gio___pe10___width 1
-#define reg_pinmux_rw_pe_gio___pe10___bit 10
-#define reg_pinmux_rw_pe_gio___pe11___lsb 11
-#define reg_pinmux_rw_pe_gio___pe11___width 1
-#define reg_pinmux_rw_pe_gio___pe11___bit 11
-#define reg_pinmux_rw_pe_gio___pe12___lsb 12
-#define reg_pinmux_rw_pe_gio___pe12___width 1
-#define reg_pinmux_rw_pe_gio___pe12___bit 12
-#define reg_pinmux_rw_pe_gio___pe13___lsb 13
-#define reg_pinmux_rw_pe_gio___pe13___width 1
-#define reg_pinmux_rw_pe_gio___pe13___bit 13
-#define reg_pinmux_rw_pe_gio___pe14___lsb 14
-#define reg_pinmux_rw_pe_gio___pe14___width 1
-#define reg_pinmux_rw_pe_gio___pe14___bit 14
-#define reg_pinmux_rw_pe_gio___pe15___lsb 15
-#define reg_pinmux_rw_pe_gio___pe15___width 1
-#define reg_pinmux_rw_pe_gio___pe15___bit 15
-#define reg_pinmux_rw_pe_gio___pe16___lsb 16
-#define reg_pinmux_rw_pe_gio___pe16___width 1
-#define reg_pinmux_rw_pe_gio___pe16___bit 16
-#define reg_pinmux_rw_pe_gio___pe17___lsb 17
-#define reg_pinmux_rw_pe_gio___pe17___width 1
-#define reg_pinmux_rw_pe_gio___pe17___bit 17
-#define reg_pinmux_rw_pe_gio_offset 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_iop___pe0___lsb 0
-#define reg_pinmux_rw_pe_iop___pe0___width 1
-#define reg_pinmux_rw_pe_iop___pe0___bit 0
-#define reg_pinmux_rw_pe_iop___pe1___lsb 1
-#define reg_pinmux_rw_pe_iop___pe1___width 1
-#define reg_pinmux_rw_pe_iop___pe1___bit 1
-#define reg_pinmux_rw_pe_iop___pe2___lsb 2
-#define reg_pinmux_rw_pe_iop___pe2___width 1
-#define reg_pinmux_rw_pe_iop___pe2___bit 2
-#define reg_pinmux_rw_pe_iop___pe3___lsb 3
-#define reg_pinmux_rw_pe_iop___pe3___width 1
-#define reg_pinmux_rw_pe_iop___pe3___bit 3
-#define reg_pinmux_rw_pe_iop___pe4___lsb 4
-#define reg_pinmux_rw_pe_iop___pe4___width 1
-#define reg_pinmux_rw_pe_iop___pe4___bit 4
-#define reg_pinmux_rw_pe_iop___pe5___lsb 5
-#define reg_pinmux_rw_pe_iop___pe5___width 1
-#define reg_pinmux_rw_pe_iop___pe5___bit 5
-#define reg_pinmux_rw_pe_iop___pe6___lsb 6
-#define reg_pinmux_rw_pe_iop___pe6___width 1
-#define reg_pinmux_rw_pe_iop___pe6___bit 6
-#define reg_pinmux_rw_pe_iop___pe7___lsb 7
-#define reg_pinmux_rw_pe_iop___pe7___width 1
-#define reg_pinmux_rw_pe_iop___pe7___bit 7
-#define reg_pinmux_rw_pe_iop___pe8___lsb 8
-#define reg_pinmux_rw_pe_iop___pe8___width 1
-#define reg_pinmux_rw_pe_iop___pe8___bit 8
-#define reg_pinmux_rw_pe_iop___pe9___lsb 9
-#define reg_pinmux_rw_pe_iop___pe9___width 1
-#define reg_pinmux_rw_pe_iop___pe9___bit 9
-#define reg_pinmux_rw_pe_iop___pe10___lsb 10
-#define reg_pinmux_rw_pe_iop___pe10___width 1
-#define reg_pinmux_rw_pe_iop___pe10___bit 10
-#define reg_pinmux_rw_pe_iop___pe11___lsb 11
-#define reg_pinmux_rw_pe_iop___pe11___width 1
-#define reg_pinmux_rw_pe_iop___pe11___bit 11
-#define reg_pinmux_rw_pe_iop___pe12___lsb 12
-#define reg_pinmux_rw_pe_iop___pe12___width 1
-#define reg_pinmux_rw_pe_iop___pe12___bit 12
-#define reg_pinmux_rw_pe_iop___pe13___lsb 13
-#define reg_pinmux_rw_pe_iop___pe13___width 1
-#define reg_pinmux_rw_pe_iop___pe13___bit 13
-#define reg_pinmux_rw_pe_iop___pe14___lsb 14
-#define reg_pinmux_rw_pe_iop___pe14___width 1
-#define reg_pinmux_rw_pe_iop___pe14___bit 14
-#define reg_pinmux_rw_pe_iop___pe15___lsb 15
-#define reg_pinmux_rw_pe_iop___pe15___width 1
-#define reg_pinmux_rw_pe_iop___pe15___bit 15
-#define reg_pinmux_rw_pe_iop___pe16___lsb 16
-#define reg_pinmux_rw_pe_iop___pe16___width 1
-#define reg_pinmux_rw_pe_iop___pe16___bit 16
-#define reg_pinmux_rw_pe_iop___pe17___lsb 17
-#define reg_pinmux_rw_pe_iop___pe17___width 1
-#define reg_pinmux_rw_pe_iop___pe17___bit 17
-#define reg_pinmux_rw_pe_iop_offset 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
-#define reg_pinmux_rw_usb_phy___en_usb0___width 1
-#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
-#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
-#define reg_pinmux_rw_usb_phy___en_usb1___width 1
-#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
-#define reg_pinmux_rw_usb_phy_offset 40
-
-
-/* Constants */
-#define regk_pinmux_no 0x00000000
-#define regk_pinmux_rw_hwprot_default 0x00000000
-#define regk_pinmux_rw_pa_default 0x00000000
-#define regk_pinmux_rw_pb_gio_default 0x00000000
-#define regk_pinmux_rw_pb_iop_default 0x00000000
-#define regk_pinmux_rw_pc_gio_default 0x00000000
-#define regk_pinmux_rw_pc_iop_default 0x00000000
-#define regk_pinmux_rw_pd_gio_default 0x00000000
-#define regk_pinmux_rw_pd_iop_default 0x00000000
-#define regk_pinmux_rw_pe_gio_default 0x00000000
-#define regk_pinmux_rw_pe_iop_default 0x00000000
-#define regk_pinmux_rw_usb_phy_default 0x00000000
-#define regk_pinmux_yes 0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index 412b8748e952..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/fakereg.rmap
- * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
- * last modified: Wed Feb 11 20:53:25 2004
- * file: ../../rtl/global.rmap
- * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
- * last modified: Mon Aug 18 17:08:23 2003
- * file: ../../mod/modreg.rmap
- * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
- * last modified: Fri Feb 20 16:40:04 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_artpec_mod 0xb7044000
-#define regi_ata 0xb0032000
-#define regi_ata_mod 0xb7006000
-#define regi_barber 0xb701a000
-#define regi_bif_core 0xb0014000
-#define regi_bif_dma 0xb0016000
-#define regi_bif_slave 0xb0018000
-#define regi_bif_slave_ext 0xac000000
-#define regi_bus_master 0xb703c000
-#define regi_config 0xb003c000
-#define regi_dma0 0xb0000000
-#define regi_dma1 0xb0002000
-#define regi_dma2 0xb0004000
-#define regi_dma3 0xb0006000
-#define regi_dma4 0xb0008000
-#define regi_dma5 0xb000a000
-#define regi_dma6 0xb000c000
-#define regi_dma7 0xb000e000
-#define regi_dma8 0xb0010000
-#define regi_dma9 0xb0012000
-#define regi_eth0 0xb0034000
-#define regi_eth1 0xb0036000
-#define regi_eth_mod 0xb7004000
-#define regi_eth_mod1 0xb701c000
-#define regi_eth_strmod 0xb7008000
-#define regi_eth_strmod1 0xb7032000
-#define regi_ext_dma 0xb703a000
-#define regi_ext_mem 0xb7046000
-#define regi_gen_io 0xb7016000
-#define regi_gio 0xb001a000
-#define regi_hook 0xb7000000
-#define regi_iop 0xb0020000
-#define regi_irq 0xb001c000
-#define regi_irq_nmi 0xb701e000
-#define regi_marb 0xb003e000
-#define regi_marb_bp0 0xb003e240
-#define regi_marb_bp1 0xb003e280
-#define regi_marb_bp2 0xb003e2c0
-#define regi_marb_bp3 0xb003e300
-#define regi_nand_mod 0xb7014000
-#define regi_p21 0xb002e000
-#define regi_p21_mod 0xb7042000
-#define regi_pci_mod 0xb7010000
-#define regi_pin_test 0xb7018000
-#define regi_pinmux 0xb0038000
-#define regi_sdram_chk 0xb703e000
-#define regi_sdram_mod 0xb7012000
-#define regi_ser0 0xb0026000
-#define regi_ser1 0xb0028000
-#define regi_ser2 0xb002a000
-#define regi_ser3 0xb002c000
-#define regi_ser_mod0 0xb7020000
-#define regi_ser_mod1 0xb7022000
-#define regi_ser_mod2 0xb7024000
-#define regi_ser_mod3 0xb7026000
-#define regi_smif_stat 0xb700e000
-#define regi_sser0 0xb0022000
-#define regi_sser1 0xb0024000
-#define regi_sser_mod0 0xb700a000
-#define regi_sser_mod1 0xb700c000
-#define regi_strcop 0xb0030000
-#define regi_strmux 0xb003a000
-#define regi_strmux_tst 0xb7040000
-#define regi_tap 0xb7002000
-#define regi_timer 0xb001e000
-#define regi_timer_mod 0xb7034000
-#define regi_trace 0xb0040000
-#define regi_usb0 0xb7028000
-#define regi_usb1 0xb702a000
-#define regi_usb2 0xb702c000
-#define regi_usb3 0xb702e000
-#define regi_usb_dev 0xb7030000
-#define regi_utmi_mod0 0xb7036000
-#define regi_utmi_mod1 0xb7038000
-#endif /* __reg_map_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index 3eb17cfbdc75..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- * last modfied: Mon Apr 11 16:09:53 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext 0x00000001
-#define regk_timer_f100 0x00000007
-#define regk_timer_f29_493 0x00000004
-#define regk_timer_f32 0x00000005
-#define regk_timer_f32_768 0x00000006
-#define regk_timer_hold 0x00000001
-#define regk_timer_ld 0x00000000
-#define regk_timer_no 0x00000000
-#define regk_timer_off 0x00000000
-#define regk_timer_run 0x00000002
-#define regk_timer_rw_cnt_cfg_default 0x00000000
-#define regk_timer_rw_intr_mask_default 0x00000000
-#define regk_timer_rw_out_default 0x00000000
-#define regk_timer_rw_test_default 0x00000000
-#define regk_timer_rw_tmr0_ctrl_default 0x00000000
-#define regk_timer_rw_tmr1_ctrl_default 0x00000000
-#define regk_timer_rw_trig_cfg_default 0x00000000
-#define regk_timer_start 0x00000001
-#define regk_timer_stop 0x00000000
-#define regk_timer_time 0x00000001
-#define regk_timer_tmr0 0x00000002
-#define regk_timer_tmr1 0x00000003
-#define regk_timer_yes 0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h
deleted file mode 100644
index a9ffb7edaf91..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_h
-#define __bif_core_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_core */
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp1_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
-#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp2_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
-#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 2;
- unsigned int gated_csp0 : 2;
- unsigned int gated_csp1 : 2;
- unsigned int gated_csp2 : 2;
- unsigned int gated_csp3 : 2;
-} reg_bif_core_rw_grp3_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
-#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 4;
- unsigned int gated_csp4 : 2;
- unsigned int gated_csp5 : 2;
- unsigned int gated_csp6 : 2;
-} reg_bif_core_rw_grp4_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
-#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int grp_sel : 5;
- unsigned int dummy1 : 12;
-} reg_bif_core_rw_sdram_cfg_grp0;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int dummy1 : 17;
-} reg_bif_core_rw_sdram_cfg_grp1;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-typedef struct {
- unsigned int cl : 3;
- unsigned int rcd : 3;
- unsigned int rp : 3;
- unsigned int rc : 2;
- unsigned int dpl : 2;
- unsigned int pde : 1;
- unsigned int ref : 2;
- unsigned int cpd : 1;
- unsigned int sdcke : 1;
- unsigned int sdclk : 1;
- unsigned int dummy1 : 13;
-} reg_bif_core_rw_sdram_timing;
-#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
-#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-typedef struct {
- unsigned int cmd : 3;
- unsigned int mrs_data : 15;
- unsigned int dummy1 : 14;
-} reg_bif_core_rw_sdram_cmd;
-#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
-#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_rs_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_r_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
-
-
-/* Constants */
-enum {
- regk_bif_core_bank2 = 0x00000000,
- regk_bif_core_bank4 = 0x00000001,
- regk_bif_core_bit10 = 0x0000000a,
- regk_bif_core_bit11 = 0x0000000b,
- regk_bif_core_bit12 = 0x0000000c,
- regk_bif_core_bit13 = 0x0000000d,
- regk_bif_core_bit14 = 0x0000000e,
- regk_bif_core_bit15 = 0x0000000f,
- regk_bif_core_bit16 = 0x00000010,
- regk_bif_core_bit17 = 0x00000011,
- regk_bif_core_bit18 = 0x00000012,
- regk_bif_core_bit19 = 0x00000013,
- regk_bif_core_bit20 = 0x00000014,
- regk_bif_core_bit21 = 0x00000015,
- regk_bif_core_bit22 = 0x00000016,
- regk_bif_core_bit23 = 0x00000017,
- regk_bif_core_bit24 = 0x00000018,
- regk_bif_core_bit25 = 0x00000019,
- regk_bif_core_bit26 = 0x0000001a,
- regk_bif_core_bit27 = 0x0000001b,
- regk_bif_core_bit28 = 0x0000001c,
- regk_bif_core_bit29 = 0x0000001d,
- regk_bif_core_bit9 = 0x00000009,
- regk_bif_core_bw16 = 0x00000001,
- regk_bif_core_bw32 = 0x00000000,
- regk_bif_core_bwe = 0x00000000,
- regk_bif_core_cwe = 0x00000001,
- regk_bif_core_e15us = 0x00000001,
- regk_bif_core_e7800ns = 0x00000002,
- regk_bif_core_grp0 = 0x00000000,
- regk_bif_core_grp1 = 0x00000001,
- regk_bif_core_mrs = 0x00000003,
- regk_bif_core_no = 0x00000000,
- regk_bif_core_none = 0x00000000,
- regk_bif_core_nop = 0x00000000,
- regk_bif_core_off = 0x00000000,
- regk_bif_core_pre = 0x00000002,
- regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rd = 0x00000002,
- regk_bif_core_ref = 0x00000001,
- regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
- regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
- regk_bif_core_slf = 0x00000004,
- regk_bif_core_wr = 0x00000001,
- regk_bif_core_yes = 0x00000001
-};
-#endif /* __bif_core_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h
deleted file mode 100644
index d1fa172f58f4..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_dma_defs_h
-#define __bif_dma_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_dma_regs.r
- * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
- * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_dma */
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch0_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
-#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch0_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
-#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch0_start;
-#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
-#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch0_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
-#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch0_stat;
-#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch1_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
-#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch1_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
-#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch1_start;
-#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
-#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch1_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
-#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch1_stat;
-#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch2_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
-#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch2_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
-#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch2_start;
-#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
-#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch2_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
-#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch2_stat;
-#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch3_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
-#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch3_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
-#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch3_start;
-#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
-#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch3_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
-#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch3_stat;
-#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_intr_mask;
-#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
-#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_ack_intr;
-#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
-#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
-
-/* Register r_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_intr;
-#define REG_RD_ADDR_bif_dma_r_intr 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_masked_intr;
-#define REG_RD_ADDR_bif_dma_r_masked_intr 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin0_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
-#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin1_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
-#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin2_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
-#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin3_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
-#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin4_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
-#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin5_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
-#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin6_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
-#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin7_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
-#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int pin0 : 1;
- unsigned int pin1 : 1;
- unsigned int pin2 : 1;
- unsigned int pin3 : 1;
- unsigned int pin4 : 1;
- unsigned int pin5 : 1;
- unsigned int pin6 : 1;
- unsigned int pin7 : 1;
- unsigned int dummy1 : 24;
-} reg_bif_dma_r_pin_stat;
-#define REG_RD_ADDR_bif_dma_r_pin_stat 192
-
-
-/* Constants */
-enum {
- regk_bif_dma_as_master = 0x00000001,
- regk_bif_dma_as_slave = 0x00000001,
- regk_bif_dma_burst1 = 0x00000000,
- regk_bif_dma_burst8 = 0x00000001,
- regk_bif_dma_bw16 = 0x00000001,
- regk_bif_dma_bw32 = 0x00000002,
- regk_bif_dma_bw8 = 0x00000000,
- regk_bif_dma_dack = 0x00000006,
- regk_bif_dma_dack_inv = 0x00000007,
- regk_bif_dma_force = 0x00000001,
- regk_bif_dma_hi = 0x00000003,
- regk_bif_dma_inv = 0x00000003,
- regk_bif_dma_lo = 0x00000002,
- regk_bif_dma_master = 0x00000001,
- regk_bif_dma_no = 0x00000000,
- regk_bif_dma_norm = 0x00000002,
- regk_bif_dma_off = 0x00000000,
- regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch0_start_default = 0x00000000,
- regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch1_start_default = 0x00000000,
- regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch2_start_default = 0x00000000,
- regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch3_start_default = 0x00000000,
- regk_bif_dma_rw_intr_mask_default = 0x00000000,
- regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
- regk_bif_dma_slave = 0x00000002,
- regk_bif_dma_sreq = 0x00000006,
- regk_bif_dma_sreq_inv = 0x00000007,
- regk_bif_dma_tc = 0x00000004,
- regk_bif_dma_tc_inv = 0x00000005,
- regk_bif_dma_yes = 0x00000001
-};
-#endif /* __bif_dma_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h
deleted file mode 100644
index a8d7cc528546..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_slave_defs_h
-#define __bif_slave_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_slave_regs.r
- * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- * last modfied: Mon Apr 11 16:06:34 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
- * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_slave */
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int slave_id : 3;
- unsigned int use_slave_id : 1;
- unsigned int boot_rdy : 1;
- unsigned int loopback : 1;
- unsigned int dis : 1;
- unsigned int dummy1 : 25;
-} reg_bif_slave_rw_slave_cfg;
-#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
-#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-typedef struct {
- unsigned int ch0_mode : 1;
- unsigned int ch1_mode : 1;
- unsigned int ch2_mode : 1;
- unsigned int ch3_mode : 1;
- unsigned int dummy1 : 28;
-} reg_bif_slave_r_slave_mode;
-#define REG_RD_ADDR_bif_slave_r_slave_mode 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch0_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
-#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch1_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
-#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch2_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
-#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch3_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
-#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int brin_mode : 1;
- unsigned int brout_mode : 3;
- unsigned int bg_mode : 3;
- unsigned int release : 2;
- unsigned int acquire : 1;
- unsigned int settle_time : 2;
- unsigned int dram_ctrl : 1;
- unsigned int dummy1 : 19;
-} reg_bif_slave_rw_arb_cfg;
-#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
-#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-typedef struct {
- unsigned int init_mode : 1;
- unsigned int mode : 1;
- unsigned int brin : 1;
- unsigned int brout : 1;
- unsigned int bg : 1;
- unsigned int dummy1 : 27;
-} reg_bif_slave_r_arb_stat;
-#define REG_RD_ADDR_bif_slave_r_arb_stat 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_intr_mask;
-#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
-#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_ack_intr;
-#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
-#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
-
-/* Register r_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_intr;
-#define REG_RD_ADDR_bif_slave_r_intr 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_masked_intr;
-#define REG_RD_ADDR_bif_slave_r_masked_intr 76
-
-
-/* Constants */
-enum {
- regk_bif_slave_active_hi = 0x00000003,
- regk_bif_slave_active_lo = 0x00000002,
- regk_bif_slave_addr = 0x00000000,
- regk_bif_slave_always = 0x00000001,
- regk_bif_slave_at_idle = 0x00000002,
- regk_bif_slave_burst_end = 0x00000003,
- regk_bif_slave_dma = 0x00000001,
- regk_bif_slave_hi = 0x00000003,
- regk_bif_slave_inv = 0x00000001,
- regk_bif_slave_lo = 0x00000002,
- regk_bif_slave_local = 0x00000001,
- regk_bif_slave_master = 0x00000000,
- regk_bif_slave_mode_reg = 0x00000001,
- regk_bif_slave_no = 0x00000000,
- regk_bif_slave_norm = 0x00000000,
- regk_bif_slave_on_access = 0x00000000,
- regk_bif_slave_rw_arb_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
- regk_bif_slave_rw_intr_mask_default = 0x00000000,
- regk_bif_slave_rw_slave_cfg_default = 0x00000000,
- regk_bif_slave_shared = 0x00000000,
- regk_bif_slave_slave = 0x00000001,
- regk_bif_slave_t0ns = 0x00000003,
- regk_bif_slave_t10ns = 0x00000002,
- regk_bif_slave_t20ns = 0x00000003,
- regk_bif_slave_t30ns = 0x00000002,
- regk_bif_slave_t40ns = 0x00000001,
- regk_bif_slave_t50ns = 0x00000000,
- regk_bif_slave_yes = 0x00000001,
- regk_bif_slave_z = 0x00000004
-};
-#endif /* __bif_slave_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h
deleted file mode 100644
index cc8b20d17237..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_h
-#define __config_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
- * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope config */
-
-/* Register r_bootsel, scope config, type r */
-typedef struct {
- unsigned int boot_mode : 3;
- unsigned int full_duplex : 1;
- unsigned int user : 1;
- unsigned int pll : 1;
- unsigned int flash_bw : 1;
- unsigned int dummy1 : 25;
-} reg_config_r_bootsel;
-#define REG_RD_ADDR_config_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-typedef struct {
- unsigned int pll : 1;
- unsigned int cpu : 1;
- unsigned int iop : 1;
- unsigned int dma01_eth0 : 1;
- unsigned int dma23 : 1;
- unsigned int dma45 : 1;
- unsigned int dma67 : 1;
- unsigned int dma89_strcop : 1;
- unsigned int bif : 1;
- unsigned int fix_io : 1;
- unsigned int dummy1 : 22;
-} reg_config_rw_clk_ctrl;
-#define REG_RD_ADDR_config_rw_clk_ctrl 4
-#define REG_WR_ADDR_config_rw_clk_ctrl 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-typedef struct {
- unsigned int usb_susp : 1;
- unsigned int phyrst_n : 1;
- unsigned int dummy1 : 30;
-} reg_config_rw_pad_ctrl;
-#define REG_RD_ADDR_config_rw_pad_ctrl 8
-#define REG_WR_ADDR_config_rw_pad_ctrl 8
-
-
-/* Constants */
-enum {
- regk_config_bw16 = 0x00000000,
- regk_config_bw32 = 0x00000001,
- regk_config_master = 0x00000005,
- regk_config_nand = 0x00000003,
- regk_config_net_rx = 0x00000001,
- regk_config_net_tx_rx = 0x00000002,
- regk_config_no = 0x00000000,
- regk_config_none = 0x00000007,
- regk_config_nor = 0x00000000,
- regk_config_rw_clk_ctrl_default = 0x00000002,
- regk_config_rw_pad_ctrl_default = 0x00000000,
- regk_config_ser = 0x00000004,
- regk_config_slave = 0x00000006,
- regk_config_yes = 0x00000001
-};
-#endif /* __config_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h
deleted file mode 100644
index da0b1103b66d..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/gio/rtl/gio_regs.r
- * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- * last modfied: Mon Apr 11 16:07:47 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
- * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 0
-#define REG_WR_ADDR_gio_rw_pa_dout 0
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
- unsigned int pa0 : 3;
- unsigned int pa1 : 3;
- unsigned int pa2 : 3;
- unsigned int pa3 : 3;
- unsigned int pa4 : 3;
- unsigned int pa5 : 3;
- unsigned int pa6 : 3;
- unsigned int pa7 : 3;
- unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 12
-#define REG_WR_ADDR_gio_rw_intr_cfg 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 16
-#define REG_WR_ADDR_gio_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 20
-#define REG_WR_ADDR_gio_rw_ack_intr 20
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 24
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 32
-#define REG_WR_ADDR_gio_rw_pb_dout 32
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 40
-#define REG_WR_ADDR_gio_rw_pb_oe 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 48
-#define REG_WR_ADDR_gio_rw_pc_dout 48
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 56
-#define REG_WR_ADDR_gio_rw_pc_oe 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pd_dout;
-#define REG_RD_ADDR_gio_rw_pd_dout 64
-#define REG_WR_ADDR_gio_rw_pd_dout 64
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pd_oe;
-#define REG_RD_ADDR_gio_rw_pd_oe 72
-#define REG_WR_ADDR_gio_rw_pd_oe 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pe_dout;
-#define REG_RD_ADDR_gio_rw_pe_dout 80
-#define REG_WR_ADDR_gio_rw_pe_dout 80
-
-/* Register r_pe_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pe_din;
-#define REG_RD_ADDR_gio_r_pe_din 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pe_oe;
-#define REG_RD_ADDR_gio_rw_pe_oe 88
-#define REG_WR_ADDR_gio_rw_pe_oe 88
-
-
-/* Constants */
-enum {
- regk_gio_anyedge = 0x00000007,
- regk_gio_hi = 0x00000001,
- regk_gio_lo = 0x00000002,
- regk_gio_negedge = 0x00000006,
- regk_gio_no = 0x00000000,
- regk_gio_off = 0x00000000,
- regk_gio_posedge = 0x00000005,
- regk_gio_rw_intr_cfg_default = 0x00000000,
- regk_gio_rw_intr_mask_default = 0x00000000,
- regk_gio_rw_pa_oe_default = 0x00000000,
- regk_gio_rw_pb_oe_default = 0x00000000,
- regk_gio_rw_pc_oe_default = 0x00000000,
- regk_gio_rw_pd_oe_default = 0x00000000,
- regk_gio_rw_pe_oe_default = 0x00000000,
- regk_gio_set = 0x00000003,
- regk_gio_yes = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h
deleted file mode 100644
index ea752a2d8ee2..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define MEMARB_INTR_VECT 0x31
-#define GEN_IO_INTR_VECT 0x32
-#define GIO_INTR_VECT GEN_IO_INTR_VECT
-#define IOP0_INTR_VECT 0x33
-#define IOP1_INTR_VECT 0x34
-#define IOP2_INTR_VECT 0x35
-#define IOP3_INTR_VECT 0x36
-#define DMA0_INTR_VECT 0x37
-#define DMA1_INTR_VECT 0x38
-#define DMA2_INTR_VECT 0x39
-#define DMA3_INTR_VECT 0x3a
-#define DMA4_INTR_VECT 0x3b
-#define DMA5_INTR_VECT 0x3c
-#define DMA6_INTR_VECT 0x3d
-#define DMA7_INTR_VECT 0x3e
-#define DMA8_INTR_VECT 0x3f
-#define DMA9_INTR_VECT 0x40
-#define ATA_INTR_VECT 0x41
-#define SSER0_INTR_VECT 0x42
-#define SSER1_INTR_VECT 0x43
-#define SER0_INTR_VECT 0x44
-#define SER1_INTR_VECT 0x45
-#define SER2_INTR_VECT 0x46
-#define SER3_INTR_VECT 0x47
-#define P21_INTR_VECT 0x48
-#define ETH0_INTR_VECT 0x49
-#define ETH1_INTR_VECT 0x4a
-#define TIMER_INTR_VECT 0x4b
-#define TIMER0_INTR_VECT TIMER_INTR_VECT
-#define BIF_ARB_INTR_VECT 0x4c
-#define BIF_DMA_INTR_VECT 0x4d
-#define EXT_INTR_VECT 0x4e
-#define IPI_INTR_VECT 0x4f
-#define NBR_INTR_VECT 0x50
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h
deleted file mode 100644
index 11ebd66585cd..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __intr_vect_defs_h
-#define __intr_vect_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
- * last modfied: Mon Apr 11 16:08:03 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope intr_vect */
-
-#define STRIDE_intr_vect_rw_mask 0
-/* Register rw_mask, scope intr_vect, type rw */
-typedef struct {
- unsigned int memarb : 1;
- unsigned int gen_io : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int iop2 : 1;
- unsigned int iop3 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int ata : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int p21 : 1;
- unsigned int eth0 : 1;
- unsigned int eth1 : 1;
- unsigned int timer0 : 1;
- unsigned int bif_arb : 1;
- unsigned int bif_dma : 1;
- unsigned int ext : 1;
- unsigned int dummy1 : 2;
-} reg_intr_vect_rw_mask;
-#define REG_RD_ADDR_intr_vect_rw_mask 0
-#define REG_WR_ADDR_intr_vect_rw_mask 0
-
-#define STRIDE_intr_vect_r_vect 0
-/* Register r_vect, scope intr_vect, type r */
-typedef struct {
- unsigned int memarb : 1;
- unsigned int gen_io : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int iop2 : 1;
- unsigned int iop3 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int ata : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int p21 : 1;
- unsigned int eth0 : 1;
- unsigned int eth1 : 1;
- unsigned int timer : 1;
- unsigned int bif_arb : 1;
- unsigned int bif_dma : 1;
- unsigned int ext : 1;
- unsigned int dummy1 : 2;
-} reg_intr_vect_r_vect;
-#define REG_RD_ADDR_intr_vect_r_vect 4
-
-#define STRIDE_intr_vect_r_masked_vect 0
-/* Register r_masked_vect, scope intr_vect, type r */
-typedef struct {
- unsigned int memarb : 1;
- unsigned int gen_io : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int iop2 : 1;
- unsigned int iop3 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int ata : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int p21 : 1;
- unsigned int eth0 : 1;
- unsigned int eth1 : 1;
- unsigned int timer : 1;
- unsigned int bif_arb : 1;
- unsigned int bif_dma : 1;
- unsigned int ext : 1;
- unsigned int dummy1 : 2;
-} reg_intr_vect_r_masked_vect;
-#define REG_RD_ADDR_intr_vect_r_masked_vect 8
-
-/* Register r_nmi, scope intr_vect, type r */
-typedef struct {
- unsigned int ext : 1;
- unsigned int watchdog : 1;
- unsigned int dummy1 : 30;
-} reg_intr_vect_r_nmi;
-#define REG_RD_ADDR_intr_vect_r_nmi 12
-
-/* Register r_guru, scope intr_vect, type r */
-typedef struct {
- unsigned int jtag : 1;
- unsigned int dummy1 : 31;
-} reg_intr_vect_r_guru;
-#define REG_RD_ADDR_intr_vect_r_guru 16
-
-/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct
-{
- unsigned int vector;
-} reg_intr_vect_rw_ipi;
-#define REG_RD_ADDR_intr_vect_rw_ipi 20
-#define REG_WR_ADDR_intr_vect_rw_ipi 20
-
-/* Constants */
-enum {
- regk_intr_vect_off = 0x00000000,
- regk_intr_vect_on = 0x00000001,
- regk_intr_vect_rw_mask_default = 0x00000000
-};
-#endif /* __intr_vect_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h
deleted file mode 100644
index fb7e20d77591..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Fri Nov 7 15:36:04 2003
- *
- * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_break_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_addr;
-#define REG_RD_ADDR_marb_bp_r_break_addr 20
-
-/* Register r_break_op, scope marb_bp, type r */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_break_op;
-#define REG_RD_ADDR_marb_bp_r_break_op 24
-
-/* Register r_break_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_clients;
-#define REG_RD_ADDR_marb_bp_r_break_clients 28
-
-/* Register r_break_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_first_client;
-#define REG_RD_ADDR_marb_bp_r_break_first_client 32
-
-/* Register r_break_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_size;
-#define REG_RD_ADDR_marb_bp_r_break_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h
deleted file mode 100644
index 872a7942916a..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_defs_h
-#define __marb_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb */
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_int_slots;
-#define REG_RD_ADDR_marb_rw_int_slots 0
-#define REG_WR_ADDR_marb_rw_int_slots 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ext_slots;
-#define REG_RD_ADDR_marb_rw_ext_slots 256
-#define REG_WR_ADDR_marb_rw_ext_slots 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_regs_slots;
-#define REG_RD_ADDR_marb_rw_regs_slots 512
-#define REG_WR_ADDR_marb_rw_regs_slots 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_intr_mask;
-#define REG_RD_ADDR_marb_rw_intr_mask 528
-#define REG_WR_ADDR_marb_rw_intr_mask 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ack_intr;
-#define REG_RD_ADDR_marb_rw_ack_intr 532
-#define REG_WR_ADDR_marb_rw_ack_intr 532
-
-/* Register r_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_intr;
-#define REG_RD_ADDR_marb_r_intr 536
-
-/* Register r_masked_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_masked_intr;
-#define REG_RD_ADDR_marb_r_masked_intr 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_stop_mask;
-#define REG_RD_ADDR_marb_rw_stop_mask 544
-#define REG_WR_ADDR_marb_rw_stop_mask 544
-
-/* Register r_stopped, scope marb, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_r_stopped;
-#define REG_RD_ADDR_marb_r_stopped 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_no_snoop;
-#define REG_RD_ADDR_marb_rw_no_snoop 832
-#define REG_WR_ADDR_marb_rw_no_snoop 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-typedef struct {
- unsigned int dummy1 : 10;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int dummy2 : 20;
-} reg_marb_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
-#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
-
-
-/* Constants */
-enum {
- regk_marb_cpud = 0x0000000b,
- regk_marb_cpui = 0x0000000a,
- regk_marb_dma0 = 0x00000000,
- regk_marb_dma1 = 0x00000001,
- regk_marb_dma2 = 0x00000002,
- regk_marb_dma3 = 0x00000003,
- regk_marb_dma4 = 0x00000004,
- regk_marb_dma5 = 0x00000005,
- regk_marb_dma6 = 0x00000006,
- regk_marb_dma7 = 0x00000007,
- regk_marb_dma8 = 0x00000008,
- regk_marb_dma9 = 0x00000009,
- regk_marb_iop = 0x0000000c,
- regk_marb_no = 0x00000000,
- regk_marb_r_stopped_default = 0x00000000,
- regk_marb_rw_ext_slots_default = 0x00000000,
- regk_marb_rw_ext_slots_size = 0x00000040,
- regk_marb_rw_int_slots_default = 0x00000000,
- regk_marb_rw_int_slots_size = 0x00000040,
- regk_marb_rw_intr_mask_default = 0x00000000,
- regk_marb_rw_no_snoop_default = 0x00000000,
- regk_marb_rw_no_snoop_rq_default = 0x00000000,
- regk_marb_rw_regs_slots_default = 0x00000000,
- regk_marb_rw_regs_slots_size = 0x00000004,
- regk_marb_rw_stop_mask_default = 0x00000000,
- regk_marb_slave = 0x0000000d,
- regk_marb_yes = 0x00000001
-};
-#endif /* __marb_defs_h */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h
deleted file mode 100644
index 0a316dc36a6b..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
- * last modfied: Mon Apr 11 16:09:11 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_pa, scope pinmux, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int csp2_n : 1;
- unsigned int csp3_n : 1;
- unsigned int csp5_n : 1;
- unsigned int csp6_n : 1;
- unsigned int hsh4 : 1;
- unsigned int hsh5 : 1;
- unsigned int hsh6 : 1;
- unsigned int hsh7 : 1;
- unsigned int dummy1 : 16;
-} reg_pinmux_rw_pa;
-#define REG_RD_ADDR_pinmux_rw_pa 0
-#define REG_WR_ADDR_pinmux_rw_pa 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ata0 : 1;
- unsigned int ata1 : 1;
- unsigned int ata2 : 1;
- unsigned int ata3 : 1;
- unsigned int ata : 1;
- unsigned int eth1 : 1;
- unsigned int eth1_mgm : 1;
- unsigned int timer : 1;
- unsigned int p21 : 1;
- unsigned int dummy1 : 18;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 4
-#define REG_WR_ADDR_pinmux_rw_hwprot 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int pb8 : 1;
- unsigned int pb9 : 1;
- unsigned int pb10 : 1;
- unsigned int pb11 : 1;
- unsigned int pb12 : 1;
- unsigned int pb13 : 1;
- unsigned int pb14 : 1;
- unsigned int pb15 : 1;
- unsigned int pb16 : 1;
- unsigned int pb17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_gio;
-#define REG_RD_ADDR_pinmux_rw_pb_gio 8
-#define REG_WR_ADDR_pinmux_rw_pb_gio 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int pb8 : 1;
- unsigned int pb9 : 1;
- unsigned int pb10 : 1;
- unsigned int pb11 : 1;
- unsigned int pb12 : 1;
- unsigned int pb13 : 1;
- unsigned int pb14 : 1;
- unsigned int pb15 : 1;
- unsigned int pb16 : 1;
- unsigned int pb17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_iop;
-#define REG_RD_ADDR_pinmux_rw_pb_iop 12
-#define REG_WR_ADDR_pinmux_rw_pb_iop 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pc0 : 1;
- unsigned int pc1 : 1;
- unsigned int pc2 : 1;
- unsigned int pc3 : 1;
- unsigned int pc4 : 1;
- unsigned int pc5 : 1;
- unsigned int pc6 : 1;
- unsigned int pc7 : 1;
- unsigned int pc8 : 1;
- unsigned int pc9 : 1;
- unsigned int pc10 : 1;
- unsigned int pc11 : 1;
- unsigned int pc12 : 1;
- unsigned int pc13 : 1;
- unsigned int pc14 : 1;
- unsigned int pc15 : 1;
- unsigned int pc16 : 1;
- unsigned int pc17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_gio;
-#define REG_RD_ADDR_pinmux_rw_pc_gio 16
-#define REG_WR_ADDR_pinmux_rw_pc_gio 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pc0 : 1;
- unsigned int pc1 : 1;
- unsigned int pc2 : 1;
- unsigned int pc3 : 1;
- unsigned int pc4 : 1;
- unsigned int pc5 : 1;
- unsigned int pc6 : 1;
- unsigned int pc7 : 1;
- unsigned int pc8 : 1;
- unsigned int pc9 : 1;
- unsigned int pc10 : 1;
- unsigned int pc11 : 1;
- unsigned int pc12 : 1;
- unsigned int pc13 : 1;
- unsigned int pc14 : 1;
- unsigned int pc15 : 1;
- unsigned int pc16 : 1;
- unsigned int pc17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_iop;
-#define REG_RD_ADDR_pinmux_rw_pc_iop 20
-#define REG_WR_ADDR_pinmux_rw_pc_iop 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pd0 : 1;
- unsigned int pd1 : 1;
- unsigned int pd2 : 1;
- unsigned int pd3 : 1;
- unsigned int pd4 : 1;
- unsigned int pd5 : 1;
- unsigned int pd6 : 1;
- unsigned int pd7 : 1;
- unsigned int pd8 : 1;
- unsigned int pd9 : 1;
- unsigned int pd10 : 1;
- unsigned int pd11 : 1;
- unsigned int pd12 : 1;
- unsigned int pd13 : 1;
- unsigned int pd14 : 1;
- unsigned int pd15 : 1;
- unsigned int pd16 : 1;
- unsigned int pd17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_gio;
-#define REG_RD_ADDR_pinmux_rw_pd_gio 24
-#define REG_WR_ADDR_pinmux_rw_pd_gio 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pd0 : 1;
- unsigned int pd1 : 1;
- unsigned int pd2 : 1;
- unsigned int pd3 : 1;
- unsigned int pd4 : 1;
- unsigned int pd5 : 1;
- unsigned int pd6 : 1;
- unsigned int pd7 : 1;
- unsigned int pd8 : 1;
- unsigned int pd9 : 1;
- unsigned int pd10 : 1;
- unsigned int pd11 : 1;
- unsigned int pd12 : 1;
- unsigned int pd13 : 1;
- unsigned int pd14 : 1;
- unsigned int pd15 : 1;
- unsigned int pd16 : 1;
- unsigned int pd17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_iop;
-#define REG_RD_ADDR_pinmux_rw_pd_iop 28
-#define REG_WR_ADDR_pinmux_rw_pd_iop 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pe0 : 1;
- unsigned int pe1 : 1;
- unsigned int pe2 : 1;
- unsigned int pe3 : 1;
- unsigned int pe4 : 1;
- unsigned int pe5 : 1;
- unsigned int pe6 : 1;
- unsigned int pe7 : 1;
- unsigned int pe8 : 1;
- unsigned int pe9 : 1;
- unsigned int pe10 : 1;
- unsigned int pe11 : 1;
- unsigned int pe12 : 1;
- unsigned int pe13 : 1;
- unsigned int pe14 : 1;
- unsigned int pe15 : 1;
- unsigned int pe16 : 1;
- unsigned int pe17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_gio;
-#define REG_RD_ADDR_pinmux_rw_pe_gio 32
-#define REG_WR_ADDR_pinmux_rw_pe_gio 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pe0 : 1;
- unsigned int pe1 : 1;
- unsigned int pe2 : 1;
- unsigned int pe3 : 1;
- unsigned int pe4 : 1;
- unsigned int pe5 : 1;
- unsigned int pe6 : 1;
- unsigned int pe7 : 1;
- unsigned int pe8 : 1;
- unsigned int pe9 : 1;
- unsigned int pe10 : 1;
- unsigned int pe11 : 1;
- unsigned int pe12 : 1;
- unsigned int pe13 : 1;
- unsigned int pe14 : 1;
- unsigned int pe15 : 1;
- unsigned int pe16 : 1;
- unsigned int pe17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_iop;
-#define REG_RD_ADDR_pinmux_rw_pe_iop 36
-#define REG_WR_ADDR_pinmux_rw_pe_iop 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-typedef struct {
- unsigned int en_usb0 : 1;
- unsigned int en_usb1 : 1;
- unsigned int dummy1 : 30;
-} reg_pinmux_rw_usb_phy;
-#define REG_RD_ADDR_pinmux_rw_usb_phy 40
-#define REG_WR_ADDR_pinmux_rw_usb_phy 40
-
-
-/* Constants */
-enum {
- regk_pinmux_no = 0x00000000,
- regk_pinmux_rw_hwprot_default = 0x00000000,
- regk_pinmux_rw_pa_default = 0x00000000,
- regk_pinmux_rw_pb_gio_default = 0x00000000,
- regk_pinmux_rw_pb_iop_default = 0x00000000,
- regk_pinmux_rw_pc_gio_default = 0x00000000,
- regk_pinmux_rw_pc_iop_default = 0x00000000,
- regk_pinmux_rw_pd_gio_default = 0x00000000,
- regk_pinmux_rw_pd_iop_default = 0x00000000,
- regk_pinmux_rw_pe_gio_default = 0x00000000,
- regk_pinmux_rw_pe_iop_default = 0x00000000,
- regk_pinmux_rw_usb_phy_default = 0x00000000,
- regk_pinmux_yes = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h
deleted file mode 100644
index 1bfca2666158..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/fakereg.rmap
- * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
- * last modified: Wed Feb 11 20:53:25 2004
- * file: ../../rtl/global.rmap
- * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
- * last modified: Mon Aug 18 17:08:23 2003
- * file: ../../mod/modreg.rmap
- * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
- * last modified: Fri Feb 20 16:40:04 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-typedef enum {
- regi_ata = 0xb0032000,
- regi_bif_core = 0xb0014000,
- regi_bif_dma = 0xb0016000,
- regi_bif_slave = 0xb0018000,
- regi_config = 0xb003c000,
- regi_dma0 = 0xb0000000,
- regi_dma1 = 0xb0002000,
- regi_dma2 = 0xb0004000,
- regi_dma3 = 0xb0006000,
- regi_dma4 = 0xb0008000,
- regi_dma5 = 0xb000a000,
- regi_dma6 = 0xb000c000,
- regi_dma7 = 0xb000e000,
- regi_dma8 = 0xb0010000,
- regi_dma9 = 0xb0012000,
- regi_eth0 = 0xb0034000,
- regi_eth1 = 0xb0036000,
- regi_gio = 0xb001a000,
- regi_iop = 0xb0020000,
- regi_iop_version = 0xb0020000,
- regi_iop_fifo_in0_extra = 0xb0020040,
- regi_iop_fifo_in1_extra = 0xb0020080,
- regi_iop_fifo_out0_extra = 0xb00200c0,
- regi_iop_fifo_out1_extra = 0xb0020100,
- regi_iop_trigger_grp0 = 0xb0020140,
- regi_iop_trigger_grp1 = 0xb0020180,
- regi_iop_trigger_grp2 = 0xb00201c0,
- regi_iop_trigger_grp3 = 0xb0020200,
- regi_iop_trigger_grp4 = 0xb0020240,
- regi_iop_trigger_grp5 = 0xb0020280,
- regi_iop_trigger_grp6 = 0xb00202c0,
- regi_iop_trigger_grp7 = 0xb0020300,
- regi_iop_crc_par0 = 0xb0020380,
- regi_iop_crc_par1 = 0xb0020400,
- regi_iop_dmc_in0 = 0xb0020480,
- regi_iop_dmc_in1 = 0xb0020500,
- regi_iop_dmc_out0 = 0xb0020580,
- regi_iop_dmc_out1 = 0xb0020600,
- regi_iop_fifo_in0 = 0xb0020680,
- regi_iop_fifo_in1 = 0xb0020700,
- regi_iop_fifo_out0 = 0xb0020780,
- regi_iop_fifo_out1 = 0xb0020800,
- regi_iop_scrc_in0 = 0xb0020880,
- regi_iop_scrc_in1 = 0xb0020900,
- regi_iop_scrc_out0 = 0xb0020980,
- regi_iop_scrc_out1 = 0xb0020a00,
- regi_iop_timer_grp0 = 0xb0020a80,
- regi_iop_timer_grp1 = 0xb0020b00,
- regi_iop_timer_grp2 = 0xb0020b80,
- regi_iop_timer_grp3 = 0xb0020c00,
- regi_iop_sap_in = 0xb0020d00,
- regi_iop_sap_out = 0xb0020e00,
- regi_iop_spu0 = 0xb0020f00,
- regi_iop_spu1 = 0xb0021000,
- regi_iop_sw_cfg = 0xb0021100,
- regi_iop_sw_cpu = 0xb0021200,
- regi_iop_sw_mpu = 0xb0021300,
- regi_iop_sw_spu0 = 0xb0021400,
- regi_iop_sw_spu1 = 0xb0021500,
- regi_iop_mpu = 0xb0021600,
- regi_irq = 0xb001c000,
- regi_irq2 = 0xb005c000,
- regi_marb = 0xb003e000,
- regi_marb_bp0 = 0xb003e240,
- regi_marb_bp1 = 0xb003e280,
- regi_marb_bp2 = 0xb003e2c0,
- regi_marb_bp3 = 0xb003e300,
- regi_pinmux = 0xb0038000,
- regi_ser0 = 0xb0026000,
- regi_ser1 = 0xb0028000,
- regi_ser2 = 0xb002a000,
- regi_ser3 = 0xb002c000,
- regi_sser0 = 0xb0022000,
- regi_sser1 = 0xb0024000,
- regi_strcop = 0xb0030000,
- regi_strmux = 0xb003a000,
- regi_timer = 0xb001e000,
- regi_timer0 = 0xb001e000,
- regi_timer2 = 0xb005e000,
- regi_trace = 0xb0040000,
-} reg_scope_instances;
-#endif /* __reg_map_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h
deleted file mode 100644
index 0ab49edb1c81..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
- * last modfied: Mon Apr 11 16:09:43 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
- unsigned int dma0 : 3;
- unsigned int dma1 : 3;
- unsigned int dma2 : 3;
- unsigned int dma3 : 3;
- unsigned int dma4 : 3;
- unsigned int dma5 : 3;
- unsigned int dma6 : 3;
- unsigned int dma7 : 3;
- unsigned int dma8 : 3;
- unsigned int dma9 : 3;
- unsigned int dummy1 : 2;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
- regk_strmux_ata = 0x00000003,
- regk_strmux_eth0 = 0x00000001,
- regk_strmux_eth1 = 0x00000004,
- regk_strmux_ext0 = 0x00000001,
- regk_strmux_ext1 = 0x00000001,
- regk_strmux_ext2 = 0x00000001,
- regk_strmux_ext3 = 0x00000001,
- regk_strmux_iop0 = 0x00000002,
- regk_strmux_iop1 = 0x00000001,
- regk_strmux_off = 0x00000000,
- regk_strmux_p21 = 0x00000004,
- regk_strmux_rw_cfg_default = 0x00000000,
- regk_strmux_ser0 = 0x00000002,
- regk_strmux_ser1 = 0x00000002,
- regk_strmux_ser2 = 0x00000004,
- regk_strmux_ser3 = 0x00000003,
- regk_strmux_sser0 = 0x00000003,
- regk_strmux_sser1 = 0x00000003,
- regk_strmux_strcop = 0x00000002
-};
-#endif /* __strmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h
deleted file mode 100644
index 59c70ba9959b..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_h
-#define __timer_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- * last modfied: Mon Apr 11 16:09:53 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope timer */
-
-/* Register rw_tmr0_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr0_div;
-#define REG_RD_ADDR_timer_rw_tmr0_div 0
-#define REG_WR_ADDR_timer_rw_tmr0_div 0
-
-/* Register r_tmr0_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr0_data;
-#define REG_RD_ADDR_timer_r_tmr0_data 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr0_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
-#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr1_div;
-#define REG_RD_ADDR_timer_rw_tmr1_div 16
-#define REG_WR_ADDR_timer_rw_tmr1_div 16
-
-/* Register r_tmr1_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr1_data;
-#define REG_RD_ADDR_timer_r_tmr1_data 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr1_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
-#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_rs_cnt_data;
-#define REG_RD_ADDR_timer_rs_cnt_data 32
-
-/* Register r_cnt_data, scope timer, type r */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_r_cnt_data;
-#define REG_RD_ADDR_timer_r_cnt_data 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-typedef struct {
- unsigned int clk : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_cnt_cfg;
-#define REG_RD_ADDR_timer_rw_cnt_cfg 40
-#define REG_WR_ADDR_timer_rw_cnt_cfg 40
-
-/* Register rw_trig, scope timer, type rw */
-typedef unsigned int reg_timer_rw_trig;
-#define REG_RD_ADDR_timer_rw_trig 48
-#define REG_WR_ADDR_timer_rw_trig 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_trig_cfg;
-#define REG_RD_ADDR_timer_rw_trig_cfg 52
-#define REG_WR_ADDR_timer_rw_trig_cfg 52
-
-/* Register r_time, scope timer, type r */
-typedef unsigned int reg_timer_r_time;
-#define REG_RD_ADDR_timer_r_time 56
-
-/* Register rw_out, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_out;
-#define REG_RD_ADDR_timer_rw_out 60
-#define REG_WR_ADDR_timer_rw_out 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int key : 7;
- unsigned int dummy1 : 16;
-} reg_timer_rw_wd_ctrl;
-#define REG_RD_ADDR_timer_rw_wd_ctrl 64
-#define REG_WR_ADDR_timer_rw_wd_ctrl 64
-
-/* Register r_wd_stat, scope timer, type r */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int dummy1 : 23;
-} reg_timer_r_wd_stat;
-#define REG_RD_ADDR_timer_r_wd_stat 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_intr_mask;
-#define REG_RD_ADDR_timer_rw_intr_mask 72
-#define REG_WR_ADDR_timer_rw_intr_mask 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_ack_intr;
-#define REG_RD_ADDR_timer_rw_ack_intr 76
-#define REG_WR_ADDR_timer_rw_ack_intr 76
-
-/* Register r_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_intr;
-#define REG_RD_ADDR_timer_r_intr 80
-
-/* Register r_masked_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_masked_intr;
-#define REG_RD_ADDR_timer_r_masked_intr 84
-
-/* Register rw_test, scope timer, type rw */
-typedef struct {
- unsigned int dis : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 30;
-} reg_timer_rw_test;
-#define REG_RD_ADDR_timer_rw_test 88
-#define REG_WR_ADDR_timer_rw_test 88
-
-
-/* Constants */
-enum {
- regk_timer_ext = 0x00000001,
- regk_timer_f100 = 0x00000007,
- regk_timer_f29_493 = 0x00000004,
- regk_timer_f32 = 0x00000005,
- regk_timer_f32_768 = 0x00000006,
- regk_timer_hold = 0x00000001,
- regk_timer_ld = 0x00000000,
- regk_timer_no = 0x00000000,
- regk_timer_off = 0x00000000,
- regk_timer_run = 0x00000002,
- regk_timer_rw_cnt_cfg_default = 0x00000000,
- regk_timer_rw_intr_mask_default = 0x00000000,
- regk_timer_rw_out_default = 0x00000000,
- regk_timer_rw_test_default = 0x00000000,
- regk_timer_rw_tmr0_ctrl_default = 0x00000000,
- regk_timer_rw_tmr1_ctrl_default = 0x00000000,
- regk_timer_rw_trig_cfg_default = 0x00000000,
- regk_timer_start = 0x00000001,
- regk_timer_stop = 0x00000000,
- regk_timer_time = 0x00000001,
- regk_timer_tmr0 = 0x00000002,
- regk_timer_tmr1 = 0x00000003,
- regk_timer_yes = 0x00000001
-};
-#endif /* __timer_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
deleted file mode 100644
index 94328936cc91..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00020000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h b/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h
deleted file mode 100644
index 1d87f1392dc8..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_B 0
-#define PORT_C 1
-#define PORT_D 2
-#define PORT_E 3
-
-enum pin_mode {
- pinmux_none = 0,
- pinmux_fixed,
- pinmux_gpio,
- pinmux_iop
-};
-
-enum fixed_function {
- pinmux_ser1,
- pinmux_ser2,
- pinmux_ser3,
- pinmux_sser0,
- pinmux_sser1,
- pinmux_ata0,
- pinmux_ata1,
- pinmux_ata2,
- pinmux_ata3,
- pinmux_ata,
- pinmux_eth1,
- pinmux_timer
-};
-
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
deleted file mode 100644
index 96c3b0fb62c1..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef STARTUP_INC_INCLUDED
-#define STARTUP_INC_INCLUDED
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-#include <hwregs/asm/config_defs_asm.h>
-
- .macro GIO_INIT
- move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1
- move.d $r0, [$r1]
- .endm
-
- .macro START_CLOCKS
- move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(config, rw_clk_ctrl, bif, yes) | \
- REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
- move.d $r0, [$r1]
- .endm
-
- .macro SETUP_WAIT_STATES
- ;; Set up waitstates etc
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
- move.d $r1, [$r0]
- .endm
-
-#endif
diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild
deleted file mode 100644
index 6a547fe8752b..000000000000
--- a/arch/cris/include/asm/Kbuild
+++ /dev/null
@@ -1,31 +0,0 @@
-generic-y += atomic.h
-generic-y += barrier.h
-generic-y += cmpxchg.h
-generic-y += current.h
-generic-y += device.h
-generic-y += div64.h
-generic-y += dma-mapping.h
-generic-y += emergency-restart.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += futex.h
-generic-y += hardirq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += linkage.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += module.h
-generic-y += percpu.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += topology.h
-generic-y += trace_clock.h
-generic-y += vga.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
diff --git a/arch/cris/include/asm/asm-offsets.h b/arch/cris/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/cris/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/cris/include/asm/axisflashmap.h b/arch/cris/include/asm/axisflashmap.h
deleted file mode 100644
index 185596c2caab..000000000000
--- a/arch/cris/include/asm/axisflashmap.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_AXISFLASHMAP_H
-#define __ASM_AXISFLASHMAP_H
-
-/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC
- * as start, it ends with 0xFFFFFFFF */
-#define FLASH_BOOT_MAGIC 0xbeefcace
-#define BOOTPARAM_OFFSET 0xc000
-/* apps/bootblocktool is used to read and write the parameters,
- * and it has nothing to do with the partition table.
- */
-
-#define PARTITION_TABLE_OFFSET 10
-#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */
-
-/* The partitiontable_head is located at offset +10: */
-struct partitiontable_head {
- __u16 magic; /* PARTITION_TABLE_MAGIC */
- __u16 size; /* Length of ptable block (entries + end marker) */
- __u32 checksum; /* simple longword sum, over entries + end marker */
-};
-
-/* And followed by partition table entries */
-struct partitiontable_entry {
- __u32 offset; /* relative to the sector the ptable is in */
- __u32 size; /* in bytes */
- __u32 checksum; /* simple longword sum */
- __u16 type; /* see type codes below */
- __u16 flags; /* bit 0: ro/rw = 1/0 */
- __u32 future0; /* 16 bytes reserved for future use */
- __u32 future1;
- __u32 future2;
- __u32 future3;
-};
-/* ended by an end marker: */
-#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF
-#define PARTITIONTABLE_END_MARKER_SIZE 4
-
-#define PARTITIONTABLE_END_PAD 10
-
-/* Complete structure for whole partition table */
-/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting
- * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER.
- */
-struct partitiontable {
- __u8 skip[PARTITION_TABLE_OFFSET];
- struct partitiontable_head head;
- struct partitiontable_entry entries[];
-};
-
-#define PARTITION_TYPE_PARAM 0x0001
-#define PARTITION_TYPE_KERNEL 0x0002
-#define PARTITION_TYPE_JFFS 0x0003
-#define PARTITION_TYPE_JFFS2 0x0000
-
-#define PARTITION_FLAGS_READONLY_MASK 0x0001
-#define PARTITION_FLAGS_READONLY 0x0001
-
-/* The master mtd for the entire flash. */
-extern struct mtd_info *axisflash_mtd;
-
-#endif
diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h
deleted file mode 100644
index 78f975ad42d9..000000000000
--- a/arch/cris/include/asm/bitops.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* asm/bitops.h for Linux/CRIS
- *
- * TODO: asm versions if speed is needed
- *
- * All bit operations return 0 if the bit was cleared before the
- * operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-#ifndef _CRIS_BITOPS_H
-#define _CRIS_BITOPS_H
-
-/* Currently this is unsuitable for consumption outside the kernel. */
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <arch/bitops.h>
-#include <linux/compiler.h>
-#include <asm/barrier.h>
-
-#include <asm-generic/bitops/atomic.h>
-#include <asm-generic/bitops/non-atomic.h>
-
-/*
- * Since we define it "external", it collides with the built-in
- * definition, which doesn't have the same semantics. We don't want to
- * use -fno-builtin, so just hide the name ffs.
- */
-#define ffs(x) kernel_ffs(x)
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/le.h>
-
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-
-#include <asm-generic/bitops/sched.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _CRIS_BITOPS_H */
diff --git a/arch/cris/include/asm/bug.h b/arch/cris/include/asm/bug.h
deleted file mode 100644
index f1fa72a426c2..000000000000
--- a/arch/cris/include/asm/bug.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_BUG_H
-#define _CRIS_BUG_H
-#include <arch/bug.h>
-#endif
diff --git a/arch/cris/include/asm/bugs.h b/arch/cris/include/asm/bugs.h
deleted file mode 100644
index c5907aac1007..000000000000
--- a/arch/cris/include/asm/bugs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $
- *
- * include/asm-cris/bugs.h
- *
- * Copyright (C) 2001 Axis Communications AB
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- * void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
-
-
-
-
diff --git a/arch/cris/include/asm/cache.h b/arch/cris/include/asm/cache.h
deleted file mode 100644
index 8dac0922721c..000000000000
--- a/arch/cris/include/asm/cache.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <arch/cache.h>
-
-#endif /* _ASM_CACHE_H */
diff --git a/arch/cris/include/asm/cacheflush.h b/arch/cris/include/asm/cacheflush.h
deleted file mode 100644
index 0da1c76a2bbc..000000000000
--- a/arch/cris/include/asm/cacheflush.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_CACHEFLUSH_H
-#define _CRIS_CACHEFLUSH_H
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-
-/* The cache doesn't need to be flushed when TLB entries change because
- * the cache is mapped to physical memory, not virtual memory
- */
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_range(start, end) do { } while (0)
-#define flush_icache_page(vma,pg) do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-
-int change_page_attr(struct page *page, int numpages, pgprot_t prot);
-
-#endif /* _CRIS_CACHEFLUSH_H */
diff --git a/arch/cris/include/asm/checksum.h b/arch/cris/include/asm/checksum.h
deleted file mode 100644
index 61b6a4f6a002..000000000000
--- a/arch/cris/include/asm/checksum.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */
-
-#ifndef _CRIS_CHECKSUM_H
-#define _CRIS_CHECKSUM_H
-
-#include <arch/checksum.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-
-/*
- * Fold a partial checksum into a word
- */
-
-static inline __sum16 csum_fold(__wsum csum)
-{
- u32 sum = (__force u32)csum;
- sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */
- sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */
- return (__force __sum16)~sum;
-}
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum,
- int *errptr);
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- */
-
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- return csum_fold(csum_partial(iph, ihl * 4, 0));
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold (csum_partial(buff, len, 0));
-}
-
-#endif
diff --git a/arch/cris/include/asm/delay.h b/arch/cris/include/asm/delay.h
deleted file mode 100644
index 2dfdb13e1a9e..000000000000
--- a/arch/cris/include/asm/delay.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_DELAY_H
-#define _CRIS_DELAY_H
-
-/*
- * Copyright (C) 1998-2002 Axis Communications AB
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-#include <arch/delay.h>
-
-/* Use only for very small delays ( < 1 msec). */
-
-extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */
-
-/* May be defined by arch/delay.h. */
-#ifndef udelay
-static inline void udelay(unsigned long usecs)
-{
- __delay(usecs * loops_per_usec);
-}
-#endif
-
-#endif /* defined(_CRIS_DELAY_H) */
-
-
-
diff --git a/arch/cris/include/asm/dma.h b/arch/cris/include/asm/dma.h
deleted file mode 100644
index e1f7d6d9bfc2..000000000000
--- a/arch/cris/include/asm/dma.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <arch/dma.h>
-
-/* it's useless on the Etrax, but unfortunately needed by the new
- bootmem allocator (but this should do it for this) */
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/arch/cris/include/asm/eshlibld.h b/arch/cris/include/asm/eshlibld.h
deleted file mode 100644
index 88940556c2db..000000000000
--- a/arch/cris/include/asm/eshlibld.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*!**************************************************************************
-*!
-*! FILE NAME : eshlibld.h
-*!
-*! DESCRIPTION: Prototypes for exported shared library functions
-*!
-*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit
-*! (EXPORTED)
-*!
-*!---------------------------------------------------------------------------
-*!
-*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN
-*!
-*!**************************************************************************/
-/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */
-
-#ifndef _cris_relocate_h
-#define _cris_relocate_h
-
-/* Please note that this file is also compiled into the xsim simulator.
- Try to avoid breaking its double use (only works on a little-endian
- 32-bit machine such as the i386 anyway).
-
- Use __KERNEL__ when you're about to use kernel functions,
- (which you should not do here anyway, since this file is
- used by glibc).
- Use defined(__KERNEL__) || defined(__elinux__) when doing
- things that only makes sense on an elinux system.
- Use __CRIS__ when you're about to do (really) CRIS-specific code.
-*/
-
-/* We have dependencies all over the place for the host system
- for xsim being a linux system, so let's not pretend anything
- else with #ifdef:s here until fixed. */
-#include <linux/limits.h>
-
-/* Maybe do sanity checking if file input. */
-#undef SANITYCHECK_RELOC
-
-/* Maybe output debug messages. */
-#undef RELOC_DEBUG
-
-/* Maybe we want to share core as well as disk space.
- Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is
- assumed that we want to share code when debugging (exposes more
- trouble). */
-#ifndef SHARE_LIB_CORE
-# if (defined(__KERNEL__) || !defined(RELOC_DEBUG))
-# define SHARE_LIB_CORE 0
-# else
-# define SHARE_LIB_CORE 1
-# endif /* __KERNEL__ etc */
-#endif /* SHARE_LIB_CORE */
-
-
-/* Main exported function; supposed to be called when the program a.out
- has been read in. */
-extern int
-perform_cris_aout_relocations(unsigned long text, unsigned long tlength,
- unsigned long data, unsigned long dlength,
- unsigned long baddr, unsigned long blength,
-
- /* These may be zero when there's "perfect"
- position-independent code. */
- unsigned char *trel, unsigned long tsrel,
- unsigned long dsrel,
-
- /* These will be zero at a first try, to see
- if code is statically linked. Else a
- second try, with the symbol table and
- string table nonzero should be done. */
- unsigned char *symbols, unsigned long symlength,
- unsigned char *strings, unsigned long stringlength,
-
- /* These will only be used when symbol table
- information is present. */
- char **env, int envc,
- int euid, int is_suid);
-
-
-#ifdef RELOC_DEBUG
-/* Task-specific debug stuff. */
-struct task_reloc_debug {
- struct memdebug *alloclast;
- unsigned long alloc_total;
- unsigned long export_total;
-};
-#endif /* RELOC_DEBUG */
-
-#if SHARE_LIB_CORE
-
-/* When code (and some very specific data) is shared and not just
- dynamically linked, we need to export hooks for exec beginning and
- end. */
-
-struct shlibdep;
-
-extern void
-shlibmod_exit(struct shlibdep **deps);
-
-/* Returns 0 if failure, nonzero for ok. */
-extern int
-shlibmod_fork(struct shlibdep **deps);
-
-#else /* ! SHARE_LIB_CORE */
-# define shlibmod_exit(x)
-# define shlibmod_fork(x) 1
-#endif /* ! SHARE_LIB_CORE */
-
-#endif _cris_relocate_h
-/********************** END OF FILE eshlibld.h *****************************/
-
diff --git a/arch/cris/include/asm/etraxi2c.h b/arch/cris/include/asm/etraxi2c.h
deleted file mode 100644
index 0fa6f03d93e7..000000000000
--- a/arch/cris/include/asm/etraxi2c.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */
-
-#ifndef _LINUX_ETRAXI2C_H
-#define _LINUX_ETRAXI2C_H
-
-/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-
-#define ETRAXI2C_IOCTYPE 44
-
-/* supported ioctl _IOC_NR's */
-
-/* in write operations, the argument contains both i2c
- * slave, register and value.
- */
-
-#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
-#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))
-
-#define I2C_ARGSLAVE(arg) ((arg) >> 16)
-#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)
-#define I2C_ARGVALUE(arg) ((arg) & 0xff)
-
-#define I2C_WRITEREG 0x1 /* write to an i2c register */
-#define I2C_READREG 0x2 /* read from an i2c register */
-
-/*
-EXAMPLE usage:
-
- i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
- ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
-
- i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
- val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
-
-*/
-#endif
diff --git a/arch/cris/include/asm/fasttimer.h b/arch/cris/include/asm/fasttimer.h
deleted file mode 100644
index bc109f4a8377..000000000000
--- a/arch/cris/include/asm/fasttimer.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/include/asm-cris/fasttimer.h
- *
- * Fast timers for ETRAX100LX
- * Copyright (C) 2000-2007 Axis Communications AB
- */
-#include <linux/time.h> /* struct timeval */
-#include <linux/timex.h>
-
-#ifdef CONFIG_ETRAX_FAST_TIMER
-
-typedef void fast_timer_function_type(unsigned long);
-
-struct fasttime_t {
- unsigned long tv_jiff; /* jiffies */
- unsigned long tv_usec; /* microseconds */
-};
-
-struct fast_timer{ /* Close to timer_list */
- struct fast_timer *next;
- struct fast_timer *prev;
- struct fasttime_t tv_set;
- struct fasttime_t tv_expires;
- unsigned long delay_us;
- fast_timer_function_type *function;
- unsigned long data;
- const char *name;
-};
-
-extern struct fast_timer *fast_timer_list;
-
-void start_one_shot_timer(struct fast_timer *t,
- fast_timer_function_type *function,
- unsigned long data,
- unsigned long delay_us,
- const char *name);
-
-int del_fast_timer(struct fast_timer * t);
-/* return 1 if deleted */
-
-
-void schedule_usleep(unsigned long us);
-
-
-int fast_timer_init(void);
-
-#endif
diff --git a/arch/cris/include/asm/fb.h b/arch/cris/include/asm/fb.h
deleted file mode 100644
index e10150073c30..000000000000
--- a/arch/cris/include/asm/fb.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
- return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/arch/cris/include/asm/ftrace.h b/arch/cris/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/cris/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/cris/include/asm/hw_irq.h b/arch/cris/include/asm/hw_irq.h
deleted file mode 100644
index 298066020af2..000000000000
--- a/arch/cris/include/asm/hw_irq.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-#endif
-
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h
deleted file mode 100644
index c92712d30f54..000000000000
--- a/arch/cris/include/asm/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_IO_H
-#define _ASM_CRIS_IO_H
-
-#include <asm/page.h> /* for __va, __pa */
-#ifdef CONFIG_ETRAX_ARCH_V10
-#include <arch/io.h>
-#endif
-#include <asm-generic/iomap.h>
-#include <linux/kernel.h>
-
-extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
-
-static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
-{
- return __ioremap(offset, size, 0);
-}
-
-extern void iounmap(volatile void * __iomem addr);
-
-extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
-
-#include <asm-generic/io.h>
-
-#endif
diff --git a/arch/cris/include/asm/irq.h b/arch/cris/include/asm/irq.h
deleted file mode 100644
index 6a932f7db58e..000000000000
--- a/arch/cris/include/asm/irq.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-
-#include <arch/irq.h>
-
-static inline int irq_canonicalize(int irq)
-{
- return irq;
-}
-
-#endif /* _ASM_IRQ_H */
-
-
diff --git a/arch/cris/include/asm/irqflags.h b/arch/cris/include/asm/irqflags.h
deleted file mode 100644
index 943ba5ca6d2c..000000000000
--- a/arch/cris/include/asm/irqflags.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <arch/irqflags.h>
diff --git a/arch/cris/include/asm/mmu.h b/arch/cris/include/asm/mmu.h
deleted file mode 100644
index 54da8f64b37a..000000000000
--- a/arch/cris/include/asm/mmu.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRIS MMU constants and PTE layout
- */
-
-#ifndef _CRIS_MMU_H
-#define _CRIS_MMU_H
-
-#include <arch/mmu.h>
-
-#endif
diff --git a/arch/cris/include/asm/mmu_context.h b/arch/cris/include/asm/mmu_context.h
deleted file mode 100644
index 178f3b72e9e3..000000000000
--- a/arch/cris/include/asm/mmu_context.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CRIS_MMU_CONTEXT_H
-#define __CRIS_MMU_CONTEXT_H
-
-#include <asm-generic/mm_hooks.h>
-
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void get_mmu_context(struct mm_struct *mm);
-extern void destroy_context(struct mm_struct *mm);
-extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk);
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- switch_mm(prev, next, NULL);
- local_irq_restore(flags);
-}
-
-/* current active pgd - this is similar to other processors pgd
- * registers like cr3 on the i386
- */
-
-/* defined in arch/cris/mm/fault.c */
-DECLARE_PER_CPU(pgd_t *, current_pgd);
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#endif
diff --git a/arch/cris/include/asm/page.h b/arch/cris/include/asm/page.h
deleted file mode 100644
index 5b5b3dad7484..000000000000
--- a/arch/cris/include/asm/page.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_PAGE_H
-#define _CRIS_PAGE_H
-
-#include <arch/page.h>
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT 13
-#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr, pg) clear_page(page)
-#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
- alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-#ifndef __ASSEMBLY__
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-#endif
-
-#define pte_val(x) ((x).pte)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-
-/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */
-/* for that before indexing into the page table starting at mem_map */
-#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
-#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr)
-
-/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so
- * we can let the map start there. notice that we subtract PAGE_OFFSET because
- * we start our mem_map there - in other ports they map mem_map physically and
- * use __pa instead. in our system both the physical and virtual address of DRAM
- * is too high to let mem_map start at 0, so we do it this way instead (similar
- * to arm and m68k I think)
- */
-
-#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT))
-#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT)
-
-/* convert a page (based on mem_map and forward) to a physical address
- * do this by figuring out the virtual address and then use __pa
- */
-
-#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _CRIS_PAGE_H */
-
diff --git a/arch/cris/include/asm/pci.h b/arch/cris/include/asm/pci.h
deleted file mode 100644
index dcfef6407ae6..000000000000
--- a/arch/cris/include/asm/pci.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_PCI_H
-#define __ASM_CRIS_PCI_H
-
-
-#ifdef __KERNEL__
-#include <linux/mm.h> /* for struct page */
-
-/* Can be used to override the logic in pci_scan_bus for skipping
- already-configured bus numbers - to be used for buggy BIOSes
- or architectures with incomplete PCI setup by the loader */
-
-#define pcibios_assign_all_busses(void) 1
-
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#define PCIBIOS_MIN_CARDBUS_IO 0x4000
-
-/* Dynamic DMA mapping stuff.
- * i386 has everything mapped statically.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/scatterlist.h>
-#include <linux/string.h>
-#include <asm/io.h>
-
-/* The PCI address space does equal the physical memory
- * address space. The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS (1)
-
-#define HAVE_PCI_MMAP
-#define ARCH_GENERIC_PCI_MMAP_RESOURCE
-
-#endif /* __KERNEL__ */
-
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
-#endif /* __ASM_CRIS_PCI_H */
diff --git a/arch/cris/include/asm/pgalloc.h b/arch/cris/include/asm/pgalloc.h
deleted file mode 100644
index d8dc1b834b7d..000000000000
--- a/arch/cris/include/asm/pgalloc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_PGALLOC_H
-#define _CRIS_PGALLOC_H
-
-#include <linux/threads.h>
-#include <linux/mm.h>
-
-#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte)
-#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-
-static inline pgd_t *pgd_alloc (struct mm_struct *mm)
-{
- return (pgd_t *)get_zeroed_page(GFP_KERNEL);
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
- return pte;
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *pte;
- pte = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
- if (!pte)
- return NULL;
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb,pte,address) \
-do { \
- pgtable_page_dtor(pte); \
- tlb_remove_page((tlb), pte); \
-} while (0)
-
-#define check_pgt_cache() do { } while (0)
-
-#endif
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
deleted file mode 100644
index 03fca401e23c..000000000000
--- a/arch/cris/include/asm/pgtable.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRIS pgtable.h - macros and functions to manipulate page tables.
- */
-
-#ifndef _CRIS_PGTABLE_H
-#define _CRIS_PGTABLE_H
-
-#include <asm/page.h>
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopmd.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/sched/mm.h>
-#include <asm/mmu.h>
-#endif
-#include <arch/pgtable.h>
-
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * CRIS, we use that, but "fold" the mid level into the top-level page
- * table. Since the MMU TLB is software loaded through an interrupt, it
- * supports any page table structure, so we could have used a three-level
- * setup, but for the amounts of memory we normally use, a two-level is
- * probably more efficient.
- *
- * This file contains the functions and defines necessary to modify and use
- * the CRIS page table tree.
- */
-#ifndef __ASSEMBLY__
-extern void paging_init(void);
-#endif
-
-/* Certain architectures need to do special things when pte's
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
-
-/* PGDIR_SHIFT determines the size of the area a second-level page table can
- * map. It is equal to the page size times the number of PTE's that fit in
- * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
- */
-
-#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: we use a two-level, so
- * we don't really have any PMD directory physically.
- * pointers are 4 bytes so we can use the page size and
- * divide it by 4 (shift by 2).
- */
-#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
-#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
-
-/* calculate how many PGD entries a user-level program can use
- * the first mappable virtual address is 0
- * (TASK_SIZE is the maximum virtual address space)
- */
-
-#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-/* zero page used for uninitialized stuff */
-#ifndef __ASSEMBLY__
-extern unsigned long empty_zero_page;
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-#endif
-
-/* number of bits that fit into a memory pointer */
-#define BITS_PER_PTR (8*sizeof(unsigned long))
-
-/* to align the pointer to a pointer address */
-#define PTR_MASK (~(sizeof(void*)-1))
-
-/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
-/* 64-bit machines, beware! SRB. */
-#define SIZEOF_PTR_LOG2 2
-
-/* to find an entry in a page-table */
-#define PAGE_PTR(address) \
-((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
-
-/* to set the page-dir */
-#define SET_PAGE_DIR(tsk,pgdir)
-
-#define pte_none(x) (!pte_val(x))
-#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad
- * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
- */
-#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-
-static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
-static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_special(pte_t pte) { return 0; }
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
- return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
- return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
- return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= _PAGE_WRITE;
- if (pte_val(pte) & _PAGE_MODIFIED)
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
- pte_val(pte) |= _PAGE_MODIFIED;
- if (pte_val(pte) & _PAGE_WRITE)
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
- pte_val(pte) |= _PAGE_ACCESSED;
- if (pte_val(pte) & _PAGE_READ)
- {
- pte_val(pte) |= _PAGE_SILENT_READ;
- if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
- (_PAGE_WRITE | _PAGE_MODIFIED))
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- }
- return pte;
-}
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-/* What actually goes as arguments to the various functions is less than
- * obvious, but a rule of thumb is that struct page's goes as struct page *,
- * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
- * addresses (the 0xc0xxxxxx's) goes as void *'s.
- */
-
-static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
-{
- pte_t pte;
- /* the PTE needs a physical address */
- pte_val(pte) = __pa(page) | pgprot_val(pgprot);
- return pte;
-}
-
-#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
-
-#define mk_pte_phys(physpage, pgprot) \
-({ \
- pte_t __pte; \
- \
- pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
- __pte; \
-})
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
-
-#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
-
-
-/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
- * __pte_page(pte_val) refers to the "virtual" DRAM interval
- * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
- */
-
-static inline unsigned long __pte_page(pte_t pte)
-{
- /* the PTE contains a physical address */
- return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
-}
-
-#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
-
-/* permanent address of a page */
-
-#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
-#define pte_page(pte) (mem_map+pte_pagenr(pte))
-
-/* only the pte's themselves need to point to physical DRAM (see above)
- * the pagetable links are purely handled within the kernel SW and thus
- * don't need the __pa and __va transformations.
- */
-
-static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
-{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
-
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
-/* to find an entry in a page-table-directory */
-static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
-{
- return mm->pgd + pgd_index(address);
-}
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* Find an entry in the third-level page table.. */
-#define __pte_offset(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-
-#define pte_unmap(pte) do { } while (0)
-#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
-
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
-
-/*
- * CRIS doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- *
- * Actually I am not sure on what this could be used for.
- */
-static inline void update_mmu_cache(struct vm_area_struct * vma,
- unsigned long address, pte_t *ptep)
-{
-}
-
-/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
-/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
-
-#define __swp_type(x) (((x).val >> 5) & 0x7f)
-#define __swp_offset(x) ((x).val >> 12)
-#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define kern_addr_valid(addr) (1)
-
-#include <asm-generic/pgtable.h>
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init() do { } while (0)
-
-typedef pte_t *pte_addr_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* _CRIS_PGTABLE_H */
diff --git a/arch/cris/include/asm/processor.h b/arch/cris/include/asm/processor.h
deleted file mode 100644
index ee4d8b03d048..000000000000
--- a/arch/cris/include/asm/processor.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * include/asm-cris/processor.h
- *
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen Initial version
- *
- */
-
-#ifndef __ASM_CRIS_PROCESSOR_H
-#define __ASM_CRIS_PROCESSOR_H
-
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <arch/processor.h>
-#include <arch/system.h>
-
-struct task_struct;
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
-
-/*
- * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack.
- * This macro allows us to find those regs for a task.
- * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while
- * we're in the kernel, won't affect this - only the first user->kernel transition
- * registers are reached by this.
- */
-
-#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1)
-
-/*
- * Dito but for the currently running task
- */
-
-#define task_pt_regs(task) user_regs(task_thread_info(task))
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
- /* Nothing needs to be done. */
-}
-
-#define cpu_relax() barrier()
-
-void default_idle(void);
-
-#endif /* __ASM_CRIS_PROCESSOR_H */
diff --git a/arch/cris/include/asm/ptrace.h b/arch/cris/include/asm/ptrace.h
deleted file mode 100644
index d69295f1a7c8..000000000000
--- a/arch/cris/include/asm/ptrace.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_PTRACE_H
-#define _CRIS_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-
-#define profile_pc(regs) instruction_pointer(regs)
-#define current_user_stack_pointer() rdusp()
-
-#endif /* _CRIS_PTRACE_H */
diff --git a/arch/cris/include/asm/segment.h b/arch/cris/include/asm/segment.h
deleted file mode 100644
index 6ac914b098bf..000000000000
--- a/arch/cris/include/asm/segment.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SEGMENT_H
-#define _ASM_SEGMENT_H
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#endif
diff --git a/arch/cris/include/asm/serial.h b/arch/cris/include/asm/serial.h
deleted file mode 100644
index f51e0e10faa7..000000000000
--- a/arch/cris/include/asm/serial.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SERIAL_H
-#define _ASM_SERIAL_H
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- */
-#define BASE_BAUD (1843200 / 16)
-
-#endif /* _ASM_SERIAL_H */
diff --git a/arch/cris/include/asm/shmparam.h b/arch/cris/include/asm/shmparam.h
deleted file mode 100644
index 704a7257cb0d..000000000000
--- a/arch/cris/include/asm/shmparam.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_SHMPARAM_H
-#define _ASM_CRIS_SHMPARAM_H
-
-/* same as asm-i386/ version.. */
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_CRIS_SHMPARAM_H */
diff --git a/arch/cris/include/asm/signal.h b/arch/cris/include/asm/signal.h
deleted file mode 100644
index 64b0943c0b00..000000000000
--- a/arch/cris/include/asm/signal.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_SIGNAL_H
-#define _ASM_CRIS_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-/* Most things should be clean enough to redefine this at will, if care
- is taken to make libc match. */
-
-#define _NSIG 64
-#define _NSIG_BPW 32
-#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t; /* at least 32 bits */
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#define __ARCH_HAS_SA_RESTORER
-
-#include <asm/sigcontext.h>
-
-#endif
diff --git a/arch/cris/include/asm/stacktrace.h b/arch/cris/include/asm/stacktrace.h
deleted file mode 100644
index 154f0c90d0fa..000000000000
--- a/arch/cris/include/asm/stacktrace.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CRIS_STACKTRACE_H
-#define __CRIS_STACKTRACE_H
-
-void walk_stackframe(unsigned long sp,
- int (*fn)(unsigned long addr, void *data),
- void *data);
-
-#endif
diff --git a/arch/cris/include/asm/string.h b/arch/cris/include/asm/string.h
deleted file mode 100644
index bae5a0867785..000000000000
--- a/arch/cris/include/asm/string.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_STRING_H
-#define _ASM_CRIS_STRING_H
-
-/* the optimized memcpy is in arch/cris/lib/string.c */
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *, const void *, size_t);
-
-/* New and improved. In arch/cris/lib/memset.c */
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *, int, size_t);
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-/* For v32 we provide strcmp. */
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *s1, const char *s2);
-#endif
-
-#endif
diff --git a/arch/cris/include/asm/swab.h b/arch/cris/include/asm/swab.h
deleted file mode 100644
index 5e1d8cf277fb..000000000000
--- a/arch/cris/include/asm/swab.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_SWAB_H
-#define _CRIS_SWAB_H
-
-#include <arch/swab.h>
-#include <uapi/asm/swab.h>
-
-#endif /* _CRIS_SWAB_H */
diff --git a/arch/cris/include/asm/switch_to.h b/arch/cris/include/asm/switch_to.h
deleted file mode 100644
index dde4acf6e54d..000000000000
--- a/arch/cris/include/asm/switch_to.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_SWITCH_TO_H
-#define __ASM_CRIS_SWITCH_TO_H
-
-/* the switch_to macro calls resume, an asm function in entry.S which does the actual
- * task switching.
- */
-
-extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int);
-#define switch_to(prev,next,last) last = resume(prev,next, \
- (int)&((struct task_struct *)0)->thread)
-
-#endif /* __ASM_CRIS_SWITCH_TO_H */
diff --git a/arch/cris/include/asm/termios.h b/arch/cris/include/asm/termios.h
deleted file mode 100644
index 9832bf3221d0..000000000000
--- a/arch/cris/include/asm/termios.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_TERMIOS_H
-#define _CRIS_TERMIOS_H
-
-#include <uapi/asm/termios.h>
-
-
-/* intr=^C quit=^\ erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
- unsigned short __tmp; \
- get_user(__tmp,&(termio)->x); \
- *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
- copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- put_user((termios)->c_iflag, &(termio)->c_iflag); \
- put_user((termios)->c_oflag, &(termio)->c_oflag); \
- put_user((termios)->c_cflag, &(termio)->c_cflag); \
- put_user((termios)->c_lflag, &(termio)->c_lflag); \
- put_user((termios)->c_line, &(termio)->c_line); \
- copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* _CRIS_TERMIOS_H */
diff --git a/arch/cris/include/asm/thread_info.h b/arch/cris/include/asm/thread_info.h
deleted file mode 100644
index 996fef3be1d5..000000000000
--- a/arch/cris/include/asm/thread_info.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* thread_info.h: CRIS low-level thread information
- *
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- *
- * CRIS port by Axis Communications
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/processor.h>
-#include <arch/thread_info.h>
-#include <asm/segment.h>
-#endif
-
-
-/* THREAD_SIZE is the size of the thread_info/kernel_stack combo.
- * normally, the stack is found by doing something like p + THREAD_SIZE
- * in CRIS, a page is 8192 bytes, which seems like a sane size
- */
-#define THREAD_SIZE PAGE_SIZE
-#define THREAD_SIZE_ORDER (0)
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- __u32 tls; /* TLS for this thread */
-
- mm_segment_t addr_limit; /* thread address space:
- 0-0xBFFFFFFF for user-thead
- 0-0xFFFFFFFF for kernel-thread
- */
- __u8 supervisor_stack[0];
-};
-
-#endif
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
-#define TIF_MEMDIE 17 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/cris/include/asm/timex.h b/arch/cris/include/asm/timex.h
deleted file mode 100644
index 3840a556612b..000000000000
--- a/arch/cris/include/asm/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/include/asm-cris/timex.h
- *
- * CRIS architecture timex specifications
- */
-
-#ifndef _ASM_CRIS_TIMEX_H
-#define _ASM_CRIS_TIMEX_H
-
-#include <arch/timex.h>
-
-/*
- * We don't have a cycle-counter.. but we do not support SMP anyway where this is
- * used so it does not matter.
- */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- return 0;
-}
-
-#endif
diff --git a/arch/cris/include/asm/tlb.h b/arch/cris/include/asm/tlb.h
deleted file mode 100644
index 1f6a8a67cfda..000000000000
--- a/arch/cris/include/asm/tlb.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_TLB_H
-#define _CRIS_TLB_H
-
-#include <linux/pagemap.h>
-
-#include <arch/tlb.h>
-
-/*
- * cris doesn't need any special per-pte or
- * per-vma handling..
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-#include <asm-generic/tlb.h>
-
-#endif
diff --git a/arch/cris/include/asm/tlbflush.h b/arch/cris/include/asm/tlbflush.h
deleted file mode 100644
index e7cb964536d0..000000000000
--- a/arch/cris/include/asm/tlbflush.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_TLBFLUSH_H
-#define _CRIS_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/processor.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-
-/*
- * TLB flushing (implemented in arch/cris/mm/tlb.c):
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(mm, start, end) flushes a range of pages
- *
- */
-
-extern void __flush_tlb_all(void);
-extern void __flush_tlb_mm(struct mm_struct *mm);
-extern void __flush_tlb_page(struct vm_area_struct *vma,
- unsigned long addr);
-
-#define flush_tlb_all __flush_tlb_all
-#define flush_tlb_mm __flush_tlb_mm
-#define flush_tlb_page __flush_tlb_page
-
-static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
-{
- flush_tlb_mm(vma->vm_mm);
-}
-
-static inline void flush_tlb(void)
-{
- flush_tlb_mm(current->mm);
-}
-
-#define flush_tlb_kernel_range(start, end) flush_tlb_all()
-
-#endif /* _CRIS_TLBFLUSH_H */
diff --git a/arch/cris/include/asm/uaccess.h b/arch/cris/include/asm/uaccess.h
deleted file mode 100644
index 3b42ab0cae93..000000000000
--- a/arch/cris/include/asm/uaccess.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Hans-Peter Nilsson (hp@axis.com)
- */
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
- satisfactory results for "gcc version 2.96 20000427 (experimental)".
-
- Check regularly...
-
- Register $r9 is chosen for temporaries, being a call-clobbered register
- first in line to be used (notably for local blocks), not colliding with
- parameter registers. */
-
-#ifndef _CRIS_UACCESS_H
-#define _CRIS_UACCESS_H
-
-#include <asm/processor.h>
-#include <asm/page.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-/* addr_limit is the maximum accessible address for the task. we misuse
- * the KERNEL_DS and USER_DS values to both assign and compare the
- * addr_limit values through the equally misnamed get/set_fs macros.
- * (see above)
- */
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(TASK_SIZE)
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#define __kernel_ok (uaccess_kernel())
-#define __user_ok(addr, size) \
- (((size) <= TASK_SIZE) && ((addr) <= TASK_SIZE-(size)))
-#define __access_ok(addr, size) (__kernel_ok || __user_ok((addr), (size)))
-#define access_ok(type, addr, size) __access_ok((unsigned long)(addr), (size))
-
-#include <arch/uaccess.h>
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- *
- * As we use the same address space for kernel and user data on
- * CRIS, we can just do these as direct assignments. (Of course, the
- * exception handling means that it's no longer "just"...)
- */
-#define get_user(x, ptr) \
- __get_user_check((x), (ptr), sizeof(*(ptr)))
-#define put_user(x, ptr) \
- __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user(x, ptr) \
- __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __put_user(x, ptr) \
- __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-extern long __put_user_bad(void);
-
-#define __put_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- switch (size) { \
- case 1: \
- __put_user_asm(x, ptr, retval, "move.b"); \
- break; \
- case 2: \
- __put_user_asm(x, ptr, retval, "move.w"); \
- break; \
- case 4: \
- __put_user_asm(x, ptr, retval, "move.d"); \
- break; \
- case 8: \
- __put_user_asm_64(x, ptr, retval); \
- break; \
- default: \
- __put_user_bad(); \
- } \
-} while (0)
-
-#define __get_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- switch (size) { \
- case 1: \
- __get_user_asm(x, ptr, retval, "move.b"); \
- break; \
- case 2: \
- __get_user_asm(x, ptr, retval, "move.w"); \
- break; \
- case 4: \
- __get_user_asm(x, ptr, retval, "move.d"); \
- break; \
- case 8: \
- __get_user_asm_64(x, ptr, retval); \
- break; \
- default: \
- (x) = __get_user_bad(); \
- } \
-} while (0)
-
-#define __put_user_nocheck(x, ptr, size) \
-({ \
- long __pu_err; \
- __put_user_size((x), (ptr), (size), __pu_err); \
- __pu_err; \
-})
-
-#define __put_user_check(x, ptr, size) \
-({ \
- long __pu_err = -EFAULT; \
- __typeof__(*(ptr)) *__pu_addr = (ptr); \
- if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
- __put_user_size((x), __pu_addr, (size), __pu_err); \
- __pu_err; \
-})
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
-
-
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- long __gu_err, __gu_val; \
- __get_user_size(__gu_val, (ptr), (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- long __gu_err = -EFAULT, __gu_val = 0; \
- const __typeof__(*(ptr)) *__gu_addr = (ptr); \
- if (access_ok(VERIFY_READ, __gu_addr, size)) \
- __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-extern long __get_user_bad(void);
-
-/* More complex functions. Most are inline, but some call functions that
- live in lib/usercopy.c */
-
-extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n);
-extern unsigned long __copy_user_in(void *to, const void __user *from, unsigned long n);
-extern unsigned long __do_clear_user(void __user *to, unsigned long n);
-
-static inline long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- long res = -EFAULT;
-
- if (access_ok(VERIFY_READ, src, 1))
- res = __do_strncpy_from_user(dst, src, count);
- return res;
-}
-
-
-/* Note that these expand awfully if made into switch constructs, so
- don't do that. */
-
-static inline unsigned long
-__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- unsigned long ret = 0;
-
- if (n == 0)
- ;
- else if (n == 1)
- __asm_copy_from_user_1(to, from, ret);
- else if (n == 2)
- __asm_copy_from_user_2(to, from, ret);
- else if (n == 3)
- __asm_copy_from_user_3(to, from, ret);
- else if (n == 4)
- __asm_copy_from_user_4(to, from, ret);
- else if (n == 5)
- __asm_copy_from_user_5(to, from, ret);
- else if (n == 6)
- __asm_copy_from_user_6(to, from, ret);
- else if (n == 7)
- __asm_copy_from_user_7(to, from, ret);
- else if (n == 8)
- __asm_copy_from_user_8(to, from, ret);
- else if (n == 9)
- __asm_copy_from_user_9(to, from, ret);
- else if (n == 10)
- __asm_copy_from_user_10(to, from, ret);
- else if (n == 11)
- __asm_copy_from_user_11(to, from, ret);
- else if (n == 12)
- __asm_copy_from_user_12(to, from, ret);
- else if (n == 13)
- __asm_copy_from_user_13(to, from, ret);
- else if (n == 14)
- __asm_copy_from_user_14(to, from, ret);
- else if (n == 15)
- __asm_copy_from_user_15(to, from, ret);
- else if (n == 16)
- __asm_copy_from_user_16(to, from, ret);
- else if (n == 20)
- __asm_copy_from_user_20(to, from, ret);
- else if (n == 24)
- __asm_copy_from_user_24(to, from, ret);
- else
- ret = __copy_user_in(to, from, n);
-
- return ret;
-}
-
-/* Ditto, don't make a switch out of this. */
-
-static inline unsigned long
-__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- unsigned long ret = 0;
-
- if (n == 0)
- ;
- else if (n == 1)
- __asm_copy_to_user_1(to, from, ret);
- else if (n == 2)
- __asm_copy_to_user_2(to, from, ret);
- else if (n == 3)
- __asm_copy_to_user_3(to, from, ret);
- else if (n == 4)
- __asm_copy_to_user_4(to, from, ret);
- else if (n == 5)
- __asm_copy_to_user_5(to, from, ret);
- else if (n == 6)
- __asm_copy_to_user_6(to, from, ret);
- else if (n == 7)
- __asm_copy_to_user_7(to, from, ret);
- else if (n == 8)
- __asm_copy_to_user_8(to, from, ret);
- else if (n == 9)
- __asm_copy_to_user_9(to, from, ret);
- else if (n == 10)
- __asm_copy_to_user_10(to, from, ret);
- else if (n == 11)
- __asm_copy_to_user_11(to, from, ret);
- else if (n == 12)
- __asm_copy_to_user_12(to, from, ret);
- else if (n == 13)
- __asm_copy_to_user_13(to, from, ret);
- else if (n == 14)
- __asm_copy_to_user_14(to, from, ret);
- else if (n == 15)
- __asm_copy_to_user_15(to, from, ret);
- else if (n == 16)
- __asm_copy_to_user_16(to, from, ret);
- else if (n == 20)
- __asm_copy_to_user_20(to, from, ret);
- else if (n == 24)
- __asm_copy_to_user_24(to, from, ret);
- else
- ret = __copy_user(to, from, n);
-
- return ret;
-}
-
-/* No switch, please. */
-
-static inline unsigned long
-__constant_clear_user(void __user *to, unsigned long n)
-{
- unsigned long ret = 0;
-
- if (n == 0)
- ;
- else if (n == 1)
- __asm_clear_1(to, ret);
- else if (n == 2)
- __asm_clear_2(to, ret);
- else if (n == 3)
- __asm_clear_3(to, ret);
- else if (n == 4)
- __asm_clear_4(to, ret);
- else if (n == 8)
- __asm_clear_8(to, ret);
- else if (n == 12)
- __asm_clear_12(to, ret);
- else if (n == 16)
- __asm_clear_16(to, ret);
- else if (n == 20)
- __asm_clear_20(to, ret);
- else if (n == 24)
- __asm_clear_24(to, ret);
- else
- ret = __do_clear_user(to, n);
-
- return ret;
-}
-
-
-static inline size_t clear_user(void __user *to, size_t n)
-{
- if (unlikely(!access_ok(VERIFY_WRITE, to, n)))
- return n;
- if (__builtin_constant_p(n))
- return __constant_clear_user(to, n);
- else
- return __do_clear_user(to, n);
-}
-
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- if (__builtin_constant_p(n))
- return __constant_copy_from_user(to, from, n);
- else
- return __copy_user_in(to, from, n);
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- if (__builtin_constant_p(n))
- return __constant_copy_to_user(to, from, n);
- else
- return __copy_user(to, from, n);
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-
-static inline unsigned long
-__clear_user(void __user *to, unsigned long n)
-{
- return __do_clear_user(to, n);
-}
-
-#endif /* _CRIS_UACCESS_H */
diff --git a/arch/cris/include/asm/ucontext.h b/arch/cris/include/asm/ucontext.h
deleted file mode 100644
index 22f7e7cf59c8..000000000000
--- a/arch/cris/include/asm/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_UCONTEXT_H
-#define _ASM_CRIS_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif /* !_ASM_CRIS_UCONTEXT_H */
diff --git a/arch/cris/include/asm/unaligned.h b/arch/cris/include/asm/unaligned.h
deleted file mode 100644
index 21772cf600dd..000000000000
--- a/arch/cris/include/asm/unaligned.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_UNALIGNED_H
-#define _ASM_CRIS_UNALIGNED_H
-
-/*
- * CRIS can do unaligned accesses itself.
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-
-#endif /* _ASM_CRIS_UNALIGNED_H */
diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h
deleted file mode 100644
index 6a92c0505156..000000000000
--- a/arch/cris/include/asm/unistd.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_UNISTD_H_
-#define _ASM_CRIS_UNISTD_H_
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 365
-
-#include <arch/unistd.h>
-
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLD_MMAP
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-#define __ARCH_WANT_SYS_CLONE
-
-#endif /* _ASM_CRIS_UNISTD_H_ */
diff --git a/arch/cris/include/asm/user.h b/arch/cris/include/asm/user.h
deleted file mode 100644
index a19c39547248..000000000000
--- a/arch/cris/include/asm/user.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_USER_H
-#define __ASM_CRIS_USER_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <arch/user.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd). The file contents are as follows:
- *
- * upage: 1 page consisting of a user struct that tells gdb
- * what is present in the file. Directly after this is a
- * copy of the task_struct, which is currently not used by gdb,
- * but it may come in handy at some point. All of the registers
- * are stored as part of the upage. The upage should always be
- * only one page long.
- * data: The data segment follows next. We use current->end_text to
- * current->brk to pick up all of the user variables, plus any memory
- * that may have been sbrk'ed. No attempt is made to determine if a
- * page is demand-zero or if a page is totally unused, we just cover
- * the entire range. All of the addresses are rounded in such a way
- * that an integral number of pages is written.
- * stack: We need the stack information in order to get a meaningful
- * backtrace. We need to write the data from usp to
- * current->start_stack, so we round each of these in order to be able
- * to write an integer number of pages.
- */
-
-struct user {
- struct user_regs_struct regs; /* entire machine state */
- size_t u_tsize; /* text size (pages) */
- size_t u_dsize; /* data size (pages) */
- size_t u_ssize; /* stack size (pages) */
- unsigned long start_code; /* text starting address */
- unsigned long start_data; /* data starting address */
- unsigned long start_stack; /* stack starting address */
- long int signal; /* signal causing core dump */
- unsigned long u_ar0; /* help gdb find registers */
- unsigned long magic; /* identifies a core file */
- char u_comm[32]; /* user command name */
-};
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_DATA_START_ADDR (u.start_data)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* __ASM_CRIS_USER_H */
diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh b/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh
deleted file mode 100644
index 6ac3a7bc9760..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh
+++ /dev/null
@@ -1,7306 +0,0 @@
-/*
-!* This file was automatically generated by /n/asic/bin/reg_macro_gen
-!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'.
-!* Editing within this file is thus not recommended,
-!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
-!*/
-
-
-/*
-!* Bus interface configuration registers
-!*/
-
-#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000)
-#define R_WAITSTATES__pcs4_7_zw__BITNR 30
-#define R_WAITSTATES__pcs4_7_zw__WIDTH 2
-#define R_WAITSTATES__pcs4_7_ew__BITNR 28
-#define R_WAITSTATES__pcs4_7_ew__WIDTH 2
-#define R_WAITSTATES__pcs4_7_lw__BITNR 24
-#define R_WAITSTATES__pcs4_7_lw__WIDTH 4
-#define R_WAITSTATES__pcs0_3_zw__BITNR 22
-#define R_WAITSTATES__pcs0_3_zw__WIDTH 2
-#define R_WAITSTATES__pcs0_3_ew__BITNR 20
-#define R_WAITSTATES__pcs0_3_ew__WIDTH 2
-#define R_WAITSTATES__pcs0_3_lw__BITNR 16
-#define R_WAITSTATES__pcs0_3_lw__WIDTH 4
-#define R_WAITSTATES__sram_zw__BITNR 14
-#define R_WAITSTATES__sram_zw__WIDTH 2
-#define R_WAITSTATES__sram_ew__BITNR 12
-#define R_WAITSTATES__sram_ew__WIDTH 2
-#define R_WAITSTATES__sram_lw__BITNR 8
-#define R_WAITSTATES__sram_lw__WIDTH 4
-#define R_WAITSTATES__flash_zw__BITNR 6
-#define R_WAITSTATES__flash_zw__WIDTH 2
-#define R_WAITSTATES__flash_ew__BITNR 4
-#define R_WAITSTATES__flash_ew__WIDTH 2
-#define R_WAITSTATES__flash_lw__BITNR 0
-#define R_WAITSTATES__flash_lw__WIDTH 4
-
-#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004)
-#define R_BUS_CONFIG__sram_type__BITNR 9
-#define R_BUS_CONFIG__sram_type__WIDTH 1
-#define R_BUS_CONFIG__sram_type__cwe 1
-#define R_BUS_CONFIG__sram_type__bwe 0
-#define R_BUS_CONFIG__dma_burst__BITNR 8
-#define R_BUS_CONFIG__dma_burst__WIDTH 1
-#define R_BUS_CONFIG__dma_burst__burst16 1
-#define R_BUS_CONFIG__dma_burst__burst32 0
-#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
-#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1
-#define R_BUS_CONFIG__pcs4_7_wr__ext 1
-#define R_BUS_CONFIG__pcs4_7_wr__norm 0
-#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
-#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1
-#define R_BUS_CONFIG__pcs0_3_wr__ext 1
-#define R_BUS_CONFIG__pcs0_3_wr__norm 0
-#define R_BUS_CONFIG__sram_wr__BITNR 5
-#define R_BUS_CONFIG__sram_wr__WIDTH 1
-#define R_BUS_CONFIG__sram_wr__ext 1
-#define R_BUS_CONFIG__sram_wr__norm 0
-#define R_BUS_CONFIG__flash_wr__BITNR 4
-#define R_BUS_CONFIG__flash_wr__WIDTH 1
-#define R_BUS_CONFIG__flash_wr__ext 1
-#define R_BUS_CONFIG__flash_wr__norm 0
-#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
-#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1
-#define R_BUS_CONFIG__pcs4_7_bw__bw32 1
-#define R_BUS_CONFIG__pcs4_7_bw__bw16 0
-#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
-#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1
-#define R_BUS_CONFIG__pcs0_3_bw__bw32 1
-#define R_BUS_CONFIG__pcs0_3_bw__bw16 0
-#define R_BUS_CONFIG__sram_bw__BITNR 1
-#define R_BUS_CONFIG__sram_bw__WIDTH 1
-#define R_BUS_CONFIG__sram_bw__bw32 1
-#define R_BUS_CONFIG__sram_bw__bw16 0
-#define R_BUS_CONFIG__flash_bw__BITNR 0
-#define R_BUS_CONFIG__flash_bw__WIDTH 1
-#define R_BUS_CONFIG__flash_bw__bw32 1
-#define R_BUS_CONFIG__flash_bw__bw16 0
-
-#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004)
-#define R_BUS_STATUS__pll_lock_tm__BITNR 5
-#define R_BUS_STATUS__pll_lock_tm__WIDTH 1
-#define R_BUS_STATUS__pll_lock_tm__expired 0
-#define R_BUS_STATUS__pll_lock_tm__counting 1
-#define R_BUS_STATUS__both_faults__BITNR 4
-#define R_BUS_STATUS__both_faults__WIDTH 1
-#define R_BUS_STATUS__both_faults__no 0
-#define R_BUS_STATUS__both_faults__yes 1
-#define R_BUS_STATUS__bsen___BITNR 3
-#define R_BUS_STATUS__bsen___WIDTH 1
-#define R_BUS_STATUS__bsen___enable 0
-#define R_BUS_STATUS__bsen___disable 1
-#define R_BUS_STATUS__boot__BITNR 1
-#define R_BUS_STATUS__boot__WIDTH 2
-#define R_BUS_STATUS__boot__uncached 0
-#define R_BUS_STATUS__boot__serial 1
-#define R_BUS_STATUS__boot__network 2
-#define R_BUS_STATUS__boot__parallel 3
-#define R_BUS_STATUS__flashw__BITNR 0
-#define R_BUS_STATUS__flashw__WIDTH 1
-#define R_BUS_STATUS__flashw__bw32 1
-#define R_BUS_STATUS__flashw__bw16 0
-
-#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
-#define R_DRAM_TIMING__sdram__BITNR 31
-#define R_DRAM_TIMING__sdram__WIDTH 1
-#define R_DRAM_TIMING__sdram__enable 1
-#define R_DRAM_TIMING__sdram__disable 0
-#define R_DRAM_TIMING__ref__BITNR 14
-#define R_DRAM_TIMING__ref__WIDTH 2
-#define R_DRAM_TIMING__ref__e52us 0
-#define R_DRAM_TIMING__ref__e13us 1
-#define R_DRAM_TIMING__ref__e8700ns 2
-#define R_DRAM_TIMING__ref__disable 3
-#define R_DRAM_TIMING__rp__BITNR 12
-#define R_DRAM_TIMING__rp__WIDTH 2
-#define R_DRAM_TIMING__rs__BITNR 10
-#define R_DRAM_TIMING__rs__WIDTH 2
-#define R_DRAM_TIMING__rh__BITNR 8
-#define R_DRAM_TIMING__rh__WIDTH 2
-#define R_DRAM_TIMING__w__BITNR 7
-#define R_DRAM_TIMING__w__WIDTH 1
-#define R_DRAM_TIMING__w__norm 0
-#define R_DRAM_TIMING__w__ext 1
-#define R_DRAM_TIMING__c__BITNR 6
-#define R_DRAM_TIMING__c__WIDTH 1
-#define R_DRAM_TIMING__c__norm 0
-#define R_DRAM_TIMING__c__ext 1
-#define R_DRAM_TIMING__cz__BITNR 4
-#define R_DRAM_TIMING__cz__WIDTH 2
-#define R_DRAM_TIMING__cp__BITNR 2
-#define R_DRAM_TIMING__cp__WIDTH 2
-#define R_DRAM_TIMING__cw__BITNR 0
-#define R_DRAM_TIMING__cw__WIDTH 2
-
-#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
-#define R_SDRAM_TIMING__sdram__BITNR 31
-#define R_SDRAM_TIMING__sdram__WIDTH 1
-#define R_SDRAM_TIMING__sdram__enable 1
-#define R_SDRAM_TIMING__sdram__disable 0
-#define R_SDRAM_TIMING__mrs_data__BITNR 16
-#define R_SDRAM_TIMING__mrs_data__WIDTH 15
-#define R_SDRAM_TIMING__ref__BITNR 14
-#define R_SDRAM_TIMING__ref__WIDTH 2
-#define R_SDRAM_TIMING__ref__e52us 0
-#define R_SDRAM_TIMING__ref__e13us 1
-#define R_SDRAM_TIMING__ref__e6500ns 2
-#define R_SDRAM_TIMING__ref__disable 3
-#define R_SDRAM_TIMING__ddr__BITNR 13
-#define R_SDRAM_TIMING__ddr__WIDTH 1
-#define R_SDRAM_TIMING__ddr__on 1
-#define R_SDRAM_TIMING__ddr__off 0
-#define R_SDRAM_TIMING__clk100__BITNR 12
-#define R_SDRAM_TIMING__clk100__WIDTH 1
-#define R_SDRAM_TIMING__clk100__on 1
-#define R_SDRAM_TIMING__clk100__off 0
-#define R_SDRAM_TIMING__ps__BITNR 11
-#define R_SDRAM_TIMING__ps__WIDTH 1
-#define R_SDRAM_TIMING__ps__on 1
-#define R_SDRAM_TIMING__ps__off 0
-#define R_SDRAM_TIMING__cmd__BITNR 9
-#define R_SDRAM_TIMING__cmd__WIDTH 2
-#define R_SDRAM_TIMING__cmd__pre 3
-#define R_SDRAM_TIMING__cmd__ref 2
-#define R_SDRAM_TIMING__cmd__mrs 1
-#define R_SDRAM_TIMING__cmd__nop 0
-#define R_SDRAM_TIMING__pde__BITNR 8
-#define R_SDRAM_TIMING__pde__WIDTH 1
-#define R_SDRAM_TIMING__rc__BITNR 6
-#define R_SDRAM_TIMING__rc__WIDTH 2
-#define R_SDRAM_TIMING__rp__BITNR 4
-#define R_SDRAM_TIMING__rp__WIDTH 2
-#define R_SDRAM_TIMING__rcd__BITNR 2
-#define R_SDRAM_TIMING__rcd__WIDTH 2
-#define R_SDRAM_TIMING__cl__BITNR 0
-#define R_SDRAM_TIMING__cl__WIDTH 2
-
-#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
-#define R_DRAM_CONFIG__wmm1__BITNR 31
-#define R_DRAM_CONFIG__wmm1__WIDTH 1
-#define R_DRAM_CONFIG__wmm1__wmm 1
-#define R_DRAM_CONFIG__wmm1__norm 0
-#define R_DRAM_CONFIG__wmm0__BITNR 30
-#define R_DRAM_CONFIG__wmm0__WIDTH 1
-#define R_DRAM_CONFIG__wmm0__wmm 1
-#define R_DRAM_CONFIG__wmm0__norm 0
-#define R_DRAM_CONFIG__sh1__BITNR 27
-#define R_DRAM_CONFIG__sh1__WIDTH 3
-#define R_DRAM_CONFIG__sh0__BITNR 24
-#define R_DRAM_CONFIG__sh0__WIDTH 3
-#define R_DRAM_CONFIG__w__BITNR 23
-#define R_DRAM_CONFIG__w__WIDTH 1
-#define R_DRAM_CONFIG__w__bw16 0
-#define R_DRAM_CONFIG__w__bw32 1
-#define R_DRAM_CONFIG__c__BITNR 22
-#define R_DRAM_CONFIG__c__WIDTH 1
-#define R_DRAM_CONFIG__c__byte 0
-#define R_DRAM_CONFIG__c__bank 1
-#define R_DRAM_CONFIG__e__BITNR 21
-#define R_DRAM_CONFIG__e__WIDTH 1
-#define R_DRAM_CONFIG__e__fast 0
-#define R_DRAM_CONFIG__e__edo 1
-#define R_DRAM_CONFIG__group_sel__BITNR 16
-#define R_DRAM_CONFIG__group_sel__WIDTH 5
-#define R_DRAM_CONFIG__group_sel__grp0 0
-#define R_DRAM_CONFIG__group_sel__grp1 1
-#define R_DRAM_CONFIG__group_sel__bit9 9
-#define R_DRAM_CONFIG__group_sel__bit10 10
-#define R_DRAM_CONFIG__group_sel__bit11 11
-#define R_DRAM_CONFIG__group_sel__bit12 12
-#define R_DRAM_CONFIG__group_sel__bit13 13
-#define R_DRAM_CONFIG__group_sel__bit14 14
-#define R_DRAM_CONFIG__group_sel__bit15 15
-#define R_DRAM_CONFIG__group_sel__bit16 16
-#define R_DRAM_CONFIG__group_sel__bit17 17
-#define R_DRAM_CONFIG__group_sel__bit18 18
-#define R_DRAM_CONFIG__group_sel__bit19 19
-#define R_DRAM_CONFIG__group_sel__bit20 20
-#define R_DRAM_CONFIG__group_sel__bit21 21
-#define R_DRAM_CONFIG__group_sel__bit22 22
-#define R_DRAM_CONFIG__group_sel__bit23 23
-#define R_DRAM_CONFIG__group_sel__bit24 24
-#define R_DRAM_CONFIG__group_sel__bit25 25
-#define R_DRAM_CONFIG__group_sel__bit26 26
-#define R_DRAM_CONFIG__group_sel__bit27 27
-#define R_DRAM_CONFIG__group_sel__bit28 28
-#define R_DRAM_CONFIG__group_sel__bit29 29
-#define R_DRAM_CONFIG__ca1__BITNR 13
-#define R_DRAM_CONFIG__ca1__WIDTH 3
-#define R_DRAM_CONFIG__bank23sel__BITNR 8
-#define R_DRAM_CONFIG__bank23sel__WIDTH 5
-#define R_DRAM_CONFIG__bank23sel__bank0 0
-#define R_DRAM_CONFIG__bank23sel__bank1 1
-#define R_DRAM_CONFIG__bank23sel__bit9 9
-#define R_DRAM_CONFIG__bank23sel__bit10 10
-#define R_DRAM_CONFIG__bank23sel__bit11 11
-#define R_DRAM_CONFIG__bank23sel__bit12 12
-#define R_DRAM_CONFIG__bank23sel__bit13 13
-#define R_DRAM_CONFIG__bank23sel__bit14 14
-#define R_DRAM_CONFIG__bank23sel__bit15 15
-#define R_DRAM_CONFIG__bank23sel__bit16 16
-#define R_DRAM_CONFIG__bank23sel__bit17 17
-#define R_DRAM_CONFIG__bank23sel__bit18 18
-#define R_DRAM_CONFIG__bank23sel__bit19 19
-#define R_DRAM_CONFIG__bank23sel__bit20 20
-#define R_DRAM_CONFIG__bank23sel__bit21 21
-#define R_DRAM_CONFIG__bank23sel__bit22 22
-#define R_DRAM_CONFIG__bank23sel__bit23 23
-#define R_DRAM_CONFIG__bank23sel__bit24 24
-#define R_DRAM_CONFIG__bank23sel__bit25 25
-#define R_DRAM_CONFIG__bank23sel__bit26 26
-#define R_DRAM_CONFIG__bank23sel__bit27 27
-#define R_DRAM_CONFIG__bank23sel__bit28 28
-#define R_DRAM_CONFIG__bank23sel__bit29 29
-#define R_DRAM_CONFIG__ca0__BITNR 5
-#define R_DRAM_CONFIG__ca0__WIDTH 3
-#define R_DRAM_CONFIG__bank01sel__BITNR 0
-#define R_DRAM_CONFIG__bank01sel__WIDTH 5
-#define R_DRAM_CONFIG__bank01sel__bank0 0
-#define R_DRAM_CONFIG__bank01sel__bank1 1
-#define R_DRAM_CONFIG__bank01sel__bit9 9
-#define R_DRAM_CONFIG__bank01sel__bit10 10
-#define R_DRAM_CONFIG__bank01sel__bit11 11
-#define R_DRAM_CONFIG__bank01sel__bit12 12
-#define R_DRAM_CONFIG__bank01sel__bit13 13
-#define R_DRAM_CONFIG__bank01sel__bit14 14
-#define R_DRAM_CONFIG__bank01sel__bit15 15
-#define R_DRAM_CONFIG__bank01sel__bit16 16
-#define R_DRAM_CONFIG__bank01sel__bit17 17
-#define R_DRAM_CONFIG__bank01sel__bit18 18
-#define R_DRAM_CONFIG__bank01sel__bit19 19
-#define R_DRAM_CONFIG__bank01sel__bit20 20
-#define R_DRAM_CONFIG__bank01sel__bit21 21
-#define R_DRAM_CONFIG__bank01sel__bit22 22
-#define R_DRAM_CONFIG__bank01sel__bit23 23
-#define R_DRAM_CONFIG__bank01sel__bit24 24
-#define R_DRAM_CONFIG__bank01sel__bit25 25
-#define R_DRAM_CONFIG__bank01sel__bit26 26
-#define R_DRAM_CONFIG__bank01sel__bit27 27
-#define R_DRAM_CONFIG__bank01sel__bit28 28
-#define R_DRAM_CONFIG__bank01sel__bit29 29
-
-#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
-#define R_SDRAM_CONFIG__wmm1__BITNR 31
-#define R_SDRAM_CONFIG__wmm1__WIDTH 1
-#define R_SDRAM_CONFIG__wmm1__wmm 1
-#define R_SDRAM_CONFIG__wmm1__norm 0
-#define R_SDRAM_CONFIG__wmm0__BITNR 30
-#define R_SDRAM_CONFIG__wmm0__WIDTH 1
-#define R_SDRAM_CONFIG__wmm0__wmm 1
-#define R_SDRAM_CONFIG__wmm0__norm 0
-#define R_SDRAM_CONFIG__sh1__BITNR 27
-#define R_SDRAM_CONFIG__sh1__WIDTH 3
-#define R_SDRAM_CONFIG__sh0__BITNR 24
-#define R_SDRAM_CONFIG__sh0__WIDTH 3
-#define R_SDRAM_CONFIG__w__BITNR 23
-#define R_SDRAM_CONFIG__w__WIDTH 1
-#define R_SDRAM_CONFIG__w__bw16 0
-#define R_SDRAM_CONFIG__w__bw32 1
-#define R_SDRAM_CONFIG__type1__BITNR 22
-#define R_SDRAM_CONFIG__type1__WIDTH 1
-#define R_SDRAM_CONFIG__type1__bank2 0
-#define R_SDRAM_CONFIG__type1__bank4 1
-#define R_SDRAM_CONFIG__type0__BITNR 21
-#define R_SDRAM_CONFIG__type0__WIDTH 1
-#define R_SDRAM_CONFIG__type0__bank2 0
-#define R_SDRAM_CONFIG__type0__bank4 1
-#define R_SDRAM_CONFIG__group_sel__BITNR 16
-#define R_SDRAM_CONFIG__group_sel__WIDTH 5
-#define R_SDRAM_CONFIG__group_sel__grp0 0
-#define R_SDRAM_CONFIG__group_sel__grp1 1
-#define R_SDRAM_CONFIG__group_sel__bit9 9
-#define R_SDRAM_CONFIG__group_sel__bit10 10
-#define R_SDRAM_CONFIG__group_sel__bit11 11
-#define R_SDRAM_CONFIG__group_sel__bit12 12
-#define R_SDRAM_CONFIG__group_sel__bit13 13
-#define R_SDRAM_CONFIG__group_sel__bit14 14
-#define R_SDRAM_CONFIG__group_sel__bit15 15
-#define R_SDRAM_CONFIG__group_sel__bit16 16
-#define R_SDRAM_CONFIG__group_sel__bit17 17
-#define R_SDRAM_CONFIG__group_sel__bit18 18
-#define R_SDRAM_CONFIG__group_sel__bit19 19
-#define R_SDRAM_CONFIG__group_sel__bit20 20
-#define R_SDRAM_CONFIG__group_sel__bit21 21
-#define R_SDRAM_CONFIG__group_sel__bit22 22
-#define R_SDRAM_CONFIG__group_sel__bit23 23
-#define R_SDRAM_CONFIG__group_sel__bit24 24
-#define R_SDRAM_CONFIG__group_sel__bit25 25
-#define R_SDRAM_CONFIG__group_sel__bit26 26
-#define R_SDRAM_CONFIG__group_sel__bit27 27
-#define R_SDRAM_CONFIG__group_sel__bit28 28
-#define R_SDRAM_CONFIG__group_sel__bit29 29
-#define R_SDRAM_CONFIG__ca1__BITNR 13
-#define R_SDRAM_CONFIG__ca1__WIDTH 3
-#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
-#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5
-#define R_SDRAM_CONFIG__bank_sel1__bit9 9
-#define R_SDRAM_CONFIG__bank_sel1__bit10 10
-#define R_SDRAM_CONFIG__bank_sel1__bit11 11
-#define R_SDRAM_CONFIG__bank_sel1__bit12 12
-#define R_SDRAM_CONFIG__bank_sel1__bit13 13
-#define R_SDRAM_CONFIG__bank_sel1__bit14 14
-#define R_SDRAM_CONFIG__bank_sel1__bit15 15
-#define R_SDRAM_CONFIG__bank_sel1__bit16 16
-#define R_SDRAM_CONFIG__bank_sel1__bit17 17
-#define R_SDRAM_CONFIG__bank_sel1__bit18 18
-#define R_SDRAM_CONFIG__bank_sel1__bit19 19
-#define R_SDRAM_CONFIG__bank_sel1__bit20 20
-#define R_SDRAM_CONFIG__bank_sel1__bit21 21
-#define R_SDRAM_CONFIG__bank_sel1__bit22 22
-#define R_SDRAM_CONFIG__bank_sel1__bit23 23
-#define R_SDRAM_CONFIG__bank_sel1__bit24 24
-#define R_SDRAM_CONFIG__bank_sel1__bit25 25
-#define R_SDRAM_CONFIG__bank_sel1__bit26 26
-#define R_SDRAM_CONFIG__bank_sel1__bit27 27
-#define R_SDRAM_CONFIG__bank_sel1__bit28 28
-#define R_SDRAM_CONFIG__bank_sel1__bit29 29
-#define R_SDRAM_CONFIG__ca0__BITNR 5
-#define R_SDRAM_CONFIG__ca0__WIDTH 3
-#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
-#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5
-#define R_SDRAM_CONFIG__bank_sel0__bit9 9
-#define R_SDRAM_CONFIG__bank_sel0__bit10 10
-#define R_SDRAM_CONFIG__bank_sel0__bit11 11
-#define R_SDRAM_CONFIG__bank_sel0__bit12 12
-#define R_SDRAM_CONFIG__bank_sel0__bit13 13
-#define R_SDRAM_CONFIG__bank_sel0__bit14 14
-#define R_SDRAM_CONFIG__bank_sel0__bit15 15
-#define R_SDRAM_CONFIG__bank_sel0__bit16 16
-#define R_SDRAM_CONFIG__bank_sel0__bit17 17
-#define R_SDRAM_CONFIG__bank_sel0__bit18 18
-#define R_SDRAM_CONFIG__bank_sel0__bit19 19
-#define R_SDRAM_CONFIG__bank_sel0__bit20 20
-#define R_SDRAM_CONFIG__bank_sel0__bit21 21
-#define R_SDRAM_CONFIG__bank_sel0__bit22 22
-#define R_SDRAM_CONFIG__bank_sel0__bit23 23
-#define R_SDRAM_CONFIG__bank_sel0__bit24 24
-#define R_SDRAM_CONFIG__bank_sel0__bit25 25
-#define R_SDRAM_CONFIG__bank_sel0__bit26 26
-#define R_SDRAM_CONFIG__bank_sel0__bit27 27
-#define R_SDRAM_CONFIG__bank_sel0__bit28 28
-#define R_SDRAM_CONFIG__bank_sel0__bit29 29
-
-/*
-!* External DMA registers
-!*/
-
-#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010)
-#define R_EXT_DMA_0_CMD__cnt__BITNR 23
-#define R_EXT_DMA_0_CMD__cnt__WIDTH 1
-#define R_EXT_DMA_0_CMD__cnt__enable 1
-#define R_EXT_DMA_0_CMD__cnt__disable 0
-#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
-#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1
-#define R_EXT_DMA_0_CMD__rqpol__ahigh 0
-#define R_EXT_DMA_0_CMD__rqpol__alow 1
-#define R_EXT_DMA_0_CMD__apol__BITNR 21
-#define R_EXT_DMA_0_CMD__apol__WIDTH 1
-#define R_EXT_DMA_0_CMD__apol__ahigh 0
-#define R_EXT_DMA_0_CMD__apol__alow 1
-#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
-#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1
-#define R_EXT_DMA_0_CMD__rq_ack__burst 0
-#define R_EXT_DMA_0_CMD__rq_ack__handsh 1
-#define R_EXT_DMA_0_CMD__wid__BITNR 18
-#define R_EXT_DMA_0_CMD__wid__WIDTH 2
-#define R_EXT_DMA_0_CMD__wid__byte 0
-#define R_EXT_DMA_0_CMD__wid__word 1
-#define R_EXT_DMA_0_CMD__wid__dword 2
-#define R_EXT_DMA_0_CMD__dir__BITNR 17
-#define R_EXT_DMA_0_CMD__dir__WIDTH 1
-#define R_EXT_DMA_0_CMD__dir__input 0
-#define R_EXT_DMA_0_CMD__dir__output 1
-#define R_EXT_DMA_0_CMD__run__BITNR 16
-#define R_EXT_DMA_0_CMD__run__WIDTH 1
-#define R_EXT_DMA_0_CMD__run__start 1
-#define R_EXT_DMA_0_CMD__run__stop 0
-#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
-#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16
-
-#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010)
-#define R_EXT_DMA_0_STAT__run__BITNR 16
-#define R_EXT_DMA_0_STAT__run__WIDTH 1
-#define R_EXT_DMA_0_STAT__run__start 1
-#define R_EXT_DMA_0_STAT__run__stop 0
-#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
-#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16
-
-#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014)
-#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
-#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28
-
-#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018)
-#define R_EXT_DMA_1_CMD__cnt__BITNR 23
-#define R_EXT_DMA_1_CMD__cnt__WIDTH 1
-#define R_EXT_DMA_1_CMD__cnt__enable 1
-#define R_EXT_DMA_1_CMD__cnt__disable 0
-#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
-#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1
-#define R_EXT_DMA_1_CMD__rqpol__ahigh 0
-#define R_EXT_DMA_1_CMD__rqpol__alow 1
-#define R_EXT_DMA_1_CMD__apol__BITNR 21
-#define R_EXT_DMA_1_CMD__apol__WIDTH 1
-#define R_EXT_DMA_1_CMD__apol__ahigh 0
-#define R_EXT_DMA_1_CMD__apol__alow 1
-#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
-#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1
-#define R_EXT_DMA_1_CMD__rq_ack__burst 0
-#define R_EXT_DMA_1_CMD__rq_ack__handsh 1
-#define R_EXT_DMA_1_CMD__wid__BITNR 18
-#define R_EXT_DMA_1_CMD__wid__WIDTH 2
-#define R_EXT_DMA_1_CMD__wid__byte 0
-#define R_EXT_DMA_1_CMD__wid__word 1
-#define R_EXT_DMA_1_CMD__wid__dword 2
-#define R_EXT_DMA_1_CMD__dir__BITNR 17
-#define R_EXT_DMA_1_CMD__dir__WIDTH 1
-#define R_EXT_DMA_1_CMD__dir__input 0
-#define R_EXT_DMA_1_CMD__dir__output 1
-#define R_EXT_DMA_1_CMD__run__BITNR 16
-#define R_EXT_DMA_1_CMD__run__WIDTH 1
-#define R_EXT_DMA_1_CMD__run__start 1
-#define R_EXT_DMA_1_CMD__run__stop 0
-#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
-#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16
-
-#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018)
-#define R_EXT_DMA_1_STAT__run__BITNR 16
-#define R_EXT_DMA_1_STAT__run__WIDTH 1
-#define R_EXT_DMA_1_STAT__run__start 1
-#define R_EXT_DMA_1_STAT__run__stop 0
-#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
-#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16
-
-#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c)
-#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
-#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28
-
-/*
-!* Timer registers
-!*/
-
-#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020)
-#define R_TIMER_CTRL__timerdiv1__BITNR 24
-#define R_TIMER_CTRL__timerdiv1__WIDTH 8
-#define R_TIMER_CTRL__timerdiv0__BITNR 16
-#define R_TIMER_CTRL__timerdiv0__WIDTH 8
-#define R_TIMER_CTRL__presc_timer1__BITNR 15
-#define R_TIMER_CTRL__presc_timer1__WIDTH 1
-#define R_TIMER_CTRL__presc_timer1__normal 0
-#define R_TIMER_CTRL__presc_timer1__prescale 1
-#define R_TIMER_CTRL__i1__BITNR 14
-#define R_TIMER_CTRL__i1__WIDTH 1
-#define R_TIMER_CTRL__i1__clr 1
-#define R_TIMER_CTRL__i1__nop 0
-#define R_TIMER_CTRL__tm1__BITNR 12
-#define R_TIMER_CTRL__tm1__WIDTH 2
-#define R_TIMER_CTRL__tm1__stop_ld 0
-#define R_TIMER_CTRL__tm1__freeze 1
-#define R_TIMER_CTRL__tm1__run 2
-#define R_TIMER_CTRL__tm1__reserved 3
-#define R_TIMER_CTRL__clksel1__BITNR 8
-#define R_TIMER_CTRL__clksel1__WIDTH 4
-#define R_TIMER_CTRL__clksel1__c300Hz 0
-#define R_TIMER_CTRL__clksel1__c600Hz 1
-#define R_TIMER_CTRL__clksel1__c1200Hz 2
-#define R_TIMER_CTRL__clksel1__c2400Hz 3
-#define R_TIMER_CTRL__clksel1__c4800Hz 4
-#define R_TIMER_CTRL__clksel1__c9600Hz 5
-#define R_TIMER_CTRL__clksel1__c19k2Hz 6
-#define R_TIMER_CTRL__clksel1__c38k4Hz 7
-#define R_TIMER_CTRL__clksel1__c57k6Hz 8
-#define R_TIMER_CTRL__clksel1__c115k2Hz 9
-#define R_TIMER_CTRL__clksel1__c230k4Hz 10
-#define R_TIMER_CTRL__clksel1__c460k8Hz 11
-#define R_TIMER_CTRL__clksel1__c921k6Hz 12
-#define R_TIMER_CTRL__clksel1__c1843k2Hz 13
-#define R_TIMER_CTRL__clksel1__c6250kHz 14
-#define R_TIMER_CTRL__clksel1__cascade0 15
-#define R_TIMER_CTRL__presc_ext__BITNR 7
-#define R_TIMER_CTRL__presc_ext__WIDTH 1
-#define R_TIMER_CTRL__presc_ext__prescale 0
-#define R_TIMER_CTRL__presc_ext__external 1
-#define R_TIMER_CTRL__i0__BITNR 6
-#define R_TIMER_CTRL__i0__WIDTH 1
-#define R_TIMER_CTRL__i0__clr 1
-#define R_TIMER_CTRL__i0__nop 0
-#define R_TIMER_CTRL__tm0__BITNR 4
-#define R_TIMER_CTRL__tm0__WIDTH 2
-#define R_TIMER_CTRL__tm0__stop_ld 0
-#define R_TIMER_CTRL__tm0__freeze 1
-#define R_TIMER_CTRL__tm0__run 2
-#define R_TIMER_CTRL__tm0__reserved 3
-#define R_TIMER_CTRL__clksel0__BITNR 0
-#define R_TIMER_CTRL__clksel0__WIDTH 4
-#define R_TIMER_CTRL__clksel0__c300Hz 0
-#define R_TIMER_CTRL__clksel0__c600Hz 1
-#define R_TIMER_CTRL__clksel0__c1200Hz 2
-#define R_TIMER_CTRL__clksel0__c2400Hz 3
-#define R_TIMER_CTRL__clksel0__c4800Hz 4
-#define R_TIMER_CTRL__clksel0__c9600Hz 5
-#define R_TIMER_CTRL__clksel0__c19k2Hz 6
-#define R_TIMER_CTRL__clksel0__c38k4Hz 7
-#define R_TIMER_CTRL__clksel0__c57k6Hz 8
-#define R_TIMER_CTRL__clksel0__c115k2Hz 9
-#define R_TIMER_CTRL__clksel0__c230k4Hz 10
-#define R_TIMER_CTRL__clksel0__c460k8Hz 11
-#define R_TIMER_CTRL__clksel0__c921k6Hz 12
-#define R_TIMER_CTRL__clksel0__c1843k2Hz 13
-#define R_TIMER_CTRL__clksel0__c6250kHz 14
-#define R_TIMER_CTRL__clksel0__flexible 15
-
-#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020)
-#define R_TIMER_DATA__timer1__BITNR 24
-#define R_TIMER_DATA__timer1__WIDTH 8
-#define R_TIMER_DATA__timer0__BITNR 16
-#define R_TIMER_DATA__timer0__WIDTH 8
-#define R_TIMER_DATA__clkdiv_high__BITNR 8
-#define R_TIMER_DATA__clkdiv_high__WIDTH 8
-#define R_TIMER_DATA__clkdiv_low__BITNR 0
-#define R_TIMER_DATA__clkdiv_low__WIDTH 8
-
-#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022)
-#define R_TIMER01_DATA__count__BITNR 0
-#define R_TIMER01_DATA__count__WIDTH 16
-
-#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022)
-#define R_TIMER0_DATA__count__BITNR 0
-#define R_TIMER0_DATA__count__WIDTH 8
-
-#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023)
-#define R_TIMER1_DATA__count__BITNR 0
-#define R_TIMER1_DATA__count__WIDTH 8
-
-#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024)
-#define R_WATCHDOG__key__BITNR 1
-#define R_WATCHDOG__key__WIDTH 3
-#define R_WATCHDOG__enable__BITNR 0
-#define R_WATCHDOG__enable__WIDTH 1
-#define R_WATCHDOG__enable__stop 0
-#define R_WATCHDOG__enable__start 1
-
-#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0)
-#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
-#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16
-#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
-#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16
-
-#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2)
-#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
-#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16
-
-#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0)
-#define R_TIMER_PRESCALE__tim_presc__BITNR 0
-#define R_TIMER_PRESCALE__tim_presc__WIDTH 16
-
-#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0)
-#define R_PRESCALE_STATUS__ser_status__BITNR 16
-#define R_PRESCALE_STATUS__ser_status__WIDTH 16
-#define R_PRESCALE_STATUS__tim_status__BITNR 0
-#define R_PRESCALE_STATUS__tim_status__WIDTH 16
-
-#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2)
-#define R_SER_PRESC_STATUS__ser_status__BITNR 0
-#define R_SER_PRESC_STATUS__ser_status__WIDTH 16
-
-#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0)
-#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
-#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16
-
-#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4)
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1
-#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
-#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1
-#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
-#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4
-#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
-#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10
-
-/*
-!* Shared RAM interface registers
-!*/
-
-#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_SHARED_RAM_CONFIG__width__BITNR 3
-#define R_SHARED_RAM_CONFIG__width__WIDTH 1
-#define R_SHARED_RAM_CONFIG__width__byte 0
-#define R_SHARED_RAM_CONFIG__width__word 1
-#define R_SHARED_RAM_CONFIG__enable__BITNR 2
-#define R_SHARED_RAM_CONFIG__enable__WIDTH 1
-#define R_SHARED_RAM_CONFIG__enable__yes 1
-#define R_SHARED_RAM_CONFIG__enable__no 0
-#define R_SHARED_RAM_CONFIG__pint__BITNR 1
-#define R_SHARED_RAM_CONFIG__pint__WIDTH 1
-#define R_SHARED_RAM_CONFIG__pint__int 1
-#define R_SHARED_RAM_CONFIG__pint__nop 0
-#define R_SHARED_RAM_CONFIG__clri__BITNR 0
-#define R_SHARED_RAM_CONFIG__clri__WIDTH 1
-#define R_SHARED_RAM_CONFIG__clri__clr 1
-#define R_SHARED_RAM_CONFIG__clri__nop 0
-
-#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
-#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22
-
-/*
-!* General config registers
-!*/
-
-#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c)
-#define R_GEN_CONFIG__par_w__BITNR 31
-#define R_GEN_CONFIG__par_w__WIDTH 1
-#define R_GEN_CONFIG__par_w__select 1
-#define R_GEN_CONFIG__par_w__disable 0
-#define R_GEN_CONFIG__usb2__BITNR 30
-#define R_GEN_CONFIG__usb2__WIDTH 1
-#define R_GEN_CONFIG__usb2__select 1
-#define R_GEN_CONFIG__usb2__disable 0
-#define R_GEN_CONFIG__usb1__BITNR 29
-#define R_GEN_CONFIG__usb1__WIDTH 1
-#define R_GEN_CONFIG__usb1__select 1
-#define R_GEN_CONFIG__usb1__disable 0
-#define R_GEN_CONFIG__g24dir__BITNR 27
-#define R_GEN_CONFIG__g24dir__WIDTH 1
-#define R_GEN_CONFIG__g24dir__in 0
-#define R_GEN_CONFIG__g24dir__out 1
-#define R_GEN_CONFIG__g16_23dir__BITNR 26
-#define R_GEN_CONFIG__g16_23dir__WIDTH 1
-#define R_GEN_CONFIG__g16_23dir__in 0
-#define R_GEN_CONFIG__g16_23dir__out 1
-#define R_GEN_CONFIG__g8_15dir__BITNR 25
-#define R_GEN_CONFIG__g8_15dir__WIDTH 1
-#define R_GEN_CONFIG__g8_15dir__in 0
-#define R_GEN_CONFIG__g8_15dir__out 1
-#define R_GEN_CONFIG__g0dir__BITNR 24
-#define R_GEN_CONFIG__g0dir__WIDTH 1
-#define R_GEN_CONFIG__g0dir__in 0
-#define R_GEN_CONFIG__g0dir__out 1
-#define R_GEN_CONFIG__dma9__BITNR 23
-#define R_GEN_CONFIG__dma9__WIDTH 1
-#define R_GEN_CONFIG__dma9__usb 0
-#define R_GEN_CONFIG__dma9__serial1 1
-#define R_GEN_CONFIG__dma8__BITNR 22
-#define R_GEN_CONFIG__dma8__WIDTH 1
-#define R_GEN_CONFIG__dma8__usb 0
-#define R_GEN_CONFIG__dma8__serial1 1
-#define R_GEN_CONFIG__dma7__BITNR 20
-#define R_GEN_CONFIG__dma7__WIDTH 2
-#define R_GEN_CONFIG__dma7__unused 0
-#define R_GEN_CONFIG__dma7__serial0 1
-#define R_GEN_CONFIG__dma7__extdma1 2
-#define R_GEN_CONFIG__dma7__intdma6 3
-#define R_GEN_CONFIG__dma6__BITNR 18
-#define R_GEN_CONFIG__dma6__WIDTH 2
-#define R_GEN_CONFIG__dma6__unused 0
-#define R_GEN_CONFIG__dma6__serial0 1
-#define R_GEN_CONFIG__dma6__extdma1 2
-#define R_GEN_CONFIG__dma6__intdma7 3
-#define R_GEN_CONFIG__dma5__BITNR 16
-#define R_GEN_CONFIG__dma5__WIDTH 2
-#define R_GEN_CONFIG__dma5__par1 0
-#define R_GEN_CONFIG__dma5__scsi1 1
-#define R_GEN_CONFIG__dma5__serial3 2
-#define R_GEN_CONFIG__dma5__extdma0 3
-#define R_GEN_CONFIG__dma4__BITNR 14
-#define R_GEN_CONFIG__dma4__WIDTH 2
-#define R_GEN_CONFIG__dma4__par1 0
-#define R_GEN_CONFIG__dma4__scsi1 1
-#define R_GEN_CONFIG__dma4__serial3 2
-#define R_GEN_CONFIG__dma4__extdma0 3
-#define R_GEN_CONFIG__dma3__BITNR 12
-#define R_GEN_CONFIG__dma3__WIDTH 2
-#define R_GEN_CONFIG__dma3__par0 0
-#define R_GEN_CONFIG__dma3__scsi0 1
-#define R_GEN_CONFIG__dma3__serial2 2
-#define R_GEN_CONFIG__dma3__ata 3
-#define R_GEN_CONFIG__dma2__BITNR 10
-#define R_GEN_CONFIG__dma2__WIDTH 2
-#define R_GEN_CONFIG__dma2__par0 0
-#define R_GEN_CONFIG__dma2__scsi0 1
-#define R_GEN_CONFIG__dma2__serial2 2
-#define R_GEN_CONFIG__dma2__ata 3
-#define R_GEN_CONFIG__mio_w__BITNR 9
-#define R_GEN_CONFIG__mio_w__WIDTH 1
-#define R_GEN_CONFIG__mio_w__select 1
-#define R_GEN_CONFIG__mio_w__disable 0
-#define R_GEN_CONFIG__ser3__BITNR 8
-#define R_GEN_CONFIG__ser3__WIDTH 1
-#define R_GEN_CONFIG__ser3__select 1
-#define R_GEN_CONFIG__ser3__disable 0
-#define R_GEN_CONFIG__par1__BITNR 7
-#define R_GEN_CONFIG__par1__WIDTH 1
-#define R_GEN_CONFIG__par1__select 1
-#define R_GEN_CONFIG__par1__disable 0
-#define R_GEN_CONFIG__scsi0w__BITNR 6
-#define R_GEN_CONFIG__scsi0w__WIDTH 1
-#define R_GEN_CONFIG__scsi0w__select 1
-#define R_GEN_CONFIG__scsi0w__disable 0
-#define R_GEN_CONFIG__scsi1__BITNR 5
-#define R_GEN_CONFIG__scsi1__WIDTH 1
-#define R_GEN_CONFIG__scsi1__select 1
-#define R_GEN_CONFIG__scsi1__disable 0
-#define R_GEN_CONFIG__mio__BITNR 4
-#define R_GEN_CONFIG__mio__WIDTH 1
-#define R_GEN_CONFIG__mio__select 1
-#define R_GEN_CONFIG__mio__disable 0
-#define R_GEN_CONFIG__ser2__BITNR 3
-#define R_GEN_CONFIG__ser2__WIDTH 1
-#define R_GEN_CONFIG__ser2__select 1
-#define R_GEN_CONFIG__ser2__disable 0
-#define R_GEN_CONFIG__par0__BITNR 2
-#define R_GEN_CONFIG__par0__WIDTH 1
-#define R_GEN_CONFIG__par0__select 1
-#define R_GEN_CONFIG__par0__disable 0
-#define R_GEN_CONFIG__ata__BITNR 1
-#define R_GEN_CONFIG__ata__WIDTH 1
-#define R_GEN_CONFIG__ata__select 1
-#define R_GEN_CONFIG__ata__disable 0
-#define R_GEN_CONFIG__scsi0__BITNR 0
-#define R_GEN_CONFIG__scsi0__WIDTH 1
-#define R_GEN_CONFIG__scsi0__select 1
-#define R_GEN_CONFIG__scsi0__disable 0
-
-#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034)
-#define R_GEN_CONFIG_II__sermode3__BITNR 6
-#define R_GEN_CONFIG_II__sermode3__WIDTH 1
-#define R_GEN_CONFIG_II__sermode3__async 0
-#define R_GEN_CONFIG_II__sermode3__sync 1
-#define R_GEN_CONFIG_II__sermode1__BITNR 4
-#define R_GEN_CONFIG_II__sermode1__WIDTH 1
-#define R_GEN_CONFIG_II__sermode1__async 0
-#define R_GEN_CONFIG_II__sermode1__sync 1
-#define R_GEN_CONFIG_II__ext_clk__BITNR 2
-#define R_GEN_CONFIG_II__ext_clk__WIDTH 1
-#define R_GEN_CONFIG_II__ext_clk__select 1
-#define R_GEN_CONFIG_II__ext_clk__disable 0
-#define R_GEN_CONFIG_II__ser2__BITNR 1
-#define R_GEN_CONFIG_II__ser2__WIDTH 1
-#define R_GEN_CONFIG_II__ser2__select 1
-#define R_GEN_CONFIG_II__ser2__disable 0
-#define R_GEN_CONFIG_II__ser3__BITNR 0
-#define R_GEN_CONFIG_II__ser3__WIDTH 1
-#define R_GEN_CONFIG_II__ser3__select 1
-#define R_GEN_CONFIG_II__ser3__disable 0
-
-#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028)
-#define R_PORT_G_DATA__data__BITNR 0
-#define R_PORT_G_DATA__data__WIDTH 32
-
-/*
-!* General port configuration registers
-!*/
-
-#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030)
-#define R_PORT_PA_SET__dir7__BITNR 15
-#define R_PORT_PA_SET__dir7__WIDTH 1
-#define R_PORT_PA_SET__dir7__input 0
-#define R_PORT_PA_SET__dir7__output 1
-#define R_PORT_PA_SET__dir6__BITNR 14
-#define R_PORT_PA_SET__dir6__WIDTH 1
-#define R_PORT_PA_SET__dir6__input 0
-#define R_PORT_PA_SET__dir6__output 1
-#define R_PORT_PA_SET__dir5__BITNR 13
-#define R_PORT_PA_SET__dir5__WIDTH 1
-#define R_PORT_PA_SET__dir5__input 0
-#define R_PORT_PA_SET__dir5__output 1
-#define R_PORT_PA_SET__dir4__BITNR 12
-#define R_PORT_PA_SET__dir4__WIDTH 1
-#define R_PORT_PA_SET__dir4__input 0
-#define R_PORT_PA_SET__dir4__output 1
-#define R_PORT_PA_SET__dir3__BITNR 11
-#define R_PORT_PA_SET__dir3__WIDTH 1
-#define R_PORT_PA_SET__dir3__input 0
-#define R_PORT_PA_SET__dir3__output 1
-#define R_PORT_PA_SET__dir2__BITNR 10
-#define R_PORT_PA_SET__dir2__WIDTH 1
-#define R_PORT_PA_SET__dir2__input 0
-#define R_PORT_PA_SET__dir2__output 1
-#define R_PORT_PA_SET__dir1__BITNR 9
-#define R_PORT_PA_SET__dir1__WIDTH 1
-#define R_PORT_PA_SET__dir1__input 0
-#define R_PORT_PA_SET__dir1__output 1
-#define R_PORT_PA_SET__dir0__BITNR 8
-#define R_PORT_PA_SET__dir0__WIDTH 1
-#define R_PORT_PA_SET__dir0__input 0
-#define R_PORT_PA_SET__dir0__output 1
-#define R_PORT_PA_SET__data_out__BITNR 0
-#define R_PORT_PA_SET__data_out__WIDTH 8
-
-#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030)
-#define R_PORT_PA_DATA__data_out__BITNR 0
-#define R_PORT_PA_DATA__data_out__WIDTH 8
-
-#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031)
-#define R_PORT_PA_DIR__dir7__BITNR 7
-#define R_PORT_PA_DIR__dir7__WIDTH 1
-#define R_PORT_PA_DIR__dir7__input 0
-#define R_PORT_PA_DIR__dir7__output 1
-#define R_PORT_PA_DIR__dir6__BITNR 6
-#define R_PORT_PA_DIR__dir6__WIDTH 1
-#define R_PORT_PA_DIR__dir6__input 0
-#define R_PORT_PA_DIR__dir6__output 1
-#define R_PORT_PA_DIR__dir5__BITNR 5
-#define R_PORT_PA_DIR__dir5__WIDTH 1
-#define R_PORT_PA_DIR__dir5__input 0
-#define R_PORT_PA_DIR__dir5__output 1
-#define R_PORT_PA_DIR__dir4__BITNR 4
-#define R_PORT_PA_DIR__dir4__WIDTH 1
-#define R_PORT_PA_DIR__dir4__input 0
-#define R_PORT_PA_DIR__dir4__output 1
-#define R_PORT_PA_DIR__dir3__BITNR 3
-#define R_PORT_PA_DIR__dir3__WIDTH 1
-#define R_PORT_PA_DIR__dir3__input 0
-#define R_PORT_PA_DIR__dir3__output 1
-#define R_PORT_PA_DIR__dir2__BITNR 2
-#define R_PORT_PA_DIR__dir2__WIDTH 1
-#define R_PORT_PA_DIR__dir2__input 0
-#define R_PORT_PA_DIR__dir2__output 1
-#define R_PORT_PA_DIR__dir1__BITNR 1
-#define R_PORT_PA_DIR__dir1__WIDTH 1
-#define R_PORT_PA_DIR__dir1__input 0
-#define R_PORT_PA_DIR__dir1__output 1
-#define R_PORT_PA_DIR__dir0__BITNR 0
-#define R_PORT_PA_DIR__dir0__WIDTH 1
-#define R_PORT_PA_DIR__dir0__input 0
-#define R_PORT_PA_DIR__dir0__output 1
-
-#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030)
-#define R_PORT_PA_READ__data_in__BITNR 0
-#define R_PORT_PA_READ__data_in__WIDTH 8
-
-#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038)
-#define R_PORT_PB_SET__syncser3__BITNR 29
-#define R_PORT_PB_SET__syncser3__WIDTH 1
-#define R_PORT_PB_SET__syncser3__port_cs 0
-#define R_PORT_PB_SET__syncser3__ss3extra 1
-#define R_PORT_PB_SET__syncser1__BITNR 28
-#define R_PORT_PB_SET__syncser1__WIDTH 1
-#define R_PORT_PB_SET__syncser1__port_cs 0
-#define R_PORT_PB_SET__syncser1__ss1extra 1
-#define R_PORT_PB_SET__i2c_en__BITNR 27
-#define R_PORT_PB_SET__i2c_en__WIDTH 1
-#define R_PORT_PB_SET__i2c_en__off 0
-#define R_PORT_PB_SET__i2c_en__on 1
-#define R_PORT_PB_SET__i2c_d__BITNR 26
-#define R_PORT_PB_SET__i2c_d__WIDTH 1
-#define R_PORT_PB_SET__i2c_clk__BITNR 25
-#define R_PORT_PB_SET__i2c_clk__WIDTH 1
-#define R_PORT_PB_SET__i2c_oe___BITNR 24
-#define R_PORT_PB_SET__i2c_oe___WIDTH 1
-#define R_PORT_PB_SET__i2c_oe___enable 0
-#define R_PORT_PB_SET__i2c_oe___disable 1
-#define R_PORT_PB_SET__cs7__BITNR 23
-#define R_PORT_PB_SET__cs7__WIDTH 1
-#define R_PORT_PB_SET__cs7__port 0
-#define R_PORT_PB_SET__cs7__cs 1
-#define R_PORT_PB_SET__cs6__BITNR 22
-#define R_PORT_PB_SET__cs6__WIDTH 1
-#define R_PORT_PB_SET__cs6__port 0
-#define R_PORT_PB_SET__cs6__cs 1
-#define R_PORT_PB_SET__cs5__BITNR 21
-#define R_PORT_PB_SET__cs5__WIDTH 1
-#define R_PORT_PB_SET__cs5__port 0
-#define R_PORT_PB_SET__cs5__cs 1
-#define R_PORT_PB_SET__cs4__BITNR 20
-#define R_PORT_PB_SET__cs4__WIDTH 1
-#define R_PORT_PB_SET__cs4__port 0
-#define R_PORT_PB_SET__cs4__cs 1
-#define R_PORT_PB_SET__cs3__BITNR 19
-#define R_PORT_PB_SET__cs3__WIDTH 1
-#define R_PORT_PB_SET__cs3__port 0
-#define R_PORT_PB_SET__cs3__cs 1
-#define R_PORT_PB_SET__cs2__BITNR 18
-#define R_PORT_PB_SET__cs2__WIDTH 1
-#define R_PORT_PB_SET__cs2__port 0
-#define R_PORT_PB_SET__cs2__cs 1
-#define R_PORT_PB_SET__scsi1__BITNR 17
-#define R_PORT_PB_SET__scsi1__WIDTH 1
-#define R_PORT_PB_SET__scsi1__port_cs 0
-#define R_PORT_PB_SET__scsi1__enph 1
-#define R_PORT_PB_SET__scsi0__BITNR 16
-#define R_PORT_PB_SET__scsi0__WIDTH 1
-#define R_PORT_PB_SET__scsi0__port_cs 0
-#define R_PORT_PB_SET__scsi0__enph 1
-#define R_PORT_PB_SET__dir7__BITNR 15
-#define R_PORT_PB_SET__dir7__WIDTH 1
-#define R_PORT_PB_SET__dir7__input 0
-#define R_PORT_PB_SET__dir7__output 1
-#define R_PORT_PB_SET__dir6__BITNR 14
-#define R_PORT_PB_SET__dir6__WIDTH 1
-#define R_PORT_PB_SET__dir6__input 0
-#define R_PORT_PB_SET__dir6__output 1
-#define R_PORT_PB_SET__dir5__BITNR 13
-#define R_PORT_PB_SET__dir5__WIDTH 1
-#define R_PORT_PB_SET__dir5__input 0
-#define R_PORT_PB_SET__dir5__output 1
-#define R_PORT_PB_SET__dir4__BITNR 12
-#define R_PORT_PB_SET__dir4__WIDTH 1
-#define R_PORT_PB_SET__dir4__input 0
-#define R_PORT_PB_SET__dir4__output 1
-#define R_PORT_PB_SET__dir3__BITNR 11
-#define R_PORT_PB_SET__dir3__WIDTH 1
-#define R_PORT_PB_SET__dir3__input 0
-#define R_PORT_PB_SET__dir3__output 1
-#define R_PORT_PB_SET__dir2__BITNR 10
-#define R_PORT_PB_SET__dir2__WIDTH 1
-#define R_PORT_PB_SET__dir2__input 0
-#define R_PORT_PB_SET__dir2__output 1
-#define R_PORT_PB_SET__dir1__BITNR 9
-#define R_PORT_PB_SET__dir1__WIDTH 1
-#define R_PORT_PB_SET__dir1__input 0
-#define R_PORT_PB_SET__dir1__output 1
-#define R_PORT_PB_SET__dir0__BITNR 8
-#define R_PORT_PB_SET__dir0__WIDTH 1
-#define R_PORT_PB_SET__dir0__input 0
-#define R_PORT_PB_SET__dir0__output 1
-#define R_PORT_PB_SET__data_out__BITNR 0
-#define R_PORT_PB_SET__data_out__WIDTH 8
-
-#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038)
-#define R_PORT_PB_DATA__data_out__BITNR 0
-#define R_PORT_PB_DATA__data_out__WIDTH 8
-
-#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039)
-#define R_PORT_PB_DIR__dir7__BITNR 7
-#define R_PORT_PB_DIR__dir7__WIDTH 1
-#define R_PORT_PB_DIR__dir7__input 0
-#define R_PORT_PB_DIR__dir7__output 1
-#define R_PORT_PB_DIR__dir6__BITNR 6
-#define R_PORT_PB_DIR__dir6__WIDTH 1
-#define R_PORT_PB_DIR__dir6__input 0
-#define R_PORT_PB_DIR__dir6__output 1
-#define R_PORT_PB_DIR__dir5__BITNR 5
-#define R_PORT_PB_DIR__dir5__WIDTH 1
-#define R_PORT_PB_DIR__dir5__input 0
-#define R_PORT_PB_DIR__dir5__output 1
-#define R_PORT_PB_DIR__dir4__BITNR 4
-#define R_PORT_PB_DIR__dir4__WIDTH 1
-#define R_PORT_PB_DIR__dir4__input 0
-#define R_PORT_PB_DIR__dir4__output 1
-#define R_PORT_PB_DIR__dir3__BITNR 3
-#define R_PORT_PB_DIR__dir3__WIDTH 1
-#define R_PORT_PB_DIR__dir3__input 0
-#define R_PORT_PB_DIR__dir3__output 1
-#define R_PORT_PB_DIR__dir2__BITNR 2
-#define R_PORT_PB_DIR__dir2__WIDTH 1
-#define R_PORT_PB_DIR__dir2__input 0
-#define R_PORT_PB_DIR__dir2__output 1
-#define R_PORT_PB_DIR__dir1__BITNR 1
-#define R_PORT_PB_DIR__dir1__WIDTH 1
-#define R_PORT_PB_DIR__dir1__input 0
-#define R_PORT_PB_DIR__dir1__output 1
-#define R_PORT_PB_DIR__dir0__BITNR 0
-#define R_PORT_PB_DIR__dir0__WIDTH 1
-#define R_PORT_PB_DIR__dir0__input 0
-#define R_PORT_PB_DIR__dir0__output 1
-
-#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a)
-#define R_PORT_PB_CONFIG__cs7__BITNR 7
-#define R_PORT_PB_CONFIG__cs7__WIDTH 1
-#define R_PORT_PB_CONFIG__cs7__port 0
-#define R_PORT_PB_CONFIG__cs7__cs 1
-#define R_PORT_PB_CONFIG__cs6__BITNR 6
-#define R_PORT_PB_CONFIG__cs6__WIDTH 1
-#define R_PORT_PB_CONFIG__cs6__port 0
-#define R_PORT_PB_CONFIG__cs6__cs 1
-#define R_PORT_PB_CONFIG__cs5__BITNR 5
-#define R_PORT_PB_CONFIG__cs5__WIDTH 1
-#define R_PORT_PB_CONFIG__cs5__port 0
-#define R_PORT_PB_CONFIG__cs5__cs 1
-#define R_PORT_PB_CONFIG__cs4__BITNR 4
-#define R_PORT_PB_CONFIG__cs4__WIDTH 1
-#define R_PORT_PB_CONFIG__cs4__port 0
-#define R_PORT_PB_CONFIG__cs4__cs 1
-#define R_PORT_PB_CONFIG__cs3__BITNR 3
-#define R_PORT_PB_CONFIG__cs3__WIDTH 1
-#define R_PORT_PB_CONFIG__cs3__port 0
-#define R_PORT_PB_CONFIG__cs3__cs 1
-#define R_PORT_PB_CONFIG__cs2__BITNR 2
-#define R_PORT_PB_CONFIG__cs2__WIDTH 1
-#define R_PORT_PB_CONFIG__cs2__port 0
-#define R_PORT_PB_CONFIG__cs2__cs 1
-#define R_PORT_PB_CONFIG__scsi1__BITNR 1
-#define R_PORT_PB_CONFIG__scsi1__WIDTH 1
-#define R_PORT_PB_CONFIG__scsi1__port_cs 0
-#define R_PORT_PB_CONFIG__scsi1__enph 1
-#define R_PORT_PB_CONFIG__scsi0__BITNR 0
-#define R_PORT_PB_CONFIG__scsi0__WIDTH 1
-#define R_PORT_PB_CONFIG__scsi0__port_cs 0
-#define R_PORT_PB_CONFIG__scsi0__enph 1
-
-#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b)
-#define R_PORT_PB_I2C__syncser3__BITNR 5
-#define R_PORT_PB_I2C__syncser3__WIDTH 1
-#define R_PORT_PB_I2C__syncser3__port_cs 0
-#define R_PORT_PB_I2C__syncser3__ss3extra 1
-#define R_PORT_PB_I2C__syncser1__BITNR 4
-#define R_PORT_PB_I2C__syncser1__WIDTH 1
-#define R_PORT_PB_I2C__syncser1__port_cs 0
-#define R_PORT_PB_I2C__syncser1__ss1extra 1
-#define R_PORT_PB_I2C__i2c_en__BITNR 3
-#define R_PORT_PB_I2C__i2c_en__WIDTH 1
-#define R_PORT_PB_I2C__i2c_en__off 0
-#define R_PORT_PB_I2C__i2c_en__on 1
-#define R_PORT_PB_I2C__i2c_d__BITNR 2
-#define R_PORT_PB_I2C__i2c_d__WIDTH 1
-#define R_PORT_PB_I2C__i2c_clk__BITNR 1
-#define R_PORT_PB_I2C__i2c_clk__WIDTH 1
-#define R_PORT_PB_I2C__i2c_oe___BITNR 0
-#define R_PORT_PB_I2C__i2c_oe___WIDTH 1
-#define R_PORT_PB_I2C__i2c_oe___enable 0
-#define R_PORT_PB_I2C__i2c_oe___disable 1
-
-#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038)
-#define R_PORT_PB_READ__data_in__BITNR 0
-#define R_PORT_PB_READ__data_in__WIDTH 8
-
-/*
-!* Serial port registers
-!*/
-
-#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060)
-#define R_SERIAL0_CTRL__tr_baud__BITNR 28
-#define R_SERIAL0_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL0_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL0_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL0_CTRL__tr_baud__reserved 15
-#define R_SERIAL0_CTRL__rec_baud__BITNR 24
-#define R_SERIAL0_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL0_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL0_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL0_CTRL__rec_baud__reserved 15
-#define R_SERIAL0_CTRL__dma_err__BITNR 23
-#define R_SERIAL0_CTRL__dma_err__WIDTH 1
-#define R_SERIAL0_CTRL__dma_err__stop 0
-#define R_SERIAL0_CTRL__dma_err__ignore 1
-#define R_SERIAL0_CTRL__rec_enable__BITNR 22
-#define R_SERIAL0_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL0_CTRL__rec_enable__disable 0
-#define R_SERIAL0_CTRL__rec_enable__enable 1
-#define R_SERIAL0_CTRL__rts___BITNR 21
-#define R_SERIAL0_CTRL__rts___WIDTH 1
-#define R_SERIAL0_CTRL__rts___active 0
-#define R_SERIAL0_CTRL__rts___inactive 1
-#define R_SERIAL0_CTRL__sampling__BITNR 20
-#define R_SERIAL0_CTRL__sampling__WIDTH 1
-#define R_SERIAL0_CTRL__sampling__middle 0
-#define R_SERIAL0_CTRL__sampling__majority 1
-#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL0_CTRL__rec_stick_par__normal 0
-#define R_SERIAL0_CTRL__rec_stick_par__stick 1
-#define R_SERIAL0_CTRL__rec_par__BITNR 18
-#define R_SERIAL0_CTRL__rec_par__WIDTH 1
-#define R_SERIAL0_CTRL__rec_par__even 0
-#define R_SERIAL0_CTRL__rec_par__odd 1
-#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL0_CTRL__rec_par_en__disable 0
-#define R_SERIAL0_CTRL__rec_par_en__enable 1
-#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL0_CTRL__txd__BITNR 15
-#define R_SERIAL0_CTRL__txd__WIDTH 1
-#define R_SERIAL0_CTRL__tr_enable__BITNR 14
-#define R_SERIAL0_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL0_CTRL__tr_enable__disable 0
-#define R_SERIAL0_CTRL__tr_enable__enable 1
-#define R_SERIAL0_CTRL__auto_cts__BITNR 13
-#define R_SERIAL0_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL0_CTRL__auto_cts__disabled 0
-#define R_SERIAL0_CTRL__auto_cts__active 1
-#define R_SERIAL0_CTRL__stop_bits__BITNR 12
-#define R_SERIAL0_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL0_CTRL__stop_bits__one_bit 0
-#define R_SERIAL0_CTRL__stop_bits__two_bits 1
-#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL0_CTRL__tr_stick_par__normal 0
-#define R_SERIAL0_CTRL__tr_stick_par__stick 1
-#define R_SERIAL0_CTRL__tr_par__BITNR 10
-#define R_SERIAL0_CTRL__tr_par__WIDTH 1
-#define R_SERIAL0_CTRL__tr_par__even 0
-#define R_SERIAL0_CTRL__tr_par__odd 1
-#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL0_CTRL__tr_par_en__disable 0
-#define R_SERIAL0_CTRL__tr_par_en__enable 1
-#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL0_CTRL__data_out__BITNR 0
-#define R_SERIAL0_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063)
-#define R_SERIAL0_BAUD__tr_baud__BITNR 4
-#define R_SERIAL0_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL0_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL0_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL0_BAUD__tr_baud__reserved 15
-#define R_SERIAL0_BAUD__rec_baud__BITNR 0
-#define R_SERIAL0_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL0_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL0_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL0_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062)
-#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL0_REC_CTRL__dma_err__stop 0
-#define R_SERIAL0_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL0_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL0_REC_CTRL__rts___BITNR 5
-#define R_SERIAL0_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL0_REC_CTRL__rts___active 0
-#define R_SERIAL0_REC_CTRL__rts___inactive 1
-#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL0_REC_CTRL__sampling__middle 0
-#define R_SERIAL0_REC_CTRL__sampling__majority 1
-#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_par__even 0
-#define R_SERIAL0_REC_CTRL__rec_par__odd 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061)
-#define R_SERIAL0_TR_CTRL__txd__BITNR 7
-#define R_SERIAL0_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL0_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL0_TR_CTRL__auto_cts__active 1
-#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_par__even 0
-#define R_SERIAL0_TR_CTRL__tr_par__odd 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060)
-#define R_SERIAL0_TR_DATA__data_out__BITNR 0
-#define R_SERIAL0_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060)
-#define R_SERIAL0_READ__xoff_detect__BITNR 15
-#define R_SERIAL0_READ__xoff_detect__WIDTH 1
-#define R_SERIAL0_READ__xoff_detect__no_xoff 0
-#define R_SERIAL0_READ__xoff_detect__xoff 1
-#define R_SERIAL0_READ__cts___BITNR 14
-#define R_SERIAL0_READ__cts___WIDTH 1
-#define R_SERIAL0_READ__cts___active 0
-#define R_SERIAL0_READ__cts___inactive 1
-#define R_SERIAL0_READ__tr_ready__BITNR 13
-#define R_SERIAL0_READ__tr_ready__WIDTH 1
-#define R_SERIAL0_READ__tr_ready__full 0
-#define R_SERIAL0_READ__tr_ready__ready 1
-#define R_SERIAL0_READ__rxd__BITNR 12
-#define R_SERIAL0_READ__rxd__WIDTH 1
-#define R_SERIAL0_READ__overrun__BITNR 11
-#define R_SERIAL0_READ__overrun__WIDTH 1
-#define R_SERIAL0_READ__overrun__no 0
-#define R_SERIAL0_READ__overrun__yes 1
-#define R_SERIAL0_READ__par_err__BITNR 10
-#define R_SERIAL0_READ__par_err__WIDTH 1
-#define R_SERIAL0_READ__par_err__no 0
-#define R_SERIAL0_READ__par_err__yes 1
-#define R_SERIAL0_READ__framing_err__BITNR 9
-#define R_SERIAL0_READ__framing_err__WIDTH 1
-#define R_SERIAL0_READ__framing_err__no 0
-#define R_SERIAL0_READ__framing_err__yes 1
-#define R_SERIAL0_READ__data_avail__BITNR 8
-#define R_SERIAL0_READ__data_avail__WIDTH 1
-#define R_SERIAL0_READ__data_avail__no 0
-#define R_SERIAL0_READ__data_avail__yes 1
-#define R_SERIAL0_READ__data_in__BITNR 0
-#define R_SERIAL0_READ__data_in__WIDTH 8
-
-#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061)
-#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL0_STATUS__xoff_detect__xoff 1
-#define R_SERIAL0_STATUS__cts___BITNR 6
-#define R_SERIAL0_STATUS__cts___WIDTH 1
-#define R_SERIAL0_STATUS__cts___active 0
-#define R_SERIAL0_STATUS__cts___inactive 1
-#define R_SERIAL0_STATUS__tr_ready__BITNR 5
-#define R_SERIAL0_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL0_STATUS__tr_ready__full 0
-#define R_SERIAL0_STATUS__tr_ready__ready 1
-#define R_SERIAL0_STATUS__rxd__BITNR 4
-#define R_SERIAL0_STATUS__rxd__WIDTH 1
-#define R_SERIAL0_STATUS__overrun__BITNR 3
-#define R_SERIAL0_STATUS__overrun__WIDTH 1
-#define R_SERIAL0_STATUS__overrun__no 0
-#define R_SERIAL0_STATUS__overrun__yes 1
-#define R_SERIAL0_STATUS__par_err__BITNR 2
-#define R_SERIAL0_STATUS__par_err__WIDTH 1
-#define R_SERIAL0_STATUS__par_err__no 0
-#define R_SERIAL0_STATUS__par_err__yes 1
-#define R_SERIAL0_STATUS__framing_err__BITNR 1
-#define R_SERIAL0_STATUS__framing_err__WIDTH 1
-#define R_SERIAL0_STATUS__framing_err__no 0
-#define R_SERIAL0_STATUS__framing_err__yes 1
-#define R_SERIAL0_STATUS__data_avail__BITNR 0
-#define R_SERIAL0_STATUS__data_avail__WIDTH 1
-#define R_SERIAL0_STATUS__data_avail__no 0
-#define R_SERIAL0_STATUS__data_avail__yes 1
-
-#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060)
-#define R_SERIAL0_REC_DATA__data_in__BITNR 0
-#define R_SERIAL0_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064)
-#define R_SERIAL0_XOFF__tx_stop__BITNR 9
-#define R_SERIAL0_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL0_XOFF__tx_stop__enable 0
-#define R_SERIAL0_XOFF__tx_stop__stop 1
-#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL0_XOFF__auto_xoff__disable 0
-#define R_SERIAL0_XOFF__auto_xoff__enable 1
-#define R_SERIAL0_XOFF__xoff_char__BITNR 0
-#define R_SERIAL0_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
-#define R_SERIAL1_CTRL__tr_baud__BITNR 28
-#define R_SERIAL1_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL1_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL1_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL1_CTRL__tr_baud__reserved 15
-#define R_SERIAL1_CTRL__rec_baud__BITNR 24
-#define R_SERIAL1_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL1_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL1_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL1_CTRL__rec_baud__reserved 15
-#define R_SERIAL1_CTRL__dma_err__BITNR 23
-#define R_SERIAL1_CTRL__dma_err__WIDTH 1
-#define R_SERIAL1_CTRL__dma_err__stop 0
-#define R_SERIAL1_CTRL__dma_err__ignore 1
-#define R_SERIAL1_CTRL__rec_enable__BITNR 22
-#define R_SERIAL1_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL1_CTRL__rec_enable__disable 0
-#define R_SERIAL1_CTRL__rec_enable__enable 1
-#define R_SERIAL1_CTRL__rts___BITNR 21
-#define R_SERIAL1_CTRL__rts___WIDTH 1
-#define R_SERIAL1_CTRL__rts___active 0
-#define R_SERIAL1_CTRL__rts___inactive 1
-#define R_SERIAL1_CTRL__sampling__BITNR 20
-#define R_SERIAL1_CTRL__sampling__WIDTH 1
-#define R_SERIAL1_CTRL__sampling__middle 0
-#define R_SERIAL1_CTRL__sampling__majority 1
-#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL1_CTRL__rec_stick_par__normal 0
-#define R_SERIAL1_CTRL__rec_stick_par__stick 1
-#define R_SERIAL1_CTRL__rec_par__BITNR 18
-#define R_SERIAL1_CTRL__rec_par__WIDTH 1
-#define R_SERIAL1_CTRL__rec_par__even 0
-#define R_SERIAL1_CTRL__rec_par__odd 1
-#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL1_CTRL__rec_par_en__disable 0
-#define R_SERIAL1_CTRL__rec_par_en__enable 1
-#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL1_CTRL__txd__BITNR 15
-#define R_SERIAL1_CTRL__txd__WIDTH 1
-#define R_SERIAL1_CTRL__tr_enable__BITNR 14
-#define R_SERIAL1_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL1_CTRL__tr_enable__disable 0
-#define R_SERIAL1_CTRL__tr_enable__enable 1
-#define R_SERIAL1_CTRL__auto_cts__BITNR 13
-#define R_SERIAL1_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL1_CTRL__auto_cts__disabled 0
-#define R_SERIAL1_CTRL__auto_cts__active 1
-#define R_SERIAL1_CTRL__stop_bits__BITNR 12
-#define R_SERIAL1_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL1_CTRL__stop_bits__one_bit 0
-#define R_SERIAL1_CTRL__stop_bits__two_bits 1
-#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL1_CTRL__tr_stick_par__normal 0
-#define R_SERIAL1_CTRL__tr_stick_par__stick 1
-#define R_SERIAL1_CTRL__tr_par__BITNR 10
-#define R_SERIAL1_CTRL__tr_par__WIDTH 1
-#define R_SERIAL1_CTRL__tr_par__even 0
-#define R_SERIAL1_CTRL__tr_par__odd 1
-#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL1_CTRL__tr_par_en__disable 0
-#define R_SERIAL1_CTRL__tr_par_en__enable 1
-#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL1_CTRL__data_out__BITNR 0
-#define R_SERIAL1_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b)
-#define R_SERIAL1_BAUD__tr_baud__BITNR 4
-#define R_SERIAL1_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL1_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL1_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL1_BAUD__tr_baud__reserved 15
-#define R_SERIAL1_BAUD__rec_baud__BITNR 0
-#define R_SERIAL1_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL1_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL1_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL1_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a)
-#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL1_REC_CTRL__dma_err__stop 0
-#define R_SERIAL1_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL1_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL1_REC_CTRL__rts___BITNR 5
-#define R_SERIAL1_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL1_REC_CTRL__rts___active 0
-#define R_SERIAL1_REC_CTRL__rts___inactive 1
-#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL1_REC_CTRL__sampling__middle 0
-#define R_SERIAL1_REC_CTRL__sampling__majority 1
-#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_par__even 0
-#define R_SERIAL1_REC_CTRL__rec_par__odd 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069)
-#define R_SERIAL1_TR_CTRL__txd__BITNR 7
-#define R_SERIAL1_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL1_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL1_TR_CTRL__auto_cts__active 1
-#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_par__even 0
-#define R_SERIAL1_TR_CTRL__tr_par__odd 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068)
-#define R_SERIAL1_TR_DATA__data_out__BITNR 0
-#define R_SERIAL1_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068)
-#define R_SERIAL1_READ__xoff_detect__BITNR 15
-#define R_SERIAL1_READ__xoff_detect__WIDTH 1
-#define R_SERIAL1_READ__xoff_detect__no_xoff 0
-#define R_SERIAL1_READ__xoff_detect__xoff 1
-#define R_SERIAL1_READ__cts___BITNR 14
-#define R_SERIAL1_READ__cts___WIDTH 1
-#define R_SERIAL1_READ__cts___active 0
-#define R_SERIAL1_READ__cts___inactive 1
-#define R_SERIAL1_READ__tr_ready__BITNR 13
-#define R_SERIAL1_READ__tr_ready__WIDTH 1
-#define R_SERIAL1_READ__tr_ready__full 0
-#define R_SERIAL1_READ__tr_ready__ready 1
-#define R_SERIAL1_READ__rxd__BITNR 12
-#define R_SERIAL1_READ__rxd__WIDTH 1
-#define R_SERIAL1_READ__overrun__BITNR 11
-#define R_SERIAL1_READ__overrun__WIDTH 1
-#define R_SERIAL1_READ__overrun__no 0
-#define R_SERIAL1_READ__overrun__yes 1
-#define R_SERIAL1_READ__par_err__BITNR 10
-#define R_SERIAL1_READ__par_err__WIDTH 1
-#define R_SERIAL1_READ__par_err__no 0
-#define R_SERIAL1_READ__par_err__yes 1
-#define R_SERIAL1_READ__framing_err__BITNR 9
-#define R_SERIAL1_READ__framing_err__WIDTH 1
-#define R_SERIAL1_READ__framing_err__no 0
-#define R_SERIAL1_READ__framing_err__yes 1
-#define R_SERIAL1_READ__data_avail__BITNR 8
-#define R_SERIAL1_READ__data_avail__WIDTH 1
-#define R_SERIAL1_READ__data_avail__no 0
-#define R_SERIAL1_READ__data_avail__yes 1
-#define R_SERIAL1_READ__data_in__BITNR 0
-#define R_SERIAL1_READ__data_in__WIDTH 8
-
-#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069)
-#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL1_STATUS__xoff_detect__xoff 1
-#define R_SERIAL1_STATUS__cts___BITNR 6
-#define R_SERIAL1_STATUS__cts___WIDTH 1
-#define R_SERIAL1_STATUS__cts___active 0
-#define R_SERIAL1_STATUS__cts___inactive 1
-#define R_SERIAL1_STATUS__tr_ready__BITNR 5
-#define R_SERIAL1_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL1_STATUS__tr_ready__full 0
-#define R_SERIAL1_STATUS__tr_ready__ready 1
-#define R_SERIAL1_STATUS__rxd__BITNR 4
-#define R_SERIAL1_STATUS__rxd__WIDTH 1
-#define R_SERIAL1_STATUS__overrun__BITNR 3
-#define R_SERIAL1_STATUS__overrun__WIDTH 1
-#define R_SERIAL1_STATUS__overrun__no 0
-#define R_SERIAL1_STATUS__overrun__yes 1
-#define R_SERIAL1_STATUS__par_err__BITNR 2
-#define R_SERIAL1_STATUS__par_err__WIDTH 1
-#define R_SERIAL1_STATUS__par_err__no 0
-#define R_SERIAL1_STATUS__par_err__yes 1
-#define R_SERIAL1_STATUS__framing_err__BITNR 1
-#define R_SERIAL1_STATUS__framing_err__WIDTH 1
-#define R_SERIAL1_STATUS__framing_err__no 0
-#define R_SERIAL1_STATUS__framing_err__yes 1
-#define R_SERIAL1_STATUS__data_avail__BITNR 0
-#define R_SERIAL1_STATUS__data_avail__WIDTH 1
-#define R_SERIAL1_STATUS__data_avail__no 0
-#define R_SERIAL1_STATUS__data_avail__yes 1
-
-#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068)
-#define R_SERIAL1_REC_DATA__data_in__BITNR 0
-#define R_SERIAL1_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c)
-#define R_SERIAL1_XOFF__tx_stop__BITNR 9
-#define R_SERIAL1_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL1_XOFF__tx_stop__enable 0
-#define R_SERIAL1_XOFF__tx_stop__stop 1
-#define R_SERIAL1_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL1_XOFF__auto_xoff__disable 0
-#define R_SERIAL1_XOFF__auto_xoff__enable 1
-#define R_SERIAL1_XOFF__xoff_char__BITNR 0
-#define R_SERIAL1_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070)
-#define R_SERIAL2_CTRL__tr_baud__BITNR 28
-#define R_SERIAL2_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL2_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL2_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL2_CTRL__tr_baud__reserved 15
-#define R_SERIAL2_CTRL__rec_baud__BITNR 24
-#define R_SERIAL2_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL2_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL2_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL2_CTRL__rec_baud__reserved 15
-#define R_SERIAL2_CTRL__dma_err__BITNR 23
-#define R_SERIAL2_CTRL__dma_err__WIDTH 1
-#define R_SERIAL2_CTRL__dma_err__stop 0
-#define R_SERIAL2_CTRL__dma_err__ignore 1
-#define R_SERIAL2_CTRL__rec_enable__BITNR 22
-#define R_SERIAL2_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL2_CTRL__rec_enable__disable 0
-#define R_SERIAL2_CTRL__rec_enable__enable 1
-#define R_SERIAL2_CTRL__rts___BITNR 21
-#define R_SERIAL2_CTRL__rts___WIDTH 1
-#define R_SERIAL2_CTRL__rts___active 0
-#define R_SERIAL2_CTRL__rts___inactive 1
-#define R_SERIAL2_CTRL__sampling__BITNR 20
-#define R_SERIAL2_CTRL__sampling__WIDTH 1
-#define R_SERIAL2_CTRL__sampling__middle 0
-#define R_SERIAL2_CTRL__sampling__majority 1
-#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL2_CTRL__rec_stick_par__normal 0
-#define R_SERIAL2_CTRL__rec_stick_par__stick 1
-#define R_SERIAL2_CTRL__rec_par__BITNR 18
-#define R_SERIAL2_CTRL__rec_par__WIDTH 1
-#define R_SERIAL2_CTRL__rec_par__even 0
-#define R_SERIAL2_CTRL__rec_par__odd 1
-#define R_SERIAL2_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL2_CTRL__rec_par_en__disable 0
-#define R_SERIAL2_CTRL__rec_par_en__enable 1
-#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL2_CTRL__txd__BITNR 15
-#define R_SERIAL2_CTRL__txd__WIDTH 1
-#define R_SERIAL2_CTRL__tr_enable__BITNR 14
-#define R_SERIAL2_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL2_CTRL__tr_enable__disable 0
-#define R_SERIAL2_CTRL__tr_enable__enable 1
-#define R_SERIAL2_CTRL__auto_cts__BITNR 13
-#define R_SERIAL2_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL2_CTRL__auto_cts__disabled 0
-#define R_SERIAL2_CTRL__auto_cts__active 1
-#define R_SERIAL2_CTRL__stop_bits__BITNR 12
-#define R_SERIAL2_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL2_CTRL__stop_bits__one_bit 0
-#define R_SERIAL2_CTRL__stop_bits__two_bits 1
-#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL2_CTRL__tr_stick_par__normal 0
-#define R_SERIAL2_CTRL__tr_stick_par__stick 1
-#define R_SERIAL2_CTRL__tr_par__BITNR 10
-#define R_SERIAL2_CTRL__tr_par__WIDTH 1
-#define R_SERIAL2_CTRL__tr_par__even 0
-#define R_SERIAL2_CTRL__tr_par__odd 1
-#define R_SERIAL2_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL2_CTRL__tr_par_en__disable 0
-#define R_SERIAL2_CTRL__tr_par_en__enable 1
-#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL2_CTRL__data_out__BITNR 0
-#define R_SERIAL2_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073)
-#define R_SERIAL2_BAUD__tr_baud__BITNR 4
-#define R_SERIAL2_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL2_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL2_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL2_BAUD__tr_baud__reserved 15
-#define R_SERIAL2_BAUD__rec_baud__BITNR 0
-#define R_SERIAL2_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL2_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL2_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL2_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072)
-#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL2_REC_CTRL__dma_err__stop 0
-#define R_SERIAL2_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL2_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL2_REC_CTRL__rts___BITNR 5
-#define R_SERIAL2_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL2_REC_CTRL__rts___active 0
-#define R_SERIAL2_REC_CTRL__rts___inactive 1
-#define R_SERIAL2_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL2_REC_CTRL__sampling__middle 0
-#define R_SERIAL2_REC_CTRL__sampling__majority 1
-#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_par__even 0
-#define R_SERIAL2_REC_CTRL__rec_par__odd 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071)
-#define R_SERIAL2_TR_CTRL__txd__BITNR 7
-#define R_SERIAL2_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL2_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL2_TR_CTRL__auto_cts__active 1
-#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_par__even 0
-#define R_SERIAL2_TR_CTRL__tr_par__odd 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070)
-#define R_SERIAL2_TR_DATA__data_out__BITNR 0
-#define R_SERIAL2_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070)
-#define R_SERIAL2_READ__xoff_detect__BITNR 15
-#define R_SERIAL2_READ__xoff_detect__WIDTH 1
-#define R_SERIAL2_READ__xoff_detect__no_xoff 0
-#define R_SERIAL2_READ__xoff_detect__xoff 1
-#define R_SERIAL2_READ__cts___BITNR 14
-#define R_SERIAL2_READ__cts___WIDTH 1
-#define R_SERIAL2_READ__cts___active 0
-#define R_SERIAL2_READ__cts___inactive 1
-#define R_SERIAL2_READ__tr_ready__BITNR 13
-#define R_SERIAL2_READ__tr_ready__WIDTH 1
-#define R_SERIAL2_READ__tr_ready__full 0
-#define R_SERIAL2_READ__tr_ready__ready 1
-#define R_SERIAL2_READ__rxd__BITNR 12
-#define R_SERIAL2_READ__rxd__WIDTH 1
-#define R_SERIAL2_READ__overrun__BITNR 11
-#define R_SERIAL2_READ__overrun__WIDTH 1
-#define R_SERIAL2_READ__overrun__no 0
-#define R_SERIAL2_READ__overrun__yes 1
-#define R_SERIAL2_READ__par_err__BITNR 10
-#define R_SERIAL2_READ__par_err__WIDTH 1
-#define R_SERIAL2_READ__par_err__no 0
-#define R_SERIAL2_READ__par_err__yes 1
-#define R_SERIAL2_READ__framing_err__BITNR 9
-#define R_SERIAL2_READ__framing_err__WIDTH 1
-#define R_SERIAL2_READ__framing_err__no 0
-#define R_SERIAL2_READ__framing_err__yes 1
-#define R_SERIAL2_READ__data_avail__BITNR 8
-#define R_SERIAL2_READ__data_avail__WIDTH 1
-#define R_SERIAL2_READ__data_avail__no 0
-#define R_SERIAL2_READ__data_avail__yes 1
-#define R_SERIAL2_READ__data_in__BITNR 0
-#define R_SERIAL2_READ__data_in__WIDTH 8
-
-#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071)
-#define R_SERIAL2_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL2_STATUS__xoff_detect__xoff 1
-#define R_SERIAL2_STATUS__cts___BITNR 6
-#define R_SERIAL2_STATUS__cts___WIDTH 1
-#define R_SERIAL2_STATUS__cts___active 0
-#define R_SERIAL2_STATUS__cts___inactive 1
-#define R_SERIAL2_STATUS__tr_ready__BITNR 5
-#define R_SERIAL2_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL2_STATUS__tr_ready__full 0
-#define R_SERIAL2_STATUS__tr_ready__ready 1
-#define R_SERIAL2_STATUS__rxd__BITNR 4
-#define R_SERIAL2_STATUS__rxd__WIDTH 1
-#define R_SERIAL2_STATUS__overrun__BITNR 3
-#define R_SERIAL2_STATUS__overrun__WIDTH 1
-#define R_SERIAL2_STATUS__overrun__no 0
-#define R_SERIAL2_STATUS__overrun__yes 1
-#define R_SERIAL2_STATUS__par_err__BITNR 2
-#define R_SERIAL2_STATUS__par_err__WIDTH 1
-#define R_SERIAL2_STATUS__par_err__no 0
-#define R_SERIAL2_STATUS__par_err__yes 1
-#define R_SERIAL2_STATUS__framing_err__BITNR 1
-#define R_SERIAL2_STATUS__framing_err__WIDTH 1
-#define R_SERIAL2_STATUS__framing_err__no 0
-#define R_SERIAL2_STATUS__framing_err__yes 1
-#define R_SERIAL2_STATUS__data_avail__BITNR 0
-#define R_SERIAL2_STATUS__data_avail__WIDTH 1
-#define R_SERIAL2_STATUS__data_avail__no 0
-#define R_SERIAL2_STATUS__data_avail__yes 1
-
-#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070)
-#define R_SERIAL2_REC_DATA__data_in__BITNR 0
-#define R_SERIAL2_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074)
-#define R_SERIAL2_XOFF__tx_stop__BITNR 9
-#define R_SERIAL2_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL2_XOFF__tx_stop__enable 0
-#define R_SERIAL2_XOFF__tx_stop__stop 1
-#define R_SERIAL2_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL2_XOFF__auto_xoff__disable 0
-#define R_SERIAL2_XOFF__auto_xoff__enable 1
-#define R_SERIAL2_XOFF__xoff_char__BITNR 0
-#define R_SERIAL2_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
-#define R_SERIAL3_CTRL__tr_baud__BITNR 28
-#define R_SERIAL3_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL3_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL3_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL3_CTRL__tr_baud__reserved 15
-#define R_SERIAL3_CTRL__rec_baud__BITNR 24
-#define R_SERIAL3_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL3_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL3_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL3_CTRL__rec_baud__reserved 15
-#define R_SERIAL3_CTRL__dma_err__BITNR 23
-#define R_SERIAL3_CTRL__dma_err__WIDTH 1
-#define R_SERIAL3_CTRL__dma_err__stop 0
-#define R_SERIAL3_CTRL__dma_err__ignore 1
-#define R_SERIAL3_CTRL__rec_enable__BITNR 22
-#define R_SERIAL3_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL3_CTRL__rec_enable__disable 0
-#define R_SERIAL3_CTRL__rec_enable__enable 1
-#define R_SERIAL3_CTRL__rts___BITNR 21
-#define R_SERIAL3_CTRL__rts___WIDTH 1
-#define R_SERIAL3_CTRL__rts___active 0
-#define R_SERIAL3_CTRL__rts___inactive 1
-#define R_SERIAL3_CTRL__sampling__BITNR 20
-#define R_SERIAL3_CTRL__sampling__WIDTH 1
-#define R_SERIAL3_CTRL__sampling__middle 0
-#define R_SERIAL3_CTRL__sampling__majority 1
-#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL3_CTRL__rec_stick_par__normal 0
-#define R_SERIAL3_CTRL__rec_stick_par__stick 1
-#define R_SERIAL3_CTRL__rec_par__BITNR 18
-#define R_SERIAL3_CTRL__rec_par__WIDTH 1
-#define R_SERIAL3_CTRL__rec_par__even 0
-#define R_SERIAL3_CTRL__rec_par__odd 1
-#define R_SERIAL3_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL3_CTRL__rec_par_en__disable 0
-#define R_SERIAL3_CTRL__rec_par_en__enable 1
-#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL3_CTRL__txd__BITNR 15
-#define R_SERIAL3_CTRL__txd__WIDTH 1
-#define R_SERIAL3_CTRL__tr_enable__BITNR 14
-#define R_SERIAL3_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL3_CTRL__tr_enable__disable 0
-#define R_SERIAL3_CTRL__tr_enable__enable 1
-#define R_SERIAL3_CTRL__auto_cts__BITNR 13
-#define R_SERIAL3_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL3_CTRL__auto_cts__disabled 0
-#define R_SERIAL3_CTRL__auto_cts__active 1
-#define R_SERIAL3_CTRL__stop_bits__BITNR 12
-#define R_SERIAL3_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL3_CTRL__stop_bits__one_bit 0
-#define R_SERIAL3_CTRL__stop_bits__two_bits 1
-#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL3_CTRL__tr_stick_par__normal 0
-#define R_SERIAL3_CTRL__tr_stick_par__stick 1
-#define R_SERIAL3_CTRL__tr_par__BITNR 10
-#define R_SERIAL3_CTRL__tr_par__WIDTH 1
-#define R_SERIAL3_CTRL__tr_par__even 0
-#define R_SERIAL3_CTRL__tr_par__odd 1
-#define R_SERIAL3_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL3_CTRL__tr_par_en__disable 0
-#define R_SERIAL3_CTRL__tr_par_en__enable 1
-#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL3_CTRL__data_out__BITNR 0
-#define R_SERIAL3_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b)
-#define R_SERIAL3_BAUD__tr_baud__BITNR 4
-#define R_SERIAL3_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL3_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL3_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL3_BAUD__tr_baud__reserved 15
-#define R_SERIAL3_BAUD__rec_baud__BITNR 0
-#define R_SERIAL3_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL3_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL3_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL3_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a)
-#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL3_REC_CTRL__dma_err__stop 0
-#define R_SERIAL3_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL3_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL3_REC_CTRL__rts___BITNR 5
-#define R_SERIAL3_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL3_REC_CTRL__rts___active 0
-#define R_SERIAL3_REC_CTRL__rts___inactive 1
-#define R_SERIAL3_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL3_REC_CTRL__sampling__middle 0
-#define R_SERIAL3_REC_CTRL__sampling__majority 1
-#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_par__even 0
-#define R_SERIAL3_REC_CTRL__rec_par__odd 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079)
-#define R_SERIAL3_TR_CTRL__txd__BITNR 7
-#define R_SERIAL3_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL3_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL3_TR_CTRL__auto_cts__active 1
-#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_par__even 0
-#define R_SERIAL3_TR_CTRL__tr_par__odd 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078)
-#define R_SERIAL3_TR_DATA__data_out__BITNR 0
-#define R_SERIAL3_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078)
-#define R_SERIAL3_READ__xoff_detect__BITNR 15
-#define R_SERIAL3_READ__xoff_detect__WIDTH 1
-#define R_SERIAL3_READ__xoff_detect__no_xoff 0
-#define R_SERIAL3_READ__xoff_detect__xoff 1
-#define R_SERIAL3_READ__cts___BITNR 14
-#define R_SERIAL3_READ__cts___WIDTH 1
-#define R_SERIAL3_READ__cts___active 0
-#define R_SERIAL3_READ__cts___inactive 1
-#define R_SERIAL3_READ__tr_ready__BITNR 13
-#define R_SERIAL3_READ__tr_ready__WIDTH 1
-#define R_SERIAL3_READ__tr_ready__full 0
-#define R_SERIAL3_READ__tr_ready__ready 1
-#define R_SERIAL3_READ__rxd__BITNR 12
-#define R_SERIAL3_READ__rxd__WIDTH 1
-#define R_SERIAL3_READ__overrun__BITNR 11
-#define R_SERIAL3_READ__overrun__WIDTH 1
-#define R_SERIAL3_READ__overrun__no 0
-#define R_SERIAL3_READ__overrun__yes 1
-#define R_SERIAL3_READ__par_err__BITNR 10
-#define R_SERIAL3_READ__par_err__WIDTH 1
-#define R_SERIAL3_READ__par_err__no 0
-#define R_SERIAL3_READ__par_err__yes 1
-#define R_SERIAL3_READ__framing_err__BITNR 9
-#define R_SERIAL3_READ__framing_err__WIDTH 1
-#define R_SERIAL3_READ__framing_err__no 0
-#define R_SERIAL3_READ__framing_err__yes 1
-#define R_SERIAL3_READ__data_avail__BITNR 8
-#define R_SERIAL3_READ__data_avail__WIDTH 1
-#define R_SERIAL3_READ__data_avail__no 0
-#define R_SERIAL3_READ__data_avail__yes 1
-#define R_SERIAL3_READ__data_in__BITNR 0
-#define R_SERIAL3_READ__data_in__WIDTH 8
-
-#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079)
-#define R_SERIAL3_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL3_STATUS__xoff_detect__xoff 1
-#define R_SERIAL3_STATUS__cts___BITNR 6
-#define R_SERIAL3_STATUS__cts___WIDTH 1
-#define R_SERIAL3_STATUS__cts___active 0
-#define R_SERIAL3_STATUS__cts___inactive 1
-#define R_SERIAL3_STATUS__tr_ready__BITNR 5
-#define R_SERIAL3_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL3_STATUS__tr_ready__full 0
-#define R_SERIAL3_STATUS__tr_ready__ready 1
-#define R_SERIAL3_STATUS__rxd__BITNR 4
-#define R_SERIAL3_STATUS__rxd__WIDTH 1
-#define R_SERIAL3_STATUS__overrun__BITNR 3
-#define R_SERIAL3_STATUS__overrun__WIDTH 1
-#define R_SERIAL3_STATUS__overrun__no 0
-#define R_SERIAL3_STATUS__overrun__yes 1
-#define R_SERIAL3_STATUS__par_err__BITNR 2
-#define R_SERIAL3_STATUS__par_err__WIDTH 1
-#define R_SERIAL3_STATUS__par_err__no 0
-#define R_SERIAL3_STATUS__par_err__yes 1
-#define R_SERIAL3_STATUS__framing_err__BITNR 1
-#define R_SERIAL3_STATUS__framing_err__WIDTH 1
-#define R_SERIAL3_STATUS__framing_err__no 0
-#define R_SERIAL3_STATUS__framing_err__yes 1
-#define R_SERIAL3_STATUS__data_avail__BITNR 0
-#define R_SERIAL3_STATUS__data_avail__WIDTH 1
-#define R_SERIAL3_STATUS__data_avail__no 0
-#define R_SERIAL3_STATUS__data_avail__yes 1
-
-#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078)
-#define R_SERIAL3_REC_DATA__data_in__BITNR 0
-#define R_SERIAL3_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c)
-#define R_SERIAL3_XOFF__tx_stop__BITNR 9
-#define R_SERIAL3_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL3_XOFF__tx_stop__enable 0
-#define R_SERIAL3_XOFF__tx_stop__stop 1
-#define R_SERIAL3_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL3_XOFF__auto_xoff__disable 0
-#define R_SERIAL3_XOFF__auto_xoff__enable 1
-#define R_SERIAL3_XOFF__xoff_char__BITNR 0
-#define R_SERIAL3_XOFF__xoff_char__WIDTH 8
-
-#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c)
-#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
-#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
-#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
-#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
-#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
-#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
-#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
-#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
-#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3
-
-/*
-!* Network interface registers
-!*/
-
-#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080)
-#define R_NETWORK_SA_0__ma0_low__BITNR 0
-#define R_NETWORK_SA_0__ma0_low__WIDTH 32
-
-#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084)
-#define R_NETWORK_SA_1__ma1_low__BITNR 16
-#define R_NETWORK_SA_1__ma1_low__WIDTH 16
-#define R_NETWORK_SA_1__ma0_high__BITNR 0
-#define R_NETWORK_SA_1__ma0_high__WIDTH 16
-
-#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088)
-#define R_NETWORK_SA_2__ma1_high__BITNR 0
-#define R_NETWORK_SA_2__ma1_high__WIDTH 32
-
-#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c)
-#define R_NETWORK_GA_0__ga_low__BITNR 0
-#define R_NETWORK_GA_0__ga_low__WIDTH 32
-
-#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090)
-#define R_NETWORK_GA_1__ga_high__BITNR 0
-#define R_NETWORK_GA_1__ga_high__WIDTH 32
-
-#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094)
-#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
-#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1
-#define R_NETWORK_REC_CONFIG__max_size__size1518 0
-#define R_NETWORK_REC_CONFIG__max_size__size1522 1
-#define R_NETWORK_REC_CONFIG__duplex__BITNR 9
-#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1
-#define R_NETWORK_REC_CONFIG__duplex__full 1
-#define R_NETWORK_REC_CONFIG__duplex__half 0
-#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
-#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1
-#define R_NETWORK_REC_CONFIG__bad_crc__receive 1
-#define R_NETWORK_REC_CONFIG__bad_crc__discard 0
-#define R_NETWORK_REC_CONFIG__oversize__BITNR 7
-#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1
-#define R_NETWORK_REC_CONFIG__oversize__receive 1
-#define R_NETWORK_REC_CONFIG__oversize__discard 0
-#define R_NETWORK_REC_CONFIG__undersize__BITNR 6
-#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1
-#define R_NETWORK_REC_CONFIG__undersize__receive 1
-#define R_NETWORK_REC_CONFIG__undersize__discard 0
-#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
-#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1
-#define R_NETWORK_REC_CONFIG__all_roots__receive 1
-#define R_NETWORK_REC_CONFIG__all_roots__discard 0
-#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
-#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1
-#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1
-#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0
-#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
-#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1
-#define R_NETWORK_REC_CONFIG__broadcast__receive 1
-#define R_NETWORK_REC_CONFIG__broadcast__discard 0
-#define R_NETWORK_REC_CONFIG__individual__BITNR 2
-#define R_NETWORK_REC_CONFIG__individual__WIDTH 1
-#define R_NETWORK_REC_CONFIG__individual__receive 1
-#define R_NETWORK_REC_CONFIG__individual__discard 0
-#define R_NETWORK_REC_CONFIG__ma1__BITNR 1
-#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1
-#define R_NETWORK_REC_CONFIG__ma1__enable 1
-#define R_NETWORK_REC_CONFIG__ma1__disable 0
-#define R_NETWORK_REC_CONFIG__ma0__BITNR 0
-#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1
-#define R_NETWORK_REC_CONFIG__ma0__enable 1
-#define R_NETWORK_REC_CONFIG__ma0__disable 0
-
-#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098)
-#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
-#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__loopback__on 1
-#define R_NETWORK_GEN_CONFIG__loopback__off 0
-#define R_NETWORK_GEN_CONFIG__frame__BITNR 4
-#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__frame__tokenr 1
-#define R_NETWORK_GEN_CONFIG__frame__ether 0
-#define R_NETWORK_GEN_CONFIG__vg__BITNR 3
-#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__vg__on 1
-#define R_NETWORK_GEN_CONFIG__vg__off 0
-#define R_NETWORK_GEN_CONFIG__phy__BITNR 1
-#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2
-#define R_NETWORK_GEN_CONFIG__phy__sni 0
-#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1
-#define R_NETWORK_GEN_CONFIG__phy__mii_err 2
-#define R_NETWORK_GEN_CONFIG__phy__mii_req 3
-#define R_NETWORK_GEN_CONFIG__enable__BITNR 0
-#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__enable__on 1
-#define R_NETWORK_GEN_CONFIG__enable__off 0
-
-#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c)
-#define R_NETWORK_TR_CTRL__clr_error__BITNR 8
-#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1
-#define R_NETWORK_TR_CTRL__clr_error__clr 1
-#define R_NETWORK_TR_CTRL__clr_error__nop 0
-#define R_NETWORK_TR_CTRL__delay__BITNR 5
-#define R_NETWORK_TR_CTRL__delay__WIDTH 1
-#define R_NETWORK_TR_CTRL__delay__d2us 1
-#define R_NETWORK_TR_CTRL__delay__none 0
-#define R_NETWORK_TR_CTRL__cancel__BITNR 4
-#define R_NETWORK_TR_CTRL__cancel__WIDTH 1
-#define R_NETWORK_TR_CTRL__cancel__do 1
-#define R_NETWORK_TR_CTRL__cancel__dont 0
-#define R_NETWORK_TR_CTRL__cd__BITNR 3
-#define R_NETWORK_TR_CTRL__cd__WIDTH 1
-#define R_NETWORK_TR_CTRL__cd__enable 0
-#define R_NETWORK_TR_CTRL__cd__disable 1
-#define R_NETWORK_TR_CTRL__cd__ack_col 0
-#define R_NETWORK_TR_CTRL__cd__ack_crs 1
-#define R_NETWORK_TR_CTRL__retry__BITNR 2
-#define R_NETWORK_TR_CTRL__retry__WIDTH 1
-#define R_NETWORK_TR_CTRL__retry__enable 0
-#define R_NETWORK_TR_CTRL__retry__disable 1
-#define R_NETWORK_TR_CTRL__pad__BITNR 1
-#define R_NETWORK_TR_CTRL__pad__WIDTH 1
-#define R_NETWORK_TR_CTRL__pad__enable 1
-#define R_NETWORK_TR_CTRL__pad__disable 0
-#define R_NETWORK_TR_CTRL__crc__BITNR 0
-#define R_NETWORK_TR_CTRL__crc__WIDTH 1
-#define R_NETWORK_TR_CTRL__crc__enable 0
-#define R_NETWORK_TR_CTRL__crc__disable 1
-
-#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0)
-#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
-#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4
-#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
-#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdck__BITNR 2
-#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
-#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdoe__enable 1
-#define R_NETWORK_MGM_CTRL__mdoe__disable 0
-#define R_NETWORK_MGM_CTRL__mdio__BITNR 0
-#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1
-
-#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0)
-#define R_NETWORK_STAT__rxd_pins__BITNR 4
-#define R_NETWORK_STAT__rxd_pins__WIDTH 4
-#define R_NETWORK_STAT__rxer__BITNR 3
-#define R_NETWORK_STAT__rxer__WIDTH 1
-#define R_NETWORK_STAT__underrun__BITNR 2
-#define R_NETWORK_STAT__underrun__WIDTH 1
-#define R_NETWORK_STAT__underrun__yes 1
-#define R_NETWORK_STAT__underrun__no 0
-#define R_NETWORK_STAT__exc_col__BITNR 1
-#define R_NETWORK_STAT__exc_col__WIDTH 1
-#define R_NETWORK_STAT__exc_col__yes 1
-#define R_NETWORK_STAT__exc_col__no 0
-#define R_NETWORK_STAT__mdio__BITNR 0
-#define R_NETWORK_STAT__mdio__WIDTH 1
-
-#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4)
-#define R_REC_COUNTERS__congestion__BITNR 24
-#define R_REC_COUNTERS__congestion__WIDTH 8
-#define R_REC_COUNTERS__oversize__BITNR 16
-#define R_REC_COUNTERS__oversize__WIDTH 8
-#define R_REC_COUNTERS__alignment_error__BITNR 8
-#define R_REC_COUNTERS__alignment_error__WIDTH 8
-#define R_REC_COUNTERS__crc_error__BITNR 0
-#define R_REC_COUNTERS__crc_error__WIDTH 8
-
-#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8)
-#define R_TR_COUNTERS__deferred__BITNR 24
-#define R_TR_COUNTERS__deferred__WIDTH 8
-#define R_TR_COUNTERS__late_col__BITNR 16
-#define R_TR_COUNTERS__late_col__WIDTH 8
-#define R_TR_COUNTERS__multiple_col__BITNR 8
-#define R_TR_COUNTERS__multiple_col__WIDTH 8
-#define R_TR_COUNTERS__single_col__BITNR 0
-#define R_TR_COUNTERS__single_col__WIDTH 8
-
-#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac)
-#define R_PHY_COUNTERS__sqe_test_error__BITNR 8
-#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8
-#define R_PHY_COUNTERS__carrier_loss__BITNR 0
-#define R_PHY_COUNTERS__carrier_loss__WIDTH 8
-
-/*
-!* Parallel printer port registers
-!*/
-
-#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_PAR0_CTRL_DATA__peri_int__BITNR 24
-#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1
-#define R_PAR0_CTRL_DATA__peri_int__ack 1
-#define R_PAR0_CTRL_DATA__peri_int__nop 0
-#define R_PAR0_CTRL_DATA__oe__BITNR 20
-#define R_PAR0_CTRL_DATA__oe__WIDTH 1
-#define R_PAR0_CTRL_DATA__oe__enable 1
-#define R_PAR0_CTRL_DATA__oe__disable 0
-#define R_PAR0_CTRL_DATA__seli__BITNR 19
-#define R_PAR0_CTRL_DATA__seli__WIDTH 1
-#define R_PAR0_CTRL_DATA__seli__active 1
-#define R_PAR0_CTRL_DATA__seli__inactive 0
-#define R_PAR0_CTRL_DATA__autofd__BITNR 18
-#define R_PAR0_CTRL_DATA__autofd__WIDTH 1
-#define R_PAR0_CTRL_DATA__autofd__active 1
-#define R_PAR0_CTRL_DATA__autofd__inactive 0
-#define R_PAR0_CTRL_DATA__strb__BITNR 17
-#define R_PAR0_CTRL_DATA__strb__WIDTH 1
-#define R_PAR0_CTRL_DATA__strb__active 1
-#define R_PAR0_CTRL_DATA__strb__inactive 0
-#define R_PAR0_CTRL_DATA__init__BITNR 16
-#define R_PAR0_CTRL_DATA__init__WIDTH 1
-#define R_PAR0_CTRL_DATA__init__active 1
-#define R_PAR0_CTRL_DATA__init__inactive 0
-#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
-#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1
-#define R_PAR0_CTRL_DATA__ecp_cmd__command 1
-#define R_PAR0_CTRL_DATA__ecp_cmd__data 0
-#define R_PAR0_CTRL_DATA__data__BITNR 0
-#define R_PAR0_CTRL_DATA__data__WIDTH 8
-
-#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042)
-#define R_PAR0_CTRL__ctrl__BITNR 0
-#define R_PAR0_CTRL__ctrl__WIDTH 5
-
-#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
-#define R_PAR0_STATUS_DATA__mode__BITNR 29
-#define R_PAR0_STATUS_DATA__mode__WIDTH 3
-#define R_PAR0_STATUS_DATA__mode__manual 0
-#define R_PAR0_STATUS_DATA__mode__centronics 1
-#define R_PAR0_STATUS_DATA__mode__fastbyte 2
-#define R_PAR0_STATUS_DATA__mode__nibble 3
-#define R_PAR0_STATUS_DATA__mode__byte 4
-#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5
-#define R_PAR0_STATUS_DATA__mode__ecp_rev 6
-#define R_PAR0_STATUS_DATA__mode__off 7
-#define R_PAR0_STATUS_DATA__mode__epp_wr1 5
-#define R_PAR0_STATUS_DATA__mode__epp_wr2 6
-#define R_PAR0_STATUS_DATA__mode__epp_wr3 7
-#define R_PAR0_STATUS_DATA__mode__epp_rd 0
-#define R_PAR0_STATUS_DATA__perr__BITNR 28
-#define R_PAR0_STATUS_DATA__perr__WIDTH 1
-#define R_PAR0_STATUS_DATA__perr__active 1
-#define R_PAR0_STATUS_DATA__perr__inactive 0
-#define R_PAR0_STATUS_DATA__ack__BITNR 27
-#define R_PAR0_STATUS_DATA__ack__WIDTH 1
-#define R_PAR0_STATUS_DATA__ack__active 0
-#define R_PAR0_STATUS_DATA__ack__inactive 1
-#define R_PAR0_STATUS_DATA__busy__BITNR 26
-#define R_PAR0_STATUS_DATA__busy__WIDTH 1
-#define R_PAR0_STATUS_DATA__busy__active 1
-#define R_PAR0_STATUS_DATA__busy__inactive 0
-#define R_PAR0_STATUS_DATA__fault__BITNR 25
-#define R_PAR0_STATUS_DATA__fault__WIDTH 1
-#define R_PAR0_STATUS_DATA__fault__active 0
-#define R_PAR0_STATUS_DATA__fault__inactive 1
-#define R_PAR0_STATUS_DATA__sel__BITNR 24
-#define R_PAR0_STATUS_DATA__sel__WIDTH 1
-#define R_PAR0_STATUS_DATA__sel__active 1
-#define R_PAR0_STATUS_DATA__sel__inactive 0
-#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
-#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1
-#define R_PAR0_STATUS_DATA__ext_mode__enable 1
-#define R_PAR0_STATUS_DATA__ext_mode__disable 0
-#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
-#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1
-#define R_PAR0_STATUS_DATA__ecp_16__active 1
-#define R_PAR0_STATUS_DATA__ecp_16__inactive 0
-#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
-#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_PAR0_STATUS_DATA__tr_rdy__ready 1
-#define R_PAR0_STATUS_DATA__tr_rdy__busy 0
-#define R_PAR0_STATUS_DATA__dav__BITNR 16
-#define R_PAR0_STATUS_DATA__dav__WIDTH 1
-#define R_PAR0_STATUS_DATA__dav__data 1
-#define R_PAR0_STATUS_DATA__dav__nodata 0
-#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
-#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1
-#define R_PAR0_STATUS_DATA__ecp_cmd__command 1
-#define R_PAR0_STATUS_DATA__ecp_cmd__data 0
-#define R_PAR0_STATUS_DATA__data__BITNR 0
-#define R_PAR0_STATUS_DATA__data__WIDTH 8
-
-#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042)
-#define R_PAR0_STATUS__mode__BITNR 13
-#define R_PAR0_STATUS__mode__WIDTH 3
-#define R_PAR0_STATUS__mode__manual 0
-#define R_PAR0_STATUS__mode__centronics 1
-#define R_PAR0_STATUS__mode__fastbyte 2
-#define R_PAR0_STATUS__mode__nibble 3
-#define R_PAR0_STATUS__mode__byte 4
-#define R_PAR0_STATUS__mode__ecp_fwd 5
-#define R_PAR0_STATUS__mode__ecp_rev 6
-#define R_PAR0_STATUS__mode__off 7
-#define R_PAR0_STATUS__mode__epp_wr1 5
-#define R_PAR0_STATUS__mode__epp_wr2 6
-#define R_PAR0_STATUS__mode__epp_wr3 7
-#define R_PAR0_STATUS__mode__epp_rd 0
-#define R_PAR0_STATUS__perr__BITNR 12
-#define R_PAR0_STATUS__perr__WIDTH 1
-#define R_PAR0_STATUS__perr__active 1
-#define R_PAR0_STATUS__perr__inactive 0
-#define R_PAR0_STATUS__ack__BITNR 11
-#define R_PAR0_STATUS__ack__WIDTH 1
-#define R_PAR0_STATUS__ack__active 0
-#define R_PAR0_STATUS__ack__inactive 1
-#define R_PAR0_STATUS__busy__BITNR 10
-#define R_PAR0_STATUS__busy__WIDTH 1
-#define R_PAR0_STATUS__busy__active 1
-#define R_PAR0_STATUS__busy__inactive 0
-#define R_PAR0_STATUS__fault__BITNR 9
-#define R_PAR0_STATUS__fault__WIDTH 1
-#define R_PAR0_STATUS__fault__active 0
-#define R_PAR0_STATUS__fault__inactive 1
-#define R_PAR0_STATUS__sel__BITNR 8
-#define R_PAR0_STATUS__sel__WIDTH 1
-#define R_PAR0_STATUS__sel__active 1
-#define R_PAR0_STATUS__sel__inactive 0
-#define R_PAR0_STATUS__ext_mode__BITNR 7
-#define R_PAR0_STATUS__ext_mode__WIDTH 1
-#define R_PAR0_STATUS__ext_mode__enable 1
-#define R_PAR0_STATUS__ext_mode__disable 0
-#define R_PAR0_STATUS__ecp_16__BITNR 6
-#define R_PAR0_STATUS__ecp_16__WIDTH 1
-#define R_PAR0_STATUS__ecp_16__active 1
-#define R_PAR0_STATUS__ecp_16__inactive 0
-#define R_PAR0_STATUS__tr_rdy__BITNR 1
-#define R_PAR0_STATUS__tr_rdy__WIDTH 1
-#define R_PAR0_STATUS__tr_rdy__ready 1
-#define R_PAR0_STATUS__tr_rdy__busy 0
-#define R_PAR0_STATUS__dav__BITNR 0
-#define R_PAR0_STATUS__dav__WIDTH 1
-#define R_PAR0_STATUS__dav__data 1
-#define R_PAR0_STATUS__dav__nodata 0
-
-#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040)
-#define R_PAR_ECP16_DATA__data__BITNR 0
-#define R_PAR_ECP16_DATA__data__WIDTH 16
-
-#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_PAR0_CONFIG__ioe__BITNR 25
-#define R_PAR0_CONFIG__ioe__WIDTH 1
-#define R_PAR0_CONFIG__ioe__inv 1
-#define R_PAR0_CONFIG__ioe__noninv 0
-#define R_PAR0_CONFIG__iseli__BITNR 24
-#define R_PAR0_CONFIG__iseli__WIDTH 1
-#define R_PAR0_CONFIG__iseli__inv 1
-#define R_PAR0_CONFIG__iseli__noninv 0
-#define R_PAR0_CONFIG__iautofd__BITNR 23
-#define R_PAR0_CONFIG__iautofd__WIDTH 1
-#define R_PAR0_CONFIG__iautofd__inv 1
-#define R_PAR0_CONFIG__iautofd__noninv 0
-#define R_PAR0_CONFIG__istrb__BITNR 22
-#define R_PAR0_CONFIG__istrb__WIDTH 1
-#define R_PAR0_CONFIG__istrb__inv 1
-#define R_PAR0_CONFIG__istrb__noninv 0
-#define R_PAR0_CONFIG__iinit__BITNR 21
-#define R_PAR0_CONFIG__iinit__WIDTH 1
-#define R_PAR0_CONFIG__iinit__inv 1
-#define R_PAR0_CONFIG__iinit__noninv 0
-#define R_PAR0_CONFIG__iperr__BITNR 20
-#define R_PAR0_CONFIG__iperr__WIDTH 1
-#define R_PAR0_CONFIG__iperr__inv 1
-#define R_PAR0_CONFIG__iperr__noninv 0
-#define R_PAR0_CONFIG__iack__BITNR 19
-#define R_PAR0_CONFIG__iack__WIDTH 1
-#define R_PAR0_CONFIG__iack__inv 1
-#define R_PAR0_CONFIG__iack__noninv 0
-#define R_PAR0_CONFIG__ibusy__BITNR 18
-#define R_PAR0_CONFIG__ibusy__WIDTH 1
-#define R_PAR0_CONFIG__ibusy__inv 1
-#define R_PAR0_CONFIG__ibusy__noninv 0
-#define R_PAR0_CONFIG__ifault__BITNR 17
-#define R_PAR0_CONFIG__ifault__WIDTH 1
-#define R_PAR0_CONFIG__ifault__inv 1
-#define R_PAR0_CONFIG__ifault__noninv 0
-#define R_PAR0_CONFIG__isel__BITNR 16
-#define R_PAR0_CONFIG__isel__WIDTH 1
-#define R_PAR0_CONFIG__isel__inv 1
-#define R_PAR0_CONFIG__isel__noninv 0
-#define R_PAR0_CONFIG__ext_mode__BITNR 11
-#define R_PAR0_CONFIG__ext_mode__WIDTH 1
-#define R_PAR0_CONFIG__ext_mode__enable 1
-#define R_PAR0_CONFIG__ext_mode__disable 0
-#define R_PAR0_CONFIG__wide__BITNR 10
-#define R_PAR0_CONFIG__wide__WIDTH 1
-#define R_PAR0_CONFIG__wide__enable 1
-#define R_PAR0_CONFIG__wide__disable 0
-#define R_PAR0_CONFIG__dma__BITNR 9
-#define R_PAR0_CONFIG__dma__WIDTH 1
-#define R_PAR0_CONFIG__dma__enable 1
-#define R_PAR0_CONFIG__dma__disable 0
-#define R_PAR0_CONFIG__rle_in__BITNR 8
-#define R_PAR0_CONFIG__rle_in__WIDTH 1
-#define R_PAR0_CONFIG__rle_in__enable 1
-#define R_PAR0_CONFIG__rle_in__disable 0
-#define R_PAR0_CONFIG__rle_out__BITNR 7
-#define R_PAR0_CONFIG__rle_out__WIDTH 1
-#define R_PAR0_CONFIG__rle_out__enable 1
-#define R_PAR0_CONFIG__rle_out__disable 0
-#define R_PAR0_CONFIG__enable__BITNR 6
-#define R_PAR0_CONFIG__enable__WIDTH 1
-#define R_PAR0_CONFIG__enable__on 1
-#define R_PAR0_CONFIG__enable__reset 0
-#define R_PAR0_CONFIG__force__BITNR 5
-#define R_PAR0_CONFIG__force__WIDTH 1
-#define R_PAR0_CONFIG__force__on 1
-#define R_PAR0_CONFIG__force__off 0
-#define R_PAR0_CONFIG__ign_ack__BITNR 4
-#define R_PAR0_CONFIG__ign_ack__WIDTH 1
-#define R_PAR0_CONFIG__ign_ack__ignore 1
-#define R_PAR0_CONFIG__ign_ack__wait 0
-#define R_PAR0_CONFIG__oe_ack__BITNR 3
-#define R_PAR0_CONFIG__oe_ack__WIDTH 1
-#define R_PAR0_CONFIG__oe_ack__wait_oe 1
-#define R_PAR0_CONFIG__oe_ack__dont_wait 0
-#define R_PAR0_CONFIG__oe_ack__epp_addr 1
-#define R_PAR0_CONFIG__oe_ack__epp_data 0
-#define R_PAR0_CONFIG__epp_addr_data__BITNR 3
-#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1
-#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1
-#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0
-#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1
-#define R_PAR0_CONFIG__epp_addr_data__epp_data 0
-#define R_PAR0_CONFIG__mode__BITNR 0
-#define R_PAR0_CONFIG__mode__WIDTH 3
-#define R_PAR0_CONFIG__mode__manual 0
-#define R_PAR0_CONFIG__mode__centronics 1
-#define R_PAR0_CONFIG__mode__fastbyte 2
-#define R_PAR0_CONFIG__mode__nibble 3
-#define R_PAR0_CONFIG__mode__byte 4
-#define R_PAR0_CONFIG__mode__ecp_fwd 5
-#define R_PAR0_CONFIG__mode__ecp_rev 6
-#define R_PAR0_CONFIG__mode__off 7
-#define R_PAR0_CONFIG__mode__epp_wr1 5
-#define R_PAR0_CONFIG__mode__epp_wr2 6
-#define R_PAR0_CONFIG__mode__epp_wr3 7
-#define R_PAR0_CONFIG__mode__epp_rd 0
-
-#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048)
-#define R_PAR0_DELAY__fine_hold__BITNR 21
-#define R_PAR0_DELAY__fine_hold__WIDTH 3
-#define R_PAR0_DELAY__hold__BITNR 16
-#define R_PAR0_DELAY__hold__WIDTH 5
-#define R_PAR0_DELAY__fine_strb__BITNR 13
-#define R_PAR0_DELAY__fine_strb__WIDTH 3
-#define R_PAR0_DELAY__strobe__BITNR 8
-#define R_PAR0_DELAY__strobe__WIDTH 5
-#define R_PAR0_DELAY__fine_setup__BITNR 5
-#define R_PAR0_DELAY__fine_setup__WIDTH 3
-#define R_PAR0_DELAY__setup__BITNR 0
-#define R_PAR0_DELAY__setup__WIDTH 5
-
-#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050)
-#define R_PAR1_CTRL_DATA__peri_int__BITNR 24
-#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1
-#define R_PAR1_CTRL_DATA__peri_int__ack 1
-#define R_PAR1_CTRL_DATA__peri_int__nop 0
-#define R_PAR1_CTRL_DATA__oe__BITNR 20
-#define R_PAR1_CTRL_DATA__oe__WIDTH 1
-#define R_PAR1_CTRL_DATA__oe__enable 1
-#define R_PAR1_CTRL_DATA__oe__disable 0
-#define R_PAR1_CTRL_DATA__seli__BITNR 19
-#define R_PAR1_CTRL_DATA__seli__WIDTH 1
-#define R_PAR1_CTRL_DATA__seli__active 1
-#define R_PAR1_CTRL_DATA__seli__inactive 0
-#define R_PAR1_CTRL_DATA__autofd__BITNR 18
-#define R_PAR1_CTRL_DATA__autofd__WIDTH 1
-#define R_PAR1_CTRL_DATA__autofd__active 1
-#define R_PAR1_CTRL_DATA__autofd__inactive 0
-#define R_PAR1_CTRL_DATA__strb__BITNR 17
-#define R_PAR1_CTRL_DATA__strb__WIDTH 1
-#define R_PAR1_CTRL_DATA__strb__active 1
-#define R_PAR1_CTRL_DATA__strb__inactive 0
-#define R_PAR1_CTRL_DATA__init__BITNR 16
-#define R_PAR1_CTRL_DATA__init__WIDTH 1
-#define R_PAR1_CTRL_DATA__init__active 1
-#define R_PAR1_CTRL_DATA__init__inactive 0
-#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
-#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1
-#define R_PAR1_CTRL_DATA__ecp_cmd__command 1
-#define R_PAR1_CTRL_DATA__ecp_cmd__data 0
-#define R_PAR1_CTRL_DATA__data__BITNR 0
-#define R_PAR1_CTRL_DATA__data__WIDTH 8
-
-#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052)
-#define R_PAR1_CTRL__ctrl__BITNR 0
-#define R_PAR1_CTRL__ctrl__WIDTH 5
-
-#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050)
-#define R_PAR1_STATUS_DATA__mode__BITNR 29
-#define R_PAR1_STATUS_DATA__mode__WIDTH 3
-#define R_PAR1_STATUS_DATA__mode__manual 0
-#define R_PAR1_STATUS_DATA__mode__centronics 1
-#define R_PAR1_STATUS_DATA__mode__fastbyte 2
-#define R_PAR1_STATUS_DATA__mode__nibble 3
-#define R_PAR1_STATUS_DATA__mode__byte 4
-#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5
-#define R_PAR1_STATUS_DATA__mode__ecp_rev 6
-#define R_PAR1_STATUS_DATA__mode__off 7
-#define R_PAR1_STATUS_DATA__mode__epp_wr1 5
-#define R_PAR1_STATUS_DATA__mode__epp_wr2 6
-#define R_PAR1_STATUS_DATA__mode__epp_wr3 7
-#define R_PAR1_STATUS_DATA__mode__epp_rd 0
-#define R_PAR1_STATUS_DATA__perr__BITNR 28
-#define R_PAR1_STATUS_DATA__perr__WIDTH 1
-#define R_PAR1_STATUS_DATA__perr__active 1
-#define R_PAR1_STATUS_DATA__perr__inactive 0
-#define R_PAR1_STATUS_DATA__ack__BITNR 27
-#define R_PAR1_STATUS_DATA__ack__WIDTH 1
-#define R_PAR1_STATUS_DATA__ack__active 0
-#define R_PAR1_STATUS_DATA__ack__inactive 1
-#define R_PAR1_STATUS_DATA__busy__BITNR 26
-#define R_PAR1_STATUS_DATA__busy__WIDTH 1
-#define R_PAR1_STATUS_DATA__busy__active 1
-#define R_PAR1_STATUS_DATA__busy__inactive 0
-#define R_PAR1_STATUS_DATA__fault__BITNR 25
-#define R_PAR1_STATUS_DATA__fault__WIDTH 1
-#define R_PAR1_STATUS_DATA__fault__active 0
-#define R_PAR1_STATUS_DATA__fault__inactive 1
-#define R_PAR1_STATUS_DATA__sel__BITNR 24
-#define R_PAR1_STATUS_DATA__sel__WIDTH 1
-#define R_PAR1_STATUS_DATA__sel__active 1
-#define R_PAR1_STATUS_DATA__sel__inactive 0
-#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
-#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1
-#define R_PAR1_STATUS_DATA__ext_mode__enable 1
-#define R_PAR1_STATUS_DATA__ext_mode__disable 0
-#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
-#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_PAR1_STATUS_DATA__tr_rdy__ready 1
-#define R_PAR1_STATUS_DATA__tr_rdy__busy 0
-#define R_PAR1_STATUS_DATA__dav__BITNR 16
-#define R_PAR1_STATUS_DATA__dav__WIDTH 1
-#define R_PAR1_STATUS_DATA__dav__data 1
-#define R_PAR1_STATUS_DATA__dav__nodata 0
-#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
-#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1
-#define R_PAR1_STATUS_DATA__ecp_cmd__command 1
-#define R_PAR1_STATUS_DATA__ecp_cmd__data 0
-#define R_PAR1_STATUS_DATA__data__BITNR 0
-#define R_PAR1_STATUS_DATA__data__WIDTH 8
-
-#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052)
-#define R_PAR1_STATUS__mode__BITNR 13
-#define R_PAR1_STATUS__mode__WIDTH 3
-#define R_PAR1_STATUS__mode__manual 0
-#define R_PAR1_STATUS__mode__centronics 1
-#define R_PAR1_STATUS__mode__fastbyte 2
-#define R_PAR1_STATUS__mode__nibble 3
-#define R_PAR1_STATUS__mode__byte 4
-#define R_PAR1_STATUS__mode__ecp_fwd 5
-#define R_PAR1_STATUS__mode__ecp_rev 6
-#define R_PAR1_STATUS__mode__off 7
-#define R_PAR1_STATUS__mode__epp_wr1 5
-#define R_PAR1_STATUS__mode__epp_wr2 6
-#define R_PAR1_STATUS__mode__epp_wr3 7
-#define R_PAR1_STATUS__mode__epp_rd 0
-#define R_PAR1_STATUS__perr__BITNR 12
-#define R_PAR1_STATUS__perr__WIDTH 1
-#define R_PAR1_STATUS__perr__active 1
-#define R_PAR1_STATUS__perr__inactive 0
-#define R_PAR1_STATUS__ack__BITNR 11
-#define R_PAR1_STATUS__ack__WIDTH 1
-#define R_PAR1_STATUS__ack__active 0
-#define R_PAR1_STATUS__ack__inactive 1
-#define R_PAR1_STATUS__busy__BITNR 10
-#define R_PAR1_STATUS__busy__WIDTH 1
-#define R_PAR1_STATUS__busy__active 1
-#define R_PAR1_STATUS__busy__inactive 0
-#define R_PAR1_STATUS__fault__BITNR 9
-#define R_PAR1_STATUS__fault__WIDTH 1
-#define R_PAR1_STATUS__fault__active 0
-#define R_PAR1_STATUS__fault__inactive 1
-#define R_PAR1_STATUS__sel__BITNR 8
-#define R_PAR1_STATUS__sel__WIDTH 1
-#define R_PAR1_STATUS__sel__active 1
-#define R_PAR1_STATUS__sel__inactive 0
-#define R_PAR1_STATUS__ext_mode__BITNR 7
-#define R_PAR1_STATUS__ext_mode__WIDTH 1
-#define R_PAR1_STATUS__ext_mode__enable 1
-#define R_PAR1_STATUS__ext_mode__disable 0
-#define R_PAR1_STATUS__tr_rdy__BITNR 1
-#define R_PAR1_STATUS__tr_rdy__WIDTH 1
-#define R_PAR1_STATUS__tr_rdy__ready 1
-#define R_PAR1_STATUS__tr_rdy__busy 0
-#define R_PAR1_STATUS__dav__BITNR 0
-#define R_PAR1_STATUS__dav__WIDTH 1
-#define R_PAR1_STATUS__dav__data 1
-#define R_PAR1_STATUS__dav__nodata 0
-
-#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054)
-#define R_PAR1_CONFIG__ioe__BITNR 25
-#define R_PAR1_CONFIG__ioe__WIDTH 1
-#define R_PAR1_CONFIG__ioe__inv 1
-#define R_PAR1_CONFIG__ioe__noninv 0
-#define R_PAR1_CONFIG__iseli__BITNR 24
-#define R_PAR1_CONFIG__iseli__WIDTH 1
-#define R_PAR1_CONFIG__iseli__inv 1
-#define R_PAR1_CONFIG__iseli__noninv 0
-#define R_PAR1_CONFIG__iautofd__BITNR 23
-#define R_PAR1_CONFIG__iautofd__WIDTH 1
-#define R_PAR1_CONFIG__iautofd__inv 1
-#define R_PAR1_CONFIG__iautofd__noninv 0
-#define R_PAR1_CONFIG__istrb__BITNR 22
-#define R_PAR1_CONFIG__istrb__WIDTH 1
-#define R_PAR1_CONFIG__istrb__inv 1
-#define R_PAR1_CONFIG__istrb__noninv 0
-#define R_PAR1_CONFIG__iinit__BITNR 21
-#define R_PAR1_CONFIG__iinit__WIDTH 1
-#define R_PAR1_CONFIG__iinit__inv 1
-#define R_PAR1_CONFIG__iinit__noninv 0
-#define R_PAR1_CONFIG__iperr__BITNR 20
-#define R_PAR1_CONFIG__iperr__WIDTH 1
-#define R_PAR1_CONFIG__iperr__inv 1
-#define R_PAR1_CONFIG__iperr__noninv 0
-#define R_PAR1_CONFIG__iack__BITNR 19
-#define R_PAR1_CONFIG__iack__WIDTH 1
-#define R_PAR1_CONFIG__iack__inv 1
-#define R_PAR1_CONFIG__iack__noninv 0
-#define R_PAR1_CONFIG__ibusy__BITNR 18
-#define R_PAR1_CONFIG__ibusy__WIDTH 1
-#define R_PAR1_CONFIG__ibusy__inv 1
-#define R_PAR1_CONFIG__ibusy__noninv 0
-#define R_PAR1_CONFIG__ifault__BITNR 17
-#define R_PAR1_CONFIG__ifault__WIDTH 1
-#define R_PAR1_CONFIG__ifault__inv 1
-#define R_PAR1_CONFIG__ifault__noninv 0
-#define R_PAR1_CONFIG__isel__BITNR 16
-#define R_PAR1_CONFIG__isel__WIDTH 1
-#define R_PAR1_CONFIG__isel__inv 1
-#define R_PAR1_CONFIG__isel__noninv 0
-#define R_PAR1_CONFIG__ext_mode__BITNR 11
-#define R_PAR1_CONFIG__ext_mode__WIDTH 1
-#define R_PAR1_CONFIG__ext_mode__enable 1
-#define R_PAR1_CONFIG__ext_mode__disable 0
-#define R_PAR1_CONFIG__dma__BITNR 9
-#define R_PAR1_CONFIG__dma__WIDTH 1
-#define R_PAR1_CONFIG__dma__enable 1
-#define R_PAR1_CONFIG__dma__disable 0
-#define R_PAR1_CONFIG__rle_in__BITNR 8
-#define R_PAR1_CONFIG__rle_in__WIDTH 1
-#define R_PAR1_CONFIG__rle_in__enable 1
-#define R_PAR1_CONFIG__rle_in__disable 0
-#define R_PAR1_CONFIG__rle_out__BITNR 7
-#define R_PAR1_CONFIG__rle_out__WIDTH 1
-#define R_PAR1_CONFIG__rle_out__enable 1
-#define R_PAR1_CONFIG__rle_out__disable 0
-#define R_PAR1_CONFIG__enable__BITNR 6
-#define R_PAR1_CONFIG__enable__WIDTH 1
-#define R_PAR1_CONFIG__enable__on 1
-#define R_PAR1_CONFIG__enable__reset 0
-#define R_PAR1_CONFIG__force__BITNR 5
-#define R_PAR1_CONFIG__force__WIDTH 1
-#define R_PAR1_CONFIG__force__on 1
-#define R_PAR1_CONFIG__force__off 0
-#define R_PAR1_CONFIG__ign_ack__BITNR 4
-#define R_PAR1_CONFIG__ign_ack__WIDTH 1
-#define R_PAR1_CONFIG__ign_ack__ignore 1
-#define R_PAR1_CONFIG__ign_ack__wait 0
-#define R_PAR1_CONFIG__oe_ack__BITNR 3
-#define R_PAR1_CONFIG__oe_ack__WIDTH 1
-#define R_PAR1_CONFIG__oe_ack__wait_oe 1
-#define R_PAR1_CONFIG__oe_ack__dont_wait 0
-#define R_PAR1_CONFIG__oe_ack__epp_addr 1
-#define R_PAR1_CONFIG__oe_ack__epp_data 0
-#define R_PAR1_CONFIG__epp_addr_data__BITNR 3
-#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1
-#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1
-#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0
-#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1
-#define R_PAR1_CONFIG__epp_addr_data__epp_data 0
-#define R_PAR1_CONFIG__mode__BITNR 0
-#define R_PAR1_CONFIG__mode__WIDTH 3
-#define R_PAR1_CONFIG__mode__manual 0
-#define R_PAR1_CONFIG__mode__centronics 1
-#define R_PAR1_CONFIG__mode__fastbyte 2
-#define R_PAR1_CONFIG__mode__nibble 3
-#define R_PAR1_CONFIG__mode__byte 4
-#define R_PAR1_CONFIG__mode__ecp_fwd 5
-#define R_PAR1_CONFIG__mode__ecp_rev 6
-#define R_PAR1_CONFIG__mode__off 7
-#define R_PAR1_CONFIG__mode__epp_wr1 5
-#define R_PAR1_CONFIG__mode__epp_wr2 6
-#define R_PAR1_CONFIG__mode__epp_wr3 7
-#define R_PAR1_CONFIG__mode__epp_rd 0
-
-#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058)
-#define R_PAR1_DELAY__fine_hold__BITNR 21
-#define R_PAR1_DELAY__fine_hold__WIDTH 3
-#define R_PAR1_DELAY__hold__BITNR 16
-#define R_PAR1_DELAY__hold__WIDTH 5
-#define R_PAR1_DELAY__fine_strb__BITNR 13
-#define R_PAR1_DELAY__fine_strb__WIDTH 3
-#define R_PAR1_DELAY__strobe__BITNR 8
-#define R_PAR1_DELAY__strobe__WIDTH 5
-#define R_PAR1_DELAY__fine_setup__BITNR 5
-#define R_PAR1_DELAY__fine_setup__WIDTH 3
-#define R_PAR1_DELAY__setup__BITNR 0
-#define R_PAR1_DELAY__setup__WIDTH 5
-
-/*
-!* ATA interface registers
-!*/
-
-#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_ATA_CTRL_DATA__sel__BITNR 30
-#define R_ATA_CTRL_DATA__sel__WIDTH 2
-#define R_ATA_CTRL_DATA__cs1__BITNR 29
-#define R_ATA_CTRL_DATA__cs1__WIDTH 1
-#define R_ATA_CTRL_DATA__cs1__active 1
-#define R_ATA_CTRL_DATA__cs1__inactive 0
-#define R_ATA_CTRL_DATA__cs0__BITNR 28
-#define R_ATA_CTRL_DATA__cs0__WIDTH 1
-#define R_ATA_CTRL_DATA__cs0__active 1
-#define R_ATA_CTRL_DATA__cs0__inactive 0
-#define R_ATA_CTRL_DATA__addr__BITNR 25
-#define R_ATA_CTRL_DATA__addr__WIDTH 3
-#define R_ATA_CTRL_DATA__rw__BITNR 24
-#define R_ATA_CTRL_DATA__rw__WIDTH 1
-#define R_ATA_CTRL_DATA__rw__read 1
-#define R_ATA_CTRL_DATA__rw__write 0
-#define R_ATA_CTRL_DATA__src_dst__BITNR 23
-#define R_ATA_CTRL_DATA__src_dst__WIDTH 1
-#define R_ATA_CTRL_DATA__src_dst__dma 1
-#define R_ATA_CTRL_DATA__src_dst__register 0
-#define R_ATA_CTRL_DATA__handsh__BITNR 22
-#define R_ATA_CTRL_DATA__handsh__WIDTH 1
-#define R_ATA_CTRL_DATA__handsh__dma 1
-#define R_ATA_CTRL_DATA__handsh__pio 0
-#define R_ATA_CTRL_DATA__multi__BITNR 21
-#define R_ATA_CTRL_DATA__multi__WIDTH 1
-#define R_ATA_CTRL_DATA__multi__on 1
-#define R_ATA_CTRL_DATA__multi__off 0
-#define R_ATA_CTRL_DATA__dma_size__BITNR 20
-#define R_ATA_CTRL_DATA__dma_size__WIDTH 1
-#define R_ATA_CTRL_DATA__dma_size__byte 1
-#define R_ATA_CTRL_DATA__dma_size__word 0
-#define R_ATA_CTRL_DATA__data__BITNR 0
-#define R_ATA_CTRL_DATA__data__WIDTH 16
-
-#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
-#define R_ATA_STATUS_DATA__busy__BITNR 18
-#define R_ATA_STATUS_DATA__busy__WIDTH 1
-#define R_ATA_STATUS_DATA__busy__yes 1
-#define R_ATA_STATUS_DATA__busy__no 0
-#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
-#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_ATA_STATUS_DATA__tr_rdy__ready 1
-#define R_ATA_STATUS_DATA__tr_rdy__busy 0
-#define R_ATA_STATUS_DATA__dav__BITNR 16
-#define R_ATA_STATUS_DATA__dav__WIDTH 1
-#define R_ATA_STATUS_DATA__dav__data 1
-#define R_ATA_STATUS_DATA__dav__nodata 0
-#define R_ATA_STATUS_DATA__data__BITNR 0
-#define R_ATA_STATUS_DATA__data__WIDTH 16
-
-#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_ATA_CONFIG__enable__BITNR 25
-#define R_ATA_CONFIG__enable__WIDTH 1
-#define R_ATA_CONFIG__enable__on 1
-#define R_ATA_CONFIG__enable__off 0
-#define R_ATA_CONFIG__dma_strobe__BITNR 20
-#define R_ATA_CONFIG__dma_strobe__WIDTH 5
-#define R_ATA_CONFIG__dma_hold__BITNR 15
-#define R_ATA_CONFIG__dma_hold__WIDTH 5
-#define R_ATA_CONFIG__pio_setup__BITNR 10
-#define R_ATA_CONFIG__pio_setup__WIDTH 5
-#define R_ATA_CONFIG__pio_strobe__BITNR 5
-#define R_ATA_CONFIG__pio_strobe__WIDTH 5
-#define R_ATA_CONFIG__pio_hold__BITNR 0
-#define R_ATA_CONFIG__pio_hold__WIDTH 5
-
-#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048)
-#define R_ATA_TRANSFER_CNT__count__BITNR 0
-#define R_ATA_TRANSFER_CNT__count__WIDTH 17
-
-/*
-!* SCSI registers
-!*/
-
-#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_SCSI0_CTRL__id_type__BITNR 31
-#define R_SCSI0_CTRL__id_type__WIDTH 1
-#define R_SCSI0_CTRL__id_type__software 1
-#define R_SCSI0_CTRL__id_type__hardware 0
-#define R_SCSI0_CTRL__sel_timeout__BITNR 24
-#define R_SCSI0_CTRL__sel_timeout__WIDTH 7
-#define R_SCSI0_CTRL__synch_per__BITNR 16
-#define R_SCSI0_CTRL__synch_per__WIDTH 8
-#define R_SCSI0_CTRL__rst__BITNR 15
-#define R_SCSI0_CTRL__rst__WIDTH 1
-#define R_SCSI0_CTRL__rst__yes 1
-#define R_SCSI0_CTRL__rst__no 0
-#define R_SCSI0_CTRL__atn__BITNR 14
-#define R_SCSI0_CTRL__atn__WIDTH 1
-#define R_SCSI0_CTRL__atn__yes 1
-#define R_SCSI0_CTRL__atn__no 0
-#define R_SCSI0_CTRL__my_id__BITNR 9
-#define R_SCSI0_CTRL__my_id__WIDTH 4
-#define R_SCSI0_CTRL__target_id__BITNR 4
-#define R_SCSI0_CTRL__target_id__WIDTH 4
-#define R_SCSI0_CTRL__fast_20__BITNR 3
-#define R_SCSI0_CTRL__fast_20__WIDTH 1
-#define R_SCSI0_CTRL__fast_20__yes 1
-#define R_SCSI0_CTRL__fast_20__no 0
-#define R_SCSI0_CTRL__bus_width__BITNR 2
-#define R_SCSI0_CTRL__bus_width__WIDTH 1
-#define R_SCSI0_CTRL__bus_width__wide 1
-#define R_SCSI0_CTRL__bus_width__narrow 0
-#define R_SCSI0_CTRL__synch__BITNR 1
-#define R_SCSI0_CTRL__synch__WIDTH 1
-#define R_SCSI0_CTRL__synch__synch 1
-#define R_SCSI0_CTRL__synch__asynch 0
-#define R_SCSI0_CTRL__enable__BITNR 0
-#define R_SCSI0_CTRL__enable__WIDTH 1
-#define R_SCSI0_CTRL__enable__on 1
-#define R_SCSI0_CTRL__enable__off 0
-
-#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_SCSI0_CMD_DATA__parity_in__BITNR 26
-#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1
-#define R_SCSI0_CMD_DATA__parity_in__on 0
-#define R_SCSI0_CMD_DATA__parity_in__off 1
-#define R_SCSI0_CMD_DATA__skip__BITNR 25
-#define R_SCSI0_CMD_DATA__skip__WIDTH 1
-#define R_SCSI0_CMD_DATA__skip__on 1
-#define R_SCSI0_CMD_DATA__skip__off 0
-#define R_SCSI0_CMD_DATA__clr_status__BITNR 24
-#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1
-#define R_SCSI0_CMD_DATA__clr_status__yes 1
-#define R_SCSI0_CMD_DATA__clr_status__nop 0
-#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
-#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4
-#define R_SCSI0_CMD_DATA__command__BITNR 16
-#define R_SCSI0_CMD_DATA__command__WIDTH 4
-#define R_SCSI0_CMD_DATA__command__full_din_1 0
-#define R_SCSI0_CMD_DATA__command__full_dout_1 1
-#define R_SCSI0_CMD_DATA__command__full_stat_1 2
-#define R_SCSI0_CMD_DATA__command__resel_din 3
-#define R_SCSI0_CMD_DATA__command__resel_dout 4
-#define R_SCSI0_CMD_DATA__command__resel_stat 5
-#define R_SCSI0_CMD_DATA__command__arb_only 6
-#define R_SCSI0_CMD_DATA__command__full_din_3 8
-#define R_SCSI0_CMD_DATA__command__full_dout_3 9
-#define R_SCSI0_CMD_DATA__command__full_stat_3 10
-#define R_SCSI0_CMD_DATA__command__man_data_in 11
-#define R_SCSI0_CMD_DATA__command__man_data_out 12
-#define R_SCSI0_CMD_DATA__command__man_rat 13
-#define R_SCSI0_CMD_DATA__data_out__BITNR 0
-#define R_SCSI0_CMD_DATA__data_out__WIDTH 16
-
-#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040)
-#define R_SCSI0_DATA__data_out__BITNR 0
-#define R_SCSI0_DATA__data_out__WIDTH 16
-
-#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042)
-#define R_SCSI0_CMD__asynch_setup__BITNR 4
-#define R_SCSI0_CMD__asynch_setup__WIDTH 4
-#define R_SCSI0_CMD__command__BITNR 0
-#define R_SCSI0_CMD__command__WIDTH 4
-#define R_SCSI0_CMD__command__full_din_1 0
-#define R_SCSI0_CMD__command__full_dout_1 1
-#define R_SCSI0_CMD__command__full_stat_1 2
-#define R_SCSI0_CMD__command__resel_din 3
-#define R_SCSI0_CMD__command__resel_dout 4
-#define R_SCSI0_CMD__command__resel_stat 5
-#define R_SCSI0_CMD__command__arb_only 6
-#define R_SCSI0_CMD__command__full_din_3 8
-#define R_SCSI0_CMD__command__full_dout_3 9
-#define R_SCSI0_CMD__command__full_stat_3 10
-#define R_SCSI0_CMD__command__man_data_in 11
-#define R_SCSI0_CMD__command__man_data_out 12
-#define R_SCSI0_CMD__command__man_rat 13
-
-#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043)
-#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
-#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__parity_in__on 0
-#define R_SCSI0_STATUS_CTRL__parity_in__off 1
-#define R_SCSI0_STATUS_CTRL__skip__BITNR 1
-#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__skip__on 1
-#define R_SCSI0_STATUS_CTRL__skip__off 0
-#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
-#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__clr_status__yes 1
-#define R_SCSI0_STATUS_CTRL__clr_status__nop 0
-
-#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048)
-#define R_SCSI0_STATUS__tst_arb_won__BITNR 23
-#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1
-#define R_SCSI0_STATUS__tst_resel__BITNR 22
-#define R_SCSI0_STATUS__tst_resel__WIDTH 1
-#define R_SCSI0_STATUS__parity_error__BITNR 21
-#define R_SCSI0_STATUS__parity_error__WIDTH 1
-#define R_SCSI0_STATUS__bus_reset__BITNR 20
-#define R_SCSI0_STATUS__bus_reset__WIDTH 1
-#define R_SCSI0_STATUS__bus_reset__yes 1
-#define R_SCSI0_STATUS__bus_reset__no 0
-#define R_SCSI0_STATUS__resel_target__BITNR 15
-#define R_SCSI0_STATUS__resel_target__WIDTH 4
-#define R_SCSI0_STATUS__resel__BITNR 14
-#define R_SCSI0_STATUS__resel__WIDTH 1
-#define R_SCSI0_STATUS__resel__yes 1
-#define R_SCSI0_STATUS__resel__no 0
-#define R_SCSI0_STATUS__curr_phase__BITNR 11
-#define R_SCSI0_STATUS__curr_phase__WIDTH 3
-#define R_SCSI0_STATUS__curr_phase__ph_undef 0
-#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7
-#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6
-#define R_SCSI0_STATUS__curr_phase__ph_status 3
-#define R_SCSI0_STATUS__curr_phase__ph_command 2
-#define R_SCSI0_STATUS__curr_phase__ph_data_in 5
-#define R_SCSI0_STATUS__curr_phase__ph_data_out 4
-#define R_SCSI0_STATUS__curr_phase__ph_resel 1
-#define R_SCSI0_STATUS__last_seq_step__BITNR 6
-#define R_SCSI0_STATUS__last_seq_step__WIDTH 5
-#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24
-#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8
-#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29
-#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2
-#define R_SCSI0_STATUS__last_seq_step__st_manual 28
-#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30
-#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6
-#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22
-#define R_SCSI0_STATUS__last_seq_step__st_answer 3
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1
-#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15
-#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9
-#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11
-#define R_SCSI0_STATUS__last_seq_step__st_iwr 27
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21
-#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7
-#define R_SCSI0_STATUS__last_seq_step__st_cc 31
-#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14
-#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16
-#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10
-#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18
-#define R_SCSI0_STATUS__valid_status__BITNR 5
-#define R_SCSI0_STATUS__valid_status__WIDTH 1
-#define R_SCSI0_STATUS__valid_status__yes 1
-#define R_SCSI0_STATUS__valid_status__no 0
-#define R_SCSI0_STATUS__seq_status__BITNR 0
-#define R_SCSI0_STATUS__seq_status__WIDTH 5
-#define R_SCSI0_STATUS__seq_status__info_seq_complete 0
-#define R_SCSI0_STATUS__seq_status__info_parity_error 1
-#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2
-#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3
-#define R_SCSI0_STATUS__seq_status__info_arb_lost 4
-#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5
-#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6
-#define R_SCSI0_STATUS__seq_status__info_illegal_op 7
-#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8
-#define R_SCSI0_STATUS__seq_status__info_reselected 9
-#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10
-#define R_SCSI0_STATUS__seq_status__info_bus_reset 11
-#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12
-#define R_SCSI0_STATUS__seq_status__info_bus_free 13
-
-#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040)
-#define R_SCSI0_DATA_IN__data_in__BITNR 0
-#define R_SCSI0_DATA_IN__data_in__WIDTH 16
-
-#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054)
-#define R_SCSI1_CTRL__id_type__BITNR 31
-#define R_SCSI1_CTRL__id_type__WIDTH 1
-#define R_SCSI1_CTRL__id_type__software 1
-#define R_SCSI1_CTRL__id_type__hardware 0
-#define R_SCSI1_CTRL__sel_timeout__BITNR 24
-#define R_SCSI1_CTRL__sel_timeout__WIDTH 7
-#define R_SCSI1_CTRL__synch_per__BITNR 16
-#define R_SCSI1_CTRL__synch_per__WIDTH 8
-#define R_SCSI1_CTRL__rst__BITNR 15
-#define R_SCSI1_CTRL__rst__WIDTH 1
-#define R_SCSI1_CTRL__rst__yes 1
-#define R_SCSI1_CTRL__rst__no 0
-#define R_SCSI1_CTRL__atn__BITNR 14
-#define R_SCSI1_CTRL__atn__WIDTH 1
-#define R_SCSI1_CTRL__atn__yes 1
-#define R_SCSI1_CTRL__atn__no 0
-#define R_SCSI1_CTRL__my_id__BITNR 9
-#define R_SCSI1_CTRL__my_id__WIDTH 4
-#define R_SCSI1_CTRL__target_id__BITNR 4
-#define R_SCSI1_CTRL__target_id__WIDTH 4
-#define R_SCSI1_CTRL__fast_20__BITNR 3
-#define R_SCSI1_CTRL__fast_20__WIDTH 1
-#define R_SCSI1_CTRL__fast_20__yes 1
-#define R_SCSI1_CTRL__fast_20__no 0
-#define R_SCSI1_CTRL__bus_width__BITNR 2
-#define R_SCSI1_CTRL__bus_width__WIDTH 1
-#define R_SCSI1_CTRL__bus_width__wide 1
-#define R_SCSI1_CTRL__bus_width__narrow 0
-#define R_SCSI1_CTRL__synch__BITNR 1
-#define R_SCSI1_CTRL__synch__WIDTH 1
-#define R_SCSI1_CTRL__synch__synch 1
-#define R_SCSI1_CTRL__synch__asynch 0
-#define R_SCSI1_CTRL__enable__BITNR 0
-#define R_SCSI1_CTRL__enable__WIDTH 1
-#define R_SCSI1_CTRL__enable__on 1
-#define R_SCSI1_CTRL__enable__off 0
-
-#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050)
-#define R_SCSI1_CMD_DATA__parity_in__BITNR 26
-#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1
-#define R_SCSI1_CMD_DATA__parity_in__on 0
-#define R_SCSI1_CMD_DATA__parity_in__off 1
-#define R_SCSI1_CMD_DATA__skip__BITNR 25
-#define R_SCSI1_CMD_DATA__skip__WIDTH 1
-#define R_SCSI1_CMD_DATA__skip__on 1
-#define R_SCSI1_CMD_DATA__skip__off 0
-#define R_SCSI1_CMD_DATA__clr_status__BITNR 24
-#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1
-#define R_SCSI1_CMD_DATA__clr_status__yes 1
-#define R_SCSI1_CMD_DATA__clr_status__nop 0
-#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
-#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4
-#define R_SCSI1_CMD_DATA__command__BITNR 16
-#define R_SCSI1_CMD_DATA__command__WIDTH 4
-#define R_SCSI1_CMD_DATA__command__full_din_1 0
-#define R_SCSI1_CMD_DATA__command__full_dout_1 1
-#define R_SCSI1_CMD_DATA__command__full_stat_1 2
-#define R_SCSI1_CMD_DATA__command__resel_din 3
-#define R_SCSI1_CMD_DATA__command__resel_dout 4
-#define R_SCSI1_CMD_DATA__command__resel_stat 5
-#define R_SCSI1_CMD_DATA__command__arb_only 6
-#define R_SCSI1_CMD_DATA__command__full_din_3 8
-#define R_SCSI1_CMD_DATA__command__full_dout_3 9
-#define R_SCSI1_CMD_DATA__command__full_stat_3 10
-#define R_SCSI1_CMD_DATA__command__man_data_in 11
-#define R_SCSI1_CMD_DATA__command__man_data_out 12
-#define R_SCSI1_CMD_DATA__command__man_rat 13
-#define R_SCSI1_CMD_DATA__data_out__BITNR 0
-#define R_SCSI1_CMD_DATA__data_out__WIDTH 16
-
-#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050)
-#define R_SCSI1_DATA__data_out__BITNR 0
-#define R_SCSI1_DATA__data_out__WIDTH 16
-
-#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052)
-#define R_SCSI1_CMD__asynch_setup__BITNR 4
-#define R_SCSI1_CMD__asynch_setup__WIDTH 4
-#define R_SCSI1_CMD__command__BITNR 0
-#define R_SCSI1_CMD__command__WIDTH 4
-#define R_SCSI1_CMD__command__full_din_1 0
-#define R_SCSI1_CMD__command__full_dout_1 1
-#define R_SCSI1_CMD__command__full_stat_1 2
-#define R_SCSI1_CMD__command__resel_din 3
-#define R_SCSI1_CMD__command__resel_dout 4
-#define R_SCSI1_CMD__command__resel_stat 5
-#define R_SCSI1_CMD__command__arb_only 6
-#define R_SCSI1_CMD__command__full_din_3 8
-#define R_SCSI1_CMD__command__full_dout_3 9
-#define R_SCSI1_CMD__command__full_stat_3 10
-#define R_SCSI1_CMD__command__man_data_in 11
-#define R_SCSI1_CMD__command__man_data_out 12
-#define R_SCSI1_CMD__command__man_rat 13
-
-#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053)
-#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
-#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__parity_in__on 0
-#define R_SCSI1_STATUS_CTRL__parity_in__off 1
-#define R_SCSI1_STATUS_CTRL__skip__BITNR 1
-#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__skip__on 1
-#define R_SCSI1_STATUS_CTRL__skip__off 0
-#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
-#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__clr_status__yes 1
-#define R_SCSI1_STATUS_CTRL__clr_status__nop 0
-
-#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058)
-#define R_SCSI1_STATUS__tst_arb_won__BITNR 23
-#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1
-#define R_SCSI1_STATUS__tst_resel__BITNR 22
-#define R_SCSI1_STATUS__tst_resel__WIDTH 1
-#define R_SCSI1_STATUS__parity_error__BITNR 21
-#define R_SCSI1_STATUS__parity_error__WIDTH 1
-#define R_SCSI1_STATUS__bus_reset__BITNR 20
-#define R_SCSI1_STATUS__bus_reset__WIDTH 1
-#define R_SCSI1_STATUS__bus_reset__yes 1
-#define R_SCSI1_STATUS__bus_reset__no 0
-#define R_SCSI1_STATUS__resel_target__BITNR 15
-#define R_SCSI1_STATUS__resel_target__WIDTH 4
-#define R_SCSI1_STATUS__resel__BITNR 14
-#define R_SCSI1_STATUS__resel__WIDTH 1
-#define R_SCSI1_STATUS__resel__yes 1
-#define R_SCSI1_STATUS__resel__no 0
-#define R_SCSI1_STATUS__curr_phase__BITNR 11
-#define R_SCSI1_STATUS__curr_phase__WIDTH 3
-#define R_SCSI1_STATUS__curr_phase__ph_undef 0
-#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7
-#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6
-#define R_SCSI1_STATUS__curr_phase__ph_status 3
-#define R_SCSI1_STATUS__curr_phase__ph_command 2
-#define R_SCSI1_STATUS__curr_phase__ph_data_in 5
-#define R_SCSI1_STATUS__curr_phase__ph_data_out 4
-#define R_SCSI1_STATUS__curr_phase__ph_resel 1
-#define R_SCSI1_STATUS__last_seq_step__BITNR 6
-#define R_SCSI1_STATUS__last_seq_step__WIDTH 5
-#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24
-#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8
-#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29
-#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2
-#define R_SCSI1_STATUS__last_seq_step__st_manual 28
-#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30
-#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6
-#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22
-#define R_SCSI1_STATUS__last_seq_step__st_answer 3
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1
-#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15
-#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9
-#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11
-#define R_SCSI1_STATUS__last_seq_step__st_iwr 27
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21
-#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7
-#define R_SCSI1_STATUS__last_seq_step__st_cc 31
-#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14
-#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16
-#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10
-#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18
-#define R_SCSI1_STATUS__valid_status__BITNR 5
-#define R_SCSI1_STATUS__valid_status__WIDTH 1
-#define R_SCSI1_STATUS__valid_status__yes 1
-#define R_SCSI1_STATUS__valid_status__no 0
-#define R_SCSI1_STATUS__seq_status__BITNR 0
-#define R_SCSI1_STATUS__seq_status__WIDTH 5
-#define R_SCSI1_STATUS__seq_status__info_seq_complete 0
-#define R_SCSI1_STATUS__seq_status__info_parity_error 1
-#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2
-#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3
-#define R_SCSI1_STATUS__seq_status__info_arb_lost 4
-#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5
-#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6
-#define R_SCSI1_STATUS__seq_status__info_illegal_op 7
-#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8
-#define R_SCSI1_STATUS__seq_status__info_reselected 9
-#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10
-#define R_SCSI1_STATUS__seq_status__info_bus_reset 11
-#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12
-#define R_SCSI1_STATUS__seq_status__info_bus_free 13
-
-#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050)
-#define R_SCSI1_DATA_IN__data_in__BITNR 0
-#define R_SCSI1_DATA_IN__data_in__WIDTH 16
-
-/*
-!* Interrupt mask and status registers
-!*/
-
-#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0)
-#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_RD__nmi_pin__active 1
-#define R_IRQ_MASK0_RD__nmi_pin__inactive 0
-#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_RD__watchdog_nmi__active 1
-#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0
-#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_RD__sqe_test_error__active 1
-#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0
-#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_RD__carrier_loss__active 1
-#define R_IRQ_MASK0_RD__carrier_loss__inactive 0
-#define R_IRQ_MASK0_RD__deferred__BITNR 27
-#define R_IRQ_MASK0_RD__deferred__WIDTH 1
-#define R_IRQ_MASK0_RD__deferred__active 1
-#define R_IRQ_MASK0_RD__deferred__inactive 0
-#define R_IRQ_MASK0_RD__late_col__BITNR 26
-#define R_IRQ_MASK0_RD__late_col__WIDTH 1
-#define R_IRQ_MASK0_RD__late_col__active 1
-#define R_IRQ_MASK0_RD__late_col__inactive 0
-#define R_IRQ_MASK0_RD__multiple_col__BITNR 25
-#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_RD__multiple_col__active 1
-#define R_IRQ_MASK0_RD__multiple_col__inactive 0
-#define R_IRQ_MASK0_RD__single_col__BITNR 24
-#define R_IRQ_MASK0_RD__single_col__WIDTH 1
-#define R_IRQ_MASK0_RD__single_col__active 1
-#define R_IRQ_MASK0_RD__single_col__inactive 0
-#define R_IRQ_MASK0_RD__congestion__BITNR 23
-#define R_IRQ_MASK0_RD__congestion__WIDTH 1
-#define R_IRQ_MASK0_RD__congestion__active 1
-#define R_IRQ_MASK0_RD__congestion__inactive 0
-#define R_IRQ_MASK0_RD__oversize__BITNR 22
-#define R_IRQ_MASK0_RD__oversize__WIDTH 1
-#define R_IRQ_MASK0_RD__oversize__active 1
-#define R_IRQ_MASK0_RD__oversize__inactive 0
-#define R_IRQ_MASK0_RD__alignment_error__BITNR 21
-#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_RD__alignment_error__active 1
-#define R_IRQ_MASK0_RD__alignment_error__inactive 0
-#define R_IRQ_MASK0_RD__crc_error__BITNR 20
-#define R_IRQ_MASK0_RD__crc_error__WIDTH 1
-#define R_IRQ_MASK0_RD__crc_error__active 1
-#define R_IRQ_MASK0_RD__crc_error__inactive 0
-#define R_IRQ_MASK0_RD__overrun__BITNR 19
-#define R_IRQ_MASK0_RD__overrun__WIDTH 1
-#define R_IRQ_MASK0_RD__overrun__active 1
-#define R_IRQ_MASK0_RD__overrun__inactive 0
-#define R_IRQ_MASK0_RD__underrun__BITNR 18
-#define R_IRQ_MASK0_RD__underrun__WIDTH 1
-#define R_IRQ_MASK0_RD__underrun__active 1
-#define R_IRQ_MASK0_RD__underrun__inactive 0
-#define R_IRQ_MASK0_RD__excessive_col__BITNR 17
-#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_RD__excessive_col__active 1
-#define R_IRQ_MASK0_RD__excessive_col__inactive 0
-#define R_IRQ_MASK0_RD__mdio__BITNR 16
-#define R_IRQ_MASK0_RD__mdio__WIDTH 1
-#define R_IRQ_MASK0_RD__mdio__active 1
-#define R_IRQ_MASK0_RD__mdio__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq3__active 1
-#define R_IRQ_MASK0_RD__ata_drq3__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq2__active 1
-#define R_IRQ_MASK0_RD__ata_drq2__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq1__active 1
-#define R_IRQ_MASK0_RD__ata_drq1__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq0__active 1
-#define R_IRQ_MASK0_RD__ata_drq0__inactive 0
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq3__active 1
-#define R_IRQ_MASK0_RD__ata_irq3__inactive 0
-#define R_IRQ_MASK0_RD__par0_peri__BITNR 10
-#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_peri__active 1
-#define R_IRQ_MASK0_RD__par0_peri__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq2__active 1
-#define R_IRQ_MASK0_RD__ata_irq2__inactive 0
-#define R_IRQ_MASK0_RD__par0_data__BITNR 9
-#define R_IRQ_MASK0_RD__par0_data__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_data__active 1
-#define R_IRQ_MASK0_RD__par0_data__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq1__active 1
-#define R_IRQ_MASK0_RD__ata_irq1__inactive 0
-#define R_IRQ_MASK0_RD__par0_ready__BITNR 8
-#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_ready__active 1
-#define R_IRQ_MASK0_RD__par0_ready__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq0__active 1
-#define R_IRQ_MASK0_RD__ata_irq0__inactive 0
-#define R_IRQ_MASK0_RD__mio__BITNR 8
-#define R_IRQ_MASK0_RD__mio__WIDTH 1
-#define R_IRQ_MASK0_RD__mio__active 1
-#define R_IRQ_MASK0_RD__mio__inactive 0
-#define R_IRQ_MASK0_RD__scsi0__BITNR 8
-#define R_IRQ_MASK0_RD__scsi0__WIDTH 1
-#define R_IRQ_MASK0_RD__scsi0__active 1
-#define R_IRQ_MASK0_RD__scsi0__inactive 0
-#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_dmaend__active 1
-#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0
-#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_RD__ext_dma1__active 1
-#define R_IRQ_MASK0_RD__ext_dma1__inactive 0
-#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_RD__ext_dma0__active 1
-#define R_IRQ_MASK0_RD__ext_dma0__inactive 0
-#define R_IRQ_MASK0_RD__timer1__BITNR 1
-#define R_IRQ_MASK0_RD__timer1__WIDTH 1
-#define R_IRQ_MASK0_RD__timer1__active 1
-#define R_IRQ_MASK0_RD__timer1__inactive 0
-#define R_IRQ_MASK0_RD__timer0__BITNR 0
-#define R_IRQ_MASK0_RD__timer0__WIDTH 1
-#define R_IRQ_MASK0_RD__timer0__active 1
-#define R_IRQ_MASK0_RD__timer0__inactive 0
-
-#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0)
-#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_CLR__nmi_pin__clr 1
-#define R_IRQ_MASK0_CLR__nmi_pin__nop 0
-#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1
-#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0
-#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1
-#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0
-#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_CLR__carrier_loss__clr 1
-#define R_IRQ_MASK0_CLR__carrier_loss__nop 0
-#define R_IRQ_MASK0_CLR__deferred__BITNR 27
-#define R_IRQ_MASK0_CLR__deferred__WIDTH 1
-#define R_IRQ_MASK0_CLR__deferred__clr 1
-#define R_IRQ_MASK0_CLR__deferred__nop 0
-#define R_IRQ_MASK0_CLR__late_col__BITNR 26
-#define R_IRQ_MASK0_CLR__late_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__late_col__clr 1
-#define R_IRQ_MASK0_CLR__late_col__nop 0
-#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
-#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__multiple_col__clr 1
-#define R_IRQ_MASK0_CLR__multiple_col__nop 0
-#define R_IRQ_MASK0_CLR__single_col__BITNR 24
-#define R_IRQ_MASK0_CLR__single_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__single_col__clr 1
-#define R_IRQ_MASK0_CLR__single_col__nop 0
-#define R_IRQ_MASK0_CLR__congestion__BITNR 23
-#define R_IRQ_MASK0_CLR__congestion__WIDTH 1
-#define R_IRQ_MASK0_CLR__congestion__clr 1
-#define R_IRQ_MASK0_CLR__congestion__nop 0
-#define R_IRQ_MASK0_CLR__oversize__BITNR 22
-#define R_IRQ_MASK0_CLR__oversize__WIDTH 1
-#define R_IRQ_MASK0_CLR__oversize__clr 1
-#define R_IRQ_MASK0_CLR__oversize__nop 0
-#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
-#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__alignment_error__clr 1
-#define R_IRQ_MASK0_CLR__alignment_error__nop 0
-#define R_IRQ_MASK0_CLR__crc_error__BITNR 20
-#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__crc_error__clr 1
-#define R_IRQ_MASK0_CLR__crc_error__nop 0
-#define R_IRQ_MASK0_CLR__overrun__BITNR 19
-#define R_IRQ_MASK0_CLR__overrun__WIDTH 1
-#define R_IRQ_MASK0_CLR__overrun__clr 1
-#define R_IRQ_MASK0_CLR__overrun__nop 0
-#define R_IRQ_MASK0_CLR__underrun__BITNR 18
-#define R_IRQ_MASK0_CLR__underrun__WIDTH 1
-#define R_IRQ_MASK0_CLR__underrun__clr 1
-#define R_IRQ_MASK0_CLR__underrun__nop 0
-#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
-#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__excessive_col__clr 1
-#define R_IRQ_MASK0_CLR__excessive_col__nop 0
-#define R_IRQ_MASK0_CLR__mdio__BITNR 16
-#define R_IRQ_MASK0_CLR__mdio__WIDTH 1
-#define R_IRQ_MASK0_CLR__mdio__clr 1
-#define R_IRQ_MASK0_CLR__mdio__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq3__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq3__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq2__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq2__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq1__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq1__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq0__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq0__nop 0
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq3__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq3__nop 0
-#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
-#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_peri__clr 1
-#define R_IRQ_MASK0_CLR__par0_peri__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq2__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq2__nop 0
-#define R_IRQ_MASK0_CLR__par0_data__BITNR 9
-#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_data__clr 1
-#define R_IRQ_MASK0_CLR__par0_data__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq1__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq1__nop 0
-#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
-#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_ready__clr 1
-#define R_IRQ_MASK0_CLR__par0_ready__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq0__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq0__nop 0
-#define R_IRQ_MASK0_CLR__mio__BITNR 8
-#define R_IRQ_MASK0_CLR__mio__WIDTH 1
-#define R_IRQ_MASK0_CLR__mio__clr 1
-#define R_IRQ_MASK0_CLR__mio__nop 0
-#define R_IRQ_MASK0_CLR__scsi0__BITNR 8
-#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1
-#define R_IRQ_MASK0_CLR__scsi0__clr 1
-#define R_IRQ_MASK0_CLR__scsi0__nop 0
-#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1
-#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0
-#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ext_dma1__clr 1
-#define R_IRQ_MASK0_CLR__ext_dma1__nop 0
-#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ext_dma0__clr 1
-#define R_IRQ_MASK0_CLR__ext_dma0__nop 0
-#define R_IRQ_MASK0_CLR__timer1__BITNR 1
-#define R_IRQ_MASK0_CLR__timer1__WIDTH 1
-#define R_IRQ_MASK0_CLR__timer1__clr 1
-#define R_IRQ_MASK0_CLR__timer1__nop 0
-#define R_IRQ_MASK0_CLR__timer0__BITNR 0
-#define R_IRQ_MASK0_CLR__timer0__WIDTH 1
-#define R_IRQ_MASK0_CLR__timer0__clr 1
-#define R_IRQ_MASK0_CLR__timer0__nop 0
-
-#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4)
-#define R_IRQ_READ0__nmi_pin__BITNR 31
-#define R_IRQ_READ0__nmi_pin__WIDTH 1
-#define R_IRQ_READ0__nmi_pin__active 1
-#define R_IRQ_READ0__nmi_pin__inactive 0
-#define R_IRQ_READ0__watchdog_nmi__BITNR 30
-#define R_IRQ_READ0__watchdog_nmi__WIDTH 1
-#define R_IRQ_READ0__watchdog_nmi__active 1
-#define R_IRQ_READ0__watchdog_nmi__inactive 0
-#define R_IRQ_READ0__sqe_test_error__BITNR 29
-#define R_IRQ_READ0__sqe_test_error__WIDTH 1
-#define R_IRQ_READ0__sqe_test_error__active 1
-#define R_IRQ_READ0__sqe_test_error__inactive 0
-#define R_IRQ_READ0__carrier_loss__BITNR 28
-#define R_IRQ_READ0__carrier_loss__WIDTH 1
-#define R_IRQ_READ0__carrier_loss__active 1
-#define R_IRQ_READ0__carrier_loss__inactive 0
-#define R_IRQ_READ0__deferred__BITNR 27
-#define R_IRQ_READ0__deferred__WIDTH 1
-#define R_IRQ_READ0__deferred__active 1
-#define R_IRQ_READ0__deferred__inactive 0
-#define R_IRQ_READ0__late_col__BITNR 26
-#define R_IRQ_READ0__late_col__WIDTH 1
-#define R_IRQ_READ0__late_col__active 1
-#define R_IRQ_READ0__late_col__inactive 0
-#define R_IRQ_READ0__multiple_col__BITNR 25
-#define R_IRQ_READ0__multiple_col__WIDTH 1
-#define R_IRQ_READ0__multiple_col__active 1
-#define R_IRQ_READ0__multiple_col__inactive 0
-#define R_IRQ_READ0__single_col__BITNR 24
-#define R_IRQ_READ0__single_col__WIDTH 1
-#define R_IRQ_READ0__single_col__active 1
-#define R_IRQ_READ0__single_col__inactive 0
-#define R_IRQ_READ0__congestion__BITNR 23
-#define R_IRQ_READ0__congestion__WIDTH 1
-#define R_IRQ_READ0__congestion__active 1
-#define R_IRQ_READ0__congestion__inactive 0
-#define R_IRQ_READ0__oversize__BITNR 22
-#define R_IRQ_READ0__oversize__WIDTH 1
-#define R_IRQ_READ0__oversize__active 1
-#define R_IRQ_READ0__oversize__inactive 0
-#define R_IRQ_READ0__alignment_error__BITNR 21
-#define R_IRQ_READ0__alignment_error__WIDTH 1
-#define R_IRQ_READ0__alignment_error__active 1
-#define R_IRQ_READ0__alignment_error__inactive 0
-#define R_IRQ_READ0__crc_error__BITNR 20
-#define R_IRQ_READ0__crc_error__WIDTH 1
-#define R_IRQ_READ0__crc_error__active 1
-#define R_IRQ_READ0__crc_error__inactive 0
-#define R_IRQ_READ0__overrun__BITNR 19
-#define R_IRQ_READ0__overrun__WIDTH 1
-#define R_IRQ_READ0__overrun__active 1
-#define R_IRQ_READ0__overrun__inactive 0
-#define R_IRQ_READ0__underrun__BITNR 18
-#define R_IRQ_READ0__underrun__WIDTH 1
-#define R_IRQ_READ0__underrun__active 1
-#define R_IRQ_READ0__underrun__inactive 0
-#define R_IRQ_READ0__excessive_col__BITNR 17
-#define R_IRQ_READ0__excessive_col__WIDTH 1
-#define R_IRQ_READ0__excessive_col__active 1
-#define R_IRQ_READ0__excessive_col__inactive 0
-#define R_IRQ_READ0__mdio__BITNR 16
-#define R_IRQ_READ0__mdio__WIDTH 1
-#define R_IRQ_READ0__mdio__active 1
-#define R_IRQ_READ0__mdio__inactive 0
-#define R_IRQ_READ0__ata_drq3__BITNR 15
-#define R_IRQ_READ0__ata_drq3__WIDTH 1
-#define R_IRQ_READ0__ata_drq3__active 1
-#define R_IRQ_READ0__ata_drq3__inactive 0
-#define R_IRQ_READ0__ata_drq2__BITNR 14
-#define R_IRQ_READ0__ata_drq2__WIDTH 1
-#define R_IRQ_READ0__ata_drq2__active 1
-#define R_IRQ_READ0__ata_drq2__inactive 0
-#define R_IRQ_READ0__ata_drq1__BITNR 13
-#define R_IRQ_READ0__ata_drq1__WIDTH 1
-#define R_IRQ_READ0__ata_drq1__active 1
-#define R_IRQ_READ0__ata_drq1__inactive 0
-#define R_IRQ_READ0__ata_drq0__BITNR 12
-#define R_IRQ_READ0__ata_drq0__WIDTH 1
-#define R_IRQ_READ0__ata_drq0__active 1
-#define R_IRQ_READ0__ata_drq0__inactive 0
-#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
-#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_READ0__par0_ecp_cmd__active 1
-#define R_IRQ_READ0__par0_ecp_cmd__inactive 0
-#define R_IRQ_READ0__ata_irq3__BITNR 11
-#define R_IRQ_READ0__ata_irq3__WIDTH 1
-#define R_IRQ_READ0__ata_irq3__active 1
-#define R_IRQ_READ0__ata_irq3__inactive 0
-#define R_IRQ_READ0__par0_peri__BITNR 10
-#define R_IRQ_READ0__par0_peri__WIDTH 1
-#define R_IRQ_READ0__par0_peri__active 1
-#define R_IRQ_READ0__par0_peri__inactive 0
-#define R_IRQ_READ0__ata_irq2__BITNR 10
-#define R_IRQ_READ0__ata_irq2__WIDTH 1
-#define R_IRQ_READ0__ata_irq2__active 1
-#define R_IRQ_READ0__ata_irq2__inactive 0
-#define R_IRQ_READ0__par0_data__BITNR 9
-#define R_IRQ_READ0__par0_data__WIDTH 1
-#define R_IRQ_READ0__par0_data__active 1
-#define R_IRQ_READ0__par0_data__inactive 0
-#define R_IRQ_READ0__ata_irq1__BITNR 9
-#define R_IRQ_READ0__ata_irq1__WIDTH 1
-#define R_IRQ_READ0__ata_irq1__active 1
-#define R_IRQ_READ0__ata_irq1__inactive 0
-#define R_IRQ_READ0__par0_ready__BITNR 8
-#define R_IRQ_READ0__par0_ready__WIDTH 1
-#define R_IRQ_READ0__par0_ready__active 1
-#define R_IRQ_READ0__par0_ready__inactive 0
-#define R_IRQ_READ0__ata_irq0__BITNR 8
-#define R_IRQ_READ0__ata_irq0__WIDTH 1
-#define R_IRQ_READ0__ata_irq0__active 1
-#define R_IRQ_READ0__ata_irq0__inactive 0
-#define R_IRQ_READ0__mio__BITNR 8
-#define R_IRQ_READ0__mio__WIDTH 1
-#define R_IRQ_READ0__mio__active 1
-#define R_IRQ_READ0__mio__inactive 0
-#define R_IRQ_READ0__scsi0__BITNR 8
-#define R_IRQ_READ0__scsi0__WIDTH 1
-#define R_IRQ_READ0__scsi0__active 1
-#define R_IRQ_READ0__scsi0__inactive 0
-#define R_IRQ_READ0__ata_dmaend__BITNR 7
-#define R_IRQ_READ0__ata_dmaend__WIDTH 1
-#define R_IRQ_READ0__ata_dmaend__active 1
-#define R_IRQ_READ0__ata_dmaend__inactive 0
-#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_READ0__irq_ext_vector_nr__active 1
-#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0
-#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
-#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_READ0__irq_int_vector_nr__active 1
-#define R_IRQ_READ0__irq_int_vector_nr__inactive 0
-#define R_IRQ_READ0__ext_dma1__BITNR 3
-#define R_IRQ_READ0__ext_dma1__WIDTH 1
-#define R_IRQ_READ0__ext_dma1__active 1
-#define R_IRQ_READ0__ext_dma1__inactive 0
-#define R_IRQ_READ0__ext_dma0__BITNR 2
-#define R_IRQ_READ0__ext_dma0__WIDTH 1
-#define R_IRQ_READ0__ext_dma0__active 1
-#define R_IRQ_READ0__ext_dma0__inactive 0
-#define R_IRQ_READ0__timer1__BITNR 1
-#define R_IRQ_READ0__timer1__WIDTH 1
-#define R_IRQ_READ0__timer1__active 1
-#define R_IRQ_READ0__timer1__inactive 0
-#define R_IRQ_READ0__timer0__BITNR 0
-#define R_IRQ_READ0__timer0__WIDTH 1
-#define R_IRQ_READ0__timer0__active 1
-#define R_IRQ_READ0__timer0__inactive 0
-
-#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4)
-#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_SET__nmi_pin__set 1
-#define R_IRQ_MASK0_SET__nmi_pin__nop 0
-#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_SET__watchdog_nmi__set 1
-#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0
-#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_SET__sqe_test_error__set 1
-#define R_IRQ_MASK0_SET__sqe_test_error__nop 0
-#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_SET__carrier_loss__set 1
-#define R_IRQ_MASK0_SET__carrier_loss__nop 0
-#define R_IRQ_MASK0_SET__deferred__BITNR 27
-#define R_IRQ_MASK0_SET__deferred__WIDTH 1
-#define R_IRQ_MASK0_SET__deferred__set 1
-#define R_IRQ_MASK0_SET__deferred__nop 0
-#define R_IRQ_MASK0_SET__late_col__BITNR 26
-#define R_IRQ_MASK0_SET__late_col__WIDTH 1
-#define R_IRQ_MASK0_SET__late_col__set 1
-#define R_IRQ_MASK0_SET__late_col__nop 0
-#define R_IRQ_MASK0_SET__multiple_col__BITNR 25
-#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_SET__multiple_col__set 1
-#define R_IRQ_MASK0_SET__multiple_col__nop 0
-#define R_IRQ_MASK0_SET__single_col__BITNR 24
-#define R_IRQ_MASK0_SET__single_col__WIDTH 1
-#define R_IRQ_MASK0_SET__single_col__set 1
-#define R_IRQ_MASK0_SET__single_col__nop 0
-#define R_IRQ_MASK0_SET__congestion__BITNR 23
-#define R_IRQ_MASK0_SET__congestion__WIDTH 1
-#define R_IRQ_MASK0_SET__congestion__set 1
-#define R_IRQ_MASK0_SET__congestion__nop 0
-#define R_IRQ_MASK0_SET__oversize__BITNR 22
-#define R_IRQ_MASK0_SET__oversize__WIDTH 1
-#define R_IRQ_MASK0_SET__oversize__set 1
-#define R_IRQ_MASK0_SET__oversize__nop 0
-#define R_IRQ_MASK0_SET__alignment_error__BITNR 21
-#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_SET__alignment_error__set 1
-#define R_IRQ_MASK0_SET__alignment_error__nop 0
-#define R_IRQ_MASK0_SET__crc_error__BITNR 20
-#define R_IRQ_MASK0_SET__crc_error__WIDTH 1
-#define R_IRQ_MASK0_SET__crc_error__set 1
-#define R_IRQ_MASK0_SET__crc_error__nop 0
-#define R_IRQ_MASK0_SET__overrun__BITNR 19
-#define R_IRQ_MASK0_SET__overrun__WIDTH 1
-#define R_IRQ_MASK0_SET__overrun__set 1
-#define R_IRQ_MASK0_SET__overrun__nop 0
-#define R_IRQ_MASK0_SET__underrun__BITNR 18
-#define R_IRQ_MASK0_SET__underrun__WIDTH 1
-#define R_IRQ_MASK0_SET__underrun__set 1
-#define R_IRQ_MASK0_SET__underrun__nop 0
-#define R_IRQ_MASK0_SET__excessive_col__BITNR 17
-#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_SET__excessive_col__set 1
-#define R_IRQ_MASK0_SET__excessive_col__nop 0
-#define R_IRQ_MASK0_SET__mdio__BITNR 16
-#define R_IRQ_MASK0_SET__mdio__WIDTH 1
-#define R_IRQ_MASK0_SET__mdio__set 1
-#define R_IRQ_MASK0_SET__mdio__nop 0
-#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq3__set 1
-#define R_IRQ_MASK0_SET__ata_drq3__nop 0
-#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq2__set 1
-#define R_IRQ_MASK0_SET__ata_drq2__nop 0
-#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq1__set 1
-#define R_IRQ_MASK0_SET__ata_drq1__nop 0
-#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq0__set 1
-#define R_IRQ_MASK0_SET__ata_drq0__nop 0
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0
-#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq3__set 1
-#define R_IRQ_MASK0_SET__ata_irq3__nop 0
-#define R_IRQ_MASK0_SET__par0_peri__BITNR 10
-#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_peri__set 1
-#define R_IRQ_MASK0_SET__par0_peri__nop 0
-#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq2__set 1
-#define R_IRQ_MASK0_SET__ata_irq2__nop 0
-#define R_IRQ_MASK0_SET__par0_data__BITNR 9
-#define R_IRQ_MASK0_SET__par0_data__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_data__set 1
-#define R_IRQ_MASK0_SET__par0_data__nop 0
-#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq1__set 1
-#define R_IRQ_MASK0_SET__ata_irq1__nop 0
-#define R_IRQ_MASK0_SET__par0_ready__BITNR 8
-#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_ready__set 1
-#define R_IRQ_MASK0_SET__par0_ready__nop 0
-#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq0__set 1
-#define R_IRQ_MASK0_SET__ata_irq0__nop 0
-#define R_IRQ_MASK0_SET__mio__BITNR 8
-#define R_IRQ_MASK0_SET__mio__WIDTH 1
-#define R_IRQ_MASK0_SET__mio__set 1
-#define R_IRQ_MASK0_SET__mio__nop 0
-#define R_IRQ_MASK0_SET__scsi0__BITNR 8
-#define R_IRQ_MASK0_SET__scsi0__WIDTH 1
-#define R_IRQ_MASK0_SET__scsi0__set 1
-#define R_IRQ_MASK0_SET__scsi0__nop 0
-#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_dmaend__set 1
-#define R_IRQ_MASK0_SET__ata_dmaend__nop 0
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0
-#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_SET__ext_dma1__set 1
-#define R_IRQ_MASK0_SET__ext_dma1__nop 0
-#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_SET__ext_dma0__set 1
-#define R_IRQ_MASK0_SET__ext_dma0__nop 0
-#define R_IRQ_MASK0_SET__timer1__BITNR 1
-#define R_IRQ_MASK0_SET__timer1__WIDTH 1
-#define R_IRQ_MASK0_SET__timer1__set 1
-#define R_IRQ_MASK0_SET__timer1__nop 0
-#define R_IRQ_MASK0_SET__timer0__BITNR 0
-#define R_IRQ_MASK0_SET__timer0__WIDTH 1
-#define R_IRQ_MASK0_SET__timer0__set 1
-#define R_IRQ_MASK0_SET__timer0__nop 0
-
-#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8)
-#define R_IRQ_MASK1_RD__sw_int7__BITNR 31
-#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int7__active 1
-#define R_IRQ_MASK1_RD__sw_int7__inactive 0
-#define R_IRQ_MASK1_RD__sw_int6__BITNR 30
-#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int6__active 1
-#define R_IRQ_MASK1_RD__sw_int6__inactive 0
-#define R_IRQ_MASK1_RD__sw_int5__BITNR 29
-#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int5__active 1
-#define R_IRQ_MASK1_RD__sw_int5__inactive 0
-#define R_IRQ_MASK1_RD__sw_int4__BITNR 28
-#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int4__active 1
-#define R_IRQ_MASK1_RD__sw_int4__inactive 0
-#define R_IRQ_MASK1_RD__sw_int3__BITNR 27
-#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int3__active 1
-#define R_IRQ_MASK1_RD__sw_int3__inactive 0
-#define R_IRQ_MASK1_RD__sw_int2__BITNR 26
-#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int2__active 1
-#define R_IRQ_MASK1_RD__sw_int2__inactive 0
-#define R_IRQ_MASK1_RD__sw_int1__BITNR 25
-#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int1__active 1
-#define R_IRQ_MASK1_RD__sw_int1__inactive 0
-#define R_IRQ_MASK1_RD__sw_int0__BITNR 24
-#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int0__active 1
-#define R_IRQ_MASK1_RD__sw_int0__inactive 0
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0
-#define R_IRQ_MASK1_RD__par1_peri__BITNR 18
-#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_peri__active 1
-#define R_IRQ_MASK1_RD__par1_peri__inactive 0
-#define R_IRQ_MASK1_RD__par1_data__BITNR 17
-#define R_IRQ_MASK1_RD__par1_data__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_data__active 1
-#define R_IRQ_MASK1_RD__par1_data__inactive 0
-#define R_IRQ_MASK1_RD__par1_ready__BITNR 16
-#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_ready__active 1
-#define R_IRQ_MASK1_RD__par1_ready__inactive 0
-#define R_IRQ_MASK1_RD__scsi1__BITNR 16
-#define R_IRQ_MASK1_RD__scsi1__WIDTH 1
-#define R_IRQ_MASK1_RD__scsi1__active 1
-#define R_IRQ_MASK1_RD__scsi1__inactive 0
-#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser3_ready__active 1
-#define R_IRQ_MASK1_RD__ser3_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser3_data__BITNR 14
-#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser3_data__active 1
-#define R_IRQ_MASK1_RD__ser3_data__inactive 0
-#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser2_ready__active 1
-#define R_IRQ_MASK1_RD__ser2_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser2_data__BITNR 12
-#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser2_data__active 1
-#define R_IRQ_MASK1_RD__ser2_data__inactive 0
-#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser1_ready__active 1
-#define R_IRQ_MASK1_RD__ser1_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser1_data__BITNR 10
-#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser1_data__active 1
-#define R_IRQ_MASK1_RD__ser1_data__inactive 0
-#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser0_ready__active 1
-#define R_IRQ_MASK1_RD__ser0_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser0_data__BITNR 8
-#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser0_data__active 1
-#define R_IRQ_MASK1_RD__ser0_data__inactive 0
-#define R_IRQ_MASK1_RD__pa7__BITNR 7
-#define R_IRQ_MASK1_RD__pa7__WIDTH 1
-#define R_IRQ_MASK1_RD__pa7__active 1
-#define R_IRQ_MASK1_RD__pa7__inactive 0
-#define R_IRQ_MASK1_RD__pa6__BITNR 6
-#define R_IRQ_MASK1_RD__pa6__WIDTH 1
-#define R_IRQ_MASK1_RD__pa6__active 1
-#define R_IRQ_MASK1_RD__pa6__inactive 0
-#define R_IRQ_MASK1_RD__pa5__BITNR 5
-#define R_IRQ_MASK1_RD__pa5__WIDTH 1
-#define R_IRQ_MASK1_RD__pa5__active 1
-#define R_IRQ_MASK1_RD__pa5__inactive 0
-#define R_IRQ_MASK1_RD__pa4__BITNR 4
-#define R_IRQ_MASK1_RD__pa4__WIDTH 1
-#define R_IRQ_MASK1_RD__pa4__active 1
-#define R_IRQ_MASK1_RD__pa4__inactive 0
-#define R_IRQ_MASK1_RD__pa3__BITNR 3
-#define R_IRQ_MASK1_RD__pa3__WIDTH 1
-#define R_IRQ_MASK1_RD__pa3__active 1
-#define R_IRQ_MASK1_RD__pa3__inactive 0
-#define R_IRQ_MASK1_RD__pa2__BITNR 2
-#define R_IRQ_MASK1_RD__pa2__WIDTH 1
-#define R_IRQ_MASK1_RD__pa2__active 1
-#define R_IRQ_MASK1_RD__pa2__inactive 0
-#define R_IRQ_MASK1_RD__pa1__BITNR 1
-#define R_IRQ_MASK1_RD__pa1__WIDTH 1
-#define R_IRQ_MASK1_RD__pa1__active 1
-#define R_IRQ_MASK1_RD__pa1__inactive 0
-#define R_IRQ_MASK1_RD__pa0__BITNR 0
-#define R_IRQ_MASK1_RD__pa0__WIDTH 1
-#define R_IRQ_MASK1_RD__pa0__active 1
-#define R_IRQ_MASK1_RD__pa0__inactive 0
-
-#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8)
-#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
-#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int7__clr 1
-#define R_IRQ_MASK1_CLR__sw_int7__nop 0
-#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
-#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int6__clr 1
-#define R_IRQ_MASK1_CLR__sw_int6__nop 0
-#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
-#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int5__clr 1
-#define R_IRQ_MASK1_CLR__sw_int5__nop 0
-#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
-#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int4__clr 1
-#define R_IRQ_MASK1_CLR__sw_int4__nop 0
-#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
-#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int3__clr 1
-#define R_IRQ_MASK1_CLR__sw_int3__nop 0
-#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
-#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int2__clr 1
-#define R_IRQ_MASK1_CLR__sw_int2__nop 0
-#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
-#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int1__clr 1
-#define R_IRQ_MASK1_CLR__sw_int1__nop 0
-#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
-#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int0__clr 1
-#define R_IRQ_MASK1_CLR__sw_int0__nop 0
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0
-#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
-#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_peri__clr 1
-#define R_IRQ_MASK1_CLR__par1_peri__nop 0
-#define R_IRQ_MASK1_CLR__par1_data__BITNR 17
-#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_data__clr 1
-#define R_IRQ_MASK1_CLR__par1_data__nop 0
-#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
-#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_ready__clr 1
-#define R_IRQ_MASK1_CLR__par1_ready__nop 0
-#define R_IRQ_MASK1_CLR__scsi1__BITNR 16
-#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1
-#define R_IRQ_MASK1_CLR__scsi1__clr 1
-#define R_IRQ_MASK1_CLR__scsi1__nop 0
-#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser3_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser3_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
-#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser3_data__clr 1
-#define R_IRQ_MASK1_CLR__ser3_data__nop 0
-#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser2_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser2_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
-#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser2_data__clr 1
-#define R_IRQ_MASK1_CLR__ser2_data__nop 0
-#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser1_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser1_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
-#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser1_data__clr 1
-#define R_IRQ_MASK1_CLR__ser1_data__nop 0
-#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser0_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser0_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
-#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser0_data__clr 1
-#define R_IRQ_MASK1_CLR__ser0_data__nop 0
-#define R_IRQ_MASK1_CLR__pa7__BITNR 7
-#define R_IRQ_MASK1_CLR__pa7__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa7__clr 1
-#define R_IRQ_MASK1_CLR__pa7__nop 0
-#define R_IRQ_MASK1_CLR__pa6__BITNR 6
-#define R_IRQ_MASK1_CLR__pa6__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa6__clr 1
-#define R_IRQ_MASK1_CLR__pa6__nop 0
-#define R_IRQ_MASK1_CLR__pa5__BITNR 5
-#define R_IRQ_MASK1_CLR__pa5__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa5__clr 1
-#define R_IRQ_MASK1_CLR__pa5__nop 0
-#define R_IRQ_MASK1_CLR__pa4__BITNR 4
-#define R_IRQ_MASK1_CLR__pa4__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa4__clr 1
-#define R_IRQ_MASK1_CLR__pa4__nop 0
-#define R_IRQ_MASK1_CLR__pa3__BITNR 3
-#define R_IRQ_MASK1_CLR__pa3__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa3__clr 1
-#define R_IRQ_MASK1_CLR__pa3__nop 0
-#define R_IRQ_MASK1_CLR__pa2__BITNR 2
-#define R_IRQ_MASK1_CLR__pa2__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa2__clr 1
-#define R_IRQ_MASK1_CLR__pa2__nop 0
-#define R_IRQ_MASK1_CLR__pa1__BITNR 1
-#define R_IRQ_MASK1_CLR__pa1__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa1__clr 1
-#define R_IRQ_MASK1_CLR__pa1__nop 0
-#define R_IRQ_MASK1_CLR__pa0__BITNR 0
-#define R_IRQ_MASK1_CLR__pa0__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa0__clr 1
-#define R_IRQ_MASK1_CLR__pa0__nop 0
-
-#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc)
-#define R_IRQ_READ1__sw_int7__BITNR 31
-#define R_IRQ_READ1__sw_int7__WIDTH 1
-#define R_IRQ_READ1__sw_int7__active 1
-#define R_IRQ_READ1__sw_int7__inactive 0
-#define R_IRQ_READ1__sw_int6__BITNR 30
-#define R_IRQ_READ1__sw_int6__WIDTH 1
-#define R_IRQ_READ1__sw_int6__active 1
-#define R_IRQ_READ1__sw_int6__inactive 0
-#define R_IRQ_READ1__sw_int5__BITNR 29
-#define R_IRQ_READ1__sw_int5__WIDTH 1
-#define R_IRQ_READ1__sw_int5__active 1
-#define R_IRQ_READ1__sw_int5__inactive 0
-#define R_IRQ_READ1__sw_int4__BITNR 28
-#define R_IRQ_READ1__sw_int4__WIDTH 1
-#define R_IRQ_READ1__sw_int4__active 1
-#define R_IRQ_READ1__sw_int4__inactive 0
-#define R_IRQ_READ1__sw_int3__BITNR 27
-#define R_IRQ_READ1__sw_int3__WIDTH 1
-#define R_IRQ_READ1__sw_int3__active 1
-#define R_IRQ_READ1__sw_int3__inactive 0
-#define R_IRQ_READ1__sw_int2__BITNR 26
-#define R_IRQ_READ1__sw_int2__WIDTH 1
-#define R_IRQ_READ1__sw_int2__active 1
-#define R_IRQ_READ1__sw_int2__inactive 0
-#define R_IRQ_READ1__sw_int1__BITNR 25
-#define R_IRQ_READ1__sw_int1__WIDTH 1
-#define R_IRQ_READ1__sw_int1__active 1
-#define R_IRQ_READ1__sw_int1__inactive 0
-#define R_IRQ_READ1__sw_int0__BITNR 24
-#define R_IRQ_READ1__sw_int0__WIDTH 1
-#define R_IRQ_READ1__sw_int0__active 1
-#define R_IRQ_READ1__sw_int0__inactive 0
-#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
-#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_READ1__par1_ecp_cmd__active 1
-#define R_IRQ_READ1__par1_ecp_cmd__inactive 0
-#define R_IRQ_READ1__par1_peri__BITNR 18
-#define R_IRQ_READ1__par1_peri__WIDTH 1
-#define R_IRQ_READ1__par1_peri__active 1
-#define R_IRQ_READ1__par1_peri__inactive 0
-#define R_IRQ_READ1__par1_data__BITNR 17
-#define R_IRQ_READ1__par1_data__WIDTH 1
-#define R_IRQ_READ1__par1_data__active 1
-#define R_IRQ_READ1__par1_data__inactive 0
-#define R_IRQ_READ1__par1_ready__BITNR 16
-#define R_IRQ_READ1__par1_ready__WIDTH 1
-#define R_IRQ_READ1__par1_ready__active 1
-#define R_IRQ_READ1__par1_ready__inactive 0
-#define R_IRQ_READ1__scsi1__BITNR 16
-#define R_IRQ_READ1__scsi1__WIDTH 1
-#define R_IRQ_READ1__scsi1__active 1
-#define R_IRQ_READ1__scsi1__inactive 0
-#define R_IRQ_READ1__ser3_ready__BITNR 15
-#define R_IRQ_READ1__ser3_ready__WIDTH 1
-#define R_IRQ_READ1__ser3_ready__active 1
-#define R_IRQ_READ1__ser3_ready__inactive 0
-#define R_IRQ_READ1__ser3_data__BITNR 14
-#define R_IRQ_READ1__ser3_data__WIDTH 1
-#define R_IRQ_READ1__ser3_data__active 1
-#define R_IRQ_READ1__ser3_data__inactive 0
-#define R_IRQ_READ1__ser2_ready__BITNR 13
-#define R_IRQ_READ1__ser2_ready__WIDTH 1
-#define R_IRQ_READ1__ser2_ready__active 1
-#define R_IRQ_READ1__ser2_ready__inactive 0
-#define R_IRQ_READ1__ser2_data__BITNR 12
-#define R_IRQ_READ1__ser2_data__WIDTH 1
-#define R_IRQ_READ1__ser2_data__active 1
-#define R_IRQ_READ1__ser2_data__inactive 0
-#define R_IRQ_READ1__ser1_ready__BITNR 11
-#define R_IRQ_READ1__ser1_ready__WIDTH 1
-#define R_IRQ_READ1__ser1_ready__active 1
-#define R_IRQ_READ1__ser1_ready__inactive 0
-#define R_IRQ_READ1__ser1_data__BITNR 10
-#define R_IRQ_READ1__ser1_data__WIDTH 1
-#define R_IRQ_READ1__ser1_data__active 1
-#define R_IRQ_READ1__ser1_data__inactive 0
-#define R_IRQ_READ1__ser0_ready__BITNR 9
-#define R_IRQ_READ1__ser0_ready__WIDTH 1
-#define R_IRQ_READ1__ser0_ready__active 1
-#define R_IRQ_READ1__ser0_ready__inactive 0
-#define R_IRQ_READ1__ser0_data__BITNR 8
-#define R_IRQ_READ1__ser0_data__WIDTH 1
-#define R_IRQ_READ1__ser0_data__active 1
-#define R_IRQ_READ1__ser0_data__inactive 0
-#define R_IRQ_READ1__pa7__BITNR 7
-#define R_IRQ_READ1__pa7__WIDTH 1
-#define R_IRQ_READ1__pa7__active 1
-#define R_IRQ_READ1__pa7__inactive 0
-#define R_IRQ_READ1__pa6__BITNR 6
-#define R_IRQ_READ1__pa6__WIDTH 1
-#define R_IRQ_READ1__pa6__active 1
-#define R_IRQ_READ1__pa6__inactive 0
-#define R_IRQ_READ1__pa5__BITNR 5
-#define R_IRQ_READ1__pa5__WIDTH 1
-#define R_IRQ_READ1__pa5__active 1
-#define R_IRQ_READ1__pa5__inactive 0
-#define R_IRQ_READ1__pa4__BITNR 4
-#define R_IRQ_READ1__pa4__WIDTH 1
-#define R_IRQ_READ1__pa4__active 1
-#define R_IRQ_READ1__pa4__inactive 0
-#define R_IRQ_READ1__pa3__BITNR 3
-#define R_IRQ_READ1__pa3__WIDTH 1
-#define R_IRQ_READ1__pa3__active 1
-#define R_IRQ_READ1__pa3__inactive 0
-#define R_IRQ_READ1__pa2__BITNR 2
-#define R_IRQ_READ1__pa2__WIDTH 1
-#define R_IRQ_READ1__pa2__active 1
-#define R_IRQ_READ1__pa2__inactive 0
-#define R_IRQ_READ1__pa1__BITNR 1
-#define R_IRQ_READ1__pa1__WIDTH 1
-#define R_IRQ_READ1__pa1__active 1
-#define R_IRQ_READ1__pa1__inactive 0
-#define R_IRQ_READ1__pa0__BITNR 0
-#define R_IRQ_READ1__pa0__WIDTH 1
-#define R_IRQ_READ1__pa0__active 1
-#define R_IRQ_READ1__pa0__inactive 0
-
-#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc)
-#define R_IRQ_MASK1_SET__sw_int7__BITNR 31
-#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int7__set 1
-#define R_IRQ_MASK1_SET__sw_int7__nop 0
-#define R_IRQ_MASK1_SET__sw_int6__BITNR 30
-#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int6__set 1
-#define R_IRQ_MASK1_SET__sw_int6__nop 0
-#define R_IRQ_MASK1_SET__sw_int5__BITNR 29
-#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int5__set 1
-#define R_IRQ_MASK1_SET__sw_int5__nop 0
-#define R_IRQ_MASK1_SET__sw_int4__BITNR 28
-#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int4__set 1
-#define R_IRQ_MASK1_SET__sw_int4__nop 0
-#define R_IRQ_MASK1_SET__sw_int3__BITNR 27
-#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int3__set 1
-#define R_IRQ_MASK1_SET__sw_int3__nop 0
-#define R_IRQ_MASK1_SET__sw_int2__BITNR 26
-#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int2__set 1
-#define R_IRQ_MASK1_SET__sw_int2__nop 0
-#define R_IRQ_MASK1_SET__sw_int1__BITNR 25
-#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int1__set 1
-#define R_IRQ_MASK1_SET__sw_int1__nop 0
-#define R_IRQ_MASK1_SET__sw_int0__BITNR 24
-#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int0__set 1
-#define R_IRQ_MASK1_SET__sw_int0__nop 0
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0
-#define R_IRQ_MASK1_SET__par1_peri__BITNR 18
-#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_peri__set 1
-#define R_IRQ_MASK1_SET__par1_peri__nop 0
-#define R_IRQ_MASK1_SET__par1_data__BITNR 17
-#define R_IRQ_MASK1_SET__par1_data__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_data__set 1
-#define R_IRQ_MASK1_SET__par1_data__nop 0
-#define R_IRQ_MASK1_SET__par1_ready__BITNR 16
-#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_ready__set 1
-#define R_IRQ_MASK1_SET__par1_ready__nop 0
-#define R_IRQ_MASK1_SET__scsi1__BITNR 16
-#define R_IRQ_MASK1_SET__scsi1__WIDTH 1
-#define R_IRQ_MASK1_SET__scsi1__set 1
-#define R_IRQ_MASK1_SET__scsi1__nop 0
-#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser3_ready__set 1
-#define R_IRQ_MASK1_SET__ser3_ready__nop 0
-#define R_IRQ_MASK1_SET__ser3_data__BITNR 14
-#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser3_data__set 1
-#define R_IRQ_MASK1_SET__ser3_data__nop 0
-#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser2_ready__set 1
-#define R_IRQ_MASK1_SET__ser2_ready__nop 0
-#define R_IRQ_MASK1_SET__ser2_data__BITNR 12
-#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser2_data__set 1
-#define R_IRQ_MASK1_SET__ser2_data__nop 0
-#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser1_ready__set 1
-#define R_IRQ_MASK1_SET__ser1_ready__nop 0
-#define R_IRQ_MASK1_SET__ser1_data__BITNR 10
-#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser1_data__set 1
-#define R_IRQ_MASK1_SET__ser1_data__nop 0
-#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser0_ready__set 1
-#define R_IRQ_MASK1_SET__ser0_ready__nop 0
-#define R_IRQ_MASK1_SET__ser0_data__BITNR 8
-#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser0_data__set 1
-#define R_IRQ_MASK1_SET__ser0_data__nop 0
-#define R_IRQ_MASK1_SET__pa7__BITNR 7
-#define R_IRQ_MASK1_SET__pa7__WIDTH 1
-#define R_IRQ_MASK1_SET__pa7__set 1
-#define R_IRQ_MASK1_SET__pa7__nop 0
-#define R_IRQ_MASK1_SET__pa6__BITNR 6
-#define R_IRQ_MASK1_SET__pa6__WIDTH 1
-#define R_IRQ_MASK1_SET__pa6__set 1
-#define R_IRQ_MASK1_SET__pa6__nop 0
-#define R_IRQ_MASK1_SET__pa5__BITNR 5
-#define R_IRQ_MASK1_SET__pa5__WIDTH 1
-#define R_IRQ_MASK1_SET__pa5__set 1
-#define R_IRQ_MASK1_SET__pa5__nop 0
-#define R_IRQ_MASK1_SET__pa4__BITNR 4
-#define R_IRQ_MASK1_SET__pa4__WIDTH 1
-#define R_IRQ_MASK1_SET__pa4__set 1
-#define R_IRQ_MASK1_SET__pa4__nop 0
-#define R_IRQ_MASK1_SET__pa3__BITNR 3
-#define R_IRQ_MASK1_SET__pa3__WIDTH 1
-#define R_IRQ_MASK1_SET__pa3__set 1
-#define R_IRQ_MASK1_SET__pa3__nop 0
-#define R_IRQ_MASK1_SET__pa2__BITNR 2
-#define R_IRQ_MASK1_SET__pa2__WIDTH 1
-#define R_IRQ_MASK1_SET__pa2__set 1
-#define R_IRQ_MASK1_SET__pa2__nop 0
-#define R_IRQ_MASK1_SET__pa1__BITNR 1
-#define R_IRQ_MASK1_SET__pa1__WIDTH 1
-#define R_IRQ_MASK1_SET__pa1__set 1
-#define R_IRQ_MASK1_SET__pa1__nop 0
-#define R_IRQ_MASK1_SET__pa0__BITNR 0
-#define R_IRQ_MASK1_SET__pa0__WIDTH 1
-#define R_IRQ_MASK1_SET__pa0__set 1
-#define R_IRQ_MASK1_SET__pa0__nop 0
-
-#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0)
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma9_eop__active 1
-#define R_IRQ_MASK2_RD__dma9_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma9_descr__active 1
-#define R_IRQ_MASK2_RD__dma9_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_eop__active 1
-#define R_IRQ_MASK2_RD__dma8_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma7_eop__active 1
-#define R_IRQ_MASK2_RD__dma7_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma7_descr__active 1
-#define R_IRQ_MASK2_RD__dma7_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma6_eop__active 1
-#define R_IRQ_MASK2_RD__dma6_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma6_descr__active 1
-#define R_IRQ_MASK2_RD__dma6_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma5_eop__active 1
-#define R_IRQ_MASK2_RD__dma5_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma5_descr__active 1
-#define R_IRQ_MASK2_RD__dma5_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma4_eop__active 1
-#define R_IRQ_MASK2_RD__dma4_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma4_descr__active 1
-#define R_IRQ_MASK2_RD__dma4_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma3_eop__active 1
-#define R_IRQ_MASK2_RD__dma3_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma3_descr__active 1
-#define R_IRQ_MASK2_RD__dma3_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma2_eop__active 1
-#define R_IRQ_MASK2_RD__dma2_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma2_descr__active 1
-#define R_IRQ_MASK2_RD__dma2_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma1_eop__active 1
-#define R_IRQ_MASK2_RD__dma1_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma1_descr__active 1
-#define R_IRQ_MASK2_RD__dma1_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma0_eop__active 1
-#define R_IRQ_MASK2_RD__dma0_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma0_descr__active 1
-#define R_IRQ_MASK2_RD__dma0_descr__inactive 0
-
-#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0)
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma9_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma9_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma9_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma9_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma8_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma7_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma7_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma7_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma7_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma6_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma6_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma6_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma6_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma5_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma5_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma5_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma5_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma4_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma4_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma4_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma4_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma3_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma3_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma3_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma3_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma2_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma2_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma2_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma2_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma1_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma1_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma1_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma1_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma0_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma0_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma0_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma0_descr__nop 0
-
-#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4)
-#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
-#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub3_descr__active 1
-#define R_IRQ_READ2__dma8_sub3_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
-#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub2_descr__active 1
-#define R_IRQ_READ2__dma8_sub2_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
-#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub1_descr__active 1
-#define R_IRQ_READ2__dma8_sub1_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
-#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub0_descr__active 1
-#define R_IRQ_READ2__dma8_sub0_descr__inactive 0
-#define R_IRQ_READ2__dma9_eop__BITNR 19
-#define R_IRQ_READ2__dma9_eop__WIDTH 1
-#define R_IRQ_READ2__dma9_eop__active 1
-#define R_IRQ_READ2__dma9_eop__inactive 0
-#define R_IRQ_READ2__dma9_descr__BITNR 18
-#define R_IRQ_READ2__dma9_descr__WIDTH 1
-#define R_IRQ_READ2__dma9_descr__active 1
-#define R_IRQ_READ2__dma9_descr__inactive 0
-#define R_IRQ_READ2__dma8_eop__BITNR 17
-#define R_IRQ_READ2__dma8_eop__WIDTH 1
-#define R_IRQ_READ2__dma8_eop__active 1
-#define R_IRQ_READ2__dma8_eop__inactive 0
-#define R_IRQ_READ2__dma8_descr__BITNR 16
-#define R_IRQ_READ2__dma8_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_descr__active 1
-#define R_IRQ_READ2__dma8_descr__inactive 0
-#define R_IRQ_READ2__dma7_eop__BITNR 15
-#define R_IRQ_READ2__dma7_eop__WIDTH 1
-#define R_IRQ_READ2__dma7_eop__active 1
-#define R_IRQ_READ2__dma7_eop__inactive 0
-#define R_IRQ_READ2__dma7_descr__BITNR 14
-#define R_IRQ_READ2__dma7_descr__WIDTH 1
-#define R_IRQ_READ2__dma7_descr__active 1
-#define R_IRQ_READ2__dma7_descr__inactive 0
-#define R_IRQ_READ2__dma6_eop__BITNR 13
-#define R_IRQ_READ2__dma6_eop__WIDTH 1
-#define R_IRQ_READ2__dma6_eop__active 1
-#define R_IRQ_READ2__dma6_eop__inactive 0
-#define R_IRQ_READ2__dma6_descr__BITNR 12
-#define R_IRQ_READ2__dma6_descr__WIDTH 1
-#define R_IRQ_READ2__dma6_descr__active 1
-#define R_IRQ_READ2__dma6_descr__inactive 0
-#define R_IRQ_READ2__dma5_eop__BITNR 11
-#define R_IRQ_READ2__dma5_eop__WIDTH 1
-#define R_IRQ_READ2__dma5_eop__active 1
-#define R_IRQ_READ2__dma5_eop__inactive 0
-#define R_IRQ_READ2__dma5_descr__BITNR 10
-#define R_IRQ_READ2__dma5_descr__WIDTH 1
-#define R_IRQ_READ2__dma5_descr__active 1
-#define R_IRQ_READ2__dma5_descr__inactive 0
-#define R_IRQ_READ2__dma4_eop__BITNR 9
-#define R_IRQ_READ2__dma4_eop__WIDTH 1
-#define R_IRQ_READ2__dma4_eop__active 1
-#define R_IRQ_READ2__dma4_eop__inactive 0
-#define R_IRQ_READ2__dma4_descr__BITNR 8
-#define R_IRQ_READ2__dma4_descr__WIDTH 1
-#define R_IRQ_READ2__dma4_descr__active 1
-#define R_IRQ_READ2__dma4_descr__inactive 0
-#define R_IRQ_READ2__dma3_eop__BITNR 7
-#define R_IRQ_READ2__dma3_eop__WIDTH 1
-#define R_IRQ_READ2__dma3_eop__active 1
-#define R_IRQ_READ2__dma3_eop__inactive 0
-#define R_IRQ_READ2__dma3_descr__BITNR 6
-#define R_IRQ_READ2__dma3_descr__WIDTH 1
-#define R_IRQ_READ2__dma3_descr__active 1
-#define R_IRQ_READ2__dma3_descr__inactive 0
-#define R_IRQ_READ2__dma2_eop__BITNR 5
-#define R_IRQ_READ2__dma2_eop__WIDTH 1
-#define R_IRQ_READ2__dma2_eop__active 1
-#define R_IRQ_READ2__dma2_eop__inactive 0
-#define R_IRQ_READ2__dma2_descr__BITNR 4
-#define R_IRQ_READ2__dma2_descr__WIDTH 1
-#define R_IRQ_READ2__dma2_descr__active 1
-#define R_IRQ_READ2__dma2_descr__inactive 0
-#define R_IRQ_READ2__dma1_eop__BITNR 3
-#define R_IRQ_READ2__dma1_eop__WIDTH 1
-#define R_IRQ_READ2__dma1_eop__active 1
-#define R_IRQ_READ2__dma1_eop__inactive 0
-#define R_IRQ_READ2__dma1_descr__BITNR 2
-#define R_IRQ_READ2__dma1_descr__WIDTH 1
-#define R_IRQ_READ2__dma1_descr__active 1
-#define R_IRQ_READ2__dma1_descr__inactive 0
-#define R_IRQ_READ2__dma0_eop__BITNR 1
-#define R_IRQ_READ2__dma0_eop__WIDTH 1
-#define R_IRQ_READ2__dma0_eop__active 1
-#define R_IRQ_READ2__dma0_eop__inactive 0
-#define R_IRQ_READ2__dma0_descr__BITNR 0
-#define R_IRQ_READ2__dma0_descr__WIDTH 1
-#define R_IRQ_READ2__dma0_descr__active 1
-#define R_IRQ_READ2__dma0_descr__inactive 0
-
-#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4)
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0
-#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma9_eop__set 1
-#define R_IRQ_MASK2_SET__dma9_eop__nop 0
-#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma9_descr__set 1
-#define R_IRQ_MASK2_SET__dma9_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_eop__set 1
-#define R_IRQ_MASK2_SET__dma8_eop__nop 0
-#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_descr__nop 0
-#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma7_eop__set 1
-#define R_IRQ_MASK2_SET__dma7_eop__nop 0
-#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma7_descr__set 1
-#define R_IRQ_MASK2_SET__dma7_descr__nop 0
-#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma6_eop__set 1
-#define R_IRQ_MASK2_SET__dma6_eop__nop 0
-#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma6_descr__set 1
-#define R_IRQ_MASK2_SET__dma6_descr__nop 0
-#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma5_eop__set 1
-#define R_IRQ_MASK2_SET__dma5_eop__nop 0
-#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma5_descr__set 1
-#define R_IRQ_MASK2_SET__dma5_descr__nop 0
-#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma4_eop__set 1
-#define R_IRQ_MASK2_SET__dma4_eop__nop 0
-#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma4_descr__set 1
-#define R_IRQ_MASK2_SET__dma4_descr__nop 0
-#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma3_eop__set 1
-#define R_IRQ_MASK2_SET__dma3_eop__nop 0
-#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma3_descr__set 1
-#define R_IRQ_MASK2_SET__dma3_descr__nop 0
-#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma2_eop__set 1
-#define R_IRQ_MASK2_SET__dma2_eop__nop 0
-#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma2_descr__set 1
-#define R_IRQ_MASK2_SET__dma2_descr__nop 0
-#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma1_eop__set 1
-#define R_IRQ_MASK2_SET__dma1_eop__nop 0
-#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma1_descr__set 1
-#define R_IRQ_MASK2_SET__dma1_descr__nop 0
-#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma0_eop__set 1
-#define R_IRQ_MASK2_SET__dma0_eop__nop 0
-#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma0_descr__set 1
-#define R_IRQ_MASK2_SET__dma0_descr__nop 0
-
-#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8)
-#define R_VECT_MASK_RD__usb__BITNR 31
-#define R_VECT_MASK_RD__usb__WIDTH 1
-#define R_VECT_MASK_RD__usb__active 1
-#define R_VECT_MASK_RD__usb__inactive 0
-#define R_VECT_MASK_RD__dma9__BITNR 25
-#define R_VECT_MASK_RD__dma9__WIDTH 1
-#define R_VECT_MASK_RD__dma9__active 1
-#define R_VECT_MASK_RD__dma9__inactive 0
-#define R_VECT_MASK_RD__dma8__BITNR 24
-#define R_VECT_MASK_RD__dma8__WIDTH 1
-#define R_VECT_MASK_RD__dma8__active 1
-#define R_VECT_MASK_RD__dma8__inactive 0
-#define R_VECT_MASK_RD__dma7__BITNR 23
-#define R_VECT_MASK_RD__dma7__WIDTH 1
-#define R_VECT_MASK_RD__dma7__active 1
-#define R_VECT_MASK_RD__dma7__inactive 0
-#define R_VECT_MASK_RD__dma6__BITNR 22
-#define R_VECT_MASK_RD__dma6__WIDTH 1
-#define R_VECT_MASK_RD__dma6__active 1
-#define R_VECT_MASK_RD__dma6__inactive 0
-#define R_VECT_MASK_RD__dma5__BITNR 21
-#define R_VECT_MASK_RD__dma5__WIDTH 1
-#define R_VECT_MASK_RD__dma5__active 1
-#define R_VECT_MASK_RD__dma5__inactive 0
-#define R_VECT_MASK_RD__dma4__BITNR 20
-#define R_VECT_MASK_RD__dma4__WIDTH 1
-#define R_VECT_MASK_RD__dma4__active 1
-#define R_VECT_MASK_RD__dma4__inactive 0
-#define R_VECT_MASK_RD__dma3__BITNR 19
-#define R_VECT_MASK_RD__dma3__WIDTH 1
-#define R_VECT_MASK_RD__dma3__active 1
-#define R_VECT_MASK_RD__dma3__inactive 0
-#define R_VECT_MASK_RD__dma2__BITNR 18
-#define R_VECT_MASK_RD__dma2__WIDTH 1
-#define R_VECT_MASK_RD__dma2__active 1
-#define R_VECT_MASK_RD__dma2__inactive 0
-#define R_VECT_MASK_RD__dma1__BITNR 17
-#define R_VECT_MASK_RD__dma1__WIDTH 1
-#define R_VECT_MASK_RD__dma1__active 1
-#define R_VECT_MASK_RD__dma1__inactive 0
-#define R_VECT_MASK_RD__dma0__BITNR 16
-#define R_VECT_MASK_RD__dma0__WIDTH 1
-#define R_VECT_MASK_RD__dma0__active 1
-#define R_VECT_MASK_RD__dma0__inactive 0
-#define R_VECT_MASK_RD__ext_dma1__BITNR 13
-#define R_VECT_MASK_RD__ext_dma1__WIDTH 1
-#define R_VECT_MASK_RD__ext_dma1__active 1
-#define R_VECT_MASK_RD__ext_dma1__inactive 0
-#define R_VECT_MASK_RD__ext_dma0__BITNR 12
-#define R_VECT_MASK_RD__ext_dma0__WIDTH 1
-#define R_VECT_MASK_RD__ext_dma0__active 1
-#define R_VECT_MASK_RD__ext_dma0__inactive 0
-#define R_VECT_MASK_RD__pa__BITNR 11
-#define R_VECT_MASK_RD__pa__WIDTH 1
-#define R_VECT_MASK_RD__pa__active 1
-#define R_VECT_MASK_RD__pa__inactive 0
-#define R_VECT_MASK_RD__irq_intnr__BITNR 10
-#define R_VECT_MASK_RD__irq_intnr__WIDTH 1
-#define R_VECT_MASK_RD__irq_intnr__active 1
-#define R_VECT_MASK_RD__irq_intnr__inactive 0
-#define R_VECT_MASK_RD__sw__BITNR 9
-#define R_VECT_MASK_RD__sw__WIDTH 1
-#define R_VECT_MASK_RD__sw__active 1
-#define R_VECT_MASK_RD__sw__inactive 0
-#define R_VECT_MASK_RD__serial__BITNR 8
-#define R_VECT_MASK_RD__serial__WIDTH 1
-#define R_VECT_MASK_RD__serial__active 1
-#define R_VECT_MASK_RD__serial__inactive 0
-#define R_VECT_MASK_RD__snmp__BITNR 7
-#define R_VECT_MASK_RD__snmp__WIDTH 1
-#define R_VECT_MASK_RD__snmp__active 1
-#define R_VECT_MASK_RD__snmp__inactive 0
-#define R_VECT_MASK_RD__network__BITNR 6
-#define R_VECT_MASK_RD__network__WIDTH 1
-#define R_VECT_MASK_RD__network__active 1
-#define R_VECT_MASK_RD__network__inactive 0
-#define R_VECT_MASK_RD__scsi1__BITNR 5
-#define R_VECT_MASK_RD__scsi1__WIDTH 1
-#define R_VECT_MASK_RD__scsi1__active 1
-#define R_VECT_MASK_RD__scsi1__inactive 0
-#define R_VECT_MASK_RD__par1__BITNR 5
-#define R_VECT_MASK_RD__par1__WIDTH 1
-#define R_VECT_MASK_RD__par1__active 1
-#define R_VECT_MASK_RD__par1__inactive 0
-#define R_VECT_MASK_RD__scsi0__BITNR 4
-#define R_VECT_MASK_RD__scsi0__WIDTH 1
-#define R_VECT_MASK_RD__scsi0__active 1
-#define R_VECT_MASK_RD__scsi0__inactive 0
-#define R_VECT_MASK_RD__par0__BITNR 4
-#define R_VECT_MASK_RD__par0__WIDTH 1
-#define R_VECT_MASK_RD__par0__active 1
-#define R_VECT_MASK_RD__par0__inactive 0
-#define R_VECT_MASK_RD__ata__BITNR 4
-#define R_VECT_MASK_RD__ata__WIDTH 1
-#define R_VECT_MASK_RD__ata__active 1
-#define R_VECT_MASK_RD__ata__inactive 0
-#define R_VECT_MASK_RD__mio__BITNR 4
-#define R_VECT_MASK_RD__mio__WIDTH 1
-#define R_VECT_MASK_RD__mio__active 1
-#define R_VECT_MASK_RD__mio__inactive 0
-#define R_VECT_MASK_RD__timer1__BITNR 3
-#define R_VECT_MASK_RD__timer1__WIDTH 1
-#define R_VECT_MASK_RD__timer1__active 1
-#define R_VECT_MASK_RD__timer1__inactive 0
-#define R_VECT_MASK_RD__timer0__BITNR 2
-#define R_VECT_MASK_RD__timer0__WIDTH 1
-#define R_VECT_MASK_RD__timer0__active 1
-#define R_VECT_MASK_RD__timer0__inactive 0
-#define R_VECT_MASK_RD__nmi__BITNR 1
-#define R_VECT_MASK_RD__nmi__WIDTH 1
-#define R_VECT_MASK_RD__nmi__active 1
-#define R_VECT_MASK_RD__nmi__inactive 0
-#define R_VECT_MASK_RD__some__BITNR 0
-#define R_VECT_MASK_RD__some__WIDTH 1
-#define R_VECT_MASK_RD__some__active 1
-#define R_VECT_MASK_RD__some__inactive 0
-
-#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8)
-#define R_VECT_MASK_CLR__usb__BITNR 31
-#define R_VECT_MASK_CLR__usb__WIDTH 1
-#define R_VECT_MASK_CLR__usb__clr 1
-#define R_VECT_MASK_CLR__usb__nop 0
-#define R_VECT_MASK_CLR__dma9__BITNR 25
-#define R_VECT_MASK_CLR__dma9__WIDTH 1
-#define R_VECT_MASK_CLR__dma9__clr 1
-#define R_VECT_MASK_CLR__dma9__nop 0
-#define R_VECT_MASK_CLR__dma8__BITNR 24
-#define R_VECT_MASK_CLR__dma8__WIDTH 1
-#define R_VECT_MASK_CLR__dma8__clr 1
-#define R_VECT_MASK_CLR__dma8__nop 0
-#define R_VECT_MASK_CLR__dma7__BITNR 23
-#define R_VECT_MASK_CLR__dma7__WIDTH 1
-#define R_VECT_MASK_CLR__dma7__clr 1
-#define R_VECT_MASK_CLR__dma7__nop 0
-#define R_VECT_MASK_CLR__dma6__BITNR 22
-#define R_VECT_MASK_CLR__dma6__WIDTH 1
-#define R_VECT_MASK_CLR__dma6__clr 1
-#define R_VECT_MASK_CLR__dma6__nop 0
-#define R_VECT_MASK_CLR__dma5__BITNR 21
-#define R_VECT_MASK_CLR__dma5__WIDTH 1
-#define R_VECT_MASK_CLR__dma5__clr 1
-#define R_VECT_MASK_CLR__dma5__nop 0
-#define R_VECT_MASK_CLR__dma4__BITNR 20
-#define R_VECT_MASK_CLR__dma4__WIDTH 1
-#define R_VECT_MASK_CLR__dma4__clr 1
-#define R_VECT_MASK_CLR__dma4__nop 0
-#define R_VECT_MASK_CLR__dma3__BITNR 19
-#define R_VECT_MASK_CLR__dma3__WIDTH 1
-#define R_VECT_MASK_CLR__dma3__clr 1
-#define R_VECT_MASK_CLR__dma3__nop 0
-#define R_VECT_MASK_CLR__dma2__BITNR 18
-#define R_VECT_MASK_CLR__dma2__WIDTH 1
-#define R_VECT_MASK_CLR__dma2__clr 1
-#define R_VECT_MASK_CLR__dma2__nop 0
-#define R_VECT_MASK_CLR__dma1__BITNR 17
-#define R_VECT_MASK_CLR__dma1__WIDTH 1
-#define R_VECT_MASK_CLR__dma1__clr 1
-#define R_VECT_MASK_CLR__dma1__nop 0
-#define R_VECT_MASK_CLR__dma0__BITNR 16
-#define R_VECT_MASK_CLR__dma0__WIDTH 1
-#define R_VECT_MASK_CLR__dma0__clr 1
-#define R_VECT_MASK_CLR__dma0__nop 0
-#define R_VECT_MASK_CLR__ext_dma1__BITNR 13
-#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1
-#define R_VECT_MASK_CLR__ext_dma1__clr 1
-#define R_VECT_MASK_CLR__ext_dma1__nop 0
-#define R_VECT_MASK_CLR__ext_dma0__BITNR 12
-#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1
-#define R_VECT_MASK_CLR__ext_dma0__clr 1
-#define R_VECT_MASK_CLR__ext_dma0__nop 0
-#define R_VECT_MASK_CLR__pa__BITNR 11
-#define R_VECT_MASK_CLR__pa__WIDTH 1
-#define R_VECT_MASK_CLR__pa__clr 1
-#define R_VECT_MASK_CLR__pa__nop 0
-#define R_VECT_MASK_CLR__irq_intnr__BITNR 10
-#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1
-#define R_VECT_MASK_CLR__irq_intnr__clr 1
-#define R_VECT_MASK_CLR__irq_intnr__nop 0
-#define R_VECT_MASK_CLR__sw__BITNR 9
-#define R_VECT_MASK_CLR__sw__WIDTH 1
-#define R_VECT_MASK_CLR__sw__clr 1
-#define R_VECT_MASK_CLR__sw__nop 0
-#define R_VECT_MASK_CLR__serial__BITNR 8
-#define R_VECT_MASK_CLR__serial__WIDTH 1
-#define R_VECT_MASK_CLR__serial__clr 1
-#define R_VECT_MASK_CLR__serial__nop 0
-#define R_VECT_MASK_CLR__snmp__BITNR 7
-#define R_VECT_MASK_CLR__snmp__WIDTH 1
-#define R_VECT_MASK_CLR__snmp__clr 1
-#define R_VECT_MASK_CLR__snmp__nop 0
-#define R_VECT_MASK_CLR__network__BITNR 6
-#define R_VECT_MASK_CLR__network__WIDTH 1
-#define R_VECT_MASK_CLR__network__clr 1
-#define R_VECT_MASK_CLR__network__nop 0
-#define R_VECT_MASK_CLR__scsi1__BITNR 5
-#define R_VECT_MASK_CLR__scsi1__WIDTH 1
-#define R_VECT_MASK_CLR__scsi1__clr 1
-#define R_VECT_MASK_CLR__scsi1__nop 0
-#define R_VECT_MASK_CLR__par1__BITNR 5
-#define R_VECT_MASK_CLR__par1__WIDTH 1
-#define R_VECT_MASK_CLR__par1__clr 1
-#define R_VECT_MASK_CLR__par1__nop 0
-#define R_VECT_MASK_CLR__scsi0__BITNR 4
-#define R_VECT_MASK_CLR__scsi0__WIDTH 1
-#define R_VECT_MASK_CLR__scsi0__clr 1
-#define R_VECT_MASK_CLR__scsi0__nop 0
-#define R_VECT_MASK_CLR__par0__BITNR 4
-#define R_VECT_MASK_CLR__par0__WIDTH 1
-#define R_VECT_MASK_CLR__par0__clr 1
-#define R_VECT_MASK_CLR__par0__nop 0
-#define R_VECT_MASK_CLR__ata__BITNR 4
-#define R_VECT_MASK_CLR__ata__WIDTH 1
-#define R_VECT_MASK_CLR__ata__clr 1
-#define R_VECT_MASK_CLR__ata__nop 0
-#define R_VECT_MASK_CLR__mio__BITNR 4
-#define R_VECT_MASK_CLR__mio__WIDTH 1
-#define R_VECT_MASK_CLR__mio__clr 1
-#define R_VECT_MASK_CLR__mio__nop 0
-#define R_VECT_MASK_CLR__timer1__BITNR 3
-#define R_VECT_MASK_CLR__timer1__WIDTH 1
-#define R_VECT_MASK_CLR__timer1__clr 1
-#define R_VECT_MASK_CLR__timer1__nop 0
-#define R_VECT_MASK_CLR__timer0__BITNR 2
-#define R_VECT_MASK_CLR__timer0__WIDTH 1
-#define R_VECT_MASK_CLR__timer0__clr 1
-#define R_VECT_MASK_CLR__timer0__nop 0
-#define R_VECT_MASK_CLR__nmi__BITNR 1
-#define R_VECT_MASK_CLR__nmi__WIDTH 1
-#define R_VECT_MASK_CLR__nmi__clr 1
-#define R_VECT_MASK_CLR__nmi__nop 0
-#define R_VECT_MASK_CLR__some__BITNR 0
-#define R_VECT_MASK_CLR__some__WIDTH 1
-#define R_VECT_MASK_CLR__some__clr 1
-#define R_VECT_MASK_CLR__some__nop 0
-
-#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc)
-#define R_VECT_READ__usb__BITNR 31
-#define R_VECT_READ__usb__WIDTH 1
-#define R_VECT_READ__usb__active 1
-#define R_VECT_READ__usb__inactive 0
-#define R_VECT_READ__dma9__BITNR 25
-#define R_VECT_READ__dma9__WIDTH 1
-#define R_VECT_READ__dma9__active 1
-#define R_VECT_READ__dma9__inactive 0
-#define R_VECT_READ__dma8__BITNR 24
-#define R_VECT_READ__dma8__WIDTH 1
-#define R_VECT_READ__dma8__active 1
-#define R_VECT_READ__dma8__inactive 0
-#define R_VECT_READ__dma7__BITNR 23
-#define R_VECT_READ__dma7__WIDTH 1
-#define R_VECT_READ__dma7__active 1
-#define R_VECT_READ__dma7__inactive 0
-#define R_VECT_READ__dma6__BITNR 22
-#define R_VECT_READ__dma6__WIDTH 1
-#define R_VECT_READ__dma6__active 1
-#define R_VECT_READ__dma6__inactive 0
-#define R_VECT_READ__dma5__BITNR 21
-#define R_VECT_READ__dma5__WIDTH 1
-#define R_VECT_READ__dma5__active 1
-#define R_VECT_READ__dma5__inactive 0
-#define R_VECT_READ__dma4__BITNR 20
-#define R_VECT_READ__dma4__WIDTH 1
-#define R_VECT_READ__dma4__active 1
-#define R_VECT_READ__dma4__inactive 0
-#define R_VECT_READ__dma3__BITNR 19
-#define R_VECT_READ__dma3__WIDTH 1
-#define R_VECT_READ__dma3__active 1
-#define R_VECT_READ__dma3__inactive 0
-#define R_VECT_READ__dma2__BITNR 18
-#define R_VECT_READ__dma2__WIDTH 1
-#define R_VECT_READ__dma2__active 1
-#define R_VECT_READ__dma2__inactive 0
-#define R_VECT_READ__dma1__BITNR 17
-#define R_VECT_READ__dma1__WIDTH 1
-#define R_VECT_READ__dma1__active 1
-#define R_VECT_READ__dma1__inactive 0
-#define R_VECT_READ__dma0__BITNR 16
-#define R_VECT_READ__dma0__WIDTH 1
-#define R_VECT_READ__dma0__active 1
-#define R_VECT_READ__dma0__inactive 0
-#define R_VECT_READ__ext_dma1__BITNR 13
-#define R_VECT_READ__ext_dma1__WIDTH 1
-#define R_VECT_READ__ext_dma1__active 1
-#define R_VECT_READ__ext_dma1__inactive 0
-#define R_VECT_READ__ext_dma0__BITNR 12
-#define R_VECT_READ__ext_dma0__WIDTH 1
-#define R_VECT_READ__ext_dma0__active 1
-#define R_VECT_READ__ext_dma0__inactive 0
-#define R_VECT_READ__pa__BITNR 11
-#define R_VECT_READ__pa__WIDTH 1
-#define R_VECT_READ__pa__active 1
-#define R_VECT_READ__pa__inactive 0
-#define R_VECT_READ__irq_intnr__BITNR 10
-#define R_VECT_READ__irq_intnr__WIDTH 1
-#define R_VECT_READ__irq_intnr__active 1
-#define R_VECT_READ__irq_intnr__inactive 0
-#define R_VECT_READ__sw__BITNR 9
-#define R_VECT_READ__sw__WIDTH 1
-#define R_VECT_READ__sw__active 1
-#define R_VECT_READ__sw__inactive 0
-#define R_VECT_READ__serial__BITNR 8
-#define R_VECT_READ__serial__WIDTH 1
-#define R_VECT_READ__serial__active 1
-#define R_VECT_READ__serial__inactive 0
-#define R_VECT_READ__snmp__BITNR 7
-#define R_VECT_READ__snmp__WIDTH 1
-#define R_VECT_READ__snmp__active 1
-#define R_VECT_READ__snmp__inactive 0
-#define R_VECT_READ__network__BITNR 6
-#define R_VECT_READ__network__WIDTH 1
-#define R_VECT_READ__network__active 1
-#define R_VECT_READ__network__inactive 0
-#define R_VECT_READ__scsi1__BITNR 5
-#define R_VECT_READ__scsi1__WIDTH 1
-#define R_VECT_READ__scsi1__active 1
-#define R_VECT_READ__scsi1__inactive 0
-#define R_VECT_READ__par1__BITNR 5
-#define R_VECT_READ__par1__WIDTH 1
-#define R_VECT_READ__par1__active 1
-#define R_VECT_READ__par1__inactive 0
-#define R_VECT_READ__scsi0__BITNR 4
-#define R_VECT_READ__scsi0__WIDTH 1
-#define R_VECT_READ__scsi0__active 1
-#define R_VECT_READ__scsi0__inactive 0
-#define R_VECT_READ__par0__BITNR 4
-#define R_VECT_READ__par0__WIDTH 1
-#define R_VECT_READ__par0__active 1
-#define R_VECT_READ__par0__inactive 0
-#define R_VECT_READ__ata__BITNR 4
-#define R_VECT_READ__ata__WIDTH 1
-#define R_VECT_READ__ata__active 1
-#define R_VECT_READ__ata__inactive 0
-#define R_VECT_READ__mio__BITNR 4
-#define R_VECT_READ__mio__WIDTH 1
-#define R_VECT_READ__mio__active 1
-#define R_VECT_READ__mio__inactive 0
-#define R_VECT_READ__timer1__BITNR 3
-#define R_VECT_READ__timer1__WIDTH 1
-#define R_VECT_READ__timer1__active 1
-#define R_VECT_READ__timer1__inactive 0
-#define R_VECT_READ__timer0__BITNR 2
-#define R_VECT_READ__timer0__WIDTH 1
-#define R_VECT_READ__timer0__active 1
-#define R_VECT_READ__timer0__inactive 0
-#define R_VECT_READ__nmi__BITNR 1
-#define R_VECT_READ__nmi__WIDTH 1
-#define R_VECT_READ__nmi__active 1
-#define R_VECT_READ__nmi__inactive 0
-#define R_VECT_READ__some__BITNR 0
-#define R_VECT_READ__some__WIDTH 1
-#define R_VECT_READ__some__active 1
-#define R_VECT_READ__some__inactive 0
-
-#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc)
-#define R_VECT_MASK_SET__usb__BITNR 31
-#define R_VECT_MASK_SET__usb__WIDTH 1
-#define R_VECT_MASK_SET__usb__set 1
-#define R_VECT_MASK_SET__usb__nop 0
-#define R_VECT_MASK_SET__dma9__BITNR 25
-#define R_VECT_MASK_SET__dma9__WIDTH 1
-#define R_VECT_MASK_SET__dma9__set 1
-#define R_VECT_MASK_SET__dma9__nop 0
-#define R_VECT_MASK_SET__dma8__BITNR 24
-#define R_VECT_MASK_SET__dma8__WIDTH 1
-#define R_VECT_MASK_SET__dma8__set 1
-#define R_VECT_MASK_SET__dma8__nop 0
-#define R_VECT_MASK_SET__dma7__BITNR 23
-#define R_VECT_MASK_SET__dma7__WIDTH 1
-#define R_VECT_MASK_SET__dma7__set 1
-#define R_VECT_MASK_SET__dma7__nop 0
-#define R_VECT_MASK_SET__dma6__BITNR 22
-#define R_VECT_MASK_SET__dma6__WIDTH 1
-#define R_VECT_MASK_SET__dma6__set 1
-#define R_VECT_MASK_SET__dma6__nop 0
-#define R_VECT_MASK_SET__dma5__BITNR 21
-#define R_VECT_MASK_SET__dma5__WIDTH 1
-#define R_VECT_MASK_SET__dma5__set 1
-#define R_VECT_MASK_SET__dma5__nop 0
-#define R_VECT_MASK_SET__dma4__BITNR 20
-#define R_VECT_MASK_SET__dma4__WIDTH 1
-#define R_VECT_MASK_SET__dma4__set 1
-#define R_VECT_MASK_SET__dma4__nop 0
-#define R_VECT_MASK_SET__dma3__BITNR 19
-#define R_VECT_MASK_SET__dma3__WIDTH 1
-#define R_VECT_MASK_SET__dma3__set 1
-#define R_VECT_MASK_SET__dma3__nop 0
-#define R_VECT_MASK_SET__dma2__BITNR 18
-#define R_VECT_MASK_SET__dma2__WIDTH 1
-#define R_VECT_MASK_SET__dma2__set 1
-#define R_VECT_MASK_SET__dma2__nop 0
-#define R_VECT_MASK_SET__dma1__BITNR 17
-#define R_VECT_MASK_SET__dma1__WIDTH 1
-#define R_VECT_MASK_SET__dma1__set 1
-#define R_VECT_MASK_SET__dma1__nop 0
-#define R_VECT_MASK_SET__dma0__BITNR 16
-#define R_VECT_MASK_SET__dma0__WIDTH 1
-#define R_VECT_MASK_SET__dma0__set 1
-#define R_VECT_MASK_SET__dma0__nop 0
-#define R_VECT_MASK_SET__ext_dma1__BITNR 13
-#define R_VECT_MASK_SET__ext_dma1__WIDTH 1
-#define R_VECT_MASK_SET__ext_dma1__set 1
-#define R_VECT_MASK_SET__ext_dma1__nop 0
-#define R_VECT_MASK_SET__ext_dma0__BITNR 12
-#define R_VECT_MASK_SET__ext_dma0__WIDTH 1
-#define R_VECT_MASK_SET__ext_dma0__set 1
-#define R_VECT_MASK_SET__ext_dma0__nop 0
-#define R_VECT_MASK_SET__pa__BITNR 11
-#define R_VECT_MASK_SET__pa__WIDTH 1
-#define R_VECT_MASK_SET__pa__set 1
-#define R_VECT_MASK_SET__pa__nop 0
-#define R_VECT_MASK_SET__irq_intnr__BITNR 10
-#define R_VECT_MASK_SET__irq_intnr__WIDTH 1
-#define R_VECT_MASK_SET__irq_intnr__set 1
-#define R_VECT_MASK_SET__irq_intnr__nop 0
-#define R_VECT_MASK_SET__sw__BITNR 9
-#define R_VECT_MASK_SET__sw__WIDTH 1
-#define R_VECT_MASK_SET__sw__set 1
-#define R_VECT_MASK_SET__sw__nop 0
-#define R_VECT_MASK_SET__serial__BITNR 8
-#define R_VECT_MASK_SET__serial__WIDTH 1
-#define R_VECT_MASK_SET__serial__set 1
-#define R_VECT_MASK_SET__serial__nop 0
-#define R_VECT_MASK_SET__snmp__BITNR 7
-#define R_VECT_MASK_SET__snmp__WIDTH 1
-#define R_VECT_MASK_SET__snmp__set 1
-#define R_VECT_MASK_SET__snmp__nop 0
-#define R_VECT_MASK_SET__network__BITNR 6
-#define R_VECT_MASK_SET__network__WIDTH 1
-#define R_VECT_MASK_SET__network__set 1
-#define R_VECT_MASK_SET__network__nop 0
-#define R_VECT_MASK_SET__scsi1__BITNR 5
-#define R_VECT_MASK_SET__scsi1__WIDTH 1
-#define R_VECT_MASK_SET__scsi1__set 1
-#define R_VECT_MASK_SET__scsi1__nop 0
-#define R_VECT_MASK_SET__par1__BITNR 5
-#define R_VECT_MASK_SET__par1__WIDTH 1
-#define R_VECT_MASK_SET__par1__set 1
-#define R_VECT_MASK_SET__par1__nop 0
-#define R_VECT_MASK_SET__scsi0__BITNR 4
-#define R_VECT_MASK_SET__scsi0__WIDTH 1
-#define R_VECT_MASK_SET__scsi0__set 1
-#define R_VECT_MASK_SET__scsi0__nop 0
-#define R_VECT_MASK_SET__par0__BITNR 4
-#define R_VECT_MASK_SET__par0__WIDTH 1
-#define R_VECT_MASK_SET__par0__set 1
-#define R_VECT_MASK_SET__par0__nop 0
-#define R_VECT_MASK_SET__ata__BITNR 4
-#define R_VECT_MASK_SET__ata__WIDTH 1
-#define R_VECT_MASK_SET__ata__set 1
-#define R_VECT_MASK_SET__ata__nop 0
-#define R_VECT_MASK_SET__mio__BITNR 4
-#define R_VECT_MASK_SET__mio__WIDTH 1
-#define R_VECT_MASK_SET__mio__set 1
-#define R_VECT_MASK_SET__mio__nop 0
-#define R_VECT_MASK_SET__timer1__BITNR 3
-#define R_VECT_MASK_SET__timer1__WIDTH 1
-#define R_VECT_MASK_SET__timer1__set 1
-#define R_VECT_MASK_SET__timer1__nop 0
-#define R_VECT_MASK_SET__timer0__BITNR 2
-#define R_VECT_MASK_SET__timer0__WIDTH 1
-#define R_VECT_MASK_SET__timer0__set 1
-#define R_VECT_MASK_SET__timer0__nop 0
-#define R_VECT_MASK_SET__nmi__BITNR 1
-#define R_VECT_MASK_SET__nmi__WIDTH 1
-#define R_VECT_MASK_SET__nmi__set 1
-#define R_VECT_MASK_SET__nmi__nop 0
-#define R_VECT_MASK_SET__some__BITNR 0
-#define R_VECT_MASK_SET__some__WIDTH 1
-#define R_VECT_MASK_SET__some__set 1
-#define R_VECT_MASK_SET__some__nop 0
-
-/*
-!* DMA registers
-!*/
-
-#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c)
-#define R_SET_EOP__ch9_eop__BITNR 3
-#define R_SET_EOP__ch9_eop__WIDTH 1
-#define R_SET_EOP__ch9_eop__set 1
-#define R_SET_EOP__ch9_eop__nop 0
-#define R_SET_EOP__ch7_eop__BITNR 2
-#define R_SET_EOP__ch7_eop__WIDTH 1
-#define R_SET_EOP__ch7_eop__set 1
-#define R_SET_EOP__ch7_eop__nop 0
-#define R_SET_EOP__ch5_eop__BITNR 1
-#define R_SET_EOP__ch5_eop__WIDTH 1
-#define R_SET_EOP__ch5_eop__set 1
-#define R_SET_EOP__ch5_eop__nop 0
-#define R_SET_EOP__ch3_eop__BITNR 0
-#define R_SET_EOP__ch3_eop__WIDTH 1
-#define R_SET_EOP__ch3_eop__set 1
-#define R_SET_EOP__ch3_eop__nop 0
-
-#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100)
-#define R_DMA_CH0_HWSW__hw__BITNR 16
-#define R_DMA_CH0_HWSW__hw__WIDTH 16
-#define R_DMA_CH0_HWSW__sw__BITNR 0
-#define R_DMA_CH0_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c)
-#define R_DMA_CH0_DESCR__descr__BITNR 0
-#define R_DMA_CH0_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104)
-#define R_DMA_CH0_NEXT__next__BITNR 0
-#define R_DMA_CH0_NEXT__next__WIDTH 32
-
-#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108)
-#define R_DMA_CH0_BUF__buf__BITNR 0
-#define R_DMA_CH0_BUF__buf__WIDTH 32
-
-#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0)
-#define R_DMA_CH0_FIRST__first__BITNR 0
-#define R_DMA_CH0_FIRST__first__WIDTH 32
-
-#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0)
-#define R_DMA_CH0_CMD__cmd__BITNR 0
-#define R_DMA_CH0_CMD__cmd__WIDTH 3
-#define R_DMA_CH0_CMD__cmd__hold 0
-#define R_DMA_CH0_CMD__cmd__start 1
-#define R_DMA_CH0_CMD__cmd__restart 3
-#define R_DMA_CH0_CMD__cmd__continue 3
-#define R_DMA_CH0_CMD__cmd__reset 4
-
-#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1)
-#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH0_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2)
-#define R_DMA_CH0_STATUS__avail__BITNR 0
-#define R_DMA_CH0_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110)
-#define R_DMA_CH1_HWSW__hw__BITNR 16
-#define R_DMA_CH1_HWSW__hw__WIDTH 16
-#define R_DMA_CH1_HWSW__sw__BITNR 0
-#define R_DMA_CH1_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c)
-#define R_DMA_CH1_DESCR__descr__BITNR 0
-#define R_DMA_CH1_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114)
-#define R_DMA_CH1_NEXT__next__BITNR 0
-#define R_DMA_CH1_NEXT__next__WIDTH 32
-
-#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118)
-#define R_DMA_CH1_BUF__buf__BITNR 0
-#define R_DMA_CH1_BUF__buf__WIDTH 32
-
-#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4)
-#define R_DMA_CH1_FIRST__first__BITNR 0
-#define R_DMA_CH1_FIRST__first__WIDTH 32
-
-#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4)
-#define R_DMA_CH1_CMD__cmd__BITNR 0
-#define R_DMA_CH1_CMD__cmd__WIDTH 3
-#define R_DMA_CH1_CMD__cmd__hold 0
-#define R_DMA_CH1_CMD__cmd__start 1
-#define R_DMA_CH1_CMD__cmd__restart 3
-#define R_DMA_CH1_CMD__cmd__continue 3
-#define R_DMA_CH1_CMD__cmd__reset 4
-
-#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5)
-#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH1_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6)
-#define R_DMA_CH1_STATUS__avail__BITNR 0
-#define R_DMA_CH1_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120)
-#define R_DMA_CH2_HWSW__hw__BITNR 16
-#define R_DMA_CH2_HWSW__hw__WIDTH 16
-#define R_DMA_CH2_HWSW__sw__BITNR 0
-#define R_DMA_CH2_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c)
-#define R_DMA_CH2_DESCR__descr__BITNR 0
-#define R_DMA_CH2_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124)
-#define R_DMA_CH2_NEXT__next__BITNR 0
-#define R_DMA_CH2_NEXT__next__WIDTH 32
-
-#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128)
-#define R_DMA_CH2_BUF__buf__BITNR 0
-#define R_DMA_CH2_BUF__buf__WIDTH 32
-
-#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8)
-#define R_DMA_CH2_FIRST__first__BITNR 0
-#define R_DMA_CH2_FIRST__first__WIDTH 32
-
-#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8)
-#define R_DMA_CH2_CMD__cmd__BITNR 0
-#define R_DMA_CH2_CMD__cmd__WIDTH 3
-#define R_DMA_CH2_CMD__cmd__hold 0
-#define R_DMA_CH2_CMD__cmd__start 1
-#define R_DMA_CH2_CMD__cmd__restart 3
-#define R_DMA_CH2_CMD__cmd__continue 3
-#define R_DMA_CH2_CMD__cmd__reset 4
-
-#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9)
-#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH2_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da)
-#define R_DMA_CH2_STATUS__avail__BITNR 0
-#define R_DMA_CH2_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130)
-#define R_DMA_CH3_HWSW__hw__BITNR 16
-#define R_DMA_CH3_HWSW__hw__WIDTH 16
-#define R_DMA_CH3_HWSW__sw__BITNR 0
-#define R_DMA_CH3_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c)
-#define R_DMA_CH3_DESCR__descr__BITNR 0
-#define R_DMA_CH3_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134)
-#define R_DMA_CH3_NEXT__next__BITNR 0
-#define R_DMA_CH3_NEXT__next__WIDTH 32
-
-#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138)
-#define R_DMA_CH3_BUF__buf__BITNR 0
-#define R_DMA_CH3_BUF__buf__WIDTH 32
-
-#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac)
-#define R_DMA_CH3_FIRST__first__BITNR 0
-#define R_DMA_CH3_FIRST__first__WIDTH 32
-
-#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc)
-#define R_DMA_CH3_CMD__cmd__BITNR 0
-#define R_DMA_CH3_CMD__cmd__WIDTH 3
-#define R_DMA_CH3_CMD__cmd__hold 0
-#define R_DMA_CH3_CMD__cmd__start 1
-#define R_DMA_CH3_CMD__cmd__restart 3
-#define R_DMA_CH3_CMD__cmd__continue 3
-#define R_DMA_CH3_CMD__cmd__reset 4
-
-#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd)
-#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH3_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de)
-#define R_DMA_CH3_STATUS__avail__BITNR 0
-#define R_DMA_CH3_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140)
-#define R_DMA_CH4_HWSW__hw__BITNR 16
-#define R_DMA_CH4_HWSW__hw__WIDTH 16
-#define R_DMA_CH4_HWSW__sw__BITNR 0
-#define R_DMA_CH4_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c)
-#define R_DMA_CH4_DESCR__descr__BITNR 0
-#define R_DMA_CH4_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144)
-#define R_DMA_CH4_NEXT__next__BITNR 0
-#define R_DMA_CH4_NEXT__next__WIDTH 32
-
-#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148)
-#define R_DMA_CH4_BUF__buf__BITNR 0
-#define R_DMA_CH4_BUF__buf__WIDTH 32
-
-#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0)
-#define R_DMA_CH4_FIRST__first__BITNR 0
-#define R_DMA_CH4_FIRST__first__WIDTH 32
-
-#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0)
-#define R_DMA_CH4_CMD__cmd__BITNR 0
-#define R_DMA_CH4_CMD__cmd__WIDTH 3
-#define R_DMA_CH4_CMD__cmd__hold 0
-#define R_DMA_CH4_CMD__cmd__start 1
-#define R_DMA_CH4_CMD__cmd__restart 3
-#define R_DMA_CH4_CMD__cmd__continue 3
-#define R_DMA_CH4_CMD__cmd__reset 4
-
-#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1)
-#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH4_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2)
-#define R_DMA_CH4_STATUS__avail__BITNR 0
-#define R_DMA_CH4_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150)
-#define R_DMA_CH5_HWSW__hw__BITNR 16
-#define R_DMA_CH5_HWSW__hw__WIDTH 16
-#define R_DMA_CH5_HWSW__sw__BITNR 0
-#define R_DMA_CH5_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c)
-#define R_DMA_CH5_DESCR__descr__BITNR 0
-#define R_DMA_CH5_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154)
-#define R_DMA_CH5_NEXT__next__BITNR 0
-#define R_DMA_CH5_NEXT__next__WIDTH 32
-
-#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158)
-#define R_DMA_CH5_BUF__buf__BITNR 0
-#define R_DMA_CH5_BUF__buf__WIDTH 32
-
-#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4)
-#define R_DMA_CH5_FIRST__first__BITNR 0
-#define R_DMA_CH5_FIRST__first__WIDTH 32
-
-#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4)
-#define R_DMA_CH5_CMD__cmd__BITNR 0
-#define R_DMA_CH5_CMD__cmd__WIDTH 3
-#define R_DMA_CH5_CMD__cmd__hold 0
-#define R_DMA_CH5_CMD__cmd__start 1
-#define R_DMA_CH5_CMD__cmd__restart 3
-#define R_DMA_CH5_CMD__cmd__continue 3
-#define R_DMA_CH5_CMD__cmd__reset 4
-
-#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5)
-#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH5_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6)
-#define R_DMA_CH5_STATUS__avail__BITNR 0
-#define R_DMA_CH5_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160)
-#define R_DMA_CH6_HWSW__hw__BITNR 16
-#define R_DMA_CH6_HWSW__hw__WIDTH 16
-#define R_DMA_CH6_HWSW__sw__BITNR 0
-#define R_DMA_CH6_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c)
-#define R_DMA_CH6_DESCR__descr__BITNR 0
-#define R_DMA_CH6_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164)
-#define R_DMA_CH6_NEXT__next__BITNR 0
-#define R_DMA_CH6_NEXT__next__WIDTH 32
-
-#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168)
-#define R_DMA_CH6_BUF__buf__BITNR 0
-#define R_DMA_CH6_BUF__buf__WIDTH 32
-
-#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8)
-#define R_DMA_CH6_FIRST__first__BITNR 0
-#define R_DMA_CH6_FIRST__first__WIDTH 32
-
-#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8)
-#define R_DMA_CH6_CMD__cmd__BITNR 0
-#define R_DMA_CH6_CMD__cmd__WIDTH 3
-#define R_DMA_CH6_CMD__cmd__hold 0
-#define R_DMA_CH6_CMD__cmd__start 1
-#define R_DMA_CH6_CMD__cmd__restart 3
-#define R_DMA_CH6_CMD__cmd__continue 3
-#define R_DMA_CH6_CMD__cmd__reset 4
-
-#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9)
-#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH6_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea)
-#define R_DMA_CH6_STATUS__avail__BITNR 0
-#define R_DMA_CH6_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170)
-#define R_DMA_CH7_HWSW__hw__BITNR 16
-#define R_DMA_CH7_HWSW__hw__WIDTH 16
-#define R_DMA_CH7_HWSW__sw__BITNR 0
-#define R_DMA_CH7_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c)
-#define R_DMA_CH7_DESCR__descr__BITNR 0
-#define R_DMA_CH7_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174)
-#define R_DMA_CH7_NEXT__next__BITNR 0
-#define R_DMA_CH7_NEXT__next__WIDTH 32
-
-#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178)
-#define R_DMA_CH7_BUF__buf__BITNR 0
-#define R_DMA_CH7_BUF__buf__WIDTH 32
-
-#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc)
-#define R_DMA_CH7_FIRST__first__BITNR 0
-#define R_DMA_CH7_FIRST__first__WIDTH 32
-
-#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec)
-#define R_DMA_CH7_CMD__cmd__BITNR 0
-#define R_DMA_CH7_CMD__cmd__WIDTH 3
-#define R_DMA_CH7_CMD__cmd__hold 0
-#define R_DMA_CH7_CMD__cmd__start 1
-#define R_DMA_CH7_CMD__cmd__restart 3
-#define R_DMA_CH7_CMD__cmd__continue 3
-#define R_DMA_CH7_CMD__cmd__reset 4
-
-#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed)
-#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH7_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee)
-#define R_DMA_CH7_STATUS__avail__BITNR 0
-#define R_DMA_CH7_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180)
-#define R_DMA_CH8_HWSW__hw__BITNR 16
-#define R_DMA_CH8_HWSW__hw__WIDTH 16
-#define R_DMA_CH8_HWSW__sw__BITNR 0
-#define R_DMA_CH8_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c)
-#define R_DMA_CH8_DESCR__descr__BITNR 0
-#define R_DMA_CH8_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184)
-#define R_DMA_CH8_NEXT__next__BITNR 0
-#define R_DMA_CH8_NEXT__next__WIDTH 32
-
-#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188)
-#define R_DMA_CH8_BUF__buf__BITNR 0
-#define R_DMA_CH8_BUF__buf__WIDTH 32
-
-#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0)
-#define R_DMA_CH8_FIRST__first__BITNR 0
-#define R_DMA_CH8_FIRST__first__WIDTH 32
-
-#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0)
-#define R_DMA_CH8_CMD__cmd__BITNR 0
-#define R_DMA_CH8_CMD__cmd__WIDTH 3
-#define R_DMA_CH8_CMD__cmd__hold 0
-#define R_DMA_CH8_CMD__cmd__start 1
-#define R_DMA_CH8_CMD__cmd__restart 3
-#define R_DMA_CH8_CMD__cmd__continue 3
-#define R_DMA_CH8_CMD__cmd__reset 4
-
-#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1)
-#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2)
-#define R_DMA_CH8_STATUS__avail__BITNR 0
-#define R_DMA_CH8_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c)
-#define R_DMA_CH8_SUB__sub__BITNR 0
-#define R_DMA_CH8_SUB__sub__WIDTH 32
-
-#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0)
-#define R_DMA_CH8_NEP__nep__BITNR 0
-#define R_DMA_CH8_NEP__nep__WIDTH 32
-
-#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8)
-#define R_DMA_CH8_SUB0_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3)
-#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB0_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB0_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3)
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc)
-#define R_DMA_CH8_SUB1_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7)
-#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB1_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB1_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7)
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8)
-#define R_DMA_CH8_SUB2_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db)
-#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB2_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB2_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb)
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc)
-#define R_DMA_CH8_SUB3_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df)
-#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB3_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB3_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef)
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190)
-#define R_DMA_CH9_HWSW__hw__BITNR 16
-#define R_DMA_CH9_HWSW__hw__WIDTH 16
-#define R_DMA_CH9_HWSW__sw__BITNR 0
-#define R_DMA_CH9_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c)
-#define R_DMA_CH9_DESCR__descr__BITNR 0
-#define R_DMA_CH9_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194)
-#define R_DMA_CH9_NEXT__next__BITNR 0
-#define R_DMA_CH9_NEXT__next__WIDTH 32
-
-#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198)
-#define R_DMA_CH9_BUF__buf__BITNR 0
-#define R_DMA_CH9_BUF__buf__WIDTH 32
-
-#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4)
-#define R_DMA_CH9_FIRST__first__BITNR 0
-#define R_DMA_CH9_FIRST__first__WIDTH 32
-
-#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4)
-#define R_DMA_CH9_CMD__cmd__BITNR 0
-#define R_DMA_CH9_CMD__cmd__WIDTH 3
-#define R_DMA_CH9_CMD__cmd__hold 0
-#define R_DMA_CH9_CMD__cmd__start 1
-#define R_DMA_CH9_CMD__cmd__restart 3
-#define R_DMA_CH9_CMD__cmd__continue 3
-#define R_DMA_CH9_CMD__cmd__reset 4
-
-#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5)
-#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH9_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6)
-#define R_DMA_CH9_STATUS__avail__BITNR 0
-#define R_DMA_CH9_STATUS__avail__WIDTH 7
-
-/*
-!* Test mode registers
-!*/
-
-#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc)
-#define R_TEST_MODE__single_step__BITNR 19
-#define R_TEST_MODE__single_step__WIDTH 1
-#define R_TEST_MODE__single_step__on 1
-#define R_TEST_MODE__single_step__off 0
-#define R_TEST_MODE__step_wr__BITNR 18
-#define R_TEST_MODE__step_wr__WIDTH 1
-#define R_TEST_MODE__step_wr__on 1
-#define R_TEST_MODE__step_wr__off 0
-#define R_TEST_MODE__step_rd__BITNR 17
-#define R_TEST_MODE__step_rd__WIDTH 1
-#define R_TEST_MODE__step_rd__on 1
-#define R_TEST_MODE__step_rd__off 0
-#define R_TEST_MODE__step_fetch__BITNR 16
-#define R_TEST_MODE__step_fetch__WIDTH 1
-#define R_TEST_MODE__step_fetch__on 1
-#define R_TEST_MODE__step_fetch__off 0
-#define R_TEST_MODE__mmu_test__BITNR 12
-#define R_TEST_MODE__mmu_test__WIDTH 1
-#define R_TEST_MODE__mmu_test__on 1
-#define R_TEST_MODE__mmu_test__off 0
-#define R_TEST_MODE__usb_test__BITNR 11
-#define R_TEST_MODE__usb_test__WIDTH 1
-#define R_TEST_MODE__usb_test__on 1
-#define R_TEST_MODE__usb_test__off 0
-#define R_TEST_MODE__scsi_timer_test__BITNR 10
-#define R_TEST_MODE__scsi_timer_test__WIDTH 1
-#define R_TEST_MODE__scsi_timer_test__on 1
-#define R_TEST_MODE__scsi_timer_test__off 0
-#define R_TEST_MODE__backoff__BITNR 9
-#define R_TEST_MODE__backoff__WIDTH 1
-#define R_TEST_MODE__backoff__on 1
-#define R_TEST_MODE__backoff__off 0
-#define R_TEST_MODE__snmp_test__BITNR 8
-#define R_TEST_MODE__snmp_test__WIDTH 1
-#define R_TEST_MODE__snmp_test__on 1
-#define R_TEST_MODE__snmp_test__off 0
-#define R_TEST_MODE__snmp_inc__BITNR 7
-#define R_TEST_MODE__snmp_inc__WIDTH 1
-#define R_TEST_MODE__snmp_inc__do 1
-#define R_TEST_MODE__snmp_inc__dont 0
-#define R_TEST_MODE__ser_loop__BITNR 6
-#define R_TEST_MODE__ser_loop__WIDTH 1
-#define R_TEST_MODE__ser_loop__on 1
-#define R_TEST_MODE__ser_loop__off 0
-#define R_TEST_MODE__baudrate__BITNR 5
-#define R_TEST_MODE__baudrate__WIDTH 1
-#define R_TEST_MODE__baudrate__on 1
-#define R_TEST_MODE__baudrate__off 0
-#define R_TEST_MODE__timer__BITNR 3
-#define R_TEST_MODE__timer__WIDTH 2
-#define R_TEST_MODE__timer__off 0
-#define R_TEST_MODE__timer__even 1
-#define R_TEST_MODE__timer__odd 2
-#define R_TEST_MODE__timer__all 3
-#define R_TEST_MODE__cache_test__BITNR 2
-#define R_TEST_MODE__cache_test__WIDTH 1
-#define R_TEST_MODE__cache_test__normal 0
-#define R_TEST_MODE__cache_test__test 1
-#define R_TEST_MODE__tag_test__BITNR 1
-#define R_TEST_MODE__tag_test__WIDTH 1
-#define R_TEST_MODE__tag_test__normal 0
-#define R_TEST_MODE__tag_test__test 1
-#define R_TEST_MODE__cache_enable__BITNR 0
-#define R_TEST_MODE__cache_enable__WIDTH 1
-#define R_TEST_MODE__cache_enable__enable 1
-#define R_TEST_MODE__cache_enable__disable 0
-
-#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe)
-#define R_SINGLE_STEP__single_step__BITNR 3
-#define R_SINGLE_STEP__single_step__WIDTH 1
-#define R_SINGLE_STEP__single_step__on 1
-#define R_SINGLE_STEP__single_step__off 0
-#define R_SINGLE_STEP__step_wr__BITNR 2
-#define R_SINGLE_STEP__step_wr__WIDTH 1
-#define R_SINGLE_STEP__step_wr__on 1
-#define R_SINGLE_STEP__step_wr__off 0
-#define R_SINGLE_STEP__step_rd__BITNR 1
-#define R_SINGLE_STEP__step_rd__WIDTH 1
-#define R_SINGLE_STEP__step_rd__on 1
-#define R_SINGLE_STEP__step_rd__off 0
-#define R_SINGLE_STEP__step_fetch__BITNR 0
-#define R_SINGLE_STEP__step_fetch__WIDTH 1
-#define R_SINGLE_STEP__step_fetch__on 1
-#define R_SINGLE_STEP__step_fetch__off 0
-
-/*
-!* USB interface control registers
-!*/
-
-#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200)
-#define R_USB_REVISION__major__BITNR 4
-#define R_USB_REVISION__major__WIDTH 4
-#define R_USB_REVISION__minor__BITNR 0
-#define R_USB_REVISION__minor__WIDTH 4
-
-#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201)
-#define R_USB_COMMAND__port_sel__BITNR 6
-#define R_USB_COMMAND__port_sel__WIDTH 2
-#define R_USB_COMMAND__port_sel__nop 0
-#define R_USB_COMMAND__port_sel__port1 1
-#define R_USB_COMMAND__port_sel__port2 2
-#define R_USB_COMMAND__port_sel__both 3
-#define R_USB_COMMAND__port_cmd__BITNR 4
-#define R_USB_COMMAND__port_cmd__WIDTH 2
-#define R_USB_COMMAND__port_cmd__reset 0
-#define R_USB_COMMAND__port_cmd__disable 1
-#define R_USB_COMMAND__port_cmd__suspend 2
-#define R_USB_COMMAND__port_cmd__resume 3
-#define R_USB_COMMAND__busy__BITNR 3
-#define R_USB_COMMAND__busy__WIDTH 1
-#define R_USB_COMMAND__busy__no 0
-#define R_USB_COMMAND__busy__yes 1
-#define R_USB_COMMAND__ctrl_cmd__BITNR 0
-#define R_USB_COMMAND__ctrl_cmd__WIDTH 3
-#define R_USB_COMMAND__ctrl_cmd__nop 0
-#define R_USB_COMMAND__ctrl_cmd__reset 1
-#define R_USB_COMMAND__ctrl_cmd__deconfig 2
-#define R_USB_COMMAND__ctrl_cmd__host_config 3
-#define R_USB_COMMAND__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND__ctrl_cmd__host_nop 5
-#define R_USB_COMMAND__ctrl_cmd__host_run 6
-#define R_USB_COMMAND__ctrl_cmd__host_stop 7
-
-#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201)
-#define R_USB_COMMAND_DEV__port_sel__BITNR 6
-#define R_USB_COMMAND_DEV__port_sel__WIDTH 2
-#define R_USB_COMMAND_DEV__port_sel__nop 0
-#define R_USB_COMMAND_DEV__port_sel__dummy1 1
-#define R_USB_COMMAND_DEV__port_sel__dummy2 2
-#define R_USB_COMMAND_DEV__port_sel__any 3
-#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
-#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2
-#define R_USB_COMMAND_DEV__port_cmd__active 0
-#define R_USB_COMMAND_DEV__port_cmd__passive 1
-#define R_USB_COMMAND_DEV__port_cmd__nop 2
-#define R_USB_COMMAND_DEV__port_cmd__wakeup 3
-#define R_USB_COMMAND_DEV__busy__BITNR 3
-#define R_USB_COMMAND_DEV__busy__WIDTH 1
-#define R_USB_COMMAND_DEV__busy__no 0
-#define R_USB_COMMAND_DEV__busy__yes 1
-#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
-#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3
-#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0
-#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1
-#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2
-#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7
-
-#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202)
-#define R_USB_STATUS__ourun__BITNR 5
-#define R_USB_STATUS__ourun__WIDTH 1
-#define R_USB_STATUS__ourun__no 0
-#define R_USB_STATUS__ourun__yes 1
-#define R_USB_STATUS__perror__BITNR 4
-#define R_USB_STATUS__perror__WIDTH 1
-#define R_USB_STATUS__perror__no 0
-#define R_USB_STATUS__perror__yes 1
-#define R_USB_STATUS__device_mode__BITNR 3
-#define R_USB_STATUS__device_mode__WIDTH 1
-#define R_USB_STATUS__device_mode__no 0
-#define R_USB_STATUS__device_mode__yes 1
-#define R_USB_STATUS__host_mode__BITNR 2
-#define R_USB_STATUS__host_mode__WIDTH 1
-#define R_USB_STATUS__host_mode__no 0
-#define R_USB_STATUS__host_mode__yes 1
-#define R_USB_STATUS__started__BITNR 1
-#define R_USB_STATUS__started__WIDTH 1
-#define R_USB_STATUS__started__no 0
-#define R_USB_STATUS__started__yes 1
-#define R_USB_STATUS__running__BITNR 0
-#define R_USB_STATUS__running__WIDTH 1
-#define R_USB_STATUS__running__no 0
-#define R_USB_STATUS__running__yes 1
-
-#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__iso_eof__nop 0
-#define R_USB_IRQ_MASK_SET__iso_eof__set 1
-#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eof__set 1
-#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__iso_eot__nop 0
-#define R_USB_IRQ_MASK_SET__iso_eot__set 1
-#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eot__set 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
-#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_SET__epid_attn__nop 0
-#define R_USB_IRQ_MASK_SET__epid_attn__set 1
-#define R_USB_IRQ_MASK_SET__sof__BITNR 2
-#define R_USB_IRQ_MASK_SET__sof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__sof__nop 0
-#define R_USB_IRQ_MASK_SET__sof__set 1
-#define R_USB_IRQ_MASK_SET__port_status__BITNR 1
-#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET__port_status__nop 0
-#define R_USB_IRQ_MASK_SET__port_status__set 1
-#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_status__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_status__set 1
-
-#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__iso_eof__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
-#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__iso_eot__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
-#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0
-#define R_USB_IRQ_MASK_READ__epid_attn__pend 1
-#define R_USB_IRQ_MASK_READ__sof__BITNR 2
-#define R_USB_IRQ_MASK_READ__sof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__sof__no_pend 0
-#define R_USB_IRQ_MASK_READ__sof__pend 1
-#define R_USB_IRQ_MASK_READ__port_status__BITNR 1
-#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ__port_status__no_pend 0
-#define R_USB_IRQ_MASK_READ__port_status__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0
-#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1
-#define R_USB_IRQ_MASK_CLR__sof__BITNR 2
-#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__sof__nop 0
-#define R_USB_IRQ_MASK_CLR__sof__clr 1
-#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
-#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__port_status__nop 0
-#define R_USB_IRQ_MASK_CLR__port_status__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1
-
-#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ__iso_eof__BITNR 13
-#define R_USB_IRQ_READ__iso_eof__WIDTH 1
-#define R_USB_IRQ_READ__iso_eof__no_pend 0
-#define R_USB_IRQ_READ__iso_eof__pend 1
-#define R_USB_IRQ_READ__intr_eof__BITNR 12
-#define R_USB_IRQ_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_READ__intr_eof__pend 1
-#define R_USB_IRQ_READ__iso_eot__BITNR 11
-#define R_USB_IRQ_READ__iso_eot__WIDTH 1
-#define R_USB_IRQ_READ__iso_eot__no_pend 0
-#define R_USB_IRQ_READ__iso_eot__pend 1
-#define R_USB_IRQ_READ__intr_eot__BITNR 10
-#define R_USB_IRQ_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_READ__intr_eot__pend 1
-#define R_USB_IRQ_READ__ctl_eot__BITNR 9
-#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_READ__ctl_eot__pend 1
-#define R_USB_IRQ_READ__bulk_eot__BITNR 8
-#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_READ__bulk_eot__pend 1
-#define R_USB_IRQ_READ__epid_attn__BITNR 3
-#define R_USB_IRQ_READ__epid_attn__WIDTH 1
-#define R_USB_IRQ_READ__epid_attn__no_pend 0
-#define R_USB_IRQ_READ__epid_attn__pend 1
-#define R_USB_IRQ_READ__sof__BITNR 2
-#define R_USB_IRQ_READ__sof__WIDTH 1
-#define R_USB_IRQ_READ__sof__no_pend 0
-#define R_USB_IRQ_READ__sof__pend 1
-#define R_USB_IRQ_READ__port_status__BITNR 1
-#define R_USB_IRQ_READ__port_status__WIDTH 1
-#define R_USB_IRQ_READ__port_status__no_pend 0
-#define R_USB_IRQ_READ__port_status__pend 1
-#define R_USB_IRQ_READ__ctl_status__BITNR 0
-#define R_USB_IRQ_READ__ctl_status__WIDTH 1
-#define R_USB_IRQ_READ__ctl_status__no_pend 0
-#define R_USB_IRQ_READ__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1
-#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__sof__set 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1
-
-#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1
-
-#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__out_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0
-#define R_USB_IRQ_READ_DEV__epid_attn__pend 1
-#define R_USB_IRQ_READ_DEV__sof__BITNR 2
-#define R_USB_IRQ_READ_DEV__sof__WIDTH 1
-#define R_USB_IRQ_READ_DEV__sof__no_pend 0
-#define R_USB_IRQ_READ_DEV__sof__pend 1
-#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
-#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_READ_DEV__port_status__no_pend 0
-#define R_USB_IRQ_READ_DEV__port_status__pend 1
-#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0
-#define R_USB_IRQ_READ_DEV__ctl_status__pend 1
-
-#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c)
-#define R_USB_FM_NUMBER__value__BITNR 0
-#define R_USB_FM_NUMBER__value__WIDTH 32
-
-#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210)
-#define R_USB_FM_INTERVAL__fixed__BITNR 6
-#define R_USB_FM_INTERVAL__fixed__WIDTH 8
-#define R_USB_FM_INTERVAL__adj__BITNR 0
-#define R_USB_FM_INTERVAL__adj__WIDTH 6
-
-#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212)
-#define R_USB_FM_REMAINING__value__BITNR 0
-#define R_USB_FM_REMAINING__value__WIDTH 14
-
-#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214)
-#define R_USB_FM_PSTART__value__BITNR 0
-#define R_USB_FM_PSTART__value__WIDTH 14
-
-#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203)
-#define R_USB_RH_STATUS__babble2__BITNR 7
-#define R_USB_RH_STATUS__babble2__WIDTH 1
-#define R_USB_RH_STATUS__babble2__no 0
-#define R_USB_RH_STATUS__babble2__yes 1
-#define R_USB_RH_STATUS__babble1__BITNR 6
-#define R_USB_RH_STATUS__babble1__WIDTH 1
-#define R_USB_RH_STATUS__babble1__no 0
-#define R_USB_RH_STATUS__babble1__yes 1
-#define R_USB_RH_STATUS__bus1__BITNR 4
-#define R_USB_RH_STATUS__bus1__WIDTH 2
-#define R_USB_RH_STATUS__bus1__SE0 0
-#define R_USB_RH_STATUS__bus1__Diff0 1
-#define R_USB_RH_STATUS__bus1__Diff1 2
-#define R_USB_RH_STATUS__bus1__SE1 3
-#define R_USB_RH_STATUS__bus2__BITNR 2
-#define R_USB_RH_STATUS__bus2__WIDTH 2
-#define R_USB_RH_STATUS__bus2__SE0 0
-#define R_USB_RH_STATUS__bus2__Diff0 1
-#define R_USB_RH_STATUS__bus2__Diff1 2
-#define R_USB_RH_STATUS__bus2__SE1 3
-#define R_USB_RH_STATUS__nports__BITNR 0
-#define R_USB_RH_STATUS__nports__WIDTH 2
-
-#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218)
-#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
-#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__speed__full 0
-#define R_USB_RH_PORT_STATUS_1__speed__low 1
-#define R_USB_RH_PORT_STATUS_1__power__BITNR 8
-#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
-#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__reset__no 0
-#define R_USB_RH_PORT_STATUS_1__reset__yes 1
-#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
-#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0
-#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1
-#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
-#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__suspended__no 0
-#define R_USB_RH_PORT_STATUS_1__suspended__yes 1
-#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
-#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__enabled__no 0
-#define R_USB_RH_PORT_STATUS_1__enabled__yes 1
-#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
-#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__connected__no 0
-#define R_USB_RH_PORT_STATUS_1__connected__yes 1
-
-#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a)
-#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
-#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__speed__full 0
-#define R_USB_RH_PORT_STATUS_2__speed__low 1
-#define R_USB_RH_PORT_STATUS_2__power__BITNR 8
-#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
-#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__reset__no 0
-#define R_USB_RH_PORT_STATUS_2__reset__yes 1
-#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
-#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0
-#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1
-#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
-#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__suspended__no 0
-#define R_USB_RH_PORT_STATUS_2__suspended__yes 1
-#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
-#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__enabled__no 0
-#define R_USB_RH_PORT_STATUS_2__enabled__yes 1
-#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
-#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__connected__no 0
-#define R_USB_RH_PORT_STATUS_2__connected__yes 1
-
-#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208)
-#define R_USB_EPT_INDEX__value__BITNR 0
-#define R_USB_EPT_INDEX__value__WIDTH 5
-
-#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA__valid__BITNR 31
-#define R_USB_EPT_DATA__valid__WIDTH 1
-#define R_USB_EPT_DATA__valid__no 0
-#define R_USB_EPT_DATA__valid__yes 1
-#define R_USB_EPT_DATA__hold__BITNR 30
-#define R_USB_EPT_DATA__hold__WIDTH 1
-#define R_USB_EPT_DATA__hold__no 0
-#define R_USB_EPT_DATA__hold__yes 1
-#define R_USB_EPT_DATA__error_count_in__BITNR 28
-#define R_USB_EPT_DATA__error_count_in__WIDTH 2
-#define R_USB_EPT_DATA__t_in__BITNR 27
-#define R_USB_EPT_DATA__t_in__WIDTH 1
-#define R_USB_EPT_DATA__low_speed__BITNR 26
-#define R_USB_EPT_DATA__low_speed__WIDTH 1
-#define R_USB_EPT_DATA__low_speed__no 0
-#define R_USB_EPT_DATA__low_speed__yes 1
-#define R_USB_EPT_DATA__port__BITNR 24
-#define R_USB_EPT_DATA__port__WIDTH 2
-#define R_USB_EPT_DATA__port__any 0
-#define R_USB_EPT_DATA__port__p1 1
-#define R_USB_EPT_DATA__port__p2 2
-#define R_USB_EPT_DATA__port__undef 3
-#define R_USB_EPT_DATA__error_code__BITNR 22
-#define R_USB_EPT_DATA__error_code__WIDTH 2
-#define R_USB_EPT_DATA__error_code__no_error 0
-#define R_USB_EPT_DATA__error_code__stall 1
-#define R_USB_EPT_DATA__error_code__bus_error 2
-#define R_USB_EPT_DATA__error_code__buffer_error 3
-#define R_USB_EPT_DATA__t_out__BITNR 21
-#define R_USB_EPT_DATA__t_out__WIDTH 1
-#define R_USB_EPT_DATA__error_count_out__BITNR 19
-#define R_USB_EPT_DATA__error_count_out__WIDTH 2
-#define R_USB_EPT_DATA__max_len__BITNR 11
-#define R_USB_EPT_DATA__max_len__WIDTH 7
-#define R_USB_EPT_DATA__ep__BITNR 7
-#define R_USB_EPT_DATA__ep__WIDTH 4
-#define R_USB_EPT_DATA__dev__BITNR 0
-#define R_USB_EPT_DATA__dev__WIDTH 7
-
-#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA_ISO__valid__BITNR 31
-#define R_USB_EPT_DATA_ISO__valid__WIDTH 1
-#define R_USB_EPT_DATA_ISO__valid__no 0
-#define R_USB_EPT_DATA_ISO__valid__yes 1
-#define R_USB_EPT_DATA_ISO__port__BITNR 24
-#define R_USB_EPT_DATA_ISO__port__WIDTH 2
-#define R_USB_EPT_DATA_ISO__port__any 0
-#define R_USB_EPT_DATA_ISO__port__p1 1
-#define R_USB_EPT_DATA_ISO__port__p2 2
-#define R_USB_EPT_DATA_ISO__port__undef 3
-#define R_USB_EPT_DATA_ISO__error_code__BITNR 22
-#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2
-#define R_USB_EPT_DATA_ISO__error_code__no_error 0
-#define R_USB_EPT_DATA_ISO__error_code__stall 1
-#define R_USB_EPT_DATA_ISO__error_code__bus_error 2
-#define R_USB_EPT_DATA_ISO__error_code__TBD3 3
-#define R_USB_EPT_DATA_ISO__max_len__BITNR 11
-#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10
-#define R_USB_EPT_DATA_ISO__ep__BITNR 7
-#define R_USB_EPT_DATA_ISO__ep__WIDTH 4
-#define R_USB_EPT_DATA_ISO__dev__BITNR 0
-#define R_USB_EPT_DATA_ISO__dev__WIDTH 7
-
-#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA_DEV__valid__BITNR 31
-#define R_USB_EPT_DATA_DEV__valid__WIDTH 1
-#define R_USB_EPT_DATA_DEV__valid__no 0
-#define R_USB_EPT_DATA_DEV__valid__yes 1
-#define R_USB_EPT_DATA_DEV__hold__BITNR 30
-#define R_USB_EPT_DATA_DEV__hold__WIDTH 1
-#define R_USB_EPT_DATA_DEV__hold__no 0
-#define R_USB_EPT_DATA_DEV__hold__yes 1
-#define R_USB_EPT_DATA_DEV__stall__BITNR 29
-#define R_USB_EPT_DATA_DEV__stall__WIDTH 1
-#define R_USB_EPT_DATA_DEV__stall__no 0
-#define R_USB_EPT_DATA_DEV__stall__yes 1
-#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
-#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1
-#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0
-#define R_USB_EPT_DATA_DEV__iso_resp__yes 1
-#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
-#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1
-#define R_USB_EPT_DATA_DEV__ctrl__no 0
-#define R_USB_EPT_DATA_DEV__ctrl__yes 1
-#define R_USB_EPT_DATA_DEV__iso__BITNR 26
-#define R_USB_EPT_DATA_DEV__iso__WIDTH 1
-#define R_USB_EPT_DATA_DEV__iso__no 0
-#define R_USB_EPT_DATA_DEV__iso__yes 1
-#define R_USB_EPT_DATA_DEV__port__BITNR 24
-#define R_USB_EPT_DATA_DEV__port__WIDTH 2
-#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
-#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1
-#define R_USB_EPT_DATA_DEV__t__BITNR 21
-#define R_USB_EPT_DATA_DEV__t__WIDTH 1
-#define R_USB_EPT_DATA_DEV__max_len__BITNR 11
-#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10
-#define R_USB_EPT_DATA_DEV__ep__BITNR 7
-#define R_USB_EPT_DATA_DEV__ep__WIDTH 4
-#define R_USB_EPT_DATA_DEV__dev__BITNR 0
-#define R_USB_EPT_DATA_DEV__dev__WIDTH 7
-
-#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220)
-#define R_USB_SNMP_TERROR__value__BITNR 0
-#define R_USB_SNMP_TERROR__value__WIDTH 32
-
-#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224)
-#define R_USB_EPID_ATTN__value__BITNR 0
-#define R_USB_EPID_ATTN__value__WIDTH 32
-
-#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a)
-#define R_USB_PORT1_DISABLE__disable__BITNR 0
-#define R_USB_PORT1_DISABLE__disable__WIDTH 1
-#define R_USB_PORT1_DISABLE__disable__yes 0
-#define R_USB_PORT1_DISABLE__disable__no 1
-
-#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052)
-#define R_USB_PORT2_DISABLE__disable__BITNR 0
-#define R_USB_PORT2_DISABLE__disable__WIDTH 1
-#define R_USB_PORT2_DISABLE__disable__yes 0
-#define R_USB_PORT2_DISABLE__disable__no 1
-
-/*
-!* MMU registers
-!*/
-
-#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240)
-#define R_MMU_CONFIG__mmu_enable__BITNR 31
-#define R_MMU_CONFIG__mmu_enable__WIDTH 1
-#define R_MMU_CONFIG__mmu_enable__enable 1
-#define R_MMU_CONFIG__mmu_enable__disable 0
-#define R_MMU_CONFIG__inv_excp__BITNR 18
-#define R_MMU_CONFIG__inv_excp__WIDTH 1
-#define R_MMU_CONFIG__inv_excp__enable 1
-#define R_MMU_CONFIG__inv_excp__disable 0
-#define R_MMU_CONFIG__acc_excp__BITNR 17
-#define R_MMU_CONFIG__acc_excp__WIDTH 1
-#define R_MMU_CONFIG__acc_excp__enable 1
-#define R_MMU_CONFIG__acc_excp__disable 0
-#define R_MMU_CONFIG__we_excp__BITNR 16
-#define R_MMU_CONFIG__we_excp__WIDTH 1
-#define R_MMU_CONFIG__we_excp__enable 1
-#define R_MMU_CONFIG__we_excp__disable 0
-#define R_MMU_CONFIG__seg_f__BITNR 15
-#define R_MMU_CONFIG__seg_f__WIDTH 1
-#define R_MMU_CONFIG__seg_f__seg 1
-#define R_MMU_CONFIG__seg_f__page 0
-#define R_MMU_CONFIG__seg_e__BITNR 14
-#define R_MMU_CONFIG__seg_e__WIDTH 1
-#define R_MMU_CONFIG__seg_e__seg 1
-#define R_MMU_CONFIG__seg_e__page 0
-#define R_MMU_CONFIG__seg_d__BITNR 13
-#define R_MMU_CONFIG__seg_d__WIDTH 1
-#define R_MMU_CONFIG__seg_d__seg 1
-#define R_MMU_CONFIG__seg_d__page 0
-#define R_MMU_CONFIG__seg_c__BITNR 12
-#define R_MMU_CONFIG__seg_c__WIDTH 1
-#define R_MMU_CONFIG__seg_c__seg 1
-#define R_MMU_CONFIG__seg_c__page 0
-#define R_MMU_CONFIG__seg_b__BITNR 11
-#define R_MMU_CONFIG__seg_b__WIDTH 1
-#define R_MMU_CONFIG__seg_b__seg 1
-#define R_MMU_CONFIG__seg_b__page 0
-#define R_MMU_CONFIG__seg_a__BITNR 10
-#define R_MMU_CONFIG__seg_a__WIDTH 1
-#define R_MMU_CONFIG__seg_a__seg 1
-#define R_MMU_CONFIG__seg_a__page 0
-#define R_MMU_CONFIG__seg_9__BITNR 9
-#define R_MMU_CONFIG__seg_9__WIDTH 1
-#define R_MMU_CONFIG__seg_9__seg 1
-#define R_MMU_CONFIG__seg_9__page 0
-#define R_MMU_CONFIG__seg_8__BITNR 8
-#define R_MMU_CONFIG__seg_8__WIDTH 1
-#define R_MMU_CONFIG__seg_8__seg 1
-#define R_MMU_CONFIG__seg_8__page 0
-#define R_MMU_CONFIG__seg_7__BITNR 7
-#define R_MMU_CONFIG__seg_7__WIDTH 1
-#define R_MMU_CONFIG__seg_7__seg 1
-#define R_MMU_CONFIG__seg_7__page 0
-#define R_MMU_CONFIG__seg_6__BITNR 6
-#define R_MMU_CONFIG__seg_6__WIDTH 1
-#define R_MMU_CONFIG__seg_6__seg 1
-#define R_MMU_CONFIG__seg_6__page 0
-#define R_MMU_CONFIG__seg_5__BITNR 5
-#define R_MMU_CONFIG__seg_5__WIDTH 1
-#define R_MMU_CONFIG__seg_5__seg 1
-#define R_MMU_CONFIG__seg_5__page 0
-#define R_MMU_CONFIG__seg_4__BITNR 4
-#define R_MMU_CONFIG__seg_4__WIDTH 1
-#define R_MMU_CONFIG__seg_4__seg 1
-#define R_MMU_CONFIG__seg_4__page 0
-#define R_MMU_CONFIG__seg_3__BITNR 3
-#define R_MMU_CONFIG__seg_3__WIDTH 1
-#define R_MMU_CONFIG__seg_3__seg 1
-#define R_MMU_CONFIG__seg_3__page 0
-#define R_MMU_CONFIG__seg_2__BITNR 2
-#define R_MMU_CONFIG__seg_2__WIDTH 1
-#define R_MMU_CONFIG__seg_2__seg 1
-#define R_MMU_CONFIG__seg_2__page 0
-#define R_MMU_CONFIG__seg_1__BITNR 1
-#define R_MMU_CONFIG__seg_1__WIDTH 1
-#define R_MMU_CONFIG__seg_1__seg 1
-#define R_MMU_CONFIG__seg_1__page 0
-#define R_MMU_CONFIG__seg_0__BITNR 0
-#define R_MMU_CONFIG__seg_0__WIDTH 1
-#define R_MMU_CONFIG__seg_0__seg 1
-#define R_MMU_CONFIG__seg_0__page 0
-
-#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240)
-#define R_MMU_KSEG__seg_f__BITNR 15
-#define R_MMU_KSEG__seg_f__WIDTH 1
-#define R_MMU_KSEG__seg_f__seg 1
-#define R_MMU_KSEG__seg_f__page 0
-#define R_MMU_KSEG__seg_e__BITNR 14
-#define R_MMU_KSEG__seg_e__WIDTH 1
-#define R_MMU_KSEG__seg_e__seg 1
-#define R_MMU_KSEG__seg_e__page 0
-#define R_MMU_KSEG__seg_d__BITNR 13
-#define R_MMU_KSEG__seg_d__WIDTH 1
-#define R_MMU_KSEG__seg_d__seg 1
-#define R_MMU_KSEG__seg_d__page 0
-#define R_MMU_KSEG__seg_c__BITNR 12
-#define R_MMU_KSEG__seg_c__WIDTH 1
-#define R_MMU_KSEG__seg_c__seg 1
-#define R_MMU_KSEG__seg_c__page 0
-#define R_MMU_KSEG__seg_b__BITNR 11
-#define R_MMU_KSEG__seg_b__WIDTH 1
-#define R_MMU_KSEG__seg_b__seg 1
-#define R_MMU_KSEG__seg_b__page 0
-#define R_MMU_KSEG__seg_a__BITNR 10
-#define R_MMU_KSEG__seg_a__WIDTH 1
-#define R_MMU_KSEG__seg_a__seg 1
-#define R_MMU_KSEG__seg_a__page 0
-#define R_MMU_KSEG__seg_9__BITNR 9
-#define R_MMU_KSEG__seg_9__WIDTH 1
-#define R_MMU_KSEG__seg_9__seg 1
-#define R_MMU_KSEG__seg_9__page 0
-#define R_MMU_KSEG__seg_8__BITNR 8
-#define R_MMU_KSEG__seg_8__WIDTH 1
-#define R_MMU_KSEG__seg_8__seg 1
-#define R_MMU_KSEG__seg_8__page 0
-#define R_MMU_KSEG__seg_7__BITNR 7
-#define R_MMU_KSEG__seg_7__WIDTH 1
-#define R_MMU_KSEG__seg_7__seg 1
-#define R_MMU_KSEG__seg_7__page 0
-#define R_MMU_KSEG__seg_6__BITNR 6
-#define R_MMU_KSEG__seg_6__WIDTH 1
-#define R_MMU_KSEG__seg_6__seg 1
-#define R_MMU_KSEG__seg_6__page 0
-#define R_MMU_KSEG__seg_5__BITNR 5
-#define R_MMU_KSEG__seg_5__WIDTH 1
-#define R_MMU_KSEG__seg_5__seg 1
-#define R_MMU_KSEG__seg_5__page 0
-#define R_MMU_KSEG__seg_4__BITNR 4
-#define R_MMU_KSEG__seg_4__WIDTH 1
-#define R_MMU_KSEG__seg_4__seg 1
-#define R_MMU_KSEG__seg_4__page 0
-#define R_MMU_KSEG__seg_3__BITNR 3
-#define R_MMU_KSEG__seg_3__WIDTH 1
-#define R_MMU_KSEG__seg_3__seg 1
-#define R_MMU_KSEG__seg_3__page 0
-#define R_MMU_KSEG__seg_2__BITNR 2
-#define R_MMU_KSEG__seg_2__WIDTH 1
-#define R_MMU_KSEG__seg_2__seg 1
-#define R_MMU_KSEG__seg_2__page 0
-#define R_MMU_KSEG__seg_1__BITNR 1
-#define R_MMU_KSEG__seg_1__WIDTH 1
-#define R_MMU_KSEG__seg_1__seg 1
-#define R_MMU_KSEG__seg_1__page 0
-#define R_MMU_KSEG__seg_0__BITNR 0
-#define R_MMU_KSEG__seg_0__WIDTH 1
-#define R_MMU_KSEG__seg_0__seg 1
-#define R_MMU_KSEG__seg_0__page 0
-
-#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242)
-#define R_MMU_CTRL__inv_excp__BITNR 2
-#define R_MMU_CTRL__inv_excp__WIDTH 1
-#define R_MMU_CTRL__inv_excp__enable 1
-#define R_MMU_CTRL__inv_excp__disable 0
-#define R_MMU_CTRL__acc_excp__BITNR 1
-#define R_MMU_CTRL__acc_excp__WIDTH 1
-#define R_MMU_CTRL__acc_excp__enable 1
-#define R_MMU_CTRL__acc_excp__disable 0
-#define R_MMU_CTRL__we_excp__BITNR 0
-#define R_MMU_CTRL__we_excp__WIDTH 1
-#define R_MMU_CTRL__we_excp__enable 1
-#define R_MMU_CTRL__we_excp__disable 0
-
-#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243)
-#define R_MMU_ENABLE__mmu_enable__BITNR 7
-#define R_MMU_ENABLE__mmu_enable__WIDTH 1
-#define R_MMU_ENABLE__mmu_enable__enable 1
-#define R_MMU_ENABLE__mmu_enable__disable 0
-
-#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244)
-#define R_MMU_KBASE_LO__base_7__BITNR 28
-#define R_MMU_KBASE_LO__base_7__WIDTH 4
-#define R_MMU_KBASE_LO__base_6__BITNR 24
-#define R_MMU_KBASE_LO__base_6__WIDTH 4
-#define R_MMU_KBASE_LO__base_5__BITNR 20
-#define R_MMU_KBASE_LO__base_5__WIDTH 4
-#define R_MMU_KBASE_LO__base_4__BITNR 16
-#define R_MMU_KBASE_LO__base_4__WIDTH 4
-#define R_MMU_KBASE_LO__base_3__BITNR 12
-#define R_MMU_KBASE_LO__base_3__WIDTH 4
-#define R_MMU_KBASE_LO__base_2__BITNR 8
-#define R_MMU_KBASE_LO__base_2__WIDTH 4
-#define R_MMU_KBASE_LO__base_1__BITNR 4
-#define R_MMU_KBASE_LO__base_1__WIDTH 4
-#define R_MMU_KBASE_LO__base_0__BITNR 0
-#define R_MMU_KBASE_LO__base_0__WIDTH 4
-
-#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248)
-#define R_MMU_KBASE_HI__base_f__BITNR 28
-#define R_MMU_KBASE_HI__base_f__WIDTH 4
-#define R_MMU_KBASE_HI__base_e__BITNR 24
-#define R_MMU_KBASE_HI__base_e__WIDTH 4
-#define R_MMU_KBASE_HI__base_d__BITNR 20
-#define R_MMU_KBASE_HI__base_d__WIDTH 4
-#define R_MMU_KBASE_HI__base_c__BITNR 16
-#define R_MMU_KBASE_HI__base_c__WIDTH 4
-#define R_MMU_KBASE_HI__base_b__BITNR 12
-#define R_MMU_KBASE_HI__base_b__WIDTH 4
-#define R_MMU_KBASE_HI__base_a__BITNR 8
-#define R_MMU_KBASE_HI__base_a__WIDTH 4
-#define R_MMU_KBASE_HI__base_9__BITNR 4
-#define R_MMU_KBASE_HI__base_9__WIDTH 4
-#define R_MMU_KBASE_HI__base_8__BITNR 0
-#define R_MMU_KBASE_HI__base_8__WIDTH 4
-
-#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c)
-#define R_MMU_CONTEXT__page_id__BITNR 0
-#define R_MMU_CONTEXT__page_id__WIDTH 6
-
-#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250)
-#define R_MMU_CAUSE__vpn__BITNR 13
-#define R_MMU_CAUSE__vpn__WIDTH 19
-#define R_MMU_CAUSE__miss_excp__BITNR 12
-#define R_MMU_CAUSE__miss_excp__WIDTH 1
-#define R_MMU_CAUSE__miss_excp__yes 1
-#define R_MMU_CAUSE__miss_excp__no 0
-#define R_MMU_CAUSE__inv_excp__BITNR 11
-#define R_MMU_CAUSE__inv_excp__WIDTH 1
-#define R_MMU_CAUSE__inv_excp__yes 1
-#define R_MMU_CAUSE__inv_excp__no 0
-#define R_MMU_CAUSE__acc_excp__BITNR 10
-#define R_MMU_CAUSE__acc_excp__WIDTH 1
-#define R_MMU_CAUSE__acc_excp__yes 1
-#define R_MMU_CAUSE__acc_excp__no 0
-#define R_MMU_CAUSE__we_excp__BITNR 9
-#define R_MMU_CAUSE__we_excp__WIDTH 1
-#define R_MMU_CAUSE__we_excp__yes 1
-#define R_MMU_CAUSE__we_excp__no 0
-#define R_MMU_CAUSE__wr_rd__BITNR 8
-#define R_MMU_CAUSE__wr_rd__WIDTH 1
-#define R_MMU_CAUSE__wr_rd__write 1
-#define R_MMU_CAUSE__wr_rd__read 0
-#define R_MMU_CAUSE__page_id__BITNR 0
-#define R_MMU_CAUSE__page_id__WIDTH 6
-
-#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254)
-#define R_TLB_SELECT__index__BITNR 0
-#define R_TLB_SELECT__index__WIDTH 6
-
-#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258)
-#define R_TLB_LO__pfn__BITNR 13
-#define R_TLB_LO__pfn__WIDTH 19
-#define R_TLB_LO__global__BITNR 3
-#define R_TLB_LO__global__WIDTH 1
-#define R_TLB_LO__global__yes 1
-#define R_TLB_LO__global__no 0
-#define R_TLB_LO__valid__BITNR 2
-#define R_TLB_LO__valid__WIDTH 1
-#define R_TLB_LO__valid__yes 1
-#define R_TLB_LO__valid__no 0
-#define R_TLB_LO__kernel__BITNR 1
-#define R_TLB_LO__kernel__WIDTH 1
-#define R_TLB_LO__kernel__yes 1
-#define R_TLB_LO__kernel__no 0
-#define R_TLB_LO__we__BITNR 0
-#define R_TLB_LO__we__WIDTH 1
-#define R_TLB_LO__we__yes 1
-#define R_TLB_LO__we__no 0
-
-#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c)
-#define R_TLB_HI__vpn__BITNR 13
-#define R_TLB_HI__vpn__WIDTH 19
-#define R_TLB_HI__page_id__BITNR 0
-#define R_TLB_HI__page_id__WIDTH 6
-
-/*
-!* Syncrounous serial port registers
-!*/
-
-#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c)
-#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32
-
-#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c)
-#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16
-
-#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c)
-#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8
-
-#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068)
-#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
-#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__rec_status__running 0
-#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
-#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0
-#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
-#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0
-#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1
-#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
-#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__pin_1__low 0
-#define R_SYNC_SERIAL1_STATUS__pin_1__high 1
-#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
-#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__pin_0__low 0
-#define R_SYNC_SERIAL1_STATUS__pin_0__high 1
-#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
-#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__underflow__no 0
-#define R_SYNC_SERIAL1_STATUS__underflow__yes 1
-#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
-#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__overrun__no 0
-#define R_SYNC_SERIAL1_STATUS__overrun__yes 1
-#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
-#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__data_avail__no 0
-#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1
-#define R_SYNC_SERIAL1_STATUS__data__BITNR 0
-#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8
-
-#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c)
-#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32
-
-#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c)
-#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16
-
-#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c)
-#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8
-
-#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
-#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
-#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14
-#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15
-#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
-#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1
-#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0
-#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
-#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3
-#define R_SYNC_SERIAL1_CTRL__mode__master_output 0
-#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1
-#define R_SYNC_SERIAL1_CTRL__mode__master_input 2
-#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3
-#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4
-#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5
-#define R_SYNC_SERIAL1_CTRL__error__BITNR 23
-#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__error__normal 0
-#define R_SYNC_SERIAL1_CTRL__error__ignore 1
-#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
-#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0
-#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1
-#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
-#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0
-#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3
-#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
-#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__f_sync__on 0
-#define R_SYNC_SERIAL1_CTRL__f_sync__off 1
-#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
-#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0
-#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1
-#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
-#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0
-#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1
-#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
-#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0
-#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1
-#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
-#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0
-#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1
-#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
-#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3
-#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0
-#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1
-#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2
-#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3
-#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4
-#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
-#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0
-#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1
-#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
-#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0
-#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1
-#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
-#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0
-#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1
-#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
-#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
-#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
-#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__high 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__low 0
-
-#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c)
-#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32
-
-#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c)
-#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16
-
-#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c)
-#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8
-
-#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078)
-#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
-#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__rec_status__running 0
-#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
-#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0
-#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
-#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0
-#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1
-#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
-#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__pin_1__low 0
-#define R_SYNC_SERIAL3_STATUS__pin_1__high 1
-#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
-#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__pin_0__low 0
-#define R_SYNC_SERIAL3_STATUS__pin_0__high 1
-#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
-#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__underflow__no 0
-#define R_SYNC_SERIAL3_STATUS__underflow__yes 1
-#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
-#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__overrun__no 0
-#define R_SYNC_SERIAL3_STATUS__overrun__yes 1
-#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
-#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__data_avail__no 0
-#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1
-#define R_SYNC_SERIAL3_STATUS__data__BITNR 0
-#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8
-
-#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c)
-#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32
-
-#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c)
-#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16
-
-#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c)
-#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8
-
-#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
-#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
-#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14
-#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15
-#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
-#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1
-#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0
-#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
-#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3
-#define R_SYNC_SERIAL3_CTRL__mode__master_output 0
-#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1
-#define R_SYNC_SERIAL3_CTRL__mode__master_input 2
-#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3
-#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4
-#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5
-#define R_SYNC_SERIAL3_CTRL__error__BITNR 23
-#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__error__normal 0
-#define R_SYNC_SERIAL3_CTRL__error__ignore 1
-#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
-#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0
-#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1
-#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
-#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0
-#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3
-#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
-#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__f_sync__on 0
-#define R_SYNC_SERIAL3_CTRL__f_sync__off 1
-#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
-#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0
-#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1
-#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
-#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0
-#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1
-#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
-#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0
-#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1
-#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
-#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0
-#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1
-#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
-#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3
-#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0
-#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1
-#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2
-#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3
-#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4
-#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
-#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0
-#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1
-#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
-#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0
-#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1
-#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
-#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0
-#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1
-#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
-#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
-#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
-#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__high 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__low 0
-
diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h
deleted file mode 100644
index 2644bcbe4490..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*!**************************************************************************
-*!
-*! MACROS:
-*! IO_MASK(reg,field)
-*! IO_STATE(reg,field,state)
-*! IO_EXTRACT(reg,field,val)
-*! IO_STATE_VALUE(reg,field,state)
-*! IO_BITNR(reg,field)
-*! IO_WIDTH(reg,field)
-*! IO_FIELD(reg,field,val)
-*! IO_RD(reg)
-*! All moderegister addresses and fields of these.
-*!
-*!**************************************************************************/
-
-#ifndef __sv_addr_ag_h__
-#define __sv_addr_ag_h__
-
-
-#define __test_sv_addr__ 0
-
-/*------------------------------------------------------------
-!* General macros to manipulate moderegisters.
-!*-----------------------------------------------------------*/
-
-/* IO_MASK returns a mask for a specified bitfield in a register.
- Note that this macro doesn't work when field width is 32 bits. */
-#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
-#define IO_MASK_(reg_, field_) \
- ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR )
-
-/* IO_STATE returns a constant corresponding to a one of the symbolic
- states that the bitfield can have. (Shifted to correct position) */
-#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
-#define IO_STATE_(reg_, field_, _state) \
- ( reg_##_##field_##_state << reg_##_##field_##_BITNR )
-
-/* IO_EXTRACT returns the masked and shifted value corresponding to the
- bitfield can have. */
-#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
-#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \
- - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR )
-
-/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic
- states that the bitfield can have. (Not shifted) */
-#define IO_STATE_VALUE(reg, field, state) \
- IO_STATE_VALUE_ (reg##_, field##_, _##state)
-#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state )
-
-/* IO_FIELD shifts the val parameter to be aligned with the bitfield
- specified. */
-#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
-#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR)
-
-/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is
- LSB and the returned bitnumber is LSB of the field. */
-#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_)
-#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR)
-
-/* IO_WIDTH returns the width, in bits, of a bitfield. */
-#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
-#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH)
-
-/*--- Obsolete. Kept for backward compatibility. ---*/
-/* Reads (or writes) a byte/uword/udword from the specified mode
- register. */
-#define IO_RD(reg) (*(volatile u32*)(reg))
-#define IO_RD_B(reg) (*(volatile u8*)(reg))
-#define IO_RD_W(reg) (*(volatile u16*)(reg))
-#define IO_RD_D(reg) (*(volatile u32*)(reg))
-
-/*------------------------------------------------------------
-!* Start addresses of the different memory areas.
-!*-----------------------------------------------------------*/
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-/*------------------------------------------------------------
-!* Type casts used in mode register macros, making pointer
-!* dereferencing possible. Empty in assembler.
-!*-----------------------------------------------------------*/
-
-#ifndef __ASSEMBLER__
-# define IO_TYPECAST_UDWORD (volatile u32*)
-# define IO_TYPECAST_RO_UDWORD (const volatile u32*)
-# define IO_TYPECAST_UWORD (volatile u16*)
-# define IO_TYPECAST_RO_UWORD (const volatile u16*)
-# define IO_TYPECAST_BYTE (volatile u8*)
-# define IO_TYPECAST_RO_BYTE (const volatile u8*)
-#else
-# define IO_TYPECAST_UDWORD
-# define IO_TYPECAST_RO_UDWORD
-# define IO_TYPECAST_UWORD
-# define IO_TYPECAST_RO_UWORD
-# define IO_TYPECAST_BYTE
-# define IO_TYPECAST_RO_BYTE
-#endif
-
-/*------------------------------------------------------------*/
-
-#include <arch/sv_addr.agh>
-
-#if __test_sv_addr__
-/* IO_MASK( R_BUS_CONFIG , CE ) */
-IO_MASK( R_WAITSTATES , SRAM_WS )
-IO_MASK( R_TEST , W32 )
-
-IO_STATE( R_BUS_CONFIG, CE, DISABLE )
-IO_STATE( R_BUS_CONFIG, CE, ENABLE )
-
-IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
-
-IO_MASK( R_DRAM_TIMING, REF )
-
-IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT )
-
-IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S )
- == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
-#endif
-
-
-#endif /* ifndef __sv_addr_ag_h__ */
-
diff --git a/arch/cris/include/uapi/arch-v10/arch/svinto.h b/arch/cris/include/uapi/arch-v10/arch/svinto.h
deleted file mode 100644
index 793a4275d26a..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/svinto.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_CRIS_SVINTO_H
-#define _ASM_CRIS_SVINTO_H
-
-#include <arch/sv_addr_ag.h>
-
-extern unsigned int genconfig_shadow; /* defined and set in head.S */
-
-/* dma stuff */
-
-enum { /* Available in: */
- d_eol = (1 << 0), /* flags */
- d_eop = (1 << 1), /* flags & status */
- d_wait = (1 << 2), /* flags */
- d_int = (1 << 3), /* flags */
- d_txerr = (1 << 4), /* flags */
- d_stop = (1 << 4), /* status */
- d_ecp = (1 << 4), /* flags & status */
- d_pri = (1 << 5), /* flags & status */
- d_alignerr = (1 << 6), /* status */
- d_crcerr = (1 << 7) /* status */
-};
-
-/* Do remember that DMA does not go through the MMU and needs
- * a real physical address, not an address virtually mapped or
- * paged. Therefore the buf/next ptrs below are unsigned long instead
- * of void * to give a warning if you try to put a pointer directly
- * to them instead of going through virt_to_phys/phys_to_virt.
- */
-
-typedef struct etrax_dma_descr {
- unsigned short sw_len; /* 0-1 */
- unsigned short ctrl; /* 2-3 */
- unsigned long next; /* 4-7 */
- unsigned long buf; /* 8-11 */
- unsigned short hw_len; /* 12-13 */
- unsigned char status; /* 14 */
- unsigned char fifo_len; /* 15 */
-} etrax_dma_descr;
-
-
-/* Use this for constant numbers only */
-#define RESET_DMA_NUM( n ) \
- *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset )
-
-/* Use this for constant numbers or symbols,
- * having two macros makes it possible to use constant expressions.
- */
-#define RESET_DMA( n ) RESET_DMA_NUM( n )
-
-
-/* Use this for constant numbers only */
-#define WAIT_DMA_NUM( n ) \
- while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \
- IO_STATE( R_DMA_CH0_CMD, cmd, hold ) )
-
-/* Use this for constant numbers or symbols
- * having two macros makes it possible to use constant expressions.
- */
-#define WAIT_DMA( n ) WAIT_DMA_NUM( n )
-
-extern void prepare_rx_descriptor(struct etrax_dma_descr *desc);
-extern void flush_etrax_cache(void);
-
-#endif
diff --git a/arch/cris/include/uapi/arch-v10/arch/user.h b/arch/cris/include/uapi/arch-v10/arch/user.h
deleted file mode 100644
index 5b9288527b98..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/user.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASM_CRIS_ARCH_USER_H
-#define __ASM_CRIS_ARCH_USER_H
-
-/* User mode registers, used for core dumps. In order to keep ELF_NGREG
- sensible we let all registers be 32 bits. The csr registers are included
- for future use. */
-struct user_regs_struct {
- unsigned long r0; /* General registers. */
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- unsigned long r13;
- unsigned long sp; /* Stack pointer. */
- unsigned long pc; /* Program counter. */
- unsigned long p0; /* Constant zero (only 8 bits). */
- unsigned long vr; /* Version register (only 8 bits). */
- unsigned long p2; /* Reserved. */
- unsigned long p3; /* Reserved. */
- unsigned long p4; /* Constant zero (only 16 bits). */
- unsigned long ccr; /* Condition code register (only 16 bits). */
- unsigned long p6; /* Reserved. */
- unsigned long mof; /* Multiply overflow register. */
- unsigned long p8; /* Constant zero. */
- unsigned long ibr; /* Not accessible. */
- unsigned long irp; /* Not accessible. */
- unsigned long srp; /* Subroutine return pointer. */
- unsigned long bar; /* Not accessible. */
- unsigned long dccr; /* Dword condition code register. */
- unsigned long brp; /* Not accessible. */
- unsigned long usp; /* User-mode stack pointer. Same as sp when
- in user mode. */
- unsigned long csrinstr; /* Internal status registers. */
- unsigned long csraddr;
- unsigned long csrdata;
-};
-
-#endif
diff --git a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h b/arch/cris/include/uapi/arch-v32/arch/cryptocop.h
deleted file mode 100644
index 1072d5bf7d4f..000000000000
--- a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * The device /dev/cryptocop is accessible using this driver using
- * CRYPTOCOP_MAJOR (254) and minor number 0.
- */
-
-#ifndef _UAPICRYPTOCOP_H
-#define _UAPICRYPTOCOP_H
-
-#include <linux/uio.h>
-
-
-#define CRYPTOCOP_SESSION_ID_NONE (0)
-
-typedef unsigned long long int cryptocop_session_id;
-
-/* cryptocop ioctls */
-#define ETRAXCRYPTOCOP_IOCTYPE (250)
-
-#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op)
-#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op)
-#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op)
-#define CRYPTOCOP_IO_MAXNR (3)
-
-typedef enum {
- cryptocop_cipher_des = 0,
- cryptocop_cipher_3des = 1,
- cryptocop_cipher_aes = 2,
- cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */
- cryptocop_cipher_none
-} cryptocop_cipher_type;
-
-typedef enum {
- cryptocop_digest_sha1 = 0,
- cryptocop_digest_md5 = 1,
- cryptocop_digest_none
-} cryptocop_digest_type;
-
-typedef enum {
- cryptocop_csum_le = 0,
- cryptocop_csum_be = 1,
- cryptocop_csum_none
-} cryptocop_csum_type;
-
-typedef enum {
- cryptocop_cipher_mode_ecb = 0,
- cryptocop_cipher_mode_cbc,
- cryptocop_cipher_mode_none
-} cryptocop_cipher_mode;
-
-typedef enum {
- cryptocop_3des_eee = 0,
- cryptocop_3des_eed = 1,
- cryptocop_3des_ede = 2,
- cryptocop_3des_edd = 3,
- cryptocop_3des_dee = 4,
- cryptocop_3des_ded = 5,
- cryptocop_3des_dde = 6,
- cryptocop_3des_ddd = 7
-} cryptocop_3des_mode;
-
-/* Usermode accessible (ioctl) operations. */
-struct strcop_session_op{
- cryptocop_session_id ses_id;
-
- cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */
-
- cryptocop_cipher_mode cmode; /* ECB, CBC, none */
- cryptocop_3des_mode des3_mode;
-
- cryptocop_digest_type digest; /* MD5, SHA1, none */
-
- cryptocop_csum_type csum; /* BE, LE, none */
-
- unsigned char *key;
- size_t keylen;
-};
-
-#define CRYPTOCOP_CSUM_LENGTH (2)
-#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */
-#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */
-#define CRYPTOCOP_MAX_KEY_LENGTH (32)
-
-struct strcop_crypto_op{
- cryptocop_session_id ses_id;
-
- /* Indata. */
- unsigned char *indata;
- size_t inlen; /* Total indata length. */
-
- /* Cipher configuration. */
- unsigned char do_cipher:1;
- unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */
- unsigned char cipher_explicit:1;
- size_t cipher_start;
- size_t cipher_len;
- /* cipher_iv is used if do_cipher and cipher_explicit and the cipher
- mode is CBC. The length is controlled by the type of cipher,
- e.g. DES/3DES 8 octets and AES 16 octets. */
- unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH];
- /* Outdata. */
- unsigned char *cipher_outdata;
- size_t cipher_outlen;
-
- /* digest configuration. */
- unsigned char do_digest:1;
- size_t digest_start;
- size_t digest_len;
- /* Outdata. The actual length is determined by the type of the digest. */
- unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH];
-
- /* Checksum configuration. */
- unsigned char do_csum:1;
- size_t csum_start;
- size_t csum_len;
- /* Outdata. */
- unsigned char csum[CRYPTOCOP_CSUM_LENGTH];
-};
-
-
-
-
-#endif /* _UAPICRYPTOCOP_H */
diff --git a/arch/cris/include/uapi/arch-v32/arch/user.h b/arch/cris/include/uapi/arch-v32/arch/user.h
deleted file mode 100644
index 3576b540ba78..000000000000
--- a/arch/cris/include/uapi/arch-v32/arch/user.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_CRIS_ARCH_USER_H
-#define _ASM_CRIS_ARCH_USER_H
-
-/* User-mode register used for core dumps. */
-
-struct user_regs_struct {
- unsigned long r0; /* General registers. */
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- unsigned long r13;
- unsigned long sp; /* R14, Stack pointer. */
- unsigned long acr; /* R15, Address calculation register. */
- unsigned long bz; /* P0, Constant zero (8-bits). */
- unsigned long vr; /* P1, Version register (8-bits). */
- unsigned long pid; /* P2, Process ID (8-bits). */
- unsigned long srs; /* P3, Support register select (8-bits). */
- unsigned long wz; /* P4, Constant zero (16-bits). */
- unsigned long exs; /* P5, Exception status. */
- unsigned long eda; /* P6, Exception data address. */
- unsigned long mof; /* P7, Multiply overflow regiter. */
- unsigned long dz; /* P8, Constant zero (32-bits). */
- unsigned long ebp; /* P9, Exception base pointer. */
- unsigned long erp; /* P10, Exception return pointer. */
- unsigned long srp; /* P11, Subroutine return pointer. */
- unsigned long nrp; /* P12, NMI return pointer. */
- unsigned long ccs; /* P13, Condition code stack. */
- unsigned long usp; /* P14, User mode stack pointer. */
- unsigned long spc; /* P15, Single step PC. */
-};
-
-#endif /* _ASM_CRIS_ARCH_USER_H */
diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild
deleted file mode 100644
index 3470c6e9c7b9..000000000000
--- a/arch/cris/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,22 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += auxvec.h
-generic-y += bitsperlong.h
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += fcntl.h
-generic-y += ioctl.h
-generic-y += ipcbuf.h
-generic-y += kvm_para.h
-generic-y += mman.h
-generic-y += msgbuf.h
-generic-y += poll.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += shmbuf.h
-generic-y += siginfo.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += types.h
diff --git a/arch/cris/include/uapi/asm/byteorder.h b/arch/cris/include/uapi/asm/byteorder.h
deleted file mode 100644
index 6e19891e06ee..000000000000
--- a/arch/cris/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_BYTEORDER_H
-#define _CRIS_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif
-
-
diff --git a/arch/cris/include/uapi/asm/elf.h b/arch/cris/include/uapi/asm/elf.h
deleted file mode 100644
index ea4cbdafe885..000000000000
--- a/arch/cris/include/uapi/asm/elf.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASMCRIS_ELF_H
-#define __ASMCRIS_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#ifdef __arch_v32
-#include <asm/elf_v32.h>
-#else
-#include <asm/elf_v10.h>
-#endif
-
-#define R_CRIS_NONE 0
-#define R_CRIS_8 1
-#define R_CRIS_16 2
-#define R_CRIS_32 3
-#define R_CRIS_8_PCREL 4
-#define R_CRIS_16_PCREL 5
-#define R_CRIS_32_PCREL 6
-#define R_CRIS_GNU_VTINHERIT 7
-#define R_CRIS_GNU_VTENTRY 8
-#define R_CRIS_COPY 9
-#define R_CRIS_GLOB_DAT 10
-#define R_CRIS_JUMP_SLOT 11
-#define R_CRIS_RELATIVE 12
-#define R_CRIS_16_GOT 13
-#define R_CRIS_32_GOT 14
-#define R_CRIS_16_GOTPLT 15
-#define R_CRIS_32_GOTPLT 16
-#define R_CRIS_32_GOTREL 17
-#define R_CRIS_32_PLT_GOTREL 18
-#define R_CRIS_32_PLT_PCREL 19
-
-typedef unsigned long elf_greg_t;
-
-/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
- thus exposed to user-space. */
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* A placeholder; CRIS does not have any fp regs. */
-typedef unsigned long elf_fpregset_t;
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_CRIS
-
-/* The master for these definitions is {binutils}/include/elf/cris.h: */
-/* User symbols in this file have a leading underscore. */
-#define EF_CRIS_UNDERSCORE 0x00000001
-
-/* This is a mask for different incompatible machine variants. */
-#define EF_CRIS_VARIANT_MASK 0x0000000e
-
-/* Variant 0; may contain v0..10 object. */
-#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000
-
-/* Variant 1; contains v32 object. */
-#define EF_CRIS_VARIANT_V32 0x00000002
-
-/* Variant 2; contains object compatible with v32 and v10. */
-#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004
-/* End of excerpt from {binutils}/include/elf/cris.h. */
-
-#define ELF_EXEC_PAGESIZE 8192
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this CPU supports. This could be done in user space,
- but it's not easy, and we've already done it here. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo.
-*/
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/cris/include/uapi/asm/elf_v10.h b/arch/cris/include/uapi/asm/elf_v10.h
deleted file mode 100644
index b1515f2684da..000000000000
--- a/arch/cris/include/uapi/asm/elf_v10.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASMCRIS_ARCH_ELF_H
-#define __ASMCRIS_ARCH_ELF_H
-
-#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
-
-/* Matches struct user_regs_struct */
-#define ELF_NGREG 35
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- ((x)->e_machine == EM_CRIS \
- && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \
- || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-
-/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program
- starts (a register; assume first param register for CRIS)
- contains a pointer to a function which might be
- registered using `atexit'. This provides a mean for the
- dynamic linker to call DT_FINI functions for shared libraries
- that have been loaded before the code runs.
-
- A value of 0 tells we have no such handler. */
-
-/* Explicitly set registers to 0 to increase determinism. */
-#define ELF_PLAT_INIT(_r, load_addr) do { \
- (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
- (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
- (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
- (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
-} while (0)
-
-/* The additional layer below is because the stack pointer is missing in
- the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t,
- and should be filled in according to the layout of the user_regs_struct
- struct; regs is a pt_regs struct. We dump all registers, though several are
- obviously unnecessary. That way there's less need for intelligence at
- the receiving end (i.e. gdb). */
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- pr_reg[0] = regs->r0; \
- pr_reg[1] = regs->r1; \
- pr_reg[2] = regs->r2; \
- pr_reg[3] = regs->r3; \
- pr_reg[4] = regs->r4; \
- pr_reg[5] = regs->r5; \
- pr_reg[6] = regs->r6; \
- pr_reg[7] = regs->r7; \
- pr_reg[8] = regs->r8; \
- pr_reg[9] = regs->r9; \
- pr_reg[10] = regs->r10; \
- pr_reg[11] = regs->r11; \
- pr_reg[12] = regs->r12; \
- pr_reg[13] = regs->r13; \
- pr_reg[14] = rdusp(); /* sp */ \
- pr_reg[15] = regs->irp; /* pc */ \
- pr_reg[16] = 0; /* p0 */ \
- pr_reg[17] = rdvr(); /* vr */ \
- pr_reg[18] = 0; /* p2 */ \
- pr_reg[19] = 0; /* p3 */ \
- pr_reg[20] = 0; /* p4 */ \
- pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \
- pr_reg[22] = 0; /* p6 */ \
- pr_reg[23] = regs->mof; /* mof */ \
- pr_reg[24] = 0; /* p8 */ \
- pr_reg[25] = 0; /* ibr */ \
- pr_reg[26] = 0; /* irp */ \
- pr_reg[27] = regs->srp; /* srp */ \
- pr_reg[28] = 0; /* bar */ \
- pr_reg[29] = regs->dccr; /* dccr */ \
- pr_reg[30] = 0; /* brp */ \
- pr_reg[31] = rdusp(); /* usp */ \
- pr_reg[32] = 0; /* csrinstr */ \
- pr_reg[33] = 0; /* csraddr */ \
- pr_reg[34] = 0; /* csrdata */
-
-
-#endif
diff --git a/arch/cris/include/uapi/asm/elf_v32.h b/arch/cris/include/uapi/asm/elf_v32.h
deleted file mode 100644
index cc00ffdb7f9c..000000000000
--- a/arch/cris/include/uapi/asm/elf_v32.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_CRIS_ELF_H
-#define _ASM_CRIS_ELF_H
-
-#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
-
-/* Matches struct user_regs_struct */
-#define ELF_NGREG 32
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- ((x)->e_machine == EM_CRIS \
- && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \
- || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
-
-/* CRISv32 ELF register definitions. */
-
-#include <asm/ptrace.h>
-
-/* Explicitly zero out registers to increase determinism. */
-#define ELF_PLAT_INIT(_r, load_addr) do { \
- (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
- (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
- (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
- (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
- (_r)->acr = 0; \
-} while (0)
-
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically.
- */
-#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack))
-
-/*
- * This is basically a pt_regs with the additional definition
- * of the stack pointer since it's needed in a core dump.
- * pr_regs is a elf_gregset_t and should be filled according
- * to the layout of user_regs_struct.
- */
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- pr_reg[0] = regs->r0; \
- pr_reg[1] = regs->r1; \
- pr_reg[2] = regs->r2; \
- pr_reg[3] = regs->r3; \
- pr_reg[4] = regs->r4; \
- pr_reg[5] = regs->r5; \
- pr_reg[6] = regs->r6; \
- pr_reg[7] = regs->r7; \
- pr_reg[8] = regs->r8; \
- pr_reg[9] = regs->r9; \
- pr_reg[10] = regs->r10; \
- pr_reg[11] = regs->r11; \
- pr_reg[12] = regs->r12; \
- pr_reg[13] = regs->r13; \
- pr_reg[14] = rdusp(); /* SP */ \
- pr_reg[15] = regs->acr; /* ACR */ \
- pr_reg[16] = 0; /* BZ */ \
- pr_reg[17] = rdvr(); /* VR */ \
- pr_reg[18] = 0; /* PID */ \
- pr_reg[19] = regs->srs; /* SRS */ \
- pr_reg[20] = 0; /* WZ */ \
- pr_reg[21] = regs->exs; /* EXS */ \
- pr_reg[22] = regs->eda; /* EDA */ \
- pr_reg[23] = regs->mof; /* MOF */ \
- pr_reg[24] = 0; /* DZ */ \
- pr_reg[25] = 0; /* EBP */ \
- pr_reg[26] = regs->erp; /* ERP */ \
- pr_reg[27] = regs->srp; /* SRP */ \
- pr_reg[28] = 0; /* NRP */ \
- pr_reg[29] = regs->ccs; /* CCS */ \
- pr_reg[30] = rdusp(); /* USP */ \
- pr_reg[31] = regs->spc; /* SPC */ \
-
-#endif /* _ASM_CRIS_ELF_H */
diff --git a/arch/cris/include/uapi/asm/ethernet.h b/arch/cris/include/uapi/asm/ethernet.h
deleted file mode 100644
index e0c1a6322824..000000000000
--- a/arch/cris/include/uapi/asm/ethernet.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * ioctl defines for ethernet driver
- *
- * Copyright (c) 2001 Axis Communications AB
- *
- * Author: Mikael Starvik
- *
- */
-
-#ifndef _CRIS_ETHERNET_H
-#define _CRIS_ETHERNET_H
-#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */
-#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */
-#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */
-#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */
-#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */
-#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */
-#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */
-#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */
-#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8
-#endif /* _CRIS_ETHERNET_H */
diff --git a/arch/cris/include/uapi/asm/etraxgpio.h b/arch/cris/include/uapi/asm/etraxgpio.h
deleted file mode 100644
index 10ab0dd45bfe..000000000000
--- a/arch/cris/include/uapi/asm/etraxgpio.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * The following devices are accessible using this driver using
- * GPIO_MAJOR (120) and a couple of minor numbers.
- *
- * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
- * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
- * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
- * /dev/leds minor 2, Access to leds depending on kernelconfig
- * /dev/gpiog minor 3
- * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
- * g1-g7 and g25-g31 is both input and outputs but on different pins
- * Also note that some bits change pins depending on what interfaces
- * are enabled.
- */
-#ifndef _ASM_ETRAXGPIO_H
-#define _ASM_ETRAXGPIO_H
-
-#define GPIO_MINOR_FIRST 0
-
-#define ETRAXGPIO_IOCTYPE 43
-
-/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-#define GPIO_MINOR_A 0
-#define GPIO_MINOR_B 1
-#define GPIO_MINOR_LEDS 2
-#define GPIO_MINOR_G 3
-#define GPIO_MINOR_LAST 3
-#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
-
-
-/* supported ioctl _IOC_NR's */
-
-#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
-#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */
-#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */
-
-/* the alarm is waited for by select() */
-
-#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */
-#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */
-#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */
-
-/* LED ioctl */
-#define IO_LEDACTIVE_SET 0x7 /* set active led
- * 0=off, 1=green, 2=red, 3=yellow */
-
-/* GPIO direction ioctl's */
-#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */
-#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
- returns mask with current inputs (obsolete) */
-#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output,
- returns mask with current outputs (obsolete)*/
-
-/* LED ioctl extended */
-#define IO_LED_SETBIT 0xB
-#define IO_LED_CLRBIT 0xC
-
-/* SHUTDOWN ioctl */
-#define IO_SHUTDOWN 0xD
-#define IO_GET_PWR_BT 0xE
-
-/* Bit toggling in driver settings */
-/* bit set in low byte0 is CLK mask (0x00FF),
- bit set in byte1 is DATA mask (0xFF00)
- msb, data_mask[7:0] , clk_mask[7:0]
- */
-#define IO_CFG_WRITE_MODE 0xF
-#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
- ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
-
-/* The following 4 ioctl's take a pointer as argument and handles
- * 32 bit ports (port G) properly.
- * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
- */
-#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
-#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
-#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */
- /* *arg updated with current input pins. */
-#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
- /* *arg updated with current output pins. */
-
-#endif
diff --git a/arch/cris/include/uapi/asm/ioctls.h b/arch/cris/include/uapi/asm/ioctls.h
deleted file mode 100644
index 92d654ce3d84..000000000000
--- a/arch/cris/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ARCH_CRIS_IOCTLS_H__
-#define __ARCH_CRIS_IOCTLS_H__
-
-#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
-#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */
-#define TIOCSERWRRS485 0x5462 /* write rs-485 */
-#define TIOCSRS485 0x5463 /* enable rs-485 */
-
-#include <asm-generic/ioctls.h>
-
-#endif
diff --git a/arch/cris/include/uapi/asm/param.h b/arch/cris/include/uapi/asm/param.h
deleted file mode 100644
index ae296115c7c9..000000000000
--- a/arch/cris/include/uapi/asm/param.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASMCRIS_PARAM_H
-#define _ASMCRIS_PARAM_H
-
-/* Currently we assume that HZ=100 is good for CRIS. */
-
-#define EXEC_PAGESIZE 8192
-
-#include <asm-generic/param.h>
-
-#endif /* _ASMCRIS_PARAM_H */
diff --git a/arch/cris/include/uapi/asm/posix_types.h b/arch/cris/include/uapi/asm/posix_types.h
deleted file mode 100644
index c75d8b0acc99..000000000000
--- a/arch/cris/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */
-/* I guess we should write these in assembler because they are used often. */
-
-#ifndef __ARCH_CRIS_POSIX_TYPES_H
-#define __ARCH_CRIS_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* __ARCH_CRIS_POSIX_TYPES_H */
diff --git a/arch/cris/include/uapi/asm/ptrace.h b/arch/cris/include/uapi/asm/ptrace.h
deleted file mode 100644
index 99de59e54613..000000000000
--- a/arch/cris/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifdef __arch_v32
-#include <asm/ptrace_v32.h>
-#else
-#include <asm/ptrace_v10.h>
-#endif
diff --git a/arch/cris/include/uapi/asm/ptrace_v10.h b/arch/cris/include/uapi/asm/ptrace_v10.h
deleted file mode 100644
index 4ffffb7ab102..000000000000
--- a/arch/cris/include/uapi/asm/ptrace_v10.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_ARCH_PTRACE_H
-#define _CRIS_ARCH_PTRACE_H
-
-/* Frame types */
-
-#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */
-#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return
- path */
-
-/* Register numbers in the ptrace system call interface */
-
-#define PT_FRAMETYPE 0
-#define PT_ORIG_R10 1
-#define PT_R13 2
-#define PT_R12 3
-#define PT_R11 4
-#define PT_R10 5
-#define PT_R9 6
-#define PT_R8 7
-#define PT_R7 8
-#define PT_R6 9
-#define PT_R5 10
-#define PT_R4 11
-#define PT_R3 12
-#define PT_R2 13
-#define PT_R1 14
-#define PT_R0 15
-#define PT_MOF 16
-#define PT_DCCR 17
-#define PT_SRP 18
-#define PT_IRP 19 /* This is actually the debugged process' PC */
-#define PT_CSRINSTR 20 /* CPU Status record remnants -
- valid if frametype == busfault */
-#define PT_CSRADDR 21
-#define PT_CSRDATA 22
-#define PT_USP 23 /* special case - USP is not in the pt_regs */
-#define PT_MAX 23
-
-/* Condition code bit numbers. The same numbers apply to CCR of course,
- but we use DCCR everywhere else, so let's try and be consistent. */
-#define C_DCCR_BITNR 0
-#define V_DCCR_BITNR 1
-#define Z_DCCR_BITNR 2
-#define N_DCCR_BITNR 3
-#define X_DCCR_BITNR 4
-#define I_DCCR_BITNR 5
-#define B_DCCR_BITNR 6
-#define M_DCCR_BITNR 7
-#define U_DCCR_BITNR 8
-#define P_DCCR_BITNR 9
-#define F_DCCR_BITNR 10
-
-/* pt_regs not only specifices the format in the user-struct during
- * ptrace but is also the frame format used in the kernel prologue/epilogues
- * themselves
- */
-
-struct pt_regs {
- unsigned long frametype; /* type of stackframe */
- unsigned long orig_r10;
- /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */
- unsigned long r13;
- unsigned long r12;
- unsigned long r11;
- unsigned long r10;
- unsigned long r9;
- unsigned long r8;
- unsigned long r7;
- unsigned long r6;
- unsigned long r5;
- unsigned long r4;
- unsigned long r3;
- unsigned long r2;
- unsigned long r1;
- unsigned long r0;
- unsigned long mof;
- unsigned long dccr;
- unsigned long srp;
- unsigned long irp; /* This is actually the debugged process' PC */
- unsigned long csrinstr;
- unsigned long csraddr;
- unsigned long csrdata;
-};
-
-/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
- * when doing a context-switch. it is used (apart from in resume) when a new
- * thread is made and we need to make _resume (which is starting it for the
- * first time) realise what is going on.
- *
- * Actually, the use is very close to the thread struct (TSS) in that both the
- * switch_stack and the TSS are used to keep thread stuff when switching in
- * _resume.
- */
-
-struct switch_stack {
- unsigned long r9;
- unsigned long r8;
- unsigned long r7;
- unsigned long r6;
- unsigned long r5;
- unsigned long r4;
- unsigned long r3;
- unsigned long r2;
- unsigned long r1;
- unsigned long r0;
- unsigned long return_ip; /* ip that _resume will return to */
-};
-
-#ifdef __KERNEL__
-
-/* bit 8 is user-mode flag */
-#define user_mode(regs) (((regs)->dccr & 0x100) != 0)
-#define instruction_pointer(regs) ((regs)->irp)
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/cris/include/uapi/asm/ptrace_v32.h b/arch/cris/include/uapi/asm/ptrace_v32.h
deleted file mode 100644
index a91c4aacb14f..000000000000
--- a/arch/cris/include/uapi/asm/ptrace_v32.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_ARCH_PTRACE_H
-#define _CRIS_ARCH_PTRACE_H
-
-/* Register numbers in the ptrace system call interface */
-
-#define PT_ORIG_R10 0
-#define PT_R0 1
-#define PT_R1 2
-#define PT_R2 3
-#define PT_R3 4
-#define PT_R4 5
-#define PT_R5 6
-#define PT_R6 7
-#define PT_R7 8
-#define PT_R8 9
-#define PT_R9 10
-#define PT_R10 11
-#define PT_R11 12
-#define PT_R12 13
-#define PT_R13 14
-#define PT_ACR 15
-#define PT_SRS 16
-#define PT_MOF 17
-#define PT_SPC 18
-#define PT_CCS 19
-#define PT_SRP 20
-#define PT_ERP 21 /* This is actually the debugged process' PC */
-#define PT_EXS 22
-#define PT_EDA 23
-#define PT_USP 24 /* special case - USP is not in the pt_regs */
-#define PT_PPC 25 /* special case - pseudo PC */
-#define PT_BP 26 /* Base number for BP registers. */
-#define PT_BP_CTRL 26 /* BP control register. */
-#define PT_MAX 40
-
-/* Condition code bit numbers. */
-#define C_CCS_BITNR 0
-#define V_CCS_BITNR 1
-#define Z_CCS_BITNR 2
-#define N_CCS_BITNR 3
-#define X_CCS_BITNR 4
-#define I_CCS_BITNR 5
-#define U_CCS_BITNR 6
-#define P_CCS_BITNR 7
-#define R_CCS_BITNR 8
-#define S_CCS_BITNR 9
-#define M_CCS_BITNR 30
-#define Q_CCS_BITNR 31
-#define CCS_SHIFT 10 /* Shift count for each level in CCS */
-
-/* pt_regs not only specifices the format in the user-struct during
- * ptrace but is also the frame format used in the kernel prologue/epilogues
- * themselves
- */
-
-struct pt_regs {
- unsigned long orig_r10;
- /* pushed by movem r13, [sp] in SAVE_ALL. */
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- unsigned long r13;
- unsigned long acr;
- unsigned long srs;
- unsigned long mof;
- unsigned long spc;
- unsigned long ccs;
- unsigned long srp;
- unsigned long erp; /* This is actually the debugged process' PC */
- /* For debugging purposes; saved only when needed. */
- unsigned long exs;
- unsigned long eda;
-};
-
-/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
- * when doing a context-switch. it is used (apart from in resume) when a new
- * thread is made and we need to make _resume (which is starting it for the
- * first time) realise what is going on.
- *
- * Actually, the use is very close to the thread struct (TSS) in that both the
- * switch_stack and the TSS are used to keep thread stuff when switching in
- * _resume.
- */
-
-struct switch_stack {
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long return_ip; /* ip that _resume will return to */
-};
-
-#ifdef __KERNEL__
-
-#define arch_has_single_step() (1)
-#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0)
-#define instruction_pointer(regs) ((regs)->erp)
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/cris/include/uapi/asm/rs485.h b/arch/cris/include/uapi/asm/rs485.h
deleted file mode 100644
index 041d31fa33d5..000000000000
--- a/arch/cris/include/uapi/asm/rs485.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* RS-485 structures */
-
-/* Used with ioctl() TIOCSERSETRS485 for backward compatibility!
- * XXX: Do not use it for new code!
- */
-struct rs485_control {
- unsigned short rts_on_send;
- unsigned short rts_after_sent;
- unsigned long delay_rts_before_send;
- unsigned short enabled;
-};
-
-/* Used with ioctl() TIOCSERWRRS485 */
-struct rs485_write {
- unsigned short outc_size;
- unsigned char *outc;
-};
-
diff --git a/arch/cris/include/uapi/asm/setup.h b/arch/cris/include/uapi/asm/setup.h
deleted file mode 100644
index 4854ace9db76..000000000000
--- a/arch/cris/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_SETUP_H
-#define _CRIS_SETUP_H
-
-#define COMMAND_LINE_SIZE 256
-
-#endif
diff --git a/arch/cris/include/uapi/asm/sigcontext.h b/arch/cris/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 97565ce3f0b9..000000000000
--- a/arch/cris/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-#ifndef _ASM_CRIS_SIGCONTEXT_H
-#define _ASM_CRIS_SIGCONTEXT_H
-
-#include <asm/ptrace.h>
-
-/* This struct is saved by setup_frame in signal.c, to keep the current context while
- a signal handler is executed. It's restored by sys_sigreturn.
-
- To keep things simple, we use pt_regs here even though normally you just specify
- the list of regs to save. Then we can use copy_from_user on the entire regs instead
- of a bunch of get_user's as well...
-
-*/
-
-struct sigcontext {
- struct pt_regs regs; /* needs to be first */
- unsigned long oldmask;
- unsigned long usp; /* usp before stacking this gunk on it */
-};
-
-#endif
-
diff --git a/arch/cris/include/uapi/asm/signal.h b/arch/cris/include/uapi/asm/signal.h
deleted file mode 100644
index e4ab00f00111..000000000000
--- a/arch/cris/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_CRIS_SIGNAL_H
-#define _UAPI_ASM_CRIS_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems. */
-struct siginfo;
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-#define SIGBUS 7
-#define SIGFPE 8
-#define SIGKILL 9
-#define SIGUSR1 10
-#define SIGSEGV 11
-#define SIGUSR2 12
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGSTKFLT 16
-#define SIGCHLD 17
-#define SIGCONT 18
-#define SIGSTOP 19
-#define SIGTSTP 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGURG 23
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGIO 29
-#define SIGPOLL SIGIO
-/*
-#define SIGLOST 29
-*/
-#define SIGPWR 30
-#define SIGSYS 31
-#define SIGUNUSED 31
-
-/* These should not be considered constants from userland. */
-#define SIGRTMIN 32
-#define SIGRTMAX _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-
-#define SA_NOCLDSTOP 0x00000001u
-#define SA_NOCLDWAIT 0x00000002u
-#define SA_SIGINFO 0x00000004u
-#define SA_ONSTACK 0x08000000u
-#define SA_RESTART 0x10000000u
-#define SA_NODEFER 0x40000000u
-#define SA_RESETHAND 0x80000000u
-
-#define SA_NOMASK SA_NODEFER
-#define SA_ONESHOT SA_RESETHAND
-
-#define SA_RESTORER 0x04000000
-
-#define MINSIGSTKSZ 2048
-#define SIGSTKSZ 8192
-
-#include <asm-generic/signal-defs.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
- void *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-
-#endif /* _UAPI_ASM_CRIS_SIGNAL_H */
diff --git a/arch/cris/include/uapi/asm/stat.h b/arch/cris/include/uapi/asm/stat.h
deleted file mode 100644
index cdb74d5862e4..000000000000
--- a/arch/cris/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_STAT_H
-#define _CRIS_STAT_H
-
-/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in
- the kernel if necessary. */
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-#define STAT_HAVE_NSEC 1
-
-struct stat {
- unsigned long st_dev;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned long st_rdev;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad0[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad3[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
- unsigned long __pad4; /* future possible st_blocks high bits */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */
-
- unsigned long long st_ino;
-};
-
-#endif
diff --git a/arch/cris/include/uapi/asm/swab.h b/arch/cris/include/uapi/asm/swab.h
deleted file mode 100644
index 4adf1e9f0b09..000000000000
--- a/arch/cris/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * CRIS byte swapping.
- */
diff --git a/arch/cris/include/uapi/asm/sync_serial.h b/arch/cris/include/uapi/asm/sync_serial.h
deleted file mode 100644
index f2d468889ba9..000000000000
--- a/arch/cris/include/uapi/asm/sync_serial.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * ioctl defines for synchronous serial port driver
- *
- * Copyright (c) 2001-2003 Axis Communications AB
- *
- * Author: Mikael Starvik
- *
- */
-
-#ifndef SYNC_SERIAL_H
-#define SYNC_SERIAL_H
-
-#include <linux/ioctl.h>
-
-#define SSP_SPEED _IOR('S', 0, unsigned int)
-#define SSP_MODE _IOR('S', 1, unsigned int)
-#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int)
-#define SSP_IPOLARITY _IOR('S', 3, unsigned int)
-#define SSP_OPOLARITY _IOR('S', 4, unsigned int)
-#define SSP_SPI _IOR('S', 5, unsigned int)
-#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
-#define SSP_INPUT _IOR('S', 7, unsigned int)
-
-/* Values for SSP_SPEED */
-#define SSP150 0
-#define SSP300 1
-#define SSP600 2
-#define SSP1200 3
-#define SSP2400 4
-#define SSP4800 5
-#define SSP9600 6
-#define SSP19200 7
-#define SSP28800 8
-#define SSP57600 9
-#define SSP115200 10
-#define SSP230400 11
-#define SSP460800 12
-#define SSP921600 13
-#define SSP3125000 14
-#define CODEC 15
-#define CODEC_f32768 16
-
-#define FREQ_4MHz 0
-#define FREQ_2MHz 1
-#define FREQ_1MHz 2
-#define FREQ_512kHz 3
-#define FREQ_256kHz 4
-#define FREQ_128kHz 5
-#define FREQ_64kHz 6
-#define FREQ_32kHz 7
-/* FREQ_* with values where bit (value & 0x10) is set are */
-/* used for CODEC_f32768 */
-#define FREQ_4096kHz 16 /* CODEC_f32768 */
-
-/* Used by application to set CODEC divider, word rate and frame rate */
-#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \
- ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \
- (clk_per_sync << 16) | (sync_per_frame << 28))
-
-/* Used by driver to extract speed */
-#define GET_SPEED(x) (x & 0xff)
-#define GET_FREQ(x) ((x & 0xff00) >> 8)
-#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1)
-#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1)
-
-/* Values for SSP_MODE */
-#define MASTER_OUTPUT 0
-#define SLAVE_OUTPUT 1
-#define MASTER_INPUT 2
-#define SLAVE_INPUT 3
-#define MASTER_BIDIR 4
-#define SLAVE_BIDIR 5
-
-/* Values for SSP_FRAME_SYNC */
-#define NORMAL_SYNC 1
-#define EARLY_SYNC 2
-#define SECOND_WORD_SYNC 0x40000
-#define LATE_SYNC 0x80000
-
-#define BIT_SYNC 4
-#define WORD_SYNC 8
-#define EXTENDED_SYNC 0x10
-
-#define SYNC_OFF 0x20
-#define SYNC_ON 0x40
-#define WORD_SIZE_8 0x80
-#define WORD_SIZE_12 0x100
-#define WORD_SIZE_16 0x200
-#define WORD_SIZE_24 0x400
-#define WORD_SIZE_32 0x800
-#define BIT_ORDER_LSB 0x1000
-#define BIT_ORDER_MSB 0x2000
-#define FLOW_CONTROL_ENABLE 0x4000
-#define FLOW_CONTROL_DISABLE 0x8000
-#define CLOCK_GATED 0x10000
-#define CLOCK_NOT_GATED 0x20000
-
-/* Values for SSP_IPOLARITY and SSP_OPOLARITY */
-#define CLOCK_NORMAL 1
-#define CLOCK_INVERT 2
-#define CLOCK_INEGEDGE CLOCK_NORMAL
-#define CLOCK_IPOSEDGE CLOCK_INVERT
-#define FRAME_NORMAL 4
-#define FRAME_INVERT 8
-#define STATUS_NORMAL 0x10
-#define STATUS_INVERT 0x20
-
-/* Values for SSP_SPI */
-#define SPI_MASTER 0
-#define SPI_SLAVE 1
-
-/* Values for SSP_INBUFCHUNK */
-/* plain integer with the size of DMA chunks */
-
-/* To ensure that the timestamps are aligned with the data being read
- * the read length MUST be a multiple of the length of the DMA buffers.
- *
- * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below.
- */
-#define SSP_INPUT_CHUNK_SIZE 256
-
-/* Request struct to pass through the ioctl interface to read
- * data with timestamps.
- */
-struct ssp_request {
- char __user *buf; /* Where to put the data. */
- size_t len; /* Size of buf. MUST be a multiple of */
- /* SSP_INPUT_CHUNK_SIZE! */
- struct timespec ts; /* The time the data was sampled. */
-};
-
-#endif
diff --git a/arch/cris/include/uapi/asm/termbits.h b/arch/cris/include/uapi/asm/termbits.h
deleted file mode 100644
index 86925dc1fcae..000000000000
--- a/arch/cris/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-#ifndef __ARCH_ETRAX100_TERMBITS_H__
-#define __ARCH_ETRAX100_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-/*
- * 3 2 1
- * 10 987 654 321 098 765 432 109 876 543 210
- * | | ||| CBAUD
- * obaud
- *
- * ||CSIZE
- *
- * |CSTOP
- * |CREAD
- * |CPARENB
- *
- * |CPARODD
- * |HUPCL
- * |CLOCAL
- * |CBAUDEX
- * 10 987 654 321 098 765 432 109 876 543 210
- * | || || CIBAUD, IBSHIFT=16
- * ibaud
- * |CMSPAR
- * | CRTSCTS
- * x x xxx xxx x x xx Free bits
- */
-
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-
-/* Unsupported rates, but needed to avoid compile error. */
-#define B500000 0010005
-#define B576000 0010006
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-
-/* etrax supports these additional three baud rates */
-#define B921600 0010005
-#define B1843200 0010006
-#define B6250000 0010007
-/* ETRAX FS supports this as well */
-#define B12500000 0010010
-#define CIBAUD 002003600000 /* input baud rate (used in v32) */
-/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX
- * shifted left IBSHIFT bits.
- */
-#define IBSHIFT 16
-#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/
-#define CRTSCTS 020000000000 /* flow control */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif
diff --git a/arch/cris/include/uapi/asm/termios.h b/arch/cris/include/uapi/asm/termios.h
deleted file mode 100644
index d87800a6d854..000000000000
--- a/arch/cris/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_CRIS_TERMIOS_H
-#define _UAPI_CRIS_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-#include <asm/rs485.h>
-#include <linux/serial.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-
-#endif /* _UAPI_CRIS_TERMIOS_H */
diff --git a/arch/cris/include/uapi/asm/unistd.h b/arch/cris/include/uapi/asm/unistd.h
deleted file mode 100644
index 7aba513b082d..000000000000
--- a/arch/cris/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_CRIS_UNISTD_H_
-#define _UAPI_ASM_CRIS_UNISTD_H_
-
-/*
- * This file contains the system call numbers, and stub macros for libc.
- */
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_lchown 16
-#define __NR_break 17
-#define __NR_oldstat 18
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-#define __NR_oldfstat 28
-#define __NR_pause 29
-#define __NR_utime 30
-#define __NR_stty 31
-#define __NR_gtty 32
-#define __NR_access 33
-#define __NR_nice 34
-#define __NR_ftime 35
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-#define __NR_prof 44
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
-#define __NR_signal 48
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
-#define __NR_lock 53
-#define __NR_ioctl 54
-#define __NR_fcntl 55
-#define __NR_mpx 56
-#define __NR_setpgid 57
-#define __NR_ulimit 58
-#define __NR_oldolduname 59
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-#define __NR_sigaction 67
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
-#define __NR_sigsuspend 72
-#define __NR_sigpending 73
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-#define __NR_getrlimit 76
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
-#define __NR_select 82
-#define __NR_symlink 83
-#define __NR_oldlstat 84
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-#define __NR_readdir 89
-#define __NR_mmap 90
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-#define __NR_profil 98
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-#define __NR_ioperm 101
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-#define __NR_olduname 109
-#define __NR_iopl 110
-#define __NR_vhangup 111
-#define __NR_idle 112
-#define __NR_vm86 113
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-#define __NR_sigreturn 119
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-#define __NR_modify_ldt 123
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-#define __NR_sigprocmask 126
-#define __NR_create_module 127
-#define __NR_init_module 128
-#define __NR_delete_module 129
-#define __NR_get_kernel_syms 130
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
-
-#define __NR_query_module 167
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-#define __NR_chown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-#define __NR_getpmsg 188 /* some people actually want streams */
-#define __NR_putpmsg 189 /* some people actually want streams */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-/* 223 is unused */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-/* #define __NR_sys_setaltroot 285 */
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
-#define __NR_migrate_pages 294
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-#define __NR_set_robust_list 311
-#define __NR_get_robust_list 312
-#define __NR_splice 313
-#define __NR_sync_file_range 314
-#define __NR_tee 315
-#define __NR_vmsplice 316
-#define __NR_move_pages 317
-#define __NR_getcpu 318
-#define __NR_epoll_pwait 319
-#define __NR_utimensat 320
-#define __NR_signalfd 321
-#define __NR_timerfd_create 322
-#define __NR_eventfd 323
-#define __NR_fallocate 324
-#define __NR_timerfd_settime 325
-#define __NR_timerfd_gettime 326
-#define __NR_signalfd4 327
-#define __NR_eventfd2 328
-#define __NR_epoll_create1 329
-#define __NR_dup3 330
-#define __NR_pipe2 331
-#define __NR_inotify_init1 332
-#define __NR_preadv 333
-#define __NR_pwritev 334
-#define __NR_setns 335
-#define __NR_name_to_handle_at 336
-#define __NR_open_by_handle_at 337
-#define __NR_rt_tgsigqueueinfo 338
-#define __NR_perf_event_open 339
-#define __NR_recvmmsg 340
-#define __NR_accept4 341
-#define __NR_fanotify_init 342
-#define __NR_fanotify_mark 343
-#define __NR_prlimit64 344
-#define __NR_clock_adjtime 345
-#define __NR_syncfs 346
-#define __NR_sendmmsg 347
-#define __NR_process_vm_readv 348
-#define __NR_process_vm_writev 349
-#define __NR_kcmp 350
-#define __NR_finit_module 351
-#define __NR_sched_setattr 352
-#define __NR_sched_getattr 353
-#define __NR_renameat2 354
-#define __NR_seccomp 355
-#define __NR_getrandom 356
-#define __NR_memfd_create 357
-#define __NR_bpf 358
-#define __NR_execveat 359
-
-#endif /* _UAPI_ASM_CRIS_UNISTD_H_ */
diff --git a/arch/cris/kernel/Makefile b/arch/cris/kernel/Makefile
deleted file mode 100644
index f6bfee6c8c1b..000000000000
--- a/arch/cris/kernel/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the CRIS port.
-#
-
-CPPFLAGS_vmlinux.lds := -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE)
-extra-y := vmlinux.lds
-
-obj-y := process.o traps.o irq.o ptrace.o setup.o time.o sys_cris.o
-obj-y += stacktrace.o
-
-obj-$(CONFIG_MODULES) += crisksyms.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_SYSTEM_PROFILER) += profile.o
-
-clean:
-
diff --git a/arch/cris/kernel/asm-offsets.c b/arch/cris/kernel/asm-offsets.c
deleted file mode 100644
index 0a5129941485..000000000000
--- a/arch/cris/kernel/asm-offsets.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/kbuild.h>
-#include <linux/sched.h>
-#include <asm/thread_info.h>
-
-/*
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed to extract
- * and format the required data.
- */
-
-#if !defined(CONFIG_ETRAX_ARCH_V10) && !defined(CONFIG_ETRAX_ARCH_V32)
-#error One of ARCH v10 and ARCH v32 must be true!
-#endif
-
-int main(void)
-{
-#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry))
- ENTRY(orig_r10);
- ENTRY(r13);
- ENTRY(r12);
- ENTRY(r11);
- ENTRY(r10);
- ENTRY(r9);
-#ifdef CONFIG_ETRAX_ARCH_V32
- ENTRY(acr);
- ENTRY(srs);
-#endif
- ENTRY(mof);
-#ifdef CONFIG_ETRAX_ARCH_V10
- ENTRY(dccr);
-#else
- ENTRY(ccs);
-#endif
- ENTRY(srp);
- BLANK();
-#undef ENTRY
-#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry))
- ENTRY(task);
- ENTRY(flags);
- ENTRY(preempt_count);
- BLANK();
-#undef ENTRY
-#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry))
- ENTRY(ksp);
- ENTRY(usp);
-#ifdef CONFIG_ETRAX_ARCH_V10
- ENTRY(dccr);
-#else
- ENTRY(ccs);
-#endif
- BLANK();
-#undef ENTRY
-#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry))
- ENTRY(pid);
- BLANK();
- DEFINE(LCLONE_VM, CLONE_VM);
- DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED);
- return 0;
-}
diff --git a/arch/cris/kernel/crisksyms.c b/arch/cris/kernel/crisksyms.c
deleted file mode 100644
index 7024f7278c89..000000000000
--- a/arch/cris/kernel/crisksyms.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/sched.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-#include <linux/pm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/checksum.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/fasttimer.h>
-
-extern void __Udiv(void);
-extern void __Umod(void);
-extern void __Div(void);
-extern void __Mod(void);
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __lshrdi3(void);
-extern void __negdi2(void);
-extern void iounmap(volatile void * __iomem);
-
-/* Platform dependent support */
-EXPORT_SYMBOL(loops_per_usec);
-
-/* Math functions */
-EXPORT_SYMBOL(__Udiv);
-EXPORT_SYMBOL(__Umod);
-EXPORT_SYMBOL(__Div);
-EXPORT_SYMBOL(__Mod);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__negdi2);
-
-/* Memory functions */
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-
-#undef memcpy
-#undef memset
-extern void * memset(void *, int, __kernel_size_t);
-extern void * memcpy(void *, const void *, __kernel_size_t);
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-#ifdef CONFIG_ETRAX_ARCH_V32
-#undef strcmp
-EXPORT_SYMBOL(strcmp);
-#endif
-
-#ifdef CONFIG_ETRAX_FAST_TIMER
-/* Fast timer functions */
-EXPORT_SYMBOL(fast_timer_list);
-EXPORT_SYMBOL(start_one_shot_timer);
-EXPORT_SYMBOL(del_fast_timer);
-EXPORT_SYMBOL(schedule_usleep);
-#endif
-EXPORT_SYMBOL(csum_partial);
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
deleted file mode 100644
index 726cdf4bf2d8..000000000000
--- a/arch/cris/kernel/irq.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- *
- * linux/arch/cris/kernel/irq.c
- *
- * Copyright (c) 2000,2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * This file contains the code used by various IRQ handling routines:
- * asking for different IRQs should be done through these routines
- * instead of just grabbing them. Thus setups with different IRQ numbers
- * shouldn't result in any weird surprises, and installing new handlers
- * should be easier.
- *
- */
-
-/*
- * IRQs are in fact implemented a bit like signal handlers for the kernel.
- * Naturally it's not a 1:1 relation, but there are similarities.
- */
-
-#include <linux/module.h>
-#include <linux/ptrace.h>
-#include <linux/irq.h>
-#include <linux/sched/debug.h>
-
-#include <linux/kernel_stat.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/random.h>
-#include <linux/init.h>
-#include <linux/seq_file.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-
-#include <asm/io.h>
-#include <arch/system.h>
-
-/* called by the assembler IRQ entry functions defined in irq.h
- * to dispatch the interrupts to registered handlers
- */
-
-asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
-{
- unsigned long sp;
- struct pt_regs *old_regs;
-
- trace_hardirqs_off();
-
- old_regs = set_irq_regs(regs);
- irq_enter();
- sp = rdsp();
- if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) {
- printk("do_IRQ: stack overflow: %lX\n", sp);
- show_stack(NULL, (unsigned long *)sp);
- }
- generic_handle_irq(irq);
- irq_exit();
- set_irq_regs(old_regs);
-}
-
-void weird_irq(void)
-{
- local_irq_disable();
- printk("weird irq\n");
- while(1);
-}
-
diff --git a/arch/cris/kernel/module.c b/arch/cris/kernel/module.c
deleted file mode 100644
index af04cb6b6dc9..000000000000
--- a/arch/cris/kernel/module.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Kernel module help for i386.
- Copyright (C) 2001 Rusty Russell.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#if 0
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt , ...)
-#endif
-
-#ifdef CONFIG_ETRAX_KMALLOCED_MODULES
-void *module_alloc(unsigned long size)
-{
- return kmalloc(size, GFP_KERNEL);
-}
-
-/* Free memory returned from module_alloc */
-void module_memfree(void *module_region)
-{
- kfree(module_region);
-}
-#endif
-
-int apply_relocate_add(Elf32_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct module *me)
-{
- unsigned int i;
- Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr;
-
- DEBUGP ("Applying add relocate section %u to %u\n", relsec,
- sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof (*rela); i++) {
- /* This is where to make the change */
- uint32_t *loc
- = ((void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
- + rela[i].r_offset);
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- Elf32_Sym *sym
- = ((Elf32_Sym *)sechdrs[symindex].sh_addr
- + ELF32_R_SYM (rela[i].r_info));
- switch (ELF32_R_TYPE(rela[i].r_info)) {
- case R_CRIS_32:
- *loc = sym->st_value + rela[i].r_addend;
- break;
- case R_CRIS_32_PCREL:
- *loc = sym->st_value - (unsigned)loc + rela[i].r_addend - 4;
- break;
- default:
- printk(KERN_ERR "module %s: Unknown relocation: %u\n",
- me->name, ELF32_R_TYPE(rela[i].r_info));
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
deleted file mode 100644
index 50e5cf09841d..000000000000
--- a/arch/cris/kernel/process.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/process.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-/*
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/atomic.h>
-#include <asm/pgtable.h>
-#include <linux/uaccess.h>
-#include <asm/irq.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/init_task.h>
-#include <linux/sched.h>
-#include <linux/sched/task.h>
-#include <linux/fs.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/mqueue.h>
-#include <linux/reboot.h>
-#include <linux/rcupdate.h>
-
-//#define DEBUG
-
-extern void default_idle(void);
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-void arch_cpu_idle(void)
-{
- default_idle();
-}
-
-void hard_reset_now (void);
-
-void machine_restart(char *cmd)
-{
- hard_reset_now();
-}
-
-/*
- * Similar to machine_power_off, but don't shut off power. Add code
- * here to freeze the system for e.g. post-mortem debug purpose when
- * possible. This halt has nothing to do with the idle halt.
- */
-
-void machine_halt(void)
-{
-}
-
-/* If or when software power-off is implemented, add code here. */
-
-void machine_power_off(void)
-{
-}
-
-/*
- * When a process does an "exec", machine state like FPU and debug
- * registers need to be reset. This is a hook function for that.
- * Currently we don't have any such state to reset, so this is empty.
- */
-
-void flush_thread(void)
-{
-}
-
-/* Fill in the fpu structure for a core dump. */
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
-{
- return 0;
-}
diff --git a/arch/cris/kernel/profile.c b/arch/cris/kernel/profile.c
deleted file mode 100644
index d2f978ad129a..000000000000
--- a/arch/cris/kernel/profile.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <linux/uaccess.h>
-
-#define SAMPLE_BUFFER_SIZE 8192
-
-static char *sample_buffer;
-static char *sample_buffer_pos;
-static int prof_running = 0;
-
-void cris_profile_sample(struct pt_regs *regs)
-{
- if (!prof_running)
- return;
-
- if (user_mode(regs))
- *(unsigned int*)sample_buffer_pos = current->pid;
- else
- *(unsigned int*)sample_buffer_pos = 0;
-
- *(unsigned int *)(sample_buffer_pos + 4) = instruction_pointer(regs);
- sample_buffer_pos += 8;
-
- if (sample_buffer_pos == sample_buffer + SAMPLE_BUFFER_SIZE)
- sample_buffer_pos = sample_buffer;
-}
-
-static ssize_t
-read_cris_profile(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- unsigned long p = *ppos;
- ssize_t ret;
-
- ret = simple_read_from_buffer(buf, count, ppos, sample_buffer,
- SAMPLE_BUFFER_SIZE);
- if (ret < 0)
- return ret;
-
- memset(sample_buffer + p, 0, ret);
-
- return ret;
-}
-
-static ssize_t
-write_cris_profile(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- sample_buffer_pos = sample_buffer;
- memset(sample_buffer, 0, SAMPLE_BUFFER_SIZE);
- return count < SAMPLE_BUFFER_SIZE ? count : SAMPLE_BUFFER_SIZE;
-}
-
-static const struct file_operations cris_proc_profile_operations = {
- .read = read_cris_profile,
- .write = write_cris_profile,
- .llseek = default_llseek,
-};
-
-static int __init init_cris_profile(void)
-{
- struct proc_dir_entry *entry;
-
- sample_buffer = kmalloc(SAMPLE_BUFFER_SIZE, GFP_KERNEL);
- if (!sample_buffer) {
- return -ENOMEM;
- }
-
- sample_buffer_pos = sample_buffer;
-
- entry = proc_create("system_profile", S_IWUSR | S_IRUGO, NULL,
- &cris_proc_profile_operations);
- if (entry) {
- proc_set_size(entry, SAMPLE_BUFFER_SIZE);
- }
- prof_running = 1;
-
- return 0;
-}
-__initcall(init_cris_profile);
-
diff --git a/arch/cris/kernel/ptrace.c b/arch/cris/kernel/ptrace.c
deleted file mode 100644
index af42789a1544..000000000000
--- a/arch/cris/kernel/ptrace.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/ptrace.c
- *
- * Parts taken from the m68k port.
- *
- * Copyright (c) 2000, 2001, 2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/tracehook.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-
-
-/* notification of userspace execution resumption
- * - triggered by current->work.notify_resume
- */
-extern int do_signal(int canrestart, struct pt_regs *regs);
-
-
-void do_notify_resume(int canrestart, struct pt_regs *regs,
- __u32 thread_info_flags)
-{
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal(canrestart,regs);
-
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
-
-void do_work_pending(int syscall, struct pt_regs *regs,
- unsigned int thread_flags)
-{
- do {
- if (likely(thread_flags & _TIF_NEED_RESCHED)) {
- schedule();
- } else {
- if (unlikely(!user_mode(regs)))
- return;
- local_irq_enable();
- if (thread_flags & _TIF_SIGPENDING) {
- do_signal(syscall, regs);
- syscall = 0;
- } else {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
- }
- local_irq_disable();
- thread_flags = current_thread_info()->flags;
- } while (thread_flags & _TIF_WORK_MASK);
-}
diff --git a/arch/cris/kernel/setup.c b/arch/cris/kernel/setup.c
deleted file mode 100644
index 1b61a7207afb..000000000000
--- a/arch/cris/kernel/setup.c
+++ /dev/null
@@ -1,214 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- *
- * linux/arch/cris/kernel/setup.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (c) 2001 Axis Communications AB
- */
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/pgtable.h>
-#include <linux/seq_file.h>
-#include <linux/screen_info.h>
-#include <linux/utsname.h>
-#include <linux/pfn.h>
-#include <linux/cpu.h>
-#include <linux/of.h>
-#include <linux/of_fdt.h>
-#include <asm/setup.h>
-#include <arch/system.h>
-#include <asm/sections.h>
-
-/*
- * Setup options
- */
-struct screen_info screen_info;
-
-extern int root_mountflags;
-
-char __initdata cris_command_line[COMMAND_LINE_SIZE] = { 0, };
-
-extern const unsigned long text_start, edata; /* set by the linker script */
-extern unsigned long dram_start, dram_end;
-
-extern unsigned long romfs_start, romfs_length, romfs_in_flash; /* from head.S */
-
-static struct cpu cpu_devices[NR_CPUS];
-
-extern void show_etrax_copyright(void); /* arch-vX/kernel/setup.c */
-
-/* This mainly sets up the memory area, and can be really confusing.
- *
- * The physical DRAM is virtually mapped into dram_start to dram_end
- * (usually c0000000 to c0000000 + DRAM size). The physical address is
- * given by the macro __pa().
- *
- * In this DRAM, the kernel code and data is loaded, in the beginning.
- * It really starts at c0004000 to make room for some special pages -
- * the start address is text_start. The kernel data ends at _end. After
- * this the ROM filesystem is appended (if there is any).
- *
- * Between this address and dram_end, we have RAM pages usable to the
- * boot code and the system.
- *
- */
-
-void __init setup_arch(char **cmdline_p)
-{
- extern void init_etrax_debug(void);
- unsigned long bootmap_size;
- unsigned long start_pfn, max_pfn;
- unsigned long memory_start;
-
-#ifdef CONFIG_OF
- early_init_dt_scan(__dtb_start);
-#endif
-
- /* register an initial console printing routine for printk's */
-
- init_etrax_debug();
-
- /* we should really poll for DRAM size! */
-
- high_memory = &dram_end;
-
- if(romfs_in_flash || !romfs_length) {
- /* if we have the romfs in flash, or if there is no rom filesystem,
- * our free area starts directly after the BSS
- */
- memory_start = (unsigned long) &_end;
- } else {
- /* otherwise the free area starts after the ROM filesystem */
- printk("ROM fs in RAM, size %lu bytes\n", romfs_length);
- memory_start = romfs_start + romfs_length;
- }
-
- /* process 1's initial memory region is the kernel code/data */
-
- init_mm.start_code = (unsigned long) &text_start;
- init_mm.end_code = (unsigned long) &_etext;
- init_mm.end_data = (unsigned long) &_edata;
- init_mm.brk = (unsigned long) &_end;
-
- /* min_low_pfn points to the start of DRAM, start_pfn points
- * to the first DRAM pages after the kernel, and max_low_pfn
- * to the end of DRAM.
- */
-
- /*
- * partially used pages are not usable - thus
- * we are rounding upwards:
- */
-
- start_pfn = PFN_UP(memory_start); /* usually c0000000 + kernel + romfs */
- max_pfn = PFN_DOWN((unsigned long)high_memory); /* usually c0000000 + dram size */
-
- /*
- * Initialize the boot-time allocator (start, end)
- *
- * We give it access to all our DRAM, but we could as well just have
- * given it a small slice. No point in doing that though, unless we
- * have non-contiguous memory and want the boot-stuff to be in, say,
- * the smallest area.
- *
- * It will put a bitmap of the allocated pages in the beginning
- * of the range we give it, but it won't mark the bitmaps pages
- * as reserved. We have to do that ourselves below.
- *
- * We need to use init_bootmem_node instead of init_bootmem
- * because our map starts at a quite high address (min_low_pfn).
- */
-
- max_low_pfn = max_pfn;
- min_low_pfn = PAGE_OFFSET >> PAGE_SHIFT;
-
- bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
- min_low_pfn,
- max_low_pfn);
-
- /* And free all memory not belonging to the kernel (addr, size) */
-
- free_bootmem(PFN_PHYS(start_pfn), PFN_PHYS(max_pfn - start_pfn));
-
- /*
- * Reserve the bootmem bitmap itself as well. We do this in two
- * steps (first step was init_bootmem()) because this catches
- * the (very unlikely) case of us accidentally initializing the
- * bootmem allocator with an invalid RAM area.
- *
- * Arguments are start, size
- */
-
- reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT);
-
- unflatten_and_copy_device_tree();
-
- /* paging_init() sets up the MMU and marks all pages as reserved */
-
- paging_init();
-
- *cmdline_p = cris_command_line;
-
-#ifdef CONFIG_ETRAX_CMDLINE
- if (!strcmp(cris_command_line, "")) {
- strlcpy(cris_command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE);
- cris_command_line[COMMAND_LINE_SIZE - 1] = '\0';
- }
-#endif
-
- /* Save command line for future references. */
- memcpy(boot_command_line, cris_command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- /* give credit for the CRIS port */
- show_etrax_copyright();
-
- /* Setup utsname */
- strcpy(init_utsname()->machine, cris_machine_name);
-}
-
-#ifdef CONFIG_PROC_FS
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < nr_cpu_ids ? (void *)(int)(*pos + 1) : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-extern int show_cpuinfo(struct seq_file *m, void *v);
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-#endif /* CONFIG_PROC_FS */
-
-static int __init topology_init(void)
-{
- int i;
-
- for_each_possible_cpu(i) {
- return register_cpu(&cpu_devices[i], i);
- }
-
- return 0;
-}
-
-subsys_initcall(topology_init);
diff --git a/arch/cris/kernel/stacktrace.c b/arch/cris/kernel/stacktrace.c
deleted file mode 100644
index f1cc3aaacd8d..000000000000
--- a/arch/cris/kernel/stacktrace.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/stacktrace.h>
-#include <asm/stacktrace.h>
-
-void walk_stackframe(unsigned long sp,
- int (*fn)(unsigned long addr, void *data),
- void *data)
-{
- unsigned long high = ALIGN(sp, THREAD_SIZE);
-
- for (; sp <= high - 4; sp += 4) {
- unsigned long addr = *(unsigned long *) sp;
-
- if (!kernel_text_address(addr))
- continue;
-
- if (fn(addr, data))
- break;
- }
-}
-
-struct stack_trace_data {
- struct stack_trace *trace;
- unsigned int no_sched_functions;
- unsigned int skip;
-};
-
-#ifdef CONFIG_STACKTRACE
-
-static int save_trace(unsigned long addr, void *d)
-{
- struct stack_trace_data *data = d;
- struct stack_trace *trace = data->trace;
-
- if (data->no_sched_functions && in_sched_functions(addr))
- return 0;
-
- if (data->skip) {
- data->skip--;
- return 0;
- }
-
- trace->entries[trace->nr_entries++] = addr;
-
- return trace->nr_entries >= trace->max_entries;
-}
-
-void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
-{
- struct stack_trace_data data;
- unsigned long sp;
-
- data.trace = trace;
- data.skip = trace->skip;
-
- if (tsk != current) {
- data.no_sched_functions = 1;
- sp = tsk->thread.ksp;
- } else {
- data.no_sched_functions = 0;
- sp = rdsp();
- }
-
- walk_stackframe(sp, save_trace, &data);
- if (trace->nr_entries < trace->max_entries)
- trace->entries[trace->nr_entries++] = ULONG_MAX;
-}
-
-void save_stack_trace(struct stack_trace *trace)
-{
- save_stack_trace_tsk(current, trace);
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
-
-#endif /* CONFIG_STACKTRACE */
diff --git a/arch/cris/kernel/sys_cris.c b/arch/cris/kernel/sys_cris.c
deleted file mode 100644
index ecea13f1d760..000000000000
--- a/arch/cris/kernel/sys_cris.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* $Id: sys_cris.c,v 1.6 2004/03/11 11:38:40 starvik Exp $
- *
- * linux/arch/cris/kernel/sys_cris.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on some platforms.
- * Since we don't have to do any backwards compatibility, our
- * versions are done in the most "normal" way possible.
- *
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/syscalls.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/ipc.h>
-
-#include <linux/uaccess.h>
-#include <asm/segment.h>
-
-asmlinkage long
-sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
- unsigned long flags, unsigned long fd, unsigned long pgoff)
-{
- /* bug(?): 8Kb pages here */
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
-}
diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c
deleted file mode 100644
index 593239274f98..000000000000
--- a/arch/cris/kernel/time.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/time.c
- *
- * Copyright (C) 1991, 1992, 1995 Linus Torvalds
- * Copyright (C) 1999, 2000, 2001 Axis Communications AB
- *
- * 1994-07-02 Alan Modra
- * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
- * 1995-03-26 Markus Kuhn
- * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
- * precision CMOS clock update
- * 1996-05-03 Ingo Molnar
- * fixed time warps in do_[slow|fast]_gettimeoffset()
- * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
- * "A Kernel Model for Precision Timekeeping" by Dave Mills
- *
- * Linux/CRIS specific code:
- *
- * Authors: Bjorn Wesen
- * Johan Adolfsson
- *
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/jiffies.h>
-#include <linux/bcd.h>
-#include <linux/timex.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/sched/clock.h>
-
-
-#define D(x)
-
-#define TICK_SIZE tick
-
-extern unsigned long loops_per_jiffy; /* init/main.c */
-unsigned long loops_per_usec;
-
-extern void cris_profile_sample(struct pt_regs* regs);
-
-void
-cris_do_profile(struct pt_regs* regs)
-{
-
-#ifdef CONFIG_SYSTEM_PROFILER
- cris_profile_sample(regs);
-#endif
-
-#ifdef CONFIG_PROFILING
- profile_tick(CPU_PROFILING);
-#endif
-}
-
-#ifndef CONFIG_GENERIC_SCHED_CLOCK
-unsigned long long sched_clock(void)
-{
- return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ) +
- get_ns_in_jiffie();
-}
-#endif
-
-static int
-__init init_udelay(void)
-{
- loops_per_usec = (loops_per_jiffy * HZ) / 1000000;
- return 0;
-}
-
-__initcall(init_udelay);
diff --git a/arch/cris/kernel/traps.c b/arch/cris/kernel/traps.c
deleted file mode 100644
index d4bc80469218..000000000000
--- a/arch/cris/kernel/traps.c
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/traps.c
- *
- * Here we handle the break vectors not used by the system call
- * mechanism, as well as some general stack/register dumping
- * things.
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- * Hans-Peter Nilsson
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/utsname.h>
-#include <linux/sched/debug.h>
-#ifdef CONFIG_KALLSYMS
-#include <linux/kallsyms.h>
-#endif
-
-#include <asm/pgtable.h>
-#include <linux/uaccess.h>
-#include <arch/system.h>
-
-extern void arch_enable_nmi(void);
-extern void stop_watchdog(void);
-extern void reset_watchdog(void);
-extern void show_registers(struct pt_regs *regs);
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-extern void handle_BUG(struct pt_regs *regs);
-#else
-#define handle_BUG(regs)
-#endif
-
-static int kstack_depth_to_print = 24;
-
-void (*nmi_handler)(struct pt_regs *);
-
-void show_trace(unsigned long *stack)
-{
- unsigned long addr, module_start, module_end;
- extern char _stext[], _etext[];
- int i;
-
- pr_err("\nCall Trace: ");
-
- i = 1;
- module_start = VMALLOC_START;
- module_end = VMALLOC_END;
-
- while (((long)stack & (THREAD_SIZE - 1)) != 0) {
- if (__get_user(addr, stack)) {
- /* This message matches "failing address" marked
- s390 in ksymoops, so lines containing it will
- not be filtered out by ksymoops. */
- pr_err("Failing address 0x%lx\n", (unsigned long)stack);
- break;
- }
- stack++;
-
- /*
- * If the address is either in the text segment of the
- * kernel, or in the region which contains vmalloc'ed
- * memory, it *may* be the address of a calling
- * routine; if so, print it so that someone tracing
- * down the cause of the crash will be able to figure
- * out the call path that was taken.
- */
- if (((addr >= (unsigned long)_stext) &&
- (addr <= (unsigned long)_etext)) ||
- ((addr >= module_start) && (addr <= module_end))) {
-#ifdef CONFIG_KALLSYMS
- print_ip_sym(addr);
-#else
- if (i && ((i % 8) == 0))
- pr_err("\n ");
- pr_err("[<%08lx>] ", addr);
- i++;
-#endif
- }
- }
-}
-
-/*
- * These constants are for searching for possible module text
- * segments. MODULE_RANGE is a guess of how much space is likely
- * to be vmalloced.
- */
-
-#define MODULE_RANGE (8*1024*1024)
-
-/*
- * The output (format, strings and order) is adjusted to be usable with
- * ksymoops-2.4.1 with some necessary CRIS-specific patches. Please don't
- * change it unless you're serious about adjusting ksymoops and syncing
- * with the ksymoops maintainer.
- */
-
-void
-show_stack(struct task_struct *task, unsigned long *sp)
-{
- unsigned long *stack, addr;
- int i;
-
- /*
- * debugging aid: "show_stack(NULL);" prints a
- * back trace.
- */
-
- if (sp == NULL) {
- if (task)
- sp = (unsigned long*)task->thread.ksp;
- else
- sp = (unsigned long*)rdsp();
- }
-
- stack = sp;
-
- pr_err("\nStack from %08lx:\n ", (unsigned long)stack);
- for (i = 0; i < kstack_depth_to_print; i++) {
- if (((long)stack & (THREAD_SIZE-1)) == 0)
- break;
- if (i && ((i % 8) == 0))
- pr_err("\n ");
- if (__get_user(addr, stack)) {
- /* This message matches "failing address" marked
- s390 in ksymoops, so lines containing it will
- not be filtered out by ksymoops. */
- pr_err("Failing address 0x%lx\n", (unsigned long)stack);
- break;
- }
- stack++;
- pr_err("%08lx ", addr);
- }
- show_trace(sp);
-}
-
-#if 0
-/* displays a short stack trace */
-
-int
-show_stack(void)
-{
- unsigned long *sp = (unsigned long *)rdusp();
- int i;
-
- pr_err("Stack dump [0x%08lx]:\n", (unsigned long)sp);
- for (i = 0; i < 16; i++)
- pr_err("sp + %d: 0x%08lx\n", i*4, sp[i]);
- return 0;
-}
-#endif
-
-void set_nmi_handler(void (*handler)(struct pt_regs *))
-{
- nmi_handler = handler;
- arch_enable_nmi();
-}
-
-#ifdef CONFIG_DEBUG_NMI_OOPS
-void oops_nmi_handler(struct pt_regs *regs)
-{
- stop_watchdog();
- oops_in_progress = 1;
- pr_err("NMI!\n");
- show_registers(regs);
- oops_in_progress = 0;
- oops_exit();
- pr_err("\n"); /* Flush mtdoops. */
-}
-
-static int __init oops_nmi_register(void)
-{
- set_nmi_handler(oops_nmi_handler);
- return 0;
-}
-
-__initcall(oops_nmi_register);
-
-#endif
-
-/*
- * This gets called from entry.S when the watchdog has bitten. Show something
- * similar to an Oops dump, and if the kernel is configured to be a nice
- * doggy, then halt instead of reboot.
- */
-void watchdog_bite_hook(struct pt_regs *regs)
-{
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- local_irq_disable();
- stop_watchdog();
- show_registers(regs);
-
- while (1)
- ; /* Do nothing. */
-#else
- show_registers(regs);
-#endif
-}
-
-/* This is normally the Oops function. */
-void die_if_kernel(const char *str, struct pt_regs *regs, long err)
-{
- if (user_mode(regs))
- return;
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- /*
- * This printout might take too long and could trigger
- * the watchdog normally. If NICE_DOGGY is set, simply
- * stop the watchdog during the printout.
- */
- stop_watchdog();
-#endif
-
- oops_enter();
- handle_BUG(regs);
-
- pr_err("Linux %s %s\n", utsname()->release, utsname()->version);
- pr_err("%s: %04lx\n", str, err & 0xffff);
-
- show_registers(regs);
-
- oops_exit();
- oops_in_progress = 0;
- pr_err("\n"); /* Flush mtdoops. */
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
- do_exit(SIGSEGV);
-}
-
-void __init trap_init(void)
-{
- /* Nothing needs to be done */
-}
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
deleted file mode 100644
index 9b232e0f673e..000000000000
--- a/arch/cris/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ld script to make the Linux/CRIS kernel
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * It is VERY DANGEROUS to fiddle around with the symbols in this
- * script. It is for example quite vital that all generated sections
- * that are used are actually named here, otherwise the linker will
- * put them at the end, where the init stuff is which is FREED after
- * the kernel has booted.
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-#ifdef CONFIG_ETRAX_VMEM_SIZE
-#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE
-#else
-#define __CONFIG_ETRAX_VMEM_SIZE 0
-#endif
-
-
-jiffies = jiffies_64;
-SECTIONS
-{
- . = DRAM_VIRTUAL_BASE;
- dram_start = .;
-#ifdef CONFIG_ETRAX_ARCH_V10
- ibr_start = .;
-#else
- ebp_start = .;
- /* The boot section is only necessary until the VCS top */
- /* level testbench includes both flash and DRAM. */
- .boot : { *(.boot) }
-#endif
-
- /* see head.S and pages reserved at the start */
- . = DRAM_VIRTUAL_BASE + 0x4000;
-
- _text = .; /* Text and read-only data. */
- text_start = .; /* Lots of aliases. */
- _stext = .;
- __stext = .;
- .text : {
- HEAD_TEXT
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- *(.fixup)
- *(.text.__*)
- }
-
- _etext = . ; /* End of text section. */
- __etext = .;
-
- EXCEPTION_TABLE(4)
-
- _sdata = .;
- RODATA
-
- . = ALIGN (4);
- ___data_start = . ;
- __Sdata = . ;
- .data : { /* Data */
- CACHELINE_ALIGNED_DATA(32)
- READ_MOSTLY_DATA(32)
- DATA_DATA
- }
- __edata = . ; /* End of data section. */
- _edata = . ;
-
- BUG_TABLE
-
- INIT_TASK_DATA_SECTION(PAGE_SIZE)
-
- . = ALIGN(PAGE_SIZE); /* Init code and data. */
- __init_begin = .;
- INIT_TEXT_SECTION(PAGE_SIZE)
- .init.data : { INIT_DATA }
- .init.setup : { INIT_SETUP(16) }
- .initcall.init : {
- INIT_CALLS
- }
-
- .con_initcall.init : {
- CON_INITCALL
- }
- SECURITY_INIT
-
- /* .exit.text is discarded at runtime, not link time,
- * to deal with references from __bug_table
- */
- .exit.text : {
- EXIT_TEXT
- }
- .exit.data : {
- EXIT_DATA
- }
-
-#ifdef CONFIG_ETRAX_ARCH_V10
-#ifdef CONFIG_BLK_DEV_INITRD
- .init.ramfs : {
- __initramfs_start = .;
- *(.init.ramfs)
- __initramfs_end = .;
- }
-#endif
-#endif
- __vmlinux_end = .; /* Last address of the physical file. */
-#ifdef CONFIG_ETRAX_ARCH_V32
- PERCPU_SECTION(32)
-
- .init.ramfs : {
- INIT_RAM_FS
- }
-#endif
-
- /*
- * We fill to the next page, so we can discard all init
- * pages without needing to consider what payload might be
- * appended to the kernel image.
- */
- . = ALIGN(PAGE_SIZE);
-
- __init_end = .;
-
- __data_end = . ; /* Move to _edata ? */
- BSS_SECTION(1, 1, 1)
-
- . = ALIGN (0x20);
- _end = .;
- __end = .;
-
- dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024;
-
- DISCARDS
-}
diff --git a/arch/cris/mm/Makefile b/arch/cris/mm/Makefile
deleted file mode 100644
index d3ae08c90b4e..000000000000
--- a/arch/cris/mm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for the linux cris-specific parts of the memory manager.
-#
-
-obj-y := init.o fault.o tlb.o ioremap.o
-
diff --git a/arch/cris/mm/fault.c b/arch/cris/mm/fault.c
deleted file mode 100644
index 29cc58038b98..000000000000
--- a/arch/cris/mm/fault.c
+++ /dev/null
@@ -1,390 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/cris/mm/fault.c
- *
- * Copyright (C) 2000-2010 Axis Communications AB
- */
-
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/extable.h>
-#include <linux/wait.h>
-#include <linux/sched/signal.h>
-#include <linux/uaccess.h>
-#include <arch/system.h>
-
-extern int find_fixup_code(struct pt_regs *);
-extern void die_if_kernel(const char *, struct pt_regs *, long);
-extern void show_registers(struct pt_regs *regs);
-
-/* debug of low-level TLB reload */
-#undef DEBUG
-
-#ifdef DEBUG
-#define D(x) x
-#else
-#define D(x)
-#endif
-
-/* debug of higher-level faults */
-#define DPG(x)
-
-/* current active page directory */
-
-DEFINE_PER_CPU(pgd_t *, current_pgd);
-unsigned long cris_signal_return_page;
-
-/*
- * This routine handles page faults. It determines the address,
- * and the problem, and then passes it off to one of the appropriate
- * routines.
- *
- * Notice that the address we're given is aligned to the page the fault
- * occurred in, since we only get the PFN in R_MMU_CAUSE not the complete
- * address.
- *
- * error_code:
- * bit 0 == 0 means no page found, 1 means protection fault
- * bit 1 == 0 means read, 1 means write
- *
- * If this routine detects a bad access, it returns 1, otherwise it
- * returns 0.
- */
-
-asmlinkage void
-do_page_fault(unsigned long address, struct pt_regs *regs,
- int protection, int writeaccess)
-{
- struct task_struct *tsk;
- struct mm_struct *mm;
- struct vm_area_struct * vma;
- siginfo_t info;
- int fault;
- unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
-
- D(printk(KERN_DEBUG
- "Page fault for %lX on %X at %lX, prot %d write %d\n",
- address, smp_processor_id(), instruction_pointer(regs),
- protection, writeaccess));
-
- tsk = current;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * NOTE2: This is done so that, when updating the vmalloc
- * mappings we don't have to walk all processes pgdirs and
- * add the high mappings all at once. Instead we do it as they
- * are used. However vmalloc'ed page entries have the PAGE_GLOBAL
- * bit set so sometimes the TLB can use a lingering entry.
- *
- * This verifies that the fault happens in kernel space
- * and that the fault was not a protection error (error_code & 1).
- */
-
- if (address >= VMALLOC_START &&
- !protection &&
- !user_mode(regs))
- goto vmalloc_fault;
-
- /* When stack execution is not allowed we store the signal
- * trampolines in the reserved cris_signal_return_page.
- * Handle this in the exact same way as vmalloc (we know
- * that the mapping is there and is valid so no need to
- * call handle_mm_fault).
- */
- if (cris_signal_return_page &&
- address == cris_signal_return_page &&
- !protection && user_mode(regs))
- goto vmalloc_fault;
-
- /* we can and should enable interrupts at this point */
- local_irq_enable();
-
- mm = tsk->mm;
- info.si_code = SEGV_MAPERR;
-
- /*
- * If we're in an interrupt, have pagefaults disabled or have no
- * user context, we must not take the fault.
- */
-
- if (faulthandler_disabled() || !mm)
- goto no_context;
-
- if (user_mode(regs))
- flags |= FAULT_FLAG_USER;
-retry:
- down_read(&mm->mmap_sem);
- vma = find_vma(mm, address);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= address)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
- if (user_mode(regs)) {
- /*
- * accessing the stack below usp is always a bug.
- * we get page-aligned addresses so we can only check
- * if we're within a page from usp, but that might be
- * enough to catch brutal errors at least.
- */
- if (address + PAGE_SIZE < rdusp())
- goto bad_area;
- }
- if (expand_stack(vma, address))
- goto bad_area;
-
- /*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
-
- good_area:
- info.si_code = SEGV_ACCERR;
-
- /* first do some preliminary protection checks */
-
- if (writeaccess == 2){
- if (!(vma->vm_flags & VM_EXEC))
- goto bad_area;
- } else if (writeaccess == 1) {
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- } else {
- if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
- goto bad_area;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
-
- fault = handle_mm_fault(vma, address, flags);
-
- if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
- return;
-
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
-
- if (flags & FAULT_FLAG_ALLOW_RETRY) {
- if (fault & VM_FAULT_MAJOR)
- tsk->maj_flt++;
- else
- tsk->min_flt++;
- if (fault & VM_FAULT_RETRY) {
- flags &= ~FAULT_FLAG_ALLOW_RETRY;
- flags |= FAULT_FLAG_TRIED;
-
- /*
- * No need to up_read(&mm->mmap_sem) as we would
- * have already released it in __lock_page_or_retry
- * in mm/filemap.c.
- */
-
- goto retry;
- }
- }
-
- up_read(&mm->mmap_sem);
- return;
-
- /*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
-
- bad_area:
- up_read(&mm->mmap_sem);
-
- bad_area_nosemaphore:
- DPG(show_registers(regs));
-
- /* User mode accesses just cause a SIGSEGV */
-
- if (user_mode(regs)) {
-#ifdef CONFIG_NO_SEGFAULT_TERMINATION
- DECLARE_WAIT_QUEUE_HEAD(wq);
-#endif
- printk(KERN_NOTICE "%s (pid %d) segfaults for page "
- "address %08lx at pc %08lx\n",
- tsk->comm, tsk->pid,
- address, instruction_pointer(regs));
-
- /* With DPG on, we've already dumped registers above. */
- DPG(if (0))
- show_registers(regs);
-
-#ifdef CONFIG_NO_SEGFAULT_TERMINATION
- wait_event_interruptible(wq, 0 == 1);
-#else
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void *)address;
- force_sig_info(SIGSEGV, &info, tsk);
-#endif
- return;
- }
-
- no_context:
-
- /* Are we prepared to handle this kernel fault?
- *
- * (The kernel has valid exception-points in the source
- * when it accesses user-memory. When it fails in one
- * of those points, we find it in a table and do a jump
- * to some fixup code that loads an appropriate error
- * code)
- */
-
- if (find_fixup_code(regs))
- return;
-
- /*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- if (!oops_in_progress) {
- oops_in_progress = 1;
- if ((unsigned long) (address) < PAGE_SIZE)
- printk(KERN_ALERT "Unable to handle kernel NULL "
- "pointer dereference");
- else
- printk(KERN_ALERT "Unable to handle kernel access"
- " at virtual address %08lx\n", address);
-
- die_if_kernel("Oops", regs, (writeaccess << 1) | protection);
- oops_in_progress = 0;
- }
-
- do_exit(SIGKILL);
-
- /*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-
- out_of_memory:
- up_read(&mm->mmap_sem);
- if (!user_mode(regs))
- goto no_context;
- pagefault_out_of_memory();
- return;
-
- do_sigbus:
- up_read(&mm->mmap_sem);
-
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void *)address;
- force_sig_info(SIGBUS, &info, tsk);
-
- /* Kernel mode? Handle exceptions or die */
- if (!user_mode(regs))
- goto no_context;
- return;
-
-vmalloc_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Use current_pgd instead of tsk->active_mm->pgd
- * since the latter might be unavailable if this
- * code is executed in a misfortunately run irq
- * (like inside schedule() between switch_mm and
- * switch_to...).
- */
-
- int offset = pgd_index(address);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = (pgd_t *)per_cpu(current_pgd, smp_processor_id()) + offset;
- pgd_k = init_mm.pgd + offset;
-
- /* Since we're two-level, we don't need to do both
- * set_pgd and set_pmd (they do the same thing). If
- * we go three-level at some point, do the right thing
- * with pgd_present and set_pgd here.
- *
- * Also, since the vmalloc area is global, we don't
- * need to copy individual PTE's, it is enough to
- * copy the pgd pointer into the pte page of the
- * root task. If that is there, we'll find our pte if
- * it exists.
- */
-
- pud = pud_offset(pgd, address);
- pud_k = pud_offset(pgd_k, address);
- if (!pud_present(*pud_k))
- goto no_context;
-
- pmd = pmd_offset(pud, address);
- pmd_k = pmd_offset(pud_k, address);
-
- if (!pmd_present(*pmd_k))
- goto bad_area_nosemaphore;
-
- set_pmd(pmd, *pmd_k);
-
- /* Make sure the actual PTE exists as well to
- * catch kernel vmalloc-area accesses to non-mapped
- * addresses. If we don't do this, this will just
- * silently loop forever.
- */
-
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- goto no_context;
-
- return;
- }
-}
-
-/* Find fixup code. */
-int
-find_fixup_code(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
- /* in case of delay slot fault (v32) */
- unsigned long ip = (instruction_pointer(regs) & ~0x1);
-
- fixup = search_exception_tables(ip);
- if (fixup != 0) {
- /* Adjust the instruction pointer in the stackframe. */
- instruction_pointer(regs) = fixup->fixup;
- arch_fixup(regs);
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c
deleted file mode 100644
index e41d9c833e1c..000000000000
--- a/arch/cris/mm/init.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/mm/init.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 2000,2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/gfp.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/proc_fs.h>
-#include <linux/kcore.h>
-#include <asm/tlb.h>
-#include <asm/sections.h>
-
-unsigned long empty_zero_page;
-EXPORT_SYMBOL(empty_zero_page);
-
-void __init mem_init(void)
-{
- BUG_ON(!mem_map);
-
- /* max/min_low_pfn was set by setup.c
- * now we just copy it to some other necessary places...
- *
- * high_memory was also set in setup.c
- */
- max_mapnr = max_low_pfn - min_low_pfn;
- free_all_bootmem();
- mem_init_print_info(NULL);
-}
-
-/* Free a range of init pages. Virtual addresses. */
-
-void free_init_pages(const char *what, unsigned long begin, unsigned long end)
-{
- unsigned long addr;
-
- for (addr = begin; addr < end; addr += PAGE_SIZE) {
- ClearPageReserved(virt_to_page(addr));
- init_page_count(virt_to_page(addr));
- free_page(addr);
- totalram_pages++;
- }
-
- printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
-/* Free the pages occupied by initialization code. */
-
-void free_initmem(void)
-{
- free_initmem_default(-1);
-}
-
-/* Free the pages occupied by initrd code. */
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_init_pages("initrd memory",
- start,
- end);
-}
-#endif
diff --git a/arch/cris/mm/ioremap.c b/arch/cris/mm/ioremap.c
deleted file mode 100644
index 350bd2a86ade..000000000000
--- a/arch/cris/mm/ioremap.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/cris/mm/ioremap.c
- *
- * Re-map IO memory to kernel address space so that we can access it.
- * Needed for memory-mapped I/O devices mapped outside our normal DRAM
- * window (that is, all memory-mapped I/O devices).
- *
- * (C) Copyright 1995 1996 Linus Torvalds
- * CRIS-port by Axis Communications AB
- */
-
-#include <linux/vmalloc.h>
-#include <linux/io.h>
-#include <asm/pgalloc.h>
-#include <arch/memmap.h>
-
-/*
- * Generic mapping function (not visible outside):
- */
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- */
-void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot)
-{
- void __iomem * addr;
- struct vm_struct * area;
- unsigned long offset, last_addr;
-
- /* Don't allow wraparound or zero size */
- last_addr = phys_addr + size - 1;
- if (!size || last_addr < phys_addr)
- return NULL;
-
- /*
- * Mappings have to be page-aligned
- */
- offset = phys_addr & ~PAGE_MASK;
- phys_addr &= PAGE_MASK;
- size = PAGE_ALIGN(last_addr+1) - phys_addr;
-
- /*
- * Ok, go for it..
- */
- area = get_vm_area(size, VM_IOREMAP);
- if (!area)
- return NULL;
- addr = (void __iomem *)area->addr;
- if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
- phys_addr, prot)) {
- vfree((void __force *)addr);
- return NULL;
- }
- return (void __iomem *) (offset + (char __iomem *)addr);
-}
-
-void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
-{
- return __ioremap_prot(phys_addr, size,
- __pgprot(_PAGE_PRESENT | __READABLE |
- __WRITEABLE | _PAGE_GLOBAL |
- _PAGE_KERNEL | flags));
-}
-
-/**
- * ioremap_nocache - map bus memory into CPU space
- * @offset: bus address of the memory
- * @size: size of the resource to map
- *
- * Must be freed with iounmap.
- */
-
-void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size)
-{
- return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0);
-}
-EXPORT_SYMBOL(ioremap_nocache);
-
-void iounmap(volatile void __iomem *addr)
-{
- if (addr > high_memory)
- return vfree((void *) (PAGE_MASK & (unsigned long) addr));
-}
diff --git a/arch/cris/mm/tlb.c b/arch/cris/mm/tlb.c
deleted file mode 100644
index e0dbea62cb81..000000000000
--- a/arch/cris/mm/tlb.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/mm/tlb.c
- *
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/mm_types.h>
-
-#include <asm/tlb.h>
-
-#define D(x)
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The running context is R_MMU_CONTEXT, and each TLB entry contains a
- * page_id that has to match to give a hit. In page_id_map, we keep track
- * of which mm we have assigned to which page_id, so that we know when
- * to invalidate TLB entries.
- *
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match.
- *
- * Notice that we need to make the flushes atomic, otherwise an interrupt
- * handler that uses vmalloced memory might cause a TLB load in the middle
- * of a flush causing.
- */
-
-struct mm_struct *page_id_map[NUM_PAGEID];
-static int map_replace_ptr = 1; /* which page_id_map entry to replace next */
-
-/* the following functions are similar to those used in the PPC port */
-
-static inline void
-alloc_context(struct mm_struct *mm)
-{
- struct mm_struct *old_mm;
-
- D(printk("tlb: alloc context %d (%p)\n", map_replace_ptr, mm));
-
- /* did we replace an mm ? */
-
- old_mm = page_id_map[map_replace_ptr];
-
- if(old_mm) {
- /* throw out any TLB entries belonging to the mm we replace
- * in the map
- */
- flush_tlb_mm(old_mm);
-
- old_mm->context.page_id = NO_CONTEXT;
- }
-
- /* insert it into the page_id_map */
-
- mm->context.page_id = map_replace_ptr;
- page_id_map[map_replace_ptr] = mm;
-
- map_replace_ptr++;
-
- if(map_replace_ptr == INVALID_PAGEID)
- map_replace_ptr = 0; /* wrap around */
-}
-
-/*
- * if needed, get a new MMU context for the mm. otherwise nothing is done.
- */
-
-void
-get_mmu_context(struct mm_struct *mm)
-{
- if(mm->context.page_id == NO_CONTEXT)
- alloc_context(mm);
-}
-
-/* called by __exit_mm to destroy the used MMU context if any before
- * destroying the mm itself. this is only called when the last user of the mm
- * drops it.
- *
- * the only thing we really need to do here is mark the used PID slot
- * as empty.
- */
-
-void
-destroy_context(struct mm_struct *mm)
-{
- if(mm->context.page_id != NO_CONTEXT) {
- D(printk("destroy_context %d (%p)\n", mm->context.page_id, mm));
- flush_tlb_mm(mm); /* TODO this might be redundant ? */
- page_id_map[mm->context.page_id] = NULL;
- }
-}
-
-/* called once during VM initialization, from init.c */
-
-void __init
-tlb_init(void)
-{
- int i;
-
- /* clear the page_id map */
-
- for (i = 1; i < ARRAY_SIZE(page_id_map); i++)
- page_id_map[i] = NULL;
-
- /* invalidate the entire TLB */
-
- flush_tlb_all();
-
- /* the init_mm has context 0 from the boot */
-
- page_id_map[0] = &init_mm;
-}
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
deleted file mode 100644
index af369b05fed5..000000000000
--- a/arch/frv/Kconfig
+++ /dev/null
@@ -1,386 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config FRV
- bool
- default y
- select HAVE_IDE
- select HAVE_ARCH_TRACEHOOK
- select HAVE_PERF_EVENTS
- select HAVE_UID16
- select VIRT_TO_BUS
- select GENERIC_IRQ_SHOW
- select HAVE_DEBUG_BUGVERBOSE
- select ARCH_HAVE_NMI_SAFE_CMPXCHG
- select GENERIC_CPU_DEVICES
- select ARCH_HAS_DEVMEM_IS_ALLOWED
- select ARCH_WANT_IPC_PARSE_VERSION
- select OLD_SIGSUSPEND3
- select OLD_SIGACTION
- select HAVE_DEBUG_STACKOVERFLOW
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config CPU_BIG_ENDIAN
- def_bool y
-
-config ZONE_DMA
- bool
- default y
-
-config RWSEM_GENERIC_SPINLOCK
- bool
- default y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
-
-config GENERIC_HWEIGHT
- bool
- default y
-
-config GENERIC_CALIBRATE_DELAY
- bool
- default n
-
-config TIME_LOW_RES
- bool
- default y
-
-config QUICKLIST
- bool
- default y
-
-config ARCH_HAS_ILOG2_U32
- bool
- default y
-
-config ARCH_HAS_ILOG2_U64
- bool
- default y
-
-config HZ
- int
- default 1000
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-
-menu "Fujitsu FR-V system setup"
-
-config MMU
- bool "MMU support"
- help
- This options switches on and off support for the FR-V MMU
- (effectively switching between vmlinux and uClinux). Not all FR-V
- CPUs support this. Currently only the FR451 has a sufficiently
- featured MMU.
-
-config FRV_OUTOFLINE_ATOMIC_OPS
- bool "Out-of-line the FRV atomic operations"
- default n
- help
- Setting this option causes the FR-V atomic operations to be mostly
- implemented out-of-line.
-
- See Documentation/frv/atomic-ops.txt for more information.
-
-config HIGHMEM
- bool "High memory support"
- depends on MMU
- default y
- help
- If you wish to use more than 256MB of memory with your MMU based
- system, you will need to select this option. The kernel can only see
- the memory between 0xC0000000 and 0xD0000000 directly... everything
- else must be kmapped.
-
- The arch is, however, capable of supporting up to 3GB of SDRAM.
-
-config HIGHPTE
- bool "Allocate page tables in highmem"
- depends on HIGHMEM
- default y
- help
- The VM uses one page of memory for each page table. For systems
- with a lot of RAM, this can be wasteful of precious low memory.
- Setting this option will put user-space page tables in high memory.
-
-source "mm/Kconfig"
-
-choice
- prompt "uClinux kernel load address"
- depends on !MMU
- default UCPAGE_OFFSET_C0000000
- help
- This option sets the base address for the uClinux kernel. The kernel
- will rearrange the SDRAM layout to start at this address, and move
- itself to start there. It must be greater than 0, and it must be
- sufficiently less than 0xE0000000 that the SDRAM does not intersect
- the I/O region.
-
- The base address must also be aligned such that the SDRAM controller
- can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
-
-config UCPAGE_OFFSET_20000000
- bool "0x20000000"
-
-config UCPAGE_OFFSET_40000000
- bool "0x40000000"
-
-config UCPAGE_OFFSET_60000000
- bool "0x60000000"
-
-config UCPAGE_OFFSET_80000000
- bool "0x80000000"
-
-config UCPAGE_OFFSET_A0000000
- bool "0xA0000000"
-
-config UCPAGE_OFFSET_C0000000
- bool "0xC0000000 (Recommended)"
-
-endchoice
-
-config PAGE_OFFSET
- hex
- default 0x20000000 if UCPAGE_OFFSET_20000000
- default 0x40000000 if UCPAGE_OFFSET_40000000
- default 0x60000000 if UCPAGE_OFFSET_60000000
- default 0x80000000 if UCPAGE_OFFSET_80000000
- default 0xA0000000 if UCPAGE_OFFSET_A0000000
- default 0xC0000000
-
-config PROTECT_KERNEL
- bool "Protect core kernel against userspace"
- depends on !MMU
- default y
- help
- Selecting this option causes the uClinux kernel to change the
- permittivity of DAMPR register covering the core kernel image to
- prevent userspace accessing the underlying memory directly.
-
-choice
- prompt "CPU Caching mode"
- default FRV_DEFL_CACHE_WBACK
- help
- This option determines the default caching mode for the kernel.
-
- Write-Back caching mode involves the all reads and writes causing
- the affected cacheline to be read into the cache first before being
- operated upon. Memory is not then updated by a write until the cache
- is filled and a cacheline needs to be displaced from the cache to
- make room. Only at that point is it written back.
-
- Write-Behind caching is similar to Write-Back caching, except that a
- write won't fetch a cacheline into the cache if there isn't already
- one there; it will write directly to memory instead.
-
- Write-Through caching only fetches cachelines from memory on a
- read. Writes always get written directly to memory. If the affected
- cacheline is also in cache, it will be updated too.
-
- The final option is to turn of caching entirely.
-
- Note that not all CPUs support Write-Behind caching. If the CPU on
- which the kernel is running doesn't, it'll fall back to Write-Back
- caching.
-
-config FRV_DEFL_CACHE_WBACK
- bool "Write-Back"
-
-config FRV_DEFL_CACHE_WBEHIND
- bool "Write-Behind"
-
-config FRV_DEFL_CACHE_WTHRU
- bool "Write-Through"
-
-config FRV_DEFL_CACHE_DISABLED
- bool "Disabled"
-
-endchoice
-
-menu "CPU core support"
-
-config CPU_FR401
- bool "Include FR401 core support"
- depends on !MMU
- default y
- help
- This enables support for the FR401, FR401A and FR403 CPUs
-
-config CPU_FR405
- bool "Include FR405 core support"
- depends on !MMU
- default y
- help
- This enables support for the FR405 CPU
-
-config CPU_FR451
- bool "Include FR451 core support"
- default y
- help
- This enables support for the FR451 CPU
-
-config CPU_FR451_COMPILE
- bool "Specifically compile for FR451 core"
- depends on CPU_FR451 && !CPU_FR401 && !CPU_FR405 && !CPU_FR551
- default y
- help
- This causes appropriate flags to be passed to the compiler to
- optimise for the FR451 CPU
-
-config CPU_FR551
- bool "Include FR551 core support"
- depends on !MMU
- default y
- help
- This enables support for the FR555 CPU
-
-config CPU_FR551_COMPILE
- bool "Specifically compile for FR551 core"
- depends on CPU_FR551 && !CPU_FR401 && !CPU_FR405 && !CPU_FR451
- default y
- help
- This causes appropriate flags to be passed to the compiler to
- optimise for the FR555 CPU
-
-config FRV_L1_CACHE_SHIFT
- int
- default "5" if CPU_FR401 || CPU_FR405 || CPU_FR451
- default "6" if CPU_FR551
-
-endmenu
-
-choice
- prompt "System support"
- default MB93091_VDK
-
-config MB93091_VDK
- bool "MB93091 CPU board with or without motherboard"
-
-config MB93093_PDK
- bool "MB93093 PDK unit"
-
-endchoice
-
-if MB93091_VDK
-choice
- prompt "Motherboard support"
- default MB93090_MB00
-
-config MB93090_MB00
- bool "Use the MB93090-MB00 motherboard"
- help
- Select this option if the MB93091 CPU board is going to be used with
- a MB93090-MB00 VDK motherboard
-
-config MB93091_NO_MB
- bool "Use standalone"
- help
- Select this option if the MB93091 CPU board is going to be used
- without a motherboard
-
-endchoice
-endif
-
-config FUJITSU_MB93493
- bool "MB93493 Multimedia chip"
- help
- Select this option if the MB93493 multimedia chip is going to be
- used.
-
-choice
- prompt "GP-Relative data support"
- default GPREL_DATA_8
- help
- This option controls what data, if any, should be placed in the GP
- relative data sections. Using this means that the compiler can
- generate accesses to the data using GR16-relative addressing which
- is faster than absolute instructions and saves space (2 instructions
- per access).
-
- However, the GPREL region is limited in size because the immediate
- value used in the load and store instructions is limited to a 12-bit
- signed number.
-
- So if the linker starts complaining that accesses to GPREL data are
- out of range, try changing this option from the default.
-
- Note that modules will always be compiled with this feature disabled
- as the module data will not be in range of the GP base address.
-
-config GPREL_DATA_8
- bool "Put data objects of up to 8 bytes into GP-REL"
-
-config GPREL_DATA_4
- bool "Put data objects of up to 4 bytes into GP-REL"
-
-config GPREL_DATA_NONE
- bool "Don't use GP-REL"
-
-endchoice
-
-config FRV_ONCPU_SERIAL
- bool "Use on-CPU serial ports"
- select SERIAL_8250
- default y
-
-config PCI
- bool "Use PCI"
- depends on MB93090_MB00
- default y
- select GENERIC_PCI_IOMAP
- help
- Some FR-V systems (such as the MB93090-MB00 VDK) have PCI
- onboard. If you have one of these boards and you wish to use the PCI
- facilities, say Y here.
-
-config RESERVE_DMA_COHERENT
- bool "Reserve DMA coherent memory"
- depends on PCI && !MMU
- default y
- help
- Many PCI drivers require access to uncached memory for DMA device
- communications (such as is done with some Ethernet buffer rings). If
- a fully featured MMU is available, this can be done through page
- table settings, but if not, a region has to be set aside and marked
- with a special DAMPR register.
-
- Setting this option causes uClinux to set aside a portion of the
- available memory for use in this manner. The memory will then be
- unavailable for normal kernel use.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-menu "Power management options"
-
-config ARCH_SUSPEND_POSSIBLE
- def_bool y
-
-source kernel/power/Kconfig
-endmenu
-
-endmenu
-
-
-menu "Executable formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/frv/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/frv/Kconfig.debug b/arch/frv/Kconfig.debug
deleted file mode 100644
index ecab6d8a79ed..000000000000
--- a/arch/frv/Kconfig.debug
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config GDBSTUB
- bool "Remote GDB kernel debugging"
- depends on DEBUG_KERNEL
- select DEBUG_INFO
- select FRAME_POINTER
- help
- If you say Y here, it will be possible to remotely debug the kernel
- using gdb. This enlarges your kernel ELF image disk size by several
- megabytes and requires a machine with more than 16 MB, better 32 MB
- RAM to avoid excessive linking time. This is only useful for kernel
- hackers. If unsure, say N.
-
-choice
- prompt "GDB stub port"
- default GDBSTUB_UART1
- depends on GDBSTUB
- help
- Select the on-CPU port used for GDB-stub
-
-config GDBSTUB_UART0
- bool "/dev/ttyS0"
-
-config GDBSTUB_UART1
- bool "/dev/ttyS1"
-
-endchoice
-
-config GDBSTUB_IMMEDIATE
- bool "Break into GDB stub immediately"
- depends on GDBSTUB
- help
- If you say Y here, GDB stub will break into the program as soon as
- possible, leaving the program counter at the beginning of
- start_kernel() in init/main.c.
-
-config GDB_CONSOLE
- bool "Console output to GDB"
- depends on GDBSTUB
- help
- If you are using GDB for remote debugging over a serial port and
- would like kernel messages to be formatted into GDB $O packets so
- that GDB prints them as program output, say 'Y'.
-
-endmenu
diff --git a/arch/frv/Makefile b/arch/frv/Makefile
deleted file mode 100644
index 2a8fb730d1ca..000000000000
--- a/arch/frv/Makefile
+++ /dev/null
@@ -1,90 +0,0 @@
-#
-# frv/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies. Remember to do have actions
-# for "archclean" and "archdep" for cleaning up and making dependencies for
-# this architecture
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (c) 2003, 2004 Red Hat Inc.
-# - Written by David Howells <dhowells@redhat.com>
-# - Derived from arch/m68knommu/Makefile,
-# Copyright (c) 1999,2001 D. Jeff Dionne <jeff@lineo.ca>,
-# Rt-Control Inc. / Lineo, Inc.
-#
-# Copyright (C) 1998,1999 D. Jeff Dionne <jeff@uclinux.org>,
-# Kenneth Albanowski <kjahds@kjahds.com>,
-#
-# Based on arch/m68k/Makefile:
-# Copyright (C) 1994 by Hamish Macdonald
-#
-
-ifdef CONFIG_MMU
-UTS_SYSNAME = -DUTS_SYSNAME=\"Linux\"
-else
-UTS_SYSNAME = -DUTS_SYSNAME=\"uClinux\"
-endif
-
-KBUILD_AFLAGS_MODULE += -G0 -mlong-calls
-KBUILD_CFLAGS_MODULE += -G0 -mlong-calls
-
-ifdef CONFIG_GPREL_DATA_8
-KBUILD_CFLAGS += -G8
-else
-ifdef CONFIG_GPREL_DATA_4
-KBUILD_CFLAGS += -G4
-else
-ifdef CONFIG_GPREL_DATA_NONE
-KBUILD_CFLAGS += -G0
-endif
-endif
-endif
-
-#LDFLAGS_vmlinux := -Map linkmap.txt
-
-ifdef CONFIG_GC_SECTIONS
-KBUILD_CFLAGS += -ffunction-sections -fdata-sections
-endif
-
-ifndef CONFIG_FRAME_POINTER
-KBUILD_CFLAGS += -mno-linked-fp
-endif
-
-ifdef CONFIG_CPU_FR451_COMPILE
-KBUILD_CFLAGS += -mcpu=fr450
-KBUILD_AFLAGS += -mcpu=fr450
-else
-ifdef CONFIG_CPU_FR551_COMPILE
-KBUILD_CFLAGS += -mcpu=fr550
-KBUILD_AFLAGS += -mcpu=fr550
-else
-KBUILD_CFLAGS += -mcpu=fr400
-KBUILD_AFLAGS += -mcpu=fr400
-endif
-endif
-
-# pretend the kernel is going to run on an FR400 with no media-fp unit
-# - reserve CC3 for use with atomic ops
-# - all the extra registers are dealt with only at context switch time
-KBUILD_CFLAGS += -mno-fdpic -mgpr-32 -msoft-float -mno-media
-KBUILD_CFLAGS += -ffixed-fcc3 -ffixed-cc3 -ffixed-gr15 -ffixed-icc2
-KBUILD_AFLAGS += -mno-fdpic
-
-head-y := arch/frv/kernel/head.o
-
-core-y += arch/frv/kernel/ arch/frv/mm/
-libs-y += arch/frv/lib/
-
-core-$(CONFIG_MB93090_MB00) += arch/frv/mb93090-mb00/
-
-all: Image
-
-Image: vmlinux
- $(Q)$(MAKE) $(build)=arch/frv/boot $@
-
-archclean:
- $(Q)$(MAKE) $(clean)=arch/frv/boot
diff --git a/arch/frv/boot/Makefile b/arch/frv/boot/Makefile
deleted file mode 100644
index 636d5bbcd53f..000000000000
--- a/arch/frv/boot/Makefile
+++ /dev/null
@@ -1,76 +0,0 @@
-#
-# arch/arm/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995-2000 Russell King
-#
-
-targets := Image zImage bootpImage
-
-SYSTEM =$(LINUX)
-
-ZTEXTADDR = 0x02080000
-PARAMS_PHYS = 0x0207c000
-INITRD_PHYS = 0x02180000
-INITRD_VIRT = 0x02180000
-
-OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment
-
-#
-# If you don't define ZRELADDR above,
-# then it defaults to ZTEXTADDR
-#
-ifeq ($(ZRELADDR),)
-ZRELADDR = $(ZTEXTADDR)
-endif
-
-export SYSTEM ZTEXTADDR ZBSSADDR ZRELADDR INITRD_PHYS INITRD_VIRT PARAMS_PHYS
-
-Image: $(obj)/Image
-
-targets: $(obj)/Image
-
-$(obj)/Image: vmlinux FORCE
- $(OBJCOPY) $(OBJCOPYFLAGS) -S vmlinux $@
-
-#$(obj)/Image: $(CONFIGURE) $(SYSTEM)
-# $(OBJCOPY) $(OBJCOPYFLAGS) -g -S $(SYSTEM) $@
-
-bzImage: zImage
-
-zImage: $(CONFIGURE) compressed/$(LINUX)
- $(OBJCOPY) $(OBJCOPYFLAGS) -S compressed/$(LINUX) $@
-
-bootpImage: bootp/bootp
- $(OBJCOPY) $(OBJCOPYFLAGS) -S bootp/bootp $@
-
-compressed/$(LINUX): $(LINUX) dep
- @$(MAKE) -C compressed $(LINUX)
-
-bootp/bootp: zImage initrd
- @$(MAKE) -C bootp bootp
-
-initrd:
- @test "$(INITRD_VIRT)" != "" || (echo This architecture does not support INITRD; exit -1)
- @test "$(INITRD)" != "" || (echo You must specify INITRD; exit -1)
-
-#
-# installation
-#
-install: $(CONFIGURE) Image
- sh ./install.sh $(KERNELRELEASE) Image System.map "$(INSTALL_PATH)"
-
-zinstall: $(CONFIGURE) zImage
- sh ./install.sh $(KERNELRELEASE) zImage System.map "$(INSTALL_PATH)"
-
-#
-# miscellany
-#
-mrproper clean:
-# @$(MAKE) -C compressed clean
-# @$(MAKE) -C bootp clean
-
-dep:
diff --git a/arch/frv/defconfig b/arch/frv/defconfig
deleted file mode 100644
index b1b792610fdf..000000000000
--- a/arch/frv/defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MMU=y
-CONFIG_FRV_OUTOFLINE_ATOMIC_OPS=y
-CONFIG_FRV_DEFL_CACHE_WTHRU=y
-CONFIG_GPREL_DATA_4=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_NET_PCI=y
-CONFIG_NE2K_PCI=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_STACKOVERFLOW=y
diff --git a/arch/frv/include/asm/Kbuild b/arch/frv/include/asm/Kbuild
deleted file mode 100644
index b16b9c48ea09..000000000000
--- a/arch/frv/include/asm/Kbuild
+++ /dev/null
@@ -1,12 +0,0 @@
-
-generic-y += device.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += irq_work.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += preempt.h
-generic-y += trace_clock.h
-generic-y += word-at-a-time.h
-generic-y += kprobes.h
diff --git a/arch/frv/include/asm/asm-offsets.h b/arch/frv/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/frv/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h
deleted file mode 100644
index e93c9494503a..000000000000
--- a/arch/frv/include/asm/atomic.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* atomic.h: atomic operation emulation for FR-V
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_ATOMIC_H
-#define _ASM_ATOMIC_H
-
-#include <linux/types.h>
-#include <asm/cmpxchg.h>
-#include <asm/barrier.h>
-
-#ifdef CONFIG_SMP
-#error not SMP safe
-#endif
-
-#include <asm/atomic_defs.h>
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- *
- * We do not have SMP systems, so we don't have to deal with that.
- */
-
-#define ATOMIC_INIT(i) { (i) }
-#define atomic_read(v) READ_ONCE((v)->counter)
-#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
-
-static inline int atomic_inc_return(atomic_t *v)
-{
- return __atomic_add_return(1, &v->counter);
-}
-
-static inline int atomic_dec_return(atomic_t *v)
-{
- return __atomic_sub_return(1, &v->counter);
-}
-
-static inline int atomic_add_return(int i, atomic_t *v)
-{
- return __atomic_add_return(i, &v->counter);
-}
-
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
- return __atomic_sub_return(i, &v->counter);
-}
-
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
- return atomic_add_return(i, v) < 0;
-}
-
-static inline void atomic_inc(atomic_t *v)
-{
- atomic_inc_return(v);
-}
-
-static inline void atomic_dec(atomic_t *v)
-{
- atomic_dec_return(v);
-}
-
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
-
-/*
- * 64-bit atomic ops
- */
-typedef struct {
- long long counter;
-} atomic64_t;
-
-#define ATOMIC64_INIT(i) { (i) }
-
-static inline long long atomic64_read(const atomic64_t *v)
-{
- long long counter;
-
- asm("ldd%I1 %M1,%0"
- : "=e"(counter)
- : "m"(v->counter));
-
- return counter;
-}
-
-static inline void atomic64_set(atomic64_t *v, long long i)
-{
- asm volatile("std%I0 %1,%M0"
- : "=m"(v->counter)
- : "e"(i));
-}
-
-static inline long long atomic64_inc_return(atomic64_t *v)
-{
- return __atomic64_add_return(1, &v->counter);
-}
-
-static inline long long atomic64_dec_return(atomic64_t *v)
-{
- return __atomic64_sub_return(1, &v->counter);
-}
-
-static inline long long atomic64_add_return(long long i, atomic64_t *v)
-{
- return __atomic64_add_return(i, &v->counter);
-}
-
-static inline long long atomic64_sub_return(long long i, atomic64_t *v)
-{
- return __atomic64_sub_return(i, &v->counter);
-}
-
-static inline long long atomic64_add_negative(long long i, atomic64_t *v)
-{
- return atomic64_add_return(i, v) < 0;
-}
-
-static inline void atomic64_inc(atomic64_t *v)
-{
- atomic64_inc_return(v);
-}
-
-static inline void atomic64_dec(atomic64_t *v)
-{
- atomic64_dec_return(v);
-}
-
-#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
-#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
-#define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0)
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new))
-#define atomic_xchg(v, new) (xchg(&(v)->counter, new))
-#define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter))
-#define atomic64_xchg(v, new) (__xchg_64(new, &(v)->counter))
-
-static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int c, old;
- c = atomic_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c;
-}
-
-static inline int atomic64_add_unless(atomic64_t *v, long long i, long long u)
-{
- long long c, old;
-
- c = atomic64_read(v);
- for (;;) {
- if (unlikely(c == u))
- break;
- old = atomic64_cmpxchg(v, c, c + i);
- if (likely(old == c))
- break;
- c = old;
- }
- return c != u;
-}
-
-static inline long long atomic64_dec_if_positive(atomic64_t *v)
-{
- long long c, old, dec;
-
- c = atomic64_read(v);
- for (;;) {
- dec = c - 1;
- if (unlikely(dec < 0))
- break;
- old = atomic64_cmpxchg((v), c, dec);
- if (likely(old == c))
- break;
- c = old;
- }
- return dec;
-}
-
-#define ATOMIC_OP(op) \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- return __atomic32_fetch_##op(i, &v->counter); \
-} \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- (void)__atomic32_fetch_##op(i, &v->counter); \
-} \
- \
-static inline long long atomic64_fetch_##op(long long i, atomic64_t *v) \
-{ \
- return __atomic64_fetch_##op(i, &v->counter); \
-} \
-static inline void atomic64_##op(long long i, atomic64_t *v) \
-{ \
- (void)__atomic64_fetch_##op(i, &v->counter); \
-}
-
-ATOMIC_OP(or)
-ATOMIC_OP(and)
-ATOMIC_OP(xor)
-ATOMIC_OP(add)
-ATOMIC_OP(sub)
-
-#undef ATOMIC_OP
-
-#endif /* _ASM_ATOMIC_H */
diff --git a/arch/frv/include/asm/atomic_defs.h b/arch/frv/include/asm/atomic_defs.h
deleted file mode 100644
index ce3b8a4efc12..000000000000
--- a/arch/frv/include/asm/atomic_defs.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#include <asm/spr-regs.h>
-
-#ifdef __ATOMIC_LIB__
-
-#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define ATOMIC_QUALS
-#define ATOMIC_EXPORT(x) EXPORT_SYMBOL(x)
-
-#else /* !OUTOFLINE && LIB */
-
-#define ATOMIC_OP_RETURN(op)
-#define ATOMIC_FETCH_OP(op)
-
-#endif /* OUTOFLINE */
-
-#else /* !__ATOMIC_LIB__ */
-
-#define ATOMIC_EXPORT(x)
-
-#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define ATOMIC_OP_RETURN(op) \
-extern int __atomic_##op##_return(int i, int *v); \
-extern long long __atomic64_##op##_return(long long i, long long *v);
-
-#define ATOMIC_FETCH_OP(op) \
-extern int __atomic32_fetch_##op(int i, int *v); \
-extern long long __atomic64_fetch_##op(long long i, long long *v);
-
-#else /* !OUTOFLINE && !LIB */
-
-#define ATOMIC_QUALS static inline
-
-#endif /* OUTOFLINE */
-#endif /* __ATOMIC_LIB__ */
-
-
-/*
- * Note on the 64 bit inline asm variants...
- *
- * CSTD is a conditional instruction and needs a constrained memory reference.
- * Normally 'U' provides the correct constraints for conditional instructions
- * and this is used for the 32 bit version, however 'U' does not appear to work
- * for 64 bit values (gcc-4.9)
- *
- * The exact constraint is that conditional instructions cannot deal with an
- * immediate displacement in the memory reference, so what we do is we read the
- * address through a volatile cast into a local variable in order to insure we
- * _have_ to compute the correct address without displacement. This allows us
- * to use the regular 'm' for the memory address.
- *
- * Furthermore, the %Ln operand, which prints the low word register (r+1),
- * really only works for registers, this means we cannot allow immediate values
- * for the 64 bit versions -- like we do for the 32 bit ones.
- *
- */
-
-#ifndef ATOMIC_OP_RETURN
-#define ATOMIC_OP_RETURN(op) \
-ATOMIC_QUALS int __atomic_##op##_return(int i, int *v) \
-{ \
- int val; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ld.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op"%I2 %1,%2,%1 \n" \
- " cst.p %1,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+U"(*v), "=&r"(val) \
- : "NPr"(i) \
- : "memory", "cc7", "cc3", "icc3" \
- ); \
- \
- return val; \
-} \
-ATOMIC_EXPORT(__atomic_##op##_return); \
- \
-ATOMIC_QUALS long long __atomic64_##op##_return(long long i, long long *v) \
-{ \
- long long *__v = READ_ONCE(v); \
- long long val; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ldd.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op"cc %L1,%L2,%L1,icc0 \n" \
- " "#op"x %1,%2,%1,icc0 \n" \
- " cstd.p %1,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+m"(*__v), "=&e"(val) \
- : "e"(i) \
- : "memory", "cc7", "cc3", "icc0", "icc3" \
- ); \
- \
- return val; \
-} \
-ATOMIC_EXPORT(__atomic64_##op##_return);
-#endif
-
-#ifndef ATOMIC_FETCH_OP
-#define ATOMIC_FETCH_OP(op) \
-ATOMIC_QUALS int __atomic32_fetch_##op(int i, int *v) \
-{ \
- int old, tmp; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ld.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op"%I3 %1,%3,%2 \n" \
- " cst.p %2,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+U"(*v), "=&r"(old), "=r"(tmp) \
- : "NPr"(i) \
- : "memory", "cc7", "cc3", "icc3" \
- ); \
- \
- return old; \
-} \
-ATOMIC_EXPORT(__atomic32_fetch_##op); \
- \
-ATOMIC_QUALS long long __atomic64_fetch_##op(long long i, long long *v) \
-{ \
- long long *__v = READ_ONCE(v); \
- long long old, tmp; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ldd.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op" %L1,%L3,%L2 \n" \
- " "#op" %1,%3,%2 \n" \
- " cstd.p %2,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+m"(*__v), "=&e"(old), "=e"(tmp) \
- : "e"(i) \
- : "memory", "cc7", "cc3", "icc3" \
- ); \
- \
- return old; \
-} \
-ATOMIC_EXPORT(__atomic64_fetch_##op);
-#endif
-
-ATOMIC_FETCH_OP(or)
-ATOMIC_FETCH_OP(and)
-ATOMIC_FETCH_OP(xor)
-ATOMIC_FETCH_OP(add)
-ATOMIC_FETCH_OP(sub)
-
-ATOMIC_OP_RETURN(add)
-ATOMIC_OP_RETURN(sub)
-
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_QUALS
-#undef ATOMIC_EXPORT
diff --git a/arch/frv/include/asm/ax88796.h b/arch/frv/include/asm/ax88796.h
deleted file mode 100644
index 637e980393c5..000000000000
--- a/arch/frv/include/asm/ax88796.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* ax88796.h: access points to the driver for the AX88796 NE2000 clone
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_AX88796_H
-#define _ASM_AX88796_H
-
-#include <asm/mb-regs.h>
-
-#define AX88796_IOADDR (__region_CS1 + 0x200)
-#define AX88796_IRQ IRQ_CPU_EXTERNAL7
-#define AX88796_FULL_DUPLEX 0 /* force full duplex */
-#define AX88796_BUS_INFO "CS1#+0x200" /* bus info for ethtool */
-
-#endif /* _ASM_AX88796_H */
diff --git a/arch/frv/include/asm/barrier.h b/arch/frv/include/asm/barrier.h
deleted file mode 100644
index abbef470154c..000000000000
--- a/arch/frv/include/asm/barrier.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* FR-V CPU memory barrier definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_BARRIER_H
-#define _ASM_BARRIER_H
-
-#define nop() asm volatile ("nop"::)
-
-#define mb() asm volatile ("membar" : : :"memory")
-#define rmb() asm volatile ("membar" : : :"memory")
-#define wmb() asm volatile ("membar" : : :"memory")
-
-#include <asm-generic/barrier.h>
-
-#endif /* _ASM_BARRIER_H */
diff --git a/arch/frv/include/asm/bitops.h b/arch/frv/include/asm/bitops.h
deleted file mode 100644
index 0df8e95e3715..000000000000
--- a/arch/frv/include/asm/bitops.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/* bitops.h: bit operations for the Fujitsu FR-V CPUs
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_BITOPS_H
-#define _ASM_BITOPS_H
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/ffz.h>
-
-#include <asm/atomic.h>
-
-static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *ptr = (void *)addr;
- unsigned int mask = 1UL << (nr & 31);
- ptr += nr >> 5;
- return (__atomic32_fetch_and(~mask, ptr) & mask) != 0;
-}
-
-static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *ptr = (void *)addr;
- unsigned int mask = 1UL << (nr & 31);
- ptr += nr >> 5;
- return (__atomic32_fetch_or(mask, ptr) & mask) != 0;
-}
-
-static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *ptr = (void *)addr;
- unsigned int mask = 1UL << (nr & 31);
- ptr += nr >> 5;
- return (__atomic32_fetch_xor(mask, ptr) & mask) != 0;
-}
-
-static inline void clear_bit(unsigned long nr, volatile void *addr)
-{
- test_and_clear_bit(nr, addr);
-}
-
-static inline void set_bit(unsigned long nr, volatile void *addr)
-{
- test_and_set_bit(nr, addr);
-}
-
-static inline void change_bit(unsigned long nr, volatile void *addr)
-{
- test_and_change_bit(nr, addr);
-}
-
-static inline void __clear_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- *a &= ~mask;
-}
-
-static inline void __set_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- *a |= mask;
-}
-
-static inline void __change_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- *a ^= mask;
-}
-
-static inline int __test_and_clear_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask, retval;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- retval = (mask & *a) != 0;
- *a &= ~mask;
- return retval;
-}
-
-static inline int __test_and_set_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask, retval;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- retval = (mask & *a) != 0;
- *a |= mask;
- return retval;
-}
-
-static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask, retval;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- retval = (mask & *a) != 0;
- *a ^= mask;
- return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static inline int
-__constant_test_bit(unsigned long nr, const volatile void *addr)
-{
- return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
-}
-
-static inline int __test_bit(unsigned long nr, const volatile void *addr)
-{
- int * a = (int *) addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- return ((mask & *a) != 0);
-}
-
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#include <asm-generic/bitops/find.h>
-
-/**
- * fls - find last bit set
- * @x: the word to search
- *
- * This is defined the same way as ffs:
- * - return 32..1 to indicate bit 31..0 most significant bit set
- * - return 0 to indicate no bits set
- */
-#define fls(x) \
-({ \
- int bit; \
- \
- asm(" subcc %1,gr0,gr0,icc0 \n" \
- " ckne icc0,cc4 \n" \
- " cscan.p %1,gr0,%0 ,cc4,#1 \n" \
- " csub %0,%0,%0 ,cc4,#0 \n" \
- " csub %2,%0,%0 ,cc4,#1 \n" \
- : "=&r"(bit) \
- : "r"(x), "r"(32) \
- : "icc0", "cc4" \
- ); \
- \
- bit; \
-})
-
-/**
- * fls64 - find last bit set in a 64-bit value
- * @n: the value to search
- *
- * This is defined the same way as ffs:
- * - return 64..1 to indicate bit 63..0 most significant bit set
- * - return 0 to indicate no bits set
- */
-static inline __attribute__((const))
-int fls64(u64 n)
-{
- union {
- u64 ll;
- struct { u32 h, l; };
- } _;
- int bit, x, y;
-
- _.ll = n;
-
- asm(" subcc.p %3,gr0,gr0,icc0 \n"
- " subcc %4,gr0,gr0,icc1 \n"
- " ckne icc0,cc4 \n"
- " ckne icc1,cc5 \n"
- " norcr cc4,cc5,cc6 \n"
- " csub.p %0,%0,%0 ,cc6,1 \n"
- " orcr cc5,cc4,cc4 \n"
- " andcr cc4,cc5,cc4 \n"
- " cscan.p %3,gr0,%0 ,cc4,0 \n"
- " setlos #64,%1 \n"
- " cscan.p %4,gr0,%0 ,cc4,1 \n"
- " setlos #32,%2 \n"
- " csub.p %1,%0,%0 ,cc4,0 \n"
- " csub %2,%0,%0 ,cc4,1 \n"
- : "=&r"(bit), "=r"(x), "=r"(y)
- : "0r"(_.h), "r"(_.l)
- : "icc0", "icc1", "cc4", "cc5", "cc6"
- );
- return bit;
-
-}
-
-/**
- * ffs - find first bit set
- * @x: the word to search
- *
- * - return 32..1 to indicate bit 31..0 most least significant bit set
- * - return 0 to indicate no bits set
- */
-static inline __attribute__((const))
-int ffs(int x)
-{
- /* Note: (x & -x) gives us a mask that is the least significant
- * (rightmost) 1-bit of the value in x.
- */
- return fls(x & -x);
-}
-
-/**
- * __ffs - find first bit set
- * @x: the word to search
- *
- * - return 31..0 to indicate bit 31..0 most least significant bit set
- * - if no bits are set in x, the result is undefined
- */
-static inline __attribute__((const))
-int __ffs(unsigned long x)
-{
- int bit;
- asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
- return 31 - bit;
-}
-
-/**
- * __fls - find last (most-significant) set bit in a long word
- * @word: the word to search
- *
- * Undefined if no set bit exists, so code should check against 0 first.
- */
-static inline unsigned long __fls(unsigned long word)
-{
- unsigned long bit;
- asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word));
- return bit;
-}
-
-/*
- * special slimline version of fls() for calculating ilog2_u32()
- * - note: no protection against n == 0
- */
-#define ARCH_HAS_ILOG2_U32
-static inline __attribute__((const))
-int __ilog2_u32(u32 n)
-{
- int bit;
- asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
- return 31 - bit;
-}
-
-/*
- * special slimline version of fls64() for calculating ilog2_u64()
- * - note: no protection against n == 0
- */
-#define ARCH_HAS_ILOG2_U64
-static inline __attribute__((const))
-int __ilog2_u64(u64 n)
-{
- union {
- u64 ll;
- struct { u32 h, l; };
- } _;
- int bit, x, y;
-
- _.ll = n;
-
- asm(" subcc %3,gr0,gr0,icc0 \n"
- " ckeq icc0,cc4 \n"
- " cscan.p %3,gr0,%0 ,cc4,0 \n"
- " setlos #63,%1 \n"
- " cscan.p %4,gr0,%0 ,cc4,1 \n"
- " setlos #31,%2 \n"
- " csub.p %1,%0,%0 ,cc4,0 \n"
- " csub %2,%0,%0 ,cc4,1 \n"
- : "=&r"(bit), "=r"(x), "=r"(y)
- : "0r"(_.h), "r"(_.l)
- : "icc0", "cc4"
- );
- return bit;
-}
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/le.h>
-
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_BITOPS_H */
diff --git a/arch/frv/include/asm/bug.h b/arch/frv/include/asm/bug.h
deleted file mode 100644
index dd01bcf42ee6..000000000000
--- a/arch/frv/include/asm/bug.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* bug.h: FRV bug trapping
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_BUG_H
-#define _ASM_BUG_H
-
-#include <linux/linkage.h>
-
-#ifdef CONFIG_BUG
-/*
- * Tell the user there is some problem.
- */
-extern asmlinkage void __debug_bug_trap(int signr);
-
-#ifdef CONFIG_NO_KERNEL_MSG
-#define _debug_bug_printk()
-#else
-extern void __debug_bug_printk(const char *file, unsigned line);
-#define _debug_bug_printk() __debug_bug_printk(__FILE__, __LINE__)
-#endif
-
-#define _debug_bug_trap(signr) \
-do { \
- __debug_bug_trap(signr); \
- asm volatile("nop"); \
-} while(1)
-
-#define HAVE_ARCH_BUG
-#define BUG() \
-do { \
- _debug_bug_printk(); \
- _debug_bug_trap(6 /*SIGABRT*/); \
-} while (0)
-
-#ifdef CONFIG_GDBSTUB
-#define HAVE_ARCH_KGDB_RAISE
-#define kgdb_raise(signr) do { _debug_bug_trap(signr); } while(0)
-
-#define HAVE_ARCH_KGDB_BAD_PAGE
-#define kgdb_bad_page(page) do { kgdb_raise(SIGABRT); } while(0)
-#endif
-
-#endif /* CONFIG_BUG */
-
-#include <asm-generic/bug.h>
-
-extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
-
-#endif
diff --git a/arch/frv/include/asm/bugs.h b/arch/frv/include/asm/bugs.h
deleted file mode 100644
index f2382be2b46c..000000000000
--- a/arch/frv/include/asm/bugs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* bugs.h: arch bug checking entry
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-static inline void check_bugs(void)
-{
-}
diff --git a/arch/frv/include/asm/busctl-regs.h b/arch/frv/include/asm/busctl-regs.h
deleted file mode 100644
index bb0ff4816e27..000000000000
--- a/arch/frv/include/asm/busctl-regs.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* busctl-regs.h: FR400-series CPU bus controller registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_BUSCTL_REGS_H
-#define _ASM_BUSCTL_REGS_H
-
-/* bus controller registers */
-#define __get_LGCR() ({ *(volatile unsigned long *)(0xfe000010); })
-#define __get_LMAICR() ({ *(volatile unsigned long *)(0xfe000030); })
-#define __get_LEMBR() ({ *(volatile unsigned long *)(0xfe000040); })
-#define __get_LEMAM() ({ *(volatile unsigned long *)(0xfe000048); })
-#define __get_LCR(R) ({ *(volatile unsigned long *)(0xfe000100 + 8*(R)); })
-#define __get_LSBR(R) ({ *(volatile unsigned long *)(0xfe000c00 + 8*(R)); })
-#define __get_LSAM(R) ({ *(volatile unsigned long *)(0xfe000d00 + 8*(R)); })
-
-#define __set_LGCR(V) do { *(volatile unsigned long *)(0xfe000010) = (V); } while(0)
-#define __set_LMAICR(V) do { *(volatile unsigned long *)(0xfe000030) = (V); } while(0)
-#define __set_LEMBR(V) do { *(volatile unsigned long *)(0xfe000040) = (V); } while(0)
-#define __set_LEMAM(V) do { *(volatile unsigned long *)(0xfe000048) = (V); } while(0)
-#define __set_LCR(R,V) do { *(volatile unsigned long *)(0xfe000100 + 8*(R)) = (V); } while(0)
-#define __set_LSBR(R,V) do { *(volatile unsigned long *)(0xfe000c00 + 8*(R)) = (V); } while(0)
-#define __set_LSAM(R,V) do { *(volatile unsigned long *)(0xfe000d00 + 8*(R)) = (V); } while(0)
-
-/* FR401 SDRAM controller registers */
-#define __get_DBR(R) ({ *(volatile unsigned long *)(0xfe000e00 + 8*(R)); })
-#define __get_DAM(R) ({ *(volatile unsigned long *)(0xfe000f00 + 8*(R)); })
-
-/* FR551 SDRAM controller registers */
-#define __get_DARS(R) ({ *(volatile unsigned long *)(0xfeff0100 + 8*(R)); })
-#define __get_DAMK(R) ({ *(volatile unsigned long *)(0xfeff0110 + 8*(R)); })
-
-
-#endif /* _ASM_BUSCTL_REGS_H */
diff --git a/arch/frv/include/asm/cache.h b/arch/frv/include/asm/cache.h
deleted file mode 100644
index 2797163b8f4f..000000000000
--- a/arch/frv/include/asm/cache.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* cache.h: FRV cache definitions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_CACHE_H
-#define __ASM_CACHE_H
-
-
-/* bytes per L1 cache line */
-#define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT)
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
-#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
-
-#endif
diff --git a/arch/frv/include/asm/cacheflush.h b/arch/frv/include/asm/cacheflush.h
deleted file mode 100644
index edbac54ae015..000000000000
--- a/arch/frv/include/asm/cacheflush.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* cacheflush.h: FRV cache flushing routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CACHEFLUSH_H
-#define _ASM_CACHEFLUSH_H
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-
-/*
- * virtually-indexed cache management (our cache is physically indexed)
- */
-#define flush_cache_all() do {} while(0)
-#define flush_cache_mm(mm) do {} while(0)
-#define flush_cache_dup_mm(mm) do {} while(0)
-#define flush_cache_range(mm, start, end) do {} while(0)
-#define flush_cache_page(vma, vmaddr, pfn) do {} while(0)
-#define flush_cache_vmap(start, end) do {} while(0)
-#define flush_cache_vunmap(start, end) do {} while(0)
-#define flush_dcache_mmap_lock(mapping) do {} while(0)
-#define flush_dcache_mmap_unlock(mapping) do {} while(0)
-
-/*
- * physically-indexed cache management
- * - see arch/frv/lib/cache.S
- */
-extern void frv_dcache_writeback(unsigned long start, unsigned long size);
-extern void frv_cache_invalidate(unsigned long start, unsigned long size);
-extern void frv_icache_invalidate(unsigned long start, unsigned long size);
-extern void frv_cache_wback_inv(unsigned long start, unsigned long size);
-
-static inline void __flush_cache_all(void)
-{
- asm volatile(" dcef @(gr0,gr0),#1 \n"
- " icei @(gr0,gr0),#1 \n"
- " membar \n"
- : : : "memory"
- );
-}
-
-/* dcache/icache coherency... */
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-#ifdef CONFIG_MMU
-extern void flush_dcache_page(struct page *page);
-#else
-static inline void flush_dcache_page(struct page *page)
-{
- unsigned long addr = page_to_phys(page);
- frv_dcache_writeback(addr, addr + PAGE_SIZE);
-}
-#endif
-
-static inline void flush_page_to_ram(struct page *page)
-{
- flush_dcache_page(page);
-}
-
-static inline void flush_icache(void)
-{
- __flush_cache_all();
-}
-
-static inline void flush_icache_range(unsigned long start, unsigned long end)
-{
- frv_cache_wback_inv(start, end);
-}
-
-#ifdef CONFIG_MMU
-extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long start, unsigned long len);
-#else
-static inline void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long start, unsigned long len)
-{
- frv_cache_wback_inv(start, start + len);
-}
-#endif
-
-static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page)
-{
- flush_icache_user_range(vma, page, page_to_phys(page), PAGE_SIZE);
-}
-
-/*
- * permit ptrace to access another process's address space through the icache
- * and the dcache
- */
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { \
- memcpy((dst), (src), (len)); \
- flush_icache_user_range((vma), (page), (vaddr), (len)); \
-} while(0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy((dst), (src), (len))
-
-#endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/frv/include/asm/checksum.h b/arch/frv/include/asm/checksum.h
deleted file mode 100644
index b77388c5901d..000000000000
--- a/arch/frv/include/asm/checksum.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* checksum.h: FRV checksumming
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CHECKSUM_H
-#define _ASM_CHECKSUM_H
-
-#include <linux/in6.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum, int *csum_err);
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- */
-static inline
-__sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- unsigned int tmp, inc, sum = 0;
-
- asm(" addcc gr0,gr0,gr0,icc0\n" /* clear icc0.C */
- " subi %1,#4,%1 \n"
- "0: \n"
- " ldu.p @(%1,%3),%4 \n"
- " subicc %2,#1,%2,icc1 \n"
- " addxcc.p %4,%0,%0,icc0 \n"
- " bhi icc1,#2,0b \n"
-
- /* fold the 33-bit result into 16-bits */
- " addxcc gr0,%0,%0,icc0 \n"
- " srli %0,#16,%1 \n"
- " sethi #0,%0 \n"
- " add %1,%0,%0 \n"
- " srli %0,#16,%1 \n"
- " add %1,%0,%0 \n"
-
- : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (inc), "=&r"(tmp)
- : "0" (sum), "1" (iph), "2" (ihl), "3" (4),
- "m"(*(volatile struct { int _[100]; } *)iph)
- : "icc0", "icc1", "memory"
- );
-
- return (__force __sum16)~sum;
-}
-
-/*
- * Fold a partial checksum
- */
-static inline __sum16 csum_fold(__wsum sum)
-{
- unsigned int tmp;
-
- asm(" srli %0,#16,%1 \n"
- " sethi #0,%0 \n"
- " add %1,%0,%0 \n"
- " srli %0,#16,%1 \n"
- " add %1,%0,%0 \n"
- : "=r"(sum), "=&r"(tmp)
- : "0"(sum)
- );
-
- return (__force __sum16)~sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- asm(" addcc %1,%0,%0,icc0 \n"
- " addxcc %2,%0,%0,icc0 \n"
- " addxcc %3,%0,%0,icc0 \n"
- " addxcc gr0,%0,%0,icc0 \n"
- : "=r" (sum)
- : "r" (daddr), "r" (saddr), "r" (len + proto), "0"(sum)
- : "icc0"
- );
- return sum;
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#define _HAVE_ARCH_IPV6_CSUM
-static inline __sum16
-csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
- __u32 len, __u8 proto, __wsum sum)
-{
- unsigned long tmp, tmp2;
-
- asm(" addcc %2,%0,%0,icc0 \n"
-
- /* add up the source addr */
- " ldi @(%3,0),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%3,4),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
- " ldi @(%3,8),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%3,12),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
-
- /* add up the dest addr */
- " ldi @(%4,0),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%4,4),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
- " ldi @(%4,8),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%4,12),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
-
- /* fold the 33-bit result into 16-bits */
- " addxcc gr0,%0,%0,icc0 \n"
- " srli %0,#16,%1 \n"
- " sethi #0,%0 \n"
- " add %1,%0,%0 \n"
- " srli %0,#16,%1 \n"
- " add %1,%0,%0 \n"
-
- : "=r" (sum), "=&r" (tmp), "=r" (tmp2)
- : "r" (saddr), "r" (daddr), "0" (sum), "2" (len + proto)
- : "icc0"
- );
-
- return (__force __sum16)~sum;
-}
-
-#endif /* _ASM_CHECKSUM_H */
diff --git a/arch/frv/include/asm/cmpxchg.h b/arch/frv/include/asm/cmpxchg.h
deleted file mode 100644
index ad1f11cfa92a..000000000000
--- a/arch/frv/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* xchg and cmpxchg operation emulation for FR-V
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_CMPXCHG_H
-#define _ASM_CMPXCHG_H
-
-#include <linux/types.h>
-
-/*****************************************************************************/
-/*
- * exchange value with memory
- */
-extern uint64_t __xchg_64(uint64_t i, volatile void *v);
-
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define xchg(ptr, x) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig; \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: \
- asm volatile( \
- "swap%I0 %M0,%1" \
- : "+m"(*__xg_ptr), "=r"(__xg_orig) \
- : "1"(x) \
- : "memory" \
- ); \
- break; \
- \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- \
- __xg_orig; \
-})
-
-#else
-
-extern uint32_t __xchg_32(uint32_t i, volatile void *v);
-
-#define xchg(ptr, x) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig; \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- __xg_orig; \
-})
-
-#endif
-
-/*****************************************************************************/
-/*
- * compare and conditionally exchange value with memory
- * - if (*ptr == test) then orig = *ptr; *ptr = test;
- * - if (*ptr != test) then orig = *ptr;
- */
-extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v);
-#define cmpxchg64(p, o, n) __cmpxchg_64((o), (n), (p))
-
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define cmpxchg(ptr, test, new) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig, __xg_tmp; \
- __typeof__(*(ptr)) __xg_test = (test); \
- __typeof__(*(ptr)) __xg_new = (new); \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ld.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " sub%I4cc %1,%4,%2,icc0 \n" \
- " bne icc0,#0,1f \n" \
- " cst.p %3,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- "1: \n" \
- : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
- : "r"(__xg_new), "NPr"(__xg_test) \
- : "memory", "cc7", "cc3", "icc3", "icc0" \
- ); \
- break; \
- \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- \
- __xg_orig; \
-})
-
-#else
-
-extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
-
-#define cmpxchg(ptr, test, new) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig; \
- __typeof__(*(ptr)) __xg_test = (test); \
- __typeof__(*(ptr)) __xg_new = (new); \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: __xg_orig = (__force __typeof__(*ptr)) \
- __cmpxchg_32((__force uint32_t *)__xg_ptr, \
- (__force uint32_t)__xg_test, \
- (__force uint32_t)__xg_new); break; \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- \
- __xg_orig; \
-})
-
-#endif
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
- unsigned long old,
- unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return cmpxchg((unsigned long *)ptr, old, new);
- default:
- return __cmpxchg_local_generic(ptr, old, new, size);
- }
-
- return old;
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif /* _ASM_CMPXCHG_H */
diff --git a/arch/frv/include/asm/cpu-irqs.h b/arch/frv/include/asm/cpu-irqs.h
deleted file mode 100644
index 478f3498fcfe..000000000000
--- a/arch/frv/include/asm/cpu-irqs.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* cpu-irqs.h: on-CPU peripheral irqs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CPU_IRQS_H
-#define _ASM_CPU_IRQS_H
-
-#ifndef __ASSEMBLY__
-
-/* IRQ to level mappings */
-#define IRQ_GDBSTUB_LEVEL 15
-#define IRQ_UART_LEVEL 13
-
-#ifdef CONFIG_GDBSTUB_UART0
-#define IRQ_UART0_LEVEL IRQ_GDBSTUB_LEVEL
-#else
-#define IRQ_UART0_LEVEL IRQ_UART_LEVEL
-#endif
-
-#ifdef CONFIG_GDBSTUB_UART1
-#define IRQ_UART1_LEVEL IRQ_GDBSTUB_LEVEL
-#else
-#define IRQ_UART1_LEVEL IRQ_UART_LEVEL
-#endif
-
-#define IRQ_DMA0_LEVEL 14
-#define IRQ_DMA1_LEVEL 14
-#define IRQ_DMA2_LEVEL 14
-#define IRQ_DMA3_LEVEL 14
-#define IRQ_DMA4_LEVEL 14
-#define IRQ_DMA5_LEVEL 14
-#define IRQ_DMA6_LEVEL 14
-#define IRQ_DMA7_LEVEL 14
-
-#define IRQ_TIMER0_LEVEL 12
-#define IRQ_TIMER1_LEVEL 11
-#define IRQ_TIMER2_LEVEL 10
-
-#define IRQ_XIRQ0_LEVEL 1
-#define IRQ_XIRQ1_LEVEL 2
-#define IRQ_XIRQ2_LEVEL 3
-#define IRQ_XIRQ3_LEVEL 4
-#define IRQ_XIRQ4_LEVEL 5
-#define IRQ_XIRQ5_LEVEL 6
-#define IRQ_XIRQ6_LEVEL 7
-#define IRQ_XIRQ7_LEVEL 8
-
-/* IRQ IDs presented to drivers */
-#define IRQ_CPU__UNUSED IRQ_BASE_CPU
-#define IRQ_CPU_UART0 (IRQ_BASE_CPU + IRQ_UART0_LEVEL)
-#define IRQ_CPU_UART1 (IRQ_BASE_CPU + IRQ_UART1_LEVEL)
-#define IRQ_CPU_TIMER0 (IRQ_BASE_CPU + IRQ_TIMER0_LEVEL)
-#define IRQ_CPU_TIMER1 (IRQ_BASE_CPU + IRQ_TIMER1_LEVEL)
-#define IRQ_CPU_TIMER2 (IRQ_BASE_CPU + IRQ_TIMER2_LEVEL)
-#define IRQ_CPU_DMA0 (IRQ_BASE_CPU + IRQ_DMA0_LEVEL)
-#define IRQ_CPU_DMA1 (IRQ_BASE_CPU + IRQ_DMA1_LEVEL)
-#define IRQ_CPU_DMA2 (IRQ_BASE_CPU + IRQ_DMA2_LEVEL)
-#define IRQ_CPU_DMA3 (IRQ_BASE_CPU + IRQ_DMA3_LEVEL)
-#define IRQ_CPU_DMA4 (IRQ_BASE_CPU + IRQ_DMA4_LEVEL)
-#define IRQ_CPU_DMA5 (IRQ_BASE_CPU + IRQ_DMA5_LEVEL)
-#define IRQ_CPU_DMA6 (IRQ_BASE_CPU + IRQ_DMA6_LEVEL)
-#define IRQ_CPU_DMA7 (IRQ_BASE_CPU + IRQ_DMA7_LEVEL)
-#define IRQ_CPU_EXTERNAL0 (IRQ_BASE_CPU + IRQ_XIRQ0_LEVEL)
-#define IRQ_CPU_EXTERNAL1 (IRQ_BASE_CPU + IRQ_XIRQ1_LEVEL)
-#define IRQ_CPU_EXTERNAL2 (IRQ_BASE_CPU + IRQ_XIRQ2_LEVEL)
-#define IRQ_CPU_EXTERNAL3 (IRQ_BASE_CPU + IRQ_XIRQ3_LEVEL)
-#define IRQ_CPU_EXTERNAL4 (IRQ_BASE_CPU + IRQ_XIRQ4_LEVEL)
-#define IRQ_CPU_EXTERNAL5 (IRQ_BASE_CPU + IRQ_XIRQ5_LEVEL)
-#define IRQ_CPU_EXTERNAL6 (IRQ_BASE_CPU + IRQ_XIRQ6_LEVEL)
-#define IRQ_CPU_EXTERNAL7 (IRQ_BASE_CPU + IRQ_XIRQ7_LEVEL)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_CPU_IRQS_H */
diff --git a/arch/frv/include/asm/current.h b/arch/frv/include/asm/current.h
deleted file mode 100644
index 86b027491b08..000000000000
--- a/arch/frv/include/asm/current.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* current.h: FRV current task pointer
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CURRENT_H
-#define _ASM_CURRENT_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * dedicate GR29 to keeping the current task pointer
- */
-register struct task_struct *current asm("gr29");
-
-#define get_current() current
-
-#else
-
-#define CURRENT gr29
-
-#endif
-
-#endif /* _ASM_CURRENT_H */
diff --git a/arch/frv/include/asm/delay.h b/arch/frv/include/asm/delay.h
deleted file mode 100644
index 597b4ebf03b4..000000000000
--- a/arch/frv/include/asm/delay.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* delay.h: FRV delay code
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DELAY_H
-#define _ASM_DELAY_H
-
-#include <asm/param.h>
-#include <asm/timer-regs.h>
-
-/*
- * delay loop - runs at __core_clock_speed_HZ / 2 [there are 2 insns in the loop]
- */
-extern unsigned long __delay_loops_MHz;
-
-static inline void __delay(unsigned long loops)
-{
- asm volatile("1: subicc %0,#1,%0,icc0 \n"
- " bnc icc0,#2,1b \n"
- : "=r" (loops)
- : "0" (loops)
- : "icc0"
- );
-}
-
-/*
- * Use only for very small delays ( < 1 msec). Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays. This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-
-extern unsigned long loops_per_jiffy;
-
-static inline void udelay(unsigned long usecs)
-{
- __delay(usecs * __delay_loops_MHz);
-}
-
-#define ndelay(n) udelay((n) * 5)
-
-#endif /* _ASM_DELAY_H */
diff --git a/arch/frv/include/asm/div64.h b/arch/frv/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/frv/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/frv/include/asm/dm9000.h b/arch/frv/include/asm/dm9000.h
deleted file mode 100644
index f6f48fd9ec6e..000000000000
--- a/arch/frv/include/asm/dm9000.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* dm9000.h: Davicom DM9000 adapter configuration
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DM9000_H
-#define _ASM_DM9000_H
-
-#include <asm/mb-regs.h>
-
-#define DM9000_ARCH_IOBASE (__region_CS6 + 0x300)
-#define DM9000_ARCH_IRQ IRQ_CPU_EXTERNAL3 /* XIRQ #3 (shared with FPGA) */
-#undef DM9000_ARCH_IRQ_ACTLOW /* IRQ pin active high */
-#define DM9000_ARCH_BUS_INFO "CS6#+0x300" /* bus info for ethtool */
-
-#undef __is_PCI_IO
-#define __is_PCI_IO(addr) 0 /* not PCI */
-
-#undef inl
-#define inl(addr) \
-({ \
- unsigned long __ioaddr = (unsigned long) addr; \
- uint32_t x = readl(__ioaddr); \
- ((x & 0xff) << 24) | ((x & 0xff00) << 8) | ((x >> 8) & 0xff00) | ((x >> 24) & 0xff); \
-})
-
-#undef insl
-#define insl(a,b,l) __insl(a,b,l,0) /* don't byte-swap */
-
-
-#endif /* _ASM_DM9000_H */
diff --git a/arch/frv/include/asm/dma-mapping.h b/arch/frv/include/asm/dma-mapping.h
deleted file mode 100644
index fd80e840a1e6..000000000000
--- a/arch/frv/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-
-#include <asm/cache.h>
-#include <asm/cacheflush.h>
-
-extern unsigned long __nongprelbss dma_coherent_mem_start;
-extern unsigned long __nongprelbss dma_coherent_mem_end;
-
-extern const struct dma_map_ops frv_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &frv_dma_ops;
-}
-
-#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/frv/include/asm/dma.h b/arch/frv/include/asm/dma.h
deleted file mode 100644
index 683c47d48a5b..000000000000
--- a/arch/frv/include/asm/dma.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* dma.h: FRV DMA controller management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-//#define DMA_DEBUG 1
-
-#include <linux/interrupt.h>
-
-#undef MAX_DMA_CHANNELS /* don't use kernel/dma.c */
-
-/* under 2.4 this is actually needed by the new bootmem allocator */
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/*
- * FRV DMA controller management
- */
-typedef irqreturn_t (*dma_irq_handler_t)(int dmachan, unsigned long cstr, void *data);
-
-extern void frv_dma_init(void);
-
-extern int frv_dma_open(const char *devname,
- unsigned long dmamask,
- int dmacap,
- dma_irq_handler_t handler,
- unsigned long irq_flags,
- void *data);
-
-/* channels required */
-#define FRV_DMA_MASK_ANY ULONG_MAX /* any channel */
-
-/* capabilities required */
-#define FRV_DMA_CAP_DREQ 0x01 /* DMA request pin */
-#define FRV_DMA_CAP_DACK 0x02 /* DMA ACK pin */
-#define FRV_DMA_CAP_DONE 0x04 /* DMA done pin */
-
-extern void frv_dma_close(int dma);
-
-extern void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr);
-
-extern void frv_dma_start(int dma,
- unsigned long sba, unsigned long dba,
- unsigned long pix, unsigned long six, unsigned long bcl);
-
-extern void frv_dma_restart_circular(int dma, unsigned long six);
-
-extern void frv_dma_stop(int dma);
-
-extern int is_frv_dma_interrupting(int dma);
-
-extern void frv_dma_dump(int dma);
-
-extern void frv_dma_status_clear(int dma);
-
-#define FRV_DMA_NCHANS 8
-#define FRV_DMA_4CHANS 4
-#define FRV_DMA_8CHANS 8
-
-#define DMAC_CCFRx 0x00 /* channel configuration reg */
-#define DMAC_CCFRx_CM_SHIFT 16
-#define DMAC_CCFRx_CM_DA 0x00000000
-#define DMAC_CCFRx_CM_SCA 0x00010000
-#define DMAC_CCFRx_CM_DCA 0x00020000
-#define DMAC_CCFRx_CM_2D 0x00030000
-#define DMAC_CCFRx_ATS_SHIFT 8
-#define DMAC_CCFRx_RS_INTERN 0x00000000
-#define DMAC_CCFRx_RS_EXTERN 0x00000001
-#define DMAC_CCFRx_RS_SHIFT 0
-
-#define DMAC_CSTRx 0x08 /* channel status reg */
-#define DMAC_CSTRx_FS 0x0000003f
-#define DMAC_CSTRx_NE 0x00000100
-#define DMAC_CSTRx_FED 0x00000200
-#define DMAC_CSTRx_WER 0x00000800
-#define DMAC_CSTRx_RER 0x00001000
-#define DMAC_CSTRx_CE 0x00002000
-#define DMAC_CSTRx_INT 0x00800000
-#define DMAC_CSTRx_BUSY 0x80000000
-
-#define DMAC_CCTRx 0x10 /* channel control reg */
-#define DMAC_CCTRx_DSIZ_1 0x00000000
-#define DMAC_CCTRx_DSIZ_2 0x00000001
-#define DMAC_CCTRx_DSIZ_4 0x00000002
-#define DMAC_CCTRx_DSIZ_32 0x00000005
-#define DMAC_CCTRx_DAU_HOLD 0x00000000
-#define DMAC_CCTRx_DAU_INC 0x00000010
-#define DMAC_CCTRx_DAU_DEC 0x00000020
-#define DMAC_CCTRx_SSIZ_1 0x00000000
-#define DMAC_CCTRx_SSIZ_2 0x00000100
-#define DMAC_CCTRx_SSIZ_4 0x00000200
-#define DMAC_CCTRx_SSIZ_32 0x00000500
-#define DMAC_CCTRx_SAU_HOLD 0x00000000
-#define DMAC_CCTRx_SAU_INC 0x00001000
-#define DMAC_CCTRx_SAU_DEC 0x00002000
-#define DMAC_CCTRx_FC 0x08000000
-#define DMAC_CCTRx_ICE 0x10000000
-#define DMAC_CCTRx_IE 0x40000000
-#define DMAC_CCTRx_ACT 0x80000000
-
-#define DMAC_SBAx 0x18 /* source base address reg */
-#define DMAC_DBAx 0x20 /* data base address reg */
-#define DMAC_PIXx 0x28 /* primary index reg */
-#define DMAC_SIXx 0x30 /* secondary index reg */
-#define DMAC_BCLx 0x38 /* byte count limit reg */
-#define DMAC_APRx 0x40 /* alternate pointer reg */
-
-/*
- * required for PCI + MODULES
- */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/arch/frv/include/asm/elf.h b/arch/frv/include/asm/elf.h
deleted file mode 100644
index 2bac6446db41..000000000000
--- a/arch/frv/include/asm/elf.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* elf.h: FR-V ELF definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-m68knommu/elf.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_ELF_H
-#define __ASM_ELF_H
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-struct elf32_hdr;
-
-/*
- * ELF header e_flags defines.
- */
-#define EF_FRV_GPR_MASK 0x00000003 /* mask for # of gprs */
-#define EF_FRV_GPR32 0x00000001 /* Only uses GR on 32-register */
-#define EF_FRV_GPR64 0x00000002 /* Only uses GR on 64-register */
-#define EF_FRV_FPR_MASK 0x0000000c /* mask for # of fprs */
-#define EF_FRV_FPR32 0x00000004 /* Only uses FR on 32-register */
-#define EF_FRV_FPR64 0x00000008 /* Only uses FR on 64-register */
-#define EF_FRV_FPR_NONE 0x0000000C /* Uses software floating-point */
-#define EF_FRV_DWORD_MASK 0x00000030 /* mask for dword support */
-#define EF_FRV_DWORD_YES 0x00000010 /* Assumes stack aligned to 8-byte boundaries. */
-#define EF_FRV_DWORD_NO 0x00000020 /* Assumes stack aligned to 4-byte boundaries. */
-#define EF_FRV_DOUBLE 0x00000040 /* Uses double instructions. */
-#define EF_FRV_MEDIA 0x00000080 /* Uses media instructions. */
-#define EF_FRV_PIC 0x00000100 /* Uses position independent code. */
-#define EF_FRV_NON_PIC_RELOCS 0x00000200 /* Does not use position Independent code. */
-#define EF_FRV_MULADD 0x00000400 /* -mmuladd */
-#define EF_FRV_BIGPIC 0x00000800 /* -fPIC */
-#define EF_FRV_LIBPIC 0x00001000 /* -mlibrary-pic */
-#define EF_FRV_G0 0x00002000 /* -G 0, no small data ptr */
-#define EF_FRV_NOPACK 0x00004000 /* -mnopack */
-#define EF_FRV_FDPIC 0x00008000 /* -mfdpic */
-#define EF_FRV_CPU_MASK 0xff000000 /* specific cpu bits */
-#define EF_FRV_CPU_GENERIC 0x00000000 /* Set CPU type is FR-V */
-#define EF_FRV_CPU_FR500 0x01000000 /* Set CPU type is FR500 */
-#define EF_FRV_CPU_FR300 0x02000000 /* Set CPU type is FR300 */
-#define EF_FRV_CPU_SIMPLE 0x03000000 /* SIMPLE */
-#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */
-#define EF_FRV_CPU_FR400 0x05000000 /* Set CPU type is FR400 */
-#define EF_FRV_CPU_FR550 0x06000000 /* Set CPU type is FR550 */
-#define EF_FRV_CPU_FR405 0x07000000 /* Set CPU type is FR405 */
-#define EF_FRV_CPU_FR450 0x08000000 /* Set CPU type is FR450 */
-
-/*
- * FR-V ELF relocation types
- */
-
-
-/*
- * ELF register definitions..
- */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_fpmedia_regs elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-extern int elf_check_arch(const struct elf32_hdr *hdr);
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_FRV_FDPIC && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS))
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_FRV_PIC)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2MSB
-#define ELF_ARCH EM_FRV
-
-#define ELF_PLAT_INIT(_r) \
-do { \
- __kernel_frame0_ptr->gr16 = 0; \
- __kernel_frame0_ptr->gr17 = 0; \
- __kernel_frame0_ptr->gr18 = 0; \
- __kernel_frame0_ptr->gr19 = 0; \
- __kernel_frame0_ptr->gr20 = 0; \
- __kernel_frame0_ptr->gr21 = 0; \
- __kernel_frame0_ptr->gr22 = 0; \
- __kernel_frame0_ptr->gr23 = 0; \
- __kernel_frame0_ptr->gr24 = 0; \
- __kernel_frame0_ptr->gr25 = 0; \
- __kernel_frame0_ptr->gr26 = 0; \
- __kernel_frame0_ptr->gr27 = 0; \
- __kernel_frame0_ptr->gr29 = 0; \
-} while(0)
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
-do { \
- __kernel_frame0_ptr->gr16 = _exec_map_addr; \
- __kernel_frame0_ptr->gr17 = _interp_map_addr; \
- __kernel_frame0_ptr->gr18 = _dynamic_addr; \
- __kernel_frame0_ptr->gr19 = 0; \
- __kernel_frame0_ptr->gr20 = 0; \
- __kernel_frame0_ptr->gr21 = 0; \
- __kernel_frame0_ptr->gr22 = 0; \
- __kernel_frame0_ptr->gr23 = 0; \
- __kernel_frame0_ptr->gr24 = 0; \
- __kernel_frame0_ptr->gr25 = 0; \
- __kernel_frame0_ptr->gr26 = 0; \
- __kernel_frame0_ptr->gr27 = 0; \
- __kernel_frame0_ptr->gr29 = 0; \
-} while(0)
-
-#define CORE_DUMP_USE_REGSET
-#define ELF_FDPIC_CORE_EFLAGS EF_FRV_FDPIC
-#define ELF_EXEC_PAGESIZE 16384
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0x08000000UL
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/frv/include/asm/emergency-restart.h b/arch/frv/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/frv/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/frv/include/asm/fpu.h b/arch/frv/include/asm/fpu.h
deleted file mode 100644
index 2f0929333f91..000000000000
--- a/arch/frv/include/asm/fpu.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_FPU_H
-#define __ASM_FPU_H
-
-
-/*
- * MAX floating point unit state size (FSAVE/FRESTORE)
- */
-
-#define kernel_fpu_end() do { asm volatile("bar":::"memory"); preempt_enable(); } while(0)
-
-#endif /* __ASM_FPU_H */
diff --git a/arch/frv/include/asm/ftrace.h b/arch/frv/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/frv/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/frv/include/asm/futex.h b/arch/frv/include/asm/futex.h
deleted file mode 100644
index dfcc3484231d..000000000000
--- a/arch/frv/include/asm/futex.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#ifdef __KERNEL__
-
-#include <linux/futex.h>
-#include <asm/errno.h>
-#include <linux/uaccess.h>
-
-extern int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
- u32 __user *uaddr);
-
-static inline int
-futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
- u32 oldval, u32 newval)
-{
- return -ENOSYS;
-}
-
-#endif
-#endif
diff --git a/arch/frv/include/asm/gdb-stub.h b/arch/frv/include/asm/gdb-stub.h
deleted file mode 100644
index e6bedd0cd9a5..000000000000
--- a/arch/frv/include/asm/gdb-stub.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* gdb-stub.h: FRV GDB stub
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_GDB_STUB_H
-#define __ASM_GDB_STUB_H
-
-#undef GDBSTUB_DEBUG_IO
-#undef GDBSTUB_DEBUG_PROTOCOL
-
-#include <asm/ptrace.h>
-
-/*
- * important register numbers in GDB protocol
- * - GR0, GR1, GR2, GR3, GR4, GR5, GR6, GR7,
- * - GR8, GR9, GR10, GR11, GR12, GR13, GR14, GR15,
- * - GR16, GR17, GR18, GR19, GR20, GR21, GR22, GR23,
- * - GR24, GR25, GR26, GR27, GR28, GR29, GR30, GR31,
- * - GR32, GR33, GR34, GR35, GR36, GR37, GR38, GR39,
- * - GR40, GR41, GR42, GR43, GR44, GR45, GR46, GR47,
- * - GR48, GR49, GR50, GR51, GR52, GR53, GR54, GR55,
- * - GR56, GR57, GR58, GR59, GR60, GR61, GR62, GR63,
- * - FR0, FR1, FR2, FR3, FR4, FR5, FR6, FR7,
- * - FR8, FR9, FR10, FR11, FR12, FR13, FR14, FR15,
- * - FR16, FR17, FR18, FR19, FR20, FR21, FR22, FR23,
- * - FR24, FR25, FR26, FR27, FR28, FR29, FR30, FR31,
- * - FR32, FR33, FR34, FR35, FR36, FR37, FR38, FR39,
- * - FR40, FR41, FR42, FR43, FR44, FR45, FR46, FR47,
- * - FR48, FR49, FR50, FR51, FR52, FR53, FR54, FR55,
- * - FR56, FR57, FR58, FR59, FR60, FR61, FR62, FR63,
- * - PC, PSR, CCR, CCCR,
- * - _X132, _X133, _X134
- * - TBR, BRR, DBAR0, DBAR1, DBAR2, DBAR3,
- * - SCR0, SCR1, SCR2, SCR3,
- * - LR, LCR,
- * - IACC0H, IACC0L,
- * - FSR0,
- * - ACC0, ACC1, ACC2, ACC3, ACC4, ACC5, ACC6, ACC7,
- * - ACCG0123, ACCG4567,
- * - MSR0, MSR1,
- * - GNER0, GNER1,
- * - FNER0, FNER1,
- */
-#define GDB_REG_GR(N) (N)
-#define GDB_REG_FR(N) (64+(N))
-#define GDB_REG_PC 128
-#define GDB_REG_PSR 129
-#define GDB_REG_CCR 130
-#define GDB_REG_CCCR 131
-#define GDB_REG_TBR 135
-#define GDB_REG_BRR 136
-#define GDB_REG_DBAR(N) (137+(N))
-#define GDB_REG_SCR(N) (141+(N))
-#define GDB_REG_LR 145
-#define GDB_REG_LCR 146
-#define GDB_REG_FSR0 149
-#define GDB_REG_ACC(N) (150+(N))
-#define GDB_REG_ACCG(N) (158+(N)/4)
-#define GDB_REG_MSR(N) (160+(N))
-#define GDB_REG_GNER(N) (162+(N))
-#define GDB_REG_FNER(N) (164+(N))
-
-#define GDB_REG_SP GDB_REG_GR(1)
-#define GDB_REG_FP GDB_REG_GR(2)
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-/*
- * Prototypes
- */
-extern void show_registers_only(struct pt_regs *regs);
-
-extern void gdbstub_init(void);
-extern void gdbstub(int type);
-extern void gdbstub_exit(int status);
-
-extern void gdbstub_io_init(void);
-extern void gdbstub_set_baud(unsigned baud);
-extern int gdbstub_rx_char(unsigned char *_ch, int nonblock);
-extern void gdbstub_tx_char(unsigned char ch);
-extern void gdbstub_tx_flush(void);
-extern void gdbstub_do_rx(void);
-
-extern asmlinkage void __debug_stub_init_break(void);
-extern asmlinkage void __break_hijack_kernel_event(void);
-extern asmlinkage void __break_hijack_kernel_event_breaks_here(void);
-
-extern asmlinkage void gdbstub_rx_handler(void);
-extern asmlinkage void gdbstub_rx_irq(void);
-extern asmlinkage void gdbstub_intercept(void);
-
-extern uint32_t __entry_usertrap_table[];
-extern uint32_t __entry_kerneltrap_table[];
-
-extern volatile u8 gdbstub_rx_buffer[PAGE_SIZE];
-extern volatile u32 gdbstub_rx_inp;
-extern volatile u32 gdbstub_rx_outp;
-extern volatile u8 gdbstub_rx_overflow;
-extern u8 gdbstub_rx_unget;
-
-extern void gdbstub_printk(const char *fmt, ...);
-extern void debug_to_serial(const char *p, int n);
-extern void console_set_baud(unsigned baud);
-
-#ifdef GDBSTUB_DEBUG_IO
-#define gdbstub_io(FMT,...) gdbstub_printk(FMT, ##__VA_ARGS__)
-#else
-#define gdbstub_io(FMT,...) ({ 0; })
-#endif
-
-#ifdef GDBSTUB_DEBUG_PROTOCOL
-#define gdbstub_proto(FMT,...) gdbstub_printk(FMT,##__VA_ARGS__)
-#else
-#define gdbstub_proto(FMT,...) ({ 0; })
-#endif
-
-/*
- * we dedicate GR31 to keeping a pointer to the gdbstub exception frame
- * - gr31 is destroyed on entry to the gdbstub if !MMU
- * - gr31 is saved in scr3 on entry to the gdbstub if in !MMU
- */
-register struct frv_frame0 *__debug_frame0 asm("gr31");
-
-#define __debug_frame (&__debug_frame0->regs)
-#define __debug_user_context (&__debug_frame0->uc)
-#define __debug_regs (&__debug_frame0->debug)
-#define __debug_reg(X) ((unsigned long *) ((unsigned long) &__debug_frame0 + (X)))
-
-struct frv_debug_status {
- unsigned long bpsr;
- unsigned long dcr;
- unsigned long brr;
- unsigned long nmar;
-};
-
-extern struct frv_debug_status __debug_status;
-
-#endif /* _LANGUAGE_ASSEMBLY */
-#endif /* __ASM_GDB_STUB_H */
diff --git a/arch/frv/include/asm/gpio-regs.h b/arch/frv/include/asm/gpio-regs.h
deleted file mode 100644
index 9edf5d5d4d3f..000000000000
--- a/arch/frv/include/asm/gpio-regs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* gpio-regs.h: on-chip general purpose I/O registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_GPIO_REGS
-#define _ASM_GPIO_REGS
-
-#define __reg(ADDR) (*(volatile unsigned long *)(ADDR))
-
-#define __get_PDR() ({ __reg(0xfeff0400); })
-#define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0)
-
-#define __get_GPDR() ({ __reg(0xfeff0408); })
-#define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0)
-
-#define __get_SIR() ({ __reg(0xfeff0410); })
-#define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0)
-
-#define __get_SOR() ({ __reg(0xfeff0418); })
-#define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0)
-
-#define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0)
-
-#define __set_PDCR(V) do { __reg(0xfeff0428) = (V); mb(); } while(0)
-
-#define __get_RSTR() ({ __reg(0xfeff0500); })
-#define __set_RSTR(V) do { __reg(0xfeff0500) = (V); mb(); } while(0)
-
-
-
-/* PDR definitions */
-#define PDR_GPIO_DATA(X) (1 << (X))
-
-/* GPDR definitions */
-#define GPDR_INPUT 0
-#define GPDR_OUTPUT 1
-#define GPDR_DREQ0_BIT 0x00001000
-#define GPDR_DREQ1_BIT 0x00008000
-#define GPDR_DREQ2_BIT 0x00040000
-#define GPDR_DREQ3_BIT 0x00080000
-#define GPDR_DREQ4_BIT 0x00004000
-#define GPDR_DREQ5_BIT 0x00020000
-#define GPDR_DREQ6_BIT 0x00100000
-#define GPDR_DREQ7_BIT 0x00200000
-#define GPDR_DACK0_BIT 0x00002000
-#define GPDR_DACK1_BIT 0x00010000
-#define GPDR_DACK2_BIT 0x00100000
-#define GPDR_DACK3_BIT 0x00200000
-#define GPDR_DONE0_BIT 0x00004000
-#define GPDR_DONE1_BIT 0x00020000
-#define GPDR_GPIO_DIR(X,D) ((D) << (X))
-
-/* SIR definitions */
-#define SIR_GPIO_INPUT 0
-#define SIR_DREQ7_INPUT 0x00200000
-#define SIR_DREQ6_INPUT 0x00100000
-#define SIR_DREQ3_INPUT 0x00080000
-#define SIR_DREQ2_INPUT 0x00040000
-#define SIR_DREQ5_INPUT 0x00020000
-#define SIR_DREQ1_INPUT 0x00008000
-#define SIR_DREQ4_INPUT 0x00004000
-#define SIR_DREQ0_INPUT 0x00001000
-#define SIR_RXD1_INPUT 0x00000400
-#define SIR_CTS0_INPUT 0x00000100
-#define SIR_RXD0_INPUT 0x00000040
-#define SIR_GATE1_INPUT 0x00000020
-#define SIR_GATE0_INPUT 0x00000010
-#define SIR_IRQ3_INPUT 0x00000008
-#define SIR_IRQ2_INPUT 0x00000004
-#define SIR_IRQ1_INPUT 0x00000002
-#define SIR_IRQ0_INPUT 0x00000001
-#define SIR_DREQ_BITS (SIR_DREQ0_INPUT | SIR_DREQ1_INPUT | \
- SIR_DREQ2_INPUT | SIR_DREQ3_INPUT | \
- SIR_DREQ4_INPUT | SIR_DREQ5_INPUT | \
- SIR_DREQ6_INPUT | SIR_DREQ7_INPUT)
-
-/* SOR definitions */
-#define SOR_GPIO_OUTPUT 0
-#define SOR_DACK3_OUTPUT 0x00200000
-#define SOR_DACK2_OUTPUT 0x00100000
-#define SOR_DONE1_OUTPUT 0x00020000
-#define SOR_DACK1_OUTPUT 0x00010000
-#define SOR_DONE0_OUTPUT 0x00004000
-#define SOR_DACK0_OUTPUT 0x00002000
-#define SOR_TXD1_OUTPUT 0x00000800
-#define SOR_RTS0_OUTPUT 0x00000200
-#define SOR_TXD0_OUTPUT 0x00000080
-#define SOR_TOUT1_OUTPUT 0x00000020
-#define SOR_TOUT0_OUTPUT 0x00000010
-#define SOR_DONE_BITS (SOR_DONE0_OUTPUT | SOR_DONE1_OUTPUT)
-#define SOR_DACK_BITS (SOR_DACK0_OUTPUT | SOR_DACK1_OUTPUT | \
- SOR_DACK2_OUTPUT | SOR_DACK3_OUTPUT)
-
-/* PDSR definitions */
-#define PDSR_UNCHANGED 0
-#define PDSR_SET_BIT(X) (1 << (X))
-
-/* PDCR definitions */
-#define PDCR_UNCHANGED 0
-#define PDCR_CLEAR_BIT(X) (1 << (X))
-
-/* RSTR definitions */
-/* Read Only */
-#define RSTR_POWERON 0x00000400
-#define RSTR_SOFTRESET_STATUS 0x00000100
-/* Write Only */
-#define RSTR_SOFTRESET 0x00000001
-
-#endif /* _ASM_GPIO_REGS */
diff --git a/arch/frv/include/asm/hardirq.h b/arch/frv/include/asm/hardirq.h
deleted file mode 100644
index c62833d6ebbb..000000000000
--- a/arch/frv/include/asm/hardirq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* hardirq.h: FRV hardware IRQ management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-
-#include <linux/atomic.h>
-
-extern atomic_t irq_err_count;
-static inline void ack_bad_irq(int irq)
-{
- atomic_inc(&irq_err_count);
-}
-#define ack_bad_irq ack_bad_irq
-
-#include <asm-generic/hardirq.h>
-
-#endif
diff --git a/arch/frv/include/asm/highmem.h b/arch/frv/include/asm/highmem.h
deleted file mode 100644
index 1f58938703ab..000000000000
--- a/arch/frv/include/asm/highmem.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* highmem.h: virtual kernel memory mappings for high memory
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-i386/highmem.h
- *
- * See Documentation/frv/mmu-layout.txt for more information.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/highmem.h>
-#include <asm/mem-layout.h>
-#include <asm/spr-regs.h>
-#include <asm/mb-regs.h>
-
-#define NR_TLB_LINES 64 /* number of lines in the TLB */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-#include <asm/kmap_types.h>
-#include <asm/pgtable.h>
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define HIGHMEM_DEBUG 1
-#else
-#define HIGHMEM_DEBUG 0
-#endif
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-#define kmap_prot PAGE_KERNEL
-#define kmap_pte ______kmap_pte_in_TLB
-extern pte_t *pkmap_page_table;
-
-#define flush_cache_kmaps() do { } while (0)
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define LAST_PKMAP PTRS_PER_PTE
-#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
-#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-extern void *kmap(struct page *page);
-extern void kunmap(struct page *page);
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
- * gives a more generic (and caching) interface. But kmap_atomic can
- * be used in IRQ contexts, so in some (very limited) cases we need
- * it.
- */
-#define KMAP_ATOMIC_CACHE_DAMR 8
-
-#ifndef __ASSEMBLY__
-
-#define __kmap_atomic_primary(cached, paddr, ampr) \
-({ \
- unsigned long damlr, dampr; \
- \
- dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V; \
- \
- if (!cached) \
- asm volatile("movgs %0,dampr"#ampr :: "r"(dampr) : "memory"); \
- else \
- /* cache flush page attachment point */ \
- asm volatile("movgs %0,iampr"#ampr"\n" \
- "movgs %0,dampr"#ampr"\n" \
- :: "r"(dampr) : "memory" \
- ); \
- \
- asm("movsg damlr"#ampr",%0" : "=r"(damlr)); \
- \
- /*printk("DAMR"#ampr": PRIM sl=%d L=%08lx P=%08lx\n", type, damlr, dampr);*/ \
- \
- (void *) damlr; \
-})
-
-#define __kmap_atomic_secondary(slot, paddr) \
-({ \
- unsigned long damlr = KMAP_ATOMIC_SECONDARY_FRAME + (slot) * PAGE_SIZE; \
- unsigned long dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V; \
- \
- asm volatile("movgs %0,tplr \n" \
- "movgs %1,tppr \n" \
- "tlbpr %0,gr0,#2,#1" \
- : : "r"(damlr), "r"(dampr) : "memory"); \
- \
- /*printk("TLB: SECN sl=%d L=%08lx P=%08lx\n", slot, damlr, dampr);*/ \
- \
- (void *) damlr; \
-})
-
-static inline void *kmap_atomic_primary(struct page *page)
-{
- unsigned long paddr;
-
- pagefault_disable();
- paddr = page_to_phys(page);
-
- return __kmap_atomic_primary(1, paddr, 2);
-}
-
-#define __kunmap_atomic_primary(cached, ampr) \
-do { \
- asm volatile("movgs gr0,dampr"#ampr"\n" ::: "memory"); \
- if (cached) \
- asm volatile("movgs gr0,iampr"#ampr"\n" ::: "memory"); \
-} while(0)
-
-#define __kunmap_atomic_secondary(slot, vaddr) \
-do { \
- asm volatile("tlbpr %0,gr0,#4,#1" : : "r"(vaddr) : "memory"); \
-} while(0)
-
-static inline void kunmap_atomic_primary(void *kvaddr)
-{
- __kunmap_atomic_primary(1, 2);
- pagefault_enable();
-}
-
-void *kmap_atomic(struct page *page);
-void __kunmap_atomic(void *kvaddr);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/frv/include/asm/hw_irq.h b/arch/frv/include/asm/hw_irq.h
deleted file mode 100644
index 522ad37923d8..000000000000
--- a/arch/frv/include/asm/hw_irq.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* hw_irq.h: FR-V specific h/w IRQ stuff
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-
-#endif /* _ASM_HW_IRQ_H */
diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h
deleted file mode 100644
index 8062fc73fad0..000000000000
--- a/arch/frv/include/asm/io.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/* io.h: FRV I/O operations
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * This gets interesting when talking to the PCI bus - the CPU is in big endian
- * mode, the PCI bus is little endian and the hardware in the middle can do
- * byte swapping
- */
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#ifdef __KERNEL__
-
-#define ARCH_HAS_IOREMAP_WT
-
-#include <linux/types.h>
-#include <asm/virtconvert.h>
-#include <asm/string.h>
-#include <asm/mb-regs.h>
-#include <asm-generic/pci_iomap.h>
-#include <linux/delay.h>
-
-/*
- * swap functions are sometimes needed to interface little-endian hardware
- */
-
-static inline unsigned short _swapw(unsigned short v)
-{
- return ((v << 8) | (v >> 8));
-}
-
-static inline unsigned long _swapl(unsigned long v)
-{
- return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
-}
-
-//#define __iormb() asm volatile("membar")
-//#define __iowmb() asm volatile("membar")
-
-static inline u8 __raw_readb(const volatile void __iomem *addr)
-{
- return __builtin_read8((volatile void __iomem *)addr);
-}
-
-static inline u16 __raw_readw(const volatile void __iomem *addr)
-{
- return __builtin_read16((volatile void __iomem *)addr);
-}
-
-static inline u32 __raw_readl(const volatile void __iomem *addr)
-{
- return __builtin_read32((volatile void __iomem *)addr);
-}
-
-#define __raw_writeb(datum, addr) __builtin_write8(addr, datum)
-#define __raw_writew(datum, addr) __builtin_write16(addr, datum)
-#define __raw_writel(datum, addr) __builtin_write32(addr, datum)
-
-static inline void io_outsb(unsigned int addr, const void *buf, int len)
-{
- unsigned long __ioaddr = (unsigned long) addr;
- const uint8_t *bp = buf;
-
- while (len--)
- __builtin_write8((volatile void __iomem *) __ioaddr, *bp++);
-}
-
-static inline void io_outsw(unsigned int addr, const void *buf, int len)
-{
- unsigned long __ioaddr = (unsigned long) addr;
- const uint16_t *bp = buf;
-
- while (len--)
- __builtin_write16((volatile void __iomem *) __ioaddr, (*bp++));
-}
-
-extern void __outsl_ns(unsigned int addr, const void *buf, int len);
-extern void __outsl_sw(unsigned int addr, const void *buf, int len);
-static inline void __outsl(unsigned int addr, const void *buf, int len, int swap)
-{
- unsigned long __ioaddr = (unsigned long) addr;
-
- if (!swap)
- __outsl_ns(__ioaddr, buf, len);
- else
- __outsl_sw(__ioaddr, buf, len);
-}
-
-static inline void io_insb(unsigned long addr, void *buf, int len)
-{
- uint8_t *bp = buf;
-
- while (len--)
- *bp++ = __builtin_read8((volatile void __iomem *) addr);
-}
-
-static inline void io_insw(unsigned long addr, void *buf, int len)
-{
- uint16_t *bp = buf;
-
- while (len--)
- *bp++ = __builtin_read16((volatile void __iomem *) addr);
-}
-
-extern void __insl_ns(unsigned long addr, void *buf, int len);
-extern void __insl_sw(unsigned long addr, void *buf, int len);
-static inline void __insl(unsigned long addr, void *buf, int len, int swap)
-{
- if (!swap)
- __insl_ns(addr, buf, len);
- else
- __insl_sw(addr, buf, len);
-}
-
-#define mmiowb() mb()
-
-/*
- * make the short names macros so specific devices
- * can override them as required
- */
-
-static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
- memset((void __force *) addr, val, count);
-}
-
-static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
-{
- memcpy(dst, (void __force *) src, count);
-}
-
-static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
- memcpy((void __force *) dst, src, count);
-}
-
-static inline uint8_t inb(unsigned long addr)
-{
- return __builtin_read8((void __iomem *)addr);
-}
-
-static inline uint16_t inw(unsigned long addr)
-{
- uint16_t ret = __builtin_read16((void __iomem *)addr);
-
- if (__is_PCI_IO(addr))
- ret = _swapw(ret);
-
- return ret;
-}
-
-static inline uint32_t inl(unsigned long addr)
-{
- uint32_t ret = __builtin_read32((void __iomem *)addr);
-
- if (__is_PCI_IO(addr))
- ret = _swapl(ret);
-
- return ret;
-}
-
-static inline void outb(uint8_t datum, unsigned long addr)
-{
- __builtin_write8((void __iomem *)addr, datum);
-}
-
-static inline void outw(uint16_t datum, unsigned long addr)
-{
- if (__is_PCI_IO(addr))
- datum = _swapw(datum);
- __builtin_write16((void __iomem *)addr, datum);
-}
-
-static inline void outl(uint32_t datum, unsigned long addr)
-{
- if (__is_PCI_IO(addr))
- datum = _swapl(datum);
- __builtin_write32((void __iomem *)addr, datum);
-}
-
-#define inb_p(addr) inb(addr)
-#define inw_p(addr) inw(addr)
-#define inl_p(addr) inl(addr)
-#define outb_p(x,addr) outb(x,addr)
-#define outw_p(x,addr) outw(x,addr)
-#define outl_p(x,addr) outl(x,addr)
-
-#define outsb(a,b,l) io_outsb(a,b,l)
-#define outsw(a,b,l) io_outsw(a,b,l)
-#define outsl(a,b,l) __outsl(a,b,l,0)
-
-#define insb(a,b,l) io_insb(a,b,l)
-#define insw(a,b,l) io_insw(a,b,l)
-#define insl(a,b,l) __insl(a,b,l,0)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline uint8_t readb(const volatile void __iomem *addr)
-{
- return __builtin_read8((__force void volatile __iomem *) addr);
-}
-
-static inline uint16_t readw(const volatile void __iomem *addr)
-{
- uint16_t ret = __builtin_read16((__force void volatile __iomem *)addr);
-
- if (__is_PCI_MEM(addr))
- ret = _swapw(ret);
- return ret;
-}
-
-static inline uint32_t readl(const volatile void __iomem *addr)
-{
- uint32_t ret = __builtin_read32((__force void volatile __iomem *)addr);
-
- if (__is_PCI_MEM(addr))
- ret = _swapl(ret);
-
- return ret;
-}
-
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-
-static inline void writeb(uint8_t datum, volatile void __iomem *addr)
-{
- __builtin_write8(addr, datum);
- if (__is_PCI_MEM(addr))
- __flush_PCI_writes();
-}
-
-static inline void writew(uint16_t datum, volatile void __iomem *addr)
-{
- if (__is_PCI_MEM(addr))
- datum = _swapw(datum);
-
- __builtin_write16(addr, datum);
- if (__is_PCI_MEM(addr))
- __flush_PCI_writes();
-}
-
-static inline void writel(uint32_t datum, volatile void __iomem *addr)
-{
- if (__is_PCI_MEM(addr))
- datum = _swapl(datum);
-
- __builtin_write32(addr, datum);
- if (__is_PCI_MEM(addr))
- __flush_PCI_writes();
-}
-
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_FULL_CACHING 0
-#define IOMAP_NOCACHE_SER 1
-#define IOMAP_NOCACHE_NONSER 2
-#define IOMAP_WRITETHROUGH 3
-
-extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-
-static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-
-static inline void __iomem *ioremap_wt(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
-}
-
-static inline void __iomem *ioremap_fullcache(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
-}
-
-#define ioremap_wc ioremap_nocache
-#define ioremap_uc ioremap_nocache
-
-extern void iounmap(void volatile __iomem *addr);
-
-static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
- return (void __iomem *) port;
-}
-
-static inline void ioport_unmap(void __iomem *p)
-{
-}
-
-static inline void flush_write_buffers(void)
-{
- __asm__ __volatile__ ("membar" : : :"memory");
-}
-
-/*
- * do appropriate I/O accesses for token type
- */
-static inline unsigned int ioread8(void __iomem *p)
-{
- return __builtin_read8(p);
-}
-
-static inline unsigned int ioread16(void __iomem *p)
-{
- uint16_t ret = __builtin_read16(p);
- if (__is_PCI_addr(p))
- ret = _swapw(ret);
- return ret;
-}
-
-static inline unsigned int ioread32(void __iomem *p)
-{
- uint32_t ret = __builtin_read32(p);
- if (__is_PCI_addr(p))
- ret = _swapl(ret);
- return ret;
-}
-
-static inline void iowrite8(u8 val, void __iomem *p)
-{
- __builtin_write8(p, val);
- if (__is_PCI_MEM(p))
- __flush_PCI_writes();
-}
-
-static inline void iowrite16(u16 val, void __iomem *p)
-{
- if (__is_PCI_addr(p))
- val = _swapw(val);
- __builtin_write16(p, val);
- if (__is_PCI_MEM(p))
- __flush_PCI_writes();
-}
-
-static inline void iowrite32(u32 val, void __iomem *p)
-{
- if (__is_PCI_addr(p))
- val = _swapl(val);
- __builtin_write32(p, val);
- if (__is_PCI_MEM(p))
- __flush_PCI_writes();
-}
-
-#define ioread16be(addr) be16_to_cpu(ioread16(addr))
-#define ioread32be(addr) be32_to_cpu(ioread32(addr))
-#define iowrite16be(v, addr) iowrite16(cpu_to_be16(v), (addr))
-#define iowrite32be(v, addr) iowrite32(cpu_to_be32(v), (addr))
-
-static inline void ioread8_rep(void __iomem *p, void *dst, unsigned long count)
-{
- io_insb((unsigned long) p, dst, count);
-}
-
-static inline void ioread16_rep(void __iomem *p, void *dst, unsigned long count)
-{
- io_insw((unsigned long) p, dst, count);
-}
-
-static inline void ioread32_rep(void __iomem *p, void *dst, unsigned long count)
-{
- __insl_ns((unsigned long) p, dst, count);
-}
-
-static inline void iowrite8_rep(void __iomem *p, const void *src, unsigned long count)
-{
- io_outsb((unsigned long) p, src, count);
-}
-
-static inline void iowrite16_rep(void __iomem *p, const void *src, unsigned long count)
-{
- io_outsw((unsigned long) p, src, count);
-}
-
-static inline void iowrite32_rep(void __iomem *p, const void *src, unsigned long count)
-{
- __outsl_ns((unsigned long) p, src, count);
-}
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
-{
-}
-
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IO_H */
diff --git a/arch/frv/include/asm/irc-regs.h b/arch/frv/include/asm/irc-regs.h
deleted file mode 100644
index afa30aeacc82..000000000000
--- a/arch/frv/include/asm/irc-regs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* irc-regs.h: on-chip interrupt controller registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRC_REGS
-#define _ASM_IRC_REGS
-
-#define __reg(ADDR) (*(volatile unsigned long *)(ADDR))
-
-#define __get_TM0() ({ __reg(0xfeff9800); })
-#define __get_TM1() ({ __reg(0xfeff9808); })
-#define __set_TM1(V) do { __reg(0xfeff9808) = (V); mb(); } while(0)
-
-#define __set_TM1x(XI,V) \
-do { \
- int shift = (XI) * 2 + 16; \
- unsigned long tm1 = __reg(0xfeff9808); \
- tm1 &= ~(0x3 << shift); \
- tm1 |= (V) << shift; \
- __reg(0xfeff9808) = tm1; \
- mb(); \
-} while(0)
-
-#define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; })
-
-#define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0)
-
-#define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; })
-#define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0)
-#define __clr_MASK(C) do { __reg(0xfeff9820) &= ~(1 << ((C)+16)); mb(); } while(0)
-
-#define __get_MASK_all() __get_MASK(0)
-#define __set_MASK_all() __set_MASK(0)
-#define __clr_MASK_all() __clr_MASK(0)
-
-#define __get_IRL() ({ (__reg(0xfeff9828) >> 16) & 0xf; })
-#define __clr_IRL() do { __reg(0xfeff9828) = 0x100000; mb(); } while(0)
-
-#define __get_IRR(N) ({ __reg(0xfeff9840 + (N) * 8); })
-#define __set_IRR(N,V) do { __reg(0xfeff9840 + (N) * 8) = (V); } while(0)
-
-#define __get_IITMR(N) ({ __reg(0xfeff9880 + (N) * 8); })
-#define __set_IITMR(N,V) do { __reg(0xfeff9880 + (N) * 8) = (V); } while(0)
-
-
-#endif /* _ASM_IRC_REGS */
diff --git a/arch/frv/include/asm/irq.h b/arch/frv/include/asm/irq.h
deleted file mode 100644
index 3a66ebd754bd..000000000000
--- a/arch/frv/include/asm/irq.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* irq.h: FRV IRQ definitions
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQ_H_
-#define _ASM_IRQ_H_
-
-#define NR_IRQS 48
-#define IRQ_BASE_CPU (0 * 16)
-#define IRQ_BASE_FPGA (1 * 16)
-#define IRQ_BASE_MB93493 (2 * 16)
-
-/* probe returns a 32-bit IRQ mask:-/ */
-#define MIN_PROBE_IRQ (NR_IRQS - 32)
-
-#ifndef __ASSEMBLY__
-static inline int irq_canonicalize(int irq)
-{
- return irq;
-}
-#endif
-
-#endif /* _ASM_IRQ_H_ */
diff --git a/arch/frv/include/asm/irq_regs.h b/arch/frv/include/asm/irq_regs.h
deleted file mode 100644
index d22e83289ad1..000000000000
--- a/arch/frv/include/asm/irq_regs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* FRV per-CPU frame pointer holder
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQ_REGS_H
-#define _ASM_IRQ_REGS_H
-
-/*
- * Per-cpu current frame pointer - the location of the last exception frame on
- * the stack
- * - on FRV, GR28 is dedicated to keeping a pointer to the current exception
- * frame
- */
-#define ARCH_HAS_OWN_IRQ_REGS
-
-#ifndef __ASSEMBLY__
-#define get_irq_regs() (__frame)
-#endif
-
-#endif /* _ASM_IRQ_REGS_H */
diff --git a/arch/frv/include/asm/irqflags.h b/arch/frv/include/asm/irqflags.h
deleted file mode 100644
index 82f0b5363f42..000000000000
--- a/arch/frv/include/asm/irqflags.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* FR-V interrupt handling
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-/*
- * interrupt flag manipulation
- * - use virtual interrupt management since touching the PSR is slow
- * - ICC2.Z: T if interrupts virtually disabled
- * - ICC2.C: F if interrupts really disabled
- * - if Z==1 upon interrupt:
- * - C is set to 0
- * - interrupts are really disabled
- * - entry.S returns immediately
- * - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
- * - if taken, the trap:
- * - sets ICC2.C
- * - enables interrupts
- */
-static inline void arch_local_irq_disable(void)
-{
- /* set Z flag, but don't change the C flag */
- asm volatile(" andcc gr0,gr0,gr0,icc2 \n"
- :
- :
- : "memory", "icc2"
- );
-}
-
-static inline void arch_local_irq_enable(void)
-{
- /* clear Z flag and then test the C flag */
- asm volatile(" oricc gr0,#1,gr0,icc2 \n"
- " tihi icc2,gr0,#2 \n"
- :
- :
- : "memory", "icc2"
- );
-}
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
-
- asm volatile("movsg ccr,%0"
- : "=r"(flags)
- :
- : "memory");
-
- /* shift ICC2.Z to bit 0 */
- flags >>= 26;
-
- /* make flags 1 if interrupts disabled, 0 otherwise */
- return flags & 1UL;
-
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- /* load the Z flag by turning 1 if disabled into 0 if disabled
- * and thus setting the Z flag but not the C flag */
- asm volatile(" xoricc %0,#1,gr0,icc2 \n"
- /* then trap if Z=0 and C=0 */
- " tihi icc2,gr0,#2 \n"
- :
- : "r"(flags)
- : "memory", "icc2"
- );
-
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return flags;
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-/*
- * real interrupt flag manipulation
- */
-#define __arch_local_irq_disable() \
-do { \
- unsigned long psr; \
- asm volatile(" movsg psr,%0 \n" \
- " andi %0,%2,%0 \n" \
- " ori %0,%1,%0 \n" \
- " movgs %0,psr \n" \
- : "=r"(psr) \
- : "i" (PSR_PIL_14), "i" (~PSR_PIL) \
- : "memory"); \
-} while (0)
-
-#define __arch_local_irq_enable() \
-do { \
- unsigned long psr; \
- asm volatile(" movsg psr,%0 \n" \
- " andi %0,%1,%0 \n" \
- " movgs %0,psr \n" \
- : "=r"(psr) \
- : "i" (~PSR_PIL) \
- : "memory"); \
-} while (0)
-
-#define __arch_local_save_flags(flags) \
-do { \
- typecheck(unsigned long, flags); \
- asm("movsg psr,%0" \
- : "=r"(flags) \
- : \
- : "memory"); \
-} while (0)
-
-#define __arch_local_irq_save(flags) \
-do { \
- unsigned long npsr; \
- typecheck(unsigned long, flags); \
- asm volatile(" movsg psr,%0 \n" \
- " andi %0,%3,%1 \n" \
- " ori %1,%2,%1 \n" \
- " movgs %1,psr \n" \
- : "=r"(flags), "=r"(npsr) \
- : "i" (PSR_PIL_14), "i" (~PSR_PIL) \
- : "memory"); \
-} while (0)
-
-#define __arch_local_irq_restore(flags) \
-do { \
- typecheck(unsigned long, flags); \
- asm volatile(" movgs %0,psr \n" \
- : \
- : "r" (flags) \
- : "memory"); \
-} while (0)
-
-#define __arch_irqs_disabled() \
- ((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
-
-#endif /* _ASM_IRQFLAGS_H */
diff --git a/arch/frv/include/asm/kdebug.h b/arch/frv/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/frv/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/frv/include/asm/kmap_types.h b/arch/frv/include/asm/kmap_types.h
deleted file mode 100644
index 0849db1362d6..000000000000
--- a/arch/frv/include/asm/kmap_types.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-#define KM_TYPE_NR 17
-
-#endif
diff --git a/arch/frv/include/asm/linkage.h b/arch/frv/include/asm/linkage.h
deleted file mode 100644
index 636c1bced7d4..000000000000
--- a/arch/frv/include/asm/linkage.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/arch/frv/include/asm/local.h b/arch/frv/include/asm/local.h
deleted file mode 100644
index 259ae7b041a7..000000000000
--- a/arch/frv/include/asm/local.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_LOCAL_H
-#define _ASM_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif /* _ASM_LOCAL_H */
diff --git a/arch/frv/include/asm/local64.h b/arch/frv/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/frv/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/frv/include/asm/math-emu.h b/arch/frv/include/asm/math-emu.h
deleted file mode 100644
index 8af762dd6109..000000000000
--- a/arch/frv/include/asm/math-emu.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_MATH_EMU_H
-#define _ASM_MATH_EMU_H
-
-#include <asm/setup.h>
-#include <linux/linkage.h>
-
-/* Status Register bits */
-
-/* accrued exception bits */
-#define FPSR_AEXC_INEX 3
-#define FPSR_AEXC_DZ 4
-#define FPSR_AEXC_UNFL 5
-#define FPSR_AEXC_OVFL 6
-#define FPSR_AEXC_IOP 7
-
-/* exception status bits */
-#define FPSR_EXC_INEX1 8
-#define FPSR_EXC_INEX2 9
-#define FPSR_EXC_DZ 10
-#define FPSR_EXC_UNFL 11
-#define FPSR_EXC_OVFL 12
-#define FPSR_EXC_OPERR 13
-#define FPSR_EXC_SNAN 14
-#define FPSR_EXC_BSUN 15
-
-/* quotient byte, assumes big-endian, of course */
-#define FPSR_QUOTIENT(fpsr) (*((signed char *) &(fpsr) + 1))
-
-/* condition code bits */
-#define FPSR_CC_NAN 24
-#define FPSR_CC_INF 25
-#define FPSR_CC_Z 26
-#define FPSR_CC_NEG 27
-
-
-/* Control register bits */
-
-/* rounding mode */
-#define FPCR_ROUND_RN 0 /* round to nearest/even */
-#define FPCR_ROUND_RZ 1 /* round to zero */
-#define FPCR_ROUND_RM 2 /* minus infinity */
-#define FPCR_ROUND_RP 3 /* plus infinity */
-
-/* rounding precision */
-#define FPCR_PRECISION_X 0 /* long double */
-#define FPCR_PRECISION_S 1 /* double */
-#define FPCR_PRECISION_D 2 /* float */
-
-
-/* Flags to select the debugging output */
-#define PDECODE 0
-#define PEXECUTE 1
-#define PCONV 2
-#define PNORM 3
-#define PREGISTER 4
-#define PINSTR 5
-#define PUNIMPL 6
-#define PMOVEM 7
-
-#define PMDECODE (1<<PDECODE)
-#define PMEXECUTE (1<<PEXECUTE)
-#define PMCONV (1<<PCONV)
-#define PMNORM (1<<PNORM)
-#define PMREGISTER (1<<PREGISTER)
-#define PMINSTR (1<<PINSTR)
-#define PMUNIMPL (1<<PUNIMPL)
-#define PMMOVEM (1<<PMOVEM)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-union fp_mant64 {
- unsigned long long m64;
- unsigned long m32[2];
-};
-
-union fp_mant128 {
- unsigned long long m64[2];
- unsigned long m32[4];
-};
-
-/* internal representation of extended fp numbers */
-struct fp_ext {
- unsigned char lowmant;
- unsigned char sign;
- unsigned short exp;
- union fp_mant64 mant;
-};
-
-/* C representation of FPU registers */
-/* NOTE: if you change this, you have to change the assembler offsets
- below and the size in <asm/fpu.h>, too */
-struct fp_data {
- struct fp_ext fpreg[8];
- unsigned int fpcr;
- unsigned int fpsr;
- unsigned int fpiar;
- unsigned short prec;
- unsigned short rnd;
- struct fp_ext temp[2];
-};
-
-#if FPU_EMU_DEBUG
-extern unsigned int fp_debugprint;
-
-#define dprint(bit, fmt, args...) ({ \
- if (fp_debugprint & (1 << (bit))) \
- printk(fmt, ## args); \
-})
-#else
-#define dprint(bit, fmt, args...)
-#endif
-
-#define uprint(str) ({ \
- static int __count = 3; \
- \
- if (__count > 0) { \
- printk("You just hit an unimplemented " \
- "fpu instruction (%s)\n", str); \
- printk("Please report this to ....\n"); \
- __count--; \
- } \
-})
-
-#define FPDATA ((struct fp_data *)current->thread.fp)
-
-#else /* __ASSEMBLY__ */
-
-#define FPDATA %a2
-
-/* offsets from the base register to the floating point data in the task struct */
-#define FPD_FPREG (TASK_THREAD+THREAD_FPREG+0)
-#define FPD_FPCR (TASK_THREAD+THREAD_FPREG+96)
-#define FPD_FPSR (TASK_THREAD+THREAD_FPREG+100)
-#define FPD_FPIAR (TASK_THREAD+THREAD_FPREG+104)
-#define FPD_PREC (TASK_THREAD+THREAD_FPREG+108)
-#define FPD_RND (TASK_THREAD+THREAD_FPREG+110)
-#define FPD_TEMPFP1 (TASK_THREAD+THREAD_FPREG+112)
-#define FPD_TEMPFP2 (TASK_THREAD+THREAD_FPREG+124)
-#define FPD_SIZEOF (TASK_THREAD+THREAD_FPREG+136)
-
-/* offsets on the stack to access saved registers,
- * these are only used during instruction decoding
- * where we always know how deep we're on the stack.
- */
-#define FPS_DO (PT_D0)
-#define FPS_D1 (PT_D1)
-#define FPS_D2 (PT_D2)
-#define FPS_A0 (PT_A0)
-#define FPS_A1 (PT_A1)
-#define FPS_A2 (PT_A2)
-#define FPS_SR (PT_SR)
-#define FPS_PC (PT_PC)
-#define FPS_EA (PT_PC+6)
-#define FPS_PC2 (PT_PC+10)
-
-.macro fp_get_fp_reg
- lea (FPD_FPREG,FPDATA,%d0.w*4),%a0
- lea (%a0,%d0.w*8),%a0
-.endm
-
-/* Macros used to get/put the current program counter.
- * 020/030 use a different stack frame then 040/060, for the
- * 040/060 the return pc points already to the next location,
- * so this only needs to be modified for jump instructions.
- */
-.macro fp_get_pc dest
- move.l (FPS_PC+4,%sp),\dest
-.endm
-
-.macro fp_put_pc src,jump=0
- move.l \src,(FPS_PC+4,%sp)
-.endm
-
-.macro fp_get_instr_data f,s,dest,label
- getuser \f,%sp@(FPS_PC+4)@(0),\dest,\label,%sp@(FPS_PC+4)
- addq.l #\s,%sp@(FPS_PC+4)
-.endm
-
-.macro fp_get_instr_word dest,label,addr
- fp_get_instr_data w,2,\dest,\label,\addr
-.endm
-
-.macro fp_get_instr_long dest,label,addr
- fp_get_instr_data l,4,\dest,\label,\addr
-.endm
-
-/* These macros are used to read from/write to user space
- * on error we jump to the fixup section, load the fault
- * address into %a0 and jump to the exit.
- * (derived from <asm/uaccess.h>)
- */
-.macro getuser size,src,dest,label,addr
-| printf ,"[\size<%08x]",1,\addr
-.Lu1\@: moves\size \src,\dest
-
- .section .fixup,"ax"
- .even
-.Lu2\@: move.l \addr,%a0
- jra \label
- .previous
-
- .section __ex_table,"a"
- .align 4
- .long .Lu1\@,.Lu2\@
- .previous
-.endm
-
-.macro putuser size,src,dest,label,addr
-| printf ,"[\size>%08x]",1,\addr
-.Lu1\@: moves\size \src,\dest
-.Lu2\@:
-
- .section .fixup,"ax"
- .even
-.Lu3\@: move.l \addr,%a0
- jra \label
- .previous
-
- .section __ex_table,"a"
- .align 4
- .long .Lu1\@,.Lu3\@
- .long .Lu2\@,.Lu3\@
- .previous
-.endm
-
-
-.macro movestack nr,arg1,arg2,arg3,arg4,arg5
- .if \nr
- movestack (\nr-1),\arg2,\arg3,\arg4,\arg5
- move.l \arg1,-(%sp)
- .endif
-.endm
-
-.macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
-#ifdef FPU_EMU_DEBUG
- .data
-.Lpdata\@:
- .string "\string"
- .previous
-
- movem.l %d0/%d1/%a0/%a1,-(%sp)
- .if \bit+1
-#if 0
- moveq #\bit,%d0
- andw #7,%d0
- btst %d0,fp_debugprint+((31-\bit)/8)
-#else
- btst #\bit,fp_debugprint+((31-\bit)/8)
-#endif
- jeq .Lpskip\@
- .endif
- movestack \nr,\arg1,\arg2,\arg3,\arg4,\arg5
- pea .Lpdata\@
- jsr printk
- lea ((\nr+1)*4,%sp),%sp
-.Lpskip\@:
- movem.l (%sp)+,%d0/%d1/%a0/%a1
-#endif
-.endm
-
-.macro printx bit,fp
-#ifdef FPU_EMU_DEBUG
- movem.l %d0/%a0,-(%sp)
- lea \fp,%a0
-#if 0
- moveq #'+',%d0
- tst.w (%a0)
- jeq .Lx1\@
- moveq #'-',%d0
-.Lx1\@: printf \bit," %c",1,%d0
- move.l (4,%a0),%d0
- bclr #31,%d0
- jne .Lx2\@
- printf \bit,"0."
- jra .Lx3\@
-.Lx2\@: printf \bit,"1."
-.Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8)
- move.w (2,%a0),%d0
- ext.l %d0
- printf \bit,"E%04x",1,%d0
-#else
- printf \bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8)
-#endif
- movem.l (%sp)+,%d0/%a0
-#endif
-.endm
-
-.macro debug instr,args
-#ifdef FPU_EMU_DEBUG
- \instr \args
-#endif
-.endm
-
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_FRV_MATH_EMU_H */
-
diff --git a/arch/frv/include/asm/mb-regs.h b/arch/frv/include/asm/mb-regs.h
deleted file mode 100644
index 219e5f926f18..000000000000
--- a/arch/frv/include/asm/mb-regs.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* mb-regs.h: motherboard registers
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB_REGS_H
-#define _ASM_MB_REGS_H
-
-#include <asm/cpu-irqs.h>
-#include <asm/sections.h>
-#include <asm/mem-layout.h>
-
-#ifndef __ASSEMBLY__
-/* gcc builtins, annotated */
-
-unsigned long __builtin_read8(volatile void __iomem *);
-unsigned long __builtin_read16(volatile void __iomem *);
-unsigned long __builtin_read32(volatile void __iomem *);
-void __builtin_write8(volatile void __iomem *, unsigned char);
-void __builtin_write16(volatile void __iomem *, unsigned short);
-void __builtin_write32(volatile void __iomem *, unsigned long);
-#endif
-
-#define __region_IO KERNEL_IO_START /* the region from 0xe0000000 to 0xffffffff has suitable
- * protection laid over the top for use in memory-mapped
- * I/O
- */
-
-#define __region_CS0 0xff000000 /* Boot ROMs area */
-
-#ifdef CONFIG_MB93091_VDK
-/*
- * VDK motherboard and CPU card specific stuff
- */
-
-#include <asm/mb93091-fpga-irqs.h>
-
-#define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0
-#define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1
-
-#define __region_CS2 0xe0000000 /* SLBUS/PCI I/O space */
-#define __region_CS2_M 0x0fffffff /* mask */
-#define __region_CS2_C 0x00000000 /* control */
-#define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */
-#define __region_CS5_M 0x00ffffff
-#define __region_CS5_C 0x00010000
-#define __region_CS7 0xf1000000 /* CB70 CPU-card PCMCIA port I/O space */
-#define __region_CS7_M 0x00ffffff
-#define __region_CS7_C 0x00410701
-#define __region_CS1 0xfc000000 /* SLBUS/PCI bridge control registers */
-#define __region_CS1_M 0x000fffff
-#define __region_CS1_C 0x00000000
-#define __region_CS6 0xfc100000 /* CB70 CPU-card DM9000 LAN I/O space */
-#define __region_CS6_M 0x000fffff
-#define __region_CS6_C 0x00400707
-#define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
-#define __region_CS3_M 0x000fffff
-#define __region_CS3_C 0xc8100000
-#define __region_CS4 0xfd000000 /* CB70 CPU-card extra flash space */
-#define __region_CS4_M 0x00ffffff
-#define __region_CS4_C 0x00000f07
-
-#define __region_PCI_IO (__region_CS2 + 0x04000000UL)
-#define __region_PCI_MEM (__region_CS2 + 0x08000000UL)
-#define __flush_PCI_writes() \
-do { \
- __builtin_write8((volatile void __iomem *) __region_PCI_MEM, 0); \
-} while(0)
-
-#define __is_PCI_IO(addr) \
- (((unsigned long)(addr) >> 24) - (__region_PCI_IO >> 24) < (0x04000000UL >> 24))
-
-#define __is_PCI_MEM(addr) \
- ((unsigned long)(addr) - __region_PCI_MEM < 0x08000000UL)
-
-#define __is_PCI_addr(addr) \
- ((unsigned long)(addr) - __region_PCI_IO < 0x0c000000UL)
-
-#define __get_CLKSW() ({ *(volatile unsigned long *)(__region_CS2 + 0x0130000cUL) & 0xffUL; })
-#define __get_CLKIN() (__get_CLKSW() * 125U * 100000U / 24U)
-
-#ifndef __ASSEMBLY__
-extern int __nongprelbss mb93090_mb00_detected;
-#endif
-
-#define __addr_LEDS() (__region_CS2 + 0x01200004UL)
-#ifdef CONFIG_MB93090_MB00
-#define __set_LEDS(X) \
-do { \
- if (mb93090_mb00_detected) \
- __builtin_write32((void __iomem *) __addr_LEDS(), ~(X)); \
-} while (0)
-#else
-#define __set_LEDS(X)
-#endif
-
-#define __addr_LCD() (__region_CS2 + 0x01200008UL)
-#define __get_LCD(B) __builtin_read32((volatile void __iomem *) (B))
-#define __set_LCD(B,X) __builtin_write32((volatile void __iomem *) (B), (X))
-
-#define LCD_D 0x000000ff /* LCD data bus */
-#define LCD_RW 0x00000100 /* LCD R/W signal */
-#define LCD_RS 0x00000200 /* LCD Register Select */
-#define LCD_E 0x00000400 /* LCD Start Enable Signal */
-
-#define LCD_CMD_CLEAR (LCD_E|0x001)
-#define LCD_CMD_HOME (LCD_E|0x002)
-#define LCD_CMD_CURSOR_INC (LCD_E|0x004)
-#define LCD_CMD_SCROLL_INC (LCD_E|0x005)
-#define LCD_CMD_CURSOR_DEC (LCD_E|0x006)
-#define LCD_CMD_SCROLL_DEC (LCD_E|0x007)
-#define LCD_CMD_OFF (LCD_E|0x008)
-#define LCD_CMD_ON(CRSR,BLINK) (LCD_E|0x00c|(CRSR<<1)|BLINK)
-#define LCD_CMD_CURSOR_MOVE_L (LCD_E|0x010)
-#define LCD_CMD_CURSOR_MOVE_R (LCD_E|0x014)
-#define LCD_CMD_DISPLAY_SHIFT_L (LCD_E|0x018)
-#define LCD_CMD_DISPLAY_SHIFT_R (LCD_E|0x01c)
-#define LCD_CMD_FUNCSET(DL,N,F) (LCD_E|0x020|(DL<<4)|(N<<3)|(F<<2))
-#define LCD_CMD_SET_CG_ADDR(X) (LCD_E|0x040|X)
-#define LCD_CMD_SET_DD_ADDR(X) (LCD_E|0x080|X)
-#define LCD_CMD_READ_BUSY (LCD_E|LCD_RW)
-#define LCD_DATA_WRITE(X) (LCD_E|LCD_RS|(X))
-#define LCD_DATA_READ (LCD_E|LCD_RS|LCD_RW)
-
-#else
-/*
- * PDK unit specific stuff
- */
-
-#include <asm/mb93093-fpga-irqs.h>
-
-#define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0
-#define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1
-
-#define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */
-#define __region_CS5_M 0x00ffffff /* mask */
-#define __region_CS5_C 0x00010000 /* control */
-#define __region_CS2 0x20000000 /* FPGA registers */
-#define __region_CS2_M 0x000fffff
-#define __region_CS2_C 0x00000000
-#define __region_CS1 0xfc100000 /* LAN registers */
-#define __region_CS1_M 0x000fffff
-#define __region_CS1_C 0x00010404
-#define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
-#define __region_CS3_M 0x000fffff
-#define __region_CS3_C 0xc8000000
-#define __region_CS4 0xfd000000 /* extra ROMs area */
-#define __region_CS4_M 0x00ffffff
-#define __region_CS4_C 0x00000f07
-
-#define __region_CS6 0xfe000000 /* not used - hide behind CPU resource I/O regs */
-#define __region_CS6_M 0x000fffff
-#define __region_CS6_C 0x00000f07
-#define __region_CS7 0xfe000000 /* not used - hide behind CPU resource I/O regs */
-#define __region_CS7_M 0x000fffff
-#define __region_CS7_C 0x00000f07
-
-#define __is_PCI_IO(addr) 0 /* no PCI */
-#define __is_PCI_MEM(addr) 0
-#define __is_PCI_addr(addr) 0
-#define __region_PCI_IO 0
-#define __region_PCI_MEM 0
-#define __flush_PCI_writes() do { } while(0)
-
-#define __get_CLKSW() 0UL
-#define __get_CLKIN() 66000000UL
-
-#define __addr_LEDS() (__region_CS2 + 0x00000023UL)
-#define __set_LEDS(X) __builtin_write8((volatile void __iomem *) __addr_LEDS(), (X))
-
-#define __addr_FPGATR() (__region_CS2 + 0x00000030UL)
-#define __set_FPGATR(X) __builtin_write32((volatile void __iomem *) __addr_FPGATR(), (X))
-#define __get_FPGATR() __builtin_read32((volatile void __iomem *) __addr_FPGATR())
-
-#define MB93093_FPGA_FPGATR_AUDIO_CLK 0x00000003
-
-#define __set_FPGATR_AUDIO_CLK(V) \
- __set_FPGATR((__get_FPGATR() & ~MB93093_FPGA_FPGATR_AUDIO_CLK) | (V))
-
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_OFF 0x0
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_11MHz 0x1
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_12MHz 0x2
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_02MHz 0x3
-
-#define MB93093_FPGA_SWR_PUSHSWMASK (0x1F<<26)
-#define MB93093_FPGA_SWR_PUSHSW4 (1<<29)
-
-#define __addr_FPGA_SWR ((volatile void __iomem *)(__region_CS2 + 0x28UL))
-#define __get_FPGA_PUSHSW1_5() (__builtin_read32(__addr_FPGA_SWR) & MB93093_FPGA_SWR_PUSHSWMASK)
-
-
-#endif
-
-#endif /* _ASM_MB_REGS_H */
diff --git a/arch/frv/include/asm/mb86943a.h b/arch/frv/include/asm/mb86943a.h
deleted file mode 100644
index e87ef924bfb4..000000000000
--- a/arch/frv/include/asm/mb86943a.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mb86943a.h: MB86943 SPARClite <-> PCI bridge registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB86943A_H
-#define _ASM_MB86943A_H
-
-#include <asm/mb-regs.h>
-
-#define __reg_MB86943_sl_ctl *(volatile uint32_t *) (__region_CS1 + 0x00)
-
-#define MB86943_SL_CTL_BUS_WIDTH_64 0x00000001
-#define MB86943_SL_CTL_AS_HOST 0x00000002
-#define MB86943_SL_CTL_DRCT_MASTER_SWAP 0x00000004
-#define MB86943_SL_CTL_DRCT_SLAVE_SWAP 0x00000008
-#define MB86943_SL_CTL_PCI_CONFIG_SWAP 0x00000010
-#define MB86943_SL_CTL_ECS0_ENABLE 0x00000020
-#define MB86943_SL_CTL_ECS1_ENABLE 0x00000040
-#define MB86943_SL_CTL_ECS2_ENABLE 0x00000080
-
-#define __reg_MB86943_ecs_ctl(N) *(volatile uint32_t *) (__region_CS1 + 0x08 + (0x08*(N)))
-#define __reg_MB86943_ecs_range(N) *(volatile uint32_t *) (__region_CS1 + 0x20 + (0x10*(N)))
-#define __reg_MB86943_ecs_base(N) *(volatile uint32_t *) (__region_CS1 + 0x28 + (0x10*(N)))
-
-#define __reg_MB86943_sl_pci_io_range *(volatile uint32_t *) (__region_CS1 + 0x50)
-#define __reg_MB86943_sl_pci_io_base *(volatile uint32_t *) (__region_CS1 + 0x58)
-#define __reg_MB86943_sl_pci_mem_range *(volatile uint32_t *) (__region_CS1 + 0x60)
-#define __reg_MB86943_sl_pci_mem_base *(volatile uint32_t *) (__region_CS1 + 0x68)
-#define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70)
-#define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78)
-
-#define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014)
-#define MB86943_PCIARB_EN 0x00000001
-
-#endif /* _ASM_MB86943A_H */
diff --git a/arch/frv/include/asm/mb93091-fpga-irqs.h b/arch/frv/include/asm/mb93091-fpga-irqs.h
deleted file mode 100644
index 19778c5ba9d6..000000000000
--- a/arch/frv/include/asm/mb93091-fpga-irqs.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mb93091-fpga-irqs.h: MB93091 CPU board FPGA IRQs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93091_FPGA_IRQS_H
-#define _ASM_MB93091_FPGA_IRQS_H
-
-#include <asm/irq.h>
-
-#ifndef __ASSEMBLY__
-
-/* IRQ IDs presented to drivers */
-enum {
- IRQ_FPGA__UNUSED = IRQ_BASE_FPGA,
- IRQ_FPGA_SYSINT_BUS_EXPANSION_1,
- IRQ_FPGA_SL_BUS_EXPANSION_2,
- IRQ_FPGA_PCI_INTD,
- IRQ_FPGA_PCI_INTC,
- IRQ_FPGA_PCI_INTB,
- IRQ_FPGA_PCI_INTA,
- IRQ_FPGA_SL_BUS_EXPANSION_7,
- IRQ_FPGA_SYSINT_BUS_EXPANSION_8,
- IRQ_FPGA_SL_BUS_EXPANSION_9,
- IRQ_FPGA_MB86943_PCI_INTA,
- IRQ_FPGA_MB86943_SLBUS_SIDE,
- IRQ_FPGA_RTL8029_INTA,
- IRQ_FPGA_SYSINT_BUS_EXPANSION_13,
- IRQ_FPGA_SL_BUS_EXPANSION_14,
- IRQ_FPGA_NMI,
-};
-
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MB93091_FPGA_IRQS_H */
diff --git a/arch/frv/include/asm/mb93093-fpga-irqs.h b/arch/frv/include/asm/mb93093-fpga-irqs.h
deleted file mode 100644
index 590266b1a6d3..000000000000
--- a/arch/frv/include/asm/mb93093-fpga-irqs.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* mb93093-fpga-irqs.h: MB93093 CPU board FPGA IRQs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93093_FPGA_IRQS_H
-#define _ASM_MB93093_FPGA_IRQS_H
-
-#include <asm/irq.h>
-
-#ifndef __ASSEMBLY__
-
-/* IRQ IDs presented to drivers */
-enum {
- IRQ_FPGA_PUSH_BUTTON_SW1_5 = IRQ_BASE_FPGA + 8,
- IRQ_FPGA_ROCKER_C_SW8 = IRQ_BASE_FPGA + 9,
- IRQ_FPGA_ROCKER_C_SW9 = IRQ_BASE_FPGA + 10,
-};
-
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MB93093_FPGA_IRQS_H */
diff --git a/arch/frv/include/asm/mb93493-irqs.h b/arch/frv/include/asm/mb93493-irqs.h
deleted file mode 100644
index 82c7aeddd333..000000000000
--- a/arch/frv/include/asm/mb93493-irqs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* mb93493-irqs.h: MB93493 companion chip IRQs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93493_IRQS_H
-#define _ASM_MB93493_IRQS_H
-
-#include <asm/irq.h>
-
-#ifndef __ASSEMBLY__
-
-/* IRQ IDs presented to drivers */
-enum {
- IRQ_MB93493_VDC = IRQ_BASE_MB93493 + 0,
- IRQ_MB93493_VCC = IRQ_BASE_MB93493 + 1,
- IRQ_MB93493_AUDIO_OUT = IRQ_BASE_MB93493 + 2,
- IRQ_MB93493_I2C_0 = IRQ_BASE_MB93493 + 3,
- IRQ_MB93493_I2C_1 = IRQ_BASE_MB93493 + 4,
- IRQ_MB93493_USB = IRQ_BASE_MB93493 + 5,
- IRQ_MB93493_LOCAL_BUS = IRQ_BASE_MB93493 + 7,
- IRQ_MB93493_PCMCIA = IRQ_BASE_MB93493 + 8,
- IRQ_MB93493_GPIO = IRQ_BASE_MB93493 + 9,
- IRQ_MB93493_AUDIO_IN = IRQ_BASE_MB93493 + 10,
-};
-
-/* IRQ multiplexor mappings */
-#define ROUTE_VIA_IRQ0 0 /* route IRQ by way of CPU external IRQ 0 */
-#define ROUTE_VIA_IRQ1 1 /* route IRQ by way of CPU external IRQ 1 */
-
-#define IRQ_MB93493_VDC_ROUTE ROUTE_VIA_IRQ0
-#define IRQ_MB93493_VCC_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_AUDIO_OUT_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_I2C_0_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_I2C_1_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_USB_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_LOCAL_BUS_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_PCMCIA_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_GPIO_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_AUDIO_IN_ROUTE ROUTE_VIA_IRQ1
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MB93493_IRQS_H */
diff --git a/arch/frv/include/asm/mb93493-regs.h b/arch/frv/include/asm/mb93493-regs.h
deleted file mode 100644
index 8a1f6aac8cf1..000000000000
--- a/arch/frv/include/asm/mb93493-regs.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/* mb93493-regs.h: MB93493 companion chip registers
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93493_REGS_H
-#define _ASM_MB93493_REGS_H
-
-#include <asm/mb-regs.h>
-#include <asm/mb93493-irqs.h>
-
-#define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X)))
-#define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); })
-
-#define __set_MB93493(X,V) \
-do { \
- *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \
-} while(0)
-
-#define __get_MB93493_STSR(X) __get_MB93493(0x3c0 + (X) * 4)
-#define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V))
-#define MB93493_STSR_EN
-
-#define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4)
-#define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4)
-#define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V))
-
-#define __get_MB93493_DQSR(X) __get_MB93493(0x3e0 + (X) * 4)
-#define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V))
-
-#define __get_MB93493_LBSER() __get_MB93493(0x3f0)
-#define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V))
-
-#define MB93493_LBSER_VDC 0x00010000
-#define MB93493_LBSER_VCC 0x00020000
-#define MB93493_LBSER_AUDIO 0x00040000
-#define MB93493_LBSER_I2C_0 0x00080000
-#define MB93493_LBSER_I2C_1 0x00100000
-#define MB93493_LBSER_USB 0x00200000
-#define MB93493_LBSER_GPIO 0x00800000
-#define MB93493_LBSER_PCMCIA 0x01000000
-
-#define __get_MB93493_LBSR() __get_MB93493(0x3fc)
-#define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V))
-
-/*
- * video display controller
- */
-#define __get_MB93493_VDC(X) __get_MB93493(MB93493_VDC_##X)
-#define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V))
-
-#define MB93493_VDC_RCURSOR 0x140 /* cursor position */
-#define MB93493_VDC_RCT1 0x144 /* cursor colour 1 */
-#define MB93493_VDC_RCT2 0x148 /* cursor colour 2 */
-#define MB93493_VDC_RHDC 0x150 /* horizontal display period */
-#define MB93493_VDC_RH_MARGINS 0x154 /* horizontal margin sizes */
-#define MB93493_VDC_RVDC 0x158 /* vertical display period */
-#define MB93493_VDC_RV_MARGINS 0x15c /* vertical margin sizes */
-#define MB93493_VDC_RC 0x170 /* VDC control */
-#define MB93493_VDC_RCLOCK 0x174 /* clock divider, DMA req delay */
-#define MB93493_VDC_RBLACK 0x178 /* black insert sizes */
-#define MB93493_VDC_RS 0x17c /* VDC status */
-
-#define __addr_MB93493_VDC_BCI(X) ({ (volatile unsigned long *)(__region_CS3 + 0x000 + (X)); })
-#define __addr_MB93493_VDC_TPO(X) (__region_CS3 + 0x1c0 + (X))
-
-#define VDC_TPO_WIDTH 32
-
-#define VDC_RC_DSR 0x00000080 /* VDC master reset */
-
-#define VDC_RS_IT 0x00060000 /* interrupt indicators */
-#define VDC_RS_IT_UNDERFLOW 0x00040000 /* - underflow event */
-#define VDC_RS_IT_VSYNC 0x00020000 /* - VSYNC event */
-#define VDC_RS_DFI 0x00010000 /* current interlace field number */
-#define VDC_RS_DFI_TOP 0x00000000 /* - top field */
-#define VDC_RS_DFI_BOTTOM 0x00010000 /* - bottom field */
-#define VDC_RS_DCSR 0x00000010 /* cursor state */
-#define VDC_RS_DCM 0x00000003 /* display mode */
-#define VDC_RS_DCM_DISABLED 0x00000000 /* - display disabled */
-#define VDC_RS_DCM_STOPPED 0x00000001 /* - VDC stopped */
-#define VDC_RS_DCM_FREERUNNING 0x00000002 /* - VDC free-running */
-#define VDC_RS_DCM_TRANSFERRING 0x00000003 /* - data being transferred to VDC */
-
-/*
- * video capture controller
- */
-#define __get_MB93493_VCC(X) __get_MB93493(MB93493_VCC_##X)
-#define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V))
-
-#define MB93493_VCC_RREDUCT 0x104 /* reduction rate */
-#define MB93493_VCC_RHY 0x108 /* horizontal brightness filter coefficients */
-#define MB93493_VCC_RHC 0x10c /* horizontal colour-difference filter coefficients */
-#define MB93493_VCC_RHSIZE 0x110 /* horizontal cycle sizes */
-#define MB93493_VCC_RHBC 0x114 /* horizontal back porch size */
-#define MB93493_VCC_RVCC 0x118 /* vertical capture period */
-#define MB93493_VCC_RVBC 0x11c /* vertical back porch period */
-#define MB93493_VCC_RV 0x120 /* vertical filter coefficients */
-#define MB93493_VCC_RDTS 0x128 /* DMA transfer size */
-#define MB93493_VCC_RDTS_4B 0x01000000 /* 4-byte transfer */
-#define MB93493_VCC_RDTS_32B 0x03000000 /* 32-byte transfer */
-#define MB93493_VCC_RDTS_SHIFT 24
-#define MB93493_VCC_RCC 0x130 /* VCC control */
-#define MB93493_VCC_RIS 0x134 /* VCC interrupt status */
-
-#define __addr_MB93493_VCC_TPI(X) (__region_CS3 + 0x180 + (X))
-
-#define VCC_RHSIZE_RHCC 0x000007ff
-#define VCC_RHSIZE_RHCC_SHIFT 0
-#define VCC_RHSIZE_RHTCC 0x0fff0000
-#define VCC_RHSIZE_RHTCC_SHIFT 16
-
-#define VCC_RVBC_RVBC 0x00003f00
-#define VCC_RVBC_RVBC_SHIFT 8
-
-#define VCC_RREDUCT_RHR 0x07ff0000
-#define VCC_RREDUCT_RHR_SHIFT 16
-#define VCC_RREDUCT_RVR 0x000007ff
-#define VCC_RREDUCT_RVR_SHIFT 0
-
-#define VCC_RCC_CE 0x00000001 /* VCC enable */
-#define VCC_RCC_CS 0x00000002 /* request video capture start */
-#define VCC_RCC_CPF 0x0000000c /* pixel format */
-#define VCC_RCC_CPF_YCBCR_16 0x00000000 /* - YCbCr 4:2:2 16-bit format */
-#define VCC_RCC_CPF_RGB 0x00000004 /* - RGB 4:4:4 format */
-#define VCC_RCC_CPF_YCBCR_24 0x00000008 /* - YCbCr 4:2:2 24-bit format */
-#define VCC_RCC_CPF_BT656 0x0000000c /* - ITU R-BT.656 format */
-#define VCC_RCC_CPF_SHIFT 2
-#define VCC_RCC_CSR 0x00000080 /* request reset */
-#define VCC_RCC_HSIP 0x00000100 /* HSYNC polarity */
-#define VCC_RCC_HSIP_LOACT 0x00000000 /* - low active */
-#define VCC_RCC_HSIP_HIACT 0x00000100 /* - high active */
-#define VCC_RCC_VSIP 0x00000200 /* VSYNC polarity */
-#define VCC_RCC_VSIP_LOACT 0x00000000 /* - low active */
-#define VCC_RCC_VSIP_HIACT 0x00000200 /* - high active */
-#define VCC_RCC_CIE 0x00000800 /* interrupt enable */
-#define VCC_RCC_CFP 0x00001000 /* RGB pixel packing */
-#define VCC_RCC_CFP_4TO3 0x00000000 /* - pack 4 pixels into 3 words */
-#define VCC_RCC_CFP_1TO1 0x00001000 /* - pack 1 pixel into 1 words */
-#define VCC_RCC_CSM 0x00006000 /* interlace specification */
-#define VCC_RCC_CSM_ONEPASS 0x00002000 /* - non-interlaced */
-#define VCC_RCC_CSM_INTERLACE 0x00004000 /* - interlaced */
-#define VCC_RCC_CSM_SHIFT 13
-#define VCC_RCC_ES 0x00008000 /* capture start polarity */
-#define VCC_RCC_ES_NEG 0x00000000 /* - negative edge */
-#define VCC_RCC_ES_POS 0x00008000 /* - positive edge */
-#define VCC_RCC_IFI 0x00080000 /* inferlace field evaluation reverse */
-#define VCC_RCC_FDTS 0x00300000 /* interlace field start */
-#define VCC_RCC_FDTS_3_8 0x00000000 /* - 3/8 of horizontal entire cycle */
-#define VCC_RCC_FDTS_1_4 0x00100000 /* - 1/4 of horizontal entire cycle */
-#define VCC_RCC_FDTS_7_16 0x00200000 /* - 7/16 of horizontal entire cycle */
-#define VCC_RCC_FDTS_SHIFT 20
-#define VCC_RCC_MOV 0x00400000 /* test bit - always set to 1 */
-#define VCC_RCC_STP 0x00800000 /* request video capture stop */
-#define VCC_RCC_TO 0x01000000 /* input during top-field only */
-
-#define VCC_RIS_VSYNC 0x01000000 /* VSYNC interrupt */
-#define VCC_RIS_OV 0x02000000 /* overflow interrupt */
-#define VCC_RIS_BOTTOM 0x08000000 /* interlace bottom field */
-#define VCC_RIS_STARTED 0x10000000 /* capture started */
-
-/*
- * I2C
- */
-#define MB93493_I2C_BSR 0x340 /* bus status */
-#define MB93493_I2C_BCR 0x344 /* bus control */
-#define MB93493_I2C_CCR 0x348 /* clock control */
-#define MB93493_I2C_ADR 0x34c /* address */
-#define MB93493_I2C_DTR 0x350 /* data */
-#define MB93493_I2C_BC2R 0x35c /* bus control 2 */
-
-#define __addr_MB93493_I2C(port,X) (__region_CS3 + MB93493_I2C_##X + ((port)*0x20))
-#define __get_MB93493_I2C(port,X) __get_MB93493(MB93493_I2C_##X + ((port)*0x20))
-#define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V))
-
-#define I2C_BSR_BB (1 << 7)
-
-/*
- * audio controller (I2S) registers
- */
-#define __get_MB93493_I2S(X) __get_MB93493(MB93493_I2S_##X)
-#define __set_MB93493_I2S(X,V) __set_MB93493(MB93493_I2S_##X, (V))
-
-#define MB93493_I2S_ALDR 0x300 /* L-channel data */
-#define MB93493_I2S_ARDR 0x304 /* R-channel data */
-#define MB93493_I2S_APDR 0x308 /* 16-bit packed data */
-#define MB93493_I2S_AISTR 0x310 /* status */
-#define MB93493_I2S_AICR 0x314 /* control */
-
-#define __addr_MB93493_I2S_ALDR(X) (__region_CS3 + MB93493_I2S_ALDR + (X))
-#define __addr_MB93493_I2S_ARDR(X) (__region_CS3 + MB93493_I2S_ARDR + (X))
-#define __addr_MB93493_I2S_APDR(X) (__region_CS3 + MB93493_I2S_APDR + (X))
-#define __addr_MB93493_I2S_ADR(X) (__region_CS3 + 0x320 + (X))
-
-#define I2S_AISTR_OTST 0x00000003 /* status of output data transfer */
-#define I2S_AISTR_OTR 0x00000010 /* output transfer request pending */
-#define I2S_AISTR_OUR 0x00000020 /* output FIFO underrun detected */
-#define I2S_AISTR_OOR 0x00000040 /* output FIFO overrun detected */
-#define I2S_AISTR_ODS 0x00000100 /* output DMA transfer size */
-#define I2S_AISTR_ODE 0x00000400 /* output DMA transfer request enable */
-#define I2S_AISTR_OTRIE 0x00001000 /* output transfer request interrupt enable */
-#define I2S_AISTR_OURIE 0x00002000 /* output FIFO underrun interrupt enable */
-#define I2S_AISTR_OORIE 0x00004000 /* output FIFO overrun interrupt enable */
-#define I2S_AISTR__OUT_MASK 0x00007570
-#define I2S_AISTR_ITST 0x00030000 /* status of input data transfer */
-#define I2S_AISTR_ITST_SHIFT 16
-#define I2S_AISTR_ITR 0x00100000 /* input transfer request pending */
-#define I2S_AISTR_IUR 0x00200000 /* input FIFO underrun detected */
-#define I2S_AISTR_IOR 0x00400000 /* input FIFO overrun detected */
-#define I2S_AISTR_IDS 0x01000000 /* input DMA transfer size */
-#define I2S_AISTR_IDE 0x04000000 /* input DMA transfer request enable */
-#define I2S_AISTR_ITRIE 0x10000000 /* input transfer request interrupt enable */
-#define I2S_AISTR_IURIE 0x20000000 /* input FIFO underrun interrupt enable */
-#define I2S_AISTR_IORIE 0x40000000 /* input FIFO overrun interrupt enable */
-#define I2S_AISTR__IN_MASK 0x75700000
-
-#define I2S_AICR_MI 0x00000001 /* mono input requested */
-#define I2S_AICR_AMI 0x00000002 /* relation between LRCKI/FS1 and SDI */
-#define I2S_AICR_LRI 0x00000004 /* function of LRCKI pin */
-#define I2S_AICR_SDMI 0x00000070 /* format of input audio data */
-#define I2S_AICR_SDMI_SHIFT 4
-#define I2S_AICR_CLI 0x00000080 /* input FIFO clearing control */
-#define I2S_AICR_IM 0x00000300 /* input state control */
-#define I2S_AICR_IM_SHIFT 8
-#define I2S_AICR__IN_MASK 0x000003f7
-#define I2S_AICR_MO 0x00001000 /* mono output requested */
-#define I2S_AICR_AMO 0x00002000 /* relation between LRCKO/FS0 and SDO */
-#define I2S_AICR_AMO_SHIFT 13
-#define I2S_AICR_LRO 0x00004000 /* function of LRCKO pin */
-#define I2S_AICR_SDMO 0x00070000 /* format of output audio data */
-#define I2S_AICR_SDMO_SHIFT 16
-#define I2S_AICR_CLO 0x00080000 /* output FIFO clearing control */
-#define I2S_AICR_OM 0x00100000 /* output state control */
-#define I2S_AICR__OUT_MASK 0x001f7000
-#define I2S_AICR_DIV 0x03000000 /* frequency division rate */
-#define I2S_AICR_DIV_SHIFT 24
-#define I2S_AICR_FL 0x20000000 /* frame length */
-#define I2S_AICR_FS 0x40000000 /* frame sync method */
-#define I2S_AICR_ME 0x80000000 /* master enable */
-
-/*
- * PCMCIA
- */
-#define __addr_MB93493_PCMCIA(X) ((volatile unsigned long *)(__region_CS5 + (X)))
-
-/*
- * GPIO
- */
-#define __get_MB93493_GPIO_PDR(X) __get_MB93493(0x380 + (X) * 0xc0)
-#define __set_MB93493_GPIO_PDR(X,V) __set_MB93493(0x380 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_GPDR(X) __get_MB93493(0x384 + (X) * 0xc0)
-#define __set_MB93493_GPIO_GPDR(X,V) __set_MB93493(0x384 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_SIR(X) __get_MB93493(0x388 + (X) * 0xc0)
-#define __set_MB93493_GPIO_SIR(X,V) __set_MB93493(0x388 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_SOR(X) __get_MB93493(0x38c + (X) * 0xc0)
-#define __set_MB93493_GPIO_SOR(X,V) __set_MB93493(0x38c + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_PDSR(X) __get_MB93493(0x390 + (X) * 0xc0)
-#define __set_MB93493_GPIO_PDSR(X,V) __set_MB93493(0x390 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_PDCR(X) __get_MB93493(0x394 + (X) * 0xc0)
-#define __set_MB93493_GPIO_PDCR(X,V) __set_MB93493(0x394 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_INTST(X) __get_MB93493(0x398 + (X) * 0xc0)
-#define __set_MB93493_GPIO_INTST(X,V) __set_MB93493(0x398 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_IEHL(X) __get_MB93493(0x39c + (X) * 0xc0)
-#define __set_MB93493_GPIO_IEHL(X,V) __set_MB93493(0x39c + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_IELH(X) __get_MB93493(0x3a0 + (X) * 0xc0)
-#define __set_MB93493_GPIO_IELH(X,V) __set_MB93493(0x3a0 + (X) * 0xc0, (V))
-
-#endif /* _ASM_MB93493_REGS_H */
diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h
deleted file mode 100644
index e9a0ec85a402..000000000000
--- a/arch/frv/include/asm/mem-layout.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* mem-layout.h: memory layout
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MEM_LAYOUT_H
-#define _ASM_MEM_LAYOUT_H
-
-#ifndef __ASSEMBLY__
-#define __UL(X) ((unsigned long) (X))
-#else
-#define __UL(X) (X)
-#endif
-
-/*
- * PAGE_SHIFT determines the page size
- */
-#define PAGE_SHIFT 14
-
-#ifndef __ASSEMBLY__
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE (1 << PAGE_SHIFT)
-#endif
-
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-/*
- * the slab must be aligned such that load- and store-double instructions don't
- * fault if used
- */
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
-
-/*****************************************************************************/
-/*
- * virtual memory layout from kernel's point of view
- */
-#define PAGE_OFFSET ((unsigned long) &__page_offset)
-
-#ifdef CONFIG_MMU
-
-/* see Documentation/frv/mmu-layout.txt */
-#define KERNEL_LOWMEM_START __UL(0xc0000000)
-#define KERNEL_LOWMEM_END __UL(0xd0000000)
-#define VMALLOC_START __UL(0xd0000000)
-#define VMALLOC_END __UL(0xd8000000)
-#define PKMAP_BASE __UL(0xd8000000)
-#define PKMAP_END __UL(0xdc000000)
-#define KMAP_ATOMIC_SECONDARY_FRAME __UL(0xdc000000)
-#define KMAP_ATOMIC_PRIMARY_FRAME __UL(0xdd000000)
-
-#endif
-
-#define KERNEL_IO_START __UL(0xe0000000)
-
-
-/*****************************************************************************/
-/*
- * memory layout from userspace's point of view
- */
-#define BRK_BASE __UL(2 * 1024 * 1024 + PAGE_SIZE)
-#define STACK_TOP __UL(2 * 1024 * 1024)
-#define STACK_TOP_MAX __UL(0xc0000000)
-
-/* userspace process size */
-#ifdef CONFIG_MMU
-#define TASK_SIZE (PAGE_OFFSET)
-#else
-#define TASK_SIZE __UL(0xFFFFFFFFUL)
-#endif
-
-/* base of area at which unspecified mmaps will start */
-#ifdef CONFIG_BINFMT_ELF_FDPIC
-#define TASK_UNMAPPED_BASE __UL(16 * 1024 * 1024)
-#else
-#define TASK_UNMAPPED_BASE __UL(TASK_SIZE / 3)
-#endif
-
-#endif /* _ASM_MEM_LAYOUT_H */
diff --git a/arch/frv/include/asm/mmu.h b/arch/frv/include/asm/mmu.h
deleted file mode 100644
index 86ca0e86e7d2..000000000000
--- a/arch/frv/include/asm/mmu.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* mmu.h: memory management context for FR-V with or without MMU support
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_MMU_H
-#define _ASM_MMU_H
-
-typedef struct {
-#ifdef CONFIG_MMU
- struct list_head id_link; /* link in list of context ID owners */
- unsigned short id; /* MMU context ID */
- unsigned short id_busy; /* true if ID is in CXNR */
- unsigned long itlb_cached_pge; /* [SCR0] PGE cached for insn TLB handler */
- unsigned long itlb_ptd_mapping; /* [DAMR4] PTD mapping for itlb cached PGE */
- unsigned long dtlb_cached_pge; /* [SCR1] PGE cached for data TLB handler */
- unsigned long dtlb_ptd_mapping; /* [DAMR5] PTD mapping for dtlb cached PGE */
-
-#else
- unsigned long end_brk;
-
-#endif
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
- unsigned long exec_fdpic_loadmap;
- unsigned long interp_fdpic_loadmap;
-#endif
-
-} mm_context_t;
-
-#ifdef CONFIG_MMU
-extern int __nongpreldata cxn_pinned;
-extern int cxn_pin_by_pid(pid_t pid);
-#endif
-
-#endif /* _ASM_MMU_H */
diff --git a/arch/frv/include/asm/mmu_context.h b/arch/frv/include/asm/mmu_context.h
deleted file mode 100644
index c7daa395156a..000000000000
--- a/arch/frv/include/asm/mmu_context.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* mmu_context.h: MMU context management routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MMU_CONTEXT_H
-#define _ASM_MMU_CONTEXT_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#ifdef CONFIG_MMU
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void change_mm_context(mm_context_t *old, mm_context_t *ctx, pgd_t *_pgd);
-extern void destroy_context(struct mm_struct *mm);
-
-#else
-#define init_new_context(tsk, mm) ({ 0; })
-#define change_mm_context(old, ctx, _pml4) do {} while(0)
-#define destroy_context(mm) do {} while(0)
-#endif
-
-#define switch_mm(prev, next, tsk) \
-do { \
- if (prev != next) \
- change_mm_context(&prev->context, &next->context, next->pgd); \
-} while(0)
-
-#define activate_mm(prev, next) \
-do { \
- change_mm_context(&prev->context, &next->context, next->pgd); \
-} while(0)
-
-#define deactivate_mm(tsk, mm) \
-do { \
-} while(0)
-
-#endif
diff --git a/arch/frv/include/asm/module.h b/arch/frv/include/asm/module.h
deleted file mode 100644
index a8848f09a217..000000000000
--- a/arch/frv/include/asm/module.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* module.h: FRV module stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_MODULE_H
-#define _ASM_MODULE_H
-
-#include <asm-generic/module.h>
-
-/*
- * Include the architecture version.
- */
-#define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " "
-
-#endif /* _ASM_MODULE_H */
-
diff --git a/arch/frv/include/asm/page.h b/arch/frv/include/asm/page.h
deleted file mode 100644
index 0f76a0d586f6..000000000000
--- a/arch/frv/include/asm/page.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_PAGE_H
-#define _ASM_PAGE_H
-
-#include <asm/virtconvert.h>
-#include <asm/mem-layout.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-
-#ifndef __ASSEMBLY__
-
-#define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE)
-#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE)
-#define copy_user_page(vto, vfrom, vaddr, topg) memcpy((vto), (vfrom), PAGE_SIZE)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long ste[64];} pmd_t;
-typedef struct { pmd_t pue[1]; } pud_t;
-typedef struct { pud_t pge[1]; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x) ((x).pte)
-#define pmd_val(x) ((x).ste[0])
-#define pud_val(x) ((x).pue[0])
-#define pgd_val(x) ((x).pge[0])
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pmd(x) ((pmd_t) { { (x) } } )
-#define __pud(x) ((pud_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-#define PTE_MASK PAGE_MASK
-
-#define devmem_is_allowed(pfn) 1
-
-#define __pa(vaddr) virt_to_phys((void *) (unsigned long) (vaddr))
-#define __va(paddr) phys_to_virt((unsigned long) (paddr))
-
-#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
-
-extern unsigned long max_low_pfn;
-extern unsigned long min_low_pfn;
-extern unsigned long max_pfn;
-
-#ifdef CONFIG_MMU
-#define pfn_valid(pfn) ((pfn) < max_mapnr)
-#else
-#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
-#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
-
-#endif
-
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _ASM_PAGE_H */
diff --git a/arch/frv/include/asm/pci.h b/arch/frv/include/asm/pci.h
deleted file mode 100644
index 895af9d558ba..000000000000
--- a/arch/frv/include/asm/pci.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* pci.h: FR-V specific PCI declarations
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-m68k/pci.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_FRV_PCI_H
-#define _ASM_FRV_PCI_H
-
-#include <linux/mm.h>
-#include <linux/scatterlist.h>
-#include <asm-generic/pci.h>
-
-#define pcibios_assign_all_busses() 0
-
-#ifdef CONFIG_MMU
-extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
-extern void consistent_free(void *vaddr);
-extern void consistent_sync(void *vaddr, size_t size, int direction);
-extern void consistent_sync_page(struct page *page, unsigned long offset,
- size_t size, int direction);
-#endif
-
-/* Return the index of the PCI controller for device PDEV. */
-#define pci_controller_num(PDEV) (0)
-
-/*
- * These are pretty much arbitrary with the CoMEM implementation.
- * We have the whole address space to ourselves.
- */
-#define PCIBIOS_MIN_IO 0x100
-#define PCIBIOS_MIN_MEM 0x00010000
-
-#endif /* _ASM_FRV_PCI_H */
diff --git a/arch/frv/include/asm/percpu.h b/arch/frv/include/asm/percpu.h
deleted file mode 100644
index 4209fe5fe0a2..000000000000
--- a/arch/frv/include/asm/percpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_PERCPU_H
-#define __ASM_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ASM_PERCPU_H */
diff --git a/arch/frv/include/asm/perf_event.h b/arch/frv/include/asm/perf_event.h
deleted file mode 100644
index c52ea5546b5b..000000000000
--- a/arch/frv/include/asm/perf_event.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* FRV performance event support
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_PERF_EVENT_H
-#define _ASM_PERF_EVENT_H
-
-#endif /* _ASM_PERF_EVENT_H */
diff --git a/arch/frv/include/asm/pgalloc.h b/arch/frv/include/asm/pgalloc.h
deleted file mode 100644
index 416d19a632f2..000000000000
--- a/arch/frv/include/asm/pgalloc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* pgalloc.h: Page allocation routines for FRV
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Derived from:
- * include/asm-m68knommu/pgalloc.h
- * include/asm-i386/pgalloc.h
- */
-#ifndef _ASM_PGALLOC_H
-#define _ASM_PGALLOC_H
-
-#include <asm/setup.h>
-#include <asm/virtconvert.h>
-
-#ifdef CONFIG_MMU
-
-#define pmd_populate_kernel(mm, pmd, pte) __set_pmd(pmd, __pa(pte) | _PAGE_TABLE)
-#define pmd_populate(MM, PMD, PAGE) \
-do { \
- __set_pmd((PMD), page_to_pfn(PAGE) << PAGE_SHIFT | _PAGE_TABLE); \
-} while(0)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-
-extern pgd_t *pgd_alloc(struct mm_struct *);
-extern void pgd_free(struct mm_struct *mm, pgd_t *);
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-
-extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb,pte,address) \
-do { \
- pgtable_page_dtor(pte); \
- tlb_remove_page((tlb),(pte)); \
-} while (0)
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- * (In the PAE case we free the pmds as part of the pgd.)
- */
-#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *) 2); })
-#define pmd_free(mm, x) do { } while (0)
-#define __pmd_free_tlb(tlb,x,a) do { } while (0)
-
-#endif /* CONFIG_MMU */
-
-#endif /* _ASM_PGALLOC_H */
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
deleted file mode 100644
index ab6e7e961b54..000000000000
--- a/arch/frv/include/asm/pgtable.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/* pgtable.h: FR-V page table mangling
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Derived from:
- * include/asm-m68knommu/pgtable.h
- * include/asm-i386/pgtable.h
- */
-
-#ifndef _ASM_PGTABLE_H
-#define _ASM_PGTABLE_H
-
-#include <asm-generic/5level-fixup.h>
-#include <asm/mem-layout.h>
-#include <asm/setup.h>
-#include <asm/processor.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/threads.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-struct vm_area_struct;
-#endif
-
-#ifndef __ASSEMBLY__
-#if defined(CONFIG_HIGHPTE)
-typedef unsigned long pte_addr_t;
-#else
-typedef pte_t *pte_addr_t;
-#endif
-#endif
-
-/*****************************************************************************/
-/*
- * MMU-less operation case first
- */
-#ifndef CONFIG_MMU
-
-#define pgd_present(pgd) (1) /* pages are always present on NO_MM */
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-#define pmd_offset(a, b) ((void *) 0)
-
-#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
-
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define ZERO_PAGE(vaddr) ({ BUG(); NULL; })
-
-#define swapper_pg_dir ((pgd_t *) NULL)
-
-#define pgtable_cache_init() do {} while (0)
-
-#include <asm-generic/pgtable.h>
-
-#else /* !CONFIG_MMU */
-/*****************************************************************************/
-/*
- * then MMU operation
- */
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#ifndef __ASSEMBLY__
-extern unsigned long empty_zero_page;
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-#endif
-
-/*
- * we use 2-level page tables, folding the PMD (mid-level table) into the PGE (top-level entry)
- * [see Documentation/frv/mmu-layout.txt]
- *
- * Page Directory:
- * - Size: 16KB
- * - 64 PGEs per PGD
- * - Each PGE holds 1 PUD and covers 64MB
- *
- * Page Upper Directory:
- * - Size: 256B
- * - 1 PUE per PUD
- * - Each PUE holds 1 PMD and covers 64MB
- *
- * Page Mid-Level Directory
- * - Size: 256B
- * - 1 PME per PMD
- * - Each PME holds 64 STEs, all of which point to separate chunks of the same Page Table
- * - All STEs are instantiated at the same time
- *
- * Page Table
- * - Size: 16KB
- * - 4096 PTEs per PT
- * - Each Linux PT is subdivided into 64 FR451 PT's, each of which holds 64 entries
- *
- * Pages
- * - Size: 4KB
- *
- * total PTEs
- * = 1 PML4E * 64 PGEs * 1 PUEs * 1 PMEs * 4096 PTEs
- * = 1 PML4E * 64 PGEs * 64 STEs * 64 PTEs/FR451-PT
- * = 262144 (or 256 * 1024)
- */
-#define PGDIR_SHIFT 26
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-#define PTRS_PER_PGD 64
-
-#define __PAGETABLE_PUD_FOLDED
-#define PUD_SHIFT 26
-#define PTRS_PER_PUD 1
-#define PUD_SIZE (1UL << PUD_SHIFT)
-#define PUD_MASK (~(PUD_SIZE - 1))
-#define PUE_SIZE 256
-
-#define __PAGETABLE_PMD_FOLDED
-#define PMD_SHIFT 26
-#define PMD_SIZE (1UL << PMD_SHIFT)
-#define PMD_MASK (~(PMD_SIZE - 1))
-#define PTRS_PER_PMD 1
-#define PME_SIZE 256
-
-#define __frv_PT_SIZE 256
-
-#define PTRS_PER_PTE 4096
-
-#define USER_PGDS_IN_LAST_PML4 (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS)
-
-#define TWOLEVEL_PGDIR_SHIFT 26
-#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
-#define BOOT_KERNEL_PGD_PTRS (PTRS_PER_PGD - BOOT_USER_PGD_PTRS)
-
-#ifndef __ASSEMBLY__
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte)
-#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pud_ERROR(e) \
- printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pmd_val(pud_val(e)))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pmd_val(pud_val(pgd_val(e))))
-
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) \
-do { \
- *(pteptr) = (pteval); \
- asm volatile("dcf %M0" :: "U"(*pteptr)); \
-} while(0)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * pgd_offset() returns a (pgd_t *)
- * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
- */
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/*
- * a shortcut which implies the use of the kernel's pgd, instead
- * of a process's
- */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pud is never bad, and a pud always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd) { return 0; }
-static inline int pgd_bad(pgd_t pgd) { return 0; }
-static inline int pgd_present(pgd_t pgd) { return 1; }
-static inline void pgd_clear(pgd_t *pgd) { }
-
-#define pgd_populate(mm, pgd, pud) do { } while (0)
-/*
- * (puds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pgd(pgdptr, pgdval) \
-do { \
- memcpy((pgdptr), &(pgdval), sizeof(pgd_t)); \
- asm volatile("dcf %M0" :: "U"(*(pgdptr))); \
-} while(0)
-
-static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
-{
- return (pud_t *) pgd;
-}
-
-#define pgd_page(pgd) (pud_page((pud_t){ pgd }))
-#define pgd_page_vaddr(pgd) (pud_page_vaddr((pud_t){ pgd }))
-
-/*
- * allocating and freeing a pud is trivial: the 1-entry pud is
- * inside the pgd, so has no extra memory associated with it.
- */
-#define pud_alloc_one(mm, address) NULL
-#define pud_free(mm, x) do { } while (0)
-#define __pud_free_tlb(tlb, x, address) do { } while (0)
-
-/*
- * The "pud_xxx()" functions here are trivial for a folded two-level
- * setup: the pmd is never bad, and a pmd always exists (as it's folded
- * into the pud entry)
- */
-static inline int pud_none(pud_t pud) { return 0; }
-static inline int pud_bad(pud_t pud) { return 0; }
-static inline int pud_present(pud_t pud) { return 1; }
-static inline void pud_clear(pud_t *pud) { }
-
-#define pud_populate(mm, pmd, pte) do { } while (0)
-
-/*
- * (pmds are folded into puds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pud(pudptr, pudval) set_pmd((pmd_t *)(pudptr), (pmd_t) { pudval })
-
-#define pud_page(pud) (pmd_page((pmd_t){ pud }))
-#define pud_page_vaddr(pud) (pmd_page_vaddr((pmd_t){ pud }))
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-extern void __set_pmd(pmd_t *pmdptr, unsigned long __pmd);
-
-#define set_pmd(pmdptr, pmdval) \
-do { \
- __set_pmd((pmdptr), (pmdval).ste[0]); \
-} while(0)
-
-#define __pmd_index(address) 0
-
-static inline pmd_t *pmd_offset(pud_t *dir, unsigned long address)
-{
- return (pmd_t *) dir + __pmd_index(address);
-}
-
-#define pte_same(a, b) ((a).pte == (b).pte)
-#define pte_page(x) (mem_map + ((unsigned long)(((x).pte >> PAGE_SHIFT))))
-#define pte_none(x) (!(x).pte)
-#define pte_pfn(x) ((unsigned long)(((x).pte >> PAGE_SHIFT)))
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define VMALLOC_VMADDR(x) ((unsigned long) (x))
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * control flags in AMPR registers and TLB entries
- */
-#define _PAGE_BIT_PRESENT xAMPRx_V_BIT
-#define _PAGE_BIT_WP DAMPRx_WP_BIT
-#define _PAGE_BIT_NOCACHE xAMPRx_C_BIT
-#define _PAGE_BIT_SUPER xAMPRx_S_BIT
-#define _PAGE_BIT_ACCESSED xAMPRx_RESERVED8_BIT
-#define _PAGE_BIT_DIRTY xAMPRx_M_BIT
-#define _PAGE_BIT_NOTGLOBAL xAMPRx_NG_BIT
-
-#define _PAGE_PRESENT xAMPRx_V
-#define _PAGE_WP DAMPRx_WP
-#define _PAGE_NOCACHE xAMPRx_C
-#define _PAGE_SUPER xAMPRx_S
-#define _PAGE_ACCESSED xAMPRx_RESERVED8 /* accessed if set */
-#define _PAGE_DIRTY xAMPRx_M
-#define _PAGE_NOTGLOBAL xAMPRx_NG
-
-#define _PAGE_RESERVED_MASK (xAMPRx_RESERVED8 | xAMPRx_RESERVED13)
-
-#define _PAGE_PROTNONE 0x000 /* If not present */
-
-#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-#define __PGPROT_BASE \
- (_PAGE_PRESENT | xAMPRx_SS_16Kb | xAMPRx_D | _PAGE_NOTGLOBAL | _PAGE_ACCESSED)
-
-#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
-#define PAGE_SHARED __pgprot(__PGPROT_BASE)
-#define PAGE_COPY __pgprot(__PGPROT_BASE | _PAGE_WP)
-#define PAGE_READONLY __pgprot(__PGPROT_BASE | _PAGE_WP)
-
-#define __PAGE_KERNEL (__PGPROT_BASE | _PAGE_SUPER | _PAGE_DIRTY)
-#define __PAGE_KERNEL_NOCACHE (__PGPROT_BASE | _PAGE_SUPER | _PAGE_DIRTY | _PAGE_NOCACHE)
-#define __PAGE_KERNEL_RO (__PGPROT_BASE | _PAGE_SUPER | _PAGE_DIRTY | _PAGE_WP)
-
-#define MAKE_GLOBAL(x) __pgprot((x) & ~_PAGE_NOTGLOBAL)
-
-#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
-#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
-#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
-
-#define _PAGE_TABLE (_PAGE_PRESENT | xAMPRx_SS_16Kb)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The FR451 can do execute protection by virtue of having separate TLB miss handlers for
- * instruction access and for data access. However, we don't have enough reserved bits to say
- * "execute only", so we don't bother. If you can read it, you can execute it and vice versa.
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY
-#define __P101 PAGE_READONLY
-#define __P110 PAGE_COPY
-#define __P111 PAGE_COPY
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY
-#define __S101 PAGE_READONLY
-#define __S110 PAGE_SHARED
-#define __S111 PAGE_SHARED
-
-/*
- * Define this to warn about kernel memory accesses that are
- * done without a 'access_ok(VERIFY_WRITE,..)'
- */
-#undef TEST_ACCESS_OK
-
-#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_bad(x) (pmd_val(x) & xAMPRx_SS)
-#define pmd_clear(xp) do { __set_pmd(xp, 0); } while(0)
-
-#define pmd_page_vaddr(pmd) \
- ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#endif
-
-#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_dirty(pte_t pte) { return (pte).pte & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte) { return (pte).pte & _PAGE_ACCESSED; }
-static inline int pte_write(pte_t pte) { return !((pte).pte & _PAGE_WP); }
-static inline int pte_special(pte_t pte) { return 0; }
-
-static inline pte_t pte_mkclean(pte_t pte) { (pte).pte &= ~_PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkold(pte_t pte) { (pte).pte &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte |= _PAGE_WP; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte &= ~_PAGE_WP; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
-static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
-{
- int i = test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep);
- asm volatile("dcf %M0" :: "U"(*ptep));
- return i;
-}
-
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- unsigned long x = xchg(&ptep->pte, 0);
- asm volatile("dcf %M0" :: "U"(*ptep));
- return __pte(x);
-}
-
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- set_bit(_PAGE_BIT_WP, ptep);
- asm volatile("dcf %M0" :: "U"(*ptep));
-}
-
-/*
- * Macro to mark a page protection value as "uncacheable"
- */
-#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE))
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-#define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
-
-/* This takes a physical page address that is used by the remapping functions */
-#define mk_pte_phys(physpage, pgprot) pfn_pte((physpage) >> PAGE_SHIFT, pgprot)
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- pte.pte &= _PAGE_CHG_MASK;
- pte.pte |= pgprot_val(newprot);
- return pte;
-}
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-#define pgd_index_k(addr) pgd_index(addr)
-
-/* Find an entry in the bottom-level page table.. */
-#define __pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-
-/*
- * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
- *
- * this macro returns the index of the entry in the pte page which would
- * control the given virtual address
- */
-#define pte_index(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
-
-#if defined(CONFIG_HIGHPTE)
-#define pte_offset_map(dir, address) \
- ((pte_t *)kmap_atomic(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) kunmap_atomic(pte)
-#else
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) do { } while (0)
-#endif
-
-/*
- * Handle swap and file entries
- * - the PTE is encoded in the following format:
- * bit 0: Must be 0 (!_PAGE_PRESENT)
- * bits 1-6: Swap type
- * bits 7-31: Swap offset
- */
-#define __swp_type(x) (((x).val >> 1) & 0x1f)
-#define __swp_offset(x) ((x).val >> 7)
-#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 7) })
-#define __pte_to_swp_entry(_pte) ((swp_entry_t) { (_pte).pte })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define PageSkip(page) (0)
-#define kern_addr_valid(addr) (1)
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define __HAVE_ARCH_PTE_SAME
-#include <asm-generic/pgtable.h>
-
-/*
- * preload information about a newly instantiated PTE into the SCR0/SCR1 PGE cache
- */
-static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
-{
- struct mm_struct *mm;
- unsigned long ampr;
-
- mm = current->mm;
- if (mm) {
- pgd_t *pge = pgd_offset(mm, address);
- pud_t *pue = pud_offset(pge, address);
- pmd_t *pme = pmd_offset(pue, address);
-
- ampr = pme->ste[0] & 0xffffff00;
- ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C |
- xAMPRx_V;
- } else {
- address = ULONG_MAX;
- ampr = 0;
- }
-
- asm volatile("movgs %0,scr0\n"
- "movgs %0,scr1\n"
- "movgs %1,dampr4\n"
- "movgs %1,dampr5\n"
- :
- : "r"(address), "r"(ampr)
- );
-}
-
-#ifdef CONFIG_PROC_FS
-extern char *proc_pid_status_frv_cxnr(struct mm_struct *mm, char *buffer);
-#endif
-
-extern void __init pgtable_cache_init(void);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* !CONFIG_MMU */
-
-#ifndef __ASSEMBLY__
-extern void __init paging_init(void);
-#endif /* !__ASSEMBLY__ */
-#define HAVE_ARCH_UNMAPPED_AREA
-
-#endif /* _ASM_PGTABLE_H */
diff --git a/arch/frv/include/asm/processor.h b/arch/frv/include/asm/processor.h
deleted file mode 100644
index 021cce78b401..000000000000
--- a/arch/frv/include/asm/processor.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* processor.h: FRV processor definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROCESSOR_H
-#define _ASM_PROCESSOR_H
-
-#include <asm/mem-layout.h>
-
-#ifndef __ASSEMBLY__
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <asm/sections.h>
-#include <asm/segment.h>
-#include <asm/fpu.h>
-#include <asm/registers.h>
-#include <asm/ptrace.h>
-#include <asm/current.h>
-#include <asm/cache.h>
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/*
- * Bus types
- */
-#define EISA_bus 0
-
-struct thread_struct {
- struct pt_regs *frame; /* [GR28] exception frame ptr for this thread */
- struct task_struct *curr; /* [GR29] current pointer for this thread */
- unsigned long sp; /* [GR1 ] kernel stack pointer */
- unsigned long fp; /* [GR2 ] kernel frame pointer */
- unsigned long lr; /* link register */
- unsigned long pc; /* program counter */
- unsigned long gr[12]; /* [GR16-GR27] */
- unsigned long sched_lr; /* LR from schedule() */
-
- union {
- struct pt_regs *frame0; /* top (user) stack frame */
- struct user_context *user; /* userspace context */
- };
-} __attribute__((aligned(8)));
-
-extern struct pt_regs *__kernel_frame0_ptr;
-extern struct task_struct *__kernel_current_task;
-
-#endif
-
-#ifndef __ASSEMBLY__
-#define INIT_THREAD_FRAME0 \
- ((struct pt_regs *) \
- (sizeof(init_stack) + (unsigned long) init_stack - sizeof(struct user_context)))
-
-#define INIT_THREAD { \
- NULL, \
- (struct task_struct *) init_stack, \
- 0, 0, 0, 0, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
- 0, \
- { INIT_THREAD_FRAME0 }, \
-}
-
-/*
- * do necessary setup to start up a newly executed thread.
- */
-#define start_thread(_regs, _pc, _usp) \
-do { \
- _regs->pc = (_pc); \
- _regs->psr &= ~PSR_S; \
- _regs->sp = (_usp); \
-} while(0)
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-extern asmlinkage void save_user_regs(struct user_context *target);
-extern asmlinkage void *restore_user_regs(const struct user_context *target, ...);
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc)
-#define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp)
-
-#define cpu_relax() barrier()
-
-/* data cache prefetch */
-#define ARCH_HAS_PREFETCH
-static inline void prefetch(const void *x)
-{
- asm volatile("dcpl %0,gr0,#0" : : "r"(x));
-}
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/frv/include/asm/ptrace.h b/arch/frv/include/asm/ptrace.h
deleted file mode 100644
index 034f17934192..000000000000
--- a/arch/frv/include/asm/ptrace.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* ptrace.h: ptrace() relevant definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_PTRACE_H
-#define _ASM_PTRACE_H
-
-#include <asm/irq_regs.h>
-#include <uapi/asm/ptrace.h>
-
-#define in_syscall(regs) (((regs)->tbr & TBR_TT) == TBR_TT_TRAP0)
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/*
- * we dedicate GR28 to keeping a pointer to the current exception frame
- * - gr28 is destroyed on entry to the kernel from userspace
- */
-register struct pt_regs *__frame asm("gr28");
-
-#define user_mode(regs) (!((regs)->psr & PSR_S))
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_stack_pointer(regs) ((regs)->sp)
-#define current_pt_regs() (__frame)
-
-extern unsigned long user_stack(const struct pt_regs *);
-#define profile_pc(regs) ((regs)->pc)
-
-#define task_pt_regs(task) ((task)->thread.frame0)
-
-#define arch_has_single_step() (1)
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_PTRACE_H */
diff --git a/arch/frv/include/asm/sections.h b/arch/frv/include/asm/sections.h
deleted file mode 100644
index d03fb64e93e9..000000000000
--- a/arch/frv/include/asm/sections.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* sections.h: linkage layout variables
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SECTIONS_H
-#define _ASM_SECTIONS_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <asm-generic/sections.h>
-
-#ifdef __KERNEL__
-
-/*
- * we don't want to put variables in the GP-REL section if they're not used very much - that would
- * be waste since GP-REL addressing is limited to GP16+/-2048
- */
-#define __nongpreldata __attribute__((section(".data")))
-#define __nongprelbss __attribute__((section(".bss")))
-
-/*
- * linker symbols
- */
-extern const void __kernel_image_start, __kernel_image_end, __page_offset;
-
-extern unsigned long __nongprelbss memory_start;
-extern unsigned long __nongprelbss memory_end;
-extern unsigned long __nongprelbss rom_length;
-
-#endif
-#endif
-#endif /* _ASM_SECTIONS_H */
diff --git a/arch/frv/include/asm/segment.h b/arch/frv/include/asm/segment.h
deleted file mode 100644
index 2305142d4cf8..000000000000
--- a/arch/frv/include/asm/segment.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* segment.h: MMU segment settings
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SEGMENT_H
-#define _ASM_SEGMENT_H
-
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-#ifdef CONFIG_MMU
-#define USER_DS MAKE_MM_SEG(TASK_SIZE - 1)
-#define KERNEL_DS MAKE_MM_SEG(0xdfffffffUL)
-#else
-#define USER_DS MAKE_MM_SEG(memory_end)
-#define KERNEL_DS MAKE_MM_SEG(0xe0000000UL)
-#endif
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (__current_thread_info->addr_limit)
-#define segment_eq(a, b) ((a).seg == (b).seg)
-#define get_addr_limit() (get_fs().seg)
-
-#define set_fs(_x) \
-do { \
- __current_thread_info->addr_limit = (_x); \
-} while(0)
-
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_SEGMENT_H */
diff --git a/arch/frv/include/asm/serial-regs.h b/arch/frv/include/asm/serial-regs.h
deleted file mode 100644
index e1286bda00eb..000000000000
--- a/arch/frv/include/asm/serial-regs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* serial-regs.h: serial port registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SERIAL_REGS_H
-#define _ASM_SERIAL_REGS_H
-
-#include <linux/serial_reg.h>
-#include <asm/irc-regs.h>
-
-#define SERIAL_ICLK 33333333 /* the target serial input clock */
-#define UART0_BASE 0xfeff9c00
-#define UART1_BASE 0xfeff9c40
-
-#define __get_UART0(R) ({ __reg(UART0_BASE + (R) * 8) >> 24; })
-#define __get_UART1(R) ({ __reg(UART1_BASE + (R) * 8) >> 24; })
-#define __set_UART0(R,V) do { __reg(UART0_BASE + (R) * 8) = (V) << 24; } while(0)
-#define __set_UART1(R,V) do { __reg(UART1_BASE + (R) * 8) = (V) << 24; } while(0)
-
-#define __get_UART0_LSR() ({ __get_UART0(UART_LSR); })
-#define __get_UART1_LSR() ({ __get_UART1(UART_LSR); })
-
-#define __set_UART0_IER(V) __set_UART0(UART_IER,(V))
-#define __set_UART1_IER(V) __set_UART1(UART_IER,(V))
-
-/* serial prescaler select register */
-#define __get_UCPSR() ({ *(volatile unsigned long *)(0xfeff9c90); })
-#define __set_UCPSR(V) do { *(volatile unsigned long *)(0xfeff9c90) = (V); } while(0)
-#define UCPSR_SELECT0 0x07000000
-#define UCPSR_SELECT1 0x38000000
-
-/* serial prescaler base value register */
-#define __get_UCPVR() ({ *(volatile unsigned long *)(0xfeff9c98); mb(); })
-#define __set_UCPVR(V) do { *(volatile unsigned long *)(0xfeff9c98) = (V) << 24; mb(); } while(0)
-
-
-#endif /* _ASM_SERIAL_REGS_H */
diff --git a/arch/frv/include/asm/serial.h b/arch/frv/include/asm/serial.h
deleted file mode 100644
index 614c6d76789a..000000000000
--- a/arch/frv/include/asm/serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * serial.h
- *
- * Copyright (C) 2003 Develer S.r.l. (http://www.develer.com/)
- * Author: Bernardo Innocenti <bernie@codewiz.org>
- *
- * Based on linux/include/asm-i386/serial.h
- */
-#include <asm/serial-regs.h>
-
-/*
- * the base baud is derived from the clock speed and so is variable
- */
-#define BASE_BAUD 0
diff --git a/arch/frv/include/asm/setup.h b/arch/frv/include/asm/setup.h
deleted file mode 100644
index aa76f2eac09a..000000000000
--- a/arch/frv/include/asm/setup.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* setup.h: setup stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_SETUP_H
-#define _ASM_SETUP_H
-
-
-#include <linux/init.h>
-#include <uapi/asm/setup.h>
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_MMU
-extern unsigned long __initdata num_mappedpages;
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_SETUP_H */
diff --git a/arch/frv/include/asm/shmparam.h b/arch/frv/include/asm/shmparam.h
deleted file mode 100644
index 50ea51f26c46..000000000000
--- a/arch/frv/include/asm/shmparam.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SHMPARAM_H
-#define _ASM_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_SHMPARAM_H */
-
diff --git a/arch/frv/include/asm/signal.h b/arch/frv/include/asm/signal.h
deleted file mode 100644
index 796394113904..000000000000
--- a/arch/frv/include/asm/signal.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SIGNAL_H
-#define _ASM_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-#endif /* _ASM_SIGNAL_H */
diff --git a/arch/frv/include/asm/smp.h b/arch/frv/include/asm/smp.h
deleted file mode 100644
index 0d7fa409312d..000000000000
--- a/arch/frv/include/asm/smp.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-
-#ifdef CONFIG_SMP
-#error SMP not supported
-#endif
-
-#endif
diff --git a/arch/frv/include/asm/spinlock.h b/arch/frv/include/asm/spinlock.h
deleted file mode 100644
index fe385f45d1fd..000000000000
--- a/arch/frv/include/asm/spinlock.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* spinlock.h: spinlocks for FR-V
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SPINLOCK_H
-#define _ASM_SPINLOCK_H
-
-#error no spinlocks for FR-V yet
-
-#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/frv/include/asm/spr-regs.h b/arch/frv/include/asm/spr-regs.h
deleted file mode 100644
index d3883021f236..000000000000
--- a/arch/frv/include/asm/spr-regs.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/* spr-regs.h: special-purpose registers on the FRV
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SPR_REGS_H
-#define _ASM_SPR_REGS_H
-
-/*
- * PSR - Processor Status Register
- */
-#define PSR_ET 0x00000001 /* enable interrupts/exceptions flag */
-#define PSR_PS 0x00000002 /* previous supervisor mode flag */
-#define PSR_S 0x00000004 /* supervisor mode flag */
-#define PSR_PIL 0x00000078 /* processor external interrupt level */
-#define PSR_PIL_0 0x00000000 /* - no interrupt in progress */
-#define PSR_PIL_13 0x00000068 /* - debugging only */
-#define PSR_PIL_14 0x00000070 /* - debugging in progress */
-#define PSR_PIL_15 0x00000078 /* - NMI in progress */
-#define PSR_EM 0x00000080 /* enable media operation */
-#define PSR_EF 0x00000100 /* enable FPU operation */
-#define PSR_BE 0x00001000 /* endianness mode */
-#define PSR_BE_LE 0x00000000 /* - little endian mode */
-#define PSR_BE_BE 0x00001000 /* - big endian mode */
-#define PSR_CM 0x00002000 /* conditional mode */
-#define PSR_NEM 0x00004000 /* non-excepting mode */
-#define PSR_ICE 0x00010000 /* in-circuit emulation mode */
-#define PSR_VERSION_SHIFT 24 /* CPU silicon ID */
-#define PSR_IMPLE_SHIFT 28 /* CPU core ID */
-
-#define PSR_VERSION(psr) (((psr) >> PSR_VERSION_SHIFT) & 0xf)
-#define PSR_IMPLE(psr) (((psr) >> PSR_IMPLE_SHIFT) & 0xf)
-
-#define PSR_IMPLE_FR401 0x2
-#define PSR_VERSION_FR401_MB93401 0x0
-#define PSR_VERSION_FR401_MB93401A 0x1
-#define PSR_VERSION_FR401_MB93403 0x2
-
-#define PSR_IMPLE_FR405 0x4
-#define PSR_VERSION_FR405_MB93405 0x0
-
-#define PSR_IMPLE_FR451 0x5
-#define PSR_VERSION_FR451_MB93451 0x0
-
-#define PSR_IMPLE_FR501 0x1
-#define PSR_VERSION_FR501_MB93501 0x1
-#define PSR_VERSION_FR501_MB93501A 0x2
-
-#define PSR_IMPLE_FR551 0x3
-#define PSR_VERSION_FR551_MB93555 0x1
-
-#define __get_PSR() ({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; })
-#define __set_PSR(V) do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0)
-
-/*
- * TBR - Trap Base Register
- */
-#define TBR_TT 0x00000ff0
-#define TBR_TT_INSTR_MMU_MISS (0x01 << 4)
-#define TBR_TT_INSTR_ACC_ERROR (0x02 << 4)
-#define TBR_TT_INSTR_ACC_EXCEP (0x03 << 4)
-#define TBR_TT_PRIV_INSTR (0x06 << 4)
-#define TBR_TT_ILLEGAL_INSTR (0x07 << 4)
-#define TBR_TT_FP_EXCEPTION (0x0d << 4)
-#define TBR_TT_MP_EXCEPTION (0x0e << 4)
-#define TBR_TT_DATA_ACC_ERROR (0x11 << 4)
-#define TBR_TT_DATA_MMU_MISS (0x12 << 4)
-#define TBR_TT_DATA_ACC_EXCEP (0x13 << 4)
-#define TBR_TT_DATA_STR_ERROR (0x14 << 4)
-#define TBR_TT_DIVISION_EXCEP (0x17 << 4)
-#define TBR_TT_COMMIT_EXCEP (0x19 << 4)
-#define TBR_TT_INSTR_TLB_MISS (0x1a << 4)
-#define TBR_TT_DATA_TLB_MISS (0x1b << 4)
-#define TBR_TT_DATA_DAT_EXCEP (0x1d << 4)
-#define TBR_TT_DECREMENT_TIMER (0x1f << 4)
-#define TBR_TT_COMPOUND_EXCEP (0x20 << 4)
-#define TBR_TT_INTERRUPT_1 (0x21 << 4)
-#define TBR_TT_INTERRUPT_2 (0x22 << 4)
-#define TBR_TT_INTERRUPT_3 (0x23 << 4)
-#define TBR_TT_INTERRUPT_4 (0x24 << 4)
-#define TBR_TT_INTERRUPT_5 (0x25 << 4)
-#define TBR_TT_INTERRUPT_6 (0x26 << 4)
-#define TBR_TT_INTERRUPT_7 (0x27 << 4)
-#define TBR_TT_INTERRUPT_8 (0x28 << 4)
-#define TBR_TT_INTERRUPT_9 (0x29 << 4)
-#define TBR_TT_INTERRUPT_10 (0x2a << 4)
-#define TBR_TT_INTERRUPT_11 (0x2b << 4)
-#define TBR_TT_INTERRUPT_12 (0x2c << 4)
-#define TBR_TT_INTERRUPT_13 (0x2d << 4)
-#define TBR_TT_INTERRUPT_14 (0x2e << 4)
-#define TBR_TT_INTERRUPT_15 (0x2f << 4)
-#define TBR_TT_TRAP0 (0x80 << 4)
-#define TBR_TT_TRAP1 (0x81 << 4)
-#define TBR_TT_TRAP2 (0x82 << 4)
-#define TBR_TT_TRAP3 (0x83 << 4)
-#define TBR_TT_TRAP120 (0xf8 << 4)
-#define TBR_TT_TRAP121 (0xf9 << 4)
-#define TBR_TT_TRAP122 (0xfa << 4)
-#define TBR_TT_TRAP123 (0xfb << 4)
-#define TBR_TT_TRAP124 (0xfc << 4)
-#define TBR_TT_TRAP125 (0xfd << 4)
-#define TBR_TT_TRAP126 (0xfe << 4)
-#define TBR_TT_BREAK (0xff << 4)
-
-#define TBR_TT_ATOMIC_CMPXCHG32 TBR_TT_TRAP120
-#define TBR_TT_ATOMIC_XCHG32 TBR_TT_TRAP121
-#define TBR_TT_ATOMIC_XOR TBR_TT_TRAP122
-#define TBR_TT_ATOMIC_OR TBR_TT_TRAP123
-#define TBR_TT_ATOMIC_AND TBR_TT_TRAP124
-#define TBR_TT_ATOMIC_SUB TBR_TT_TRAP125
-#define TBR_TT_ATOMIC_ADD TBR_TT_TRAP126
-
-#define __get_TBR() ({ unsigned long x; asm volatile("movsg tbr,%0" : "=r"(x)); x; })
-
-/*
- * HSR0 - Hardware Status Register 0
- */
-#define HSR0_PDM 0x00000007 /* power down mode */
-#define HSR0_PDM_NORMAL 0x00000000 /* - normal mode */
-#define HSR0_PDM_CORE_SLEEP 0x00000001 /* - CPU core sleep mode */
-#define HSR0_PDM_BUS_SLEEP 0x00000003 /* - bus sleep mode */
-#define HSR0_PDM_PLL_RUN 0x00000005 /* - PLL run */
-#define HSR0_PDM_PLL_STOP 0x00000007 /* - PLL stop */
-#define HSR0_GRLE 0x00000040 /* GR lower register set enable */
-#define HSR0_GRHE 0x00000080 /* GR higher register set enable */
-#define HSR0_FRLE 0x00000100 /* FR lower register set enable */
-#define HSR0_FRHE 0x00000200 /* FR higher register set enable */
-#define HSR0_GRN 0x00000400 /* GR quantity */
-#define HSR0_GRN_64 0x00000000 /* - 64 GR registers */
-#define HSR0_GRN_32 0x00000400 /* - 32 GR registers */
-#define HSR0_FRN 0x00000800 /* FR quantity */
-#define HSR0_FRN_64 0x00000000 /* - 64 FR registers */
-#define HSR0_FRN_32 0x00000800 /* - 32 FR registers */
-#define HSR0_SA 0x00001000 /* start address (RAMBOOT#) */
-#define HSR0_ETMI 0x00008000 /* enable TIMERI (64-bit up timer) */
-#define HSR0_ETMD 0x00004000 /* enable TIMERD (32-bit down timer) */
-#define HSR0_PEDAT 0x00010000 /* previous DAT mode */
-#define HSR0_XEDAT 0x00020000 /* exception DAT mode */
-#define HSR0_EDAT 0x00080000 /* enable DAT mode */
-#define HSR0_RME 0x00400000 /* enable RAM mode */
-#define HSR0_EMEM 0x00800000 /* enable MMU_Miss mask */
-#define HSR0_EXMMU 0x01000000 /* enable extended MMU mode */
-#define HSR0_EDMMU 0x02000000 /* enable data MMU */
-#define HSR0_EIMMU 0x04000000 /* enable instruction MMU */
-#define HSR0_CBM 0x08000000 /* copy back mode */
-#define HSR0_CBM_WRITE_THRU 0x00000000 /* - write through */
-#define HSR0_CBM_COPY_BACK 0x08000000 /* - copy back */
-#define HSR0_NWA 0x10000000 /* no write allocate */
-#define HSR0_DCE 0x40000000 /* data cache enable */
-#define HSR0_ICE 0x80000000 /* instruction cache enable */
-
-#define __get_HSR(R) ({ unsigned long x; asm volatile("movsg hsr"#R",%0" : "=r"(x)); x; })
-#define __set_HSR(R,V) do { asm volatile("movgs %0,hsr"#R : : "r"(V)); } while(0)
-
-/*
- * CCR - Condition Codes Register
- */
-#define CCR_FCC0 0x0000000f /* FP/Media condition 0 (fcc0 reg) */
-#define CCR_FCC1 0x000000f0 /* FP/Media condition 1 (fcc1 reg) */
-#define CCR_FCC2 0x00000f00 /* FP/Media condition 2 (fcc2 reg) */
-#define CCR_FCC3 0x0000f000 /* FP/Media condition 3 (fcc3 reg) */
-#define CCR_ICC0 0x000f0000 /* Integer condition 0 (icc0 reg) */
-#define CCR_ICC0_C 0x00010000 /* - Carry flag */
-#define CCR_ICC0_V 0x00020000 /* - Overflow flag */
-#define CCR_ICC0_Z 0x00040000 /* - Zero flag */
-#define CCR_ICC0_N 0x00080000 /* - Negative flag */
-#define CCR_ICC1 0x00f00000 /* Integer condition 1 (icc1 reg) */
-#define CCR_ICC2 0x0f000000 /* Integer condition 2 (icc2 reg) */
-#define CCR_ICC3 0xf0000000 /* Integer condition 3 (icc3 reg) */
-
-/*
- * CCCR - Condition Codes for Conditional Instructions Register
- */
-#define CCCR_CC0 0x00000003 /* condition 0 (cc0 reg) */
-#define CCCR_CC0_FALSE 0x00000002 /* - condition is false */
-#define CCCR_CC0_TRUE 0x00000003 /* - condition is true */
-#define CCCR_CC1 0x0000000c /* condition 1 (cc1 reg) */
-#define CCCR_CC2 0x00000030 /* condition 2 (cc2 reg) */
-#define CCCR_CC3 0x000000c0 /* condition 3 (cc3 reg) */
-#define CCCR_CC4 0x00000300 /* condition 4 (cc4 reg) */
-#define CCCR_CC5 0x00000c00 /* condition 5 (cc5 reg) */
-#define CCCR_CC6 0x00003000 /* condition 6 (cc6 reg) */
-#define CCCR_CC7 0x0000c000 /* condition 7 (cc7 reg) */
-
-/*
- * ISR - Integer Status Register
- */
-#define ISR_EMAM 0x00000001 /* memory misaligned access handling */
-#define ISR_EMAM_EXCEPTION 0x00000000 /* - generate exception */
-#define ISR_EMAM_FUDGE 0x00000001 /* - mask out invalid address bits */
-#define ISR_AEXC 0x00000004 /* accrued [overflow] exception */
-#define ISR_DTT 0x00000018 /* division type trap */
-#define ISR_DTT_IGNORE 0x00000000 /* - ignore division error */
-#define ISR_DTT_DIVBYZERO 0x00000008 /* - generate exception */
-#define ISR_DTT_OVERFLOW 0x00000010 /* - record overflow */
-#define ISR_EDE 0x00000020 /* enable division exception */
-#define ISR_PLI 0x20000000 /* pre-load instruction information */
-#define ISR_QI 0x80000000 /* quad data implementation information */
-
-/*
- * EPCR0 - Exception PC Register
- */
-#define EPCR0_V 0x00000001 /* register content validity indicator */
-#define EPCR0_PC 0xfffffffc /* faulting instruction address */
-
-/*
- * ESR0/14/15 - Exception Status Register
- */
-#define ESRx_VALID 0x00000001 /* register content validity indicator */
-#define ESRx_EC 0x0000003e /* exception type */
-#define ESRx_EC_DATA_STORE 0x00000000 /* - data_store_error */
-#define ESRx_EC_INSN_ACCESS 0x00000006 /* - instruction_access_error */
-#define ESRx_EC_PRIV_INSN 0x00000008 /* - privileged_instruction */
-#define ESRx_EC_ILL_INSN 0x0000000a /* - illegal_instruction */
-#define ESRx_EC_MP_EXCEP 0x0000001c /* - mp_exception */
-#define ESRx_EC_DATA_ACCESS 0x00000020 /* - data_access_error */
-#define ESRx_EC_DIVISION 0x00000026 /* - division_exception */
-#define ESRx_EC_ITLB_MISS 0x00000034 /* - instruction_access_TLB_miss */
-#define ESRx_EC_DTLB_MISS 0x00000036 /* - data_access_TLB_miss */
-#define ESRx_EC_DATA_ACCESS_DAT 0x0000003a /* - data_access_DAT_exception */
-
-#define ESR0_IAEC 0x00000100 /* info for instruction-access-exception */
-#define ESR0_IAEC_RESV 0x00000000 /* - reserved */
-#define ESR0_IAEC_PROT_VIOL 0x00000100 /* - protection violation */
-
-#define ESR0_ATXC 0x00f00000 /* address translation exception code */
-#define ESR0_ATXC_MMU_MISS 0x00000000 /* - MMU miss exception and more (?) */
-#define ESR0_ATXC_MULTI_DAT 0x00800000 /* - multiple DAT entry hit */
-#define ESR0_ATXC_MULTI_SAT 0x00900000 /* - multiple SAT entry hit */
-#define ESR0_ATXC_AMRTLB_MISS 0x00a00000 /* - MMU/TLB miss exception */
-#define ESR0_ATXC_PRIV_EXCEP 0x00c00000 /* - privilege protection fault */
-#define ESR0_ATXC_WP_EXCEP 0x00d00000 /* - write protection fault */
-
-#define ESR0_EAV 0x00000800 /* true if EAR0 register valid */
-#define ESR15_EAV 0x00000800 /* true if EAR15 register valid */
-
-/*
- * ESFR1 - Exception Status Valid Flag Register
- */
-#define ESFR1_ESR0 0x00000001 /* true if ESR0 is valid */
-#define ESFR1_ESR14 0x00004000 /* true if ESR14 is valid */
-#define ESFR1_ESR15 0x00008000 /* true if ESR15 is valid */
-
-/*
- * MSR - Media Status Register
- */
-#define MSR0_AOVF 0x00000001 /* overflow exception accrued */
-#define MSRx_OVF 0x00000002 /* overflow exception detected */
-#define MSRx_SIE 0x0000003c /* last SIMD instruction exception detected */
-#define MSRx_SIE_NONE 0x00000000 /* - none detected */
-#define MSRx_SIE_FRkHI_ACCk 0x00000020 /* - exception at FRkHI or ACCk */
-#define MSRx_SIE_FRkLO_ACCk1 0x00000010 /* - exception at FRkLO or ACCk+1 */
-#define MSRx_SIE_FRk1HI_ACCk2 0x00000008 /* - exception at FRk+1HI or ACCk+2 */
-#define MSRx_SIE_FRk1LO_ACCk3 0x00000004 /* - exception at FRk+1LO or ACCk+3 */
-#define MSR0_MTT 0x00007000 /* type of last media trap detected */
-#define MSR0_MTT_NONE 0x00000000 /* - none detected */
-#define MSR0_MTT_OVERFLOW 0x00001000 /* - overflow detected */
-#define MSR0_HI 0x00c00000 /* hardware implementation */
-#define MSR0_HI_ROUNDING 0x00000000 /* - rounding mode */
-#define MSR0_HI_NONROUNDING 0x00c00000 /* - non-rounding mode */
-#define MSR0_EMCI 0x01000000 /* enable media custom instructions */
-#define MSR0_SRDAV 0x10000000 /* select rounding mode of MAVEH */
-#define MSR0_SRDAV_RDAV 0x00000000 /* - controlled by MSR.RDAV */
-#define MSR0_SRDAV_RD 0x10000000 /* - controlled by MSR.RD */
-#define MSR0_RDAV 0x20000000 /* rounding mode of MAVEH */
-#define MSR0_RDAV_NEAREST_MI 0x00000000 /* - round to nearest minus */
-#define MSR0_RDAV_NEAREST_PL 0x20000000 /* - round to nearest plus */
-#define MSR0_RD 0xc0000000 /* rounding mode */
-#define MSR0_RD_NEAREST 0x00000000 /* - nearest */
-#define MSR0_RD_ZERO 0x40000000 /* - zero */
-#define MSR0_RD_POS_INF 0x80000000 /* - positive infinity */
-#define MSR0_RD_NEG_INF 0xc0000000 /* - negative infinity */
-
-/*
- * IAMPR0-7 - Instruction Address Mapping Register
- * DAMPR0-7 - Data Address Mapping Register
- */
-#define xAMPRx_V 0x00000001 /* register content validity indicator */
-#define DAMPRx_WP 0x00000002 /* write protect */
-#define DAMPRx_WP_RW 0x00000000 /* - read/write */
-#define DAMPRx_WP_RO 0x00000002 /* - read-only */
-#define xAMPRx_C 0x00000004 /* cached/uncached */
-#define xAMPRx_C_CACHED 0x00000000 /* - cached */
-#define xAMPRx_C_UNCACHED 0x00000004 /* - uncached */
-#define xAMPRx_S 0x00000008 /* supervisor only */
-#define xAMPRx_S_USER 0x00000000 /* - userspace can access */
-#define xAMPRx_S_KERNEL 0x00000008 /* - kernel only */
-#define xAMPRx_SS 0x000000f0 /* segment size */
-#define xAMPRx_SS_16Kb 0x00000000 /* - 16 kilobytes */
-#define xAMPRx_SS_64Kb 0x00000010 /* - 64 kilobytes */
-#define xAMPRx_SS_256Kb 0x00000020 /* - 256 kilobytes */
-#define xAMPRx_SS_1Mb 0x00000030 /* - 1 megabyte */
-#define xAMPRx_SS_2Mb 0x00000040 /* - 2 megabytes */
-#define xAMPRx_SS_4Mb 0x00000050 /* - 4 megabytes */
-#define xAMPRx_SS_8Mb 0x00000060 /* - 8 megabytes */
-#define xAMPRx_SS_16Mb 0x00000070 /* - 16 megabytes */
-#define xAMPRx_SS_32Mb 0x00000080 /* - 32 megabytes */
-#define xAMPRx_SS_64Mb 0x00000090 /* - 64 megabytes */
-#define xAMPRx_SS_128Mb 0x000000a0 /* - 128 megabytes */
-#define xAMPRx_SS_256Mb 0x000000b0 /* - 256 megabytes */
-#define xAMPRx_SS_512Mb 0x000000c0 /* - 512 megabytes */
-#define xAMPRx_RESERVED8 0x00000100 /* reserved bit */
-#define xAMPRx_NG 0x00000200 /* non-global */
-#define xAMPRx_L 0x00000400 /* locked */
-#define xAMPRx_M 0x00000800 /* modified */
-#define xAMPRx_D 0x00001000 /* DAT entry */
-#define xAMPRx_RESERVED13 0x00002000 /* reserved bit */
-#define xAMPRx_PPFN 0xfff00000 /* physical page frame number */
-
-#define xAMPRx_V_BIT 0
-#define DAMPRx_WP_BIT 1
-#define xAMPRx_C_BIT 2
-#define xAMPRx_S_BIT 3
-#define xAMPRx_RESERVED8_BIT 8
-#define xAMPRx_NG_BIT 9
-#define xAMPRx_L_BIT 10
-#define xAMPRx_M_BIT 11
-#define xAMPRx_D_BIT 12
-#define xAMPRx_RESERVED13_BIT 13
-
-#define __get_IAMPR(R) ({ unsigned long x; asm volatile("movsg iampr"#R",%0" : "=r"(x)); x; })
-#define __get_DAMPR(R) ({ unsigned long x; asm volatile("movsg dampr"#R",%0" : "=r"(x)); x; })
-
-#define __get_IAMLR(R) ({ unsigned long x; asm volatile("movsg iamlr"#R",%0" : "=r"(x)); x; })
-#define __get_DAMLR(R) ({ unsigned long x; asm volatile("movsg damlr"#R",%0" : "=r"(x)); x; })
-
-#define __set_IAMPR(R,V) do { asm volatile("movgs %0,iampr"#R : : "r"(V)); } while(0)
-#define __set_DAMPR(R,V) do { asm volatile("movgs %0,dampr"#R : : "r"(V)); } while(0)
-
-#define __set_IAMLR(R,V) do { asm volatile("movgs %0,iamlr"#R : : "r"(V)); } while(0)
-#define __set_DAMLR(R,V) do { asm volatile("movgs %0,damlr"#R : : "r"(V)); } while(0)
-
-#define save_dampr(R, _dampr) \
-do { \
- asm volatile("movsg dampr"R",%0" : "=r"(_dampr)); \
-} while(0)
-
-#define restore_dampr(R, _dampr) \
-do { \
- asm volatile("movgs %0,dampr"R :: "r"(_dampr)); \
-} while(0)
-
-/*
- * AMCR - Address Mapping Control Register
- */
-#define AMCR_IAMRN 0x000000ff /* quantity of IAMPR registers */
-#define AMCR_DAMRN 0x0000ff00 /* quantity of DAMPR registers */
-
-/*
- * TTBR - Address Translation Table Base Register
- */
-#define __get_TTBR() ({ unsigned long x; asm volatile("movsg ttbr,%0" : "=r"(x)); x; })
-
-/*
- * TPXR - TLB Probe Extend Register
- */
-#define TPXR_E 0x00000001
-#define TPXR_LMAX_SHIFT 20
-#define TPXR_LMAX_SMASK 0xf
-#define TPXR_WMAX_SHIFT 24
-#define TPXR_WMAX_SMASK 0xf
-#define TPXR_WAY_SHIFT 28
-#define TPXR_WAY_SMASK 0xf
-
-/*
- * DCR - Debug Control Register
- */
-#define DCR_IBCE3 0x00000001 /* break on conditional insn pointed to by IBAR3 */
-#define DCR_IBE3 0x00000002 /* break on insn pointed to by IBAR3 */
-#define DCR_IBCE1 0x00000004 /* break on conditional insn pointed to by IBAR2 */
-#define DCR_IBE1 0x00000008 /* break on insn pointed to by IBAR2 */
-#define DCR_IBCE2 0x00000010 /* break on conditional insn pointed to by IBAR1 */
-#define DCR_IBE2 0x00000020 /* break on insn pointed to by IBAR1 */
-#define DCR_IBCE0 0x00000040 /* break on conditional insn pointed to by IBAR0 */
-#define DCR_IBE0 0x00000080 /* break on insn pointed to by IBAR0 */
-
-#define DCR_DDBE1 0x00004000 /* use DBDR1x when checking DBAR1 */
-#define DCR_DWBE1 0x00008000 /* break on store to address in DBAR1/DBMR1x */
-#define DCR_DRBE1 0x00010000 /* break on load from address in DBAR1/DBMR1x */
-#define DCR_DDBE0 0x00020000 /* use DBDR0x when checking DBAR0 */
-#define DCR_DWBE0 0x00040000 /* break on store to address in DBAR0/DBMR0x */
-#define DCR_DRBE0 0x00080000 /* break on load from address in DBAR0/DBMR0x */
-
-#define DCR_EIM 0x0c000000 /* external interrupt disable */
-#define DCR_IBM 0x10000000 /* instruction break disable */
-#define DCR_SE 0x20000000 /* single step enable */
-#define DCR_EBE 0x40000000 /* exception break enable */
-
-/*
- * BRR - Break Interrupt Request Register
- */
-#define BRR_ST 0x00000001 /* single-step detected */
-#define BRR_SB 0x00000002 /* break instruction detected */
-#define BRR_BB 0x00000004 /* branch with hint detected */
-#define BRR_CBB 0x00000008 /* branch to LR detected */
-#define BRR_IBx 0x000000f0 /* hardware breakpoint detected */
-#define BRR_DBx 0x00000f00 /* hardware watchpoint detected */
-#define BRR_DBNEx 0x0000f000 /* ? */
-#define BRR_EBTT 0x00ff0000 /* trap type of exception break */
-#define BRR_TB 0x10000000 /* external break request detected */
-#define BRR_CB 0x20000000 /* ICE break command detected */
-#define BRR_EB 0x40000000 /* exception break detected */
-
-/*
- * BPSR - Break PSR Save Register
- */
-#define BPSR_BET 0x00000001 /* former PSR.ET */
-#define BPSR_BS 0x00001000 /* former PSR.S */
-
-#endif /* _ASM_SPR_REGS_H */
diff --git a/arch/frv/include/asm/string.h b/arch/frv/include/asm/string.h
deleted file mode 100644
index 1f6c35990439..000000000000
--- a/arch/frv/include/asm/string.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* string.h: FRV string handling
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_STRING_H_
-#define _ASM_STRING_H_
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-
-extern void *memset(void *, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-
-#else /* KERNEL */
-
-/*
- * let user libraries deal with these,
- * IMHO the kernel has no place defining these functions for user apps
- */
-
-#define __HAVE_ARCH_STRCPY 1
-#define __HAVE_ARCH_STRNCPY 1
-#define __HAVE_ARCH_STRCAT 1
-#define __HAVE_ARCH_STRNCAT 1
-#define __HAVE_ARCH_STRCMP 1
-#define __HAVE_ARCH_STRNCMP 1
-#define __HAVE_ARCH_STRCHR 1
-#define __HAVE_ARCH_STRRCHR 1
-#define __HAVE_ARCH_STRSTR 1
-#define __HAVE_ARCH_STRLEN 1
-#define __HAVE_ARCH_STRNLEN 1
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-#define __HAVE_ARCH_MEMMOVE 1
-#define __HAVE_ARCH_MEMSCAN 1
-#define __HAVE_ARCH_MEMCMP 1
-#define __HAVE_ARCH_MEMCHR 1
-#define __HAVE_ARCH_STRTOK 1
-
-#endif /* KERNEL */
-#endif /* _ASM_STRING_H_ */
diff --git a/arch/frv/include/asm/switch_to.h b/arch/frv/include/asm/switch_to.h
deleted file mode 100644
index 2cf0f6a7fbb1..000000000000
--- a/arch/frv/include/asm/switch_to.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* FR-V CPU basic task switching
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SWITCH_TO_H
-#define _ASM_SWITCH_TO_H
-
-#include <linux/thread_info.h>
-
-/*
- * switch_to(prev, next) should switch from task `prev' to `next'
- * `prev' will never be the same as `next'.
- * The `mb' is to tell GCC not to cache `current' across this call.
- */
-extern asmlinkage
-struct task_struct *__switch_to(struct thread_struct *prev_thread,
- struct thread_struct *next_thread,
- struct task_struct *prev);
-
-#define switch_to(prev, next, last) \
-do { \
- (prev)->thread.sched_lr = \
- (unsigned long) __builtin_return_address(0); \
- (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
- mb(); \
-} while(0)
-
-#endif /* _ASM_SWITCH_TO_H */
diff --git a/arch/frv/include/asm/syscall.h b/arch/frv/include/asm/syscall.h
deleted file mode 100644
index 70689eb29b98..000000000000
--- a/arch/frv/include/asm/syscall.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* syscall parameter access functions
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_SYSCALL_H
-#define _ASM_SYSCALL_H
-
-#include <linux/err.h>
-#include <asm/ptrace.h>
-
-/*
- * Get the system call number or -1
- */
-static inline long syscall_get_nr(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->syscallno;
-}
-
-/*
- * Restore the clobbered GR8 register
- * (1st syscall arg was overwritten with syscall return or error)
- */
-static inline void syscall_rollback(struct task_struct *task,
- struct pt_regs *regs)
-{
- regs->gr8 = regs->orig_gr8;
-}
-
-/*
- * See if the syscall return value is an error, returning it if it is and 0 if
- * not
- */
-static inline long syscall_get_error(struct task_struct *task,
- struct pt_regs *regs)
-{
- return IS_ERR_VALUE(regs->gr8) ? regs->gr8 : 0;
-}
-
-/*
- * Get the syscall return value
- */
-static inline long syscall_get_return_value(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->gr8;
-}
-
-/*
- * Set the syscall return value
- */
-static inline void syscall_set_return_value(struct task_struct *task,
- struct pt_regs *regs,
- int error, long val)
-{
- if (error)
- regs->gr8 = -error;
- else
- regs->gr8 = val;
-}
-
-/*
- * Retrieve the system call arguments
- */
-static inline void syscall_get_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- unsigned long *args)
-{
- /*
- * Do this simply for now. If we need to start supporting
- * fetching arguments from arbitrary indices, this will need some
- * extra logic. Presently there are no in-tree users that depend
- * on this behaviour.
- */
- BUG_ON(i);
-
- /* Argument pattern is: GR8, GR9, GR10, GR11, GR12, GR13 */
- switch (n) {
- case 6: args[5] = regs->gr13;
- case 5: args[4] = regs->gr12;
- case 4: args[3] = regs->gr11;
- case 3: args[2] = regs->gr10;
- case 2: args[1] = regs->gr9;
- case 1: args[0] = regs->gr8;
- break;
- default:
- BUG();
- }
-}
-
-/*
- * Alter the system call arguments
- */
-static inline void syscall_set_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- const unsigned long *args)
-{
- /* Same note as above applies */
- BUG_ON(i);
-
- switch (n) {
- case 6: regs->gr13 = args[5];
- case 5: regs->gr12 = args[4];
- case 4: regs->gr11 = args[3];
- case 3: regs->gr10 = args[2];
- case 2: regs->gr9 = args[1];
- case 1: regs->gr8 = args[0];
- break;
- default:
- BUG();
- }
-}
-
-#endif /* _ASM_SYSCALL_H */
diff --git a/arch/frv/include/asm/termios.h b/arch/frv/include/asm/termios.h
deleted file mode 100644
index 5a8c63554617..000000000000
--- a/arch/frv/include/asm/termios.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TERMIOS_H
-#define _ASM_TERMIOS_H
-
-#include <uapi/asm/termios.h>
-
-/* intr=^C quit=^| erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#include <asm-generic/termios-base.h>
-#endif /* _ASM_TERMIOS_H */
diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h
deleted file mode 100644
index 0f950845fad9..000000000000
--- a/arch/frv/include/asm/thread_info.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* thread_info.h: description
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * Derived from include/asm-i386/thread_info.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#endif
-
-#define THREAD_SIZE 8192
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long status; /* thread-synchronous flags */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space:
- * 0-0xBFFFFFFF for user-thead
- * 0-0xFFFFFFFF for kernel-thread
- */
-
- __u8 supervisor_stack[0];
-};
-
-#else /* !__ASSEMBLY__ */
-
-#include <asm/asm-offsets.h>
-
-#endif
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-/* how to get the thread information struct from C */
-register struct thread_info *__current_thread_info asm("gr15");
-
-#define current_thread_info() ({ __current_thread_info; })
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_MEMDIE 7 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
-
-/* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK \
- (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_SINGLESTEP)
-
-/* work to do on any return to u-space */
-#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_SYSCALL_TRACE)
-
-#if _TIF_ALLWORK_MASK >= 0x2000
-#error "_TIF_ALLWORK_MASK won't fit in an ANDI now (see entry.S)"
-#endif
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- */
-#define TS_USEDFPM 0x0001 /* FPU/Media was used by this task this quantum (SMP) */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/frv/include/asm/timer-regs.h b/arch/frv/include/asm/timer-regs.h
deleted file mode 100644
index 6c5a871ce5e9..000000000000
--- a/arch/frv/include/asm/timer-regs.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* timer-regs.h: hardware timer register definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_TIMER_REGS_H
-#define _ASM_TIMER_REGS_H
-
-#include <asm/sections.h>
-
-extern unsigned long __nongprelbss __clkin_clock_speed_HZ;
-extern unsigned long __nongprelbss __ext_bus_clock_speed_HZ;
-extern unsigned long __nongprelbss __res_bus_clock_speed_HZ;
-extern unsigned long __nongprelbss __sdram_clock_speed_HZ;
-extern unsigned long __nongprelbss __core_bus_clock_speed_HZ;
-extern unsigned long __nongprelbss __core_clock_speed_HZ;
-extern unsigned long __nongprelbss __dsu_clock_speed_HZ;
-extern unsigned long __nongprelbss __serial_clock_speed_HZ;
-
-#define __get_CLKC() ({ *(volatile unsigned long *)(0xfeff9a00); })
-
-static inline void __set_CLKC(unsigned long v)
-{
- int tmp;
-
- asm volatile(" st%I0.p %2,%M0 \n"
- " setlos %3,%1 \n"
- " membar \n"
- "0: \n"
- " subicc %1,#1,%1,icc0 \n"
- " bnc icc0,#1,0b \n"
- : "=m"(*(volatile unsigned long *) 0xfeff9a00), "=r"(tmp)
- : "r"(v), "i"(256)
- : "icc0");
-}
-
-#define __get_TCTR() ({ *(volatile unsigned long *)(0xfeff9418); })
-#define __get_TPRV() ({ *(volatile unsigned long *)(0xfeff9420); })
-#define __get_TPRCKSL() ({ *(volatile unsigned long *)(0xfeff9428); })
-#define __get_TCSR(T) ({ *(volatile unsigned long *)(0xfeff9400 + 8 * (T)); })
-#define __get_TxCKSL(T) ({ *(volatile unsigned long *)(0xfeff9430 + 8 * (T)); })
-
-#define __get_TCSR_DATA(T) ({ __get_TCSR(T) >> 24; })
-
-#define __set_TCTR(V) do { *(volatile unsigned long *)(0xfeff9418) = (V); mb(); } while(0)
-#define __set_TPRV(V) do { *(volatile unsigned long *)(0xfeff9420) = (V) << 24; mb(); } while(0)
-#define __set_TPRCKSL(V) do { *(volatile unsigned long *)(0xfeff9428) = (V); mb(); } while(0)
-#define __set_TCSR(T,V) \
-do { *(volatile unsigned long *)(0xfeff9400 + 8 * (T)) = (V); mb(); } while(0)
-
-#define __set_TxCKSL(T,V) \
-do { *(volatile unsigned long *)(0xfeff9430 + 8 * (T)) = (V); mb(); } while(0)
-
-#define __set_TCSR_DATA(T,V) __set_TCSR(T, (V) << 24)
-#define __set_TxCKSL_DATA(T,V) __set_TxCKSL(T, TxCKSL_EIGHT | __TxCKSL_SELECT((V)))
-
-/* clock control register */
-#define CLKC_CMODE 0x0f000000
-#define CLKC_SLPL 0x000f0000
-#define CLKC_P0 0x00000100
-#define CLKC_CM 0x00000003
-
-#define CLKC_CMODE_s 24
-
-/* timer control register - non-readback mode */
-#define TCTR_MODE_0 0x00000000
-#define TCTR_MODE_2 0x04000000
-#define TCTR_MODE_4 0x08000000
-#define TCTR_MODE_5 0x0a000000
-#define TCTR_RL_LATCH 0x00000000
-#define TCTR_RL_RW_LOW8 0x10000000
-#define TCTR_RL_RW_HIGH8 0x20000000
-#define TCTR_RL_RW_LH8 0x30000000
-#define TCTR_SC_CTR0 0x00000000
-#define TCTR_SC_CTR1 0x40000000
-#define TCTR_SC_CTR2 0x80000000
-
-/* timer control register - readback mode */
-#define TCTR_CNT0 0x02000000
-#define TCTR_CNT1 0x04000000
-#define TCTR_CNT2 0x08000000
-#define TCTR_NSTATUS 0x10000000
-#define TCTR_NCOUNT 0x20000000
-#define TCTR_SC_READBACK 0xc0000000
-
-/* timer control status registers - non-readback mode */
-#define TCSRx_DATA 0xff000000
-
-/* timer control status registers - readback mode */
-#define TCSRx_OUTPUT 0x80000000
-#define TCSRx_NULLCOUNT 0x40000000
-#define TCSRx_RL 0x30000000
-#define TCSRx_MODE 0x07000000
-
-/* timer clock select registers */
-#define TxCKSL_SELECT 0x0f000000
-#define __TxCKSL_SELECT(X) ((X) << 24)
-#define TxCKSL_EIGHT 0xf0000000
-
-#endif /* _ASM_TIMER_REGS_H */
diff --git a/arch/frv/include/asm/timex.h b/arch/frv/include/asm/timex.h
deleted file mode 100644
index bf53166f2793..000000000000
--- a/arch/frv/include/asm/timex.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* timex.h: FR-V architecture timex specifications
- */
-#ifndef _ASM_TIMEX_H
-#define _ASM_TIMEX_H
-
-#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
-#define CLOCK_TICK_FACTOR 20 /* Factor of both 1000000 and CLOCK_TICK_RATE */
-
-typedef unsigned long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- return 0;
-}
-
-#define vxtime_lock() do {} while (0)
-#define vxtime_unlock() do {} while (0)
-
-/* This attribute is used in include/linux/jiffies.h alongside with
- * __cacheline_aligned_in_smp. It is assumed that __cacheline_aligned_in_smp
- * for frv does not contain another section specification.
- */
-#define __jiffy_arch_data __attribute__((__section__(".data")))
-
-#endif
-
diff --git a/arch/frv/include/asm/tlb.h b/arch/frv/include/asm/tlb.h
deleted file mode 100644
index d3e361ad725a..000000000000
--- a/arch/frv/include/asm/tlb.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TLB_H
-#define _ASM_TLB_H
-
-#include <asm/tlbflush.h>
-
-#ifdef CONFIG_MMU
-extern void check_pgt_cache(void);
-#else
-#define check_pgt_cache() do {} while(0)
-#endif
-
-/*
- * we don't need any special per-pte or per-vma handling...
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it fills up
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _ASM_TLB_H */
-
diff --git a/arch/frv/include/asm/tlbflush.h b/arch/frv/include/asm/tlbflush.h
deleted file mode 100644
index 75879420f578..000000000000
--- a/arch/frv/include/asm/tlbflush.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* tlbflush.h: TLB flushing functions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_TLBFLUSH_H
-#define _ASM_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_MMU
-
-#ifndef __ASSEMBLY__
-extern asmlinkage void __flush_tlb_all(void);
-extern asmlinkage void __flush_tlb_mm(unsigned long contextid);
-extern asmlinkage void __flush_tlb_page(unsigned long contextid, unsigned long start);
-extern asmlinkage void __flush_tlb_range(unsigned long contextid,
- unsigned long start, unsigned long end);
-#endif /* !__ASSEMBLY__ */
-
-#define flush_tlb_all() \
-do { \
- preempt_disable(); \
- __flush_tlb_all(); \
- preempt_enable(); \
-} while(0)
-
-#define flush_tlb_mm(mm) \
-do { \
- preempt_disable(); \
- __flush_tlb_mm((mm)->context.id); \
- preempt_enable(); \
-} while(0)
-
-#define flush_tlb_range(vma,start,end) \
-do { \
- preempt_disable(); \
- __flush_tlb_range((vma)->vm_mm->context.id, start, end); \
- preempt_enable(); \
-} while(0)
-
-#define flush_tlb_page(vma,addr) \
-do { \
- preempt_disable(); \
- __flush_tlb_page((vma)->vm_mm->context.id, addr); \
- preempt_enable(); \
-} while(0)
-
-
-#define __flush_tlb_global() flush_tlb_all()
-#define flush_tlb() flush_tlb_all()
-#define flush_tlb_kernel_range(start, end) flush_tlb_all()
-
-#else
-
-#define flush_tlb() BUG()
-#define flush_tlb_all() BUG()
-#define flush_tlb_mm(mm) BUG()
-#define flush_tlb_page(vma,addr) BUG()
-#define flush_tlb_range(mm,start,end) BUG()
-#define flush_tlb_kernel_range(start, end) BUG()
-
-#endif
-
-
-#endif /* _ASM_TLBFLUSH_H */
diff --git a/arch/frv/include/asm/topology.h b/arch/frv/include/asm/topology.h
deleted file mode 100644
index 207603071f78..000000000000
--- a/arch/frv/include/asm/topology.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TOPOLOGY_H
-#define _ASM_TOPOLOGY_H
-
-#ifdef CONFIG_NUMA
-
-#error NUMA not supported yet
-
-#endif /* CONFIG_NUMA */
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_TOPOLOGY_H */
diff --git a/arch/frv/include/asm/types.h b/arch/frv/include/asm/types.h
deleted file mode 100644
index 6bc63650d832..000000000000
--- a/arch/frv/include/asm/types.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* types.h: FRV types
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-#include <uapi/asm/types.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-
-#define BITS_PER_LONG 32
-
-#endif /* _ASM_TYPES_H */
diff --git a/arch/frv/include/asm/uaccess.h b/arch/frv/include/asm/uaccess.h
deleted file mode 100644
index ff9562dc6825..000000000000
--- a/arch/frv/include/asm/uaccess.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* uaccess.h: userspace accessor functions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UACCESS_H
-#define _ASM_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <asm/segment.h>
-#include <asm/sections.h>
-#include <asm/extable.h>
-
-#define __ptr(x) ((unsigned long __force *)(x))
-
-/*
- * check that a range of addresses falls within the current address limit
- */
-static inline int ___range_ok(unsigned long addr, unsigned long size)
-{
-#ifdef CONFIG_MMU
- int flag = -EFAULT, tmp;
-
- asm volatile (
- " addcc %3,%2,%1,icc0 \n" /* set C-flag if addr+size>4GB */
- " subcc.p %1,%4,gr0,icc1 \n" /* jump if addr+size>limit */
- " bc icc0,#0,0f \n"
- " bhi icc1,#0,0f \n"
- " setlos #0,%0 \n" /* mark okay */
- "0: \n"
- : "=r"(flag), "=&r"(tmp)
- : "r"(addr), "r"(size), "r"(get_addr_limit()), "0"(flag)
- );
-
- return flag;
-
-#else
-
- if (addr < memory_start ||
- addr > memory_end ||
- size > memory_end - memory_start ||
- addr + size > memory_end)
- return -EFAULT;
-
- return 0;
-#endif
-}
-
-#define __range_ok(addr,size) ___range_ok((unsigned long) (addr), (unsigned long) (size))
-
-#define access_ok(type,addr,size) (__range_ok((void __user *)(addr), (size)) == 0)
-#define __access_ok(addr,size) (__range_ok((addr), (size)) == 0)
-
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-#define __put_user(x, ptr) \
-({ \
- int __pu_err = 0; \
- \
- typeof(*(ptr)) __pu_val = (x); \
- __chk_user_ptr(ptr); \
- \
- switch (sizeof (*(ptr))) { \
- case 1: \
- __put_user_asm(__pu_err, __pu_val, ptr, "b", "r"); \
- break; \
- case 2: \
- __put_user_asm(__pu_err, __pu_val, ptr, "h", "r"); \
- break; \
- case 4: \
- __put_user_asm(__pu_err, __pu_val, ptr, "", "r"); \
- break; \
- case 8: \
- __put_user_asm(__pu_err, __pu_val, ptr, "d", "e"); \
- break; \
- default: \
- __pu_err = __put_user_bad(); \
- break; \
- } \
- __pu_err; \
-})
-
-#define put_user(x, ptr) \
-({ \
- typeof(*(ptr)) __user *_p = (ptr); \
- int _e; \
- \
- _e = __range_ok(_p, sizeof(*_p)); \
- if (_e == 0) \
- _e = __put_user((x), _p); \
- _e; \
-})
-
-extern int __put_user_bad(void);
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#ifdef CONFIG_MMU
-
-#define __put_user_asm(err,x,ptr,dsize,constraint) \
-do { \
- asm volatile("1: st"dsize"%I1 %2,%M1 \n" \
- "2: \n" \
- ".subsection 2 \n" \
- "3: setlos %3,%0 \n" \
- " bra 2b \n" \
- ".previous \n" \
- ".section __ex_table,\"a\" \n" \
- " .balign 8 \n" \
- " .long 1b,3b \n" \
- ".previous" \
- : "=r" (err) \
- : "m" (*__ptr(ptr)), constraint (x), "i"(-EFAULT), "0"(err) \
- : "memory"); \
-} while (0)
-
-#else
-
-#define __put_user_asm(err,x,ptr,bwl,con) \
-do { \
- asm(" st"bwl"%I0 %1,%M0 \n" \
- " membar \n" \
- : \
- : "m" (*__ptr(ptr)), con (x) \
- : "memory"); \
-} while (0)
-
-#endif
-
-/*****************************************************************************/
-/*
- *
- */
-#define __get_user(x, ptr) \
-({ \
- int __gu_err = 0; \
- __chk_user_ptr(ptr); \
- \
- switch (sizeof(*(ptr))) { \
- case 1: { \
- unsigned char __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "ub", "=r"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- case 2: { \
- unsigned short __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "uh", "=r"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- case 4: { \
- unsigned int __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "", "=r"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- case 8: { \
- unsigned long long __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "d", "=e"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- default: \
- __gu_err = __get_user_bad(); \
- break; \
- } \
- __gu_err; \
-})
-
-#define get_user(x, ptr) \
-({ \
- const typeof(*(ptr)) __user *_p = (ptr);\
- int _e; \
- \
- _e = __range_ok(_p, sizeof(*_p)); \
- if (likely(_e == 0)) \
- _e = __get_user((x), _p); \
- else \
- (x) = (typeof(x)) 0; \
- _e; \
-})
-
-extern int __get_user_bad(void);
-
-#ifdef CONFIG_MMU
-
-#define __get_user_asm(err,x,ptr,dtype,constraint) \
-do { \
- asm("1: ld"dtype"%I2 %M2,%1 \n" \
- "2: \n" \
- ".subsection 2 \n" \
- "3: setlos %3,%0 \n" \
- " setlos #0,%1 \n" \
- " bra 2b \n" \
- ".previous \n" \
- ".section __ex_table,\"a\" \n" \
- " .balign 8 \n" \
- " .long 1b,3b \n" \
- ".previous" \
- : "=r" (err), constraint (x) \
- : "m" (*__ptr(ptr)), "i"(-EFAULT), "0"(err) \
- ); \
-} while(0)
-
-#else
-
-#define __get_user_asm(err,x,ptr,bwl,con) \
- asm(" ld"bwl"%I1 %M1,%0 \n" \
- " membar \n" \
- : con(x) \
- : "m" (*__ptr(ptr)))
-
-#endif
-
-/*****************************************************************************/
-/*
- *
- */
-
-#define ____force(x) (__force void *)(void __user *)(x)
-#ifdef CONFIG_MMU
-extern long __memset_user(void *dst, unsigned long count);
-extern long __memcpy_user(void *dst, const void *src, unsigned long count);
-
-#define __clear_user(dst,count) __memset_user(____force(dst), (count))
-
-#else
-
-#define __clear_user(dst,count) (memset(____force(dst), 0, (count)), 0)
-
-#endif
-
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-#ifdef CONFIG_MMU
- return __memcpy_user(to, (__force const void *)from, n);
-#else
- memcpy(to, (__force const void *)from, n);
- return 0;
-#endif
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-#ifdef CONFIG_MMU
- return __memcpy_user((__force void *)to, from, n);
-#else
- memcpy((__force void *)to, from, n);
- return 0;
-#endif
-}
-#define INLINE_COPY_TO_USER
-#define INLINE_COPY_FROM_USER
-
-static inline unsigned long __must_check
-clear_user(void __user *to, unsigned long n)
-{
- if (likely(__access_ok(to, n)))
- n = __clear_user(to, n);
- return n;
-}
-
-extern long strncpy_from_user(char *dst, const char __user *src, long count);
-extern long strnlen_user(const char __user *src, long count);
-
-#endif /* _ASM_UACCESS_H */
diff --git a/arch/frv/include/asm/ucontext.h b/arch/frv/include/asm/ucontext.h
deleted file mode 100644
index 0cc2d95dd209..000000000000
--- a/arch/frv/include/asm/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_UCONTEXT_H
-#define _ASM_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif
diff --git a/arch/frv/include/asm/unaligned.h b/arch/frv/include/asm/unaligned.h
deleted file mode 100644
index 6c61c05b2e0c..000000000000
--- a/arch/frv/include/asm/unaligned.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* unaligned.h: unaligned access handler
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNALIGNED_H
-#define _ASM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_struct.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-
-#endif /* _ASM_UNALIGNED_H */
diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h
deleted file mode 100644
index b4b3f9b26b81..000000000000
--- a/arch/frv/include/asm/unistd.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_UNISTD_H_
-#define _ASM_UNISTD_H_
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 338
-
-/* #define __ARCH_WANT_OLD_READDIR */
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-/* #define __ARCH_WANT_SYS_GETHOSTNAME */
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-/* #define __ARCH_WANT_SYS_SIGNAL */
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-/* #define __ARCH_WANT_SYS_OLD_GETRLIMIT */
-#define __ARCH_WANT_SYS_OLDUMOUNT
-/* #define __ARCH_WANT_SYS_SIGPENDING */
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-#define __ARCH_WANT_SYS_CLONE
-
-#endif /* _ASM_UNISTD_H_ */
diff --git a/arch/frv/include/asm/user.h b/arch/frv/include/asm/user.h
deleted file mode 100644
index 82fa8fab64ae..000000000000
--- a/arch/frv/include/asm/user.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* user.h: FR-V core file format stuff
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_USER_H
-#define _ASM_USER_H
-
-#include <asm/page.h>
-#include <asm/registers.h>
-
-/* Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the 'trad-core' bfd). There are quite a number of
- * obstacles to being able to view the contents of the floating point
- * registers, and until these are solved you will not be able to view
- * the contents of them. Actually, you can read in the core file and
- * look at the contents of the user struct to find out what the
- * floating point registers contain.
- *
- * The actual file contents are as follows:
- * UPAGE:
- * 1 page consisting of a user struct that tells gdb what is present
- * in the file. Directly after this is a copy of the task_struct,
- * which is currently not used by gdb, but it may come in useful at
- * some point. All of the registers are stored as part of the
- * upage. The upage should always be only one page.
- *
- * DATA:
- * The data area is stored. We use current->end_text to
- * current->brk to pick up all of the user variables, plus any
- * memory that may have been malloced. No attempt is made to
- * determine if a page is demand-zero or if a page is totally
- * unused, we just cover the entire range. All of the addresses are
- * rounded in such a way that an integral number of pages is
- * written.
- *
- * STACK:
- * We need the stack information in order to get a meaningful
- * backtrace. We need to write the data from (esp) to
- * current->start_stack, so we round each of these off in order to
- * be able to write an integer number of pages. The minimum core
- * file size is 3 pages, or 12288 bytes.
- */
-
-/* When the kernel dumps core, it starts by dumping the user struct -
- * this will be used by gdb to figure out where the data and stack segments
- * are within the file, and what virtual addresses to use.
- */
-struct user {
- /* We start with the registers, to mimic the way that "memory" is returned
- * from the ptrace(3,...) function. */
- struct user_context regs;
-
- /* The rest of this junk is to help gdb figure out what goes where */
- unsigned long u_tsize; /* Text segment size (pages). */
- unsigned long u_dsize; /* Data segment size (pages). */
- unsigned long u_ssize; /* Stack segment size (pages). */
- unsigned long start_code; /* Starting virtual address of text. */
- unsigned long start_stack; /* Starting virtual address of stack area.
- * This is actually the bottom of the stack,
- * the top of the stack is always found in the
- * esp register. */
- long int signal; /* Signal that caused the core dump. */
-
- unsigned long magic; /* To uniquely identify a core file */
- char u_comm[32]; /* User command that was responsible */
-};
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif
diff --git a/arch/frv/include/asm/vga.h b/arch/frv/include/asm/vga.h
deleted file mode 100644
index a702c800a229..000000000000
--- a/arch/frv/include/asm/vga.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* vga.h: VGA register stuff
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_VGA_H
-#define _ASM_VGA_H
-
-
-
-#endif /* _ASM_VGA_H */
diff --git a/arch/frv/include/asm/virtconvert.h b/arch/frv/include/asm/virtconvert.h
deleted file mode 100644
index b26d70ab9111..000000000000
--- a/arch/frv/include/asm/virtconvert.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* virtconvert.h: virtual/physical/page address conversion
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_VIRTCONVERT_H
-#define _ASM_VIRTCONVERT_H
-
-/*
- * Macros used for converting between virtual and physical mappings.
- */
-
-#ifdef __KERNEL__
-
-#include <asm/setup.h>
-
-#ifdef CONFIG_MMU
-
-#define phys_to_virt(vaddr) ((void *) ((unsigned long)(vaddr) + PAGE_OFFSET))
-#define virt_to_phys(vaddr) ((unsigned long) (vaddr) - PAGE_OFFSET)
-
-#else
-
-#define phys_to_virt(vaddr) ((void *) (vaddr))
-#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
-
-#endif
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
-#define page_to_phys(page) virt_to_phys((void *)__page_address(page))
-
-#endif
-#endif
diff --git a/arch/frv/include/asm/xor.h b/arch/frv/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/frv/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/arch/frv/include/uapi/asm/Kbuild b/arch/frv/include/uapi/asm/Kbuild
deleted file mode 100644
index 5354b0f84d41..000000000000
--- a/arch/frv/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,5 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += siginfo.h
-generic-y += bpf_perf_event.h
diff --git a/arch/frv/include/uapi/asm/auxvec.h b/arch/frv/include/uapi/asm/auxvec.h
deleted file mode 100644
index 07710778fa10..000000000000
--- a/arch/frv/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __FRV_AUXVEC_H
-#define __FRV_AUXVEC_H
-
-#endif
diff --git a/arch/frv/include/uapi/asm/bitsperlong.h b/arch/frv/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 76da34b10f59..000000000000
--- a/arch/frv/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/frv/include/uapi/asm/byteorder.h b/arch/frv/include/uapi/asm/byteorder.h
deleted file mode 100644
index a46f6472acdc..000000000000
--- a/arch/frv/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_BYTEORDER_H
-#define _ASM_BYTEORDER_H
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/frv/include/uapi/asm/errno.h b/arch/frv/include/uapi/asm/errno.h
deleted file mode 100644
index c5b82f2f2970..000000000000
--- a/arch/frv/include/uapi/asm/errno.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_ERRNO_H
-#define _ASM_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _ASM_ERRNO_H */
-
diff --git a/arch/frv/include/uapi/asm/fcntl.h b/arch/frv/include/uapi/asm/fcntl.h
deleted file mode 100644
index a77648c505d1..000000000000
--- a/arch/frv/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/fcntl.h>
diff --git a/arch/frv/include/uapi/asm/ioctl.h b/arch/frv/include/uapi/asm/ioctl.h
deleted file mode 100644
index b809c4566e5f..000000000000
--- a/arch/frv/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ioctl.h>
diff --git a/arch/frv/include/uapi/asm/ioctls.h b/arch/frv/include/uapi/asm/ioctls.h
deleted file mode 100644
index dd9f5eb9feda..000000000000
--- a/arch/frv/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASM_IOCTLS_H__
-#define __ASM_IOCTLS_H__
-
-#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
-#define FIOQSIZE 0x545E
-
-#include <asm-generic/ioctls.h>
-
-#endif /* __ASM_IOCTLS_H__ */
-
diff --git a/arch/frv/include/uapi/asm/ipcbuf.h b/arch/frv/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 90d6445a14df..000000000000
--- a/arch/frv/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/frv/include/uapi/asm/kvm_para.h b/arch/frv/include/uapi/asm/kvm_para.h
deleted file mode 100644
index baacc4996d18..000000000000
--- a/arch/frv/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/kvm_para.h>
diff --git a/arch/frv/include/uapi/asm/mman.h b/arch/frv/include/uapi/asm/mman.h
deleted file mode 100644
index 306fc0460b80..000000000000
--- a/arch/frv/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/mman.h>
diff --git a/arch/frv/include/uapi/asm/msgbuf.h b/arch/frv/include/uapi/asm/msgbuf.h
deleted file mode 100644
index 156c81bb46d7..000000000000
--- a/arch/frv/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_MSGBUF_H
-#define _ASM_MSGBUF_H
-
-/*
- * The msqid64_ds structure for FR-V architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
- struct ipc64_perm msg_perm;
- __kernel_time_t msg_stime; /* last msgsnd time */
- unsigned long __unused1;
- __kernel_time_t msg_rtime; /* last msgrcv time */
- unsigned long __unused2;
- __kernel_time_t msg_ctime; /* last change time */
- unsigned long __unused3;
- unsigned long msg_cbytes; /* current number of bytes on queue */
- unsigned long msg_qnum; /* number of messages in queue */
- unsigned long msg_qbytes; /* max number of bytes on queue */
- __kernel_pid_t msg_lspid; /* pid of last msgsnd */
- __kernel_pid_t msg_lrpid; /* last receive pid */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-#endif /* _ASM_MSGBUF_H */
-
diff --git a/arch/frv/include/uapi/asm/param.h b/arch/frv/include/uapi/asm/param.h
deleted file mode 100644
index d3e0168d8937..000000000000
--- a/arch/frv/include/uapi/asm/param.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_PARAM_H
-#define _ASM_PARAM_H
-
-#define EXEC_PAGESIZE 16384
-
-#include <asm-generic/param.h>
-
-#endif /* _ASM_PARAM_H */
diff --git a/arch/frv/include/uapi/asm/poll.h b/arch/frv/include/uapi/asm/poll.h
deleted file mode 100644
index f55b45f475ec..000000000000
--- a/arch/frv/include/uapi/asm/poll.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_POLL_H
-#define _ASM_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-
-#include <asm-generic/poll.h>
-#undef POLLREMOVE
-
-#endif
diff --git a/arch/frv/include/uapi/asm/posix_types.h b/arch/frv/include/uapi/asm/posix_types.h
deleted file mode 100644
index 2995777227b3..000000000000
--- a/arch/frv/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_POSIX_TYPES_H
-#define _ASM_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif
-
diff --git a/arch/frv/include/uapi/asm/ptrace.h b/arch/frv/include/uapi/asm/ptrace.h
deleted file mode 100644
index f1d2f652d083..000000000000
--- a/arch/frv/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* ptrace.h: ptrace() relevant definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _UAPI_ASM_PTRACE_H
-#define _UAPI_ASM_PTRACE_H
-
-#include <asm/registers.h>
-
-
-#define PT_PSR 0
-#define PT_ISR 1
-#define PT_CCR 2
-#define PT_CCCR 3
-#define PT_LR 4
-#define PT_LCR 5
-#define PT_PC 6
-
-#define PT__STATUS 7 /* exception status */
-#define PT_SYSCALLNO 8 /* syscall number or -1 */
-#define PT_ORIG_GR8 9 /* saved GR8 for signal handling */
-#define PT_GNER0 10
-#define PT_GNER1 11
-#define PT_IACC0H 12
-#define PT_IACC0L 13
-
-#define PT_GR(j) ( 14 + (j)) /* GRj for 0<=j<=63 */
-#define PT_FR(j) ( 78 + (j)) /* FRj for 0<=j<=63 */
-#define PT_FNER(j) (142 + (j)) /* FNERj for 0<=j<=1 */
-#define PT_MSR(j) (144 + (j)) /* MSRj for 0<=j<=2 */
-#define PT_ACC(j) (146 + (j)) /* ACCj for 0<=j<=7 */
-#define PT_ACCG(jklm) (154 + (jklm)) /* ACCGjklm for 0<=jklm<=1 (reads four regs per slot) */
-#define PT_FSR(j) (156 + (j)) /* FSRj for 0<=j<=0 */
-#define PT__GPEND 78
-#define PT__END 157
-
-#define PT_TBR PT_GR(0)
-#define PT_SP PT_GR(1)
-#define PT_FP PT_GR(2)
-#define PT_PREV_FRAME PT_GR(28) /* previous exception frame pointer (old gr28 value) */
-#define PT_CURR_TASK PT_GR(29) /* current task */
-
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#endif /* _UAPI_ASM_PTRACE_H */
diff --git a/arch/frv/include/uapi/asm/registers.h b/arch/frv/include/uapi/asm/registers.h
deleted file mode 100644
index 4caf09b6c193..000000000000
--- a/arch/frv/include/uapi/asm/registers.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* registers.h: register frame declarations
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * notes:
- *
- * (1) that the members of all these structures are carefully aligned to permit
- * usage of STD/STDF instructions
- *
- * (2) if you change these structures, you must change the code in
- * arch/frvnommu/kernel/{break.S,entry.S,switch_to.S,gdb-stub.c}
- *
- *
- * the kernel stack space block looks like this:
- *
- * +0x2000 +----------------------
- * | union {
- * | struct frv_frame0 {
- * | struct user_context {
- * | struct user_int_regs
- * | struct user_fpmedia_regs
- * | }
- * | struct frv_debug_regs
- * | }
- * | struct pt_regs [user exception]
- * | }
- * +---------------------- <-- __kernel_frame0_ptr (maybe GR28)
- * |
- * | kernel stack
- * |
- * |......................
- * | struct pt_regs [kernel exception]
- * |...................... <-- __kernel_frame0_ptr (maybe GR28)
- * |
- * | kernel stack
- * |
- * |...................... <-- stack pointer (GR1)
- * |
- * | unused stack space
- * |
- * +----------------------
- * | struct thread_info
- * +0x0000 +---------------------- <-- __current_thread_info (GR15);
- *
- * note that GR28 points to the current exception frame
- */
-
-#ifndef _ASM_REGISTERS_H
-#define _ASM_REGISTERS_H
-
-#ifndef __ASSEMBLY__
-#define __OFFSET(X,N) ((X)+(N)*4)
-#define __OFFSETC(X,N) xxxxxxxxxxxxxxxxxxxxxxxx
-#else
-#define __OFFSET(X,N) ((X)+(N)*4)
-#define __OFFSETC(X,N) ((X)+(N))
-#endif
-
-/*****************************************************************************/
-/*
- * Exception/Interrupt frame
- * - held on kernel stack
- * - 8-byte aligned on stack (old SP is saved in frame)
- * - GR0 is fixed 0, so we don't save it
- */
-#ifndef __ASSEMBLY__
-
-struct pt_regs {
- unsigned long psr; /* Processor Status Register */
- unsigned long isr; /* Integer Status Register */
- unsigned long ccr; /* Condition Code Register */
- unsigned long cccr; /* Condition Code for Conditional Insns Register */
- unsigned long lr; /* Link Register */
- unsigned long lcr; /* Loop Count Register */
- unsigned long pc; /* Program Counter Register */
- unsigned long __status; /* exception status */
- unsigned long syscallno; /* syscall number or -1 */
- unsigned long orig_gr8; /* original syscall arg #1 */
- unsigned long gner0;
- unsigned long gner1;
- unsigned long long iacc0;
- unsigned long tbr; /* GR0 is fixed zero, so we use this for TBR */
- unsigned long sp; /* GR1: USP/KSP */
- unsigned long fp; /* GR2: FP */
- unsigned long gr3;
- unsigned long gr4;
- unsigned long gr5;
- unsigned long gr6;
- unsigned long gr7; /* syscall number */
- unsigned long gr8; /* 1st syscall param; syscall return */
- unsigned long gr9; /* 2nd syscall param */
- unsigned long gr10; /* 3rd syscall param */
- unsigned long gr11; /* 4th syscall param */
- unsigned long gr12; /* 5th syscall param */
- unsigned long gr13; /* 6th syscall param */
- unsigned long gr14;
- unsigned long gr15;
- unsigned long gr16; /* GP pointer */
- unsigned long gr17; /* small data */
- unsigned long gr18; /* PIC/PID */
- unsigned long gr19;
- unsigned long gr20;
- unsigned long gr21;
- unsigned long gr22;
- unsigned long gr23;
- unsigned long gr24;
- unsigned long gr25;
- unsigned long gr26;
- unsigned long gr27;
- struct pt_regs *next_frame; /* GR28 - next exception frame */
- unsigned long gr29; /* GR29 - OS reserved */
- unsigned long gr30; /* GR30 - OS reserved */
- unsigned long gr31; /* GR31 - OS reserved */
-} __attribute__((aligned(8)));
-
-#endif
-
-#define REG__STATUS_STEP 0x00000001 /* - reenable single stepping on return */
-#define REG__STATUS_STEPPED 0x00000002 /* - single step caused exception */
-#define REG__STATUS_BROKE 0x00000004 /* - BREAK insn caused exception */
-#define REG__STATUS_SYSC_ENTRY 0x40000000 /* - T on syscall entry (ptrace.c only) */
-#define REG__STATUS_SYSC_EXIT 0x80000000 /* - T on syscall exit (ptrace.c only) */
-
-#define REG_GR(R) __OFFSET(REG_GR0, (R))
-
-#define REG_SP REG_GR(1)
-#define REG_FP REG_GR(2)
-#define REG_PREV_FRAME REG_GR(28) /* previous exception frame pointer (old gr28 value) */
-#define REG_CURR_TASK REG_GR(29) /* current task */
-
-/*****************************************************************************/
-/*
- * debugging registers
- */
-#ifndef __ASSEMBLY__
-
-struct frv_debug_regs
-{
- unsigned long dcr;
- unsigned long ibar[4] __attribute__((aligned(8)));
- unsigned long dbar[4] __attribute__((aligned(8)));
- unsigned long dbdr[4][4] __attribute__((aligned(8)));
- unsigned long dbmr[4][4] __attribute__((aligned(8)));
-} __attribute__((aligned(8)));
-
-#endif
-
-/*****************************************************************************/
-/*
- * userspace registers
- */
-#ifndef __ASSEMBLY__
-
-struct user_int_regs
-{
- /* integer registers
- * - up to gr[31] mirror pt_regs
- * - total size must be multiple of 8 bytes
- */
- unsigned long psr; /* Processor Status Register */
- unsigned long isr; /* Integer Status Register */
- unsigned long ccr; /* Condition Code Register */
- unsigned long cccr; /* Condition Code for Conditional Insns Register */
- unsigned long lr; /* Link Register */
- unsigned long lcr; /* Loop Count Register */
- unsigned long pc; /* Program Counter Register */
- unsigned long __status; /* exception status */
- unsigned long syscallno; /* syscall number or -1 */
- unsigned long orig_gr8; /* original syscall arg #1 */
- unsigned long gner[2];
- unsigned long long iacc[1];
-
- union {
- unsigned long tbr;
- unsigned long gr[64];
- };
-};
-
-struct user_fpmedia_regs
-{
- /* FP/Media registers */
- unsigned long fr[64];
- unsigned long fner[2];
- unsigned long msr[2];
- unsigned long acc[8];
- unsigned char accg[8];
- unsigned long fsr[1];
-};
-
-struct user_context
-{
- struct user_int_regs i;
- struct user_fpmedia_regs f;
-
- /* we provide a context extension so that we can save the regs for CPUs that
- * implement many more of Fujitsu's lavish register spec
- */
- void *extension;
-} __attribute__((aligned(8)));
-
-struct frv_frame0 {
- union {
- struct pt_regs regs;
- struct user_context uc;
- };
-
- struct frv_debug_regs debug;
-
-} __attribute__((aligned(32)));
-
-#endif
-
-#define __INT_GR(R) __OFFSET(__INT_GR0, (R))
-
-#define __FPMEDIA_FR(R) __OFFSET(__FPMEDIA_FR0, (R))
-#define __FPMEDIA_FNER(R) __OFFSET(__FPMEDIA_FNER0, (R))
-#define __FPMEDIA_MSR(R) __OFFSET(__FPMEDIA_MSR0, (R))
-#define __FPMEDIA_ACC(R) __OFFSET(__FPMEDIA_ACC0, (R))
-#define __FPMEDIA_ACCG(R) __OFFSETC(__FPMEDIA_ACCG0, (R))
-#define __FPMEDIA_FSR(R) __OFFSET(__FPMEDIA_FSR0, (R))
-
-#define __THREAD_GR(R) __OFFSET(__THREAD_GR16, (R) - 16)
-
-#endif /* _ASM_REGISTERS_H */
diff --git a/arch/frv/include/uapi/asm/resource.h b/arch/frv/include/uapi/asm/resource.h
deleted file mode 100644
index 2100305f9b3e..000000000000
--- a/arch/frv/include/uapi/asm/resource.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_RESOURCE_H
-#define _ASM_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _ASM_RESOURCE_H */
-
diff --git a/arch/frv/include/uapi/asm/sembuf.h b/arch/frv/include/uapi/asm/sembuf.h
deleted file mode 100644
index d5477f95832b..000000000000
--- a/arch/frv/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SEMBUF_H
-#define _ASM_SEMBUF_H
-
-/*
- * The semid64_ds structure for FR-V architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
- struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
- __kernel_time_t sem_otime; /* last semop time */
- unsigned long __unused1;
- __kernel_time_t sem_ctime; /* last change time */
- unsigned long __unused2;
- unsigned long sem_nsems; /* no. of semaphores in array */
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_SEMBUF_H */
-
diff --git a/arch/frv/include/uapi/asm/setup.h b/arch/frv/include/uapi/asm/setup.h
deleted file mode 100644
index f54957047900..000000000000
--- a/arch/frv/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* setup.h: setup stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _UAPI_ASM_SETUP_H
-#define _UAPI_ASM_SETUP_H
-
-#define COMMAND_LINE_SIZE 512
-
-
-#endif /* _UAPI_ASM_SETUP_H */
diff --git a/arch/frv/include/uapi/asm/shmbuf.h b/arch/frv/include/uapi/asm/shmbuf.h
deleted file mode 100644
index 1de8f892e412..000000000000
--- a/arch/frv/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SHMBUF_H
-#define _ASM_SHMBUF_H
-
-/*
- * The shmid64_ds structure for FR-V architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
- struct ipc64_perm shm_perm; /* operation perms */
- size_t shm_segsz; /* size of segment (bytes) */
- __kernel_time_t shm_atime; /* last attach time */
- unsigned long __unused1;
- __kernel_time_t shm_dtime; /* last detach time */
- unsigned long __unused2;
- __kernel_time_t shm_ctime; /* last change time */
- unsigned long __unused3;
- __kernel_pid_t shm_cpid; /* pid of creator */
- __kernel_pid_t shm_lpid; /* pid of last operator */
- unsigned long shm_nattch; /* no. of current attaches */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-struct shminfo64 {
- unsigned long shmmax;
- unsigned long shmmin;
- unsigned long shmmni;
- unsigned long shmseg;
- unsigned long shmall;
- unsigned long __unused1;
- unsigned long __unused2;
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_SHMBUF_H */
-
diff --git a/arch/frv/include/uapi/asm/sigcontext.h b/arch/frv/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 8fbb0b00afdd..000000000000
--- a/arch/frv/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* sigcontext.h: FRV signal context
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_SIGCONTEXT_H
-#define _ASM_SIGCONTEXT_H
-
-#include <asm/registers.h>
-
-/*
- * Signal context structure - contains all info to do with the state
- * before the signal handler was invoked. Note: only add new entries
- * to the end of the structure.
- */
-struct sigcontext {
- struct user_context sc_context;
- unsigned long sc_oldmask; /* old sigmask */
-} __attribute__((aligned(8)));
-
-#endif
diff --git a/arch/frv/include/uapi/asm/signal.h b/arch/frv/include/uapi/asm/signal.h
deleted file mode 100644
index 603bb796cf46..000000000000
--- a/arch/frv/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_SIGNAL_H
-#define _UAPI_ASM_SIGNAL_H
-
-#include <linux/types.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* !__KERNEL__ */
-
-#define SA_RESTORER 0x04000000 /* to get struct sigaction correct */
-
-#include <asm-generic/signal.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-#endif /* _UAPI_ASM_SIGNAL_H */
diff --git a/arch/frv/include/uapi/asm/socket.h b/arch/frv/include/uapi/asm/socket.h
deleted file mode 100644
index 9168e78fa32a..000000000000
--- a/arch/frv/include/uapi/asm/socket.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET 1
-
-#define SO_DEBUG 1
-#define SO_REUSEADDR 2
-#define SO_TYPE 3
-#define SO_ERROR 4
-#define SO_DONTROUTE 5
-#define SO_BROADCAST 6
-#define SO_SNDBUF 7
-#define SO_RCVBUF 8
-#define SO_SNDBUFFORCE 32
-#define SO_RCVBUFFORCE 33
-#define SO_KEEPALIVE 9
-#define SO_OOBINLINE 10
-#define SO_NO_CHECK 11
-#define SO_PRIORITY 12
-#define SO_LINGER 13
-#define SO_BSDCOMPAT 14
-#define SO_REUSEPORT 15
-#define SO_PASSCRED 16
-#define SO_PEERCRED 17
-#define SO_RCVLOWAT 18
-#define SO_SNDLOWAT 19
-#define SO_RCVTIMEO 20
-#define SO_SNDTIMEO 21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION 22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
-#define SO_SECURITY_ENCRYPTION_NETWORK 24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER 26
-#define SO_DETACH_FILTER 27
-#define SO_GET_FILTER SO_ATTACH_FILTER
-
-#define SO_PEERNAME 28
-#define SO_TIMESTAMP 29
-#define SCM_TIMESTAMP SO_TIMESTAMP
-
-#define SO_ACCEPTCONN 30
-
-#define SO_PEERSEC 31
-#define SO_PASSSEC 34
-#define SO_TIMESTAMPNS 35
-#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
-
-#define SO_MARK 36
-
-#define SO_TIMESTAMPING 37
-#define SCM_TIMESTAMPING SO_TIMESTAMPING
-
-#define SO_PROTOCOL 38
-#define SO_DOMAIN 39
-
-#define SO_RXQ_OVFL 40
-
-#define SO_WIFI_STATUS 41
-#define SCM_WIFI_STATUS SO_WIFI_STATUS
-#define SO_PEEK_OFF 42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS 43
-
-#define SO_LOCK_FILTER 44
-
-#define SO_SELECT_ERR_QUEUE 45
-
-#define SO_BUSY_POLL 46
-
-#define SO_MAX_PACING_RATE 47
-
-#define SO_BPF_EXTENSIONS 48
-
-#define SO_INCOMING_CPU 49
-
-#define SO_ATTACH_BPF 50
-#define SO_DETACH_BPF SO_DETACH_FILTER
-
-#define SO_ATTACH_REUSEPORT_CBPF 51
-#define SO_ATTACH_REUSEPORT_EBPF 52
-
-#define SO_CNX_ADVICE 53
-
-#define SCM_TIMESTAMPING_OPT_STATS 54
-
-#define SO_MEMINFO 55
-
-#define SO_INCOMING_NAPI_ID 56
-
-#define SO_COOKIE 57
-
-#define SCM_TIMESTAMPING_PKTINFO 58
-
-#define SO_PEERGROUPS 59
-
-#define SO_ZEROCOPY 60
-
-#endif /* _ASM_SOCKET_H */
-
diff --git a/arch/frv/include/uapi/asm/sockios.h b/arch/frv/include/uapi/asm/sockios.h
deleted file mode 100644
index 2f62caf1ce84..000000000000
--- a/arch/frv/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SOCKIOS__
-#define _ASM_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
-#define SIOCSPGRP 0x8902
-#define FIOGETOWN 0x8903
-#define SIOCGPGRP 0x8904
-#define SIOCATMARK 0x8905
-#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
-#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
-
-#endif /* _ASM_SOCKIOS__ */
-
diff --git a/arch/frv/include/uapi/asm/stat.h b/arch/frv/include/uapi/asm/stat.h
deleted file mode 100644
index 0ff9fab915a4..000000000000
--- a/arch/frv/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_STAT_H
-#define _ASM_STAT_H
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-/* This matches struct stat in uClibc/glibc. */
-struct stat {
- unsigned char __pad1[6];
- unsigned short st_dev;
-
- unsigned long __pad2;
- unsigned long st_ino;
-
- unsigned short __pad3;
- unsigned short st_mode;
- unsigned short __pad4;
- unsigned short st_nlink;
-
- unsigned short __pad5;
- unsigned short st_uid;
- unsigned short __pad6;
- unsigned short st_gid;
-
- unsigned char __pad7[6];
- unsigned short st_rdev;
-
- unsigned long __pad8;
- unsigned long st_size;
-
- unsigned long __pad9; /* align 64-bit st_blocks to 2-word */
- unsigned long st_blksize;
-
- unsigned long __pad10; /* future possible st_blocks high bits */
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long __unused1;
- unsigned long st_atime;
-
- unsigned long __unused2;
- unsigned long st_mtime;
-
- unsigned long __unused3;
- unsigned long st_ctime;
-
- unsigned long long __unused4;
-};
-
-/* This matches struct stat64 in uClibc/glibc. The layout is exactly
- the same as that of struct stat above, with 64-bit types taking up
- space that was formerly used by padding. stat syscalls are still
- different from stat64, though, in that the former tests for
- overflow. */
-struct stat64 {
- unsigned char __pad1[6];
- unsigned short st_dev;
-
- unsigned long long st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned char __pad2[6];
- unsigned short st_rdev;
-
- long long st_size;
-
- unsigned long __pad3; /* align 64-bit st_blocks to 2-word */
- unsigned long st_blksize;
-
- unsigned long __pad4; /* future possible st_blocks high bits */
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long st_atime_nsec;
- unsigned long st_atime;
-
- unsigned int st_mtime_nsec;
- unsigned long st_mtime;
-
- unsigned long st_ctime_nsec;
- unsigned long st_ctime;
-
- unsigned long long __unused4;
-};
-
-#endif /* _ASM_STAT_H */
diff --git a/arch/frv/include/uapi/asm/statfs.h b/arch/frv/include/uapi/asm/statfs.h
deleted file mode 100644
index 2a378cbff07f..000000000000
--- a/arch/frv/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_STATFS_H
-#define _ASM_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _ASM_STATFS_H */
-
diff --git a/arch/frv/include/uapi/asm/swab.h b/arch/frv/include/uapi/asm/swab.h
deleted file mode 100644
index c78257d172e5..000000000000
--- a/arch/frv/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SWAB_H
-#define _ASM_SWAB_H
-
-#include <linux/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __SWAB_64_THRU_32__
-#endif
-
-#endif /* _ASM_SWAB_H */
diff --git a/arch/frv/include/uapi/asm/termbits.h b/arch/frv/include/uapi/asm/termbits.h
deleted file mode 100644
index b1dcd8d0ff78..000000000000
--- a/arch/frv/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_TERMBITS_H__
-#define _ASM_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-#define B500000 0010005
-#define B576000 0010006
-#define B921600 0010007
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-#define CIBAUD 002003600000 /* Input baud rate */
-#define CTVB 004000000000 /* VisioBraille Terminal flow control */
-#define CMSPAR 010000000000 /* mark or space (stick) parity */
-#define CRTSCTS 020000000000 /* flow control */
-
-#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif /* _ASM_TERMBITS_H__ */
-
diff --git a/arch/frv/include/uapi/asm/termios.h b/arch/frv/include/uapi/asm/termios.h
deleted file mode 100644
index ae35bedae6a2..000000000000
--- a/arch/frv/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_TERMIOS_H
-#define _UAPI_ASM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-#define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-
-#endif /* _UAPI_ASM_TERMIOS_H */
diff --git a/arch/frv/include/uapi/asm/types.h b/arch/frv/include/uapi/asm/types.h
deleted file mode 100644
index db74ad9ba6c0..000000000000
--- a/arch/frv/include/uapi/asm/types.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* types.h: FRV types
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <asm-generic/int-ll64.h>
diff --git a/arch/frv/include/uapi/asm/unistd.h b/arch/frv/include/uapi/asm/unistd.h
deleted file mode 100644
index 4b46acaf832b..000000000000
--- a/arch/frv/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_UNISTD_H_
-#define _UAPI_ASM_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_lchown 16
-#define __NR_break 17
-#define __NR_oldstat 18
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-#define __NR_oldfstat 28
-#define __NR_pause 29
-#define __NR_utime 30
-#define __NR_stty 31
-#define __NR_gtty 32
-#define __NR_access 33
-#define __NR_nice 34
-#define __NR_ftime 35
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-#define __NR_prof 44
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
-#define __NR_signal 48
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
-#define __NR_lock 53
-#define __NR_ioctl 54
-#define __NR_fcntl 55
-#define __NR_mpx 56
-#define __NR_setpgid 57
-#define __NR_ulimit 58
-// #define __NR_oldolduname /* 59 */ obsolete
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-#define __NR_sigaction 67
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
-#define __NR_sigsuspend 72
-#define __NR_sigpending 73
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
-#define __NR_select 82
-#define __NR_symlink 83
-#define __NR_oldlstat 84
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-#define __NR_readdir 89
-// #define __NR_mmap 90 /* obsolete - not implemented */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-// #define __NR_profil /* 98 */ obsolete
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-// #define __NR_ioperm /* 101 */ not supported
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-// #define __NR_olduname /* 109 */ obsolete
-// #define __NR_iopl /* 110 */ not supported
-#define __NR_vhangup 111
-// #define __NR_idle /* 112 */ Obsolete
-// #define __NR_vm86old /* 113 */ not supported
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-#define __NR_sigreturn 119
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-// #define __NR_modify_ldt /* 123 */ not supported
-#define __NR_cacheflush 123
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-#define __NR_sigprocmask 126
-#define __NR_create_module 127
-#define __NR_init_module 128
-#define __NR_delete_module 129
-#define __NR_get_kernel_syms 130
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
-// #define __NR_vm86 /* 166 */ not supported
-#define __NR_query_module 167
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-#define __NR_chown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-#define __NR_getpmsg 188 /* some people actually want streams */
-#define __NR_putpmsg 189 /* some people actually want streams */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-#define __NR_security 223 /* syscall for security modules */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-/* #define __NR_sys_setaltroot 285 */
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
-#define __NR_migrate_pages 294
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-#define __NR_set_robust_list 311
-#define __NR_get_robust_list 312
-#define __NR_splice 313
-#define __NR_sync_file_range 314
-#define __NR_tee 315
-#define __NR_vmsplice 316
-#define __NR_move_pages 317
-#define __NR_getcpu 318
-#define __NR_epoll_pwait 319
-#define __NR_utimensat 320
-#define __NR_signalfd 321
-#define __NR_timerfd_create 322
-#define __NR_eventfd 323
-#define __NR_fallocate 324
-#define __NR_timerfd_settime 325
-#define __NR_timerfd_gettime 326
-#define __NR_signalfd4 327
-#define __NR_eventfd2 328
-#define __NR_epoll_create1 329
-#define __NR_dup3 330
-#define __NR_pipe2 331
-#define __NR_inotify_init1 332
-#define __NR_preadv 333
-#define __NR_pwritev 334
-#define __NR_rt_tgsigqueueinfo 335
-#define __NR_perf_event_open 336
-#define __NR_setns 337
-
-#endif /* _UAPI_ASM_UNISTD_H_ */
diff --git a/arch/frv/kernel/.gitignore b/arch/frv/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/frv/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/frv/kernel/Makefile b/arch/frv/kernel/Makefile
deleted file mode 100644
index 216ddf30c3c1..000000000000
--- a/arch/frv/kernel/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-heads-y := head-uc-fr401.o head-uc-fr451.o head-uc-fr555.o
-heads-$(CONFIG_MMU) := head-mmu-fr451.o
-
-extra-y:= head.o vmlinux.lds
-
-obj-y := $(heads-y) entry.o entry-table.o break.o switch_to.o \
- process.o traps.o ptrace.o signal.o dma.o \
- sys_frv.o time.o setup.o frv_ksyms.o \
- debug-stub.o irq.o sleep.o uaccess.o
-
-obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-io.o
-
-obj-$(CONFIG_MB93091_VDK) += irq-mb93091.o
-obj-$(CONFIG_PM) += pm.o cmode.o
-obj-$(CONFIG_MB93093_PDK) += pm-mb93093.o
-obj-$(CONFIG_FUJITSU_MB93493) += irq-mb93493.o
-obj-$(CONFIG_SYSCTL) += sysctl.o
-obj-$(CONFIG_FUTEX) += futex.o
-obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/frv/kernel/asm-offsets.c b/arch/frv/kernel/asm-offsets.c
deleted file mode 100644
index 0a468e9b51ad..000000000000
--- a/arch/frv/kernel/asm-offsets.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed
- * to extract and format the required data.
- */
-
-#include <linux/sched.h>
-#include <linux/signal.h>
-#include <linux/personality.h>
-#include <linux/kbuild.h>
-#include <asm/registers.h>
-#include <asm/ucontext.h>
-#include <asm/processor.h>
-#include <asm/thread_info.h>
-#include <asm/gdb-stub.h>
-
-#define DEF_PTREG(sym, reg) OFFSET(sym, pt_regs, reg)
-#define DEF_IREG(sym, reg) OFFSET(sym, user_context, reg)
-#define DEF_FREG(sym, reg) OFFSET(sym, user_context, reg)
-#define DEF_0REG(sym, reg) OFFSET(sym, frv_frame0, reg)
-
-void foo(void)
-{
- /* offsets into the thread_info structure */
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_STATUS, thread_info, status);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PREEMPT_COUNT, thread_info, preempt_count);
- OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
- BLANK();
-
- /* offsets into register file storage */
- DEF_PTREG(REG_PSR, psr);
- DEF_PTREG(REG_ISR, isr);
- DEF_PTREG(REG_CCR, ccr);
- DEF_PTREG(REG_CCCR, cccr);
- DEF_PTREG(REG_LR, lr);
- DEF_PTREG(REG_LCR, lcr);
- DEF_PTREG(REG_PC, pc);
- DEF_PTREG(REG__STATUS, __status);
- DEF_PTREG(REG_SYSCALLNO, syscallno);
- DEF_PTREG(REG_ORIG_GR8, orig_gr8);
- DEF_PTREG(REG_GNER0, gner0);
- DEF_PTREG(REG_GNER1, gner1);
- DEF_PTREG(REG_IACC0, iacc0);
- DEF_PTREG(REG_TBR, tbr);
- DEF_PTREG(REG_GR0, tbr);
- DEFINE(REG__END, sizeof(struct pt_regs));
- BLANK();
-
- DEF_0REG(REG_DCR, debug.dcr);
- DEF_0REG(REG_IBAR0, debug.ibar[0]);
- DEF_0REG(REG_DBAR0, debug.dbar[0]);
- DEF_0REG(REG_DBDR00, debug.dbdr[0][0]);
- DEF_0REG(REG_DBMR00, debug.dbmr[0][0]);
- BLANK();
-
- DEF_IREG(__INT_GR0, i.gr[0]);
- DEF_FREG(__USER_FPMEDIA, f);
- DEF_FREG(__FPMEDIA_FR0, f.fr[0]);
- DEF_FREG(__FPMEDIA_FNER0, f.fner[0]);
- DEF_FREG(__FPMEDIA_MSR0, f.msr[0]);
- DEF_FREG(__FPMEDIA_ACC0, f.acc[0]);
- DEF_FREG(__FPMEDIA_ACCG0, f.accg[0]);
- DEF_FREG(__FPMEDIA_FSR0, f.fsr[0]);
- BLANK();
-
- DEFINE(NR_PT_REGS, sizeof(struct pt_regs) / 4);
- DEFINE(NR_USER_INT_REGS, sizeof(struct user_int_regs) / 4);
- DEFINE(NR_USER_FPMEDIA_REGS, sizeof(struct user_fpmedia_regs) / 4);
- DEFINE(NR_USER_CONTEXT, sizeof(struct user_context) / 4);
- DEFINE(FRV_FRAME0_SIZE, sizeof(struct frv_frame0));
- BLANK();
-
- /* offsets into thread_struct */
- OFFSET(__THREAD_FRAME, thread_struct, frame);
- OFFSET(__THREAD_CURR, thread_struct, curr);
- OFFSET(__THREAD_SP, thread_struct, sp);
- OFFSET(__THREAD_FP, thread_struct, fp);
- OFFSET(__THREAD_LR, thread_struct, lr);
- OFFSET(__THREAD_PC, thread_struct, pc);
- OFFSET(__THREAD_GR16, thread_struct, gr[0]);
- OFFSET(__THREAD_SCHED_LR, thread_struct, sched_lr);
- OFFSET(__THREAD_FRAME0, thread_struct, frame0);
- OFFSET(__THREAD_USER, thread_struct, user);
- BLANK();
-
- /* offsets into frv_debug_status */
- OFFSET(DEBUG_BPSR, frv_debug_status, bpsr);
- OFFSET(DEBUG_DCR, frv_debug_status, dcr);
- OFFSET(DEBUG_BRR, frv_debug_status, brr);
- OFFSET(DEBUG_NMAR, frv_debug_status, nmar);
- BLANK();
-}
diff --git a/arch/frv/kernel/break.S b/arch/frv/kernel/break.S
deleted file mode 100644
index cbb6958a3147..000000000000
--- a/arch/frv/kernel/break.S
+++ /dev/null
@@ -1,792 +0,0 @@
-/* break.S: Break interrupt handling (kept separate from entry.S)
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/linkage.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/thread_info.h>
-#include <asm/spr-regs.h>
-
-#include <asm/errno.h>
-
-#
-# the break handler has its own stack
-#
- .section .bss..stack
- .globl __break_user_context
- .balign THREAD_SIZE
-__break_stack:
- .space THREAD_SIZE - FRV_FRAME0_SIZE
-__break_frame_0:
- .space FRV_FRAME0_SIZE
-
-#
-# miscellaneous variables
-#
- .section .bss
-#ifdef CONFIG_MMU
- .globl __break_tlb_miss_real_return_info
-__break_tlb_miss_real_return_info:
- .balign 8
- .space 2*4 /* saved PCSR, PSR for TLB-miss handler fixup */
-#endif
-
-__break_trace_through_exceptions:
- .space 4
-
-#define CS2_ECS1 0xe1200000
-#define CS2_USERLED 0x4
-
-.macro LEDS val,reg
-# sethi.p %hi(CS2_ECS1+CS2_USERLED),gr30
-# setlo %lo(CS2_ECS1+CS2_USERLED),gr30
-# setlos #~\val,\reg
-# st \reg,@(gr30,gr0)
-# setlos #0x5555,\reg
-# sethi.p %hi(0xffc00100),gr30
-# setlo %lo(0xffc00100),gr30
-# sth \reg,@(gr30,gr0)
-# membar
-.endm
-
-###############################################################################
-#
-# entry point for Break Exceptions/Interrupts
-#
-###############################################################################
- .section .text..break
- .balign 4
- .globl __entry_break
-__entry_break:
-#ifdef CONFIG_MMU
- movgs gr31,scr3
-#endif
- LEDS 0x1001,gr31
-
- sethi.p %hi(__break_frame_0),gr31
- setlo %lo(__break_frame_0),gr31
-
- stdi gr2,@(gr31,#REG_GR(2))
- movsg ccr,gr3
- sti gr3,@(gr31,#REG_CCR)
-
- # catch the return from a TLB-miss handler that had single-step disabled
- # traps will be enabled, so we have to do this now
-#ifdef CONFIG_MMU
- movsg bpcsr,gr3
- sethi.p %hi(__break_tlb_miss_return_breaks_here),gr2
- setlo %lo(__break_tlb_miss_return_breaks_here),gr2
- subcc gr2,gr3,gr0,icc0
- beq icc0,#2,__break_return_singlestep_tlbmiss
-#endif
-
- # determine whether we have stepped through into an exception
- # - we need to take special action to suspend h/w single stepping if we've done
- # that, so that the gdbstub doesn't get bogged down endlessly stepping through
- # external interrupt handling
- movsg bpsr,gr3
- andicc gr3,#BPSR_BET,gr0,icc0
- bne icc0,#2,__break_maybe_userspace /* jump if PSR.ET was 1 */
-
- LEDS 0x1003,gr2
-
- movsg brr,gr3
- andicc gr3,#BRR_ST,gr0,icc0
- andicc.p gr3,#BRR_SB,gr0,icc1
- bne icc0,#2,__break_step /* jump if single-step caused break */
- beq icc1,#2,__break_continue /* jump if BREAK didn't cause break */
-
- LEDS 0x1007,gr2
-
- # handle special breaks
- movsg bpcsr,gr3
-
- sethi.p %hi(__entry_return_singlestep_breaks_here),gr2
- setlo %lo(__entry_return_singlestep_breaks_here),gr2
- subcc gr2,gr3,gr0,icc0
- beq icc0,#2,__break_return_singlestep
-
- bra __break_continue
-
-
-###############################################################################
-#
-# handle BREAK instruction in kernel-mode exception epilogue
-#
-###############################################################################
-__break_return_singlestep:
- LEDS 0x100f,gr2
-
- # special break insn requests single-stepping to be turned back on
- # HERE RETT
- # PSR.ET 0 0
- # PSR.PS old PSR.S ?
- # PSR.S 1 1
- # BPSR.ET 0 1 (can't have caused orig excep otherwise)
- # BPSR.BS 1 old PSR.S
- movsg dcr,gr2
- sethi.p %hi(DCR_SE),gr3
- setlo %lo(DCR_SE),gr3
- or gr2,gr3,gr2
- movgs gr2,dcr
-
- movsg psr,gr2
- andi gr2,#PSR_PS,gr2
- slli gr2,#11,gr2 /* PSR.PS -> BPSR.BS */
- ori gr2,#BPSR_BET,gr2 /* 1 -> BPSR.BET */
- movgs gr2,bpsr
-
- # return to the invoker of the original kernel exception
- movsg pcsr,gr2
- movgs gr2,bpcsr
-
- LEDS 0x101f,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-###############################################################################
-#
-# handle BREAK instruction in TLB-miss handler return path
-#
-###############################################################################
-#ifdef CONFIG_MMU
-__break_return_singlestep_tlbmiss:
- LEDS 0x1100,gr2
-
- sethi.p %hi(__break_tlb_miss_real_return_info),gr3
- setlo %lo(__break_tlb_miss_real_return_info),gr3
- lddi @(gr3,#0),gr2
- movgs gr2,pcsr
- movgs gr3,psr
-
- bra __break_return_singlestep
-#endif
-
-
-###############################################################################
-#
-# handle single stepping into an exception prologue from kernel mode
-# - we try and catch it whilst it is still in the main vector table
-# - if we catch it there, we have to jump to the fixup handler
-# - there is a fixup table that has a pointer for every 16b slot in the trap
-# table
-#
-###############################################################################
-__break_step:
- LEDS 0x2003,gr2
-
- # external interrupts seem to escape from the trap table before single
- # step catches up with them
- movsg bpcsr,gr2
- sethi.p %hi(__entry_kernel_external_interrupt),gr3
- setlo %lo(__entry_kernel_external_interrupt),gr3
- subcc.p gr2,gr3,gr0,icc0
- sethi %hi(__entry_uspace_external_interrupt),gr3
- setlo.p %lo(__entry_uspace_external_interrupt),gr3
- beq icc0,#2,__break_step_kernel_external_interrupt
- subcc.p gr2,gr3,gr0,icc0
- sethi %hi(__entry_kernel_external_interrupt_virtually_disabled),gr3
- setlo.p %lo(__entry_kernel_external_interrupt_virtually_disabled),gr3
- beq icc0,#2,__break_step_uspace_external_interrupt
- subcc.p gr2,gr3,gr0,icc0
- sethi %hi(__entry_kernel_external_interrupt_virtual_reenable),gr3
- setlo.p %lo(__entry_kernel_external_interrupt_virtual_reenable),gr3
- beq icc0,#2,__break_step_kernel_external_interrupt_virtually_disabled
- subcc gr2,gr3,gr0,icc0
- beq icc0,#2,__break_step_kernel_external_interrupt_virtual_reenable
-
- LEDS 0x2007,gr2
-
- # the two main vector tables are adjacent on one 8Kb slab
- movsg bpcsr,gr2
- setlos #0xffffe000,gr3
- and gr2,gr3,gr2
- sethi.p %hi(__trap_tables),gr3
- setlo %lo(__trap_tables),gr3
- subcc gr2,gr3,gr0,icc0
- bne icc0,#2,__break_continue
-
- LEDS 0x200f,gr2
-
- # skip workaround if so requested by GDB
- sethi.p %hi(__break_trace_through_exceptions),gr3
- setlo %lo(__break_trace_through_exceptions),gr3
- ld @(gr3,gr0),gr3
- subcc gr3,gr0,gr0,icc0
- bne icc0,#0,__break_continue
-
- LEDS 0x201f,gr2
-
- # access the fixup table - there's a 1:1 mapping between the slots in the trap tables and
- # the slots in the trap fixup tables allowing us to simply divide the offset into the
- # former by 4 to access the latter
- sethi.p %hi(__trap_tables),gr3
- setlo %lo(__trap_tables),gr3
- movsg bpcsr,gr2
- sub gr2,gr3,gr2
- srli.p gr2,#2,gr2
-
- sethi %hi(__trap_fixup_tables),gr3
- setlo.p %lo(__trap_fixup_tables),gr3
- andi gr2,#~3,gr2
- ld @(gr2,gr3),gr2
- jmpil @(gr2,#0)
-
-# step through an internal exception from kernel mode
- .globl __break_step_kernel_softprog_interrupt
-__break_step_kernel_softprog_interrupt:
- sethi.p %hi(__entry_kernel_softprog_interrupt_reentry),gr3
- setlo %lo(__entry_kernel_softprog_interrupt_reentry),gr3
- bra __break_return_as_kernel_prologue
-
-# step through an external interrupt from kernel mode
- .globl __break_step_kernel_external_interrupt
-__break_step_kernel_external_interrupt:
- # deal with virtual interrupt disablement
- beq icc2,#0,__break_step_kernel_external_interrupt_virtually_disabled
-
- sethi.p %hi(__entry_kernel_external_interrupt_reentry),gr3
- setlo %lo(__entry_kernel_external_interrupt_reentry),gr3
-
-__break_return_as_kernel_prologue:
- LEDS 0x203f,gr2
-
- movgs gr3,bpcsr
-
- # do the bit we had to skip
-#ifdef CONFIG_MMU
- movsg ear0,gr2 /* EAR0 can get clobbered by gdb-stub (ICI/ICEI) */
- movgs gr2,scr2
-#endif
-
- or.p sp,gr0,gr2 /* set up the stack pointer */
- subi sp,#REG__END,sp
- sti.p gr2,@(sp,#REG_SP)
-
- setlos #REG__STATUS_STEP,gr2
- sti gr2,@(sp,#REG__STATUS) /* record single step status */
-
- # cancel single-stepping mode
- movsg dcr,gr2
- sethi.p %hi(~DCR_SE),gr3
- setlo %lo(~DCR_SE),gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
-
- LEDS 0x207f,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-# we single-stepped into an interrupt handler whilst interrupts were merely virtually disabled
-# need to really disable interrupts, set flag, fix up and return
-__break_step_kernel_external_interrupt_virtually_disabled:
- movsg psr,gr2
- andi gr2,#~PSR_PIL,gr2
- ori gr2,#PSR_PIL_14,gr2 /* debugging interrupts only */
- movgs gr2,psr
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- subcc.p gr0,gr0,gr0,icc2 /* leave Z set, clear C */
-
- # exceptions must've been enabled and we must've been in supervisor mode
- setlos BPSR_BET|BPSR_BS,gr3
- movgs gr3,bpsr
-
- # return to where the interrupt happened
- movsg pcsr,gr2
- movgs gr2,bpcsr
-
- lddi.p @(gr31,#REG_GR(2)),gr2
-
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-# we stepped through into the virtual interrupt reenablement trap
-#
-# we also want to single step anyway, but after fixing up so that we get an event on the
-# instruction after the broken-into exception returns
- .globl __break_step_kernel_external_interrupt_virtual_reenable
-__break_step_kernel_external_interrupt_virtual_reenable:
- movsg psr,gr2
- andi gr2,#~PSR_PIL,gr2
- movgs gr2,psr
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- subicc gr0,#1,gr0,icc2 /* clear Z, set C */
-
- # save the adjusted ICC2
- movsg ccr,gr3
- sti gr3,@(gr31,#REG_CCR)
-
- # exceptions must've been enabled and we must've been in supervisor mode
- setlos BPSR_BET|BPSR_BS,gr3
- movgs gr3,bpsr
-
- # return to where the trap happened
- movsg pcsr,gr2
- movgs gr2,bpcsr
-
- # and then process the single step
- bra __break_continue
-
-# step through an internal exception from uspace mode
- .globl __break_step_uspace_softprog_interrupt
-__break_step_uspace_softprog_interrupt:
- sethi.p %hi(__entry_uspace_softprog_interrupt_reentry),gr3
- setlo %lo(__entry_uspace_softprog_interrupt_reentry),gr3
- bra __break_return_as_uspace_prologue
-
-# step through an external interrupt from kernel mode
- .globl __break_step_uspace_external_interrupt
-__break_step_uspace_external_interrupt:
- sethi.p %hi(__entry_uspace_external_interrupt_reentry),gr3
- setlo %lo(__entry_uspace_external_interrupt_reentry),gr3
-
-__break_return_as_uspace_prologue:
- LEDS 0x20ff,gr2
-
- movgs gr3,bpcsr
-
- # do the bit we had to skip
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi.p @(gr28,#0),gr28
-
- setlos #REG__STATUS_STEP,gr2
- sti gr2,@(gr28,#REG__STATUS) /* record single step status */
-
- # cancel single-stepping mode
- movsg dcr,gr2
- sethi.p %hi(~DCR_SE),gr3
- setlo %lo(~DCR_SE),gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
-
- LEDS 0x20fe,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-#ifdef CONFIG_MMU
-# step through an ITLB-miss handler from user mode
- .globl __break_user_insn_tlb_miss
-__break_user_insn_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_user_insn_tlb_miss),gr2
- setlo %lo(__trap_user_insn_tlb_miss),gr2
- movgs gr2,bpcsr
-
-__break_tlb_miss_common:
- LEDS 0x2101,gr2
-
- # cancel single-stepping mode
- movsg dcr,gr2
- sethi.p %hi(~DCR_SE),gr3
- setlo %lo(~DCR_SE),gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
-
- # we'll swap the real return address for one with a BREAK insn so that we can re-enable
- # single stepping on return
- movsg pcsr,gr2
- sethi.p %hi(__break_tlb_miss_real_return_info),gr3
- setlo %lo(__break_tlb_miss_real_return_info),gr3
- sti gr2,@(gr3,#0)
-
- sethi.p %hi(__break_tlb_miss_return_break),gr2
- setlo %lo(__break_tlb_miss_return_break),gr2
- movgs gr2,pcsr
-
- # we also have to fudge PSR because the return BREAK is in kernel space and we want
- # to get a BREAK fault not an access violation should the return be to userspace
- movsg psr,gr2
- sti.p gr2,@(gr3,#4)
- ori gr2,#PSR_PS,gr2
- movgs gr2,psr
-
- LEDS 0x2102,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi @(gr31,#REG_GR(2)),gr2
- movsg scr3,gr31
- movgs gr0,brr
- rett #1
-
-# step through a DTLB-miss handler from user mode
- .globl __break_user_data_tlb_miss
-__break_user_data_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_user_data_tlb_miss),gr2
- setlo %lo(__trap_user_data_tlb_miss),gr2
- movgs gr2,bpcsr
- bra __break_tlb_miss_common
-
-# step through an ITLB-miss handler from kernel mode
- .globl __break_kernel_insn_tlb_miss
-__break_kernel_insn_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_kernel_insn_tlb_miss),gr2
- setlo %lo(__trap_kernel_insn_tlb_miss),gr2
- movgs gr2,bpcsr
- bra __break_tlb_miss_common
-
-# step through a DTLB-miss handler from kernel mode
- .globl __break_kernel_data_tlb_miss
-__break_kernel_data_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_kernel_data_tlb_miss),gr2
- setlo %lo(__trap_kernel_data_tlb_miss),gr2
- movgs gr2,bpcsr
- bra __break_tlb_miss_common
-#endif
-
-###############################################################################
-#
-# handle debug events originating with userspace
-#
-###############################################################################
-__break_maybe_userspace:
- LEDS 0x3003,gr2
-
- setlos #BPSR_BS,gr2
- andcc gr3,gr2,gr0,icc0
- bne icc0,#0,__break_continue /* skip if PSR.S was 1 */
-
- movsg brr,gr2
- andicc gr2,#BRR_ST|BRR_SB,gr0,icc0
- beq icc0,#0,__break_continue /* jump if not BREAK or single-step */
-
- LEDS 0x3007,gr2
-
- # do the first part of the exception prologue here
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
- andi gr28,#~7,gr28
-
- # set up the kernel stack pointer
- sti sp ,@(gr28,#REG_SP)
- ori gr28,0,sp
- sti gr0 ,@(gr28,#REG_GR(28))
-
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
-
- movsg tbr,gr20
- movsg bpcsr,gr21
- movsg psr,gr22
-
- # determine the exception type and cancel single-stepping mode
- or gr0,gr0,gr23
-
- movsg dcr,gr2
- sethi.p %hi(DCR_SE),gr3
- setlo %lo(DCR_SE),gr3
- andcc gr2,gr3,gr0,icc0
- beq icc0,#0,__break_no_user_sstep /* must have been a BREAK insn */
-
- not gr3,gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
- ori gr23,#REG__STATUS_STEP,gr23
-
-__break_no_user_sstep:
- LEDS 0x300f,gr2
-
- movsg brr,gr2
- andi gr2,#BRR_ST|BRR_SB,gr2
- slli gr2,#1,gr2
- or gr23,gr2,gr23
- sti.p gr23,@(gr28,#REG__STATUS) /* record single step status */
-
- # adjust the value acquired from TBR - this indicates the exception
- setlos #~TBR_TT,gr2
- and.p gr20,gr2,gr20
- setlos #TBR_TT_BREAK,gr2
- or.p gr20,gr2,gr20
-
- # fudge PSR.PS and BPSR.BS to return to kernel mode through the trap
- # table as trap 126
- andi gr22,#~PSR_PS,gr22 /* PSR.PS should be 0 */
- movgs gr22,psr
-
- setlos #BPSR_BS,gr2 /* BPSR.BS should be 1 and BPSR.BET 0 */
- movgs gr2,bpsr
-
- # return through remainder of the exception prologue
- # - need to load gr23 with return handler address
- sethi.p %hi(__entry_return_from_user_exception),gr23
- setlo %lo(__entry_return_from_user_exception),gr23
- sethi.p %hi(__entry_common),gr3
- setlo %lo(__entry_common),gr3
- movgs gr3,bpcsr
-
- LEDS 0x301f,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-###############################################################################
-#
-# resume normal debug-mode entry
-#
-###############################################################################
-__break_continue:
- LEDS 0x4003,gr2
-
- # set up the kernel stack pointer
- sti sp,@(gr31,#REG_SP)
-
- sethi.p %hi(__break_frame_0),sp
- setlo %lo(__break_frame_0),sp
-
- # finish building the exception frame
- stdi gr4 ,@(gr31,#REG_GR(4))
- stdi gr6 ,@(gr31,#REG_GR(6))
- stdi gr8 ,@(gr31,#REG_GR(8))
- stdi gr10,@(gr31,#REG_GR(10))
- stdi gr12,@(gr31,#REG_GR(12))
- stdi gr14,@(gr31,#REG_GR(14))
- stdi gr16,@(gr31,#REG_GR(16))
- stdi gr18,@(gr31,#REG_GR(18))
- stdi gr20,@(gr31,#REG_GR(20))
- stdi gr22,@(gr31,#REG_GR(22))
- stdi gr24,@(gr31,#REG_GR(24))
- stdi gr26,@(gr31,#REG_GR(26))
- sti gr0 ,@(gr31,#REG_GR(28)) /* NULL frame pointer */
- sti gr29,@(gr31,#REG_GR(29))
- sti gr30,@(gr31,#REG_GR(30))
- sti gr8 ,@(gr31,#REG_ORIG_GR8)
-
-#ifdef CONFIG_MMU
- movsg scr3,gr19
- sti gr19,@(gr31,#REG_GR(31))
-#endif
-
- movsg bpsr ,gr19
- movsg tbr ,gr20
- movsg bpcsr,gr21
- movsg psr ,gr22
- movsg isr ,gr23
- movsg cccr ,gr25
- movsg lr ,gr26
- movsg lcr ,gr27
-
- andi.p gr22,#~(PSR_S|PSR_ET),gr5 /* rebuild PSR */
- andi gr19,#PSR_ET,gr4
- or.p gr4,gr5,gr5
- srli gr19,#10,gr4
- andi gr4,#PSR_S,gr4
- or.p gr4,gr5,gr5
-
- setlos #-1,gr6
- sti gr20,@(gr31,#REG_TBR)
- sti gr21,@(gr31,#REG_PC)
- sti gr5 ,@(gr31,#REG_PSR)
- sti gr23,@(gr31,#REG_ISR)
- sti gr25,@(gr31,#REG_CCCR)
- stdi gr26,@(gr31,#REG_LR)
- sti gr6 ,@(gr31,#REG_SYSCALLNO)
-
- # store CPU-specific regs
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr31,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi gr4,@(gr31,#REG_GNER0)
-
- # build the debug register frame
- movsg brr,gr4
- movgs gr0,brr
- movsg nmar,gr5
- movsg dcr,gr6
-
- sethi.p %hi(__debug_status),gr7
- setlo %lo(__debug_status),gr7
-
- stdi gr4 ,@(gr7,#DEBUG_BRR)
- sti gr19,@(gr7,#DEBUG_BPSR)
- sti.p gr6 ,@(gr7,#DEBUG_DCR)
-
- # trap exceptions during break handling and disable h/w breakpoints/watchpoints
- sethi %hi(DCR_EBE),gr5
- setlo.p %lo(DCR_EBE),gr5
- sethi %hi(__entry_breaktrap_table),gr4
- setlo %lo(__entry_breaktrap_table),gr4
- movgs gr5,dcr
- movgs gr4,tbr
-
- # set up kernel global registers
- sethi.p %hi(__kernel_current_task),gr5
- setlo %lo(__kernel_current_task),gr5
- ld @(gr5,gr0),gr29
- ldi.p @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
-
- sethi %hi(_gp),gr16
- setlo.p %lo(_gp),gr16
-
- # make sure we (the kernel) get div-zero and misalignment exceptions
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # enter the GDB stub
- LEDS 0x4007,gr2
-
- or.p gr0,gr0,fp
- call debug_stub
-
- LEDS 0x403f,gr2
-
- # return from break
- lddi @(gr31,#REG_IACC0),gr4
- movgs gr4,iacc0h
- movgs gr5,iacc0l
-
- lddi @(gr31,#REG_GNER0),gr4
- movgs gr4,gner0
- movgs gr5,gner1
-
- lddi @(gr31,#REG_LR) ,gr26
- lddi @(gr31,#REG_CCR) ,gr24
- lddi @(gr31,#REG_PSR) ,gr22
- ldi @(gr31,#REG_PC) ,gr21
- ldi @(gr31,#REG_TBR) ,gr20
-
- sethi.p %hi(__debug_status),gr6
- setlo %lo(__debug_status),gr6
- ldi.p @(gr6,#DEBUG_DCR) ,gr6
-
- andi gr22,#PSR_S,gr19 /* rebuild BPSR */
- andi.p gr22,#PSR_ET,gr5
- slli gr19,#10,gr19
- or gr5,gr19,gr19
-
- movgs gr6 ,dcr
- movgs gr19,bpsr
- movgs gr20,tbr
- movgs gr21,bpcsr
- movgs gr23,isr
- movgs gr24,ccr
- movgs gr25,cccr
- movgs gr26,lr
- movgs gr27,lcr
-
- LEDS 0x407f,gr2
-
-#ifdef CONFIG_MMU
- ldi @(gr31,#REG_GR(31)),gr2
- movgs gr2,scr3
-#endif
-
- ldi @(gr31,#REG_GR(30)),gr30
- ldi @(gr31,#REG_GR(29)),gr29
- lddi @(gr31,#REG_GR(26)),gr26
- lddi @(gr31,#REG_GR(24)),gr24
- lddi @(gr31,#REG_GR(22)),gr22
- lddi @(gr31,#REG_GR(20)),gr20
- lddi @(gr31,#REG_GR(18)),gr18
- lddi @(gr31,#REG_GR(16)),gr16
- lddi @(gr31,#REG_GR(14)),gr14
- lddi @(gr31,#REG_GR(12)),gr12
- lddi @(gr31,#REG_GR(10)),gr10
- lddi @(gr31,#REG_GR(8)) ,gr8
- lddi @(gr31,#REG_GR(6)) ,gr6
- lddi @(gr31,#REG_GR(4)) ,gr4
- lddi @(gr31,#REG_GR(2)) ,gr2
- ldi.p @(gr31,#REG_SP) ,sp
-
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-###################################################################################################
-#
-# GDB stub "system calls"
-#
-###################################################################################################
-
-#ifdef CONFIG_GDBSTUB
- # void gdbstub_console_write(struct console *con, const char *p, unsigned n)
- .globl gdbstub_console_write
-gdbstub_console_write:
- break
- bralr
-#endif
-
- # GDB stub BUG() trap
- # GR8 is the proposed signal number
- .globl __debug_bug_trap
-__debug_bug_trap:
- break
- bralr
-
- # transfer kernel exeception to GDB for handling
- .globl __break_hijack_kernel_event
-__break_hijack_kernel_event:
- break
- .globl __break_hijack_kernel_event_breaks_here
-__break_hijack_kernel_event_breaks_here:
- nop
-
-#ifdef CONFIG_MMU
- # handle a return from TLB-miss that requires single-step reactivation
- .globl __break_tlb_miss_return_break
-__break_tlb_miss_return_break:
- break
-__break_tlb_miss_return_breaks_here:
- nop
-#endif
-
- # guard the first .text label in the next file from confusion
- nop
diff --git a/arch/frv/kernel/cmode.S b/arch/frv/kernel/cmode.S
deleted file mode 100644
index 53deeb5d7e87..000000000000
--- a/arch/frv/kernel/cmode.S
+++ /dev/null
@@ -1,189 +0,0 @@
-/* cmode.S: clock mode management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Woodhouse (dwmw2@infradead.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <asm/spr-regs.h>
-
-#define __addr_MASK 0xfeff9820 /* interrupt controller mask */
-
-#define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */
-#define SDRAMC_DSTS 0x28 /* SDRAM status */
-#define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
-#define SDRAMC_DRCN 0x30 /* SDRAM refresh control */
-#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
-#define __addr_CLKC 0xfeff9a00
-#define CLKC_SWCMODE 0x00000008
-#define __addr_LEDS 0xe1200004
-
-.macro li v r
- sethi.p %hi(\v),\r
- setlo %lo(\v),\r
-.endm
-
- .text
- .balign 4
-
-
-###############################################################################
-#
-# Change CMODE
-# - void frv_change_cmode(int cmode)
-#
-###############################################################################
- .globl frv_change_cmode
- .type frv_change_cmode,@function
-
-.macro LEDS v
-#ifdef DEBUG_CMODE
- setlos #~\v,gr10
- sti gr10,@(gr11,#0)
- membar
-#endif
-.endm
-
-frv_change_cmode:
- movsg lr,gr9
-#ifdef DEBUG_CMODE
- li __addr_LEDS,gr11
-#endif
- dcef @(gr0,gr0),#1
-
- # Shift argument left by 24 bits to fit in SWCMODE register later.
- slli gr8,#24,gr8
-
- # (1) Set '0' in the PSR.ET bit, and prohibit interrupts.
- movsg psr,gr14
- andi gr14,#~PSR_ET,gr3
- movgs gr3,psr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (2) Set '0' to all bits of the MASK register of the interrupt
- # controller, and mask interrupts.
- li __addr_MASK,gr12
- ldi @(gr12,#0),gr13
- li 0xffff0000,gr4
- sti gr4,@(gr12,#0)
-#endif
-
- # (3) Stop the transfer function of DMAC. Stop all the bus masters
- # to access SDRAM and the internal resources.
-
- # (already done by caller)
-
- # (4) Preload a series of following instructions to the instruction
- # cache.
- li #__cmode_icache_lock_start,gr3
- li #__cmode_icache_lock_end,gr4
-
-1: icpl gr3,gr0,#1
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- # Set up addresses in regs for later steps.
- setlos SDRAMC_DRCN_SR,gr3
- li __addr_SDRAMC,gr4
- li __addr_CLKC,gr5
- ldi @(gr5,#0),gr6
- li #0x80000000,gr7
- or gr6,gr7,gr6
-
- bra __cmode_icache_lock_start
-
- .balign L1_CACHE_BYTES
-__cmode_icache_lock_start:
-
- # (5) Flush the content of all caches by the DCEF instruction.
- dcef @(gr0,gr0),#1
-
- # (6) Execute loading the dummy for SDRAM.
- ldi @(gr9,#0),gr0
-
- # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
- # self-refresh mode. Execute the dummy load to all memory
- # devices set to cacheable on the external bus side in parallel
- # with this.
- sti gr3,@(gr4,#SDRAMC_DRCN)
-
- # (8) Execute memory barrier instruction (MEMBAR).
- membar
-
- # (9) Read the DSTS register repeatedly until '1' stands in the
- # DSTS.SSI field.
-1: ldi @(gr4,#SDRAMC_DSTS),gr3
- andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
- beq icc0,#0,1b
-
- # (10) Execute memory barrier instruction (MEMBAR).
- membar
-
-#if 1
- # (11) Set the value of CMODE that you want to change to
- # SWCMODE.SWCM[3:0].
- sti gr8,@(gr5,#CLKC_SWCMODE)
-
- # (12) Set '1' to the CLKC.SWEN bit. In that case, do not change
- # fields other than SWEN of the CLKC register.
- sti gr6,@(gr5,#0)
-#endif
- # (13) Execute the instruction just after the memory barrier
- # instruction that executes the self-loop 256 times. (Meanwhile,
- # the CMODE switch is done.)
- membar
- setlos #256,gr7
-2: subicc gr7,#1,gr7,icc0
- bne icc0,#2,2b
-
- LEDS 0x36
-
- # (14) Release the self-refresh of SDRAM.
- sti gr0,@(gr4,#SDRAMC_DRCN)
-
- # Wait for it...
-3: ldi @(gr4,#SDRAMC_DSTS),gr3
- andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
- bne icc0,#2,3b
-
-#if 0
- li 0x0100000,gr10
-4: subicc gr10,#1,gr10,icc0
-
- bne icc0,#0,4b
-#endif
-
-__cmode_icache_lock_end:
-
- li #__cmode_icache_lock_start,gr3
- li #__cmode_icache_lock_end,gr4
-
-4: icul gr3
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,4b
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (15) Release the interrupt mask setting of the MASK register of
- # the interrupt controller if necessary.
- sti gr13,@(gr12,#0)
-#endif
- # (16) Set 1' in the PSR.ET bit, and permit interrupt.
- movgs gr14,psr
-
- bralr
-
- .size frv_change_cmode, .-frv_change_cmode
diff --git a/arch/frv/kernel/debug-stub.c b/arch/frv/kernel/debug-stub.c
deleted file mode 100644
index a0228f717ef2..000000000000
--- a/arch/frv/kernel/debug-stub.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* debug-stub.c: debug-mode stub
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/serial_reg.h>
-#include <linux/start_kernel.h>
-
-#include <asm/serial-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/irc-regs.h>
-#include <asm/gdb-stub.h>
-#include "gdb-io.h"
-
-/* CPU board CON5 */
-#define __UART0(X) (*(volatile uint8_t *)(UART0_BASE + (UART_##X)))
-
-#define LSR_WAIT_FOR0(STATE) \
-do { \
-} while (!(__UART0(LSR) & UART_LSR_##STATE))
-
-#define FLOWCTL_QUERY0(LINE) ({ __UART0(MSR) & UART_MSR_##LINE; })
-#define FLOWCTL_CLEAR0(LINE) do { __UART0(MCR) &= ~UART_MCR_##LINE; } while (0)
-#define FLOWCTL_SET0(LINE) do { __UART0(MCR) |= UART_MCR_##LINE; } while (0)
-
-#define FLOWCTL_WAIT_FOR0(LINE) \
-do { \
- gdbstub_do_rx(); \
-} while(!FLOWCTL_QUERY(LINE))
-
-struct frv_debug_status __debug_status;
-
-static void __init debug_stub_init(void);
-
-/*****************************************************************************/
-/*
- * debug mode handler stub
- * - we come here with the CPU in debug mode and with exceptions disabled
- * - handle debugging services for userspace
- */
-asmlinkage void debug_stub(void)
-{
- unsigned long hsr0;
- int type = 0;
-
- static u8 inited = 0;
- if (!inited) {
- debug_stub_init();
- type = -1;
- inited = 1;
- }
-
- hsr0 = __get_HSR(0);
- if (hsr0 & HSR0_ETMD)
- __set_HSR(0, hsr0 & ~HSR0_ETMD);
-
- /* disable single stepping */
- __debug_status.dcr &= ~DCR_SE;
-
- /* kernel mode can propose an exception be handled in debug mode by jumping to a special
- * location */
- if (__debug_frame->pc == (unsigned long) __break_hijack_kernel_event_breaks_here) {
- /* replace the debug frame with the kernel frame and discard
- * the top kernel context */
- *__debug_frame = *__frame;
- __frame = __debug_frame->next_frame;
- __debug_status.brr = (__debug_frame->tbr & TBR_TT) << 12;
- __debug_status.brr |= BRR_EB;
- }
-
- if (__debug_frame->pc == (unsigned long) __debug_bug_trap + 4) {
- __debug_frame->pc = __debug_frame->lr;
- type = __debug_frame->gr8;
- }
-
-#ifdef CONFIG_GDBSTUB
- gdbstub(type);
-#endif
-
- if (hsr0 & HSR0_ETMD)
- __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
-
-} /* end debug_stub() */
-
-/*****************************************************************************/
-/*
- * debug stub initialisation
- */
-static void __init debug_stub_init(void)
-{
- __set_IRR(6, 0xff000000); /* map ERRs to NMI */
- __set_IITMR(1, 0x20000000); /* ERR0/1, UART0/1 IRQ detect levels */
-
- asm volatile(" movgs gr0,ibar0 \n"
- " movgs gr0,ibar1 \n"
- " movgs gr0,ibar2 \n"
- " movgs gr0,ibar3 \n"
- " movgs gr0,dbar0 \n"
- " movgs gr0,dbmr00 \n"
- " movgs gr0,dbmr01 \n"
- " movgs gr0,dbdr00 \n"
- " movgs gr0,dbdr01 \n"
- " movgs gr0,dbar1 \n"
- " movgs gr0,dbmr10 \n"
- " movgs gr0,dbmr11 \n"
- " movgs gr0,dbdr10 \n"
- " movgs gr0,dbdr11 \n"
- );
-
- /* deal with debugging stub initialisation and initial pause */
- if (__debug_frame->pc == (unsigned long) __debug_stub_init_break)
- __debug_frame->pc = (unsigned long) start_kernel;
-
- /* enable the debug events we want to trap */
- __debug_status.dcr = DCR_EBE;
-
-#ifdef CONFIG_GDBSTUB
- gdbstub_init();
-#endif
-
- __clr_MASK_all();
- __clr_MASK(15);
- __clr_RC(15);
-
-} /* end debug_stub_init() */
-
-/*****************************************************************************/
-/*
- * kernel "exit" trap for gdb stub
- */
-void debug_stub_exit(int status)
-{
-
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(status);
-#endif
-
-} /* end debug_stub_exit() */
-
-/*****************************************************************************/
-/*
- * send string to serial port
- */
-void debug_to_serial(const char *p, int n)
-{
- char ch;
-
- for (; n > 0; n--) {
- ch = *p++;
- FLOWCTL_SET0(DTR);
- LSR_WAIT_FOR0(THRE);
- // FLOWCTL_WAIT_FOR(CTS);
-
- if (ch == 0x0a) {
- __UART0(TX) = 0x0d;
- mb();
- LSR_WAIT_FOR0(THRE);
- // FLOWCTL_WAIT_FOR(CTS);
- }
- __UART0(TX) = ch;
- mb();
-
- FLOWCTL_CLEAR0(DTR);
- }
-
-} /* end debug_to_serial() */
-
-/*****************************************************************************/
-/*
- * send string to serial port
- */
-void debug_to_serial2(const char *fmt, ...)
-{
- va_list va;
- char buf[64];
- int n;
-
- va_start(va, fmt);
- n = vsprintf(buf, fmt, va);
- va_end(va);
-
- debug_to_serial(buf, n);
-
-} /* end debug_to_serial2() */
-
-/*****************************************************************************/
-/*
- * set up the ttyS0 serial port baud rate timers
- */
-void __init console_set_baud(unsigned baud)
-{
- unsigned value, high, low;
- u8 lcr;
-
- /* work out the divisor to give us the nearest higher baud rate */
- value = __serial_clock_speed_HZ / 16 / baud;
-
- /* determine the baud rate range */
- high = __serial_clock_speed_HZ / 16 / value;
- low = __serial_clock_speed_HZ / 16 / (value + 1);
-
- /* pick the nearest bound */
- if (low + (high - low) / 2 > baud)
- value++;
-
- lcr = __UART0(LCR);
- __UART0(LCR) |= UART_LCR_DLAB;
- mb();
- __UART0(DLL) = value & 0xff;
- __UART0(DLM) = (value >> 8) & 0xff;
- mb();
- __UART0(LCR) = lcr;
- mb();
-
-} /* end console_set_baud() */
-
-/*****************************************************************************/
-/*
- *
- */
-int __init console_get_baud(void)
-{
- unsigned value;
- u8 lcr;
-
- lcr = __UART0(LCR);
- __UART0(LCR) |= UART_LCR_DLAB;
- mb();
- value = __UART0(DLM) << 8;
- value |= __UART0(DLL);
- __UART0(LCR) = lcr;
- mb();
-
- return value;
-} /* end console_get_baud() */
-
-/*****************************************************************************/
-/*
- * display BUG() info
- */
-#ifndef CONFIG_NO_KERNEL_MSG
-void __debug_bug_printk(const char *file, unsigned line)
-{
- printk("kernel BUG at %s:%d!\n", file, line);
-
-} /* end __debug_bug_printk() */
-#endif
diff --git a/arch/frv/kernel/dma.c b/arch/frv/kernel/dma.c
deleted file mode 100644
index 370dc9fa0b11..000000000000
--- a/arch/frv/kernel/dma.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/* dma.c: DMA controller management on FR401 and the like
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <asm/dma.h>
-#include <asm/gpio-regs.h>
-#include <asm/irc-regs.h>
-#include <asm/cpu-irqs.h>
-
-struct frv_dma_channel {
- uint8_t flags;
-#define FRV_DMA_FLAGS_RESERVED 0x01
-#define FRV_DMA_FLAGS_INUSE 0x02
-#define FRV_DMA_FLAGS_PAUSED 0x04
- uint8_t cap; /* capabilities available */
- int irq; /* completion IRQ */
- uint32_t dreqbit;
- uint32_t dackbit;
- uint32_t donebit;
- const unsigned long ioaddr; /* DMA controller regs addr */
- const char *devname;
- dma_irq_handler_t handler;
- void *data;
-};
-
-
-#define __get_DMAC(IO,X) ({ *(volatile unsigned long *)((IO) + DMAC_##X##x); })
-
-#define __set_DMAC(IO,X,V) \
-do { \
- *(volatile unsigned long *)((IO) + DMAC_##X##x) = (V); \
- mb(); \
-} while(0)
-
-#define ___set_DMAC(IO,X,V) \
-do { \
- *(volatile unsigned long *)((IO) + DMAC_##X##x) = (V); \
-} while(0)
-
-
-static struct frv_dma_channel frv_dma_channels[FRV_DMA_NCHANS] = {
- [0] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK | FRV_DMA_CAP_DONE,
- .irq = IRQ_CPU_DMA0,
- .dreqbit = SIR_DREQ0_INPUT,
- .dackbit = SOR_DACK0_OUTPUT,
- .donebit = SOR_DONE0_OUTPUT,
- .ioaddr = 0xfe000900,
- },
- [1] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK | FRV_DMA_CAP_DONE,
- .irq = IRQ_CPU_DMA1,
- .dreqbit = SIR_DREQ1_INPUT,
- .dackbit = SOR_DACK1_OUTPUT,
- .donebit = SOR_DONE1_OUTPUT,
- .ioaddr = 0xfe000980,
- },
- [2] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK,
- .irq = IRQ_CPU_DMA2,
- .dreqbit = SIR_DREQ2_INPUT,
- .dackbit = SOR_DACK2_OUTPUT,
- .ioaddr = 0xfe000a00,
- },
- [3] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK,
- .irq = IRQ_CPU_DMA3,
- .dreqbit = SIR_DREQ3_INPUT,
- .dackbit = SOR_DACK3_OUTPUT,
- .ioaddr = 0xfe000a80,
- },
- [4] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA4,
- .dreqbit = SIR_DREQ4_INPUT,
- .ioaddr = 0xfe001000,
- },
- [5] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA5,
- .dreqbit = SIR_DREQ5_INPUT,
- .ioaddr = 0xfe001080,
- },
- [6] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA6,
- .dreqbit = SIR_DREQ6_INPUT,
- .ioaddr = 0xfe001100,
- },
- [7] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA7,
- .dreqbit = SIR_DREQ7_INPUT,
- .ioaddr = 0xfe001180,
- },
-};
-
-static DEFINE_RWLOCK(frv_dma_channels_lock);
-
-unsigned int frv_dma_inprogress;
-
-#define frv_clear_dma_inprogress(channel) \
- (void)__atomic32_fetch_and(~(1 << (channel)), &frv_dma_inprogress);
-
-#define frv_set_dma_inprogress(channel) \
- (void)__atomic32_fetch_or(1 << (channel), &frv_dma_inprogress);
-
-/*****************************************************************************/
-/*
- * DMA irq handler - determine channel involved, grab status and call real handler
- */
-static irqreturn_t dma_irq_handler(int irq, void *_channel)
-{
- struct frv_dma_channel *channel = _channel;
-
- frv_clear_dma_inprogress(channel - frv_dma_channels);
- return channel->handler(channel - frv_dma_channels,
- __get_DMAC(channel->ioaddr, CSTR),
- channel->data);
-
-} /* end dma_irq_handler() */
-
-/*****************************************************************************/
-/*
- * Determine which DMA controllers are present on this CPU
- */
-void __init frv_dma_init(void)
-{
- unsigned long psr = __get_PSR();
- int num_dma, i;
-
- /* First, determine how many DMA channels are available */
- switch (PSR_IMPLE(psr)) {
- case PSR_IMPLE_FR405:
- case PSR_IMPLE_FR451:
- case PSR_IMPLE_FR501:
- case PSR_IMPLE_FR551:
- num_dma = FRV_DMA_8CHANS;
- break;
-
- case PSR_IMPLE_FR401:
- default:
- num_dma = FRV_DMA_4CHANS;
- break;
- }
-
- /* Now mark all of the non-existent channels as reserved */
- for(i = num_dma; i < FRV_DMA_NCHANS; i++)
- frv_dma_channels[i].flags = FRV_DMA_FLAGS_RESERVED;
-
-} /* end frv_dma_init() */
-
-/*****************************************************************************/
-/*
- * allocate a DMA controller channel and the IRQ associated with it
- */
-int frv_dma_open(const char *devname,
- unsigned long dmamask,
- int dmacap,
- dma_irq_handler_t handler,
- unsigned long irq_flags,
- void *data)
-{
- struct frv_dma_channel *channel;
- int dma, ret;
- uint32_t val;
-
- write_lock(&frv_dma_channels_lock);
-
- ret = -ENOSPC;
-
- for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
- channel = &frv_dma_channels[dma];
-
- if (!test_bit(dma, &dmamask))
- continue;
-
- if ((channel->cap & dmacap) != dmacap)
- continue;
-
- if (!frv_dma_channels[dma].flags)
- goto found;
- }
-
- goto out;
-
- found:
- ret = request_irq(channel->irq, dma_irq_handler, irq_flags, devname, channel);
- if (ret < 0)
- goto out;
-
- /* okay, we've allocated all the resources */
- channel = &frv_dma_channels[dma];
-
- channel->flags |= FRV_DMA_FLAGS_INUSE;
- channel->devname = devname;
- channel->handler = handler;
- channel->data = data;
-
- /* Now make sure we are set up for DMA and not GPIO */
- /* SIR bit must be set for DMA to work */
- __set_SIR(channel->dreqbit | __get_SIR());
- /* SOR bits depend on what the caller requests */
- val = __get_SOR();
- if(dmacap & FRV_DMA_CAP_DACK)
- val |= channel->dackbit;
- else
- val &= ~channel->dackbit;
- if(dmacap & FRV_DMA_CAP_DONE)
- val |= channel->donebit;
- else
- val &= ~channel->donebit;
- __set_SOR(val);
-
- ret = dma;
- out:
- write_unlock(&frv_dma_channels_lock);
- return ret;
-} /* end frv_dma_open() */
-
-EXPORT_SYMBOL(frv_dma_open);
-
-/*****************************************************************************/
-/*
- * close a DMA channel and its associated interrupt
- */
-void frv_dma_close(int dma)
-{
- struct frv_dma_channel *channel = &frv_dma_channels[dma];
- unsigned long flags;
-
- write_lock_irqsave(&frv_dma_channels_lock, flags);
-
- free_irq(channel->irq, channel);
- frv_dma_stop(dma);
-
- channel->flags &= ~FRV_DMA_FLAGS_INUSE;
-
- write_unlock_irqrestore(&frv_dma_channels_lock, flags);
-} /* end frv_dma_close() */
-
-EXPORT_SYMBOL(frv_dma_close);
-
-/*****************************************************************************/
-/*
- * set static configuration on a DMA channel
- */
-void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- ___set_DMAC(ioaddr, CCFR, ccfr);
- ___set_DMAC(ioaddr, CCTR, cctr);
- ___set_DMAC(ioaddr, APR, apr);
- mb();
-
-} /* end frv_dma_config() */
-
-EXPORT_SYMBOL(frv_dma_config);
-
-/*****************************************************************************/
-/*
- * start a DMA channel
- */
-void frv_dma_start(int dma,
- unsigned long sba, unsigned long dba,
- unsigned long pix, unsigned long six, unsigned long bcl)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- ___set_DMAC(ioaddr, SBA, sba);
- ___set_DMAC(ioaddr, DBA, dba);
- ___set_DMAC(ioaddr, PIX, pix);
- ___set_DMAC(ioaddr, SIX, six);
- ___set_DMAC(ioaddr, BCL, bcl);
- ___set_DMAC(ioaddr, CSTR, 0);
- mb();
-
- __set_DMAC(ioaddr, CCTR, __get_DMAC(ioaddr, CCTR) | DMAC_CCTRx_ACT);
- frv_set_dma_inprogress(dma);
-
-} /* end frv_dma_start() */
-
-EXPORT_SYMBOL(frv_dma_start);
-
-/*****************************************************************************/
-/*
- * restart a DMA channel that's been stopped in circular addressing mode by comparison-end
- */
-void frv_dma_restart_circular(int dma, unsigned long six)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- ___set_DMAC(ioaddr, SIX, six);
- ___set_DMAC(ioaddr, CSTR, __get_DMAC(ioaddr, CSTR) & ~DMAC_CSTRx_CE);
- mb();
-
- __set_DMAC(ioaddr, CCTR, __get_DMAC(ioaddr, CCTR) | DMAC_CCTRx_ACT);
- frv_set_dma_inprogress(dma);
-
-} /* end frv_dma_restart_circular() */
-
-EXPORT_SYMBOL(frv_dma_restart_circular);
-
-/*****************************************************************************/
-/*
- * stop a DMA channel
- */
-void frv_dma_stop(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
- uint32_t cctr;
-
- ___set_DMAC(ioaddr, CSTR, 0);
- cctr = __get_DMAC(ioaddr, CCTR);
- cctr &= ~(DMAC_CCTRx_IE | DMAC_CCTRx_ACT);
- cctr |= DMAC_CCTRx_FC; /* fifo clear */
- __set_DMAC(ioaddr, CCTR, cctr);
- __set_DMAC(ioaddr, BCL, 0);
- frv_clear_dma_inprogress(dma);
-} /* end frv_dma_stop() */
-
-EXPORT_SYMBOL(frv_dma_stop);
-
-/*****************************************************************************/
-/*
- * test interrupt status of DMA channel
- */
-int is_frv_dma_interrupting(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- return __get_DMAC(ioaddr, CSTR) & (1 << 23);
-
-} /* end is_frv_dma_interrupting() */
-
-EXPORT_SYMBOL(is_frv_dma_interrupting);
-
-/*****************************************************************************/
-/*
- * dump data about a DMA channel
- */
-void frv_dma_dump(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
- unsigned long cstr, pix, six, bcl;
-
- cstr = __get_DMAC(ioaddr, CSTR);
- pix = __get_DMAC(ioaddr, PIX);
- six = __get_DMAC(ioaddr, SIX);
- bcl = __get_DMAC(ioaddr, BCL);
-
- printk("DMA[%d] cstr=%lx pix=%lx six=%lx bcl=%lx\n", dma, cstr, pix, six, bcl);
-
-} /* end frv_dma_dump() */
-
-EXPORT_SYMBOL(frv_dma_dump);
-
-/*****************************************************************************/
-/*
- * pause all DMA controllers
- * - called by clock mangling routines
- * - caller must be holding interrupts disabled
- */
-void frv_dma_pause_all(void)
-{
- struct frv_dma_channel *channel;
- unsigned long ioaddr;
- unsigned long cstr, cctr;
- int dma;
-
- write_lock(&frv_dma_channels_lock);
-
- for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
- channel = &frv_dma_channels[dma];
-
- if (!(channel->flags & FRV_DMA_FLAGS_INUSE))
- continue;
-
- ioaddr = channel->ioaddr;
- cctr = __get_DMAC(ioaddr, CCTR);
- if (cctr & DMAC_CCTRx_ACT) {
- cctr &= ~DMAC_CCTRx_ACT;
- __set_DMAC(ioaddr, CCTR, cctr);
-
- do {
- cstr = __get_DMAC(ioaddr, CSTR);
- } while (cstr & DMAC_CSTRx_BUSY);
-
- if (cstr & DMAC_CSTRx_FED)
- channel->flags |= FRV_DMA_FLAGS_PAUSED;
- frv_clear_dma_inprogress(dma);
- }
- }
-
-} /* end frv_dma_pause_all() */
-
-EXPORT_SYMBOL(frv_dma_pause_all);
-
-/*****************************************************************************/
-/*
- * resume paused DMA controllers
- * - called by clock mangling routines
- * - caller must be holding interrupts disabled
- */
-void frv_dma_resume_all(void)
-{
- struct frv_dma_channel *channel;
- unsigned long ioaddr;
- unsigned long cstr, cctr;
- int dma;
-
- for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
- channel = &frv_dma_channels[dma];
-
- if (!(channel->flags & FRV_DMA_FLAGS_PAUSED))
- continue;
-
- ioaddr = channel->ioaddr;
- cstr = __get_DMAC(ioaddr, CSTR);
- cstr &= ~(DMAC_CSTRx_FED | DMAC_CSTRx_INT);
- __set_DMAC(ioaddr, CSTR, cstr);
-
- cctr = __get_DMAC(ioaddr, CCTR);
- cctr |= DMAC_CCTRx_ACT;
- __set_DMAC(ioaddr, CCTR, cctr);
-
- channel->flags &= ~FRV_DMA_FLAGS_PAUSED;
- frv_set_dma_inprogress(dma);
- }
-
- write_unlock(&frv_dma_channels_lock);
-
-} /* end frv_dma_resume_all() */
-
-EXPORT_SYMBOL(frv_dma_resume_all);
-
-/*****************************************************************************/
-/*
- * dma status clear
- */
-void frv_dma_status_clear(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
- uint32_t cctr;
- ___set_DMAC(ioaddr, CSTR, 0);
-
- cctr = __get_DMAC(ioaddr, CCTR);
-} /* end frv_dma_status_clear() */
-
-EXPORT_SYMBOL(frv_dma_status_clear);
diff --git a/arch/frv/kernel/entry-table.S b/arch/frv/kernel/entry-table.S
deleted file mode 100644
index 06c5ae191e59..000000000000
--- a/arch/frv/kernel/entry-table.S
+++ /dev/null
@@ -1,329 +0,0 @@
-/* entry-table.S: main trap vector tables and exception jump table
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/spr-regs.h>
-
-###############################################################################
-#
-# Declare the main trap and vector tables
-#
-# There are six tables:
-#
-# (1) The trap table for debug mode
-# (2) The trap table for kernel mode
-# (3) The trap table for user mode
-#
-# The CPU jumps to an appropriate slot in the appropriate table to perform
-# exception processing. We have three different tables for the three
-# different CPU modes because there is no hardware differentiation between
-# stack pointers for these three modes, and so we have to invent one when
-# crossing mode boundaries.
-#
-# (4) The exception handler vector table
-#
-# The user and kernel trap tables use the same prologue for normal
-# exception processing. The prologue then jumps to the handler in this
-# table, as indexed by the exception ID from the TBR.
-#
-# (5) The fixup table for kernel-trap single-step
-# (6) The fixup table for user-trap single-step
-#
-# Due to the way single-stepping works on this CPU (single-step is not
-# disabled when crossing exception boundaries, only when in debug mode),
-# we have to catch the single-step event in break.S and jump to the fixup
-# routine pointed to by this table.
-#
-# The linker script places the user mode and kernel mode trap tables on to
-# the same 8Kb page, so that break.S can be more efficient when performing
-# single-step bypass management
-#
-###############################################################################
-
- # trap table for entry from debug mode
- .section .trap.break,"ax"
- .balign 256*16
- .globl __entry_breaktrap_table
-__entry_breaktrap_table:
-
- # trap table for entry from user mode
- .section .trap.user,"ax"
- .balign 256*16
- .globl __entry_usertrap_table
-__entry_usertrap_table:
-
- # trap table for entry from kernel mode
- .section .trap.kernel,"ax"
- .balign 256*16
- .globl __entry_kerneltrap_table
-__entry_kerneltrap_table:
-
- # exception handler jump table
- .section .trap.vector,"ax"
- .balign 256*4
- .globl __entry_vector_table
-__entry_vector_table:
-
- # trap fixup table for single-stepping in user mode
- .section .trap.fixup.user,"a"
- .balign 256*4
- .globl __break_usertrap_fixup_table
-__break_usertrap_fixup_table:
-
- # trap fixup table for single-stepping in user mode
- .section .trap.fixup.kernel,"a"
- .balign 256*4
- .globl __break_kerneltrap_fixup_table
-__break_kerneltrap_fixup_table:
-
- # handler declaration for a software or program interrupt
-.macro VECTOR_SOFTPROG tbr_tt, vec
- .section .trap.user
- .org \tbr_tt
- bra __entry_uspace_softprog_interrupt
- .section .trap.fixup.user
- .org \tbr_tt >> 2
- .long __break_step_uspace_softprog_interrupt
- .section .trap.kernel
- .org \tbr_tt
- bra __entry_kernel_softprog_interrupt
- .section .trap.fixup.kernel
- .org \tbr_tt >> 2
- .long __break_step_kernel_softprog_interrupt
- .section .trap.vector
- .org \tbr_tt >> 2
- .long \vec
-.endm
-
- # handler declaration for a maskable external interrupt
-.macro VECTOR_IRQ tbr_tt, vec
- .section .trap.user
- .org \tbr_tt
- bra __entry_uspace_external_interrupt
- .section .trap.fixup.user
- .org \tbr_tt >> 2
- .long __break_step_uspace_external_interrupt
- .section .trap.kernel
- .org \tbr_tt
- # deal with virtual interrupt disablement
- beq icc2,#0,__entry_kernel_external_interrupt_virtually_disabled
- bra __entry_kernel_external_interrupt
- .section .trap.fixup.kernel
- .org \tbr_tt >> 2
- .long __break_step_kernel_external_interrupt
- .section .trap.vector
- .org \tbr_tt >> 2
- .long \vec
-.endm
-
- # handler declaration for an NMI external interrupt
-.macro VECTOR_NMI tbr_tt, vec
- .section .trap.user
- .org \tbr_tt
- break
- break
- break
- break
- .section .trap.kernel
- .org \tbr_tt
- break
- break
- break
- break
- .section .trap.vector
- .org \tbr_tt >> 2
- .long \vec
-.endm
-
- # handler declaration for an MMU only software or program interrupt
-.macro VECTOR_SP_MMU tbr_tt, vec
-#ifdef CONFIG_MMU
- VECTOR_SOFTPROG \tbr_tt, \vec
-#else
- VECTOR_NMI \tbr_tt, 0
-#endif
-.endm
-
-
-###############################################################################
-#
-# specification of the vectors
-# - note: each macro inserts code into multiple sections
-#
-###############################################################################
- VECTOR_SP_MMU TBR_TT_INSTR_MMU_MISS, __entry_insn_mmu_miss
- VECTOR_SOFTPROG TBR_TT_INSTR_ACC_ERROR, __entry_insn_access_error
- VECTOR_SOFTPROG TBR_TT_INSTR_ACC_EXCEP, __entry_insn_access_exception
- VECTOR_SOFTPROG TBR_TT_PRIV_INSTR, __entry_privileged_instruction
- VECTOR_SOFTPROG TBR_TT_ILLEGAL_INSTR, __entry_illegal_instruction
- VECTOR_SOFTPROG TBR_TT_FP_EXCEPTION, __entry_media_exception
- VECTOR_SOFTPROG TBR_TT_MP_EXCEPTION, __entry_media_exception
- VECTOR_SOFTPROG TBR_TT_DATA_ACC_ERROR, __entry_data_access_error
- VECTOR_SP_MMU TBR_TT_DATA_MMU_MISS, __entry_data_mmu_miss
- VECTOR_SOFTPROG TBR_TT_DATA_ACC_EXCEP, __entry_data_access_exception
- VECTOR_SOFTPROG TBR_TT_DATA_STR_ERROR, __entry_data_store_error
- VECTOR_SOFTPROG TBR_TT_DIVISION_EXCEP, __entry_division_exception
-
-#ifdef CONFIG_MMU
- .section .trap.user
- .org TBR_TT_INSTR_TLB_MISS
- .globl __trap_user_insn_tlb_miss
-__trap_user_insn_tlb_miss:
- movsg ear0,gr28 /* faulting address */
- movsg scr0,gr31 /* get mapped PTD coverage start address */
- xor.p gr28,gr31,gr31 /* compare addresses */
- bra __entry_user_insn_tlb_miss
-
- .org TBR_TT_DATA_TLB_MISS
- .globl __trap_user_data_tlb_miss
-__trap_user_data_tlb_miss:
- movsg ear0,gr28 /* faulting address */
- movsg scr1,gr31 /* get mapped PTD coverage start address */
- xor.p gr28,gr31,gr31 /* compare addresses */
- bra __entry_user_data_tlb_miss
-
- .section .trap.kernel
- .org TBR_TT_INSTR_TLB_MISS
- .globl __trap_kernel_insn_tlb_miss
-__trap_kernel_insn_tlb_miss:
- movsg ear0,gr29 /* faulting address */
- movsg scr0,gr31 /* get mapped PTD coverage start address */
- xor.p gr29,gr31,gr31 /* compare addresses */
- bra __entry_kernel_insn_tlb_miss
-
- .org TBR_TT_DATA_TLB_MISS
- .globl __trap_kernel_data_tlb_miss
-__trap_kernel_data_tlb_miss:
- movsg ear0,gr29 /* faulting address */
- movsg scr1,gr31 /* get mapped PTD coverage start address */
- xor.p gr29,gr31,gr31 /* compare addresses */
- bra __entry_kernel_data_tlb_miss
-
- .section .trap.fixup.user
- .org TBR_TT_INSTR_TLB_MISS >> 2
- .globl __trap_fixup_user_insn_tlb_miss
-__trap_fixup_user_insn_tlb_miss:
- .long __break_user_insn_tlb_miss
- .org TBR_TT_DATA_TLB_MISS >> 2
- .globl __trap_fixup_user_data_tlb_miss
-__trap_fixup_user_data_tlb_miss:
- .long __break_user_data_tlb_miss
-
- .section .trap.fixup.kernel
- .org TBR_TT_INSTR_TLB_MISS >> 2
- .globl __trap_fixup_kernel_insn_tlb_miss
-__trap_fixup_kernel_insn_tlb_miss:
- .long __break_kernel_insn_tlb_miss
- .org TBR_TT_DATA_TLB_MISS >> 2
- .globl __trap_fixup_kernel_data_tlb_miss
-__trap_fixup_kernel_data_tlb_miss:
- .long __break_kernel_data_tlb_miss
-
- .section .trap.vector
- .org TBR_TT_INSTR_TLB_MISS >> 2
- .long __entry_insn_mmu_fault
- .org TBR_TT_DATA_TLB_MISS >> 2
- .long __entry_data_mmu_fault
-#endif
-
- VECTOR_SP_MMU TBR_TT_DATA_DAT_EXCEP, __entry_data_dat_fault
- VECTOR_NMI TBR_TT_DECREMENT_TIMER, __entry_do_NMI
- VECTOR_SOFTPROG TBR_TT_COMPOUND_EXCEP, __entry_compound_exception
- VECTOR_IRQ TBR_TT_INTERRUPT_1, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_2, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_3, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_4, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_5, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_6, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_7, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_8, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_9, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_10, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_11, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_12, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_13, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_14, __entry_do_IRQ
- VECTOR_NMI TBR_TT_INTERRUPT_15, __entry_do_NMI
-
- # miscellaneous user mode entry points
- .section .trap.user
- .org TBR_TT_TRAP0
- .rept 127
- bra __entry_uspace_softprog_interrupt
- .long 0,0,0
- .endr
- .org TBR_TT_BREAK
- bra __entry_break
- .long 0,0,0
-
- .section .trap.fixup.user
- .org TBR_TT_TRAP0 >> 2
- .rept 127
- .long __break_step_uspace_softprog_interrupt
- .endr
- .org TBR_TT_BREAK >> 2
- .long 0
-
- # miscellaneous kernel mode entry points
- .section .trap.kernel
- .org TBR_TT_TRAP0
- bra __entry_kernel_softprog_interrupt
- .org TBR_TT_TRAP1
- bra __entry_kernel_softprog_interrupt
-
- # trap #2 in kernel - reenable interrupts
- .org TBR_TT_TRAP2
- bra __entry_kernel_external_interrupt_virtual_reenable
-
- # miscellaneous kernel traps
- .org TBR_TT_TRAP3
- .rept 124
- bra __entry_kernel_softprog_interrupt
- .long 0,0,0
- .endr
- .org TBR_TT_BREAK
- bra __entry_break
- .long 0,0,0
-
- .section .trap.fixup.kernel
- .org TBR_TT_TRAP0 >> 2
- .long __break_step_kernel_softprog_interrupt
- .long __break_step_kernel_softprog_interrupt
- .long __break_step_kernel_external_interrupt_virtual_reenable
- .rept 124
- .long __break_step_kernel_softprog_interrupt
- .endr
- .org TBR_TT_BREAK >> 2
- .long 0
-
- # miscellaneous debug mode entry points
- .section .trap.break
- .org TBR_TT_BREAK
- movsg bpcsr,gr30
- jmpl @(gr30,gr0)
-
- # miscellaneous vectors
- .section .trap.vector
- .org TBR_TT_TRAP0 >> 2
- .long system_call
- .rept 119
- .long __entry_unsupported_trap
- .endr
-
- # userspace atomic op emulation, traps 120-126
- .rept 7
- .long __entry_atomic_op
- .endr
-
- .org TBR_TT_BREAK >> 2
- .long __entry_debug_exception
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
deleted file mode 100644
index dfcd263c0517..000000000000
--- a/arch/frv/kernel/entry.S
+++ /dev/null
@@ -1,1519 +0,0 @@
-/* entry.S: FR-V entry
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- *
- * Entry to the kernel is "interesting":
- * (1) There are no stack pointers, not even for the kernel
- * (2) General Registers should not be clobbered
- * (3) There are no kernel-only data registers
- * (4) Since all addressing modes are wrt to a General Register, no global
- * variables can be reached
- *
- * We deal with this by declaring that we shall kill GR28 on entering the
- * kernel from userspace
- *
- * However, since break interrupts can interrupt the CPU even when PSR.ET==0,
- * they can't rely on GR28 to be anything useful, and so need to clobber a
- * separate register (GR31). Break interrupts are managed in break.S
- *
- * GR29 _is_ saved, and holds the current task pointer globally
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <asm/spr-regs.h>
-
-#define nr_syscalls ((syscall_table_size)/4)
-
- .section .text..entry
- .balign 4
-
-.macro LEDS val
-# sethi.p %hi(0xe1200004),gr30
-# setlo %lo(0xe1200004),gr30
-# setlos #~\val,gr31
-# st gr31,@(gr30,gr0)
-# sethi.p %hi(0xffc00100),gr30
-# setlo %lo(0xffc00100),gr30
-# sth gr0,@(gr30,gr0)
-# membar
-.endm
-
-.macro LEDS32
-# not gr31,gr31
-# sethi.p %hi(0xe1200004),gr30
-# setlo %lo(0xe1200004),gr30
-# st.p gr31,@(gr30,gr0)
-# srli gr31,#16,gr31
-# sethi.p %hi(0xffc00100),gr30
-# setlo %lo(0xffc00100),gr30
-# sth gr31,@(gr30,gr0)
-# membar
-.endm
-
-###############################################################################
-#
-# entry point for External interrupts received whilst executing userspace code
-#
-###############################################################################
- .globl __entry_uspace_external_interrupt
- .type __entry_uspace_external_interrupt,@function
-__entry_uspace_external_interrupt:
- LEDS 0x6200
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
-
- # handle h/w single-step through exceptions
- sti gr0,@(gr28,#REG__STATUS)
-
- .globl __entry_uspace_external_interrupt_reentry
-__entry_uspace_external_interrupt_reentry:
- LEDS 0x6201
-
- setlos #REG__END,gr30
- dcpl gr28,gr30,#0
-
- # finish building the exception frame
- sti sp, @(gr28,#REG_SP)
- stdi gr2, @(gr28,#REG_GR(2))
- stdi gr4, @(gr28,#REG_GR(4))
- stdi gr6, @(gr28,#REG_GR(6))
- stdi gr8, @(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr0, @(gr28,#REG_GR(28))
- sti gr29,@(gr28,#REG_GR(29))
- stdi.p gr30,@(gr28,#REG_GR(30))
-
- # set up the kernel stack pointer
- ori gr28,0,sp
-
- movsg tbr ,gr20
- movsg psr ,gr22
- movsg pcsr,gr21
- movsg isr ,gr23
- movsg ccr ,gr24
- movsg cccr,gr25
- movsg lr ,gr26
- movsg lcr ,gr27
-
- setlos.p #-1,gr4
- andi gr22,#PSR_PS,gr5 /* try to rebuild original PSR value */
- andi.p gr22,#~(PSR_PS|PSR_S),gr6
- slli gr5,#1,gr5
- or gr6,gr5,gr5
- andi gr5,#~PSR_ET,gr5
-
- sti gr20,@(gr28,#REG_TBR)
- sti gr21,@(gr28,#REG_PC)
- sti gr5 ,@(gr28,#REG_PSR)
- sti gr23,@(gr28,#REG_ISR)
- stdi gr24,@(gr28,#REG_CCR)
- stdi gr26,@(gr28,#REG_LR)
- sti gr4 ,@(gr28,#REG_SYSCALLNO)
-
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr28,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi.p gr4,@(gr28,#REG_GNER0)
-
- # interrupts start off fully disabled in the interrupt handler
- subcc gr0,gr0,gr0,icc2 /* set Z and clear C */
-
- # set up kernel global registers
- sethi.p %hi(__kernel_current_task),gr5
- setlo %lo(__kernel_current_task),gr5
- sethi.p %hi(_gp),gr16
- setlo %lo(_gp),gr16
- ldi @(gr5,#0),gr29
- ldi.p @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
-
- # make sure we (the kernel) get div-zero and misalignment exceptions
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # switch to the kernel trap table
- sethi.p %hi(__entry_kerneltrap_table),gr6
- setlo %lo(__entry_kerneltrap_table),gr6
- movgs gr6,tbr
-
- # set the return address
- sethi.p %hi(__entry_return_from_user_interrupt),gr4
- setlo %lo(__entry_return_from_user_interrupt),gr4
- movgs gr4,lr
-
- # raise the minimum interrupt priority to 15 (NMI only) and enable exceptions
- movsg psr,gr4
-
- ori gr4,#PSR_PIL_14,gr4
- movgs gr4,psr
- ori gr4,#PSR_PIL_14|PSR_ET,gr4
- movgs gr4,psr
-
- LEDS 0x6202
- bra do_IRQ
-
- .size __entry_uspace_external_interrupt,.-__entry_uspace_external_interrupt
-
-###############################################################################
-#
-# entry point for External interrupts received whilst executing kernel code
-# - on arriving here, the following registers should already be set up:
-# GR15 - current thread_info struct pointer
-# GR16 - kernel GP-REL pointer
-# GR29 - current task struct pointer
-# TBR - kernel trap vector table
-# ISR - kernel's preferred integer controls
-#
-###############################################################################
- .globl __entry_kernel_external_interrupt
- .type __entry_kernel_external_interrupt,@function
-__entry_kernel_external_interrupt:
- LEDS 0x6210
-// sub sp,gr15,gr31
-// LEDS32
-
- # set up the stack pointer
- or.p sp,gr0,gr30
- subi sp,#REG__END,sp
- sti gr30,@(sp,#REG_SP)
-
- # handle h/w single-step through exceptions
- sti gr0,@(sp,#REG__STATUS)
-
- .globl __entry_kernel_external_interrupt_reentry
-__entry_kernel_external_interrupt_reentry:
- LEDS 0x6211
-
- # set up the exception frame
- setlos #REG__END,gr30
- dcpl sp,gr30,#0
-
- sti.p gr28,@(sp,#REG_GR(28))
- ori sp,0,gr28
-
- # finish building the exception frame
- stdi gr2,@(gr28,#REG_GR(2))
- stdi gr4,@(gr28,#REG_GR(4))
- stdi gr6,@(gr28,#REG_GR(6))
- stdi gr8,@(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr29,@(gr28,#REG_GR(29))
- stdi.p gr30,@(gr28,#REG_GR(30))
-
- # note virtual interrupts will be fully enabled upon return
- subicc gr0,#1,gr0,icc2 /* clear Z, set C */
-
- movsg tbr ,gr20
- movsg psr ,gr22
- movsg pcsr,gr21
- movsg isr ,gr23
- movsg ccr ,gr24
- movsg cccr,gr25
- movsg lr ,gr26
- movsg lcr ,gr27
-
- setlos.p #-1,gr4
- andi gr22,#PSR_PS,gr5 /* try to rebuild original PSR value */
- andi.p gr22,#~(PSR_PS|PSR_S),gr6
- slli gr5,#1,gr5
- or gr6,gr5,gr5
- andi.p gr5,#~PSR_ET,gr5
-
- # set CCCR.CC3 to Undefined to abort atomic-modify completion inside the kernel
- # - for an explanation of how it works, see: Documentation/frv/atomic-ops.txt
- andi gr25,#~0xc0,gr25
-
- sti gr20,@(gr28,#REG_TBR)
- sti gr21,@(gr28,#REG_PC)
- sti gr5 ,@(gr28,#REG_PSR)
- sti gr23,@(gr28,#REG_ISR)
- stdi gr24,@(gr28,#REG_CCR)
- stdi gr26,@(gr28,#REG_LR)
- sti gr4 ,@(gr28,#REG_SYSCALLNO)
-
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr28,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi.p gr4,@(gr28,#REG_GNER0)
-
- # interrupts start off fully disabled in the interrupt handler
- subcc gr0,gr0,gr0,icc2 /* set Z and clear C */
-
- # set the return address
- sethi.p %hi(__entry_return_from_kernel_interrupt),gr4
- setlo %lo(__entry_return_from_kernel_interrupt),gr4
- movgs gr4,lr
-
- # clear power-saving mode flags
- movsg hsr0,gr4
- andi gr4,#~HSR0_PDM,gr4
- movgs gr4,hsr0
-
- # raise the minimum interrupt priority to 15 (NMI only) and enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_PIL_14,gr4
- movgs gr4,psr
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- LEDS 0x6212
- bra do_IRQ
-
- .size __entry_kernel_external_interrupt,.-__entry_kernel_external_interrupt
-
-###############################################################################
-#
-# deal with interrupts that were actually virtually disabled
-# - we need to really disable them, flag the fact and return immediately
-# - if you change this, you must alter break.S also
-#
-###############################################################################
- .balign L1_CACHE_BYTES
- .globl __entry_kernel_external_interrupt_virtually_disabled
- .type __entry_kernel_external_interrupt_virtually_disabled,@function
-__entry_kernel_external_interrupt_virtually_disabled:
- movsg psr,gr30
- andi gr30,#~PSR_PIL,gr30
- ori gr30,#PSR_PIL_14,gr30 ; debugging interrupts only
- movgs gr30,psr
- subcc gr0,gr0,gr0,icc2 ; leave Z set, clear C
- rett #0
-
- .size __entry_kernel_external_interrupt_virtually_disabled,.-__entry_kernel_external_interrupt_virtually_disabled
-
-###############################################################################
-#
-# deal with re-enablement of interrupts that were pending when virtually re-enabled
-# - set ICC2.C, re-enable the real interrupts and return
-# - we can clear ICC2.Z because we shouldn't be here if it's not 0 [due to TIHI]
-# - if you change this, you must alter break.S also
-#
-###############################################################################
- .balign L1_CACHE_BYTES
- .globl __entry_kernel_external_interrupt_virtual_reenable
- .type __entry_kernel_external_interrupt_virtual_reenable,@function
-__entry_kernel_external_interrupt_virtual_reenable:
- movsg psr,gr30
- andi gr30,#~PSR_PIL,gr30 ; re-enable interrupts
- movgs gr30,psr
- subicc gr0,#1,gr0,icc2 ; clear Z, set C
- rett #0
-
- .size __entry_kernel_external_interrupt_virtual_reenable,.-__entry_kernel_external_interrupt_virtual_reenable
-
-###############################################################################
-#
-# entry point for Software and Progam interrupts generated whilst executing userspace code
-#
-###############################################################################
- .globl __entry_uspace_softprog_interrupt
- .type __entry_uspace_softprog_interrupt,@function
- .globl __entry_uspace_handle_mmu_fault
-__entry_uspace_softprog_interrupt:
- LEDS 0x6000
-#ifdef CONFIG_MMU
- movsg ear0,gr28
-__entry_uspace_handle_mmu_fault:
- movgs gr28,scr2
-#endif
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
-
- # handle h/w single-step through exceptions
- sti gr0,@(gr28,#REG__STATUS)
-
- .globl __entry_uspace_softprog_interrupt_reentry
-__entry_uspace_softprog_interrupt_reentry:
- LEDS 0x6001
-
- setlos #REG__END,gr30
- dcpl gr28,gr30,#0
-
- # set up the kernel stack pointer
- sti.p sp,@(gr28,#REG_SP)
- ori gr28,0,sp
- sti gr0,@(gr28,#REG_GR(28))
-
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
-
- movsg tbr,gr20
- movsg pcsr,gr21
- movsg psr,gr22
-
- sethi.p %hi(__entry_return_from_user_exception),gr23
- setlo %lo(__entry_return_from_user_exception),gr23
-
- bra __entry_common
-
- .size __entry_uspace_softprog_interrupt,.-__entry_uspace_softprog_interrupt
-
- # single-stepping was disabled on entry to a TLB handler that then faulted
-#ifdef CONFIG_MMU
- .globl __entry_uspace_handle_mmu_fault_sstep
-__entry_uspace_handle_mmu_fault_sstep:
- movgs gr28,scr2
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
-
- # flag single-step re-enablement
- sti gr0,@(gr28,#REG__STATUS)
- bra __entry_uspace_softprog_interrupt_reentry
-#endif
-
-
-###############################################################################
-#
-# entry point for Software and Progam interrupts generated whilst executing kernel code
-#
-###############################################################################
- .globl __entry_kernel_softprog_interrupt
- .type __entry_kernel_softprog_interrupt,@function
-__entry_kernel_softprog_interrupt:
- LEDS 0x6004
-
-#ifdef CONFIG_MMU
- movsg ear0,gr30
- movgs gr30,scr2
-#endif
-
- .globl __entry_kernel_handle_mmu_fault
-__entry_kernel_handle_mmu_fault:
- # set up the stack pointer
- subi sp,#REG__END,sp
- sti sp,@(sp,#REG_SP)
- sti sp,@(sp,#REG_SP-4)
- andi sp,#~7,sp
-
- # handle h/w single-step through exceptions
- sti gr0,@(sp,#REG__STATUS)
-
- .globl __entry_kernel_softprog_interrupt_reentry
-__entry_kernel_softprog_interrupt_reentry:
- LEDS 0x6005
-
- setlos #REG__END,gr30
- dcpl sp,gr30,#0
-
- # set up the exception frame
- sti.p gr28,@(sp,#REG_GR(28))
- ori sp,0,gr28
-
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
-
- ldi @(sp,#REG_SP),gr22 /* reconstruct the old SP */
- addi gr22,#REG__END,gr22
- sti gr22,@(sp,#REG_SP)
-
- # set CCCR.CC3 to Undefined to abort atomic-modify completion inside the kernel
- # - for an explanation of how it works, see: Documentation/frv/atomic-ops.txt
- movsg cccr,gr20
- andi gr20,#~0xc0,gr20
- movgs gr20,cccr
-
- movsg tbr,gr20
- movsg pcsr,gr21
- movsg psr,gr22
-
- sethi.p %hi(__entry_return_from_kernel_exception),gr23
- setlo %lo(__entry_return_from_kernel_exception),gr23
- bra __entry_common
-
- .size __entry_kernel_softprog_interrupt,.-__entry_kernel_softprog_interrupt
-
- # single-stepping was disabled on entry to a TLB handler that then faulted
-#ifdef CONFIG_MMU
- .globl __entry_kernel_handle_mmu_fault_sstep
-__entry_kernel_handle_mmu_fault_sstep:
- # set up the stack pointer
- subi sp,#REG__END,sp
- sti sp,@(sp,#REG_SP)
- sti sp,@(sp,#REG_SP-4)
- andi sp,#~7,sp
-
- # flag single-step re-enablement
- sethi #REG__STATUS_STEP,gr30
- sti gr30,@(sp,#REG__STATUS)
- bra __entry_kernel_softprog_interrupt_reentry
-#endif
-
-
-###############################################################################
-#
-# the rest of the kernel entry point code
-# - on arriving here, the following registers should be set up:
-# GR1 - kernel stack pointer
-# GR7 - syscall number (trap 0 only)
-# GR8-13 - syscall args (trap 0 only)
-# GR20 - saved TBR
-# GR21 - saved PC
-# GR22 - saved PSR
-# GR23 - return handler address
-# GR28 - exception frame on stack
-# SCR2 - saved EAR0 where applicable (clobbered by ICI & ICEF insns on FR451)
-# PSR - PSR.S 1, PSR.ET 0
-#
-###############################################################################
- .globl __entry_common
- .type __entry_common,@function
-__entry_common:
- LEDS 0x6008
-
- # finish building the exception frame
- stdi gr2,@(gr28,#REG_GR(2))
- stdi gr4,@(gr28,#REG_GR(4))
- stdi gr6,@(gr28,#REG_GR(6))
- stdi gr8,@(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr29,@(gr28,#REG_GR(29))
- stdi gr30,@(gr28,#REG_GR(30))
-
- movsg lcr ,gr27
- movsg lr ,gr26
- movgs gr23,lr
- movsg cccr,gr25
- movsg ccr ,gr24
- movsg isr ,gr23
-
- setlos.p #-1,gr4
- andi gr22,#PSR_PS,gr5 /* try to rebuild original PSR value */
- andi.p gr22,#~(PSR_PS|PSR_S),gr6
- slli gr5,#1,gr5
- or gr6,gr5,gr5
- andi gr5,#~PSR_ET,gr5
-
- sti gr20,@(gr28,#REG_TBR)
- sti gr21,@(gr28,#REG_PC)
- sti gr5 ,@(gr28,#REG_PSR)
- sti gr23,@(gr28,#REG_ISR)
- stdi gr24,@(gr28,#REG_CCR)
- stdi gr26,@(gr28,#REG_LR)
- sti gr4 ,@(gr28,#REG_SYSCALLNO)
-
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr28,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi.p gr4,@(gr28,#REG_GNER0)
-
- # set up virtual interrupt disablement
- subicc gr0,#1,gr0,icc2 /* clear Z flag, set C flag */
-
- # set up kernel global registers
- sethi.p %hi(__kernel_current_task),gr5
- setlo %lo(__kernel_current_task),gr5
- sethi.p %hi(_gp),gr16
- setlo %lo(_gp),gr16
- ldi @(gr5,#0),gr29
- ldi @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
-
- # switch to the kernel trap table
- sethi.p %hi(__entry_kerneltrap_table),gr6
- setlo %lo(__entry_kerneltrap_table),gr6
- movgs gr6,tbr
-
- # make sure we (the kernel) get div-zero and misalignment exceptions
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # clear power-saving mode flags
- movsg hsr0,gr4
- andi gr4,#~HSR0_PDM,gr4
- movgs gr4,hsr0
-
- # multiplex again using old TBR as a guide
- setlos.p #TBR_TT,gr3
- sethi %hi(__entry_vector_table),gr6
- and.p gr20,gr3,gr5
- setlo %lo(__entry_vector_table),gr6
- srli gr5,#2,gr5
- ld @(gr5,gr6),gr5
-
- LEDS 0x6009
- jmpl @(gr5,gr0)
-
-
- .size __entry_common,.-__entry_common
-
-###############################################################################
-#
-# handle instruction MMU fault
-#
-###############################################################################
-#ifdef CONFIG_MMU
- .globl __entry_insn_mmu_fault
-__entry_insn_mmu_fault:
- LEDS 0x6010
- setlos #0,gr8
- movsg esr0,gr9
- movsg scr2,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- sethi.p %hi(do_page_fault),gr5
- setlo %lo(do_page_fault),gr5
- jmpl @(gr5,gr0) ; call do_page_fault(0,esr0,ear0)
-#endif
-
-
-###############################################################################
-#
-# handle instruction access error
-#
-###############################################################################
- .globl __entry_insn_access_error
-__entry_insn_access_error:
- LEDS 0x6011
- sethi.p %hi(insn_access_error),gr5
- setlo %lo(insn_access_error),gr5
- movsg esfr1,gr8
- movsg epcr0,gr9
- movsg esr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call insn_access_error(esfr1,epcr0,esr0)
-
-###############################################################################
-#
-# handle various instructions of dubious legality
-#
-###############################################################################
- .globl __entry_unsupported_trap
- .globl __entry_illegal_instruction
- .globl __entry_privileged_instruction
- .globl __entry_debug_exception
-__entry_unsupported_trap:
- subi gr21,#4,gr21
- sti gr21,@(gr28,#REG_PC)
-__entry_illegal_instruction:
-__entry_privileged_instruction:
-__entry_debug_exception:
- LEDS 0x6012
- sethi.p %hi(illegal_instruction),gr5
- setlo %lo(illegal_instruction),gr5
- movsg esfr1,gr8
- movsg epcr0,gr9
- movsg esr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call ill_insn(esfr1,epcr0,esr0)
-
-###############################################################################
-#
-# handle atomic operation emulation for userspace
-#
-###############################################################################
- .globl __entry_atomic_op
-__entry_atomic_op:
- LEDS 0x6012
- sethi.p %hi(atomic_operation),gr5
- setlo %lo(atomic_operation),gr5
- movsg esfr1,gr8
- movsg epcr0,gr9
- movsg esr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call atomic_operation(esfr1,epcr0,esr0)
-
-###############################################################################
-#
-# handle media exception
-#
-###############################################################################
- .globl __entry_media_exception
-__entry_media_exception:
- LEDS 0x6013
- sethi.p %hi(media_exception),gr5
- setlo %lo(media_exception),gr5
- movsg msr0,gr8
- movsg msr1,gr9
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call media_excep(msr0,msr1)
-
-###############################################################################
-#
-# handle data MMU fault
-# handle data DAT fault (write-protect exception)
-#
-###############################################################################
-#ifdef CONFIG_MMU
- .globl __entry_data_mmu_fault
-__entry_data_mmu_fault:
- .globl __entry_data_dat_fault
-__entry_data_dat_fault:
- LEDS 0x6014
- setlos #1,gr8
- movsg esr0,gr9
- movsg scr2,gr10 ; saved EAR0
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- sethi.p %hi(do_page_fault),gr5
- setlo %lo(do_page_fault),gr5
- jmpl @(gr5,gr0) ; call do_page_fault(1,esr0,ear0)
-#endif
-
-###############################################################################
-#
-# handle data and instruction access exceptions
-#
-###############################################################################
- .globl __entry_insn_access_exception
- .globl __entry_data_access_exception
-__entry_insn_access_exception:
-__entry_data_access_exception:
- LEDS 0x6016
- sethi.p %hi(memory_access_exception),gr5
- setlo %lo(memory_access_exception),gr5
- movsg esr0,gr8
- movsg scr2,gr9 ; saved EAR0
- movsg epcr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call memory_access_error(esr0,ear0,epcr0)
-
-###############################################################################
-#
-# handle data access error
-#
-###############################################################################
- .globl __entry_data_access_error
-__entry_data_access_error:
- LEDS 0x6016
- sethi.p %hi(data_access_error),gr5
- setlo %lo(data_access_error),gr5
- movsg esfr1,gr8
- movsg esr15,gr9
- movsg ear15,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call data_access_error(esfr1,esr15,ear15)
-
-###############################################################################
-#
-# handle data store error
-#
-###############################################################################
- .globl __entry_data_store_error
-__entry_data_store_error:
- LEDS 0x6017
- sethi.p %hi(data_store_error),gr5
- setlo %lo(data_store_error),gr5
- movsg esfr1,gr8
- movsg esr14,gr9
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call data_store_error(esfr1,esr14)
-
-###############################################################################
-#
-# handle division exception
-#
-###############################################################################
- .globl __entry_division_exception
-__entry_division_exception:
- LEDS 0x6018
- sethi.p %hi(division_exception),gr5
- setlo %lo(division_exception),gr5
- movsg esfr1,gr8
- movsg esr0,gr9
- movsg isr,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call div_excep(esfr1,esr0,isr)
-
-###############################################################################
-#
-# handle compound exception
-#
-###############################################################################
- .globl __entry_compound_exception
-__entry_compound_exception:
- LEDS 0x6019
- sethi.p %hi(compound_exception),gr5
- setlo %lo(compound_exception),gr5
- movsg esfr1,gr8
- movsg esr0,gr9
- movsg esr14,gr10
- movsg esr15,gr11
- movsg msr0,gr12
- movsg msr1,gr13
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call comp_excep(esfr1,esr0,esr14,esr15,msr0,msr1)
-
-###############################################################################
-#
-# handle interrupts and NMIs
-#
-###############################################################################
- .globl __entry_do_IRQ
-__entry_do_IRQ:
- LEDS 0x6020
-
- # we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- bra do_IRQ
-
- .globl __entry_do_NMI
-__entry_do_NMI:
- LEDS 0x6021
-
- # we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- bra do_NMI
-
-###############################################################################
-#
-# the return path for a newly forked child process
-# - __switch_to() saved the old current pointer in GR8 for us
-#
-###############################################################################
- .globl ret_from_fork
-ret_from_fork:
- LEDS 0x6100
- call schedule_tail
-
- # fork & co. return 0 to child
- setlos.p #0,gr8
- bra __syscall_exit
-
- .globl ret_from_kernel_thread
-ret_from_kernel_thread:
- lddi.p @(gr28,#REG_GR(8)),gr20
- call schedule_tail
- calll.p @(gr21,gr0)
- or gr20,gr20,gr8
- bra __syscall_exit
-
-###################################################################################################
-#
-# Return to user mode is not as complex as all this looks,
-# but we want the default path for a system call return to
-# go as quickly as possible which is why some of this is
-# less clear than it otherwise should be.
-#
-###################################################################################################
- .balign L1_CACHE_BYTES
- .globl system_call
-system_call:
- LEDS 0x6101
- movsg psr,gr4 ; enable exceptions
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- sti gr7,@(gr28,#REG_SYSCALLNO)
- sti.p gr8,@(gr28,#REG_ORIG_GR8)
-
- subicc gr7,#nr_syscalls,gr0,icc0
- bnc icc0,#0,__syscall_badsys
-
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_SYSCALL_TRACE,gr0,icc0
- bne icc0,#0,__syscall_trace_entry
-
-__syscall_call:
- slli.p gr7,#2,gr7
- sethi %hi(sys_call_table),gr5
- setlo %lo(sys_call_table),gr5
- ld @(gr5,gr7),gr4
- calll @(gr4,gr0)
-
-
-###############################################################################
-#
-# return to interrupted process
-#
-###############################################################################
-__syscall_exit:
- LEDS 0x6300
-
- # keep current PSR in GR23
- movsg psr,gr23
-
- ldi @(gr28,#REG_PSR),gr22
-
- sti.p gr8,@(gr28,#REG_GR(8)) ; save return value
-
- # rebuild saved psr - execve will change it for init/main.c
- srli gr22,#1,gr5
- andi.p gr22,#~PSR_PS,gr22
- andi gr5,#PSR_PS,gr5
- or gr5,gr22,gr22
- ori.p gr22,#PSR_S,gr22
-
- # make sure we don't miss an interrupt setting need_resched or sigpending between
- # sampling and the RETT
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_ALLWORK_MASK,gr0,icc0
- bne icc0,#0,__syscall_exit_work
-
- # restore all registers and return
-__entry_return_direct:
- LEDS 0x6301
-
- andi gr22,#~PSR_ET,gr22
- movgs gr22,psr
-
- ldi @(gr28,#REG_ISR),gr23
- lddi @(gr28,#REG_CCR),gr24
- lddi @(gr28,#REG_LR) ,gr26
- ldi @(gr28,#REG_PC) ,gr21
- ldi @(gr28,#REG_TBR),gr20
-
- movgs gr20,tbr
- movgs gr21,pcsr
- movgs gr23,isr
- movgs gr24,ccr
- movgs gr25,cccr
- movgs gr26,lr
- movgs gr27,lcr
-
- lddi @(gr28,#REG_GNER0),gr4
- movgs gr4,gner0
- movgs gr5,gner1
-
- lddi @(gr28,#REG_IACC0),gr4
- movgs gr4,iacc0h
- movgs gr5,iacc0l
-
- lddi @(gr28,#REG_GR(4)) ,gr4
- lddi @(gr28,#REG_GR(6)) ,gr6
- lddi @(gr28,#REG_GR(8)) ,gr8
- lddi @(gr28,#REG_GR(10)),gr10
- lddi @(gr28,#REG_GR(12)),gr12
- lddi @(gr28,#REG_GR(14)),gr14
- lddi @(gr28,#REG_GR(16)),gr16
- lddi @(gr28,#REG_GR(18)),gr18
- lddi @(gr28,#REG_GR(20)),gr20
- lddi @(gr28,#REG_GR(22)),gr22
- lddi @(gr28,#REG_GR(24)),gr24
- lddi @(gr28,#REG_GR(26)),gr26
- ldi @(gr28,#REG_GR(29)),gr29
- lddi @(gr28,#REG_GR(30)),gr30
-
- # check to see if a debugging return is required
- LEDS 0x67f0
- movsg ccr,gr2
- ldi @(gr28,#REG__STATUS),gr3
- andicc gr3,#REG__STATUS_STEP,gr0,icc0
- bne icc0,#0,__entry_return_singlestep
- movgs gr2,ccr
-
- ldi @(gr28,#REG_SP) ,sp
- lddi @(gr28,#REG_GR(2)) ,gr2
- ldi @(gr28,#REG_GR(28)),gr28
-
- LEDS 0x67fe
-// movsg pcsr,gr31
-// LEDS32
-
-#if 0
- # store the current frame in the workram on the FR451
- movgs gr28,scr2
- sethi.p %hi(0xfe800000),gr28
- setlo %lo(0xfe800000),gr28
-
- stdi gr2,@(gr28,#REG_GR(2))
- stdi gr4,@(gr28,#REG_GR(4))
- stdi gr6,@(gr28,#REG_GR(6))
- stdi gr8,@(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr29,@(gr28,#REG_GR(29))
- stdi gr30,@(gr28,#REG_GR(30))
-
- movsg tbr ,gr30
- sti gr30,@(gr28,#REG_TBR)
- movsg pcsr,gr30
- sti gr30,@(gr28,#REG_PC)
- movsg psr ,gr30
- sti gr30,@(gr28,#REG_PSR)
- movsg isr ,gr30
- sti gr30,@(gr28,#REG_ISR)
- movsg ccr ,gr30
- movsg cccr,gr31
- stdi gr30,@(gr28,#REG_CCR)
- movsg lr ,gr30
- movsg lcr ,gr31
- stdi gr30,@(gr28,#REG_LR)
- sti gr0 ,@(gr28,#REG_SYSCALLNO)
- movsg scr2,gr28
-#endif
-
- rett #0
-
- # return via break.S
-__entry_return_singlestep:
- movgs gr2,ccr
- lddi @(gr28,#REG_GR(2)) ,gr2
- ldi @(gr28,#REG_SP) ,sp
- ldi @(gr28,#REG_GR(28)),gr28
- LEDS 0x67ff
- break
- .globl __entry_return_singlestep_breaks_here
-__entry_return_singlestep_breaks_here:
- nop
-
-
-###############################################################################
-#
-# return to a process interrupted in kernel space
-# - we need to consider preemption if that is enabled
-#
-###############################################################################
- .balign L1_CACHE_BYTES
-__entry_return_from_kernel_exception:
- LEDS 0x6302
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
- bra __entry_return_direct
-
- .balign L1_CACHE_BYTES
-__entry_return_from_kernel_interrupt:
- LEDS 0x6303
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
-#ifdef CONFIG_PREEMPT
- ldi @(gr15,#TI_PRE_COUNT),gr5
- subicc gr5,#0,gr0,icc0
- beq icc0,#0,__entry_return_direct
-
- subcc gr0,gr0,gr0,icc2 /* set Z and clear C */
- call preempt_schedule_irq
-#endif
- bra __entry_return_direct
-
-
-###############################################################################
-#
-# perform work that needs to be done immediately before resumption
-#
-###############################################################################
- .globl __entry_return_from_user_exception
- .balign L1_CACHE_BYTES
-__entry_return_from_user_exception:
- LEDS 0x6501
-
-__entry_resume_userspace:
- # make sure we don't miss an interrupt setting need_resched or sigpending between
- # sampling and the RETT
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
-__entry_return_from_user_interrupt:
- LEDS 0x6402
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_WORK_MASK,gr0,icc0
- beq icc0,#1,__entry_return_direct
-
-__entry_work_pending:
- LEDS 0x6404
- andicc gr4,#_TIF_NEED_RESCHED,gr0,icc0
- beq icc0,#1,__entry_work_notifysig
-
-__entry_work_resched:
- LEDS 0x6408
- movsg psr,gr23
- andi gr23,#~PSR_PIL,gr23
- movgs gr23,psr
- call schedule
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
- LEDS 0x6401
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_WORK_MASK,gr0,icc0
- beq icc0,#1,__entry_return_direct
- andicc gr4,#_TIF_NEED_RESCHED,gr0,icc0
- bne icc0,#1,__entry_work_resched
-
-__entry_work_notifysig:
- LEDS 0x6410
- ori.p gr4,#0,gr8
- call do_notify_resume
- bra __entry_resume_userspace
-
- # perform syscall entry tracing
-__syscall_trace_entry:
- LEDS 0x6320
- call syscall_trace_entry
-
- lddi.p @(gr28,#REG_GR(8)) ,gr8
- ori gr8,#0,gr7 ; syscall_trace_entry() returned new syscallno
- lddi @(gr28,#REG_GR(10)),gr10
- lddi.p @(gr28,#REG_GR(12)),gr12
-
- subicc gr7,#nr_syscalls,gr0,icc0
- bnc icc0,#0,__syscall_badsys
- bra __syscall_call
-
- # perform syscall exit tracing
-__syscall_exit_work:
- LEDS 0x6340
- andicc gr22,#PSR_PS,gr0,icc1 ; don't handle on return to kernel mode
- andicc.p gr4,#_TIF_SYSCALL_TRACE,gr0,icc0
- bne icc1,#0,__entry_return_direct
- beq icc0,#1,__entry_work_pending
-
- movsg psr,gr23
- andi gr23,#~PSR_PIL,gr23 ; could let syscall_trace_exit() call schedule()
- movgs gr23,psr
-
- call syscall_trace_exit
- bra __entry_resume_userspace
-
-__syscall_badsys:
- LEDS 0x6380
- setlos #-ENOSYS,gr8
- sti gr8,@(gr28,#REG_GR(8)) ; save return value
- bra __entry_resume_userspace
-
-
-###############################################################################
-#
-# syscall vector table
-#
-###############################################################################
- .section .rodata
-ALIGN
- .globl sys_call_table
-sys_call_table:
- .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_ni_syscall // sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_ni_syscall // sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys( */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old old uname syscall */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_ni_syscall // sys_sgetmask
- .long sys_ni_syscall // sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_ni_syscall // sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_ni_syscall // sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_ni_syscall /* old_select slot */
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_ni_syscall // old_readdir
- .long sys_ni_syscall /* 90 */ /* old_mmap slot */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* ioperm for i386 */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* obsolete olduname( syscall */
- .long sys_ni_syscall /* iopl for i386 */ /* 110 */
- .long sys_vhangup
- .long sys_ni_syscall /* obsolete idle( syscall */
- .long sys_ni_syscall /* vm86old for i386 */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* old "cacheflush" */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* for vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* Old nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap2
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall /* Reserved for Security */
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall //sys_set_thread_area
- .long sys_ni_syscall //sys_get_thread_area
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_mbind
- .long sys_get_mempolicy
- .long sys_set_mempolicy
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall /* reserved for kexec */
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate
- .long sys_timerfd_settime /* 325 */
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1
- .long sys_dup3 /* 330 */
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev
- .long sys_rt_tgsigqueueinfo /* 335 */
- .long sys_perf_event_open
- .long sys_setns
-
-syscall_table_size = (. - sys_call_table)
diff --git a/arch/frv/kernel/frv_ksyms.c b/arch/frv/kernel/frv_ksyms.c
deleted file mode 100644
index 6ea430d58149..000000000000
--- a/arch/frv/kernel/frv_ksyms.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/linkage.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-
-#include <asm/setup.h>
-#include <asm/pgalloc.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/checksum.h>
-#include <asm/hardirq.h>
-#include <asm/cacheflush.h>
-
-extern long __memcpy_user(void *dst, const void *src, size_t count);
-extern long __memset_user(void *dst, const void *src, size_t count);
-
-/* platform dependent support */
-
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-
-EXPORT_SYMBOL(ip_fast_csum);
-
-#if 0
-EXPORT_SYMBOL(local_irq_count);
-EXPORT_SYMBOL(local_bh_count);
-#endif
-
-EXPORT_SYMBOL(__res_bus_clock_speed_HZ);
-EXPORT_SYMBOL(__page_offset);
-EXPORT_SYMBOL(__memcpy_user);
-EXPORT_SYMBOL(__memset_user);
-EXPORT_SYMBOL(frv_dcache_writeback);
-EXPORT_SYMBOL(frv_cache_invalidate);
-EXPORT_SYMBOL(frv_icache_invalidate);
-EXPORT_SYMBOL(frv_cache_wback_inv);
-
-#ifndef CONFIG_MMU
-EXPORT_SYMBOL(memory_start);
-EXPORT_SYMBOL(memory_end);
-#endif
-
-EXPORT_SYMBOL(__debug_bug_trap);
-
-/* The following are special because they're not called
- explicitly (the C compiler generates them). Fortunately,
- their interface isn't gonna change any time soon now, so
- it's OK to leave it out of version control. */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-
-EXPORT_SYMBOL(__outsl_ns);
-EXPORT_SYMBOL(__insl_ns);
-
-#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-EXPORT_SYMBOL(__xchg_32);
-EXPORT_SYMBOL(__cmpxchg_32);
-#endif
-EXPORT_SYMBOL(atomic64_add_return);
-EXPORT_SYMBOL(atomic64_sub_return);
-EXPORT_SYMBOL(__xchg_64);
-EXPORT_SYMBOL(__cmpxchg_64);
-
-EXPORT_SYMBOL(__debug_bug_printk);
-EXPORT_SYMBOL(__delay_loops_MHz);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __gcc_bcmp(void);
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __cmpdi2(void);
-extern void __divdi3(void);
-extern void __lshrdi3(void);
-extern void __moddi3(void);
-extern void __muldi3(void);
-extern void __mulll(void);
-extern void __umulll(void);
-extern void __negdi2(void);
-extern void __ucmpdi2(void);
-extern void __udivdi3(void);
-extern void __udivmoddi4(void);
-extern void __umoddi3(void);
-
- /* gcc lib functions */
-//EXPORT_SYMBOL(__gcc_bcmp);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-//EXPORT_SYMBOL(__cmpdi2);
-//EXPORT_SYMBOL(__divdi3);
-EXPORT_SYMBOL(__lshrdi3);
-//EXPORT_SYMBOL(__moddi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__mulll);
-EXPORT_SYMBOL(__umulll);
-EXPORT_SYMBOL(__negdi2);
-EXPORT_SYMBOL(__ucmpdi2);
-//EXPORT_SYMBOL(__udivdi3);
-//EXPORT_SYMBOL(__udivmoddi4);
-//EXPORT_SYMBOL(__umoddi3);
diff --git a/arch/frv/kernel/futex.c b/arch/frv/kernel/futex.c
deleted file mode 100644
index 37f7b2bf7f73..000000000000
--- a/arch/frv/kernel/futex.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* futex.c: futex operations
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <asm/futex.h>
-#include <asm/errno.h>
-
-/*
- * the various futex operations; MMU fault checking is ignored under no-MMU
- * conditions
- */
-static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_add(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " add %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_or(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " or %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_and(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " and %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_xor(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " xor %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-/*****************************************************************************/
-/*
- * do the futex operations
- */
-int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
-{
- int oldval = 0, ret;
-
- pagefault_disable();
-
- switch (op) {
- case FUTEX_OP_SET:
- ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_ADD:
- ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_OR:
- ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_ANDN:
- ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_XOR:
- ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
- break;
- default:
- ret = -ENOSYS;
- break;
- }
-
- pagefault_enable();
-
- if (!ret)
- *oval = oldval;
-
- return ret;
-
-} /* end arch_futex_atomic_op_inuser() */
diff --git a/arch/frv/kernel/gdb-io.c b/arch/frv/kernel/gdb-io.c
deleted file mode 100644
index 0707d35079ba..000000000000
--- a/arch/frv/kernel/gdb-io.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* gdb-io.c: FR403 GDB stub I/O
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/serial_reg.h>
-
-#include <asm/pgtable.h>
-#include <asm/irc-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/gdb-stub.h>
-#include "gdb-io.h"
-
-#ifdef CONFIG_GDBSTUB_UART0
-#define __UART(X) (*(volatile uint8_t *)(UART0_BASE + (UART_##X)))
-#define __UART_IRR_NMI 0xff0f0000
-#else /* CONFIG_GDBSTUB_UART1 */
-#define __UART(X) (*(volatile uint8_t *)(UART1_BASE + (UART_##X)))
-#define __UART_IRR_NMI 0xfff00000
-#endif
-
-#define LSR_WAIT_FOR(STATE) \
-do { \
- gdbstub_do_rx(); \
-} while (!(__UART(LSR) & UART_LSR_##STATE))
-
-#define FLOWCTL_QUERY(LINE) ({ __UART(MSR) & UART_MSR_##LINE; })
-#define FLOWCTL_CLEAR(LINE) do { __UART(MCR) &= ~UART_MCR_##LINE; mb(); } while (0)
-#define FLOWCTL_SET(LINE) do { __UART(MCR) |= UART_MCR_##LINE; mb(); } while (0)
-
-#define FLOWCTL_WAIT_FOR(LINE) \
-do { \
- gdbstub_do_rx(); \
-} while(!FLOWCTL_QUERY(LINE))
-
-/*****************************************************************************/
-/*
- * initialise the GDB stub
- * - called with PSR.ET==0, so can't incur external interrupts
- */
-void gdbstub_io_init(void)
-{
- /* set up the serial port */
- __UART(LCR) = UART_LCR_WLEN8; /* 1N8 */
- __UART(FCR) =
- UART_FCR_ENABLE_FIFO |
- UART_FCR_CLEAR_RCVR |
- UART_FCR_CLEAR_XMIT |
- UART_FCR_TRIGGER_1;
-
- FLOWCTL_CLEAR(DTR);
- FLOWCTL_SET(RTS);
-
-// gdbstub_set_baud(115200);
-
- /* we want to get serial receive interrupts */
- __UART(IER) = UART_IER_RDI | UART_IER_RLSI;
- mb();
-
- __set_IRR(6, __UART_IRR_NMI); /* map ERRs and UARTx to NMI */
-
-} /* end gdbstub_io_init() */
-
-/*****************************************************************************/
-/*
- * set up the GDB stub serial port baud rate timers
- */
-void gdbstub_set_baud(unsigned baud)
-{
- unsigned value, high, low;
- u8 lcr;
-
- /* work out the divisor to give us the nearest higher baud rate */
- value = __serial_clock_speed_HZ / 16 / baud;
-
- /* determine the baud rate range */
- high = __serial_clock_speed_HZ / 16 / value;
- low = __serial_clock_speed_HZ / 16 / (value + 1);
-
- /* pick the nearest bound */
- if (low + (high - low) / 2 > baud)
- value++;
-
- lcr = __UART(LCR);
- __UART(LCR) |= UART_LCR_DLAB;
- mb();
- __UART(DLL) = value & 0xff;
- __UART(DLM) = (value >> 8) & 0xff;
- mb();
- __UART(LCR) = lcr;
- mb();
-
-} /* end gdbstub_set_baud() */
-
-/*****************************************************************************/
-/*
- * receive characters into the receive FIFO
- */
-void gdbstub_do_rx(void)
-{
- unsigned ix, nix;
-
- ix = gdbstub_rx_inp;
-
- while (__UART(LSR) & UART_LSR_DR) {
- nix = (ix + 2) & 0xfff;
- if (nix == gdbstub_rx_outp)
- break;
-
- gdbstub_rx_buffer[ix++] = __UART(LSR);
- gdbstub_rx_buffer[ix++] = __UART(RX);
- ix = nix;
- }
-
- gdbstub_rx_inp = ix;
-
- __clr_RC(15);
- __clr_IRL();
-
-} /* end gdbstub_do_rx() */
-
-/*****************************************************************************/
-/*
- * wait for a character to come from the debugger
- */
-int gdbstub_rx_char(unsigned char *_ch, int nonblock)
-{
- unsigned ix;
- u8 ch, st;
-
- *_ch = 0xff;
-
- if (gdbstub_rx_unget) {
- *_ch = gdbstub_rx_unget;
- gdbstub_rx_unget = 0;
- return 0;
- }
-
- try_again:
- gdbstub_do_rx();
-
- /* pull chars out of the buffer */
- ix = gdbstub_rx_outp;
- if (ix == gdbstub_rx_inp) {
- if (nonblock)
- return -EAGAIN;
- //watchdog_alert_counter = 0;
- goto try_again;
- }
-
- st = gdbstub_rx_buffer[ix++];
- ch = gdbstub_rx_buffer[ix++];
- gdbstub_rx_outp = ix & 0x00000fff;
-
- if (st & UART_LSR_BI) {
- gdbstub_proto("### GDB Rx Break Detected ###\n");
- return -EINTR;
- }
- else if (st & (UART_LSR_FE|UART_LSR_OE|UART_LSR_PE)) {
- gdbstub_io("### GDB Rx Error (st=%02x) ###\n",st);
- return -EIO;
- }
- else {
- gdbstub_io("### GDB Rx %02x (st=%02x) ###\n",ch,st);
- *_ch = ch & 0x7f;
- return 0;
- }
-
-} /* end gdbstub_rx_char() */
-
-/*****************************************************************************/
-/*
- * send a character to the debugger
- */
-void gdbstub_tx_char(unsigned char ch)
-{
- FLOWCTL_SET(DTR);
- LSR_WAIT_FOR(THRE);
-// FLOWCTL_WAIT_FOR(CTS);
-
- if (ch == 0x0a) {
- __UART(TX) = 0x0d;
- mb();
- LSR_WAIT_FOR(THRE);
-// FLOWCTL_WAIT_FOR(CTS);
- }
- __UART(TX) = ch;
- mb();
-
- FLOWCTL_CLEAR(DTR);
-} /* end gdbstub_tx_char() */
-
-/*****************************************************************************/
-/*
- * send a character to the debugger
- */
-void gdbstub_tx_flush(void)
-{
- LSR_WAIT_FOR(TEMT);
- LSR_WAIT_FOR(THRE);
- FLOWCTL_CLEAR(DTR);
-} /* end gdbstub_tx_flush() */
diff --git a/arch/frv/kernel/gdb-io.h b/arch/frv/kernel/gdb-io.h
deleted file mode 100644
index 138714bacc40..000000000000
--- a/arch/frv/kernel/gdb-io.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* gdb-io.h: FR403 GDB I/O port defs
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _GDB_IO_H
-#define _GDB_IO_H
-
-#include <asm/serial-regs.h>
-
-#undef UART_RX
-#undef UART_TX
-#undef UART_DLL
-#undef UART_DLM
-#undef UART_IER
-#undef UART_IIR
-#undef UART_FCR
-#undef UART_LCR
-#undef UART_MCR
-#undef UART_LSR
-#undef UART_MSR
-#undef UART_SCR
-
-#define UART_RX 0*8 /* In: Receive buffer (DLAB=0) */
-#define UART_TX 0*8 /* Out: Transmit buffer (DLAB=0) */
-#define UART_DLL 0*8 /* Out: Divisor Latch Low (DLAB=1) */
-#define UART_DLM 1*8 /* Out: Divisor Latch High (DLAB=1) */
-#define UART_IER 1*8 /* Out: Interrupt Enable Register */
-#define UART_IIR 2*8 /* In: Interrupt ID Register */
-#define UART_FCR 2*8 /* Out: FIFO Control Register */
-#define UART_LCR 3*8 /* Out: Line Control Register */
-#define UART_MCR 4*8 /* Out: Modem Control Register */
-#define UART_LSR 5*8 /* In: Line Status Register */
-#define UART_MSR 6*8 /* In: Modem Status Register */
-#define UART_SCR 7*8 /* I/O: Scratch Register */
-
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-#define UART_LCR_SBC 0x40 /* Set break control */
-#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
-#define UART_LCR_EPAR 0x10 /* Even parity select */
-#define UART_LCR_PARITY 0x08 /* Parity Enable */
-#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-
-#endif /* _GDB_IO_H */
diff --git a/arch/frv/kernel/gdb-stub.c b/arch/frv/kernel/gdb-stub.c
deleted file mode 100644
index bbe78b0bffec..000000000000
--- a/arch/frv/kernel/gdb-stub.c
+++ /dev/null
@@ -1,2149 +0,0 @@
-/* gdb-stub.c: FRV GDB stub
- *
- * Copyright (C) 2003,4 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from Linux/MIPS version, Copyright (C) 1995 Andreas Busse
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to set_debug_traps() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint(). Breakpoint()
- * simulates a breakpoint by executing a BREAK instruction.
- *
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- *
- * ==============
- * MORE EXAMPLES:
- * ==============
- *
- * For reference -- the following are the steps that one
- * company took (RidgeRun Inc) to get remote gdb debugging
- * going. In this scenario the host machine was a PC and the
- * target platform was a Galileo EVB64120A MIPS evaluation
- * board.
- *
- * Step 1:
- * First download gdb-5.0.tar.gz from the internet.
- * and then build/install the package.
- *
- * Example:
- * $ tar zxf gdb-5.0.tar.gz
- * $ cd gdb-5.0
- * $ ./configure --target=frv-elf-gdb
- * $ make
- * $ frv-elf-gdb
- *
- * Step 2:
- * Configure linux for remote debugging and build it.
- *
- * Example:
- * $ cd ~/linux
- * $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
- * $ make vmlinux
- *
- * Step 3:
- * Download the kernel to the remote target and start
- * the kernel running. It will promptly halt and wait
- * for the host gdb session to connect. It does this
- * since the "Kernel Hacking" option has defined
- * CONFIG_REMOTE_DEBUG which in turn enables your calls
- * to:
- * set_debug_traps();
- * breakpoint();
- *
- * Step 4:
- * Start the gdb session on the host.
- *
- * Example:
- * $ frv-elf-gdb vmlinux
- * (gdb) set remotebaud 115200
- * (gdb) target remote /dev/ttyS1
- * ...at this point you are connected to
- * the remote target and can use gdb
- * in the normal fasion. Setting
- * breakpoints, single stepping,
- * printing variables, etc.
- *
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/nmi.h>
-
-#include <asm/asm-offsets.h>
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-
-#define LEDS(x) do { /* *(u32*)0xe1200004 = ~(x); mb(); */ } while(0)
-
-#undef GDBSTUB_DEBUG_PROTOCOL
-
-extern void debug_to_serial(const char *p, int n);
-extern void gdbstub_console_write(struct console *co, const char *p, unsigned n);
-
-extern volatile uint32_t __break_error_detect[3]; /* ESFR1, ESR15, EAR15 */
-
-struct __debug_amr {
- unsigned long L, P;
-} __attribute__((aligned(8)));
-
-struct __debug_mmu {
- struct {
- unsigned long hsr0, pcsr, esr0, ear0, epcr0;
-#ifdef CONFIG_MMU
- unsigned long tplr, tppr, tpxr, cxnr;
-#endif
- } regs;
-
- struct __debug_amr iamr[16];
- struct __debug_amr damr[16];
-
-#ifdef CONFIG_MMU
- struct __debug_amr tlb[64*2];
-#endif
-};
-
-static struct __debug_mmu __debug_mmu;
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers
- * at least NUMREGBYTES*2 are needed for register packets
- */
-#define BUFMAX 2048
-
-#define BREAK_INSN 0x801000c0 /* use "break" as bkpt */
-
-static const char gdbstub_banner[] = "Linux/FR-V GDB Stub (c) RedHat 2003\n";
-
-volatile u8 gdbstub_rx_buffer[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-volatile u32 gdbstub_rx_inp = 0;
-volatile u32 gdbstub_rx_outp = 0;
-volatile u8 gdbstub_rx_overflow = 0;
-u8 gdbstub_rx_unget = 0;
-
-/* set with GDB whilst running to permit step through exceptions */
-extern volatile u32 __attribute__((section(".bss"))) gdbstub_trace_through_exceptions;
-
-static char input_buffer[BUFMAX];
-static char output_buffer[BUFMAX];
-
-static const char *regnames[] = {
- "PSR ", "ISR ", "CCR ", "CCCR",
- "LR ", "LCR ", "PC ", "_stt",
- "sys ", "GR8*", "GNE0", "GNE1",
- "IACH", "IACL",
- "TBR ", "SP ", "FP ", "GR3 ",
- "GR4 ", "GR5 ", "GR6 ", "GR7 ",
- "GR8 ", "GR9 ", "GR10", "GR11",
- "GR12", "GR13", "GR14", "GR15",
- "GR16", "GR17", "GR18", "GR19",
- "GR20", "GR21", "GR22", "GR23",
- "GR24", "GR25", "GR26", "GR27",
- "EFRM", "CURR", "GR30", "BFRM"
-};
-
-struct gdbstub_bkpt {
- unsigned long addr; /* address of breakpoint */
- unsigned len; /* size of breakpoint */
- uint32_t originsns[7]; /* original instructions */
-};
-
-static struct gdbstub_bkpt gdbstub_bkpts[256];
-
-/*
- * local prototypes
- */
-
-static void gdbstub_recv_packet(char *buffer);
-static int gdbstub_send_packet(char *buffer);
-static int gdbstub_compute_signal(unsigned long tbr);
-static int hex(unsigned char ch);
-static int hexToInt(char **ptr, unsigned long *intValue);
-static unsigned char *mem2hex(const void *mem, char *buf, int count, int may_fault);
-static char *hex2mem(const char *buf, void *_mem, int count);
-
-/*
- * Convert ch from a hex digit to an int
- */
-static int hex(unsigned char ch)
-{
- if (ch >= 'a' && ch <= 'f')
- return ch-'a'+10;
- if (ch >= '0' && ch <= '9')
- return ch-'0';
- if (ch >= 'A' && ch <= 'F')
- return ch-'A'+10;
- return -1;
-}
-
-void gdbstub_printk(const char *fmt, ...)
-{
- static char buf[1024];
- va_list args;
- int len;
-
- /* Emit the output into the temporary buffer */
- va_start(args, fmt);
- len = vsnprintf(buf, sizeof(buf), fmt, args);
- va_end(args);
- debug_to_serial(buf, len);
-}
-
-static inline char *gdbstub_strcpy(char *dst, const char *src)
-{
- int loop = 0;
- while ((dst[loop] = src[loop]))
- loop++;
- return dst;
-}
-
-static void gdbstub_purge_cache(void)
-{
- asm volatile(" dcef @(gr0,gr0),#1 \n"
- " icei @(gr0,gr0),#1 \n"
- " membar \n"
- " bar \n"
- );
-}
-
-/*****************************************************************************/
-/*
- * scan for the sequence $<data>#<checksum>
- */
-static void gdbstub_recv_packet(char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- unsigned char ch;
- int count, i, ret, error;
-
- for (;;) {
- /* wait around for the start character, ignore all other characters */
- do {
- gdbstub_rx_char(&ch, 0);
- } while (ch != '$');
-
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- error = 0;
-
- /* now, read until a # or end of buffer is found */
- while (count < BUFMAX) {
- ret = gdbstub_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
-
- if (ch == '#')
- break;
- checksum += ch;
- buffer[count] = ch;
- count++;
- }
-
- if (error == -EIO) {
- gdbstub_proto("### GDB Rx Error - Skipping packet ###\n");
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-');
- continue;
- }
-
- if (count >= BUFMAX || error)
- continue;
-
- buffer[count] = 0;
-
- /* read the checksum */
- ret = gdbstub_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
- xmitcsum = hex(ch) << 4;
-
- ret = gdbstub_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
- xmitcsum |= hex(ch);
-
- if (error) {
- if (error == -EIO)
- gdbstub_proto("### GDB Rx Error - Skipping packet\n");
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-');
- continue;
- }
-
- /* check the checksum */
- if (checksum != xmitcsum) {
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-'); /* failed checksum */
- continue;
- }
-
- gdbstub_proto("### GDB Rx '$%s#%02x' ###\n", buffer, checksum);
- gdbstub_proto("### GDB Tx ACK\n");
- gdbstub_tx_char('+'); /* successful transfer */
-
- /* if a sequence char is present, reply the sequence ID */
- if (buffer[2] == ':') {
- gdbstub_tx_char(buffer[0]);
- gdbstub_tx_char(buffer[1]);
-
- /* remove sequence chars from buffer */
- count = 0;
- while (buffer[count]) count++;
- for (i=3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
-
- break;
- }
-} /* end gdbstub_recv_packet() */
-
-/*****************************************************************************/
-/*
- * send the packet in buffer.
- * - return 0 if successfully ACK'd
- * - return 1 if abandoned due to new incoming packet
- */
-static int gdbstub_send_packet(char *buffer)
-{
- unsigned char checksum;
- int count;
- unsigned char ch;
-
- /* $<packet info>#<checksum> */
- gdbstub_proto("### GDB Tx '%s' ###\n", buffer);
-
- do {
- gdbstub_tx_char('$');
- checksum = 0;
- count = 0;
-
- while ((ch = buffer[count]) != 0) {
- gdbstub_tx_char(ch);
- checksum += ch;
- count += 1;
- }
-
- gdbstub_tx_char('#');
- gdbstub_tx_char(hex_asc_hi(checksum));
- gdbstub_tx_char(hex_asc_lo(checksum));
-
- } while (gdbstub_rx_char(&ch,0),
-#ifdef GDBSTUB_DEBUG_PROTOCOL
- ch=='-' && (gdbstub_proto("### GDB Rx NAK\n"),0),
- ch!='-' && ch!='+' && (gdbstub_proto("### GDB Rx ??? %02x\n",ch),0),
-#endif
- ch!='+' && ch!='$');
-
- if (ch=='+') {
- gdbstub_proto("### GDB Rx ACK\n");
- return 0;
- }
-
- gdbstub_proto("### GDB Tx Abandoned\n");
- gdbstub_rx_unget = ch;
- return 1;
-} /* end gdbstub_send_packet() */
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-static int hexToInt(char **ptr, unsigned long *_value)
-{
- int count = 0, ch;
-
- *_value = 0;
- while (**ptr) {
- ch = hex(**ptr);
- if (ch < 0)
- break;
-
- *_value = (*_value << 4) | ((uint8_t) ch & 0xf);
- count++;
-
- (*ptr)++;
- }
-
- return count;
-}
-
-/*****************************************************************************/
-/*
- * probe an address to see whether it maps to anything
- */
-static inline int gdbstub_addr_probe(const void *vaddr)
-{
-#ifdef CONFIG_MMU
- unsigned long paddr;
-
- asm("lrad %1,%0,#1,#0,#0" : "=r"(paddr) : "r"(vaddr));
- if (!(paddr & xAMPRx_V))
- return 0;
-#endif
-
- return 1;
-} /* end gdbstub_addr_probe() */
-
-#ifdef CONFIG_MMU
-static unsigned long __saved_dampr, __saved_damlr;
-
-static inline unsigned long gdbstub_virt_to_pte(unsigned long vaddr)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned long val, dampr5;
-
- pgd = (pgd_t *) __get_DAMLR(3) + pgd_index(vaddr);
- pud = pud_offset(pgd, vaddr);
- pmd = pmd_offset(pud, vaddr);
-
- if (pmd_bad(*pmd) || !pmd_present(*pmd))
- return 0;
-
- /* make sure dampr5 maps to the correct pmd */
- dampr5 = __get_DAMPR(5);
- val = pmd_val(*pmd);
- __set_DAMPR(5, val | xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C | xAMPRx_V);
-
- /* now its safe to access pmd */
- pte = (pte_t *)__get_DAMLR(5) + __pte_index(vaddr);
- if (pte_present(*pte))
- val = pte_val(*pte);
- else
- val = 0;
-
- /* restore original dampr5 */
- __set_DAMPR(5, dampr5);
-
- return val;
-}
-#endif
-
-static inline int gdbstub_addr_map(const void *vaddr)
-{
-#ifdef CONFIG_MMU
- unsigned long pte;
-
- __saved_dampr = __get_DAMPR(2);
- __saved_damlr = __get_DAMLR(2);
-#endif
- if (gdbstub_addr_probe(vaddr))
- return 1;
-#ifdef CONFIG_MMU
- pte = gdbstub_virt_to_pte((unsigned long) vaddr);
- if (pte) {
- __set_DAMPR(2, pte);
- __set_DAMLR(2, (unsigned long) vaddr & PAGE_MASK);
- return 1;
- }
-#endif
- return 0;
-}
-
-static inline void gdbstub_addr_unmap(void)
-{
-#ifdef CONFIG_MMU
- __set_DAMPR(2, __saved_dampr);
- __set_DAMLR(2, __saved_damlr);
-#endif
-}
-
-/*
- * access potentially dodgy memory through a potentially dodgy pointer
- */
-static inline int gdbstub_read_dword(const void *addr, uint32_t *_res)
-{
- unsigned long brr;
- uint32_t res;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " ld%I2 %M2,%0 \n"
- " movsg brr,%1 \n"
- : "=r"(res), "=r"(brr)
- : "m"(*(uint32_t *) addr));
- *_res = res;
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_write_dword(void *addr, uint32_t val)
-{
- unsigned long brr;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " st%I2 %1,%M2 \n"
- " movsg brr,%0 \n"
- : "=r"(brr)
- : "r"(val), "m"(*(uint32_t *) addr));
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_read_word(const void *addr, uint16_t *_res)
-{
- unsigned long brr;
- uint16_t res;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " lduh%I2 %M2,%0 \n"
- " movsg brr,%1 \n"
- : "=r"(res), "=r"(brr)
- : "m"(*(uint16_t *) addr));
- *_res = res;
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_write_word(void *addr, uint16_t val)
-{
- unsigned long brr;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " sth%I2 %1,%M2 \n"
- " movsg brr,%0 \n"
- : "=r"(brr)
- : "r"(val), "m"(*(uint16_t *) addr));
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_read_byte(const void *addr, uint8_t *_res)
-{
- unsigned long brr;
- uint8_t res;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " ldub%I2 %M2,%0 \n"
- " movsg brr,%1 \n"
- : "=r"(res), "=r"(brr)
- : "m"(*(uint8_t *) addr));
- *_res = res;
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_write_byte(void *addr, uint8_t val)
-{
- unsigned long brr;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " stb%I2 %1,%M2 \n"
- " movsg brr,%0 \n"
- : "=r"(brr)
- : "r"(val), "m"(*(uint8_t *) addr));
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static void __gdbstub_console_write(struct console *co, const char *p, unsigned n)
-{
- char outbuf[26];
- int qty;
-
- outbuf[0] = 'O';
-
- while (n > 0) {
- qty = 1;
-
- while (n > 0 && qty < 20) {
- mem2hex(p, outbuf + qty, 2, 0);
- qty += 2;
- if (*p == 0x0a) {
- outbuf[qty++] = '0';
- outbuf[qty++] = 'd';
- }
- p++;
- n--;
- }
-
- outbuf[qty] = 0;
- gdbstub_send_packet(outbuf);
- }
-}
-
-#if 0
-void debug_to_serial(const char *p, int n)
-{
- gdbstub_console_write(NULL,p,n);
-}
-#endif
-
-#ifdef CONFIG_GDB_CONSOLE
-
-static struct console gdbstub_console = {
- .name = "gdb",
- .write = gdbstub_console_write, /* in break.S */
- .flags = CON_PRINTBUFFER,
- .index = -1,
-};
-
-#endif
-
-/*****************************************************************************/
-/*
- * Convert the memory pointed to by mem into hex, placing result in buf.
- * - if successful, return a pointer to the last char put in buf (NUL)
- * - in case of mem fault, return NULL
- * may_fault is non-zero if we are reading from arbitrary memory, but is currently
- * not used.
- */
-static unsigned char *mem2hex(const void *_mem, char *buf, int count, int may_fault)
-{
- const uint8_t *mem = _mem;
- uint8_t ch[4] __attribute__((aligned(4)));
-
- if ((uint32_t)mem&1 && count>=1) {
- if (!gdbstub_read_byte(mem,ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- mem++;
- count--;
- }
-
- if ((uint32_t)mem&3 && count>=2) {
- if (!gdbstub_read_word(mem,(uint16_t *)ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- mem += 2;
- count -= 2;
- }
-
- while (count>=4) {
- if (!gdbstub_read_dword(mem,(uint32_t *)ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- buf = hex_byte_pack(buf, ch[2]);
- buf = hex_byte_pack(buf, ch[3]);
- mem += 4;
- count -= 4;
- }
-
- if (count>=2) {
- if (!gdbstub_read_word(mem,(uint16_t *)ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- mem += 2;
- count -= 2;
- }
-
- if (count>=1) {
- if (!gdbstub_read_byte(mem,ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- }
-
- *buf = 0;
-
- return buf;
-} /* end mem2hex() */
-
-/*****************************************************************************/
-/*
- * convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character AFTER the last byte of buffer consumed
- */
-static char *hex2mem(const char *buf, void *_mem, int count)
-{
- uint8_t *mem = _mem;
- union {
- uint32_t l;
- uint16_t w;
- uint8_t b[4];
- } ch;
-
- if ((u32)mem&1 && count>=1) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- if (!gdbstub_write_byte(mem,ch.b[0]))
- return NULL;
- mem++;
- count--;
- }
-
- if ((u32)mem&3 && count>=2) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- if (!gdbstub_write_word(mem,ch.w))
- return NULL;
- mem += 2;
- count -= 2;
- }
-
- while (count>=4) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- ch.b[2] = hex(*buf++) << 4;
- ch.b[2] |= hex(*buf++);
- ch.b[3] = hex(*buf++) << 4;
- ch.b[3] |= hex(*buf++);
- if (!gdbstub_write_dword(mem,ch.l))
- return NULL;
- mem += 4;
- count -= 4;
- }
-
- if (count>=2) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- if (!gdbstub_write_word(mem,ch.w))
- return NULL;
- mem += 2;
- count -= 2;
- }
-
- if (count>=1) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- if (!gdbstub_write_byte(mem,ch.b[0]))
- return NULL;
- }
-
- return (char *) buf;
-} /* end hex2mem() */
-
-/*****************************************************************************/
-/*
- * This table contains the mapping between FRV TBR.TT exception codes,
- * and signals, which are primarily what GDB understands. It also
- * indicates which hardware traps we need to commandeer when
- * initializing the stub.
- */
-static const struct brr_to_sig_map {
- unsigned long brr_mask; /* BRR bitmask */
- unsigned long tbr_tt; /* TBR.TT code (in BRR.EBTT) */
- unsigned int signo; /* Signal that we map this into */
-} brr_to_sig_map[] = {
- { BRR_EB, TBR_TT_INSTR_ACC_ERROR, SIGSEGV },
- { BRR_EB, TBR_TT_ILLEGAL_INSTR, SIGILL },
- { BRR_EB, TBR_TT_PRIV_INSTR, SIGILL },
- { BRR_EB, TBR_TT_MP_EXCEPTION, SIGFPE },
- { BRR_EB, TBR_TT_DATA_ACC_ERROR, SIGSEGV },
- { BRR_EB, TBR_TT_DATA_STR_ERROR, SIGSEGV },
- { BRR_EB, TBR_TT_DIVISION_EXCEP, SIGFPE },
- { BRR_EB, TBR_TT_COMPOUND_EXCEP, SIGSEGV },
- { BRR_EB, TBR_TT_INTERRUPT_13, SIGALRM }, /* watchdog */
- { BRR_EB, TBR_TT_INTERRUPT_14, SIGINT }, /* GDB serial */
- { BRR_EB, TBR_TT_INTERRUPT_15, SIGQUIT }, /* NMI */
- { BRR_CB, 0, SIGUSR1 },
- { BRR_TB, 0, SIGUSR2 },
- { BRR_DBNEx, 0, SIGTRAP },
- { BRR_DBx, 0, SIGTRAP }, /* h/w watchpoint */
- { BRR_IBx, 0, SIGTRAP }, /* h/w breakpoint */
- { BRR_CBB, 0, SIGTRAP },
- { BRR_SB, 0, SIGTRAP },
- { BRR_ST, 0, SIGTRAP }, /* single step */
- { 0, 0, SIGHUP } /* default */
-};
-
-/*****************************************************************************/
-/*
- * convert the FRV BRR register contents into a UNIX signal number
- */
-static inline int gdbstub_compute_signal(unsigned long brr)
-{
- const struct brr_to_sig_map *map;
- unsigned long tbr = (brr & BRR_EBTT) >> 12;
-
- for (map = brr_to_sig_map; map->brr_mask; map++)
- if (map->brr_mask & brr)
- if (!map->tbr_tt || map->tbr_tt == tbr)
- break;
-
- return map->signo;
-} /* end gdbstub_compute_signal() */
-
-/*****************************************************************************/
-/*
- * set a software breakpoint or a hardware breakpoint or watchpoint
- */
-static int gdbstub_set_breakpoint(unsigned long type, unsigned long addr, unsigned long len)
-{
- unsigned long tmp;
- int bkpt, loop, xloop;
-
- union {
- struct {
- unsigned long mask0, mask1;
- };
- uint8_t bytes[8];
- } dbmr;
-
- //gdbstub_printk("setbkpt(%ld,%08lx,%ld)\n", type, addr, len);
-
- switch (type) {
- /* set software breakpoint */
- case 0:
- if (addr & 3 || len > 7*4)
- return -EINVAL;
-
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (!gdbstub_bkpts[bkpt].addr)
- break;
- if (bkpt < 0)
- return -ENOSPC;
-
- for (loop = 0; loop < len/4; loop++)
- if (!gdbstub_read_dword(&((uint32_t *) addr)[loop],
- &gdbstub_bkpts[bkpt].originsns[loop]))
- return -EFAULT;
-
- for (loop = 0; loop < len/4; loop++)
- if (!gdbstub_write_dword(&((uint32_t *) addr)[loop],
- BREAK_INSN)
- ) {
- /* need to undo the changes if possible */
- for (xloop = 0; xloop < loop; xloop++)
- gdbstub_write_dword(&((uint32_t *) addr)[xloop],
- gdbstub_bkpts[bkpt].originsns[xloop]);
- return -EFAULT;
- }
-
- gdbstub_bkpts[bkpt].addr = addr;
- gdbstub_bkpts[bkpt].len = len;
-
-#if 0
- gdbstub_printk("Set BKPT[%02x]: %08lx #%d {%04x, %04x} -> { %04x, %04x }\n",
- bkpt,
- gdbstub_bkpts[bkpt].addr,
- gdbstub_bkpts[bkpt].len,
- gdbstub_bkpts[bkpt].originsns[0],
- gdbstub_bkpts[bkpt].originsns[1],
- ((uint32_t *) addr)[0],
- ((uint32_t *) addr)[1]
- );
-#endif
- return 0;
-
- /* set hardware breakpoint */
- case 1:
- if (addr & 3 || len != 4)
- return -EINVAL;
-
- if (!(__debug_regs->dcr & DCR_IBE0)) {
- //gdbstub_printk("set h/w break 0: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE0;
- __debug_regs->ibar[0] = addr;
- asm volatile("movgs %0,ibar0" : : "r"(addr));
- return 0;
- }
-
- if (!(__debug_regs->dcr & DCR_IBE1)) {
- //gdbstub_printk("set h/w break 1: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE1;
- __debug_regs->ibar[1] = addr;
- asm volatile("movgs %0,ibar1" : : "r"(addr));
- return 0;
- }
-
- if (!(__debug_regs->dcr & DCR_IBE2)) {
- //gdbstub_printk("set h/w break 2: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE2;
- __debug_regs->ibar[2] = addr;
- asm volatile("movgs %0,ibar2" : : "r"(addr));
- return 0;
- }
-
- if (!(__debug_regs->dcr & DCR_IBE3)) {
- //gdbstub_printk("set h/w break 3: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE3;
- __debug_regs->ibar[3] = addr;
- asm volatile("movgs %0,ibar3" : : "r"(addr));
- return 0;
- }
-
- return -ENOSPC;
-
- /* set data read/write/access watchpoint */
- case 2:
- case 3:
- case 4:
- if ((addr & ~7) != ((addr + len - 1) & ~7))
- return -EINVAL;
-
- tmp = addr & 7;
-
- memset(dbmr.bytes, 0xff, sizeof(dbmr.bytes));
- for (loop = 0; loop < len; loop++)
- dbmr.bytes[tmp + loop] = 0;
-
- addr &= ~7;
-
- if (!(__debug_regs->dcr & (DCR_DRBE0|DCR_DWBE0))) {
- //gdbstub_printk("set h/w watchpoint 0 type %ld: %08lx\n", type, addr);
- tmp = type==2 ? DCR_DWBE0 : type==3 ? DCR_DRBE0 : DCR_DRBE0|DCR_DWBE0;
-
- __debug_regs->dcr |= tmp;
- __debug_regs->dbar[0] = addr;
- __debug_regs->dbmr[0][0] = dbmr.mask0;
- __debug_regs->dbmr[0][1] = dbmr.mask1;
- __debug_regs->dbdr[0][0] = 0;
- __debug_regs->dbdr[0][1] = 0;
-
- asm volatile(" movgs %0,dbar0 \n"
- " movgs %1,dbmr00 \n"
- " movgs %2,dbmr01 \n"
- " movgs gr0,dbdr00 \n"
- " movgs gr0,dbdr01 \n"
- : : "r"(addr), "r"(dbmr.mask0), "r"(dbmr.mask1));
- return 0;
- }
-
- if (!(__debug_regs->dcr & (DCR_DRBE1|DCR_DWBE1))) {
- //gdbstub_printk("set h/w watchpoint 1 type %ld: %08lx\n", type, addr);
- tmp = type==2 ? DCR_DWBE1 : type==3 ? DCR_DRBE1 : DCR_DRBE1|DCR_DWBE1;
-
- __debug_regs->dcr |= tmp;
- __debug_regs->dbar[1] = addr;
- __debug_regs->dbmr[1][0] = dbmr.mask0;
- __debug_regs->dbmr[1][1] = dbmr.mask1;
- __debug_regs->dbdr[1][0] = 0;
- __debug_regs->dbdr[1][1] = 0;
-
- asm volatile(" movgs %0,dbar1 \n"
- " movgs %1,dbmr10 \n"
- " movgs %2,dbmr11 \n"
- " movgs gr0,dbdr10 \n"
- " movgs gr0,dbdr11 \n"
- : : "r"(addr), "r"(dbmr.mask0), "r"(dbmr.mask1));
- return 0;
- }
-
- return -ENOSPC;
-
- default:
- return -EINVAL;
- }
-
-} /* end gdbstub_set_breakpoint() */
-
-/*****************************************************************************/
-/*
- * clear a breakpoint or watchpoint
- */
-int gdbstub_clear_breakpoint(unsigned long type, unsigned long addr, unsigned long len)
-{
- unsigned long tmp;
- int bkpt, loop;
-
- union {
- struct {
- unsigned long mask0, mask1;
- };
- uint8_t bytes[8];
- } dbmr;
-
- //gdbstub_printk("clearbkpt(%ld,%08lx,%ld)\n", type, addr, len);
-
- switch (type) {
- /* clear software breakpoint */
- case 0:
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (gdbstub_bkpts[bkpt].addr == addr && gdbstub_bkpts[bkpt].len == len)
- break;
- if (bkpt < 0)
- return -ENOENT;
-
- gdbstub_bkpts[bkpt].addr = 0;
-
- for (loop = 0; loop < len/4; loop++)
- if (!gdbstub_write_dword(&((uint32_t *) addr)[loop],
- gdbstub_bkpts[bkpt].originsns[loop]))
- return -EFAULT;
- return 0;
-
- /* clear hardware breakpoint */
- case 1:
- if (addr & 3 || len != 4)
- return -EINVAL;
-
-#define __get_ibar(X) ({ unsigned long x; asm volatile("movsg ibar"#X",%0" : "=r"(x)); x; })
-
- if (__debug_regs->dcr & DCR_IBE0 && __get_ibar(0) == addr) {
- //gdbstub_printk("clear h/w break 0: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE0;
- __debug_regs->ibar[0] = 0;
- asm volatile("movgs gr0,ibar0");
- return 0;
- }
-
- if (__debug_regs->dcr & DCR_IBE1 && __get_ibar(1) == addr) {
- //gdbstub_printk("clear h/w break 1: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE1;
- __debug_regs->ibar[1] = 0;
- asm volatile("movgs gr0,ibar1");
- return 0;
- }
-
- if (__debug_regs->dcr & DCR_IBE2 && __get_ibar(2) == addr) {
- //gdbstub_printk("clear h/w break 2: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE2;
- __debug_regs->ibar[2] = 0;
- asm volatile("movgs gr0,ibar2");
- return 0;
- }
-
- if (__debug_regs->dcr & DCR_IBE3 && __get_ibar(3) == addr) {
- //gdbstub_printk("clear h/w break 3: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE3;
- __debug_regs->ibar[3] = 0;
- asm volatile("movgs gr0,ibar3");
- return 0;
- }
-
- return -EINVAL;
-
- /* clear data read/write/access watchpoint */
- case 2:
- case 3:
- case 4:
- if ((addr & ~7) != ((addr + len - 1) & ~7))
- return -EINVAL;
-
- tmp = addr & 7;
-
- memset(dbmr.bytes, 0xff, sizeof(dbmr.bytes));
- for (loop = 0; loop < len; loop++)
- dbmr.bytes[tmp + loop] = 0;
-
- addr &= ~7;
-
-#define __get_dbar(X) ({ unsigned long x; asm volatile("movsg dbar"#X",%0" : "=r"(x)); x; })
-#define __get_dbmr0(X) ({ unsigned long x; asm volatile("movsg dbmr"#X"0,%0" : "=r"(x)); x; })
-#define __get_dbmr1(X) ({ unsigned long x; asm volatile("movsg dbmr"#X"1,%0" : "=r"(x)); x; })
-
- /* consider DBAR 0 */
- tmp = type==2 ? DCR_DWBE0 : type==3 ? DCR_DRBE0 : DCR_DRBE0|DCR_DWBE0;
-
- if ((__debug_regs->dcr & (DCR_DRBE0|DCR_DWBE0)) != tmp ||
- __get_dbar(0) != addr ||
- __get_dbmr0(0) != dbmr.mask0 ||
- __get_dbmr1(0) != dbmr.mask1)
- goto skip_dbar0;
-
- //gdbstub_printk("clear h/w watchpoint 0 type %ld: %08lx\n", type, addr);
- __debug_regs->dcr &= ~(DCR_DRBE0|DCR_DWBE0);
- __debug_regs->dbar[0] = 0;
- __debug_regs->dbmr[0][0] = 0;
- __debug_regs->dbmr[0][1] = 0;
- __debug_regs->dbdr[0][0] = 0;
- __debug_regs->dbdr[0][1] = 0;
-
- asm volatile(" movgs gr0,dbar0 \n"
- " movgs gr0,dbmr00 \n"
- " movgs gr0,dbmr01 \n"
- " movgs gr0,dbdr00 \n"
- " movgs gr0,dbdr01 \n");
- return 0;
-
- skip_dbar0:
- /* consider DBAR 0 */
- tmp = type==2 ? DCR_DWBE1 : type==3 ? DCR_DRBE1 : DCR_DRBE1|DCR_DWBE1;
-
- if ((__debug_regs->dcr & (DCR_DRBE1|DCR_DWBE1)) != tmp ||
- __get_dbar(1) != addr ||
- __get_dbmr0(1) != dbmr.mask0 ||
- __get_dbmr1(1) != dbmr.mask1)
- goto skip_dbar1;
-
- //gdbstub_printk("clear h/w watchpoint 1 type %ld: %08lx\n", type, addr);
- __debug_regs->dcr &= ~(DCR_DRBE1|DCR_DWBE1);
- __debug_regs->dbar[1] = 0;
- __debug_regs->dbmr[1][0] = 0;
- __debug_regs->dbmr[1][1] = 0;
- __debug_regs->dbdr[1][0] = 0;
- __debug_regs->dbdr[1][1] = 0;
-
- asm volatile(" movgs gr0,dbar1 \n"
- " movgs gr0,dbmr10 \n"
- " movgs gr0,dbmr11 \n"
- " movgs gr0,dbdr10 \n"
- " movgs gr0,dbdr11 \n");
- return 0;
-
- skip_dbar1:
- return -ENOSPC;
-
- default:
- return -EINVAL;
- }
-} /* end gdbstub_clear_breakpoint() */
-
-/*****************************************************************************/
-/*
- * check a for an internal software breakpoint, and wind the PC back if necessary
- */
-static void gdbstub_check_breakpoint(void)
-{
- unsigned long addr = __debug_frame->pc - 4;
- int bkpt;
-
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (gdbstub_bkpts[bkpt].addr == addr)
- break;
- if (bkpt >= 0)
- __debug_frame->pc = addr;
-
- //gdbstub_printk("alter pc [%d] %08lx\n", bkpt, __debug_frame->pc);
-
-} /* end gdbstub_check_breakpoint() */
-
-/*****************************************************************************/
-/*
- *
- */
-static void __maybe_unused gdbstub_show_regs(void)
-{
- unsigned long *reg;
- int loop;
-
- gdbstub_printk("\n");
-
- gdbstub_printk("Frame: @%p [%s]\n",
- __debug_frame,
- __debug_frame->psr & PSR_S ? "kernel" : "user");
-
- reg = (unsigned long *) __debug_frame;
- for (loop = 0; loop < NR_PT_REGS; loop++) {
- printk("%s %08lx", regnames[loop + 0], reg[loop + 0]);
-
- if (loop == NR_PT_REGS - 1 || loop % 5 == 4)
- printk("\n");
- else
- printk(" | ");
- }
-
- gdbstub_printk("Process %s (pid: %d)\n", current->comm, current->pid);
-} /* end gdbstub_show_regs() */
-
-/*****************************************************************************/
-/*
- * dump debugging regs
- */
-static void __maybe_unused gdbstub_dump_debugregs(void)
-{
- gdbstub_printk("DCR %08lx ", __debug_status.dcr);
- gdbstub_printk("BRR %08lx\n", __debug_status.brr);
-
- gdbstub_printk("IBAR0 %08lx ", __get_ibar(0));
- gdbstub_printk("IBAR1 %08lx ", __get_ibar(1));
- gdbstub_printk("IBAR2 %08lx ", __get_ibar(2));
- gdbstub_printk("IBAR3 %08lx\n", __get_ibar(3));
-
- gdbstub_printk("DBAR0 %08lx ", __get_dbar(0));
- gdbstub_printk("DBMR00 %08lx ", __get_dbmr0(0));
- gdbstub_printk("DBMR01 %08lx\n", __get_dbmr1(0));
-
- gdbstub_printk("DBAR1 %08lx ", __get_dbar(1));
- gdbstub_printk("DBMR10 %08lx ", __get_dbmr0(1));
- gdbstub_printk("DBMR11 %08lx\n", __get_dbmr1(1));
-
- gdbstub_printk("\n");
-} /* end gdbstub_dump_debugregs() */
-
-/*****************************************************************************/
-/*
- * dump the MMU state into a structure so that it can be accessed with GDB
- */
-void gdbstub_get_mmu_state(void)
-{
- asm volatile("movsg hsr0,%0" : "=r"(__debug_mmu.regs.hsr0));
- asm volatile("movsg pcsr,%0" : "=r"(__debug_mmu.regs.pcsr));
- asm volatile("movsg esr0,%0" : "=r"(__debug_mmu.regs.esr0));
- asm volatile("movsg ear0,%0" : "=r"(__debug_mmu.regs.ear0));
- asm volatile("movsg epcr0,%0" : "=r"(__debug_mmu.regs.epcr0));
-
- /* read the protection / SAT registers */
- __debug_mmu.iamr[0].L = __get_IAMLR(0);
- __debug_mmu.iamr[0].P = __get_IAMPR(0);
- __debug_mmu.iamr[1].L = __get_IAMLR(1);
- __debug_mmu.iamr[1].P = __get_IAMPR(1);
- __debug_mmu.iamr[2].L = __get_IAMLR(2);
- __debug_mmu.iamr[2].P = __get_IAMPR(2);
- __debug_mmu.iamr[3].L = __get_IAMLR(3);
- __debug_mmu.iamr[3].P = __get_IAMPR(3);
- __debug_mmu.iamr[4].L = __get_IAMLR(4);
- __debug_mmu.iamr[4].P = __get_IAMPR(4);
- __debug_mmu.iamr[5].L = __get_IAMLR(5);
- __debug_mmu.iamr[5].P = __get_IAMPR(5);
- __debug_mmu.iamr[6].L = __get_IAMLR(6);
- __debug_mmu.iamr[6].P = __get_IAMPR(6);
- __debug_mmu.iamr[7].L = __get_IAMLR(7);
- __debug_mmu.iamr[7].P = __get_IAMPR(7);
- __debug_mmu.iamr[8].L = __get_IAMLR(8);
- __debug_mmu.iamr[8].P = __get_IAMPR(8);
- __debug_mmu.iamr[9].L = __get_IAMLR(9);
- __debug_mmu.iamr[9].P = __get_IAMPR(9);
- __debug_mmu.iamr[10].L = __get_IAMLR(10);
- __debug_mmu.iamr[10].P = __get_IAMPR(10);
- __debug_mmu.iamr[11].L = __get_IAMLR(11);
- __debug_mmu.iamr[11].P = __get_IAMPR(11);
- __debug_mmu.iamr[12].L = __get_IAMLR(12);
- __debug_mmu.iamr[12].P = __get_IAMPR(12);
- __debug_mmu.iamr[13].L = __get_IAMLR(13);
- __debug_mmu.iamr[13].P = __get_IAMPR(13);
- __debug_mmu.iamr[14].L = __get_IAMLR(14);
- __debug_mmu.iamr[14].P = __get_IAMPR(14);
- __debug_mmu.iamr[15].L = __get_IAMLR(15);
- __debug_mmu.iamr[15].P = __get_IAMPR(15);
-
- __debug_mmu.damr[0].L = __get_DAMLR(0);
- __debug_mmu.damr[0].P = __get_DAMPR(0);
- __debug_mmu.damr[1].L = __get_DAMLR(1);
- __debug_mmu.damr[1].P = __get_DAMPR(1);
- __debug_mmu.damr[2].L = __get_DAMLR(2);
- __debug_mmu.damr[2].P = __get_DAMPR(2);
- __debug_mmu.damr[3].L = __get_DAMLR(3);
- __debug_mmu.damr[3].P = __get_DAMPR(3);
- __debug_mmu.damr[4].L = __get_DAMLR(4);
- __debug_mmu.damr[4].P = __get_DAMPR(4);
- __debug_mmu.damr[5].L = __get_DAMLR(5);
- __debug_mmu.damr[5].P = __get_DAMPR(5);
- __debug_mmu.damr[6].L = __get_DAMLR(6);
- __debug_mmu.damr[6].P = __get_DAMPR(6);
- __debug_mmu.damr[7].L = __get_DAMLR(7);
- __debug_mmu.damr[7].P = __get_DAMPR(7);
- __debug_mmu.damr[8].L = __get_DAMLR(8);
- __debug_mmu.damr[8].P = __get_DAMPR(8);
- __debug_mmu.damr[9].L = __get_DAMLR(9);
- __debug_mmu.damr[9].P = __get_DAMPR(9);
- __debug_mmu.damr[10].L = __get_DAMLR(10);
- __debug_mmu.damr[10].P = __get_DAMPR(10);
- __debug_mmu.damr[11].L = __get_DAMLR(11);
- __debug_mmu.damr[11].P = __get_DAMPR(11);
- __debug_mmu.damr[12].L = __get_DAMLR(12);
- __debug_mmu.damr[12].P = __get_DAMPR(12);
- __debug_mmu.damr[13].L = __get_DAMLR(13);
- __debug_mmu.damr[13].P = __get_DAMPR(13);
- __debug_mmu.damr[14].L = __get_DAMLR(14);
- __debug_mmu.damr[14].P = __get_DAMPR(14);
- __debug_mmu.damr[15].L = __get_DAMLR(15);
- __debug_mmu.damr[15].P = __get_DAMPR(15);
-
-#ifdef CONFIG_MMU
- do {
- /* read the DAT entries from the TLB */
- struct __debug_amr *p;
- int loop;
-
- asm volatile("movsg tplr,%0" : "=r"(__debug_mmu.regs.tplr));
- asm volatile("movsg tppr,%0" : "=r"(__debug_mmu.regs.tppr));
- asm volatile("movsg tpxr,%0" : "=r"(__debug_mmu.regs.tpxr));
- asm volatile("movsg cxnr,%0" : "=r"(__debug_mmu.regs.cxnr));
-
- p = __debug_mmu.tlb;
-
- /* way 0 */
- asm volatile("movgs %0,tpxr" :: "r"(0 << TPXR_WAY_SHIFT));
- for (loop = 0; loop < 64; loop++) {
- asm volatile("tlbpr %0,gr0,#1,#0" :: "r"(loop << PAGE_SHIFT));
- asm volatile("movsg tplr,%0" : "=r"(p->L));
- asm volatile("movsg tppr,%0" : "=r"(p->P));
- p++;
- }
-
- /* way 1 */
- asm volatile("movgs %0,tpxr" :: "r"(1 << TPXR_WAY_SHIFT));
- for (loop = 0; loop < 64; loop++) {
- asm volatile("tlbpr %0,gr0,#1,#0" :: "r"(loop << PAGE_SHIFT));
- asm volatile("movsg tplr,%0" : "=r"(p->L));
- asm volatile("movsg tppr,%0" : "=r"(p->P));
- p++;
- }
-
- asm volatile("movgs %0,tplr" :: "r"(__debug_mmu.regs.tplr));
- asm volatile("movgs %0,tppr" :: "r"(__debug_mmu.regs.tppr));
- asm volatile("movgs %0,tpxr" :: "r"(__debug_mmu.regs.tpxr));
- } while(0);
-#endif
-
-} /* end gdbstub_get_mmu_state() */
-
-/*
- * handle general query commands of the form 'qXXXXX'
- */
-static void gdbstub_handle_query(void)
-{
- if (strcmp(input_buffer, "qAttached") == 0) {
- /* return current thread ID */
- sprintf(output_buffer, "1");
- return;
- }
-
- if (strcmp(input_buffer, "qC") == 0) {
- /* return current thread ID */
- sprintf(output_buffer, "QC 0");
- return;
- }
-
- if (strcmp(input_buffer, "qOffsets") == 0) {
- /* return relocation offset of text and data segments */
- sprintf(output_buffer, "Text=0;Data=0;Bss=0");
- return;
- }
-
- if (strcmp(input_buffer, "qSymbol::") == 0) {
- sprintf(output_buffer, "OK");
- return;
- }
-
- if (strcmp(input_buffer, "qSupported") == 0) {
- /* query of supported features */
- sprintf(output_buffer, "PacketSize=%u;ReverseContinue-;ReverseStep-",
- sizeof(input_buffer));
- return;
- }
-
- gdbstub_strcpy(output_buffer,"E01");
-}
-
-/*****************************************************************************/
-/*
- * handle event interception and GDB remote protocol processing
- * - on entry:
- * PSR.ET==0, PSR.S==1 and the CPU is in debug mode
- * __debug_frame points to the saved registers
- * __frame points to the kernel mode exception frame, if it was in kernel
- * mode when the break happened
- */
-void gdbstub(int sigval)
-{
- unsigned long addr, length, loop, dbar, temp, temp2, temp3;
- uint32_t zero;
- char *ptr;
- int flush_cache = 0;
-
- LEDS(0x5000);
-
- if (sigval < 0) {
-#ifndef CONFIG_GDBSTUB_IMMEDIATE
- /* return immediately if GDB immediate activation option not set */
- return;
-#else
- sigval = SIGINT;
-#endif
- }
-
- save_user_regs(&__debug_frame0->uc);
-
-#if 0
- gdbstub_printk("--> gdbstub() %08x %p %08x %08x\n",
- __debug_frame->pc,
- __debug_frame,
- __debug_regs->brr,
- __debug_regs->bpsr);
-// gdbstub_show_regs();
-#endif
-
- LEDS(0x5001);
-
- /* if we were interrupted by input on the serial gdbstub serial port,
- * restore the context prior to the interrupt so that we return to that
- * directly
- */
- temp = (unsigned long) __entry_kerneltrap_table;
- temp2 = (unsigned long) __entry_usertrap_table;
- temp3 = __debug_frame->pc & ~15;
-
- if (temp3 == temp + TBR_TT_INTERRUPT_15 ||
- temp3 == temp2 + TBR_TT_INTERRUPT_15
- ) {
- asm volatile("movsg pcsr,%0" : "=r"(__debug_frame->pc));
- __debug_frame->psr |= PSR_ET;
- __debug_frame->psr &= ~PSR_S;
- if (__debug_frame->psr & PSR_PS)
- __debug_frame->psr |= PSR_S;
- __debug_status.brr = (__debug_frame->tbr & TBR_TT) << 12;
- __debug_status.brr |= BRR_EB;
- sigval = SIGINT;
- }
-
- /* handle the decrement timer going off (FR451 only) */
- if (temp3 == temp + TBR_TT_DECREMENT_TIMER ||
- temp3 == temp2 + TBR_TT_DECREMENT_TIMER
- ) {
- asm volatile("movgs %0,timerd" :: "r"(10000000));
- asm volatile("movsg pcsr,%0" : "=r"(__debug_frame->pc));
- __debug_frame->psr |= PSR_ET;
- __debug_frame->psr &= ~PSR_S;
- if (__debug_frame->psr & PSR_PS)
- __debug_frame->psr |= PSR_S;
- __debug_status.brr = (__debug_frame->tbr & TBR_TT) << 12;
- __debug_status.brr |= BRR_EB;
- sigval = SIGXCPU;
- }
-
- LEDS(0x5002);
-
- /* after a BREAK insn, the PC lands on the far side of it */
- if (__debug_status.brr & BRR_SB)
- gdbstub_check_breakpoint();
-
- LEDS(0x5003);
-
- /* handle attempts to write console data via GDB "O" commands */
- if (__debug_frame->pc == (unsigned long) gdbstub_console_write + 4) {
- __gdbstub_console_write((struct console *) __debug_frame->gr8,
- (const char *) __debug_frame->gr9,
- (unsigned) __debug_frame->gr10);
- goto done;
- }
-
- if (gdbstub_rx_unget) {
- sigval = SIGINT;
- goto packet_waiting;
- }
-
- if (!sigval)
- sigval = gdbstub_compute_signal(__debug_status.brr);
-
- LEDS(0x5004);
-
- /* send a message to the debugger's user saying what happened if it may
- * not be clear cut (we can't map exceptions onto signals properly)
- */
- if (sigval != SIGINT && sigval != SIGTRAP && sigval != SIGILL) {
- static const char title[] = "Break ";
- static const char crlf[] = "\r\n";
- unsigned long brr = __debug_status.brr;
- char hx;
-
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(title, ptr, sizeof(title) - 1,0);
-
- hx = hex_asc_hi(brr >> 24);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr >> 24);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(brr >> 16);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr >> 16);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(brr >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(brr);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr);
- ptr = hex_byte_pack(ptr, hx);
-
- ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0);
- *ptr = 0;
- gdbstub_send_packet(output_buffer); /* send it off... */
- }
-
- LEDS(0x5005);
-
- /* tell the debugger that an exception has occurred */
- ptr = output_buffer;
-
- /* Send trap type (converted to signal) */
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- /* Send Error PC */
- ptr = hex_byte_pack(ptr, GDB_REG_PC);
- *ptr++ = ':';
- ptr = mem2hex(&__debug_frame->pc, ptr, 4, 0);
- *ptr++ = ';';
-
- /*
- * Send frame pointer
- */
- ptr = hex_byte_pack(ptr, GDB_REG_FP);
- *ptr++ = ':';
- ptr = mem2hex(&__debug_frame->fp, ptr, 4, 0);
- *ptr++ = ';';
-
- /*
- * Send stack pointer
- */
- ptr = hex_byte_pack(ptr, GDB_REG_SP);
- *ptr++ = ':';
- ptr = mem2hex(&__debug_frame->sp, ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = 0;
- gdbstub_send_packet(output_buffer); /* send it off... */
-
- LEDS(0x5006);
-
- packet_waiting:
- gdbstub_get_mmu_state();
-
- /* wait for input from remote GDB */
- while (1) {
- output_buffer[0] = 0;
-
- LEDS(0x5007);
- gdbstub_recv_packet(input_buffer);
- LEDS(0x5600 | input_buffer[0]);
-
- switch (input_buffer[0]) {
- /* request repeat of last signal number */
- case '?':
- output_buffer[0] = 'S';
- output_buffer[1] = hex_asc_hi(sigval);
- output_buffer[2] = hex_asc_lo(sigval);
- output_buffer[3] = 0;
- break;
-
- case 'd':
- /* toggle debug flag */
- break;
-
- /* return the value of the CPU registers
- * - GR0, GR1, GR2, GR3, GR4, GR5, GR6, GR7,
- * - GR8, GR9, GR10, GR11, GR12, GR13, GR14, GR15,
- * - GR16, GR17, GR18, GR19, GR20, GR21, GR22, GR23,
- * - GR24, GR25, GR26, GR27, GR28, GR29, GR30, GR31,
- * - GR32, GR33, GR34, GR35, GR36, GR37, GR38, GR39,
- * - GR40, GR41, GR42, GR43, GR44, GR45, GR46, GR47,
- * - GR48, GR49, GR50, GR51, GR52, GR53, GR54, GR55,
- * - GR56, GR57, GR58, GR59, GR60, GR61, GR62, GR63,
- * - FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
- * - FP8, FP9, FP10, FP11, FP12, FP13, FP14, FP15,
- * - FP16, FP17, FP18, FP19, FP20, FP21, FP22, FP23,
- * - FP24, FP25, FP26, FP27, FP28, FP29, FP30, FP31,
- * - FP32, FP33, FP34, FP35, FP36, FP37, FP38, FP39,
- * - FP40, FP41, FP42, FP43, FP44, FP45, FP46, FP47,
- * - FP48, FP49, FP50, FP51, FP52, FP53, FP54, FP55,
- * - FP56, FP57, FP58, FP59, FP60, FP61, FP62, FP63,
- * - PC, PSR, CCR, CCCR,
- * - _X132, _X133, _X134
- * - TBR, BRR, DBAR0, DBAR1, DBAR2, DBAR3,
- * - _X141, _X142, _X143, _X144,
- * - LR, LCR
- */
- case 'g':
- zero = 0;
- ptr = output_buffer;
-
- /* deal with GR0, GR1-GR27, GR28-GR31, GR32-GR63 */
- ptr = mem2hex(&zero, ptr, 4, 0);
-
- for (loop = 1; loop <= 27; loop++)
- ptr = mem2hex(&__debug_user_context->i.gr[loop], ptr, 4, 0);
- temp = (unsigned long) __frame;
- ptr = mem2hex(&temp, ptr, 4, 0);
- ptr = mem2hex(&__debug_user_context->i.gr[29], ptr, 4, 0);
- ptr = mem2hex(&__debug_user_context->i.gr[30], ptr, 4, 0);
-#ifdef CONFIG_MMU
- ptr = mem2hex(&__debug_user_context->i.gr[31], ptr, 4, 0);
-#else
- temp = (unsigned long) __debug_frame;
- ptr = mem2hex(&temp, ptr, 4, 0);
-#endif
-
- for (loop = 32; loop <= 63; loop++)
- ptr = mem2hex(&__debug_user_context->i.gr[loop], ptr, 4, 0);
-
- /* deal with FR0-FR63 */
- for (loop = 0; loop <= 63; loop++)
- ptr = mem2hex(&__debug_user_context->f.fr[loop], ptr, 4, 0);
-
- /* deal with special registers */
- ptr = mem2hex(&__debug_frame->pc, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->psr, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->ccr, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->cccr, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->tbr, ptr, 4, 0);
- ptr = mem2hex(&__debug_status.brr , ptr, 4, 0);
-
- asm volatile("movsg dbar0,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg dbar1,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg dbar2,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg dbar3,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
-
- asm volatile("movsg scr0,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg scr1,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg scr2,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg scr3,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
-
- ptr = mem2hex(&__debug_frame->lr, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->lcr, ptr, 4, 0);
-
- ptr = mem2hex(&__debug_frame->iacc0, ptr, 8, 0);
-
- ptr = mem2hex(&__debug_user_context->f.fsr[0], ptr, 4, 0);
-
- for (loop = 0; loop <= 7; loop++)
- ptr = mem2hex(&__debug_user_context->f.acc[loop], ptr, 4, 0);
-
- ptr = mem2hex(&__debug_user_context->f.accg, ptr, 8, 0);
-
- for (loop = 0; loop <= 1; loop++)
- ptr = mem2hex(&__debug_user_context->f.msr[loop], ptr, 4, 0);
-
- ptr = mem2hex(&__debug_frame->gner0, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->gner1, ptr, 4, 0);
-
- ptr = mem2hex(&__debug_user_context->f.fner[0], ptr, 4, 0);
- ptr = mem2hex(&__debug_user_context->f.fner[1], ptr, 4, 0);
-
- break;
-
- /* set the values of the CPU registers */
- case 'G':
- ptr = &input_buffer[1];
-
- /* deal with GR0, GR1-GR27, GR28-GR31, GR32-GR63 */
- ptr = hex2mem(ptr, &temp, 4);
-
- for (loop = 1; loop <= 27; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->i.gr[loop], 4);
-
- ptr = hex2mem(ptr, &temp, 4);
- __frame = (struct pt_regs *) temp;
- ptr = hex2mem(ptr, &__debug_frame->gr29, 4);
- ptr = hex2mem(ptr, &__debug_frame->gr30, 4);
-#ifdef CONFIG_MMU
- ptr = hex2mem(ptr, &__debug_frame->gr31, 4);
-#else
- ptr = hex2mem(ptr, &temp, 4);
-#endif
-
- for (loop = 32; loop <= 63; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->i.gr[loop], 4);
-
- /* deal with FR0-FR63 */
- for (loop = 0; loop <= 63; loop++)
- ptr = mem2hex(&__debug_user_context->f.fr[loop], ptr, 4, 0);
-
- /* deal with special registers */
- ptr = hex2mem(ptr, &__debug_frame->pc, 4);
- ptr = hex2mem(ptr, &__debug_frame->psr, 4);
- ptr = hex2mem(ptr, &__debug_frame->ccr, 4);
- ptr = hex2mem(ptr, &__debug_frame->cccr,4);
-
- for (loop = 132; loop <= 140; loop++)
- ptr = hex2mem(ptr, &temp, 4);
-
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr0" :: "r"(temp));
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr1" :: "r"(temp));
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr2" :: "r"(temp));
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr3" :: "r"(temp));
-
- ptr = hex2mem(ptr, &__debug_frame->lr, 4);
- ptr = hex2mem(ptr, &__debug_frame->lcr, 4);
-
- ptr = hex2mem(ptr, &__debug_frame->iacc0, 8);
-
- ptr = hex2mem(ptr, &__debug_user_context->f.fsr[0], 4);
-
- for (loop = 0; loop <= 7; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->f.acc[loop], 4);
-
- ptr = hex2mem(ptr, &__debug_user_context->f.accg, 8);
-
- for (loop = 0; loop <= 1; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->f.msr[loop], 4);
-
- ptr = hex2mem(ptr, &__debug_frame->gner0, 4);
- ptr = hex2mem(ptr, &__debug_frame->gner1, 4);
-
- ptr = hex2mem(ptr, &__debug_user_context->f.fner[0], 4);
- ptr = hex2mem(ptr, &__debug_user_context->f.fner[1], 4);
-
- gdbstub_strcpy(output_buffer,"OK");
- break;
-
- /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
- case 'm':
- ptr = &input_buffer[1];
-
- if (hexToInt(&ptr, &addr) &&
- *ptr++ == ',' &&
- hexToInt(&ptr, &length)
- ) {
- if (mem2hex((char *)addr, output_buffer, length, 1))
- break;
- gdbstub_strcpy (output_buffer, "E03");
- }
- else {
- gdbstub_strcpy(output_buffer,"E01");
- }
- break;
-
- /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
- case 'M':
- ptr = &input_buffer[1];
-
- if (hexToInt(&ptr, &addr) &&
- *ptr++ == ',' &&
- hexToInt(&ptr, &length) &&
- *ptr++ == ':'
- ) {
- if (hex2mem(ptr, (char *)addr, length)) {
- gdbstub_strcpy(output_buffer, "OK");
- }
- else {
- gdbstub_strcpy(output_buffer, "E03");
- }
- }
- else
- gdbstub_strcpy(output_buffer, "E02");
-
- flush_cache = 1;
- break;
-
- /* pNN: Read value of reg N and return it */
- case 'p':
- /* return no value, indicating that we don't support
- * this command and that gdb should use 'g' instead */
- break;
-
- /* PNN,=RRRRRRRR: Write value R to reg N return OK */
- case 'P':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr, &addr) ||
- *ptr++ != '=' ||
- !hexToInt(&ptr, &temp)
- ) {
- gdbstub_strcpy(output_buffer, "E01");
- break;
- }
-
- temp2 = 1;
- switch (addr) {
- case GDB_REG_GR(0):
- break;
- case GDB_REG_GR(1) ... GDB_REG_GR(63):
- __debug_user_context->i.gr[addr - GDB_REG_GR(0)] = temp;
- break;
- case GDB_REG_FR(0) ... GDB_REG_FR(63):
- __debug_user_context->f.fr[addr - GDB_REG_FR(0)] = temp;
- break;
- case GDB_REG_PC:
- __debug_user_context->i.pc = temp;
- break;
- case GDB_REG_PSR:
- __debug_user_context->i.psr = temp;
- break;
- case GDB_REG_CCR:
- __debug_user_context->i.ccr = temp;
- break;
- case GDB_REG_CCCR:
- __debug_user_context->i.cccr = temp;
- break;
- case GDB_REG_BRR:
- __debug_status.brr = temp;
- break;
- case GDB_REG_LR:
- __debug_user_context->i.lr = temp;
- break;
- case GDB_REG_LCR:
- __debug_user_context->i.lcr = temp;
- break;
- case GDB_REG_FSR0:
- __debug_user_context->f.fsr[0] = temp;
- break;
- case GDB_REG_ACC(0) ... GDB_REG_ACC(7):
- __debug_user_context->f.acc[addr - GDB_REG_ACC(0)] = temp;
- break;
- case GDB_REG_ACCG(0):
- *(uint32_t *) &__debug_user_context->f.accg[0] = temp;
- break;
- case GDB_REG_ACCG(4):
- *(uint32_t *) &__debug_user_context->f.accg[4] = temp;
- break;
- case GDB_REG_MSR(0) ... GDB_REG_MSR(1):
- __debug_user_context->f.msr[addr - GDB_REG_MSR(0)] = temp;
- break;
- case GDB_REG_GNER(0) ... GDB_REG_GNER(1):
- __debug_user_context->i.gner[addr - GDB_REG_GNER(0)] = temp;
- break;
- case GDB_REG_FNER(0) ... GDB_REG_FNER(1):
- __debug_user_context->f.fner[addr - GDB_REG_FNER(0)] = temp;
- break;
- default:
- temp2 = 0;
- break;
- }
-
- if (temp2) {
- gdbstub_strcpy(output_buffer, "OK");
- }
- else {
- gdbstub_strcpy(output_buffer, "E02");
- }
- break;
-
- /* cAA..AA Continue at address AA..AA(optional) */
- case 'c':
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &input_buffer[1];
- if (hexToInt(&ptr, &addr))
- __debug_frame->pc = addr;
- goto done;
-
- /* kill the program */
- case 'k' :
- goto done; /* just continue */
-
- /* detach */
- case 'D':
- gdbstub_strcpy(output_buffer, "OK");
- break;
-
- /* reset the whole machine (FIXME: system dependent) */
- case 'r':
- break;
-
-
- /* step to next instruction */
- case 's':
- __debug_regs->dcr |= DCR_SE;
- __debug_status.dcr |= DCR_SE;
- goto done;
-
- /* extended command */
- case 'v':
- if (strcmp(input_buffer, "vCont?") == 0) {
- output_buffer[0] = 0;
- break;
- }
- goto unsupported_cmd;
-
- /* set baud rate (bBB) */
- case 'b':
- ptr = &input_buffer[1];
- if (!hexToInt(&ptr, &temp)) {
- gdbstub_strcpy(output_buffer,"B01");
- break;
- }
-
- if (temp) {
- /* ack before changing speed */
- gdbstub_send_packet("OK");
- gdbstub_set_baud(temp);
- }
- break;
-
- /* set breakpoint */
- case 'Z':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr,&temp) || *ptr++ != ',' ||
- !hexToInt(&ptr,&addr) || *ptr++ != ',' ||
- !hexToInt(&ptr,&length)
- ) {
- gdbstub_strcpy(output_buffer,"E01");
- break;
- }
-
- if (temp >= 5) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (gdbstub_set_breakpoint(temp, addr, length) < 0) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (temp == 0)
- flush_cache = 1; /* soft bkpt by modified memory */
-
- gdbstub_strcpy(output_buffer,"OK");
- break;
-
- /* clear breakpoint */
- case 'z':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr,&temp) || *ptr++ != ',' ||
- !hexToInt(&ptr,&addr) || *ptr++ != ',' ||
- !hexToInt(&ptr,&length)
- ) {
- gdbstub_strcpy(output_buffer,"E01");
- break;
- }
-
- if (temp >= 5) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (gdbstub_clear_breakpoint(temp, addr, length) < 0) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (temp == 0)
- flush_cache = 1; /* soft bkpt by modified memory */
-
- gdbstub_strcpy(output_buffer,"OK");
- break;
-
- /* Thread-setting packet */
- case 'H':
- gdbstub_strcpy(output_buffer, "OK");
- break;
-
- case 'q':
- gdbstub_handle_query();
- break;
-
- default:
- unsupported_cmd:
- gdbstub_proto("### GDB Unsupported Cmd '%s'\n",input_buffer);
- gdbstub_strcpy(output_buffer,"E01");
- break;
- }
-
- /* reply to the request */
- LEDS(0x5009);
- gdbstub_send_packet(output_buffer);
- }
-
- done:
- restore_user_regs(&__debug_frame0->uc);
-
- //gdbstub_dump_debugregs();
- //gdbstub_printk("<-- gdbstub() %08x\n", __debug_frame->pc);
-
- /* need to flush the instruction cache before resuming, as we may have
- * deposited a breakpoint, and the icache probably has no way of
- * knowing that a data ref to some location may have changed something
- * that is in the instruction cache. NB: We flush both caches, just to
- * be sure...
- */
-
- /* note: flushing the icache will clobber EAR0 on the FR451 */
- if (flush_cache)
- gdbstub_purge_cache();
-
- LEDS(0x5666);
-
-} /* end gdbstub() */
-
-/*****************************************************************************/
-/*
- * initialise the GDB stub
- */
-void __init gdbstub_init(void)
-{
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- unsigned char ch;
- int ret;
-#endif
-
- gdbstub_printk("%s", gdbstub_banner);
-
- gdbstub_io_init();
-
- /* try to talk to GDB (or anyone insane enough to want to type GDB protocol by hand) */
- gdbstub_proto("### GDB Tx ACK\n");
- gdbstub_tx_char('+'); /* 'hello world' */
-
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- gdbstub_printk("GDB Stub waiting for packet\n");
-
- /*
- * In case GDB is started before us, ack any packets
- * (presumably "$?#xx") sitting there.
- */
- do { gdbstub_rx_char(&ch, 0); } while (ch != '$');
- do { gdbstub_rx_char(&ch, 0); } while (ch != '#');
- do { ret = gdbstub_rx_char(&ch, 0); } while (ret != 0); /* eat first csum byte */
- do { ret = gdbstub_rx_char(&ch, 0); } while (ret != 0); /* eat second csum byte */
-
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-'); /* nak it */
-
-#else
- gdbstub_printk("GDB Stub set\n");
-#endif
-
-#if 0
- /* send banner */
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(gdbstub_banner, ptr, sizeof(gdbstub_banner) - 1, 0);
- gdbstub_send_packet(output_buffer);
-#endif
-#if defined(CONFIG_GDB_CONSOLE) && defined(CONFIG_GDBSTUB_IMMEDIATE)
- register_console(&gdbstub_console);
-#endif
-
-} /* end gdbstub_init() */
-
-/*****************************************************************************/
-/*
- * register the console at a more appropriate time
- */
-#if defined (CONFIG_GDB_CONSOLE) && !defined(CONFIG_GDBSTUB_IMMEDIATE)
-static int __init gdbstub_postinit(void)
-{
- printk("registering console\n");
- register_console(&gdbstub_console);
- return 0;
-} /* end gdbstub_postinit() */
-
-__initcall(gdbstub_postinit);
-#endif
-
-/*****************************************************************************/
-/*
- * send an exit message to GDB
- */
-void gdbstub_exit(int status)
-{
- unsigned char checksum;
- int count;
- unsigned char ch;
-
- sprintf(output_buffer,"W%02x",status&0xff);
-
- gdbstub_tx_char('$');
- checksum = 0;
- count = 0;
-
- while ((ch = output_buffer[count]) != 0) {
- gdbstub_tx_char(ch);
- checksum += ch;
- count += 1;
- }
-
- gdbstub_tx_char('#');
- gdbstub_tx_char(hex_asc_hi(checksum));
- gdbstub_tx_char(hex_asc_lo(checksum));
-
- /* make sure the output is flushed, or else RedBoot might clobber it */
- gdbstub_tx_char('-');
- gdbstub_tx_flush();
-
-} /* end gdbstub_exit() */
-
-/*****************************************************************************/
-/*
- * GDB wants to call malloc() and free() to allocate memory for calling kernel
- * functions directly from its command line
- */
-static void *malloc(size_t size) __maybe_unused;
-static void *malloc(size_t size)
-{
- return kmalloc(size, GFP_ATOMIC);
-}
-
-static void free(void *p) __maybe_unused;
-static void free(void *p)
-{
- kfree(p);
-}
-
-static uint32_t ___get_HSR0(void) __maybe_unused;
-static uint32_t ___get_HSR0(void)
-{
- return __get_HSR(0);
-}
-
-static uint32_t ___set_HSR0(uint32_t x) __maybe_unused;
-static uint32_t ___set_HSR0(uint32_t x)
-{
- __set_HSR(0, x);
- return __get_HSR(0);
-}
diff --git a/arch/frv/kernel/head-mmu-fr451.S b/arch/frv/kernel/head-mmu-fr451.S
deleted file mode 100644
index 98f87d586e59..000000000000
--- a/arch/frv/kernel/head-mmu-fr451.S
+++ /dev/null
@@ -1,374 +0,0 @@
-/* head-mmu-fr451.S: FR451 mmu-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/mem-layout.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __400_DBR0 0xfe000e00
-#define __400_DBR1 0xfe000e08
-#define __400_DBR2 0xfe000e10
-#define __400_DBR3 0xfe000e18
-#define __400_DAM0 0xfe000f00
-#define __400_DAM1 0xfe000f08
-#define __400_DAM2 0xfe000f10
-#define __400_DAM3 0xfe000f18
-#define __400_LGCR 0xfe000010
-#define __400_LCR 0xfe000100
-#define __400_LSBR 0xfe000c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# describe the position and layout of the SDRAM controller registers
-#
-# ENTRY: EXIT:
-# GR5 - cacheline size
-# GR11 - displacement of 2nd SDRAM addr reg from GR14
-# GR12 - displacement of 3rd SDRAM addr reg from GR14
-# GR13 - displacement of 4th SDRAM addr reg from GR14
-# GR14 - address of 1st SDRAM addr reg
-# GR15 - amount to shift address by to match SDRAM addr reg
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-# CC0 - T if DBR0 is present
-# CC1 - T if DBR1 is present
-# CC2 - T if DBR2 is present
-# CC3 - T if DBR3 is present
-#
-###############################################################################
- .globl __head_fr451_describe_sdram
-__head_fr451_describe_sdram:
- sethi.p %hi(__400_DBR0),gr14
- setlo %lo(__400_DBR0),gr14
- setlos.p #__400_DBR1-__400_DBR0,gr11
- setlos #__400_DBR2-__400_DBR0,gr12
- setlos.p #__400_DBR3-__400_DBR0,gr13
- setlos #32,gr5 ; cacheline size
- setlos.p #0,gr15 ; amount to shift addr reg by
- setlos #0x00ff,gr4
- movgs gr4,cccr ; extant DARS/DAMK regs
- bralr
-
-###############################################################################
-#
-# rearrange the bus controller registers
-#
-# ENTRY: EXIT:
-# GR26 &__head_reference [saved]
-# GR30 LED address revised LED address
-#
-###############################################################################
- .globl __head_fr451_set_busctl
-__head_fr451_set_busctl:
- sethi.p %hi(__400_LGCR),gr4
- setlo %lo(__400_LGCR),gr4
- sethi.p %hi(__400_LSBR),gr10
- setlo %lo(__400_LSBR),gr10
- sethi.p %hi(__400_LCR),gr11
- setlo %lo(__400_LCR),gr11
-
- # set the bus controller
- ldi @(gr4,#0),gr5
- ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
- sti gr5,@(gr4,#0)
-
- sethi.p %hi(__region_CS1),gr4
- setlo %lo(__region_CS1),gr4
- sethi.p %hi(__region_CS1_M),gr5
- setlo %lo(__region_CS1_M),gr5
- sethi.p %hi(__region_CS1_C),gr6
- setlo %lo(__region_CS1_C),gr6
- sti gr4,@(gr10,#1*0x08)
- sti gr5,@(gr10,#1*0x08+0x100)
- sti gr6,@(gr11,#1*0x08)
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- sethi.p %hi(__region_CS2_M),gr5
- setlo %lo(__region_CS2_M),gr5
- sethi.p %hi(__region_CS2_C),gr6
- setlo %lo(__region_CS2_C),gr6
- sti gr4,@(gr10,#2*0x08)
- sti gr5,@(gr10,#2*0x08+0x100)
- sti gr6,@(gr11,#2*0x08)
- sethi.p %hi(__region_CS3),gr4
- setlo %lo(__region_CS3),gr4
- sethi.p %hi(__region_CS3_M),gr5
- setlo %lo(__region_CS3_M),gr5
- sethi.p %hi(__region_CS3_C),gr6
- setlo %lo(__region_CS3_C),gr6
- sti gr4,@(gr10,#3*0x08)
- sti gr5,@(gr10,#3*0x08+0x100)
- sti gr6,@(gr11,#3*0x08)
- sethi.p %hi(__region_CS4),gr4
- setlo %lo(__region_CS4),gr4
- sethi.p %hi(__region_CS4_M),gr5
- setlo %lo(__region_CS4_M),gr5
- sethi.p %hi(__region_CS4_C),gr6
- setlo %lo(__region_CS4_C),gr6
- sti gr4,@(gr10,#4*0x08)
- sti gr5,@(gr10,#4*0x08+0x100)
- sti gr6,@(gr11,#4*0x08)
- sethi.p %hi(__region_CS5),gr4
- setlo %lo(__region_CS5),gr4
- sethi.p %hi(__region_CS5_M),gr5
- setlo %lo(__region_CS5_M),gr5
- sethi.p %hi(__region_CS5_C),gr6
- setlo %lo(__region_CS5_C),gr6
- sti gr4,@(gr10,#5*0x08)
- sti gr5,@(gr10,#5*0x08+0x100)
- sti gr6,@(gr11,#5*0x08)
- sethi.p %hi(__region_CS6),gr4
- setlo %lo(__region_CS6),gr4
- sethi.p %hi(__region_CS6_M),gr5
- setlo %lo(__region_CS6_M),gr5
- sethi.p %hi(__region_CS6_C),gr6
- setlo %lo(__region_CS6_C),gr6
- sti gr4,@(gr10,#6*0x08)
- sti gr5,@(gr10,#6*0x08+0x100)
- sti gr6,@(gr11,#6*0x08)
- sethi.p %hi(__region_CS7),gr4
- setlo %lo(__region_CS7),gr4
- sethi.p %hi(__region_CS7_M),gr5
- setlo %lo(__region_CS7_M),gr5
- sethi.p %hi(__region_CS7_C),gr6
- setlo %lo(__region_CS7_C),gr6
- sti gr4,@(gr10,#7*0x08)
- sti gr5,@(gr10,#7*0x08+0x100)
- sti gr6,@(gr11,#7*0x08)
- membar
- bar
-
- # adjust LED bank address
-#ifdef CONFIG_MB93091_VDK
- sethi.p %hi(__region_CS2 + 0x01200004),gr30
- setlo %lo(__region_CS2 + 0x01200004),gr30
-#endif
- bralr
-
-###############################################################################
-#
-# determine the total SDRAM size
-#
-# ENTRY: EXIT:
-# GR25 - SDRAM size
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr451_survey_sdram
-__head_fr451_survey_sdram:
- sethi.p %hi(__400_DAM0),gr11
- setlo %lo(__400_DAM0),gr11
- sethi.p %hi(__400_DBR0),gr12
- setlo %lo(__400_DBR0),gr12
-
- sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
- setlo %lo(0xfe000000),gr17
- setlos #0,gr25
-
- ldi @(gr12,#0x00),gr4 ; DAR0
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS0
- ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS0:
-
- ldi @(gr12,#0x08),gr4 ; DAR1
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS1
- ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS1:
-
- ldi @(gr12,#0x10),gr4 ; DAR2
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS2
- ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS2:
-
- ldi @(gr12,#0x18),gr4 ; DAR3
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS3
- ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS3:
- bralr
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size [saved]
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-#
-# Using this map:
-# REGISTERS ADDRESS RANGE VIEW
-# =============== ====================== ===============================
-# IAMPR0/DAMPR0 0xC0000000-0xCFFFFFFF Cached kernel RAM Window
-# DAMPR11 0xE0000000-0xFFFFFFFF Uncached I/O
-#
-###############################################################################
- .globl __head_fr451_set_protection
-__head_fr451_set_protection:
- movsg lr,gr27
-
- # set the I/O region protection registers for FR451 in MMU mode
-#define PGPROT_IO xAMPRx_L|xAMPRx_M|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V
-
- sethi.p %hi(__region_IO),gr5
- setlo %lo(__region_IO),gr5
- setlos #PGPROT_IO|xAMPRx_SS_512Mb,gr4
- or gr4,gr5,gr4
- movgs gr5,damlr11 ; General I/O tile
- movgs gr4,dampr11
-
- # need to open a window onto at least part of the RAM for the kernel's use
- sethi.p %hi(__sdram_base),gr8
- setlo %lo(__sdram_base),gr8 ; physical address
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9 ; virtual address
-
- setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr11
- or gr8,gr11,gr8
-
- movgs gr9,iamlr0 ; mapped from real address 0
- movgs gr8,iampr0 ; cached kernel memory at 0xC0000000
- movgs gr9,damlr0
- movgs gr8,dampr0
-
- # set a temporary mapping for the kernel running at address 0 until we've turned on the MMU
- sethi.p %hi(__sdram_base),gr9
- setlo %lo(__sdram_base),gr9 ; virtual address
-
- and.p gr4,gr11,gr4
- and gr5,gr11,gr5
- or.p gr4,gr11,gr4
- or gr5,gr11,gr5
-
- movgs gr9,iamlr1 ; mapped from real address 0
- movgs gr8,iampr1 ; cached kernel memory at 0x00000000
- movgs gr9,damlr1
- movgs gr8,dampr1
-
- # we use DAMR2-10 for kmap_atomic(), cache flush and TLB management
- # since the DAMLR regs are not going to change, we can set them now
- # also set up IAMLR2 to the same as DAMLR5
- sethi.p %hi(KMAP_ATOMIC_PRIMARY_FRAME),gr4
- setlo %lo(KMAP_ATOMIC_PRIMARY_FRAME),gr4
- sethi.p %hi(PAGE_SIZE),gr5
- setlo %lo(PAGE_SIZE),gr5
-
- movgs gr4,damlr2
- movgs gr4,iamlr2
- add gr4,gr5,gr4
- movgs gr4,damlr3
- add gr4,gr5,gr4
- movgs gr4,damlr4
- add gr4,gr5,gr4
- movgs gr4,damlr5
- add gr4,gr5,gr4
- movgs gr4,damlr6
- add gr4,gr5,gr4
- movgs gr4,damlr7
- add gr4,gr5,gr4
- movgs gr4,damlr8
- add gr4,gr5,gr4
- movgs gr4,damlr9
- add gr4,gr5,gr4
- movgs gr4,damlr10
-
- movgs gr0,dampr2
- movgs gr0,dampr4
- movgs gr0,dampr5
- movgs gr0,dampr6
- movgs gr0,dampr7
- movgs gr0,dampr8
- movgs gr0,dampr9
- movgs gr0,dampr10
-
- movgs gr0,iamlr3
- movgs gr0,iamlr4
- movgs gr0,iamlr5
- movgs gr0,iamlr6
- movgs gr0,iamlr7
-
- movgs gr0,iampr2
- movgs gr0,iampr3
- movgs gr0,iampr4
- movgs gr0,iampr5
- movgs gr0,iampr6
- movgs gr0,iampr7
-
- # start in TLB context 0 with the swapper's page tables
- movgs gr0,cxnr
-
- sethi.p %hi(swapper_pg_dir),gr4
- setlo %lo(swapper_pg_dir),gr4
- sethi.p %hi(__page_offset),gr5
- setlo %lo(__page_offset),gr5
- sub gr4,gr5,gr4
- movgs gr4,ttbr
- setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5
- or gr4,gr5,gr4
- movgs gr4,dampr3
-
- # the FR451 also has an extra trap base register
- movsg tbr,gr4
- movgs gr4,btbr
-
- LEDS 0x3300
- jmpl @(gr27,gr0)
-
-###############################################################################
-#
-# finish setting up the protection registers
-#
-###############################################################################
- .globl __head_fr451_finalise_protection
-__head_fr451_finalise_protection:
- # turn on the timers as appropriate
- movgs gr0,timerh
- movgs gr0,timerl
- movgs gr0,timerd
- movsg hsr0,gr4
- sethi.p %hi(HSR0_ETMI),gr5
- setlo %lo(HSR0_ETMI),gr5
- or gr4,gr5,gr4
- movgs gr4,hsr0
-
- # clear the TLB entry cache
- movgs gr0,iamlr1
- movgs gr0,iampr1
- movgs gr0,damlr1
- movgs gr0,dampr1
-
- # clear the PGE cache
- sethi.p %hi(__flush_tlb_all),gr4
- setlo %lo(__flush_tlb_all),gr4
- jmpl @(gr4,gr0)
diff --git a/arch/frv/kernel/head-uc-fr401.S b/arch/frv/kernel/head-uc-fr401.S
deleted file mode 100644
index 438643cfa38e..000000000000
--- a/arch/frv/kernel/head-uc-fr401.S
+++ /dev/null
@@ -1,311 +0,0 @@
-/* head-uc-fr401.S: FR401/3/5 uc-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __400_DBR0 0xfe000e00
-#define __400_DBR1 0xfe000e08
-#define __400_DBR2 0xfe000e10 /* not on FR401 */
-#define __400_DBR3 0xfe000e18 /* not on FR401 */
-#define __400_DAM0 0xfe000f00
-#define __400_DAM1 0xfe000f08
-#define __400_DAM2 0xfe000f10 /* not on FR401 */
-#define __400_DAM3 0xfe000f18 /* not on FR401 */
-#define __400_LGCR 0xfe000010
-#define __400_LCR 0xfe000100
-#define __400_LSBR 0xfe000c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# describe the position and layout of the SDRAM controller registers
-#
-# ENTRY: EXIT:
-# GR5 - cacheline size
-# GR11 - displacement of 2nd SDRAM addr reg from GR14
-# GR12 - displacement of 3rd SDRAM addr reg from GR14
-# GR13 - displacement of 4th SDRAM addr reg from GR14
-# GR14 - address of 1st SDRAM addr reg
-# GR15 - amount to shift address by to match SDRAM addr reg
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-# CC0 - T if DBR0 is present
-# CC1 - T if DBR1 is present
-# CC2 - T if DBR2 is present (not FR401/FR401A)
-# CC3 - T if DBR3 is present (not FR401/FR401A)
-#
-###############################################################################
- .globl __head_fr401_describe_sdram
-__head_fr401_describe_sdram:
- sethi.p %hi(__400_DBR0),gr14
- setlo %lo(__400_DBR0),gr14
- setlos.p #__400_DBR1-__400_DBR0,gr11
- setlos #__400_DBR2-__400_DBR0,gr12
- setlos.p #__400_DBR3-__400_DBR0,gr13
- setlos #32,gr5 ; cacheline size
- setlos.p #0,gr15 ; amount to shift addr reg by
-
- # specify which DBR regs are present
- setlos #0x00ff,gr4
- movgs gr4,cccr
- movsg psr,gr3 ; check for FR401/FR401A
- srli gr3,#25,gr3
- subicc gr3,#0x20>>1,gr0,icc0
- bnelr icc0,#1
- setlos #0x000f,gr4
- movgs gr4,cccr
- bralr
-
-###############################################################################
-#
-# rearrange the bus controller registers
-#
-# ENTRY: EXIT:
-# GR26 &__head_reference [saved]
-# GR30 LED address revised LED address
-#
-###############################################################################
- .globl __head_fr401_set_busctl
-__head_fr401_set_busctl:
- sethi.p %hi(__400_LGCR),gr4
- setlo %lo(__400_LGCR),gr4
- sethi.p %hi(__400_LSBR),gr10
- setlo %lo(__400_LSBR),gr10
- sethi.p %hi(__400_LCR),gr11
- setlo %lo(__400_LCR),gr11
-
- # set the bus controller
- ldi @(gr4,#0),gr5
- ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
- sti gr5,@(gr4,#0)
-
- sethi.p %hi(__region_CS1),gr4
- setlo %lo(__region_CS1),gr4
- sethi.p %hi(__region_CS1_M),gr5
- setlo %lo(__region_CS1_M),gr5
- sethi.p %hi(__region_CS1_C),gr6
- setlo %lo(__region_CS1_C),gr6
- sti gr4,@(gr10,#1*0x08)
- sti gr5,@(gr10,#1*0x08+0x100)
- sti gr6,@(gr11,#1*0x08)
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- sethi.p %hi(__region_CS2_M),gr5
- setlo %lo(__region_CS2_M),gr5
- sethi.p %hi(__region_CS2_C),gr6
- setlo %lo(__region_CS2_C),gr6
- sti gr4,@(gr10,#2*0x08)
- sti gr5,@(gr10,#2*0x08+0x100)
- sti gr6,@(gr11,#2*0x08)
- sethi.p %hi(__region_CS3),gr4
- setlo %lo(__region_CS3),gr4
- sethi.p %hi(__region_CS3_M),gr5
- setlo %lo(__region_CS3_M),gr5
- sethi.p %hi(__region_CS3_C),gr6
- setlo %lo(__region_CS3_C),gr6
- sti gr4,@(gr10,#3*0x08)
- sti gr5,@(gr10,#3*0x08+0x100)
- sti gr6,@(gr11,#3*0x08)
- sethi.p %hi(__region_CS4),gr4
- setlo %lo(__region_CS4),gr4
- sethi.p %hi(__region_CS4_M),gr5
- setlo %lo(__region_CS4_M),gr5
- sethi.p %hi(__region_CS4_C),gr6
- setlo %lo(__region_CS4_C),gr6
- sti gr4,@(gr10,#4*0x08)
- sti gr5,@(gr10,#4*0x08+0x100)
- sti gr6,@(gr11,#4*0x08)
- sethi.p %hi(__region_CS5),gr4
- setlo %lo(__region_CS5),gr4
- sethi.p %hi(__region_CS5_M),gr5
- setlo %lo(__region_CS5_M),gr5
- sethi.p %hi(__region_CS5_C),gr6
- setlo %lo(__region_CS5_C),gr6
- sti gr4,@(gr10,#5*0x08)
- sti gr5,@(gr10,#5*0x08+0x100)
- sti gr6,@(gr11,#5*0x08)
- sethi.p %hi(__region_CS6),gr4
- setlo %lo(__region_CS6),gr4
- sethi.p %hi(__region_CS6_M),gr5
- setlo %lo(__region_CS6_M),gr5
- sethi.p %hi(__region_CS6_C),gr6
- setlo %lo(__region_CS6_C),gr6
- sti gr4,@(gr10,#6*0x08)
- sti gr5,@(gr10,#6*0x08+0x100)
- sti gr6,@(gr11,#6*0x08)
- sethi.p %hi(__region_CS7),gr4
- setlo %lo(__region_CS7),gr4
- sethi.p %hi(__region_CS7_M),gr5
- setlo %lo(__region_CS7_M),gr5
- sethi.p %hi(__region_CS7_C),gr6
- setlo %lo(__region_CS7_C),gr6
- sti gr4,@(gr10,#7*0x08)
- sti gr5,@(gr10,#7*0x08+0x100)
- sti gr6,@(gr11,#7*0x08)
- membar
- bar
-
- # adjust LED bank address
- sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
- setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
- bralr
-
-###############################################################################
-#
-# determine the total SDRAM size
-#
-# ENTRY: EXIT:
-# GR25 - SDRAM size
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr401_survey_sdram
-__head_fr401_survey_sdram:
- sethi.p %hi(__400_DAM0),gr11
- setlo %lo(__400_DAM0),gr11
- sethi.p %hi(__400_DBR0),gr12
- setlo %lo(__400_DBR0),gr12
-
- sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
- setlo %lo(0xfe000000),gr17
- setlos #0,gr25
-
- ldi @(gr12,#0x00),gr4 ; DAR0
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS0
- ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS0:
-
- ldi @(gr12,#0x08),gr4 ; DAR1
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS1
- ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS1:
-
- # FR401/FR401A does not have DCS2/3
- movsg psr,gr3
- srli gr3,#25,gr3
- subicc gr3,#0x20>>1,gr0,icc0
- beq icc0,#0,__head_no_DCS3
-
- ldi @(gr12,#0x10),gr4 ; DAR2
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS2
- ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS2:
-
- ldi @(gr12,#0x18),gr4 ; DAR3
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS3
- ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS3:
- bralr
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size [saved]
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr401_set_protection
-__head_fr401_set_protection:
- movsg lr,gr27
-
- # set the I/O region protection registers for FR401/3/5
- sethi.p %hi(__region_IO),gr5
- setlo %lo(__region_IO),gr5
- ori gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
- movgs gr0,iampr7
- movgs gr5,dampr7 ; General I/O tile
-
- # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
- # - start with the highest numbered registers
- sethi.p %hi(__kernel_image_end),gr8
- setlo %lo(__kernel_image_end),gr8
- sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
- setlo %lo(32768),gr4
- add gr8,gr4,gr8
- sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
- setlo %lo(1024*2048-1),gr4
- add.p gr8,gr4,gr8
- not gr4,gr4
- and gr8,gr4,gr8
-
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9
- add gr9,gr25,gr9
-
- # GR8 = base of uncovered RAM
- # GR9 = top of uncovered RAM
-
-#ifdef CONFIG_MB93093_PDK
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- ori gr4,#xAMPRx_SS_1Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr4
- movgs gr4,dampr6
- movgs gr0,iampr6
-#else
- call __head_split_region
- movgs gr4,iampr6
- movgs gr5,dampr6
-#endif
- call __head_split_region
- movgs gr4,iampr5
- movgs gr5,dampr5
- call __head_split_region
- movgs gr4,iampr4
- movgs gr5,dampr4
- call __head_split_region
- movgs gr4,iampr3
- movgs gr5,dampr3
- call __head_split_region
- movgs gr4,iampr2
- movgs gr5,dampr2
- call __head_split_region
- movgs gr4,iampr1
- movgs gr5,dampr1
-
- # cover kernel core image with kernel-only segment
- sethi.p %hi(__page_offset),gr8
- setlo %lo(__page_offset),gr8
- call __head_split_region
-
-#ifdef CONFIG_PROTECT_KERNEL
- ori.p gr4,#xAMPRx_S_KERNEL,gr4
- ori gr5,#xAMPRx_S_KERNEL,gr5
-#endif
-
- movgs gr4,iampr0
- movgs gr5,dampr0
- jmpl @(gr27,gr0)
diff --git a/arch/frv/kernel/head-uc-fr451.S b/arch/frv/kernel/head-uc-fr451.S
deleted file mode 100644
index b2a76c4a1786..000000000000
--- a/arch/frv/kernel/head-uc-fr451.S
+++ /dev/null
@@ -1,174 +0,0 @@
-/* head-uc-fr451.S: FR451 uc-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __400_DBR0 0xfe000e00
-#define __400_DBR1 0xfe000e08
-#define __400_DBR2 0xfe000e10
-#define __400_DBR3 0xfe000e18
-#define __400_DAM0 0xfe000f00
-#define __400_DAM1 0xfe000f08
-#define __400_DAM2 0xfe000f10
-#define __400_DAM3 0xfe000f18
-#define __400_LGCR 0xfe000010
-#define __400_LCR 0xfe000100
-#define __400_LSBR 0xfe000c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size [saved]
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr451_set_protection
-__head_fr451_set_protection:
- movsg lr,gr27
-
- movgs gr0,dampr10
- movgs gr0,damlr10
- movgs gr0,dampr9
- movgs gr0,damlr9
- movgs gr0,dampr8
- movgs gr0,damlr8
-
- # set the I/O region protection registers for FR401/3/5
- sethi.p %hi(__region_IO),gr5
- setlo %lo(__region_IO),gr5
- sethi.p %hi(0x1fffffff),gr7
- setlo %lo(0x1fffffff),gr7
- ori gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
- movgs gr5,dampr11 ; General I/O tile
- movgs gr7,damlr11
-
- # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
- # - start with the highest numbered registers
- sethi.p %hi(__kernel_image_end),gr8
- setlo %lo(__kernel_image_end),gr8
- sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
- setlo %lo(32768),gr4
- add gr8,gr4,gr8
- sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
- setlo %lo(1024*2048-1),gr4
- add.p gr8,gr4,gr8
- not gr4,gr4
- and gr8,gr4,gr8
-
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9
- add gr9,gr25,gr9
-
- sethi.p %hi(0xffffc000),gr11
- setlo %lo(0xffffc000),gr11
-
- # GR8 = base of uncovered RAM
- # GR9 = top of uncovered RAM
- # GR11 = xAMLR mask
- LEDS 0x3317
- call __head_split_region
- movgs gr4,iampr7
- movgs gr6,iamlr7
- movgs gr5,dampr7
- movgs gr7,damlr7
-
- LEDS 0x3316
- call __head_split_region
- movgs gr4,iampr6
- movgs gr6,iamlr6
- movgs gr5,dampr6
- movgs gr7,damlr6
-
- LEDS 0x3315
- call __head_split_region
- movgs gr4,iampr5
- movgs gr6,iamlr5
- movgs gr5,dampr5
- movgs gr7,damlr5
-
- LEDS 0x3314
- call __head_split_region
- movgs gr4,iampr4
- movgs gr6,iamlr4
- movgs gr5,dampr4
- movgs gr7,damlr4
-
- LEDS 0x3313
- call __head_split_region
- movgs gr4,iampr3
- movgs gr6,iamlr3
- movgs gr5,dampr3
- movgs gr7,damlr3
-
- LEDS 0x3312
- call __head_split_region
- movgs gr4,iampr2
- movgs gr6,iamlr2
- movgs gr5,dampr2
- movgs gr7,damlr2
-
- LEDS 0x3311
- call __head_split_region
- movgs gr4,iampr1
- movgs gr6,iamlr1
- movgs gr5,dampr1
- movgs gr7,damlr1
-
- # cover kernel core image with kernel-only segment
- LEDS 0x3310
- sethi.p %hi(__page_offset),gr8
- setlo %lo(__page_offset),gr8
- call __head_split_region
-
-#ifdef CONFIG_PROTECT_KERNEL
- ori.p gr4,#xAMPRx_S_KERNEL,gr4
- ori gr5,#xAMPRx_S_KERNEL,gr5
-#endif
-
- movgs gr4,iampr0
- movgs gr6,iamlr0
- movgs gr5,dampr0
- movgs gr7,damlr0
-
- # start in TLB context 0 with no page tables
- movgs gr0,cxnr
- movgs gr0,ttbr
-
- # the FR451 also has an extra trap base register
- movsg tbr,gr4
- movgs gr4,btbr
-
- # turn on the timers as appropriate
- movgs gr0,timerh
- movgs gr0,timerl
- movgs gr0,timerd
- movsg hsr0,gr4
- sethi.p %hi(HSR0_ETMI),gr5
- setlo %lo(HSR0_ETMI),gr5
- or gr4,gr5,gr4
- movgs gr4,hsr0
-
- LEDS 0x3300
- jmpl @(gr27,gr0)
diff --git a/arch/frv/kernel/head-uc-fr555.S b/arch/frv/kernel/head-uc-fr555.S
deleted file mode 100644
index 5497aaf34f77..000000000000
--- a/arch/frv/kernel/head-uc-fr555.S
+++ /dev/null
@@ -1,347 +0,0 @@
-/* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __551_DARS0 0xfeff0100
-#define __551_DARS1 0xfeff0104
-#define __551_DARS2 0xfeff0108
-#define __551_DARS3 0xfeff010c
-#define __551_DAMK0 0xfeff0110
-#define __551_DAMK1 0xfeff0114
-#define __551_DAMK2 0xfeff0118
-#define __551_DAMK3 0xfeff011c
-#define __551_LCR 0xfeff1100
-#define __551_LSBR 0xfeff1c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# describe the position and layout of the SDRAM controller registers
-#
-# ENTRY: EXIT:
-# GR5 - cacheline size
-# GR11 - displacement of 2nd SDRAM addr reg from GR14
-# GR12 - displacement of 3rd SDRAM addr reg from GR14
-# GR13 - displacement of 4th SDRAM addr reg from GR14
-# GR14 - address of 1st SDRAM addr reg
-# GR15 - amount to shift address by to match SDRAM addr reg
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-# CC0 - T if DARS0 is present
-# CC1 - T if DARS1 is present
-# CC2 - T if DARS2 is present
-# CC3 - T if DARS3 is present
-#
-###############################################################################
- .globl __head_fr555_describe_sdram
-__head_fr555_describe_sdram:
- sethi.p %hi(__551_DARS0),gr14
- setlo %lo(__551_DARS0),gr14
- setlos.p #__551_DARS1-__551_DARS0,gr11
- setlos #__551_DARS2-__551_DARS0,gr12
- setlos.p #__551_DARS3-__551_DARS0,gr13
- setlos #64,gr5 ; cacheline size
- setlos #20,gr15 ; amount to shift addr by
- setlos #0x00ff,gr4
- movgs gr4,cccr ; extant DARS/DAMK regs
- bralr
-
-###############################################################################
-#
-# rearrange the bus controller registers
-#
-# ENTRY: EXIT:
-# GR26 &__head_reference [saved]
-# GR30 LED address revised LED address
-#
-###############################################################################
- .globl __head_fr555_set_busctl
-__head_fr555_set_busctl:
- LEDS 0x100f
- sethi.p %hi(__551_LSBR),gr10
- setlo %lo(__551_LSBR),gr10
- sethi.p %hi(__551_LCR),gr11
- setlo %lo(__551_LCR),gr11
-
- # set the bus controller
- sethi.p %hi(__region_CS1),gr4
- setlo %lo(__region_CS1),gr4
- sethi.p %hi(__region_CS1_M),gr5
- setlo %lo(__region_CS1_M),gr5
- sethi.p %hi(__region_CS1_C),gr6
- setlo %lo(__region_CS1_C),gr6
- sti gr4,@(gr10,#1*0x08)
- sti gr5,@(gr10,#1*0x08+0x100)
- sti gr6,@(gr11,#1*0x08)
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- sethi.p %hi(__region_CS2_M),gr5
- setlo %lo(__region_CS2_M),gr5
- sethi.p %hi(__region_CS2_C),gr6
- setlo %lo(__region_CS2_C),gr6
- sti gr4,@(gr10,#2*0x08)
- sti gr5,@(gr10,#2*0x08+0x100)
- sti gr6,@(gr11,#2*0x08)
- sethi.p %hi(__region_CS3),gr4
- setlo %lo(__region_CS3),gr4
- sethi.p %hi(__region_CS3_M),gr5
- setlo %lo(__region_CS3_M),gr5
- sethi.p %hi(__region_CS3_C),gr6
- setlo %lo(__region_CS3_C),gr6
- sti gr4,@(gr10,#3*0x08)
- sti gr5,@(gr10,#3*0x08+0x100)
- sti gr6,@(gr11,#3*0x08)
- sethi.p %hi(__region_CS4),gr4
- setlo %lo(__region_CS4),gr4
- sethi.p %hi(__region_CS4_M),gr5
- setlo %lo(__region_CS4_M),gr5
- sethi.p %hi(__region_CS4_C),gr6
- setlo %lo(__region_CS4_C),gr6
- sti gr4,@(gr10,#4*0x08)
- sti gr5,@(gr10,#4*0x08+0x100)
- sti gr6,@(gr11,#4*0x08)
- sethi.p %hi(__region_CS5),gr4
- setlo %lo(__region_CS5),gr4
- sethi.p %hi(__region_CS5_M),gr5
- setlo %lo(__region_CS5_M),gr5
- sethi.p %hi(__region_CS5_C),gr6
- setlo %lo(__region_CS5_C),gr6
- sti gr4,@(gr10,#5*0x08)
- sti gr5,@(gr10,#5*0x08+0x100)
- sti gr6,@(gr11,#5*0x08)
- sethi.p %hi(__region_CS6),gr4
- setlo %lo(__region_CS6),gr4
- sethi.p %hi(__region_CS6_M),gr5
- setlo %lo(__region_CS6_M),gr5
- sethi.p %hi(__region_CS6_C),gr6
- setlo %lo(__region_CS6_C),gr6
- sti gr4,@(gr10,#6*0x08)
- sti gr5,@(gr10,#6*0x08+0x100)
- sti gr6,@(gr11,#6*0x08)
- sethi.p %hi(__region_CS7),gr4
- setlo %lo(__region_CS7),gr4
- sethi.p %hi(__region_CS7_M),gr5
- setlo %lo(__region_CS7_M),gr5
- sethi.p %hi(__region_CS7_C),gr6
- setlo %lo(__region_CS7_C),gr6
- sti gr4,@(gr10,#7*0x08)
- sti gr5,@(gr10,#7*0x08+0x100)
- sti gr6,@(gr11,#7*0x08)
- membar
- bar
-
- # adjust LED bank address
-#ifdef CONFIG_MB93091_VDK
- sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
- setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
-#endif
- bralr
-
-###############################################################################
-#
-# determine the total SDRAM size
-#
-# ENTRY: EXIT:
-# GR25 - SDRAM size
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr555_survey_sdram
-__head_fr555_survey_sdram:
- sethi.p %hi(__551_DAMK0),gr11
- setlo %lo(__551_DAMK0),gr11
- sethi.p %hi(__551_DARS0),gr12
- setlo %lo(__551_DARS0),gr12
-
- sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
- setlo %lo(0xfff),gr17
- setlos #0,gr25
-
- ldi @(gr11,#0x00),gr6 ; DAMK0: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS0
- ldi @(gr12,#0x00),gr4 ; DARS0
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS0:
-
- ldi @(gr11,#0x04),gr6 ; DAMK1: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS1
- ldi @(gr12,#0x04),gr4 ; DARS1
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS1:
-
- ldi @(gr11,#0x8),gr6 ; DAMK2: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS2
- ldi @(gr12,#0x8),gr4 ; DARS2
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS2:
-
- ldi @(gr11,#0xc),gr6 ; DAMK3: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS3
- ldi @(gr12,#0xc),gr4 ; DARS3
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS3:
-
- slli gr25,#20,gr25 ; shift [11:0] -> [31:20]
- bralr
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size saved
-# GR30 LED address saved
-#
-###############################################################################
- .globl __head_fr555_set_protection
-__head_fr555_set_protection:
- movsg lr,gr27
-
- sethi.p %hi(0xfff00000),gr11
- setlo %lo(0xfff00000),gr11
-
- # set the I/O region protection registers for FR555
- sethi.p %hi(__region_IO),gr7
- setlo %lo(__region_IO),gr7
- ori gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
- movgs gr0,iampr15
- movgs gr0,iamlr15
- movgs gr5,dampr15
- movgs gr7,damlr15
-
- # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
- # - start with the highest numbered registers
- sethi.p %hi(__kernel_image_end),gr8
- setlo %lo(__kernel_image_end),gr8
- sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
- setlo %lo(32768),gr4
- add gr8,gr4,gr8
- sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
- setlo %lo(1024*2048-1),gr4
- add.p gr8,gr4,gr8
- not gr4,gr4
- and gr8,gr4,gr8
-
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9
- add gr9,gr25,gr9
-
- # GR8 = base of uncovered RAM
- # GR9 = top of uncovered RAM
- # GR11 - mask for DAMLR/IAMLR regs
- #
- call __head_split_region
- movgs gr4,iampr14
- movgs gr6,iamlr14
- movgs gr5,dampr14
- movgs gr7,damlr14
- call __head_split_region
- movgs gr4,iampr13
- movgs gr6,iamlr13
- movgs gr5,dampr13
- movgs gr7,damlr13
- call __head_split_region
- movgs gr4,iampr12
- movgs gr6,iamlr12
- movgs gr5,dampr12
- movgs gr7,damlr12
- call __head_split_region
- movgs gr4,iampr11
- movgs gr6,iamlr11
- movgs gr5,dampr11
- movgs gr7,damlr11
- call __head_split_region
- movgs gr4,iampr10
- movgs gr6,iamlr10
- movgs gr5,dampr10
- movgs gr7,damlr10
- call __head_split_region
- movgs gr4,iampr9
- movgs gr6,iamlr9
- movgs gr5,dampr9
- movgs gr7,damlr9
- call __head_split_region
- movgs gr4,iampr8
- movgs gr6,iamlr8
- movgs gr5,dampr8
- movgs gr7,damlr8
-
- call __head_split_region
- movgs gr4,iampr7
- movgs gr6,iamlr7
- movgs gr5,dampr7
- movgs gr7,damlr7
- call __head_split_region
- movgs gr4,iampr6
- movgs gr6,iamlr6
- movgs gr5,dampr6
- movgs gr7,damlr6
- call __head_split_region
- movgs gr4,iampr5
- movgs gr6,iamlr5
- movgs gr5,dampr5
- movgs gr7,damlr5
- call __head_split_region
- movgs gr4,iampr4
- movgs gr6,iamlr4
- movgs gr5,dampr4
- movgs gr7,damlr4
- call __head_split_region
- movgs gr4,iampr3
- movgs gr6,iamlr3
- movgs gr5,dampr3
- movgs gr7,damlr3
- call __head_split_region
- movgs gr4,iampr2
- movgs gr6,iamlr2
- movgs gr5,dampr2
- movgs gr7,damlr2
- call __head_split_region
- movgs gr4,iampr1
- movgs gr6,iamlr1
- movgs gr5,dampr1
- movgs gr7,damlr1
-
- # cover kernel core image with kernel-only segment
- sethi.p %hi(__page_offset),gr8
- setlo %lo(__page_offset),gr8
- call __head_split_region
-
-#ifdef CONFIG_PROTECT_KERNEL
- ori.p gr4,#xAMPRx_S_KERNEL,gr4
- ori gr5,#xAMPRx_S_KERNEL,gr5
-#endif
-
- movgs gr4,iampr0
- movgs gr6,iamlr0
- movgs gr5,dampr0
- movgs gr7,damlr0
- jmpl @(gr27,gr0)
diff --git a/arch/frv/kernel/head.S b/arch/frv/kernel/head.S
deleted file mode 100644
index a7d0bea9c036..000000000000
--- a/arch/frv/kernel/head.S
+++ /dev/null
@@ -1,638 +0,0 @@
-/* head.S: kernel entry point for FR-V kernel
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include <asm/cache.h>
-#include "head.inc"
-
-###############################################################################
-#
-# void _boot(unsigned long magic, char *command_line) __attribute__((noreturn))
-#
-# - if magic is 0xdead1eaf, then command_line is assumed to point to the kernel
-# command line string
-#
-###############################################################################
- __HEAD
- .balign 4
-
- .globl _boot, __head_reference
- .type _boot,@function
-_boot:
-__head_reference:
- sethi.p %hi(LED_ADDR),gr30
- setlo %lo(LED_ADDR),gr30
-
- LEDS 0x0000
-
- # calculate reference address for PC-relative stuff
- call 0f
-0: movsg lr,gr26
- addi gr26,#__head_reference-0b,gr26
-
- # invalidate and disable both of the caches and turn off the memory access checking
- dcef @(gr0,gr0),1
- bar
-
- sethi.p %hi(~(HSR0_ICE|HSR0_DCE|HSR0_CBM|HSR0_EIMMU|HSR0_EDMMU)),gr4
- setlo %lo(~(HSR0_ICE|HSR0_DCE|HSR0_CBM|HSR0_EIMMU|HSR0_EDMMU)),gr4
- movsg hsr0,gr5
- and gr4,gr5,gr5
- movgs gr5,hsr0
- movsg hsr0,gr5
-
- LEDS 0x0001
-
- icei @(gr0,gr0),1
- dcei @(gr0,gr0),1
- bar
-
- # turn the instruction cache back on
- sethi.p %hi(HSR0_ICE),gr4
- setlo %lo(HSR0_ICE),gr4
- movsg hsr0,gr5
- or gr4,gr5,gr5
- movgs gr5,hsr0
- movsg hsr0,gr5
-
- bar
-
- LEDS 0x0002
-
- # retrieve the parameters (including command line) before we overwrite them
- sethi.p %hi(0xdead1eaf),gr7
- setlo %lo(0xdead1eaf),gr7
- subcc gr7,gr8,gr0,icc0
- bne icc0,#0,__head_no_parameters
-
- sethi.p %hi(redboot_command_line-1),gr6
- setlo %lo(redboot_command_line-1),gr6
- sethi.p %hi(__head_reference),gr4
- setlo %lo(__head_reference),gr4
- sub gr6,gr4,gr6
- add.p gr6,gr26,gr6
- subi gr9,#1,gr9
- setlos.p #511,gr4
- setlos #1,gr5
-
-__head_copy_cmdline:
- ldubu.p @(gr9,gr5),gr16
- subicc gr4,#1,gr4,icc0
- stbu.p gr16,@(gr6,gr5)
- subicc gr16,#0,gr0,icc1
- bls icc0,#0,__head_end_cmdline
- bne icc1,#1,__head_copy_cmdline
-__head_end_cmdline:
- stbu gr0,@(gr6,gr5)
-__head_no_parameters:
-
-###############################################################################
-#
-# we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
-# - note that we're going to have to run entirely out of the icache whilst
-# fiddling with the SDRAM controller registers
-#
-###############################################################################
-#ifdef CONFIG_MMU
- call __head_fr451_describe_sdram
-
-#else
- movsg psr,gr5
- srli gr5,#28,gr5
- subicc gr5,#3,gr0,icc0
- beq icc0,#0,__head_fr551_sdram
-
- call __head_fr401_describe_sdram
- bra __head_do_sdram
-
-__head_fr551_sdram:
- call __head_fr555_describe_sdram
- LEDS 0x000d
-
-__head_do_sdram:
-#endif
-
- # preload the registers with invalid values in case any DBR/DARS are marked not present
- sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
- setlo %lo(0xfe000000),gr17
- or.p gr17,gr0,gr20
- or gr17,gr0,gr21
- or.p gr17,gr0,gr22
- or gr17,gr0,gr23
-
- # consult the SDRAM controller CS address registers
- cld @(gr14,gr0 ),gr20, cc0,#1 ; DBR0 / DARS0
- cld @(gr14,gr11),gr21, cc1,#1 ; DBR1 / DARS1
- cld @(gr14,gr12),gr22, cc2,#1 ; DBR2 / DARS2
- cld.p @(gr14,gr13),gr23, cc3,#1 ; DBR3 / DARS3
-
- sll gr20,gr15,gr20 ; shift values up for FR551
- sll gr21,gr15,gr21
- sll gr22,gr15,gr22
- sll gr23,gr15,gr23
-
- LEDS 0x0003
-
- # assume the lowest valid CS line to be the SDRAM base and get its address
- subcc gr20,gr17,gr0,icc0
- subcc.p gr21,gr17,gr0,icc1
- subcc gr22,gr17,gr0,icc2
- subcc.p gr23,gr17,gr0,icc3
- ckne icc0,cc4 ; T if DBR0 != 0xfe000000
- ckne icc1,cc5
- ckne icc2,cc6
- ckne icc3,cc7
- cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
- cor gr22,gr0,gr24, cc6,#1
- cor gr21,gr0,gr24, cc5,#1
- cor gr20,gr0,gr24, cc4,#1
-
- # calculate the displacement required to get the SDRAM into the right place in memory
- sethi.p %hi(__sdram_base),gr16
- setlo %lo(__sdram_base),gr16
- sub gr16,gr24,gr16 ; delta = __sdram_base - DBRx
-
- # calculate the new values to go in the controller regs
- cadd.p gr20,gr16,gr20, cc4,#1 ; DCS#0 (new) = DCS#0 (old) + delta
- cadd gr21,gr16,gr21, cc5,#1
- cadd.p gr22,gr16,gr22, cc6,#1
- cadd gr23,gr16,gr23, cc7,#1
-
- srl gr20,gr15,gr20 ; shift values down for FR551
- srl gr21,gr15,gr21
- srl gr22,gr15,gr22
- srl gr23,gr15,gr23
-
- # work out the address at which the reg updater resides and lock it into icache
- # also work out the address the updater will jump to when finished
- sethi.p %hi(__head_move_sdram-__head_reference),gr18
- setlo %lo(__head_move_sdram-__head_reference),gr18
- sethi.p %hi(__head_sdram_moved-__head_reference),gr19
- setlo %lo(__head_sdram_moved-__head_reference),gr19
- add.p gr18,gr26,gr18
- add gr19,gr26,gr19
- add.p gr19,gr16,gr19 ; moved = addr + (__sdram_base - DBRx)
- add gr18,gr5,gr4 ; two cachelines probably required
-
- icpl gr18,gr0,#1 ; load and lock the cachelines
- icpl gr4,gr0,#1
- LEDS 0x0004
- membar
- bar
- jmpl @(gr18,gr0)
-
- .balign L1_CACHE_BYTES
-__head_move_sdram:
- cst gr20,@(gr14,gr0 ), cc4,#1
- cst gr21,@(gr14,gr11), cc5,#1
- cst gr22,@(gr14,gr12), cc6,#1
- cst gr23,@(gr14,gr13), cc7,#1
- cld @(gr14,gr0 ),gr20, cc4,#1
- cld @(gr14,gr11),gr21, cc5,#1
- cld @(gr14,gr12),gr22, cc4,#1
- cld @(gr14,gr13),gr23, cc7,#1
- bar
- membar
- jmpl @(gr19,gr0)
-
- .balign L1_CACHE_BYTES
-__head_sdram_moved:
- icul gr18
- add gr18,gr5,gr4
- icul gr4
- icei @(gr0,gr0),1
- dcei @(gr0,gr0),1
-
- LEDS 0x0005
-
- # recalculate reference address
- call 0f
-0: movsg lr,gr26
- addi gr26,#__head_reference-0b,gr26
-
-
-###############################################################################
-#
-# move the kernel image down to the bottom of the SDRAM
-#
-###############################################################################
- sethi.p %hi(__kernel_image_size_no_bss+15),gr4
- setlo %lo(__kernel_image_size_no_bss+15),gr4
- srli.p gr4,#4,gr4 ; count
- or gr26,gr26,gr16 ; source
-
- sethi.p %hi(__sdram_base),gr17 ; destination
- setlo %lo(__sdram_base),gr17
-
- setlos #8,gr5
- sub.p gr16,gr5,gr16 ; adjust src for LDDU
- sub gr17,gr5,gr17 ; adjust dst for LDDU
-
- sethi.p %hi(__head_move_kernel-__head_reference),gr18
- setlo %lo(__head_move_kernel-__head_reference),gr18
- sethi.p %hi(__head_kernel_moved-__head_reference+__sdram_base),gr19
- setlo %lo(__head_kernel_moved-__head_reference+__sdram_base),gr19
- add gr18,gr26,gr18
- icpl gr18,gr0,#1
- jmpl @(gr18,gr0)
-
- .balign 32
-__head_move_kernel:
- lddu @(gr16,gr5),gr10
- lddu @(gr16,gr5),gr12
- stdu.p gr10,@(gr17,gr5)
- subicc gr4,#1,gr4,icc0
- stdu.p gr12,@(gr17,gr5)
- bhi icc0,#0,__head_move_kernel
- jmpl @(gr19,gr0)
-
- .balign 32
-__head_kernel_moved:
- icul gr18
- icei @(gr0,gr0),1
- dcei @(gr0,gr0),1
-
- LEDS 0x0006
-
- # recalculate reference address
- call 0f
-0: movsg lr,gr26
- addi gr26,#__head_reference-0b,gr26
-
-
-###############################################################################
-#
-# rearrange the iomem map and set the protection registers
-#
-###############################################################################
-
-#ifdef CONFIG_MMU
- LEDS 0x3301
- call __head_fr451_set_busctl
- LEDS 0x3303
- call __head_fr451_survey_sdram
- LEDS 0x3305
- call __head_fr451_set_protection
-
-#else
- movsg psr,gr5
- srli gr5,#PSR_IMPLE_SHIFT,gr5
- subicc gr5,#PSR_IMPLE_FR551,gr0,icc0
- beq icc0,#0,__head_fr555_memmap
- subicc gr5,#PSR_IMPLE_FR451,gr0,icc0
- beq icc0,#0,__head_fr451_memmap
-
- LEDS 0x3101
- call __head_fr401_set_busctl
- LEDS 0x3103
- call __head_fr401_survey_sdram
- LEDS 0x3105
- call __head_fr401_set_protection
- bra __head_done_memmap
-
-__head_fr451_memmap:
- LEDS 0x3301
- call __head_fr401_set_busctl
- LEDS 0x3303
- call __head_fr401_survey_sdram
- LEDS 0x3305
- call __head_fr451_set_protection
- bra __head_done_memmap
-
-__head_fr555_memmap:
- LEDS 0x3501
- call __head_fr555_set_busctl
- LEDS 0x3503
- call __head_fr555_survey_sdram
- LEDS 0x3505
- call __head_fr555_set_protection
-
-__head_done_memmap:
-#endif
- LEDS 0x0007
-
-###############################################################################
-#
-# turn the data cache and MMU on
-# - for the FR451 this'll mean that the window through which the kernel is
-# viewed will change
-#
-###############################################################################
-
-#ifdef CONFIG_MMU
-#define MMUMODE HSR0_EIMMU|HSR0_EDMMU|HSR0_EXMMU|HSR0_EDAT|HSR0_XEDAT
-#else
-#define MMUMODE HSR0_EIMMU|HSR0_EDMMU
-#endif
-
- movsg hsr0,gr5
-
- sethi.p %hi(MMUMODE),gr4
- setlo %lo(MMUMODE),gr4
- or gr4,gr5,gr5
-
-#if defined(CONFIG_FRV_DEFL_CACHE_WTHRU)
- sethi.p %hi(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
- setlo %lo(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
-#elif defined(CONFIG_FRV_DEFL_CACHE_WBACK)
- sethi.p %hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
- setlo %lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
-#elif defined(CONFIG_FRV_DEFL_CACHE_WBEHIND)
- sethi.p %hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
- setlo %lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
-
- movsg psr,gr6
- srli gr6,#24,gr6
- cmpi gr6,#0x50,icc0 // FR451
- beq icc0,#0,0f
- cmpi gr6,#0x40,icc0 // FR405
- bne icc0,#0,1f
-0:
- # turn off write-allocate
- sethi.p %hi(HSR0_NWA),gr6
- setlo %lo(HSR0_NWA),gr6
- or gr4,gr6,gr4
-1:
-
-#else
-#error No default cache configuration set
-#endif
-
- or gr4,gr5,gr5
- movgs gr5,hsr0
- bar
-
- LEDS 0x0008
-
- sethi.p %hi(__head_mmu_enabled),gr19
- setlo %lo(__head_mmu_enabled),gr19
- jmpl @(gr19,gr0)
-
-__head_mmu_enabled:
- icei @(gr0,gr0),#1
- dcei @(gr0,gr0),#1
-
- LEDS 0x0009
-
-#ifdef CONFIG_MMU
- call __head_fr451_finalise_protection
-#endif
-
- LEDS 0x000a
-
-###############################################################################
-#
-# set up the runtime environment
-#
-###############################################################################
-
- # clear the BSS area
- sethi.p %hi(__bss_start),gr4
- setlo %lo(__bss_start),gr4
- sethi.p %hi(_end),gr5
- setlo %lo(_end),gr5
- or.p gr0,gr0,gr18
- or gr0,gr0,gr19
-
-0:
- stdi gr18,@(gr4,#0)
- stdi gr18,@(gr4,#8)
- stdi gr18,@(gr4,#16)
- stdi.p gr18,@(gr4,#24)
- addi gr4,#24,gr4
- subcc gr5,gr4,gr0,icc0
- bhi icc0,#2,0b
-
- LEDS 0x000b
-
- # save the SDRAM details
- sethi.p %hi(__sdram_old_base),gr4
- setlo %lo(__sdram_old_base),gr4
- st gr24,@(gr4,gr0)
-
- sethi.p %hi(__sdram_base),gr5
- setlo %lo(__sdram_base),gr5
- sethi.p %hi(memory_start),gr4
- setlo %lo(memory_start),gr4
- st gr5,@(gr4,gr0)
-
- add gr25,gr5,gr25
- sethi.p %hi(memory_end),gr4
- setlo %lo(memory_end),gr4
- st gr25,@(gr4,gr0)
-
- # point the TBR at the kernel trap table
- sethi.p %hi(__entry_kerneltrap_table),gr4
- setlo %lo(__entry_kerneltrap_table),gr4
- movgs gr4,tbr
-
- # set up the exception frame for init
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- sethi.p %hi(_gp),gr16
- setlo %lo(_gp),gr16
- sethi.p %hi(__entry_usertrap_table),gr4
- setlo %lo(__entry_usertrap_table),gr4
-
- lddi @(gr28,#0),gr28 ; load __frame & current
- ldi.p @(gr29,#4),gr15 ; set current_thread
-
- or gr0,gr0,fp
- or gr28,gr0,sp
-
- sti.p gr4,@(gr28,REG_TBR)
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # turn on and off various CPU services
- movsg psr,gr22
- sethi.p %hi(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
- setlo %lo(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
- or gr22,gr4,gr22
- movgs gr22,psr
-
- andi gr22,#~(PSR_PIL|PSR_PS|PSR_S),gr22
- ori gr22,#PSR_ET,gr22
- sti gr22,@(gr28,REG_PSR)
-
-
-###############################################################################
-#
-# set up the registers and jump into the kernel
-#
-###############################################################################
-
- LEDS 0x000c
-
- sethi.p #0xe5e5,gr3
- setlo #0xe5e5,gr3
- or.p gr3,gr0,gr4
- or gr3,gr0,gr5
- or.p gr3,gr0,gr6
- or gr3,gr0,gr7
- or.p gr3,gr0,gr8
- or gr3,gr0,gr9
- or.p gr3,gr0,gr10
- or gr3,gr0,gr11
- or.p gr3,gr0,gr12
- or gr3,gr0,gr13
- or.p gr3,gr0,gr14
- or gr3,gr0,gr17
- or.p gr3,gr0,gr18
- or gr3,gr0,gr19
- or.p gr3,gr0,gr20
- or gr3,gr0,gr21
- or.p gr3,gr0,gr23
- or gr3,gr0,gr24
- or.p gr3,gr0,gr25
- or gr3,gr0,gr26
- or.p gr3,gr0,gr27
-# or gr3,gr0,gr30
- or gr3,gr0,gr31
- movgs gr0,lr
- movgs gr0,lcr
- movgs gr0,ccr
- movgs gr0,cccr
-
- # initialise the virtual interrupt handling
- subcc gr0,gr0,gr0,icc2 /* set Z, clear C */
-
-#ifdef CONFIG_MMU
- movgs gr3,scr2
- movgs gr3,scr3
-#endif
-
- LEDS 0x0fff
-
- # invoke the debugging stub if present
- # - arch/frv/kernel/debug-stub.c will shift control directly to init/main.c
- # (it will not return here)
- break
- .globl __debug_stub_init_break
-__debug_stub_init_break:
-
- # however, if you need to use an ICE, and don't care about using any userspace
- # debugging tools (such as the ptrace syscall), you can just step over the break
- # above and get to the kernel this way
- # look at arch/frv/kernel/debug-stub.c: debug_stub_init() to see what you've missed
- call start_kernel
-
- .globl __head_end
-__head_end:
- .size _boot, .-_boot
-
- # provide a point for GDB to place a break
- .section .text..start,"ax"
- .globl _start
- .balign 4
-_start:
- call _boot
-
- .previous
-###############################################################################
-#
-# split a tile off of the region defined by GR8-GR9
-#
-# ENTRY: EXIT:
-# GR4 - IAMPR value representing tile
-# GR5 - DAMPR value representing tile
-# GR6 - IAMLR value representing tile
-# GR7 - DAMLR value representing tile
-# GR8 region base pointer [saved]
-# GR9 region top pointer updated to exclude new tile
-# GR11 xAMLR mask [saved]
-# GR25 SDRAM size [saved]
-# GR30 LED address [saved]
-#
-# - GR8 and GR9 should be rounded up/down to the nearest megabyte before calling
-#
-###############################################################################
- .globl __head_split_region
- .type __head_split_region,@function
-__head_split_region:
- subcc.p gr9,gr8,gr4,icc0
- setlos #31,gr5
- scan.p gr4,gr0,gr6
- beq icc0,#0,__head_region_empty
- sub.p gr5,gr6,gr6 ; bit number of highest set bit (1MB=>20)
- setlos #1,gr4
- sll.p gr4,gr6,gr4 ; size of region (1 << bitno)
- subi gr6,#17,gr6 ; 1MB => 0x03
- slli.p gr6,#4,gr6 ; 1MB => 0x30
- sub gr9,gr4,gr9 ; move uncovered top down
-
- or gr9,gr6,gr4
- ori gr4,#xAMPRx_S_USER|xAMPRx_C_CACHED|xAMPRx_V,gr4
- or.p gr4,gr0,gr5
-
- and gr4,gr11,gr6
- and.p gr5,gr11,gr7
- bralr
-
-__head_region_empty:
- or.p gr0,gr0,gr4
- or gr0,gr0,gr5
- or.p gr0,gr0,gr6
- or gr0,gr0,gr7
- bralr
- .size __head_split_region, .-__head_split_region
-
-###############################################################################
-#
-# write the 32-bit hex number in GR8 to ttyS0
-#
-###############################################################################
-#if 0
- .globl __head_write_to_ttyS0
- .type __head_write_to_ttyS0,@function
-__head_write_to_ttyS0:
- sethi.p %hi(0xfeff9c00),gr31
- setlo %lo(0xfeff9c00),gr31
- setlos #8,gr20
-
-0: ldubi @(gr31,#5*8),gr21
- andi gr21,#0x60,gr21
- subicc gr21,#0x60,gr21,icc0
- bne icc0,#0,0b
-
-1: srli gr8,#28,gr21
- slli gr8,#4,gr8
-
- addi gr21,#'0',gr21
- subicc gr21,#'9',gr0,icc0
- bls icc0,#2,2f
- addi gr21,#'A'-'0'-10,gr21
-2:
- stbi gr21,@(gr31,#0*8)
- subicc gr20,#1,gr20,icc0
- bhi icc0,#2,1b
-
- setlos #'\r',gr21
- stbi gr21,@(gr31,#0*8)
-
- setlos #'\n',gr21
- stbi gr21,@(gr31,#0*8)
-
-3: ldubi @(gr31,#5*8),gr21
- andi gr21,#0x60,gr21
- subicc gr21,#0x60,gr21,icc0
- bne icc0,#0,3b
- bralr
-
- .size __head_write_to_ttyS0, .-__head_write_to_ttyS0
-#endif
diff --git a/arch/frv/kernel/head.inc b/arch/frv/kernel/head.inc
deleted file mode 100644
index bff66628b99a..000000000000
--- a/arch/frv/kernel/head.inc
+++ /dev/null
@@ -1,50 +0,0 @@
-/* head.inc: head common definitions -*- asm -*-
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
-#if defined(CONFIG_MB93090_MB00)
-#define LED_ADDR (0x21200000+4)
-
-.macro LEDS val
- sethi.p %hi(0xFFC00030),gr3
- setlo %lo(0xFFC00030),gr3
- lduh @(gr3,gr0),gr3
- andicc gr3,#0x100,gr0,icc0
- bne icc0,0,999f
-
- setlos #~\val,gr3
- st gr3,@(gr30,gr0)
- membar
- dcf @(gr30,gr0)
- 999:
-.endm
-
-#elif defined(CONFIG_MB93093_PDK)
-#define LED_ADDR (0x20000023)
-
-.macro LEDS val
- setlos #\val,gr3
- stb gr3,@(gr30,gr0)
- membar
-.endm
-
-#else
-#define LED_ADDR 0
-
-.macro LEDS val
-.endm
-#endif
-
-#ifdef CONFIG_MMU
-__sdram_base = 0x00000000 /* base address to which SDRAM relocated */
-#else
-__sdram_base = __page_offset /* base address to which SDRAM relocated */
-#endif
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c
deleted file mode 100644
index 091b2839be90..000000000000
--- a/arch/frv/kernel/irq-mb93091.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* irq-mb93091.c: MB93091 FPGA interrupt handling
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-
-#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
-
-#define __get_IMR() ({ __reg16(0xffc00004); })
-#define __set_IMR(M) do { __reg16(0xffc00004) = (M); wmb(); } while(0)
-#define __get_IFR() ({ __reg16(0xffc0000c); })
-#define __clr_IFR(M) do { __reg16(0xffc0000c) = ~(M); wmb(); } while(0)
-
-
-/*
- * on-motherboard FPGA PIC operations
- */
-static void frv_fpga_mask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
-
- __set_IMR(imr);
-}
-
-static void frv_fpga_ack(struct irq_data *d)
-{
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_mask_ack(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
- __set_IMR(imr);
-
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_unmask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
-
- __set_IMR(imr);
-}
-
-static struct irq_chip frv_fpga_pic = {
- .name = "mb93091",
- .irq_ack = frv_fpga_ack,
- .irq_mask = frv_fpga_mask,
- .irq_mask_ack = frv_fpga_mask_ack,
- .irq_unmask = frv_fpga_unmask,
-};
-
-/*
- * FPGA PIC interrupt handler
- */
-static irqreturn_t fpga_interrupt(int irq, void *_mask)
-{
- uint16_t imr, mask = (unsigned long) _mask;
-
- imr = __get_IMR();
- mask = mask & ~imr & __get_IFR();
-
- /* poll all the triggered IRQs */
- while (mask) {
- int irq;
-
- asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
- irq = 31 - irq;
- mask &= ~(1 << irq);
-
- generic_handle_irq(IRQ_BASE_FPGA + irq);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * define an interrupt action for each FPGA PIC output
- * - use dev_id to indicate the FPGA PIC input to output mappings
- */
-static struct irqaction fpga_irq[4] = {
- [0] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.0",
- .dev_id = (void *) 0x0028UL,
- },
- [1] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.1",
- .dev_id = (void *) 0x0050UL,
- },
- [2] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.2",
- .dev_id = (void *) 0x1c00UL,
- },
- [3] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.3",
- .dev_id = (void *) 0x6386UL,
- }
-};
-
-/*
- * initialise the motherboard FPGA's PIC
- */
-void __init fpga_init(void)
-{
- int irq;
-
- /* all PIC inputs are all set to be low-level driven, apart from the
- * NMI button (15) which is fixed at falling-edge
- */
- __set_IMR(0x7ffe);
- __clr_IFR(0x0000);
-
- for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
- irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
-
- irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
-
- /* the FPGA drives the first four external IRQ inputs on the CPU PIC */
- setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
- setup_irq(IRQ_CPU_EXTERNAL1, &fpga_irq[1]);
- setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[2]);
- setup_irq(IRQ_CPU_EXTERNAL3, &fpga_irq[3]);
-}
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c
deleted file mode 100644
index 1f3015cf80f5..000000000000
--- a/arch/frv/kernel/irq-mb93093.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* irq-mb93093.c: MB93093 FPGA interrupt handling
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-
-#define __reg16(ADDR) (*(volatile unsigned short *)(__region_CS2 + (ADDR)))
-
-#define __get_IMR() ({ __reg16(0x0a); })
-#define __set_IMR(M) do { __reg16(0x0a) = (M); wmb(); } while(0)
-#define __get_IFR() ({ __reg16(0x02); })
-#define __clr_IFR(M) do { __reg16(0x02) = ~(M); wmb(); } while(0)
-
-/*
- * off-CPU FPGA PIC operations
- */
-static void frv_fpga_mask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
- __set_IMR(imr);
-}
-
-static void frv_fpga_ack(struct irq_data *d)
-{
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_mask_ack(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
- __set_IMR(imr);
-
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_unmask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
-
- __set_IMR(imr);
-}
-
-static struct irq_chip frv_fpga_pic = {
- .name = "mb93093",
- .irq_ack = frv_fpga_ack,
- .irq_mask = frv_fpga_mask,
- .irq_mask_ack = frv_fpga_mask_ack,
- .irq_unmask = frv_fpga_unmask,
-};
-
-/*
- * FPGA PIC interrupt handler
- */
-static irqreturn_t fpga_interrupt(int irq, void *_mask)
-{
- uint16_t imr, mask = (unsigned long) _mask;
-
- imr = __get_IMR();
- mask = mask & ~imr & __get_IFR();
-
- /* poll all the triggered IRQs */
- while (mask) {
- int irq;
-
- asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
- irq = 31 - irq;
- mask &= ~(1 << irq);
-
- generic_handle_irq(IRQ_BASE_FPGA + irq);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * define an interrupt action for each FPGA PIC output
- * - use dev_id to indicate the FPGA PIC input to output mappings
- */
-static struct irqaction fpga_irq[1] = {
- [0] = {
- .handler = fpga_interrupt,
- .name = "fpga.0",
- .dev_id = (void *) 0x0700UL,
- }
-};
-
-/*
- * initialise the motherboard FPGA's PIC
- */
-void __init fpga_init(void)
-{
- int irq;
-
- /* all PIC inputs are all set to be edge triggered */
- __set_IMR(0x0700);
- __clr_IFR(0x0000);
-
- for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
- irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
-
- /* the FPGA drives external IRQ input #2 on the CPU PIC */
- setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
-}
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c
deleted file mode 100644
index 8ca5aa4ff595..000000000000
--- a/arch/frv/kernel/irq-mb93493.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* irq-mb93493.c: MB93493 companion chip interrupt handler
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-#include <asm/mb93493-irqs.h>
-#include <asm/mb93493-regs.h>
-
-#define IRQ_ROUTE_ONE(X) (X##_ROUTE << (X - IRQ_BASE_MB93493))
-
-#define IRQ_ROUTING \
- (IRQ_ROUTE_ONE(IRQ_MB93493_VDC) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_VCC) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_OUT) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_I2C_0) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_I2C_1) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_USB) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_LOCAL_BUS) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_PCMCIA) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_GPIO) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_IN))
-
-/*
- * daughter board PIC operations
- * - there is no way to ACK interrupts in the MB93493 chip
- */
-static void frv_mb93493_mask(struct irq_data *d)
-{
- uint32_t iqsr;
- volatile void *piqsr;
-
- if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
- piqsr = __addr_MB93493_IQSR(1);
- else
- piqsr = __addr_MB93493_IQSR(0);
-
- iqsr = readl(piqsr);
- iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16));
- writel(iqsr, piqsr);
-}
-
-static void frv_mb93493_ack(struct irq_data *d)
-{
-}
-
-static void frv_mb93493_unmask(struct irq_data *d)
-{
- uint32_t iqsr;
- volatile void *piqsr;
-
- if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
- piqsr = __addr_MB93493_IQSR(1);
- else
- piqsr = __addr_MB93493_IQSR(0);
-
- iqsr = readl(piqsr);
- iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16);
- writel(iqsr, piqsr);
-}
-
-static struct irq_chip frv_mb93493_pic = {
- .name = "mb93093",
- .irq_ack = frv_mb93493_ack,
- .irq_mask = frv_mb93493_mask,
- .irq_mask_ack = frv_mb93493_mask,
- .irq_unmask = frv_mb93493_unmask,
-};
-
-/*
- * MB93493 PIC interrupt handler
- */
-static irqreturn_t mb93493_interrupt(int irq, void *_piqsr)
-{
- volatile void *piqsr = _piqsr;
- uint32_t iqsr;
-
- iqsr = readl(piqsr);
- iqsr = iqsr & (iqsr >> 16) & 0xffff;
-
- /* poll all the triggered IRQs */
- while (iqsr) {
- int irq;
-
- asm("scan %1,gr0,%0" : "=r"(irq) : "r"(iqsr));
- irq = 31 - irq;
- iqsr &= ~(1 << irq);
-
- generic_handle_irq(IRQ_BASE_MB93493 + irq);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * define an interrupt action for each MB93493 PIC output
- * - use dev_id to indicate the MB93493 PIC input to output mappings
- */
-static struct irqaction mb93493_irq[2] = {
- [0] = {
- .handler = mb93493_interrupt,
- .flags = IRQF_SHARED,
- .name = "mb93493.0",
- .dev_id = (void *) __addr_MB93493_IQSR(0),
- },
- [1] = {
- .handler = mb93493_interrupt,
- .flags = IRQF_SHARED,
- .name = "mb93493.1",
- .dev_id = (void *) __addr_MB93493_IQSR(1),
- }
-};
-
-/*
- * initialise the motherboard MB93493's PIC
- */
-void __init mb93493_init(void)
-{
- int irq;
-
- for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
- irq_set_chip_and_handler(irq, &frv_mb93493_pic,
- handle_edge_irq);
-
- /* the MB93493 drives external IRQ inputs on the CPU PIC */
- setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
- setup_irq(IRQ_CPU_MB93493_1, &mb93493_irq[1]);
-}
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
deleted file mode 100644
index 93513e4ccd2b..000000000000
--- a/arch/frv/kernel/irq.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* irq.c: FRV IRQ handling
- *
- * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/random.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/irq.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/module.h>
-#include <linux/bitops.h>
-
-#include <linux/atomic.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <linux/uaccess.h>
-#include <asm/pgalloc.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-#include <asm/gdb-stub.h>
-
-#define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
-
-extern void __init fpga_init(void);
-#ifdef CONFIG_FUJITSU_MB93493
-extern void __init mb93493_init(void);
-#endif
-
-#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
-
-atomic_t irq_err_count;
-
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
- seq_printf(p, "%*s: ", prec, "ERR");
- seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
- return 0;
-}
-
-/*
- * on-CPU PIC operations
- */
-static void frv_cpupic_ack(struct irq_data *d)
-{
- __clr_RC(d->irq);
- __clr_IRL();
-}
-
-static void frv_cpupic_mask(struct irq_data *d)
-{
- __set_MASK(d->irq);
-}
-
-static void frv_cpupic_mask_ack(struct irq_data *d)
-{
- __set_MASK(d->irq);
- __clr_RC(d->irq);
- __clr_IRL();
-}
-
-static void frv_cpupic_unmask(struct irq_data *d)
-{
- __clr_MASK(d->irq);
-}
-
-static struct irq_chip frv_cpu_pic = {
- .name = "cpu",
- .irq_ack = frv_cpupic_ack,
- .irq_mask = frv_cpupic_mask,
- .irq_mask_ack = frv_cpupic_mask_ack,
- .irq_unmask = frv_cpupic_unmask,
-};
-
-/*
- * handles all normal device IRQs
- * - registers are referred to by the __frame variable (GR28)
- * - IRQ distribution is complicated in this arch because of the many PICs, the
- * way they work and the way they cascade
- */
-asmlinkage void do_IRQ(void)
-{
- irq_enter();
- generic_handle_irq(__get_IRL());
- irq_exit();
-}
-
-/*
- * handles all NMIs when not co-opted by the debugger
- * - registers are referred to by the __frame variable (GR28)
- */
-asmlinkage void do_NMI(void)
-{
-}
-
-/*
- * initialise the interrupt system
- */
-void __init init_IRQ(void)
-{
- int level;
-
- for (level = 1; level <= 14; level++)
- irq_set_chip_and_handler(level, &frv_cpu_pic,
- handle_level_irq);
-
- irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
-
- /* set the trigger levels for internal interrupt sources
- * - timers all falling-edge
- * - ERR0 is rising-edge
- * - all others are high-level
- */
- __set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 */
- __set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 */
-
- /* route internal interrupts */
- set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL,
- IRQ_DMA0_LEVEL);
- set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
- set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL,
- IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
- set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL,
- IRQ_DMA4_LEVEL);
-
- /* route external interrupts */
- set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL,
- IRQ_XIRQ4_LEVEL);
- set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL,
- IRQ_XIRQ0_LEVEL);
-
-#if defined(CONFIG_MB93091_VDK)
- __set_TM1(0x55550000); /* XIRQ7-0 all active low */
-#elif defined(CONFIG_MB93093_PDK)
- __set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
-#else
-#error dont know external IRQ trigger levels for this setup
-#endif
-
- fpga_init();
-#ifdef CONFIG_FUJITSU_MB93493
- mb93493_init();
-#endif
-}
diff --git a/arch/frv/kernel/local.h b/arch/frv/kernel/local.h
deleted file mode 100644
index 76606d13b1aa..000000000000
--- a/arch/frv/kernel/local.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* local.h: local definitions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _FRV_LOCAL_H
-#define _FRV_LOCAL_H
-
-#include <asm/sections.h>
-
-#ifndef __ASSEMBLY__
-
-/* dma.c */
-extern unsigned long frv_dma_inprogress;
-
-extern void frv_dma_pause_all(void);
-extern void frv_dma_resume_all(void);
-
-/* sleep.S */
-extern asmlinkage void frv_cpu_suspend(unsigned long);
-extern asmlinkage void frv_cpu_core_sleep(void);
-
-/* setup.c */
-extern unsigned long __nongprelbss pdm_suspend_mode;
-extern void determine_clocks(int verbose);
-extern int __nongprelbss clock_p0_current;
-extern int __nongprelbss clock_cm_current;
-extern int __nongprelbss clock_cmode_current;
-
-#ifdef CONFIG_PM
-extern int __nongprelbss clock_cmodes_permitted;
-extern unsigned long __nongprelbss clock_bits_settable;
-#define CLOCK_BIT_CM 0x0000000f
-#define CLOCK_BIT_CM_H 0x00000001 /* CLKC.CM can be set to 0 */
-#define CLOCK_BIT_CM_M 0x00000002 /* CLKC.CM can be set to 1 */
-#define CLOCK_BIT_CM_L 0x00000004 /* CLKC.CM can be set to 2 */
-#define CLOCK_BIT_P0 0x00000010 /* CLKC.P0 can be changed */
-#define CLOCK_BIT_CMODE 0x00000020 /* CLKC.CMODE can be changed */
-
-extern void (*__power_switch_wake_setup)(void);
-extern int (*__power_switch_wake_check)(void);
-extern void (*__power_switch_wake_cleanup)(void);
-#endif
-
-/* time.c */
-extern void time_divisor_init(void);
-
-/* cmode.S */
-extern asmlinkage void frv_change_cmode(int);
-
-
-#endif /* __ASSEMBLY__ */
-#endif /* _FRV_LOCAL_H */
diff --git a/arch/frv/kernel/local64.h b/arch/frv/kernel/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/frv/kernel/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/frv/kernel/module.c b/arch/frv/kernel/module.c
deleted file mode 100644
index 9d9835f1fe2b..000000000000
--- a/arch/frv/kernel/module.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* module.c: FRV specific module loading bits
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/i386/kernel/module.c, Copyright (C) 2001 Rusty Russell.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-
-#if 0
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt...)
-#endif
-
-/* TODO: At least one of apply_relocate or apply_relocate_add must be
- * implemented in order to get working module support.
- */
diff --git a/arch/frv/kernel/pm-mb93093.c b/arch/frv/kernel/pm-mb93093.c
deleted file mode 100644
index 8358e34a3fad..000000000000
--- a/arch/frv/kernel/pm-mb93093.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * FR-V MB93093 Power Management Routines
- *
- * Copyright (c) 2004 Red Hat, Inc.
- *
- * Written by: msalter@redhat.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- *
- */
-
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/sysctl.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-
-#include <asm/mb86943a.h>
-
-#include "local.h"
-
-static unsigned long imask;
-/*
- * Setup interrupt masks, etc to enable wakeup by power switch
- */
-static void mb93093_power_switch_setup(void)
-{
- /* mask all but FPGA interrupt sources. */
- imask = *(volatile unsigned long *)0xfeff9820;
- *(volatile unsigned long *)0xfeff9820 = ~(1 << (IRQ_XIRQ2_LEVEL + 16)) & 0xfffe0000;
-}
-
-/*
- * Cleanup interrupt masks, etc after wakeup by power switch
- */
-static void mb93093_power_switch_cleanup(void)
-{
- *(volatile unsigned long *)0xfeff9820 = imask;
-}
-
-/*
- * Return non-zero if wakeup irq was caused by power switch
- */
-static int mb93093_power_switch_check(void)
-{
- return 1;
-}
-
-/*
- * Initialize power interface
- */
-static int __init mb93093_pm_init(void)
-{
- __power_switch_wake_setup = mb93093_power_switch_setup;
- __power_switch_wake_check = mb93093_power_switch_check;
- __power_switch_wake_cleanup = mb93093_power_switch_cleanup;
- return 0;
-}
-
-__initcall(mb93093_pm_init);
-
diff --git a/arch/frv/kernel/pm.c b/arch/frv/kernel/pm.c
deleted file mode 100644
index 051ccecbf7f1..000000000000
--- a/arch/frv/kernel/pm.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * FR-V Power Management Routines
- *
- * Copyright (c) 2004 Red Hat, Inc.
- *
- * Based on SA1100 version:
- * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/sysctl.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-
-#include <asm/mb86943a.h>
-
-#include "local.h"
-
-/*
- * Debug macros
- */
-#define DEBUG
-
-int pm_do_suspend(void)
-{
- local_irq_disable();
-
- __set_LEDS(0xb1);
-
- /* go zzz */
- frv_cpu_suspend(pdm_suspend_mode);
-
- __set_LEDS(0xb2);
-
- local_irq_enable();
-
- return 0;
-}
-
-static unsigned long __irq_mask;
-
-/*
- * Setup interrupt masks, etc to enable wakeup by power switch
- */
-static void __default_power_switch_setup(void)
-{
- /* default is to mask all interrupt sources. */
- __irq_mask = *(unsigned long *)0xfeff9820;
- *(unsigned long *)0xfeff9820 = 0xfffe0000;
-}
-
-/*
- * Cleanup interrupt masks, etc after wakeup by power switch
- */
-static void __default_power_switch_cleanup(void)
-{
- *(unsigned long *)0xfeff9820 = __irq_mask;
-}
-
-/*
- * Return non-zero if wakeup irq was caused by power switch
- */
-static int __default_power_switch_check(void)
-{
- return 1;
-}
-
-void (*__power_switch_wake_setup)(void) = __default_power_switch_setup;
-int (*__power_switch_wake_check)(void) = __default_power_switch_check;
-void (*__power_switch_wake_cleanup)(void) = __default_power_switch_cleanup;
-
-int pm_do_bus_sleep(void)
-{
- local_irq_disable();
-
- /*
- * Here is where we need some platform-dependent setup
- * of the interrupt state so that appropriate wakeup
- * sources are allowed and all others are masked.
- */
- __power_switch_wake_setup();
-
- __set_LEDS(0xa1);
-
- /* go zzz
- *
- * This is in a loop in case power switch shares an irq with other
- * devices. The wake_check() tells us if we need to finish waking
- * or go back to sleep.
- */
- do {
- frv_cpu_suspend(HSR0_PDM_BUS_SLEEP);
- } while (__power_switch_wake_check && !__power_switch_wake_check());
-
- __set_LEDS(0xa2);
-
- /*
- * Here is where we need some platform-dependent restore
- * of the interrupt state prior to being called.
- */
- __power_switch_wake_cleanup();
-
- local_irq_enable();
-
- return 0;
-}
-
-unsigned long sleep_phys_sp(void *sp)
-{
- return virt_to_phys(sp);
-}
-
-#ifdef CONFIG_SYSCTL
-/*
- * Use a temporary sysctl number. Horrid, but will be cleaned up in 2.6
- * when all the PM interfaces exist nicely.
- */
-#define CTL_PM_SUSPEND 1
-#define CTL_PM_CMODE 2
-#define CTL_PM_P0 4
-#define CTL_PM_CM 5
-
-static int user_atoi(char __user *ubuf, size_t len)
-{
- char buf[16];
- unsigned long ret;
-
- if (len > 15)
- return -EINVAL;
-
- if (copy_from_user(buf, ubuf, len))
- return -EFAULT;
-
- buf[len] = 0;
- ret = simple_strtoul(buf, NULL, 0);
- if (ret > INT_MAX)
- return -ERANGE;
- return ret;
-}
-
-/*
- * Send us to sleep.
- */
-static int sysctl_pm_do_suspend(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int mode;
-
- if (*lenp <= 0)
- return -EIO;
-
- mode = user_atoi(buffer, *lenp);
- switch (mode) {
- case 1:
- return pm_do_suspend();
-
- case 5:
- return pm_do_bus_sleep();
-
- default:
- return -EINVAL;
- }
-}
-
-static int try_set_cmode(int new_cmode)
-{
- if (new_cmode > 15)
- return -EINVAL;
- if (!(clock_cmodes_permitted & (1<<new_cmode)))
- return -EINVAL;
-
- /* now change cmode */
- local_irq_disable();
- frv_dma_pause_all();
-
- frv_change_cmode(new_cmode);
-
- determine_clocks(0);
- time_divisor_init();
-
-#ifdef DEBUG
- determine_clocks(1);
-#endif
- frv_dma_resume_all();
- local_irq_enable();
-
- return 0;
-}
-
-
-static int cmode_procctl(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int new_cmode;
-
- if (!write)
- return proc_dointvec(ctl, write, buffer, lenp, fpos);
-
- new_cmode = user_atoi(buffer, *lenp);
-
- return try_set_cmode(new_cmode)?:*lenp;
-}
-
-static int try_set_p0(int new_p0)
-{
- unsigned long flags, clkc;
-
- if (new_p0 < 0 || new_p0 > 1)
- return -EINVAL;
-
- local_irq_save(flags);
- __set_PSR(flags & ~PSR_ET);
-
- frv_dma_pause_all();
-
- clkc = __get_CLKC();
- if (new_p0)
- clkc |= CLKC_P0;
- else
- clkc &= ~CLKC_P0;
- __set_CLKC(clkc);
-
- determine_clocks(0);
- time_divisor_init();
-
-#ifdef DEBUG
- determine_clocks(1);
-#endif
- frv_dma_resume_all();
- local_irq_restore(flags);
- return 0;
-}
-
-static int try_set_cm(int new_cm)
-{
- unsigned long flags, clkc;
-
- if (new_cm < 0 || new_cm > 1)
- return -EINVAL;
-
- local_irq_save(flags);
- __set_PSR(flags & ~PSR_ET);
-
- frv_dma_pause_all();
-
- clkc = __get_CLKC();
- clkc &= ~CLKC_CM;
- clkc |= new_cm;
- __set_CLKC(clkc);
-
- determine_clocks(0);
- time_divisor_init();
-
-#if 1 //def DEBUG
- determine_clocks(1);
-#endif
-
- frv_dma_resume_all();
- local_irq_restore(flags);
- return 0;
-}
-
-static int p0_procctl(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int new_p0;
-
- if (!write)
- return proc_dointvec(ctl, write, buffer, lenp, fpos);
-
- new_p0 = user_atoi(buffer, *lenp);
-
- return try_set_p0(new_p0)?:*lenp;
-}
-
-static int cm_procctl(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int new_cm;
-
- if (!write)
- return proc_dointvec(ctl, write, buffer, lenp, fpos);
-
- new_cm = user_atoi(buffer, *lenp);
-
- return try_set_cm(new_cm)?:*lenp;
-}
-
-static struct ctl_table pm_table[] =
-{
- {
- .procname = "suspend",
- .data = NULL,
- .maxlen = 0,
- .mode = 0200,
- .proc_handler = sysctl_pm_do_suspend,
- },
- {
- .procname = "cmode",
- .data = &clock_cmode_current,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = cmode_procctl,
- },
- {
- .procname = "p0",
- .data = &clock_p0_current,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = p0_procctl,
- },
- {
- .procname = "cm",
- .data = &clock_cm_current,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = cm_procctl,
- },
- { }
-};
-
-static struct ctl_table pm_dir_table[] =
-{
- {
- .procname = "pm",
- .mode = 0555,
- .child = pm_table,
- },
- { }
-};
-
-/*
- * Initialize power interface
- */
-static int __init pm_init(void)
-{
- register_sysctl_table(pm_dir_table);
- return 0;
-}
-
-__initcall(pm_init);
-
-#endif
diff --git a/arch/frv/kernel/process.c b/arch/frv/kernel/process.c
deleted file mode 100644
index a957b374e3a6..000000000000
--- a/arch/frv/kernel/process.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/* process.c: FRV specific parts of process handling
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/process.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/elf.h>
-#include <linux/reboot.h>
-#include <linux/interrupt.h>
-#include <linux/pagemap.h>
-#include <linux/rcupdate.h>
-
-#include <asm/asm-offsets.h>
-#include <linux/uaccess.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/tlb.h>
-#include <asm/gdb-stub.h>
-#include <asm/mb-regs.h>
-
-#include "local.h"
-
-asmlinkage void ret_from_fork(void);
-asmlinkage void ret_from_kernel_thread(void);
-
-#include <asm/pgalloc.h>
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-static void core_sleep_idle(void)
-{
-#ifdef LED_DEBUG_SLEEP
- /* Show that we're sleeping... */
- __set_LEDS(0x55aa);
-#endif
- frv_cpu_core_sleep();
-#ifdef LED_DEBUG_SLEEP
- /* ... and that we woke up */
- __set_LEDS(0);
-#endif
- mb();
-}
-
-void arch_cpu_idle(void)
-{
- if (!frv_dma_inprogress)
- core_sleep_idle();
- else
- local_irq_enable();
-}
-
-void machine_restart(char * __unused)
-{
- unsigned long reset_addr;
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(0);
-#endif
-
- if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551)
- reset_addr = 0xfefff500;
- else
- reset_addr = 0xfeff0500;
-
- /* Software reset. */
- asm volatile(" dcef @(gr0,gr0),1 ! membar !"
- " sti %1,@(%0,0) !"
- " nop ! nop ! nop ! nop ! nop ! "
- " nop ! nop ! nop ! nop ! nop ! "
- " nop ! nop ! nop ! nop ! nop ! "
- " nop ! nop ! nop ! nop ! nop ! "
- : : "r" (reset_addr), "r" (1) );
-
- for (;;)
- ;
-}
-
-void machine_halt(void)
-{
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(0);
-#endif
-
- for (;;);
-}
-
-void machine_power_off(void)
-{
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(0);
-#endif
-
- for (;;);
-}
-
-void flush_thread(void)
-{
- /* nothing */
-}
-
-inline unsigned long user_stack(const struct pt_regs *regs)
-{
- while (regs->next_frame)
- regs = regs->next_frame;
- return user_mode(regs) ? regs->sp : 0;
-}
-
-/*
- * set up the kernel stack and exception frames for a new process
- */
-int copy_thread(unsigned long clone_flags,
- unsigned long usp, unsigned long arg,
- struct task_struct *p)
-{
- struct pt_regs *childregs;
-
- childregs = (struct pt_regs *)
- (task_stack_page(p) + THREAD_SIZE - FRV_FRAME0_SIZE);
-
- /* set up the userspace frame (the only place that the USP is stored) */
- *childregs = *current_pt_regs();
-
- p->thread.frame = childregs;
- p->thread.curr = p;
- p->thread.sp = (unsigned long) childregs;
- p->thread.fp = 0;
- p->thread.lr = 0;
- p->thread.frame0 = childregs;
-
- if (unlikely(p->flags & PF_KTHREAD)) {
- childregs->gr9 = usp; /* function */
- childregs->gr8 = arg;
- p->thread.pc = (unsigned long) ret_from_kernel_thread;
- save_user_regs(p->thread.user);
- return 0;
- }
- if (usp)
- childregs->sp = usp;
- childregs->next_frame = NULL;
-
- p->thread.pc = (unsigned long) ret_from_fork;
-
- /* the new TLS pointer is passed in as arg #5 to sys_clone() */
- if (clone_flags & CLONE_SETTLS)
- childregs->gr29 = childregs->gr12;
-
- save_user_regs(p->thread.user);
-
- return 0;
-} /* end copy_thread() */
-
-unsigned long get_wchan(struct task_struct *p)
-{
- struct pt_regs *regs0;
- unsigned long fp, pc;
- unsigned long stack_limit;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- stack_limit = (unsigned long) (p + 1);
- fp = p->thread.fp;
- regs0 = p->thread.frame0;
-
- do {
- if (fp < stack_limit || fp >= (unsigned long) regs0 || fp & 3)
- return 0;
-
- pc = ((unsigned long *) fp)[2];
-
- /* FIXME: This depends on the order of these functions. */
- if (!in_sched_functions(pc))
- return pc;
-
- fp = *(unsigned long *) fp;
- } while (count++ < 16);
-
- return 0;
-}
-
-int elf_check_arch(const struct elf32_hdr *hdr)
-{
- unsigned long hsr0 = __get_HSR(0);
- unsigned long psr = __get_PSR();
-
- if (hdr->e_machine != EM_FRV)
- return 0;
-
- switch (hdr->e_flags & EF_FRV_GPR_MASK) {
- case EF_FRV_GPR64:
- if ((hsr0 & HSR0_GRN) == HSR0_GRN_32)
- return 0;
- case EF_FRV_GPR32:
- case 0:
- break;
- default:
- return 0;
- }
-
- switch (hdr->e_flags & EF_FRV_FPR_MASK) {
- case EF_FRV_FPR64:
- if ((hsr0 & HSR0_FRN) == HSR0_FRN_32)
- return 0;
- case EF_FRV_FPR32:
- case EF_FRV_FPR_NONE:
- case 0:
- break;
- default:
- return 0;
- }
-
- if ((hdr->e_flags & EF_FRV_MULADD) == EF_FRV_MULADD)
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR405 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR451)
- return 0;
-
- switch (hdr->e_flags & EF_FRV_CPU_MASK) {
- case EF_FRV_CPU_GENERIC:
- break;
- case EF_FRV_CPU_FR300:
- case EF_FRV_CPU_SIMPLE:
- case EF_FRV_CPU_TOMCAT:
- default:
- return 0;
- case EF_FRV_CPU_FR400:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR401 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR405 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR451 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR551)
- return 0;
- break;
- case EF_FRV_CPU_FR450:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR451)
- return 0;
- break;
- case EF_FRV_CPU_FR500:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR501)
- return 0;
- break;
- case EF_FRV_CPU_FR550:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR551)
- return 0;
- break;
- }
-
- return 1;
-}
-
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpregs)
-{
- memcpy(fpregs,
- &current->thread.user->f,
- sizeof(current->thread.user->f));
- return 1;
-}
diff --git a/arch/frv/kernel/ptrace.c b/arch/frv/kernel/ptrace.c
deleted file mode 100644
index 49768401ce0f..000000000000
--- a/arch/frv/kernel/ptrace.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/* ptrace.c: FRV specific parts of process tracing
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/ptrace.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/security.h>
-#include <linux/signal.h>
-#include <linux/regset.h>
-#include <linux/elf.h>
-#include <linux/tracehook.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/unistd.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/*
- * retrieve the contents of FRV userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct user_int_regs *iregs = &target->thread.user->i;
- int ret;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- iregs, 0, sizeof(*iregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*iregs), -1);
-}
-
-/*
- * update the contents of the FRV userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct user_int_regs *iregs = &target->thread.user->i;
- unsigned int offs_gr0, offs_gr1;
- int ret;
-
- /* not allowed to set PSR or __status */
- if (pos < offsetof(struct user_int_regs, psr) + sizeof(long) &&
- pos + count > offsetof(struct user_int_regs, psr))
- return -EIO;
-
- if (pos < offsetof(struct user_int_regs, __status) + sizeof(long) &&
- pos + count > offsetof(struct user_int_regs, __status))
- return -EIO;
-
- /* set the control regs */
- offs_gr0 = offsetof(struct user_int_regs, gr[0]);
- offs_gr1 = offsetof(struct user_int_regs, gr[1]);
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- iregs, 0, offs_gr0);
- if (ret < 0)
- return ret;
-
- /* skip GR0/TBR */
- ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- offs_gr0, offs_gr1);
- if (ret < 0)
- return ret;
-
- /* set the general regs */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &iregs->gr[1], offs_gr1, sizeof(*iregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- sizeof(*iregs), -1);
-}
-
-/*
- * retrieve the contents of FRV userspace FP/Media registers
- */
-static int fpmregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct user_fpmedia_regs *fpregs = &target->thread.user->f;
- int ret;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- fpregs, 0, sizeof(*fpregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*fpregs), -1);
-}
-
-/*
- * update the contents of the FRV userspace FP/Media registers
- */
-static int fpmregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct user_fpmedia_regs *fpregs = &target->thread.user->f;
- int ret;
-
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- fpregs, 0, sizeof(*fpregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- sizeof(*fpregs), -1);
-}
-
-/*
- * determine if the FP/Media registers have actually been used
- */
-static int fpmregs_active(struct task_struct *target,
- const struct user_regset *regset)
-{
- return tsk_used_math(target) ? regset->n : 0;
-}
-
-/*
- * Define the register sets available on the FRV under Linux
- */
-enum frv_regset {
- REGSET_GENERAL,
- REGSET_FPMEDIA,
-};
-
-static const struct user_regset frv_regsets[] = {
- /*
- * General register format is:
- * PSR, ISR, CCR, CCCR, LR, LCR, PC, (STATUS), SYSCALLNO, ORIG_G8
- * GNER0-1, IACC0, TBR, GR1-63
- */
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = ELF_NGREG,
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
- /*
- * FPU/Media register format is:
- * FR0-63, FNER0-1, MSR0-1, ACC0-7, ACCG0-8, FSR
- */
- [REGSET_FPMEDIA] = {
- .core_note_type = NT_PRFPREG,
- .n = sizeof(struct user_fpmedia_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = fpmregs_get,
- .set = fpmregs_set,
- .active = fpmregs_active,
- },
-};
-
-static const struct user_regset_view user_frv_native_view = {
- .name = "frv",
- .e_machine = EM_FRV,
- .regsets = frv_regsets,
- .n = ARRAY_SIZE(frv_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_frv_native_view;
-}
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long get_reg(struct task_struct *task, int regno)
-{
- struct user_context *user = task->thread.user;
-
- if (regno < 0 || regno >= PT__END)
- return 0;
-
- return ((unsigned long *) user)[regno];
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int put_reg(struct task_struct *task, int regno,
- unsigned long data)
-{
- struct user_context *user = task->thread.user;
-
- if (regno < 0 || regno >= PT__END)
- return -EIO;
-
- switch (regno) {
- case PT_GR(0):
- return 0;
- case PT_PSR:
- case PT__STATUS:
- return -EIO;
- default:
- ((unsigned long *) user)[regno] = data;
- return 0;
- }
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- *
- * Control h/w single stepping
- */
-void user_enable_single_step(struct task_struct *child)
-{
- child->thread.frame0->__status |= REG__STATUS_STEP;
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- child->thread.frame0->__status &= ~REG__STATUS_STEP;
-}
-
-void ptrace_disable(struct task_struct *child)
-{
- user_disable_single_step(child);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- unsigned long tmp;
- int ret;
- int regno = addr >> 2;
- unsigned long __user *datap = (unsigned long __user *) data;
-
- switch (request) {
- /* read the word at location addr in the USER area. */
- case PTRACE_PEEKUSR: {
- tmp = 0;
- ret = -EIO;
- if (addr & 3)
- break;
-
- ret = 0;
- switch (regno) {
- case 0 ... PT__END - 1:
- tmp = get_reg(child, regno);
- break;
-
- case PT__END + 0:
- tmp = child->mm->end_code - child->mm->start_code;
- break;
-
- case PT__END + 1:
- tmp = child->mm->end_data - child->mm->start_data;
- break;
-
- case PT__END + 2:
- tmp = child->mm->start_stack - child->mm->start_brk;
- break;
-
- case PT__END + 3:
- tmp = child->mm->start_code;
- break;
-
- case PT__END + 4:
- tmp = child->mm->start_stack;
- break;
-
- default:
- ret = -EIO;
- break;
- }
-
- if (ret == 0)
- ret = put_user(tmp, datap);
- break;
- }
-
- case PTRACE_POKEUSR: /* write the word at location addr in the USER area */
- ret = -EIO;
- if (addr & 3)
- break;
-
- switch (regno) {
- case 0 ... PT__END - 1:
- ret = put_reg(child, regno, data);
- break;
- }
- break;
-
- case PTRACE_GETREGS: /* Get all integer regs from the child. */
- return copy_regset_to_user(child, &user_frv_native_view,
- REGSET_GENERAL,
- 0, sizeof(child->thread.user->i),
- datap);
-
- case PTRACE_SETREGS: /* Set all integer regs in the child. */
- return copy_regset_from_user(child, &user_frv_native_view,
- REGSET_GENERAL,
- 0, sizeof(child->thread.user->i),
- datap);
-
- case PTRACE_GETFPREGS: /* Get the child FP/Media state. */
- return copy_regset_to_user(child, &user_frv_native_view,
- REGSET_FPMEDIA,
- 0, sizeof(child->thread.user->f),
- datap);
-
- case PTRACE_SETFPREGS: /* Set the child FP/Media state. */
- return copy_regset_from_user(child, &user_frv_native_view,
- REGSET_FPMEDIA,
- 0, sizeof(child->thread.user->f),
- datap);
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
- return ret;
-}
-
-/*
- * handle tracing of system call entry
- * - return the revised system call number or ULONG_MAX to cause ENOSYS
- */
-asmlinkage unsigned long syscall_trace_entry(void)
-{
- __frame->__status |= REG__STATUS_SYSC_ENTRY;
- if (tracehook_report_syscall_entry(__frame)) {
- /* tracing decided this syscall should not happen, so
- * We'll return a bogus call number to get an ENOSYS
- * error, but leave the original number in
- * __frame->syscallno
- */
- return ULONG_MAX;
- }
-
- return __frame->syscallno;
-}
-
-/*
- * handle tracing of system call exit
- */
-asmlinkage void syscall_trace_exit(void)
-{
- __frame->__status |= REG__STATUS_SYSC_EXIT;
- tracehook_report_syscall_exit(__frame, 0);
-}
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
deleted file mode 100644
index 9f4a9a607dbe..000000000000
--- a/arch/frv/kernel/setup.c
+++ /dev/null
@@ -1,1178 +0,0 @@
-/* setup.c: FRV specific setup
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/setup.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <generated/utsrelease.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/console.h>
-#include <linux/genhd.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/major.h>
-#include <linux/bootmem.h>
-#include <linux/highmem.h>
-#include <linux/seq_file.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-#include <linux/serial_8250.h>
-
-#include <asm/setup.h>
-#include <asm/irq.h>
-#include <asm/sections.h>
-#include <asm/pgalloc.h>
-#include <asm/busctl-regs.h>
-#include <asm/serial-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/irc-regs.h>
-#include <asm/spr-regs.h>
-#include <asm/mb-regs.h>
-#include <asm/mb93493-regs.h>
-#include <asm/gdb-stub.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_BLK_DEV_INITRD
-#include <asm/pgtable.h>
-#endif
-
-#include "local.h"
-
-#ifdef CONFIG_MB93090_MB00
-static void __init mb93090_display(void);
-#endif
-#ifdef CONFIG_MMU
-static void __init setup_linux_memory(void);
-#else
-static void __init setup_uclinux_memory(void);
-#endif
-
-#ifdef CONFIG_MB93090_MB00
-static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
-static char __initdata mb93090_version[] = UTS_RELEASE;
-
-int __nongprelbss mb93090_mb00_detected;
-#endif
-
-const char __frv_unknown_system[] = "unknown";
-const char __frv_mb93091_cb10[] = "mb93091-cb10";
-const char __frv_mb93091_cb11[] = "mb93091-cb11";
-const char __frv_mb93091_cb30[] = "mb93091-cb30";
-const char __frv_mb93091_cb41[] = "mb93091-cb41";
-const char __frv_mb93091_cb60[] = "mb93091-cb60";
-const char __frv_mb93091_cb70[] = "mb93091-cb70";
-const char __frv_mb93091_cb451[] = "mb93091-cb451";
-const char __frv_mb93090_mb00[] = "mb93090-mb00";
-
-const char __frv_mb93493[] = "mb93493";
-
-const char __frv_mb93093[] = "mb93093";
-
-static const char *__nongprelbss cpu_series;
-static const char *__nongprelbss cpu_core;
-static const char *__nongprelbss cpu_silicon;
-static const char *__nongprelbss cpu_mmu;
-static const char *__nongprelbss cpu_system;
-static const char *__nongprelbss cpu_board1;
-static const char *__nongprelbss cpu_board2;
-
-static unsigned long __nongprelbss cpu_psr_all;
-static unsigned long __nongprelbss cpu_hsr0_all;
-
-unsigned long __nongprelbss pdm_suspend_mode;
-
-unsigned long __nongprelbss rom_length;
-unsigned long __nongprelbss memory_start;
-unsigned long __nongprelbss memory_end;
-
-unsigned long __nongprelbss dma_coherent_mem_start;
-unsigned long __nongprelbss dma_coherent_mem_end;
-
-unsigned long __initdata __sdram_old_base;
-unsigned long __initdata num_mappedpages;
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-char __initdata redboot_command_line[COMMAND_LINE_SIZE];
-
-#ifdef CONFIG_PM
-#define __pminit
-#define __pminitdata
-#define __pminitconst
-#else
-#define __pminit __init
-#define __pminitdata __initdata
-#define __pminitconst __initconst
-#endif
-
-struct clock_cmode {
- uint8_t xbus, sdram, corebus, core, dsu;
-};
-
-#define _frac(N,D) ((N)<<4 | (D))
-#define _x0_16 _frac(1,6)
-#define _x0_25 _frac(1,4)
-#define _x0_33 _frac(1,3)
-#define _x0_375 _frac(3,8)
-#define _x0_5 _frac(1,2)
-#define _x0_66 _frac(2,3)
-#define _x0_75 _frac(3,4)
-#define _x1 _frac(1,1)
-#define _x1_5 _frac(3,2)
-#define _x2 _frac(2,1)
-#define _x3 _frac(3,1)
-#define _x4 _frac(4,1)
-#define _x4_5 _frac(9,2)
-#define _x6 _frac(6,1)
-#define _x8 _frac(8,1)
-#define _x9 _frac(9,1)
-
-int __nongprelbss clock_p0_current;
-int __nongprelbss clock_cm_current;
-int __nongprelbss clock_cmode_current;
-#ifdef CONFIG_PM
-int __nongprelbss clock_cmodes_permitted;
-unsigned long __nongprelbss clock_bits_settable;
-#endif
-
-static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
-
-static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
- [4] = { _x1, _x1, _x2, _x2, _x0_25 },
- [5] = { _x1, _x2, _x4, _x4, _x0_5 },
- [8] = { _x1, _x1, _x1, _x2, _x0_25 },
- [9] = { _x1, _x2, _x2, _x4, _x0_5 },
- [11] = { _x1, _x4, _x4, _x8, _x1 },
- [12] = { _x1, _x1, _x2, _x4, _x0_5 },
- [13] = { _x1, _x2, _x4, _x8, _x1 },
-};
-
-static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
- [0] = { _x1, _x1, _x1, _x1, _x0_5 },
- [1] = { _x1, _x1, _x1, _x3, _x0_25 },
- [2] = { _x1, _x1, _x2, _x6, _x0_5 },
- [3] = { _x1, _x2, _x2, _x6, _x0_5 },
- [4] = { _x1, _x1, _x2, _x2, _x0_16 },
- [8] = { _x1, _x1, _x1, _x2, _x0_16 },
- [9] = { _x1, _x2, _x2, _x4, _x0_33 },
- [12] = { _x1, _x1, _x2, _x4, _x0_33 },
- [14] = { _x1, _x3, _x3, _x9, _x0_75 },
- [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
-
-#define CLOCK_CMODES_PERMITTED_FR405 0xd31f
-};
-
-static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
- [0] = { _x1, _x2, _x2, _x4, _x0_33 },
- [1] = { _x1, _x3, _x3, _x6, _x0_5 },
- [2] = { _x1, _x2, _x4, _x8, _x0_66 },
- [3] = { _x1, _x1_5, _x3, _x6, _x0_5 },
- [4] = { _x1, _x3, _x3, _x9, _x0_75 },
- [5] = { _x1, _x2, _x2, _x6, _x0_5 },
- [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
-};
-
-static const struct clock_cmode __pminitconst *clock_cmodes;
-static int __pminitdata clock_doubled;
-
-static struct uart_port __pminitdata __frv_uart0 = {
- .uartclk = 0,
- .membase = (char *) UART0_BASE,
- .irq = IRQ_CPU_UART0,
- .regshift = 3,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-};
-
-static struct uart_port __pminitdata __frv_uart1 = {
- .uartclk = 0,
- .membase = (char *) UART1_BASE,
- .irq = IRQ_CPU_UART1,
- .regshift = 3,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-};
-
-#if 0
-static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
-{
- unsigned long phys, virt, cxn, size;
-
-#ifdef CONFIG_MMU
- virt = amlr & 0xffffc000;
- cxn = amlr & 0x3fff;
-#else
- virt = ampr & 0xffffc000;
- cxn = 0;
-#endif
- phys = ampr & xAMPRx_PPFN;
- size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
-
- printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
- i_d, n,
- virt, virt + size - 1,
- phys,
- ampr & xAMPRx_S ? 'S' : '-',
- ampr & xAMPRx_C ? 'C' : '-',
- ampr & DAMPRx_WP ? 'W' : '-',
- ampr & xAMPRx_V ? 'V' : '-',
- cxn
- );
-}
-#endif
-
-/*****************************************************************************/
-/*
- * dump the memory map
- */
-static void __init dump_memory_map(void)
-{
-
-#if 0
- /* dump the protection map */
- printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
- printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
- printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
- printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
- printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
- printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
- printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
- printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
- printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
- printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
- printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
- printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
- printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
- printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
- printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
- printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
-
- printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
- printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
- printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
- printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
- printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
- printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
- printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
- printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
- printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
- printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
- printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
- printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
- printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
- printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
- printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
- printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
-#endif
-
-#if 0
- /* dump the bus controller registers */
- printk("LGCR: %08lx\n", __get_LGCR());
- printk("Master: %08lx-%08lx CR=%08lx\n",
- __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
- __get_LMAICR());
-
- int loop;
- for (loop = 1; loop <= 7; loop++) {
- unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
- printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
- loop,
- lsbr, lsbr + __get_LSAM(loop),
- lcr & 0x80000000 ? 'r' : '-',
- lcr & 0x40000000 ? 'w' : '-',
- lcr & 0x08000000 ? 'b' : '-',
- lcr & 0x04000000 ? 'B' : '-',
- lcr & 0x02000000 ? 'C' : '-',
- lcr & 0x01000000 ? 'D' : '-',
- lcr & 0x00800000 ? 'W' : '-',
- lcr & 0x00400000 ? 'R' : '-',
- (lcr & 0x00030000) == 0x00000000 ? '4' :
- (lcr & 0x00030000) == 0x00010000 ? '2' :
- (lcr & 0x00030000) == 0x00020000 ? '1' :
- '-'
- );
- }
-#endif
-
-#if 0
- printk("\n");
-#endif
-} /* end dump_memory_map() */
-
-/*****************************************************************************/
-/*
- * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
- */
-#ifdef CONFIG_MB93091_VDK
-static void __init detect_mb93091(void)
-{
-#ifdef CONFIG_MB93090_MB00
- /* Detect CB70 without motherboard */
- if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
- cpu_board1 = __frv_mb93090_mb00;
- mb93090_mb00_detected = 1;
- }
-#endif
-
-#ifdef CONFIG_FUJITSU_MB93493
- cpu_board2 = __frv_mb93493;
-#endif
-
-} /* end detect_mb93091() */
-#endif
-
-/*****************************************************************************/
-/*
- * determine the CPU type and set appropriate parameters
- *
- * Family Series CPU Core Silicon Imple Vers
- * ----------------------------------------------------------
- * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
- * | | |
- * | | +-> MB93401/A 02 01
- * | | |
- * | | +-> MB93403 02 02
- * | |
- * | +-> FR405 ----> MB93405 04 00
- * |
- * +-> FR450 ----> FR451 ----> MB93451 05 00
- * |
- * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
- * | |
- * | +-> MB93501/A 01 02
- * |
- * +-> FR550 --+-> FR551 ----> MB93555 03 01
- *
- * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
- * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
- *
- * Imple is PSR(Processor Status Register)[31:28].
- * Vers is PSR(Processor Status Register)[27:24].
- *
- * A "Silicon" consists of CPU core and some on-chip peripherals.
- */
-static void __init determine_cpu(void)
-{
- unsigned long hsr0 = __get_HSR(0);
- unsigned long psr = __get_PSR();
-
- /* work out what selectable services the CPU supports */
- __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
- cpu_psr_all = __get_PSR();
- __set_PSR(psr);
-
- __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
- cpu_hsr0_all = __get_HSR(0);
- __set_HSR(0, hsr0);
-
- /* derive other service specs from the CPU type */
- cpu_series = "unknown";
- cpu_core = "unknown";
- cpu_silicon = "unknown";
- cpu_mmu = "Prot";
- cpu_system = __frv_unknown_system;
- clock_cmodes = NULL;
- clock_doubled = 0;
-#ifdef CONFIG_PM
- clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
-#endif
-
- switch (PSR_IMPLE(psr)) {
- case PSR_IMPLE_FR401:
- cpu_series = "fr400";
- cpu_core = "fr401";
- pdm_suspend_mode = HSR0_PDM_PLL_RUN;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR401_MB93401:
- cpu_silicon = "mb93401";
- cpu_system = __frv_mb93091_cb10;
- clock_cmodes = clock_cmodes_fr401_fr403;
- clock_doubled = 1;
- break;
- case PSR_VERSION_FR401_MB93401A:
- cpu_silicon = "mb93401/A";
- cpu_system = __frv_mb93091_cb11;
- clock_cmodes = clock_cmodes_fr401_fr403;
- break;
- case PSR_VERSION_FR401_MB93403:
- cpu_silicon = "mb93403";
-#ifndef CONFIG_MB93093_PDK
- cpu_system = __frv_mb93091_cb30;
-#else
- cpu_system = __frv_mb93093;
-#endif
- clock_cmodes = clock_cmodes_fr401_fr403;
- break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR405:
- cpu_series = "fr400";
- cpu_core = "fr405";
- pdm_suspend_mode = HSR0_PDM_PLL_STOP;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR405_MB93405:
- cpu_silicon = "mb93405";
- cpu_system = __frv_mb93091_cb60;
- clock_cmodes = clock_cmodes_fr405;
-#ifdef CONFIG_PM
- clock_bits_settable |= CLOCK_BIT_CMODE;
- clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
-#endif
-
- /* the FPGA on the CB70 has extra registers
- * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
- * how we tell the difference between it and a CB60
- */
- if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
- cpu_system = __frv_mb93091_cb70;
- break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR451:
- cpu_series = "fr450";
- cpu_core = "fr451";
- pdm_suspend_mode = HSR0_PDM_PLL_STOP;
-#ifdef CONFIG_PM
- clock_bits_settable |= CLOCK_BIT_CMODE;
- clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
-#endif
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR451_MB93451:
- cpu_silicon = "mb93451";
- cpu_mmu = "Prot, SAT, xSAT, DAT";
- cpu_system = __frv_mb93091_cb451;
- clock_cmodes = clock_cmodes_fr405;
- break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR501:
- cpu_series = "fr500";
- cpu_core = "fr501";
- pdm_suspend_mode = HSR0_PDM_PLL_STOP;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break;
- case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR551:
- cpu_series = "fr550";
- cpu_core = "fr551";
- pdm_suspend_mode = HSR0_PDM_PLL_RUN;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR551_MB93555:
- cpu_silicon = "mb93555";
- cpu_mmu = "Prot, SAT";
- cpu_system = __frv_mb93091_cb41;
- clock_cmodes = clock_cmodes_fr555;
- clock_doubled = 1;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
-
- printk("- Series:%s CPU:%s Silicon:%s\n",
- cpu_series, cpu_core, cpu_silicon);
-
-#ifdef CONFIG_MB93091_VDK
- detect_mb93091();
-#endif
-
-#if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
- cpu_board2 = __frv_mb93493;
-#endif
-
-} /* end determine_cpu() */
-
-/*****************************************************************************/
-/*
- * calculate the bus clock speed
- */
-void __pminit determine_clocks(int verbose)
-{
- const struct clock_cmode *mode, *tmode;
- unsigned long clkc, psr, quot;
-
- clkc = __get_CLKC();
- psr = __get_PSR();
-
- clock_p0_current = !!(clkc & CLKC_P0);
- clock_cm_current = clkc & CLKC_CM;
- clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
-
- if (verbose)
- printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
-
- /* the CB70 has some alternative ways of setting the clock speed through switches accessed
- * through the FPGA. */
- if (cpu_system == __frv_mb93091_cb70) {
- unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
-
- if (clkswr & 0x1000)
- __clkin_clock_speed_HZ = 60000000UL;
- else
- __clkin_clock_speed_HZ =
- ((clkswr >> 8) & 0xf) * 10000000 +
- ((clkswr >> 4) & 0xf) * 1000000 +
- ((clkswr ) & 0xf) * 100000;
- }
- /* the FR451 is currently fixed at 24MHz */
- else if (cpu_system == __frv_mb93091_cb451) {
- //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
- unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
-
- if (clkswr & 0x1000)
- __clkin_clock_speed_HZ = 60000000UL;
- else
- __clkin_clock_speed_HZ =
- ((clkswr >> 8) & 0xf) * 10000000 +
- ((clkswr >> 4) & 0xf) * 1000000 +
- ((clkswr ) & 0xf) * 100000;
- }
- /* otherwise determine the clockspeed from VDK or other registers */
- else {
- __clkin_clock_speed_HZ = __get_CLKIN();
- }
-
- /* look up the appropriate clock relationships table entry */
- mode = &undef_clock_cmode;
- if (clock_cmodes) {
- tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
- if (tmode->xbus)
- mode = tmode;
- }
-
-#define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
-
- if (clock_doubled)
- __clkin_clock_speed_HZ <<= 1;
-
- __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
- __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
- __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
-
- switch (clkc & CLKC_CM) {
- case 0: /* High */
- __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
- __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core);
- break;
- case 1: /* Medium */
- __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
- __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
- break;
- case 2: /* Low; not supported */
- case 3: /* UNDEF */
- printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
- panic("Bye");
- }
-
- __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
- if (clkc & CLKC_P0)
- __res_bus_clock_speed_HZ >>= 1;
-
- if (verbose) {
- printk("CLKIN: %lu.%3.3luMHz\n",
- __clkin_clock_speed_HZ / 1000000,
- (__clkin_clock_speed_HZ / 1000) % 1000);
-
- printk("CLKS:"
- " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
- __ext_bus_clock_speed_HZ / 1000000,
- __res_bus_clock_speed_HZ / 1000000,
- __sdram_clock_speed_HZ / 1000000,
- __core_bus_clock_speed_HZ / 1000000,
- __core_clock_speed_HZ / 1000000,
- __dsu_clock_speed_HZ / 1000000
- );
- }
-
- /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
- __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
-
- /* set the serial prescaler */
- __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
- quot = 1;
- while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
- quot += 1;
-
- /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
- * - we have to be careful - dividing too much can mean we can't get 115200 baud
- */
- if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
- quot <<= 1;
-
- __serial_clock_speed_HZ /= quot;
- __frv_uart0.uartclk = __serial_clock_speed_HZ;
- __frv_uart1.uartclk = __serial_clock_speed_HZ;
-
- if (verbose)
- printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
-
- while (!(__get_UART0_LSR() & UART_LSR_TEMT))
- continue;
-
- while (!(__get_UART1_LSR() & UART_LSR_TEMT))
- continue;
-
- __set_UCPVR(quot);
- __set_UCPSR(0);
-} /* end determine_clocks() */
-
-/*****************************************************************************/
-/*
- * reserve some DMA consistent memory
- */
-#ifdef CONFIG_RESERVE_DMA_COHERENT
-static void __init reserve_dma_coherent(void)
-{
- unsigned long ampr;
-
- /* find the first non-kernel memory tile and steal it */
-#define __steal_AMPR(r) \
- if (__get_DAMPR(r) & xAMPRx_V) { \
- ampr = __get_DAMPR(r); \
- __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
- __set_IAMPR(r, 0); \
- goto found; \
- }
-
- __steal_AMPR(1);
- __steal_AMPR(2);
- __steal_AMPR(3);
- __steal_AMPR(4);
- __steal_AMPR(5);
- __steal_AMPR(6);
-
- if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
- __steal_AMPR(7);
- __steal_AMPR(8);
- __steal_AMPR(9);
- __steal_AMPR(10);
- __steal_AMPR(11);
- __steal_AMPR(12);
- __steal_AMPR(13);
- __steal_AMPR(14);
- }
-
- /* unable to grant any DMA consistent memory */
- printk("No DMA consistent memory reserved\n");
- return;
-
- found:
- dma_coherent_mem_start = ampr & xAMPRx_PPFN;
- ampr &= xAMPRx_SS;
- ampr >>= 4;
- ampr = 1 << (ampr - 3 + 20);
- dma_coherent_mem_end = dma_coherent_mem_start + ampr;
-
- printk("DMA consistent memory reserved %lx-%lx\n",
- dma_coherent_mem_start, dma_coherent_mem_end);
-
-} /* end reserve_dma_coherent() */
-#endif
-
-/*****************************************************************************/
-/*
- * calibrate the delay loop
- */
-void calibrate_delay(void)
-{
- loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
-
- printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
- loops_per_jiffy / (500000 / HZ),
- (loops_per_jiffy / (5000 / HZ)) % 100);
-
-} /* end calibrate_delay() */
-
-/*****************************************************************************/
-/*
- * look through the command line for some things we need to know immediately
- */
-static void __init parse_cmdline_early(char *cmdline)
-{
- if (!cmdline)
- return;
-
- while (*cmdline) {
- if (*cmdline == ' ')
- cmdline++;
-
- /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
- * out from the SDRAM controller mask register
- */
- if (!strncmp(cmdline, "mem=", 4)) {
- unsigned long long mem_size;
-
- mem_size = memparse(cmdline + 4, &cmdline);
- memory_end = memory_start + mem_size;
- }
-
- while (*cmdline && *cmdline != ' ')
- cmdline++;
- }
-
-} /* end parse_cmdline_early() */
-
-/*****************************************************************************/
-/*
- *
- */
-void __init setup_arch(char **cmdline_p)
-{
-#ifdef CONFIG_MMU
- printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
-#else
- printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
-#endif
-
- memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
-
- determine_cpu();
- determine_clocks(1);
-
- /* For printk-directly-beats-on-serial-hardware hack */
- console_set_baud(115200);
-#ifdef CONFIG_GDBSTUB
- gdbstub_set_baud(115200);
-#endif
-
-#ifdef CONFIG_RESERVE_DMA_COHERENT
- reserve_dma_coherent();
-#endif
- dump_memory_map();
-
-#ifdef CONFIG_MB93090_MB00
- if (mb93090_mb00_detected)
- mb93090_display();
-#endif
-
- /* register those serial ports that are available */
-#ifdef CONFIG_FRV_ONCPU_SERIAL
-#ifndef CONFIG_GDBSTUB_UART0
- __reg(UART0_BASE + UART_IER * 8) = 0;
- early_serial_setup(&__frv_uart0);
-#endif
-#ifndef CONFIG_GDBSTUB_UART1
- __reg(UART1_BASE + UART_IER * 8) = 0;
- early_serial_setup(&__frv_uart1);
-#endif
-#endif
-
- /* deal with the command line - RedBoot may have passed one to the kernel */
- memcpy(command_line, boot_command_line, sizeof(command_line));
- *cmdline_p = &command_line[0];
- parse_cmdline_early(command_line);
-
- /* set up the memory description
- * - by now the stack is part of the init task */
- printk("Memory %08lx-%08lx\n", memory_start, memory_end);
-
- BUG_ON(memory_start == memory_end);
-
- init_mm.start_code = (unsigned long) _stext;
- init_mm.end_code = (unsigned long) _etext;
- init_mm.end_data = (unsigned long) _edata;
-#if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
- init_mm.brk = (unsigned long) &_end;
-#else
- init_mm.brk = (unsigned long) 0;
-#endif
-
-#ifdef DEBUG
- printk("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n",
- _stext, _etext, _sdata, _edata, __bss_start, __bss_stop);
-#endif
-
-#ifdef CONFIG_VT
-#if defined(CONFIG_VGA_CONSOLE)
- conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
- conswitchp = &dummy_con;
-#endif
-#endif
-
-#ifdef CONFIG_MMU
- setup_linux_memory();
-#else
- setup_uclinux_memory();
-#endif
-
- /* get kmalloc into gear */
- paging_init();
-
- /* init DMA */
- frv_dma_init();
-#ifdef DEBUG
- printk("Done setup_arch\n");
-#endif
-
- /* start the decrement timer running */
-// asm volatile("movgs %0,timerd" :: "r"(10000000));
-// __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
-
-} /* end setup_arch() */
-
-#if 0
-/*****************************************************************************/
-/*
- *
- */
-static int setup_arch_serial(void)
-{
- /* register those serial ports that are available */
-#ifndef CONFIG_GDBSTUB_UART0
- early_serial_setup(&__frv_uart0);
-#endif
-#ifndef CONFIG_GDBSTUB_UART1
- early_serial_setup(&__frv_uart1);
-#endif
-
- return 0;
-} /* end setup_arch_serial() */
-
-late_initcall(setup_arch_serial);
-#endif
-
-/*****************************************************************************/
-/*
- * set up the memory map for normal MMU linux
- */
-#ifdef CONFIG_MMU
-static void __init setup_linux_memory(void)
-{
- unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
- unsigned long physpages;
-
- kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
- kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
-
- kstart = kstart & PAGE_MASK;
- kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
-
- /* give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map immediately following the kernel image
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- kend >> PAGE_SHIFT, /* map addr */
- memory_start >> PAGE_SHIFT, /* start of RAM */
- memory_end >> PAGE_SHIFT /* end of RAM */
- );
-
- /* pass the memory that the kernel can immediately use over to the bootmem allocator */
- max_mapnr = physpages = (memory_end - memory_start) >> PAGE_SHIFT;
- low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
- high_mem = 0;
-
- if (physpages > low_top_pfn) {
-#ifdef CONFIG_HIGHMEM
- high_mem = physpages - low_top_pfn;
-#else
- max_mapnr = physpages = low_top_pfn;
-#endif
- }
- else {
- low_top_pfn = physpages;
- }
-
- min_low_pfn = memory_start >> PAGE_SHIFT;
- max_low_pfn = low_top_pfn;
- max_pfn = memory_end >> PAGE_SHIFT;
-
- num_mappedpages = low_top_pfn;
-
- printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
-
- free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
-
-#ifdef CONFIG_HIGHMEM
- if (high_mem)
- printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
-#endif
-
- /* take back the memory occupied by the kernel image and the bootmem alloc map */
- reserve_bootmem(kstart, kend - kstart + bootmap_size,
- BOOTMEM_DEFAULT);
-
- /* reserve the memory occupied by the initial ramdisk */
-#ifdef CONFIG_BLK_DEV_INITRD
- if (LOADER_TYPE && INITRD_START) {
- if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
- reserve_bootmem(INITRD_START, INITRD_SIZE,
- BOOTMEM_DEFAULT);
- initrd_start = INITRD_START + PAGE_OFFSET;
- initrd_end = initrd_start + INITRD_SIZE;
- }
- else {
- printk(KERN_ERR
- "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
- "disabling initrd\n",
- INITRD_START + INITRD_SIZE,
- low_top_pfn << PAGE_SHIFT);
- initrd_start = 0;
- }
- }
-#endif
-
-} /* end setup_linux_memory() */
-#endif
-
-/*****************************************************************************/
-/*
- * set up the memory map for uClinux
- */
-#ifndef CONFIG_MMU
-static void __init setup_uclinux_memory(void)
-{
-#ifdef CONFIG_PROTECT_KERNEL
- unsigned long dampr;
-#endif
- unsigned long kend;
- int bootmap_size;
-
- kend = (unsigned long) &__kernel_image_end;
- kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
-
- /* give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map immediately following the kernel image
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- kend >> PAGE_SHIFT, /* map addr */
- memory_start >> PAGE_SHIFT, /* start of RAM */
- memory_end >> PAGE_SHIFT /* end of RAM */
- );
-
- /* free all the usable memory */
- free_bootmem(memory_start, memory_end - memory_start);
-
- high_memory = (void *) (memory_end & PAGE_MASK);
- max_mapnr = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
- min_low_pfn = memory_start >> PAGE_SHIFT;
- max_low_pfn = memory_end >> PAGE_SHIFT;
- max_pfn = max_low_pfn;
-
- /* now take back the bits the core kernel is occupying */
-#ifndef CONFIG_PROTECT_KERNEL
- reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT);
- reserve_bootmem((unsigned long) &__kernel_image_start,
- kend - (unsigned long) &__kernel_image_start,
- BOOTMEM_DEFAULT);
-
-#else
- dampr = __get_DAMPR(0);
- dampr &= xAMPRx_SS;
- dampr = (dampr >> 4) + 17;
- dampr = 1 << dampr;
-
- reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT);
-#endif
-
- /* reserve some memory to do uncached DMA through if requested */
-#ifdef CONFIG_RESERVE_DMA_COHERENT
- if (dma_coherent_mem_start)
- reserve_bootmem(dma_coherent_mem_start,
- dma_coherent_mem_end - dma_coherent_mem_start,
- BOOTMEM_DEFAULT);
-#endif
-
-} /* end setup_uclinux_memory() */
-#endif
-
-/*****************************************************************************/
-/*
- * get CPU information for use by procfs
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
-#ifdef CONFIG_PM
- const char *sep;
-#endif
-
- gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31";
- fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31";
- fm = cpu_psr_all & PSR_EM ? ", Media" : "";
- fp = cpu_psr_all & PSR_EF ? ", FPU" : "";
- cm = cpu_psr_all & PSR_CM ? ", CCCR" : "";
- nem = cpu_psr_all & PSR_NEM ? ", NE" : "";
- ble = cpu_psr_all & PSR_BE ? "BE" : "LE";
-
- seq_printf(m,
- "CPU-Series:\t%s\n"
- "CPU-Core:\t%s, %s, %s%s%s\n"
- "CPU:\t\t%s\n"
- "MMU:\t\t%s\n"
- "FP-Media:\t%s%s%s\n"
- "System:\t\t%s",
- cpu_series,
- cpu_core, gr, ble, cm, nem,
- cpu_silicon,
- cpu_mmu,
- fr, fm, fp,
- cpu_system);
-
- if (cpu_board1)
- seq_printf(m, ", %s", cpu_board1);
-
- if (cpu_board2)
- seq_printf(m, ", %s", cpu_board2);
-
- seq_printf(m, "\n");
-
-#ifdef CONFIG_PM
- seq_printf(m, "PM-Controls:");
- sep = "\t";
-
- if (clock_bits_settable & CLOCK_BIT_CMODE) {
- seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
- sep = ", ";
- }
-
- if (clock_bits_settable & CLOCK_BIT_CM) {
- seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
- sep = ", ";
- }
-
- if (clock_bits_settable & CLOCK_BIT_P0) {
- seq_printf(m, "%sp0=0x3", sep);
- sep = ", ";
- }
-
- seq_printf(m, "%ssuspend=0x22\n", sep);
-#endif
-
- seq_printf(m,
- "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
- clock_cmode_current, clock_cm_current, clock_p0_current);
-
-#define print_clk(TAG, VAR) \
- seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
-
- print_clk("In", __clkin_clock_speed_HZ);
- print_clk("Core", __core_clock_speed_HZ);
- print_clk("SDRAM", __sdram_clock_speed_HZ);
- print_clk("CBus", __core_bus_clock_speed_HZ);
- print_clk("Res", __res_bus_clock_speed_HZ);
- print_clk("Ext", __ext_bus_clock_speed_HZ);
- print_clk("DSU", __dsu_clock_speed_HZ);
-
- seq_printf(m,
- "BogoMips:\t%lu.%02lu\n",
- (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
-
- return 0;
-} /* end show_cpuinfo() */
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-void arch_gettod(int *year, int *mon, int *day, int *hour,
- int *min, int *sec)
-{
- *year = *mon = *day = *hour = *min = *sec = 0;
-}
-
-/*****************************************************************************/
-/*
- *
- */
-#ifdef CONFIG_MB93090_MB00
-static void __init mb93090_sendlcdcmd(uint32_t cmd)
-{
- unsigned long base = __addr_LCD();
- int loop;
-
- /* request reading of the busy flag */
- __set_LCD(base, LCD_CMD_READ_BUSY);
- __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
-
- /* wait for the busy flag to become clear */
- for (loop = 10000; loop > 0; loop--)
- if (!(__get_LCD(base) & 0x80))
- break;
-
- /* send the command */
- __set_LCD(base, cmd);
- __set_LCD(base, cmd & ~LCD_E);
-
-} /* end mb93090_sendlcdcmd() */
-
-/*****************************************************************************/
-/*
- * write to the MB93090 LEDs and LCD
- */
-static void __init mb93090_display(void)
-{
- const char *p;
-
- __set_LEDS(0);
-
- /* set up the LCD */
- mb93090_sendlcdcmd(LCD_CMD_CLEAR);
- mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
- mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
- mb93090_sendlcdcmd(LCD_CMD_HOME);
-
- mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
- for (p = mb93090_banner; *p; p++)
- mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
-
- mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
- for (p = mb93090_version; *p; p++)
- mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
-
-} /* end mb93090_display() */
-
-#endif // CONFIG_MB93090_MB00
diff --git a/arch/frv/kernel/signal.c b/arch/frv/kernel/signal.c
deleted file mode 100644
index bf6e07a7a1b1..000000000000
--- a/arch/frv/kernel/signal.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/* signal.c: FRV specific bits of signal handling
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/signal.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/personality.h>
-#include <linux/tracehook.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <asm/cacheflush.h>
-
-#define DEBUG_SIG 0
-
-struct fdpic_func_descriptor {
- unsigned long text;
- unsigned long GOT;
-};
-
-/*
- * Do a signal return; undo the signal stack.
- */
-
-struct sigframe
-{
- __sigrestore_t pretcode;
- int sig;
- struct sigcontext sc;
- unsigned long extramask[_NSIG_WORDS-1];
- uint32_t retcode[2];
-};
-
-struct rt_sigframe
-{
- __sigrestore_t pretcode;
- int sig;
- struct siginfo __user *pinfo;
- void __user *puc;
- struct siginfo info;
- struct ucontext uc;
- uint32_t retcode[2];
-};
-
-static int restore_sigcontext(struct sigcontext __user *sc, int *_gr8)
-{
- struct user_context *user = current->thread.user;
- unsigned long tbr, psr;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- tbr = user->i.tbr;
- psr = user->i.psr;
- if (copy_from_user(user, &sc->sc_context, sizeof(sc->sc_context)))
- goto badframe;
- user->i.tbr = tbr;
- user->i.psr = psr;
-
- restore_user_regs(user);
-
- user->i.syscallno = -1; /* disable syscall checks */
-
- *_gr8 = user->i.gr[8];
- return 0;
-
- badframe:
- return 1;
-}
-
-asmlinkage int sys_sigreturn(void)
-{
- struct sigframe __user *frame = (struct sigframe __user *) __frame->sp;
- sigset_t set;
- int gr8;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__get_user(set.sig[0], &frame->sc.sc_oldmask))
- goto badframe;
-
- if (_NSIG_WORDS > 1 &&
- __copy_from_user(&set.sig[1], &frame->extramask, sizeof(frame->extramask)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(&frame->sc, &gr8))
- goto badframe;
- return gr8;
-
- badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct rt_sigframe __user *frame = (struct rt_sigframe __user *) __frame->sp;
- sigset_t set;
- int gr8;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(&frame->uc.uc_mcontext, &gr8))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return gr8;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * Set up a signal frame
- */
-static int setup_sigcontext(struct sigcontext __user *sc, unsigned long mask)
-{
- save_user_regs(current->thread.user);
-
- if (copy_to_user(&sc->sc_context, current->thread.user, sizeof(sc->sc_context)) != 0)
- goto badframe;
-
- /* non-iBCS2 extensions.. */
- if (__put_user(mask, &sc->sc_oldmask) < 0)
- goto badframe;
-
- return 0;
-
- badframe:
- return 1;
-}
-
-/*****************************************************************************/
-/*
- * Determine which stack to use..
- */
-static inline void __user *get_sigframe(struct ksignal *ksig,
- size_t frame_size)
-{
- unsigned long sp = sigsp(__frame->sp, ksig);
-
- return (void __user *) ((sp - frame_size) & ~7UL);
-
-} /* end get_sigframe() */
-
-/*****************************************************************************/
-/*
- *
- */
-static int setup_frame(struct ksignal *ksig, sigset_t *set)
-{
- struct sigframe __user *frame;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- if (__put_user(sig, &frame->sig) < 0)
- return -EFAULT;
-
- if (setup_sigcontext(&frame->sc, set->sig[0]))
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- if (__copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask)))
- return -EFAULT;
- }
-
- /* Set up to return from userspace. If provided, use a stub
- * already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode) < 0)
- return -EFAULT;
- }
- else {
- /* Set up the following code on the stack:
- * setlos #__NR_sigreturn,gr7
- * tira gr0,0
- */
- if (__put_user((__sigrestore_t)frame->retcode, &frame->pretcode) ||
- __put_user(0x8efc0000|__NR_sigreturn, &frame->retcode[0]) ||
- __put_user(0xc0700000, &frame->retcode[1]))
- return -EFAULT;
-
- flush_icache_range((unsigned long) frame->retcode,
- (unsigned long) (frame->retcode + 2));
- }
-
- /* Set up registers for the signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor __user *) ksig->ka.sa.sa_handler;
- struct fdpic_func_descriptor desc;
- if (copy_from_user(&desc, funcptr, sizeof(desc)))
- return -EFAULT;
- __frame->pc = desc.text;
- __frame->gr15 = desc.GOT;
- } else {
- __frame->pc = (unsigned long) ksig->ka.sa.sa_handler;
- __frame->gr15 = 0;
- }
-
- __frame->sp = (unsigned long) frame;
- __frame->lr = (unsigned long) &frame->retcode;
- __frame->gr8 = sig;
-
-#if DEBUG_SIG
- printk("SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
- sig, current->comm, current->pid, frame, __frame->pc,
- frame->pretcode);
-#endif
-
- return 0;
-} /* end setup_frame() */
-
-/*****************************************************************************/
-/*
- *
- */
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set)
-{
- struct rt_sigframe __user *frame;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- if (__put_user(sig, &frame->sig) ||
- __put_user(&frame->info, &frame->pinfo) ||
- __put_user(&frame->uc, &frame->puc))
- return -EFAULT;
-
- if (copy_siginfo_to_user(&frame->info, &ksig->info))
- return -EFAULT;
-
- /* Create the ucontext. */
- if (__put_user(0, &frame->uc.uc_flags) ||
- __put_user(NULL, &frame->uc.uc_link) ||
- __save_altstack(&frame->uc.uc_stack, __frame->sp))
- return -EFAULT;
-
- if (setup_sigcontext(&frame->uc.uc_mcontext, set->sig[0]))
- return -EFAULT;
-
- if (__copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)))
- return -EFAULT;
-
- /* Set up to return from userspace. If provided, use a stub
- * already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode))
- return -EFAULT;
- }
- else {
- /* Set up the following code on the stack:
- * setlos #__NR_sigreturn,gr7
- * tira gr0,0
- */
- if (__put_user((__sigrestore_t)frame->retcode, &frame->pretcode) ||
- __put_user(0x8efc0000|__NR_rt_sigreturn, &frame->retcode[0]) ||
- __put_user(0xc0700000, &frame->retcode[1]))
- return -EFAULT;
-
- flush_icache_range((unsigned long) frame->retcode,
- (unsigned long) (frame->retcode + 2));
- }
-
- /* Set up registers for signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor __user *) ksig->ka.sa.sa_handler;
- struct fdpic_func_descriptor desc;
- if (copy_from_user(&desc, funcptr, sizeof(desc)))
- return -EFAULT;
- __frame->pc = desc.text;
- __frame->gr15 = desc.GOT;
- } else {
- __frame->pc = (unsigned long) ksig->ka.sa.sa_handler;
- __frame->gr15 = 0;
- }
-
- __frame->sp = (unsigned long) frame;
- __frame->lr = (unsigned long) &frame->retcode;
- __frame->gr8 = sig;
- __frame->gr9 = (unsigned long) &frame->info;
-
-#if DEBUG_SIG
- printk("SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
- sig, current->comm, current->pid, frame, __frame->pc,
- frame->pretcode);
-#endif
- return 0;
-
-} /* end setup_rt_frame() */
-
-/*****************************************************************************/
-/*
- * OK, we're invoking a handler
- */
-static void handle_signal(struct ksignal *ksig)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Are we from a system call? */
- if (__frame->syscallno != -1) {
- /* If so, check system call restarting.. */
- switch (__frame->gr8) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- __frame->gr8 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- __frame->gr8 = -EINTR;
- break;
- }
-
- /* fallthrough */
- case -ERESTARTNOINTR:
- __frame->gr8 = __frame->orig_gr8;
- __frame->pc -= 4;
- }
- __frame->syscallno = -1;
- }
-
- /* Set up the stack frame */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset);
- else
- ret = setup_frame(ksig, oldset);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-} /* end handle_signal() */
-
-/*****************************************************************************/
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- */
-static void do_signal(void)
-{
- struct ksignal ksig;
-
- if (get_signal(&ksig)) {
- handle_signal(&ksig);
- return;
- }
-
- /* Did we come from a system call? */
- if (__frame->syscallno != -1) {
- /* Restart the system call - no handlers present */
- switch (__frame->gr8) {
- case -ERESTARTNOHAND:
- case -ERESTARTSYS:
- case -ERESTARTNOINTR:
- __frame->gr8 = __frame->orig_gr8;
- __frame->pc -= 4;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- __frame->gr7 = __NR_restart_syscall;
- __frame->pc -= 4;
- break;
- }
- __frame->syscallno = -1;
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-} /* end do_signal() */
-
-/*****************************************************************************/
-/*
- * notification of userspace execution resumption
- * - triggered by the TIF_WORK_MASK flags
- */
-asmlinkage void do_notify_resume(__u32 thread_info_flags)
-{
- /* pending single-step? */
- if (thread_info_flags & _TIF_SINGLESTEP)
- clear_thread_flag(TIF_SINGLESTEP);
-
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal();
-
- /* deal with notification on about to resume userspace execution */
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(__frame);
- }
-
-} /* end do_notify_resume() */
diff --git a/arch/frv/kernel/sleep.S b/arch/frv/kernel/sleep.S
deleted file mode 100644
index f67bf73cd2cc..000000000000
--- a/arch/frv/kernel/sleep.S
+++ /dev/null
@@ -1,373 +0,0 @@
-/* sleep.S: power saving mode entry
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Woodhouse (dwmw2@infradead.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <asm/spr-regs.h>
-
-#define __addr_MASK 0xfeff9820 /* interrupt controller mask */
-
-#define __addr_FR55X_DRCN 0xfeff0218 /* Address of DRCN register */
-#define FR55X_DSTS_OFFSET -4 /* Offset from DRCN to DSTS */
-#define FR55X_SDRAMC_DSTS_SSI 0x00000002 /* indicates that the SDRAM is in self-refresh mode */
-
-#define __addr_FR4XX_DRCN 0xfe000430 /* Address of DRCN register */
-#define FR4XX_DSTS_OFFSET -8 /* Offset from DRCN to DSTS */
-#define FR4XX_SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
-
-#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
-
- .section .bss
- .balign 8
- .globl __sleep_save_area
-__sleep_save_area:
- .space 16
-
-
- .text
- .balign 4
-
-.macro li v r
- sethi.p %hi(\v),\r
- setlo %lo(\v),\r
-.endm
-
-#ifdef CONFIG_PM
-###############################################################################
-#
-# CPU suspension routine
-# - void frv_cpu_suspend(unsigned long pdm_mode)
-#
-###############################################################################
- .globl frv_cpu_suspend
- .type frv_cpu_suspend,@function
-frv_cpu_suspend:
-
- #----------------------------------------------------
- # save hsr0, psr, isr, and lr for resume code
- #----------------------------------------------------
- li __sleep_save_area,gr11
-
- movsg hsr0,gr4
- movsg psr,gr5
- movsg isr,gr6
- movsg lr,gr7
- stdi gr4,@(gr11,#0)
- stdi gr6,@(gr11,#8)
-
- # store the return address from sleep in GR14, and its complement in GR13 as a check
- li __ramboot_resume,gr14
-#ifdef CONFIG_MMU
- # Resume via RAMBOOT# will turn MMU off, so bootloader needs a physical address.
- sethi.p %hi(__page_offset),gr13
- setlo %lo(__page_offset),gr13
- sub gr14,gr13,gr14
-#endif
- not gr14,gr13
-
- #----------------------------------------------------
- # preload and lock into icache that code which may have to run
- # when dram is in self-refresh state.
- #----------------------------------------------------
- movsg hsr0, gr3
- li HSR0_ICE,gr4
- or gr3,gr4,gr3
- movgs gr3,hsr0
- or gr3,gr8,gr7 // add the sleep bits for later
-
- li #__icache_lock_start,gr3
- li #__icache_lock_end,gr4
-1: icpl gr3,gr0,#1
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- # disable exceptions
- movsg psr,gr8
- andi.p gr8,#~PSR_PIL,gr8
- andi gr8,~PSR_ET,gr8
- movgs gr8,psr
- ori gr8,#PSR_ET,gr8
-
- srli gr8,#28,gr4
- subicc gr4,#3,gr0,icc0
- beq icc0,#0,1f
- # FR4xx
- li __addr_FR4XX_DRCN,gr4
- li FR4XX_SDRAMC_DSTS_SSI,gr5
- li FR4XX_DSTS_OFFSET,gr6
- bra __icache_lock_start
-1:
- # FR5xx
- li __addr_FR55X_DRCN,gr4
- li FR55X_SDRAMC_DSTS_SSI,gr5
- li FR55X_DSTS_OFFSET,gr6
- bra __icache_lock_start
-
- .size frv_cpu_suspend, .-frv_cpu_suspend
-
-#
-# the final part of the sleep sequence...
-# - we want it to be be cacheline aligned so we can lock it into the icache easily
-# On entry: gr7 holds desired hsr0 sleep value
-# gr8 holds desired psr sleep value
-#
- .balign L1_CACHE_BYTES
- .type __icache_lock_start,@function
-__icache_lock_start:
-
- #----------------------------------------------------
- # put SDRAM in self-refresh mode
- #----------------------------------------------------
-
- # Flush all data in the cache using the DCEF instruction.
- dcef @(gr0,gr0),#1
-
- # Stop DMAC transfer
-
- # Execute dummy load from SDRAM
- ldi @(gr11,#0),gr11
-
- # put the SDRAM into self-refresh mode
- ld @(gr4,gr0),gr11
- ori gr11,#SDRAMC_DRCN_SR,gr11
- st gr11,@(gr4,gr0)
- membar
-
- # wait for SDRAM to reach self-refresh mode
-1: ld @(gr4,gr6),gr11
- andcc gr11,gr5,gr11,icc0
- beq icc0,#0,1b
-
- # Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
- # Set the clock mode (CLKC register) as required.
- # - At this time, also set the CLKC register P0 bit.
-
- # Set the HSR0 register PDM field.
- movgs gr7,hsr0
-
- # Execute NOP 32 times.
- .rept 32
- nop
- .endr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # Release the interrupt mask setting of the MASK register of the
- # interrupt controller if necessary.
- sti gr10,@(gr9,#0)
- membar
-#endif
-
- # Set the PSR register ET bit to 1 to enable interrupts.
- movgs gr8,psr
-
- ###################################################
- # this is only reached if waking up via interrupt
- ###################################################
-
- # Execute NOP 32 times.
- .rept 32
- nop
- .endr
-
- #----------------------------------------------------
- # wake SDRAM from self-refresh mode
- #----------------------------------------------------
- ld @(gr4,gr0),gr11
- andi gr11,#~SDRAMC_DRCN_SR,gr11
- st gr11,@(gr4,gr0)
- membar
-2:
- ld @(gr4,gr6),gr11 // Wait for it to come back...
- andcc gr11,gr5,gr0,icc0
- bne icc0,0,2b
-
- # wait for the SDRAM to stabilise
- li 0x0100000,gr3
-3: subicc gr3,#1,gr3,icc0
- bne icc0,#0,3b
-
- # now that DRAM is back, this is the end of the code which gets
- # locked in icache.
-__icache_lock_end:
- .size __icache_lock_start, .-__icache_lock_start
-
- # Fall-through to the RAMBOOT# wakeup path
-
-###############################################################################
-#
-# resume from suspend re-entry point reached via RAMBOOT# and bootloader
-#
-###############################################################################
-__ramboot_resume:
-
- #----------------------------------------------------
- # restore hsr0, psr, isr, and leave saved lr in gr7
- #----------------------------------------------------
- li __sleep_save_area,gr11
-#ifdef CONFIG_MMU
- movsg hsr0,gr4
- sethi.p %hi(HSR0_EXMMU),gr3
- setlo %lo(HSR0_EXMMU),gr3
- andcc gr3,gr4,gr0,icc0
- bne icc0,#0,2f
-
- # need to use physical address
- sethi.p %hi(__page_offset),gr3
- setlo %lo(__page_offset),gr3
- sub gr11,gr3,gr11
-
- # flush all tlb entries
- setlos #64,gr4
- setlos.p #PAGE_SIZE,gr5
- setlos #0,gr6
-1:
- tlbpr gr6,gr0,#6,#0
- subicc.p gr4,#1,gr4,icc0
- add gr6,gr5,gr6
- bne icc0,#2,1b
-
- # need a temporary mapping for the current physical address we are
- # using between time MMU is enabled and jump to virtual address is
- # made.
- sethi.p %hi(0x00000000),gr4
- setlo %lo(0x00000000),gr4 ; physical address
- setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr5
- or gr4,gr5,gr5
-
- movsg cxnr,gr13
- or gr4,gr13,gr4
-
- movgs gr4,iamlr1 ; mapped from real address 0
- movgs gr5,iampr1 ; cached kernel memory at 0x00000000
-2:
-#endif
-
- lddi @(gr11,#0),gr4 ; hsr0, psr
- lddi @(gr11,#8),gr6 ; isr, lr
- movgs gr4,hsr0
- bar
-
-#ifdef CONFIG_MMU
- sethi.p %hi(1f),gr11
- setlo %lo(1f),gr11
- jmpl @(gr11,gr0)
-1:
- movgs gr0,iampr1 ; get rid of temporary mapping
-#endif
- movgs gr5,psr
- movgs gr6,isr
-
- #----------------------------------------------------
- # unlock the icache which was locked before going to sleep
- #----------------------------------------------------
- li __icache_lock_start,gr3
- li __icache_lock_end,gr4
-1: icul gr3
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- #----------------------------------------------------
- # back to business as usual
- #----------------------------------------------------
- jmpl @(gr7,gr0) ;
-
-#endif /* CONFIG_PM */
-
-###############################################################################
-#
-# CPU core sleep mode routine
-#
-###############################################################################
- .globl frv_cpu_core_sleep
- .type frv_cpu_core_sleep,@function
-frv_cpu_core_sleep:
-
- # Preload into icache.
- li #__core_sleep_icache_lock_start,gr3
- li #__core_sleep_icache_lock_end,gr4
-
-1: icpl gr3,gr0,#1
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- bra __core_sleep_icache_lock_start
-
- .balign L1_CACHE_BYTES
-__core_sleep_icache_lock_start:
-
- # (1) Set the PSR register ET bit to 0 to disable interrupts.
- movsg psr,gr8
- andi.p gr8,#~(PSR_PIL),gr8
- andi gr8,#~(PSR_ET),gr4
- movgs gr4,psr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (2) Set '1' to all bits in the MASK register of the interrupt
- # controller and mask interrupts.
- sethi.p %hi(__addr_MASK),gr9
- setlo %lo(__addr_MASK),gr9
- sethi.p %hi(0xffff0000),gr4
- setlo %lo(0xffff0000),gr4
- ldi @(gr9,#0),gr10
- sti gr4,@(gr9,#0)
-#endif
- # (3) Flush all data in the cache using the DCEF instruction.
- dcef @(gr0,gr0),#1
-
- # (4) Execute the memory barrier instruction
- membar
-
- # (5) Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
- # (6) Set the clock mode (CLKC register) as required.
- # - At this time, also set the CLKC register P0 bit.
- # (7) Set the HSR0 register PDM field to 001 .
- movsg hsr0,gr4
- ori gr4,HSR0_PDM_CORE_SLEEP,gr4
- movgs gr4,hsr0
-
- # (8) Execute NOP 32 times.
- .rept 32
- nop
- .endr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (9) Release the interrupt mask setting of the MASK register of the
- # interrupt controller if necessary.
- sti gr10,@(gr9,#0)
- membar
-#endif
-
- # (10) Set the PSR register ET bit to 1 to enable interrupts.
- movgs gr8,psr
-
-__core_sleep_icache_lock_end:
-
- # Unlock from icache
- li __core_sleep_icache_lock_start,gr3
- li __core_sleep_icache_lock_end,gr4
-1: icul gr3
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- bralr
-
- .size frv_cpu_core_sleep, .-frv_cpu_core_sleep
diff --git a/arch/frv/kernel/switch_to.S b/arch/frv/kernel/switch_to.S
deleted file mode 100644
index b06668670fcc..000000000000
--- a/arch/frv/kernel/switch_to.S
+++ /dev/null
@@ -1,489 +0,0 @@
-###############################################################################
-#
-# switch_to.S: context switch operation
-#
-# Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; either version
-# 2 of the License, or (at your option) any later version.
-#
-###############################################################################
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/processor.h>
-#include <asm/registers.h>
-#include <asm/spr-regs.h>
-
-.macro LEDS val
- setlos #~\val,gr27
- st gr27,@(gr30,gr0)
- membar
- dcf @(gr30,gr0)
-.endm
-
- .section .sdata
- .balign 8
-
- # address of frame 0 (userspace) on current kernel stack
- .globl __kernel_frame0_ptr
-__kernel_frame0_ptr:
- .long init_thread_union + THREAD_SIZE - FRV_FRAME0_SIZE
-
- # address of current task
- .globl __kernel_current_task
-__kernel_current_task:
- .long init_task
-
- .section .text
- .balign 4
-
-###############################################################################
-#
-# struct task_struct *__switch_to(struct thread_struct *prev_thread,
-# struct thread_struct *next_thread,
-# struct task_struct *prev)
-#
-###############################################################################
- .globl __switch_to
-__switch_to:
- # save outgoing process's context
- sethi.p %hi(__switch_back),gr13
- setlo %lo(__switch_back),gr13
- movsg lr,gr12
-
- stdi gr28,@(gr8,#__THREAD_FRAME)
- sti sp ,@(gr8,#__THREAD_SP)
- sti fp ,@(gr8,#__THREAD_FP)
- stdi gr12,@(gr8,#__THREAD_LR)
- stdi gr16,@(gr8,#__THREAD_GR(16))
- stdi gr18,@(gr8,#__THREAD_GR(18))
- stdi gr20,@(gr8,#__THREAD_GR(20))
- stdi gr22,@(gr8,#__THREAD_GR(22))
- stdi gr24,@(gr8,#__THREAD_GR(24))
- stdi.p gr26,@(gr8,#__THREAD_GR(26))
-
- or gr8,gr8,gr22
- ldi.p @(gr8,#__THREAD_USER),gr8
- call save_user_regs
- or gr22,gr22,gr8
-
- # retrieve the new context
- sethi.p %hi(__kernel_frame0_ptr),gr6
- setlo %lo(__kernel_frame0_ptr),gr6
- movsg psr,gr4
-
- lddi.p @(gr9,#__THREAD_FRAME),gr10
- or gr10,gr10,gr27 ; save prev for the return value
-
- ldi @(gr11,#4),gr19 ; get new_current->thread_info
-
- lddi @(gr9,#__THREAD_SP),gr12
- ldi @(gr9,#__THREAD_LR),gr14
- ldi @(gr9,#__THREAD_PC),gr18
- ldi.p @(gr9,#__THREAD_FRAME0),gr7
-
- # actually switch kernel contexts with ordinary exceptions disabled
- andi gr4,#~PSR_ET,gr5
- movgs gr5,psr
-
- or.p gr10,gr0,gr28 ; set __frame
- or gr11,gr0,gr29 ; set __current
- or.p gr12,gr0,sp
- or gr13,gr0,fp
- or gr19,gr0,gr15 ; set __current_thread_info
-
- sti gr7,@(gr6,#0) ; set __kernel_frame0_ptr
- sti gr29,@(gr6,#4) ; set __kernel_current_task
-
- movgs gr14,lr
- bar
-
- # jump to __switch_back or ret_from_fork as appropriate
- # - move prev to GR8
- movgs gr4,psr
- jmpl.p @(gr18,gr0)
- or gr27,gr27,gr8
-
-###############################################################################
-#
-# restore incoming process's context
-# - on entry:
-# - SP, FP, LR, GR15, GR28 and GR29 will have been set up appropriately
-# - GR8 will point to the outgoing task_struct
-# - GR9 will point to the incoming thread_struct
-#
-###############################################################################
-__switch_back:
- lddi @(gr9,#__THREAD_GR(16)),gr16
- lddi @(gr9,#__THREAD_GR(18)),gr18
- lddi @(gr9,#__THREAD_GR(20)),gr20
- lddi @(gr9,#__THREAD_GR(22)),gr22
- lddi @(gr9,#__THREAD_GR(24)),gr24
- lddi @(gr9,#__THREAD_GR(26)),gr26
-
- # fall through into restore_user_regs()
- ldi.p @(gr9,#__THREAD_USER),gr8
- or gr8,gr8,gr9
-
-###############################################################################
-#
-# restore extra general regs and FP/Media regs
-# - void *restore_user_regs(const struct user_context *target, void *retval)
-# - on entry:
-# - GR8 will point to the user context to swap in
-# - GR9 will contain the value to be returned in GR8 (prev task on context switch)
-#
-###############################################################################
- .globl restore_user_regs
-restore_user_regs:
- movsg hsr0,gr6
- ori gr6,#HSR0_GRHE|HSR0_FRLE|HSR0_FRHE,gr6
- movgs gr6,hsr0
- movsg hsr0,gr6
-
- movsg psr,gr7
- ori gr7,#PSR_EF|PSR_EM,gr7
- movgs gr7,psr
- movsg psr,gr7
- srli gr7,#24,gr7
- bar
-
- lddi @(gr8,#__FPMEDIA_MSR(0)),gr4
-
- movgs gr4,msr0
- movgs gr5,msr1
-
- lddfi @(gr8,#__FPMEDIA_ACC(0)),fr16
- lddfi @(gr8,#__FPMEDIA_ACC(2)),fr18
- ldbfi @(gr8,#__FPMEDIA_ACCG(0)),fr20
- ldbfi @(gr8,#__FPMEDIA_ACCG(1)),fr21
- ldbfi @(gr8,#__FPMEDIA_ACCG(2)),fr22
- ldbfi @(gr8,#__FPMEDIA_ACCG(3)),fr23
-
- mwtacc fr16,acc0
- mwtacc fr17,acc1
- mwtacc fr18,acc2
- mwtacc fr19,acc3
- mwtaccg fr20,accg0
- mwtaccg fr21,accg1
- mwtaccg fr22,accg2
- mwtaccg fr23,accg3
-
- # some CPUs have extra ACCx and ACCGx regs and maybe FSRx regs
- subicc.p gr7,#0x50,gr0,icc0
- subicc gr7,#0x31,gr0,icc1
- beq icc0,#0,__restore_acc_fr451
- beq icc1,#0,__restore_acc_fr555
-__restore_acc_cont:
-
- # some CPU's have GR32-GR63
- setlos #HSR0_FRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__restore_skip_gr32_gr63
-
- lddi @(gr8,#__INT_GR(32)),gr32
- lddi @(gr8,#__INT_GR(34)),gr34
- lddi @(gr8,#__INT_GR(36)),gr36
- lddi @(gr8,#__INT_GR(38)),gr38
- lddi @(gr8,#__INT_GR(40)),gr40
- lddi @(gr8,#__INT_GR(42)),gr42
- lddi @(gr8,#__INT_GR(44)),gr44
- lddi @(gr8,#__INT_GR(46)),gr46
- lddi @(gr8,#__INT_GR(48)),gr48
- lddi @(gr8,#__INT_GR(50)),gr50
- lddi @(gr8,#__INT_GR(52)),gr52
- lddi @(gr8,#__INT_GR(54)),gr54
- lddi @(gr8,#__INT_GR(56)),gr56
- lddi @(gr8,#__INT_GR(58)),gr58
- lddi @(gr8,#__INT_GR(60)),gr60
- lddi @(gr8,#__INT_GR(62)),gr62
-__restore_skip_gr32_gr63:
-
- # all CPU's have FR0-FR31
- lddfi @(gr8,#__FPMEDIA_FR( 0)),fr0
- lddfi @(gr8,#__FPMEDIA_FR( 2)),fr2
- lddfi @(gr8,#__FPMEDIA_FR( 4)),fr4
- lddfi @(gr8,#__FPMEDIA_FR( 6)),fr6
- lddfi @(gr8,#__FPMEDIA_FR( 8)),fr8
- lddfi @(gr8,#__FPMEDIA_FR(10)),fr10
- lddfi @(gr8,#__FPMEDIA_FR(12)),fr12
- lddfi @(gr8,#__FPMEDIA_FR(14)),fr14
- lddfi @(gr8,#__FPMEDIA_FR(16)),fr16
- lddfi @(gr8,#__FPMEDIA_FR(18)),fr18
- lddfi @(gr8,#__FPMEDIA_FR(20)),fr20
- lddfi @(gr8,#__FPMEDIA_FR(22)),fr22
- lddfi @(gr8,#__FPMEDIA_FR(24)),fr24
- lddfi @(gr8,#__FPMEDIA_FR(26)),fr26
- lddfi @(gr8,#__FPMEDIA_FR(28)),fr28
- lddfi.p @(gr8,#__FPMEDIA_FR(30)),fr30
-
- # some CPU's have FR32-FR63
- setlos #HSR0_FRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__restore_skip_fr32_fr63
-
- lddfi @(gr8,#__FPMEDIA_FR(32)),fr32
- lddfi @(gr8,#__FPMEDIA_FR(34)),fr34
- lddfi @(gr8,#__FPMEDIA_FR(36)),fr36
- lddfi @(gr8,#__FPMEDIA_FR(38)),fr38
- lddfi @(gr8,#__FPMEDIA_FR(40)),fr40
- lddfi @(gr8,#__FPMEDIA_FR(42)),fr42
- lddfi @(gr8,#__FPMEDIA_FR(44)),fr44
- lddfi @(gr8,#__FPMEDIA_FR(46)),fr46
- lddfi @(gr8,#__FPMEDIA_FR(48)),fr48
- lddfi @(gr8,#__FPMEDIA_FR(50)),fr50
- lddfi @(gr8,#__FPMEDIA_FR(52)),fr52
- lddfi @(gr8,#__FPMEDIA_FR(54)),fr54
- lddfi @(gr8,#__FPMEDIA_FR(56)),fr56
- lddfi @(gr8,#__FPMEDIA_FR(58)),fr58
- lddfi @(gr8,#__FPMEDIA_FR(60)),fr60
- lddfi @(gr8,#__FPMEDIA_FR(62)),fr62
-__restore_skip_fr32_fr63:
-
- lddi @(gr8,#__FPMEDIA_FNER(0)),gr4
- movsg fner0,gr4
- movsg fner1,gr5
- or.p gr9,gr9,gr8
- bralr
-
- # the FR451 also has ACC8-11/ACCG8-11 regs (but not 4-7...)
-__restore_acc_fr451:
- lddfi @(gr8,#__FPMEDIA_ACC(4)),fr16
- lddfi @(gr8,#__FPMEDIA_ACC(6)),fr18
- ldbfi @(gr8,#__FPMEDIA_ACCG(4)),fr20
- ldbfi @(gr8,#__FPMEDIA_ACCG(5)),fr21
- ldbfi @(gr8,#__FPMEDIA_ACCG(6)),fr22
- ldbfi @(gr8,#__FPMEDIA_ACCG(7)),fr23
-
- mwtacc fr16,acc8
- mwtacc fr17,acc9
- mwtacc fr18,acc10
- mwtacc fr19,acc11
- mwtaccg fr20,accg8
- mwtaccg fr21,accg9
- mwtaccg fr22,accg10
- mwtaccg fr23,accg11
- bra __restore_acc_cont
-
- # the FR555 also has ACC4-7/ACCG4-7 regs and an FSR0 reg
-__restore_acc_fr555:
- lddfi @(gr8,#__FPMEDIA_ACC(4)),fr16
- lddfi @(gr8,#__FPMEDIA_ACC(6)),fr18
- ldbfi @(gr8,#__FPMEDIA_ACCG(4)),fr20
- ldbfi @(gr8,#__FPMEDIA_ACCG(5)),fr21
- ldbfi @(gr8,#__FPMEDIA_ACCG(6)),fr22
- ldbfi @(gr8,#__FPMEDIA_ACCG(7)),fr23
-
- mnop.p
- mwtacc fr16,acc4
- mnop.p
- mwtacc fr17,acc5
- mnop.p
- mwtacc fr18,acc6
- mnop.p
- mwtacc fr19,acc7
- mnop.p
- mwtaccg fr20,accg4
- mnop.p
- mwtaccg fr21,accg5
- mnop.p
- mwtaccg fr22,accg6
- mnop.p
- mwtaccg fr23,accg7
-
- ldi @(gr8,#__FPMEDIA_FSR(0)),gr4
- movgs gr4,fsr0
-
- bra __restore_acc_cont
-
-
-###############################################################################
-#
-# save extra general regs and FP/Media regs
-# - void save_user_regs(struct user_context *target)
-#
-###############################################################################
- .globl save_user_regs
-save_user_regs:
- movsg hsr0,gr6
- ori gr6,#HSR0_GRHE|HSR0_FRLE|HSR0_FRHE,gr6
- movgs gr6,hsr0
- movsg hsr0,gr6
-
- movsg psr,gr7
- ori gr7,#PSR_EF|PSR_EM,gr7
- movgs gr7,psr
- movsg psr,gr7
- srli gr7,#24,gr7
- bar
-
- movsg fner0,gr4
- movsg fner1,gr5
- stdi.p gr4,@(gr8,#__FPMEDIA_FNER(0))
-
- # some CPU's have GR32-GR63
- setlos #HSR0_GRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__save_skip_gr32_gr63
-
- stdi gr32,@(gr8,#__INT_GR(32))
- stdi gr34,@(gr8,#__INT_GR(34))
- stdi gr36,@(gr8,#__INT_GR(36))
- stdi gr38,@(gr8,#__INT_GR(38))
- stdi gr40,@(gr8,#__INT_GR(40))
- stdi gr42,@(gr8,#__INT_GR(42))
- stdi gr44,@(gr8,#__INT_GR(44))
- stdi gr46,@(gr8,#__INT_GR(46))
- stdi gr48,@(gr8,#__INT_GR(48))
- stdi gr50,@(gr8,#__INT_GR(50))
- stdi gr52,@(gr8,#__INT_GR(52))
- stdi gr54,@(gr8,#__INT_GR(54))
- stdi gr56,@(gr8,#__INT_GR(56))
- stdi gr58,@(gr8,#__INT_GR(58))
- stdi gr60,@(gr8,#__INT_GR(60))
- stdi gr62,@(gr8,#__INT_GR(62))
-__save_skip_gr32_gr63:
-
- # all CPU's have FR0-FR31
- stdfi fr0 ,@(gr8,#__FPMEDIA_FR( 0))
- stdfi fr2 ,@(gr8,#__FPMEDIA_FR( 2))
- stdfi fr4 ,@(gr8,#__FPMEDIA_FR( 4))
- stdfi fr6 ,@(gr8,#__FPMEDIA_FR( 6))
- stdfi fr8 ,@(gr8,#__FPMEDIA_FR( 8))
- stdfi fr10,@(gr8,#__FPMEDIA_FR(10))
- stdfi fr12,@(gr8,#__FPMEDIA_FR(12))
- stdfi fr14,@(gr8,#__FPMEDIA_FR(14))
- stdfi fr16,@(gr8,#__FPMEDIA_FR(16))
- stdfi fr18,@(gr8,#__FPMEDIA_FR(18))
- stdfi fr20,@(gr8,#__FPMEDIA_FR(20))
- stdfi fr22,@(gr8,#__FPMEDIA_FR(22))
- stdfi fr24,@(gr8,#__FPMEDIA_FR(24))
- stdfi fr26,@(gr8,#__FPMEDIA_FR(26))
- stdfi fr28,@(gr8,#__FPMEDIA_FR(28))
- stdfi.p fr30,@(gr8,#__FPMEDIA_FR(30))
-
- # some CPU's have FR32-FR63
- setlos #HSR0_FRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__save_skip_fr32_fr63
-
- stdfi fr32,@(gr8,#__FPMEDIA_FR(32))
- stdfi fr34,@(gr8,#__FPMEDIA_FR(34))
- stdfi fr36,@(gr8,#__FPMEDIA_FR(36))
- stdfi fr38,@(gr8,#__FPMEDIA_FR(38))
- stdfi fr40,@(gr8,#__FPMEDIA_FR(40))
- stdfi fr42,@(gr8,#__FPMEDIA_FR(42))
- stdfi fr44,@(gr8,#__FPMEDIA_FR(44))
- stdfi fr46,@(gr8,#__FPMEDIA_FR(46))
- stdfi fr48,@(gr8,#__FPMEDIA_FR(48))
- stdfi fr50,@(gr8,#__FPMEDIA_FR(50))
- stdfi fr52,@(gr8,#__FPMEDIA_FR(52))
- stdfi fr54,@(gr8,#__FPMEDIA_FR(54))
- stdfi fr56,@(gr8,#__FPMEDIA_FR(56))
- stdfi fr58,@(gr8,#__FPMEDIA_FR(58))
- stdfi fr60,@(gr8,#__FPMEDIA_FR(60))
- stdfi fr62,@(gr8,#__FPMEDIA_FR(62))
-__save_skip_fr32_fr63:
-
- mrdacc acc0 ,fr4
- mrdacc acc1 ,fr5
-
- stdfi.p fr4 ,@(gr8,#__FPMEDIA_ACC(0))
-
- mrdacc acc2 ,fr6
- mrdacc acc3 ,fr7
-
- stdfi.p fr6 ,@(gr8,#__FPMEDIA_ACC(2))
-
- mrdaccg accg0,fr4
- stbfi.p fr4 ,@(gr8,#__FPMEDIA_ACCG(0))
-
- mrdaccg accg1,fr5
- stbfi.p fr5 ,@(gr8,#__FPMEDIA_ACCG(1))
-
- mrdaccg accg2,fr6
- stbfi.p fr6 ,@(gr8,#__FPMEDIA_ACCG(2))
-
- mrdaccg accg3,fr7
- stbfi fr7 ,@(gr8,#__FPMEDIA_ACCG(3))
-
- movsg msr0 ,gr4
- movsg msr1 ,gr5
-
- stdi gr4 ,@(gr8,#__FPMEDIA_MSR(0))
-
- # some CPUs have extra ACCx and ACCGx regs and maybe FSRx regs
- subicc.p gr7,#0x50,gr0,icc0
- subicc gr7,#0x31,gr0,icc1
- beq icc0,#0,__save_acc_fr451
- beq icc1,#0,__save_acc_fr555
-__save_acc_cont:
-
- lddfi @(gr8,#__FPMEDIA_FR(4)),fr4
- lddfi.p @(gr8,#__FPMEDIA_FR(6)),fr6
- bralr
-
- # the FR451 also has ACC8-11/ACCG8-11 regs (but not 4-7...)
-__save_acc_fr451:
- mrdacc acc8 ,fr4
- mrdacc acc9 ,fr5
-
- stdfi.p fr4 ,@(gr8,#__FPMEDIA_ACC(4))
-
- mrdacc acc10,fr6
- mrdacc acc11,fr7
-
- stdfi.p fr6 ,@(gr8,#__FPMEDIA_ACC(6))
-
- mrdaccg accg8,fr4
- stbfi.p fr4 ,@(gr8,#__FPMEDIA_ACCG(4))
-
- mrdaccg accg9,fr5
- stbfi.p fr5 ,@(gr8,#__FPMEDIA_ACCG(5))
-
- mrdaccg accg10,fr6
- stbfi.p fr6 ,@(gr8,#__FPMEDIA_ACCG(6))
-
- mrdaccg accg11,fr7
- stbfi fr7 ,@(gr8,#__FPMEDIA_ACCG(7))
- bra __save_acc_cont
-
- # the FR555 also has ACC4-7/ACCG4-7 regs and an FSR0 reg
-__save_acc_fr555:
- mnop.p
- mrdacc acc4 ,fr4
- mnop.p
- mrdacc acc5 ,fr5
-
- stdfi fr4 ,@(gr8,#__FPMEDIA_ACC(4))
-
- mnop.p
- mrdacc acc6 ,fr6
- mnop.p
- mrdacc acc7 ,fr7
-
- stdfi fr6 ,@(gr8,#__FPMEDIA_ACC(6))
-
- mnop.p
- mrdaccg accg4,fr4
- stbfi fr4 ,@(gr8,#__FPMEDIA_ACCG(4))
-
- mnop.p
- mrdaccg accg5,fr5
- stbfi fr5 ,@(gr8,#__FPMEDIA_ACCG(5))
-
- mnop.p
- mrdaccg accg6,fr6
- stbfi fr6 ,@(gr8,#__FPMEDIA_ACCG(6))
-
- mnop.p
- mrdaccg accg7,fr7
- stbfi fr7 ,@(gr8,#__FPMEDIA_ACCG(7))
-
- movsg fsr0 ,gr4
- sti gr4 ,@(gr8,#__FPMEDIA_FSR(0))
- bra __save_acc_cont
diff --git a/arch/frv/kernel/sys_frv.c b/arch/frv/kernel/sys_frv.c
deleted file mode 100644
index f80cc8b9bd45..000000000000
--- a/arch/frv/kernel/sys_frv.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* sys_frv.c: FRV arch-specific syscall wrappers
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/sys_m68k.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/syscalls.h>
-#include <linux/ipc.h>
-
-#include <asm/setup.h>
-#include <linux/uaccess.h>
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long pgoff)
-{
- /* As with sparc32, make sure the shift for mmap2 is constant
- (12), no matter what PAGE_SIZE we have.... */
-
- /* But unlike sparc32, don't just silently break if we're
- trying to map something we can't */
- if (pgoff & ((1 << (PAGE_SHIFT - 12)) - 1))
- return -EINVAL;
-
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- pgoff >> (PAGE_SHIFT - 12));
-}
diff --git a/arch/frv/kernel/sysctl.c b/arch/frv/kernel/sysctl.c
deleted file mode 100644
index b54a64971cf1..000000000000
--- a/arch/frv/kernel/sysctl.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* sysctl.c: implementation of /proc/sys files relating to FRV specifically
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sysctl.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/uaccess.h>
-
-static const char frv_cache_wback[] = "wback";
-static const char frv_cache_wthru[] = "wthru";
-
-static void frv_change_dcache_mode(unsigned long newmode)
-{
- unsigned long flags, hsr0;
-
- local_irq_save(flags);
-
- hsr0 = __get_HSR(0);
- hsr0 &= ~HSR0_DCE;
- __set_HSR(0, hsr0);
-
- asm volatile(" dcef @(gr0,gr0),#1 \n"
- " membar \n"
- : : : "memory"
- );
-
- hsr0 = (hsr0 & ~HSR0_CBM) | newmode;
- __set_HSR(0, hsr0);
- hsr0 |= HSR0_DCE;
- __set_HSR(0, hsr0);
-
- local_irq_restore(flags);
-
- //printk("HSR0 now %08lx\n", hsr0);
-}
-
-/*****************************************************************************/
-/*
- * handle requests to dynamically switch the write caching mode delivered by /proc
- */
-static int procctl_frv_cachemode(struct ctl_table *table, int write,
- void __user *buffer, size_t *lenp,
- loff_t *ppos)
-{
- unsigned long hsr0;
- char buff[8];
- int len;
-
- len = *lenp;
-
- if (write) {
- /* potential state change */
- if (len <= 1 || len > sizeof(buff) - 1)
- return -EINVAL;
-
- if (copy_from_user(buff, buffer, len) != 0)
- return -EFAULT;
-
- if (buff[len - 1] == '\n')
- buff[len - 1] = '\0';
- else
- buff[len] = '\0';
-
- if (strcmp(buff, frv_cache_wback) == 0) {
- /* switch dcache into write-back mode */
- frv_change_dcache_mode(HSR0_CBM_COPY_BACK);
- return 0;
- }
-
- if (strcmp(buff, frv_cache_wthru) == 0) {
- /* switch dcache into write-through mode */
- frv_change_dcache_mode(HSR0_CBM_WRITE_THRU);
- return 0;
- }
-
- return -EINVAL;
- }
-
- /* read the state */
- if (*ppos > 0) {
- *lenp = 0;
- return 0;
- }
-
- hsr0 = __get_HSR(0);
- switch (hsr0 & HSR0_CBM) {
- case HSR0_CBM_WRITE_THRU:
- memcpy(buff, frv_cache_wthru, sizeof(frv_cache_wthru) - 1);
- buff[sizeof(frv_cache_wthru) - 1] = '\n';
- len = sizeof(frv_cache_wthru);
- break;
- default:
- memcpy(buff, frv_cache_wback, sizeof(frv_cache_wback) - 1);
- buff[sizeof(frv_cache_wback) - 1] = '\n';
- len = sizeof(frv_cache_wback);
- break;
- }
-
- if (len > *lenp)
- len = *lenp;
-
- if (copy_to_user(buffer, buff, len) != 0)
- return -EFAULT;
-
- *lenp = len;
- *ppos = len;
- return 0;
-
-} /* end procctl_frv_cachemode() */
-
-/*****************************************************************************/
-/*
- * permit the mm_struct the nominated process is using have its MMU context ID pinned
- */
-#ifdef CONFIG_MMU
-static int procctl_frv_pin_cxnr(struct ctl_table *table, int write,
- void __user *buffer, size_t *lenp,
- loff_t *ppos)
-{
- pid_t pid;
- char buff[16], *p;
- int len;
-
- len = *lenp;
-
- if (write) {
- /* potential state change */
- if (len <= 1 || len > sizeof(buff) - 1)
- return -EINVAL;
-
- if (copy_from_user(buff, buffer, len) != 0)
- return -EFAULT;
-
- if (buff[len - 1] == '\n')
- buff[len - 1] = '\0';
- else
- buff[len] = '\0';
-
- pid = simple_strtoul(buff, &p, 10);
- if (*p)
- return -EINVAL;
-
- return cxn_pin_by_pid(pid);
- }
-
- /* read the currently pinned CXN */
- if (*ppos > 0) {
- *lenp = 0;
- return 0;
- }
-
- len = snprintf(buff, sizeof(buff), "%d\n", cxn_pinned);
- if (len > *lenp)
- len = *lenp;
-
- if (copy_to_user(buffer, buff, len) != 0)
- return -EFAULT;
-
- *lenp = len;
- *ppos = len;
- return 0;
-
-} /* end procctl_frv_pin_cxnr() */
-#endif
-
-/*
- * FR-V specific sysctls
- */
-static struct ctl_table frv_table[] =
-{
- {
- .procname = "cache-mode",
- .data = NULL,
- .maxlen = 0,
- .mode = 0644,
- .proc_handler = procctl_frv_cachemode,
- },
-#ifdef CONFIG_MMU
- {
- .procname = "pin-cxnr",
- .data = NULL,
- .maxlen = 0,
- .mode = 0644,
- .proc_handler = procctl_frv_pin_cxnr
- },
-#endif
- {}
-};
-
-/*
- * Use a temporary sysctl number. Horrid, but will be cleaned up in 2.6
- * when all the PM interfaces exist nicely.
- */
-static struct ctl_table frv_dir_table[] =
-{
- {
- .procname = "frv",
- .mode = 0555,
- .child = frv_table
- },
- {}
-};
-
-/*
- * Initialize power interface
- */
-static int __init frv_sysctl_init(void)
-{
- register_sysctl_table(frv_dir_table);
- return 0;
-}
-
-__initcall(frv_sysctl_init);
diff --git a/arch/frv/kernel/time.c b/arch/frv/kernel/time.c
deleted file mode 100644
index 332e00bf9d06..000000000000
--- a/arch/frv/kernel/time.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* time.c: FRV arch-specific time handling
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/time.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/interrupt.h>
-#include <linux/profile.h>
-#include <linux/irq.h>
-#include <linux/mm.h>
-
-#include <asm/io.h>
-#include <asm/timer-regs.h>
-#include <asm/mb-regs.h>
-#include <asm/mb86943a.h>
-
-#include <linux/timex.h>
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-unsigned long __nongprelbss __clkin_clock_speed_HZ;
-unsigned long __nongprelbss __ext_bus_clock_speed_HZ;
-unsigned long __nongprelbss __res_bus_clock_speed_HZ;
-unsigned long __nongprelbss __sdram_clock_speed_HZ;
-unsigned long __nongprelbss __core_bus_clock_speed_HZ;
-unsigned long __nongprelbss __core_clock_speed_HZ;
-unsigned long __nongprelbss __dsu_clock_speed_HZ;
-unsigned long __nongprelbss __serial_clock_speed_HZ;
-unsigned long __delay_loops_MHz;
-
-static irqreturn_t timer_interrupt(int irq, void *dummy);
-
-static struct irqaction timer_irq = {
- .handler = timer_interrupt,
- .name = "timer",
-};
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-static irqreturn_t timer_interrupt(int irq, void *dummy)
-{
- profile_tick(CPU_PROFILING);
-
- xtime_update(1);
-
-#ifdef CONFIG_HEARTBEAT
- static unsigned short n;
- n++;
- __set_LEDS(n);
-#endif /* CONFIG_HEARTBEAT */
-
- update_process_times(user_mode(get_irq_regs()));
-
- return IRQ_HANDLED;
-}
-
-void time_divisor_init(void)
-{
- unsigned short base, pre, prediv;
-
- /* set the scheduling timer going */
- pre = 1;
- prediv = 4;
- base = __res_bus_clock_speed_HZ / pre / HZ / (1 << prediv);
-
- __set_TPRV(pre);
- __set_TxCKSL_DATA(0, prediv);
- __set_TCTR(TCTR_SC_CTR0 | TCTR_RL_RW_LH8 | TCTR_MODE_2);
- __set_TCSR_DATA(0, base & 0xff);
- __set_TCSR_DATA(0, base >> 8);
-}
-
-
-void read_persistent_clock(struct timespec *ts)
-{
- unsigned int year, mon, day, hour, min, sec;
-
- extern void arch_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
-
- /* FIX by dqg : Set to zero for platforms that don't have tod */
- /* without this time is undefined and can overflow time_t, causing */
- /* very strange errors */
- year = 1980;
- mon = day = 1;
- hour = min = sec = 0;
- arch_gettod (&year, &mon, &day, &hour, &min, &sec);
-
- if ((year += 1900) < 1970)
- year += 100;
- ts->tv_sec = mktime(year, mon, day, hour, min, sec);
- ts->tv_nsec = 0;
-}
-
-void time_init(void)
-{
- /* install scheduling interrupt handler */
- setup_irq(IRQ_CPU_TIMER0, &timer_irq);
-
- time_divisor_init();
-}
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
- return jiffies_64 * (1000000000 / HZ);
-}
diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c
deleted file mode 100644
index fb08ebe0dab4..000000000000
--- a/arch/frv/kernel/traps.c
+++ /dev/null
@@ -1,642 +0,0 @@
-/* traps.c: high-level exception handler for FR-V
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/types.h>
-#include <linux/user.h>
-#include <linux/string.h>
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/asm-offsets.h>
-#include <asm/setup.h>
-#include <asm/fpu.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/siginfo.h>
-#include <asm/unaligned.h>
-
-void show_backtrace(struct pt_regs *, unsigned long);
-
-extern asmlinkage void __break_hijack_kernel_event(void);
-
-/*****************************************************************************/
-/*
- * instruction access error
- */
-asmlinkage void insn_access_error(unsigned long esfr1, unsigned long epcr0, unsigned long esr0)
-{
- siginfo_t info;
-
- die_if_kernel("-- Insn Access Error --\n"
- "EPCR0 : %08lx\n"
- "ESR0 : %08lx\n",
- epcr0, esr0);
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = (void __user *) ((epcr0 & EPCR0_V) ? (epcr0 & EPCR0_PC) : __frame->pc);
-
- force_sig_info(info.si_signo, &info, current);
-} /* end insn_access_error() */
-
-/*****************************************************************************/
-/*
- * handler for:
- * - illegal instruction
- * - privileged instruction
- * - unsupported trap
- * - debug exceptions
- */
-asmlinkage void illegal_instruction(unsigned long esfr1, unsigned long epcr0, unsigned long esr0)
-{
- siginfo_t info;
-
- die_if_kernel("-- Illegal Instruction --\n"
- "EPCR0 : %08lx\n"
- "ESR0 : %08lx\n"
- "ESFR1 : %08lx\n",
- epcr0, esr0, esfr1);
-
- info.si_errno = 0;
- info.si_addr = (void __user *) ((epcr0 & EPCR0_V) ? (epcr0 & EPCR0_PC) : __frame->pc);
-
- switch (__frame->tbr & TBR_TT) {
- case TBR_TT_ILLEGAL_INSTR:
- info.si_signo = SIGILL;
- info.si_code = ILL_ILLOPC;
- break;
- case TBR_TT_PRIV_INSTR:
- info.si_signo = SIGILL;
- info.si_code = ILL_PRVOPC;
- break;
- case TBR_TT_TRAP2 ... TBR_TT_TRAP126:
- info.si_signo = SIGILL;
- info.si_code = ILL_ILLTRP;
- break;
- /* GDB uses "tira gr0, #1" as a breakpoint instruction. */
- case TBR_TT_TRAP1:
- case TBR_TT_BREAK:
- info.si_signo = SIGTRAP;
- info.si_code =
- (__frame->__status & REG__STATUS_STEPPED) ? TRAP_TRACE : TRAP_BRKPT;
- break;
- }
-
- force_sig_info(info.si_signo, &info, current);
-} /* end illegal_instruction() */
-
-/*****************************************************************************/
-/*
- * handle atomic operations with errors
- * - arguments in gr8, gr9, gr10
- * - original memory value placed in gr5
- * - replacement memory value placed in gr9
- */
-asmlinkage void atomic_operation(unsigned long esfr1, unsigned long epcr0,
- unsigned long esr0)
-{
- static DEFINE_SPINLOCK(atomic_op_lock);
- unsigned long x, y, z;
- unsigned long __user *p;
- mm_segment_t oldfs;
- siginfo_t info;
- int ret;
-
- y = 0;
- z = 0;
-
- oldfs = get_fs();
- if (!user_mode(__frame))
- set_fs(KERNEL_DS);
-
- switch (__frame->tbr & TBR_TT) {
- /* TIRA gr0,#120
- * u32 __atomic_user_cmpxchg32(u32 *ptr, u32 test, u32 new)
- */
- case TBR_TT_ATOMIC_CMPXCHG32:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
- y = __frame->gr10;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- if (z != x)
- goto done;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- if (z != x)
- goto done2;
-
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#121
- * u32 __atomic_kernel_xchg32(void *v, u32 new)
- */
- case TBR_TT_ATOMIC_XCHG32:
- p = (unsigned long __user *) __frame->gr8;
- y = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#122
- * ulong __atomic_kernel_XOR_return(ulong i, ulong *v)
- */
- case TBR_TT_ATOMIC_XOR:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = x ^ z;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#123
- * ulong __atomic_kernel_OR_return(ulong i, ulong *v)
- */
- case TBR_TT_ATOMIC_OR:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = x ^ z;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#124
- * ulong __atomic_kernel_AND_return(ulong i, ulong *v)
- */
- case TBR_TT_ATOMIC_AND:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = x & z;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#125
- * int __atomic_user_sub_return(atomic_t *v, int i)
- */
- case TBR_TT_ATOMIC_SUB:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = z - x;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#126
- * int __atomic_user_add_return(atomic_t *v, int i)
- */
- case TBR_TT_ATOMIC_ADD:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = z + x;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- default:
- BUG();
- }
-
-done2:
- spin_unlock_irq(&atomic_op_lock);
-done:
- if (!user_mode(__frame))
- set_fs(oldfs);
- __frame->gr5 = z;
- __frame->gr9 = y;
- return;
-
-error2:
- spin_unlock_irq(&atomic_op_lock);
-error:
- if (!user_mode(__frame))
- set_fs(oldfs);
- __frame->pc -= 4;
-
- die_if_kernel("-- Atomic Op Error --\n");
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = (void __user *) __frame->pc;
-
- force_sig_info(info.si_signo, &info, current);
-}
-
-/*****************************************************************************/
-/*
- *
- */
-asmlinkage void media_exception(unsigned long msr0, unsigned long msr1)
-{
- siginfo_t info;
-
- die_if_kernel("-- Media Exception --\n"
- "MSR0 : %08lx\n"
- "MSR1 : %08lx\n",
- msr0, msr1);
-
- info.si_signo = SIGFPE;
- info.si_code = FPE_MDAOVF;
- info.si_errno = 0;
- info.si_addr = (void __user *) __frame->pc;
-
- force_sig_info(info.si_signo, &info, current);
-} /* end media_exception() */
-
-/*****************************************************************************/
-/*
- * instruction or data access exception
- */
-asmlinkage void memory_access_exception(unsigned long esr0,
- unsigned long ear0,
- unsigned long epcr0)
-{
- siginfo_t info;
-
-#ifdef CONFIG_MMU
- if (fixup_exception(__frame))
- return;
-#endif
-
- die_if_kernel("-- Memory Access Exception --\n"
- "ESR0 : %08lx\n"
- "EAR0 : %08lx\n"
- "EPCR0 : %08lx\n",
- esr0, ear0, epcr0);
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = NULL;
-
- if ((esr0 & (ESRx_VALID | ESR0_EAV)) == (ESRx_VALID | ESR0_EAV))
- info.si_addr = (void __user *) ear0;
-
- force_sig_info(info.si_signo, &info, current);
-
-} /* end memory_access_exception() */
-
-/*****************************************************************************/
-/*
- * data access error
- * - double-word data load from CPU control area (0xFExxxxxx)
- * - read performed on inactive or self-refreshing SDRAM
- * - error notification from slave device
- * - misaligned address
- * - access to out of bounds memory region
- * - user mode accessing privileged memory region
- * - write to R/O memory region
- */
-asmlinkage void data_access_error(unsigned long esfr1, unsigned long esr15, unsigned long ear15)
-{
- siginfo_t info;
-
- die_if_kernel("-- Data Access Error --\n"
- "ESR15 : %08lx\n"
- "EAR15 : %08lx\n",
- esr15, ear15);
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = (void __user *)
- (((esr15 & (ESRx_VALID|ESR15_EAV)) == (ESRx_VALID|ESR15_EAV)) ? ear15 : 0);
-
- force_sig_info(info.si_signo, &info, current);
-} /* end data_access_error() */
-
-/*****************************************************************************/
-/*
- * data store error - should only happen if accessing inactive or self-refreshing SDRAM
- */
-asmlinkage void data_store_error(unsigned long esfr1, unsigned long esr15)
-{
- die_if_kernel("-- Data Store Error --\n"
- "ESR15 : %08lx\n",
- esr15);
- BUG();
-} /* end data_store_error() */
-
-/*****************************************************************************/
-/*
- *
- */
-asmlinkage void division_exception(unsigned long esfr1, unsigned long esr0, unsigned long isr)
-{
- siginfo_t info;
-
- die_if_kernel("-- Division Exception --\n"
- "ESR0 : %08lx\n"
- "ISR : %08lx\n",
- esr0, isr);
-
- info.si_signo = SIGFPE;
- info.si_code = FPE_INTDIV;
- info.si_errno = 0;
- info.si_addr = (void __user *) __frame->pc;
-
- force_sig_info(info.si_signo, &info, current);
-} /* end division_exception() */
-
-/*****************************************************************************/
-/*
- *
- */
-asmlinkage void compound_exception(unsigned long esfr1,
- unsigned long esr0, unsigned long esr14, unsigned long esr15,
- unsigned long msr0, unsigned long msr1)
-{
- die_if_kernel("-- Compound Exception --\n"
- "ESR0 : %08lx\n"
- "ESR15 : %08lx\n"
- "ESR15 : %08lx\n"
- "MSR0 : %08lx\n"
- "MSR1 : %08lx\n",
- esr0, esr14, esr15, msr0, msr1);
- BUG();
-} /* end compound_exception() */
-
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
-}
-
-void show_trace_task(struct task_struct *tsk)
-{
- printk("CONTEXT: stack=0x%lx frame=0x%p LR=0x%lx RET=0x%lx\n",
- tsk->thread.sp, tsk->thread.frame, tsk->thread.lr, tsk->thread.sched_lr);
-}
-
-static const char *regnames[] = {
- "PSR ", "ISR ", "CCR ", "CCCR",
- "LR ", "LCR ", "PC ", "_stt",
- "sys ", "GR8*", "GNE0", "GNE1",
- "IACH", "IACL",
- "TBR ", "SP ", "FP ", "GR3 ",
- "GR4 ", "GR5 ", "GR6 ", "GR7 ",
- "GR8 ", "GR9 ", "GR10", "GR11",
- "GR12", "GR13", "GR14", "GR15",
- "GR16", "GR17", "GR18", "GR19",
- "GR20", "GR21", "GR22", "GR23",
- "GR24", "GR25", "GR26", "GR27",
- "EFRM", "CURR", "GR30", "BFRM"
-};
-
-void show_regs(struct pt_regs *regs)
-{
- unsigned long *reg;
- int loop;
-
- printk("\n");
- show_regs_print_info(KERN_DEFAULT);
-
- printk("Frame: @%08lx [%s]\n",
- (unsigned long) regs,
- regs->psr & PSR_S ? "kernel" : "user");
-
- reg = (unsigned long *) regs;
- for (loop = 0; loop < NR_PT_REGS; loop++) {
- printk("%s %08lx", regnames[loop + 0], reg[loop + 0]);
-
- if (loop == NR_PT_REGS - 1 || loop % 5 == 4)
- printk("\n");
- else
- printk(" | ");
- }
-}
-
-void die_if_kernel(const char *str, ...)
-{
- char buffer[256];
- va_list va;
-
- if (user_mode(__frame))
- return;
-
- va_start(va, str);
- vsnprintf(buffer, sizeof(buffer), str, va);
- va_end(va);
-
- console_verbose();
- printk("\n===================================\n");
- printk("%s\n", buffer);
- show_backtrace(__frame, 0);
-
- __break_hijack_kernel_event();
- do_exit(SIGSEGV);
-}
-
-/*****************************************************************************/
-/*
- * dump the contents of an exception frame
- */
-static void show_backtrace_regs(struct pt_regs *frame)
-{
- unsigned long *reg;
- int loop;
-
- /* print the registers for this frame */
- printk("<-- %s Frame: @%p -->\n",
- frame->psr & PSR_S ? "Kernel Mode" : "User Mode",
- frame);
-
- reg = (unsigned long *) frame;
- for (loop = 0; loop < NR_PT_REGS; loop++) {
- printk("%s %08lx", regnames[loop + 0], reg[loop + 0]);
-
- if (loop == NR_PT_REGS - 1 || loop % 5 == 4)
- printk("\n");
- else
- printk(" | ");
- }
-
- printk("--------\n");
-} /* end show_backtrace_regs() */
-
-/*****************************************************************************/
-/*
- * generate a backtrace of the kernel stack
- */
-void show_backtrace(struct pt_regs *frame, unsigned long sp)
-{
- struct pt_regs *frame0;
- unsigned long tos = 0, stop = 0, base;
- int format;
-
- base = ((((unsigned long) frame) + 8191) & ~8191) - sizeof(struct user_context);
- frame0 = (struct pt_regs *) base;
-
- if (sp) {
- tos = sp;
- stop = (unsigned long) frame;
- }
-
- printk("\nProcess %s (pid: %d)\n\n", current->comm, current->pid);
-
- for (;;) {
- /* dump stack segment between frames */
- //printk("%08lx -> %08lx\n", tos, stop);
- format = 0;
- while (tos < stop) {
- if (format == 0)
- printk(" %04lx :", tos & 0xffff);
-
- printk(" %08lx", *(unsigned long *) tos);
-
- tos += 4;
- format++;
- if (format == 8) {
- printk("\n");
- format = 0;
- }
- }
-
- if (format > 0)
- printk("\n");
-
- /* dump frame 0 outside of the loop */
- if (frame == frame0)
- break;
-
- tos = frame->sp;
- if (((unsigned long) frame) + sizeof(*frame) != tos) {
- printk("-- TOS %08lx does not follow frame %p --\n",
- tos, frame);
- break;
- }
-
- show_backtrace_regs(frame);
-
- /* dump the stack between this frame and the next */
- stop = (unsigned long) frame->next_frame;
- if (stop != base &&
- (stop < tos ||
- stop > base ||
- (stop < base && stop + sizeof(*frame) > base) ||
- stop & 3)) {
- printk("-- next_frame %08lx is invalid (range %08lx-%08lx) --\n",
- stop, tos, base);
- break;
- }
-
- /* move to next frame */
- frame = frame->next_frame;
- }
-
- /* we can always dump frame 0, even if the rest of the stack is corrupt */
- show_backtrace_regs(frame0);
-
-} /* end show_backtrace() */
-
-/*****************************************************************************/
-/*
- * initialise traps
- */
-void __init trap_init (void)
-{
-} /* end trap_init() */
diff --git a/arch/frv/kernel/uaccess.c b/arch/frv/kernel/uaccess.c
deleted file mode 100644
index 8b360b4222a5..000000000000
--- a/arch/frv/kernel/uaccess.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* uaccess.c: userspace access functions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-/*****************************************************************************/
-/*
- * copy a null terminated string from userspace
- */
-long strncpy_from_user(char *dst, const char __user *src, long count)
-{
- unsigned long max;
- char *p, ch;
- long err = -EFAULT;
-
- BUG_ON(count < 0);
-
- p = dst;
-
-#ifndef CONFIG_MMU
- if ((unsigned long) src < memory_start)
- goto error;
-#endif
-
- if ((unsigned long) src >= get_addr_limit())
- goto error;
-
- max = get_addr_limit() - (unsigned long) src;
- if ((unsigned long) count > max) {
- memset(dst + max, 0, count - max);
- count = max;
- }
-
- err = 0;
- for (; count > 0; count--, p++, src++) {
- __get_user_asm(err, ch, src, "ub", "=r");
- if (err < 0)
- goto error;
- if (!ch)
- break;
- *p = ch;
- }
-
- err = p - dst; /* return length excluding NUL */
-
- error:
- if (count > 0)
- memset(p, 0, count); /* clear remainder of buffer [security] */
-
- return err;
-
-} /* end strncpy_from_user() */
-
-EXPORT_SYMBOL(strncpy_from_user);
-
-/*****************************************************************************/
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-long strnlen_user(const char __user *src, long count)
-{
- const char __user *p;
- long err = 0;
- char ch;
-
- BUG_ON(count < 0);
-
-#ifndef CONFIG_MMU
- if ((unsigned long) src < memory_start)
- return 0;
-#endif
-
- if ((unsigned long) src >= get_addr_limit())
- return 0;
-
- for (p = src; count > 0; count--, p++) {
- __get_user_asm(err, ch, p, "ub", "=r");
- if (err < 0)
- return 0;
- if (!ch)
- break;
- }
-
- return p - src + 1; /* return length including NUL */
-
-} /* end strnlen_user() */
-
-EXPORT_SYMBOL(strnlen_user);
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
deleted file mode 100644
index 42806c512758..000000000000
--- a/arch/frv/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,136 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ld script to make FRV Linux kernel
- * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>;
- */
-OUTPUT_FORMAT("elf32-frv", "elf32-frv", "elf32-frv")
-OUTPUT_ARCH(frv)
-ENTRY(_start)
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/thread_info.h>
-
-jiffies = jiffies_64 + 4;
-
-__page_offset = CONFIG_PAGE_OFFSET; /* start of area covered by struct pages */
-__kernel_image_start = __page_offset; /* address at which kernel image resides */
-
-SECTIONS
-{
- . = __kernel_image_start;
-
- /* discardable initialisation code and data */
- . = ALIGN(PAGE_SIZE); /* Init code and data */
- __init_begin = .;
-
- _sinittext = .;
- .init.text : {
- HEAD_TEXT
-#ifndef CONFIG_DEBUG_INFO
- INIT_TEXT
- EXIT_TEXT
- EXIT_DATA
- *(.exitcall.exit)
-#endif
- }
- _einittext = .;
-
- INIT_DATA_SECTION(8)
- PERCPU_SECTION(L1_CACHE_BYTES)
-
- . = ALIGN(PAGE_SIZE);
- __init_end = .;
-
- .trap : {
- /* trap table management - read entry-table.S before modifying */
- . = ALIGN(8192);
- __trap_tables = .;
- *(.trap.user)
- *(.trap.kernel)
- . = ALIGN(4096);
- *(.trap.break)
- }
-
- /* Text and read-only data */
- . = ALIGN(4);
- _text = .;
- _stext = .;
- .text : {
- *(.text..start)
- *(.text..entry)
- *(.text..break)
- *(.text..tlbmiss)
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
-#ifdef CONFIG_DEBUG_INFO
- INIT_TEXT
- EXIT_TEXT
- *(.exitcall.exit)
-#endif
- *(.fixup)
- *(.gnu.warning)
- *(.exitcall.exit)
- } = 0x9090
-
- _etext = .; /* End of text section */
-
- RODATA
-
- .rodata : {
- *(.trap.vector)
-
- /* this clause must not be modified - the ordering and adjacency are imperative */
- __trap_fixup_tables = .;
- *(.trap.fixup.user .trap.fixup.kernel)
-
- }
-
- EXCEPTION_TABLE(8)
-
- _sdata = .;
- .data : { /* Data */
- INIT_TASK_DATA(THREAD_SIZE)
- CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
- DATA_DATA
- *(.data.*)
- EXIT_DATA
- CONSTRUCTORS
- }
-
- _edata = .; /* End of data section */
-
- BUG_TABLE
-
- /* GP section */
- . = ALIGN(L1_CACHE_BYTES);
- _gp = . + 2048;
- PROVIDE (gp = _gp);
-
- .sdata : { *(.sdata .sdata.*) }
-
- /* BSS */
- . = ALIGN(L1_CACHE_BYTES);
- __bss_start = .;
-
- .sbss : { *(.sbss .sbss.*) }
- .bss : { *(.bss .bss.*) }
- .bss..stack : { *(.bss) }
-
- __bss_stop = .;
- _end = . ;
- . = ALIGN(PAGE_SIZE);
- __kernel_image_end = .;
-
- STABS_DEBUG
- DWARF_DEBUG
-
- .comment 0 : { *(.comment) }
-
- DISCARDS
-}
-
-__kernel_image_size_no_bss = __bss_start - __kernel_image_start;
diff --git a/arch/frv/lib/Makefile b/arch/frv/lib/Makefile
deleted file mode 100644
index 970e8b4f1a02..000000000000
--- a/arch/frv/lib/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for FRV-specific library files..
-#
-
-lib-y := \
- __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \
- checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \
- outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o atomic-lib.o
diff --git a/arch/frv/lib/__ashldi3.S b/arch/frv/lib/__ashldi3.S
deleted file mode 100644
index db5b6dc37a11..000000000000
--- a/arch/frv/lib/__ashldi3.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* __ashldi3.S: 64-bit arithmetic shift left
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __ashldi3(unsigned long long value [GR8:GR9], unsigned by [GR10])
-#
-###############################################################################
- .globl __ashldi3
- .type __ashldi3,@function
-__ashldi3:
- andicc.p gr10,#63,gr10,icc0
- setlos #32,gr5
- andicc.p gr10,#32,gr0,icc1
- beqlr icc0,#0
- ckeq icc1,cc4 ; cc4 is true if 0<N<32
-
- # deal with a shift in the range 1<=N<=31
- csll.p gr8,gr10,gr8 ,cc4,#1 ; MSW <<= N
- csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
- csrl.p gr9,gr5,gr4 ,cc4,#1
- csll gr9,gr10,gr9 ,cc4,#1 ; LSW <<= N
- cor.p gr4,gr8,gr8 ,cc4,#1 ; MSW |= LSW >> M
-
- # deal with a shift in the range 32<=N<=63
- csll gr9,gr10,gr8 ,cc4,#0 ; MSW = LSW << (N & 31 [implicit AND])
- cor.p gr0,gr0,gr9 ,cc4,#0 ; LSW = 0
- bralr
- .size __ashldi3, .-__ashldi3
diff --git a/arch/frv/lib/__ashrdi3.S b/arch/frv/lib/__ashrdi3.S
deleted file mode 100644
index 5742665bfd29..000000000000
--- a/arch/frv/lib/__ashrdi3.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/* __ashrdi3.S: 64-bit arithmetic shift right
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# signed long long __ashrdi3(signed long long value [GR8:GR9], unsigned by [GR10])
-#
-###############################################################################
- .globl __ashrdi3
- .type __ashrdi3,@function
-__ashrdi3:
- andicc.p gr10,#63,gr10,icc0
- setlos #32,gr5
- andicc.p gr10,#32,gr0,icc1
- beqlr icc0,#0
- setlos.p #31,gr6
- ckeq icc1,cc4 ; cc4 is true if 0<N<32
-
- # deal with a shift in the range 1<=N<=31
- csrl.p gr9,gr10,gr9 ,cc4,#1 ; LSW >>= N
- csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
- csll.p gr8,gr5,gr4 ,cc4,#1
- csra gr8,gr10,gr8 ,cc4,#1 ; MSW >>= N
- cor.p gr4,gr9,gr9 ,cc4,#1 ; LSW |= MSW << M
-
- # deal with a shift in the range 32<=N<=63
- csra gr8,gr10,gr9 ,cc4,#0 ; LSW = MSW >> (N & 31 [implicit AND])
- csra.p gr8,gr6,gr8 ,cc4,#0 ; MSW >>= 31
- bralr
- .size __ashrdi3, .-__ashrdi3
diff --git a/arch/frv/lib/__lshrdi3.S b/arch/frv/lib/__lshrdi3.S
deleted file mode 100644
index 7b41f6304f04..000000000000
--- a/arch/frv/lib/__lshrdi3.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* __lshrdi3.S: 64-bit logical shift right
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __lshrdi3(unsigned long long value [GR8:GR9], unsigned by [GR10])
-#
-###############################################################################
- .globl __lshrdi3
- .type __lshrdi3,@function
-__lshrdi3:
- andicc.p gr10,#63,gr10,icc0
- setlos #32,gr5
- andicc.p gr10,#32,gr0,icc1
- beqlr icc0,#0
- ckeq icc1,cc4 ; cc4 is true if 0<N<32
-
- # deal with a shift in the range 1<=N<=31
- csrl.p gr9,gr10,gr9 ,cc4,#1 ; LSW >>= N
- csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
- csll.p gr8,gr5,gr4 ,cc4,#1
- csrl gr8,gr10,gr8 ,cc4,#1 ; MSW >>= N
- cor.p gr4,gr9,gr9 ,cc4,#1 ; LSW |= MSW << M
-
- # deal with a shift in the range 32<=N<=63
- csrl gr8,gr10,gr9 ,cc4,#0 ; LSW = MSW >> (N & 31 [implicit AND])
- cor.p gr0,gr0,gr8 ,cc4,#0 ; MSW = 0
- bralr
- .size __lshrdi3, .-__lshrdi3
diff --git a/arch/frv/lib/__muldi3.S b/arch/frv/lib/__muldi3.S
deleted file mode 100644
index 2703d9b79361..000000000000
--- a/arch/frv/lib/__muldi3.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/* __muldi3.S: 64-bit multiply
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __muldi3(unsigned long long x [GR8:GR9],
-# unsigned long long y [GR10:GR11])
-#
-###############################################################################
- .globl __muldi3, __mulll, __umulll
- .type __muldi3,@function
-__muldi3:
-__mulll:
-__umulll:
- umul gr8,gr11,gr4 ; GR4:GR5 = x.MSW * y.LSW
- umul gr9,gr10,gr6 ; GR6:GR7 = x.LSW * y.MSW
- umul.p gr9,gr11,gr8 ; GR8:GR9 = x.LSW * y.LSW
- add gr5,gr7,gr5
- add.p gr8,gr5,gr8 ; GR8 += GR5 + GR7
- bralr
- .size __muldi3, .-__muldi3
diff --git a/arch/frv/lib/__negdi2.S b/arch/frv/lib/__negdi2.S
deleted file mode 100644
index d1747bf24997..000000000000
--- a/arch/frv/lib/__negdi2.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* __negdi2.S: 64-bit negate
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __negdi2(unsigned long long value [GR8:GR9])
-#
-###############################################################################
- .globl __negdi2
- .type __negdi2,@function
-__negdi2:
- subcc gr0,gr9,gr9,icc0
- subx gr0,gr8,gr8,icc0
- bralr
- .size __negdi2, .-__negdi2
-
diff --git a/arch/frv/lib/__ucmpdi2.S b/arch/frv/lib/__ucmpdi2.S
deleted file mode 100644
index d892f16ffaa9..000000000000
--- a/arch/frv/lib/__ucmpdi2.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/* __ucmpdi2.S: 64-bit unsigned compare
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# int __ucmpdi2(unsigned long long a [GR8:GR9],
-# unsigned long long b [GR10:GR11])
-#
-# - returns 0, 1, or 2 as a <, =, > b respectively.
-#
-###############################################################################
- .globl __ucmpdi2
- .type __ucmpdi2,@function
-__ucmpdi2:
- or.p gr8,gr0,gr4
- subcc gr8,gr10,gr0,icc0
- setlos.p #0,gr8
- bclr icc0,#2 ; a.msw < b.msw
-
- setlos.p #2,gr8
- bhilr icc0,#0 ; a.msw > b.msw
-
- subcc.p gr9,gr11,gr0,icc1
- setlos #0,gr8
- setlos.p #2,gr9
- setlos #1,gr7
- cknc icc1,cc6
- cor.p gr9,gr0,gr8, cc6,#1
- cckls icc1,cc4, cc6,#1
- andcr cc6,cc4,cc4
- cor gr7,gr0,gr8, cc4,#1
- bralr
- .size __ucmpdi2, .-__ucmpdi2
diff --git a/arch/frv/lib/atomic-lib.c b/arch/frv/lib/atomic-lib.c
deleted file mode 100644
index 3027576f7782..000000000000
--- a/arch/frv/lib/atomic-lib.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <linux/export.h>
-#include <asm/atomic.h>
-
-#define __ATOMIC_LIB__
-
-#include <asm/atomic_defs.h>
diff --git a/arch/frv/lib/atomic-ops.S b/arch/frv/lib/atomic-ops.S
deleted file mode 100644
index b7439a960b5b..000000000000
--- a/arch/frv/lib/atomic-ops.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/* atomic-ops.S: kernel atomic operations
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/spr-regs.h>
-
- .text
- .balign 4
-
-###############################################################################
-#
-# uint32_t __xchg_32(uint32_t i, uint32_t *v)
-#
-###############################################################################
- .globl __xchg_32
- .type __xchg_32,@function
-__xchg_32:
- or.p gr8,gr8,gr10
-0:
- orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
- ckeq icc3,cc7
- ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
- orcr cc7,cc7,cc3 /* set CC3 to true */
- cst.p gr10,@(gr9,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
- beq icc3,#0,0b
- bralr
-
- .size __xchg_32, .-__xchg_32
-
-###############################################################################
-#
-# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new)
-#
-###############################################################################
- .globl __cmpxchg_32
- .type __cmpxchg_32,@function
-__cmpxchg_32:
- or.p gr8,gr8,gr11
-0:
- orcc gr0,gr0,gr0,icc3
- ckeq icc3,cc7
- ld.p @(gr11,gr0),gr8
- orcr cc7,cc7,cc3
- subcc gr8,gr9,gr7,icc0
- bnelr icc0,#0
- cst.p gr10,@(gr11,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1
- beq icc3,#0,0b
- bralr
-
- .size __cmpxchg_32, .-__cmpxchg_32
diff --git a/arch/frv/lib/atomic64-ops.S b/arch/frv/lib/atomic64-ops.S
deleted file mode 100644
index c4c472308a33..000000000000
--- a/arch/frv/lib/atomic64-ops.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/* kernel atomic64 operations
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/spr-regs.h>
-
- .text
- .balign 4
-
-
-###############################################################################
-#
-# uint64_t __xchg_64(uint64_t i, uint64_t *v)
-#
-###############################################################################
- .globl __xchg_64
- .type __xchg_64,@function
-__xchg_64:
- or.p gr8,gr8,gr4
- or gr9,gr9,gr5
-0:
- orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
- ckeq icc3,cc7
- ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
- orcr cc7,cc7,cc3 /* set CC3 to true */
- cstd.p gr4,@(gr10,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
- beq icc3,#0,0b
- bralr
-
- .size __xchg_64, .-__xchg_64
-
-###############################################################################
-#
-# uint64_t __cmpxchg_64(uint64_t test, uint64_t new, uint64_t *v)
-#
-###############################################################################
- .globl __cmpxchg_64
- .type __cmpxchg_64,@function
-__cmpxchg_64:
- or.p gr8,gr8,gr4
- or gr9,gr9,gr5
-0:
- orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
- ckeq icc3,cc7
- ldd.p @(gr12,gr0),gr8 /* LDD.P/ORCR must be atomic */
- orcr cc7,cc7,cc3
- subcc gr8,gr4,gr0,icc0
- subcc.p gr9,gr5,gr0,icc1
- bnelr icc0,#0
- bnelr icc1,#0
- cstd.p gr10,@(gr12,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
- beq icc3,#0,0b
- bralr
-
- .size __cmpxchg_64, .-__cmpxchg_64
-
diff --git a/arch/frv/lib/cache.S b/arch/frv/lib/cache.S
deleted file mode 100644
index 0c4fb204911b..000000000000
--- a/arch/frv/lib/cache.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/* cache.S: cache management routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/spr-regs.h>
-#include <asm/cache.h>
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# Write back a range of dcache
-# - void frv_dcache_writeback(unsigned long start [GR8], unsigned long size [GR9])
-#
-###############################################################################
- .globl frv_dcache_writeback
- .type frv_dcache_writeback,@function
-frv_dcache_writeback:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: dcf @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_dcache_writeback, .-frv_dcache_writeback
-
-##############################################################################
-#
-# Invalidate a range of dcache and icache
-# - void frv_cache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
-#
-###############################################################################
- .globl frv_cache_invalidate
- .type frv_cache_invalidate,@function
-frv_cache_invalidate:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: dci @(gr8,gr0)
- ici @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_cache_invalidate, .-frv_cache_invalidate
-
-##############################################################################
-#
-# Invalidate a range of icache
-# - void frv_icache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
-#
-###############################################################################
- .globl frv_icache_invalidate
- .type frv_icache_invalidate,@function
-frv_icache_invalidate:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: ici @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_icache_invalidate, .-frv_icache_invalidate
-
-###############################################################################
-#
-# Write back and invalidate a range of dcache and icache
-# - void frv_cache_wback_inv(unsigned long start [GR8], unsigned long end [GR9])
-#
-###############################################################################
- .globl frv_cache_wback_inv
- .type frv_cache_wback_inv,@function
-frv_cache_wback_inv:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: dcf @(gr8,gr0)
- ici @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_cache_wback_inv, .-frv_cache_wback_inv
diff --git a/arch/frv/lib/checksum.c b/arch/frv/lib/checksum.c
deleted file mode 100644
index 44e16d59bc10..000000000000
--- a/arch/frv/lib/checksum.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * INET An implementation of the TCP/IP protocol suite for the LINUX
- * operating system. INET is implemented using the BSD Socket
- * interface as the means of communication with the user level.
- *
- * IP/TCP/UDP checksumming routines
- *
- * Authors: Jorge Cwik, <jorge@laser.satlink.net>
- * Arnt Gulbrandsen, <agulbra@nvg.unit.no>
- * Tom May, <ftom@netcom.com>
- * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
- * Lots of code moved from tcp.c and ip.c; see those files
- * for more names.
- *
- * 03/02/96 Jes Sorensen, Andreas Schwab, Roman Hodek:
- * Fixed some nasty bugs, causing some horrible crashes.
- * A: At some points, the sum (%0) was used as
- * length-counter instead of the length counter
- * (%1). Thanks to Roman Hodek for pointing this out.
- * B: GCC seems to mess up if one uses too many
- * data-registers to hold input values and one tries to
- * specify d0 and d1 as scratch registers. Letting gcc choose these
- * registers itself solves the problem.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/* Revised by Kenneth Albanowski for m68knommu. Basic problem: unaligned access kills, so most
- of the assembly has to go. */
-
-#include <net/checksum.h>
-#include <linux/module.h>
-
-static inline unsigned short from32to16(unsigned long x)
-{
- /* add up 16-bit and 16-bit for 16+c bit */
- x = (x & 0xffff) + (x >> 16);
- /* add up carry.. */
- x = (x & 0xffff) + (x >> 16);
- return x;
-}
-
-static unsigned long do_csum(const unsigned char * buff, int len)
-{
- int odd, count;
- unsigned long result = 0;
-
- if (len <= 0)
- goto out;
- odd = 1 & (unsigned long) buff;
- if (odd) {
- result = *buff;
- len--;
- buff++;
- }
- count = len >> 1; /* nr of 16-bit words.. */
- if (count) {
- if (2 & (unsigned long) buff) {
- result += *(unsigned short *) buff;
- count--;
- len -= 2;
- buff += 2;
- }
- count >>= 1; /* nr of 32-bit words.. */
- if (count) {
- unsigned long carry = 0;
- do {
- unsigned long w = *(unsigned long *) buff;
- count--;
- buff += 4;
- result += carry;
- result += w;
- carry = (w > result);
- } while (count);
- result += carry;
- result = (result & 0xffff) + (result >> 16);
- }
- if (len & 2) {
- result += *(unsigned short *) buff;
- buff += 2;
- }
- }
- if (len & 1)
- result += (*buff << 8);
- result = from32to16(result);
- if (odd)
- result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
-out:
- return result;
-}
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum)
-{
- unsigned int result = do_csum(buff, len);
-
- /* add in old sum, and carry.. */
- result += (__force u32)sum;
- if ((__force u32)sum > result)
- result += 1;
- return (__force __wsum)result;
-}
-
-EXPORT_SYMBOL(csum_partial);
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-__sum16 ip_compute_csum(const void *buff, int len)
-{
- return (__force __sum16)~do_csum(buff, len);
-}
-
-EXPORT_SYMBOL(ip_compute_csum);
-
-/*
- * copy from fs while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum, int *csum_err)
-{
- int rem;
-
- if (csum_err)
- *csum_err = 0;
-
- rem = copy_from_user(dst, src, len);
- if (rem != 0) {
- if (csum_err)
- *csum_err = -EFAULT;
- memset(dst + len - rem, 0, rem);
- len = rem;
- }
-
- return csum_partial(dst, len, sum);
-}
-
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-
-/*
- * copy from ds while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
-{
- memcpy(dst, src, len);
- return csum_partial(dst, len, sum);
-}
-
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/frv/lib/insl_ns.S b/arch/frv/lib/insl_ns.S
deleted file mode 100644
index d1658425a9f7..000000000000
--- a/arch/frv/lib/insl_ns.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* insl_ns.S: input array of 4b words from device port without byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __insl_ns(unsigned int port, void *buf, int n)
-#
-###############################################################################
- .globl __insl_ns
- .type __insl_ns,@function
-__insl_ns:
- andicc.p gr9,#3,gr0,icc0
- setlos #4,gr4
- bne icc0,#0,__insl_ns_misaligned
- subi gr9,#4,gr9
-0:
- ldi.p @(gr8,#0),gr5
- subicc gr10,#1,gr10,icc0
- stu.p gr5,@(gr9,gr4)
- bhi icc0,#2,0b
- bralr
-
-__insl_ns_misaligned:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldi @(gr8,#0),gr5
-
- srli gr5,#24,gr6
- stbu.p gr6,@(gr9,gr4)
- srli gr5,#16,gr6
- stbu.p gr6,@(gr9,gr4)
- srli gr5,#8,gr6
- stbu.p gr6,@(gr9,gr4)
- subicc gr10,#1,gr10,icc0
- stbu.p gr5,@(gr9,gr4)
- bhi icc0,#2,0b
- bralr
-
- .size __insl_ns, .-__insl_ns
diff --git a/arch/frv/lib/insl_sw.S b/arch/frv/lib/insl_sw.S
deleted file mode 100644
index 9b5aa95d069b..000000000000
--- a/arch/frv/lib/insl_sw.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* insl_sw.S: input array of 4b words from device port with byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __insl_sw(unsigned int port, void *buf, int n)
-#
-###############################################################################
- .globl __insl_sw
- .type __insl_sw,@function
-__insl_sw:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldi.p @(gr8,#0),gr5 ; get 0xAABBCCDD
- subicc gr10,#1,gr10,icc0
-
- stbu.p gr5,@(gr9,gr4) ; write 0xDD
- srli gr5,#8,gr5
- stbu.p gr5,@(gr9,gr4) ; write 0xCC
- srli gr5,#8,gr5
- stbu.p gr5,@(gr9,gr4) ; write 0xBB
- srli gr5,#8,gr5
- stbu.p gr5,@(gr9,gr4) ; write 0xAA
- bhi icc0,#2,0b
- bralr
-
- .size __insl_sw, .-__insl_sw
diff --git a/arch/frv/lib/memcpy.S b/arch/frv/lib/memcpy.S
deleted file mode 100644
index 9c5965273428..000000000000
--- a/arch/frv/lib/memcpy.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/* memcpy.S: optimised assembly memcpy
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void *memcpy(void *to, const char *from, size_t count)
-#
-# - NOTE: must not use any stack. exception detection performs function return
-# to caller's fixup routine, aborting the remainder of the copy
-#
-###############################################################################
- .globl memcpy,__memcpy_end
- .type memcpy,@function
-memcpy:
- or.p gr8,gr9,gr4
- orcc gr10,gr0,gr0,icc3
- or.p gr10,gr4,gr4
- beqlr icc3,#0
-
- # optimise based on best common alignment for to, from & count
- andicc.p gr4,#0x0f,gr0,icc0
- setlos #8,gr11
- andicc.p gr4,#0x07,gr0,icc1
- beq icc0,#0,memcpy_16
- andicc.p gr4,#0x03,gr0,icc0
- beq icc1,#0,memcpy_8
- andicc.p gr4,#0x01,gr0,icc1
- beq icc0,#0,memcpy_4
- setlos.p #1,gr11
- beq icc1,#0,memcpy_2
-
- # do byte by byte copy
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: ldubu.p @(gr9,gr11),gr4
- subicc gr10,#1,gr10,icc0
- stbu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do halfword by halfword copy
-memcpy_2:
- setlos #2,gr11
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: lduhu.p @(gr9,gr11),gr4
- subicc gr10,#2,gr10,icc0
- sthu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do word by word copy
-memcpy_4:
- setlos #4,gr11
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: ldu.p @(gr9,gr11),gr4
- subicc gr10,#4,gr10,icc0
- stu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do double-word by double-word copy
-memcpy_8:
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: lddu.p @(gr9,gr11),gr4
- subicc gr10,#8,gr10,icc0
- stdu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do quad-word by quad-word copy
-memcpy_16:
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: lddu @(gr9,gr11),gr4
- lddu.p @(gr9,gr11),gr6
- subicc gr10,#16,gr10,icc0
- stdu gr4,@(gr3,gr11)
- stdu.p gr6,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-__memcpy_end:
-
- .size memcpy, __memcpy_end-memcpy
-
-###############################################################################
-#
-# copy to/from userspace
-# - return the number of bytes that could not be copied (0 on complete success)
-#
-# long __memcpy_user(void *dst, const void *src, size_t count)
-#
-###############################################################################
- .globl __memcpy_user, __memcpy_user_error_lr, __memcpy_user_error_handler
- .type __memcpy_user,@function
-__memcpy_user:
- movsg lr,gr7
- subi.p sp,#8,sp
- add gr8,gr10,gr6 ; calculate expected end address
- stdi gr6,@(sp,#0)
-
- # abuse memcpy to do the dirty work
- call memcpy
-__memcpy_user_error_lr:
- ldi.p @(sp,#4),gr7
- setlos #0,gr8
- jmpl.p @(gr7,gr0)
- addi sp,#8,sp
-
- # deal any exception generated by memcpy
- # GR8 - memcpy's current dest address
- # GR11 - memset's step value (index register for store insns)
-__memcpy_user_error_handler:
- lddi.p @(sp,#0),gr4 ; load GR4 with dst+count, GR5 with ret addr
- add gr11,gr3,gr7
- sub.p gr4,gr7,gr8
-
- addi sp,#8,sp
- jmpl @(gr5,gr0)
-
- .size __memcpy_user, .-__memcpy_user
diff --git a/arch/frv/lib/memset.S b/arch/frv/lib/memset.S
deleted file mode 100644
index 55a35263cbe3..000000000000
--- a/arch/frv/lib/memset.S
+++ /dev/null
@@ -1,182 +0,0 @@
-/* memset.S: optimised assembly memset
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void *memset(void *p, char ch, size_t count)
-#
-# - NOTE: must not use any stack. exception detection performs function return
-# to caller's fixup routine, aborting the remainder of the set
-# GR4, GR7, GR8, and GR11 must be managed
-#
-###############################################################################
- .globl memset,__memset_end
- .type memset,@function
-memset:
- orcc.p gr10,gr0,gr5,icc3 ; GR5 = count
- andi gr9,#0xff,gr9
- or.p gr8,gr0,gr4 ; GR4 = address
- beqlr icc3,#0
-
- # conditionally write a byte to 2b-align the address
- setlos.p #1,gr6
- andicc gr4,#1,gr0,icc0
- ckne icc0,cc7
- cstb.p gr9,@(gr4,gr0) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cadd.p gr4,gr6,gr4 ,cc7,#1
- beqlr icc3,#0
-
- # conditionally write a word to 4b-align the address
- andicc.p gr4,#2,gr0,icc0
- subicc gr5,#2,gr0,icc1
- setlos.p #2,gr6
- ckne icc0,cc7
- slli.p gr9,#8,gr12 ; need to double up the pattern
- cknc icc1,cc5
- or.p gr9,gr12,gr12
- andcr cc7,cc5,cc7
-
- csth.p gr12,@(gr4,gr0) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cadd.p gr4,gr6,gr4 ,cc7,#1
- beqlr icc3,#0
-
- # conditionally write a dword to 8b-align the address
- andicc.p gr4,#4,gr0,icc0
- subicc gr5,#4,gr0,icc1
- setlos.p #4,gr6
- ckne icc0,cc7
- slli.p gr12,#16,gr13 ; need to quadruple-up the pattern
- cknc icc1,cc5
- or.p gr13,gr12,gr12
- andcr cc7,cc5,cc7
-
- cst.p gr12,@(gr4,gr0) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cadd.p gr4,gr6,gr4 ,cc7,#1
- beqlr icc3,#0
-
- or.p gr12,gr12,gr13 ; need to octuple-up the pattern
-
- # the address is now 8b-aligned - loop around writing 64b chunks
- setlos #8,gr7
- subi.p gr4,#8,gr4 ; store with update index does weird stuff
- setlos #64,gr6
-
- subicc gr5,#64,gr0,icc0
-0: cknc icc0,cc7
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- subicc gr5,#64,gr0,icc0
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- beqlr icc3,#0
- bnc icc0,#2,0b
-
- # now do 32-byte remnant
- subicc.p gr5,#32,gr0,icc0
- setlos #32,gr6
- cknc icc0,cc7
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- setlos #16,gr6
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- subicc gr5,#16,gr0,icc0
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- beqlr icc3,#0
-
- # now do 16-byte remnant
- cknc icc0,cc7
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- beqlr icc3,#0
-
- # now do 8-byte remnant
- subicc gr5,#8,gr0,icc1
- cknc icc1,cc7
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr7,gr5 ,cc7,#1 ; also set ICC3
- setlos.p #4,gr7
- beqlr icc3,#0
-
- # now do 4-byte remnant
- subicc gr5,#4,gr0,icc0
- addi.p gr4,#4,gr4
- cknc icc0,cc7
- cstu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr7,gr5 ,cc7,#1 ; also set ICC3
- subicc.p gr5,#2,gr0,icc1
- beqlr icc3,#0
-
- # now do 2-byte remnant
- setlos #2,gr7
- addi.p gr4,#2,gr4
- cknc icc1,cc7
- csthu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr7,gr5 ,cc7,#1 ; also set ICC3
- subicc.p gr5,#1,gr0,icc0
- beqlr icc3,#0
-
- # now do 1-byte remnant
- setlos #0,gr7
- addi.p gr4,#2,gr4
- cknc icc0,cc7
- cstb.p gr12,@(gr4,gr0) ,cc7,#1
- bralr
-__memset_end:
-
- .size memset, __memset_end-memset
-
-###############################################################################
-#
-# clear memory in userspace
-# - return the number of bytes that could not be cleared (0 on complete success)
-#
-# long __memset_user(void *p, size_t count)
-#
-###############################################################################
- .globl __memset_user, __memset_user_error_lr, __memset_user_error_handler
- .type __memset_user,@function
-__memset_user:
- movsg lr,gr11
-
- # abuse memset to do the dirty work
- or.p gr9,gr9,gr10
- setlos #0,gr9
- call memset
-__memset_user_error_lr:
- jmpl.p @(gr11,gr0)
- setlos #0,gr8
-
- # deal any exception generated by memset
- # GR4 - memset's address tracking pointer
- # GR7 - memset's step value (index register for store insns)
- # GR8 - memset's original start address
- # GR10 - memset's original count
-__memset_user_error_handler:
- add.p gr4,gr7,gr4
- add gr8,gr10,gr8
- jmpl.p @(gr11,gr0)
- sub gr8,gr4,gr8 ; we return the amount left uncleared
-
- .size __memset_user, .-__memset_user
diff --git a/arch/frv/lib/outsl_ns.S b/arch/frv/lib/outsl_ns.S
deleted file mode 100644
index 4cd4c46a6966..000000000000
--- a/arch/frv/lib/outsl_ns.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/* outsl_ns.S: output array of 4b words to device without byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __outsl_ns(unsigned int port, const void *buf, int n)
-#
-###############################################################################
- .globl __outsl_ns
- .type __outsl_ns,@function
-__outsl_ns:
- andicc.p gr9,#3,gr0,icc0
- setlos #4,gr4
- bne icc0,#0,__outsl_ns_misaligned
- subi gr9,#4,gr9
-0:
- ldu.p @(gr9,gr4),gr5
- subicc gr10,#1,gr10,icc0
- sti.p gr5,@(gr8,#0)
- bhi icc0,#2,0b
-
- membar
- bralr
-
-__outsl_ns_misaligned:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldubu @(gr9,gr4),gr5
- ldubu.p @(gr9,gr4),gr6
- slli gr5,#8,gr5
- ldubu.p @(gr9,gr4),gr7
- or gr5,gr6,gr5
- ldubu.p @(gr9,gr4),gr6
- slli gr5,#16,gr5
- slli.p gr7,#8,gr7
- or gr5,gr6,gr5
- subicc.p gr10,#1,gr10,icc0
- or gr5,gr7,gr5
-
- sti.p gr5,@(gr8,#0)
- bhi icc0,#2,0b
-
- membar
- bralr
-
- .size __outsl_ns, .-__outsl_ns
diff --git a/arch/frv/lib/outsl_sw.S b/arch/frv/lib/outsl_sw.S
deleted file mode 100644
index 7eb56d35a956..000000000000
--- a/arch/frv/lib/outsl_sw.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/* outsl_ns.S: output array of 4b words to device with byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __outsl_sw(unsigned int port, const void *buf, int n)
-#
-###############################################################################
- .globl __outsl_sw
- .type __outsl_sw,@function
-__outsl_sw:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldubu @(gr9,gr4),gr5
- ldubu @(gr9,gr4),gr6
- slli gr6,#8,gr6
- ldubu.p @(gr9,gr4),gr7
- or gr5,gr6,gr5
- ldubu.p @(gr9,gr4),gr6
- slli gr7,#16,gr7
- slli.p gr6,#24,gr6
- or gr5,gr7,gr5
- subicc.p gr10,#1,gr10,icc0
- or gr5,gr6,gr5
-
- sti.p gr5,@(gr8,#0)
- bhi icc0,#2,0b
-
- membar
- bralr
-
- .size __outsl_sw, .-__outsl_sw
diff --git a/arch/frv/mb93090-mb00/Makefile b/arch/frv/mb93090-mb00/Makefile
deleted file mode 100644
index bcb03ebb3583..000000000000
--- a/arch/frv/mb93090-mb00/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the MB93090-MB00 motherboard stuff
-#
-
-ifeq "$(CONFIG_PCI)" "y"
-obj-y := pci-frv.o pci-irq.o pci-vdk.o
-
-ifeq "$(CONFIG_MMU)" "y"
-obj-y += pci-dma.o
-else
-obj-y += pci-dma-nommu.o
-endif
-endif
-
-obj-$(CONFIG_MTD) += flash.o
diff --git a/arch/frv/mb93090-mb00/flash.c b/arch/frv/mb93090-mb00/flash.c
deleted file mode 100644
index e1cf802d1639..000000000000
--- a/arch/frv/mb93090-mb00/flash.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Flash mappings for the MB93090-MB00 motherboard
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#define MB93090_BOOTROM_ADDR 0xFF000000 /* Boot ROM */
-#define MB93090_BOOTROM_SIZE (2 * 1024 * 1024)
-#define MB93090_USERROM_ADDR 0xFF200000 /* User ROM */
-#define MB93090_USERROM_SIZE (2 * 1024 * 1024)
-
-/*
- * default MTD partition table for both main flash devices, expected to be
- * overridden by RedBoot
- */
-static struct mtd_partition mb93090_partitions[] = {
- {
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0,
- }
-};
-
-/*
- * Definition of the MB93090 Boot ROM (on the CPU card)
- */
-static struct physmap_flash_data mb93090_bootrom_data = {
- .width = 2,
- .nr_parts = 2,
- .parts = mb93090_partitions,
-};
-
-static struct resource mb93090_bootrom_resource = {
- .start = MB93090_BOOTROM_ADDR,
- .end = MB93090_BOOTROM_ADDR + MB93090_BOOTROM_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mb93090_bootrom = {
- .name = "physmap-flash",
- .id = 0,
- .dev.platform_data = &mb93090_bootrom_data,
- .num_resources = 1,
- .resource = &mb93090_bootrom_resource,
-};
-
-/*
- * Definition of the MB93090 User ROM definition (on the motherboard)
- */
-static struct physmap_flash_data mb93090_userrom_data = {
- .width = 2,
- .nr_parts = 2,
- .parts = mb93090_partitions,
-};
-
-static struct resource mb93090_userrom_resource = {
- .start = MB93090_USERROM_ADDR,
- .end = MB93090_USERROM_ADDR + MB93090_USERROM_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mb93090_userrom = {
- .name = "physmap-flash",
- .id = 1,
- .dev.platform_data = &mb93090_userrom_data,
- .num_resources = 1,
- .resource = &mb93090_userrom_resource,
-};
-
-/*
- * register the MB93090 flashes
- */
-static int __init mb93090_mtd_init(void)
-{
- platform_device_register(&mb93090_bootrom);
- platform_device_register(&mb93090_userrom);
- return 0;
-}
-
-module_init(mb93090_mtd_init);
diff --git a/arch/frv/mb93090-mb00/pci-dma-nommu.c b/arch/frv/mb93090-mb00/pci-dma-nommu.c
deleted file mode 100644
index 4a96de7f0af4..000000000000
--- a/arch/frv/mb93090-mb00/pci-dma-nommu.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* pci-dma-nommu.c: Dynamic DMA mapping support for the FRV
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Woodhouse (dwmw2@infradead.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <linux/dma-mapping.h>
-#include <linux/list.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-
-#if 1
-#define DMA_SRAM_START dma_coherent_mem_start
-#define DMA_SRAM_END dma_coherent_mem_end
-#else // Use video RAM on Matrox
-#define DMA_SRAM_START 0xe8900000
-#define DMA_SRAM_END 0xe8a00000
-#endif
-
-struct dma_alloc_record {
- struct list_head list;
- unsigned long ofs;
- unsigned long len;
-};
-
-static DEFINE_SPINLOCK(dma_alloc_lock);
-static LIST_HEAD(dma_alloc_list);
-
-static void *frv_dma_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
- gfp_t gfp, unsigned long attrs)
-{
- struct dma_alloc_record *new;
- struct list_head *this = &dma_alloc_list;
- unsigned long flags;
- unsigned long start = DMA_SRAM_START;
- unsigned long end;
-
- if (!DMA_SRAM_START) {
- printk("%s called without any DMA area reserved!\n", __func__);
- return NULL;
- }
-
- new = kmalloc(sizeof (*new), GFP_ATOMIC);
- if (!new)
- return NULL;
-
- /* Round up to a reasonable alignment */
- new->len = (size + 31) & ~31;
-
- spin_lock_irqsave(&dma_alloc_lock, flags);
-
- list_for_each (this, &dma_alloc_list) {
- struct dma_alloc_record *this_r = list_entry(this, struct dma_alloc_record, list);
- end = this_r->ofs;
-
- if (end - start >= size)
- goto gotone;
-
- start = this_r->ofs + this_r->len;
- }
- /* Reached end of list. */
- end = DMA_SRAM_END;
- this = &dma_alloc_list;
-
- if (end - start >= size) {
- gotone:
- new->ofs = start;
- list_add_tail(&new->list, this);
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
-
- *dma_handle = start;
- return (void *)start;
- }
-
- kfree(new);
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
- return NULL;
-}
-
-static void frv_dma_free(struct device *hwdev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- struct dma_alloc_record *rec;
- unsigned long flags;
-
- spin_lock_irqsave(&dma_alloc_lock, flags);
-
- list_for_each_entry(rec, &dma_alloc_list, list) {
- if (rec->ofs == dma_handle) {
- list_del(&rec->list);
- kfree(rec);
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
- return;
- }
- }
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
- BUG();
-}
-
-static int frv_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(direction == DMA_NONE);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- return nents;
-
- for_each_sg(sglist, sg, nents, i) {
- frv_cache_wback_inv(sg_dma_address(sg),
- sg_dma_address(sg) + sg_dma_len(sg));
- }
-
- return nents;
-}
-
-static dma_addr_t frv_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction, unsigned long attrs)
-{
- BUG_ON(direction == DMA_NONE);
-
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- flush_dcache_page(page);
-
- return (dma_addr_t) page_to_phys(page) + offset;
-}
-
-static void frv_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static void frv_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-
-static int frv_dma_supported(struct device *dev, u64 mask)
-{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s,
- * so we can't guarantee allocations that must be
- * within a tighter range than GFP_DMA..
- */
- if (mask < 0x00ffffff)
- return 0;
- return 1;
-}
-
-const struct dma_map_ops frv_dma_ops = {
- .alloc = frv_dma_alloc,
- .free = frv_dma_free,
- .map_page = frv_dma_map_page,
- .map_sg = frv_dma_map_sg,
- .sync_single_for_device = frv_dma_sync_single_for_device,
- .sync_sg_for_device = frv_dma_sync_sg_for_device,
- .dma_supported = frv_dma_supported,
-};
-EXPORT_SYMBOL(frv_dma_ops);
diff --git a/arch/frv/mb93090-mb00/pci-dma.c b/arch/frv/mb93090-mb00/pci-dma.c
deleted file mode 100644
index e7130abc0dae..000000000000
--- a/arch/frv/mb93090-mb00/pci-dma.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* pci-dma.c: Dynamic DMA mapping support for the FRV CPUs that have MMUs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/dma-mapping.h>
-#include <linux/list.h>
-#include <linux/pci.h>
-#include <linux/export.h>
-#include <linux/highmem.h>
-#include <linux/scatterlist.h>
-#include <asm/io.h>
-
-static void *frv_dma_alloc(struct device *hwdev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- void *ret;
-
- ret = consistent_alloc(gfp, size, dma_handle);
- if (ret)
- memset(ret, 0, size);
-
- return ret;
-}
-
-static void frv_dma_free(struct device *hwdev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- consistent_free(vaddr);
-}
-
-static int frv_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- unsigned long dampr2;
- void *vaddr;
- int i;
-
- BUG_ON(direction == DMA_NONE);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- return nents;
-
- dampr2 = __get_DAMPR(2);
-
- for_each_sg(sglist, sg, nents, i) {
- vaddr = kmap_atomic_primary(sg_page(sg));
-
- frv_dcache_writeback((unsigned long) vaddr,
- (unsigned long) vaddr + PAGE_SIZE);
-
- }
-
- kunmap_atomic_primary(vaddr);
- if (dampr2) {
- __set_DAMPR(2, dampr2);
- __set_IAMPR(2, dampr2);
- }
-
- return nents;
-}
-
-static dma_addr_t frv_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction, unsigned long attrs)
-{
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- flush_dcache_page(page);
-
- return (dma_addr_t) page_to_phys(page) + offset;
-}
-
-static void frv_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static void frv_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-
-static int frv_dma_supported(struct device *dev, u64 mask)
-{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s,
- * so we can't guarantee allocations that must be
- * within a tighter range than GFP_DMA..
- */
- if (mask < 0x00ffffff)
- return 0;
- return 1;
-}
-
-const struct dma_map_ops frv_dma_ops = {
- .alloc = frv_dma_alloc,
- .free = frv_dma_free,
- .map_page = frv_dma_map_page,
- .map_sg = frv_dma_map_sg,
- .sync_single_for_device = frv_dma_sync_single_for_device,
- .sync_sg_for_device = frv_dma_sync_sg_for_device,
- .dma_supported = frv_dma_supported,
-};
-EXPORT_SYMBOL(frv_dma_ops);
diff --git a/arch/frv/mb93090-mb00/pci-frv.c b/arch/frv/mb93090-mb00/pci-frv.c
deleted file mode 100644
index c452ddb5620f..000000000000
--- a/arch/frv/mb93090-mb00/pci-frv.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* pci-frv.c: low-level PCI access routines
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from the i386 equivalent stuff
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/errno.h>
-
-#include "pci-frv.h"
-
-/*
- * We need to avoid collisions with `mirrored' VGA ports
- * and other strange ISA hardware, so we always want the
- * addresses to be allocated in the 0x000-0x0ff region
- * modulo 0x400.
- *
- * Why? Because some silly external IO cards only decode
- * the low 10 bits of the IO address. The 0x00-0xff region
- * is reserved for motherboard devices that decode all 16
- * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
- * but we want to try to avoid allocating at 0x2900-0x2bff
- * which might have be mirrored at 0x0100-0x03ff..
- */
-resource_size_t
-pcibios_align_resource(void *data, const struct resource *res,
- resource_size_t size, resource_size_t align)
-{
- resource_size_t start = res->start;
-
- if ((res->flags & IORESOURCE_IO) && (start & 0x300))
- start = (start + 0x3ff) & ~0x3ff;
-
- return start;
-}
-
-
-/*
- * Handle resources of PCI devices. If the world were perfect, we could
- * just allocate all the resource regions and do nothing more. It isn't.
- * On the other hand, we cannot just re-allocate all devices, as it would
- * require us to know lots of host bridge internals. So we attempt to
- * keep as much of the original configuration as possible, but tweak it
- * when it's found to be wrong.
- *
- * Known BIOS problems we have to work around:
- * - I/O or memory regions not configured
- * - regions configured, but not enabled in the command register
- * - bogus I/O addresses above 64K used
- * - expansion ROMs left enabled (this may sound harmless, but given
- * the fact the PCI specs explicitly allow address decoders to be
- * shared between expansion ROMs and other resource regions, it's
- * at least dangerous)
- *
- * Our solution:
- * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
- * This gives us fixed barriers on where we can allocate.
- * (2) Allocate resources for all enabled devices. If there is
- * a collision, just mark the resource as unallocated. Also
- * disable expansion ROMs during this step.
- * (3) Try to allocate resources for disabled devices. If the
- * resources were assigned correctly, everything goes well,
- * if they weren't, they won't disturb allocation of other
- * resources.
- * (4) Assign new addresses to resources which were either
- * not configured at all or misconfigured. If explicitly
- * requested by the user, configure expansion ROM address
- * as well.
- */
-
-static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
-{
- struct list_head *ln;
- struct pci_bus *bus;
- struct pci_dev *dev;
- int idx;
- struct resource *r;
-
- /* Depth-First Search on bus tree */
- for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
- bus = list_entry(ln, struct pci_bus, node);
- if ((dev = bus->self)) {
- for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
- r = &dev->resource[idx];
- if (!r->start)
- continue;
- pci_claim_bridge_resource(dev, idx);
- }
- }
- pcibios_allocate_bus_resources(&bus->children);
- }
-}
-
-static void __init pcibios_allocate_resources(int pass)
-{
- struct pci_dev *dev = NULL;
- int idx, disabled;
- u16 command;
- struct resource *r;
-
- for_each_pci_dev(dev) {
- pci_read_config_word(dev, PCI_COMMAND, &command);
- for(idx = 0; idx < 6; idx++) {
- r = &dev->resource[idx];
- if (r->parent) /* Already allocated */
- continue;
- if (!r->start) /* Address not assigned at all */
- continue;
- if (r->flags & IORESOURCE_IO)
- disabled = !(command & PCI_COMMAND_IO);
- else
- disabled = !(command & PCI_COMMAND_MEMORY);
- if (pass == disabled) {
- DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
- r->start, r->end, r->flags, disabled, pass);
- if (pci_claim_resource(dev, idx) < 0) {
- /* We'll assign a new address later */
- r->end -= r->start;
- r->start = 0;
- }
- }
- }
- if (!pass) {
- r = &dev->resource[PCI_ROM_RESOURCE];
- if (r->flags & IORESOURCE_ROM_ENABLE) {
- /* Turn the ROM off, leave the resource region, but keep it unregistered. */
- u32 reg;
- DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
- r->flags &= ~IORESOURCE_ROM_ENABLE;
- pci_read_config_dword(dev, dev->rom_base_reg, &reg);
- pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
- }
- }
- }
-}
-
-static void __init pcibios_assign_resources(void)
-{
- struct pci_dev *dev = NULL;
- int idx, err;
- struct resource *r;
-
- for_each_pci_dev(dev) {
- int class = dev->class >> 8;
-
- /* Don't touch classless devices and host bridges */
- if (!class || class == PCI_CLASS_BRIDGE_HOST)
- continue;
-
- for(idx=0; idx<6; idx++) {
- r = &dev->resource[idx];
-
- /*
- * Don't touch IDE controllers and I/O ports of video cards!
- */
- if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
- (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
- continue;
-
- /*
- * We shall assign a new address to this resource, either because
- * the BIOS forgot to do so or because we have decided the old
- * address was unusable for some reason.
- */
- if (!r->start && r->end) {
- err = pci_assign_resource(dev, idx);
- if (err)
- dev_err(&dev->dev,
- "Failed to assign new address to %d\n",
- idx);
- }
- }
- }
-}
-
-void __init pcibios_resource_survey(void)
-{
- DBG("PCI: Allocating resources\n");
- pcibios_allocate_bus_resources(&pci_root_buses);
- pcibios_allocate_resources(0);
- pcibios_allocate_resources(1);
- pcibios_assign_resources();
-}
diff --git a/arch/frv/mb93090-mb00/pci-frv.h b/arch/frv/mb93090-mb00/pci-frv.h
deleted file mode 100644
index 41fbb6bae558..000000000000
--- a/arch/frv/mb93090-mb00/pci-frv.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Low-Level PCI Access for FRV machines.
- *
- * (c) 1999 Martin Mares <mj@ucw.cz>
- */
-
-#include <asm/sections.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-extern unsigned int __nongpreldata pci_probe;
-
-/* pci-frv.c */
-
-void pcibios_resource_survey(void);
-
-/* pci-vdk.c */
-
-extern struct pci_ops *__nongpreldata pci_root_ops;
-
-/* pci-irq.c */
-extern unsigned int pcibios_irq_mask;
-
-void pcibios_irq_init(void);
-void pcibios_fixup_irqs(void);
-void pcibios_enable_irq(struct pci_dev *dev);
diff --git a/arch/frv/mb93090-mb00/pci-irq.c b/arch/frv/mb93090-mb00/pci-irq.c
deleted file mode 100644
index a40aa8663056..000000000000
--- a/arch/frv/mb93090-mb00/pci-irq.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* pci-irq.c: PCI IRQ routing on the FRV motherboard
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * derived from: arch/i386/kernel/pci-irq.c: (c) 1999--2000 Martin Mares <mj@suse.cz>
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-#include <asm/io.h>
-#include <asm/smp.h>
-
-#include "pci-frv.h"
-
-/*
- * DEVICE DEVNO INT#A INT#B INT#C INT#D
- * ======= ======= ======= ======= ======= =======
- * MB86943 0 fpga.10 - - -
- * RTL8029 16 fpga.12 - - -
- * SLOT 1 19 fpga.6 fpga.5 fpga.4 fpga.3
- * SLOT 2 18 fpga.5 fpga.4 fpga.3 fpga.6
- * SLOT 3 17 fpga.4 fpga.3 fpga.6 fpga.5
- *
- */
-
-static const uint8_t __initconst pci_bus0_irq_routing[32][4] = {
- [0 ] = { IRQ_FPGA_MB86943_PCI_INTA },
- [16] = { IRQ_FPGA_RTL8029_INTA },
- [17] = { IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD, IRQ_FPGA_PCI_INTA, IRQ_FPGA_PCI_INTB },
- [18] = { IRQ_FPGA_PCI_INTB, IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD, IRQ_FPGA_PCI_INTA },
- [19] = { IRQ_FPGA_PCI_INTA, IRQ_FPGA_PCI_INTB, IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD },
-};
-
-void __init pcibios_irq_init(void)
-{
-}
-
-void __init pcibios_fixup_irqs(void)
-{
- struct pci_dev *dev = NULL;
- uint8_t line, pin;
-
- for_each_pci_dev(dev) {
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
- if (pin) {
- dev->irq = pci_bus0_irq_routing[PCI_SLOT(dev->devfn)][pin - 1];
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
- }
- pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
- }
-}
-
-void pcibios_enable_irq(struct pci_dev *dev)
-{
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-}
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
deleted file mode 100644
index f211839e2cae..000000000000
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/* pci-vdk.c: MB93090-MB00 (VDK) PCI support
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-
-#include <asm/segment.h>
-#include <asm/io.h>
-#include <asm/mb-regs.h>
-#include <asm/mb86943a.h>
-#include "pci-frv.h"
-
-unsigned int __nongpreldata pci_probe = 1;
-
-struct pci_ops *__nongpreldata pci_root_ops;
-
-/*
- * The accessible PCI window does not cover the entire CPU address space, but
- * there are devices we want to access outside of that window, so we need to
- * insert specific PCI bus resources instead of using the platform-level bus
- * resources directly for the PCI root bus.
- *
- * These are configured and inserted by pcibios_init() and are attached to the
- * root bus by pcibios_fixup_bus().
- */
-static struct resource pci_ioport_resource = {
- .name = "PCI IO",
- .start = 0,
- .end = IO_SPACE_LIMIT,
- .flags = IORESOURCE_IO,
-};
-
-static struct resource pci_iomem_resource = {
- .name = "PCI mem",
- .start = 0,
- .end = -1,
- .flags = IORESOURCE_MEM,
-};
-
-/*
- * Functions for accessing PCI configuration space
- */
-
-#define CONFIG_CMD(bus, dev, where) \
- (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
-
-#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
-
-#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
-#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
-#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
-
-#define __set_PciCfgDataB(A,V) \
- writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
-
-#define __set_PciCfgDataW(A,V) \
- writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
-
-#define __set_PciCfgDataL(A,V) \
- writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
-
-#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
-
-#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
-
-static inline int __query(const struct pci_dev *dev)
-{
-// return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
-// return dev->bus->number==1;
-// return dev->bus->number==0 &&
-// (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
- return 0;
-}
-
-/*****************************************************************************/
-/*
- *
- */
-static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
- u32 *val)
-{
- u32 _value;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- _value = __get_PciBridgeDataL(where & ~3);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- _value = __get_PciCfgDataL(where & ~3);
- }
-
- switch (size) {
- case 1:
- _value = _value >> ((where & 3) * 8);
- break;
-
- case 2:
- _value = _value >> ((where & 2) * 8);
- break;
-
- case 4:
- break;
-
- default:
- BUG();
- }
-
- *val = _value;
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
- u32 value)
-{
- switch (size) {
- case 1:
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __set_PciBridgeDataB(where, value);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- __set_PciCfgDataB(where, value);
- }
- break;
-
- case 2:
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __set_PciBridgeDataW(where, value);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- __set_PciCfgDataW(where, value);
- }
- break;
-
- case 4:
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __set_PciBridgeDataL(where, value);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- __set_PciCfgDataL(where, value);
- }
- break;
-
- default:
- BUG();
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops pci_direct_frv = {
- .read = pci_frv_read_config,
- .write = pci_frv_write_config,
-};
-
-/*
- * Before we decide to use direct hardware access mechanisms, we try to do some
- * trivial checks to ensure it at least _seems_ to be working -- we just test
- * whether bus 00 contains a host bridge (this is similar to checking
- * techniques used in XFree86, but ours should be more reliable since we
- * attempt to make use of direct access hints provided by the PCI BIOS).
- *
- * This should be close to trivial, but it isn't, because there are buggy
- * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
- */
-static int __init pci_sanity_check(struct pci_ops *o)
-{
- struct pci_bus bus; /* Fake bus and device */
- u32 id;
-
- bus.number = 0;
-
- if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
- printk("PCI: VDK Bridge device:vendor: %08x\n", id);
- if (id == 0x200e10cf)
- return 1;
- }
-
- printk("PCI: VDK Bridge: Sanity check failed\n");
- return 0;
-}
-
-static struct pci_ops * __init pci_check_direct(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- /* check if access works */
- if (pci_sanity_check(&pci_direct_frv)) {
- local_irq_restore(flags);
- printk("PCI: Using configuration frv\n");
-// request_mem_region(0xBE040000, 256, "FRV bridge");
-// request_mem_region(0xBFFFFFF4, 12, "PCI frv");
- return &pci_direct_frv;
- }
-
- local_irq_restore(flags);
- return NULL;
-}
-
-/*
- * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
- */
-
-static void __init pci_fixup_umc_ide(struct pci_dev *d)
-{
- /*
- * UM8886BF IDE controller sets region type bits incorrectly,
- * therefore they look like memory despite of them being I/O.
- */
- int i;
-
- printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
- for(i=0; i<4; i++)
- d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
-}
-
-static void pci_fixup_ide_bases(struct pci_dev *d)
-{
- int i;
-
- /*
- * PCI IDE controllers use non-standard I/O port decoding, respect it.
- */
- if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
- return;
- printk("PCI: IDE base address fixup for %s\n", pci_name(d));
- for(i=0; i<4; i++) {
- struct resource *r = &d->resource[i];
- if ((r->start & ~0x80) == 0x374) {
- r->start |= 2;
- r->end = r->start;
- }
- }
-}
-
-static void pci_fixup_ide_trash(struct pci_dev *d)
-{
- int i;
-
- /*
- * There exist PCI IDE controllers which have utter garbage
- * in first four base registers. Ignore that.
- */
- printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
- for(i=0; i<4; i++)
- d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
-}
-
-static void pci_fixup_latency(struct pci_dev *d)
-{
- /*
- * SiS 5597 and 5598 chipsets require latency timer set to
- * at most 32 to avoid lockups.
- */
- DBG("PCI: Setting max latency to 32\n");
- pcibios_max_latency = 32;
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
-
-/*
- * Called after each bus is probed, but before its children
- * are examined.
- */
-
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-#if 0
- printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
-#endif
-
- pci_read_bridge_bases(bus);
-
- if (bus->number == 0) {
- struct pci_dev *dev;
- list_for_each_entry(dev, &bus->devices, bus_list) {
- if (dev->devfn == 0) {
- dev->resource[0].start = 0;
- dev->resource[0].end = 0;
- }
- }
- }
-}
-
-/*
- * Initialization. Try all known PCI access methods. Note that we support
- * using both PCI BIOS and direct access: in such cases, we use I/O ports
- * to access config space, but we still keep BIOS order of cards to be
- * compatible with 2.0.X. This should go away some day.
- */
-
-int __init pcibios_init(void)
-{
- struct pci_bus *bus;
- struct pci_ops *dir = NULL;
- LIST_HEAD(resources);
-
- if (!mb93090_mb00_detected)
- return -ENXIO;
-
- __reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;
-
- __reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
- __reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;
-
- *(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
- *(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;
-
- __reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9;
- __reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9;
- __reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000;
- __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
- mb();
-
- /* enable PCI arbitration */
- __reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
-
- pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
- pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
- pci_ioport_resource.end += pci_ioport_resource.start;
-
- printk("PCI IO window: %08llx-%08llx\n",
- (unsigned long long) pci_ioport_resource.start,
- (unsigned long long) pci_ioport_resource.end);
-
- pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
- pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
- pci_iomem_resource.end += pci_iomem_resource.start;
-
- /* Reserve somewhere to write to flush posted writes. This is used by
- * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
- * CPU-PCI bridge to flush as this doesn't happen automatically when a
- * read is performed on the MB93090 development kit motherboard.
- */
- pci_iomem_resource.start += 0x400;
-
- printk("PCI MEM window: %08llx-%08llx\n",
- (unsigned long long) pci_iomem_resource.start,
- (unsigned long long) pci_iomem_resource.end);
- printk("PCI DMA memory: %08lx-%08lx\n",
- dma_coherent_mem_start, dma_coherent_mem_end);
-
- if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
- panic("Unable to insert PCI IOMEM resource\n");
- if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
- panic("Unable to insert PCI IOPORT resource\n");
-
- if (!pci_probe)
- return -ENXIO;
-
- dir = pci_check_direct();
- if (dir)
- pci_root_ops = dir;
- else {
- printk("PCI: No PCI bus detected\n");
- return -ENXIO;
- }
-
- printk("PCI: Probing PCI hardware\n");
- pci_add_resource(&resources, &pci_ioport_resource);
- pci_add_resource(&resources, &pci_iomem_resource);
- bus = pci_scan_root_bus(NULL, 0, pci_root_ops, NULL, &resources);
-
- pcibios_irq_init();
- pcibios_fixup_irqs();
- pcibios_resource_survey();
- if (!bus)
- return 0;
-
- pci_bus_add_devices(bus);
- return 0;
-}
-
-arch_initcall(pcibios_init);
-
-char * __init pcibios_setup(char *str)
-{
- if (!strcmp(str, "off")) {
- pci_probe = 0;
- return NULL;
- }
- return str;
-}
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- int err;
-
- if ((err = pci_enable_resources(dev, mask)) < 0)
- return err;
- if (!dev->msi_enabled)
- pcibios_enable_irq(dev);
- return 0;
-}
diff --git a/arch/frv/mm/Makefile b/arch/frv/mm/Makefile
deleted file mode 100644
index 1bca5ab8a6ab..000000000000
--- a/arch/frv/mm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Makefile for the arch-specific parts of the memory manager.
-#
-
-obj-y := init.o kmap.o
-
-obj-$(CONFIG_MMU) += \
- pgalloc.o highmem.o fault.o extable.o cache-page.o tlb-flush.o tlb-miss.o \
- mmu-context.o dma-alloc.o elf-fdpic.o
diff --git a/arch/frv/mm/cache-page.c b/arch/frv/mm/cache-page.c
deleted file mode 100644
index 8e09dae0ec3f..000000000000
--- a/arch/frv/mm/cache-page.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* cache-page.c: whole-page cache wrangling functions for MMU linux
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/highmem.h>
-#include <linux/module.h>
-#include <asm/pgalloc.h>
-
-/*****************************************************************************/
-/*
- * DCF takes a virtual address and the page may not currently have one
- * - temporarily hijack a kmap_atomic() slot and attach the page to it
- */
-void flush_dcache_page(struct page *page)
-{
- unsigned long dampr2;
- void *vaddr;
-
- dampr2 = __get_DAMPR(2);
-
- vaddr = kmap_atomic_primary(page);
-
- frv_dcache_writeback((unsigned long) vaddr, (unsigned long) vaddr + PAGE_SIZE);
-
- kunmap_atomic_primary(vaddr);
-
- if (dampr2) {
- __set_DAMPR(2, dampr2);
- __set_IAMPR(2, dampr2);
- }
-
-} /* end flush_dcache_page() */
-
-EXPORT_SYMBOL(flush_dcache_page);
-
-/*****************************************************************************/
-/*
- * ICI takes a virtual address and the page may not currently have one
- * - so we temporarily attach the page to a bit of virtual space so that is can be flushed
- */
-void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long start, unsigned long len)
-{
- unsigned long dampr2;
- void *vaddr;
-
- dampr2 = __get_DAMPR(2);
-
- vaddr = kmap_atomic_primary(page);
-
- start = (start & ~PAGE_MASK) | (unsigned long) vaddr;
- frv_cache_wback_inv(start, start + len);
-
- kunmap_atomic_primary(vaddr);
-
- if (dampr2) {
- __set_DAMPR(2, dampr2);
- __set_IAMPR(2, dampr2);
- }
-
-} /* end flush_icache_user_range() */
-
-EXPORT_SYMBOL(flush_icache_user_range);
diff --git a/arch/frv/mm/dma-alloc.c b/arch/frv/mm/dma-alloc.c
deleted file mode 100644
index e701aa9e6a14..000000000000
--- a/arch/frv/mm/dma-alloc.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* dma-alloc.c: consistent DMA memory allocation
- *
- * Derived from arch/ppc/mm/cachemap.c
- *
- * PowerPC version derived from arch/arm/mm/consistent.c
- * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
- *
- * linux/arch/arm/mm/consistent.c
- *
- * Copyright (C) 2000 Russell King
- *
- * Consistent memory allocators. Used for DMA devices that want to
- * share uncached memory with the processor core. The function return
- * is the virtual address and 'dma_handle' is the physical address.
- * Mostly stolen from the ARM port, with some changes for PowerPC.
- * -- Dan
- * Modified for 36-bit support. -Matt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/stddef.h>
-#include <linux/vmalloc.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/hardirq.h>
-#include <linux/gfp.h>
-
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/mmu.h>
-#include <linux/uaccess.h>
-#include <asm/smp.h>
-
-static int map_page(unsigned long va, unsigned long pa, pgprot_t prot)
-{
- pgd_t *pge;
- pud_t *pue;
- pmd_t *pme;
- pte_t *pte;
- int err = -ENOMEM;
-
- /* Use upper 10 bits of VA to index the first level map */
- pge = pgd_offset_k(va);
- pue = pud_offset(pge, va);
- pme = pmd_offset(pue, va);
-
- /* Use middle 10 bits of VA to index the second-level map */
- pte = pte_alloc_kernel(pme, va);
- if (pte != 0) {
- err = 0;
- set_pte(pte, mk_pte_phys(pa & PAGE_MASK, prot));
- }
-
- return err;
-}
-
-/*
- * This function will allocate the requested contiguous pages and
- * map them into the kernel's vmalloc() space. This is done so we
- * get unique mapping for these pages, outside of the kernel's 1:1
- * virtual:physical mapping. This is necessary so we can cover large
- * portions of the kernel with single large page TLB entries, and
- * still get unique uncached pages for consistent DMA.
- */
-void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
-{
- struct vm_struct *area;
- unsigned long page, va, pa;
- void *ret;
- int order, err, i;
-
- if (in_interrupt())
- BUG();
-
- /* only allocate page size areas */
- size = PAGE_ALIGN(size);
- order = get_order(size);
-
- page = __get_free_pages(gfp, order);
- if (!page) {
- BUG();
- return NULL;
- }
-
- /* allocate some common virtual space to map the new pages */
- area = get_vm_area(size, VM_ALLOC);
- if (area == 0) {
- free_pages(page, order);
- return NULL;
- }
- va = VMALLOC_VMADDR(area->addr);
- ret = (void *) va;
-
- /* this gives us the real physical address of the first page */
- *dma_handle = pa = virt_to_bus((void *) page);
-
- /* set refcount=1 on all pages in an order>0 allocation so that vfree() will actually free
- * all pages that were allocated.
- */
- if (order > 0) {
- struct page *rpage = virt_to_page(page);
- split_page(rpage, order);
- }
-
- err = 0;
- for (i = 0; i < size && err == 0; i += PAGE_SIZE)
- err = map_page(va + i, pa + i, PAGE_KERNEL_NOCACHE);
-
- if (err) {
- vfree((void *) va);
- return NULL;
- }
-
- /* we need to ensure that there are no cachelines in use, or worse dirty in this area
- * - can't do until after virtual address mappings are created
- */
- frv_cache_invalidate(va, va + size);
-
- return ret;
-}
-
-/*
- * free page(s) as defined by the above mapping.
- */
-void consistent_free(void *vaddr)
-{
- if (in_interrupt())
- BUG();
- vfree(vaddr);
-}
-
-/*
- * make an area consistent.
- */
-void consistent_sync(void *vaddr, size_t size, int direction)
-{
- unsigned long start = (unsigned long) vaddr;
- unsigned long end = start + size;
-
- switch (direction) {
- case PCI_DMA_NONE:
- BUG();
- case PCI_DMA_FROMDEVICE: /* invalidate only */
- frv_cache_invalidate(start, end);
- break;
- case PCI_DMA_TODEVICE: /* writeback only */
- frv_dcache_writeback(start, end);
- break;
- case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */
- frv_dcache_writeback(start, end);
- break;
- }
-}
-
-/*
- * consistent_sync_page make a page are consistent. identical
- * to consistent_sync, but takes a struct page instead of a virtual address
- */
-
-void consistent_sync_page(struct page *page, unsigned long offset,
- size_t size, int direction)
-{
- void *start;
-
- start = page_address(page) + offset;
- consistent_sync(start, size, direction);
-}
diff --git a/arch/frv/mm/elf-fdpic.c b/arch/frv/mm/elf-fdpic.c
deleted file mode 100644
index 46aa289c5102..000000000000
--- a/arch/frv/mm/elf-fdpic.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* elf-fdpic.c: ELF FDPIC memory layout management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/mm.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/elf-fdpic.h>
-#include <asm/mman.h>
-
-/*****************************************************************************/
-/*
- * lay out the userspace VM according to our grand design
- */
-#ifdef CONFIG_MMU
-void elf_fdpic_arch_lay_out_mm(struct elf_fdpic_params *exec_params,
- struct elf_fdpic_params *interp_params,
- unsigned long *start_stack,
- unsigned long *start_brk)
-{
- *start_stack = 0x02200000UL;
-
- /* if the only executable is a shared object, assume that it is an interpreter rather than
- * a true executable, and map it such that "ld.so --list" comes out right
- */
- if (!(interp_params->flags & ELF_FDPIC_FLAG_PRESENT) &&
- exec_params->hdr.e_type != ET_EXEC
- ) {
- exec_params->load_addr = PAGE_SIZE;
-
- *start_brk = 0x80000000UL;
- }
- else {
- exec_params->load_addr = 0x02200000UL;
-
- if ((exec_params->flags & ELF_FDPIC_FLAG_ARRANGEMENT) ==
- ELF_FDPIC_FLAG_INDEPENDENT
- ) {
- exec_params->flags &= ~ELF_FDPIC_FLAG_ARRANGEMENT;
- exec_params->flags |= ELF_FDPIC_FLAG_CONSTDISP;
- }
- }
-
-} /* end elf_fdpic_arch_lay_out_mm() */
-#endif
-
-/*****************************************************************************/
-/*
- * place non-fixed mmaps firstly in the bottom part of memory, working up, and then in the top part
- * of memory, working down
- */
-unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsigned long len,
- unsigned long pgoff, unsigned long flags)
-{
- struct vm_area_struct *vma;
- struct vm_unmapped_area_info info;
-
- if (len > TASK_SIZE)
- return -ENOMEM;
-
- /* handle MAP_FIXED */
- if (flags & MAP_FIXED)
- return addr;
-
- /* only honour a hint if we're not going to clobber something doing so */
- if (addr) {
- addr = PAGE_ALIGN(addr);
- vma = find_vma(current->mm, addr);
- if (TASK_SIZE - len >= addr &&
- (!vma || addr + len <= vm_start_gap(vma)))
- goto success;
- }
-
- /* search between the bottom of user VM and the stack grow area */
- info.flags = 0;
- info.length = len;
- info.low_limit = PAGE_SIZE;
- info.high_limit = (current->mm->start_stack - 0x00200000);
- info.align_mask = 0;
- info.align_offset = 0;
- addr = vm_unmapped_area(&info);
- if (!(addr & ~PAGE_MASK))
- goto success;
- VM_BUG_ON(addr != -ENOMEM);
-
- /* search from just above the WorkRAM area to the top of memory */
- info.low_limit = PAGE_ALIGN(0x80000000);
- info.high_limit = TASK_SIZE;
- addr = vm_unmapped_area(&info);
- if (!(addr & ~PAGE_MASK))
- goto success;
- VM_BUG_ON(addr != -ENOMEM);
-
-#if 0
- printk("[area] l=%lx (ENOMEM) f='%s'\n",
- len, filp ? filp->f_path.dentry->d_name.name : "");
-#endif
- return -ENOMEM;
-
- success:
-#if 0
- printk("[area] l=%lx ad=%lx f='%s'\n",
- len, addr, filp ? filp->f_path.dentry->d_name.name : "");
-#endif
- return addr;
-} /* end arch_get_unmapped_area() */
diff --git a/arch/frv/mm/extable.c b/arch/frv/mm/extable.c
deleted file mode 100644
index 77c0c5ba88bc..000000000000
--- a/arch/frv/mm/extable.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/frv/mm/extable.c
- */
-
-#include <linux/extable.h>
-#include <linux/spinlock.h>
-#include <linux/uaccess.h>
-
-extern const void __memset_end, __memset_user_error_lr, __memset_user_error_handler;
-extern const void __memcpy_end, __memcpy_user_error_lr, __memcpy_user_error_handler;
-extern spinlock_t modlist_lock;
-
-int fixup_exception(struct pt_regs *regs)
-{
- const struct exception_table_entry *extab;
- unsigned long pc = regs->pc;
-
- /* determine if the fault lay during a memcpy_user or a memset_user */
- if (regs->lr == (unsigned long) &__memset_user_error_lr &&
- (unsigned long) &memset <= pc && pc < (unsigned long) &__memset_end
- ) {
- /* the fault occurred in a protected memset
- * - we search for the return address (in LR) instead of the program counter
- * - it was probably during a clear_user()
- */
- regs->pc = (unsigned long) &__memset_user_error_handler;
- return 1;
- }
-
- if (regs->lr == (unsigned long) &__memcpy_user_error_lr &&
- (unsigned long) &memcpy <= pc && pc < (unsigned long) &__memcpy_end
- ) {
- /* the fault occurred in a protected memset
- * - we search for the return address (in LR) instead of the program counter
- * - it was probably during a copy_to/from_user()
- */
- regs->pc = (unsigned long) &__memcpy_user_error_handler;
- return 1;
- }
-
- extab = search_exception_tables(pc);
- if (extab) {
- regs->pc = extab->fixup;
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/frv/mm/fault.c b/arch/frv/mm/fault.c
deleted file mode 100644
index cbe7aec863e3..000000000000
--- a/arch/frv/mm/fault.c
+++ /dev/null
@@ -1,328 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/frv/mm/fault.c
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * - Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68knommu/mm/fault.c
- * - Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
- * - Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
- *
- * Based on:
- *
- * linux/arch/m68k/mm/fault.c
- *
- * Copyright (C) 1995 Hamish Macdonald
- */
-
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/uaccess.h>
-
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-
-/*****************************************************************************/
-/*
- * This routine handles page faults. It determines the problem, and
- * then passes it off to one of the appropriate routines.
- */
-asmlinkage void do_page_fault(int datammu, unsigned long esr0, unsigned long ear0)
-{
- struct vm_area_struct *vma;
- struct mm_struct *mm;
- unsigned long _pme, lrai, lrad;
- unsigned long flags = 0;
- siginfo_t info;
- pgd_t *pge;
- pud_t *pue;
- pte_t *pte;
- int fault;
-
-#if 0
- const char *atxc[16] = {
- [0x0] = "mmu-miss", [0x8] = "multi-dat", [0x9] = "multi-sat",
- [0xa] = "tlb-miss", [0xc] = "privilege", [0xd] = "write-prot",
- };
-
- printk("do_page_fault(%d,%lx [%s],%lx)\n",
- datammu, esr0, atxc[esr0 >> 20 & 0xf], ear0);
-#endif
-
- mm = current->mm;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * This verifies that the fault happens in kernel space
- * and that the fault was a page not present (invalid) error
- */
- if (!user_mode(__frame) && (esr0 & ESR0_ATXC) == ESR0_ATXC_AMRTLB_MISS) {
- if (ear0 >= VMALLOC_START && ear0 < VMALLOC_END)
- goto kernel_pte_fault;
- if (ear0 >= PKMAP_BASE && ear0 < PKMAP_END)
- goto kernel_pte_fault;
- }
-
- info.si_code = SEGV_MAPERR;
-
- /*
- * If we're in an interrupt or have no user
- * context, we must not take the fault..
- */
- if (faulthandler_disabled() || !mm)
- goto no_context;
-
- if (user_mode(__frame))
- flags |= FAULT_FLAG_USER;
-
- down_read(&mm->mmap_sem);
-
- vma = find_vma(mm, ear0);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= ear0)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
-
- if (user_mode(__frame)) {
- /*
- * accessing the stack below %esp is always a bug.
- * The "+ 32" is there due to some instructions (like
- * pusha) doing post-decrement on the stack and that
- * doesn't show up until later..
- */
- if ((ear0 & PAGE_MASK) + 2 * PAGE_SIZE < __frame->sp) {
-#if 0
- printk("[%d] ### Access below stack @%lx (sp=%lx)\n",
- current->pid, ear0, __frame->sp);
- show_registers(__frame);
- printk("[%d] ### Code: [%08lx] %02x %02x %02x %02x %02x %02x %02x %02x\n",
- current->pid,
- __frame->pc,
- ((u8*)__frame->pc)[0],
- ((u8*)__frame->pc)[1],
- ((u8*)__frame->pc)[2],
- ((u8*)__frame->pc)[3],
- ((u8*)__frame->pc)[4],
- ((u8*)__frame->pc)[5],
- ((u8*)__frame->pc)[6],
- ((u8*)__frame->pc)[7]
- );
-#endif
- goto bad_area;
- }
- }
-
- if (expand_stack(vma, ear0))
- goto bad_area;
-
-/*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
- good_area:
- info.si_code = SEGV_ACCERR;
- switch (esr0 & ESR0_ATXC) {
- default:
- /* handle write to write protected page */
- case ESR0_ATXC_WP_EXCEP:
-#ifdef TEST_VERIFY_AREA
- if (!(user_mode(__frame)))
- printk("WP fault at %08lx\n", __frame->pc);
-#endif
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- break;
-
- /* handle read from protected page */
- case ESR0_ATXC_PRIV_EXCEP:
- goto bad_area;
-
- /* handle read, write or exec on absent page
- * - can't support write without permitting read
- * - don't support execute without permitting read and vice-versa
- */
- case ESR0_ATXC_AMRTLB_MISS:
- if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
- goto bad_area;
- break;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- fault = handle_mm_fault(vma, ear0, flags);
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (fault & VM_FAULT_MAJOR)
- current->maj_flt++;
- else
- current->min_flt++;
-
- up_read(&mm->mmap_sem);
- return;
-
-/*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
- bad_area:
- up_read(&mm->mmap_sem);
-
- /* User mode accesses just cause a SIGSEGV */
- if (user_mode(__frame)) {
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void *) ear0;
- force_sig_info(SIGSEGV, &info, current);
- return;
- }
-
- no_context:
- /* are we prepared to handle this kernel fault? */
- if (fixup_exception(__frame))
- return;
-
-/*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- bust_spinlocks(1);
-
- if (ear0 < PAGE_SIZE)
- printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
- else
- printk(KERN_ALERT "Unable to handle kernel paging request");
- printk(" at virtual addr %08lx\n", ear0);
- printk(" PC : %08lx\n", __frame->pc);
- printk(" EXC : esr0=%08lx ear0=%08lx\n", esr0, ear0);
-
- asm("lrai %1,%0,#1,#0,#0" : "=&r"(lrai) : "r"(ear0));
- asm("lrad %1,%0,#1,#0,#0" : "=&r"(lrad) : "r"(ear0));
-
- printk(KERN_ALERT " LRAI: %08lx\n", lrai);
- printk(KERN_ALERT " LRAD: %08lx\n", lrad);
-
- __break_hijack_kernel_event();
-
- pge = pgd_offset(current->mm, ear0);
- pue = pud_offset(pge, ear0);
- _pme = pue->pue[0].ste[0];
-
- printk(KERN_ALERT " PGE : %8p { PME %08lx }\n", pge, _pme);
-
- if (_pme & xAMPRx_V) {
- unsigned long dampr, damlr, val;
-
- asm volatile("movsg dampr2,%0 ! movgs %2,dampr2 ! movsg damlr2,%1"
- : "=&r"(dampr), "=r"(damlr)
- : "r" (_pme | xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V)
- );
-
- pte = (pte_t *) damlr + __pte_index(ear0);
- val = pte_val(*pte);
-
- asm volatile("movgs %0,dampr2" :: "r" (dampr));
-
- printk(KERN_ALERT " PTE : %8p { %08lx }\n", pte, val);
- }
-
- die_if_kernel("Oops\n");
- do_exit(SIGKILL);
-
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
- out_of_memory:
- up_read(&mm->mmap_sem);
- if (!user_mode(__frame))
- goto no_context;
- pagefault_out_of_memory();
- return;
-
- do_sigbus:
- up_read(&mm->mmap_sem);
-
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void *) ear0;
- force_sig_info(SIGBUS, &info, current);
-
- /* Kernel mode? Handle exceptions or die */
- if (!user_mode(__frame))
- goto no_context;
- return;
-
-/*
- * The fault was caused by a kernel PTE (such as installed by vmalloc or kmap)
- */
- kernel_pte_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Do _not_ use "tsk" here. We might be inside
- * an interrupt in the middle of a task switch..
- */
- int index = pgd_index(ear0);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = (pgd_t *) __get_TTBR();
- pgd = (pgd_t *)__va(pgd) + index;
- pgd_k = ((pgd_t *)(init_mm.pgd)) + index;
-
- if (!pgd_present(*pgd_k))
- goto no_context;
- //set_pgd(pgd, *pgd_k); /////// gcc ICE's on this line
-
- pud_k = pud_offset(pgd_k, ear0);
- if (!pud_present(*pud_k))
- goto no_context;
-
- pmd_k = pmd_offset(pud_k, ear0);
- if (!pmd_present(*pmd_k))
- goto no_context;
-
- pud = pud_offset(pgd, ear0);
- pmd = pmd_offset(pud, ear0);
- set_pmd(pmd, *pmd_k);
-
- pte_k = pte_offset_kernel(pmd_k, ear0);
- if (!pte_present(*pte_k))
- goto no_context;
- return;
- }
-} /* end do_page_fault() */
diff --git a/arch/frv/mm/highmem.c b/arch/frv/mm/highmem.c
deleted file mode 100644
index 45750fb65c49..000000000000
--- a/arch/frv/mm/highmem.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* highmem.c: arch-specific highmem stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/highmem.h>
-#include <linux/module.h>
-
-void *kmap(struct page *page)
-{
- might_sleep();
- if (!PageHighMem(page))
- return page_address(page);
- return kmap_high(page);
-}
-
-EXPORT_SYMBOL(kmap);
-
-void kunmap(struct page *page)
-{
- if (in_interrupt())
- BUG();
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-
-EXPORT_SYMBOL(kunmap);
-
-void *kmap_atomic(struct page *page)
-{
- unsigned long paddr;
- int type;
-
- preempt_disable();
- pagefault_disable();
- type = kmap_atomic_idx_push();
- paddr = page_to_phys(page);
-
- switch (type) {
- /*
- * The first 4 primary maps are reserved for architecture code
- */
- case 0: return __kmap_atomic_primary(0, paddr, 6);
- case 1: return __kmap_atomic_primary(0, paddr, 7);
- case 2: return __kmap_atomic_primary(0, paddr, 8);
- case 3: return __kmap_atomic_primary(0, paddr, 9);
- case 4: return __kmap_atomic_primary(0, paddr, 10);
-
- case 5 ... 5 + NR_TLB_LINES - 1:
- return __kmap_atomic_secondary(type - 5, paddr);
-
- default:
- BUG();
- return NULL;
- }
-}
-EXPORT_SYMBOL(kmap_atomic);
-
-void __kunmap_atomic(void *kvaddr)
-{
- int type = kmap_atomic_idx();
- switch (type) {
- case 0: __kunmap_atomic_primary(0, 6); break;
- case 1: __kunmap_atomic_primary(0, 7); break;
- case 2: __kunmap_atomic_primary(0, 8); break;
- case 3: __kunmap_atomic_primary(0, 9); break;
- case 4: __kunmap_atomic_primary(0, 10); break;
-
- case 5 ... 5 + NR_TLB_LINES - 1:
- __kunmap_atomic_secondary(type - 5, kvaddr);
- break;
-
- default:
- BUG();
- }
- kmap_atomic_idx_pop();
- pagefault_enable();
- preempt_enable();
-}
-EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
deleted file mode 100644
index cf464100e838..000000000000
--- a/arch/frv/mm/init.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* init.c: memory initialisation for FRV
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Derived from:
- * - linux/arch/m68knommu/mm/init.c
- * - Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, Kenneth Albanowski <kjahds@kjahds.com>,
- * - Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
- * - linux/arch/m68k/mm/init.c
- * - Copyright (C) 1995 Hamish Macdonald
- */
-
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/sched/task.h>
-#include <linux/pagemap.h>
-#include <linux/gfp.h>
-#include <linux/swap.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/bootmem.h>
-#include <linux/highmem.h>
-#include <linux/module.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/mmu_context.h>
-#include <asm/virtconvert.h>
-#include <asm/sections.h>
-#include <asm/tlb.h>
-
-#undef DEBUG
-
-/*
- * ZERO_PAGE is a special page that is used for zero-initialized
- * data and COW.
- */
-unsigned long empty_zero_page;
-EXPORT_SYMBOL(empty_zero_page);
-
-/*****************************************************************************/
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/head.S.
- * The parameters are pointers to where to stick the starting and ending
- * addresses of available kernel virtual memory.
- */
-void __init paging_init(void)
-{
- unsigned long zones_size[MAX_NR_ZONES] = {0, };
-
- /* allocate some pages for kernel housekeeping tasks */
- empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
-
- memset((void *) empty_zero_page, 0, PAGE_SIZE);
-
-#ifdef CONFIG_HIGHMEM
- if (get_num_physpages() - num_mappedpages) {
- pgd_t *pge;
- pud_t *pue;
- pmd_t *pme;
-
- pkmap_page_table = alloc_bootmem_pages(PAGE_SIZE);
-
- pge = swapper_pg_dir + pgd_index_k(PKMAP_BASE);
- pue = pud_offset(pge, PKMAP_BASE);
- pme = pmd_offset(pue, PKMAP_BASE);
- __set_pmd(pme, virt_to_phys(pkmap_page_table) | _PAGE_TABLE);
- }
-#endif
-
- /* distribute the allocatable pages across the various zones and pass them to the allocator
- */
- zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
-#ifdef CONFIG_HIGHMEM
- zones_size[ZONE_HIGHMEM] = get_num_physpages() - num_mappedpages;
-#endif
-
- free_area_init(zones_size);
-
-#ifdef CONFIG_MMU
- /* initialise init's MMU context */
- init_new_context(&init_task, &init_mm);
-#endif
-
-} /* end paging_init() */
-
-/*****************************************************************************/
-/*
- *
- */
-void __init mem_init(void)
-{
- unsigned long code_size = _etext - _stext;
-
- /* this will put all low memory onto the freelists */
- free_all_bootmem();
-#if defined(CONFIG_MMU) && defined(CONFIG_HIGHMEM)
- {
- unsigned long pfn;
-
- for (pfn = get_num_physpages() - 1;
- pfn >= num_mappedpages; pfn--)
- free_highmem_page(&mem_map[pfn]);
- }
-#endif
-
- mem_init_print_info(NULL);
- if (rom_length > 0 && rom_length >= code_size)
- printk("Memory available: %luKiB/%luKiB ROM\n",
- (rom_length - code_size) >> 10, rom_length >> 10);
-} /* end mem_init() */
-
-/*****************************************************************************/
-/*
- * free the memory that was only required for initialisation
- */
-void free_initmem(void)
-{
-#if defined(CONFIG_RAMKERNEL) && !defined(CONFIG_PROTECT_KERNEL)
- free_initmem_default(-1);
-#endif
-} /* end free_initmem() */
-
-/*****************************************************************************/
-/*
- * free the initial ramdisk memory
- */
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-} /* end free_initrd_mem() */
-#endif
diff --git a/arch/frv/mm/kmap.c b/arch/frv/mm/kmap.c
deleted file mode 100644
index e9217e605aa8..000000000000
--- a/arch/frv/mm/kmap.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* kmap.c: ioremapping handlers
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/mm/kmap.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/vmalloc.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-
-#undef DEBUG
-
-/*****************************************************************************/
-/*
- * Map some physical address range into the kernel address space.
- */
-
-void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
-{
- return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-void iounmap(void volatile __iomem *addr)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
-{
-}
diff --git a/arch/frv/mm/mmu-context.c b/arch/frv/mm/mmu-context.c
deleted file mode 100644
index 16946a58f64d..000000000000
--- a/arch/frv/mm/mmu-context.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* mmu-context.c: MMU context allocation and management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task.h>
-#include <linux/mm.h>
-#include <asm/tlbflush.h>
-
-#define NR_CXN 4096
-
-static unsigned long cxn_bitmap[NR_CXN / (sizeof(unsigned long) * 8)];
-static LIST_HEAD(cxn_owners_lru);
-static DEFINE_SPINLOCK(cxn_owners_lock);
-
-int __nongpreldata cxn_pinned = -1;
-
-
-/*****************************************************************************/
-/*
- * initialise a new context
- */
-int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- memset(&mm->context, 0, sizeof(mm->context));
- INIT_LIST_HEAD(&mm->context.id_link);
- mm->context.itlb_cached_pge = 0xffffffffUL;
- mm->context.dtlb_cached_pge = 0xffffffffUL;
-
- return 0;
-} /* end init_new_context() */
-
-/*****************************************************************************/
-/*
- * make sure a kernel MMU context has a CPU context number
- * - call with cxn_owners_lock held
- */
-static unsigned get_cxn(mm_context_t *ctx)
-{
- struct list_head *_p;
- mm_context_t *p;
- unsigned cxn;
-
- if (!list_empty(&ctx->id_link)) {
- list_move_tail(&ctx->id_link, &cxn_owners_lru);
- }
- else {
- /* find the first unallocated context number
- * - 0 is reserved for the kernel
- */
- cxn = find_next_zero_bit(cxn_bitmap, NR_CXN, 1);
- if (cxn < NR_CXN) {
- set_bit(cxn, cxn_bitmap);
- }
- else {
- /* none remaining - need to steal someone else's cxn */
- p = NULL;
- list_for_each(_p, &cxn_owners_lru) {
- p = list_entry(_p, mm_context_t, id_link);
- if (!p->id_busy && p->id != cxn_pinned)
- break;
- }
-
- BUG_ON(_p == &cxn_owners_lru);
-
- cxn = p->id;
- p->id = 0;
- list_del_init(&p->id_link);
- __flush_tlb_mm(cxn);
- }
-
- ctx->id = cxn;
- list_add_tail(&ctx->id_link, &cxn_owners_lru);
- }
-
- return ctx->id;
-} /* end get_cxn() */
-
-/*****************************************************************************/
-/*
- * restore the current TLB miss handler mapped page tables into the MMU context and set up a
- * mapping for the page directory
- */
-void change_mm_context(mm_context_t *old, mm_context_t *ctx, pgd_t *pgd)
-{
- unsigned long _pgd;
-
- _pgd = virt_to_phys(pgd);
-
- /* save the state of the outgoing MMU context */
- old->id_busy = 0;
-
- asm volatile("movsg scr0,%0" : "=r"(old->itlb_cached_pge));
- asm volatile("movsg dampr4,%0" : "=r"(old->itlb_ptd_mapping));
- asm volatile("movsg scr1,%0" : "=r"(old->dtlb_cached_pge));
- asm volatile("movsg dampr5,%0" : "=r"(old->dtlb_ptd_mapping));
-
- /* select an MMU context number */
- spin_lock(&cxn_owners_lock);
- get_cxn(ctx);
- ctx->id_busy = 1;
- spin_unlock(&cxn_owners_lock);
-
- asm volatile("movgs %0,cxnr" : : "r"(ctx->id));
-
- /* restore the state of the incoming MMU context */
- asm volatile("movgs %0,scr0" : : "r"(ctx->itlb_cached_pge));
- asm volatile("movgs %0,dampr4" : : "r"(ctx->itlb_ptd_mapping));
- asm volatile("movgs %0,scr1" : : "r"(ctx->dtlb_cached_pge));
- asm volatile("movgs %0,dampr5" : : "r"(ctx->dtlb_ptd_mapping));
-
- /* map the PGD into uncached virtual memory */
- asm volatile("movgs %0,ttbr" : : "r"(_pgd));
- asm volatile("movgs %0,dampr3"
- :: "r"(_pgd | xAMPRx_L | xAMPRx_M | xAMPRx_SS_16Kb |
- xAMPRx_S | xAMPRx_C | xAMPRx_V));
-
-} /* end change_mm_context() */
-
-/*****************************************************************************/
-/*
- * finished with an MMU context number
- */
-void destroy_context(struct mm_struct *mm)
-{
- mm_context_t *ctx = &mm->context;
-
- spin_lock(&cxn_owners_lock);
-
- if (!list_empty(&ctx->id_link)) {
- if (ctx->id == cxn_pinned)
- cxn_pinned = -1;
-
- list_del_init(&ctx->id_link);
- clear_bit(ctx->id, cxn_bitmap);
- __flush_tlb_mm(ctx->id);
- ctx->id = 0;
- }
-
- spin_unlock(&cxn_owners_lock);
-} /* end destroy_context() */
-
-/*****************************************************************************/
-/*
- * display the MMU context currently a process is currently using
- */
-#ifdef CONFIG_PROC_FS
-char *proc_pid_status_frv_cxnr(struct mm_struct *mm, char *buffer)
-{
- spin_lock(&cxn_owners_lock);
- buffer += sprintf(buffer, "CXNR: %u\n", mm->context.id);
- spin_unlock(&cxn_owners_lock);
-
- return buffer;
-} /* end proc_pid_status_frv_cxnr() */
-#endif
-
-/*****************************************************************************/
-/*
- * (un)pin a process's mm_struct's MMU context ID
- */
-int cxn_pin_by_pid(pid_t pid)
-{
- struct task_struct *tsk;
- struct mm_struct *mm = NULL;
- int ret;
-
- /* unpin if pid is zero */
- if (pid == 0) {
- cxn_pinned = -1;
- return 0;
- }
-
- ret = -ESRCH;
-
- /* get a handle on the mm_struct */
- read_lock(&tasklist_lock);
- tsk = find_task_by_vpid(pid);
- if (tsk) {
- ret = -EINVAL;
-
- task_lock(tsk);
- if (tsk->mm) {
- mm = tsk->mm;
- mmget(mm);
- ret = 0;
- }
- task_unlock(tsk);
- }
- read_unlock(&tasklist_lock);
-
- if (ret < 0)
- return ret;
-
- /* make sure it has a CXN and pin it */
- spin_lock(&cxn_owners_lock);
- cxn_pinned = get_cxn(&mm->context);
- spin_unlock(&cxn_owners_lock);
-
- mmput(mm);
- return 0;
-} /* end cxn_pin_by_pid() */
diff --git a/arch/frv/mm/pgalloc.c b/arch/frv/mm/pgalloc.c
deleted file mode 100644
index c9ed14f6c67d..000000000000
--- a/arch/frv/mm/pgalloc.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* pgalloc.c: page directory & page table allocation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/gfp.h>
-#include <linux/mm.h>
-#include <linux/highmem.h>
-#include <linux/quicklist.h>
-#include <asm/pgalloc.h>
-#include <asm/page.h>
-#include <asm/cacheflush.h>
-
-pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__((aligned(PAGE_SIZE)));
-
-pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL);
- if (pte)
- clear_page(pte);
- return pte;
-}
-
-pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *page;
-
-#ifdef CONFIG_HIGHPTE
- page = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM, 0);
-#else
- page = alloc_pages(GFP_KERNEL, 0);
-#endif
- if (!page)
- return NULL;
-
- clear_highpage(page);
- if (!pgtable_page_ctor(page)) {
- __free_page(page);
- return NULL;
- }
- flush_dcache_page(page);
- return page;
-}
-
-void __set_pmd(pmd_t *pmdptr, unsigned long pmd)
-{
- unsigned long *__ste_p = pmdptr->ste;
- int loop;
-
- if (!pmd) {
- memset(__ste_p, 0, PME_SIZE);
- }
- else {
- BUG_ON(pmd & (0x3f00 | xAMPRx_SS | 0xe));
-
- for (loop = PME_SIZE; loop > 0; loop -= 4) {
- *__ste_p++ = pmd;
- pmd += __frv_PT_SIZE;
- }
- }
-
- frv_dcache_writeback((unsigned long) pmdptr, (unsigned long) (pmdptr + 1));
-}
-
-/*
- * List of all pgd's needed for non-PAE so it can invalidate entries
- * in both cached and uncached pgd's; not needed for PAE since the
- * kernel pmd is shared. If PAE were not to share the pmd a similar
- * tactic would be needed. This is essentially codepath-based locking
- * against pageattr.c; it is the unique case in which a valid change
- * of kernel pagetables can't be lazily synchronized by vmalloc faults.
- * vmalloc faults work because attached pagetables are never freed.
- * If the locking proves to be non-performant, a ticketing scheme with
- * checks at dup_mmap(), exec(), and other mmlist addition points
- * could be used. The locking scheme was chosen on the basis of
- * manfred's recommendations and having no core impact whatsoever.
- * -- nyc
- */
-DEFINE_SPINLOCK(pgd_lock);
-struct page *pgd_list;
-
-static inline void pgd_list_add(pgd_t *pgd)
-{
- struct page *page = virt_to_page(pgd);
- page->index = (unsigned long) pgd_list;
- if (pgd_list)
- set_page_private(pgd_list, (unsigned long) &page->index);
- pgd_list = page;
- set_page_private(page, (unsigned long)&pgd_list);
-}
-
-static inline void pgd_list_del(pgd_t *pgd)
-{
- struct page *next, **pprev, *page = virt_to_page(pgd);
- next = (struct page *) page->index;
- pprev = (struct page **) page_private(page);
- *pprev = next;
- if (next)
- set_page_private(next, (unsigned long) pprev);
-}
-
-void pgd_ctor(void *pgd)
-{
- unsigned long flags;
-
- if (PTRS_PER_PMD == 1)
- spin_lock_irqsave(&pgd_lock, flags);
-
- memcpy((pgd_t *) pgd + USER_PGDS_IN_LAST_PML4,
- swapper_pg_dir + USER_PGDS_IN_LAST_PML4,
- (PTRS_PER_PGD - USER_PGDS_IN_LAST_PML4) * sizeof(pgd_t));
-
- if (PTRS_PER_PMD > 1)
- return;
-
- pgd_list_add(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
- memset(pgd, 0, USER_PGDS_IN_LAST_PML4 * sizeof(pgd_t));
-}
-
-/* never called when PTRS_PER_PMD > 1 */
-void pgd_dtor(void *pgd)
-{
- unsigned long flags; /* can be called from interrupt context */
-
- spin_lock_irqsave(&pgd_lock, flags);
- pgd_list_del(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
-}
-
-pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- return quicklist_alloc(0, GFP_KERNEL, pgd_ctor);
-}
-
-void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- /* in the non-PAE case, clear_page_tables() clears user pgd entries */
- quicklist_free(0, pgd_dtor, pgd);
-}
-
-void __init pgtable_cache_init(void)
-{
-}
-
-void check_pgt_cache(void)
-{
- quicklist_trim(0, pgd_dtor, 25, 16);
-}
-
diff --git a/arch/frv/mm/tlb-flush.S b/arch/frv/mm/tlb-flush.S
deleted file mode 100644
index 79b3c70910ac..000000000000
--- a/arch/frv/mm/tlb-flush.S
+++ /dev/null
@@ -1,184 +0,0 @@
-/* tlb-flush.S: TLB flushing routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/spr-regs.h>
-
-.macro DEBUG ch
-# sethi.p %hi(0xfeff9c00),gr4
-# setlo %lo(0xfeff9c00),gr4
-# setlos #\ch,gr5
-# stbi gr5,@(gr4,#0)
-# membar
-.endm
-
- .section .rodata
-
- # sizes corresponding to TPXR.LMAX
- .balign 1
-__tlb_lmax_sizes:
- .byte 0, 64, 0, 0
- .byte 0, 0, 0, 0
- .byte 0, 0, 0, 0
- .byte 0, 0, 0, 0
-
- .section .text
- .balign 4
-
-###############################################################################
-#
-# flush everything
-# - void __flush_tlb_all(void)
-#
-###############################################################################
- .globl __flush_tlb_all
- .type __flush_tlb_all,@function
-__flush_tlb_all:
- DEBUG 'A'
-
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # kill AMPR-cached TLB values
- movgs gr0,iamlr1
- movgs gr0,iampr1
- movgs gr0,damlr1
- movgs gr0,dampr1
-
- # find out how many lines there are
- movsg tpxr,gr5
- sethi.p %hi(__tlb_lmax_sizes),gr4
- srli gr5,#TPXR_LMAX_SHIFT,gr5
- setlo.p %lo(__tlb_lmax_sizes),gr4
- andi gr5,#TPXR_LMAX_SMASK,gr5
- ldub @(gr4,gr5),gr4
-
- # now, we assume that the TLB line step is page size in size
- setlos.p #PAGE_SIZE,gr5
- setlos #0,gr6
-1:
- tlbpr gr6,gr0,#6,#0
- subicc.p gr4,#1,gr4,icc0
- add gr6,gr5,gr6
- bne icc0,#2,1b
-
- DEBUG 'B'
- bralr
-
- .size __flush_tlb_all, .-__flush_tlb_all
-
-###############################################################################
-#
-# flush everything to do with one context
-# - void __flush_tlb_mm(unsigned long contextid [GR8])
-#
-###############################################################################
- .globl __flush_tlb_mm
- .type __flush_tlb_mm,@function
-__flush_tlb_mm:
- DEBUG 'M'
-
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # specify the context we want to flush
- movgs gr8,tplr
-
- # find out how many lines there are
- movsg tpxr,gr5
- sethi.p %hi(__tlb_lmax_sizes),gr4
- srli gr5,#TPXR_LMAX_SHIFT,gr5
- setlo.p %lo(__tlb_lmax_sizes),gr4
- andi gr5,#TPXR_LMAX_SMASK,gr5
- ldub @(gr4,gr5),gr4
-
- # now, we assume that the TLB line step is page size in size
- setlos.p #PAGE_SIZE,gr5
- setlos #0,gr6
-0:
- tlbpr gr6,gr0,#5,#0
- subicc.p gr4,#1,gr4,icc0
- add gr6,gr5,gr6
- bne icc0,#2,0b
-
- DEBUG 'N'
- bralr
-
- .size __flush_tlb_mm, .-__flush_tlb_mm
-
-###############################################################################
-#
-# flush a range of addresses from the TLB
-# - void __flush_tlb_page(unsigned long contextid [GR8],
-# unsigned long start [GR9])
-#
-###############################################################################
- .globl __flush_tlb_page
- .type __flush_tlb_page,@function
-__flush_tlb_page:
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # specify the context we want to flush
- movgs gr8,tplr
-
- # zap the matching TLB line and AMR values
- setlos #~(PAGE_SIZE-1),gr5
- and gr9,gr5,gr9
- tlbpr gr9,gr0,#5,#0
-
- bralr
-
- .size __flush_tlb_page, .-__flush_tlb_page
-
-###############################################################################
-#
-# flush a range of addresses from the TLB
-# - void __flush_tlb_range(unsigned long contextid [GR8],
-# unsigned long start [GR9],
-# unsigned long end [GR10])
-#
-###############################################################################
- .globl __flush_tlb_range
- .type __flush_tlb_range,@function
-__flush_tlb_range:
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # specify the context we want to flush
- movgs gr8,tplr
-
- # round the start down to beginning of TLB line and end up to beginning of next TLB line
- setlos.p #~(PAGE_SIZE-1),gr5
- setlos #PAGE_SIZE,gr6
- subi.p gr10,#1,gr10
- and gr9,gr5,gr9
- and gr10,gr5,gr10
-2:
- tlbpr gr9,gr0,#5,#0
- subcc.p gr9,gr10,gr0,icc0
- add gr9,gr6,gr9
- bne icc0,#0,2b ; most likely a 1-page flush
-
- bralr
-
- .size __flush_tlb_range, .-__flush_tlb_range
diff --git a/arch/frv/mm/tlb-miss.S b/arch/frv/mm/tlb-miss.S
deleted file mode 100644
index f3ac019bb18b..000000000000
--- a/arch/frv/mm/tlb-miss.S
+++ /dev/null
@@ -1,629 +0,0 @@
-/* tlb-miss.S: TLB miss handlers
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/spr-regs.h>
-
- .section .text..tlbmiss
- .balign 4
-
- .globl __entry_insn_mmu_miss
-__entry_insn_mmu_miss:
- break
- nop
-
- .globl __entry_insn_mmu_exception
-__entry_insn_mmu_exception:
- break
- nop
-
- .globl __entry_data_mmu_miss
-__entry_data_mmu_miss:
- break
- nop
-
- .globl __entry_data_mmu_exception
-__entry_data_mmu_exception:
- break
- nop
-
-###############################################################################
-#
-# handle a lookup failure of one sort or another in a kernel TLB handler
-# On entry:
-# GR29 - faulting address
-# SCR2 - saved CCR
-#
-###############################################################################
- .type __tlb_kernel_fault,@function
-__tlb_kernel_fault:
- # see if we're supposed to re-enable single-step mode upon return
- sethi.p %hi(__break_tlb_miss_return_break),gr30
- setlo %lo(__break_tlb_miss_return_break),gr30
- movsg pcsr,gr31
-
- subcc gr31,gr30,gr0,icc0
- beq icc0,#0,__tlb_kernel_fault_sstep
-
- movsg scr2,gr30
- movgs gr30,ccr
- movgs gr29,scr2 /* save EAR0 value */
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi.p @(gr29,#0),gr29 /* restore GR29 */
-
- bra __entry_kernel_handle_mmu_fault
-
- # we've got to re-enable single-stepping
-__tlb_kernel_fault_sstep:
- sethi.p %hi(__break_tlb_miss_real_return_info),gr30
- setlo %lo(__break_tlb_miss_real_return_info),gr30
- lddi @(gr30,0),gr30
- movgs gr30,pcsr
- movgs gr31,psr
-
- movsg scr2,gr30
- movgs gr30,ccr
- movgs gr29,scr2 /* save EAR0 value */
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi.p @(gr29,#0),gr29 /* restore GR29 */
- bra __entry_kernel_handle_mmu_fault_sstep
-
- .size __tlb_kernel_fault, .-__tlb_kernel_fault
-
-###############################################################################
-#
-# handle a lookup failure of one sort or another in a user TLB handler
-# On entry:
-# GR28 - faulting address
-# SCR2 - saved CCR
-#
-###############################################################################
- .type __tlb_user_fault,@function
-__tlb_user_fault:
- # see if we're supposed to re-enable single-step mode upon return
- sethi.p %hi(__break_tlb_miss_return_break),gr30
- setlo %lo(__break_tlb_miss_return_break),gr30
- movsg pcsr,gr31
- subcc gr31,gr30,gr0,icc0
- beq icc0,#0,__tlb_user_fault_sstep
-
- movsg scr2,gr30
- movgs gr30,ccr
- bra __entry_uspace_handle_mmu_fault
-
- # we've got to re-enable single-stepping
-__tlb_user_fault_sstep:
- sethi.p %hi(__break_tlb_miss_real_return_info),gr30
- setlo %lo(__break_tlb_miss_real_return_info),gr30
- lddi @(gr30,0),gr30
- movgs gr30,pcsr
- movgs gr31,psr
- movsg scr2,gr30
- movgs gr30,ccr
- bra __entry_uspace_handle_mmu_fault_sstep
-
- .size __tlb_user_fault, .-__tlb_user_fault
-
-###############################################################################
-#
-# Kernel instruction TLB miss handler
-# On entry:
-# GR1 - kernel stack pointer
-# GR28 - saved exception frame pointer
-# GR29 - faulting address
-# GR31 - EAR0 ^ SCR0
-# SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR4 - mapped page table as matched by SCR0
-#
-###############################################################################
- .globl __entry_kernel_insn_tlb_miss
- .type __entry_kernel_insn_tlb_miss,@function
-__entry_kernel_insn_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__itlb_k_PTD_miss
-
-__itlb_k_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR4 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr4,gr30
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using IAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- # - need to check DAMR1 lest we cause an multiple-DAT-hit exception
- # - IAMPR1 has no WP bit, and we mustn't lose WP information
- movsg iampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__itlb_k_nopunt /* punt not required */
-
- movsg iamlr1,gr31
- movgs gr31,tplr /* set TPLR.CXN */
- tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
-
- movsg dampr1,gr31
- ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
- movgs gr31,tppr
- movsg iamlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_kernel_fault
-
-__itlb_k_nopunt:
-
- # assemble the new TLB entry
- and gr29,gr31,gr29
- movsg cxnr,gr31
- or gr29,gr31,gr29
- movgs gr29,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr29,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi @(gr29,#0),gr29
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__itlb_k_PTD_miss:
- srli gr29,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__itlb_k_bigpage
- movgs gr30,dampr4
- movgs gr31,scr0
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __itlb_k_PTD_mapped
-
-__itlb_k_bigpage:
- break
- nop
-
- .size __entry_kernel_insn_tlb_miss, .-__entry_kernel_insn_tlb_miss
-
-###############################################################################
-#
-# Kernel data TLB miss handler
-# On entry:
-# GR1 - kernel stack pointer
-# GR28 - saved exception frame pointer
-# GR29 - faulting address
-# GR31 - EAR0 ^ SCR1
-# SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR5 - mapped page table as matched by SCR1
-#
-###############################################################################
- .globl __entry_kernel_data_tlb_miss
- .type __entry_kernel_data_tlb_miss,@function
-__entry_kernel_data_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__dtlb_k_PTD_miss
-
-__dtlb_k_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR5 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr5,gr30
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using DAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- # - need to check IAMR1 lest we cause an multiple-DAT-hit exception
- movsg dampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__dtlb_k_nopunt /* punt not required */
-
- movsg damlr1,gr31
- movgs gr31,tplr /* set TPLR.CXN */
- tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
-
- movsg dampr1,gr31
- ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
- movgs gr31,tppr
- movsg damlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_kernel_fault
-
-__dtlb_k_nopunt:
-
- # assemble the new TLB entry
- and gr29,gr31,gr29
- movsg cxnr,gr31
- or gr29,gr31,gr29
- movgs gr29,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr29,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi @(gr29,#0),gr29
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__dtlb_k_PTD_miss:
- srli gr29,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__dtlb_k_bigpage
- movgs gr30,dampr5
- movgs gr31,scr1
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __dtlb_k_PTD_mapped
-
-__dtlb_k_bigpage:
- break
- nop
-
- .size __entry_kernel_data_tlb_miss, .-__entry_kernel_data_tlb_miss
-
-###############################################################################
-#
-# Userspace instruction TLB miss handler (with PGE prediction)
-# On entry:
-# GR28 - faulting address
-# GR31 - EAR0 ^ SCR0
-# SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR4 - mapped page table as matched by SCR0
-#
-###############################################################################
- .globl __entry_user_insn_tlb_miss
- .type __entry_user_insn_tlb_miss,@function
-__entry_user_insn_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__itlb_u_PTD_miss
-
-__itlb_u_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR4 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr4,gr30
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using IAMR1/DAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- movsg dampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__itlb_u_nopunt /* punt not required */
-
- movsg dampr1,gr31
- movgs gr31,tppr
- movsg damlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_user_fault
-
-__itlb_u_nopunt:
-
- # assemble the new TLB entry
- and gr28,gr31,gr28
- movsg cxnr,gr31
- or gr28,gr31,gr28
- movgs gr28,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr28,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__itlb_u_PTD_miss:
- srli gr28,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__itlb_u_bigpage
- movgs gr30,dampr4
- movgs gr31,scr0
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __itlb_u_PTD_mapped
-
-__itlb_u_bigpage:
- break
- nop
-
- .size __entry_user_insn_tlb_miss, .-__entry_user_insn_tlb_miss
-
-###############################################################################
-#
-# Userspace data TLB miss handler
-# On entry:
-# GR28 - faulting address
-# GR31 - EAR0 ^ SCR1
-# SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR5 - mapped page table as matched by SCR1
-#
-###############################################################################
- .globl __entry_user_data_tlb_miss
- .type __entry_user_data_tlb_miss,@function
-__entry_user_data_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__dtlb_u_PTD_miss
-
-__dtlb_u_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR5 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr5,gr30
-
-__dtlb_u_using_iPTD:
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using DAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- movsg dampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__dtlb_u_nopunt /* punt not required */
-
- movsg dampr1,gr31
- movgs gr31,tppr
- movsg damlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_user_fault
-
-__dtlb_u_nopunt:
-
- # assemble the new TLB entry
- and gr28,gr31,gr28
- movsg cxnr,gr31
- or gr28,gr31,gr28
- movgs gr28,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr28,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - first of all, check the insn PGE cache - we may well get a hit there
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__dtlb_u_PTD_miss:
- movsg scr0,gr31 /* consult the insn-PGE-cache key */
- xor gr28,gr31,gr31
- srlicc gr31,#26,gr0,icc0
- srli gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__dtlb_u_iPGE_miss
-
- # what we're looking for is covered by the insn-PGE-cache
- setlos 0x3ffc,gr30
- and gr31,gr30,gr31
- movsg damlr4,gr30
- bra __dtlb_u_using_iPTD
-
-__dtlb_u_iPGE_miss:
- srli gr28,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__dtlb_u_bigpage
- movgs gr30,dampr5
- movgs gr31,scr1
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __dtlb_u_PTD_mapped
-
-__dtlb_u_bigpage:
- break
- nop
-
- .size __entry_user_data_tlb_miss, .-__entry_user_data_tlb_miss
diff --git a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c
index 085adfcc74a4..9ebe1d633abc 100644
--- a/arch/ia64/kernel/sys_ia64.c
+++ b/arch/ia64/kernel/sys_ia64.c
@@ -139,7 +139,7 @@ int ia64_mmap_check(unsigned long addr, unsigned long len,
asmlinkage unsigned long
sys_mmap2 (unsigned long addr, unsigned long len, int prot, int flags, int fd, long pgoff)
{
- addr = sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
+ addr = ksys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
if (!IS_ERR((void *) addr))
force_successful_syscall_return();
return addr;
@@ -151,7 +151,7 @@ sys_mmap (unsigned long addr, unsigned long len, int prot, int flags, int fd, lo
if (offset_in_page(off) != 0)
return -EINVAL;
- addr = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ addr = ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
if (!IS_ERR((void *) addr))
force_successful_syscall_return();
return addr;
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index f5ec736100ee..7ccc64d5fe3e 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -398,7 +398,7 @@ pcibios_enable_device (struct pci_dev *dev, int mask)
if (ret < 0)
return ret;
- if (!dev->msi_enabled)
+ if (!pci_dev_msi_enabled(dev))
return acpi_pci_irq_enable(dev);
return 0;
}
@@ -407,7 +407,7 @@ void
pcibios_disable_device (struct pci_dev *dev)
{
BUG_ON(atomic_read(&dev->enable_cnt));
- if (!dev->msi_enabled)
+ if (!pci_dev_msi_enabled(dev))
acpi_pci_irq_disable(dev);
}
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
deleted file mode 100644
index dd84ee194579..000000000000
--- a/arch/m32r/Kconfig
+++ /dev/null
@@ -1,419 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config M32R
- bool
- default y
- select HAVE_IDE
- select HAVE_OPROFILE
- select INIT_ALL_POSSIBLE
- select HAVE_KERNEL_GZIP
- select HAVE_KERNEL_BZIP2
- select HAVE_KERNEL_LZMA
- select ARCH_WANT_IPC_PARSE_VERSION
- select HAVE_DEBUG_BUGVERBOSE
- select VIRT_TO_BUS
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select GENERIC_ATOMIC64
- select ARCH_HAS_DEVMEM_IS_ALLOWED
- select ARCH_USES_GETTIMEOFFSET
- select MODULES_USE_ELF_RELA
- select HAVE_DEBUG_STACKOVERFLOW
- select CPU_NO_EFFICIENT_FFS
- select DMA_DIRECT_OPS
- select ARCH_NO_COHERENT_DMA_MMAP if !MMU
-
-config SBUS
- bool
-
-config GENERIC_ISA_DMA
- bool
- default y
-
-config ZONE_DMA
- bool
- default y
-
-config NO_IOPORT_MAP
- def_bool y
-
-config NO_DMA
- def_bool n
-
-config HZ
- int
- default 100
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-
-menu "Processor type and features"
-
-choice
- prompt "Platform Type"
- default PLAT_MAPPI
-
-config PLAT_MAPPI
- bool "Mappi-I"
- help
- The Mappi-I is an FPGA board for SOC (System-On-a-Chip) prototyping.
- You can operate a Linux system on this board by using an M32R
- softmacro core, which is a fully-synthesizable functional model
- described in Verilog-HDL.
-
- The Mappi-I board was the first platform, which had been used
- to port and develop a Linux system for the M32R processor.
- Currently, the Mappi-II, an heir to the Mappi-I, is available.
-
-config PLAT_USRV
- bool "uServer"
- select PLAT_HAS_INT1ICU
-
-config PLAT_M32700UT
- bool "M32700UT"
- select PLAT_HAS_INT0ICU
- select PLAT_HAS_INT1ICU
- select PLAT_HAS_INT2ICU
- help
- The M3T-M32700UT is an evaluation board based on uT-Engine
- specification. This board has an M32700 (Chaos) evaluation chip.
- You can say Y for SMP, because the M32700 is a single chip
- multiprocessor.
-
-config PLAT_OPSPUT
- bool "OPSPUT"
- select PLAT_HAS_INT0ICU
- select PLAT_HAS_INT1ICU
- select PLAT_HAS_INT2ICU
- help
- The OPSPUT is an evaluation board based on uT-Engine
- specification. This board has a OPSP-REP chip.
-
-config PLAT_OAKS32R
- bool "OAKS32R"
- help
- The OAKS32R is a tiny, inexpensive evaluation board.
- Please note that if you say Y here and choose chip "M32102",
- say N for MMU and select a no-MMU version kernel, otherwise
- a kernel with MMU support will not work, because the M32102
- is a microcontroller for embedded systems and it has no MMU.
-
-config PLAT_MAPPI2
- bool "Mappi-II(M3A-ZA36/M3A-ZA52)"
-
-config PLAT_MAPPI3
- bool "Mappi-III(M3A-2170)"
-
-config PLAT_M32104UT
- bool "M32104UT"
- select PLAT_HAS_INT1ICU
- help
- The M3T-M32104UT is an reference board based on uT-Engine
- specification. This board has a M32104 chip.
-
-endchoice
-
-choice
- prompt "Processor family"
- default CHIP_M32700
-
-config CHIP_M32700
- bool "M32700 (Chaos)"
-
-config CHIP_M32102
- bool "M32102"
-
-config CHIP_M32104
- bool "M32104"
- depends on PLAT_M32104UT
-
-config CHIP_VDEC2
- bool "VDEC2"
-
-config CHIP_OPSP
- bool "OPSP"
-
-endchoice
-
-config MMU
- bool "Support for memory management hardware"
- depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
- default y
-
-config TLB_ENTRIES
- int "TLB Entries"
- depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
- default 32 if CHIP_M32700 || CHIP_OPSP
- default 16 if CHIP_VDEC2
-
-
-config ISA_M32R
- bool
- depends on CHIP_M32102 || CHIP_M32104
- default y
-
-config ISA_M32R2
- bool
- depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
- default y
-
-config ISA_DSP_LEVEL2
- bool
- depends on CHIP_M32700 || CHIP_OPSP
- default y
-
-config ISA_DUAL_ISSUE
- bool
- depends on CHIP_M32700 || CHIP_OPSP
- default y
-
-config PLAT_HAS_INT0ICU
- bool
- default n
-
-config PLAT_HAS_INT1ICU
- bool
- default n
-
-config PLAT_HAS_INT2ICU
- bool
- default n
-
-config BUS_CLOCK
- int "Bus Clock [Hz] (integer)"
- default "70000000" if PLAT_MAPPI
- default "25000000" if PLAT_USRV
- default "50000000" if PLAT_MAPPI3
- default "50000000" if PLAT_M32700UT
- default "50000000" if PLAT_OPSPUT
- default "54000000" if PLAT_M32104UT
- default "33333333" if PLAT_OAKS32R
- default "20000000" if PLAT_MAPPI2
-
-config TIMER_DIVIDE
- int "Timer divider (integer)"
- default "128"
-
-config CPU_BIG_ENDIAN
- bool
- default !CPU_LITTLE_ENDIAN
-
-config CPU_LITTLE_ENDIAN
- bool "Generate little endian code"
- default n
-
-config MEMORY_START
- hex "Physical memory start address (hex)"
- default "08000000" if PLAT_MAPPI || PLAT_MAPPI2 || PLAT_MAPPI3
- default "08000000" if PLAT_USRV
- default "08000000" if PLAT_M32700UT
- default "08000000" if PLAT_OPSPUT
- default "04000000" if PLAT_M32104UT
- default "01000000" if PLAT_OAKS32R
-
-config MEMORY_SIZE
- hex "Physical memory size (hex)"
- default "08000000" if PLAT_MAPPI3
- default "04000000" if PLAT_MAPPI || PLAT_MAPPI2
- default "02000000" if PLAT_USRV
- default "01000000" if PLAT_M32700UT
- default "01000000" if PLAT_OPSPUT
- default "01000000" if PLAT_M32104UT
- default "00800000" if PLAT_OAKS32R
-
-config ARCH_DISCONTIGMEM_ENABLE
- bool "Internal RAM Support"
- depends on CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104
- default y
-
-source "mm/Kconfig"
-
-config IRAM_START
- hex "Internal memory start address (hex)"
- default "00f00000" if !CHIP_M32104
- default "00700000" if CHIP_M32104
- depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104) && DISCONTIGMEM
-
-config IRAM_SIZE
- hex "Internal memory size (hex)"
- depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104) && DISCONTIGMEM
- default "00080000" if CHIP_M32700
- default "00010000" if CHIP_M32102 || CHIP_OPSP || CHIP_M32104
- default "00008000" if CHIP_VDEC2
-
-#
-# Define implied options from the CPU selection here
-#
-
-config GENERIC_LOCKBREAK
- bool
- default y
- depends on SMP && PREEMPT
-
-config RWSEM_GENERIC_SPINLOCK
- bool
- depends on M32R
- default y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
- default n
-
-config ARCH_HAS_ILOG2_U32
- bool
- default n
-
-config ARCH_HAS_ILOG2_U64
- bool
- default n
-
-config GENERIC_HWEIGHT
- bool
- default y
-
-config GENERIC_CALIBRATE_DELAY
- bool
- default y
-
-config SCHED_OMIT_FRAME_POINTER
- bool
- default y
-
-source "kernel/Kconfig.preempt"
-
-config SMP
- bool "Symmetric multi-processing support"
- depends on MMU
- ---help---
- This enables support for systems with more than one CPU. If you have
- a system with only one CPU, say N. If you have a system with more
- than one CPU, say Y.
-
- If you say N here, the kernel will run on uni- and multiprocessor
- machines, but will use only one CPU of a multiprocessor machine. If
- you say Y here, the kernel will run on many, but not all,
- uniprocessor machines. On a uniprocessor machine, the kernel
- will run faster if you say N here.
-
- People using multiprocessor machines who say Y here should also say
- Y to "Enhanced Real Time Clock Support", below. The "Advanced Power
- Management" code will be disabled if you say Y here.
-
- See also the SMP-HOWTO available at
- <http://tldp.org/HOWTO/SMP-HOWTO.html>.
-
- If you don't know what to do here, say N.
-
-config CHIP_M32700_TS1
- bool "Workaround code for the M32700 TS1 chip's bug"
- depends on (CHIP_M32700 && SMP)
- default n
-
-config NR_CPUS
- int "Maximum number of CPUs (2-32)"
- range 2 32
- depends on SMP
- default "2"
- help
- This allows you to specify the maximum number of CPUs which this
- kernel will support. The maximum supported value is 32 and the
- minimum value which makes sense is 2.
-
- This is purely to save memory - each supported CPU adds
- approximately eight kilobytes to the kernel image.
-
-# Common NUMA Features
-config NUMA
- bool "Numa Memory Allocation Support"
- depends on SMP && BROKEN
- default n
-
-config NODES_SHIFT
- int
- default "1"
- depends on NEED_MULTIPLE_NODES
-
-endmenu
-
-
-menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
-
-config PCI
- bool "PCI support"
- depends on BROKEN
- default n
- help
- Find out whether you have a PCI motherboard. PCI is the name of a
- bus system, i.e. the way the CPU talks to the other stuff inside
- your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
- VESA. If you have PCI, say Y, otherwise N.
-
-choice
- prompt "PCI access mode"
- depends on PCI
- default PCI_GOANY
-
-config PCI_GOBIOS
- bool "BIOS"
- ---help---
- On PCI systems, the BIOS can be used to detect the PCI devices and
- determine their configuration. However, some old PCI motherboards
- have BIOS bugs and may crash if this is done. Also, some embedded
- PCI-based systems don't have any BIOS at all. Linux can also try to
- detect the PCI hardware directly without using the BIOS.
-
- With this option, you can specify how Linux should detect the PCI
- devices. If you choose "BIOS", the BIOS will be used, if you choose
- "Direct", the BIOS won't be used, and if you choose "Any", the
- kernel will try the direct access method and falls back to the BIOS
- if that doesn't work. If unsure, go with the default, which is
- "Any".
-
-config PCI_GODIRECT
- bool "Direct"
-
-config PCI_GOANY
- bool "Any"
-
-endchoice
-
-config PCI_BIOS
- bool
- depends on PCI && (PCI_GOBIOS || PCI_GOANY)
- default y
-
-config PCI_DIRECT
- bool
- depends on PCI && (PCI_GODIRECT || PCI_GOANY)
- default y
-
-source "drivers/pci/Kconfig"
-
-config ISA
- bool
-
-source "drivers/pcmcia/Kconfig"
-
-endmenu
-
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/m32r/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
deleted file mode 100644
index ffca1e194f91..000000000000
--- a/arch/m32r/Kconfig.debug
+++ /dev/null
@@ -1,22 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_PAGEALLOC
- bool "Debug page memory allocations"
- depends on DEBUG_KERNEL && BROKEN
- help
- Unmap pages from the kernel linear mapping after free_pages().
- This results in a large slowdown, but helps to find certain types
- of memory corruptions.
-
-config FRAME_POINTER
- bool "Compile the kernel with frame pointers"
- help
- If you say Y here the resulting kernel image will be slightly larger
- and slower, but it will give very useful debugging information.
- If you don't debug the kernel, you can say N, but we may not be able
- to solve problems without frame pointers.
-
-endmenu
diff --git a/arch/m32r/Makefile b/arch/m32r/Makefile
deleted file mode 100644
index d73b58c847a6..000000000000
--- a/arch/m32r/Makefile
+++ /dev/null
@@ -1,63 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# m32r/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies.
-#
-
-KBUILD_DEFCONFIG := m32700ut.smp_defconfig
-
-LDFLAGS :=
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-LDFLAGS_vmlinux :=
-
-KBUILD_CFLAGS += -pipe -fno-schedule-insns
-KBUILD_CFLAGS_KERNEL += -mmodel=medium
-KBUILD_CFLAGS_MODULE += -mmodel=large
-
-ifdef CONFIG_CHIP_VDEC2
-cflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -Wa,-bitinst
-aflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -O2 -Wa,-bitinst -Wa,-no-parallel
-else
-cflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -m32r2
-aflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -m32r2 -O2
-endif
-
-cflags-$(CONFIG_ISA_M32R) += -DNO_FPU
-aflags-$(CONFIG_ISA_M32R) += -DNO_FPU -O2 -Wa,-no-bitinst
-
-KBUILD_CFLAGS += $(cflags-y)
-KBUILD_AFLAGS += $(aflags-y)
-
-CHECKFLAGS += -D__m32r__ -D__BIG_ENDIAN__=1
-
-head-y := arch/m32r/kernel/head.o
-
-LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
-
-libs-y += arch/m32r/lib/ $(LIBGCC)
-core-y += arch/m32r/kernel/ \
- arch/m32r/mm/ \
- arch/m32r/boot/ \
- arch/m32r/platforms/
-
-drivers-$(CONFIG_OPROFILE) += arch/m32r/oprofile/
-
-boot := arch/m32r/boot
-
-PHONY += zImage
-
-all: zImage
-
-zImage: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-compressed: zImage
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-define archhelp
- echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
-endef
diff --git a/arch/m32r/boot/Makefile b/arch/m32r/boot/Makefile
deleted file mode 100644
index af2cef475d98..000000000000
--- a/arch/m32r/boot/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# arch/m32r/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-
-targets := zImage
-subdir- := compressed
-
-obj-y := setup.o
-
-$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
- $(call if_changed,objcopy)
- @echo 'Kernel: $@ is ready'
-
-$(obj)/compressed/vmlinux: FORCE
- $(Q)$(MAKE) $(build)=$(obj)/compressed $@
-
diff --git a/arch/m32r/boot/compressed/Makefile b/arch/m32r/boot/compressed/Makefile
deleted file mode 100644
index abd3c75ebd32..000000000000
--- a/arch/m32r/boot/compressed/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# linux/arch/m32r/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \
- vmlinux.bin.lzma head.o misc.o piggy.o vmlinux.lds
-
-OBJECTS = $(obj)/head.o $(obj)/misc.o
-
-#
-# IMAGE_OFFSET is the load offset of the compression loader
-#
-#IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+0x2000])
-#IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+0x00400000])
-
-LDFLAGS_vmlinux := -T
-
-$(obj)/vmlinux: $(obj)/vmlinux.lds $(OBJECTS) $(obj)/piggy.o FORCE
- $(call if_changed,ld)
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzma)
-
-CFLAGS_misc.o += -fpic
-
-ifdef CONFIG_MMU
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-m32r-linux -T
-else
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-m32r -T
-endif
-
-OBJCOPYFLAGS += -R .empty_zero_page
-
-suffix-$(CONFIG_KERNEL_GZIP) = gz
-suffix-$(CONFIG_KERNEL_BZIP2) = bz2
-suffix-$(CONFIG_KERNEL_LZMA) = lzma
-
-$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE
- $(call if_changed,ld)
diff --git a/arch/m32r/boot/compressed/boot.h b/arch/m32r/boot/compressed/boot.h
deleted file mode 100644
index 7fce713e8aac..000000000000
--- a/arch/m32r/boot/compressed/boot.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * 1. load vmlinuz
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinuz |
- * +-----------------------+
- * 2. decompressed
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinuz |
- * +-----------------------+
- * | |
- * BOOT_RELOC_ADDR +-----------------------+
- * | |
- * KERNEL_DECOMPRESS_ADDR +-----------------------+
- * | vmlinux |
- * +-----------------------+
- *
- * 3. relocate copy & jump code
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinuz |
- * +-----------------------+
- * | |
- * BOOT_RELOC_ADDR +-----------------------+
- * | boot(copy&jump) |
- * KERNEL_DECOMPRESS_ADDR +-----------------------+
- * | vmlinux |
- * +-----------------------+
- *
- * 4. relocate decompressed kernel
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinux |
- * +-----------------------+
- * | |
- * BOOT_RELOC_ADDR +-----------------------+
- * | boot(copy&jump) |
- * KERNEL_DECOMPRESS_ADDR +-----------------------+
- * | |
- * +-----------------------+
- *
- */
-#ifdef __ASSEMBLY__
-#define __val(x) x
-#else
-#define __val(x) (x)
-#endif
-
-#define DECOMPRESS_OFFSET_BASE __val(0x00900000)
-#define BOOT_RELOC_SIZE __val(0x00001000)
-
-#define KERNEL_EXEC_ADDR __val(CONFIG_MEMORY_START)
-#define KERNEL_DECOMPRESS_ADDR __val(CONFIG_MEMORY_START + \
- DECOMPRESS_OFFSET_BASE + BOOT_RELOC_SIZE)
-#define KERNEL_ENTRY __val(CONFIG_MEMORY_START + 0x1000)
-
-#define BOOT_EXEC_ADDR __val(CONFIG_MEMORY_START)
-#define BOOT_RELOC_ADDR __val(CONFIG_MEMORY_START + DECOMPRESS_OFFSET_BASE)
diff --git a/arch/m32r/boot/compressed/head.S b/arch/m32r/boot/compressed/head.S
deleted file mode 100644
index 39b693640375..000000000000
--- a/arch/m32r/boot/compressed/head.S
+++ /dev/null
@@ -1,177 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/boot/compressed/head.S
- *
- * Copyright (c) 2001-2003 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi
- * Copyright (c) 2004 Hirokazu Takata
- */
-
- .text
-#include <linux/linkage.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-#include <asm/assembler.h>
-
- /*
- * This code can be loaded anywhere, as long as output will not
- * overlap it.
- *
- * NOTE: This head.S should *NOT* be compiled with -fpic.
- *
- */
-
- .global startup
- .global __bss_start, _ebss, end, zimage_data, zimage_len
- __ALIGN
-startup:
- ldi r0, #0x0000 /* SPI, disable EI */
- mvtc r0, psw
-
- ldi r12, #-8
- bl 1f
- .fillinsn
-1:
- seth r1, #high(CONFIG_MEMORY_START + 0x00400000) /* Start address */
- add r12, r14 /* Real address */
- sub r12, r1 /* difference */
-
- .global got_len
- seth r3, #high(_GLOBAL_OFFSET_TABLE_+8)
- or3 r3, r3, #low(_GLOBAL_OFFSET_TABLE_+12)
- add r3, r14
-
- /* Update the contents of global offset table */
- ldi r1, #low(got_len)
- srli r1, #2
- beqz r1, 2f
- .fillinsn
-1:
- ld r2, @r3
- add r2, r12
- st r2, @r3
- addi r3, #4
- addi r1, #-1
- bnez r1, 1b
- .fillinsn
-2:
- /* XXX: resolve plt */
-
-/*
- * Clear BSS first so that there are no surprises...
- */
-#ifdef CONFIG_ISA_DUAL_ISSUE
- seth r2, #high(__bss_start)
- or3 r2, r2, #low(__bss_start)
- add r2, r12
- seth r3, #high(_ebss)
- or3 r3, r3, #low(_ebss)
- add r3, r12
- sub r3, r2
-
- ; R4 = BSS size in longwords (rounded down)
- mv r4, r3 || ldi r1, #0
- srli r4, #4 || addi r2, #-4
- beqz r4, .Lendloop1
-.Lloop1:
-#ifndef CONFIG_CHIP_M32310
- ; Touch memory for the no-write-allocating cache.
- ld r0, @(4,r2)
-#endif
- st r1, @+r2 || addi r4, #-1
- st r1, @+r2
- st r1, @+r2
- st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
- bnc .Lloop1
-.Lendloop1:
- and3 r4, r3, #15
- addi r2, #4
- beqz r4, .Lendloop2
-.Lloop2:
- stb r1, @r2 || addi r4, #-1
- addi r2, #1
- bnez r4, .Lloop2
-.Lendloop2:
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
- seth r2, #high(__bss_start)
- or3 r2, r2, #low(__bss_start)
- add r2, r12
- seth r3, #high(_ebss)
- or3 r3, r3, #low(_ebss)
- add r3, r12
- sub r3, r2
- mv r4, r3
- srli r4, #2 ; R4 = BSS size in longwords (rounded down)
- ldi r1, #0 ; clear R1 for longwords store
- addi r2, #-4 ; account for pre-inc store
- beqz r4, .Lendloop1 ; any more to go?
-.Lloop1:
- st r1, @+r2 ; yep, zero out another longword
- addi r4, #-1 ; decrement count
- bnez r4, .Lloop1 ; go do some more
-.Lendloop1:
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
- seth r1, #high(end)
- or3 r1, r1, #low(end)
- add r1, r12
- mv sp, r1
-
-/*
- * decompress the kernel
- */
- mv r0, sp
- srli r0, 31 /* MMU is ON or OFF */
- seth r1, #high(zimage_data)
- or3 r1, r1, #low(zimage_data)
- add r1, r12
- seth r2, #high(zimage_len)
- or3 r2, r2, #low(zimage_len)
- mv r3, sp
-
- bl decompress_kernel
-
-#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_VDEC2)
- /* Cache flush */
- ldi r0, -1
- ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
- stb r1, @r0
-#elif defined(CONFIG_CHIP_M32102)
- /* Cache flush */
- ldi r0, -2
- ldi r1, 0x0100 ; invalidate
- stb r1, @r0
-#elif defined(CONFIG_CHIP_M32104)
- /* Cache flush */
- ldi r0, -2
- ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
- sth r1, @r0
-#else
-#error "put your cache flush function, please"
-#endif
-
- mv r0, sp
- srli r0, 31 /* MMU is ON or OFF */
- slli r0, 31
- or3 r0, r0, #0x2000
- seth r1, #high(CONFIG_MEMORY_START)
- or r0, r1
- jmp r0
-
- .balign 512
-fake_headers_as_bzImage:
- .short 0
- .ascii "HdrS"
- .short 0x0202
- .short 0
- .short 0
- .byte 0x00, 0x10
- .short 0
- .byte 0
- .byte 1
- .byte 0x00, 0x80
- .long 0
- .long 0
-
diff --git a/arch/m32r/boot/compressed/install.sh b/arch/m32r/boot/compressed/install.sh
deleted file mode 100644
index 16e5a0a13437..000000000000
--- a/arch/m32r/boot/compressed/install.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/sh
-#
-# arch/sh/boot/install.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-# Adapted from code in arch/i386/boot/install.sh by Russell King
-# Adapted from code in arch/arm/boot/install.sh by Stuart Menefy
-# Adapted from code in arch/sh/boot/install.sh by Takeo Takahashi
-#
-# "make install" script for sh architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install path (blank if root directory)
-#
-
-# User may have a custom install script
-
-if [ -x /sbin/${INSTALLKERNEL} ]; then
- exec /sbin/${INSTALLKERNEL} "$@"
-fi
-
-if [ "$2" = "zImage" ]; then
-# Compressed install
- echo "Installing compressed kernel"
- if [ -f $4/vmlinuz-$1 ]; then
- mv $4/vmlinuz-$1 $4/vmlinuz.old
- fi
-
- if [ -f $4/System.map-$1 ]; then
- mv $4/System.map-$1 $4/System.old
- fi
-
- cat $2 > $4/vmlinuz-$1
- cp $3 $4/System.map-$1
-else
-# Normal install
- echo "Installing normal kernel"
- if [ -f $4/vmlinux-$1 ]; then
- mv $4/vmlinux-$1 $4/vmlinux.old
- fi
-
- if [ -f $4/System.map ]; then
- mv $4/System.map $4/System.old
- fi
-
- cat $2 > $4/vmlinux-$1
- cp $3 $4/System.map
-fi
diff --git a/arch/m32r/boot/compressed/m32r_sio.c b/arch/m32r/boot/compressed/m32r_sio.c
deleted file mode 100644
index 9d34bd063c31..000000000000
--- a/arch/m32r/boot/compressed/m32r_sio.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/m32r/boot/compressed/m32r_sio.c
- *
- * 2003-02-12: Takeo Takahashi
- * 2006-11-30: OPSPUT support by Kazuhiro Inaoka
- *
- */
-
-#include <asm/processor.h>
-
-static void m32r_putc(char c);
-
-static int puts(const char *s)
-{
- char c;
- while ((c = *s++))
- m32r_putc(c);
- return 0;
-}
-
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT)
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define USE_FPGA_MAP 0
-
-#if USE_FPGA_MAP
-/*
- * fpga configuration program uses MMU, and define map as same as
- * M32104 uT-Engine board.
- */
-#define BOOT_SIO0STS (volatile unsigned short *)(0x02c00000 + 0x20006)
-#define BOOT_SIO0TXB (volatile unsigned short *)(0x02c00000 + 0x2000c)
-#else
-#undef PLD_BASE
-#if defined(CONFIG_PLAT_OPSPUT)
-#define PLD_BASE 0x1cc00000
-#else
-#define PLD_BASE 0xa4c00000
-#endif
-#define BOOT_SIO0STS PLD_ESIO0STS
-#define BOOT_SIO0TXB PLD_ESIO0TXB
-#endif
-
-static void m32r_putc(char c)
-{
- while ((*BOOT_SIO0STS & 0x3) != 0x3)
- cpu_relax();
- if (c == '\n') {
- *BOOT_SIO0TXB = '\r';
- while ((*BOOT_SIO0STS & 0x3) != 0x3)
- cpu_relax();
- }
- *BOOT_SIO0TXB = c;
-}
-#else /* !(CONFIG_PLAT_M32700UT) */
-#if defined(CONFIG_PLAT_MAPPI2)
-#define SIO0STS (volatile unsigned short *)(0xa0efd000 + 14)
-#define SIO0TXB (volatile unsigned short *)(0xa0efd000 + 30)
-#else
-#define SIO0STS (volatile unsigned short *)(0x00efd000 + 14)
-#define SIO0TXB (volatile unsigned short *)(0x00efd000 + 30)
-#endif
-
-static void m32r_putc(char c)
-{
- while ((*SIO0STS & 0x1) == 0)
- cpu_relax();
- if (c == '\n') {
- *SIO0TXB = '\r';
- while ((*SIO0STS & 0x1) == 0)
- cpu_relax();
- }
- *SIO0TXB = c;
-}
-#endif
diff --git a/arch/m32r/boot/compressed/misc.c b/arch/m32r/boot/compressed/misc.c
deleted file mode 100644
index 43e367055669..000000000000
--- a/arch/m32r/boot/compressed/misc.c
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/m32r/boot/compressed/misc.c
- *
- * This is a collection of several routines from gzip-1.0.3
- * adapted for Linux.
- *
- * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
- *
- * Adapted for SH by Stuart Menefy, Aug 1999
- *
- * 2003-02-12: Support M32R by Takeo Takahashi
- */
-
-/*
- * gzip declarations
- */
-#define STATIC static
-
-#undef memset
-#undef memcpy
-#define memzero(s, n) memset ((s), 0, (n))
-
-static void error(char *m);
-
-#include "m32r_sio.c"
-
-static unsigned long free_mem_ptr;
-static unsigned long free_mem_end_ptr;
-
-#ifdef CONFIG_KERNEL_BZIP2
-void *memset(void *s, int c, size_t n)
-{
- char *ss = s;
-
- while (n--)
- *ss++ = c;
- return s;
-}
-#endif
-
-#ifdef CONFIG_KERNEL_GZIP
-void *memcpy(void *dest, const void *src, size_t n)
-{
- char *d = dest;
- const char *s = src;
- while (n--)
- *d++ = *s++;
-
- return dest;
-}
-
-#define BOOT_HEAP_SIZE 0x10000
-#include "../../../../lib/decompress_inflate.c"
-#endif
-
-#ifdef CONFIG_KERNEL_BZIP2
-#define BOOT_HEAP_SIZE 0x400000
-#include "../../../../lib/decompress_bunzip2.c"
-#endif
-
-#ifdef CONFIG_KERNEL_LZMA
-#define BOOT_HEAP_SIZE 0x10000
-#include "../../../../lib/decompress_unlzma.c"
-#endif
-
-static void error(char *x)
-{
- puts("\n\n");
- puts(x);
- puts("\n\n -- System halted");
-
- while(1); /* Halt */
-}
-
-void
-decompress_kernel(int mmu_on, unsigned char *zimage_data,
- unsigned int zimage_len, unsigned long heap)
-{
- unsigned char *input_data = zimage_data;
- int input_len = zimage_len;
- unsigned char *output_data;
-
- output_data = (unsigned char *)CONFIG_MEMORY_START + 0x2000
- + (mmu_on ? 0x80000000 : 0);
- free_mem_ptr = heap;
- free_mem_end_ptr = free_mem_ptr + BOOT_HEAP_SIZE;
-
- puts("\nDecompressing Linux... ");
- __decompress(input_data, input_len, NULL, NULL, output_data, 0,
- NULL, error);
- puts("done.\nBooting the kernel.\n");
-}
diff --git a/arch/m32r/boot/compressed/vmlinux.lds.S b/arch/m32r/boot/compressed/vmlinux.lds.S
deleted file mode 100644
index c393eb559c4c..000000000000
--- a/arch/m32r/boot/compressed/vmlinux.lds.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-OUTPUT_ARCH(m32r)
-ENTRY(startup)
-SECTIONS
-{
- . = CONFIG_MEMORY_START + 0x00400000;
-
- _text = .;
- .text : { *(.text) } = 0
- .rodata : { *(.rodata) *(.rodata.*) }
- _etext = .;
-
- . = ALIGN(32 / 8);
- .data : { *(.data) }
- . = ALIGN(32 / 8);
- _got = .;
- .got : { *(.got) _egot = .; *(.got.*) }
- _edata = .;
-
- . = ALIGN(32 / 8);
- __bss_start = .;
- .bss : { *(.bss) *(.sbss) }
- . = ALIGN(32 / 8);
- _ebss = .;
- . = ALIGN(4096);
- . += 4096;
- end = . ;
-
- got_len = (_egot - _got);
-}
diff --git a/arch/m32r/boot/compressed/vmlinux.scr b/arch/m32r/boot/compressed/vmlinux.scr
deleted file mode 100644
index 924c7992c55b..000000000000
--- a/arch/m32r/boot/compressed/vmlinux.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-SECTIONS
-{
- .data : {
- zimage_data = .;
- *(.data)
- zimage_data_end = .;
- }
- zimage_len = zimage_data_end - zimage_data;
-}
diff --git a/arch/m32r/boot/setup.S b/arch/m32r/boot/setup.S
deleted file mode 100644
index 5909a825e2ed..000000000000
--- a/arch/m32r/boot/setup.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/boot/setup.S -- A setup code.
- *
- * Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Hayato Fujiwara
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-#include <asm/assembler.h>
-#include <asm/mmu_context.h>
-#include <asm/m32r.h>
-
-/*
- * References to members of the boot_cpu_data structure.
- */
-
-#define CPU_PARAMS boot_cpu_data
-#define M32R_MCICAR 0xfffffff0
-#define M32R_MCDCAR 0xfffffff4
-#define M32R_MCCR 0xfffffffc
-#define M32R_BSCR0 0xffffffd2
-
-;BSEL
-#define BSEL0CR0 0x00ef5000
-#define BSEL0CR1 0x00ef5004
-#define BSEL1CR0 0x00ef5100
-#define BSEL1CR1 0x00ef5104
-#define BSEL0CR0_VAL 0x00000000
-#define BSEL0CR1_VAL 0x01200100
-#define BSEL1CR0_VAL 0x01018000
-#define BSEL1CR1_VAL 0x00200001
-
-;SDRAMC
-#define SDRAMC_SDRF0 0x00ef6000
-#define SDRAMC_SDRF1 0x00ef6004
-#define SDRAMC_SDIR0 0x00ef6008
-#define SDRAMC_SDIR1 0x00ef600c
-#define SDRAMC_SD0ADR 0x00ef6020
-#define SDRAMC_SD0ER 0x00ef6024
-#define SDRAMC_SD0TR 0x00ef6028
-#define SDRAMC_SD0MOD 0x00ef602c
-#define SDRAMC_SD1ADR 0x00ef6040
-#define SDRAMC_SD1ER 0x00ef6044
-#define SDRAMC_SD1TR 0x00ef6048
-#define SDRAMC_SD1MOD 0x00ef604c
-#define SDRAM0 0x18000000
-#define SDRAM1 0x1c000000
-
-/*------------------------------------------------------------------------
- * start up
- */
-
-/*------------------------------------------------------------------------
- * Kernel entry
- */
- .section .boot, "ax"
-ENTRY(boot)
-
-/* Set cache mode */
-#if defined(CONFIG_CHIP_XNUX2)
- ldi r0, #-2 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x0101 ; cache on (with invalidation)
-; ldi r1, #0x00 ; cache off
- sth r1, @r0
-#elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
- || defined(CONFIG_CHIP_OPSP)
- ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x73 ; cache on (with invalidation)
-; ldi r1, #0x00 ; cache off
- st r1, @r0
-#elif defined(CONFIG_CHIP_M32102)
- ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x101 ; cache on (with invalidation)
-; ldi r1, #0x00 ; cache off
- st r1, @r0
-#elif defined(CONFIG_CHIP_M32104)
- ldi r0, #-96 ; DNCR0
- seth r1, #0x0060 ; from 0x00600000
- or3 r1, r1, #0x0005 ; size 2MB
- st r1, @r0
- seth r1, #0x0100 ; from 0x01000000
- or3 r1, r1, #0x0003 ; size 16MB
- st r1, @+r0
- seth r1, #0x0200 ; from 0x02000000
- or3 r1, r1, #0x0002 ; size 32MB
- st r1, @+r0
- ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x703 ; cache on (with invalidation)
- st r1, @r0
-#else
-#error unknown chip configuration
-#endif
-
-#ifdef CONFIG_SMP
- ;; if not BSP (CPU#0) goto AP_loop
- seth r5, #shigh(M32R_CPUID_PORTL)
- ld r5, @(low(M32R_CPUID_PORTL), r5)
- bnez r5, AP_loop
-#if !defined(CONFIG_PLAT_USRV)
- ;; boot AP
- ld24 r5, #0xeff2f8 ; IPICR7
- ldi r6, #0x2 ; IPI to CPU1
- st r6, @r5
-#endif
-#endif
-
-/*
- * Now, Jump to stext
- * if with MMU, TLB on.
- * if with no MMU, only jump.
- */
- .global eit_vector
-mmu_on:
- LDIMM (r13, stext)
-#ifdef CONFIG_MMU
- bl init_tlb
- LDIMM (r2, eit_vector) ; set EVB(cr5)
- mvtc r2, cr5
- seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
- or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
- ldi r1, #0x01
- st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
- ld r0, @(MATM_offset,r0) ; Check
-#else
-#if defined(CONFIG_CHIP_M32700)
- seth r0,#high(M32R_MCDCAR)
- or3 r0,r0,#low(M32R_MCDCAR)
- ld24 r1,#0x8080
- st r1,@r0
-#elif defined(CONFIG_CHIP_M32104)
- LDIMM (r2, eit_vector) ; set EVB(cr5)
- mvtc r2, cr5
-#endif
-#endif /* CONFIG_MMU */
- jmp r13
- nop
- nop
-
-#ifdef CONFIG_SMP
-/*
- * AP wait loop
- */
-ENTRY(AP_loop)
- ;; disable interrupt
- clrpsw #0x40
- ;; reset EVB
- LDIMM (r4, _AP_RE)
- seth r5, #high(__PAGE_OFFSET)
- or3 r5, r5, #low(__PAGE_OFFSET)
- not r5, r5
- and r4, r5
- mvtc r4, cr5
- ;; disable maskable interrupt
- seth r4, #high(M32R_ICU_IMASK_PORTL)
- or3 r4, r4, #low(M32R_ICU_IMASK_PORTL)
- ldi r5, #0
- st r5, @r4
- ld r5, @r4
- ;; enable only IPI
- setpsw #0x40
- ;; LOOOOOOOOOOOOOOP!!!
- .fillinsn
-2:
- nop
- nop
- bra 2b
- nop
- nop
-
-#ifdef CONFIG_CHIP_M32700_TS1
- .global dcache_dummy
- .balign 16, 0
-dcache_dummy:
- .byte 16
-#endif /* CONFIG_CHIP_M32700_TS1 */
-#endif /* CONFIG_SMP */
-
- .end
-
diff --git a/arch/m32r/configs/m32104ut_defconfig b/arch/m32r/configs/m32104ut_defconfig
deleted file mode 100644
index 4aa42acbd512..000000000000
--- a/arch/m32r/configs/m32104ut_defconfig
+++ /dev/null
@@ -1,144 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_M32104UT=y
-CONFIG_CHIP_M32104=y
-CONFIG_MEMORY_START=0x04000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00700000
-CONFIG_IRAM_SIZE=0x00010000
-CONFIG_PREEMPT=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_PARPORT=m
-CONFIG_PARPORT_1284=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_RAID1=y
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_NE2000=m
-CONFIG_SERIAL_8250=m
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_932=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_LIBCRC32C=m
diff --git a/arch/m32r/configs/m32700ut.smp_defconfig b/arch/m32r/configs/m32700ut.smp_defconfig
deleted file mode 100644
index 41a0495b65df..000000000000
--- a/arch/m32r/configs/m32700ut.smp_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_M32700UT=y
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_SMP=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_BE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_SERIAL_M32R_PLDSIO=y
-CONFIG_HW_RANDOM=y
-CONFIG_DS1302=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_S1D13XXX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_REISERFS_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/m32700ut.up_defconfig b/arch/m32r/configs/m32700ut.up_defconfig
deleted file mode 100644
index 20078a866f45..000000000000
--- a/arch/m32r/configs/m32700ut.up_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_M32700UT=y
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_BE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_SERIAL_M32R_PLDSIO=y
-CONFIG_HW_RANDOM=y
-CONFIG_DS1302=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_S1D13XXX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_REISERFS_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi.nommu_defconfig b/arch/m32r/configs/mappi.nommu_defconfig
deleted file mode 100644
index 4bf3820e054a..000000000000
--- a/arch/m32r/configs/mappi.nommu_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_MMU is not set
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x00000000
-CONFIG_MEMORY_SIZE=0x00E00000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_M32R_PCC=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi.smp_defconfig b/arch/m32r/configs/mappi.smp_defconfig
deleted file mode 100644
index f9ed7bdbf4de..000000000000
--- a/arch/m32r/configs/mappi.smp_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_BUS_CLOCK=10000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x04000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_SMP=y
-CONFIG_CHIP_M32700_TS1=y
-CONFIG_PCCARD=y
-CONFIG_M32R_PCC=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=m
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi.up_defconfig b/arch/m32r/configs/mappi.up_defconfig
deleted file mode 100644
index 289ae7421e12..000000000000
--- a/arch/m32r/configs/mappi.up_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_BUS_CLOCK=10000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x04000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_M32R_PCC=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=m
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi2.opsp_defconfig b/arch/m32r/configs/mappi2.opsp_defconfig
deleted file mode 100644
index 2852f6e7e246..000000000000
--- a/arch/m32r/configs/mappi2.opsp_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_MAPPI2=y
-CONFIG_CHIP_OPSP=y
-CONFIG_TLB_ENTRIES=16
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00008000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi2.vdec2_defconfig b/arch/m32r/configs/mappi2.vdec2_defconfig
deleted file mode 100644
index 8da4dbad8510..000000000000
--- a/arch/m32r/configs/mappi2.vdec2_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_MAPPI2=y
-CONFIG_CHIP_VDEC2=y
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00008000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi3.smp_defconfig b/arch/m32r/configs/mappi3.smp_defconfig
deleted file mode 100644
index 5605b23e2faf..000000000000
--- a/arch/m32r/configs/mappi3.smp_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_MAPPI3=y
-CONFIG_BUS_CLOCK=10000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x08000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_SMP=y
-CONFIG_PCCARD=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/oaks32r_defconfig b/arch/m32r/configs/oaks32r_defconfig
deleted file mode 100644
index 5ccab127f6ad..000000000000
--- a/arch/m32r/configs/oaks32r_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_OAKS32R=y
-CONFIG_CHIP_M32102=y
-CONFIG_MEMORY_START=0x01000000
-CONFIG_MEMORY_SIZE=0x00800000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00010000
-CONFIG_PREEMPT=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/opsput_defconfig b/arch/m32r/configs/opsput_defconfig
deleted file mode 100644
index 3ce1d08355e5..000000000000
--- a/arch/m32r/configs/opsput_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_OPSPUT=y
-CONFIG_CHIP_OPSP=y
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00010000
-CONFIG_PCCARD=y
-CONFIG_M32R_CFC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_SERIAL_M32R_PLDSIO=y
-CONFIG_HW_RANDOM=y
-CONFIG_DS1302=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/m32r/configs/usrv_defconfig b/arch/m32r/configs/usrv_defconfig
deleted file mode 100644
index cb8c051c3d46..000000000000
--- a/arch/m32r/configs/usrv_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PLAT_USRV=y
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x02000000
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SMP=y
-CONFIG_PCCARD=y
-CONFIG_M32R_CFC=y
-CONFIG_M32R_CFC_NUM=2
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_INET_AH=y
-CONFIG_INET_ESP=y
-CONFIG_INET_IPCOMP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_BE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_M32R_SIO is not set
-# CONFIG_HWMON is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_POINTER=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ARC4=y
diff --git a/arch/m32r/include/asm/Kbuild b/arch/m32r/include/asm/Kbuild
deleted file mode 100644
index 985ef1d9f556..000000000000
--- a/arch/m32r/include/asm/Kbuild
+++ /dev/null
@@ -1,13 +0,0 @@
-generic-y += current.h
-generic-y += dma-mapping.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += irq_work.h
-generic-y += kprobes.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += module.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += trace_clock.h
-generic-y += word-at-a-time.h
diff --git a/arch/m32r/include/asm/addrspace.h b/arch/m32r/include/asm/addrspace.h
deleted file mode 100644
index 81782c122da4..000000000000
--- a/arch/m32r/include/asm/addrspace.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 by Hiroyuki Kondo
- *
- * Defitions for the address spaces of the M32R CPUs.
- */
-#ifndef __ASM_M32R_ADDRSPACE_H
-#define __ASM_M32R_ADDRSPACE_H
-
-/*
- * Memory segments (32bit kernel mode addresses)
- */
-#define KUSEG 0x00000000
-#define KSEG0 0x80000000
-#define KSEG1 0xa0000000
-#define KSEG2 0xc0000000
-#define KSEG3 0xe0000000
-
-#define K0BASE KSEG0
-
-/*
- * Returns the kernel segment base of a given address
- */
-#ifndef __ASSEMBLY__
-#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000)
-#else
-#define KSEGX(a) ((a) & 0xe0000000)
-#endif
-
-/*
- * Returns the physical address of a KSEG0/KSEG1 address
- */
-#ifndef __ASSEMBLY__
-#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
-#else
-#define PHYSADDR(a) ((a) & 0x1fffffff)
-#endif
-
-/*
- * Map an address to a certain kernel segment
- */
-#ifndef __ASSEMBLY__
-#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
-#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1))
-#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
-#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3))
-#else
-#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
-#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
-#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
-#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
-#endif
-
-#endif /* __ASM_M32R_ADDRSPACE_H */
diff --git a/arch/m32r/include/asm/asm-offsets.h b/arch/m32r/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/m32r/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/m32r/include/asm/assembler.h b/arch/m32r/include/asm/assembler.h
deleted file mode 100644
index ed90d894f285..000000000000
--- a/arch/m32r/include/asm/assembler.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_ASSEMBLER_H
-#define _ASM_M32R_ASSEMBLER_H
-
-/*
- * linux/asm-m32r/assembler.h
- *
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- *
- * This file contains M32R architecture specific macro definitions.
- */
-
-#include <linux/stringify.h>
-
-#undef __STR
-
-#ifdef __ASSEMBLY__
-#define __STR(x) x
-#else
-#define __STR(x) __stringify(x)
-#endif
-
-#ifdef CONFIG_SMP
-#define M32R_LOCK __STR(lock)
-#define M32R_UNLOCK __STR(unlock)
-#else
-#define M32R_LOCK __STR(ld)
-#define M32R_UNLOCK __STR(st)
-#endif
-
-#ifdef __ASSEMBLY__
-#undef ENTRY
-#define ENTRY(name) ENTRY_M name
- .macro ENTRY_M name
- .global \name
- ALIGN
-\name:
- .endm
-#endif
-
-
-/**
- * LDIMM - load immediate value
- * STI - enable interruption
- * CLI - disable interruption
- */
-
-#ifdef __ASSEMBLY__
-
-#define LDIMM(reg,x) LDIMM reg x
- .macro LDIMM reg x
- seth \reg, #high(\x)
- or3 \reg, \reg, #low(\x)
- .endm
-
-#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
-#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
- .macro ENABLE_INTERRUPTS reg
- setpsw #0x40 -> nop
- ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
- .endm
-
-#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
- .macro DISABLE_INTERRUPTS reg
- clrpsw #0x40 -> nop
- ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
- .endm
-#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
-#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
- .macro ENABLE_INTERRUPTS reg
- mvfc \reg, psw
- or3 \reg, \reg, #0x0040
- mvtc \reg, psw
- .endm
-
-#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
- .macro DISABLE_INTERRUPTS reg
- mvfc \reg, psw
- and3 \reg, \reg, #0xffbf
- mvtc \reg, psw
- .endm
-#endif /* CONFIG_CHIP_M32102 */
-
- .macro SAVE_ALL
- push r0 ; orig_r0
- push sp ; spi (r15)
- push lr ; r14
- push r13
- mvfc r13, cr3 ; spu
- push r13
- mvfc r13, bbpc
- push r13
- mvfc r13, bbpsw
- push r13
- mvfc r13, bpc
- push r13
- mvfc r13, psw
- push r13
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
- mvfaclo r13, a1
- push r13
- mvfachi r13, a1
- push r13
- mvfaclo r13, a0
- push r13
- mvfachi r13, a0
- push r13
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
- mvfaclo r13
- push r13
- mvfachi r13
- push r13
- ldi r13, #0
- push r13 ; dummy push acc1h
- push r13 ; dummy push acc1l
-#else
-#error unknown isa configuration
-#endif
- ldi r13, #-1
- push r13 ; syscall_nr (default: -1)
- push r12
- push r11
- push r10
- push r9
- push r8
- push r7
- push r3
- push r2
- push r1
- push r0
- addi sp, #-4 ; room for implicit pt_regs parameter
- push r6
- push r5
- push r4
- .endm
-
- .macro RESTORE_ALL
- pop r4
- pop r5
- pop r6
- addi sp, #4
- pop r0
- pop r1
- pop r2
- pop r3
- pop r7
- pop r8
- pop r9
- pop r10
- pop r11
- pop r12
- addi r15, #4 ; Skip syscall number
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
- pop r13
- mvtachi r13, a0
- pop r13
- mvtaclo r13, a0
- pop r13
- mvtachi r13, a1
- pop r13
- mvtaclo r13, a1
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
- pop r13 ; dummy pop acc1h
- pop r13 ; dummy pop acc1l
- pop r13
- mvtachi r13
- pop r13
- mvtaclo r13
-#else
-#error unknown isa configuration
-#endif
- pop r14
- mvtc r14, psw
- pop r14
- mvtc r14, bpc
- addi sp, #8 ; Skip bbpsw, bbpc
- pop r14
- mvtc r14, cr3 ; spu
- pop r13
- pop lr ; r14
- pop sp ; spi (r15)
- addi sp, #4 ; Skip orig_r0
- .fillinsn
-1: rte
- .section .fixup,"ax"
-2: bl do_exit
- .previous
- .section __ex_table,"a"
- ALIGN
- .long 1b, 2b
- .previous
- .endm
-
-#define GET_CURRENT(reg) get_current reg
- .macro get_current reg
- ldi \reg, #-8192
- and \reg, sp
- .endm
-
-#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
- .macro SWITCH_TO_KERNEL_STACK
- ; switch to kernel stack (spi)
- clrpsw #0x80 -> nop
- .endm
-#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
- .macro SWITCH_TO_KERNEL_STACK
- push r0 ; save r0 for working
- mvfc r0, psw
- and3 r0, r0, #0x00ff7f
- mvtc r0, psw
- slli r0, #16
- bltz r0, 1f ; check BSM-bit
-;
- ;; called from kernel context: previous stack = spi
- pop r0 ; retrieve r0
- bra 2f
- .fillinsn
-1:
- ;; called from user context: previous stack = spu
- mvfc r0, cr3 ; spu
- addi r0, #4
- mvtc r0, cr3 ; spu
- ld r0, @(-4,r0) ; retrieve r0
- .fillinsn
-2:
- .endm
-#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_M32R_ASSEMBLER_H */
diff --git a/arch/m32r/include/asm/atomic.h b/arch/m32r/include/asm/atomic.h
deleted file mode 100644
index 8bf67e55ff54..000000000000
--- a/arch/m32r/include/asm/atomic.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_ATOMIC_H
-#define _ASM_M32R_ATOMIC_H
-
-/*
- * linux/include/asm-m32r/atomic.h
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/types.h>
-#include <asm/assembler.h>
-#include <asm/cmpxchg.h>
-#include <asm/dcache_clear.h>
-#include <asm/barrier.h>
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- */
-
-#define ATOMIC_INIT(i) { (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-#define atomic_read(v) READ_ONCE((v)->counter)
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
-
-#ifdef CONFIG_CHIP_M32700_TS1
-#define __ATOMIC_CLOBBER , "r4"
-#else
-#define __ATOMIC_CLOBBER
-#endif
-
-#define ATOMIC_OP(op) \
-static __inline__ void atomic_##op(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- int result; \
- \
- local_irq_save(flags); \
- __asm__ __volatile__ ( \
- "# atomic_" #op " \n\t" \
- DCACHE_CLEAR("%0", "r4", "%1") \
- M32R_LOCK" %0, @%1; \n\t" \
- #op " %0, %2; \n\t" \
- M32R_UNLOCK" %0, @%1; \n\t" \
- : "=&r" (result) \
- : "r" (&v->counter), "r" (i) \
- : "memory" \
- __ATOMIC_CLOBBER \
- ); \
- local_irq_restore(flags); \
-} \
-
-#define ATOMIC_OP_RETURN(op) \
-static __inline__ int atomic_##op##_return(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- int result; \
- \
- local_irq_save(flags); \
- __asm__ __volatile__ ( \
- "# atomic_" #op "_return \n\t" \
- DCACHE_CLEAR("%0", "r4", "%1") \
- M32R_LOCK" %0, @%1; \n\t" \
- #op " %0, %2; \n\t" \
- M32R_UNLOCK" %0, @%1; \n\t" \
- : "=&r" (result) \
- : "r" (&v->counter), "r" (i) \
- : "memory" \
- __ATOMIC_CLOBBER \
- ); \
- local_irq_restore(flags); \
- \
- return result; \
-}
-
-#define ATOMIC_FETCH_OP(op) \
-static __inline__ int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- int result, val; \
- \
- local_irq_save(flags); \
- __asm__ __volatile__ ( \
- "# atomic_fetch_" #op " \n\t" \
- DCACHE_CLEAR("%0", "r4", "%2") \
- M32R_LOCK" %1, @%2; \n\t" \
- "mv %0, %1 \n\t" \
- #op " %1, %3; \n\t" \
- M32R_UNLOCK" %1, @%2; \n\t" \
- : "=&r" (result), "=&r" (val) \
- : "r" (&v->counter), "r" (i) \
- : "memory" \
- __ATOMIC_CLOBBER \
- ); \
- local_irq_restore(flags); \
- \
- return result; \
-}
-
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(add)
-ATOMIC_OPS(sub)
-
-#undef ATOMIC_OPS
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(and)
-ATOMIC_OPS(or)
-ATOMIC_OPS(xor)
-
-#undef ATOMIC_OPS
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-
-/**
- * atomic_inc_return - increment atomic variable and return it
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1 and returns the result.
- */
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
- unsigned long flags;
- int result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# atomic_inc_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "addi %0, #1; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&v->counter)
- : "memory"
- __ATOMIC_CLOBBER
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * atomic_dec_return - decrement atomic variable and return it
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and returns the result.
- */
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
- unsigned long flags;
- int result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# atomic_dec_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "addi %0, #-1; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&v->counter)
- : "memory"
- __ATOMIC_CLOBBER
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic_inc(v) ((void)atomic_inc_return(v))
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic_dec(v) ((void)atomic_dec_return(v))
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all
- * other cases.
- */
-#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
-
-/**
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0)
-
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * __atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns the old value of @v.
- */
-static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int c, old;
- c = atomic_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c;
-}
-
-#endif /* _ASM_M32R_ATOMIC_H */
diff --git a/arch/m32r/include/asm/barrier.h b/arch/m32r/include/asm/barrier.h
deleted file mode 100644
index 1a40265e8d88..000000000000
--- a/arch/m32r/include/asm/barrier.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_BARRIER_H
-#define _ASM_M32R_BARRIER_H
-
-#define nop() __asm__ __volatile__ ("nop" : : )
-
-#include <asm-generic/barrier.h>
-
-#endif /* _ASM_M32R_BARRIER_H */
diff --git a/arch/m32r/include/asm/bitops.h b/arch/m32r/include/asm/bitops.h
deleted file mode 100644
index 64e70e57c154..000000000000
--- a/arch/m32r/include/asm/bitops.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_BITOPS_H
-#define _ASM_M32R_BITOPS_H
-
-/*
- * linux/include/asm-m32r/bitops.h
- *
- * Copyright 1992, Linus Torvalds.
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <linux/irqflags.h>
-#include <asm/assembler.h>
-#include <asm/byteorder.h>
-#include <asm/dcache_clear.h>
-#include <asm/types.h>
-#include <asm/barrier.h>
-
-/*
- * These have to be done with inline assembly: that way the bit-setting
- * is guaranteed to be atomic. All bit operations return 0 if the bit
- * was cleared before the operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-/**
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered. See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void set_bit(int nr, volatile void * addr)
-{
- __u32 mask;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r6", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "or %0, %2; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/**
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered. However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
- * in order to ensure changes are visible on other processors.
- */
-static __inline__ void clear_bit(int nr, volatile void * addr)
-{
- __u32 mask;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
-
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r6", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "and %0, %2; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (a), "r" (~mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/**
- * change_bit - Toggle a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void change_bit(int nr, volatile void * addr)
-{
- __u32 mask;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r6", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "xor %0, %2; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/**
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_set_bit(int nr, volatile void * addr)
-{
- __u32 mask, oldbit;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "%1", "%2")
- M32R_LOCK" %0, @%2; \n\t"
- "mv %1, %0; \n\t"
- "and %0, %3; \n\t"
- "or %1, %3; \n\t"
- M32R_UNLOCK" %1, @%2; \n\t"
- : "=&r" (oldbit), "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
- );
- local_irq_restore(flags);
-
- return (oldbit != 0);
-}
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
-{
- __u32 mask, oldbit;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
-
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "%1", "%3")
- M32R_LOCK" %0, @%3; \n\t"
- "mv %1, %0; \n\t"
- "and %0, %2; \n\t"
- "not %2, %2; \n\t"
- "and %1, %2; \n\t"
- M32R_UNLOCK" %1, @%3; \n\t"
- : "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
- : "r" (a)
- : "memory"
- );
- local_irq_restore(flags);
-
- return (oldbit != 0);
-}
-
-/**
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_change_bit(int nr, volatile void * addr)
-{
- __u32 mask, oldbit;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "%1", "%2")
- M32R_LOCK" %0, @%2; \n\t"
- "mv %1, %0; \n\t"
- "and %0, %3; \n\t"
- "xor %1, %3; \n\t"
- M32R_UNLOCK" %1, @%2; \n\t"
- : "=&r" (oldbit), "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
- );
- local_irq_restore(flags);
-
- return (oldbit != 0);
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#endif /* __KERNEL__ */
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/le.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_BITOPS_H */
diff --git a/arch/m32r/include/asm/bug.h b/arch/m32r/include/asm/bug.h
deleted file mode 100644
index 7197688254da..000000000000
--- a/arch/m32r/include/asm/bug.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32R_BUG_H
-#define _M32R_BUG_H
-#include <asm-generic/bug.h>
-#endif
diff --git a/arch/m32r/include/asm/bugs.h b/arch/m32r/include/asm/bugs.h
deleted file mode 100644
index 74a6d428aebe..000000000000
--- a/arch/m32r/include/asm/bugs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_BUGS_H
-#define _ASM_M32R_BUGS_H
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- * void check_bugs(void);
- */
-#include <asm/processor.h>
-
-static void __init check_bugs(void)
-{
- extern unsigned long loops_per_jiffy;
-
- current_cpu_data.loops_per_jiffy = loops_per_jiffy;
-}
-
-#endif /* _ASM_M32R_BUGS_H */
diff --git a/arch/m32r/include/asm/cache.h b/arch/m32r/include/asm/cache.h
deleted file mode 100644
index 47a766a258f8..000000000000
--- a/arch/m32r/include/asm/cache.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_CACHE_H
-#define _ASM_M32R_CACHE_H
-
-/* L1 cache line size */
-#define L1_CACHE_SHIFT 4
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#endif /* _ASM_M32R_CACHE_H */
diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h
deleted file mode 100644
index 12f73f6c1759..000000000000
--- a/arch/m32r/include/asm/cachectl.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * cachectl.h -- defines for M32R cache control system calls
- *
- * Copyright (C) 2003 by Kazuhiro Inaoka
- */
-#ifndef __ASM_M32R_CACHECTL
-#define __ASM_M32R_CACHECTL
-
-/*
- * Options for cacheflush system call
- *
- * cacheflush() is currently fluch_cache_all().
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE 0 /* make pages cacheable */
-#define UNCACHEABLE 1 /* make pages uncacheable */
-
-#endif /* __ASM_M32R_CACHECTL */
diff --git a/arch/m32r/include/asm/cacheflush.h b/arch/m32r/include/asm/cacheflush.h
deleted file mode 100644
index 5ad2a3045483..000000000000
--- a/arch/m32r/include/asm/cacheflush.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_CACHEFLUSH_H
-#define _ASM_M32R_CACHEFLUSH_H
-
-#include <linux/mm.h>
-
-extern void _flush_cache_all(void);
-extern void _flush_cache_copyback_all(void);
-
-#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#ifndef CONFIG_SMP
-#define flush_icache_range(start, end) _flush_cache_copyback_all()
-#define flush_icache_page(vma,pg) _flush_cache_copyback_all()
-#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_copyback_all()
-#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
-#else /* CONFIG_SMP */
-extern void smp_flush_cache_all(void);
-#define flush_icache_range(start, end) smp_flush_cache_all()
-#define flush_icache_page(vma,pg) smp_flush_cache_all()
-#define flush_icache_user_range(vma,pg,adr,len) smp_flush_cache_all()
-#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
-#endif /* CONFIG_SMP */
-#elif defined(CONFIG_CHIP_M32102)
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_range(start, end) _flush_cache_all()
-#define flush_icache_page(vma,pg) _flush_cache_all()
-#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_all()
-#define flush_cache_sigtramp(addr) _flush_cache_all()
-#else
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_range(start, end) do { } while (0)
-#define flush_icache_page(vma,pg) do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-#define flush_cache_sigtramp(addr) do { } while (0)
-#endif /* CONFIG_CHIP_* */
-
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { \
- memcpy(dst, src, len); \
- flush_icache_user_range(vma, page, vaddr, len); \
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-
-#endif /* _ASM_M32R_CACHEFLUSH_H */
diff --git a/arch/m32r/include/asm/checksum.h b/arch/m32r/include/asm/checksum.h
deleted file mode 100644
index d68e93c9bd62..000000000000
--- a/arch/m32r/include/asm/checksum.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_M32R_CHECKSUM_H
-#define _ASM_M32R_CHECKSUM_H
-
-/*
- * include/asm-m32r/checksum.h
- *
- * IP/TCP/UDP checksum routines
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Some code taken from mips and parisc architecture.
- *
- * Copyright (C) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/in6.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * The same as csum_partial, but copies from src while it checksums.
- *
- * Here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-
-/*
- * This is a new version of the above that records errors it finds in *errp,
- * but continues and zeros thre rest of the buffer.
- */
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum,
- int *err_ptr);
-
-/*
- * Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
- unsigned long tmpreg;
- __asm__(
- " sll3 %1, %0, #16 \n"
- " cmp %0, %0 \n"
- " addx %0, %1 \n"
- " ldi %1, #0 \n"
- " srli %0, #16 \n"
- " addx %0, %1 \n"
- " xor3 %0, %0, #0x0000ffff \n"
- : "=r" (sum), "=&r" (tmpreg)
- : "0" (sum)
- : "cbit"
- );
- return (__force __sum16)sum;
-}
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- unsigned long tmpreg0, tmpreg1;
- __wsum sum;
-
- __asm__ __volatile__(
- " ld %0, @%1+ \n"
- " addi %2, #-4 \n"
- "# bgez %2, 2f \n"
- " cmp %0, %0 \n"
- " ld %3, @%1+ \n"
- " ld %4, @%1+ \n"
- " addx %0, %3 \n"
- " ld %3, @%1+ \n"
- " addx %0, %4 \n"
- " addx %0, %3 \n"
- " .fillinsn\n"
- "1: \n"
- " ld %4, @%1+ \n"
- " addi %2, #-1 \n"
- " addx %0, %4 \n"
- " bgtz %2, 1b \n"
- "\n"
- " ldi %3, #0 \n"
- " addx %0, %3 \n"
- " .fillinsn\n"
- "2: \n"
- /* Since the input registers which are loaded with iph and ihl
- are modified, we must also specify them as outputs, or gcc
- will assume they contain their original values. */
- : "=&r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmpreg0), "=&r" (tmpreg1)
- : "1" (iph), "2" (ihl)
- : "cbit", "memory");
-
- return csum_fold(sum);
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
-#if defined(__LITTLE_ENDIAN)
- unsigned long len_proto = (proto + len) << 8;
-#else
- unsigned long len_proto = proto + len;
-#endif
- unsigned long tmpreg;
-
- __asm__(
- " cmp %0, %0 \n"
- " addx %0, %2 \n"
- " addx %0, %3 \n"
- " addx %0, %4 \n"
- " ldi %1, #0 \n"
- " addx %0, %1 \n"
- : "=r" (sum), "=&r" (tmpreg)
- : "r" (daddr), "r" (saddr), "r" (len_proto), "0" (sum)
- : "cbit"
- );
-
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold (csum_partial(buff, len, 0));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, unsigned short proto,
- __wsum sum)
-{
- unsigned long tmpreg0, tmpreg1, tmpreg2, tmpreg3;
- __asm__(
- " ld %1, @(%5) \n"
- " ld %2, @(4,%5) \n"
- " ld %3, @(8,%5) \n"
- " ld %4, @(12,%5) \n"
- " add %0, %1 \n"
- " addx %0, %2 \n"
- " addx %0, %3 \n"
- " addx %0, %4 \n"
- " ld %1, @(%6) \n"
- " ld %2, @(4,%6) \n"
- " ld %3, @(8,%6) \n"
- " ld %4, @(12,%6) \n"
- " addx %0, %1 \n"
- " addx %0, %2 \n"
- " addx %0, %3 \n"
- " addx %0, %4 \n"
- " addx %0, %7 \n"
- " addx %0, %8 \n"
- " ldi %1, #0 \n"
- " addx %0, %1 \n"
- : "=&r" (sum), "=&r" (tmpreg0), "=&r" (tmpreg1),
- "=&r" (tmpreg2), "=&r" (tmpreg3)
- : "r" (saddr), "r" (daddr),
- "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
- : "cbit"
- );
-
- return csum_fold(sum);
-}
-
-#endif /* _ASM_M32R_CHECKSUM_H */
-#endif /* __KERNEL__ */
diff --git a/arch/m32r/include/asm/cmpxchg.h b/arch/m32r/include/asm/cmpxchg.h
deleted file mode 100644
index 1ccdce5ff0ac..000000000000
--- a/arch/m32r/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_CMPXCHG_H
-#define _ASM_M32R_CMPXCHG_H
-
-/*
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/irqflags.h>
-#include <asm/assembler.h>
-#include <asm/dcache_clear.h>
-
-extern void __xchg_called_with_bad_pointer(void);
-
-static __always_inline unsigned long
-__xchg(unsigned long x, volatile void *ptr, int size)
-{
- unsigned long flags;
- unsigned long tmp = 0;
-
- local_irq_save(flags);
-
- switch (size) {
-#ifndef CONFIG_SMP
- case 1:
- __asm__ __volatile__ (
- "ldb %0, @%2 \n\t"
- "stb %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 2:
- __asm__ __volatile__ (
- "ldh %0, @%2 \n\t"
- "sth %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 4:
- __asm__ __volatile__ (
- "ld %0, @%2 \n\t"
- "st %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
-#else /* CONFIG_SMP */
- case 4:
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%2")
- "lock %0, @%2; \n\t"
- "unlock %1, @%2; \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- break;
-#endif /* CONFIG_SMP */
- default:
- __xchg_called_with_bad_pointer();
- }
-
- local_irq_restore(flags);
-
- return (tmp);
-}
-
-#define xchg(ptr, x) ({ \
- ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \
- sizeof(*(ptr)))); \
-})
-
-static __always_inline unsigned long
-__xchg_local(unsigned long x, volatile void *ptr, int size)
-{
- unsigned long flags;
- unsigned long tmp = 0;
-
- local_irq_save(flags);
-
- switch (size) {
- case 1:
- __asm__ __volatile__ (
- "ldb %0, @%2 \n\t"
- "stb %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 2:
- __asm__ __volatile__ (
- "ldh %0, @%2 \n\t"
- "sth %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 4:
- __asm__ __volatile__ (
- "ld %0, @%2 \n\t"
- "st %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- default:
- __xchg_called_with_bad_pointer();
- }
-
- local_irq_restore(flags);
-
- return (tmp);
-}
-
-#define xchg_local(ptr, x) \
- ((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \
- sizeof(*(ptr))))
-
-static inline unsigned long
-__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
-{
- unsigned long flags;
- unsigned int retval;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%1")
- M32R_LOCK" %0, @%1; \n"
- " bne %0, %2, 1f; \n"
- M32R_UNLOCK" %3, @%1; \n"
- " bra 2f; \n"
- " .fillinsn \n"
- "1:"
- M32R_UNLOCK" %0, @%1; \n"
- " .fillinsn \n"
- "2:"
- : "=&r" (retval)
- : "r" (p), "r" (old), "r" (new)
- : "cbit", "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return retval;
-}
-
-static inline unsigned long
-__cmpxchg_local_u32(volatile unsigned int *p, unsigned int old,
- unsigned int new)
-{
- unsigned long flags;
- unsigned int retval;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n"
- " bne %0, %2, 1f; \n"
- "st %3, @%1; \n"
- " bra 2f; \n"
- " .fillinsn \n"
- "1:"
- "st %0, @%1; \n"
- " .fillinsn \n"
- "2:"
- : "=&r" (retval)
- : "r" (p), "r" (old), "r" (new)
- : "cbit", "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return retval;
-}
-
-/* This function doesn't exist, so you'll get a linker error
- if something tries to do an invalid cmpxchg(). */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_u32(ptr, old, new);
-#if 0 /* we don't have __cmpxchg_u64 */
- case 8:
- return __cmpxchg_u64(ptr, old, new);
-#endif /* 0 */
- }
- __cmpxchg_called_with_bad_pointer();
- return old;
-}
-
-#define cmpxchg(ptr, o, n) ({ \
- ((__typeof__(*(ptr))) \
- __cmpxchg((ptr), (unsigned long)(o), \
- (unsigned long)(n), \
- sizeof(*(ptr)))); \
-})
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
- unsigned long old,
- unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_local_u32(ptr, old, new);
- default:
- return __cmpxchg_local_generic(ptr, old, new, size);
- }
-
- return old;
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif /* _ASM_M32R_CMPXCHG_H */
diff --git a/arch/m32r/include/asm/dcache_clear.h b/arch/m32r/include/asm/dcache_clear.h
deleted file mode 100644
index a0ae06c2e9e7..000000000000
--- a/arch/m32r/include/asm/dcache_clear.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_DCACHE_CLEAR_H
-#define _ASM_M32R_DCACHE_CLEAR_H
-
-#ifdef CONFIG_CHIP_M32700_TS1
-#define DCACHE_CLEAR(reg0, reg1, addr) \
- "seth "reg1", #high(dcache_dummy); \n\t" \
- "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
- "lock "reg0", @"reg1"; \n\t" \
- "add3 "reg0", "addr", #0x1000; \n\t" \
- "ld "reg0", @"reg0"; \n\t" \
- "add3 "reg0", "addr", #0x2000; \n\t" \
- "ld "reg0", @"reg0"; \n\t" \
- "unlock "reg0", @"reg1"; \n\t"
- /* FIXME: This workaround code cannot handle kernel modules
- * correctly under SMP environment.
- */
-#else /* CONFIG_CHIP_M32700_TS1 */
-#define DCACHE_CLEAR(reg0, reg1, addr)
-#endif /* CONFIG_CHIP_M32700_TS1 */
-
-#endif /* _ASM_M32R_DCACHE_CLEAR_H */
diff --git a/arch/m32r/include/asm/delay.h b/arch/m32r/include/asm/delay.h
deleted file mode 100644
index 9670e127b7b2..000000000000
--- a/arch/m32r/include/asm/delay.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/delay.h>
diff --git a/arch/m32r/include/asm/device.h b/arch/m32r/include/asm/device.h
deleted file mode 100644
index 5203fc87f080..000000000000
--- a/arch/m32r/include/asm/device.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-struct dev_archdata {
-};
-
-struct pdev_archdata {
-};
diff --git a/arch/m32r/include/asm/div64.h b/arch/m32r/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/m32r/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/m32r/include/asm/dma.h b/arch/m32r/include/asm/dma.h
deleted file mode 100644
index 661bc3b343ed..000000000000
--- a/arch/m32r/include/asm/dma.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_DMA_H
-#define _ASM_M32R_DMA_H
-
-#include <asm/io.h>
-
-/*
- * The maximum address that we can perform a DMA transfer
- * to on this platform
- */
-#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x20000000)
-
-#endif /* _ASM_M32R_DMA_H */
diff --git a/arch/m32r/include/asm/elf.h b/arch/m32r/include/asm/elf.h
deleted file mode 100644
index 576b2ff57957..000000000000
--- a/arch/m32r/include/asm/elf.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R__ELF_H
-#define _ASM_M32R__ELF_H
-
-/*
- * ELF-specific definitions.
- *
- * Copyright (C) 1999-2004, Renesas Technology Corp.
- * Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-#include <asm/page.h>
-
-/* M32R relocation types */
-#define R_M32R_NONE 0
-#define R_M32R_16 1
-#define R_M32R_32 2
-#define R_M32R_24 3
-#define R_M32R_10_PCREL 4
-#define R_M32R_18_PCREL 5
-#define R_M32R_26_PCREL 6
-#define R_M32R_HI16_ULO 7
-#define R_M32R_HI16_SLO 8
-#define R_M32R_LO16 9
-#define R_M32R_SDA16 10
-#define R_M32R_GNU_VTINHERIT 11
-#define R_M32R_GNU_VTENTRY 12
-
-#define R_M32R_16_RELA 33
-#define R_M32R_32_RELA 34
-#define R_M32R_24_RELA 35
-#define R_M32R_10_PCREL_RELA 36
-#define R_M32R_18_PCREL_RELA 37
-#define R_M32R_26_PCREL_RELA 38
-#define R_M32R_HI16_ULO_RELA 39
-#define R_M32R_HI16_SLO_RELA 40
-#define R_M32R_LO16_RELA 41
-#define R_M32R_SDA16_RELA 42
-#define R_M32R_RELA_GNU_VTINHERIT 43
-#define R_M32R_RELA_GNU_VTENTRY 44
-
-#define R_M32R_GOT24 48
-#define R_M32R_26_PLTREL 49
-#define R_M32R_COPY 50
-#define R_M32R_GLOB_DAT 51
-#define R_M32R_JMP_SLOT 52
-#define R_M32R_RELATIVE 53
-#define R_M32R_GOTOFF 54
-#define R_M32R_GOTPC24 55
-#define R_M32R_GOT16_HI_ULO 56
-#define R_M32R_GOT16_HI_SLO 57
-#define R_M32R_GOT16_LO 58
-#define R_M32R_GOTPC_HI_ULO 59
-#define R_M32R_GOTPC_HI_SLO 60
-#define R_M32R_GOTPC_LO 61
-#define R_M32R_GOTOFF_HI_ULO 62
-#define R_M32R_GOTOFF_HI_SLO 63
-#define R_M32R_GOTOFF_LO 64
-
-#define R_M32R_NUM 256
-
-/*
- * ELF register definitions..
- */
-#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
-
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* We have no FP mumumu. */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- (((x)->e_machine == EM_M32R) || ((x)->e_machine == EM_CYGNUS_M32R))
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#if defined(__LITTLE_ENDIAN__)
-#define ELF_DATA ELFDATA2LSB
-#elif defined(__BIG_ENDIAN__)
-#define ELF_DATA ELFDATA2MSB
-#else
-#error no endian defined
-#endif
-#define ELF_ARCH EM_M32R
-
-/* r0 is set by ld.so to a pointer to a function which might be
- * registered using 'atexit'. This provides a mean for the dynamic
- * linker to call DT_FINI functions for shared libraries that have
- * been loaded before the code runs.
- *
- * So that we can use the same startup file with static executables,
- * we start programs with a value of 0 to indicate that there is no
- * such function.
- */
-#define ELF_PLAT_INIT(_r, load_addr) (_r)->r0 = 0
-
-#define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-/*
- * This is the location that an ET_DYN program is loaded if exec'ed.
- * Typical use of this is to invoke "./ld.so someprog" to test out a
- * new version of the loader. We need to make sure that it is out of
- * the way of the program that it will "exec", and that there is
- * sufficient room for the brk.
- */
-#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
-
-/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
- now struct_user_regs, they are different) */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- memcpy((char *)pr_reg, (char *)regs, sizeof (struct pt_regs));
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this CPU supports. */
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-#define ELF_PLATFORM (NULL)
-
-#endif /* _ASM_M32R__ELF_H */
diff --git a/arch/m32r/include/asm/emergency-restart.h b/arch/m32r/include/asm/emergency-restart.h
deleted file mode 100644
index cca44d5ae264..000000000000
--- a/arch/m32r/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m32r/include/asm/fb.h b/arch/m32r/include/asm/fb.h
deleted file mode 100644
index 9a0bca2686fd..000000000000
--- a/arch/m32r/include/asm/fb.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
- unsigned long off)
-{
- vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
-}
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
- return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/arch/m32r/include/asm/flat.h b/arch/m32r/include/asm/flat.h
deleted file mode 100644
index dfcb0e4eb256..000000000000
--- a/arch/m32r/include/asm/flat.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * include/asm-m32r/flat.h
- *
- * uClinux flat-format executables
- *
- * Copyright (C) 2004 Kazuhiro Inaoka
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive for
- * more details.
- */
-#ifndef __ASM_M32R_FLAT_H
-#define __ASM_M32R_FLAT_H
-
-#define flat_argvp_envp_on_stack() 0
-#define flat_old_ram_flag(flags) (flags)
-#define flat_set_persistent(relval, p) 0
-#define flat_reloc_valid(reloc, size) \
- (((reloc) - textlen_for_m32r_lo16_data) <= (size))
-
-/* Convert a relocation entry into an address. */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
- return relval & 0x00ffffff; /* Mask out top 8-bits */
-}
-
-#define flat_m32r_get_reloc_type(relval) ((relval) >> 24)
-
-#define M32R_SETH_OPCODE 0xd0c00000 /* SETH instruction code */
-
-#define FLAT_M32R_32 0x00 /* 32bits reloc */
-#define FLAT_M32R_24 0x01 /* unsigned 24bits reloc */
-#define FLAT_M32R_16 0x02 /* 16bits reloc */
-#define FLAT_M32R_LO16 0x03 /* signed low 16bits reloc (low()) */
-#define FLAT_M32R_LO16_DATA 0x04 /* signed low 16bits reloc (low())
- for a symbol in .data section */
- /* High 16bits of an address used
- when the lower 16bbits are treated
- as unsigned.
- To create SETH instruction only.
- 0x1X: X means a number of register.
- 0x10 - 0x3F are reserved. */
-#define FLAT_M32R_HI16_ULO 0x10 /* reloc for SETH Rn,#high(imm16) */
- /* High 16bits of an address used
- when the lower 16bbits are treated
- as signed.
- To create SETH instruction only.
- 0x2X: X means a number of register.
- 0x20 - 0x4F are reserved. */
-#define FLAT_M32R_HI16_SLO 0x20 /* reloc for SETH Rn,#shigh(imm16) */
-
-static unsigned long textlen_for_m32r_lo16_data = 0;
-
-static inline unsigned long m32r_flat_get_addr_from_rp (u32 *rp,
- u32 relval,
- u32 textlen)
-{
- unsigned int reloc = flat_m32r_get_reloc_type (relval);
- textlen_for_m32r_lo16_data = 0;
- if (reloc & 0xf0) {
- unsigned long addr = htonl(*rp);
- switch (reloc & 0xf0)
- {
- case FLAT_M32R_HI16_ULO:
- case FLAT_M32R_HI16_SLO:
- if (addr == 0) {
- /* put "seth Rn,#0x0" instead of 0 (addr). */
- *rp = (M32R_SETH_OPCODE | ((reloc & 0x0f)<<24));
- }
- return addr;
- default:
- break;
- }
- } else {
- switch (reloc)
- {
- case FLAT_M32R_LO16:
- return htonl(*rp) & 0xFFFF;
- case FLAT_M32R_LO16_DATA:
- /* FIXME: The return value will decrease by textlen
- at m32r_flat_put_addr_at_rp () */
- textlen_for_m32r_lo16_data = textlen;
- return (htonl(*rp) & 0xFFFF) + textlen;
- case FLAT_M32R_16:
- return htons(*(unsigned short *)rp) & 0xFFFF;
- case FLAT_M32R_24:
- return htonl(*rp) & 0xFFFFFF;
- case FLAT_M32R_32:
- return htonl(*rp);
- default:
- break;
- }
- }
- return ~0; /* bogus value */
-}
-
-static inline int flat_put_addr_at_rp(u32 *rp, u32 addr, u32 relval)
-{
- unsigned int reloc = flat_m32r_get_reloc_type (relval);
- if (reloc & 0xf0) {
- unsigned long Rn = reloc & 0x0f; /* get a number of register */
- Rn <<= 24; /* 0x0R000000 */
- reloc &= 0xf0;
- switch (reloc)
- {
- case FLAT_M32R_HI16_ULO: /* To create SETH Rn,#high(imm16) */
- *rp = (M32R_SETH_OPCODE | Rn
- | ((addr >> 16) & 0xFFFF));
- break;
- case FLAT_M32R_HI16_SLO: /* To create SETH Rn,#shigh(imm16) */
- *rp = (M32R_SETH_OPCODE | Rn
- | (((addr >> 16) + ((addr & 0x8000) ? 1 : 0))
- & 0xFFFF));
- break;
- }
- } else {
- switch (reloc) {
- case FLAT_M32R_LO16_DATA:
- addr -= textlen_for_m32r_lo16_data;
- textlen_for_m32r_lo16_data = 0;
- case FLAT_M32R_LO16:
- *rp = (htonl(*rp) & 0xFFFF0000) | (addr & 0xFFFF);
- break;
- case FLAT_M32R_16:
- *(unsigned short *)rp = addr & 0xFFFF;
- break;
- case FLAT_M32R_24:
- *rp = (htonl(*rp) & 0xFF000000) | (addr & 0xFFFFFF);
- break;
- case FLAT_M32R_32:
- *rp = addr;
- break;
- }
- }
- return 0;
-}
-
-// kludge - text_len is a local variable in the only user.
-#define flat_get_addr_from_rp(rp, relval, flags, addr, persistent) \
- (m32r_flat_get_addr_from_rp(rp, relval, text_len), 0)
-
-#endif /* __ASM_M32R_FLAT_H */
diff --git a/arch/m32r/include/asm/ftrace.h b/arch/m32r/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/m32r/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/m32r/include/asm/futex.h b/arch/m32r/include/asm/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/arch/m32r/include/asm/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/arch/m32r/include/asm/hardirq.h b/arch/m32r/include/asm/hardirq.h
deleted file mode 100644
index 10c23de02b3a..000000000000
--- a/arch/m32r/include/asm/hardirq.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifdef __KERNEL__
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-
-#include <asm/irq.h>
-#include <asm-generic/hardirq.h>
-
-#endif /* __ASM_HARDIRQ_H */
-#endif /* __KERNEL__ */
diff --git a/arch/m32r/include/asm/hw_irq.h b/arch/m32r/include/asm/hw_irq.h
deleted file mode 100644
index 7138537cda03..000000000000
--- a/arch/m32r/include/asm/hw_irq.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_M32R_HW_IRQ_H
-#define _ASM_M32R_HW_IRQ_H
-
-#endif /* _ASM_M32R_HW_IRQ_H */
diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h
deleted file mode 100644
index a4272d8f0d9c..000000000000
--- a/arch/m32r/include/asm/io.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_IO_H
-#define _ASM_M32R_IO_H
-
-#include <linux/string.h>
-#include <linux/compiler.h>
-#include <asm/page.h> /* __va */
-
-#ifdef __KERNEL__
-
-#define IO_SPACE_LIMIT 0xFFFFFFFF
-
-/**
- * virt_to_phys - map virtual addresses to physical
- * @address: address to remap
- *
- * The returned physical address is the physical (CPU) mapping for
- * the memory address given. It is only valid to use this function on
- * addresses directly mapped or allocated via kmalloc.
- *
- * This function does not give bus mappings for DMA transfers. In
- * almost all conceivable cases a device driver should not be using
- * this function
- */
-
-static inline unsigned long virt_to_phys(volatile void * address)
-{
- return __pa(address);
-}
-
-/**
- * phys_to_virt - map physical address to virtual
- * @address: address to remap
- *
- * The returned virtual address is a current CPU mapping for
- * the memory address given. It is only valid to use this function on
- * addresses that have a kernel mapping
- *
- * This function does not handle bus mappings for DMA transfers. In
- * almost all conceivable cases a device driver should not be using
- * this function
- */
-
-static inline void *phys_to_virt(unsigned long address)
-{
- return __va(address);
-}
-
-extern void __iomem *
-__ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-
-/**
- * ioremap - map bus memory into CPU space
- * @offset: bus address of the memory
- * @size: size of the resource to map
- *
- * ioremap performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- */
-
-static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
-{
- return __ioremap(offset, size, 0);
-}
-
-extern void iounmap(volatile void __iomem *addr);
-#define ioremap_nocache(off,size) ioremap(off,size)
-#define ioremap_wc ioremap_nocache
-#define ioremap_wt ioremap_nocache
-#define ioremap_uc ioremap_nocache
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- */
-#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
-#define page_to_bus page_to_phys
-#define virt_to_bus virt_to_phys
-
-extern unsigned char _inb(unsigned long);
-extern unsigned short _inw(unsigned long);
-extern unsigned long _inl(unsigned long);
-extern unsigned char _inb_p(unsigned long);
-extern unsigned short _inw_p(unsigned long);
-extern unsigned long _inl_p(unsigned long);
-extern void _outb(unsigned char, unsigned long);
-extern void _outw(unsigned short, unsigned long);
-extern void _outl(unsigned long, unsigned long);
-extern void _outb_p(unsigned char, unsigned long);
-extern void _outw_p(unsigned short, unsigned long);
-extern void _outl_p(unsigned long, unsigned long);
-extern void _insb(unsigned int, void *, unsigned long);
-extern void _insw(unsigned int, void *, unsigned long);
-extern void _insl(unsigned int, void *, unsigned long);
-extern void _outsb(unsigned int, const void *, unsigned long);
-extern void _outsw(unsigned int, const void *, unsigned long);
-extern void _outsl(unsigned int, const void *, unsigned long);
-
-static inline unsigned char _readb(unsigned long addr)
-{
- return *(volatile unsigned char __force *)addr;
-}
-
-static inline unsigned short _readw(unsigned long addr)
-{
- return *(volatile unsigned short __force *)addr;
-}
-
-static inline unsigned long _readl(unsigned long addr)
-{
- return *(volatile unsigned long __force *)addr;
-}
-
-static inline void _writeb(unsigned char b, unsigned long addr)
-{
- *(volatile unsigned char __force *)addr = b;
-}
-
-static inline void _writew(unsigned short w, unsigned long addr)
-{
- *(volatile unsigned short __force *)addr = w;
-}
-
-static inline void _writel(unsigned long l, unsigned long addr)
-{
- *(volatile unsigned long __force *)addr = l;
-}
-
-#define inb _inb
-#define inw _inw
-#define inl _inl
-#define outb _outb
-#define outw _outw
-#define outl _outl
-
-#define inb_p _inb_p
-#define inw_p _inw_p
-#define inl_p _inl_p
-#define outb_p _outb_p
-#define outw_p _outw_p
-#define outl_p _outl_p
-
-#define insb _insb
-#define insw _insw
-#define insl _insl
-#define outsb _outsb
-#define outsw _outsw
-#define outsl _outsl
-
-#define readb(addr) _readb((unsigned long)(addr))
-#define readw(addr) _readw((unsigned long)(addr))
-#define readl(addr) _readl((unsigned long)(addr))
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-
-#define writeb(val, addr) _writeb((val), (unsigned long)(addr))
-#define writew(val, addr) _writew((val), (unsigned long)(addr))
-#define writel(val, addr) _writel((val), (unsigned long)(addr))
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-
-#define ioread8 readb
-#define ioread16 readw
-#define ioread32 readl
-#define iowrite8 writeb
-#define iowrite16 writew
-#define iowrite32 writel
-
-#define ioread8_rep(p, dst, count) insb((unsigned long)(p), (dst), (count))
-#define ioread16_rep(p, dst, count) insw((unsigned long)(p), (dst), (count))
-#define ioread32_rep(p, dst, count) insl((unsigned long)(p), (dst), (count))
-
-#define iowrite8_rep(p, src, count) outsb((unsigned long)(p), (src), (count))
-#define iowrite16_rep(p, src, count) outsw((unsigned long)(p), (src), (count))
-#define iowrite32_rep(p, src, count) outsl((unsigned long)(p), (src), (count))
-
-#define ioread16be(addr) be16_to_cpu(readw(addr))
-#define ioread32be(addr) be32_to_cpu(readl(addr))
-#define iowrite16be(v, addr) writew(cpu_to_be16(v), (addr))
-#define iowrite32be(v, addr) writel(cpu_to_be32(v), (addr))
-
-#define mmiowb()
-
-static inline void
-memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
- memset((void __force *) addr, val, count);
-}
-
-static inline void
-memcpy_fromio(void *dst, volatile void __iomem *src, int count)
-{
- memcpy(dst, (void __force *) src, count);
-}
-
-static inline void
-memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
- memcpy((void __force *) dst, src, count);
-}
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_IO_H */
diff --git a/arch/m32r/include/asm/irq.h b/arch/m32r/include/asm/irq.h
deleted file mode 100644
index 85b475fff90e..000000000000
--- a/arch/m32r/include/asm/irq.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifdef __KERNEL__
-#ifndef _ASM_M32R_IRQ_H
-#define _ASM_M32R_IRQ_H
-
-
-#if defined(CONFIG_PLAT_USRV)
-/*
- * IRQ definitions for M32700UT
- * M32700 Chip: 64 interrupts
- * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- */
-#define M32700UT_NUM_CPU_IRQ (64)
-#define M32700UT_NUM_PLD_IRQ (32)
-#define M32700UT_IRQ_BASE 0
-#define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
-#define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
-
-#define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
-#elif defined(CONFIG_PLAT_M32700UT)
-/*
- * IRQ definitions for M32700UT(Rev.C) + M32R-LAN
- * M32700 Chip: 64 interrupts
- * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
- * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
- */
-#define M32700UT_NUM_CPU_IRQ (64)
-#define M32700UT_NUM_PLD_IRQ (32)
-#define M32700UT_NUM_LCD_PLD_IRQ (32)
-#define M32700UT_NUM_LAN_PLD_IRQ (32)
-#define M32700UT_IRQ_BASE 0
-#define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
-#define M32700UT_PLD_IRQ_BASE \
- (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
-#define M32700UT_LCD_PLD_IRQ_BASE \
- (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
-#define M32700UT_LAN_PLD_IRQ_BASE \
- (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
-
-#define NR_IRQS \
- (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
- + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
-#elif defined(CONFIG_PLAT_OPSPUT)
-/*
- * IRQ definitions for OPSPUT + M32R-LAN
- * OPSP Chip: 64 interrupts
- * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
- * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
- */
-#define OPSPUT_NUM_CPU_IRQ (64)
-#define OPSPUT_NUM_PLD_IRQ (32)
-#define OPSPUT_NUM_LCD_PLD_IRQ (32)
-#define OPSPUT_NUM_LAN_PLD_IRQ (32)
-#define OPSPUT_IRQ_BASE 0
-#define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
-#define OPSPUT_PLD_IRQ_BASE \
- (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
-#define OPSPUT_LCD_PLD_IRQ_BASE \
- (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
-#define OPSPUT_LAN_PLD_IRQ_BASE \
- (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
-
-#define NR_IRQS \
- (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
- + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
-
-#elif defined(CONFIG_PLAT_M32104UT)
-/*
- * IRQ definitions for M32104UT
- * M32104 Chip: 64 interrupts
- * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- */
-#define M32104UT_NUM_CPU_IRQ (64)
-#define M32104UT_NUM_PLD_IRQ (32)
-#define M32104UT_IRQ_BASE 0
-#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
-#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
-
-#define NR_IRQS \
- (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
-
-#else
-#define NR_IRQS 64
-#endif
-
-#define irq_canonicalize(irq) (irq)
-
-#endif /* _ASM_M32R_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/arch/m32r/include/asm/irq_regs.h b/arch/m32r/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/m32r/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/m32r/include/asm/irqflags.h b/arch/m32r/include/asm/irqflags.h
deleted file mode 100644
index 1f92d29982ae..000000000000
--- a/arch/m32r/include/asm/irqflags.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#ifndef _ASM_M32R_IRQFLAGS_H
-#define _ASM_M32R_IRQFLAGS_H
-
-#include <linux/types.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
- asm volatile("mvfc %0,psw" : "=r"(flags));
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
-#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
- asm volatile (
- "clrpsw #0x40 -> nop"
- : : : "memory");
-#else
- unsigned long tmpreg0, tmpreg1;
- asm volatile (
- "ld24 %0, #0 ; Use 32-bit insn. \n\t"
- "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
- "mvtc %0, psw \n\t"
- "and3 %0, %1, #0xffbf \n\t"
- "mvtc %0, psw \n\t"
- : "=&r" (tmpreg0), "=&r" (tmpreg1)
- :
- : "cbit", "memory");
-#endif
-}
-
-static inline void arch_local_irq_enable(void)
-{
-#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
- asm volatile (
- "setpsw #0x40 -> nop"
- : : : "memory");
-#else
- unsigned long tmpreg;
- asm volatile (
- "mvfc %0, psw; \n\t"
- "or3 %0, %0, #0x0040; \n\t"
- "mvtc %0, psw; \n\t"
- : "=&r" (tmpreg)
- :
- : "cbit", "memory");
-#endif
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
-#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
- asm volatile (
- "mvfc %0, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- : "=r" (flags)
- :
- : "memory");
-#else
- unsigned long tmpreg;
- asm volatile (
- "ld24 %1, #0 \n\t"
- "mvfc %0, psw \n\t"
- "mvtc %1, psw \n\t"
- "and3 %1, %0, #0xffbf \n\t"
- "mvtc %1, psw \n\t"
- : "=r" (flags), "=&r" (tmpreg)
- :
- : "cbit", "memory");
-#endif
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("mvtc %0,psw"
- :
- : "r" (flags)
- : "cbit", "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & 0x40);
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* _ASM_M32R_IRQFLAGS_H */
diff --git a/arch/m32r/include/asm/kdebug.h b/arch/m32r/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/m32r/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/m32r/include/asm/kmap_types.h b/arch/m32r/include/asm/kmap_types.h
deleted file mode 100644
index 3dcba0d17d40..000000000000
--- a/arch/m32r/include/asm/kmap_types.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __M32R_KMAP_TYPES_H
-#define __M32R_KMAP_TYPES_H
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define __WITH_KM_FENCE
-#endif
-
-#include <asm-generic/kmap_types.h>
-
-#undef __WITH_KM_FENCE
-
-#endif /* __M32R_KMAP_TYPES_H */
diff --git a/arch/m32r/include/asm/linkage.h b/arch/m32r/include/asm/linkage.h
deleted file mode 100644
index f1aee6ec5bc3..000000000000
--- a/arch/m32r/include/asm/linkage.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .balign 4
-#define __ALIGN_STR ".balign 4"
-
-#endif /* __ASM_LINKAGE_H */
diff --git a/arch/m32r/include/asm/local.h b/arch/m32r/include/asm/local.h
deleted file mode 100644
index 6780680c185d..000000000000
--- a/arch/m32r/include/asm/local.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __M32R_LOCAL_H
-#define __M32R_LOCAL_H
-
-/*
- * linux/include/asm-m32r/local.h
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- * Copyright (C) 2007 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
- */
-
-#include <linux/percpu.h>
-#include <asm/assembler.h>
-#include <asm/local.h>
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- */
-
-/*
- * Make sure gcc doesn't try to be clever and move things around
- * on us. We need to use _exactly_ the address the user gave us,
- * not some alias that contains the same information.
- */
-typedef struct { volatile int counter; } local_t;
-
-#define LOCAL_INIT(i) { (i) }
-
-/**
- * local_read - read local variable
- * @l: pointer of type local_t
- *
- * Atomically reads the value of @l.
- */
-#define local_read(l) ((l)->counter)
-
-/**
- * local_set - set local variable
- * @l: pointer of type local_t
- * @i: required value
- *
- * Atomically sets the value of @l to @i.
- */
-#define local_set(l, i) (((l)->counter) = (i))
-
-/**
- * local_add_return - add long to local variable and return it
- * @i: long value to add
- * @l: pointer of type local_t
- *
- * Atomically adds @i to @l and return (@i + @l).
- */
-static inline long local_add_return(long i, local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_add_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "add %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter), "r" (i)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_sub_return - subtract long from local variable and return it
- * @i: long value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l and return (@l - @i).
- */
-static inline long local_sub_return(long i, local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_sub_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "sub %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter), "r" (i)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_add - add long to local variable
- * @i: long value to add
- * @l: pointer of type local_t
- *
- * Atomically adds @i to @l.
- */
-#define local_add(i, l) ((void) local_add_return((i), (l)))
-
-/**
- * local_sub - subtract the local variable
- * @i: long value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l.
- */
-#define local_sub(i, l) ((void) local_sub_return((i), (l)))
-
-/**
- * local_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
-
-/**
- * local_inc_return - increment local variable and return it
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1 and returns the result.
- */
-static inline long local_inc_return(local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_inc_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "addi %0, #1; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_dec_return - decrement local variable and return it
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1 and returns the result.
- */
-static inline long local_dec_return(local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_dec_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "addi %0, #-1; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_inc - increment local variable
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1.
- */
-#define local_inc(l) ((void)local_inc_return(l))
-
-/**
- * local_dec - decrement local variable
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1.
- */
-#define local_dec(l) ((void)local_dec_return(l))
-
-/**
- * local_inc_and_test - increment and test
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define local_inc_and_test(l) (local_inc_return(l) == 0)
-
-/**
- * local_dec_and_test - decrement and test
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1 and
- * returns true if the result is 0, or false for all
- * other cases.
- */
-#define local_dec_and_test(l) (local_dec_return(l) == 0)
-
-/**
- * local_add_negative - add and test if negative
- * @l: pointer of type local_t
- * @i: integer value to add
- *
- * Atomically adds @i to @l and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define local_add_negative(i, l) (local_add_return((i), (l)) < 0)
-
-#define local_cmpxchg(l, o, n) (cmpxchg_local(&((l)->counter), (o), (n)))
-#define local_xchg(v, new) (xchg_local(&((l)->counter), new))
-
-/**
- * local_add_unless - add unless the number is a given value
- * @l: pointer of type local_t
- * @a: the amount to add to l...
- * @u: ...unless l is equal to u.
- *
- * Atomically adds @a to @l, so long as it was not @u.
- * Returns non-zero if @l was not @u, and zero otherwise.
- */
-static inline int local_add_unless(local_t *l, long a, long u)
-{
- long c, old;
- c = local_read(l);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = local_cmpxchg((l), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c != (u);
-}
-
-#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
-
-static inline void local_clear_mask(unsigned long mask, local_t *addr)
-{
- unsigned long flags;
- unsigned long tmp;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_clear_mask \n\t"
- DCACHE_CLEAR("%0", "r5", "%1")
- "ld %0, @%1; \n\t"
- "and %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (addr), "r" (~mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r5"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-static inline void local_set_mask(unsigned long mask, local_t *addr)
-{
- unsigned long flags;
- unsigned long tmp;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_set_mask \n\t"
- DCACHE_CLEAR("%0", "r5", "%1")
- "ld %0, @%1; \n\t"
- "or %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (addr), "r" (mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r5"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/* Atomic operations are already serializing on m32r */
-#define smp_mb__before_local_dec() barrier()
-#define smp_mb__after_local_dec() barrier()
-#define smp_mb__before_local_inc() barrier()
-#define smp_mb__after_local_inc() barrier()
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations. Note they take
- * a variable, not an address.
- */
-
-#define __local_inc(l) ((l)->a.counter++)
-#define __local_dec(l) ((l)->a.counter++)
-#define __local_add(i, l) ((l)->a.counter += (i))
-#define __local_sub(i, l) ((l)->a.counter -= (i))
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations. Note they take
- * a variable, not an address.
- */
-
-#endif /* __M32R_LOCAL_H */
diff --git a/arch/m32r/include/asm/local64.h b/arch/m32r/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/m32r/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/m32r/include/asm/m32102.h b/arch/m32r/include/asm/m32102.h
deleted file mode 100644
index f0a986fece65..000000000000
--- a/arch/m32r/include/asm/m32102.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32102_H_
-#define _M32102_H_
-
-/*
- * Renesas M32R 32102 group
- *
- * Copyright (c) 2001 Hitoshi Yamamoto
- * Copyright (c) 2003, 2004 Renesas Technology Corp.
- */
-
-/*======================================================================*
- * Special Function Register
- *======================================================================*/
-#if !defined(CONFIG_CHIP_M32104)
-#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
-#else
-#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
-#endif
-
-/*
- * Clock and Power Management registers.
- */
-#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
-
-#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
-#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
-#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
-
-/*
- * DMA Controller registers.
- */
-#define M32R_DMA_OFFSET (0x000F8000+M32R_SFR_OFFSET)
-
-#define M32R_DMAEN_PORTL (0x000+M32R_DMA_OFFSET)
-#define M32R_DMAISTS_PORTL (0x004+M32R_DMA_OFFSET)
-#define M32R_DMAEDET_PORTL (0x008+M32R_DMA_OFFSET)
-#define M32R_DMAASTS_PORTL (0x00c+M32R_DMA_OFFSET)
-
-#define M32R_DMA0CR0_PORTL (0x100+M32R_DMA_OFFSET)
-#define M32R_DMA0CR1_PORTL (0x104+M32R_DMA_OFFSET)
-#define M32R_DMA0CSA_PORTL (0x108+M32R_DMA_OFFSET)
-#define M32R_DMA0RSA_PORTL (0x10c+M32R_DMA_OFFSET)
-#define M32R_DMA0CDA_PORTL (0x110+M32R_DMA_OFFSET)
-#define M32R_DMA0RDA_PORTL (0x114+M32R_DMA_OFFSET)
-#define M32R_DMA0CBCUT_PORTL (0x118+M32R_DMA_OFFSET)
-#define M32R_DMA0RBCUT_PORTL (0x11c+M32R_DMA_OFFSET)
-
-#define M32R_DMA1CR0_PORTL (0x200+M32R_DMA_OFFSET)
-#define M32R_DMA1CR1_PORTL (0x204+M32R_DMA_OFFSET)
-#define M32R_DMA1CSA_PORTL (0x208+M32R_DMA_OFFSET)
-#define M32R_DMA1RSA_PORTL (0x20c+M32R_DMA_OFFSET)
-#define M32R_DMA1CDA_PORTL (0x210+M32R_DMA_OFFSET)
-#define M32R_DMA1RDA_PORTL (0x214+M32R_DMA_OFFSET)
-#define M32R_DMA1CBCUT_PORTL (0x218+M32R_DMA_OFFSET)
-#define M32R_DMA1RBCUT_PORTL (0x21c+M32R_DMA_OFFSET)
-
-/*
- * Multi Function Timer registers.
- */
-#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
-
-#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
-#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
-
-#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
-#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
-#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
-#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
-#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
-#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
-
-#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
-#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
-#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
-#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
-#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
-#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
-
-#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
-#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
-#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
-#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
-#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
-#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
-
-#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
-#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
-#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
-#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
-#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
-#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
-
-#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
-#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
-#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
-#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
-#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
-
-#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
-#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
-#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
-#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
-#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
-
-#if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
- || defined(CONFIG_CHIP_M32104)
-#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
-#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
-#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
-#define M32R_MFTCR_MFT3MSK (1UL<<28) /* b3 */
-#define M32R_MFTCR_MFT4MSK (1UL<<27) /* b4 */
-#define M32R_MFTCR_MFT5MSK (1UL<<26) /* b5 */
-#define M32R_MFTCR_MFT0EN (1UL<<23) /* b8 */
-#define M32R_MFTCR_MFT1EN (1UL<<22) /* b9 */
-#define M32R_MFTCR_MFT2EN (1UL<<21) /* b10 */
-#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
-#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
-#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
-#else
-#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
-#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
-#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
-#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
-#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
-#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
-#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
-#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
-#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
-#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
-#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
-#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
-#endif
-
-#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
-#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
-#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
-#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
-#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
-#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
-#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
-#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
-#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
-#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
-#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
-#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
-#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
-#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
-#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
-
-/*
- * Serial I/O registers.
- */
-#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
-
-#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
-#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
-#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
-#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
-#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
-#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
-#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
-
-/*
- * Interrupt Control Unit registers.
- */
-#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
-#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
-#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
-#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
-#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
-#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
-#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
-#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
-#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
-#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
-#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
-#define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */
-#define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
-#define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
-#define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
-#define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
-#define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
-#define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
-#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
-#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
-#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
-#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
-#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
-#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
-#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
-#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
-#define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
-#define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
-#define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
-#define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
-
-#ifdef CONFIG_SMP
-#define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
-#define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
-#define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
-#define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
-#define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
-#define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
-#define M32R_ICU_IPICR6_PORTL (0x2f4+M32R_ICU_OFFSET) /* IPI6 */
-#define M32R_ICU_IPICR7_PORTL (0x2f8+M32R_ICU_OFFSET) /* IPI7 */
-#endif /* CONFIG_SMP */
-
-#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
-#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
-#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
-#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
-#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
-#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
-#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
-#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
-
-#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
-#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
-#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
-#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
-#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
-#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
-#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
-#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
-#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
-#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
-#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
-#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
-#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
-#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
-
-#define M32R_IRQ_INT0 (1) /* INT0 */
-#define M32R_IRQ_INT1 (2) /* INT1 */
-#define M32R_IRQ_INT2 (3) /* INT2 */
-#define M32R_IRQ_INT3 (4) /* INT3 */
-#define M32R_IRQ_INT4 (5) /* INT4 */
-#define M32R_IRQ_INT5 (6) /* INT5 */
-#define M32R_IRQ_INT6 (7) /* INT6 */
-#define M32R_IRQ_MFT0 (16) /* MFT0 */
-#define M32R_IRQ_MFT1 (17) /* MFT1 */
-#define M32R_IRQ_MFT2 (18) /* MFT2 */
-#define M32R_IRQ_MFT3 (19) /* MFT3 */
-#ifdef CONFIG_CHIP_M32104
-#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
-#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
-#define M32R_IRQ_DMA0 (32) /* DMA0 */
-#define M32R_IRQ_DMA1 (33) /* DMA1 */
-#define M32R_IRQ_DMA2 (34) /* DMA2 */
-#define M32R_IRQ_DMA3 (35) /* DMA3 */
-#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
-#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
-#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
-#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
-#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
-#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
-#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
-#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
-#define M32R_IRQ_ADC (56) /* ADC */
-#define M32R_IRQ_PC (57) /* PC */
-#else /* ! M32104 */
-#define M32R_IRQ_DMA0 (32) /* DMA0 */
-#define M32R_IRQ_DMA1 (33) /* DMA1 */
-#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
-#define M32R_IRQ_SIO0_S (49) /* SIO0 receive */
-#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
-#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
-#define M32R_IRQ_SIO2_R (52) /* SIO2 send */
-#define M32R_IRQ_SIO2_S (53) /* SIO2 receive */
-#define M32R_IRQ_SIO3_R (54) /* SIO3 send */
-#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
-#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
-#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
-#endif /* ! M32104 */
-
-#ifdef CONFIG_SMP
-#define M32R_IRQ_IPI0 (56)
-#define M32R_IRQ_IPI1 (57)
-#define M32R_IRQ_IPI2 (58)
-#define M32R_IRQ_IPI3 (59)
-#define M32R_IRQ_IPI4 (60)
-#define M32R_IRQ_IPI5 (61)
-#define M32R_IRQ_IPI6 (62)
-#define M32R_IRQ_IPI7 (63)
-#define M32R_CPUID_PORTL (0xffffffe0)
-
-#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
-
-#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME3_PORTL (0x1c+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID3_PORTL (0x2c+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
-
-#endif /* CONFIG_SMP */
-
-#ifndef __ASSEMBLY__
-typedef struct {
- unsigned long icucr; /* ICU Control Register */
-} icu_data_t;
-#endif
-
-#endif /* _M32102_H_ */
diff --git a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h b/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
deleted file mode 100644
index 1feae9709f24..000000000000
--- a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef _M32104UT_M32104UT_PLD_H
-#define _M32104UT_M32104UT_PLD_H
-
-/*
- * include/asm-m32r/m32104ut/m32104ut_pld.h
- *
- * Definitions for Programmable Logic Device(PLD) on M32104UT board.
- * Based on m32700ut_pld.h
- *
- * Copyright (c) 2002 Takeo Takahashi
- * Copyright (c) 2005 Naoto Sugai
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#if defined(CONFIG_PLAT_M32104UT)
-#define PLD_PLAT_BASE 0x02c00000
-#else
-#error "no platform configuration"
-#endif
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- */
-
-#define PLD_IRQ_INT0 (M32104UT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_CFIREQ (M32104UT_PLD_IRQ_BASE + 3) /* CF IREQ */
-#define PLD_IRQ_CFC_INSERT (M32104UT_PLD_IRQ_BASE + 4) /* CF Insert */
-#define PLD_IRQ_CFC_EJECT (M32104UT_PLD_IRQ_BASE + 5) /* CF Eject */
-#define PLD_IRQ_EXINT (M32104UT_PLD_IRQ_BASE + 6) /* EXINT */
-#define PLD_IRQ_MMCCARD (M32104UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
-#define PLD_IRQ_SC_ERROR (M32104UT_PLD_IRQ_BASE + 13) /* SC error */
-#define PLD_IRQ_SC_RCV (M32104UT_PLD_IRQ_BASE + 14) /* SC receive */
-#define PLD_IRQ_SC_SND (M32104UT_PLD_IRQ_BASE + 15) /* SC send */
-
-#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
-#define PLD_ICUISTS_VECB_MASK (0xf000)
-#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
-#define PLD_ICUISTS_ISN_MASK (0x07c0)
-#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
-#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
-#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
-#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
-#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
-#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
-#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
-#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
-#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
-#define PLD_ICUCR_IEN (0x1000)
-#define PLD_ICUCR_IREQ (0x0100)
-#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
-#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
-#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
-#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
-#define PLD_ICUCR_ILEVEL0 (0x0000)
-#define PLD_ICUCR_ILEVEL1 (0x0001)
-#define PLD_ICUCR_ILEVEL2 (0x0002)
-#define PLD_ICUCR_ILEVEL3 (0x0003)
-#define PLD_ICUCR_ILEVEL4 (0x0004)
-#define PLD_ICUCR_ILEVEL5 (0x0005)
-#define PLD_ICUCR_ILEVEL6 (0x0006)
-#define PLD_ICUCR_ILEVEL7 (0x0007)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-#define PLD_CPCR_CDP 0x0001
-
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif /* _M32104UT_M32104UT_PLD_H */
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_lan.h b/arch/m32r/include/asm/m32700ut/m32700ut_lan.h
deleted file mode 100644
index aae810a4fb2c..000000000000
--- a/arch/m32r/include/asm/m32700ut/m32700ut_lan.h
+++ /dev/null
@@ -1,103 +0,0 @@
-#ifndef _M32700UT_M32700UT_LAN_H
-#define _M32700UT_M32700UT_LAN_H
-
-/*
- * include/asm-m32r/m32700ut/m32700ut_lan.h
- *
- * M32700UT-LAN board
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define M32700UT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define M32700UT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#define M32700UT_LAN_IRQ_LAN (M32700UT_LAN_PLD_IRQ_BASE + 1) /* LAN */
-#define M32700UT_LAN_IRQ_I2C (M32700UT_LAN_PLD_IRQ_BASE + 3) /* I2C */
-
-#define M32700UT_LAN_ICUISTS __reg16(M32700UT_LAN_BASE + 0xc0002)
-#define M32700UT_LAN_ICUISTS_VECB_MASK (0xf000)
-#define M32700UT_LAN_VECB(x) ((x) & M32700UT_LAN_ICUISTS_VECB_MASK)
-#define M32700UT_LAN_ICUISTS_ISN_MASK (0x07c0)
-#define M32700UT_LAN_ICUISTS_ISN(x) ((x) & M32700UT_LAN_ICUISTS_ISN_MASK)
-#define M32700UT_LAN_ICUIREQ0 __reg16(M32700UT_LAN_BASE + 0xc0004)
-#define M32700UT_LAN_ICUCR1 __reg16(M32700UT_LAN_BASE + 0xc0010)
-#define M32700UT_LAN_ICUCR3 __reg16(M32700UT_LAN_BASE + 0xc0014)
-
-/*
- * AR register on PLD
- */
-#define ARVCR0 __reg32(M32700UT_LAN_BASE + 0x40000)
-#define ARVCR0_VDS 0x00080000
-#define ARVCR0_RST 0x00010000
-#define ARVCR1 __reg32(M32700UT_LAN_BASE + 0x40004)
-#define ARVCR1_QVGA 0x02000000
-#define ARVCR1_NORMAL 0x01000000
-#define ARVCR1_HIEN 0x00010000
-#define ARVHCOUNT __reg32(M32700UT_LAN_BASE + 0x40008)
-#define ARDATA __reg32(M32700UT_LAN_BASE + 0x40010)
-#define ARINTSEL __reg32(M32700UT_LAN_BASE + 0x40014)
-#define ARINTSEL_INT3 0x10000000 /* CPU INT3 */
-#define ARDATA32 __reg32(M32700UT_LAN_BASE + 0x04040010) // Block 5
-/*
-#define ARINTSEL_SEL2 0x00002000
-#define ARINTSEL_SEL3 0x00001000
-#define ARINTSEL_SEL6 0x00000200
-#define ARINTSEL_SEL7 0x00000100
-#define ARINTSEL_SEL9 0x00000040
-#define ARINTSEL_SEL10 0x00000020
-#define ARINTSEL_SEL11 0x00000010
-#define ARINTSEL_SEL12 0x00000008
-*/
-
-/*
- * I2C register on PLD
- */
-#define PLDI2CCR __reg32(M32700UT_LAN_BASE + 0x40040)
-#define PLDI2CCR_ES0 0x00000001 /* enable I2C interface */
-#define PLDI2CMOD __reg32(M32700UT_LAN_BASE + 0x40044)
-#define PLDI2CMOD_ACKCLK 0x00000200
-#define PLDI2CMOD_DTWD 0x00000100
-#define PLDI2CMOD_10BT 0x00000004
-#define PLDI2CMOD_ATM_NORMAL 0x00000000
-#define PLDI2CMOD_ATM_AUTO 0x00000003
-#define PLDI2CACK __reg32(M32700UT_LAN_BASE + 0x40048)
-#define PLDI2CACK_ACK 0x00000001
-#define PLDI2CFREQ __reg32(M32700UT_LAN_BASE + 0x4004c)
-#define PLDI2CCND __reg32(M32700UT_LAN_BASE + 0x40050)
-#define PLDI2CCND_START 0x00000001
-#define PLDI2CCND_STOP 0x00000002
-#define PLDI2CSTEN __reg32(M32700UT_LAN_BASE + 0x40054)
-#define PLDI2CSTEN_STEN 0x00000001
-#define PLDI2CDATA __reg32(M32700UT_LAN_BASE + 0x40060)
-#define PLDI2CSTS __reg32(M32700UT_LAN_BASE + 0x40064)
-#define PLDI2CSTS_TRX 0x00000020
-#define PLDI2CSTS_BB 0x00000010
-#define PLDI2CSTS_NOACK 0x00000001 /* 0:ack, 1:noack */
-
-#endif /* _M32700UT_M32700UT_LAN_H */
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_lcd.h b/arch/m32r/include/asm/m32700ut/m32700ut_lcd.h
deleted file mode 100644
index 4c2489079788..000000000000
--- a/arch/m32r/include/asm/m32700ut/m32700ut_lcd.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _M32700UT_M32700UT_LCD_H
-#define _M32700UT_M32700UT_LCD_H
-
-/*
- * include/asm-m32r/m32700ut/m32700ut_lcd.h
- *
- * M32700UT-LCD board
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define M32700UT_LCD_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define M32700UT_LCD_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/*
- * ICU
- */
-#define M32700UT_LCD_IRQ_BAT_INT (M32700UT_LCD_PLD_IRQ_BASE + 1)
-#define M32700UT_LCD_IRQ_USB_INT1 (M32700UT_LCD_PLD_IRQ_BASE + 2)
-#define M32700UT_LCD_IRQ_AUDT0 (M32700UT_LCD_PLD_IRQ_BASE + 3)
-#define M32700UT_LCD_IRQ_AUDT2 (M32700UT_LCD_PLD_IRQ_BASE + 4)
-#define M32700UT_LCD_IRQ_BATSIO_RCV (M32700UT_LCD_PLD_IRQ_BASE + 16)
-#define M32700UT_LCD_IRQ_BATSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 17)
-#define M32700UT_LCD_IRQ_ASNDSIO_RCV (M32700UT_LCD_PLD_IRQ_BASE + 18)
-#define M32700UT_LCD_IRQ_ASNDSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 19)
-#define M32700UT_LCD_IRQ_ACNLSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 21)
-
-#define M32700UT_LCD_ICUISTS __reg16(M32700UT_LCD_BASE + 0x300002)
-#define M32700UT_LCD_ICUISTS_VECB_MASK (0xf000)
-#define M32700UT_LCD_VECB(x) ((x) & M32700UT_LCD_ICUISTS_VECB_MASK)
-#define M32700UT_LCD_ICUISTS_ISN_MASK (0x07c0)
-#define M32700UT_LCD_ICUISTS_ISN(x) ((x) & M32700UT_LCD_ICUISTS_ISN_MASK)
-#define M32700UT_LCD_ICUIREQ0 __reg16(M32700UT_LCD_BASE + 0x300004)
-#define M32700UT_LCD_ICUIREQ1 __reg16(M32700UT_LCD_BASE + 0x300006)
-#define M32700UT_LCD_ICUCR1 __reg16(M32700UT_LCD_BASE + 0x300020)
-#define M32700UT_LCD_ICUCR2 __reg16(M32700UT_LCD_BASE + 0x300022)
-#define M32700UT_LCD_ICUCR3 __reg16(M32700UT_LCD_BASE + 0x300024)
-#define M32700UT_LCD_ICUCR4 __reg16(M32700UT_LCD_BASE + 0x300026)
-#define M32700UT_LCD_ICUCR16 __reg16(M32700UT_LCD_BASE + 0x300030)
-#define M32700UT_LCD_ICUCR17 __reg16(M32700UT_LCD_BASE + 0x300032)
-#define M32700UT_LCD_ICUCR18 __reg16(M32700UT_LCD_BASE + 0x300034)
-#define M32700UT_LCD_ICUCR19 __reg16(M32700UT_LCD_BASE + 0x300036)
-#define M32700UT_LCD_ICUCR21 __reg16(M32700UT_LCD_BASE + 0x30003a)
-
-#endif /* _M32700UT_M32700UT_LCD_H */
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h b/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
deleted file mode 100644
index 35294670b187..000000000000
--- a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
+++ /dev/null
@@ -1,259 +0,0 @@
-#ifndef _M32700UT_M32700UT_PLD_H
-#define _M32700UT_M32700UT_PLD_H
-
-/*
- * include/asm-m32r/m32700ut/m32700ut_pld.h
- *
- * Definitions for Programmable Logic Device(PLD) on M32700UT board.
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV)
-#define PLD_PLAT_BASE 0x04c00000
-#else
-#error "no platform configuration"
-#endif
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#if !defined(CONFIG_PLAT_USRV)
-#define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CFIREQ (M32700UT_PLD_IRQ_BASE + 3) /* CF IREQ */
-#define PLD_IRQ_CFC_INSERT (M32700UT_PLD_IRQ_BASE + 4) /* CF Insert */
-#define PLD_IRQ_CFC_EJECT (M32700UT_PLD_IRQ_BASE + 5) /* CF Eject */
-#define PLD_IRQ_EXINT (M32700UT_PLD_IRQ_BASE + 6) /* EXINT */
-#define PLD_IRQ_INT7 (M32700UT_PLD_IRQ_BASE + 7) /* reserved */
-#define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_MMCCARD (M32700UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
-#define PLD_IRQ_INT12 (M32700UT_PLD_IRQ_BASE + 12) /* reserved */
-#define PLD_IRQ_SC_ERROR (M32700UT_PLD_IRQ_BASE + 13) /* SC error */
-#define PLD_IRQ_SC_RCV (M32700UT_PLD_IRQ_BASE + 14) /* SC receive */
-#define PLD_IRQ_SC_SND (M32700UT_PLD_IRQ_BASE + 15) /* SC send */
-#define PLD_IRQ_SIO0_RCV (M32700UT_PLD_IRQ_BASE + 16) /* SIO receive */
-#define PLD_IRQ_SIO0_SND (M32700UT_PLD_IRQ_BASE + 17) /* SIO send */
-#define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
-#define PLD_IRQ_INT31 (M32700UT_PLD_IRQ_BASE + 31) /* reserved */
-
-#else /* CONFIG_PLAT_USRV */
-
-#define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CF0 (M32700UT_PLD_IRQ_BASE + 3) /* CF0# */
-#define PLD_IRQ_CF1 (M32700UT_PLD_IRQ_BASE + 4) /* CF1# */
-#define PLD_IRQ_CF2 (M32700UT_PLD_IRQ_BASE + 5) /* CF2# */
-#define PLD_IRQ_CF3 (M32700UT_PLD_IRQ_BASE + 6) /* CF3# */
-#define PLD_IRQ_CF4 (M32700UT_PLD_IRQ_BASE + 7) /* CF4# */
-#define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_INT11 (M32700UT_PLD_IRQ_BASE + 11) /* reserved */
-#define PLD_IRQ_UART0 (M32700UT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
-#define PLD_IRQ_UART1 (M32700UT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
-#define PLD_IRQ_INT14 (M32700UT_PLD_IRQ_BASE + 14) /* reserved */
-#define PLD_IRQ_INT15 (M32700UT_PLD_IRQ_BASE + 15) /* reserved */
-#define PLD_IRQ_SNDINT (M32700UT_PLD_IRQ_BASE + 16) /* SNDINT# */
-#define PLD_IRQ_INT17 (M32700UT_PLD_IRQ_BASE + 17) /* reserved */
-#define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
-
-#endif /* CONFIG_PLAT_USRV */
-
-#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
-#define PLD_ICUISTS_VECB_MASK (0xf000)
-#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
-#define PLD_ICUISTS_ISN_MASK (0x07c0)
-#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
-#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
-#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
-#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
-#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
-#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
-#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
-#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
-#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
-#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
-#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
-#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
-#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
-#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
-#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
-#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
-#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
-#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
-#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
-#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
-#define PLD_ICUCR_IEN (0x1000)
-#define PLD_ICUCR_IREQ (0x0100)
-#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
-#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
-#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
-#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
-#define PLD_ICUCR_ILEVEL0 (0x0000)
-#define PLD_ICUCR_ILEVEL1 (0x0001)
-#define PLD_ICUCR_ILEVEL2 (0x0002)
-#define PLD_ICUCR_ILEVEL3 (0x0003)
-#define PLD_ICUCR_ILEVEL4 (0x0004)
-#define PLD_ICUCR_ILEVEL5 (0x0005)
-#define PLD_ICUCR_ILEVEL6 (0x0006)
-#define PLD_ICUCR_ILEVEL7 (0x0007)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-#define PLD_CPCR_CF 0x0001
-#define PLD_CPCR_MMC 0x0002
-
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif /* _M32700UT_M32700UT_PLD.H */
diff --git a/arch/m32r/include/asm/m32r.h b/arch/m32r/include/asm/m32r.h
deleted file mode 100644
index d27f056d92f3..000000000000
--- a/arch/m32r/include/asm/m32r.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_M32R_H_
-#define _ASM_M32R_M32R_H_
-
-/*
- * Renesas M32R processor
- *
- * Copyright (C) 2003, 2004 Renesas Technology Corp.
- */
-
-
-/* Chip type */
-#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
-#include <asm/m32r_mp_fpga.h>
-#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
- || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
- || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-#include <asm/m32102.h>
-#endif
-
-/* Platform type */
-#if defined(CONFIG_PLAT_M32700UT)
-#include <asm/m32700ut/m32700ut_pld.h>
-#include <asm/m32700ut/m32700ut_lan.h>
-#include <asm/m32700ut/m32700ut_lcd.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
-#define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS
-#define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE
-#define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS
-#define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE
-#endif /* CONFIG_PLAT_M32700UT */
-
-#if defined(CONFIG_PLAT_OPSPUT)
-#include <asm/opsput/opsput_pld.h>
-#include <asm/opsput/opsput_lan.h>
-#include <asm/opsput/opsput_lcd.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE
-#define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS
-#define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE
-#define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS
-#define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE
-#endif /* CONFIG_PLAT_OPSPUT */
-
-#if defined(CONFIG_PLAT_MAPPI2)
-#include <asm/mappi2/mappi2_pld.h>
-#endif /* CONFIG_PLAT_MAPPI2 */
-
-#if defined(CONFIG_PLAT_MAPPI3)
-#include <asm/mappi3/mappi3_pld.h>
-#endif /* CONFIG_PLAT_MAPPI3 */
-
-#if defined(CONFIG_PLAT_USRV)
-#include <asm/m32700ut/m32700ut_pld.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
-#endif
-
-#if defined(CONFIG_PLAT_M32104UT)
-#include <asm/m32104ut/m32104ut_pld.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE
-#endif /* CONFIG_PLAT_M32104 */
-
-/*
- * M32R Register
- */
-
-/*
- * MMU Register
- */
-
-#define MMU_REG_BASE (0xffff0000)
-#define ITLB_BASE (0xfe000000)
-#define DTLB_BASE (0xfe000800)
-
-#define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
-
-#define MATM MMU_REG_BASE /* MMU Address Translation Mode
- Register */
-#define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
-#define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
-#define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
-#define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
- Address Register */
-#define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
- Number Register */
-#define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
-#define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
- Register */
-#define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
-#define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
- Instruciton */
-#define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
-
-#define MATM_offset (MATM - MMU_REG_BASE)
-#define MPSZ_offset (MPSZ - MMU_REG_BASE)
-#define MASID_offset (MASID - MMU_REG_BASE)
-#define MESTS_offset (MESTS - MMU_REG_BASE)
-#define MDEVA_offset (MDEVA - MMU_REG_BASE)
-#define MDEVP_offset (MDEVP - MMU_REG_BASE)
-#define MPTB_offset (MPTB - MMU_REG_BASE)
-#define MSVA_offset (MSVA - MMU_REG_BASE)
-#define MTOP_offset (MTOP - MMU_REG_BASE)
-#define MIDXI_offset (MIDXI - MMU_REG_BASE)
-#define MIDXD_offset (MIDXD - MMU_REG_BASE)
-
-#define MESTS_IT (1 << 0) /* Instruction TLB miss */
-#define MESTS_IA (1 << 1) /* Instruction Access Exception */
-#define MESTS_DT (1 << 4) /* Operand TLB miss */
-#define MESTS_DA (1 << 5) /* Operand Access Exception */
-#define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
-
-/*
- * PSW (Processor Status Word)
- */
-
-/* PSW bit */
-#define M32R_PSW_BIT_SM (7) /* Stack Mode */
-#define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
-#define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
-#define M32R_PSW_BIT_C (0) /* Condition */
-#define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
-#define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
-#define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
-#define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
-
-/* PSW bit map */
-#define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
-#define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
-#define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
-#define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
-#define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
-#define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
-#define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
-#define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
-
-/*
- * Direct address to SFR
- */
-
-#include <asm/page.h>
-#ifdef CONFIG_MMU
-#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
-#else
-#define NONCACHE_OFFSET __PAGE_OFFSET
-#endif /* CONFIG_MMU */
-
-#define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
-#define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
-#define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
-
-#endif /* _ASM_M32R_M32R_H_ */
diff --git a/arch/m32r/include/asm/m32r_mp_fpga.h b/arch/m32r/include/asm/m32r_mp_fpga.h
deleted file mode 100644
index 8eeaa9a420c5..000000000000
--- a/arch/m32r/include/asm/m32r_mp_fpga.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_M32R_MP_FPGA_
-#define _ASM_M32R_M32R_MP_FPGA_
-
-/*
- * Renesas M32R-MP-FPGA
- *
- * Copyright (c) 2002 Hitoshi Yamamoto
- * Copyright (c) 2003, 2004 Renesas Technology Corp.
- */
-
-/*
- * ========================================================
- * M32R-MP-FPGA Memory Map
- * ========================================================
- * 0x00000000 : Block#0 : 64[MB]
- * 0x03E00000 : SFR
- * 0x03E00000 : reserved
- * 0x03EF0000 : FPGA
- * 0x03EF1000 : reserved
- * 0x03EF4000 : CKM
- * 0x03EF4000 : BSELC
- * 0x03EF5000 : reserved
- * 0x03EFC000 : MFT
- * 0x03EFD000 : SIO
- * 0x03EFE000 : reserved
- * 0x03EFF000 : ICU
- * 0x03F00000 : Internal SRAM 64[KB]
- * 0x03F10000 : reserved
- * --------------------------------------------------------
- * 0x04000000 : Block#1 : 64[MB]
- * 0x04000000 : Debug board SRAM 4[MB]
- * 0x04400000 : reserved
- * --------------------------------------------------------
- * 0x08000000 : Block#2 : 64[MB]
- * --------------------------------------------------------
- * 0x0C000000 : Block#3 : 64[MB]
- * --------------------------------------------------------
- * 0x10000000 : Block#4 : 64[MB]
- * --------------------------------------------------------
- * 0x14000000 : Block#5 : 64[MB]
- * --------------------------------------------------------
- * 0x18000000 : Block#6 : 64[MB]
- * --------------------------------------------------------
- * 0x1C000000 : Block#7 : 64[MB]
- * --------------------------------------------------------
- * 0xFE000000 : TLB
- * 0xFE000000 : ITLB
- * 0xFE000080 : reserved
- * 0xFE000800 : DTLB
- * 0xFE000880 : reserved
- * --------------------------------------------------------
- * 0xFF000000 : System area
- * 0xFFFF0000 : MMU
- * 0xFFFF0030 : reserved
- * 0xFFFF8000 : Debug function
- * 0xFFFFA000 : reserved
- * 0xFFFFC000 : CPU control
- * 0xFFFFFFFF
- * ========================================================
- */
-
-/*======================================================================*
- * Special Function Register
- *======================================================================*/
-#define M32R_SFR_OFFSET (0x00E00000) /* 0x03E00000-0x03EFFFFF 1[MB] */
-
-/*
- * FPGA registers.
- */
-#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
-
-#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME3_PORTL (0x1C+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID3_PORTL (0x2C+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
-
-/*
- * Clock and Power Manager registers.
- */
-#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
-
-#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
-#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
-#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
-
-/*
- * Block SELect Controller registers.
- */
-#define M32R_BSELC_OFFSET (0x000F5000+M32R_SFR_OFFSET)
-
-#define M32R_BSEL0_CR0_PORTL (0x000+M32R_BSELC_OFFSET)
-#define M32R_BSEL0_CR1_PORTL (0x004+M32R_BSELC_OFFSET)
-#define M32R_BSEL1_CR0_PORTL (0x100+M32R_BSELC_OFFSET)
-#define M32R_BSEL1_CR1_PORTL (0x104+M32R_BSELC_OFFSET)
-#define M32R_BSEL2_CR0_PORTL (0x200+M32R_BSELC_OFFSET)
-#define M32R_BSEL2_CR1_PORTL (0x204+M32R_BSELC_OFFSET)
-#define M32R_BSEL3_CR0_PORTL (0x300+M32R_BSELC_OFFSET)
-#define M32R_BSEL3_CR1_PORTL (0x304+M32R_BSELC_OFFSET)
-#define M32R_BSEL4_CR0_PORTL (0x400+M32R_BSELC_OFFSET)
-#define M32R_BSEL4_CR1_PORTL (0x404+M32R_BSELC_OFFSET)
-#define M32R_BSEL5_CR0_PORTL (0x500+M32R_BSELC_OFFSET)
-#define M32R_BSEL5_CR1_PORTL (0x504+M32R_BSELC_OFFSET)
-#define M32R_BSEL6_CR0_PORTL (0x600+M32R_BSELC_OFFSET)
-#define M32R_BSEL6_CR1_PORTL (0x604+M32R_BSELC_OFFSET)
-#define M32R_BSEL7_CR0_PORTL (0x700+M32R_BSELC_OFFSET)
-#define M32R_BSEL7_CR1_PORTL (0x704+M32R_BSELC_OFFSET)
-
-/*
- * Multi Function Timer registers.
- */
-#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
-
-#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
-#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
-
-#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
-#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
-#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
-#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
-#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
-#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
-
-#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
-#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
-#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
-#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
-#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
-#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
-
-#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
-#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
-#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
-#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
-#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
-#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
-
-#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
-#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
-#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
-#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
-#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
-#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
-
-#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
-#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
-#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
-#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
-#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
-
-#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
-#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
-#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
-#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
-#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
-
-#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
-#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
-#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
-#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
-#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
-#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
-#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
-#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
-#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
-#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
-#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
-#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
-
-#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
-#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
-#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
-#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
-#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
-#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
-#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
-#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
-#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
-#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
-#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
-#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
-#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
-#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
-#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
-
-/*
- * Serial I/O registers.
- */
-#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
-
-#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
-#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
-#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
-#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
-#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
-#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
-#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
-
-/*
- * Interrupt Control Unit registers.
- */
-#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
-
-#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
-#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
-#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
-#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
-#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
-#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
-#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
-#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
-#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
-#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
-#define M32R_ICU_CR8_PORTL (0x218+M32R_ICU_OFFSET) /* INT7 */
-#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* SIO0 RX */
-#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* SIO0 TX */
-#define M32R_ICU_CR40_PORTL (0x29C+M32R_ICU_OFFSET) /* DMAC0 */
-#define M32R_ICU_CR41_PORTL (0x2A0+M32R_ICU_OFFSET) /* DMAC1 */
-#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* MFT0 */
-#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* MFT1 */
-#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* MFT2 */
-#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* MFT3 */
-#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* MFT4 */
-#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* MFT5 */
-#define M32R_ICU_IPICR0_PORTL (0x2DC+M32R_ICU_OFFSET) /* IPI0 */
-#define M32R_ICU_IPICR1_PORTL (0x2E0+M32R_ICU_OFFSET) /* IPI1 */
-#define M32R_ICU_IPICR2_PORTL (0x2E4+M32R_ICU_OFFSET) /* IPI2 */
-#define M32R_ICU_IPICR3_PORTL (0x2E8+M32R_ICU_OFFSET) /* IPI3 */
-#define M32R_ICU_IPICR4_PORTL (0x2EC+M32R_ICU_OFFSET) /* IPI4 */
-#define M32R_ICU_IPICR5_PORTL (0x2F0+M32R_ICU_OFFSET) /* IPI5 */
-#define M32R_ICU_IPICR6_PORTL (0x2F4+M32R_ICU_OFFSET) /* IPI6 */
-#define M32R_ICU_IPICR7_PORTL (0x2FC+M32R_ICU_OFFSET) /* IPI7 */
-
-#define M32R_ICUISTS_VECB(val) ((val>>28) & 0xF)
-#define M32R_ICUISTS_ISN(val) ((val>>22) & 0x3F)
-#define M32R_ICUISTS_PIML(val) ((val>>16) & 0x7)
-
-#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
-#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
-#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
-#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
-#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
-#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
-#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
-#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
-
-#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
-#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
-#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
-#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
-#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
-#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
-#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
-#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
-#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
-#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
-#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
-#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
-#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
-#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
-#define M32R_ICUCR_ILEVEL_MASK (7UL)
-
-#define M32R_IRQ_INT0 (1) /* INT0 */
-#define M32R_IRQ_INT1 (2) /* INT1 */
-#define M32R_IRQ_INT2 (3) /* INT2 */
-#define M32R_IRQ_INT3 (4) /* INT3 */
-#define M32R_IRQ_INT4 (5) /* INT4 */
-#define M32R_IRQ_INT5 (6) /* INT5 */
-#define M32R_IRQ_INT6 (7) /* INT6 */
-#define M32R_IRQ_INT7 (8) /* INT7 */
-#define M32R_IRQ_MFT0 (16) /* MFT0 */
-#define M32R_IRQ_MFT1 (17) /* MFT1 */
-#define M32R_IRQ_MFT2 (18) /* MFT2 */
-#define M32R_IRQ_MFT3 (19) /* MFT3 */
-#define M32R_IRQ_MFT4 (20) /* MFT4 */
-#define M32R_IRQ_MFT5 (21) /* MFT5 */
-#define M32R_IRQ_DMAC0 (32) /* DMAC0 */
-#define M32R_IRQ_DMAC1 (33) /* DMAC1 */
-#define M32R_IRQ_SIO0_R (48) /* SIO0 receive */
-#define M32R_IRQ_SIO0_S (49) /* SIO0 send */
-#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
-#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
-#define M32R_IRQ_IPI0 (56) /* IPI0 */
-#define M32R_IRQ_IPI1 (57) /* IPI1 */
-#define M32R_IRQ_IPI2 (58) /* IPI2 */
-#define M32R_IRQ_IPI3 (59) /* IPI3 */
-#define M32R_IRQ_IPI4 (60) /* IPI4 */
-#define M32R_IRQ_IPI5 (61) /* IPI5 */
-#define M32R_IRQ_IPI6 (62) /* IPI6 */
-#define M32R_IRQ_IPI7 (63) /* IPI7 */
-
-/*======================================================================*
- * CPU
- *======================================================================*/
-
-#define M32R_CPUID_PORTL (0xFFFFFFE0)
-#define M32R_MCICAR_PORTL (0xFFFFFFF0)
-#define M32R_MCDCAR_PORTL (0xFFFFFFF4)
-#define M32R_MCCR_PORTL (0xFFFFFFFC)
-
-#endif /* _ASM_M32R_M32R_MP_FPGA_ */
diff --git a/arch/m32r/include/asm/mappi2/mappi2_pld.h b/arch/m32r/include/asm/mappi2/mappi2_pld.h
deleted file mode 100644
index 2624c9db7255..000000000000
--- a/arch/m32r/include/asm/mappi2/mappi2_pld.h
+++ /dev/null
@@ -1,150 +0,0 @@
-#ifndef _MAPPI2_PLD_H
-#define _MAPPI2_PLD_H
-
-/*
- * include/asm-m32r/mappi2/mappi2_pld.h
- *
- * Definitions for Extended IO Logic on MAPPI2 board.
- * based on m32700ut_pld.h
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/* FIXME:
- * Some C functions use non-cache address, so can't define non-cache address.
- */
-#define PLD_BASE (0x10c00000 /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (0x10c00000 + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-
-
-/*==== ICU ====*/
-#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
-#define M32R_IRQ_I2C (28) /* I2C-BUS */
-#if 1
-#define PLD_IRQ_CFIREQ (40) /* CFC Card Interrupt */
-#define PLD_IRQ_CFC_INSERT (41) /* CFC Card Insert */
-#define PLD_IRQ_CFC_EJECT (42) /* CFC Card Eject */
-#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
-#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
-#else
-#define PLD_IRQ_CFIREQ (34) /* CFC Card Interrupt */
-#define PLD_IRQ_CFC_INSERT (35) /* CFC Card Insert */
-#define PLD_IRQ_CFC_EJECT (36) /* CFC Card Eject */
-#define PLD_IRQ_MMCCARD (37) /* MMC Card Insert */
-#define PLD_IRQ_MMCIRQ (38) /* MMC Transfer Done */
-#endif
-
-
-#if 0
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-#endif
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-
-#if 0
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif
-
-#endif /* _MAPPI2_PLD.H */
diff --git a/arch/m32r/include/asm/mappi3/mappi3_pld.h b/arch/m32r/include/asm/mappi3/mappi3_pld.h
deleted file mode 100644
index 451c40ee70af..000000000000
--- a/arch/m32r/include/asm/mappi3/mappi3_pld.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef _MAPPI3_PLD_H
-#define _MAPPI3_PLD_H
-
-/*
- * include/asm-m32r/mappi3/mappi3_pld.h
- *
- * Definitions for Extended IO Logic on MAPPI3 board.
- * based on m32700ut_pld.h
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/* FIXME:
- * Some C functions use non-cache address, so can't define non-cache address.
- */
-#define PLD_BASE (0x1c000000 /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (0x1c000000 + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-
-/* ICU */
-#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
-#define M32R_IRQ_I2C (28) /* I2C-BUS */
-#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */
-#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert & Eject */
-#define PLD_IRQ_IDEIREQ (8) /* INT7 IDE Interrupt */
-#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
-#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
-
-#if 0
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-#endif
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-#if 0
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif
-
-/* Reset Control */
-#define PLD_REBOOT __reg16(PLD_BASE + 0x38000)
-
-#endif /* _MAPPI3_PLD.H */
diff --git a/arch/m32r/include/asm/mc146818rtc.h b/arch/m32r/include/asm/mc146818rtc.h
deleted file mode 100644
index 4effa4704347..000000000000
--- a/arch/m32r/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef _ASM_MC146818RTC_H
-#define _ASM_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x) ((x))
-#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#define RTC_IRQ 8
-
-#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/m32r/include/asm/mmu.h b/arch/m32r/include/asm/mmu.h
deleted file mode 100644
index 34bcccd8007d..000000000000
--- a/arch/m32r/include/asm/mmu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_MMU_H
-#define _ASM_M32R_MMU_H
-
-#if !defined(CONFIG_MMU)
-
-typedef struct {
- unsigned long end_brk;
-} mm_context_t;
-
-#else /* CONFIG_MMU */
-
-/* Default "unsigned long" context */
-#ifndef CONFIG_SMP
-typedef unsigned long mm_context_t;
-#else
-typedef unsigned long mm_context_t[NR_CPUS];
-#endif
-
-#endif /* CONFIG_MMU */
-
-#endif /* _ASM_M32R_MMU_H */
diff --git a/arch/m32r/include/asm/mmu_context.h b/arch/m32r/include/asm/mmu_context.h
deleted file mode 100644
index 8a499d0fb3a2..000000000000
--- a/arch/m32r/include/asm/mmu_context.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_MMU_CONTEXT_H
-#define _ASM_M32R_MMU_CONTEXT_H
-#ifdef __KERNEL__
-
-#include <asm/m32r.h>
-
-#define MMU_CONTEXT_ASID_MASK (0x000000FF)
-#define MMU_CONTEXT_VERSION_MASK (0xFFFFFF00)
-#define MMU_CONTEXT_FIRST_VERSION (0x00000100)
-#define NO_CONTEXT (0x00000000)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/atomic.h>
-#include <linux/mm_types.h>
-
-#include <asm/pgalloc.h>
-#include <asm/mmu.h>
-#include <asm/tlbflush.h>
-#include <asm-generic/mm_hooks.h>
-
-/*
- * Cache of MMU context last used.
- */
-#ifndef CONFIG_SMP
-extern unsigned long mmu_context_cache_dat;
-#define mmu_context_cache mmu_context_cache_dat
-#define mm_context(mm) mm->context
-#else /* not CONFIG_SMP */
-extern unsigned long mmu_context_cache_dat[];
-#define mmu_context_cache mmu_context_cache_dat[smp_processor_id()]
-#define mm_context(mm) mm->context[smp_processor_id()]
-#endif /* not CONFIG_SMP */
-
-#define set_tlb_tag(entry, tag) (*entry = (tag & PAGE_MASK)|get_asid())
-#define set_tlb_data(entry, data) (*entry = (data | _PAGE_PRESENT))
-
-#ifdef CONFIG_MMU
-#define enter_lazy_tlb(mm, tsk) do { } while (0)
-
-static inline void get_new_mmu_context(struct mm_struct *mm)
-{
- unsigned long mc = ++mmu_context_cache;
-
- if (!(mc & MMU_CONTEXT_ASID_MASK)) {
- /* We exhaust ASID of this version.
- Flush all TLB and start new cycle. */
- local_flush_tlb_all();
- /* Fix version if needed.
- Note that we avoid version #0 to distinguish NO_CONTEXT. */
- if (!mc)
- mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
- }
- mm_context(mm) = mc;
-}
-
-/*
- * Get MMU context if needed.
- */
-static inline void get_mmu_context(struct mm_struct *mm)
-{
- if (mm) {
- unsigned long mc = mmu_context_cache;
-
- /* Check if we have old version of context.
- If it's old, we need to get new context with new version. */
- if ((mm_context(mm) ^ mc) & MMU_CONTEXT_VERSION_MASK)
- get_new_mmu_context(mm);
- }
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-static inline int init_new_context(struct task_struct *tsk,
- struct mm_struct *mm)
-{
-#ifndef CONFIG_SMP
- mm->context = NO_CONTEXT;
-#else /* CONFIG_SMP */
- int num_cpus = num_online_cpus();
- int i;
-
- for (i = 0 ; i < num_cpus ; i++)
- mm->context[i] = NO_CONTEXT;
-#endif /* CONFIG_SMP */
-
- return 0;
-}
-
-/*
- * Destroy context related info for an mm_struct that is about
- * to be put to rest.
- */
-#define destroy_context(mm) do { } while (0)
-
-static inline void set_asid(unsigned long asid)
-{
- *(volatile unsigned long *)MASID = (asid & MMU_CONTEXT_ASID_MASK);
-}
-
-static inline unsigned long get_asid(void)
-{
- unsigned long asid;
-
- asid = *(volatile long *)MASID;
- asid &= MMU_CONTEXT_ASID_MASK;
-
- return asid;
-}
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void activate_context(struct mm_struct *mm)
-{
- get_mmu_context(mm);
- set_asid(mm_context(mm) & MMU_CONTEXT_ASID_MASK);
-}
-
-static inline void switch_mm(struct mm_struct *prev,
- struct mm_struct *next, struct task_struct *tsk)
-{
-#ifdef CONFIG_SMP
- int cpu = smp_processor_id();
-#endif /* CONFIG_SMP */
-
- if (prev != next) {
-#ifdef CONFIG_SMP
- cpumask_set_cpu(cpu, mm_cpumask(next));
-#endif /* CONFIG_SMP */
- /* Set MPTB = next->pgd */
- *(volatile unsigned long *)MPTB = (unsigned long)next->pgd;
- activate_context(next);
- }
-#ifdef CONFIG_SMP
- else
- if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)))
- activate_context(next);
-#endif /* CONFIG_SMP */
-}
-
-#define deactivate_mm(tsk, mm) do { } while (0)
-
-#define activate_mm(prev, next) \
- switch_mm((prev), (next), NULL)
-
-#else /* not CONFIG_MMU */
-#define get_mmu_context(mm) do { } while (0)
-#define init_new_context(tsk,mm) (0)
-#define destroy_context(mm) do { } while (0)
-#define set_asid(asid) do { } while (0)
-#define get_asid() (0)
-#define activate_context(mm) do { } while (0)
-#define switch_mm(prev,next,tsk) do { } while (0)
-#define deactivate_mm(mm,tsk) do { } while (0)
-#define activate_mm(prev,next) do { } while (0)
-#define enter_lazy_tlb(mm,tsk) do { } while (0)
-#endif /* not CONFIG_MMU */
-
-#endif /* not __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_M32R_MMU_CONTEXT_H */
diff --git a/arch/m32r/include/asm/mmzone.h b/arch/m32r/include/asm/mmzone.h
deleted file mode 100644
index 568946c13ba6..000000000000
--- a/arch/m32r/include/asm/mmzone.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Written by Pat Gaughen (gone@us.ibm.com) Mar 2002
- *
- */
-
-#ifndef _ASM_MMZONE_H_
-#define _ASM_MMZONE_H_
-
-#include <asm/smp.h>
-
-#ifdef CONFIG_DISCONTIGMEM
-
-extern struct pglist_data *node_data[];
-#define NODE_DATA(nid) (node_data[nid])
-
-#define node_localnr(pfn, nid) ((pfn) - NODE_DATA(nid)->node_start_pfn)
-
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-/*
- * pfn_valid should be made as fast as possible, and the current definition
- * is valid for machines that are NUMA, but still contiguous, which is what
- * is currently supported. A more generalised, but slower definition would
- * be something like this - mbligh:
- * ( pfn_to_pgdat(pfn) && ((pfn) < node_end_pfn(pfn_to_nid(pfn))) )
- */
-#if 1 /* M32R_FIXME */
-#define pfn_valid(pfn) (1)
-#else
-#define pfn_valid(pfn) ((pfn) < num_physpages)
-#endif
-
-/*
- * generic node memory support, the following assumptions apply:
- */
-
-static __inline__ int pfn_to_nid(unsigned long pfn)
-{
- int node;
-
- for (node = 0 ; node < MAX_NUMNODES ; node++)
- if (pfn >= node_start_pfn(node) && pfn < node_end_pfn(node))
- break;
-
- return node;
-}
-
-static __inline__ struct pglist_data *pfn_to_pgdat(unsigned long pfn)
-{
- return(NODE_DATA(pfn_to_nid(pfn)));
-}
-
-#endif /* CONFIG_DISCONTIGMEM */
-#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/m32r/include/asm/opsput/opsput_lan.h b/arch/m32r/include/asm/opsput/opsput_lan.h
deleted file mode 100644
index a5f18dd1ab20..000000000000
--- a/arch/m32r/include/asm/opsput/opsput_lan.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef _OPSPUT_OPSPUT_LAN_H
-#define _OPSPUT_OPSPUT_LAN_H
-
-/*
- * include/asm-m32r/opsput/opsput_lan.h
- *
- * OPSPUT-LAN board
- *
- * Copyright (c) 2002-2004 Takeo Takahashi, Mamoru Sakugawa
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define OPSPUT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define OPSPUT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#define OPSPUT_LAN_IRQ_LAN (OPSPUT_LAN_PLD_IRQ_BASE + 1) /* LAN */
-#define OPSPUT_LAN_IRQ_I2C (OPSPUT_LAN_PLD_IRQ_BASE + 3) /* I2C */
-
-#define OPSPUT_LAN_ICUISTS __reg16(OPSPUT_LAN_BASE + 0xc0002)
-#define OPSPUT_LAN_ICUISTS_VECB_MASK (0xf000)
-#define OPSPUT_LAN_VECB(x) ((x) & OPSPUT_LAN_ICUISTS_VECB_MASK)
-#define OPSPUT_LAN_ICUISTS_ISN_MASK (0x07c0)
-#define OPSPUT_LAN_ICUISTS_ISN(x) ((x) & OPSPUT_LAN_ICUISTS_ISN_MASK)
-#define OPSPUT_LAN_ICUIREQ0 __reg16(OPSPUT_LAN_BASE + 0xc0004)
-#define OPSPUT_LAN_ICUCR1 __reg16(OPSPUT_LAN_BASE + 0xc0010)
-#define OPSPUT_LAN_ICUCR3 __reg16(OPSPUT_LAN_BASE + 0xc0014)
-
-#endif /* _OPSPUT_OPSPUT_LAN_H */
diff --git a/arch/m32r/include/asm/opsput/opsput_lcd.h b/arch/m32r/include/asm/opsput/opsput_lcd.h
deleted file mode 100644
index 369c9f0832a6..000000000000
--- a/arch/m32r/include/asm/opsput/opsput_lcd.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _OPSPUT_OPSPUT_LCD_H
-#define _OPSPUT_OPSPUT_LCD_H
-
-/*
- * include/asm-m32r/opsput/opsput_lcd.h
- *
- * OPSPUT-LCD board
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define OPSPUT_LCD_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define OPSPUT_LCD_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/*
- * ICU
- */
-#define OPSPUT_LCD_IRQ_BAT_INT (OPSPUT_LCD_PLD_IRQ_BASE + 1)
-#define OPSPUT_LCD_IRQ_USB_INT1 (OPSPUT_LCD_PLD_IRQ_BASE + 2)
-#define OPSPUT_LCD_IRQ_AUDT0 (OPSPUT_LCD_PLD_IRQ_BASE + 3)
-#define OPSPUT_LCD_IRQ_AUDT2 (OPSPUT_LCD_PLD_IRQ_BASE + 4)
-#define OPSPUT_LCD_IRQ_BATSIO_RCV (OPSPUT_LCD_PLD_IRQ_BASE + 16)
-#define OPSPUT_LCD_IRQ_BATSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 17)
-#define OPSPUT_LCD_IRQ_ASNDSIO_RCV (OPSPUT_LCD_PLD_IRQ_BASE + 18)
-#define OPSPUT_LCD_IRQ_ASNDSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 19)
-#define OPSPUT_LCD_IRQ_ACNLSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 21)
-
-#define OPSPUT_LCD_ICUISTS __reg16(OPSPUT_LCD_BASE + 0x300002)
-#define OPSPUT_LCD_ICUISTS_VECB_MASK (0xf000)
-#define OPSPUT_LCD_VECB(x) ((x) & OPSPUT_LCD_ICUISTS_VECB_MASK)
-#define OPSPUT_LCD_ICUISTS_ISN_MASK (0x07c0)
-#define OPSPUT_LCD_ICUISTS_ISN(x) ((x) & OPSPUT_LCD_ICUISTS_ISN_MASK)
-#define OPSPUT_LCD_ICUIREQ0 __reg16(OPSPUT_LCD_BASE + 0x300004)
-#define OPSPUT_LCD_ICUIREQ1 __reg16(OPSPUT_LCD_BASE + 0x300006)
-#define OPSPUT_LCD_ICUCR1 __reg16(OPSPUT_LCD_BASE + 0x300020)
-#define OPSPUT_LCD_ICUCR2 __reg16(OPSPUT_LCD_BASE + 0x300022)
-#define OPSPUT_LCD_ICUCR3 __reg16(OPSPUT_LCD_BASE + 0x300024)
-#define OPSPUT_LCD_ICUCR4 __reg16(OPSPUT_LCD_BASE + 0x300026)
-#define OPSPUT_LCD_ICUCR16 __reg16(OPSPUT_LCD_BASE + 0x300030)
-#define OPSPUT_LCD_ICUCR17 __reg16(OPSPUT_LCD_BASE + 0x300032)
-#define OPSPUT_LCD_ICUCR18 __reg16(OPSPUT_LCD_BASE + 0x300034)
-#define OPSPUT_LCD_ICUCR19 __reg16(OPSPUT_LCD_BASE + 0x300036)
-#define OPSPUT_LCD_ICUCR21 __reg16(OPSPUT_LCD_BASE + 0x30003a)
-
-#endif /* _OPSPUT_OPSPUT_LCD_H */
diff --git a/arch/m32r/include/asm/opsput/opsput_pld.h b/arch/m32r/include/asm/opsput/opsput_pld.h
deleted file mode 100644
index 6901401fe9eb..000000000000
--- a/arch/m32r/include/asm/opsput/opsput_pld.h
+++ /dev/null
@@ -1,255 +0,0 @@
-#ifndef _OPSPUT_OPSPUT_PLD_H
-#define _OPSPUT_OPSPUT_PLD_H
-
-/*
- * include/asm-m32r/opsput/opsput_pld.h
- *
- * Definitions for Programmable Logic Device(PLD) on OPSPUT board.
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#define PLD_PLAT_BASE 0x1cc00000
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#if !defined(CONFIG_PLAT_USRV)
-#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CFIREQ (OPSPUT_PLD_IRQ_BASE + 3) /* CF IREQ */
-#define PLD_IRQ_CFC_INSERT (OPSPUT_PLD_IRQ_BASE + 4) /* CF Insert */
-#define PLD_IRQ_CFC_EJECT (OPSPUT_PLD_IRQ_BASE + 5) /* CF Eject */
-#define PLD_IRQ_EXINT (OPSPUT_PLD_IRQ_BASE + 6) /* EXINT */
-#define PLD_IRQ_INT7 (OPSPUT_PLD_IRQ_BASE + 7) /* reserved */
-#define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_MMCCARD (OPSPUT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
-#define PLD_IRQ_INT12 (OPSPUT_PLD_IRQ_BASE + 12) /* reserved */
-#define PLD_IRQ_SC_ERROR (OPSPUT_PLD_IRQ_BASE + 13) /* SC error */
-#define PLD_IRQ_SC_RCV (OPSPUT_PLD_IRQ_BASE + 14) /* SC receive */
-#define PLD_IRQ_SC_SND (OPSPUT_PLD_IRQ_BASE + 15) /* SC send */
-#define PLD_IRQ_SIO0_RCV (OPSPUT_PLD_IRQ_BASE + 16) /* SIO receive */
-#define PLD_IRQ_SIO0_SND (OPSPUT_PLD_IRQ_BASE + 17) /* SIO send */
-#define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */
-#define PLD_IRQ_INT31 (OPSPUT_PLD_IRQ_BASE + 31) /* reserved */
-
-#else /* CONFIG_PLAT_USRV */
-
-#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CF0 (OPSPUT_PLD_IRQ_BASE + 3) /* CF0# */
-#define PLD_IRQ_CF1 (OPSPUT_PLD_IRQ_BASE + 4) /* CF1# */
-#define PLD_IRQ_CF2 (OPSPUT_PLD_IRQ_BASE + 5) /* CF2# */
-#define PLD_IRQ_CF3 (OPSPUT_PLD_IRQ_BASE + 6) /* CF3# */
-#define PLD_IRQ_CF4 (OPSPUT_PLD_IRQ_BASE + 7) /* CF4# */
-#define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_INT11 (OPSPUT_PLD_IRQ_BASE + 11) /* reserved */
-#define PLD_IRQ_UART0 (OPSPUT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
-#define PLD_IRQ_UART1 (OPSPUT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
-#define PLD_IRQ_INT14 (OPSPUT_PLD_IRQ_BASE + 14) /* reserved */
-#define PLD_IRQ_INT15 (OPSPUT_PLD_IRQ_BASE + 15) /* reserved */
-#define PLD_IRQ_SNDINT (OPSPUT_PLD_IRQ_BASE + 16) /* SNDINT# */
-#define PLD_IRQ_INT17 (OPSPUT_PLD_IRQ_BASE + 17) /* reserved */
-#define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */
-
-#endif /* CONFIG_PLAT_USRV */
-
-#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
-#define PLD_ICUISTS_VECB_MASK (0xf000)
-#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
-#define PLD_ICUISTS_ISN_MASK (0x07c0)
-#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
-#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
-#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
-#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
-#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
-#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
-#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
-#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
-#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
-#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
-#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
-#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
-#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
-#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
-#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
-#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
-#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
-#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
-#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
-#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
-#define PLD_ICUCR_IEN (0x1000)
-#define PLD_ICUCR_IREQ (0x0100)
-#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
-#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
-#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
-#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
-#define PLD_ICUCR_ILEVEL0 (0x0000)
-#define PLD_ICUCR_ILEVEL1 (0x0001)
-#define PLD_ICUCR_ILEVEL2 (0x0002)
-#define PLD_ICUCR_ILEVEL3 (0x0003)
-#define PLD_ICUCR_ILEVEL4 (0x0004)
-#define PLD_ICUCR_ILEVEL5 (0x0005)
-#define PLD_ICUCR_ILEVEL6 (0x0006)
-#define PLD_ICUCR_ILEVEL7 (0x0007)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-#define PLD_CPCR_CF 0x0001
-#define PLD_CPCR_MMC 0x0002
-
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif /* _OPSPUT_OPSPUT_PLD.H */
diff --git a/arch/m32r/include/asm/page.h b/arch/m32r/include/asm/page.h
deleted file mode 100644
index fe4e38b394d3..000000000000
--- a/arch/m32r/include/asm/page.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PAGE_H
-#define _ASM_M32R_PAGE_H
-
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT 12
-#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#ifndef __ASSEMBLY__
-
-extern void clear_page(void *to);
-extern void copy_page(void *to, void *from);
-
-#define clear_user_page(page, vaddr, pg) clear_page(page)
-#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
- alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-#define pte_val(x) ((x).pte)
-#define PTE_MASK PAGE_MASK
-
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pmd_val(x) ((x).pmd)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pmd(x) ((pmd_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * This handles the memory map.. We could make this a config
- * option, but too many people screw it up, and too few need
- * it.
- *
- * A __PAGE_OFFSET of 0xC0000000 means that the kernel has
- * a virtual address space of one gigabyte, which limits the
- * amount of physical memory you can use to about 950MB.
- *
- * If you want more physical memory than this then see the CONFIG_HIGHMEM4G
- * and CONFIG_HIGHMEM64G options in the kernel configuration.
- */
-
-#define __MEMORY_START CONFIG_MEMORY_START
-#define __MEMORY_SIZE CONFIG_MEMORY_SIZE
-
-#ifdef CONFIG_MMU
-#define __PAGE_OFFSET (0x80000000)
-#else
-#define __PAGE_OFFSET (0x00000000)
-#endif
-
-#define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET)
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
-#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define PFN_BASE (CONFIG_MEMORY_START >> PAGE_SHIFT)
-#define ARCH_PFN_OFFSET PFN_BASE
-#define pfn_valid(pfn) (((pfn) - PFN_BASE) < max_mapnr)
-#endif /* !CONFIG_DISCONTIGMEM */
-
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC )
-
-#define devmem_is_allowed(x) 1
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _ASM_M32R_PAGE_H */
diff --git a/arch/m32r/include/asm/pci.h b/arch/m32r/include/asm/pci.h
deleted file mode 100644
index cbcb28b5f6ff..000000000000
--- a/arch/m32r/include/asm/pci.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PCI_H
-#define _ASM_M32R_PCI_H
-
-#include <asm-generic/pci.h>
-
-#endif /* _ASM_M32R_PCI_H */
diff --git a/arch/m32r/include/asm/percpu.h b/arch/m32r/include/asm/percpu.h
deleted file mode 100644
index 41e1680d1117..000000000000
--- a/arch/m32r/include/asm/percpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ARCH_M32R_PERCPU__
-#define __ARCH_M32R_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_M32R_PERCPU__ */
diff --git a/arch/m32r/include/asm/pgalloc.h b/arch/m32r/include/asm/pgalloc.h
deleted file mode 100644
index eed2cad57d68..000000000000
--- a/arch/m32r/include/asm/pgalloc.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PGALLOC_H
-#define _ASM_M32R_PGALLOC_H
-
-#include <linux/mm.h>
-
-#include <asm/io.h>
-
-#define pmd_populate_kernel(mm, pmd, pte) \
- set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
-
-static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- pgtable_t pte)
-{
- set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
-}
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
-
- return pgd;
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-static __inline__ pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
-
- return pte;
-}
-
-static __inline__ pgtable_t pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- struct page *pte = alloc_page(GFP_KERNEL|__GFP_ZERO);
-
- if (!pte)
- return NULL;
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, (pte))
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- * (In the PAE case we free the pmds as part of the pgd.)
- */
-
-#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
-#define pmd_free(mm, x) do { } while (0)
-#define __pmd_free_tlb(tlb, x, addr) do { } while (0)
-#define pgd_populate(mm, pmd, pte) BUG()
-
-#define check_pgt_cache() do { } while (0)
-
-#endif /* _ASM_M32R_PGALLOC_H */
diff --git a/arch/m32r/include/asm/pgtable-2level.h b/arch/m32r/include/asm/pgtable-2level.h
deleted file mode 100644
index d7ab1e94e3cb..000000000000
--- a/arch/m32r/include/asm/pgtable-2level.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PGTABLE_2LEVEL_H
-#define _ASM_M32R_PGTABLE_2LEVEL_H
-#ifdef __KERNEL__
-
-/*
- * traditional M32R two-level paging structure:
- */
-
-#define PGDIR_SHIFT 22
-#define PTRS_PER_PGD 1024
-
-/*
- * the M32R is two-level, so we don't really have any
- * PMD directory physically.
- */
-#define __PAGETABLE_PMD_FOLDED
-#define PMD_SHIFT 22
-#define PTRS_PER_PMD 1
-
-#define PTRS_PER_PTE 1024
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd) { return 0; }
-static inline int pgd_bad(pgd_t pgd) { return 0; }
-static inline int pgd_present(pgd_t pgd) { return 1; }
-#define pgd_clear(xp) do { } while (0)
-
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
-
-#define pgd_page_vaddr(pgd) \
-((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pgd_page(pgd) (mem_map + ((pgd_val(pgd) >> PAGE_SHIFT) - PFN_BASE))
-#endif /* !CONFIG_DISCONTIGMEM */
-
-static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
-{
- return (pmd_t *) dir;
-}
-
-#define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte, 0))
-#define pte_same(a, b) (pte_val(a) == pte_val(b))
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-#define pte_none(x) (!pte_val(x))
-#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_M32R_PGTABLE_2LEVEL_H */
diff --git a/arch/m32r/include/asm/pgtable.h b/arch/m32r/include/asm/pgtable.h
deleted file mode 100644
index eb7f9050c8d6..000000000000
--- a/arch/m32r/include/asm/pgtable.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PGTABLE_H
-#define _ASM_M32R_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#ifdef __KERNEL__
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * the M32R, we use that, but "fold" the mid level into the top-level page
- * table, so that we physically have the same two-level page table as the
- * M32R mmu expects.
- *
- * This file contains the functions and defines necessary to modify and use
- * the M32R page table tree.
- */
-
-/* CAUTION!: If you change macro definitions in this file, you might have to
- * change arch/m32r/mmu.S manually.
- */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/threads.h>
-#include <linux/bitops.h>
-#include <asm/processor.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-
-struct mm_struct;
-struct vm_area_struct;
-
-extern pgd_t swapper_pg_dir[1024];
-extern void paging_init(void);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[1024];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-#endif /* !__ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-#include <asm/pgtable-2level.h>
-#endif
-
-#define pgtable_cache_init() do { } while (0)
-
-#define PMD_SIZE (1UL << PMD_SHIFT)
-#define PMD_MASK (~(PMD_SIZE - 1))
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-
-#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-#ifndef __ASSEMBLY__
-/* Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts. That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_START KSEG2
-#define VMALLOC_END KSEG3
-
-/*
- * M32R TLB format
- *
- * [0] [1:19] [20:23] [24:31]
- * +-----------------------+----+-------------+
- * | VPN |0000| ASID |
- * +-----------------------+----+-------------+
- * +-+---------------------+----+-+---+-+-+-+-+
- * |0 PPN |0000|N|AC |L|G|V| |
- * +-+---------------------+----+-+---+-+-+-+-+
- * RWX
- */
-
-#define _PAGE_BIT_DIRTY 0 /* software: page changed */
-#define _PAGE_BIT_PRESENT 1 /* Valid: page is valid */
-#define _PAGE_BIT_GLOBAL 2 /* Global */
-#define _PAGE_BIT_LARGE 3 /* Large */
-#define _PAGE_BIT_EXEC 4 /* Execute */
-#define _PAGE_BIT_WRITE 5 /* Write */
-#define _PAGE_BIT_READ 6 /* Read */
-#define _PAGE_BIT_NONCACHABLE 7 /* Non cachable */
-#define _PAGE_BIT_ACCESSED 8 /* software: page referenced */
-#define _PAGE_BIT_PROTNONE 9 /* software: if not present */
-
-#define _PAGE_DIRTY (1UL << _PAGE_BIT_DIRTY)
-#define _PAGE_PRESENT (1UL << _PAGE_BIT_PRESENT)
-#define _PAGE_GLOBAL (1UL << _PAGE_BIT_GLOBAL)
-#define _PAGE_LARGE (1UL << _PAGE_BIT_LARGE)
-#define _PAGE_EXEC (1UL << _PAGE_BIT_EXEC)
-#define _PAGE_WRITE (1UL << _PAGE_BIT_WRITE)
-#define _PAGE_READ (1UL << _PAGE_BIT_READ)
-#define _PAGE_NONCACHABLE (1UL << _PAGE_BIT_NONCACHABLE)
-#define _PAGE_ACCESSED (1UL << _PAGE_BIT_ACCESSED)
-#define _PAGE_PROTNONE (1UL << _PAGE_BIT_PROTNONE)
-
-#define _PAGE_TABLE \
- ( _PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED \
- | _PAGE_DIRTY )
-#define _KERNPG_TABLE \
- ( _PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED \
- | _PAGE_DIRTY )
-#define _PAGE_CHG_MASK \
- ( PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY )
-
-#ifdef CONFIG_MMU
-#define PAGE_NONE \
- __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
-#define PAGE_SHARED \
- __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_SHARED_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_WRITE | _PAGE_READ \
- | _PAGE_ACCESSED)
-#define PAGE_COPY \
- __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_COPY_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_READONLY \
- __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_READONLY_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_ACCESSED)
-
-#define __PAGE_KERNEL \
- ( _PAGE_PRESENT | _PAGE_EXEC | _PAGE_WRITE | _PAGE_READ | _PAGE_DIRTY \
- | _PAGE_ACCESSED )
-#define __PAGE_KERNEL_RO ( __PAGE_KERNEL & ~_PAGE_WRITE )
-#define __PAGE_KERNEL_NOCACHE ( __PAGE_KERNEL | _PAGE_NONCACHABLE)
-
-#define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
-
-#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
-#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
-#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
-
-#else
-#define PAGE_NONE __pgprot(0)
-#define PAGE_SHARED __pgprot(0)
-#define PAGE_SHARED_EXEC __pgprot(0)
-#define PAGE_COPY __pgprot(0)
-#define PAGE_COPY_EXEC __pgprot(0)
-#define PAGE_READONLY __pgprot(0)
-#define PAGE_READONLY_EXEC __pgprot(0)
-
-#define PAGE_KERNEL __pgprot(0)
-#define PAGE_KERNEL_RO __pgprot(0)
-#define PAGE_KERNEL_NOCACHE __pgprot(0)
-#endif /* CONFIG_MMU */
-
- /* xwr */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY_EXEC
-#define __P101 PAGE_READONLY_EXEC
-#define __P110 PAGE_COPY_EXEC
-#define __P111 PAGE_COPY_EXEC
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY_EXEC
-#define __S101 PAGE_READONLY_EXEC
-#define __S110 PAGE_SHARED_EXEC
-#define __S111 PAGE_SHARED_EXEC
-
-/* page table for 0-4MB for everybody */
-
-#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
-#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK) != _KERNPG_TABLE)
-
-#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_dirty(pte_t pte)
-{
- return pte_val(pte) & _PAGE_DIRTY;
-}
-
-static inline int pte_young(pte_t pte)
-{
- return pte_val(pte) & _PAGE_ACCESSED;
-}
-
-static inline int pte_write(pte_t pte)
-{
- return pte_val(pte) & _PAGE_WRITE;
-}
-
-static inline int pte_special(pte_t pte)
-{
- return 0;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
- pte_val(pte) &= ~_PAGE_DIRTY;
- return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
- pte_val(pte) &= ~_PAGE_ACCESSED;
- return pte;
-}
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- pte_val(pte) &= ~_PAGE_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
- pte_val(pte) |= _PAGE_DIRTY;
- return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
- pte_val(pte) |= _PAGE_ACCESSED;
- return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= _PAGE_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkspecial(pte_t pte)
-{
- return pte;
-}
-
-static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
-{
- return test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep);
-}
-
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- clear_bit(_PAGE_BIT_WRITE, ptep);
-}
-
-/*
- * Macro and implementation to make a page protection as uncachable.
- */
-static inline pgprot_t pgprot_noncached(pgprot_t _prot)
-{
- unsigned long prot = pgprot_val(_prot);
-
- prot |= _PAGE_NONCACHABLE;
- return __pgprot(prot);
-}
-
-#define pgprot_writecombine(prot) pgprot_noncached(prot)
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), pgprot)
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) \
- | pgprot_val(newprot)));
-
- return pte;
-}
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
-{
- pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
-}
-
-#define pmd_page_vaddr(pmd) \
- ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pmd_page(pmd) (mem_map + ((pmd_val(pmd) >> PAGE_SHIFT) - PFN_BASE))
-#endif /* !CONFIG_DISCONTIGMEM */
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) \
- (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-#define pmd_index(address) \
- (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
-
-#define pte_index(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *)pmd_page_vaddr(*(dir)) + pte_index(address))
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) do { } while (0)
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x) (((x).val >> 2) & 0x1f)
-#define __swp_offset(x) ((x).val >> 10)
-#define __swp_entry(type, offset) \
- ((swp_entry_t) { ((type) << 2) | ((offset) << 10) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#endif /* !__ASSEMBLY__ */
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define kern_addr_valid(addr) (1)
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define __HAVE_ARCH_PTE_SAME
-#include <asm-generic/pgtable.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_PGTABLE_H */
diff --git a/arch/m32r/include/asm/processor.h b/arch/m32r/include/asm/processor.h
deleted file mode 100644
index c70fa9ac7169..000000000000
--- a/arch/m32r/include/asm/processor.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _ASM_M32R_PROCESSOR_H
-#define _ASM_M32R_PROCESSOR_H
-
-/*
- * include/asm-m32r/processor.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 Linus Torvalds
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/kernel.h>
-#include <asm/cache.h>
-#include <asm/ptrace.h> /* pt_regs */
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l; })
-
-/*
- * CPU type and hardware bug flags. Kept separately for each CPU.
- * Members of this structure are referenced in head.S, so think twice
- * before touching them. [mj]
- */
-
-struct cpuinfo_m32r {
- unsigned long pgtable_cache_sz;
- unsigned long cpu_clock;
- unsigned long bus_clock;
- unsigned long timer_divide;
- unsigned long loops_per_jiffy;
-};
-
-/*
- * capabilities of CPUs
- */
-
-extern struct cpuinfo_m32r boot_cpu_data;
-
-#ifdef CONFIG_SMP
-extern struct cpuinfo_m32r cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
-#endif
-
-/*
- * User space process size: 2GB (default).
- */
-#ifdef CONFIG_MMU
-#define TASK_SIZE (0x80000000UL)
-#else
-#define TASK_SIZE (0x00400000UL)
-#endif
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-#endif
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#define MAX_TRAPS 10
-
-struct debug_trap {
- int nr_trap;
- unsigned long addr[MAX_TRAPS];
- unsigned long insn[MAX_TRAPS];
-};
-
-struct thread_struct {
- unsigned long address;
- unsigned long trap_no; /* Trap number */
- unsigned long error_code; /* Error code of trap */
- unsigned long lr; /* saved pc */
- unsigned long sp; /* user stack pointer */
- struct debug_trap debug_trap;
-};
-
-#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD { \
- .sp = INIT_SP, \
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- */
-
-/* User process Backup PSW */
-#define USERPS_BPSW (M32R_PSW_BSM|M32R_PSW_BIE|M32R_PSW_BPM)
-
-#define start_thread(regs, new_pc, new_spu) \
- do { \
- regs->psw = (regs->psw | USERPS_BPSW) & 0x0000FFFFUL; \
- regs->bpc = new_pc; \
- regs->spu = new_spu; \
- } while (0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-struct mm_struct;
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-unsigned long get_wchan(struct task_struct *p);
-#define KSTK_EIP(tsk) ((tsk)->thread.lr)
-#define KSTK_ESP(tsk) ((tsk)->thread.sp)
-
-#define cpu_relax() barrier()
-
-#endif /* _ASM_M32R_PROCESSOR_H */
diff --git a/arch/m32r/include/asm/ptrace.h b/arch/m32r/include/asm/ptrace.h
deleted file mode 100644
index fa58ccfff865..000000000000
--- a/arch/m32r/include/asm/ptrace.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * linux/include/asm-m32r/ptrace.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * M32R version:
- * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_PTRACE_H
-#define _ASM_M32R_PTRACE_H
-
-
-#include <asm/m32r.h> /* M32R_PSW_BSM, M32R_PSW_BPM */
-#include <uapi/asm/ptrace.h>
-
-#define arch_has_single_step() (1)
-
-struct task_struct;
-extern void init_debug_traps(struct task_struct *);
-#define arch_ptrace_attach(child) \
- init_debug_traps(child)
-
-#if defined(CONFIG_ISA_M32R2) || defined(CONFIG_CHIP_VDEC2)
-#define user_mode(regs) ((M32R_PSW_BPM & (regs)->psw) != 0)
-#elif defined(CONFIG_ISA_M32R)
-#define user_mode(regs) ((M32R_PSW_BSM & (regs)->psw) != 0)
-#else
-#error unknown isa configuration
-#endif
-
-#define instruction_pointer(regs) ((regs)->bpc)
-#define profile_pc(regs) instruction_pointer(regs)
-#define user_stack_pointer(regs) ((regs)->spu)
-
-extern void withdraw_debug_trap(struct pt_regs *regs);
-
-#define task_pt_regs(task) \
- ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE) - 1)
-#define current_pt_regs() ((struct pt_regs *) \
- ((unsigned long)current_thread_info() + THREAD_SIZE) - 1)
-
-#endif /* _ASM_M32R_PTRACE_H */
diff --git a/arch/m32r/include/asm/rtc.h b/arch/m32r/include/asm/rtc.h
deleted file mode 100644
index a94cf1edc60f..000000000000
--- a/arch/m32r/include/asm/rtc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __RTC_H__
-#define __RTC_H__
-
- /* Dallas DS1302 clock/calendar register numbers. */
-# define RTC_SECONDS 0
-# define RTC_MINUTES 1
-# define RTC_HOURS 2
-# define RTC_DAY_OF_MONTH 3
-# define RTC_MONTH 4
-# define RTC_WEEKDAY 5
-# define RTC_YEAR 6
-# define RTC_CONTROL 7
-
- /* Bits in CONTROL register. */
-# define RTC_CONTROL_WRITEPROTECT 0x80
-# define RTC_TRICKLECHARGER 8
-
- /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */
-# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */
-# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */
-# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */
-# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */
-# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */
-# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */
-# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */
-
-#ifdef CONFIG_DS1302
-extern unsigned char ds1302_readreg(int reg);
-extern void ds1302_writereg(int reg, unsigned char val);
-extern int ds1302_init(void);
-# define CMOS_READ(x) ds1302_readreg(x)
-# define CMOS_WRITE(val,reg) ds1302_writereg(reg,val)
-# define RTC_INIT() ds1302_init()
-#else
- /* No RTC configured so we shouldn't try to access any. */
-# define CMOS_READ(x) 42
-# define CMOS_WRITE(x,y)
-# define RTC_INIT() (-1)
-#endif
-
-/*
- * The struct used to pass data via the following ioctl. Similar to the
- * struct tm in <time.h>, but it needs to be here so that the kernel
- * source is self contained, allowing cross-compiles, etc. etc.
- */
-struct rtc_time {
- int tm_sec;
- int tm_min;
- int tm_hour;
- int tm_mday;
- int tm_mon;
- int tm_year;
- int tm_wday;
- int tm_yday;
- int tm_isdst;
-};
-
-/* ioctl() calls that are permitted to the /dev/rtc interface. */
-#define RTC_MAGIC 'p'
-#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */
-#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */
-#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int)
-#define RTC_MAX_IOCTL 0x0b
-
-#endif /* __RTC_H__ */
diff --git a/arch/m32r/include/asm/s1d13806.h b/arch/m32r/include/asm/s1d13806.h
deleted file mode 100644
index 79e98a259ebe..000000000000
--- a/arch/m32r/include/asm/s1d13806.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-//----------------------------------------------------------------------------
-//
-// File generated by S1D13806CFG.EXE
-//
-// Copyright (c) 2000,2001 Epson Research and Development, Inc.
-// All rights reserved.
-//
-//----------------------------------------------------------------------------
-
-// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
-// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
-
-#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */
-
-static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
-
- {0x0001,0x00}, // Miscellaneous Register
- {0x01FC,0x00}, // Display Mode Register
-#if defined(CONFIG_PLAT_MAPPI)
- {0x0004,0x00}, // General IO Pins Configuration Register 0
- {0x0005,0x00}, // General IO Pins Configuration Register 1
- {0x0008,0x00}, // General IO Pins Control Register 0
- {0x0009,0x00}, // General IO Pins Control Register 1
- {0x0010,0x00}, // Memory Clock Configuration Register
- {0x0014,0x00}, // LCD Pixel Clock Configuration Register
- {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
- {0x001C,0x00}, // MediaPlug Clock Configuration Register
-/*
- * .. 10MHz: 0x00
- * .. 30MHz: 0x01
- * 30MHz ..: 0x02
- */
- {0x001E,0x02}, // CPU To Memory Wait State Select Register
- {0x0021,0x02}, // DRAM Refresh Rate Register
- {0x002A,0x11}, // DRAM Timings Control Register 0
- {0x002B,0x13}, // DRAM Timings Control Register 1
- {0x0020,0x80}, // Memory Configuration Register
- {0x0030,0x25}, // Panel Type Register
- {0x0031,0x00}, // MOD Rate Register
- {0x0032,0x4F}, // LCD Horizontal Display Width Register
- {0x0034,0x12}, // LCD Horizontal Non-Display Period Register
- {0x0035,0x01}, // TFT FPLINE Start Position Register
- {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
- {0x0038,0xDF}, // LCD Vertical Display Height Register 0
- {0x0039,0x01}, // LCD Vertical Display Height Register 1
- {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
- {0x003B,0x0A}, // TFT FPFRAME Start Position Register
- {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
-
- {0x0041,0x00}, // LCD Miscellaneous Register
- {0x0042,0x00}, // LCD Display Start Address Register 0
- {0x0043,0x00}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
-
-#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
- {0x0004,0x07}, // GPIO[0:7] direction
- {0x0005,0x00}, // GPIO[8:12] direction
- {0x0008,0x00}, // GPIO[0:7] data
- {0x0009,0x00}, // GPIO[8:12] data
- {0x0008,0x04}, // LCD panel Vcc on
- {0x0008,0x05}, // LCD panel reset
- {0x0010,0x01}, // Memory Clock Configuration Register
- {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
- {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
- {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz)
- {0x001E,0x00}, // CPU To Memory Wait State Select Register
- {0x0020,0x80}, // Memory Configuration Register
- {0x0021,0x03}, // DRAM Refresh Rate Register
- {0x002A,0x00}, // DRAM Timings Control Register 0
- {0x002B,0x01}, // DRAM Timings Control Register 1
- {0x0030,0x25}, // Panel Type Register
- {0x0031,0x00}, // MOD Rate Register
- {0x0032,0x1d}, // LCD Horizontal Display Width Register
- {0x0034,0x05}, // LCD Horizontal Non-Display Period Register
- {0x0035,0x01}, // TFT FPLINE Start Position Register
- {0x0036,0x01}, // TFT FPLINE Pulse Width Register
- {0x0038,0x3F}, // LCD Vertical Display Height Register 0
- {0x0039,0x01}, // LCD Vertical Display Height Register 1
- {0x003A,0x0b}, // LCD Vertical Non-Display Period Register
- {0x003B,0x07}, // TFT FPFRAME Start Position Register
- {0x003C,0x02}, // TFT FPFRAME Pulse Width Register
-
- {0x0041,0x00}, // LCD Miscellaneous Register
-#if (SWIVEL_VIEW == 0)
- {0x0042,0x00}, // LCD Display Start Address Register 0
- {0x0043,0x00}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
-
-#elif (SWIVEL_VIEW == 1)
- // 1024 - W(320) = 0x2C0
- {0x0042,0xC0}, // LCD Display Start Address Register 0
- {0x0043,0x02}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
- // 1024
- {0x0046,0x00}, // LCD Memory Address Offset Register 0
- {0x0047,0x02}, // LCD Memory Address Offset Register 1
-#else
-#error unsupported SWIVEL_VIEW mode
-#endif
-#else
-#error no platform configuration
-#endif /* CONFIG_PLAT_XXX */
-
- {0x0048,0x00}, // LCD Pixel Panning Register
- {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
- {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
- {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
- {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
- {0x0053,0x01}, // CRT/TV HRTC Start Position Register
- {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
- {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
- {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
- {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
- {0x0059,0x09}, // CRT/TV VRTC Start Position Register
- {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
- {0x005B,0x10}, // TV Output Control Register
-
- {0x0062,0x00}, // CRT/TV Display Start Address Register 0
- {0x0063,0x00}, // CRT/TV Display Start Address Register 1
- {0x0064,0x00}, // CRT/TV Display Start Address Register 2
-
- {0x0068,0x00}, // CRT/TV Pixel Panning Register
- {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
- {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
- {0x0070,0x00}, // LCD Ink/Cursor Control Register
- {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
- {0x0072,0x00}, // LCD Cursor X Position Register 0
- {0x0073,0x00}, // LCD Cursor X Position Register 1
- {0x0074,0x00}, // LCD Cursor Y Position Register 0
- {0x0075,0x00}, // LCD Cursor Y Position Register 1
- {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
- {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
- {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
- {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
- {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
- {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
- {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
- {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
- {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
- {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
- {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
- {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
- {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
- {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
- {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
- {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
- {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
- {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
- {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
- {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
- {0x0100,0x00}, // BitBlt Control Register 0
- {0x0101,0x00}, // BitBlt Control Register 1
- {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
- {0x0103,0x00}, // BitBlt Operation Register
- {0x0104,0x00}, // BitBlt Source Start Address Register 0
- {0x0105,0x00}, // BitBlt Source Start Address Register 1
- {0x0106,0x00}, // BitBlt Source Start Address Register 2
- {0x0108,0x00}, // BitBlt Destination Start Address Register 0
- {0x0109,0x00}, // BitBlt Destination Start Address Register 1
- {0x010A,0x00}, // BitBlt Destination Start Address Register 2
- {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
- {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
- {0x0110,0x00}, // BitBlt Width Register 0
- {0x0111,0x00}, // BitBlt Width Register 1
- {0x0112,0x00}, // BitBlt Height Register 0
- {0x0113,0x00}, // BitBlt Height Register 1
- {0x0114,0x00}, // BitBlt Background Color Register 0
- {0x0115,0x00}, // BitBlt Background Color Register 1
- {0x0118,0x00}, // BitBlt Foreground Color Register 0
- {0x0119,0x00}, // BitBlt Foreground Color Register 1
- {0x01E0,0x00}, // Look-Up Table Mode Register
- {0x01E2,0x00}, // Look-Up Table Address Register
- {0x01F0,0x10}, // Power Save Configuration Register
- {0x01F1,0x00}, // Power Save Status Register
- {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
-#if (SWIVEL_VIEW == 0)
- {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
-#elif (SWIVEL_VIEW == 1)
- {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
-#else
-#error unsupported SWIVEL_VIEW mode
-#endif /* SWIVEL_VIEW */
-
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
- {0x0008,0x07}, // LCD panel Vdd & Vg on
-#endif
-
- {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
-#if defined(CONFIG_PLAT_MAPPI)
- {0x0046,0x80}, // LCD Memory Address Offset Register 0
- {0x0047,0x02}, // LCD Memory Address Offset Register 1
-#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
- {0x0046,0xf0}, // LCD Memory Address Offset Register 0
- {0x0047,0x00}, // LCD Memory Address Offset Register 1
-#endif
- {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
- {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo
- {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
-};
diff --git a/arch/m32r/include/asm/segment.h b/arch/m32r/include/asm/segment.h
deleted file mode 100644
index 4095f14728e5..000000000000
--- a/arch/m32r/include/asm/segment.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SEGMENT_H
-#define _ASM_M32R_SEGMENT_H
-
-#define __KERNEL_CS 0x10
-#define __KERNEL_DS 0x18
-
-#define __USER_CS 0x23
-#define __USER_DS 0x2B
-
-#endif /* _ASM_M32R_SEGMENT_H */
diff --git a/arch/m32r/include/asm/serial.h b/arch/m32r/include/asm/serial.h
deleted file mode 100644
index b1375c841b4d..000000000000
--- a/arch/m32r/include/asm/serial.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SERIAL_H
-#define _ASM_M32R_SERIAL_H
-
-/* include/asm-m32r/serial.h */
-
-
-#define BASE_BAUD 115200
-
-#endif /* _ASM_M32R_SERIAL_H */
diff --git a/arch/m32r/include/asm/setup.h b/arch/m32r/include/asm/setup.h
deleted file mode 100644
index 71b4d6514078..000000000000
--- a/arch/m32r/include/asm/setup.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SETUP_H
-#define _ASM_M32R_SETUP_H
-
-#include <uapi/asm/setup.h>
-
-
-#define PARAM ((unsigned char *)empty_zero_page)
-
-#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
-#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
-#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
-#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
-#define INITRD_START (*(unsigned long *) (PARAM+0x010))
-#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
-
-#define M32R_CPUCLK (*(unsigned long *) (PARAM+0x018))
-#define M32R_BUSCLK (*(unsigned long *) (PARAM+0x01c))
-#define M32R_TIMER_DIVIDE (*(unsigned long *) (PARAM+0x020))
-
-#define COMMAND_LINE ((char *) (PARAM+0x100))
-
-#define SCREEN_INFO (*(struct screen_info *) (PARAM+0x200))
-
-#define RAMDISK_IMAGE_START_MASK (0x07FF)
-#define RAMDISK_PROMPT_FLAG (0x8000)
-#define RAMDISK_LOAD_FLAG (0x4000)
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-#endif /* _ASM_M32R_SETUP_H */
diff --git a/arch/m32r/include/asm/shmparam.h b/arch/m32r/include/asm/shmparam.h
deleted file mode 100644
index 1af73d92c96d..000000000000
--- a/arch/m32r/include/asm/shmparam.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SHMPARAM_H
-#define _ASM_M32R_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_M32R_SHMPARAM_H */
diff --git a/arch/m32r/include/asm/signal.h b/arch/m32r/include/asm/signal.h
deleted file mode 100644
index 8bf57950d21e..000000000000
--- a/arch/m32r/include/asm/signal.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SIGNAL_H
-#define _ASM_M32R_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-/* Most things should be clean enough to redefine this at will, if care
- is taken to make libc match. */
-
-#define _NSIG 64
-#define _NSIG_BPW 32
-#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t; /* at least 32 bits */
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#define __ARCH_HAS_SA_RESTORER
-#include <asm/sigcontext.h>
-
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#endif /* _ASM_M32R_SIGNAL_H */
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h
deleted file mode 100644
index 763f22700ce6..000000000000
--- a/arch/m32r/include/asm/smp.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SMP_H
-#define _ASM_M32R_SMP_H
-
-#ifdef CONFIG_SMP
-#ifndef __ASSEMBLY__
-
-#include <linux/cpumask.h>
-#include <linux/spinlock.h>
-#include <linux/threads.h>
-#include <asm/m32r.h>
-
-#define PHYSID_ARRAY_SIZE 1
-
-struct physid_mask
-{
- unsigned long mask[PHYSID_ARRAY_SIZE];
-};
-
-typedef struct physid_mask physid_mask_t;
-
-#define physid_set(physid, map) set_bit(physid, (map).mask)
-#define physid_clear(physid, map) clear_bit(physid, (map).mask)
-#define physid_isset(physid, map) test_bit(physid, (map).mask)
-#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
-
-#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
-#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
-#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
-#define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS)
-#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
-#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
-#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
-#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
-#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
-#define physids_coerce(map) ((map).mask[0])
-
-#define physids_promote(physids) \
- ({ \
- physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
- __physid_mask.mask[0] = physids; \
- __physid_mask; \
- })
-
-#define physid_mask_of_physid(physid) \
- ({ \
- physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
- physid_set(physid, __physid_mask); \
- __physid_mask; \
- })
-
-#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
-#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
-
-extern physid_mask_t phys_cpu_present_map;
-
-/*
- * Some lowlevel functions might want to know about
- * the real CPU ID <-> CPU # mapping.
- */
-extern volatile int cpu_2_physid[NR_CPUS];
-#define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id]
-
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-extern cpumask_t cpu_callout_map;
-
-static __inline__ int hard_smp_processor_id(void)
-{
- return (int)*(volatile long *)M32R_CPUID_PORTL;
-}
-
-static __inline__ int cpu_logical_map(int cpu)
-{
- return cpu;
-}
-
-static __inline__ int cpu_number_map(int cpu)
-{
- return cpu;
-}
-
-extern void smp_send_timer(void);
-extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int);
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#endif /* not __ASSEMBLY__ */
-
-#define NO_PROC_ID (0xff) /* No processor magic marker */
-
-/*
- * M32R-mp IPI
- */
-#define RESCHEDULE_IPI (M32R_IRQ_IPI0-M32R_IRQ_IPI0)
-#define INVALIDATE_TLB_IPI (M32R_IRQ_IPI1-M32R_IRQ_IPI0)
-#define CALL_FUNCTION_IPI (M32R_IRQ_IPI2-M32R_IRQ_IPI0)
-#define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
-#define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
-#define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
-#define CALL_FUNC_SINGLE_IPI (M32R_IRQ_IPI6-M32R_IRQ_IPI0)
-
-#define IPI_SHIFT (0)
-#define NR_IPIS (8)
-
-#else /* CONFIG_SMP */
-
-#define hard_smp_processor_id() 0
-
-#endif /* CONFIG_SMP */
-
-#endif /* _ASM_M32R_SMP_H */
diff --git a/arch/m32r/include/asm/spinlock.h b/arch/m32r/include/asm/spinlock.h
deleted file mode 100644
index 0189f410f8f5..000000000000
--- a/arch/m32r/include/asm/spinlock.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SPINLOCK_H
-#define _ASM_M32R_SPINLOCK_H
-
-/*
- * linux/include/asm-m32r/spinlock.h
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/compiler.h>
-#include <linux/atomic.h>
-#include <asm/dcache_clear.h>
-#include <asm/page.h>
-#include <asm/barrier.h>
-#include <asm/processor.h>
-
-/*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
- *
- * (the type definitions are in asm/spinlock_types.h)
- *
- * Simple spin lock operations. There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * We make no fairness assumptions. They have a cost.
- */
-
-#define arch_spin_is_locked(x) (*(volatile int *)(&(x)->slock) <= 0)
-
-/**
- * arch_spin_trylock - Try spin lock and return a result
- * @lock: Pointer to the lock variable
- *
- * arch_spin_trylock() tries to get the lock and returns a result.
- * On the m32r, the result value is 1 (= Success) or 0 (= Failure).
- */
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int oldval;
- unsigned long tmp1, tmp2;
-
- /*
- * lock->slock : =1 : unlock
- * : <=0 : lock
- * {
- * oldval = lock->slock; <--+ need atomic operation
- * lock->slock = 0; <--+
- * }
- */
- __asm__ __volatile__ (
- "# arch_spin_trylock \n\t"
- "ldi %1, #0; \n\t"
- "mvfc %2, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%3")
- "lock %0, @%3; \n\t"
- "unlock %1, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- : "=&r" (oldval), "=&r" (tmp1), "=&r" (tmp2)
- : "r" (&lock->slock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-
- return (oldval > 0);
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- unsigned long tmp0, tmp1;
-
- /*
- * lock->slock : =1 : unlock
- * : <=0 : lock
- *
- * for ( ; ; ) {
- * lock->slock -= 1; <-- need atomic operation
- * if (lock->slock == 0) break;
- * for ( ; lock->slock <= 0 ; );
- * }
- */
- __asm__ __volatile__ (
- "# arch_spin_lock \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "mvfc %1, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #-1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- "bltz %0, 2f; \n\t"
- LOCK_SECTION_START(".balign 4 \n\t")
- ".fillinsn \n"
- "2: \n\t"
- "ld %0, @%2; \n\t"
- "bgtz %0, 1b; \n\t"
- "bra 2b; \n\t"
- LOCK_SECTION_END
- : "=&r" (tmp0), "=&r" (tmp1)
- : "r" (&lock->slock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- mb();
- lock->slock = 1;
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- *
- * On x86, we implement read-write locks as a 32-bit counter
- * with the high bit (sign) being the "contended" bit.
- *
- * The inline assembly is non-obvious. Think about it.
- *
- * Changed to use the same technique as rw semaphores. See
- * semaphore.h for details. -ben
- */
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1;
-
- /*
- * rw->lock : >0 : unlock
- * : <=0 : lock
- *
- * for ( ; ; ) {
- * rw->lock -= 1; <-- need atomic operation
- * if (rw->lock >= 0) break;
- * rw->lock += 1; <-- need atomic operation
- * for ( ; rw->lock <= 0 ; );
- * }
- */
- __asm__ __volatile__ (
- "# read_lock \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "mvfc %1, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #-1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- "bltz %0, 2f; \n\t"
- LOCK_SECTION_START(".balign 4 \n\t")
- ".fillinsn \n"
- "2: \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- ".fillinsn \n"
- "3: \n\t"
- "ld %0, @%2; \n\t"
- "bgtz %0, 1b; \n\t"
- "bra 3b; \n\t"
- LOCK_SECTION_END
- : "=&r" (tmp0), "=&r" (tmp1)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1, tmp2;
-
- /*
- * rw->lock : =RW_LOCK_BIAS_STR : unlock
- * : !=RW_LOCK_BIAS_STR : lock
- *
- * for ( ; ; ) {
- * rw->lock -= RW_LOCK_BIAS_STR; <-- need atomic operation
- * if (rw->lock == 0) break;
- * rw->lock += RW_LOCK_BIAS_STR; <-- need atomic operation
- * for ( ; rw->lock != RW_LOCK_BIAS_STR ; ) ;
- * }
- */
- __asm__ __volatile__ (
- "# write_lock \n\t"
- "seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
- "or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "mvfc %2, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r7", "%3")
- "lock %0, @%3; \n\t"
- "sub %0, %1; \n\t"
- "unlock %0, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- "bnez %0, 2f; \n\t"
- LOCK_SECTION_START(".balign 4 \n\t")
- ".fillinsn \n"
- "2: \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r7", "%3")
- "lock %0, @%3; \n\t"
- "add %0, %1; \n\t"
- "unlock %0, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- ".fillinsn \n"
- "3: \n\t"
- "ld %0, @%3; \n\t"
- "beq %0, %1, 1b; \n\t"
- "bra 3b; \n\t"
- LOCK_SECTION_END
- : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r7"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1;
-
- __asm__ __volatile__ (
- "# read_unlock \n\t"
- "mvfc %1, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- : "=&r" (tmp0), "=&r" (tmp1)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1, tmp2;
-
- __asm__ __volatile__ (
- "# write_unlock \n\t"
- "seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
- "or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
- "mvfc %2, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r7", "%3")
- "lock %0, @%3; \n\t"
- "add %0, %1; \n\t"
- "unlock %0, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r7"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- atomic_t *count = (atomic_t*)lock;
- if (atomic_dec_return(count) >= 0)
- return 1;
- atomic_inc(count);
- return 0;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- atomic_t *count = (atomic_t *)lock;
- if (atomic_sub_and_test(RW_LOCK_BIAS, count))
- return 1;
- atomic_add(RW_LOCK_BIAS, count);
- return 0;
-}
-
-#endif /* _ASM_M32R_SPINLOCK_H */
diff --git a/arch/m32r/include/asm/spinlock_types.h b/arch/m32r/include/asm/spinlock_types.h
deleted file mode 100644
index bb0d17b64198..000000000000
--- a/arch/m32r/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SPINLOCK_TYPES_H
-#define _ASM_M32R_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
- volatile int slock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 1 }
-
-typedef struct {
- volatile int lock;
-} arch_rwlock_t;
-
-#define RW_LOCK_BIAS 0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif /* _ASM_M32R_SPINLOCK_TYPES_H */
diff --git a/arch/m32r/include/asm/string.h b/arch/m32r/include/asm/string.h
deleted file mode 100644
index a9ea3b6c3e5a..000000000000
--- a/arch/m32r/include/asm/string.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_STRING_H
-#define _ASM_M32R_STRING_H
-
-#define __HAVE_ARCH_STRLEN
-extern size_t strlen(const char * s);
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *__s, int __c, size_t __count);
-
-#endif /* _ASM_M32R_STRING_H */
diff --git a/arch/m32r/include/asm/switch_to.h b/arch/m32r/include/asm/switch_to.h
deleted file mode 100644
index 4b262f7a8fe9..000000000000
--- a/arch/m32r/include/asm/switch_to.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_SWITCH_TO_H
-#define _ASM_M32R_SWITCH_TO_H
-
-/*
- * switch_to(prev, next) should switch from task `prev' to `next'
- * `prev' will never be the same as `next'.
- *
- * `next' and `prev' should be struct task_struct, but it isn't always defined
- */
-
-#if defined(CONFIG_FRAME_POINTER) || \
- !defined(CONFIG_SCHED_OMIT_FRAME_POINTER)
-#define M32R_PUSH_FP " push fp\n"
-#define M32R_POP_FP " pop fp\n"
-#else
-#define M32R_PUSH_FP ""
-#define M32R_POP_FP ""
-#endif
-
-#define switch_to(prev, next, last) do { \
- __asm__ __volatile__ ( \
- " seth lr, #high(1f) \n" \
- " or3 lr, lr, #low(1f) \n" \
- " st lr, @%4 ; store old LR \n" \
- " ld lr, @%5 ; load new LR \n" \
- M32R_PUSH_FP \
- " st sp, @%2 ; store old SP \n" \
- " ld sp, @%3 ; load new SP \n" \
- " push %1 ; store `prev' on new stack \n" \
- " jmp lr \n" \
- " .fillinsn \n" \
- "1: \n" \
- " pop %0 ; restore `__last' from new stack \n" \
- M32R_POP_FP \
- : "=r" (last) \
- : "0" (prev), \
- "r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
- "r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
- : "memory", "lr" \
- ); \
-} while(0)
-
-#endif /* _ASM_M32R_SWITCH_TO_H */
diff --git a/arch/m32r/include/asm/syscall.h b/arch/m32r/include/asm/syscall.h
deleted file mode 100644
index 22c8516d3c18..000000000000
--- a/arch/m32r/include/asm/syscall.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SYSCALL_H
-#define _ASM_M32R_SYSCALL_H
-
-/* Definitions for the system call vector. */
-#define SYSCALL_VECTOR "2"
-#define SYSCALL_VECTOR_ADDRESS "0xa0"
-
-#endif /* _ASM_M32R_SYSCALL_H */
diff --git a/arch/m32r/include/asm/termios.h b/arch/m32r/include/asm/termios.h
deleted file mode 100644
index 40274b89cea5..000000000000
--- a/arch/m32r/include/asm/termios.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32R_TERMIOS_H
-#define _M32R_TERMIOS_H
-
-#include <linux/module.h>
-#include <uapi/asm/termios.h>
-
-/* intr=^C quit=^\ erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
- unsigned short __tmp; \
- get_user(__tmp,&(termio)->x); \
- *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
- copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- put_user((termios)->c_iflag, &(termio)->c_iflag); \
- put_user((termios)->c_oflag, &(termio)->c_oflag); \
- put_user((termios)->c_cflag, &(termio)->c_cflag); \
- put_user((termios)->c_lflag, &(termio)->c_lflag); \
- put_user((termios)->c_line, &(termio)->c_line); \
- copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* _M32R_TERMIOS_H */
diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h
deleted file mode 100644
index ba00f1032587..000000000000
--- a/arch/m32r/include/asm/thread_info.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_THREAD_INFO_H
-#define _ASM_M32R_THREAD_INFO_H
-
-/* thread_info.h: m32r low-level thread information
- *
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#endif
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long status; /* thread-synchronous flags */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space:
- 0-0xBFFFFFFF for user-thread
- 0-0xFFFFFFFF for kernel-thread
- */
-
- __u8 supervisor_stack[0];
-};
-
-#endif /* !__ASSEMBLY__ */
-
-#define THREAD_SIZE (PAGE_SIZE << 1)
-#define THREAD_SIZE_ORDER 1
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
-
- __asm__ __volatile__ (
- "ldi %0, #%1 \n\t"
- "and %0, sp \n\t"
- : "=r" (ti) : "i" (~(THREAD_SIZE - 1))
- );
-
- return ti;
-}
-
-#define TI_FLAG_FAULT_CODE_SHIFT 28
-
-static inline void set_thread_fault_code(unsigned int val)
-{
- struct thread_info *ti = current_thread_info();
- ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT)))
- | (val << TI_FLAG_FAULT_CODE_SHIFT);
-}
-
-static inline unsigned int get_thread_fault_code(void)
-{
- struct thread_info *ti = current_thread_info();
- return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT;
-}
-
-#endif
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */
-#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
-#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal() */
-#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
-#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_USEDFPU (1<<TIF_USEDFPU)
-
-#define _TIF_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
-#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_SYSCALL_TRACE)
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- */
-#define TS_USEDFPU 0x0001 /* FPU was used by this task this quantum (SMP) */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_THREAD_INFO_H */
diff --git a/arch/m32r/include/asm/timex.h b/arch/m32r/include/asm/timex.h
deleted file mode 100644
index a4f9f852d9e6..000000000000
--- a/arch/m32r/include/asm/timex.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TIMEX_H
-#define _ASM_M32R_TIMEX_H
-
-/*
- * linux/include/asm-m32r/timex.h
- *
- * m32r architecture timex specifications
- */
-
-#define CLOCK_TICK_RATE (CONFIG_BUS_CLOCK / CONFIG_TIMER_DIVIDE)
-#define CLOCK_TICK_FACTOR 20 /* Factor of both 1000000 and CLOCK_TICK_RATE */
-
-#ifdef __KERNEL__
-/*
- * Standard way to access the cycle counter.
- * Currently only used on SMP.
- */
-
-typedef unsigned long long cycles_t;
-
-static __inline__ cycles_t get_cycles (void)
-{
- return 0;
-}
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_TIMEX_H */
diff --git a/arch/m32r/include/asm/tlb.h b/arch/m32r/include/asm/tlb.h
deleted file mode 100644
index 3576f88b6ea4..000000000000
--- a/arch/m32r/include/asm/tlb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32R_TLB_H
-#define _M32R_TLB_H
-
-/*
- * x86 doesn't need any special per-pte or
- * per-vma handling..
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _M32R_TLB_H */
diff --git a/arch/m32r/include/asm/tlbflush.h b/arch/m32r/include/asm/tlbflush.h
deleted file mode 100644
index f6c7237316d0..000000000000
--- a/arch/m32r/include/asm/tlbflush.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TLBFLUSH_H
-#define _ASM_M32R_TLBFLUSH_H
-
-#include <asm/m32r.h>
-
-/*
- * TLB flushing:
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(vma, start, end) flushes a range of pages
- * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- */
-
-extern void local_flush_tlb_all(void);
-extern void local_flush_tlb_mm(struct mm_struct *);
-extern void local_flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void local_flush_tlb_range(struct vm_area_struct *, unsigned long,
- unsigned long);
-
-#ifndef CONFIG_SMP
-#ifdef CONFIG_MMU
-#define flush_tlb_all() local_flush_tlb_all()
-#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
-#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
-#define flush_tlb_range(vma, start, end) \
- local_flush_tlb_range(vma, start, end)
-#define flush_tlb_kernel_range(start, end) local_flush_tlb_all()
-#else /* CONFIG_MMU */
-#define flush_tlb_all() do { } while (0)
-#define flush_tlb_mm(mm) do { } while (0)
-#define flush_tlb_page(vma, vmaddr) do { } while (0)
-#define flush_tlb_range(vma, start, end) do { } while (0)
-#endif /* CONFIG_MMU */
-#else /* CONFIG_SMP */
-extern void smp_flush_tlb_all(void);
-extern void smp_flush_tlb_mm(struct mm_struct *);
-extern void smp_flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void smp_flush_tlb_range(struct vm_area_struct *, unsigned long,
- unsigned long);
-
-#define flush_tlb_all() smp_flush_tlb_all()
-#define flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
-#define flush_tlb_page(vma, page) smp_flush_tlb_page(vma, page)
-#define flush_tlb_range(vma, start, end) \
- smp_flush_tlb_range(vma, start, end)
-#define flush_tlb_kernel_range(start, end) smp_flush_tlb_all()
-#endif /* CONFIG_SMP */
-
-static __inline__ void __flush_tlb_page(unsigned long page)
-{
- unsigned int tmpreg0, tmpreg1, tmpreg2;
-
- __asm__ __volatile__ (
- "seth %0, #high(%4) \n\t"
- "st %3, @(%5, %0) \n\t"
- "ldi %1, #1 \n\t"
- "st %1, @(%6, %0) \n\t"
- "add3 %1, %0, %7 \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "ld %2, @(%6, %0) \n\t"
- "bnez %2, 1b \n\t"
- "ld %0, @%1+ \n\t"
- "ld %1, @%1 \n\t"
- "st %2, @+%0 \n\t"
- "st %2, @+%1 \n\t"
- : "=&r" (tmpreg0), "=&r" (tmpreg1), "=&r" (tmpreg2)
- : "r" (page), "i" (MMU_REG_BASE), "i" (MSVA_offset),
- "i" (MTOP_offset), "i" (MIDXI_offset)
- : "memory"
- );
-}
-
-static __inline__ void __flush_tlb_all(void)
-{
- unsigned int tmpreg0, tmpreg1;
-
- __asm__ __volatile__ (
- "seth %0, #high(%2) \n\t"
- "or3 %0, %0, #low(%2) \n\t"
- "ldi %1, #0xc \n\t"
- "st %1, @%0 \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "ld %1, @%0 \n\t"
- "bnez %1, 1b \n\t"
- : "=&r" (tmpreg0), "=&r" (tmpreg1)
- : "i" (MTOP) : "memory"
- );
-}
-
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
-
-#endif /* _ASM_M32R_TLBFLUSH_H */
diff --git a/arch/m32r/include/asm/topology.h b/arch/m32r/include/asm/topology.h
deleted file mode 100644
index ee79404e8878..000000000000
--- a/arch/m32r/include/asm/topology.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TOPOLOGY_H
-#define _ASM_M32R_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_M32R_TOPOLOGY_H */
diff --git a/arch/m32r/include/asm/types.h b/arch/m32r/include/asm/types.h
deleted file mode 100644
index fce0bf60536c..000000000000
--- a/arch/m32r/include/asm/types.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TYPES_H
-#define _ASM_M32R_TYPES_H
-
-#include <uapi/asm/types.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-
-#define BITS_PER_LONG 32
-
-#endif /* _ASM_M32R_TYPES_H */
diff --git a/arch/m32r/include/asm/uaccess.h b/arch/m32r/include/asm/uaccess.h
deleted file mode 100644
index 9d89bc3d8181..000000000000
--- a/arch/m32r/include/asm/uaccess.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UACCESS_H
-#define _ASM_M32R_UACCESS_H
-
-/*
- * linux/include/asm-m32r/uaccess.h
- *
- * M32R version.
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-/*
- * User space memory access functions
- */
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <linux/prefetch.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-#ifdef CONFIG_MMU
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#else /* not CONFIG_MMU */
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define get_ds() (KERNEL_DS)
-
-static inline mm_segment_t get_fs(void)
-{
- return USER_DS;
-}
-
-static inline void set_fs(mm_segment_t s)
-{
-}
-
-#endif /* not CONFIG_MMU */
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#define __addr_ok(addr) \
- ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
-
-/*
- * Test whether a block of memory is a valid user space address.
- * Returns 0 if the range is valid, nonzero otherwise.
- *
- * This is equivalent to the following test:
- * (u33)addr + (u33)size >= (u33)current->addr_limit.seg
- *
- * This needs 33-bit arithmetic. We have a carry...
- */
-#define __range_ok(addr, size) ({ \
- unsigned long flag, roksum; \
- __chk_user_ptr(addr); \
- asm ( \
- " cmpu %1, %1 ; clear cbit\n" \
- " addx %1, %3 ; set cbit if overflow\n" \
- " subx %0, %0\n" \
- " cmpu %4, %1\n" \
- " subx %0, %5\n" \
- : "=&r" (flag), "=r" (roksum) \
- : "1" (addr), "r" ((int)(size)), \
- "r" (current_thread_info()->addr_limit.seg), "r" (0) \
- : "cbit" ); \
- flag; })
-
-/**
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
- * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- * to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-#ifdef CONFIG_MMU
-#define access_ok(type, addr, size) (likely(__range_ok(addr, size) == 0))
-#else
-static inline int access_ok(int type, const void *addr, unsigned long size)
-{
- unsigned long val = (unsigned long)addr;
-
- return ((val >= memory_start) && ((val + size) < memory_end));
-}
-#endif /* CONFIG_MMU */
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the uglyness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- */
-
-/* Careful: we have to cast the result to the type of the pointer for sign
- reasons */
-/**
- * get_user: - Get a simple variable from user space.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define get_user(x, ptr) \
- __get_user_check((x), (ptr), sizeof(*(ptr)))
-
-/**
- * put_user: - Write a simple value into user space.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define put_user(x, ptr) \
- __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-/**
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define __get_user(x, ptr) \
- __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- long __gu_err = 0; \
- unsigned long __gu_val = 0; \
- might_fault(); \
- __get_user_size(__gu_val, (ptr), (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- long __gu_err = -EFAULT; \
- unsigned long __gu_val = 0; \
- const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
- might_fault(); \
- if (access_ok(VERIFY_READ, __gu_addr, size)) \
- __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-extern long __get_user_bad(void);
-
-#define __get_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- __chk_user_ptr(ptr); \
- switch (size) { \
- case 1: __get_user_asm(x, ptr, retval, "ub"); break; \
- case 2: __get_user_asm(x, ptr, retval, "uh"); break; \
- case 4: __get_user_asm(x, ptr, retval, ""); break; \
- default: (x) = __get_user_bad(); \
- } \
-} while (0)
-
-#define __get_user_asm(x, addr, err, itype) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: ld"itype" %1,@%2\n" \
- " .fillinsn\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "3: ldi %0,%3\n" \
- " seth r14,#high(2b)\n" \
- " or3 r14,r14,#low(2b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,3b\n" \
- ".previous" \
- : "=&r" (err), "=&r" (x) \
- : "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-
-/**
- * __put_user: - Write a simple value into user space, with less checking.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define __put_user(x, ptr) \
- __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-
-#define __put_user_nocheck(x, ptr, size) \
-({ \
- long __pu_err; \
- might_fault(); \
- __put_user_size((x), (ptr), (size), __pu_err); \
- __pu_err; \
-})
-
-
-#define __put_user_check(x, ptr, size) \
-({ \
- long __pu_err = -EFAULT; \
- __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
- might_fault(); \
- if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
- __put_user_size((x), __pu_addr, (size), __pu_err); \
- __pu_err; \
-})
-
-#if defined(__LITTLE_ENDIAN__)
-#define __put_user_u64(x, addr, err) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: st %L1,@%2\n" \
- " .fillinsn\n" \
- "2: st %H1,@(4,%2)\n" \
- " .fillinsn\n" \
- "3:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "4: ldi %0,%3\n" \
- " seth r14,#high(3b)\n" \
- " or3 r14,r14,#low(3b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,4b\n" \
- " .long 2b,4b\n" \
- ".previous" \
- : "=&r" (err) \
- : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-
-#elif defined(__BIG_ENDIAN__)
-#define __put_user_u64(x, addr, err) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: st %H1,@%2\n" \
- " .fillinsn\n" \
- "2: st %L1,@(4,%2)\n" \
- " .fillinsn\n" \
- "3:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "4: ldi %0,%3\n" \
- " seth r14,#high(3b)\n" \
- " or3 r14,r14,#low(3b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,4b\n" \
- " .long 2b,4b\n" \
- ".previous" \
- : "=&r" (err) \
- : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-#else
-#error no endian defined
-#endif
-
-extern void __put_user_bad(void);
-
-#define __put_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- __chk_user_ptr(ptr); \
- switch (size) { \
- case 1: __put_user_asm(x, ptr, retval, "b"); break; \
- case 2: __put_user_asm(x, ptr, retval, "h"); break; \
- case 4: __put_user_asm(x, ptr, retval, ""); break; \
- case 8: __put_user_u64((__typeof__(*ptr))(x), ptr, retval); break;\
- default: __put_user_bad(); \
- } \
-} while (0)
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-#define __put_user_asm(x, addr, err, itype) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: st"itype" %1,@%2\n" \
- " .fillinsn\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "3: ldi %0,%3\n" \
- " seth r14,#high(2b)\n" \
- " or3 r14,r14,#low(2b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,3b\n" \
- ".previous" \
- : "=&r" (err) \
- : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-
-/*
- * Here we special-case 1, 2 and 4-byte copy_*_user invocations. On a fault
- * we return the initial request size (1, 2 or 4), as copy_*_user should do.
- * If a store crosses a page boundary and gets a fault, the m32r will not write
- * anything, so this is accurate.
- */
-
-/*
- * Copy To/From Userspace
- */
-
-/* Generic arbitrary sized copy. */
-/* Return the number of bytes NOT copied. */
-#define __copy_user(to, from, size) \
-do { \
- unsigned long __dst, __src, __c; \
- __asm__ __volatile__ ( \
- " mv r14, %0\n" \
- " or r14, %1\n" \
- " beq %0, %1, 9f\n" \
- " beqz %2, 9f\n" \
- " and3 r14, r14, #3\n" \
- " bnez r14, 2f\n" \
- " and3 %2, %2, #3\n" \
- " beqz %3, 2f\n" \
- " addi %0, #-4 ; word_copy \n" \
- " .fillinsn\n" \
- "0: ld r14, @%1+\n" \
- " addi %3, #-1\n" \
- " .fillinsn\n" \
- "1: st r14, @+%0\n" \
- " bnez %3, 0b\n" \
- " beqz %2, 9f\n" \
- " addi %0, #4\n" \
- " .fillinsn\n" \
- "2: ldb r14, @%1 ; byte_copy \n" \
- " .fillinsn\n" \
- "3: stb r14, @%0\n" \
- " addi %1, #1\n" \
- " addi %2, #-1\n" \
- " addi %0, #1\n" \
- " bnez %2, 2b\n" \
- " .fillinsn\n" \
- "9:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "5: addi %3, #1\n" \
- " addi %1, #-4\n" \
- " .fillinsn\n" \
- "6: slli %3, #2\n" \
- " add %2, %3\n" \
- " addi %0, #4\n" \
- " .fillinsn\n" \
- "7: seth r14, #high(9b)\n" \
- " or3 r14, r14, #low(9b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,6b\n" \
- " .long 1b,5b\n" \
- " .long 2b,9b\n" \
- " .long 3b,9b\n" \
- ".previous\n" \
- : "=&r" (__dst), "=&r" (__src), "=&r" (size), \
- "=&r" (__c) \
- : "0" (to), "1" (from), "2" (size), "3" (size / 4) \
- : "r14", "memory"); \
-} while (0)
-
-/* We let the __ versions of copy_from/to_user inline, because they're often
- * used in fast paths and have only a small space overhead.
- */
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- prefetchw(to);
- __copy_user(to, from, n);
- return n;
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- prefetch(from);
- __copy_user(to, from, n);
- return n;
-}
-
-long __must_check strncpy_from_user(char *dst, const char __user *src,
- long count);
-
-/**
- * __clear_user: - Zero a block of memory in user space, with less checking.
- * @to: Destination address, in user space.
- * @n: Number of bytes to zero.
- *
- * Zero a block of memory in user space. Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-unsigned long __clear_user(void __user *mem, unsigned long len);
-
-/**
- * clear_user: - Zero a block of memory in user space.
- * @to: Destination address, in user space.
- * @n: Number of bytes to zero.
- *
- * Zero a block of memory in user space. Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-unsigned long clear_user(void __user *mem, unsigned long len);
-
-long strnlen_user(const char __user *str, long n);
-
-#endif /* _ASM_M32R_UACCESS_H */
diff --git a/arch/m32r/include/asm/ucontext.h b/arch/m32r/include/asm/ucontext.h
deleted file mode 100644
index 5f9de3736624..000000000000
--- a/arch/m32r/include/asm/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UCONTEXT_H
-#define _ASM_M32R_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif /* _ASM_M32R_UCONTEXT_H */
diff --git a/arch/m32r/include/asm/unaligned.h b/arch/m32r/include/asm/unaligned.h
deleted file mode 100644
index 5981361672f9..000000000000
--- a/arch/m32r/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UNALIGNED_H
-#define _ASM_M32R_UNALIGNED_H
-
-#if defined(__LITTLE_ENDIAN__)
-# include <linux/unaligned/le_memmove.h>
-# include <linux/unaligned/be_byteshift.h>
-# include <linux/unaligned/generic.h>
-# define get_unaligned __get_unaligned_le
-# define put_unaligned __put_unaligned_le
-#else
-# include <linux/unaligned/be_memmove.h>
-# include <linux/unaligned/le_byteshift.h>
-# include <linux/unaligned/generic.h>
-# define get_unaligned __get_unaligned_be
-# define put_unaligned __put_unaligned_be
-#endif
-
-#endif /* _ASM_M32R_UNALIGNED_H */
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
deleted file mode 100644
index dee4c196972e..000000000000
--- a/arch/m32r/include/asm/unistd.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UNISTD_H
-#define _ASM_M32R_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 326
-
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_CLONE
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-
-#define __IGNORE_lchown
-#define __IGNORE_setuid
-#define __IGNORE_getuid
-#define __IGNORE_setgid
-#define __IGNORE_getgid
-#define __IGNORE_geteuid
-#define __IGNORE_getegid
-#define __IGNORE_fcntl
-#define __IGNORE_setreuid
-#define __IGNORE_setregid
-#define __IGNORE_getrlimit
-#define __IGNORE_getgroups
-#define __IGNORE_setgroups
-#define __IGNORE_select
-#define __IGNORE_mmap
-#define __IGNORE_fchown
-#define __IGNORE_setfsuid
-#define __IGNORE_setfsgid
-#define __IGNORE_setresuid
-#define __IGNORE_getresuid
-#define __IGNORE_setresgid
-#define __IGNORE_getresgid
-#define __IGNORE_chown
-
-#endif /* _ASM_M32R_UNISTD_H */
diff --git a/arch/m32r/include/asm/user.h b/arch/m32r/include/asm/user.h
deleted file mode 100644
index 489b60d4aec2..000000000000
--- a/arch/m32r/include/asm/user.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_USER_H
-#define _ASM_M32R_USER_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd).
- *
- * The actual file contents are as follows:
- * UPAGE: 1 page consisting of a user struct that tells gdb
- * what is present in the file. Directly after this is a
- * copy of the task_struct, which is currently not used by gdb,
- * but it may come in handy at some point. All of the registers
- * are stored as part of the upage. The upage should always be
- * only one page.
- * DATA: The data area is stored. We use current->end_text to
- * current->brk to pick up all of the user variables, plus any memory
- * that may have been sbrk'ed. No attempt is made to determine if a
- * page is demand-zero or if a page is totally unused, we just cover
- * the entire range. All of the addresses are rounded in such a way
- * that an integral number of pages is written.
- * STACK: We need the stack information in order to get a meaningful
- * backtrace. We need to write the data from usp to
- * current->start_stack, so we round each of these off in order to be
- * able to write an integer number of pages.
- */
-
-struct user {
- struct pt_regs regs; /* entire machine state */
- size_t u_tsize; /* text size (pages) */
- size_t u_dsize; /* data size (pages) */
- size_t u_ssize; /* stack size (pages) */
- unsigned long start_code; /* text starting address */
- unsigned long start_data; /* data starting address */
- unsigned long start_stack; /* stack starting address */
- long int signal; /* signal causing core dump */
- unsigned long u_ar0; /* help gdb find registers */
- unsigned long magic; /* identifies a core file */
- char u_comm[32]; /* user command name */
-};
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_DATA_START_ADDR (u.start_data)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* _ASM_M32R_USER_H */
diff --git a/arch/m32r/include/asm/vga.h b/arch/m32r/include/asm/vga.h
deleted file mode 100644
index 783d5bf779c2..000000000000
--- a/arch/m32r/include/asm/vga.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_VGA_H
-#define _ASM_M32R_VGA_H
-
-/*
- * Access to VGA videoram
- *
- * (c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-/*
- * On the PC, we can just recalculate addresses and then
- * access the videoram directly without any black magic.
- */
-
-#define VGA_MAP_MEM(x,s) (unsigned long)phys_to_virt(x)
-
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-
-#endif /* _ASM_M32R_VGA_H */
diff --git a/arch/m32r/include/asm/xor.h b/arch/m32r/include/asm/xor.h
deleted file mode 100644
index a4d546752c77..000000000000
--- a/arch/m32r/include/asm/xor.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_XOR_H
-#define _ASM_M32R_XOR_H
-
-#include <asm-generic/xor.h>
-
-#endif /* _ASM_M32R_XOR_H */
diff --git a/arch/m32r/include/uapi/asm/Kbuild b/arch/m32r/include/uapi/asm/Kbuild
deleted file mode 100644
index c3df55aeefe7..000000000000
--- a/arch/m32r/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,7 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += bpf_perf_event.h
-generic-y += kvm_para.h
-generic-y += poll.h
-generic-y += siginfo.h
diff --git a/arch/m32r/include/uapi/asm/auxvec.h b/arch/m32r/include/uapi/asm/auxvec.h
deleted file mode 100644
index f76dcc860fae..000000000000
--- a/arch/m32r/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_M32R__AUXVEC_H
-#define _ASM_M32R__AUXVEC_H
-
-#endif /* _ASM_M32R__AUXVEC_H */
diff --git a/arch/m32r/include/uapi/asm/bitsperlong.h b/arch/m32r/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 76da34b10f59..000000000000
--- a/arch/m32r/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/m32r/include/uapi/asm/byteorder.h b/arch/m32r/include/uapi/asm/byteorder.h
deleted file mode 100644
index 9b4a8ba483cd..000000000000
--- a/arch/m32r/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_BYTEORDER_H
-#define _ASM_M32R_BYTEORDER_H
-
-#if defined(__LITTLE_ENDIAN__)
-# include <linux/byteorder/little_endian.h>
-#else
-# include <linux/byteorder/big_endian.h>
-#endif
-
-#endif /* _ASM_M32R_BYTEORDER_H */
diff --git a/arch/m32r/include/uapi/asm/errno.h b/arch/m32r/include/uapi/asm/errno.h
deleted file mode 100644
index ab38ef607882..000000000000
--- a/arch/m32r/include/uapi/asm/errno.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_ERRNO_H
-#define _ASM_M32R_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _ASM_M32R_ERRNO_H */
diff --git a/arch/m32r/include/uapi/asm/fcntl.h b/arch/m32r/include/uapi/asm/fcntl.h
deleted file mode 100644
index a77648c505d1..000000000000
--- a/arch/m32r/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/fcntl.h>
diff --git a/arch/m32r/include/uapi/asm/ioctl.h b/arch/m32r/include/uapi/asm/ioctl.h
deleted file mode 100644
index b809c4566e5f..000000000000
--- a/arch/m32r/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ioctl.h>
diff --git a/arch/m32r/include/uapi/asm/ioctls.h b/arch/m32r/include/uapi/asm/ioctls.h
deleted file mode 100644
index 31da4c3bab94..000000000000
--- a/arch/m32r/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ARCH_M32R_IOCTLS_H__
-#define __ARCH_M32R_IOCTLS_H__
-
-#include <asm-generic/ioctls.h>
-
-#endif /* __ARCH_M32R_IOCTLS_H__ */
diff --git a/arch/m32r/include/uapi/asm/ipcbuf.h b/arch/m32r/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 90d6445a14df..000000000000
--- a/arch/m32r/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/m32r/include/uapi/asm/mman.h b/arch/m32r/include/uapi/asm/mman.h
deleted file mode 100644
index 8eebf89f5ab1..000000000000
--- a/arch/m32r/include/uapi/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/mman.h>
diff --git a/arch/m32r/include/uapi/asm/msgbuf.h b/arch/m32r/include/uapi/asm/msgbuf.h
deleted file mode 100644
index 4386ff2735ba..000000000000
--- a/arch/m32r/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_MSGBUF_H
-#define _ASM_M32R_MSGBUF_H
-
-/*
- * The msqid64_ds structure for m32r architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
- struct ipc64_perm msg_perm;
- __kernel_time_t msg_stime; /* last msgsnd time */
- unsigned long __unused1;
- __kernel_time_t msg_rtime; /* last msgrcv time */
- unsigned long __unused2;
- __kernel_time_t msg_ctime; /* last change time */
- unsigned long __unused3;
- unsigned long msg_cbytes; /* current number of bytes on queue */
- unsigned long msg_qnum; /* number of messages in queue */
- unsigned long msg_qbytes; /* max number of bytes on queue */
- __kernel_pid_t msg_lspid; /* pid of last msgsnd */
- __kernel_pid_t msg_lrpid; /* last receive pid */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-#endif /* _ASM_M32R_MSGBUF_H */
diff --git a/arch/m32r/include/uapi/asm/param.h b/arch/m32r/include/uapi/asm/param.h
deleted file mode 100644
index 0bff6d6133f5..000000000000
--- a/arch/m32r/include/uapi/asm/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_PARAM_H
-#define _ASM_M32R_PARAM_H
-
-#include <asm-generic/param.h>
-
-#endif /* _ASM_M32R_PARAM_H */
-
diff --git a/arch/m32r/include/uapi/asm/posix_types.h b/arch/m32r/include/uapi/asm/posix_types.h
deleted file mode 100644
index 63316fcb1b57..000000000000
--- a/arch/m32r/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_POSIX_TYPES_H
-#define _ASM_M32R_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_M32R_POSIX_TYPES_H */
diff --git a/arch/m32r/include/uapi/asm/ptrace.h b/arch/m32r/include/uapi/asm/ptrace.h
deleted file mode 100644
index 99aec86cf5c0..000000000000
--- a/arch/m32r/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * linux/include/asm-m32r/ptrace.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * M32R version:
- * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _UAPI_ASM_M32R_PTRACE_H
-#define _UAPI_ASM_M32R_PTRACE_H
-
-
-/* 0 - 13 are integer registers (general purpose registers). */
-#define PT_R4 0
-#define PT_R5 1
-#define PT_R6 2
-#define PT_REGS 3
-#define PT_R0 4
-#define PT_R1 5
-#define PT_R2 6
-#define PT_R3 7
-#define PT_R7 8
-#define PT_R8 9
-#define PT_R9 10
-#define PT_R10 11
-#define PT_R11 12
-#define PT_R12 13
-#define PT_SYSCNR 14
-#define PT_R13 PT_FP
-#define PT_R14 PT_LR
-#define PT_R15 PT_SP
-
-/* processor status and miscellaneous context registers. */
-#define PT_ACC0H 15
-#define PT_ACC0L 16
-#define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */
-#define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */
-#define PT_PSW 19
-#define PT_BPC 20
-#define PT_BBPSW 21
-#define PT_BBPC 22
-#define PT_SPU 23
-#define PT_FP 24
-#define PT_LR 25
-#define PT_SPI 26
-#define PT_ORIGR0 27
-
-/* virtual pt_reg entry for gdb */
-#define PT_PC 30
-#define PT_CBR 31
-#define PT_EVB 32
-
-
-/* Control registers. */
-#define SPR_CR0 PT_PSW
-#define SPR_CR1 PT_CBR /* read only */
-#define SPR_CR2 PT_SPI
-#define SPR_CR3 PT_SPU
-#define SPR_CR4
-#define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */
-#define SPR_CR6 PT_BPC
-#define SPR_CR7
-#define SPR_CR8 PT_BBPSW
-#define SPR_CR9
-#define SPR_CR10
-#define SPR_CR11
-#define SPR_CR12
-#define SPR_CR13 PT_WR
-#define SPR_CR14 PT_BBPC
-#define SPR_CR15
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-struct pt_regs {
- /* Saved main processor registers. */
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- struct pt_regs *pt_regs;
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- long syscall_nr;
-
- /* Saved main processor status and miscellaneous context registers. */
- unsigned long acc0h;
- unsigned long acc0l;
- unsigned long acc1h; /* ISA_DSP_LEVEL2 only */
- unsigned long acc1l; /* ISA_DSP_LEVEL2 only */
- unsigned long psw;
- unsigned long bpc; /* saved PC for TRAP syscalls */
- unsigned long bbpsw;
- unsigned long bbpc;
- unsigned long spu; /* saved user stack */
- unsigned long fp;
- unsigned long lr; /* saved PC for JL syscalls */
- unsigned long spi; /* saved kernel stack */
- unsigned long orig_r0;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-
-#define PTRACE_OLDSETOPTIONS 21
-
-
-#endif /* _UAPI_ASM_M32R_PTRACE_H */
diff --git a/arch/m32r/include/uapi/asm/resource.h b/arch/m32r/include/uapi/asm/resource.h
deleted file mode 100644
index 3282f3c4a5ca..000000000000
--- a/arch/m32r/include/uapi/asm/resource.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_RESOURCE_H
-#define _ASM_M32R_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _ASM_M32R_RESOURCE_H */
diff --git a/arch/m32r/include/uapi/asm/sembuf.h b/arch/m32r/include/uapi/asm/sembuf.h
deleted file mode 100644
index de34664d8cd7..000000000000
--- a/arch/m32r/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SEMBUF_H
-#define _ASM_M32R_SEMBUF_H
-
-/*
- * The semid64_ds structure for m32r architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
- struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
- __kernel_time_t sem_otime; /* last semop time */
- unsigned long __unused1;
- __kernel_time_t sem_ctime; /* last change time */
- unsigned long __unused2;
- unsigned long sem_nsems; /* no. of semaphores in array */
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_M32R_SEMBUF_H */
diff --git a/arch/m32r/include/uapi/asm/setup.h b/arch/m32r/include/uapi/asm/setup.h
deleted file mode 100644
index d936a64bbafd..000000000000
--- a/arch/m32r/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_M32R_SETUP_H
-#define _UAPI_ASM_M32R_SETUP_H
-
-/*
- * This is set up by the setup-routine at boot-time
- */
-
-#define COMMAND_LINE_SIZE 512
-
-
-#endif /* _UAPI_ASM_M32R_SETUP_H */
diff --git a/arch/m32r/include/uapi/asm/shmbuf.h b/arch/m32r/include/uapi/asm/shmbuf.h
deleted file mode 100644
index 44c2ea924829..000000000000
--- a/arch/m32r/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SHMBUF_H
-#define _ASM_M32R_SHMBUF_H
-
-/*
- * The shmid64_ds structure for M32R architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
- struct ipc64_perm shm_perm; /* operation perms */
- size_t shm_segsz; /* size of segment (bytes) */
- __kernel_time_t shm_atime; /* last attach time */
- unsigned long __unused1;
- __kernel_time_t shm_dtime; /* last detach time */
- unsigned long __unused2;
- __kernel_time_t shm_ctime; /* last change time */
- unsigned long __unused3;
- __kernel_pid_t shm_cpid; /* pid of creator */
- __kernel_pid_t shm_lpid; /* pid of last operator */
- unsigned long shm_nattch; /* no. of current attaches */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-struct shminfo64 {
- unsigned long shmmax;
- unsigned long shmmin;
- unsigned long shmmni;
- unsigned long shmseg;
- unsigned long shmall;
- unsigned long __unused1;
- unsigned long __unused2;
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_M32R_SHMBUF_H */
diff --git a/arch/m32r/include/uapi/asm/sigcontext.h b/arch/m32r/include/uapi/asm/sigcontext.h
deleted file mode 100644
index cc9ee73525ff..000000000000
--- a/arch/m32r/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SIGCONTEXT_H
-#define _ASM_M32R_SIGCONTEXT_H
-
-struct sigcontext {
- /* CPU registers */
- /* Saved main processor registers. */
- unsigned long sc_r4;
- unsigned long sc_r5;
- unsigned long sc_r6;
- struct pt_regs *sc_pt_regs;
- unsigned long sc_r0;
- unsigned long sc_r1;
- unsigned long sc_r2;
- unsigned long sc_r3;
- unsigned long sc_r7;
- unsigned long sc_r8;
- unsigned long sc_r9;
- unsigned long sc_r10;
- unsigned long sc_r11;
- unsigned long sc_r12;
-
- /* Saved main processor status and miscellaneous context registers. */
- unsigned long sc_acc0h;
- unsigned long sc_acc0l;
- unsigned long sc_acc1h; /* ISA_DSP_LEVEL2 only */
- unsigned long sc_acc1l; /* ISA_DSP_LEVEL2 only */
- unsigned long sc_psw;
- unsigned long sc_bpc; /* saved PC for TRAP syscalls */
- unsigned long sc_bbpsw;
- unsigned long sc_bbpc;
- unsigned long sc_spu; /* saved user stack */
- unsigned long sc_fp;
- unsigned long sc_lr; /* saved PC for JL syscalls */
- unsigned long sc_spi; /* saved kernel stack */
-
- unsigned long oldmask;
-};
-
-#endif /* _ASM_M32R_SIGCONTEXT_H */
diff --git a/arch/m32r/include/uapi/asm/signal.h b/arch/m32r/include/uapi/asm/signal.h
deleted file mode 100644
index c2ac3417fb98..000000000000
--- a/arch/m32r/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_M32R_SIGNAL_H
-#define _UAPI_ASM_M32R_SIGNAL_H
-
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/compiler.h>
-
-/* Avoid too many header ordering problems. */
-struct siginfo;
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-#define SIGBUS 7
-#define SIGFPE 8
-#define SIGKILL 9
-#define SIGUSR1 10
-#define SIGSEGV 11
-#define SIGUSR2 12
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGSTKFLT 16
-#define SIGCHLD 17
-#define SIGCONT 18
-#define SIGSTOP 19
-#define SIGTSTP 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGURG 23
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGIO 29
-#define SIGPOLL SIGIO
-/*
-#define SIGLOST 29
-*/
-#define SIGPWR 30
-#define SIGSYS 31
-#define SIGUNUSED 31
-
-/* These should not be considered constants from userland. */
-#define SIGRTMIN 32
-#define SIGRTMAX _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP 0x00000001u
-#define SA_NOCLDWAIT 0x00000002u
-#define SA_SIGINFO 0x00000004u
-#define SA_ONSTACK 0x08000000u
-#define SA_RESTART 0x10000000u
-#define SA_NODEFER 0x40000000u
-#define SA_RESETHAND 0x80000000u
-
-#define SA_NOMASK SA_NODEFER
-#define SA_ONESHOT SA_RESETHAND
-
-#define SA_RESTORER 0x04000000
-
-#define MINSIGSTKSZ 2048
-#define SIGSTKSZ 8192
-
-#include <asm-generic/signal-defs.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
- void __user *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-
-#endif /* _UAPI_ASM_M32R_SIGNAL_H */
diff --git a/arch/m32r/include/uapi/asm/socket.h b/arch/m32r/include/uapi/asm/socket.h
deleted file mode 100644
index cf5018e82c3d..000000000000
--- a/arch/m32r/include/uapi/asm/socket.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SOCKET_H
-#define _ASM_M32R_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockoptions(2) */
-#define SOL_SOCKET 1
-
-#define SO_DEBUG 1
-#define SO_REUSEADDR 2
-#define SO_TYPE 3
-#define SO_ERROR 4
-#define SO_DONTROUTE 5
-#define SO_BROADCAST 6
-#define SO_SNDBUF 7
-#define SO_RCVBUF 8
-#define SO_SNDBUFFORCE 32
-#define SO_RCVBUFFORCE 33
-#define SO_KEEPALIVE 9
-#define SO_OOBINLINE 10
-#define SO_NO_CHECK 11
-#define SO_PRIORITY 12
-#define SO_LINGER 13
-#define SO_BSDCOMPAT 14
-#define SO_REUSEPORT 15
-#define SO_PASSCRED 16
-#define SO_PEERCRED 17
-#define SO_RCVLOWAT 18
-#define SO_SNDLOWAT 19
-#define SO_RCVTIMEO 20
-#define SO_SNDTIMEO 21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION 22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
-#define SO_SECURITY_ENCRYPTION_NETWORK 24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER 26
-#define SO_DETACH_FILTER 27
-#define SO_GET_FILTER SO_ATTACH_FILTER
-
-#define SO_PEERNAME 28
-#define SO_TIMESTAMP 29
-#define SCM_TIMESTAMP SO_TIMESTAMP
-
-#define SO_ACCEPTCONN 30
-
-#define SO_PEERSEC 31
-#define SO_PASSSEC 34
-#define SO_TIMESTAMPNS 35
-#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
-
-#define SO_MARK 36
-
-#define SO_TIMESTAMPING 37
-#define SCM_TIMESTAMPING SO_TIMESTAMPING
-
-#define SO_PROTOCOL 38
-#define SO_DOMAIN 39
-
-#define SO_RXQ_OVFL 40
-
-#define SO_WIFI_STATUS 41
-#define SCM_WIFI_STATUS SO_WIFI_STATUS
-#define SO_PEEK_OFF 42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS 43
-
-#define SO_LOCK_FILTER 44
-
-#define SO_SELECT_ERR_QUEUE 45
-
-#define SO_BUSY_POLL 46
-
-#define SO_MAX_PACING_RATE 47
-
-#define SO_BPF_EXTENSIONS 48
-
-#define SO_INCOMING_CPU 49
-
-#define SO_ATTACH_BPF 50
-#define SO_DETACH_BPF SO_DETACH_FILTER
-
-#define SO_ATTACH_REUSEPORT_CBPF 51
-#define SO_ATTACH_REUSEPORT_EBPF 52
-
-#define SO_CNX_ADVICE 53
-
-#define SCM_TIMESTAMPING_OPT_STATS 54
-
-#define SO_MEMINFO 55
-
-#define SO_INCOMING_NAPI_ID 56
-
-#define SO_COOKIE 57
-
-#define SCM_TIMESTAMPING_PKTINFO 58
-
-#define SO_PEERGROUPS 59
-
-#define SO_ZEROCOPY 60
-
-#endif /* _ASM_M32R_SOCKET_H */
diff --git a/arch/m32r/include/uapi/asm/sockios.h b/arch/m32r/include/uapi/asm/sockios.h
deleted file mode 100644
index 948229e474c5..000000000000
--- a/arch/m32r/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SOCKIOS_H
-#define _ASM_M32R_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
-#define SIOCSPGRP 0x8902
-#define FIOGETOWN 0x8903
-#define SIOCGPGRP 0x8904
-#define SIOCATMARK 0x8905
-#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
-#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
-
-#endif /* _ASM_M32R_SOCKIOS_H */
diff --git a/arch/m32r/include/uapi/asm/stat.h b/arch/m32r/include/uapi/asm/stat.h
deleted file mode 100644
index 0fe9f96ce8f0..000000000000
--- a/arch/m32r/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_STAT_H
-#define _ASM_M32R_STAT_H
-
-#include <asm/byteorder.h>
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-#define STAT_HAVE_NSEC 1
-
-struct stat {
- unsigned short st_dev;
- unsigned short __pad1;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned short __pad2;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad0[4];
-#define STAT64_HAS_BROKEN_ST_INO
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad3[4];
-
- long long st_size;
- unsigned long st_blksize;
-
-#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : defined(__BIG_ENDIAN)
- unsigned long __pad4; /* future possible st_blocks high bits */
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
-#elif defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN)
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
- unsigned long __pad4; /* future possible st_blocks high bits */
-#else
-#error no endian defined
-#endif
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#endif /* _ASM_M32R_STAT_H */
diff --git a/arch/m32r/include/uapi/asm/statfs.h b/arch/m32r/include/uapi/asm/statfs.h
deleted file mode 100644
index d42ae20dbb2b..000000000000
--- a/arch/m32r/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_STATFS_H
-#define _ASM_M32R_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _ASM_M32R_STATFS_H */
diff --git a/arch/m32r/include/uapi/asm/swab.h b/arch/m32r/include/uapi/asm/swab.h
deleted file mode 100644
index 18dce47d2841..000000000000
--- a/arch/m32r/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SWAB_H
-#define _ASM_M32R_SWAB_H
-
-#include <linux/types.h>
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __SWAB_64_THRU_32__
-#endif
-
-#endif /* _ASM_M32R_SWAB_H */
diff --git a/arch/m32r/include/uapi/asm/termbits.h b/arch/m32r/include/uapi/asm/termbits.h
deleted file mode 100644
index 6cbbae9695b4..000000000000
--- a/arch/m32r/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_TERMBITS_H
-#define _ASM_M32R_TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-#define B500000 0010005
-#define B576000 0010006
-#define B921600 0010007
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-#define CIBAUD 002003600000 /** input baud rate */
-#define CTVB 004000000000 /* VisioBraille Terminal flow control */
-#define CMSPAR 010000000000 /* mark or space (stick) parity */
-#define CRTSCTS 020000000000 /* flow control */
-
-#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif /* _ASM_M32R_TERMBITS_H */
diff --git a/arch/m32r/include/uapi/asm/termios.h b/arch/m32r/include/uapi/asm/termios.h
deleted file mode 100644
index 9b80a85e83ac..000000000000
--- a/arch/m32r/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_M32R_TERMIOS_H
-#define _UAPI_M32R_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-
-#endif /* _UAPI_M32R_TERMIOS_H */
diff --git a/arch/m32r/include/uapi/asm/types.h b/arch/m32r/include/uapi/asm/types.h
deleted file mode 100644
index 9ec9d4c5ac4d..000000000000
--- a/arch/m32r/include/uapi/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/int-ll64.h>
diff --git a/arch/m32r/include/uapi/asm/unistd.h b/arch/m32r/include/uapi/asm/unistd.h
deleted file mode 100644
index adf8666a68ef..000000000000
--- a/arch/m32r/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_M32R_UNISTD_H
-#define _UAPI_ASM_M32R_UNISTD_H
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-/* 16 is unused */
-/* 17 is unused */
-/* 18 is unused */
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-/* 23 is unused */
-/* 24 is unused */
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-/* 28 is unused */
-#define __NR_pause 29
-#define __NR_utime 30
-/* 31 is unused */
-#define __NR_cachectl 32 /* old #define __NR_gtty 32*/
-#define __NR_access 33
-/* 34 is unused */
-/* 35 is unused */
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-/* 44 is unused */
-#define __NR_brk 45
-/* 46 is unused */
-/* 47 is unused (getgid16) */
-/* 48 is unused */
-/* 49 is unused */
-/* 50 is unused */
-#define __NR_acct 51
-#define __NR_umount2 52
-/* 53 is unused */
-#define __NR_ioctl 54
-/* 55 is unused (fcntl) */
-/* 56 is unused */
-#define __NR_setpgid 57
-/* 58 is unused */
-/* 59 is unused */
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-/* 67 is unused */
-/* 68 is unused*/
-/* 69 is unused*/
-/* 70 is unused */
-/* 71 is unused */
-/* 72 is unused */
-/* 73 is unused */
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-/* 76 is unused (old getrlimit) */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-/* 80 is unused */
-/* 81 is unused */
-/* 82 is unused */
-#define __NR_symlink 83
-/* 84 is unused */
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-/* 89 is unused */
-/* 90 is unused */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-/* 95 is unused */
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-/* 98 is unused */
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-/* 101 is unused */
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-/* 109 is unused */
-/* 110 is unused */
-#define __NR_vhangup 111
-/* 112 is unused */
-/* 113 is unused */
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-/* 119 is unused */
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-/* 123 is unused */
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-/* 126 is unused */
-/* 127 is unused */
-#define __NR_init_module 128
-#define __NR_delete_module 129
-/* 130 is unused */
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-/* 137 is unused */
-/* 138 is unused */
-/* 139 is unused */
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-/* 164 is unused */
-/* 165 is unused */
-#define __NR_tas 166
-/* 167 is unused */
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-/* 170 is unused */
-/* 171 is unused */
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-/* 182 is unused */
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-/* 188 is unused */
-/* 189 is unused */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-/* 222 is unused */
-/* 223 is unused */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-/* 251 is unused */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-/* 285 is unused */
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
-#define __NR_migrate_pages 294
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-#define __NR_set_robust_list 311
-#define __NR_get_robust_list 312
-#define __NR_splice 313
-#define __NR_sync_file_range 314
-#define __NR_tee 315
-#define __NR_vmsplice 316
-#define __NR_move_pages 317
-#define __NR_getcpu 318
-#define __NR_epoll_pwait 319
-#define __NR_utimensat 320
-#define __NR_signalfd 321
-/* #define __NR_timerfd 322 removed */
-#define __NR_eventfd 323
-#define __NR_fallocate 324
-#define __NR_setns 325
-
-#endif /* _UAPI_ASM_M32R_UNISTD_H */
diff --git a/arch/m32r/kernel/.gitignore b/arch/m32r/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/m32r/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/m32r/kernel/Makefile b/arch/m32r/kernel/Makefile
deleted file mode 100644
index bd94dca51596..000000000000
--- a/arch/m32r/kernel/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Linux/M32R kernel.
-#
-
-extra-y := head.o vmlinux.lds
-
-obj-y := process.o entry.o traps.o align.o irq.o setup.o time.o \
- m32r_ksyms.o sys_m32r.o signal.o ptrace.o
-
-obj-$(CONFIG_SMP) += smp.o smpboot.o
-obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/m32r/kernel/align.c b/arch/m32r/kernel/align.c
deleted file mode 100644
index 2919a6647aff..000000000000
--- a/arch/m32r/kernel/align.c
+++ /dev/null
@@ -1,585 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * align.c - address exception handler for M32R
- *
- * Copyright (c) 2003 Hitoshi Yamamoto
- */
-
-#include <asm/ptrace.h>
-#include <linux/uaccess.h>
-
-static int get_reg(struct pt_regs *regs, int nr)
-{
- int val;
-
- if (nr < 4)
- val = *(unsigned long *)(&regs->r0 + nr);
- else if (nr < 7)
- val = *(unsigned long *)(&regs->r4 + (nr - 4));
- else if (nr < 13)
- val = *(unsigned long *)(&regs->r7 + (nr - 7));
- else
- val = *(unsigned long *)(&regs->fp + (nr - 13));
-
- return val;
-}
-
-static void set_reg(struct pt_regs *regs, int nr, int val)
-{
- if (nr < 4)
- *(unsigned long *)(&regs->r0 + nr) = val;
- else if (nr < 7)
- *(unsigned long *)(&regs->r4 + (nr - 4)) = val;
- else if (nr < 13)
- *(unsigned long *)(&regs->r7 + (nr - 7)) = val;
- else
- *(unsigned long *)(&regs->fp + (nr - 13)) = val;
-}
-
-#define REG1(insn) (((insn) & 0x0f00) >> 8)
-#define REG2(insn) ((insn) & 0x000f)
-#define PSW_BC 0x100
-
-/* O- instruction */
-#define ISA_LD1 0x20c0 /* ld Rdest, @Rsrc */
-#define ISA_LD2 0x20e0 /* ld Rdest, @Rsrc+ */
-#define ISA_LDH 0x20a0 /* ldh Rdest, @Rsrc */
-#define ISA_LDUH 0x20b0 /* lduh Rdest, @Rsrc */
-#define ISA_ST1 0x2040 /* st Rsrc1, @Rsrc2 */
-#define ISA_ST2 0x2060 /* st Rsrc1, @+Rsrc2 */
-#define ISA_ST3 0x2070 /* st Rsrc1, @-Rsrc2 */
-#define ISA_STH1 0x2020 /* sth Rsrc1, @Rsrc2 */
-#define ISA_STH2 0x2030 /* sth Rsrc1, @Rsrc2+ */
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
-/* OS instruction */
-#define ISA_ADD 0x00a0 /* add Rdest, Rsrc */
-#define ISA_ADDI 0x4000 /* addi Rdest, #imm8 */
-#define ISA_ADDX 0x0090 /* addx Rdest, Rsrc */
-#define ISA_AND 0x00c0 /* and Rdest, Rsrc */
-#define ISA_CMP 0x0040 /* cmp Rsrc1, Rsrc2 */
-#define ISA_CMPEQ 0x0060 /* cmpeq Rsrc1, Rsrc2 */
-#define ISA_CMPU 0x0050 /* cmpu Rsrc1, Rsrc2 */
-#define ISA_CMPZ 0x0070 /* cmpz Rsrc */
-#define ISA_LDI 0x6000 /* ldi Rdest, #imm8 */
-#define ISA_MV 0x1080 /* mv Rdest, Rsrc */
-#define ISA_NEG 0x0030 /* neg Rdest, Rsrc */
-#define ISA_NOP 0x7000 /* nop */
-#define ISA_NOT 0x00b0 /* not Rdest, Rsrc */
-#define ISA_OR 0x00e0 /* or Rdest, Rsrc */
-#define ISA_SUB 0x0020 /* sub Rdest, Rsrc */
-#define ISA_SUBX 0x0010 /* subx Rdest, Rsrc */
-#define ISA_XOR 0x00d0 /* xor Rdest, Rsrc */
-
-/* -S instruction */
-#define ISA_MUL 0x1060 /* mul Rdest, Rsrc */
-#define ISA_MULLO_A0 0x3010 /* mullo Rsrc1, Rsrc2, A0 */
-#define ISA_MULLO_A1 0x3090 /* mullo Rsrc1, Rsrc2, A1 */
-#define ISA_MVFACMI_A0 0x50f2 /* mvfacmi Rdest, A0 */
-#define ISA_MVFACMI_A1 0x50f6 /* mvfacmi Rdest, A1 */
-
-static int emu_addi(unsigned short insn, struct pt_regs *regs)
-{
- char imm = (char)(insn & 0xff);
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val += imm;
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_ldi(unsigned short insn, struct pt_regs *regs)
-{
- char imm = (char)(insn & 0xff);
-
- set_reg(regs, REG1(insn), (int)imm);
-
- return 0;
-}
-
-static int emu_add(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int src = REG2(insn);
- int val;
-
- val = get_reg(regs, dest);
- val += get_reg(regs, src);
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_addx(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- unsigned int val, tmp;
-
- val = regs->psw & PSW_BC ? 1 : 0;
- tmp = get_reg(regs, dest);
- val += tmp;
- val += (unsigned int)get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- /* C bit set */
- if (val < tmp)
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_and(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val &= get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_cmp(unsigned short insn, struct pt_regs *regs)
-{
- if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_cmpeq(unsigned short insn, struct pt_regs *regs)
-{
- if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_cmpu(unsigned short insn, struct pt_regs *regs)
-{
- if ((unsigned int)get_reg(regs, REG1(insn))
- < (unsigned int)get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_cmpz(unsigned short insn, struct pt_regs *regs)
-{
- if (!get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_mv(unsigned short insn, struct pt_regs *regs)
-{
- int val;
-
- val = get_reg(regs, REG2(insn));
- set_reg(regs, REG1(insn), val);
-
- return 0;
-}
-
-static int emu_neg(unsigned short insn, struct pt_regs *regs)
-{
- int val;
-
- val = get_reg(regs, REG2(insn));
- set_reg(regs, REG1(insn), 0 - val);
-
- return 0;
-}
-
-static int emu_not(unsigned short insn, struct pt_regs *regs)
-{
- int val;
-
- val = get_reg(regs, REG2(insn));
- set_reg(regs, REG1(insn), ~val);
-
- return 0;
-}
-
-static int emu_or(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val |= get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_sub(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val -= get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_subx(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- unsigned int val, tmp;
-
- val = tmp = get_reg(regs, dest);
- val -= (unsigned int)get_reg(regs, REG2(insn));
- val -= regs->psw & PSW_BC ? 1 : 0;
- set_reg(regs, dest, val);
-
- /* C bit set */
- if (val > tmp)
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_xor(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- unsigned int val;
-
- val = (unsigned int)get_reg(regs, dest);
- val ^= (unsigned int)get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_mul(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int reg1, reg2;
-
- reg1 = get_reg(regs, dest);
- reg2 = get_reg(regs, REG2(insn));
-
- __asm__ __volatile__ (
- "mul %0, %1; \n\t"
- : "+r" (reg1) : "r" (reg2)
- );
-
- set_reg(regs, dest, reg1);
-
- return 0;
-}
-
-static int emu_mullo_a0(unsigned short insn, struct pt_regs *regs)
-{
- int reg1, reg2;
-
- reg1 = get_reg(regs, REG1(insn));
- reg2 = get_reg(regs, REG2(insn));
-
- __asm__ __volatile__ (
- "mullo %0, %1, a0; \n\t"
- "mvfachi %0, a0; \n\t"
- "mvfaclo %1, a0; \n\t"
- : "+r" (reg1), "+r" (reg2)
- );
-
- regs->acc0h = reg1;
- regs->acc0l = reg2;
-
- return 0;
-}
-
-static int emu_mullo_a1(unsigned short insn, struct pt_regs *regs)
-{
- int reg1, reg2;
-
- reg1 = get_reg(regs, REG1(insn));
- reg2 = get_reg(regs, REG2(insn));
-
- __asm__ __volatile__ (
- "mullo %0, %1, a0; \n\t"
- "mvfachi %0, a0; \n\t"
- "mvfaclo %1, a0; \n\t"
- : "+r" (reg1), "+r" (reg2)
- );
-
- regs->acc1h = reg1;
- regs->acc1l = reg2;
-
- return 0;
-}
-
-static int emu_mvfacmi_a0(unsigned short insn, struct pt_regs *regs)
-{
- unsigned long val;
-
- val = (regs->acc0h << 16) | (regs->acc0l >> 16);
- set_reg(regs, REG1(insn), (int)val);
-
- return 0;
-}
-
-static int emu_mvfacmi_a1(unsigned short insn, struct pt_regs *regs)
-{
- unsigned long val;
-
- val = (regs->acc1h << 16) | (regs->acc1l >> 16);
- set_reg(regs, REG1(insn), (int)val);
-
- return 0;
-}
-
-static int emu_m32r2(unsigned short insn, struct pt_regs *regs)
-{
- int res = -1;
-
- if ((insn & 0x7fff) == ISA_NOP) /* nop */
- return 0;
-
- switch(insn & 0x7000) {
- case ISA_ADDI: /* addi Rdest, #imm8 */
- res = emu_addi(insn, regs);
- break;
- case ISA_LDI: /* ldi Rdest, #imm8 */
- res = emu_ldi(insn, regs);
- break;
- default:
- break;
- }
-
- if (!res)
- return 0;
-
- switch(insn & 0x70f0) {
- case ISA_ADD: /* add Rdest, Rsrc */
- res = emu_add(insn, regs);
- break;
- case ISA_ADDX: /* addx Rdest, Rsrc */
- res = emu_addx(insn, regs);
- break;
- case ISA_AND: /* and Rdest, Rsrc */
- res = emu_and(insn, regs);
- break;
- case ISA_CMP: /* cmp Rsrc1, Rsrc2 */
- res = emu_cmp(insn, regs);
- break;
- case ISA_CMPEQ: /* cmpeq Rsrc1, Rsrc2 */
- res = emu_cmpeq(insn, regs);
- break;
- case ISA_CMPU: /* cmpu Rsrc1, Rsrc2 */
- res = emu_cmpu(insn, regs);
- break;
- case ISA_CMPZ: /* cmpz Rsrc */
- res = emu_cmpz(insn, regs);
- break;
- case ISA_MV: /* mv Rdest, Rsrc */
- res = emu_mv(insn, regs);
- break;
- case ISA_NEG: /* neg Rdest, Rsrc */
- res = emu_neg(insn, regs);
- break;
- case ISA_NOT: /* not Rdest, Rsrc */
- res = emu_not(insn, regs);
- break;
- case ISA_OR: /* or Rdest, Rsrc */
- res = emu_or(insn, regs);
- break;
- case ISA_SUB: /* sub Rdest, Rsrc */
- res = emu_sub(insn, regs);
- break;
- case ISA_SUBX: /* subx Rdest, Rsrc */
- res = emu_subx(insn, regs);
- break;
- case ISA_XOR: /* xor Rdest, Rsrc */
- res = emu_xor(insn, regs);
- break;
- case ISA_MUL: /* mul Rdest, Rsrc */
- res = emu_mul(insn, regs);
- break;
- case ISA_MULLO_A0: /* mullo Rsrc1, Rsrc2 */
- res = emu_mullo_a0(insn, regs);
- break;
- case ISA_MULLO_A1: /* mullo Rsrc1, Rsrc2 */
- res = emu_mullo_a1(insn, regs);
- break;
- default:
- break;
- }
-
- if (!res)
- return 0;
-
- switch(insn & 0x70ff) {
- case ISA_MVFACMI_A0: /* mvfacmi Rdest */
- res = emu_mvfacmi_a0(insn, regs);
- break;
- case ISA_MVFACMI_A1: /* mvfacmi Rdest */
- res = emu_mvfacmi_a1(insn, regs);
- break;
- default:
- break;
- }
-
- return res;
-}
-
-#endif /* CONFIG_ISA_DUAL_ISSUE */
-
-/*
- * ld : ?010 dest 1100 src
- * 0010 dest 1110 src : ld Rdest, @Rsrc+
- * ldh : ?010 dest 1010 src
- * lduh : ?010 dest 1011 src
- * st : ?010 src1 0100 src2
- * 0010 src1 0110 src2 : st Rsrc1, @+Rsrc2
- * 0010 src1 0111 src2 : st Rsrc1, @-Rsrc2
- * sth : ?010 src1 0010 src2
- */
-
-static int insn_check(unsigned long insn, struct pt_regs *regs,
- unsigned char **ucp)
-{
- int res = 0;
-
- /*
- * 32bit insn
- * ld Rdest, @(disp16, Rsrc)
- * st Rdest, @(disp16, Rsrc)
- */
- if (insn & 0x80000000) { /* 32bit insn */
- *ucp += (short)(insn & 0x0000ffff);
- regs->bpc += 4;
- } else { /* 16bit insn */
-#ifdef CONFIG_ISA_DUAL_ISSUE
- /* parallel exec check */
- if (!(regs->bpc & 0x2) && insn & 0x8000) {
- res = emu_m32r2((unsigned short)insn, regs);
- regs->bpc += 4;
- } else
-#endif /* CONFIG_ISA_DUAL_ISSUE */
- regs->bpc += 2;
- }
-
- return res;
-}
-
-static int emu_ld(unsigned long insn32, struct pt_regs *regs)
-{
- unsigned char *ucp;
- unsigned long val;
- unsigned short insn16;
- int size, src;
-
- insn16 = insn32 >> 16;
- src = REG2(insn16);
- ucp = (unsigned char *)get_reg(regs, src);
-
- if (insn_check(insn32, regs, &ucp))
- return -1;
-
- size = insn16 & 0x0040 ? 4 : 2;
- if (copy_from_user(&val, ucp, size))
- return -1;
-
- if (size == 2)
- val >>= 16;
-
- /* ldh sign check */
- if ((insn16 & 0x00f0) == 0x00a0 && (val & 0x8000))
- val |= 0xffff0000;
-
- set_reg(regs, REG1(insn16), val);
-
- /* ld increment check */
- if ((insn16 & 0xf0f0) == ISA_LD2) /* ld Rdest, @Rsrc+ */
- set_reg(regs, src, (unsigned long)(ucp + 4));
-
- return 0;
-}
-
-static int emu_st(unsigned long insn32, struct pt_regs *regs)
-{
- unsigned char *ucp;
- unsigned long val;
- unsigned short insn16;
- int size, src2;
-
- insn16 = insn32 >> 16;
- src2 = REG2(insn16);
-
- ucp = (unsigned char *)get_reg(regs, src2);
-
- if (insn_check(insn32, regs, &ucp))
- return -1;
-
- size = insn16 & 0x0040 ? 4 : 2;
- val = get_reg(regs, REG1(insn16));
- if (size == 2)
- val <<= 16;
-
- /* st inc/dec check */
- if ((insn16 & 0xf0e0) == 0x2060) {
- if (insn16 & 0x0010)
- ucp -= 4;
- else
- ucp += 4;
-
- set_reg(regs, src2, (unsigned long)ucp);
- }
-
- if (copy_to_user(ucp, &val, size))
- return -1;
-
- /* sth inc check */
- if ((insn16 & 0xf0f0) == ISA_STH2) {
- ucp += 2;
- set_reg(regs, src2, (unsigned long)ucp);
- }
-
- return 0;
-}
-
-int handle_unaligned_access(unsigned long insn32, struct pt_regs *regs)
-{
- unsigned short insn16;
- int res;
-
- insn16 = insn32 >> 16;
-
- /* ld or st check */
- if ((insn16 & 0x7000) != 0x2000)
- return -1;
-
- /* insn alignment check */
- if ((insn16 & 0x8000) && (regs->bpc & 3))
- return -1;
-
- if (insn16 & 0x0080) /* ld */
- res = emu_ld(insn32, regs);
- else /* st */
- res = emu_st(insn32, regs);
-
- return res;
-}
-
diff --git a/arch/m32r/kernel/asm-offsets.c b/arch/m32r/kernel/asm-offsets.c
deleted file mode 100644
index 7cb90b459e07..000000000000
--- a/arch/m32r/kernel/asm-offsets.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/thread_info.h>
-#include <linux/kbuild.h>
-
-int foo(void)
-{
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_STATUS, thread_info, status);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
- OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
-
- return 0;
-}
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
deleted file mode 100644
index bbf48f2aa2a7..000000000000
--- a/arch/m32r/kernel/entry.S
+++ /dev/null
@@ -1,553 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/kernel/entry.S
- *
- * Copyright (c) 2001, 2002 Hirokazu Takata, Hitoshi Yamamoto, H. Kondo
- * Copyright (c) 2003 Hitoshi Yamamoto
- * Copyright (c) 2004 Hirokazu Takata <takata at linux-m32r.org>
- *
- * Taken from i386 version.
- * Copyright (C) 1991, 1992 Linus Torvalds
- */
-
-/*
- * entry.S contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all interrupts
- * and faults that can result in a task-switch.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- * Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
- * if the order here is changed, it needs to be
- * updated in fork.c:copy_thread, signal.c:do_signal,
- * ptrace.c and ptrace.h
- *
- * M32R/M32Rx/M32R2
- * @(sp) - r4
- * @(0x04,sp) - r5
- * @(0x08,sp) - r6
- * @(0x0c,sp) - *pt_regs
- * @(0x10,sp) - r0
- * @(0x14,sp) - r1
- * @(0x18,sp) - r2
- * @(0x1c,sp) - r3
- * @(0x20,sp) - r7
- * @(0x24,sp) - r8
- * @(0x28,sp) - r9
- * @(0x2c,sp) - r10
- * @(0x30,sp) - r11
- * @(0x34,sp) - r12
- * @(0x38,sp) - syscall_nr
- * @(0x3c,sp) - acc0h
- * @(0x40,sp) - acc0l
- * @(0x44,sp) - acc1h ; ISA_DSP_LEVEL2 only
- * @(0x48,sp) - acc1l ; ISA_DSP_LEVEL2 only
- * @(0x4c,sp) - psw
- * @(0x50,sp) - bpc
- * @(0x54,sp) - bbpsw
- * @(0x58,sp) - bbpc
- * @(0x5c,sp) - spu (cr3)
- * @(0x60,sp) - fp (r13)
- * @(0x64,sp) - lr (r14)
- * @(0x68,sp) - spi (cr2)
- * @(0x6c,sp) - orig_r0
- */
-
-#include <linux/linkage.h>
-#include <asm/irq.h>
-#include <asm/unistd.h>
-#include <asm/assembler.h>
-#include <asm/thread_info.h>
-#include <asm/errno.h>
-#include <asm/segment.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/m32r.h>
-#include <asm/mmu_context.h>
-#include <asm/asm-offsets.h>
-
-#if !defined(CONFIG_MMU)
-#define sys_madvise sys_ni_syscall
-#define sys_readahead sys_ni_syscall
-#define sys_mprotect sys_ni_syscall
-#define sys_msync sys_ni_syscall
-#define sys_mlock sys_ni_syscall
-#define sys_munlock sys_ni_syscall
-#define sys_mlockall sys_ni_syscall
-#define sys_munlockall sys_ni_syscall
-#define sys_mremap sys_ni_syscall
-#define sys_mincore sys_ni_syscall
-#define sys_remap_file_pages sys_ni_syscall
-#endif /* CONFIG_MMU */
-
-#define R4(reg) @reg
-#define R5(reg) @(0x04,reg)
-#define R6(reg) @(0x08,reg)
-#define PTREGS(reg) @(0x0C,reg)
-#define R0(reg) @(0x10,reg)
-#define R1(reg) @(0x14,reg)
-#define R2(reg) @(0x18,reg)
-#define R3(reg) @(0x1C,reg)
-#define R7(reg) @(0x20,reg)
-#define R8(reg) @(0x24,reg)
-#define R9(reg) @(0x28,reg)
-#define R10(reg) @(0x2C,reg)
-#define R11(reg) @(0x30,reg)
-#define R12(reg) @(0x34,reg)
-#define SYSCALL_NR(reg) @(0x38,reg)
-#define ACC0H(reg) @(0x3C,reg)
-#define ACC0L(reg) @(0x40,reg)
-#define ACC1H(reg) @(0x44,reg)
-#define ACC1L(reg) @(0x48,reg)
-#define PSW(reg) @(0x4C,reg)
-#define BPC(reg) @(0x50,reg)
-#define BBPSW(reg) @(0x54,reg)
-#define BBPC(reg) @(0x58,reg)
-#define SPU(reg) @(0x5C,reg)
-#define FP(reg) @(0x60,reg) /* FP = R13 */
-#define LR(reg) @(0x64,reg)
-#define SP(reg) @(0x68,reg)
-#define ORIG_R0(reg) @(0x6C,reg)
-
-#define nr_syscalls ((syscall_table_size)/4)
-
-#ifdef CONFIG_PREEMPT
-#define preempt_stop(x) DISABLE_INTERRUPTS(x)
-#else
-#define preempt_stop(x)
-#define resume_kernel restore_all
-#endif
-
-/* how to get the thread information struct from ASM */
-#define GET_THREAD_INFO(reg) GET_THREAD_INFO reg
- .macro GET_THREAD_INFO reg
- ldi \reg, #-THREAD_SIZE
- and \reg, sp
- .endm
-
-ENTRY(ret_from_kernel_thread)
- pop r0
- bl schedule_tail
- GET_THREAD_INFO(r8)
- ld r0, R0(r8)
- ld r1, R1(r8)
- jl r1
- bra syscall_exit
-
-ENTRY(ret_from_fork)
- pop r0
- bl schedule_tail
- GET_THREAD_INFO(r8)
- bra syscall_exit
-
-/*
- * Return to user mode is not as complex as all this looks,
- * but we want the default path for a system call return to
- * go as quickly as possible which is why some of this is
- * less clear than it otherwise should be.
- */
-
- ; userspace resumption stub bypassing syscall exit tracing
- ALIGN
-ret_from_exception:
- preempt_stop(r4)
-ret_from_intr:
- ld r4, PSW(sp)
-#ifdef CONFIG_ISA_M32R2
- and3 r4, r4, #0x8800 ; check BSM and BPM bits
-#else
- and3 r4, r4, #0x8000 ; check BSM bit
-#endif
- beqz r4, resume_kernel
-resume_userspace:
- DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
- ; setting need_resched or sigpending
- ; between sampling and the iret
- GET_THREAD_INFO(r8)
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done on
- ; int/exception return?
- bnez r4, work_pending
- bra restore_all
-
-#ifdef CONFIG_PREEMPT
-ENTRY(resume_kernel)
- GET_THREAD_INFO(r8)
- ld r9, @(TI_PRE_COUNT, r8) ; non-zero preempt_count ?
- bnez r9, restore_all
-need_resched:
- ld r9, @(TI_FLAGS, r8) ; need_resched set ?
- and3 r4, r9, #_TIF_NEED_RESCHED
- beqz r4, restore_all
- ld r4, PSW(sp) ; interrupts off (exception path) ?
- and3 r4, r4, #0x4000
- beqz r4, restore_all
- bl preempt_schedule_irq
- bra need_resched
-#endif
-
- ; system call handler stub
-ENTRY(system_call)
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- ENABLE_INTERRUPTS(r4) ; Enable interrupt
- st sp, PTREGS(sp) ; implicit pt_regs parameter
- cmpui r7, #NR_syscalls
- bnc syscall_badsys
- st r7, SYSCALL_NR(sp) ; syscall_nr
- ; system call tracing in operation
- GET_THREAD_INFO(r8)
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_SYSCALL_TRACE
- bnez r4, syscall_trace_entry
-syscall_call:
- slli r7, #2 ; table jump for the system call
- LDIMM (r4, sys_call_table)
- add r7, r4
- ld r7, @r7
- jl r7 ; execute system call
- st r0, R0(sp) ; save the return value
-syscall_exit:
- DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
- ; setting need_resched or sigpending
- ; between sampling and the iret
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_ALLWORK_MASK ; current->work
- bnez r4, syscall_exit_work
-restore_all:
- RESTORE_ALL
-
- # perform work that needs to be done immediately before resumption
- # r9 : flags
- ALIGN
-work_pending:
- and3 r4, r9, #_TIF_NEED_RESCHED
- beqz r4, work_notifysig
-work_resched:
- bl schedule
- DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
- ; setting need_resched or sigpending
- ; between sampling and the iret
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done other
- ; than syscall tracing?
- beqz r4, restore_all
- and3 r4, r4, #_TIF_NEED_RESCHED
- bnez r4, work_resched
-
-work_notifysig: ; deal with pending signals and
- ; notify-resume requests
- mv r0, sp ; arg1 : struct pt_regs *regs
- mv r1, r9 ; arg2 : __u32 thread_info_flags
- bl do_notify_resume
- bra resume_userspace
-
- ; perform syscall exit tracing
- ALIGN
-syscall_trace_entry:
- ldi r4, #-ENOSYS
- st r4, R0(sp)
- bl do_syscall_trace
- ld r0, ORIG_R0(sp)
- ld r1, R1(sp)
- ld r2, R2(sp)
- ld r3, R3(sp)
- ld r4, R4(sp)
- ld r5, R5(sp)
- ld r6, R6(sp)
- ld r7, SYSCALL_NR(sp)
- cmpui r7, #NR_syscalls
- bc syscall_call
- bra syscall_exit
-
- ; perform syscall exit tracing
- ALIGN
-syscall_exit_work:
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_SYSCALL_TRACE
- beqz r4, work_pending
- ENABLE_INTERRUPTS(r4) ; could let do_syscall_trace() call
- ; schedule() instead
- bl do_syscall_trace
- bra resume_userspace
-
- ALIGN
-syscall_fault:
- SAVE_ALL
- GET_THREAD_INFO(r8)
- ldi r4, #-EFAULT
- st r4, R0(sp)
- bra resume_userspace
-
- ALIGN
-syscall_badsys:
- ldi r4, #-ENOSYS
- st r4, R0(sp)
- bra resume_userspace
-
- .global eit_vector